Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 33
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 00:24:58.596806 lava-dispatcher, installed at version: 2024.03
2 00:24:58.597029 start: 0 validate
3 00:24:58.597144 Start time: 2024-06-21 00:24:58.597138+00:00 (UTC)
4 00:24:58.597271 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:24:58.597413 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:24:58.859001 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:24:58.859664 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:24:59.119134 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:24:59.119524 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:24:59.377902 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:24:59.378534 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:24:59.638520 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:24:59.639099 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:24:59.904659 validate duration: 1.31
16 00:24:59.905784 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:24:59.906374 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:24:59.906861 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:24:59.907599 Not decompressing ramdisk as can be used compressed.
20 00:24:59.908094 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/initrd.cpio.gz
21 00:24:59.908535 saving as /var/lib/lava/dispatcher/tmp/14479197/tftp-deploy-n9hju5wc/ramdisk/initrd.cpio.gz
22 00:24:59.908871 total size: 5628151 (5 MB)
23 00:24:59.917476 progress 0 % (0 MB)
24 00:24:59.927345 progress 5 % (0 MB)
25 00:24:59.937095 progress 10 % (0 MB)
26 00:24:59.941909 progress 15 % (0 MB)
27 00:24:59.946186 progress 20 % (1 MB)
28 00:24:59.949155 progress 25 % (1 MB)
29 00:24:59.952403 progress 30 % (1 MB)
30 00:24:59.955178 progress 35 % (1 MB)
31 00:24:59.957401 progress 40 % (2 MB)
32 00:24:59.959802 progress 45 % (2 MB)
33 00:24:59.961794 progress 50 % (2 MB)
34 00:24:59.963879 progress 55 % (2 MB)
35 00:24:59.965953 progress 60 % (3 MB)
36 00:24:59.967624 progress 65 % (3 MB)
37 00:24:59.969495 progress 70 % (3 MB)
38 00:24:59.971145 progress 75 % (4 MB)
39 00:24:59.972810 progress 80 % (4 MB)
40 00:24:59.974313 progress 85 % (4 MB)
41 00:24:59.975992 progress 90 % (4 MB)
42 00:24:59.977511 progress 95 % (5 MB)
43 00:24:59.978898 progress 100 % (5 MB)
44 00:24:59.979107 5 MB downloaded in 0.07 s (76.42 MB/s)
45 00:24:59.979258 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:24:59.979485 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:24:59.979568 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:24:59.979646 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:24:59.979779 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:24:59.979841 saving as /var/lib/lava/dispatcher/tmp/14479197/tftp-deploy-n9hju5wc/kernel/Image
52 00:24:59.979895 total size: 54813184 (52 MB)
53 00:24:59.979951 No compression specified
54 00:24:59.981051 progress 0 % (0 MB)
55 00:24:59.995016 progress 5 % (2 MB)
56 00:25:00.008772 progress 10 % (5 MB)
57 00:25:00.022371 progress 15 % (7 MB)
58 00:25:00.036078 progress 20 % (10 MB)
59 00:25:00.049901 progress 25 % (13 MB)
60 00:25:00.064031 progress 30 % (15 MB)
61 00:25:00.077886 progress 35 % (18 MB)
62 00:25:00.091776 progress 40 % (20 MB)
63 00:25:00.105558 progress 45 % (23 MB)
64 00:25:00.119543 progress 50 % (26 MB)
65 00:25:00.133337 progress 55 % (28 MB)
66 00:25:00.146993 progress 60 % (31 MB)
67 00:25:00.160992 progress 65 % (34 MB)
68 00:25:00.174823 progress 70 % (36 MB)
69 00:25:00.188705 progress 75 % (39 MB)
70 00:25:00.202510 progress 80 % (41 MB)
71 00:25:00.216220 progress 85 % (44 MB)
72 00:25:00.230127 progress 90 % (47 MB)
73 00:25:00.243731 progress 95 % (49 MB)
74 00:25:00.257130 progress 100 % (52 MB)
75 00:25:00.257350 52 MB downloaded in 0.28 s (188.41 MB/s)
76 00:25:00.257502 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:25:00.257715 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:25:00.257797 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:25:00.257873 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:25:00.258042 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:25:00.258110 saving as /var/lib/lava/dispatcher/tmp/14479197/tftp-deploy-n9hju5wc/dtb/mt8192-asurada-spherion-r0.dtb
83 00:25:00.258164 total size: 47258 (0 MB)
84 00:25:00.258217 No compression specified
85 00:25:00.259263 progress 69 % (0 MB)
86 00:25:00.259526 progress 100 % (0 MB)
87 00:25:00.259675 0 MB downloaded in 0.00 s (29.88 MB/s)
88 00:25:00.259788 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:25:00.259990 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:25:00.260066 start: 1.4 download-retry (timeout 00:10:00) [common]
92 00:25:00.260141 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 00:25:00.260243 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/full.rootfs.tar.xz
94 00:25:00.260303 saving as /var/lib/lava/dispatcher/tmp/14479197/tftp-deploy-n9hju5wc/nfsrootfs/full.rootfs.tar
95 00:25:00.260355 total size: 69067788 (65 MB)
96 00:25:00.260408 Using unxz to decompress xz
97 00:25:00.265602 progress 0 % (0 MB)
98 00:25:00.450752 progress 5 % (3 MB)
99 00:25:00.647563 progress 10 % (6 MB)
100 00:25:00.838272 progress 15 % (9 MB)
101 00:25:00.998954 progress 20 % (13 MB)
102 00:25:01.177971 progress 25 % (16 MB)
103 00:25:01.364955 progress 30 % (19 MB)
104 00:25:01.483885 progress 35 % (23 MB)
105 00:25:01.582079 progress 40 % (26 MB)
106 00:25:01.779990 progress 45 % (29 MB)
107 00:25:01.976178 progress 50 % (32 MB)
108 00:25:02.168659 progress 55 % (36 MB)
109 00:25:02.373163 progress 60 % (39 MB)
110 00:25:02.555355 progress 65 % (42 MB)
111 00:25:02.744311 progress 70 % (46 MB)
112 00:25:02.932798 progress 75 % (49 MB)
113 00:25:03.132151 progress 80 % (52 MB)
114 00:25:03.301448 progress 85 % (56 MB)
115 00:25:03.487072 progress 90 % (59 MB)
116 00:25:03.684949 progress 95 % (62 MB)
117 00:25:03.880728 progress 100 % (65 MB)
118 00:25:03.886711 65 MB downloaded in 3.63 s (18.16 MB/s)
119 00:25:03.886869 end: 1.4.1 http-download (duration 00:00:04) [common]
121 00:25:03.887079 end: 1.4 download-retry (duration 00:00:04) [common]
122 00:25:03.887161 start: 1.5 download-retry (timeout 00:09:56) [common]
123 00:25:03.887235 start: 1.5.1 http-download (timeout 00:09:56) [common]
124 00:25:03.887365 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:25:03.887425 saving as /var/lib/lava/dispatcher/tmp/14479197/tftp-deploy-n9hju5wc/modules/modules.tar
126 00:25:03.887478 total size: 8618924 (8 MB)
127 00:25:03.887533 Using unxz to decompress xz
128 00:25:03.888768 progress 0 % (0 MB)
129 00:25:03.907768 progress 5 % (0 MB)
130 00:25:03.930853 progress 10 % (0 MB)
131 00:25:03.955030 progress 15 % (1 MB)
132 00:25:03.980199 progress 20 % (1 MB)
133 00:25:04.005945 progress 25 % (2 MB)
134 00:25:04.029965 progress 30 % (2 MB)
135 00:25:04.054256 progress 35 % (2 MB)
136 00:25:04.077846 progress 40 % (3 MB)
137 00:25:04.101803 progress 45 % (3 MB)
138 00:25:04.125213 progress 50 % (4 MB)
139 00:25:04.148990 progress 55 % (4 MB)
140 00:25:04.172444 progress 60 % (4 MB)
141 00:25:04.195344 progress 65 % (5 MB)
142 00:25:04.222152 progress 70 % (5 MB)
143 00:25:04.246723 progress 75 % (6 MB)
144 00:25:04.270867 progress 80 % (6 MB)
145 00:25:04.293516 progress 85 % (7 MB)
146 00:25:04.316498 progress 90 % (7 MB)
147 00:25:04.342658 progress 95 % (7 MB)
148 00:25:04.370630 progress 100 % (8 MB)
149 00:25:04.375013 8 MB downloaded in 0.49 s (16.86 MB/s)
150 00:25:04.375170 end: 1.5.1 http-download (duration 00:00:00) [common]
152 00:25:04.375383 end: 1.5 download-retry (duration 00:00:00) [common]
153 00:25:04.375461 start: 1.6 prepare-tftp-overlay (timeout 00:09:56) [common]
154 00:25:04.375538 start: 1.6.1 extract-nfsrootfs (timeout 00:09:56) [common]
155 00:25:05.928514 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14479197/extract-nfsrootfs-dddnrq79
156 00:25:05.928685 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 00:25:05.928773 start: 1.6.2 lava-overlay (timeout 00:09:54) [common]
158 00:25:05.928928 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y
159 00:25:05.929050 makedir: /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin
160 00:25:05.929144 makedir: /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/tests
161 00:25:05.929233 makedir: /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/results
162 00:25:05.929316 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-add-keys
163 00:25:05.929493 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-add-sources
164 00:25:05.929615 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-background-process-start
165 00:25:05.929733 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-background-process-stop
166 00:25:05.929858 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-common-functions
167 00:25:05.929976 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-echo-ipv4
168 00:25:05.930123 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-install-packages
169 00:25:05.930237 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-installed-packages
170 00:25:05.930354 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-os-build
171 00:25:05.930466 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-probe-channel
172 00:25:05.930578 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-probe-ip
173 00:25:05.930691 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-target-ip
174 00:25:05.930802 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-target-mac
175 00:25:05.930912 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-target-storage
176 00:25:05.931026 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-test-case
177 00:25:05.931138 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-test-event
178 00:25:05.931248 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-test-feedback
179 00:25:05.931359 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-test-raise
180 00:25:05.931470 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-test-reference
181 00:25:05.931580 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-test-runner
182 00:25:05.931691 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-test-set
183 00:25:05.931801 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-test-shell
184 00:25:05.931913 Updating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-install-packages (oe)
185 00:25:05.932049 Updating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/bin/lava-installed-packages (oe)
186 00:25:05.932158 Creating /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/environment
187 00:25:05.932243 LAVA metadata
188 00:25:05.932309 - LAVA_JOB_ID=14479197
189 00:25:05.932365 - LAVA_DISPATCHER_IP=192.168.201.1
190 00:25:05.932455 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:54) [common]
191 00:25:05.932511 skipped lava-vland-overlay
192 00:25:05.932577 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 00:25:05.932647 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:54) [common]
194 00:25:05.932704 skipped lava-multinode-overlay
195 00:25:05.932770 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 00:25:05.932840 start: 1.6.2.3 test-definition (timeout 00:09:54) [common]
197 00:25:05.932901 Loading test definitions
198 00:25:05.932974 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:54) [common]
199 00:25:05.933032 Using /lava-14479197 at stage 0
200 00:25:05.933332 uuid=14479197_1.6.2.3.1 testdef=None
201 00:25:05.933415 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 00:25:05.933491 start: 1.6.2.3.2 test-overlay (timeout 00:09:54) [common]
203 00:25:05.933915 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 00:25:05.934147 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:54) [common]
206 00:25:05.934702 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 00:25:05.934914 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:54) [common]
209 00:25:05.935450 runner path: /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/0/tests/0_lc-compliance test_uuid 14479197_1.6.2.3.1
210 00:25:05.935595 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 00:25:05.935779 Creating lava-test-runner.conf files
213 00:25:05.935834 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14479197/lava-overlay-6_hjvu3y/lava-14479197/0 for stage 0
214 00:25:05.935914 - 0_lc-compliance
215 00:25:05.936004 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 00:25:05.936080 start: 1.6.2.4 compress-overlay (timeout 00:09:54) [common]
217 00:25:05.941622 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 00:25:05.941716 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:54) [common]
219 00:25:05.941793 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 00:25:05.941872 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 00:25:05.941948 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:54) [common]
222 00:25:06.099289 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 00:25:06.099442 start: 1.6.4 extract-modules (timeout 00:09:54) [common]
224 00:25:06.099522 extracting modules file /var/lib/lava/dispatcher/tmp/14479197/tftp-deploy-n9hju5wc/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479197/extract-nfsrootfs-dddnrq79
225 00:25:06.316926 extracting modules file /var/lib/lava/dispatcher/tmp/14479197/tftp-deploy-n9hju5wc/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479197/extract-overlay-ramdisk-roffqirx/ramdisk
226 00:25:06.544254 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 00:25:06.544420 start: 1.6.5 apply-overlay-tftp (timeout 00:09:53) [common]
228 00:25:06.544573 [common] Applying overlay to NFS
229 00:25:06.544633 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14479197/compress-overlay-zzkf_pog/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14479197/extract-nfsrootfs-dddnrq79
230 00:25:06.550924 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 00:25:06.551019 start: 1.6.6 configure-preseed-file (timeout 00:09:53) [common]
232 00:25:06.551099 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 00:25:06.551177 start: 1.6.7 compress-ramdisk (timeout 00:09:53) [common]
234 00:25:06.551242 Building ramdisk /var/lib/lava/dispatcher/tmp/14479197/extract-overlay-ramdisk-roffqirx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14479197/extract-overlay-ramdisk-roffqirx/ramdisk
235 00:25:06.848249 >> 130487 blocks
236 00:25:08.920571 rename /var/lib/lava/dispatcher/tmp/14479197/extract-overlay-ramdisk-roffqirx/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14479197/tftp-deploy-n9hju5wc/ramdisk/ramdisk.cpio.gz
237 00:25:08.920768 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 00:25:08.920871 start: 1.6.8 prepare-kernel (timeout 00:09:51) [common]
239 00:25:08.920951 start: 1.6.8.1 prepare-fit (timeout 00:09:51) [common]
240 00:25:08.921028 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14479197/tftp-deploy-n9hju5wc/kernel/Image']
241 00:25:21.978321 Returned 0 in 13 seconds
242 00:25:22.079147 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14479197/tftp-deploy-n9hju5wc/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14479197/tftp-deploy-n9hju5wc/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14479197/tftp-deploy-n9hju5wc/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14479197/tftp-deploy-n9hju5wc/kernel/image.itb
243 00:25:22.540382 output: FIT description: Kernel Image image with one or more FDT blobs
244 00:25:22.540518 output: Created: Fri Jun 21 01:25:22 2024
245 00:25:22.540581 output: Image 0 (kernel-1)
246 00:25:22.540636 output: Description:
247 00:25:22.540724 output: Created: Fri Jun 21 01:25:22 2024
248 00:25:22.540777 output: Type: Kernel Image
249 00:25:22.540827 output: Compression: lzma compressed
250 00:25:22.540883 output: Data Size: 13124896 Bytes = 12817.28 KiB = 12.52 MiB
251 00:25:22.540936 output: Architecture: AArch64
252 00:25:22.540987 output: OS: Linux
253 00:25:22.541036 output: Load Address: 0x00000000
254 00:25:22.541088 output: Entry Point: 0x00000000
255 00:25:22.541140 output: Hash algo: crc32
256 00:25:22.541195 output: Hash value: ab2f7826
257 00:25:22.541251 output: Image 1 (fdt-1)
258 00:25:22.541306 output: Description: mt8192-asurada-spherion-r0
259 00:25:22.541359 output: Created: Fri Jun 21 01:25:22 2024
260 00:25:22.541414 output: Type: Flat Device Tree
261 00:25:22.541477 output: Compression: uncompressed
262 00:25:22.541536 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 00:25:22.541590 output: Architecture: AArch64
264 00:25:22.541642 output: Hash algo: crc32
265 00:25:22.541692 output: Hash value: 0f8e4d2e
266 00:25:22.541742 output: Image 2 (ramdisk-1)
267 00:25:22.541791 output: Description: unavailable
268 00:25:22.541843 output: Created: Fri Jun 21 01:25:22 2024
269 00:25:22.541892 output: Type: RAMDisk Image
270 00:25:22.541940 output: Compression: uncompressed
271 00:25:22.541994 output: Data Size: 18749430 Bytes = 18309.99 KiB = 17.88 MiB
272 00:25:22.542077 output: Architecture: AArch64
273 00:25:22.542125 output: OS: Linux
274 00:25:22.542173 output: Load Address: unavailable
275 00:25:22.542220 output: Entry Point: unavailable
276 00:25:22.542268 output: Hash algo: crc32
277 00:25:22.542315 output: Hash value: 17217dd7
278 00:25:22.542362 output: Default Configuration: 'conf-1'
279 00:25:22.542410 output: Configuration 0 (conf-1)
280 00:25:22.542457 output: Description: mt8192-asurada-spherion-r0
281 00:25:22.542505 output: Kernel: kernel-1
282 00:25:22.542552 output: Init Ramdisk: ramdisk-1
283 00:25:22.542600 output: FDT: fdt-1
284 00:25:22.542648 output: Loadables: kernel-1
285 00:25:22.542718 output:
286 00:25:22.542863 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 00:25:22.542953 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 00:25:22.543043 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 00:25:22.543125 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:37) [common]
290 00:25:22.543193 No LXC device requested
291 00:25:22.543262 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 00:25:22.543338 start: 1.8 deploy-device-env (timeout 00:09:37) [common]
293 00:25:22.543412 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 00:25:22.543475 Checking files for TFTP limit of 4294967296 bytes.
295 00:25:22.543916 end: 1 tftp-deploy (duration 00:00:23) [common]
296 00:25:22.544018 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 00:25:22.544103 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 00:25:22.544214 substitutions:
299 00:25:22.544276 - {DTB}: 14479197/tftp-deploy-n9hju5wc/dtb/mt8192-asurada-spherion-r0.dtb
300 00:25:22.544333 - {INITRD}: 14479197/tftp-deploy-n9hju5wc/ramdisk/ramdisk.cpio.gz
301 00:25:22.544385 - {KERNEL}: 14479197/tftp-deploy-n9hju5wc/kernel/Image
302 00:25:22.544453 - {LAVA_MAC}: None
303 00:25:22.544517 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14479197/extract-nfsrootfs-dddnrq79
304 00:25:22.544567 - {NFS_SERVER_IP}: 192.168.201.1
305 00:25:22.544616 - {PRESEED_CONFIG}: None
306 00:25:22.544673 - {PRESEED_LOCAL}: None
307 00:25:22.544723 - {RAMDISK}: 14479197/tftp-deploy-n9hju5wc/ramdisk/ramdisk.cpio.gz
308 00:25:22.544771 - {ROOT_PART}: None
309 00:25:22.544820 - {ROOT}: None
310 00:25:22.544868 - {SERVER_IP}: 192.168.201.1
311 00:25:22.544916 - {TEE}: None
312 00:25:22.544965 Parsed boot commands:
313 00:25:22.545012 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 00:25:22.545162 Parsed boot commands: tftpboot 192.168.201.1 14479197/tftp-deploy-n9hju5wc/kernel/image.itb 14479197/tftp-deploy-n9hju5wc/kernel/cmdline
315 00:25:22.545245 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 00:25:22.545323 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 00:25:22.545404 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 00:25:22.545481 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 00:25:22.545548 Not connected, no need to disconnect.
320 00:25:22.545618 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 00:25:22.545695 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 00:25:22.545755 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
323 00:25:22.549286 Setting prompt string to ['lava-test: # ']
324 00:25:22.549616 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 00:25:22.549717 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 00:25:22.549807 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 00:25:22.549887 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 00:25:22.550161 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
329 00:25:29.203642 >> Command sent successfully.
330 00:25:29.216945 Returned 0 in 6 seconds
331 00:25:29.318118 end: 2.2.2.1 pdu-reboot (duration 00:00:07) [common]
333 00:25:29.319413 end: 2.2.2 reset-device (duration 00:00:07) [common]
334 00:25:29.319881 start: 2.2.3 depthcharge-start (timeout 00:04:53) [common]
335 00:25:29.320290 Setting prompt string to 'Starting depthcharge on Spherion...'
336 00:25:29.320594 Changing prompt to 'Starting depthcharge on Spherion...'
337 00:25:29.320905 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 00:25:29.322534 [Enter `^Ec?' for help]
339 00:25:29.322899
340 00:25:29.323218
341 00:25:29.323532 F0: 102B 0000
342 00:25:29.323832
343 00:25:29.324118 F3: 1001 0000 [0200]
344 00:25:29.324402
345 00:25:29.324701 F3: 1001 0000
346 00:25:29.324980
347 00:25:29.325250 F7: 102D 0000
348 00:25:29.325512
349 00:25:29.325762 F1: 0000 0000
350 00:25:29.326043
351 00:25:29.326437 V0: 0000 0000 [0001]
352 00:25:29.326868
353 00:25:29.327143 00: 0007 8000
354 00:25:29.327418
355 00:25:29.327666 01: 0000 0000
356 00:25:29.327922
357 00:25:29.328175 BP: 0C00 0209 [0000]
358 00:25:29.328457
359 00:25:29.328725 G0: 1182 0000
360 00:25:29.328977
361 00:25:29.329225 EC: 0000 0021 [4000]
362 00:25:29.329471
363 00:25:29.329746 S7: 0000 0000 [0000]
364 00:25:29.330019
365 00:25:29.330302 CC: 0000 0000 [0001]
366 00:25:29.330550
367 00:25:29.330796 T0: 0000 0040 [010F]
368 00:25:29.331047
369 00:25:29.331291 Jump to BL
370 00:25:29.331533
371 00:25:29.331815
372 00:25:29.332095
373 00:25:29.332344 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
374 00:25:29.332601 ARM64: Exception handlers installed.
375 00:25:29.332950 ARM64: Testing exception
376 00:25:29.333217 ARM64: Done test exception
377 00:25:29.334418 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
378 00:25:29.344859 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
379 00:25:29.350980 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
380 00:25:29.361642 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
381 00:25:29.368216 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
382 00:25:29.374596 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
383 00:25:29.385972 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
384 00:25:29.392879 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
385 00:25:29.412083 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
386 00:25:29.415125 WDT: Last reset was cold boot
387 00:25:29.418790 SPI1(PAD0) initialized at 2873684 Hz
388 00:25:29.422064 SPI5(PAD0) initialized at 992727 Hz
389 00:25:29.425854 VBOOT: Loading verstage.
390 00:25:29.432148 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
391 00:25:29.435369 FMAP: Found "FLASH" version 1.1 at 0x20000.
392 00:25:29.438785 FMAP: base = 0x0 size = 0x800000 #areas = 25
393 00:25:29.441900 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
394 00:25:29.449521 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
395 00:25:29.456217 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
396 00:25:29.466711 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
397 00:25:29.467166
398 00:25:29.467474
399 00:25:29.477134 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
400 00:25:29.480295 ARM64: Exception handlers installed.
401 00:25:29.483673 ARM64: Testing exception
402 00:25:29.484056 ARM64: Done test exception
403 00:25:29.490630 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
404 00:25:29.493472 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
405 00:25:29.508086 Probing TPM: . done!
406 00:25:29.508550 TPM ready after 0 ms
407 00:25:29.514941 Connected to device vid:did:rid of 1ae0:0028:00
408 00:25:29.521928 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
409 00:25:29.525578 Initialized TPM device CR50 revision 0
410 00:25:29.574547 tlcl_send_startup: Startup return code is 0
411 00:25:29.575009 TPM: setup succeeded
412 00:25:29.586042 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
413 00:25:29.594993 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
414 00:25:29.605046 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
415 00:25:29.614143 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
416 00:25:29.617602 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
417 00:25:29.620571 in-header: 03 07 00 00 08 00 00 00
418 00:25:29.624284 in-data: aa e4 47 04 13 02 00 00
419 00:25:29.627573 Chrome EC: UHEPI supported
420 00:25:29.633801 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
421 00:25:29.637355 in-header: 03 c9 00 00 08 00 00 00
422 00:25:29.640943 in-data: 04 00 20 08 00 00 00 00
423 00:25:29.641340 Phase 1
424 00:25:29.644238 FMAP: area GBB found @ 3f5000 (12032 bytes)
425 00:25:29.650823 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
426 00:25:29.657209 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
427 00:25:29.661132 Recovery requested (1009000e)
428 00:25:29.667203 TPM: Extending digest for VBOOT: boot mode into PCR 0
429 00:25:29.672533 tlcl_extend: response is 0
430 00:25:29.683503 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
431 00:25:29.686531 tlcl_extend: response is 0
432 00:25:29.693142 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
433 00:25:29.713310 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
434 00:25:29.720288 BS: bootblock times (exec / console): total (unknown) / 148 ms
435 00:25:29.720797
436 00:25:29.721127
437 00:25:29.730097 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
438 00:25:29.733221 ARM64: Exception handlers installed.
439 00:25:29.736563 ARM64: Testing exception
440 00:25:29.736972 ARM64: Done test exception
441 00:25:29.758991 pmic_efuse_setting: Set efuses in 11 msecs
442 00:25:29.762069 pmwrap_interface_init: Select PMIF_VLD_RDY
443 00:25:29.768626 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
444 00:25:29.772184 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
445 00:25:29.778926 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
446 00:25:29.782216 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
447 00:25:29.788801 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
448 00:25:29.792067 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
449 00:25:29.795707 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
450 00:25:29.802507 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
451 00:25:29.805709 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
452 00:25:29.812816 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
453 00:25:29.816191 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
454 00:25:29.819159 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
455 00:25:29.826094 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
456 00:25:29.832621 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
457 00:25:29.836042 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
458 00:25:29.842656 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
459 00:25:29.849499 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
460 00:25:29.853269 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
461 00:25:29.859534 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
462 00:25:29.866266 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
463 00:25:29.869696 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
464 00:25:29.876803 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
465 00:25:29.883373 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
466 00:25:29.886242 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
467 00:25:29.893319 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
468 00:25:29.899797 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
469 00:25:29.903200 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
470 00:25:29.906607 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
471 00:25:29.913326 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
472 00:25:29.916873 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
473 00:25:29.923514 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
474 00:25:29.927008 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
475 00:25:29.933788 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
476 00:25:29.936941 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
477 00:25:29.944026 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
478 00:25:29.947354 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
479 00:25:29.954021 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
480 00:25:29.957171 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
481 00:25:29.963958 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
482 00:25:29.967244 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
483 00:25:29.970739 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
484 00:25:29.974298 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
485 00:25:29.981104 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
486 00:25:29.984736 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
487 00:25:29.987566 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
488 00:25:29.994836 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
489 00:25:29.997888 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
490 00:25:30.001492 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
491 00:25:30.005129 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
492 00:25:30.011790 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
493 00:25:30.014999 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
494 00:25:30.021286 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
495 00:25:30.031268 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
496 00:25:30.034834 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
497 00:25:30.041243 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
498 00:25:30.051801 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
499 00:25:30.054893 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
500 00:25:30.061895 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
501 00:25:30.065026 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 00:25:30.072045 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x32
503 00:25:30.078513 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
504 00:25:30.081856 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
505 00:25:30.084889 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
506 00:25:30.096521 [RTC]rtc_get_frequency_meter,154: input=15, output=790
507 00:25:30.106064 [RTC]rtc_get_frequency_meter,154: input=23, output=979
508 00:25:30.115696 [RTC]rtc_get_frequency_meter,154: input=19, output=885
509 00:25:30.124820 [RTC]rtc_get_frequency_meter,154: input=17, output=837
510 00:25:30.134103 [RTC]rtc_get_frequency_meter,154: input=16, output=814
511 00:25:30.143571 [RTC]rtc_get_frequency_meter,154: input=15, output=791
512 00:25:30.153424 [RTC]rtc_get_frequency_meter,154: input=16, output=813
513 00:25:30.156852 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
514 00:25:30.164249 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
515 00:25:30.167103 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
516 00:25:30.170807 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
517 00:25:30.176998 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
518 00:25:30.180735 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
519 00:25:30.183743 ADC[4]: Raw value=901697 ID=7
520 00:25:30.184211 ADC[3]: Raw value=213336 ID=1
521 00:25:30.187455 RAM Code: 0x71
522 00:25:30.190614 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
523 00:25:30.197649 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
524 00:25:30.204198 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
525 00:25:30.210937 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
526 00:25:30.214525 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
527 00:25:30.217572 in-header: 03 07 00 00 08 00 00 00
528 00:25:30.221419 in-data: aa e4 47 04 13 02 00 00
529 00:25:30.224292 Chrome EC: UHEPI supported
530 00:25:30.230971 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
531 00:25:30.234469 in-header: 03 c9 00 00 08 00 00 00
532 00:25:30.237618 in-data: 04 00 20 08 00 00 00 00
533 00:25:30.240938 MRC: failed to locate region type 0.
534 00:25:30.247793 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
535 00:25:30.251290 DRAM-K: Running full calibration
536 00:25:30.257727 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
537 00:25:30.258257 header.status = 0x0
538 00:25:30.261039 header.version = 0x6 (expected: 0x6)
539 00:25:30.264836 header.size = 0xd00 (expected: 0xd00)
540 00:25:30.267938 header.flags = 0x0
541 00:25:30.274916 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
542 00:25:30.291349 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
543 00:25:30.297322 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
544 00:25:30.300812 dram_init: ddr_geometry: 2
545 00:25:30.301200 [EMI] MDL number = 2
546 00:25:30.304994 [EMI] Get MDL freq = 0
547 00:25:30.307491 dram_init: ddr_type: 0
548 00:25:30.307850 is_discrete_lpddr4: 1
549 00:25:30.311041 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
550 00:25:30.311474
551 00:25:30.311780
552 00:25:30.314901 [Bian_co] ETT version 0.0.0.1
553 00:25:30.321519 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
554 00:25:30.322027
555 00:25:30.324423 dramc_set_vcore_voltage set vcore to 650000
556 00:25:30.324809 Read voltage for 800, 4
557 00:25:30.327419 Vio18 = 0
558 00:25:30.327796 Vcore = 650000
559 00:25:30.328093 Vdram = 0
560 00:25:30.331000 Vddq = 0
561 00:25:30.331570 Vmddr = 0
562 00:25:30.334437 dram_init: config_dvfs: 1
563 00:25:30.337773 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
564 00:25:30.344352 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
565 00:25:30.348037 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
566 00:25:30.351369 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
567 00:25:30.354292 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
568 00:25:30.358012 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
569 00:25:30.361451 MEM_TYPE=3, freq_sel=18
570 00:25:30.364907 sv_algorithm_assistance_LP4_1600
571 00:25:30.368449 ============ PULL DRAM RESETB DOWN ============
572 00:25:30.371315 ========== PULL DRAM RESETB DOWN end =========
573 00:25:30.378247 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
574 00:25:30.381459 ===================================
575 00:25:30.381845 LPDDR4 DRAM CONFIGURATION
576 00:25:30.385067 ===================================
577 00:25:30.387821 EX_ROW_EN[0] = 0x0
578 00:25:30.391625 EX_ROW_EN[1] = 0x0
579 00:25:30.392097 LP4Y_EN = 0x0
580 00:25:30.394875 WORK_FSP = 0x0
581 00:25:30.395348 WL = 0x2
582 00:25:30.398273 RL = 0x2
583 00:25:30.398748 BL = 0x2
584 00:25:30.401680 RPST = 0x0
585 00:25:30.402094 RD_PRE = 0x0
586 00:25:30.404844 WR_PRE = 0x1
587 00:25:30.405321 WR_PST = 0x0
588 00:25:30.407984 DBI_WR = 0x0
589 00:25:30.408382 DBI_RD = 0x0
590 00:25:30.411715 OTF = 0x1
591 00:25:30.414841 ===================================
592 00:25:30.418604 ===================================
593 00:25:30.419073 ANA top config
594 00:25:30.421525 ===================================
595 00:25:30.425202 DLL_ASYNC_EN = 0
596 00:25:30.427952 ALL_SLAVE_EN = 1
597 00:25:30.428339 NEW_RANK_MODE = 1
598 00:25:30.431657 DLL_IDLE_MODE = 1
599 00:25:30.434649 LP45_APHY_COMB_EN = 1
600 00:25:30.438502 TX_ODT_DIS = 1
601 00:25:30.438977 NEW_8X_MODE = 1
602 00:25:30.441703 ===================================
603 00:25:30.445124 ===================================
604 00:25:30.448067 data_rate = 1600
605 00:25:30.451484 CKR = 1
606 00:25:30.455276 DQ_P2S_RATIO = 8
607 00:25:30.458848 ===================================
608 00:25:30.461807 CA_P2S_RATIO = 8
609 00:25:30.465768 DQ_CA_OPEN = 0
610 00:25:30.466283 DQ_SEMI_OPEN = 0
611 00:25:30.468760 CA_SEMI_OPEN = 0
612 00:25:30.472108 CA_FULL_RATE = 0
613 00:25:30.475355 DQ_CKDIV4_EN = 1
614 00:25:30.478881 CA_CKDIV4_EN = 1
615 00:25:30.482011 CA_PREDIV_EN = 0
616 00:25:30.482526 PH8_DLY = 0
617 00:25:30.485130 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
618 00:25:30.488465 DQ_AAMCK_DIV = 4
619 00:25:30.492196 CA_AAMCK_DIV = 4
620 00:25:30.495769 CA_ADMCK_DIV = 4
621 00:25:30.496247 DQ_TRACK_CA_EN = 0
622 00:25:30.498738 CA_PICK = 800
623 00:25:30.502100 CA_MCKIO = 800
624 00:25:30.505457 MCKIO_SEMI = 0
625 00:25:30.508647 PLL_FREQ = 3068
626 00:25:30.512292 DQ_UI_PI_RATIO = 32
627 00:25:30.516155 CA_UI_PI_RATIO = 0
628 00:25:30.519053 ===================================
629 00:25:30.522430 ===================================
630 00:25:30.522942 memory_type:LPDDR4
631 00:25:30.525802 GP_NUM : 10
632 00:25:30.526344 SRAM_EN : 1
633 00:25:30.529281 MD32_EN : 0
634 00:25:30.532044 ===================================
635 00:25:30.535678 [ANA_INIT] >>>>>>>>>>>>>>
636 00:25:30.538694 <<<<<< [CONFIGURE PHASE]: ANA_TX
637 00:25:30.542480 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
638 00:25:30.545505 ===================================
639 00:25:30.545979 data_rate = 1600,PCW = 0X7600
640 00:25:30.548685 ===================================
641 00:25:30.552105 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
642 00:25:30.559410 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
643 00:25:30.565903 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 00:25:30.569896 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
645 00:25:30.573048 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
646 00:25:30.575675 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
647 00:25:30.579467 [ANA_INIT] flow start
648 00:25:30.579952 [ANA_INIT] PLL >>>>>>>>
649 00:25:30.582689 [ANA_INIT] PLL <<<<<<<<
650 00:25:30.586331 [ANA_INIT] MIDPI >>>>>>>>
651 00:25:30.589227 [ANA_INIT] MIDPI <<<<<<<<
652 00:25:30.589699 [ANA_INIT] DLL >>>>>>>>
653 00:25:30.592825 [ANA_INIT] flow end
654 00:25:30.595995 ============ LP4 DIFF to SE enter ============
655 00:25:30.599403 ============ LP4 DIFF to SE exit ============
656 00:25:30.602649 [ANA_INIT] <<<<<<<<<<<<<
657 00:25:30.606276 [Flow] Enable top DCM control >>>>>
658 00:25:30.609628 [Flow] Enable top DCM control <<<<<
659 00:25:30.613100 Enable DLL master slave shuffle
660 00:25:30.616231 ==============================================================
661 00:25:30.619747 Gating Mode config
662 00:25:30.626356 ==============================================================
663 00:25:30.626830 Config description:
664 00:25:30.636236 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
665 00:25:30.642564 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
666 00:25:30.649668 SELPH_MODE 0: By rank 1: By Phase
667 00:25:30.652926 ==============================================================
668 00:25:30.656325 GAT_TRACK_EN = 1
669 00:25:30.659552 RX_GATING_MODE = 2
670 00:25:30.662789 RX_GATING_TRACK_MODE = 2
671 00:25:30.666311 SELPH_MODE = 1
672 00:25:30.669825 PICG_EARLY_EN = 1
673 00:25:30.672964 VALID_LAT_VALUE = 1
674 00:25:30.676418 ==============================================================
675 00:25:30.679672 Enter into Gating configuration >>>>
676 00:25:30.682923 Exit from Gating configuration <<<<
677 00:25:30.686731 Enter into DVFS_PRE_config >>>>>
678 00:25:30.696409 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
679 00:25:30.699698 Exit from DVFS_PRE_config <<<<<
680 00:25:30.703026 Enter into PICG configuration >>>>
681 00:25:30.706869 Exit from PICG configuration <<<<
682 00:25:30.709885 [RX_INPUT] configuration >>>>>
683 00:25:30.713575 [RX_INPUT] configuration <<<<<
684 00:25:30.720239 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
685 00:25:30.723004 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
686 00:25:30.729961 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
687 00:25:30.736058 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
688 00:25:30.742768 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
689 00:25:30.749934 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
690 00:25:30.753522 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
691 00:25:30.756388 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
692 00:25:30.759980 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
693 00:25:30.762763 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
694 00:25:30.769879 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
695 00:25:30.773600 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
696 00:25:30.776326 ===================================
697 00:25:30.779372 LPDDR4 DRAM CONFIGURATION
698 00:25:30.782781 ===================================
699 00:25:30.783240 EX_ROW_EN[0] = 0x0
700 00:25:30.786147 EX_ROW_EN[1] = 0x0
701 00:25:30.786539 LP4Y_EN = 0x0
702 00:25:30.789869 WORK_FSP = 0x0
703 00:25:30.790314 WL = 0x2
704 00:25:30.793788 RL = 0x2
705 00:25:30.794316 BL = 0x2
706 00:25:30.796899 RPST = 0x0
707 00:25:30.797369 RD_PRE = 0x0
708 00:25:30.799812 WR_PRE = 0x1
709 00:25:30.800288 WR_PST = 0x0
710 00:25:30.802632 DBI_WR = 0x0
711 00:25:30.806418 DBI_RD = 0x0
712 00:25:30.806840 OTF = 0x1
713 00:25:30.810312 ===================================
714 00:25:30.813606 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
715 00:25:30.816975 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
716 00:25:30.823610 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
717 00:25:30.826599 ===================================
718 00:25:30.827077 LPDDR4 DRAM CONFIGURATION
719 00:25:30.830397 ===================================
720 00:25:30.833013 EX_ROW_EN[0] = 0x10
721 00:25:30.836540 EX_ROW_EN[1] = 0x0
722 00:25:30.836931 LP4Y_EN = 0x0
723 00:25:30.840072 WORK_FSP = 0x0
724 00:25:30.840480 WL = 0x2
725 00:25:30.843005 RL = 0x2
726 00:25:30.843468 BL = 0x2
727 00:25:30.846621 RPST = 0x0
728 00:25:30.847019 RD_PRE = 0x0
729 00:25:30.850235 WR_PRE = 0x1
730 00:25:30.850806 WR_PST = 0x0
731 00:25:30.853696 DBI_WR = 0x0
732 00:25:30.854249 DBI_RD = 0x0
733 00:25:30.856494 OTF = 0x1
734 00:25:30.859782 ===================================
735 00:25:30.866320 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
736 00:25:30.869874 nWR fixed to 40
737 00:25:30.870420 [ModeRegInit_LP4] CH0 RK0
738 00:25:30.873448 [ModeRegInit_LP4] CH0 RK1
739 00:25:30.876415 [ModeRegInit_LP4] CH1 RK0
740 00:25:30.880007 [ModeRegInit_LP4] CH1 RK1
741 00:25:30.880399 match AC timing 13
742 00:25:30.883105 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
743 00:25:30.886599 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
744 00:25:30.893547 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
745 00:25:30.896870 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
746 00:25:30.903608 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
747 00:25:30.904026 [EMI DOE] emi_dcm 0
748 00:25:30.907318 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
749 00:25:30.910272 ==
750 00:25:30.913753 Dram Type= 6, Freq= 0, CH_0, rank 0
751 00:25:30.916769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
752 00:25:30.917173 ==
753 00:25:30.920052 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
754 00:25:30.927014 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
755 00:25:30.936529 [CA 0] Center 37 (7~68) winsize 62
756 00:25:30.940302 [CA 1] Center 37 (6~68) winsize 63
757 00:25:30.943126 [CA 2] Center 35 (5~66) winsize 62
758 00:25:30.946645 [CA 3] Center 34 (4~65) winsize 62
759 00:25:30.950273 [CA 4] Center 34 (3~65) winsize 63
760 00:25:30.953339 [CA 5] Center 33 (3~64) winsize 62
761 00:25:30.953705
762 00:25:30.956860 [CmdBusTrainingLP45] Vref(ca) range 1: 34
763 00:25:30.957324
764 00:25:30.960399 [CATrainingPosCal] consider 1 rank data
765 00:25:30.963247 u2DelayCellTimex100 = 270/100 ps
766 00:25:30.966630 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
767 00:25:30.970236 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
768 00:25:30.973734 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
769 00:25:30.977646 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
770 00:25:30.981006 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
771 00:25:30.987582 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
772 00:25:30.987934
773 00:25:30.990741 CA PerBit enable=1, Macro0, CA PI delay=33
774 00:25:30.991095
775 00:25:30.994466 [CBTSetCACLKResult] CA Dly = 33
776 00:25:30.994821 CS Dly: 6 (0~37)
777 00:25:30.995097 ==
778 00:25:30.997462 Dram Type= 6, Freq= 0, CH_0, rank 1
779 00:25:31.001005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 00:25:31.004431 ==
781 00:25:31.007928 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 00:25:31.014180 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 00:25:31.022827 [CA 0] Center 37 (6~68) winsize 63
784 00:25:31.026271 [CA 1] Center 37 (7~68) winsize 62
785 00:25:31.029296 [CA 2] Center 35 (4~66) winsize 63
786 00:25:31.032882 [CA 3] Center 35 (4~66) winsize 63
787 00:25:31.035928 [CA 4] Center 34 (4~65) winsize 62
788 00:25:31.039509 [CA 5] Center 33 (3~64) winsize 62
789 00:25:31.039866
790 00:25:31.043077 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 00:25:31.043434
792 00:25:31.046256 [CATrainingPosCal] consider 2 rank data
793 00:25:31.049702 u2DelayCellTimex100 = 270/100 ps
794 00:25:31.052628 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
795 00:25:31.056175 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
796 00:25:31.062684 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 00:25:31.066335 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
798 00:25:31.069609 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
799 00:25:31.073180 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 00:25:31.073533
801 00:25:31.076157 CA PerBit enable=1, Macro0, CA PI delay=33
802 00:25:31.076749
803 00:25:31.079926 [CBTSetCACLKResult] CA Dly = 33
804 00:25:31.080282 CS Dly: 6 (0~38)
805 00:25:31.080587
806 00:25:31.082919 ----->DramcWriteLeveling(PI) begin...
807 00:25:31.086285 ==
808 00:25:31.089891 Dram Type= 6, Freq= 0, CH_0, rank 0
809 00:25:31.092708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 00:25:31.093065 ==
811 00:25:31.096531 Write leveling (Byte 0): 28 => 28
812 00:25:31.099474 Write leveling (Byte 1): 27 => 27
813 00:25:31.103151 DramcWriteLeveling(PI) end<-----
814 00:25:31.103507
815 00:25:31.103785 ==
816 00:25:31.106113 Dram Type= 6, Freq= 0, CH_0, rank 0
817 00:25:31.109943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
818 00:25:31.110571 ==
819 00:25:31.112794 [Gating] SW mode calibration
820 00:25:31.119313 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
821 00:25:31.122934 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
822 00:25:31.129761 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
823 00:25:31.132904 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 00:25:31.136614 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
825 00:25:31.143210 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 00:25:31.146707 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 00:25:31.149505 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 00:25:31.156455 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 00:25:31.159403 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 00:25:31.163138 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 00:25:31.169296 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 00:25:31.172925 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 00:25:31.176421 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 00:25:31.183237 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 00:25:31.186712 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 00:25:31.189623 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 00:25:31.193106 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 00:25:31.199808 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 00:25:31.203433 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 00:25:31.206305 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
841 00:25:31.213508 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 00:25:31.216458 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 00:25:31.220217 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 00:25:31.226678 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 00:25:31.230164 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 00:25:31.233063 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 00:25:31.239861 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 00:25:31.243255 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 00:25:31.246494 0 9 12 | B1->B0 | 2424 3030 | 1 0 | (1 1) (0 0)
850 00:25:31.253592 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
851 00:25:31.256867 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 00:25:31.260235 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 00:25:31.263307 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 00:25:31.270080 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 00:25:31.273504 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
856 00:25:31.276807 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 1)
857 00:25:31.283595 0 10 12 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
858 00:25:31.286511 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:25:31.290179 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:25:31.296869 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:25:31.300242 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:25:31.303710 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:25:31.310446 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 00:25:31.313405 0 11 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
865 00:25:31.316404 0 11 12 | B1->B0 | 3837 3c3c | 1 0 | (0 0) (0 0)
866 00:25:31.323623 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 00:25:31.327374 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 00:25:31.330255 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 00:25:31.336772 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 00:25:31.340255 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 00:25:31.343335 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 00:25:31.346929 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 00:25:31.353691 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
874 00:25:31.356837 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 00:25:31.360263 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 00:25:31.366873 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 00:25:31.370271 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 00:25:31.373488 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 00:25:31.380176 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 00:25:31.383132 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 00:25:31.386547 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 00:25:31.393235 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 00:25:31.396800 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 00:25:31.400409 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 00:25:31.406876 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 00:25:31.410382 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 00:25:31.413416 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 00:25:31.419813 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
889 00:25:31.423051 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
890 00:25:31.426529 Total UI for P1: 0, mck2ui 16
891 00:25:31.429599 best dqsien dly found for B0: ( 0, 14, 8)
892 00:25:31.433121 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 00:25:31.436251 Total UI for P1: 0, mck2ui 16
894 00:25:31.439959 best dqsien dly found for B1: ( 0, 14, 10)
895 00:25:31.443128 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
896 00:25:31.446925 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
897 00:25:31.447078
898 00:25:31.449896 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
899 00:25:31.456465 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
900 00:25:31.456632 [Gating] SW calibration Done
901 00:25:31.456725 ==
902 00:25:31.459853 Dram Type= 6, Freq= 0, CH_0, rank 0
903 00:25:31.466169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 00:25:31.466245 ==
905 00:25:31.466305 RX Vref Scan: 0
906 00:25:31.466360
907 00:25:31.469815 RX Vref 0 -> 0, step: 1
908 00:25:31.469890
909 00:25:31.472817 RX Delay -130 -> 252, step: 16
910 00:25:31.476551 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
911 00:25:31.479995 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
912 00:25:31.483054 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
913 00:25:31.489889 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
914 00:25:31.492758 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
915 00:25:31.496521 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
916 00:25:31.499742 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
917 00:25:31.502605 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
918 00:25:31.509874 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
919 00:25:31.512969 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
920 00:25:31.516348 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
921 00:25:31.519808 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
922 00:25:31.522767 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
923 00:25:31.529488 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
924 00:25:31.533082 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
925 00:25:31.536100 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
926 00:25:31.536186 ==
927 00:25:31.539682 Dram Type= 6, Freq= 0, CH_0, rank 0
928 00:25:31.542906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 00:25:31.543009 ==
930 00:25:31.546321 DQS Delay:
931 00:25:31.546430 DQS0 = 0, DQS1 = 0
932 00:25:31.549740 DQM Delay:
933 00:25:31.549836 DQM0 = 83, DQM1 = 78
934 00:25:31.549915 DQ Delay:
935 00:25:31.553003 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
936 00:25:31.556489 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =85
937 00:25:31.559957 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
938 00:25:31.563292 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
939 00:25:31.563449
940 00:25:31.563571
941 00:25:31.563682 ==
942 00:25:31.566927 Dram Type= 6, Freq= 0, CH_0, rank 0
943 00:25:31.573454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 00:25:31.573692 ==
945 00:25:31.573862
946 00:25:31.574053
947 00:25:31.574209 TX Vref Scan disable
948 00:25:31.577164 == TX Byte 0 ==
949 00:25:31.580322 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
950 00:25:31.586734 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
951 00:25:31.587093 == TX Byte 1 ==
952 00:25:31.590646 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
953 00:25:31.596937 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
954 00:25:31.597299 ==
955 00:25:31.600198 Dram Type= 6, Freq= 0, CH_0, rank 0
956 00:25:31.604029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 00:25:31.604504 ==
958 00:25:31.616351 TX Vref=22, minBit 0, minWin=27, winSum=438
959 00:25:31.619760 TX Vref=24, minBit 3, minWin=27, winSum=442
960 00:25:31.622872 TX Vref=26, minBit 5, minWin=27, winSum=445
961 00:25:31.626280 TX Vref=28, minBit 5, minWin=27, winSum=450
962 00:25:31.629530 TX Vref=30, minBit 2, minWin=28, winSum=453
963 00:25:31.636351 TX Vref=32, minBit 12, minWin=27, winSum=452
964 00:25:31.639822 [TxChooseVref] Worse bit 2, Min win 28, Win sum 453, Final Vref 30
965 00:25:31.640278
966 00:25:31.642832 Final TX Range 1 Vref 30
967 00:25:31.643261
968 00:25:31.643559 ==
969 00:25:31.646422 Dram Type= 6, Freq= 0, CH_0, rank 0
970 00:25:31.649420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 00:25:31.649798 ==
972 00:25:31.650135
973 00:25:31.652779
974 00:25:31.653171 TX Vref Scan disable
975 00:25:31.656417 == TX Byte 0 ==
976 00:25:31.659456 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
977 00:25:31.662945 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
978 00:25:31.666417 == TX Byte 1 ==
979 00:25:31.669808 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
980 00:25:31.673045 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
981 00:25:31.676463
982 00:25:31.676872 [DATLAT]
983 00:25:31.677183 Freq=800, CH0 RK0
984 00:25:31.677461
985 00:25:31.679485 DATLAT Default: 0xa
986 00:25:31.679869 0, 0xFFFF, sum = 0
987 00:25:31.683206 1, 0xFFFF, sum = 0
988 00:25:31.683564 2, 0xFFFF, sum = 0
989 00:25:31.686053 3, 0xFFFF, sum = 0
990 00:25:31.686546 4, 0xFFFF, sum = 0
991 00:25:31.689651 5, 0xFFFF, sum = 0
992 00:25:31.693260 6, 0xFFFF, sum = 0
993 00:25:31.693622 7, 0xFFFF, sum = 0
994 00:25:31.696285 8, 0xFFFF, sum = 0
995 00:25:31.696669 9, 0x0, sum = 1
996 00:25:31.696950 10, 0x0, sum = 2
997 00:25:31.699925 11, 0x0, sum = 3
998 00:25:31.700324 12, 0x0, sum = 4
999 00:25:31.702866 best_step = 10
1000 00:25:31.703214
1001 00:25:31.703484 ==
1002 00:25:31.706435 Dram Type= 6, Freq= 0, CH_0, rank 0
1003 00:25:31.709708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1004 00:25:31.710181 ==
1005 00:25:31.712933 RX Vref Scan: 1
1006 00:25:31.713285
1007 00:25:31.713558 Set Vref Range= 32 -> 127
1008 00:25:31.713851
1009 00:25:31.716129 RX Vref 32 -> 127, step: 1
1010 00:25:31.716638
1011 00:25:31.719507 RX Delay -95 -> 252, step: 8
1012 00:25:31.719858
1013 00:25:31.722936 Set Vref, RX VrefLevel [Byte0]: 32
1014 00:25:31.726840 [Byte1]: 32
1015 00:25:31.727194
1016 00:25:31.729611 Set Vref, RX VrefLevel [Byte0]: 33
1017 00:25:31.733011 [Byte1]: 33
1018 00:25:31.736667
1019 00:25:31.737172 Set Vref, RX VrefLevel [Byte0]: 34
1020 00:25:31.739660 [Byte1]: 34
1021 00:25:31.744420
1022 00:25:31.744773 Set Vref, RX VrefLevel [Byte0]: 35
1023 00:25:31.747327 [Byte1]: 35
1024 00:25:31.751741
1025 00:25:31.752155 Set Vref, RX VrefLevel [Byte0]: 36
1026 00:25:31.755209 [Byte1]: 36
1027 00:25:31.759332
1028 00:25:31.759708 Set Vref, RX VrefLevel [Byte0]: 37
1029 00:25:31.762954 [Byte1]: 37
1030 00:25:31.767170
1031 00:25:31.767708 Set Vref, RX VrefLevel [Byte0]: 38
1032 00:25:31.770071 [Byte1]: 38
1033 00:25:31.774715
1034 00:25:31.775123 Set Vref, RX VrefLevel [Byte0]: 39
1035 00:25:31.778098 [Byte1]: 39
1036 00:25:31.781917
1037 00:25:31.782508 Set Vref, RX VrefLevel [Byte0]: 40
1038 00:25:31.785794 [Byte1]: 40
1039 00:25:31.789861
1040 00:25:31.790334 Set Vref, RX VrefLevel [Byte0]: 41
1041 00:25:31.793330 [Byte1]: 41
1042 00:25:31.797271
1043 00:25:31.797603 Set Vref, RX VrefLevel [Byte0]: 42
1044 00:25:31.800337 [Byte1]: 42
1045 00:25:31.804574
1046 00:25:31.804734 Set Vref, RX VrefLevel [Byte0]: 43
1047 00:25:31.808187 [Byte1]: 43
1048 00:25:31.812439
1049 00:25:31.812575 Set Vref, RX VrefLevel [Byte0]: 44
1050 00:25:31.816118 [Byte1]: 44
1051 00:25:31.819881
1052 00:25:31.820020 Set Vref, RX VrefLevel [Byte0]: 45
1053 00:25:31.823122 [Byte1]: 45
1054 00:25:31.827417
1055 00:25:31.827595 Set Vref, RX VrefLevel [Byte0]: 46
1056 00:25:31.830788 [Byte1]: 46
1057 00:25:31.835098
1058 00:25:31.835250 Set Vref, RX VrefLevel [Byte0]: 47
1059 00:25:31.838676 [Byte1]: 47
1060 00:25:31.843036
1061 00:25:31.843315 Set Vref, RX VrefLevel [Byte0]: 48
1062 00:25:31.846080 [Byte1]: 48
1063 00:25:31.850377
1064 00:25:31.850633 Set Vref, RX VrefLevel [Byte0]: 49
1065 00:25:31.853841 [Byte1]: 49
1066 00:25:31.858130
1067 00:25:31.858521 Set Vref, RX VrefLevel [Byte0]: 50
1068 00:25:31.861787 [Byte1]: 50
1069 00:25:31.865768
1070 00:25:31.866397 Set Vref, RX VrefLevel [Byte0]: 51
1071 00:25:31.868796 [Byte1]: 51
1072 00:25:31.873832
1073 00:25:31.874461 Set Vref, RX VrefLevel [Byte0]: 52
1074 00:25:31.876608 [Byte1]: 52
1075 00:25:31.881095
1076 00:25:31.881599 Set Vref, RX VrefLevel [Byte0]: 53
1077 00:25:31.884004 [Byte1]: 53
1078 00:25:31.888511
1079 00:25:31.889016 Set Vref, RX VrefLevel [Byte0]: 54
1080 00:25:31.891837 [Byte1]: 54
1081 00:25:31.895979
1082 00:25:31.896526 Set Vref, RX VrefLevel [Byte0]: 55
1083 00:25:31.899460 [Byte1]: 55
1084 00:25:31.903520
1085 00:25:31.904044 Set Vref, RX VrefLevel [Byte0]: 56
1086 00:25:31.907249 [Byte1]: 56
1087 00:25:31.911350
1088 00:25:31.911892 Set Vref, RX VrefLevel [Byte0]: 57
1089 00:25:31.914913 [Byte1]: 57
1090 00:25:31.919290
1091 00:25:31.919675 Set Vref, RX VrefLevel [Byte0]: 58
1092 00:25:31.922181 [Byte1]: 58
1093 00:25:31.926393
1094 00:25:31.926786 Set Vref, RX VrefLevel [Byte0]: 59
1095 00:25:31.929892 [Byte1]: 59
1096 00:25:31.934197
1097 00:25:31.934703 Set Vref, RX VrefLevel [Byte0]: 60
1098 00:25:31.937414 [Byte1]: 60
1099 00:25:31.941816
1100 00:25:31.942290 Set Vref, RX VrefLevel [Byte0]: 61
1101 00:25:31.944877 [Byte1]: 61
1102 00:25:31.949142
1103 00:25:31.949711 Set Vref, RX VrefLevel [Byte0]: 62
1104 00:25:31.952706 [Byte1]: 62
1105 00:25:31.956726
1106 00:25:31.957251 Set Vref, RX VrefLevel [Byte0]: 63
1107 00:25:31.959947 [Byte1]: 63
1108 00:25:31.964468
1109 00:25:31.964994 Set Vref, RX VrefLevel [Byte0]: 64
1110 00:25:31.967574 [Byte1]: 64
1111 00:25:31.971989
1112 00:25:31.972392 Set Vref, RX VrefLevel [Byte0]: 65
1113 00:25:31.975662 [Byte1]: 65
1114 00:25:31.979748
1115 00:25:31.980151 Set Vref, RX VrefLevel [Byte0]: 66
1116 00:25:31.983174 [Byte1]: 66
1117 00:25:31.987389
1118 00:25:31.987791 Set Vref, RX VrefLevel [Byte0]: 67
1119 00:25:31.990800 [Byte1]: 67
1120 00:25:31.995060
1121 00:25:31.995464 Set Vref, RX VrefLevel [Byte0]: 68
1122 00:25:31.998305 [Byte1]: 68
1123 00:25:32.002699
1124 00:25:32.003103 Set Vref, RX VrefLevel [Byte0]: 69
1125 00:25:32.005940 [Byte1]: 69
1126 00:25:32.010411
1127 00:25:32.010812 Set Vref, RX VrefLevel [Byte0]: 70
1128 00:25:32.013437 [Byte1]: 70
1129 00:25:32.017579
1130 00:25:32.018035 Set Vref, RX VrefLevel [Byte0]: 71
1131 00:25:32.021221 [Byte1]: 71
1132 00:25:32.025608
1133 00:25:32.026026 Set Vref, RX VrefLevel [Byte0]: 72
1134 00:25:32.028569 [Byte1]: 72
1135 00:25:32.032902
1136 00:25:32.033303 Set Vref, RX VrefLevel [Byte0]: 73
1137 00:25:32.036518 [Byte1]: 73
1138 00:25:32.040597
1139 00:25:32.041000 Set Vref, RX VrefLevel [Byte0]: 74
1140 00:25:32.043855 [Byte1]: 74
1141 00:25:32.048339
1142 00:25:32.048741 Set Vref, RX VrefLevel [Byte0]: 75
1143 00:25:32.051190 [Byte1]: 75
1144 00:25:32.055990
1145 00:25:32.056394 Final RX Vref Byte 0 = 61 to rank0
1146 00:25:32.059055 Final RX Vref Byte 1 = 63 to rank0
1147 00:25:32.061972 Final RX Vref Byte 0 = 61 to rank1
1148 00:25:32.065534 Final RX Vref Byte 1 = 63 to rank1==
1149 00:25:32.069036 Dram Type= 6, Freq= 0, CH_0, rank 0
1150 00:25:32.075538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 00:25:32.075960 ==
1152 00:25:32.076360 DQS Delay:
1153 00:25:32.076736 DQS0 = 0, DQS1 = 0
1154 00:25:32.079135 DQM Delay:
1155 00:25:32.079536 DQM0 = 87, DQM1 = 78
1156 00:25:32.082117 DQ Delay:
1157 00:25:32.085682 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1158 00:25:32.089086 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1159 00:25:32.089482 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1160 00:25:32.095758 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1161 00:25:32.096144
1162 00:25:32.096694
1163 00:25:32.102243 [DQSOSCAuto] RK0, (LSB)MR18= 0x280f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 399 ps
1164 00:25:32.105766 CH0 RK0: MR19=606, MR18=280F
1165 00:25:32.112150 CH0_RK0: MR19=0x606, MR18=0x280F, DQSOSC=399, MR23=63, INC=92, DEC=61
1166 00:25:32.112583
1167 00:25:32.115490 ----->DramcWriteLeveling(PI) begin...
1168 00:25:32.115930 ==
1169 00:25:32.118449 Dram Type= 6, Freq= 0, CH_0, rank 1
1170 00:25:32.122101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1171 00:25:32.122534 ==
1172 00:25:32.125221 Write leveling (Byte 0): 29 => 29
1173 00:25:32.128894 Write leveling (Byte 1): 29 => 29
1174 00:25:32.131882 DramcWriteLeveling(PI) end<-----
1175 00:25:32.132323
1176 00:25:32.132655 ==
1177 00:25:32.135504 Dram Type= 6, Freq= 0, CH_0, rank 1
1178 00:25:32.138469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1179 00:25:32.138964 ==
1180 00:25:32.142396 [Gating] SW mode calibration
1181 00:25:32.148796 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1182 00:25:32.155263 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1183 00:25:32.158735 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1184 00:25:32.162261 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1185 00:25:32.169042 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1186 00:25:32.172050 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 00:25:32.175747 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 00:25:32.182036 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 00:25:32.185299 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 00:25:32.189261 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 00:25:32.233103 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 00:25:32.233529 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 00:25:32.233835 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 00:25:32.234494 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 00:25:32.234817 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 00:25:32.235113 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 00:25:32.235392 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 00:25:32.235665 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 00:25:32.235968 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 00:25:32.236227 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1201 00:25:32.268893 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1202 00:25:32.269312 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 00:25:32.269646 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 00:25:32.270511 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 00:25:32.270869 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 00:25:32.271160 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 00:25:32.271431 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 00:25:32.273427 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 00:25:32.276743 0 9 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
1210 00:25:32.277250 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1211 00:25:32.283392 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1212 00:25:32.286415 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1213 00:25:32.289974 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1214 00:25:32.296707 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1215 00:25:32.300279 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1216 00:25:32.303475 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1217 00:25:32.310530 0 10 8 | B1->B0 | 3131 2424 | 0 0 | (0 1) (0 0)
1218 00:25:32.313206 0 10 12 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
1219 00:25:32.316509 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 00:25:32.320053 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 00:25:32.326616 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 00:25:32.330053 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 00:25:32.333497 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 00:25:32.339810 0 11 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
1225 00:25:32.343777 0 11 8 | B1->B0 | 2a2a 4141 | 0 0 | (0 0) (0 0)
1226 00:25:32.346647 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1227 00:25:32.353829 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1228 00:25:32.356764 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1229 00:25:32.359964 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1230 00:25:32.366427 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1231 00:25:32.370029 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1232 00:25:32.373174 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1233 00:25:32.380123 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1234 00:25:32.383394 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1235 00:25:32.386971 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 00:25:32.393363 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 00:25:32.396764 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 00:25:32.400482 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 00:25:32.403630 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 00:25:32.410465 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 00:25:32.413758 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 00:25:32.417337 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 00:25:32.424012 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 00:25:32.427015 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 00:25:32.430547 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 00:25:32.436953 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 00:25:32.440510 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1248 00:25:32.444014 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1249 00:25:32.450237 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1250 00:25:32.450645 Total UI for P1: 0, mck2ui 16
1251 00:25:32.453722 best dqsien dly found for B0: ( 0, 14, 2)
1252 00:25:32.460279 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 00:25:32.464003 Total UI for P1: 0, mck2ui 16
1254 00:25:32.466859 best dqsien dly found for B1: ( 0, 14, 8)
1255 00:25:32.470490 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1256 00:25:32.473585 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1257 00:25:32.474019
1258 00:25:32.477292 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1259 00:25:32.480387 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1260 00:25:32.484052 [Gating] SW calibration Done
1261 00:25:32.484458 ==
1262 00:25:32.487093 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 00:25:32.490755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 00:25:32.491192 ==
1265 00:25:32.494041 RX Vref Scan: 0
1266 00:25:32.494438
1267 00:25:32.494742 RX Vref 0 -> 0, step: 1
1268 00:25:32.497004
1269 00:25:32.497429 RX Delay -130 -> 252, step: 16
1270 00:25:32.504109 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1271 00:25:32.506953 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1272 00:25:32.510694 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1273 00:25:32.513689 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1274 00:25:32.517326 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1275 00:25:32.523661 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1276 00:25:32.526949 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1277 00:25:32.530376 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1278 00:25:32.533875 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1279 00:25:32.536934 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1280 00:25:32.543756 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1281 00:25:32.547241 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1282 00:25:32.550400 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1283 00:25:32.553690 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1284 00:25:32.557180 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1285 00:25:32.563749 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1286 00:25:32.564272 ==
1287 00:25:32.566746 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 00:25:32.570177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 00:25:32.570665 ==
1290 00:25:32.571103 DQS Delay:
1291 00:25:32.573252 DQS0 = 0, DQS1 = 0
1292 00:25:32.573733 DQM Delay:
1293 00:25:32.576704 DQM0 = 84, DQM1 = 73
1294 00:25:32.577183 DQ Delay:
1295 00:25:32.580301 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1296 00:25:32.583266 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
1297 00:25:32.587047 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1298 00:25:32.589950 DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85
1299 00:25:32.590141
1300 00:25:32.590271
1301 00:25:32.590391 ==
1302 00:25:32.593629 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 00:25:32.596628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 00:25:32.596801 ==
1305 00:25:32.596931
1306 00:25:32.597051
1307 00:25:32.600255 TX Vref Scan disable
1308 00:25:32.603229 == TX Byte 0 ==
1309 00:25:32.606492 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1310 00:25:32.609796 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1311 00:25:32.613645 == TX Byte 1 ==
1312 00:25:32.616853 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1313 00:25:32.620005 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1314 00:25:32.620173 ==
1315 00:25:32.623594 Dram Type= 6, Freq= 0, CH_0, rank 1
1316 00:25:32.629903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1317 00:25:32.630123 ==
1318 00:25:32.642172 TX Vref=22, minBit 2, minWin=27, winSum=444
1319 00:25:32.645127 TX Vref=24, minBit 3, minWin=27, winSum=448
1320 00:25:32.648820 TX Vref=26, minBit 9, minWin=27, winSum=448
1321 00:25:32.651834 TX Vref=28, minBit 9, minWin=27, winSum=452
1322 00:25:32.655409 TX Vref=30, minBit 0, minWin=28, winSum=452
1323 00:25:32.658559 TX Vref=32, minBit 0, minWin=28, winSum=455
1324 00:25:32.665081 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 32
1325 00:25:32.665486
1326 00:25:32.668672 Final TX Range 1 Vref 32
1327 00:25:32.669067
1328 00:25:32.669366 ==
1329 00:25:32.672343 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 00:25:32.675167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 00:25:32.675556 ==
1332 00:25:32.675859
1333 00:25:32.678820
1334 00:25:32.679286 TX Vref Scan disable
1335 00:25:32.681942 == TX Byte 0 ==
1336 00:25:32.684961 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1337 00:25:32.688717 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1338 00:25:32.692046 == TX Byte 1 ==
1339 00:25:32.695433 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1340 00:25:32.698754 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1341 00:25:32.702071
1342 00:25:32.702535 [DATLAT]
1343 00:25:32.702841 Freq=800, CH0 RK1
1344 00:25:32.703123
1345 00:25:32.705417 DATLAT Default: 0xa
1346 00:25:32.705804 0, 0xFFFF, sum = 0
1347 00:25:32.708351 1, 0xFFFF, sum = 0
1348 00:25:32.708744 2, 0xFFFF, sum = 0
1349 00:25:32.711472 3, 0xFFFF, sum = 0
1350 00:25:32.711867 4, 0xFFFF, sum = 0
1351 00:25:32.715080 5, 0xFFFF, sum = 0
1352 00:25:32.718801 6, 0xFFFF, sum = 0
1353 00:25:32.719273 7, 0xFFFF, sum = 0
1354 00:25:32.721800 8, 0xFFFF, sum = 0
1355 00:25:32.722423 9, 0x0, sum = 1
1356 00:25:32.722752 10, 0x0, sum = 2
1357 00:25:32.725148 11, 0x0, sum = 3
1358 00:25:32.725544 12, 0x0, sum = 4
1359 00:25:32.728180 best_step = 10
1360 00:25:32.728633
1361 00:25:32.729058 ==
1362 00:25:32.731633 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 00:25:32.734651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 00:25:32.735044 ==
1365 00:25:32.738447 RX Vref Scan: 0
1366 00:25:32.738835
1367 00:25:32.739135 RX Vref 0 -> 0, step: 1
1368 00:25:32.739415
1369 00:25:32.741243 RX Delay -95 -> 252, step: 8
1370 00:25:32.748214 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1371 00:25:32.751351 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1372 00:25:32.755031 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1373 00:25:32.758502 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1374 00:25:32.761471 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1375 00:25:32.768176 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1376 00:25:32.771821 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1377 00:25:32.774551 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1378 00:25:32.778263 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1379 00:25:32.781165 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1380 00:25:32.787905 iDelay=209, Bit 10, Center 76 (-31 ~ 184) 216
1381 00:25:32.791450 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1382 00:25:32.794808 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1383 00:25:32.798094 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1384 00:25:32.804066 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1385 00:25:32.807750 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1386 00:25:32.807847 ==
1387 00:25:32.811131 Dram Type= 6, Freq= 0, CH_0, rank 1
1388 00:25:32.814248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1389 00:25:32.814330 ==
1390 00:25:32.814392 DQS Delay:
1391 00:25:32.817737 DQS0 = 0, DQS1 = 0
1392 00:25:32.817837 DQM Delay:
1393 00:25:32.820798 DQM0 = 87, DQM1 = 78
1394 00:25:32.820885 DQ Delay:
1395 00:25:32.824308 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1396 00:25:32.827335 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1397 00:25:32.830819 DQ8 =68, DQ9 =68, DQ10 =76, DQ11 =68
1398 00:25:32.834147 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1399 00:25:32.834222
1400 00:25:32.834280
1401 00:25:32.843901 [DQSOSCAuto] RK1, (LSB)MR18= 0x321c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1402 00:25:32.844018 CH0 RK1: MR19=606, MR18=321C
1403 00:25:32.850968 CH0_RK1: MR19=0x606, MR18=0x321C, DQSOSC=397, MR23=63, INC=93, DEC=62
1404 00:25:32.854158 [RxdqsGatingPostProcess] freq 800
1405 00:25:32.861118 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1406 00:25:32.864184 Pre-setting of DQS Precalculation
1407 00:25:32.867688 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1408 00:25:32.867812 ==
1409 00:25:32.870618 Dram Type= 6, Freq= 0, CH_1, rank 0
1410 00:25:32.874311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 00:25:32.877762 ==
1412 00:25:32.880910 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 00:25:32.887520 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 00:25:32.896320 [CA 0] Center 36 (6~66) winsize 61
1415 00:25:32.900177 [CA 1] Center 36 (6~66) winsize 61
1416 00:25:32.903050 [CA 2] Center 34 (4~65) winsize 62
1417 00:25:32.906420 [CA 3] Center 33 (3~64) winsize 62
1418 00:25:32.909544 [CA 4] Center 34 (3~65) winsize 63
1419 00:25:32.913404 [CA 5] Center 33 (3~64) winsize 62
1420 00:25:32.913831
1421 00:25:32.916300 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1422 00:25:32.916690
1423 00:25:32.919654 [CATrainingPosCal] consider 1 rank data
1424 00:25:32.923308 u2DelayCellTimex100 = 270/100 ps
1425 00:25:32.926526 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1426 00:25:32.929837 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1427 00:25:32.933216 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1428 00:25:32.939743 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1429 00:25:32.943304 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1430 00:25:32.947107 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1431 00:25:32.947269
1432 00:25:32.949532 CA PerBit enable=1, Macro0, CA PI delay=33
1433 00:25:32.949706
1434 00:25:32.953118 [CBTSetCACLKResult] CA Dly = 33
1435 00:25:32.953291 CS Dly: 4 (0~35)
1436 00:25:32.953413 ==
1437 00:25:32.956120 Dram Type= 6, Freq= 0, CH_1, rank 1
1438 00:25:32.963230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 00:25:32.963362 ==
1440 00:25:32.965924 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1441 00:25:32.973252 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1442 00:25:32.982087 [CA 0] Center 36 (6~66) winsize 61
1443 00:25:32.985795 [CA 1] Center 36 (6~67) winsize 62
1444 00:25:32.988787 [CA 2] Center 34 (4~65) winsize 62
1445 00:25:32.992361 [CA 3] Center 33 (3~64) winsize 62
1446 00:25:32.995592 [CA 4] Center 34 (4~65) winsize 62
1447 00:25:32.999171 [CA 5] Center 33 (3~64) winsize 62
1448 00:25:32.999576
1449 00:25:33.002430 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1450 00:25:33.002832
1451 00:25:33.005825 [CATrainingPosCal] consider 2 rank data
1452 00:25:33.008997 u2DelayCellTimex100 = 270/100 ps
1453 00:25:33.012506 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1454 00:25:33.016051 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1455 00:25:33.022129 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1456 00:25:33.025812 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1457 00:25:33.029241 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1458 00:25:33.032347 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1459 00:25:33.032752
1460 00:25:33.035766 CA PerBit enable=1, Macro0, CA PI delay=33
1461 00:25:33.036170
1462 00:25:33.039528 [CBTSetCACLKResult] CA Dly = 33
1463 00:25:33.039932 CS Dly: 5 (0~37)
1464 00:25:33.040330
1465 00:25:33.042366 ----->DramcWriteLeveling(PI) begin...
1466 00:25:33.045937 ==
1467 00:25:33.046387 Dram Type= 6, Freq= 0, CH_1, rank 0
1468 00:25:33.052656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1469 00:25:33.053152 ==
1470 00:25:33.056335 Write leveling (Byte 0): 27 => 27
1471 00:25:33.059267 Write leveling (Byte 1): 30 => 30
1472 00:25:33.062548 DramcWriteLeveling(PI) end<-----
1473 00:25:33.062940
1474 00:25:33.063243 ==
1475 00:25:33.066058 Dram Type= 6, Freq= 0, CH_1, rank 0
1476 00:25:33.069295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1477 00:25:33.069764 ==
1478 00:25:33.072903 [Gating] SW mode calibration
1479 00:25:33.079423 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1480 00:25:33.082697 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1481 00:25:33.089102 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1482 00:25:33.092822 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1483 00:25:33.096141 0 6 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1484 00:25:33.102602 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 00:25:33.105754 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 00:25:33.109516 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 00:25:33.116115 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 00:25:33.119007 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 00:25:33.122309 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 00:25:33.129451 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 00:25:33.132162 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 00:25:33.135866 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 00:25:33.142382 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 00:25:33.145753 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 00:25:33.149078 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 00:25:33.155790 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 00:25:33.159233 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 00:25:33.162501 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1499 00:25:33.169669 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1500 00:25:33.173105 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 00:25:33.176050 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 00:25:33.179903 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 00:25:33.186122 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 00:25:33.189460 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 00:25:33.192921 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 00:25:33.199349 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 00:25:33.202857 0 9 8 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
1508 00:25:33.205738 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1509 00:25:33.212878 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1510 00:25:33.216166 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1511 00:25:33.219413 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1512 00:25:33.225843 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1513 00:25:33.229255 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1514 00:25:33.232538 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
1515 00:25:33.239320 0 10 8 | B1->B0 | 2727 2b2b | 0 1 | (1 0) (1 0)
1516 00:25:33.242769 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 00:25:33.245897 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 00:25:33.252509 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 00:25:33.256564 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 00:25:33.259261 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 00:25:33.262950 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 00:25:33.269626 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 00:25:33.272883 0 11 8 | B1->B0 | 3535 3737 | 0 0 | (0 0) (0 0)
1524 00:25:33.276178 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1525 00:25:33.283010 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1526 00:25:33.285934 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1527 00:25:33.289799 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1528 00:25:33.296320 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1529 00:25:33.299542 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1530 00:25:33.303319 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 00:25:33.309860 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1532 00:25:33.312578 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 00:25:33.316560 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 00:25:33.322933 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 00:25:33.326472 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 00:25:33.329514 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 00:25:33.335735 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 00:25:33.339029 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 00:25:33.342638 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 00:25:33.346336 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 00:25:33.352785 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 00:25:33.356319 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 00:25:33.359517 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 00:25:33.365683 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 00:25:33.369708 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 00:25:33.372884 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 00:25:33.379395 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 00:25:33.382791 Total UI for P1: 0, mck2ui 16
1549 00:25:33.386468 best dqsien dly found for B0: ( 0, 14, 6)
1550 00:25:33.386942 Total UI for P1: 0, mck2ui 16
1551 00:25:33.393023 best dqsien dly found for B1: ( 0, 14, 6)
1552 00:25:33.397223 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1553 00:25:33.399926 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1554 00:25:33.400397
1555 00:25:33.402743 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1556 00:25:33.405842 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1557 00:25:33.409158 [Gating] SW calibration Done
1558 00:25:33.409550 ==
1559 00:25:33.412714 Dram Type= 6, Freq= 0, CH_1, rank 0
1560 00:25:33.416249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1561 00:25:33.416722 ==
1562 00:25:33.419680 RX Vref Scan: 0
1563 00:25:33.420152
1564 00:25:33.420459 RX Vref 0 -> 0, step: 1
1565 00:25:33.421043
1566 00:25:33.422761 RX Delay -130 -> 252, step: 16
1567 00:25:33.426076 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1568 00:25:33.432914 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1569 00:25:33.435834 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1570 00:25:33.439599 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1571 00:25:33.442974 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1572 00:25:33.446313 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1573 00:25:33.449342 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1574 00:25:33.456008 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1575 00:25:33.459487 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1576 00:25:33.463047 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1577 00:25:33.466087 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1578 00:25:33.469787 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1579 00:25:33.476907 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1580 00:25:33.479470 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1581 00:25:33.483291 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1582 00:25:33.486093 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1583 00:25:33.486490 ==
1584 00:25:33.489607 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 00:25:33.496573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 00:25:33.496966 ==
1587 00:25:33.497275 DQS Delay:
1588 00:25:33.499792 DQS0 = 0, DQS1 = 0
1589 00:25:33.500275 DQM Delay:
1590 00:25:33.500587 DQM0 = 83, DQM1 = 72
1591 00:25:33.503195 DQ Delay:
1592 00:25:33.506571 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1593 00:25:33.509393 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1594 00:25:33.512695 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1595 00:25:33.516533 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =77
1596 00:25:33.516923
1597 00:25:33.517229
1598 00:25:33.517592 ==
1599 00:25:33.519377 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 00:25:33.522871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 00:25:33.523269 ==
1602 00:25:33.523578
1603 00:25:33.523855
1604 00:25:33.525963 TX Vref Scan disable
1605 00:25:33.526511 == TX Byte 0 ==
1606 00:25:33.532950 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1607 00:25:33.536388 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1608 00:25:33.536785 == TX Byte 1 ==
1609 00:25:33.542969 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1610 00:25:33.546008 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1611 00:25:33.546446 ==
1612 00:25:33.549360 Dram Type= 6, Freq= 0, CH_1, rank 0
1613 00:25:33.552428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1614 00:25:33.552975 ==
1615 00:25:33.566953 TX Vref=22, minBit 11, minWin=26, winSum=439
1616 00:25:33.570650 TX Vref=24, minBit 4, minWin=27, winSum=444
1617 00:25:33.573661 TX Vref=26, minBit 8, minWin=27, winSum=448
1618 00:25:33.577366 TX Vref=28, minBit 11, minWin=27, winSum=453
1619 00:25:33.580267 TX Vref=30, minBit 0, minWin=28, winSum=455
1620 00:25:33.583854 TX Vref=32, minBit 1, minWin=28, winSum=456
1621 00:25:33.590544 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 32
1622 00:25:33.590938
1623 00:25:33.593499 Final TX Range 1 Vref 32
1624 00:25:33.593891
1625 00:25:33.594229 ==
1626 00:25:33.597144 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 00:25:33.600158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 00:25:33.600551 ==
1629 00:25:33.600855
1630 00:25:33.604036
1631 00:25:33.604450 TX Vref Scan disable
1632 00:25:33.606848 == TX Byte 0 ==
1633 00:25:33.610724 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1634 00:25:33.613643 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1635 00:25:33.617184 == TX Byte 1 ==
1636 00:25:33.620659 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1637 00:25:33.623670 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1638 00:25:33.627736
1639 00:25:33.628338 [DATLAT]
1640 00:25:33.628690 Freq=800, CH1 RK0
1641 00:25:33.628979
1642 00:25:33.630221 DATLAT Default: 0xa
1643 00:25:33.630655 0, 0xFFFF, sum = 0
1644 00:25:33.633962 1, 0xFFFF, sum = 0
1645 00:25:33.634489 2, 0xFFFF, sum = 0
1646 00:25:33.637221 3, 0xFFFF, sum = 0
1647 00:25:33.637619 4, 0xFFFF, sum = 0
1648 00:25:33.640450 5, 0xFFFF, sum = 0
1649 00:25:33.643639 6, 0xFFFF, sum = 0
1650 00:25:33.644031 7, 0xFFFF, sum = 0
1651 00:25:33.646946 8, 0xFFFF, sum = 0
1652 00:25:33.647338 9, 0x0, sum = 1
1653 00:25:33.647644 10, 0x0, sum = 2
1654 00:25:33.650532 11, 0x0, sum = 3
1655 00:25:33.650921 12, 0x0, sum = 4
1656 00:25:33.653784 best_step = 10
1657 00:25:33.654234
1658 00:25:33.654537 ==
1659 00:25:33.657041 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 00:25:33.660237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1661 00:25:33.660642 ==
1662 00:25:33.663830 RX Vref Scan: 1
1663 00:25:33.664301
1664 00:25:33.664606 Set Vref Range= 32 -> 127
1665 00:25:33.666714
1666 00:25:33.667098 RX Vref 32 -> 127, step: 1
1667 00:25:33.667400
1668 00:25:33.669924 RX Delay -111 -> 252, step: 8
1669 00:25:33.670445
1670 00:25:33.673325 Set Vref, RX VrefLevel [Byte0]: 32
1671 00:25:33.677000 [Byte1]: 32
1672 00:25:33.677477
1673 00:25:33.680258 Set Vref, RX VrefLevel [Byte0]: 33
1674 00:25:33.683850 [Byte1]: 33
1675 00:25:33.687488
1676 00:25:33.687873 Set Vref, RX VrefLevel [Byte0]: 34
1677 00:25:33.691086 [Byte1]: 34
1678 00:25:33.695445
1679 00:25:33.695830 Set Vref, RX VrefLevel [Byte0]: 35
1680 00:25:33.698519 [Byte1]: 35
1681 00:25:33.702985
1682 00:25:33.703369 Set Vref, RX VrefLevel [Byte0]: 36
1683 00:25:33.706093 [Byte1]: 36
1684 00:25:33.710915
1685 00:25:33.711384 Set Vref, RX VrefLevel [Byte0]: 37
1686 00:25:33.713795 [Byte1]: 37
1687 00:25:33.718391
1688 00:25:33.718854 Set Vref, RX VrefLevel [Byte0]: 38
1689 00:25:33.722116 [Byte1]: 38
1690 00:25:33.725849
1691 00:25:33.726265 Set Vref, RX VrefLevel [Byte0]: 39
1692 00:25:33.729715 [Byte1]: 39
1693 00:25:33.733595
1694 00:25:33.734099 Set Vref, RX VrefLevel [Byte0]: 40
1695 00:25:33.736722 [Byte1]: 40
1696 00:25:33.740771
1697 00:25:33.741158 Set Vref, RX VrefLevel [Byte0]: 41
1698 00:25:33.744471 [Byte1]: 41
1699 00:25:33.748698
1700 00:25:33.749169 Set Vref, RX VrefLevel [Byte0]: 42
1701 00:25:33.751859 [Byte1]: 42
1702 00:25:33.755991
1703 00:25:33.756536 Set Vref, RX VrefLevel [Byte0]: 43
1704 00:25:33.759541 [Byte1]: 43
1705 00:25:33.764094
1706 00:25:33.764605 Set Vref, RX VrefLevel [Byte0]: 44
1707 00:25:33.767453 [Byte1]: 44
1708 00:25:33.771690
1709 00:25:33.772164 Set Vref, RX VrefLevel [Byte0]: 45
1710 00:25:33.774750 [Byte1]: 45
1711 00:25:33.779550
1712 00:25:33.779937 Set Vref, RX VrefLevel [Byte0]: 46
1713 00:25:33.782632 [Byte1]: 46
1714 00:25:33.787018
1715 00:25:33.787403 Set Vref, RX VrefLevel [Byte0]: 47
1716 00:25:33.790453 [Byte1]: 47
1717 00:25:33.794209
1718 00:25:33.794695 Set Vref, RX VrefLevel [Byte0]: 48
1719 00:25:33.798257 [Byte1]: 48
1720 00:25:33.802529
1721 00:25:33.802931 Set Vref, RX VrefLevel [Byte0]: 49
1722 00:25:33.805343 [Byte1]: 49
1723 00:25:33.810559
1724 00:25:33.811027 Set Vref, RX VrefLevel [Byte0]: 50
1725 00:25:33.813128 [Byte1]: 50
1726 00:25:33.817405
1727 00:25:33.817795 Set Vref, RX VrefLevel [Byte0]: 51
1728 00:25:33.821368 [Byte1]: 51
1729 00:25:33.825444
1730 00:25:33.825918 Set Vref, RX VrefLevel [Byte0]: 52
1731 00:25:33.828589 [Byte1]: 52
1732 00:25:33.833084
1733 00:25:33.833558 Set Vref, RX VrefLevel [Byte0]: 53
1734 00:25:33.836005 [Byte1]: 53
1735 00:25:33.840753
1736 00:25:33.841137 Set Vref, RX VrefLevel [Byte0]: 54
1737 00:25:33.843955 [Byte1]: 54
1738 00:25:33.848110
1739 00:25:33.848496 Set Vref, RX VrefLevel [Byte0]: 55
1740 00:25:33.852048 [Byte1]: 55
1741 00:25:33.856133
1742 00:25:33.856519 Set Vref, RX VrefLevel [Byte0]: 56
1743 00:25:33.859125 [Byte1]: 56
1744 00:25:33.863469
1745 00:25:33.863940 Set Vref, RX VrefLevel [Byte0]: 57
1746 00:25:33.866387 [Byte1]: 57
1747 00:25:33.871255
1748 00:25:33.871722 Set Vref, RX VrefLevel [Byte0]: 58
1749 00:25:33.874529 [Byte1]: 58
1750 00:25:33.879020
1751 00:25:33.879493 Set Vref, RX VrefLevel [Byte0]: 59
1752 00:25:33.882192 [Byte1]: 59
1753 00:25:33.886785
1754 00:25:33.887299 Set Vref, RX VrefLevel [Byte0]: 60
1755 00:25:33.891150 [Byte1]: 60
1756 00:25:33.894143
1757 00:25:33.894529 Set Vref, RX VrefLevel [Byte0]: 61
1758 00:25:33.897592 [Byte1]: 61
1759 00:25:33.902052
1760 00:25:33.902523 Set Vref, RX VrefLevel [Byte0]: 62
1761 00:25:33.905183 [Byte1]: 62
1762 00:25:33.909732
1763 00:25:33.910258 Set Vref, RX VrefLevel [Byte0]: 63
1764 00:25:33.912819 [Byte1]: 63
1765 00:25:33.917676
1766 00:25:33.918353 Set Vref, RX VrefLevel [Byte0]: 64
1767 00:25:33.920102 [Byte1]: 64
1768 00:25:33.924340
1769 00:25:33.924868 Set Vref, RX VrefLevel [Byte0]: 65
1770 00:25:33.927941 [Byte1]: 65
1771 00:25:33.932170
1772 00:25:33.932922 Set Vref, RX VrefLevel [Byte0]: 66
1773 00:25:33.935665 [Byte1]: 66
1774 00:25:33.939983
1775 00:25:33.940439 Set Vref, RX VrefLevel [Byte0]: 67
1776 00:25:33.942793 [Byte1]: 67
1777 00:25:33.947797
1778 00:25:33.948499 Set Vref, RX VrefLevel [Byte0]: 68
1779 00:25:33.950490 [Byte1]: 68
1780 00:25:33.954606
1781 00:25:33.954847 Set Vref, RX VrefLevel [Byte0]: 69
1782 00:25:33.958283 [Byte1]: 69
1783 00:25:33.962689
1784 00:25:33.962935 Set Vref, RX VrefLevel [Byte0]: 70
1785 00:25:33.965602 [Byte1]: 70
1786 00:25:33.970189
1787 00:25:33.970425 Set Vref, RX VrefLevel [Byte0]: 71
1788 00:25:33.973652 [Byte1]: 71
1789 00:25:33.977756
1790 00:25:33.978034 Set Vref, RX VrefLevel [Byte0]: 72
1791 00:25:33.981190 [Byte1]: 72
1792 00:25:33.985472
1793 00:25:33.985706 Set Vref, RX VrefLevel [Byte0]: 73
1794 00:25:33.988678 [Byte1]: 73
1795 00:25:33.993130
1796 00:25:33.993289 Set Vref, RX VrefLevel [Byte0]: 74
1797 00:25:33.996395 [Byte1]: 74
1798 00:25:34.000623
1799 00:25:34.000761 Set Vref, RX VrefLevel [Byte0]: 75
1800 00:25:34.004024 [Byte1]: 75
1801 00:25:34.008378
1802 00:25:34.008517 Set Vref, RX VrefLevel [Byte0]: 76
1803 00:25:34.011533 [Byte1]: 76
1804 00:25:34.015785
1805 00:25:34.015980 Set Vref, RX VrefLevel [Byte0]: 77
1806 00:25:34.019445 [Byte1]: 77
1807 00:25:34.023506
1808 00:25:34.023654 Set Vref, RX VrefLevel [Byte0]: 78
1809 00:25:34.026927 [Byte1]: 78
1810 00:25:34.031426
1811 00:25:34.031565 Set Vref, RX VrefLevel [Byte0]: 79
1812 00:25:34.034388 [Byte1]: 79
1813 00:25:34.038935
1814 00:25:34.039090 Final RX Vref Byte 0 = 63 to rank0
1815 00:25:34.042162 Final RX Vref Byte 1 = 61 to rank0
1816 00:25:34.045702 Final RX Vref Byte 0 = 63 to rank1
1817 00:25:34.048797 Final RX Vref Byte 1 = 61 to rank1==
1818 00:25:34.052357 Dram Type= 6, Freq= 0, CH_1, rank 0
1819 00:25:34.059104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1820 00:25:34.059246 ==
1821 00:25:34.059355 DQS Delay:
1822 00:25:34.059456 DQS0 = 0, DQS1 = 0
1823 00:25:34.062131 DQM Delay:
1824 00:25:34.062270 DQM0 = 83, DQM1 = 74
1825 00:25:34.065835 DQ Delay:
1826 00:25:34.068874 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =84
1827 00:25:34.069014 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1828 00:25:34.072595 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =72
1829 00:25:34.075427 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
1830 00:25:34.079027
1831 00:25:34.079166
1832 00:25:34.085695 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e02, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
1833 00:25:34.088783 CH1 RK0: MR19=606, MR18=2E02
1834 00:25:34.095592 CH1_RK0: MR19=0x606, MR18=0x2E02, DQSOSC=398, MR23=63, INC=93, DEC=62
1835 00:25:34.095732
1836 00:25:34.098811 ----->DramcWriteLeveling(PI) begin...
1837 00:25:34.099045 ==
1838 00:25:34.101999 Dram Type= 6, Freq= 0, CH_1, rank 1
1839 00:25:34.105248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1840 00:25:34.105388 ==
1841 00:25:34.108769 Write leveling (Byte 0): 28 => 28
1842 00:25:34.112075 Write leveling (Byte 1): 27 => 27
1843 00:25:34.115439 DramcWriteLeveling(PI) end<-----
1844 00:25:34.115578
1845 00:25:34.115687 ==
1846 00:25:34.118738 Dram Type= 6, Freq= 0, CH_1, rank 1
1847 00:25:34.122421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 00:25:34.122725 ==
1849 00:25:34.125357 [Gating] SW mode calibration
1850 00:25:34.131954 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1851 00:25:34.139024 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1852 00:25:34.142370 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1853 00:25:34.145621 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1854 00:25:34.152208 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 00:25:34.155334 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 00:25:34.159019 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 00:25:34.165817 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 00:25:34.169123 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 00:25:34.172740 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 00:25:34.179170 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 00:25:34.182492 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 00:25:34.185563 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 00:25:34.192379 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 00:25:34.195327 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 00:25:34.198875 0 7 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1866 00:25:34.205517 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 00:25:34.208951 0 7 28 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1868 00:25:34.211995 0 8 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1869 00:25:34.215342 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1870 00:25:34.222469 0 8 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1871 00:25:34.225840 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 00:25:34.228871 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 00:25:34.235858 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 00:25:34.238599 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 00:25:34.242377 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 00:25:34.248795 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 00:25:34.252884 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1878 00:25:34.255752 0 9 8 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
1879 00:25:34.262573 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1880 00:25:34.265884 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1881 00:25:34.268826 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1882 00:25:34.275795 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1883 00:25:34.278867 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1884 00:25:34.282372 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1885 00:25:34.289303 0 10 4 | B1->B0 | 2f2f 2b2b | 1 1 | (1 1) (1 0)
1886 00:25:34.292996 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1887 00:25:34.296031 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 00:25:34.302700 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 00:25:34.306009 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 00:25:34.309731 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 00:25:34.312674 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 00:25:34.319089 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 00:25:34.322747 0 11 4 | B1->B0 | 2828 3535 | 1 0 | (0 0) (0 0)
1894 00:25:34.326181 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1895 00:25:34.332462 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1896 00:25:34.336004 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1897 00:25:34.339201 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1898 00:25:34.346482 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1899 00:25:34.349741 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1900 00:25:34.353012 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1901 00:25:34.359743 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1902 00:25:34.362453 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1903 00:25:34.366269 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 00:25:34.373042 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 00:25:34.375752 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 00:25:34.379634 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 00:25:34.386190 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 00:25:34.389052 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 00:25:34.393105 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 00:25:34.396052 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 00:25:34.402990 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 00:25:34.406215 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 00:25:34.409709 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 00:25:34.416084 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 00:25:34.419644 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 00:25:34.423108 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1917 00:25:34.429431 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1918 00:25:34.429906 Total UI for P1: 0, mck2ui 16
1919 00:25:34.436156 best dqsien dly found for B0: ( 0, 14, 0)
1920 00:25:34.439754 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 00:25:34.443018 Total UI for P1: 0, mck2ui 16
1922 00:25:34.446091 best dqsien dly found for B1: ( 0, 14, 4)
1923 00:25:34.449497 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1924 00:25:34.453142 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1925 00:25:34.453611
1926 00:25:34.456120 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1927 00:25:34.459365 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1928 00:25:34.463332 [Gating] SW calibration Done
1929 00:25:34.463802 ==
1930 00:25:34.466140 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 00:25:34.469687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1932 00:25:34.470094 ==
1933 00:25:34.473014 RX Vref Scan: 0
1934 00:25:34.473481
1935 00:25:34.476060 RX Vref 0 -> 0, step: 1
1936 00:25:34.476525
1937 00:25:34.476828 RX Delay -130 -> 252, step: 16
1938 00:25:34.483048 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1939 00:25:34.486075 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1940 00:25:34.489857 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1941 00:25:34.492979 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1942 00:25:34.496645 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1943 00:25:34.502795 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1944 00:25:34.506365 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1945 00:25:34.509089 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1946 00:25:34.512827 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1947 00:25:34.516048 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1948 00:25:34.522513 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1949 00:25:34.525943 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1950 00:25:34.528967 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1951 00:25:34.532674 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1952 00:25:34.535906 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1953 00:25:34.543077 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1954 00:25:34.543547 ==
1955 00:25:34.545895 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 00:25:34.549207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 00:25:34.549605 ==
1958 00:25:34.549911 DQS Delay:
1959 00:25:34.552708 DQS0 = 0, DQS1 = 0
1960 00:25:34.553178 DQM Delay:
1961 00:25:34.556265 DQM0 = 80, DQM1 = 77
1962 00:25:34.556651 DQ Delay:
1963 00:25:34.559095 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1964 00:25:34.562609 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1965 00:25:34.565943 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1966 00:25:34.569062 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1967 00:25:34.569451
1968 00:25:34.569747
1969 00:25:34.570065 ==
1970 00:25:34.572617 Dram Type= 6, Freq= 0, CH_1, rank 1
1971 00:25:34.576414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1972 00:25:34.576885 ==
1973 00:25:34.579506
1974 00:25:34.579968
1975 00:25:34.580268 TX Vref Scan disable
1976 00:25:34.582791 == TX Byte 0 ==
1977 00:25:34.586277 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1978 00:25:34.589726 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1979 00:25:34.593013 == TX Byte 1 ==
1980 00:25:34.595642 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1981 00:25:34.599540 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1982 00:25:34.600008 ==
1983 00:25:34.602721 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 00:25:34.609304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 00:25:34.609779 ==
1986 00:25:34.621226 TX Vref=22, minBit 5, minWin=27, winSum=441
1987 00:25:34.624645 TX Vref=24, minBit 5, minWin=27, winSum=445
1988 00:25:34.627820 TX Vref=26, minBit 10, minWin=27, winSum=445
1989 00:25:34.631266 TX Vref=28, minBit 1, minWin=27, winSum=448
1990 00:25:34.634795 TX Vref=30, minBit 1, minWin=27, winSum=447
1991 00:25:34.637866 TX Vref=32, minBit 0, minWin=28, winSum=449
1992 00:25:34.644346 [TxChooseVref] Worse bit 0, Min win 28, Win sum 449, Final Vref 32
1993 00:25:34.644902
1994 00:25:34.647930 Final TX Range 1 Vref 32
1995 00:25:34.648507
1996 00:25:34.648814 ==
1997 00:25:34.651227 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 00:25:34.654204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 00:25:34.654540 ==
2000 00:25:34.654825
2001 00:25:34.655096
2002 00:25:34.658195 TX Vref Scan disable
2003 00:25:34.660884 == TX Byte 0 ==
2004 00:25:34.664782 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2005 00:25:34.667734 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2006 00:25:34.671304 == TX Byte 1 ==
2007 00:25:34.674650 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2008 00:25:34.677943 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2009 00:25:34.678358
2010 00:25:34.681329 [DATLAT]
2011 00:25:34.681792 Freq=800, CH1 RK1
2012 00:25:34.682177
2013 00:25:34.684376 DATLAT Default: 0xa
2014 00:25:34.684763 0, 0xFFFF, sum = 0
2015 00:25:34.687441 1, 0xFFFF, sum = 0
2016 00:25:34.687836 2, 0xFFFF, sum = 0
2017 00:25:34.691049 3, 0xFFFF, sum = 0
2018 00:25:34.691531 4, 0xFFFF, sum = 0
2019 00:25:34.694179 5, 0xFFFF, sum = 0
2020 00:25:34.694569 6, 0xFFFF, sum = 0
2021 00:25:34.698114 7, 0xFFFF, sum = 0
2022 00:25:34.701199 8, 0xFFFF, sum = 0
2023 00:25:34.701676 9, 0x0, sum = 1
2024 00:25:34.702022 10, 0x0, sum = 2
2025 00:25:34.704724 11, 0x0, sum = 3
2026 00:25:34.705199 12, 0x0, sum = 4
2027 00:25:34.707478 best_step = 10
2028 00:25:34.707863
2029 00:25:34.708161 ==
2030 00:25:34.711437 Dram Type= 6, Freq= 0, CH_1, rank 1
2031 00:25:34.714108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2032 00:25:34.714579 ==
2033 00:25:34.717815 RX Vref Scan: 0
2034 00:25:34.718333
2035 00:25:34.718746 RX Vref 0 -> 0, step: 1
2036 00:25:34.719037
2037 00:25:34.720762 RX Delay -95 -> 252, step: 8
2038 00:25:34.727690 iDelay=201, Bit 0, Center 84 (-31 ~ 200) 232
2039 00:25:34.730612 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2040 00:25:34.734369 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2041 00:25:34.737129 iDelay=201, Bit 3, Center 76 (-39 ~ 192) 232
2042 00:25:34.740574 iDelay=201, Bit 4, Center 76 (-39 ~ 192) 232
2043 00:25:34.747182 iDelay=201, Bit 5, Center 88 (-23 ~ 200) 224
2044 00:25:34.750826 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2045 00:25:34.754102 iDelay=201, Bit 7, Center 76 (-39 ~ 192) 232
2046 00:25:34.757525 iDelay=201, Bit 8, Center 68 (-47 ~ 184) 232
2047 00:25:34.760833 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2048 00:25:34.767587 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2049 00:25:34.770781 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2050 00:25:34.774038 iDelay=201, Bit 12, Center 84 (-31 ~ 200) 232
2051 00:25:34.777509 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2052 00:25:34.781027 iDelay=201, Bit 14, Center 84 (-31 ~ 200) 232
2053 00:25:34.787142 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2054 00:25:34.787529 ==
2055 00:25:34.790876 Dram Type= 6, Freq= 0, CH_1, rank 1
2056 00:25:34.794722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2057 00:25:34.795222 ==
2058 00:25:34.795811 DQS Delay:
2059 00:25:34.797281 DQS0 = 0, DQS1 = 0
2060 00:25:34.797901 DQM Delay:
2061 00:25:34.800853 DQM0 = 79, DQM1 = 76
2062 00:25:34.801264 DQ Delay:
2063 00:25:34.803960 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2064 00:25:34.807703 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2065 00:25:34.811216 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
2066 00:25:34.814164 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
2067 00:25:34.814549
2068 00:25:34.814851
2069 00:25:34.823966 [DQSOSCAuto] RK1, (LSB)MR18= 0x232d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2070 00:25:34.824491 CH1 RK1: MR19=606, MR18=232D
2071 00:25:34.830584 CH1_RK1: MR19=0x606, MR18=0x232D, DQSOSC=398, MR23=63, INC=93, DEC=62
2072 00:25:34.834168 [RxdqsGatingPostProcess] freq 800
2073 00:25:34.841057 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2074 00:25:34.843810 Pre-setting of DQS Precalculation
2075 00:25:34.847254 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2076 00:25:34.853978 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2077 00:25:34.860930 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2078 00:25:34.863873
2079 00:25:34.864260
2080 00:25:34.864558 [Calibration Summary] 1600 Mbps
2081 00:25:34.867252 CH 0, Rank 0
2082 00:25:34.867789 SW Impedance : PASS
2083 00:25:34.870534 DUTY Scan : NO K
2084 00:25:34.873825 ZQ Calibration : PASS
2085 00:25:34.874222 Jitter Meter : NO K
2086 00:25:34.877737 CBT Training : PASS
2087 00:25:34.880842 Write leveling : PASS
2088 00:25:34.881329 RX DQS gating : PASS
2089 00:25:34.884107 RX DQ/DQS(RDDQC) : PASS
2090 00:25:34.887324 TX DQ/DQS : PASS
2091 00:25:34.887714 RX DATLAT : PASS
2092 00:25:34.890654 RX DQ/DQS(Engine): PASS
2093 00:25:34.894349 TX OE : NO K
2094 00:25:34.894869 All Pass.
2095 00:25:34.895375
2096 00:25:34.895804 CH 0, Rank 1
2097 00:25:34.897116 SW Impedance : PASS
2098 00:25:34.900615 DUTY Scan : NO K
2099 00:25:34.901003 ZQ Calibration : PASS
2100 00:25:34.904189 Jitter Meter : NO K
2101 00:25:34.904579 CBT Training : PASS
2102 00:25:34.907565 Write leveling : PASS
2103 00:25:34.910841 RX DQS gating : PASS
2104 00:25:34.911311 RX DQ/DQS(RDDQC) : PASS
2105 00:25:34.914484 TX DQ/DQS : PASS
2106 00:25:34.917517 RX DATLAT : PASS
2107 00:25:34.918024 RX DQ/DQS(Engine): PASS
2108 00:25:34.921097 TX OE : NO K
2109 00:25:34.921568 All Pass.
2110 00:25:34.921874
2111 00:25:34.924167 CH 1, Rank 0
2112 00:25:34.924638 SW Impedance : PASS
2113 00:25:34.927820 DUTY Scan : NO K
2114 00:25:34.930848 ZQ Calibration : PASS
2115 00:25:34.931321 Jitter Meter : NO K
2116 00:25:34.934508 CBT Training : PASS
2117 00:25:34.937448 Write leveling : PASS
2118 00:25:34.937914 RX DQS gating : PASS
2119 00:25:34.940985 RX DQ/DQS(RDDQC) : PASS
2120 00:25:34.941374 TX DQ/DQS : PASS
2121 00:25:34.943818 RX DATLAT : PASS
2122 00:25:34.947383 RX DQ/DQS(Engine): PASS
2123 00:25:34.947774 TX OE : NO K
2124 00:25:34.950390 All Pass.
2125 00:25:34.950778
2126 00:25:34.951074 CH 1, Rank 1
2127 00:25:34.954345 SW Impedance : PASS
2128 00:25:34.954819 DUTY Scan : NO K
2129 00:25:34.957660 ZQ Calibration : PASS
2130 00:25:34.961004 Jitter Meter : NO K
2131 00:25:34.961477 CBT Training : PASS
2132 00:25:34.964698 Write leveling : PASS
2133 00:25:34.967465 RX DQS gating : PASS
2134 00:25:34.967938 RX DQ/DQS(RDDQC) : PASS
2135 00:25:34.970994 TX DQ/DQS : PASS
2136 00:25:34.974455 RX DATLAT : PASS
2137 00:25:34.974927 RX DQ/DQS(Engine): PASS
2138 00:25:34.977612 TX OE : NO K
2139 00:25:34.978167 All Pass.
2140 00:25:34.978641
2141 00:25:34.980900 DramC Write-DBI off
2142 00:25:34.983979 PER_BANK_REFRESH: Hybrid Mode
2143 00:25:34.984386 TX_TRACKING: ON
2144 00:25:34.988038 [GetDramInforAfterCalByMRR] Vendor 6.
2145 00:25:34.990702 [GetDramInforAfterCalByMRR] Revision 606.
2146 00:25:34.994390 [GetDramInforAfterCalByMRR] Revision 2 0.
2147 00:25:34.997404 MR0 0x3b3b
2148 00:25:34.997786 MR8 0x5151
2149 00:25:35.001188 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2150 00:25:35.001655
2151 00:25:35.001958 MR0 0x3b3b
2152 00:25:35.004220 MR8 0x5151
2153 00:25:35.007698 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2154 00:25:35.008088
2155 00:25:35.014822 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2156 00:25:35.017731 [FAST_K] Save calibration result to emmc
2157 00:25:35.023960 [FAST_K] Save calibration result to emmc
2158 00:25:35.024415 dram_init: config_dvfs: 1
2159 00:25:35.027570 dramc_set_vcore_voltage set vcore to 662500
2160 00:25:35.030815 Read voltage for 1200, 2
2161 00:25:35.031282 Vio18 = 0
2162 00:25:35.034539 Vcore = 662500
2163 00:25:35.035005 Vdram = 0
2164 00:25:35.035310 Vddq = 0
2165 00:25:35.037735 Vmddr = 0
2166 00:25:35.040977 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2167 00:25:35.047617 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2168 00:25:35.048006 MEM_TYPE=3, freq_sel=15
2169 00:25:35.050657 sv_algorithm_assistance_LP4_1600
2170 00:25:35.057747 ============ PULL DRAM RESETB DOWN ============
2171 00:25:35.061432 ========== PULL DRAM RESETB DOWN end =========
2172 00:25:35.064198 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2173 00:25:35.067683 ===================================
2174 00:25:35.071412 LPDDR4 DRAM CONFIGURATION
2175 00:25:35.074310 ===================================
2176 00:25:35.074695 EX_ROW_EN[0] = 0x0
2177 00:25:35.077562 EX_ROW_EN[1] = 0x0
2178 00:25:35.081271 LP4Y_EN = 0x0
2179 00:25:35.081738 WORK_FSP = 0x0
2180 00:25:35.084382 WL = 0x4
2181 00:25:35.084769 RL = 0x4
2182 00:25:35.087798 BL = 0x2
2183 00:25:35.088262 RPST = 0x0
2184 00:25:35.090667 RD_PRE = 0x0
2185 00:25:35.091104 WR_PRE = 0x1
2186 00:25:35.094433 WR_PST = 0x0
2187 00:25:35.094817 DBI_WR = 0x0
2188 00:25:35.097808 DBI_RD = 0x0
2189 00:25:35.098371 OTF = 0x1
2190 00:25:35.100868 ===================================
2191 00:25:35.104692 ===================================
2192 00:25:35.107652 ANA top config
2193 00:25:35.111010 ===================================
2194 00:25:35.111401 DLL_ASYNC_EN = 0
2195 00:25:35.114548 ALL_SLAVE_EN = 0
2196 00:25:35.117576 NEW_RANK_MODE = 1
2197 00:25:35.121622 DLL_IDLE_MODE = 1
2198 00:25:35.122123 LP45_APHY_COMB_EN = 1
2199 00:25:35.124034 TX_ODT_DIS = 1
2200 00:25:35.127981 NEW_8X_MODE = 1
2201 00:25:35.131243 ===================================
2202 00:25:35.134471 ===================================
2203 00:25:35.137479 data_rate = 2400
2204 00:25:35.140749 CKR = 1
2205 00:25:35.144385 DQ_P2S_RATIO = 8
2206 00:25:35.148112 ===================================
2207 00:25:35.148605 CA_P2S_RATIO = 8
2208 00:25:35.151131 DQ_CA_OPEN = 0
2209 00:25:35.154256 DQ_SEMI_OPEN = 0
2210 00:25:35.158177 CA_SEMI_OPEN = 0
2211 00:25:35.161218 CA_FULL_RATE = 0
2212 00:25:35.161686 DQ_CKDIV4_EN = 0
2213 00:25:35.164826 CA_CKDIV4_EN = 0
2214 00:25:35.167901 CA_PREDIV_EN = 0
2215 00:25:35.171153 PH8_DLY = 17
2216 00:25:35.174759 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2217 00:25:35.178083 DQ_AAMCK_DIV = 4
2218 00:25:35.178619 CA_AAMCK_DIV = 4
2219 00:25:35.181694 CA_ADMCK_DIV = 4
2220 00:25:35.184530 DQ_TRACK_CA_EN = 0
2221 00:25:35.188246 CA_PICK = 1200
2222 00:25:35.191010 CA_MCKIO = 1200
2223 00:25:35.194604 MCKIO_SEMI = 0
2224 00:25:35.197840 PLL_FREQ = 2366
2225 00:25:35.198335 DQ_UI_PI_RATIO = 32
2226 00:25:35.201601 CA_UI_PI_RATIO = 0
2227 00:25:35.204787 ===================================
2228 00:25:35.208162 ===================================
2229 00:25:35.211192 memory_type:LPDDR4
2230 00:25:35.214269 GP_NUM : 10
2231 00:25:35.214667 SRAM_EN : 1
2232 00:25:35.218202 MD32_EN : 0
2233 00:25:35.221366 ===================================
2234 00:25:35.221839 [ANA_INIT] >>>>>>>>>>>>>>
2235 00:25:35.224974 <<<<<< [CONFIGURE PHASE]: ANA_TX
2236 00:25:35.228133 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2237 00:25:35.231373 ===================================
2238 00:25:35.234361 data_rate = 2400,PCW = 0X5b00
2239 00:25:35.238310 ===================================
2240 00:25:35.241087 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2241 00:25:35.247692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2242 00:25:35.254437 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2243 00:25:35.257720 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2244 00:25:35.261323 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2245 00:25:35.264094 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2246 00:25:35.267940 [ANA_INIT] flow start
2247 00:25:35.268410 [ANA_INIT] PLL >>>>>>>>
2248 00:25:35.270899 [ANA_INIT] PLL <<<<<<<<
2249 00:25:35.274640 [ANA_INIT] MIDPI >>>>>>>>
2250 00:25:35.275106 [ANA_INIT] MIDPI <<<<<<<<
2251 00:25:35.277876 [ANA_INIT] DLL >>>>>>>>
2252 00:25:35.281392 [ANA_INIT] DLL <<<<<<<<
2253 00:25:35.281860 [ANA_INIT] flow end
2254 00:25:35.287316 ============ LP4 DIFF to SE enter ============
2255 00:25:35.290640 ============ LP4 DIFF to SE exit ============
2256 00:25:35.294668 [ANA_INIT] <<<<<<<<<<<<<
2257 00:25:35.297691 [Flow] Enable top DCM control >>>>>
2258 00:25:35.301145 [Flow] Enable top DCM control <<<<<
2259 00:25:35.301616 Enable DLL master slave shuffle
2260 00:25:35.307725 ==============================================================
2261 00:25:35.310670 Gating Mode config
2262 00:25:35.314653 ==============================================================
2263 00:25:35.317306 Config description:
2264 00:25:35.327634 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2265 00:25:35.334080 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2266 00:25:35.337857 SELPH_MODE 0: By rank 1: By Phase
2267 00:25:35.343996 ==============================================================
2268 00:25:35.347135 GAT_TRACK_EN = 1
2269 00:25:35.350621 RX_GATING_MODE = 2
2270 00:25:35.354217 RX_GATING_TRACK_MODE = 2
2271 00:25:35.354708 SELPH_MODE = 1
2272 00:25:35.357595 PICG_EARLY_EN = 1
2273 00:25:35.361219 VALID_LAT_VALUE = 1
2274 00:25:35.368197 ==============================================================
2275 00:25:35.370759 Enter into Gating configuration >>>>
2276 00:25:35.374876 Exit from Gating configuration <<<<
2277 00:25:35.377758 Enter into DVFS_PRE_config >>>>>
2278 00:25:35.388160 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2279 00:25:35.390779 Exit from DVFS_PRE_config <<<<<
2280 00:25:35.394140 Enter into PICG configuration >>>>
2281 00:25:35.397061 Exit from PICG configuration <<<<
2282 00:25:35.401093 [RX_INPUT] configuration >>>>>
2283 00:25:35.404129 [RX_INPUT] configuration <<<<<
2284 00:25:35.407563 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2285 00:25:35.413861 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2286 00:25:35.420538 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2287 00:25:35.427201 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2288 00:25:35.430607 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2289 00:25:35.437546 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2290 00:25:35.440672 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2291 00:25:35.447415 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2292 00:25:35.451110 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2293 00:25:35.454528 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2294 00:25:35.457769 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2295 00:25:35.464182 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2296 00:25:35.467516 ===================================
2297 00:25:35.467906 LPDDR4 DRAM CONFIGURATION
2298 00:25:35.471456 ===================================
2299 00:25:35.474757 EX_ROW_EN[0] = 0x0
2300 00:25:35.477557 EX_ROW_EN[1] = 0x0
2301 00:25:35.477939 LP4Y_EN = 0x0
2302 00:25:35.481619 WORK_FSP = 0x0
2303 00:25:35.482132 WL = 0x4
2304 00:25:35.484414 RL = 0x4
2305 00:25:35.484799 BL = 0x2
2306 00:25:35.487763 RPST = 0x0
2307 00:25:35.488234 RD_PRE = 0x0
2308 00:25:35.491204 WR_PRE = 0x1
2309 00:25:35.491675 WR_PST = 0x0
2310 00:25:35.494568 DBI_WR = 0x0
2311 00:25:35.494952 DBI_RD = 0x0
2312 00:25:35.497544 OTF = 0x1
2313 00:25:35.501208 ===================================
2314 00:25:35.504358 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2315 00:25:35.507849 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2316 00:25:35.511274 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2317 00:25:35.514506 ===================================
2318 00:25:35.517935 LPDDR4 DRAM CONFIGURATION
2319 00:25:35.521159 ===================================
2320 00:25:35.524763 EX_ROW_EN[0] = 0x10
2321 00:25:35.525230 EX_ROW_EN[1] = 0x0
2322 00:25:35.528397 LP4Y_EN = 0x0
2323 00:25:35.528863 WORK_FSP = 0x0
2324 00:25:35.531489 WL = 0x4
2325 00:25:35.531951 RL = 0x4
2326 00:25:35.534890 BL = 0x2
2327 00:25:35.535360 RPST = 0x0
2328 00:25:35.537853 RD_PRE = 0x0
2329 00:25:35.538366 WR_PRE = 0x1
2330 00:25:35.541327 WR_PST = 0x0
2331 00:25:35.543989 DBI_WR = 0x0
2332 00:25:35.544087 DBI_RD = 0x0
2333 00:25:35.547229 OTF = 0x1
2334 00:25:35.550449 ===================================
2335 00:25:35.554166 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2336 00:25:35.554242 ==
2337 00:25:35.556992 Dram Type= 6, Freq= 0, CH_0, rank 0
2338 00:25:35.564270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2339 00:25:35.564357 ==
2340 00:25:35.564424 [Duty_Offset_Calibration]
2341 00:25:35.567723 B0:2 B1:-1 CA:1
2342 00:25:35.567882
2343 00:25:35.570949 [DutyScan_Calibration_Flow] k_type=0
2344 00:25:35.580045
2345 00:25:35.580218 ==CLK 0==
2346 00:25:35.582729 Final CLK duty delay cell = -4
2347 00:25:35.586200 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2348 00:25:35.589198 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2349 00:25:35.593082 [-4] AVG Duty = 4953%(X100)
2350 00:25:35.593495
2351 00:25:35.596014 CH0 CLK Duty spec in!! Max-Min= 156%
2352 00:25:35.599924 [DutyScan_Calibration_Flow] ====Done====
2353 00:25:35.600390
2354 00:25:35.602820 [DutyScan_Calibration_Flow] k_type=1
2355 00:25:35.618397
2356 00:25:35.618868 ==DQS 0 ==
2357 00:25:35.621650 Final DQS duty delay cell = 0
2358 00:25:35.625457 [0] MAX Duty = 5124%(X100), DQS PI = 44
2359 00:25:35.628752 [0] MIN Duty = 4969%(X100), DQS PI = 14
2360 00:25:35.629217 [0] AVG Duty = 5046%(X100)
2361 00:25:35.632318
2362 00:25:35.632778 ==DQS 1 ==
2363 00:25:35.634929 Final DQS duty delay cell = -4
2364 00:25:35.638871 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2365 00:25:35.641702 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2366 00:25:35.645207 [-4] AVG Duty = 5062%(X100)
2367 00:25:35.645597
2368 00:25:35.649013 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2369 00:25:35.649523
2370 00:25:35.652215 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2371 00:25:35.654959 [DutyScan_Calibration_Flow] ====Done====
2372 00:25:35.655344
2373 00:25:35.658693 [DutyScan_Calibration_Flow] k_type=3
2374 00:25:35.675109
2375 00:25:35.675561 ==DQM 0 ==
2376 00:25:35.678811 Final DQM duty delay cell = 0
2377 00:25:35.681897 [0] MAX Duty = 4969%(X100), DQS PI = 30
2378 00:25:35.685390 [0] MIN Duty = 4907%(X100), DQS PI = 2
2379 00:25:35.685465 [0] AVG Duty = 4938%(X100)
2380 00:25:35.685524
2381 00:25:35.688250 ==DQM 1 ==
2382 00:25:35.691947 Final DQM duty delay cell = 0
2383 00:25:35.694798 [0] MAX Duty = 5156%(X100), DQS PI = 62
2384 00:25:35.697989 [0] MIN Duty = 4969%(X100), DQS PI = 58
2385 00:25:35.698064 [0] AVG Duty = 5062%(X100)
2386 00:25:35.701695
2387 00:25:35.704700 CH0 DQM 0 Duty spec in!! Max-Min= 62%
2388 00:25:35.704775
2389 00:25:35.708312 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2390 00:25:35.711413 [DutyScan_Calibration_Flow] ====Done====
2391 00:25:35.711489
2392 00:25:35.714453 [DutyScan_Calibration_Flow] k_type=2
2393 00:25:35.730587
2394 00:25:35.730662 ==DQ 0 ==
2395 00:25:35.733947 Final DQ duty delay cell = -4
2396 00:25:35.737048 [-4] MAX Duty = 5031%(X100), DQS PI = 38
2397 00:25:35.740085 [-4] MIN Duty = 4844%(X100), DQS PI = 18
2398 00:25:35.744055 [-4] AVG Duty = 4937%(X100)
2399 00:25:35.744410
2400 00:25:35.744748 ==DQ 1 ==
2401 00:25:35.747197 Final DQ duty delay cell = 0
2402 00:25:35.750711 [0] MAX Duty = 5031%(X100), DQS PI = 26
2403 00:25:35.754578 [0] MIN Duty = 4907%(X100), DQS PI = 46
2404 00:25:35.757712 [0] AVG Duty = 4969%(X100)
2405 00:25:35.758238
2406 00:25:35.760601 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2407 00:25:35.761064
2408 00:25:35.764328 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2409 00:25:35.767587 [DutyScan_Calibration_Flow] ====Done====
2410 00:25:35.767984 ==
2411 00:25:35.770369 Dram Type= 6, Freq= 0, CH_1, rank 0
2412 00:25:35.774235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2413 00:25:35.774747 ==
2414 00:25:35.777491 [Duty_Offset_Calibration]
2415 00:25:35.777874 B0:1 B1:1 CA:2
2416 00:25:35.778219
2417 00:25:35.780460 [DutyScan_Calibration_Flow] k_type=0
2418 00:25:35.791142
2419 00:25:35.791572 ==CLK 0==
2420 00:25:35.794380 Final CLK duty delay cell = 0
2421 00:25:35.798408 [0] MAX Duty = 5156%(X100), DQS PI = 24
2422 00:25:35.801788 [0] MIN Duty = 4938%(X100), DQS PI = 40
2423 00:25:35.802312 [0] AVG Duty = 5047%(X100)
2424 00:25:35.804938
2425 00:25:35.808120 CH1 CLK Duty spec in!! Max-Min= 218%
2426 00:25:35.811616 [DutyScan_Calibration_Flow] ====Done====
2427 00:25:35.812091
2428 00:25:35.814730 [DutyScan_Calibration_Flow] k_type=1
2429 00:25:35.830701
2430 00:25:35.831169 ==DQS 0 ==
2431 00:25:35.834125 Final DQS duty delay cell = 0
2432 00:25:35.837114 [0] MAX Duty = 5031%(X100), DQS PI = 18
2433 00:25:35.840593 [0] MIN Duty = 4844%(X100), DQS PI = 50
2434 00:25:35.844094 [0] AVG Duty = 4937%(X100)
2435 00:25:35.844481
2436 00:25:35.844797 ==DQS 1 ==
2437 00:25:35.847147 Final DQS duty delay cell = 0
2438 00:25:35.850751 [0] MAX Duty = 5062%(X100), DQS PI = 36
2439 00:25:35.853864 [0] MIN Duty = 4907%(X100), DQS PI = 16
2440 00:25:35.856878 [0] AVG Duty = 4984%(X100)
2441 00:25:35.857263
2442 00:25:35.861193 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2443 00:25:35.862035
2444 00:25:35.864413 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2445 00:25:35.867418 [DutyScan_Calibration_Flow] ====Done====
2446 00:25:35.868113
2447 00:25:35.870694 [DutyScan_Calibration_Flow] k_type=3
2448 00:25:35.887402
2449 00:25:35.887868 ==DQM 0 ==
2450 00:25:35.890819 Final DQM duty delay cell = 0
2451 00:25:35.893890 [0] MAX Duty = 5093%(X100), DQS PI = 16
2452 00:25:35.897425 [0] MIN Duty = 4875%(X100), DQS PI = 50
2453 00:25:35.897813 [0] AVG Duty = 4984%(X100)
2454 00:25:35.900444
2455 00:25:35.900825 ==DQM 1 ==
2456 00:25:35.904107 Final DQM duty delay cell = 0
2457 00:25:35.907129 [0] MAX Duty = 5125%(X100), DQS PI = 14
2458 00:25:35.910437 [0] MIN Duty = 4938%(X100), DQS PI = 24
2459 00:25:35.910821 [0] AVG Duty = 5031%(X100)
2460 00:25:35.913939
2461 00:25:35.917096 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2462 00:25:35.917592
2463 00:25:35.920667 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2464 00:25:35.923993 [DutyScan_Calibration_Flow] ====Done====
2465 00:25:35.924381
2466 00:25:35.927144 [DutyScan_Calibration_Flow] k_type=2
2467 00:25:35.943704
2468 00:25:35.944090 ==DQ 0 ==
2469 00:25:35.946655 Final DQ duty delay cell = 0
2470 00:25:35.950098 [0] MAX Duty = 5124%(X100), DQS PI = 18
2471 00:25:35.953731 [0] MIN Duty = 4907%(X100), DQS PI = 50
2472 00:25:35.954146 [0] AVG Duty = 5015%(X100)
2473 00:25:35.954453
2474 00:25:35.957432 ==DQ 1 ==
2475 00:25:35.960453 Final DQ duty delay cell = 0
2476 00:25:35.963606 [0] MAX Duty = 5093%(X100), DQS PI = 10
2477 00:25:35.967051 [0] MIN Duty = 5000%(X100), DQS PI = 50
2478 00:25:35.967435 [0] AVG Duty = 5046%(X100)
2479 00:25:35.967735
2480 00:25:35.970088 CH1 DQ 0 Duty spec in!! Max-Min= 217%
2481 00:25:35.973716
2482 00:25:35.974137 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2483 00:25:35.980639 [DutyScan_Calibration_Flow] ====Done====
2484 00:25:35.983341 nWR fixed to 30
2485 00:25:35.983731 [ModeRegInit_LP4] CH0 RK0
2486 00:25:35.987015 [ModeRegInit_LP4] CH0 RK1
2487 00:25:35.990447 [ModeRegInit_LP4] CH1 RK0
2488 00:25:35.990832 [ModeRegInit_LP4] CH1 RK1
2489 00:25:35.993898 match AC timing 7
2490 00:25:35.997057 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2491 00:25:36.000321 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2492 00:25:36.007061 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2493 00:25:36.010659 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2494 00:25:36.017149 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2495 00:25:36.017613 ==
2496 00:25:36.020513 Dram Type= 6, Freq= 0, CH_0, rank 0
2497 00:25:36.023646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2498 00:25:36.024037 ==
2499 00:25:36.030453 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2500 00:25:36.033506 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2501 00:25:36.043935 [CA 0] Center 40 (10~71) winsize 62
2502 00:25:36.047003 [CA 1] Center 39 (9~70) winsize 62
2503 00:25:36.050184 [CA 2] Center 36 (6~67) winsize 62
2504 00:25:36.053397 [CA 3] Center 36 (5~67) winsize 63
2505 00:25:36.057166 [CA 4] Center 35 (5~65) winsize 61
2506 00:25:36.060338 [CA 5] Center 35 (5~65) winsize 61
2507 00:25:36.060737
2508 00:25:36.063837 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2509 00:25:36.064223
2510 00:25:36.067652 [CATrainingPosCal] consider 1 rank data
2511 00:25:36.070530 u2DelayCellTimex100 = 270/100 ps
2512 00:25:36.074207 CA0 delay=40 (10~71),Diff = 5 PI (24 cell)
2513 00:25:36.077101 CA1 delay=39 (9~70),Diff = 4 PI (19 cell)
2514 00:25:36.083492 CA2 delay=36 (6~67),Diff = 1 PI (4 cell)
2515 00:25:36.087561 CA3 delay=36 (5~67),Diff = 1 PI (4 cell)
2516 00:25:36.090371 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
2517 00:25:36.094195 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
2518 00:25:36.094687
2519 00:25:36.097557 CA PerBit enable=1, Macro0, CA PI delay=35
2520 00:25:36.098080
2521 00:25:36.100750 [CBTSetCACLKResult] CA Dly = 35
2522 00:25:36.101229 CS Dly: 7 (0~38)
2523 00:25:36.101538 ==
2524 00:25:36.103797 Dram Type= 6, Freq= 0, CH_0, rank 1
2525 00:25:36.110562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 00:25:36.110952 ==
2527 00:25:36.113503 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2528 00:25:36.120237 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2529 00:25:36.129768 [CA 0] Center 39 (9~70) winsize 62
2530 00:25:36.132793 [CA 1] Center 39 (9~70) winsize 62
2531 00:25:36.136626 [CA 2] Center 36 (6~67) winsize 62
2532 00:25:36.140097 [CA 3] Center 35 (5~66) winsize 62
2533 00:25:36.142855 [CA 4] Center 34 (4~65) winsize 62
2534 00:25:36.146504 [CA 5] Center 34 (4~64) winsize 61
2535 00:25:36.147027
2536 00:25:36.149362 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2537 00:25:36.149786
2538 00:25:36.153007 [CATrainingPosCal] consider 2 rank data
2539 00:25:36.156354 u2DelayCellTimex100 = 270/100 ps
2540 00:25:36.160075 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2541 00:25:36.162875 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2542 00:25:36.169336 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2543 00:25:36.172841 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2544 00:25:36.176335 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2545 00:25:36.179584 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
2546 00:25:36.179984
2547 00:25:36.182602 CA PerBit enable=1, Macro0, CA PI delay=34
2548 00:25:36.182999
2549 00:25:36.186481 [CBTSetCACLKResult] CA Dly = 34
2550 00:25:36.186885 CS Dly: 8 (0~41)
2551 00:25:36.187279
2552 00:25:36.189326 ----->DramcWriteLeveling(PI) begin...
2553 00:25:36.192916 ==
2554 00:25:36.195972 Dram Type= 6, Freq= 0, CH_0, rank 0
2555 00:25:36.199480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2556 00:25:36.199881 ==
2557 00:25:36.202643 Write leveling (Byte 0): 33 => 33
2558 00:25:36.206266 Write leveling (Byte 1): 28 => 28
2559 00:25:36.209782 DramcWriteLeveling(PI) end<-----
2560 00:25:36.210222
2561 00:25:36.210616 ==
2562 00:25:36.213179 Dram Type= 6, Freq= 0, CH_0, rank 0
2563 00:25:36.216479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2564 00:25:36.216966 ==
2565 00:25:36.219732 [Gating] SW mode calibration
2566 00:25:36.226526 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2567 00:25:36.229862 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2568 00:25:36.236642 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2569 00:25:36.239881 0 15 4 | B1->B0 | 2424 3030 | 0 1 | (0 0) (0 0)
2570 00:25:36.243284 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2571 00:25:36.250035 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2572 00:25:36.252948 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2573 00:25:36.256414 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2574 00:25:36.263211 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2575 00:25:36.266424 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2576 00:25:36.269713 1 0 0 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
2577 00:25:36.276521 1 0 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
2578 00:25:36.279557 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2579 00:25:36.282823 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2580 00:25:36.289972 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2581 00:25:36.293006 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2582 00:25:36.296452 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2583 00:25:36.302897 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2584 00:25:36.306422 1 1 0 | B1->B0 | 2525 2a2a | 0 0 | (0 0) (0 0)
2585 00:25:36.309556 1 1 4 | B1->B0 | 3c3c 4545 | 0 1 | (0 0) (0 0)
2586 00:25:36.316043 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2587 00:25:36.319818 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2588 00:25:36.323051 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2589 00:25:36.329667 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2590 00:25:36.333473 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2591 00:25:36.336428 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 00:25:36.339304 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2593 00:25:36.346292 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 00:25:36.349696 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 00:25:36.353028 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 00:25:36.359933 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 00:25:36.362636 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 00:25:36.366515 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 00:25:36.372825 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 00:25:36.376315 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 00:25:36.379678 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 00:25:36.386341 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 00:25:36.389679 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 00:25:36.393243 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 00:25:36.399844 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 00:25:36.403348 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 00:25:36.406591 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 00:25:36.412745 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2609 00:25:36.416422 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2610 00:25:36.419864 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 00:25:36.422806 Total UI for P1: 0, mck2ui 16
2612 00:25:36.426755 best dqsien dly found for B0: ( 1, 4, 2)
2613 00:25:36.429913 Total UI for P1: 0, mck2ui 16
2614 00:25:36.433309 best dqsien dly found for B1: ( 1, 4, 2)
2615 00:25:36.436419 best DQS0 dly(MCK, UI, PI) = (1, 4, 2)
2616 00:25:36.439696 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2617 00:25:36.440168
2618 00:25:36.442501 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 2)
2619 00:25:36.446428 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2620 00:25:36.449684 [Gating] SW calibration Done
2621 00:25:36.450130 ==
2622 00:25:36.453021 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 00:25:36.456416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 00:25:36.459490 ==
2625 00:25:36.459884 RX Vref Scan: 0
2626 00:25:36.460184
2627 00:25:36.463277 RX Vref 0 -> 0, step: 1
2628 00:25:36.463741
2629 00:25:36.466522 RX Delay -40 -> 252, step: 8
2630 00:25:36.469540 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2631 00:25:36.472545 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2632 00:25:36.476460 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2633 00:25:36.479542 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2634 00:25:36.486304 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2635 00:25:36.489503 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2636 00:25:36.492999 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2637 00:25:36.496648 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2638 00:25:36.499599 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2639 00:25:36.503223 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2640 00:25:36.509935 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2641 00:25:36.512888 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2642 00:25:36.516308 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2643 00:25:36.519454 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2644 00:25:36.522836 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2645 00:25:36.529652 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2646 00:25:36.530198 ==
2647 00:25:36.533328 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 00:25:36.536351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 00:25:36.536889 ==
2650 00:25:36.537294 DQS Delay:
2651 00:25:36.539880 DQS0 = 0, DQS1 = 0
2652 00:25:36.540385 DQM Delay:
2653 00:25:36.543281 DQM0 = 115, DQM1 = 107
2654 00:25:36.543681 DQ Delay:
2655 00:25:36.546288 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2656 00:25:36.549877 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2657 00:25:36.553075 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2658 00:25:36.556464 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2659 00:25:36.556945
2660 00:25:36.557345
2661 00:25:36.559895 ==
2662 00:25:36.560294 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 00:25:36.566775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 00:25:36.567271 ==
2665 00:25:36.567675
2666 00:25:36.568044
2667 00:25:36.570054 TX Vref Scan disable
2668 00:25:36.570454 == TX Byte 0 ==
2669 00:25:36.572997 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2670 00:25:36.579633 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2671 00:25:36.580118 == TX Byte 1 ==
2672 00:25:36.583276 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2673 00:25:36.590352 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2674 00:25:36.590838 ==
2675 00:25:36.593218 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 00:25:36.596774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 00:25:36.597265 ==
2678 00:25:36.608997 TX Vref=22, minBit 1, minWin=24, winSum=414
2679 00:25:36.611835 TX Vref=24, minBit 1, minWin=24, winSum=422
2680 00:25:36.615854 TX Vref=26, minBit 7, minWin=25, winSum=429
2681 00:25:36.618931 TX Vref=28, minBit 0, minWin=26, winSum=432
2682 00:25:36.622510 TX Vref=30, minBit 0, minWin=26, winSum=434
2683 00:25:36.625409 TX Vref=32, minBit 1, minWin=26, winSum=436
2684 00:25:36.632219 [TxChooseVref] Worse bit 1, Min win 26, Win sum 436, Final Vref 32
2685 00:25:36.632711
2686 00:25:36.635598 Final TX Range 1 Vref 32
2687 00:25:36.636082
2688 00:25:36.636483 ==
2689 00:25:36.638787 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 00:25:36.642078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 00:25:36.642543 ==
2692 00:25:36.642938
2693 00:25:36.645386
2694 00:25:36.645864 TX Vref Scan disable
2695 00:25:36.648553 == TX Byte 0 ==
2696 00:25:36.652072 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2697 00:25:36.655394 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2698 00:25:36.658498 == TX Byte 1 ==
2699 00:25:36.661846 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2700 00:25:36.665625 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2701 00:25:36.666150
2702 00:25:36.668536 [DATLAT]
2703 00:25:36.669012 Freq=1200, CH0 RK0
2704 00:25:36.669412
2705 00:25:36.672053 DATLAT Default: 0xd
2706 00:25:36.672452 0, 0xFFFF, sum = 0
2707 00:25:36.674905 1, 0xFFFF, sum = 0
2708 00:25:36.675312 2, 0xFFFF, sum = 0
2709 00:25:36.678298 3, 0xFFFF, sum = 0
2710 00:25:36.678704 4, 0xFFFF, sum = 0
2711 00:25:36.681685 5, 0xFFFF, sum = 0
2712 00:25:36.682225 6, 0xFFFF, sum = 0
2713 00:25:36.685186 7, 0xFFFF, sum = 0
2714 00:25:36.689052 8, 0xFFFF, sum = 0
2715 00:25:36.689548 9, 0xFFFF, sum = 0
2716 00:25:36.691721 10, 0xFFFF, sum = 0
2717 00:25:36.692126 11, 0xFFFF, sum = 0
2718 00:25:36.695704 12, 0x0, sum = 1
2719 00:25:36.696197 13, 0x0, sum = 2
2720 00:25:36.698624 14, 0x0, sum = 3
2721 00:25:36.699120 15, 0x0, sum = 4
2722 00:25:36.699530 best_step = 13
2723 00:25:36.699901
2724 00:25:36.702366 ==
2725 00:25:36.705665 Dram Type= 6, Freq= 0, CH_0, rank 0
2726 00:25:36.708452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2727 00:25:36.708856 ==
2728 00:25:36.709254 RX Vref Scan: 1
2729 00:25:36.709627
2730 00:25:36.712041 Set Vref Range= 32 -> 127
2731 00:25:36.712441
2732 00:25:36.715320 RX Vref 32 -> 127, step: 1
2733 00:25:36.715809
2734 00:25:36.718882 RX Delay -21 -> 252, step: 4
2735 00:25:36.719373
2736 00:25:36.721973 Set Vref, RX VrefLevel [Byte0]: 32
2737 00:25:36.725609 [Byte1]: 32
2738 00:25:36.726145
2739 00:25:36.728710 Set Vref, RX VrefLevel [Byte0]: 33
2740 00:25:36.732478 [Byte1]: 33
2741 00:25:36.732966
2742 00:25:36.735627 Set Vref, RX VrefLevel [Byte0]: 34
2743 00:25:36.738727 [Byte1]: 34
2744 00:25:36.743181
2745 00:25:36.743668 Set Vref, RX VrefLevel [Byte0]: 35
2746 00:25:36.746081 [Byte1]: 35
2747 00:25:36.750817
2748 00:25:36.751329 Set Vref, RX VrefLevel [Byte0]: 36
2749 00:25:36.754317 [Byte1]: 36
2750 00:25:36.759197
2751 00:25:36.759692 Set Vref, RX VrefLevel [Byte0]: 37
2752 00:25:36.761744 [Byte1]: 37
2753 00:25:36.766539
2754 00:25:36.767110 Set Vref, RX VrefLevel [Byte0]: 38
2755 00:25:36.769674 [Byte1]: 38
2756 00:25:36.774348
2757 00:25:36.774746 Set Vref, RX VrefLevel [Byte0]: 39
2758 00:25:36.778308 [Byte1]: 39
2759 00:25:36.782471
2760 00:25:36.782871 Set Vref, RX VrefLevel [Byte0]: 40
2761 00:25:36.786029 [Byte1]: 40
2762 00:25:36.790669
2763 00:25:36.791137 Set Vref, RX VrefLevel [Byte0]: 41
2764 00:25:36.793433 [Byte1]: 41
2765 00:25:36.798409
2766 00:25:36.798795 Set Vref, RX VrefLevel [Byte0]: 42
2767 00:25:36.801758 [Byte1]: 42
2768 00:25:36.806542
2769 00:25:36.807010 Set Vref, RX VrefLevel [Byte0]: 43
2770 00:25:36.809371 [Byte1]: 43
2771 00:25:36.813967
2772 00:25:36.814385 Set Vref, RX VrefLevel [Byte0]: 44
2773 00:25:36.817545 [Byte1]: 44
2774 00:25:36.821760
2775 00:25:36.822191 Set Vref, RX VrefLevel [Byte0]: 45
2776 00:25:36.825878 [Byte1]: 45
2777 00:25:36.830392
2778 00:25:36.830966 Set Vref, RX VrefLevel [Byte0]: 46
2779 00:25:36.833739 [Byte1]: 46
2780 00:25:36.838571
2781 00:25:36.839047 Set Vref, RX VrefLevel [Byte0]: 47
2782 00:25:36.841288 [Byte1]: 47
2783 00:25:36.845794
2784 00:25:36.846331 Set Vref, RX VrefLevel [Byte0]: 48
2785 00:25:36.849349 [Byte1]: 48
2786 00:25:36.854013
2787 00:25:36.854408 Set Vref, RX VrefLevel [Byte0]: 49
2788 00:25:36.857104 [Byte1]: 49
2789 00:25:36.861472
2790 00:25:36.861887 Set Vref, RX VrefLevel [Byte0]: 50
2791 00:25:36.864881 [Byte1]: 50
2792 00:25:36.870029
2793 00:25:36.870416 Set Vref, RX VrefLevel [Byte0]: 51
2794 00:25:36.872904 [Byte1]: 51
2795 00:25:36.877738
2796 00:25:36.878175 Set Vref, RX VrefLevel [Byte0]: 52
2797 00:25:36.881110 [Byte1]: 52
2798 00:25:36.885538
2799 00:25:36.886044 Set Vref, RX VrefLevel [Byte0]: 53
2800 00:25:36.888973 [Byte1]: 53
2801 00:25:36.893824
2802 00:25:36.894456 Set Vref, RX VrefLevel [Byte0]: 54
2803 00:25:36.896764 [Byte1]: 54
2804 00:25:36.901371
2805 00:25:36.901838 Set Vref, RX VrefLevel [Byte0]: 55
2806 00:25:36.905004 [Byte1]: 55
2807 00:25:36.909383
2808 00:25:36.909848 Set Vref, RX VrefLevel [Byte0]: 56
2809 00:25:36.912914 [Byte1]: 56
2810 00:25:36.917268
2811 00:25:36.917738 Set Vref, RX VrefLevel [Byte0]: 57
2812 00:25:36.920459 [Byte1]: 57
2813 00:25:36.925738
2814 00:25:36.926250 Set Vref, RX VrefLevel [Byte0]: 58
2815 00:25:36.928813 [Byte1]: 58
2816 00:25:36.933092
2817 00:25:36.933560 Set Vref, RX VrefLevel [Byte0]: 59
2818 00:25:36.936819 [Byte1]: 59
2819 00:25:36.941189
2820 00:25:36.941659 Set Vref, RX VrefLevel [Byte0]: 60
2821 00:25:36.944772 [Byte1]: 60
2822 00:25:36.948931
2823 00:25:36.949403 Set Vref, RX VrefLevel [Byte0]: 61
2824 00:25:36.952128 [Byte1]: 61
2825 00:25:36.957474
2826 00:25:36.957942 Set Vref, RX VrefLevel [Byte0]: 62
2827 00:25:36.960020 [Byte1]: 62
2828 00:25:36.965283
2829 00:25:36.965752 Set Vref, RX VrefLevel [Byte0]: 63
2830 00:25:36.968041 [Byte1]: 63
2831 00:25:36.973108
2832 00:25:36.973576 Set Vref, RX VrefLevel [Byte0]: 64
2833 00:25:36.976046 [Byte1]: 64
2834 00:25:36.981026
2835 00:25:36.981494 Set Vref, RX VrefLevel [Byte0]: 65
2836 00:25:36.983692 [Byte1]: 65
2837 00:25:36.988410
2838 00:25:36.988870 Set Vref, RX VrefLevel [Byte0]: 66
2839 00:25:36.991450 [Byte1]: 66
2840 00:25:36.996551
2841 00:25:36.997055 Set Vref, RX VrefLevel [Byte0]: 67
2842 00:25:36.999434 [Byte1]: 67
2843 00:25:37.004854
2844 00:25:37.005331 Final RX Vref Byte 0 = 54 to rank0
2845 00:25:37.007903 Final RX Vref Byte 1 = 51 to rank0
2846 00:25:37.011410 Final RX Vref Byte 0 = 54 to rank1
2847 00:25:37.014829 Final RX Vref Byte 1 = 51 to rank1==
2848 00:25:37.017800 Dram Type= 6, Freq= 0, CH_0, rank 0
2849 00:25:37.024759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2850 00:25:37.025229 ==
2851 00:25:37.025533 DQS Delay:
2852 00:25:37.025812 DQS0 = 0, DQS1 = 0
2853 00:25:37.027798 DQM Delay:
2854 00:25:37.028197 DQM0 = 114, DQM1 = 106
2855 00:25:37.030820 DQ Delay:
2856 00:25:37.034341 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =112
2857 00:25:37.037876 DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122
2858 00:25:37.041419 DQ8 =94, DQ9 =90, DQ10 =108, DQ11 =96
2859 00:25:37.044499 DQ12 =114, DQ13 =112, DQ14 =120, DQ15 =114
2860 00:25:37.044969
2861 00:25:37.045273
2862 00:25:37.051134 [DQSOSCAuto] RK0, (LSB)MR18= 0xfded, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 411 ps
2863 00:25:37.054399 CH0 RK0: MR19=303, MR18=FDED
2864 00:25:37.060904 CH0_RK0: MR19=0x303, MR18=0xFDED, DQSOSC=411, MR23=63, INC=38, DEC=25
2865 00:25:37.061472
2866 00:25:37.064788 ----->DramcWriteLeveling(PI) begin...
2867 00:25:37.065265 ==
2868 00:25:37.067635 Dram Type= 6, Freq= 0, CH_0, rank 1
2869 00:25:37.070815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2870 00:25:37.071203 ==
2871 00:25:37.074364 Write leveling (Byte 0): 33 => 33
2872 00:25:37.077377 Write leveling (Byte 1): 30 => 30
2873 00:25:37.081302 DramcWriteLeveling(PI) end<-----
2874 00:25:37.081771
2875 00:25:37.082125 ==
2876 00:25:37.084232 Dram Type= 6, Freq= 0, CH_0, rank 1
2877 00:25:37.091176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2878 00:25:37.091652 ==
2879 00:25:37.091962 [Gating] SW mode calibration
2880 00:25:37.101378 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2881 00:25:37.104722 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2882 00:25:37.107940 0 15 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2883 00:25:37.114124 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2884 00:25:37.118083 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2885 00:25:37.121287 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2886 00:25:37.128159 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2887 00:25:37.131359 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2888 00:25:37.134730 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2889 00:25:37.141576 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
2890 00:25:37.144713 1 0 0 | B1->B0 | 2a2a 2323 | 1 0 | (1 1) (0 0)
2891 00:25:37.147917 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2892 00:25:37.154426 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 00:25:37.157935 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 00:25:37.161352 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 00:25:37.164648 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2896 00:25:37.171190 1 0 24 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
2897 00:25:37.174656 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2898 00:25:37.177906 1 1 0 | B1->B0 | 3535 4444 | 0 0 | (0 0) (0 0)
2899 00:25:37.184888 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2900 00:25:37.188102 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 00:25:37.191222 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 00:25:37.198126 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 00:25:37.201689 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 00:25:37.204909 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 00:25:37.211214 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2906 00:25:37.214426 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2907 00:25:37.218094 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 00:25:37.224736 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 00:25:37.228695 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 00:25:37.231340 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 00:25:37.235024 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 00:25:37.241765 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 00:25:37.245285 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 00:25:37.248330 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 00:25:37.254975 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 00:25:37.258028 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 00:25:37.261836 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 00:25:37.268196 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 00:25:37.271647 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 00:25:37.274669 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2921 00:25:37.281546 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2922 00:25:37.285151 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2923 00:25:37.288042 Total UI for P1: 0, mck2ui 16
2924 00:25:37.291707 best dqsien dly found for B0: ( 1, 3, 26)
2925 00:25:37.294702 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 00:25:37.298547 Total UI for P1: 0, mck2ui 16
2927 00:25:37.301435 best dqsien dly found for B1: ( 1, 4, 0)
2928 00:25:37.305092 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2929 00:25:37.308632 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2930 00:25:37.309107
2931 00:25:37.311514 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2932 00:25:37.318600 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2933 00:25:37.318990 [Gating] SW calibration Done
2934 00:25:37.319291 ==
2935 00:25:37.321721 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 00:25:37.328000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 00:25:37.328522 ==
2938 00:25:37.328822 RX Vref Scan: 0
2939 00:25:37.329276
2940 00:25:37.331192 RX Vref 0 -> 0, step: 1
2941 00:25:37.331546
2942 00:25:37.334771 RX Delay -40 -> 252, step: 8
2943 00:25:37.338759 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2944 00:25:37.341730 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2945 00:25:37.345068 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2946 00:25:37.351492 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2947 00:25:37.355117 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2948 00:25:37.358297 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2949 00:25:37.361719 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2950 00:25:37.364868 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2951 00:25:37.368157 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2952 00:25:37.374931 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2953 00:25:37.378350 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2954 00:25:37.381592 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2955 00:25:37.384730 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2956 00:25:37.388336 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2957 00:25:37.395410 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2958 00:25:37.398431 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2959 00:25:37.398816 ==
2960 00:25:37.401883 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 00:25:37.405462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 00:25:37.405933 ==
2963 00:25:37.408126 DQS Delay:
2964 00:25:37.408535 DQS0 = 0, DQS1 = 0
2965 00:25:37.408842 DQM Delay:
2966 00:25:37.411834 DQM0 = 116, DQM1 = 105
2967 00:25:37.412218 DQ Delay:
2968 00:25:37.414763 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2969 00:25:37.418699 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2970 00:25:37.422043 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2971 00:25:37.425005 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2972 00:25:37.425388
2973 00:25:37.428850
2974 00:25:37.429317 ==
2975 00:25:37.432341 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 00:25:37.435542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 00:25:37.436020 ==
2978 00:25:37.436322
2979 00:25:37.436599
2980 00:25:37.438508 TX Vref Scan disable
2981 00:25:37.438980 == TX Byte 0 ==
2982 00:25:37.442111 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2983 00:25:37.448621 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2984 00:25:37.449092 == TX Byte 1 ==
2985 00:25:37.454957 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2986 00:25:37.458941 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2987 00:25:37.459410 ==
2988 00:25:37.462017 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 00:25:37.465548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 00:25:37.466062 ==
2991 00:25:37.477536 TX Vref=22, minBit 1, minWin=25, winSum=419
2992 00:25:37.480688 TX Vref=24, minBit 1, minWin=26, winSum=429
2993 00:25:37.484599 TX Vref=26, minBit 2, minWin=26, winSum=429
2994 00:25:37.487862 TX Vref=28, minBit 3, minWin=26, winSum=434
2995 00:25:37.490694 TX Vref=30, minBit 3, minWin=26, winSum=434
2996 00:25:37.494385 TX Vref=32, minBit 3, minWin=26, winSum=436
2997 00:25:37.500999 [TxChooseVref] Worse bit 3, Min win 26, Win sum 436, Final Vref 32
2998 00:25:37.501471
2999 00:25:37.504611 Final TX Range 1 Vref 32
3000 00:25:37.505080
3001 00:25:37.505386 ==
3002 00:25:37.507592 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 00:25:37.510944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 00:25:37.511437 ==
3005 00:25:37.511745
3006 00:25:37.514418
3007 00:25:37.514904 TX Vref Scan disable
3008 00:25:37.517631 == TX Byte 0 ==
3009 00:25:37.521191 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3010 00:25:37.524499 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3011 00:25:37.527462 == TX Byte 1 ==
3012 00:25:37.530944 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3013 00:25:37.534657 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3014 00:25:37.535133
3015 00:25:37.537528 [DATLAT]
3016 00:25:37.538027 Freq=1200, CH0 RK1
3017 00:25:37.538343
3018 00:25:37.541258 DATLAT Default: 0xd
3019 00:25:37.541739 0, 0xFFFF, sum = 0
3020 00:25:37.544369 1, 0xFFFF, sum = 0
3021 00:25:37.544775 2, 0xFFFF, sum = 0
3022 00:25:37.547383 3, 0xFFFF, sum = 0
3023 00:25:37.547781 4, 0xFFFF, sum = 0
3024 00:25:37.550990 5, 0xFFFF, sum = 0
3025 00:25:37.551422 6, 0xFFFF, sum = 0
3026 00:25:37.554009 7, 0xFFFF, sum = 0
3027 00:25:37.554446 8, 0xFFFF, sum = 0
3028 00:25:37.557632 9, 0xFFFF, sum = 0
3029 00:25:37.560915 10, 0xFFFF, sum = 0
3030 00:25:37.561431 11, 0xFFFF, sum = 0
3031 00:25:37.564169 12, 0x0, sum = 1
3032 00:25:37.564576 13, 0x0, sum = 2
3033 00:25:37.564888 14, 0x0, sum = 3
3034 00:25:37.568102 15, 0x0, sum = 4
3035 00:25:37.568587 best_step = 13
3036 00:25:37.568892
3037 00:25:37.569171 ==
3038 00:25:37.570999 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 00:25:37.577744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 00:25:37.578269 ==
3041 00:25:37.578583 RX Vref Scan: 0
3042 00:25:37.578864
3043 00:25:37.581421 RX Vref 0 -> 0, step: 1
3044 00:25:37.581894
3045 00:25:37.584312 RX Delay -21 -> 252, step: 4
3046 00:25:37.587710 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3047 00:25:37.591421 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3048 00:25:37.597538 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3049 00:25:37.600717 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3050 00:25:37.604525 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3051 00:25:37.608072 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3052 00:25:37.610810 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3053 00:25:37.617588 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3054 00:25:37.621082 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3055 00:25:37.624608 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3056 00:25:37.627637 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3057 00:25:37.631212 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3058 00:25:37.634813 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3059 00:25:37.641756 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3060 00:25:37.644809 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3061 00:25:37.647886 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3062 00:25:37.648283 ==
3063 00:25:37.651448 Dram Type= 6, Freq= 0, CH_0, rank 1
3064 00:25:37.654368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3065 00:25:37.658043 ==
3066 00:25:37.658432 DQS Delay:
3067 00:25:37.658739 DQS0 = 0, DQS1 = 0
3068 00:25:37.661403 DQM Delay:
3069 00:25:37.661880 DQM0 = 114, DQM1 = 105
3070 00:25:37.664648 DQ Delay:
3071 00:25:37.667938 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3072 00:25:37.671317 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3073 00:25:37.674639 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3074 00:25:37.678103 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =114
3075 00:25:37.678586
3076 00:25:37.678893
3077 00:25:37.684705 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
3078 00:25:37.688421 CH0 RK1: MR19=403, MR18=3F4
3079 00:25:37.694972 CH0_RK1: MR19=0x403, MR18=0x3F4, DQSOSC=408, MR23=63, INC=39, DEC=26
3080 00:25:37.698107 [RxdqsGatingPostProcess] freq 1200
3081 00:25:37.701189 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3082 00:25:37.704632 best DQS0 dly(2T, 0.5T) = (0, 12)
3083 00:25:37.708241 best DQS1 dly(2T, 0.5T) = (0, 12)
3084 00:25:37.711309 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3085 00:25:37.714606 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3086 00:25:37.718580 best DQS0 dly(2T, 0.5T) = (0, 11)
3087 00:25:37.721405 best DQS1 dly(2T, 0.5T) = (0, 12)
3088 00:25:37.725199 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3089 00:25:37.728241 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3090 00:25:37.731555 Pre-setting of DQS Precalculation
3091 00:25:37.734566 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3092 00:25:37.734955 ==
3093 00:25:37.738293 Dram Type= 6, Freq= 0, CH_1, rank 0
3094 00:25:37.744732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3095 00:25:37.745211 ==
3096 00:25:37.747959 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3097 00:25:37.754748 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3098 00:25:37.762966 [CA 0] Center 38 (9~68) winsize 60
3099 00:25:37.766420 [CA 1] Center 38 (8~68) winsize 61
3100 00:25:37.769498 [CA 2] Center 35 (5~65) winsize 61
3101 00:25:37.773338 [CA 3] Center 34 (4~65) winsize 62
3102 00:25:37.776834 [CA 4] Center 34 (4~65) winsize 62
3103 00:25:37.780034 [CA 5] Center 33 (3~64) winsize 62
3104 00:25:37.780518
3105 00:25:37.782969 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3106 00:25:37.783360
3107 00:25:37.786696 [CATrainingPosCal] consider 1 rank data
3108 00:25:37.789958 u2DelayCellTimex100 = 270/100 ps
3109 00:25:37.793384 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3110 00:25:37.796765 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3111 00:25:37.800250 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3112 00:25:37.806853 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3113 00:25:37.810354 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3114 00:25:37.813760 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3115 00:25:37.814362
3116 00:25:37.816279 CA PerBit enable=1, Macro0, CA PI delay=33
3117 00:25:37.816677
3118 00:25:37.819919 [CBTSetCACLKResult] CA Dly = 33
3119 00:25:37.820315 CS Dly: 5 (0~36)
3120 00:25:37.820617 ==
3121 00:25:37.823689 Dram Type= 6, Freq= 0, CH_1, rank 1
3122 00:25:37.830599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3123 00:25:37.831080 ==
3124 00:25:37.833618 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3125 00:25:37.839911 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3126 00:25:37.848802 [CA 0] Center 38 (8~68) winsize 61
3127 00:25:37.852283 [CA 1] Center 38 (8~68) winsize 61
3128 00:25:37.855171 [CA 2] Center 35 (5~65) winsize 61
3129 00:25:37.858673 [CA 3] Center 34 (4~65) winsize 62
3130 00:25:37.861883 [CA 4] Center 34 (4~65) winsize 62
3131 00:25:37.865075 [CA 5] Center 34 (4~64) winsize 61
3132 00:25:37.865656
3133 00:25:37.868727 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3134 00:25:37.869117
3135 00:25:37.871901 [CATrainingPosCal] consider 2 rank data
3136 00:25:37.875430 u2DelayCellTimex100 = 270/100 ps
3137 00:25:37.878480 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3138 00:25:37.882270 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3139 00:25:37.889096 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3140 00:25:37.891935 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3141 00:25:37.895485 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3142 00:25:37.898478 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3143 00:25:37.898964
3144 00:25:37.901726 CA PerBit enable=1, Macro0, CA PI delay=34
3145 00:25:37.902166
3146 00:25:37.905813 [CBTSetCACLKResult] CA Dly = 34
3147 00:25:37.906346 CS Dly: 6 (0~39)
3148 00:25:37.906656
3149 00:25:37.908781 ----->DramcWriteLeveling(PI) begin...
3150 00:25:37.912152 ==
3151 00:25:37.912591 Dram Type= 6, Freq= 0, CH_1, rank 0
3152 00:25:37.918779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3153 00:25:37.919261 ==
3154 00:25:37.921917 Write leveling (Byte 0): 26 => 26
3155 00:25:37.925658 Write leveling (Byte 1): 29 => 29
3156 00:25:37.926269 DramcWriteLeveling(PI) end<-----
3157 00:25:37.928404
3158 00:25:37.928792 ==
3159 00:25:37.932233 Dram Type= 6, Freq= 0, CH_1, rank 0
3160 00:25:37.935466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3161 00:25:37.935866 ==
3162 00:25:37.938996 [Gating] SW mode calibration
3163 00:25:37.945763 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3164 00:25:37.948388 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3165 00:25:37.954961 0 15 0 | B1->B0 | 2626 2323 | 1 0 | (0 0) (0 0)
3166 00:25:37.958949 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3167 00:25:37.962116 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3168 00:25:37.968270 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 00:25:37.971432 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3170 00:25:37.974767 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3171 00:25:37.981804 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3172 00:25:37.985179 0 15 28 | B1->B0 | 3434 3434 | 0 0 | (0 1) (0 1)
3173 00:25:37.988612 1 0 0 | B1->B0 | 2424 2b2b | 1 1 | (1 0) (1 0)
3174 00:25:37.995376 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 00:25:37.998295 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 00:25:38.001803 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 00:25:38.008387 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3178 00:25:38.011327 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3179 00:25:38.014959 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 00:25:38.021262 1 0 28 | B1->B0 | 2b2b 2323 | 0 1 | (0 0) (0 0)
3181 00:25:38.024823 1 1 0 | B1->B0 | 4141 3939 | 0 0 | (0 0) (0 0)
3182 00:25:38.028159 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 00:25:38.034639 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 00:25:38.038364 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 00:25:38.041320 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 00:25:38.048034 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 00:25:38.051550 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 00:25:38.054755 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 00:25:38.061162 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3190 00:25:38.065035 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 00:25:38.067932 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 00:25:38.071556 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 00:25:38.078012 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 00:25:38.081273 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 00:25:38.084830 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 00:25:38.091091 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 00:25:38.094338 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 00:25:38.097979 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 00:25:38.104803 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 00:25:38.107837 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 00:25:38.111428 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 00:25:38.118182 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 00:25:38.121335 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 00:25:38.124659 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3205 00:25:38.131324 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3206 00:25:38.131447 Total UI for P1: 0, mck2ui 16
3207 00:25:38.137962 best dqsien dly found for B0: ( 1, 3, 28)
3208 00:25:38.141182 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 00:25:38.144937 Total UI for P1: 0, mck2ui 16
3210 00:25:38.148042 best dqsien dly found for B1: ( 1, 4, 0)
3211 00:25:38.151481 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3212 00:25:38.154826 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3213 00:25:38.155051
3214 00:25:38.158055 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3215 00:25:38.161607 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3216 00:25:38.164559 [Gating] SW calibration Done
3217 00:25:38.164788 ==
3218 00:25:38.168426 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 00:25:38.171805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 00:25:38.172304 ==
3221 00:25:38.175494 RX Vref Scan: 0
3222 00:25:38.175972
3223 00:25:38.176280 RX Vref 0 -> 0, step: 1
3224 00:25:38.178281
3225 00:25:38.178672 RX Delay -40 -> 252, step: 8
3226 00:25:38.185415 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3227 00:25:38.188899 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3228 00:25:38.191987 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3229 00:25:38.195363 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3230 00:25:38.198337 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3231 00:25:38.201709 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3232 00:25:38.208645 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3233 00:25:38.211908 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3234 00:25:38.214779 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3235 00:25:38.218538 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3236 00:25:38.221614 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3237 00:25:38.228792 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3238 00:25:38.231937 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3239 00:25:38.235125 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3240 00:25:38.238139 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3241 00:25:38.244818 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3242 00:25:38.245217 ==
3243 00:25:38.247978 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 00:25:38.251251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 00:25:38.251645 ==
3246 00:25:38.251947 DQS Delay:
3247 00:25:38.254934 DQS0 = 0, DQS1 = 0
3248 00:25:38.255322 DQM Delay:
3249 00:25:38.258353 DQM0 = 116, DQM1 = 108
3250 00:25:38.258742 DQ Delay:
3251 00:25:38.261535 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3252 00:25:38.265006 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3253 00:25:38.268120 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3254 00:25:38.271672 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3255 00:25:38.272268
3256 00:25:38.272726
3257 00:25:38.273188 ==
3258 00:25:38.274672 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 00:25:38.281786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 00:25:38.282311 ==
3261 00:25:38.282624
3262 00:25:38.282901
3263 00:25:38.283166 TX Vref Scan disable
3264 00:25:38.285037 == TX Byte 0 ==
3265 00:25:38.288016 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3266 00:25:38.294654 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3267 00:25:38.294930 == TX Byte 1 ==
3268 00:25:38.298146 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3269 00:25:38.301641 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3270 00:25:38.304637 ==
3271 00:25:38.308324 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 00:25:38.311246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 00:25:38.311368 ==
3274 00:25:38.322584 TX Vref=22, minBit 0, minWin=25, winSum=413
3275 00:25:38.325771 TX Vref=24, minBit 0, minWin=26, winSum=420
3276 00:25:38.328932 TX Vref=26, minBit 1, minWin=25, winSum=423
3277 00:25:38.332581 TX Vref=28, minBit 0, minWin=26, winSum=428
3278 00:25:38.336288 TX Vref=30, minBit 3, minWin=25, winSum=429
3279 00:25:38.339073 TX Vref=32, minBit 0, minWin=26, winSum=432
3280 00:25:38.345855 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 32
3281 00:25:38.345935
3282 00:25:38.348909 Final TX Range 1 Vref 32
3283 00:25:38.348985
3284 00:25:38.349043 ==
3285 00:25:38.352933 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 00:25:38.355958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 00:25:38.356041 ==
3288 00:25:38.356100
3289 00:25:38.356153
3290 00:25:38.358975 TX Vref Scan disable
3291 00:25:38.362336 == TX Byte 0 ==
3292 00:25:38.365751 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3293 00:25:38.369050 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3294 00:25:38.372744 == TX Byte 1 ==
3295 00:25:38.376130 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3296 00:25:38.379491 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3297 00:25:38.379566
3298 00:25:38.382232 [DATLAT]
3299 00:25:38.382307 Freq=1200, CH1 RK0
3300 00:25:38.382366
3301 00:25:38.385944 DATLAT Default: 0xd
3302 00:25:38.386059 0, 0xFFFF, sum = 0
3303 00:25:38.388997 1, 0xFFFF, sum = 0
3304 00:25:38.389072 2, 0xFFFF, sum = 0
3305 00:25:38.392631 3, 0xFFFF, sum = 0
3306 00:25:38.392707 4, 0xFFFF, sum = 0
3307 00:25:38.395703 5, 0xFFFF, sum = 0
3308 00:25:38.395779 6, 0xFFFF, sum = 0
3309 00:25:38.399334 7, 0xFFFF, sum = 0
3310 00:25:38.399411 8, 0xFFFF, sum = 0
3311 00:25:38.402299 9, 0xFFFF, sum = 0
3312 00:25:38.406079 10, 0xFFFF, sum = 0
3313 00:25:38.406164 11, 0xFFFF, sum = 0
3314 00:25:38.408945 12, 0x0, sum = 1
3315 00:25:38.409041 13, 0x0, sum = 2
3316 00:25:38.409101 14, 0x0, sum = 3
3317 00:25:38.412611 15, 0x0, sum = 4
3318 00:25:38.412739 best_step = 13
3319 00:25:38.412799
3320 00:25:38.415746 ==
3321 00:25:38.415885 Dram Type= 6, Freq= 0, CH_1, rank 0
3322 00:25:38.422465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3323 00:25:38.422590 ==
3324 00:25:38.422676 RX Vref Scan: 1
3325 00:25:38.422756
3326 00:25:38.425966 Set Vref Range= 32 -> 127
3327 00:25:38.426078
3328 00:25:38.429058 RX Vref 32 -> 127, step: 1
3329 00:25:38.429133
3330 00:25:38.432361 RX Delay -21 -> 252, step: 4
3331 00:25:38.432483
3332 00:25:38.435658 Set Vref, RX VrefLevel [Byte0]: 32
3333 00:25:38.439118 [Byte1]: 32
3334 00:25:38.439201
3335 00:25:38.442383 Set Vref, RX VrefLevel [Byte0]: 33
3336 00:25:38.445799 [Byte1]: 33
3337 00:25:38.445899
3338 00:25:38.448743 Set Vref, RX VrefLevel [Byte0]: 34
3339 00:25:38.452410 [Byte1]: 34
3340 00:25:38.456625
3341 00:25:38.456700 Set Vref, RX VrefLevel [Byte0]: 35
3342 00:25:38.459679 [Byte1]: 35
3343 00:25:38.464557
3344 00:25:38.464632 Set Vref, RX VrefLevel [Byte0]: 36
3345 00:25:38.468114 [Byte1]: 36
3346 00:25:38.472238
3347 00:25:38.472328 Set Vref, RX VrefLevel [Byte0]: 37
3348 00:25:38.475584 [Byte1]: 37
3349 00:25:38.480393
3350 00:25:38.480514 Set Vref, RX VrefLevel [Byte0]: 38
3351 00:25:38.483665 [Byte1]: 38
3352 00:25:38.488147
3353 00:25:38.488224 Set Vref, RX VrefLevel [Byte0]: 39
3354 00:25:38.491622 [Byte1]: 39
3355 00:25:38.495808
3356 00:25:38.495882 Set Vref, RX VrefLevel [Byte0]: 40
3357 00:25:38.499367 [Byte1]: 40
3358 00:25:38.503892
3359 00:25:38.503966 Set Vref, RX VrefLevel [Byte0]: 41
3360 00:25:38.507482 [Byte1]: 41
3361 00:25:38.511757
3362 00:25:38.511837 Set Vref, RX VrefLevel [Byte0]: 42
3363 00:25:38.515466 [Byte1]: 42
3364 00:25:38.520153
3365 00:25:38.520242 Set Vref, RX VrefLevel [Byte0]: 43
3366 00:25:38.523334 [Byte1]: 43
3367 00:25:38.528092
3368 00:25:38.528201 Set Vref, RX VrefLevel [Byte0]: 44
3369 00:25:38.531157 [Byte1]: 44
3370 00:25:38.535951
3371 00:25:38.536066 Set Vref, RX VrefLevel [Byte0]: 45
3372 00:25:38.557270 [Byte1]: 45
3373 00:25:38.557393
3374 00:25:38.557499 Set Vref, RX VrefLevel [Byte0]: 46
3375 00:25:38.557599 [Byte1]: 46
3376 00:25:38.557721
3377 00:25:38.557840 Set Vref, RX VrefLevel [Byte0]: 47
3378 00:25:38.557959 [Byte1]: 47
3379 00:25:38.559258
3380 00:25:38.559378 Set Vref, RX VrefLevel [Byte0]: 48
3381 00:25:38.562623 [Byte1]: 48
3382 00:25:38.567340
3383 00:25:38.567462 Set Vref, RX VrefLevel [Byte0]: 49
3384 00:25:38.570879 [Byte1]: 49
3385 00:25:38.575188
3386 00:25:38.575297 Set Vref, RX VrefLevel [Byte0]: 50
3387 00:25:38.578763 [Byte1]: 50
3388 00:25:38.583361
3389 00:25:38.583457 Set Vref, RX VrefLevel [Byte0]: 51
3390 00:25:38.586775 [Byte1]: 51
3391 00:25:38.591380
3392 00:25:38.591742 Set Vref, RX VrefLevel [Byte0]: 52
3393 00:25:38.594908 [Byte1]: 52
3394 00:25:38.599293
3395 00:25:38.599658 Set Vref, RX VrefLevel [Byte0]: 53
3396 00:25:38.602908 [Byte1]: 53
3397 00:25:38.607531
3398 00:25:38.607896 Set Vref, RX VrefLevel [Byte0]: 54
3399 00:25:38.610651 [Byte1]: 54
3400 00:25:38.615116
3401 00:25:38.615482 Set Vref, RX VrefLevel [Byte0]: 55
3402 00:25:38.619031 [Byte1]: 55
3403 00:25:38.623320
3404 00:25:38.623684 Set Vref, RX VrefLevel [Byte0]: 56
3405 00:25:38.626657 [Byte1]: 56
3406 00:25:38.630885
3407 00:25:38.631268 Set Vref, RX VrefLevel [Byte0]: 57
3408 00:25:38.635496 [Byte1]: 57
3409 00:25:38.638836
3410 00:25:38.639233 Set Vref, RX VrefLevel [Byte0]: 58
3411 00:25:38.642407 [Byte1]: 58
3412 00:25:38.647168
3413 00:25:38.647773 Set Vref, RX VrefLevel [Byte0]: 59
3414 00:25:38.649960 [Byte1]: 59
3415 00:25:38.655368
3416 00:25:38.655743 Set Vref, RX VrefLevel [Byte0]: 60
3417 00:25:38.658018 [Byte1]: 60
3418 00:25:38.662662
3419 00:25:38.663017 Set Vref, RX VrefLevel [Byte0]: 61
3420 00:25:38.666249 [Byte1]: 61
3421 00:25:38.670664
3422 00:25:38.671018 Set Vref, RX VrefLevel [Byte0]: 62
3423 00:25:38.674459 [Byte1]: 62
3424 00:25:38.678849
3425 00:25:38.679283 Set Vref, RX VrefLevel [Byte0]: 63
3426 00:25:38.682311 [Byte1]: 63
3427 00:25:38.686420
3428 00:25:38.686772 Set Vref, RX VrefLevel [Byte0]: 64
3429 00:25:38.690048 [Byte1]: 64
3430 00:25:38.694848
3431 00:25:38.695295 Set Vref, RX VrefLevel [Byte0]: 65
3432 00:25:38.697936 [Byte1]: 65
3433 00:25:38.702617
3434 00:25:38.703055 Set Vref, RX VrefLevel [Byte0]: 66
3435 00:25:38.705935 [Byte1]: 66
3436 00:25:38.710560
3437 00:25:38.710949 Set Vref, RX VrefLevel [Byte0]: 67
3438 00:25:38.713715 [Byte1]: 67
3439 00:25:38.718494
3440 00:25:38.718962 Set Vref, RX VrefLevel [Byte0]: 68
3441 00:25:38.721820 [Byte1]: 68
3442 00:25:38.726247
3443 00:25:38.726630 Set Vref, RX VrefLevel [Byte0]: 69
3444 00:25:38.730106 [Byte1]: 69
3445 00:25:38.734154
3446 00:25:38.734662 Final RX Vref Byte 0 = 61 to rank0
3447 00:25:38.737578 Final RX Vref Byte 1 = 53 to rank0
3448 00:25:38.740904 Final RX Vref Byte 0 = 61 to rank1
3449 00:25:38.744589 Final RX Vref Byte 1 = 53 to rank1==
3450 00:25:38.747455 Dram Type= 6, Freq= 0, CH_1, rank 0
3451 00:25:38.754555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3452 00:25:38.754946 ==
3453 00:25:38.755252 DQS Delay:
3454 00:25:38.755534 DQS0 = 0, DQS1 = 0
3455 00:25:38.757440 DQM Delay:
3456 00:25:38.757844 DQM0 = 116, DQM1 = 109
3457 00:25:38.760711 DQ Delay:
3458 00:25:38.764156 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =116
3459 00:25:38.767199 DQ4 =116, DQ5 =124, DQ6 =128, DQ7 =114
3460 00:25:38.770918 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =104
3461 00:25:38.774073 DQ12 =118, DQ13 =116, DQ14 =116, DQ15 =114
3462 00:25:38.774461
3463 00:25:38.774760
3464 00:25:38.780565 [DQSOSCAuto] RK0, (LSB)MR18= 0xe4, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
3465 00:25:38.784159 CH1 RK0: MR19=403, MR18=E4
3466 00:25:38.791066 CH1_RK0: MR19=0x403, MR18=0xE4, DQSOSC=410, MR23=63, INC=39, DEC=26
3467 00:25:38.791658
3468 00:25:38.793934 ----->DramcWriteLeveling(PI) begin...
3469 00:25:38.794372 ==
3470 00:25:38.797588 Dram Type= 6, Freq= 0, CH_1, rank 1
3471 00:25:38.800986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3472 00:25:38.801460 ==
3473 00:25:38.804848 Write leveling (Byte 0): 27 => 27
3474 00:25:38.807730 Write leveling (Byte 1): 27 => 27
3475 00:25:38.811400 DramcWriteLeveling(PI) end<-----
3476 00:25:38.811868
3477 00:25:38.812169 ==
3478 00:25:38.814179 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 00:25:38.818172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 00:25:38.818662 ==
3481 00:25:38.821123 [Gating] SW mode calibration
3482 00:25:38.827835 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3483 00:25:38.834388 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3484 00:25:38.837511 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3485 00:25:38.844236 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 00:25:38.847602 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 00:25:38.850833 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 00:25:38.858055 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 00:25:38.860644 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3490 00:25:38.864313 0 15 24 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (1 0)
3491 00:25:38.870906 0 15 28 | B1->B0 | 2626 2323 | 1 0 | (1 1) (0 0)
3492 00:25:38.874354 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 00:25:38.877738 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 00:25:38.881281 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 00:25:38.887900 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 00:25:38.890965 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 00:25:38.894440 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3498 00:25:38.901149 1 0 24 | B1->B0 | 2525 4444 | 0 0 | (0 0) (0 0)
3499 00:25:38.904540 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
3500 00:25:38.907858 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 00:25:38.914636 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 00:25:38.917525 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 00:25:38.921023 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 00:25:38.927671 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 00:25:38.931185 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 00:25:38.934390 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3507 00:25:38.940982 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3508 00:25:38.944295 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 00:25:38.947247 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 00:25:38.954043 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 00:25:38.957775 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 00:25:38.961142 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 00:25:38.967484 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 00:25:38.970907 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 00:25:38.974537 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 00:25:38.977600 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 00:25:38.984426 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 00:25:38.987744 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 00:25:38.991007 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 00:25:38.998049 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 00:25:39.001110 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3522 00:25:39.004647 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3523 00:25:39.010853 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3524 00:25:39.011309 Total UI for P1: 0, mck2ui 16
3525 00:25:39.017431 best dqsien dly found for B0: ( 1, 3, 22)
3526 00:25:39.020788 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 00:25:39.024338 Total UI for P1: 0, mck2ui 16
3528 00:25:39.027563 best dqsien dly found for B1: ( 1, 3, 28)
3529 00:25:39.030776 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3530 00:25:39.034577 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3531 00:25:39.035048
3532 00:25:39.037626 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3533 00:25:39.041406 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3534 00:25:39.044022 [Gating] SW calibration Done
3535 00:25:39.044422 ==
3536 00:25:39.047673 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 00:25:39.050696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 00:25:39.054293 ==
3539 00:25:39.054682 RX Vref Scan: 0
3540 00:25:39.054981
3541 00:25:39.057324 RX Vref 0 -> 0, step: 1
3542 00:25:39.057707
3543 00:25:39.058041 RX Delay -40 -> 252, step: 8
3544 00:25:39.063641 iDelay=192, Bit 0, Center 111 (40 ~ 183) 144
3545 00:25:39.067199 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3546 00:25:39.070196 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3547 00:25:39.073793 iDelay=192, Bit 3, Center 115 (48 ~ 183) 136
3548 00:25:39.077240 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3549 00:25:39.084035 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3550 00:25:39.087004 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3551 00:25:39.090526 iDelay=192, Bit 7, Center 111 (48 ~ 175) 128
3552 00:25:39.093331 iDelay=192, Bit 8, Center 99 (24 ~ 175) 152
3553 00:25:39.096663 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3554 00:25:39.103772 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3555 00:25:39.107253 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3556 00:25:39.110654 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3557 00:25:39.113635 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3558 00:25:39.117165 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3559 00:25:39.124060 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3560 00:25:39.124140 ==
3561 00:25:39.127560 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 00:25:39.130502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 00:25:39.130589 ==
3564 00:25:39.130656 DQS Delay:
3565 00:25:39.134432 DQS0 = 0, DQS1 = 0
3566 00:25:39.134589 DQM Delay:
3567 00:25:39.137492 DQM0 = 113, DQM1 = 110
3568 00:25:39.137620 DQ Delay:
3569 00:25:39.140904 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =115
3570 00:25:39.144142 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =111
3571 00:25:39.147451 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3572 00:25:39.150594 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3573 00:25:39.150762
3574 00:25:39.150868
3575 00:25:39.154309 ==
3576 00:25:39.154487 Dram Type= 6, Freq= 0, CH_1, rank 1
3577 00:25:39.161216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3578 00:25:39.161447 ==
3579 00:25:39.161582
3580 00:25:39.161702
3581 00:25:39.161838 TX Vref Scan disable
3582 00:25:39.164610 == TX Byte 0 ==
3583 00:25:39.167745 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3584 00:25:39.171382 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3585 00:25:39.174519 == TX Byte 1 ==
3586 00:25:39.178449 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3587 00:25:39.181644 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3588 00:25:39.184429 ==
3589 00:25:39.188708 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 00:25:39.191289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 00:25:39.191678 ==
3592 00:25:39.202720 TX Vref=22, minBit 1, minWin=25, winSum=419
3593 00:25:39.206452 TX Vref=24, minBit 3, minWin=25, winSum=421
3594 00:25:39.209553 TX Vref=26, minBit 0, minWin=26, winSum=428
3595 00:25:39.213200 TX Vref=28, minBit 2, minWin=26, winSum=432
3596 00:25:39.216342 TX Vref=30, minBit 3, minWin=26, winSum=431
3597 00:25:39.219270 TX Vref=32, minBit 2, minWin=26, winSum=429
3598 00:25:39.226442 [TxChooseVref] Worse bit 2, Min win 26, Win sum 432, Final Vref 28
3599 00:25:39.226916
3600 00:25:39.229173 Final TX Range 1 Vref 28
3601 00:25:39.229558
3602 00:25:39.229853 ==
3603 00:25:39.233357 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 00:25:39.235878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 00:25:39.236266 ==
3606 00:25:39.236565
3607 00:25:39.236838
3608 00:25:39.239929 TX Vref Scan disable
3609 00:25:39.242513 == TX Byte 0 ==
3610 00:25:39.245807 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3611 00:25:39.249214 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3612 00:25:39.252876 == TX Byte 1 ==
3613 00:25:39.255954 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3614 00:25:39.259584 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3615 00:25:39.259968
3616 00:25:39.262944 [DATLAT]
3617 00:25:39.263387 Freq=1200, CH1 RK1
3618 00:25:39.263704
3619 00:25:39.266343 DATLAT Default: 0xd
3620 00:25:39.266728 0, 0xFFFF, sum = 0
3621 00:25:39.269506 1, 0xFFFF, sum = 0
3622 00:25:39.269939 2, 0xFFFF, sum = 0
3623 00:25:39.273321 3, 0xFFFF, sum = 0
3624 00:25:39.273793 4, 0xFFFF, sum = 0
3625 00:25:39.276518 5, 0xFFFF, sum = 0
3626 00:25:39.276991 6, 0xFFFF, sum = 0
3627 00:25:39.279194 7, 0xFFFF, sum = 0
3628 00:25:39.279583 8, 0xFFFF, sum = 0
3629 00:25:39.282920 9, 0xFFFF, sum = 0
3630 00:25:39.283312 10, 0xFFFF, sum = 0
3631 00:25:39.285973 11, 0xFFFF, sum = 0
3632 00:25:39.286472 12, 0x0, sum = 1
3633 00:25:39.289818 13, 0x0, sum = 2
3634 00:25:39.290344 14, 0x0, sum = 3
3635 00:25:39.292530 15, 0x0, sum = 4
3636 00:25:39.292925 best_step = 13
3637 00:25:39.293228
3638 00:25:39.293504 ==
3639 00:25:39.296411 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 00:25:39.302897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 00:25:39.303297 ==
3642 00:25:39.303607 RX Vref Scan: 0
3643 00:25:39.303889
3644 00:25:39.306145 RX Vref 0 -> 0, step: 1
3645 00:25:39.306625
3646 00:25:39.309827 RX Delay -21 -> 252, step: 4
3647 00:25:39.313129 iDelay=187, Bit 0, Center 114 (47 ~ 182) 136
3648 00:25:39.316235 iDelay=187, Bit 1, Center 108 (43 ~ 174) 132
3649 00:25:39.322705 iDelay=187, Bit 2, Center 106 (43 ~ 170) 128
3650 00:25:39.325757 iDelay=187, Bit 3, Center 112 (47 ~ 178) 132
3651 00:25:39.329679 iDelay=187, Bit 4, Center 114 (51 ~ 178) 128
3652 00:25:39.333350 iDelay=187, Bit 5, Center 122 (59 ~ 186) 128
3653 00:25:39.335956 iDelay=187, Bit 6, Center 120 (55 ~ 186) 132
3654 00:25:39.342923 iDelay=187, Bit 7, Center 110 (47 ~ 174) 128
3655 00:25:39.346162 iDelay=187, Bit 8, Center 98 (31 ~ 166) 136
3656 00:25:39.349548 iDelay=187, Bit 9, Center 98 (35 ~ 162) 128
3657 00:25:39.352811 iDelay=187, Bit 10, Center 110 (43 ~ 178) 136
3658 00:25:39.355826 iDelay=187, Bit 11, Center 102 (35 ~ 170) 136
3659 00:25:39.362327 iDelay=187, Bit 12, Center 114 (51 ~ 178) 128
3660 00:25:39.366074 iDelay=187, Bit 13, Center 120 (55 ~ 186) 132
3661 00:25:39.369547 iDelay=187, Bit 14, Center 116 (51 ~ 182) 132
3662 00:25:39.372920 iDelay=187, Bit 15, Center 118 (51 ~ 186) 136
3663 00:25:39.373315 ==
3664 00:25:39.376270 Dram Type= 6, Freq= 0, CH_1, rank 1
3665 00:25:39.379529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3666 00:25:39.382691 ==
3667 00:25:39.383082 DQS Delay:
3668 00:25:39.383389 DQS0 = 0, DQS1 = 0
3669 00:25:39.385627 DQM Delay:
3670 00:25:39.386051 DQM0 = 113, DQM1 = 109
3671 00:25:39.389458 DQ Delay:
3672 00:25:39.392762 DQ0 =114, DQ1 =108, DQ2 =106, DQ3 =112
3673 00:25:39.396362 DQ4 =114, DQ5 =122, DQ6 =120, DQ7 =110
3674 00:25:39.399065 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3675 00:25:39.402580 DQ12 =114, DQ13 =120, DQ14 =116, DQ15 =118
3676 00:25:39.402975
3677 00:25:39.403278
3678 00:25:39.409386 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa01, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3679 00:25:39.412234 CH1 RK1: MR19=304, MR18=FA01
3680 00:25:39.419215 CH1_RK1: MR19=0x304, MR18=0xFA01, DQSOSC=409, MR23=63, INC=39, DEC=26
3681 00:25:39.422593 [RxdqsGatingPostProcess] freq 1200
3682 00:25:39.429617 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3683 00:25:39.432748 best DQS0 dly(2T, 0.5T) = (0, 11)
3684 00:25:39.433251 best DQS1 dly(2T, 0.5T) = (0, 12)
3685 00:25:39.436113 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3686 00:25:39.439507 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3687 00:25:39.442604 best DQS0 dly(2T, 0.5T) = (0, 11)
3688 00:25:39.446257 best DQS1 dly(2T, 0.5T) = (0, 11)
3689 00:25:39.449849 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3690 00:25:39.452659 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3691 00:25:39.455600 Pre-setting of DQS Precalculation
3692 00:25:39.462608 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3693 00:25:39.469620 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3694 00:25:39.476453 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3695 00:25:39.476960
3696 00:25:39.477272
3697 00:25:39.479064 [Calibration Summary] 2400 Mbps
3698 00:25:39.479456 CH 0, Rank 0
3699 00:25:39.482481 SW Impedance : PASS
3700 00:25:39.482952 DUTY Scan : NO K
3701 00:25:39.485970 ZQ Calibration : PASS
3702 00:25:39.489408 Jitter Meter : NO K
3703 00:25:39.489801 CBT Training : PASS
3704 00:25:39.492418 Write leveling : PASS
3705 00:25:39.496506 RX DQS gating : PASS
3706 00:25:39.496974 RX DQ/DQS(RDDQC) : PASS
3707 00:25:39.499197 TX DQ/DQS : PASS
3708 00:25:39.502906 RX DATLAT : PASS
3709 00:25:39.503302 RX DQ/DQS(Engine): PASS
3710 00:25:39.506110 TX OE : NO K
3711 00:25:39.506508 All Pass.
3712 00:25:39.506818
3713 00:25:39.509602 CH 0, Rank 1
3714 00:25:39.510018 SW Impedance : PASS
3715 00:25:39.512420 DUTY Scan : NO K
3716 00:25:39.515650 ZQ Calibration : PASS
3717 00:25:39.516045 Jitter Meter : NO K
3718 00:25:39.519611 CBT Training : PASS
3719 00:25:39.522928 Write leveling : PASS
3720 00:25:39.523398 RX DQS gating : PASS
3721 00:25:39.526191 RX DQ/DQS(RDDQC) : PASS
3722 00:25:39.526656 TX DQ/DQS : PASS
3723 00:25:39.529555 RX DATLAT : PASS
3724 00:25:39.533074 RX DQ/DQS(Engine): PASS
3725 00:25:39.533538 TX OE : NO K
3726 00:25:39.535875 All Pass.
3727 00:25:39.536266
3728 00:25:39.536566 CH 1, Rank 0
3729 00:25:39.539168 SW Impedance : PASS
3730 00:25:39.539640 DUTY Scan : NO K
3731 00:25:39.542741 ZQ Calibration : PASS
3732 00:25:39.545890 Jitter Meter : NO K
3733 00:25:39.546329 CBT Training : PASS
3734 00:25:39.549117 Write leveling : PASS
3735 00:25:39.552666 RX DQS gating : PASS
3736 00:25:39.553057 RX DQ/DQS(RDDQC) : PASS
3737 00:25:39.555819 TX DQ/DQS : PASS
3738 00:25:39.559629 RX DATLAT : PASS
3739 00:25:39.560124 RX DQ/DQS(Engine): PASS
3740 00:25:39.562573 TX OE : NO K
3741 00:25:39.563054 All Pass.
3742 00:25:39.563362
3743 00:25:39.566144 CH 1, Rank 1
3744 00:25:39.566542 SW Impedance : PASS
3745 00:25:39.569002 DUTY Scan : NO K
3746 00:25:39.572602 ZQ Calibration : PASS
3747 00:25:39.572994 Jitter Meter : NO K
3748 00:25:39.576123 CBT Training : PASS
3749 00:25:39.576596 Write leveling : PASS
3750 00:25:39.579492 RX DQS gating : PASS
3751 00:25:39.582509 RX DQ/DQS(RDDQC) : PASS
3752 00:25:39.583024 TX DQ/DQS : PASS
3753 00:25:39.585973 RX DATLAT : PASS
3754 00:25:39.589538 RX DQ/DQS(Engine): PASS
3755 00:25:39.590052 TX OE : NO K
3756 00:25:39.592837 All Pass.
3757 00:25:39.593229
3758 00:25:39.593532 DramC Write-DBI off
3759 00:25:39.595877 PER_BANK_REFRESH: Hybrid Mode
3760 00:25:39.596269 TX_TRACKING: ON
3761 00:25:39.606041 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3762 00:25:39.609895 [FAST_K] Save calibration result to emmc
3763 00:25:39.612648 dramc_set_vcore_voltage set vcore to 650000
3764 00:25:39.616151 Read voltage for 600, 5
3765 00:25:39.616542 Vio18 = 0
3766 00:25:39.619679 Vcore = 650000
3767 00:25:39.620145 Vdram = 0
3768 00:25:39.620462 Vddq = 0
3769 00:25:39.621056 Vmddr = 0
3770 00:25:39.625953 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3771 00:25:39.632506 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3772 00:25:39.632971 MEM_TYPE=3, freq_sel=19
3773 00:25:39.635917 sv_algorithm_assistance_LP4_1600
3774 00:25:39.639190 ============ PULL DRAM RESETB DOWN ============
3775 00:25:39.645765 ========== PULL DRAM RESETB DOWN end =========
3776 00:25:39.649470 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3777 00:25:39.652575 ===================================
3778 00:25:39.656390 LPDDR4 DRAM CONFIGURATION
3779 00:25:39.659572 ===================================
3780 00:25:39.659967 EX_ROW_EN[0] = 0x0
3781 00:25:39.662769 EX_ROW_EN[1] = 0x0
3782 00:25:39.663160 LP4Y_EN = 0x0
3783 00:25:39.666046 WORK_FSP = 0x0
3784 00:25:39.666442 WL = 0x2
3785 00:25:39.669742 RL = 0x2
3786 00:25:39.670178 BL = 0x2
3787 00:25:39.672926 RPST = 0x0
3788 00:25:39.673364 RD_PRE = 0x0
3789 00:25:39.676341 WR_PRE = 0x1
3790 00:25:39.679444 WR_PST = 0x0
3791 00:25:39.679837 DBI_WR = 0x0
3792 00:25:39.682995 DBI_RD = 0x0
3793 00:25:39.683430 OTF = 0x1
3794 00:25:39.686033 ===================================
3795 00:25:39.689755 ===================================
3796 00:25:39.690199 ANA top config
3797 00:25:39.692686 ===================================
3798 00:25:39.696406 DLL_ASYNC_EN = 0
3799 00:25:39.699413 ALL_SLAVE_EN = 1
3800 00:25:39.702978 NEW_RANK_MODE = 1
3801 00:25:39.705866 DLL_IDLE_MODE = 1
3802 00:25:39.706296 LP45_APHY_COMB_EN = 1
3803 00:25:39.709070 TX_ODT_DIS = 1
3804 00:25:39.712402 NEW_8X_MODE = 1
3805 00:25:39.715981 ===================================
3806 00:25:39.719102 ===================================
3807 00:25:39.722420 data_rate = 1200
3808 00:25:39.725953 CKR = 1
3809 00:25:39.726091 DQ_P2S_RATIO = 8
3810 00:25:39.729013 ===================================
3811 00:25:39.732315 CA_P2S_RATIO = 8
3812 00:25:39.735651 DQ_CA_OPEN = 0
3813 00:25:39.739207 DQ_SEMI_OPEN = 0
3814 00:25:39.742193 CA_SEMI_OPEN = 0
3815 00:25:39.745562 CA_FULL_RATE = 0
3816 00:25:39.745647 DQ_CKDIV4_EN = 1
3817 00:25:39.749286 CA_CKDIV4_EN = 1
3818 00:25:39.752773 CA_PREDIV_EN = 0
3819 00:25:39.755649 PH8_DLY = 0
3820 00:25:39.758816 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3821 00:25:39.758910 DQ_AAMCK_DIV = 4
3822 00:25:39.762511 CA_AAMCK_DIV = 4
3823 00:25:39.766472 CA_ADMCK_DIV = 4
3824 00:25:39.769622 DQ_TRACK_CA_EN = 0
3825 00:25:39.772932 CA_PICK = 600
3826 00:25:39.776345 CA_MCKIO = 600
3827 00:25:39.776955 MCKIO_SEMI = 0
3828 00:25:39.779390 PLL_FREQ = 2288
3829 00:25:39.783316 DQ_UI_PI_RATIO = 32
3830 00:25:39.786291 CA_UI_PI_RATIO = 0
3831 00:25:39.790079 ===================================
3832 00:25:39.793272 ===================================
3833 00:25:39.796148 memory_type:LPDDR4
3834 00:25:39.796537 GP_NUM : 10
3835 00:25:39.799739 SRAM_EN : 1
3836 00:25:39.802850 MD32_EN : 0
3837 00:25:39.806772 ===================================
3838 00:25:39.807465 [ANA_INIT] >>>>>>>>>>>>>>
3839 00:25:39.809367 <<<<<< [CONFIGURE PHASE]: ANA_TX
3840 00:25:39.813308 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3841 00:25:39.816149 ===================================
3842 00:25:39.819606 data_rate = 1200,PCW = 0X5800
3843 00:25:39.822845 ===================================
3844 00:25:39.826263 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3845 00:25:39.832429 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3846 00:25:39.836016 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3847 00:25:39.842587 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3848 00:25:39.845949 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3849 00:25:39.849024 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3850 00:25:39.849411 [ANA_INIT] flow start
3851 00:25:39.852778 [ANA_INIT] PLL >>>>>>>>
3852 00:25:39.855997 [ANA_INIT] PLL <<<<<<<<
3853 00:25:39.859433 [ANA_INIT] MIDPI >>>>>>>>
3854 00:25:39.859827 [ANA_INIT] MIDPI <<<<<<<<
3855 00:25:39.862536 [ANA_INIT] DLL >>>>>>>>
3856 00:25:39.866202 [ANA_INIT] flow end
3857 00:25:39.869436 ============ LP4 DIFF to SE enter ============
3858 00:25:39.872676 ============ LP4 DIFF to SE exit ============
3859 00:25:39.876045 [ANA_INIT] <<<<<<<<<<<<<
3860 00:25:39.879453 [Flow] Enable top DCM control >>>>>
3861 00:25:39.882788 [Flow] Enable top DCM control <<<<<
3862 00:25:39.885957 Enable DLL master slave shuffle
3863 00:25:39.889076 ==============================================================
3864 00:25:39.892722 Gating Mode config
3865 00:25:39.895777 ==============================================================
3866 00:25:39.899390 Config description:
3867 00:25:39.909522 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3868 00:25:39.915879 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3869 00:25:39.919053 SELPH_MODE 0: By rank 1: By Phase
3870 00:25:39.926241 ==============================================================
3871 00:25:39.929474 GAT_TRACK_EN = 1
3872 00:25:39.932682 RX_GATING_MODE = 2
3873 00:25:39.935926 RX_GATING_TRACK_MODE = 2
3874 00:25:39.939563 SELPH_MODE = 1
3875 00:25:39.942591 PICG_EARLY_EN = 1
3876 00:25:39.943014 VALID_LAT_VALUE = 1
3877 00:25:39.949453 ==============================================================
3878 00:25:39.952914 Enter into Gating configuration >>>>
3879 00:25:39.956339 Exit from Gating configuration <<<<
3880 00:25:39.959367 Enter into DVFS_PRE_config >>>>>
3881 00:25:39.969739 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3882 00:25:39.972571 Exit from DVFS_PRE_config <<<<<
3883 00:25:39.975960 Enter into PICG configuration >>>>
3884 00:25:39.979281 Exit from PICG configuration <<<<
3885 00:25:39.982430 [RX_INPUT] configuration >>>>>
3886 00:25:39.986175 [RX_INPUT] configuration <<<<<
3887 00:25:39.989665 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3888 00:25:39.995742 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3889 00:25:40.002514 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3890 00:25:40.009318 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3891 00:25:40.015905 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3892 00:25:40.019597 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3893 00:25:40.026171 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3894 00:25:40.029896 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3895 00:25:40.033410 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3896 00:25:40.036383 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3897 00:25:40.039917 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3898 00:25:40.046338 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3899 00:25:40.049630 ===================================
3900 00:25:40.050140 LPDDR4 DRAM CONFIGURATION
3901 00:25:40.052951 ===================================
3902 00:25:40.056290 EX_ROW_EN[0] = 0x0
3903 00:25:40.059228 EX_ROW_EN[1] = 0x0
3904 00:25:40.059615 LP4Y_EN = 0x0
3905 00:25:40.062712 WORK_FSP = 0x0
3906 00:25:40.063138 WL = 0x2
3907 00:25:40.066209 RL = 0x2
3908 00:25:40.066679 BL = 0x2
3909 00:25:40.069834 RPST = 0x0
3910 00:25:40.070355 RD_PRE = 0x0
3911 00:25:40.072600 WR_PRE = 0x1
3912 00:25:40.072984 WR_PST = 0x0
3913 00:25:40.076002 DBI_WR = 0x0
3914 00:25:40.076385 DBI_RD = 0x0
3915 00:25:40.079724 OTF = 0x1
3916 00:25:40.082683 ===================================
3917 00:25:40.086249 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3918 00:25:40.089887 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3919 00:25:40.096183 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3920 00:25:40.099442 ===================================
3921 00:25:40.099828 LPDDR4 DRAM CONFIGURATION
3922 00:25:40.102754 ===================================
3923 00:25:40.106104 EX_ROW_EN[0] = 0x10
3924 00:25:40.106527 EX_ROW_EN[1] = 0x0
3925 00:25:40.109504 LP4Y_EN = 0x0
3926 00:25:40.113334 WORK_FSP = 0x0
3927 00:25:40.113800 WL = 0x2
3928 00:25:40.116082 RL = 0x2
3929 00:25:40.116478 BL = 0x2
3930 00:25:40.119795 RPST = 0x0
3931 00:25:40.120263 RD_PRE = 0x0
3932 00:25:40.122933 WR_PRE = 0x1
3933 00:25:40.123400 WR_PST = 0x0
3934 00:25:40.126448 DBI_WR = 0x0
3935 00:25:40.126834 DBI_RD = 0x0
3936 00:25:40.129847 OTF = 0x1
3937 00:25:40.132422 ===================================
3938 00:25:40.139616 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3939 00:25:40.142571 nWR fixed to 30
3940 00:25:40.142979 [ModeRegInit_LP4] CH0 RK0
3941 00:25:40.146236 [ModeRegInit_LP4] CH0 RK1
3942 00:25:40.149685 [ModeRegInit_LP4] CH1 RK0
3943 00:25:40.150198 [ModeRegInit_LP4] CH1 RK1
3944 00:25:40.152541 match AC timing 17
3945 00:25:40.156485 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3946 00:25:40.159182 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3947 00:25:40.166163 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3948 00:25:40.169924 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3949 00:25:40.176020 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3950 00:25:40.176478 ==
3951 00:25:40.179510 Dram Type= 6, Freq= 0, CH_0, rank 0
3952 00:25:40.182767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3953 00:25:40.183168 ==
3954 00:25:40.189657 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3955 00:25:40.192660 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3956 00:25:40.197273 [CA 0] Center 36 (6~66) winsize 61
3957 00:25:40.200794 [CA 1] Center 35 (5~66) winsize 62
3958 00:25:40.203768 [CA 2] Center 34 (4~65) winsize 62
3959 00:25:40.207092 [CA 3] Center 34 (4~65) winsize 62
3960 00:25:40.210098 [CA 4] Center 34 (4~64) winsize 61
3961 00:25:40.213635 [CA 5] Center 33 (3~64) winsize 62
3962 00:25:40.214256
3963 00:25:40.216728 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3964 00:25:40.217121
3965 00:25:40.220091 [CATrainingPosCal] consider 1 rank data
3966 00:25:40.223879 u2DelayCellTimex100 = 270/100 ps
3967 00:25:40.227197 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3968 00:25:40.230423 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3969 00:25:40.237203 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3970 00:25:40.240752 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3971 00:25:40.243923 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3972 00:25:40.247623 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3973 00:25:40.248111
3974 00:25:40.250330 CA PerBit enable=1, Macro0, CA PI delay=33
3975 00:25:40.250726
3976 00:25:40.253961 [CBTSetCACLKResult] CA Dly = 33
3977 00:25:40.254398 CS Dly: 4 (0~35)
3978 00:25:40.254707 ==
3979 00:25:40.256925 Dram Type= 6, Freq= 0, CH_0, rank 1
3980 00:25:40.263718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 00:25:40.264178 ==
3982 00:25:40.266850 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3983 00:25:40.273726 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3984 00:25:40.276946 [CA 0] Center 36 (6~67) winsize 62
3985 00:25:40.280583 [CA 1] Center 36 (6~66) winsize 61
3986 00:25:40.283555 [CA 2] Center 34 (4~65) winsize 62
3987 00:25:40.287427 [CA 3] Center 34 (4~65) winsize 62
3988 00:25:40.290697 [CA 4] Center 33 (3~64) winsize 62
3989 00:25:40.293474 [CA 5] Center 33 (3~64) winsize 62
3990 00:25:40.293869
3991 00:25:40.297440 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3992 00:25:40.297909
3993 00:25:40.300441 [CATrainingPosCal] consider 2 rank data
3994 00:25:40.304104 u2DelayCellTimex100 = 270/100 ps
3995 00:25:40.307171 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3996 00:25:40.310597 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3997 00:25:40.317057 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3998 00:25:40.320687 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3999 00:25:40.323793 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4000 00:25:40.327270 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4001 00:25:40.327671
4002 00:25:40.330607 CA PerBit enable=1, Macro0, CA PI delay=33
4003 00:25:40.331070
4004 00:25:40.333939 [CBTSetCACLKResult] CA Dly = 33
4005 00:25:40.334464 CS Dly: 4 (0~36)
4006 00:25:40.334779
4007 00:25:40.336908 ----->DramcWriteLeveling(PI) begin...
4008 00:25:40.340217 ==
4009 00:25:40.343670 Dram Type= 6, Freq= 0, CH_0, rank 0
4010 00:25:40.347392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4011 00:25:40.347960 ==
4012 00:25:40.350720 Write leveling (Byte 0): 32 => 32
4013 00:25:40.353565 Write leveling (Byte 1): 28 => 28
4014 00:25:40.357210 DramcWriteLeveling(PI) end<-----
4015 00:25:40.357599
4016 00:25:40.357899 ==
4017 00:25:40.360433 Dram Type= 6, Freq= 0, CH_0, rank 0
4018 00:25:40.364032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 00:25:40.364501 ==
4020 00:25:40.366987 [Gating] SW mode calibration
4021 00:25:40.373579 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4022 00:25:40.377119 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4023 00:25:40.383650 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4024 00:25:40.387253 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4025 00:25:40.390250 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4026 00:25:40.397328 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4027 00:25:40.400592 0 9 16 | B1->B0 | 3333 3030 | 1 1 | (1 0) (0 0)
4028 00:25:40.403519 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4029 00:25:40.410501 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 00:25:40.413536 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 00:25:40.417390 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 00:25:40.424261 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 00:25:40.427024 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 00:25:40.430978 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 00:25:40.437185 0 10 16 | B1->B0 | 3030 3939 | 1 0 | (0 0) (0 0)
4036 00:25:40.440554 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 00:25:40.443552 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 00:25:40.450599 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 00:25:40.453540 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 00:25:40.456805 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 00:25:40.460208 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 00:25:40.466754 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 00:25:40.470460 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 00:25:40.473408 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 00:25:40.480507 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 00:25:40.483431 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 00:25:40.486943 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 00:25:40.493612 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 00:25:40.497499 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 00:25:40.500541 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 00:25:40.507687 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 00:25:40.510343 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 00:25:40.513584 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 00:25:40.520184 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 00:25:40.524263 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 00:25:40.526865 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 00:25:40.534156 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 00:25:40.537286 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 00:25:40.540355 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4060 00:25:40.543989 Total UI for P1: 0, mck2ui 16
4061 00:25:40.546858 best dqsien dly found for B0: ( 0, 13, 14)
4062 00:25:40.550601 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 00:25:40.553806 Total UI for P1: 0, mck2ui 16
4064 00:25:40.557604 best dqsien dly found for B1: ( 0, 13, 16)
4065 00:25:40.560515 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4066 00:25:40.567698 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4067 00:25:40.568169
4068 00:25:40.570517 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4069 00:25:40.573498 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4070 00:25:40.576828 [Gating] SW calibration Done
4071 00:25:40.577304 ==
4072 00:25:40.580969 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 00:25:40.583806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 00:25:40.584200 ==
4075 00:25:40.587477 RX Vref Scan: 0
4076 00:25:40.587961
4077 00:25:40.588364 RX Vref 0 -> 0, step: 1
4078 00:25:40.588740
4079 00:25:40.590461 RX Delay -230 -> 252, step: 16
4080 00:25:40.594062 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4081 00:25:40.600273 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4082 00:25:40.604039 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4083 00:25:40.607858 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4084 00:25:40.610935 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4085 00:25:40.614074 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4086 00:25:40.620941 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4087 00:25:40.623968 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4088 00:25:40.627624 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4089 00:25:40.630580 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4090 00:25:40.634254 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4091 00:25:40.640893 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4092 00:25:40.643774 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4093 00:25:40.647714 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4094 00:25:40.650313 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4095 00:25:40.656926 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4096 00:25:40.657402 ==
4097 00:25:40.660368 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 00:25:40.664405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 00:25:40.664891 ==
4100 00:25:40.665297 DQS Delay:
4101 00:25:40.667836 DQS0 = 0, DQS1 = 0
4102 00:25:40.668312 DQM Delay:
4103 00:25:40.670889 DQM0 = 41, DQM1 = 33
4104 00:25:40.671370 DQ Delay:
4105 00:25:40.674478 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4106 00:25:40.677273 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4107 00:25:40.680857 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4108 00:25:40.683457 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4109 00:25:40.683847
4110 00:25:40.684142
4111 00:25:40.684421 ==
4112 00:25:40.687003 Dram Type= 6, Freq= 0, CH_0, rank 0
4113 00:25:40.690838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4114 00:25:40.691321 ==
4115 00:25:40.693823
4116 00:25:40.694274
4117 00:25:40.694681 TX Vref Scan disable
4118 00:25:40.697126 == TX Byte 0 ==
4119 00:25:40.700486 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4120 00:25:40.703876 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4121 00:25:40.707393 == TX Byte 1 ==
4122 00:25:40.710366 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4123 00:25:40.713726 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4124 00:25:40.717021 ==
4125 00:25:40.717409 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 00:25:40.723749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 00:25:40.724242 ==
4128 00:25:40.724548
4129 00:25:40.724827
4130 00:25:40.726912 TX Vref Scan disable
4131 00:25:40.727301 == TX Byte 0 ==
4132 00:25:40.733584 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4133 00:25:40.737237 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4134 00:25:40.737627 == TX Byte 1 ==
4135 00:25:40.744001 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4136 00:25:40.746872 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4137 00:25:40.747343
4138 00:25:40.747764 [DATLAT]
4139 00:25:40.750432 Freq=600, CH0 RK0
4140 00:25:40.750846
4141 00:25:40.751156 DATLAT Default: 0x9
4142 00:25:40.753290 0, 0xFFFF, sum = 0
4143 00:25:40.753687 1, 0xFFFF, sum = 0
4144 00:25:40.756994 2, 0xFFFF, sum = 0
4145 00:25:40.757580 3, 0xFFFF, sum = 0
4146 00:25:40.759929 4, 0xFFFF, sum = 0
4147 00:25:40.760358 5, 0xFFFF, sum = 0
4148 00:25:40.763563 6, 0xFFFF, sum = 0
4149 00:25:40.766651 7, 0xFFFF, sum = 0
4150 00:25:40.767062 8, 0x0, sum = 1
4151 00:25:40.767371 9, 0x0, sum = 2
4152 00:25:40.770249 10, 0x0, sum = 3
4153 00:25:40.770732 11, 0x0, sum = 4
4154 00:25:40.773325 best_step = 9
4155 00:25:40.773717
4156 00:25:40.774054 ==
4157 00:25:40.777215 Dram Type= 6, Freq= 0, CH_0, rank 0
4158 00:25:40.780108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 00:25:40.780472 ==
4160 00:25:40.783721 RX Vref Scan: 1
4161 00:25:40.784103
4162 00:25:40.784473 RX Vref 0 -> 0, step: 1
4163 00:25:40.784822
4164 00:25:40.787216 RX Delay -179 -> 252, step: 8
4165 00:25:40.787588
4166 00:25:40.790120 Set Vref, RX VrefLevel [Byte0]: 54
4167 00:25:40.793584 [Byte1]: 51
4168 00:25:40.797095
4169 00:25:40.797663 Final RX Vref Byte 0 = 54 to rank0
4170 00:25:40.800652 Final RX Vref Byte 1 = 51 to rank0
4171 00:25:40.803990 Final RX Vref Byte 0 = 54 to rank1
4172 00:25:40.807311 Final RX Vref Byte 1 = 51 to rank1==
4173 00:25:40.810904 Dram Type= 6, Freq= 0, CH_0, rank 0
4174 00:25:40.817451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 00:25:40.817917 ==
4176 00:25:40.818258 DQS Delay:
4177 00:25:40.818521 DQS0 = 0, DQS1 = 0
4178 00:25:40.820505 DQM Delay:
4179 00:25:40.820861 DQM0 = 42, DQM1 = 33
4180 00:25:40.824441 DQ Delay:
4181 00:25:40.827257 DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40
4182 00:25:40.827631 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4183 00:25:40.830694 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4184 00:25:40.834467 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4185 00:25:40.837968
4186 00:25:40.838449
4187 00:25:40.843768 [DQSOSCAuto] RK0, (LSB)MR18= 0x411f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 397 ps
4188 00:25:40.847665 CH0 RK0: MR19=808, MR18=411F
4189 00:25:40.853912 CH0_RK0: MR19=0x808, MR18=0x411F, DQSOSC=397, MR23=63, INC=166, DEC=110
4190 00:25:40.854357
4191 00:25:40.857363 ----->DramcWriteLeveling(PI) begin...
4192 00:25:40.857726 ==
4193 00:25:40.860800 Dram Type= 6, Freq= 0, CH_0, rank 1
4194 00:25:40.863719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4195 00:25:40.864188 ==
4196 00:25:40.867299 Write leveling (Byte 0): 32 => 32
4197 00:25:40.870450 Write leveling (Byte 1): 31 => 31
4198 00:25:40.874082 DramcWriteLeveling(PI) end<-----
4199 00:25:40.874519
4200 00:25:40.874987 ==
4201 00:25:40.877023 Dram Type= 6, Freq= 0, CH_0, rank 1
4202 00:25:40.880626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 00:25:40.881160 ==
4204 00:25:40.884348 [Gating] SW mode calibration
4205 00:25:40.890331 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4206 00:25:40.897304 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4207 00:25:40.901039 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4208 00:25:40.904106 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4209 00:25:40.911028 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4210 00:25:40.914288 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
4211 00:25:40.917817 0 9 16 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (0 0)
4212 00:25:40.924226 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 00:25:40.927322 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 00:25:40.931047 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 00:25:40.937931 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 00:25:40.940670 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 00:25:40.944481 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 00:25:40.950741 0 10 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (1 1)
4219 00:25:40.954219 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4220 00:25:40.957198 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 00:25:40.963962 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 00:25:40.967877 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 00:25:40.970938 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 00:25:40.973679 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 00:25:40.980913 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4226 00:25:40.983858 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4227 00:25:40.987546 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4228 00:25:40.994407 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 00:25:40.997545 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 00:25:41.000878 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 00:25:41.007422 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 00:25:41.010875 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 00:25:41.014362 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 00:25:41.020444 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 00:25:41.024366 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 00:25:41.027082 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 00:25:41.033864 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 00:25:41.037486 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 00:25:41.040586 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 00:25:41.047712 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 00:25:41.050398 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 00:25:41.054374 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4243 00:25:41.060732 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 00:25:41.061167 Total UI for P1: 0, mck2ui 16
4245 00:25:41.064286 best dqsien dly found for B0: ( 0, 13, 12)
4246 00:25:41.067276 Total UI for P1: 0, mck2ui 16
4247 00:25:41.070848 best dqsien dly found for B1: ( 0, 13, 14)
4248 00:25:41.074134 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4249 00:25:41.080898 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4250 00:25:41.081349
4251 00:25:41.084403 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4252 00:25:41.087228 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4253 00:25:41.090737 [Gating] SW calibration Done
4254 00:25:41.091162 ==
4255 00:25:41.094369 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 00:25:41.097471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 00:25:41.097878 ==
4258 00:25:41.098227 RX Vref Scan: 0
4259 00:25:41.098513
4260 00:25:41.100843 RX Vref 0 -> 0, step: 1
4261 00:25:41.101249
4262 00:25:41.103954 RX Delay -230 -> 252, step: 16
4263 00:25:41.107019 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4264 00:25:41.113725 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4265 00:25:41.117532 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4266 00:25:41.120756 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4267 00:25:41.123781 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4268 00:25:41.127672 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4269 00:25:41.133885 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4270 00:25:41.137686 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4271 00:25:41.140827 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4272 00:25:41.144360 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4273 00:25:41.150671 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4274 00:25:41.153861 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4275 00:25:41.157465 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4276 00:25:41.160539 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4277 00:25:41.164020 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4278 00:25:41.170931 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4279 00:25:41.171396 ==
4280 00:25:41.174477 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 00:25:41.177554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 00:25:41.178055 ==
4283 00:25:41.178367 DQS Delay:
4284 00:25:41.180745 DQS0 = 0, DQS1 = 0
4285 00:25:41.181138 DQM Delay:
4286 00:25:41.184105 DQM0 = 38, DQM1 = 31
4287 00:25:41.184493 DQ Delay:
4288 00:25:41.186987 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4289 00:25:41.190482 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4290 00:25:41.194040 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4291 00:25:41.197613 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4292 00:25:41.198031
4293 00:25:41.198338
4294 00:25:41.198611 ==
4295 00:25:41.200730 Dram Type= 6, Freq= 0, CH_0, rank 1
4296 00:25:41.204053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4297 00:25:41.204441 ==
4298 00:25:41.207131
4299 00:25:41.207403
4300 00:25:41.207614 TX Vref Scan disable
4301 00:25:41.210622 == TX Byte 0 ==
4302 00:25:41.214738 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4303 00:25:41.217350 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4304 00:25:41.220558 == TX Byte 1 ==
4305 00:25:41.224103 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4306 00:25:41.227227 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4307 00:25:41.230755 ==
4308 00:25:41.231138 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 00:25:41.237375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 00:25:41.238037 ==
4311 00:25:41.238366
4312 00:25:41.238646
4313 00:25:41.240953 TX Vref Scan disable
4314 00:25:41.241423 == TX Byte 0 ==
4315 00:25:41.247280 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4316 00:25:41.250541 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4317 00:25:41.250928 == TX Byte 1 ==
4318 00:25:41.257009 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4319 00:25:41.260708 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4320 00:25:41.261106
4321 00:25:41.261405 [DATLAT]
4322 00:25:41.264507 Freq=600, CH0 RK1
4323 00:25:41.264973
4324 00:25:41.265274 DATLAT Default: 0x9
4325 00:25:41.267493 0, 0xFFFF, sum = 0
4326 00:25:41.267964 1, 0xFFFF, sum = 0
4327 00:25:41.270833 2, 0xFFFF, sum = 0
4328 00:25:41.271298 3, 0xFFFF, sum = 0
4329 00:25:41.274498 4, 0xFFFF, sum = 0
4330 00:25:41.274970 5, 0xFFFF, sum = 0
4331 00:25:41.277781 6, 0xFFFF, sum = 0
4332 00:25:41.278291 7, 0xFFFF, sum = 0
4333 00:25:41.280779 8, 0x0, sum = 1
4334 00:25:41.281172 9, 0x0, sum = 2
4335 00:25:41.283819 10, 0x0, sum = 3
4336 00:25:41.284211 11, 0x0, sum = 4
4337 00:25:41.287407 best_step = 9
4338 00:25:41.287791
4339 00:25:41.288091 ==
4340 00:25:41.290572 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 00:25:41.294179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 00:25:41.294646 ==
4343 00:25:41.297813 RX Vref Scan: 0
4344 00:25:41.298315
4345 00:25:41.298620 RX Vref 0 -> 0, step: 1
4346 00:25:41.298901
4347 00:25:41.300898 RX Delay -195 -> 252, step: 8
4348 00:25:41.307764 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4349 00:25:41.310669 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4350 00:25:41.314081 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4351 00:25:41.317870 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4352 00:25:41.324937 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4353 00:25:41.327596 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4354 00:25:41.330648 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4355 00:25:41.334273 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4356 00:25:41.337492 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4357 00:25:41.344135 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4358 00:25:41.347994 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4359 00:25:41.350820 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4360 00:25:41.354088 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4361 00:25:41.360955 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4362 00:25:41.364321 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4363 00:25:41.367667 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4364 00:25:41.368139 ==
4365 00:25:41.371347 Dram Type= 6, Freq= 0, CH_0, rank 1
4366 00:25:41.374507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 00:25:41.374896 ==
4368 00:25:41.377484 DQS Delay:
4369 00:25:41.377869 DQS0 = 0, DQS1 = 0
4370 00:25:41.381014 DQM Delay:
4371 00:25:41.381413 DQM0 = 40, DQM1 = 33
4372 00:25:41.381719 DQ Delay:
4373 00:25:41.384230 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4374 00:25:41.387835 DQ4 =40, DQ5 =28, DQ6 =52, DQ7 =48
4375 00:25:41.391048 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4376 00:25:41.394645 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4377 00:25:41.395120
4378 00:25:41.395425
4379 00:25:41.404787 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b2d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 395 ps
4380 00:25:41.407594 CH0 RK1: MR19=808, MR18=4B2D
4381 00:25:41.411033 CH0_RK1: MR19=0x808, MR18=0x4B2D, DQSOSC=395, MR23=63, INC=168, DEC=112
4382 00:25:41.414008 [RxdqsGatingPostProcess] freq 600
4383 00:25:41.421041 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4384 00:25:41.424192 Pre-setting of DQS Precalculation
4385 00:25:41.427348 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4386 00:25:41.427738 ==
4387 00:25:41.430937 Dram Type= 6, Freq= 0, CH_1, rank 0
4388 00:25:41.438127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 00:25:41.438604 ==
4390 00:25:41.441192 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4391 00:25:41.447931 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4392 00:25:41.451137 [CA 0] Center 35 (5~65) winsize 61
4393 00:25:41.454565 [CA 1] Center 35 (5~66) winsize 62
4394 00:25:41.457472 [CA 2] Center 34 (4~64) winsize 61
4395 00:25:41.461293 [CA 3] Center 33 (3~64) winsize 62
4396 00:25:41.464847 [CA 4] Center 34 (3~65) winsize 63
4397 00:25:41.467968 [CA 5] Center 33 (3~64) winsize 62
4398 00:25:41.468437
4399 00:25:41.471377 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4400 00:25:41.471857
4401 00:25:41.474142 [CATrainingPosCal] consider 1 rank data
4402 00:25:41.477832 u2DelayCellTimex100 = 270/100 ps
4403 00:25:41.481011 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4404 00:25:41.484024 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4405 00:25:41.490736 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4406 00:25:41.494474 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4407 00:25:41.497648 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4408 00:25:41.500937 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4409 00:25:41.501327
4410 00:25:41.504562 CA PerBit enable=1, Macro0, CA PI delay=33
4411 00:25:41.504950
4412 00:25:41.508087 [CBTSetCACLKResult] CA Dly = 33
4413 00:25:41.508477 CS Dly: 5 (0~36)
4414 00:25:41.508781 ==
4415 00:25:41.511147 Dram Type= 6, Freq= 0, CH_1, rank 1
4416 00:25:41.517846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 00:25:41.518354 ==
4418 00:25:41.521128 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4419 00:25:41.527980 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4420 00:25:41.531671 [CA 0] Center 35 (5~66) winsize 62
4421 00:25:41.534884 [CA 1] Center 35 (5~66) winsize 62
4422 00:25:41.537690 [CA 2] Center 34 (4~65) winsize 62
4423 00:25:41.541352 [CA 3] Center 34 (3~65) winsize 63
4424 00:25:41.544439 [CA 4] Center 34 (3~65) winsize 63
4425 00:25:41.548083 [CA 5] Center 33 (3~64) winsize 62
4426 00:25:41.548577
4427 00:25:41.551099 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4428 00:25:41.551627
4429 00:25:41.554720 [CATrainingPosCal] consider 2 rank data
4430 00:25:41.558035 u2DelayCellTimex100 = 270/100 ps
4431 00:25:41.561607 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4432 00:25:41.564987 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4433 00:25:41.568456 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4434 00:25:41.574511 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4435 00:25:41.578275 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4436 00:25:41.581096 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4437 00:25:41.581659
4438 00:25:41.584710 CA PerBit enable=1, Macro0, CA PI delay=33
4439 00:25:41.585098
4440 00:25:41.588077 [CBTSetCACLKResult] CA Dly = 33
4441 00:25:41.588553 CS Dly: 5 (0~37)
4442 00:25:41.588860
4443 00:25:41.591479 ----->DramcWriteLeveling(PI) begin...
4444 00:25:41.592106 ==
4445 00:25:41.594757 Dram Type= 6, Freq= 0, CH_1, rank 0
4446 00:25:41.601734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4447 00:25:41.602273 ==
4448 00:25:41.604638 Write leveling (Byte 0): 30 => 30
4449 00:25:41.607716 Write leveling (Byte 1): 31 => 31
4450 00:25:41.608108 DramcWriteLeveling(PI) end<-----
4451 00:25:41.611187
4452 00:25:41.611651 ==
4453 00:25:41.614924 Dram Type= 6, Freq= 0, CH_1, rank 0
4454 00:25:41.618442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4455 00:25:41.618915 ==
4456 00:25:41.621178 [Gating] SW mode calibration
4457 00:25:41.627729 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4458 00:25:41.631473 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4459 00:25:41.638164 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4460 00:25:41.641440 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4461 00:25:41.644307 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4462 00:25:41.651746 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
4463 00:25:41.654380 0 9 16 | B1->B0 | 2a2a 2727 | 1 0 | (0 0) (1 0)
4464 00:25:41.657529 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 00:25:41.664289 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 00:25:41.668256 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 00:25:41.671023 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 00:25:41.677969 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 00:25:41.681620 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 00:25:41.684598 0 10 12 | B1->B0 | 2525 2b2b | 0 1 | (0 0) (0 0)
4471 00:25:41.691173 0 10 16 | B1->B0 | 4141 4444 | 0 0 | (0 0) (1 1)
4472 00:25:41.694437 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 00:25:41.697792 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 00:25:41.700919 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 00:25:41.708071 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 00:25:41.710932 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 00:25:41.714553 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 00:25:41.720914 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4479 00:25:41.724344 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4480 00:25:41.727833 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 00:25:41.734696 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 00:25:41.737596 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 00:25:41.741431 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 00:25:41.748057 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 00:25:41.751092 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 00:25:41.754114 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 00:25:41.760679 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 00:25:41.764473 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 00:25:41.768235 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 00:25:41.774420 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 00:25:41.778223 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 00:25:41.781410 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 00:25:41.787750 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 00:25:41.791472 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 00:25:41.794531 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 00:25:41.798089 Total UI for P1: 0, mck2ui 16
4497 00:25:41.801393 best dqsien dly found for B0: ( 0, 13, 14)
4498 00:25:41.804137 Total UI for P1: 0, mck2ui 16
4499 00:25:41.807438 best dqsien dly found for B1: ( 0, 13, 14)
4500 00:25:41.811423 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4501 00:25:41.814446 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4502 00:25:41.814883
4503 00:25:41.817521 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4504 00:25:41.824471 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4505 00:25:41.824931 [Gating] SW calibration Done
4506 00:25:41.825363 ==
4507 00:25:41.827720 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 00:25:41.834209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 00:25:41.834528 ==
4510 00:25:41.834838 RX Vref Scan: 0
4511 00:25:41.835140
4512 00:25:41.837954 RX Vref 0 -> 0, step: 1
4513 00:25:41.838196
4514 00:25:41.840806 RX Delay -230 -> 252, step: 16
4515 00:25:41.844266 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4516 00:25:41.847329 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4517 00:25:41.851095 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4518 00:25:41.857806 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4519 00:25:41.861502 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4520 00:25:41.864300 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4521 00:25:41.867982 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4522 00:25:41.871309 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4523 00:25:41.877620 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4524 00:25:41.881317 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4525 00:25:41.884699 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4526 00:25:41.887877 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4527 00:25:41.894454 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4528 00:25:41.897932 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4529 00:25:41.901338 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4530 00:25:41.904420 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4531 00:25:41.904674 ==
4532 00:25:41.908125 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 00:25:41.914634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 00:25:41.914987 ==
4535 00:25:41.915261 DQS Delay:
4536 00:25:41.915512 DQS0 = 0, DQS1 = 0
4537 00:25:41.918149 DQM Delay:
4538 00:25:41.918498 DQM0 = 46, DQM1 = 37
4539 00:25:41.921514 DQ Delay:
4540 00:25:41.925047 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4541 00:25:41.927806 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =41
4542 00:25:41.931380 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4543 00:25:41.935264 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4544 00:25:41.935709
4545 00:25:41.935983
4546 00:25:41.936234 ==
4547 00:25:41.938481 Dram Type= 6, Freq= 0, CH_1, rank 0
4548 00:25:41.941500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4549 00:25:41.941861 ==
4550 00:25:41.942193
4551 00:25:41.942531
4552 00:25:41.945027 TX Vref Scan disable
4553 00:25:41.945381 == TX Byte 0 ==
4554 00:25:41.951646 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4555 00:25:41.955314 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4556 00:25:41.955681 == TX Byte 1 ==
4557 00:25:41.961646 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4558 00:25:41.965204 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4559 00:25:41.965569 ==
4560 00:25:41.968779 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 00:25:41.971915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 00:25:41.972274 ==
4563 00:25:41.972548
4564 00:25:41.972799
4565 00:25:41.975011 TX Vref Scan disable
4566 00:25:41.978684 == TX Byte 0 ==
4567 00:25:41.981704 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4568 00:25:41.985315 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4569 00:25:41.988425 == TX Byte 1 ==
4570 00:25:41.991852 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4571 00:25:41.995063 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4572 00:25:41.995438
4573 00:25:41.998254 [DATLAT]
4574 00:25:41.998601 Freq=600, CH1 RK0
4575 00:25:41.998879
4576 00:25:42.001760 DATLAT Default: 0x9
4577 00:25:42.002208 0, 0xFFFF, sum = 0
4578 00:25:42.004983 1, 0xFFFF, sum = 0
4579 00:25:42.005456 2, 0xFFFF, sum = 0
4580 00:25:42.008476 3, 0xFFFF, sum = 0
4581 00:25:42.008840 4, 0xFFFF, sum = 0
4582 00:25:42.011962 5, 0xFFFF, sum = 0
4583 00:25:42.012320 6, 0xFFFF, sum = 0
4584 00:25:42.014807 7, 0xFFFF, sum = 0
4585 00:25:42.015170 8, 0x0, sum = 1
4586 00:25:42.018567 9, 0x0, sum = 2
4587 00:25:42.018925 10, 0x0, sum = 3
4588 00:25:42.021782 11, 0x0, sum = 4
4589 00:25:42.022179 best_step = 9
4590 00:25:42.022456
4591 00:25:42.022707 ==
4592 00:25:42.025041 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 00:25:42.028695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 00:25:42.031938 ==
4595 00:25:42.032378 RX Vref Scan: 1
4596 00:25:42.032659
4597 00:25:42.035209 RX Vref 0 -> 0, step: 1
4598 00:25:42.035597
4599 00:25:42.038301 RX Delay -179 -> 252, step: 8
4600 00:25:42.038807
4601 00:25:42.039217 Set Vref, RX VrefLevel [Byte0]: 61
4602 00:25:42.041619 [Byte1]: 53
4603 00:25:42.046860
4604 00:25:42.047213 Final RX Vref Byte 0 = 61 to rank0
4605 00:25:42.050440 Final RX Vref Byte 1 = 53 to rank0
4606 00:25:42.053366 Final RX Vref Byte 0 = 61 to rank1
4607 00:25:42.056310 Final RX Vref Byte 1 = 53 to rank1==
4608 00:25:42.059679 Dram Type= 6, Freq= 0, CH_1, rank 0
4609 00:25:42.066305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 00:25:42.066693 ==
4611 00:25:42.067289 DQS Delay:
4612 00:25:42.067792 DQS0 = 0, DQS1 = 0
4613 00:25:42.070011 DQM Delay:
4614 00:25:42.070507 DQM0 = 41, DQM1 = 34
4615 00:25:42.073578 DQ Delay:
4616 00:25:42.077009 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =44
4617 00:25:42.077480 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4618 00:25:42.080291 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4619 00:25:42.083323 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =40
4620 00:25:42.086439
4621 00:25:42.086830
4622 00:25:42.094213 [DQSOSCAuto] RK0, (LSB)MR18= 0x450b, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4623 00:25:42.096790 CH1 RK0: MR19=808, MR18=450B
4624 00:25:42.103552 CH1_RK0: MR19=0x808, MR18=0x450B, DQSOSC=396, MR23=63, INC=167, DEC=111
4625 00:25:42.104163
4626 00:25:42.106850 ----->DramcWriteLeveling(PI) begin...
4627 00:25:42.107312 ==
4628 00:25:42.110389 Dram Type= 6, Freq= 0, CH_1, rank 1
4629 00:25:42.113575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4630 00:25:42.113962 ==
4631 00:25:42.116747 Write leveling (Byte 0): 31 => 31
4632 00:25:42.120278 Write leveling (Byte 1): 31 => 31
4633 00:25:42.123304 DramcWriteLeveling(PI) end<-----
4634 00:25:42.123715
4635 00:25:42.124040 ==
4636 00:25:42.126887 Dram Type= 6, Freq= 0, CH_1, rank 1
4637 00:25:42.130123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 00:25:42.130518 ==
4639 00:25:42.133979 [Gating] SW mode calibration
4640 00:25:42.140602 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4641 00:25:42.146617 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4642 00:25:42.150526 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4643 00:25:42.153645 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4644 00:25:42.160273 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4645 00:25:42.163601 0 9 12 | B1->B0 | 3131 2b2b | 0 0 | (0 1) (1 1)
4646 00:25:42.166757 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4647 00:25:42.173192 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4648 00:25:42.176655 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 00:25:42.179705 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4650 00:25:42.186476 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 00:25:42.190101 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 00:25:42.193148 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 00:25:42.199858 0 10 12 | B1->B0 | 2d2d 3d3d | 1 0 | (0 0) (0 0)
4654 00:25:42.202919 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4655 00:25:42.206529 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 00:25:42.213468 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 00:25:42.216402 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 00:25:42.220118 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 00:25:42.223809 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 00:25:42.229924 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4661 00:25:42.233611 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4662 00:25:42.236525 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 00:25:42.243539 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 00:25:42.246830 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 00:25:42.249761 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 00:25:42.256523 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 00:25:42.259616 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 00:25:42.263094 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 00:25:42.270214 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 00:25:42.273454 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 00:25:42.276952 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 00:25:42.283752 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 00:25:42.286703 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 00:25:42.289940 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 00:25:42.293750 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 00:25:42.300289 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4677 00:25:42.303458 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4678 00:25:42.306905 Total UI for P1: 0, mck2ui 16
4679 00:25:42.310494 best dqsien dly found for B0: ( 0, 13, 8)
4680 00:25:42.313565 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 00:25:42.317368 Total UI for P1: 0, mck2ui 16
4682 00:25:42.320623 best dqsien dly found for B1: ( 0, 13, 12)
4683 00:25:42.323456 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4684 00:25:42.326996 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4685 00:25:42.327414
4686 00:25:42.333736 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4687 00:25:42.336852 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4688 00:25:42.337244 [Gating] SW calibration Done
4689 00:25:42.340318 ==
4690 00:25:42.344151 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 00:25:42.346808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 00:25:42.347198 ==
4693 00:25:42.347503 RX Vref Scan: 0
4694 00:25:42.347785
4695 00:25:42.350127 RX Vref 0 -> 0, step: 1
4696 00:25:42.350618
4697 00:25:42.353675 RX Delay -230 -> 252, step: 16
4698 00:25:42.356772 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4699 00:25:42.360521 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4700 00:25:42.366889 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4701 00:25:42.370561 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4702 00:25:42.373722 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4703 00:25:42.377382 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4704 00:25:42.380459 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4705 00:25:42.387135 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4706 00:25:42.390655 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4707 00:25:42.393528 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4708 00:25:42.397466 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4709 00:25:42.403767 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4710 00:25:42.406786 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4711 00:25:42.410437 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4712 00:25:42.414142 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4713 00:25:42.420995 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4714 00:25:42.421474 ==
4715 00:25:42.423950 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 00:25:42.427743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 00:25:42.428215 ==
4718 00:25:42.428520 DQS Delay:
4719 00:25:42.430458 DQS0 = 0, DQS1 = 0
4720 00:25:42.430844 DQM Delay:
4721 00:25:42.434409 DQM0 = 39, DQM1 = 35
4722 00:25:42.434878 DQ Delay:
4723 00:25:42.437421 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4724 00:25:42.440984 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4725 00:25:42.443630 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4726 00:25:42.447382 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4727 00:25:42.447849
4728 00:25:42.448148
4729 00:25:42.448427 ==
4730 00:25:42.450188 Dram Type= 6, Freq= 0, CH_1, rank 1
4731 00:25:42.454120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4732 00:25:42.454592 ==
4733 00:25:42.454897
4734 00:25:42.455265
4735 00:25:42.457506 TX Vref Scan disable
4736 00:25:42.460517 == TX Byte 0 ==
4737 00:25:42.464009 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4738 00:25:42.467137 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4739 00:25:42.470338 == TX Byte 1 ==
4740 00:25:42.474056 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4741 00:25:42.477116 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4742 00:25:42.477500 ==
4743 00:25:42.480453 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 00:25:42.487135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 00:25:42.487542 ==
4746 00:25:42.487840
4747 00:25:42.488115
4748 00:25:42.488378 TX Vref Scan disable
4749 00:25:42.491011 == TX Byte 0 ==
4750 00:25:42.494358 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4751 00:25:42.501187 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4752 00:25:42.501659 == TX Byte 1 ==
4753 00:25:42.504550 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4754 00:25:42.507922 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4755 00:25:42.511434
4756 00:25:42.511901 [DATLAT]
4757 00:25:42.512208 Freq=600, CH1 RK1
4758 00:25:42.512488
4759 00:25:42.514815 DATLAT Default: 0x9
4760 00:25:42.515322 0, 0xFFFF, sum = 0
4761 00:25:42.518014 1, 0xFFFF, sum = 0
4762 00:25:42.518407 2, 0xFFFF, sum = 0
4763 00:25:42.521113 3, 0xFFFF, sum = 0
4764 00:25:42.521516 4, 0xFFFF, sum = 0
4765 00:25:42.524936 5, 0xFFFF, sum = 0
4766 00:25:42.527883 6, 0xFFFF, sum = 0
4767 00:25:42.528362 7, 0xFFFF, sum = 0
4768 00:25:42.528671 8, 0x0, sum = 1
4769 00:25:42.531454 9, 0x0, sum = 2
4770 00:25:42.531841 10, 0x0, sum = 3
4771 00:25:42.534588 11, 0x0, sum = 4
4772 00:25:42.535064 best_step = 9
4773 00:25:42.535367
4774 00:25:42.535644 ==
4775 00:25:42.538377 Dram Type= 6, Freq= 0, CH_1, rank 1
4776 00:25:42.544957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4777 00:25:42.545422 ==
4778 00:25:42.545721 RX Vref Scan: 0
4779 00:25:42.546103
4780 00:25:42.547600 RX Vref 0 -> 0, step: 1
4781 00:25:42.547982
4782 00:25:42.550968 RX Delay -195 -> 252, step: 8
4783 00:25:42.554698 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4784 00:25:42.561174 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4785 00:25:42.565125 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4786 00:25:42.568198 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4787 00:25:42.571542 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4788 00:25:42.575034 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4789 00:25:42.581254 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4790 00:25:42.584875 iDelay=205, Bit 7, Center 32 (-115 ~ 180) 296
4791 00:25:42.588056 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4792 00:25:42.591320 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4793 00:25:42.594833 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4794 00:25:42.601735 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4795 00:25:42.604967 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4796 00:25:42.608595 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4797 00:25:42.611607 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4798 00:25:42.618102 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4799 00:25:42.618575 ==
4800 00:25:42.621307 Dram Type= 6, Freq= 0, CH_1, rank 1
4801 00:25:42.624848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4802 00:25:42.625322 ==
4803 00:25:42.625629 DQS Delay:
4804 00:25:42.628326 DQS0 = 0, DQS1 = 0
4805 00:25:42.628798 DQM Delay:
4806 00:25:42.632010 DQM0 = 38, DQM1 = 32
4807 00:25:42.632476 DQ Delay:
4808 00:25:42.634951 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4809 00:25:42.638910 DQ4 =36, DQ5 =52, DQ6 =48, DQ7 =32
4810 00:25:42.641860 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4811 00:25:42.645439 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4812 00:25:42.645903
4813 00:25:42.646241
4814 00:25:42.651509 [DQSOSCAuto] RK1, (LSB)MR18= 0x3645, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4815 00:25:42.655339 CH1 RK1: MR19=808, MR18=3645
4816 00:25:42.661334 CH1_RK1: MR19=0x808, MR18=0x3645, DQSOSC=396, MR23=63, INC=167, DEC=111
4817 00:25:42.665245 [RxdqsGatingPostProcess] freq 600
4818 00:25:42.671549 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4819 00:25:42.672004 Pre-setting of DQS Precalculation
4820 00:25:42.678675 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4821 00:25:42.685067 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4822 00:25:42.691587 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4823 00:25:42.691976
4824 00:25:42.692270
4825 00:25:42.695074 [Calibration Summary] 1200 Mbps
4826 00:25:42.698346 CH 0, Rank 0
4827 00:25:42.698820 SW Impedance : PASS
4828 00:25:42.701791 DUTY Scan : NO K
4829 00:25:42.702227 ZQ Calibration : PASS
4830 00:25:42.705164 Jitter Meter : NO K
4831 00:25:42.708787 CBT Training : PASS
4832 00:25:42.709267 Write leveling : PASS
4833 00:25:42.711598 RX DQS gating : PASS
4834 00:25:42.714759 RX DQ/DQS(RDDQC) : PASS
4835 00:25:42.715143 TX DQ/DQS : PASS
4836 00:25:42.718488 RX DATLAT : PASS
4837 00:25:42.721970 RX DQ/DQS(Engine): PASS
4838 00:25:42.722476 TX OE : NO K
4839 00:25:42.724947 All Pass.
4840 00:25:42.725414
4841 00:25:42.725720 CH 0, Rank 1
4842 00:25:42.728732 SW Impedance : PASS
4843 00:25:42.729203 DUTY Scan : NO K
4844 00:25:42.731406 ZQ Calibration : PASS
4845 00:25:42.734811 Jitter Meter : NO K
4846 00:25:42.735194 CBT Training : PASS
4847 00:25:42.738062 Write leveling : PASS
4848 00:25:42.742021 RX DQS gating : PASS
4849 00:25:42.742533 RX DQ/DQS(RDDQC) : PASS
4850 00:25:42.745217 TX DQ/DQS : PASS
4851 00:25:42.745684 RX DATLAT : PASS
4852 00:25:42.748054 RX DQ/DQS(Engine): PASS
4853 00:25:42.751414 TX OE : NO K
4854 00:25:42.751800 All Pass.
4855 00:25:42.752104
4856 00:25:42.752379 CH 1, Rank 0
4857 00:25:42.755204 SW Impedance : PASS
4858 00:25:42.758256 DUTY Scan : NO K
4859 00:25:42.758642 ZQ Calibration : PASS
4860 00:25:42.761159 Jitter Meter : NO K
4861 00:25:42.764601 CBT Training : PASS
4862 00:25:42.764985 Write leveling : PASS
4863 00:25:42.768175 RX DQS gating : PASS
4864 00:25:42.771717 RX DQ/DQS(RDDQC) : PASS
4865 00:25:42.772100 TX DQ/DQS : PASS
4866 00:25:42.774773 RX DATLAT : PASS
4867 00:25:42.778826 RX DQ/DQS(Engine): PASS
4868 00:25:42.779290 TX OE : NO K
4869 00:25:42.781721 All Pass.
4870 00:25:42.782219
4871 00:25:42.782526 CH 1, Rank 1
4872 00:25:42.784504 SW Impedance : PASS
4873 00:25:42.784892 DUTY Scan : NO K
4874 00:25:42.788072 ZQ Calibration : PASS
4875 00:25:42.791168 Jitter Meter : NO K
4876 00:25:42.791552 CBT Training : PASS
4877 00:25:42.794862 Write leveling : PASS
4878 00:25:42.795248 RX DQS gating : PASS
4879 00:25:42.798103 RX DQ/DQS(RDDQC) : PASS
4880 00:25:42.801569 TX DQ/DQS : PASS
4881 00:25:42.801955 RX DATLAT : PASS
4882 00:25:42.805289 RX DQ/DQS(Engine): PASS
4883 00:25:42.807948 TX OE : NO K
4884 00:25:42.808333 All Pass.
4885 00:25:42.808631
4886 00:25:42.811370 DramC Write-DBI off
4887 00:25:42.811756 PER_BANK_REFRESH: Hybrid Mode
4888 00:25:42.815320 TX_TRACKING: ON
4889 00:25:42.821800 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4890 00:25:42.828062 [FAST_K] Save calibration result to emmc
4891 00:25:42.831563 dramc_set_vcore_voltage set vcore to 662500
4892 00:25:42.832037 Read voltage for 933, 3
4893 00:25:42.834924 Vio18 = 0
4894 00:25:42.835387 Vcore = 662500
4895 00:25:42.835687 Vdram = 0
4896 00:25:42.838480 Vddq = 0
4897 00:25:42.838865 Vmddr = 0
4898 00:25:42.841455 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4899 00:25:42.848297 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4900 00:25:42.851704 MEM_TYPE=3, freq_sel=17
4901 00:25:42.854726 sv_algorithm_assistance_LP4_1600
4902 00:25:42.858264 ============ PULL DRAM RESETB DOWN ============
4903 00:25:42.861509 ========== PULL DRAM RESETB DOWN end =========
4904 00:25:42.865109 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4905 00:25:42.867830 ===================================
4906 00:25:42.871427 LPDDR4 DRAM CONFIGURATION
4907 00:25:42.874808 ===================================
4908 00:25:42.878522 EX_ROW_EN[0] = 0x0
4909 00:25:42.879043 EX_ROW_EN[1] = 0x0
4910 00:25:42.881469 LP4Y_EN = 0x0
4911 00:25:42.881856 WORK_FSP = 0x0
4912 00:25:42.885269 WL = 0x3
4913 00:25:42.885738 RL = 0x3
4914 00:25:42.888126 BL = 0x2
4915 00:25:42.888510 RPST = 0x0
4916 00:25:42.891704 RD_PRE = 0x0
4917 00:25:42.892088 WR_PRE = 0x1
4918 00:25:42.895631 WR_PST = 0x0
4919 00:25:42.896104 DBI_WR = 0x0
4920 00:25:42.898555 DBI_RD = 0x0
4921 00:25:42.898944 OTF = 0x1
4922 00:25:42.901399 ===================================
4923 00:25:42.905260 ===================================
4924 00:25:42.908219 ANA top config
4925 00:25:42.911668 ===================================
4926 00:25:42.914914 DLL_ASYNC_EN = 0
4927 00:25:42.915415 ALL_SLAVE_EN = 1
4928 00:25:42.918073 NEW_RANK_MODE = 1
4929 00:25:42.922069 DLL_IDLE_MODE = 1
4930 00:25:42.924973 LP45_APHY_COMB_EN = 1
4931 00:25:42.925439 TX_ODT_DIS = 1
4932 00:25:42.927846 NEW_8X_MODE = 1
4933 00:25:42.931362 ===================================
4934 00:25:42.934524 ===================================
4935 00:25:42.938360 data_rate = 1866
4936 00:25:42.941724 CKR = 1
4937 00:25:42.944524 DQ_P2S_RATIO = 8
4938 00:25:42.948552 ===================================
4939 00:25:42.951716 CA_P2S_RATIO = 8
4940 00:25:42.952187 DQ_CA_OPEN = 0
4941 00:25:42.954900 DQ_SEMI_OPEN = 0
4942 00:25:42.958469 CA_SEMI_OPEN = 0
4943 00:25:42.961158 CA_FULL_RATE = 0
4944 00:25:42.964691 DQ_CKDIV4_EN = 1
4945 00:25:42.967814 CA_CKDIV4_EN = 1
4946 00:25:42.968199 CA_PREDIV_EN = 0
4947 00:25:42.971385 PH8_DLY = 0
4948 00:25:42.974416 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4949 00:25:42.977906 DQ_AAMCK_DIV = 4
4950 00:25:42.981545 CA_AAMCK_DIV = 4
4951 00:25:42.984803 CA_ADMCK_DIV = 4
4952 00:25:42.985295 DQ_TRACK_CA_EN = 0
4953 00:25:42.987985 CA_PICK = 933
4954 00:25:42.991716 CA_MCKIO = 933
4955 00:25:42.994617 MCKIO_SEMI = 0
4956 00:25:42.998271 PLL_FREQ = 3732
4957 00:25:43.001516 DQ_UI_PI_RATIO = 32
4958 00:25:43.005249 CA_UI_PI_RATIO = 0
4959 00:25:43.008131 ===================================
4960 00:25:43.011189 ===================================
4961 00:25:43.011577 memory_type:LPDDR4
4962 00:25:43.014869 GP_NUM : 10
4963 00:25:43.015364 SRAM_EN : 1
4964 00:25:43.018207 MD32_EN : 0
4965 00:25:43.021723 ===================================
4966 00:25:43.024444 [ANA_INIT] >>>>>>>>>>>>>>
4967 00:25:43.028310 <<<<<< [CONFIGURE PHASE]: ANA_TX
4968 00:25:43.031486 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4969 00:25:43.034998 ===================================
4970 00:25:43.038506 data_rate = 1866,PCW = 0X8f00
4971 00:25:43.038977 ===================================
4972 00:25:43.044633 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4973 00:25:43.048255 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4974 00:25:43.054884 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4975 00:25:43.058367 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4976 00:25:43.061521 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4977 00:25:43.064533 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4978 00:25:43.068203 [ANA_INIT] flow start
4979 00:25:43.072072 [ANA_INIT] PLL >>>>>>>>
4980 00:25:43.072553 [ANA_INIT] PLL <<<<<<<<
4981 00:25:43.074690 [ANA_INIT] MIDPI >>>>>>>>
4982 00:25:43.078396 [ANA_INIT] MIDPI <<<<<<<<
4983 00:25:43.078781 [ANA_INIT] DLL >>>>>>>>
4984 00:25:43.081860 [ANA_INIT] flow end
4985 00:25:43.084691 ============ LP4 DIFF to SE enter ============
4986 00:25:43.088236 ============ LP4 DIFF to SE exit ============
4987 00:25:43.091435 [ANA_INIT] <<<<<<<<<<<<<
4988 00:25:43.095096 [Flow] Enable top DCM control >>>>>
4989 00:25:43.098434 [Flow] Enable top DCM control <<<<<
4990 00:25:43.101374 Enable DLL master slave shuffle
4991 00:25:43.108458 ==============================================================
4992 00:25:43.108843 Gating Mode config
4993 00:25:43.114924 ==============================================================
4994 00:25:43.115313 Config description:
4995 00:25:43.124932 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4996 00:25:43.131421 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4997 00:25:43.138196 SELPH_MODE 0: By rank 1: By Phase
4998 00:25:43.141729 ==============================================================
4999 00:25:43.144982 GAT_TRACK_EN = 1
5000 00:25:43.148370 RX_GATING_MODE = 2
5001 00:25:43.152011 RX_GATING_TRACK_MODE = 2
5002 00:25:43.155051 SELPH_MODE = 1
5003 00:25:43.158301 PICG_EARLY_EN = 1
5004 00:25:43.161251 VALID_LAT_VALUE = 1
5005 00:25:43.164807 ==============================================================
5006 00:25:43.167901 Enter into Gating configuration >>>>
5007 00:25:43.171684 Exit from Gating configuration <<<<
5008 00:25:43.174609 Enter into DVFS_PRE_config >>>>>
5009 00:25:43.188506 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5010 00:25:43.191440 Exit from DVFS_PRE_config <<<<<
5011 00:25:43.194878 Enter into PICG configuration >>>>
5012 00:25:43.195273 Exit from PICG configuration <<<<
5013 00:25:43.198365 [RX_INPUT] configuration >>>>>
5014 00:25:43.201689 [RX_INPUT] configuration <<<<<
5015 00:25:43.208056 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5016 00:25:43.211559 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5017 00:25:43.218016 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5018 00:25:43.224900 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5019 00:25:43.231584 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5020 00:25:43.238495 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5021 00:25:43.242125 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5022 00:25:43.245081 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5023 00:25:43.248140 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5024 00:25:43.254977 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5025 00:25:43.258193 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5026 00:25:43.261646 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5027 00:25:43.265110 ===================================
5028 00:25:43.268393 LPDDR4 DRAM CONFIGURATION
5029 00:25:43.271688 ===================================
5030 00:25:43.272081 EX_ROW_EN[0] = 0x0
5031 00:25:43.274654 EX_ROW_EN[1] = 0x0
5032 00:25:43.278536 LP4Y_EN = 0x0
5033 00:25:43.279120 WORK_FSP = 0x0
5034 00:25:43.281328 WL = 0x3
5035 00:25:43.281687 RL = 0x3
5036 00:25:43.284684 BL = 0x2
5037 00:25:43.285080 RPST = 0x0
5038 00:25:43.288613 RD_PRE = 0x0
5039 00:25:43.289085 WR_PRE = 0x1
5040 00:25:43.291360 WR_PST = 0x0
5041 00:25:43.291957 DBI_WR = 0x0
5042 00:25:43.294766 DBI_RD = 0x0
5043 00:25:43.295119 OTF = 0x1
5044 00:25:43.298209 ===================================
5045 00:25:43.301435 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5046 00:25:43.308455 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5047 00:25:43.311795 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5048 00:25:43.315179 ===================================
5049 00:25:43.318340 LPDDR4 DRAM CONFIGURATION
5050 00:25:43.321569 ===================================
5051 00:25:43.321965 EX_ROW_EN[0] = 0x10
5052 00:25:43.325072 EX_ROW_EN[1] = 0x0
5053 00:25:43.325677 LP4Y_EN = 0x0
5054 00:25:43.328372 WORK_FSP = 0x0
5055 00:25:43.328764 WL = 0x3
5056 00:25:43.331393 RL = 0x3
5057 00:25:43.331784 BL = 0x2
5058 00:25:43.335117 RPST = 0x0
5059 00:25:43.338118 RD_PRE = 0x0
5060 00:25:43.338631 WR_PRE = 0x1
5061 00:25:43.341635 WR_PST = 0x0
5062 00:25:43.342069 DBI_WR = 0x0
5063 00:25:43.344956 DBI_RD = 0x0
5064 00:25:43.345346 OTF = 0x1
5065 00:25:43.348430 ===================================
5066 00:25:43.354951 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5067 00:25:43.358656 nWR fixed to 30
5068 00:25:43.361685 [ModeRegInit_LP4] CH0 RK0
5069 00:25:43.362081 [ModeRegInit_LP4] CH0 RK1
5070 00:25:43.364725 [ModeRegInit_LP4] CH1 RK0
5071 00:25:43.368615 [ModeRegInit_LP4] CH1 RK1
5072 00:25:43.368975 match AC timing 9
5073 00:25:43.375464 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5074 00:25:43.378438 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5075 00:25:43.381717 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5076 00:25:43.388364 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5077 00:25:43.391530 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5078 00:25:43.391891 ==
5079 00:25:43.394911 Dram Type= 6, Freq= 0, CH_0, rank 0
5080 00:25:43.397827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5081 00:25:43.398365 ==
5082 00:25:43.405241 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5083 00:25:43.412057 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5084 00:25:43.414735 [CA 0] Center 38 (8~69) winsize 62
5085 00:25:43.418511 [CA 1] Center 38 (7~69) winsize 63
5086 00:25:43.421490 [CA 2] Center 35 (5~66) winsize 62
5087 00:25:43.424862 [CA 3] Center 34 (4~65) winsize 62
5088 00:25:43.428154 [CA 4] Center 34 (4~64) winsize 61
5089 00:25:43.431327 [CA 5] Center 34 (4~64) winsize 61
5090 00:25:43.431686
5091 00:25:43.435475 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5092 00:25:43.435973
5093 00:25:43.438408 [CATrainingPosCal] consider 1 rank data
5094 00:25:43.441732 u2DelayCellTimex100 = 270/100 ps
5095 00:25:43.445206 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5096 00:25:43.448335 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5097 00:25:43.452055 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5098 00:25:43.455265 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5099 00:25:43.458146 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5100 00:25:43.461444 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5101 00:25:43.461841
5102 00:25:43.468101 CA PerBit enable=1, Macro0, CA PI delay=34
5103 00:25:43.468495
5104 00:25:43.471871 [CBTSetCACLKResult] CA Dly = 34
5105 00:25:43.472345 CS Dly: 6 (0~37)
5106 00:25:43.472651 ==
5107 00:25:43.474805 Dram Type= 6, Freq= 0, CH_0, rank 1
5108 00:25:43.478455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 00:25:43.478849 ==
5110 00:25:43.484855 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5111 00:25:43.491708 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5112 00:25:43.495119 [CA 0] Center 38 (7~69) winsize 63
5113 00:25:43.498579 [CA 1] Center 38 (7~69) winsize 63
5114 00:25:43.501514 [CA 2] Center 35 (5~66) winsize 62
5115 00:25:43.504603 [CA 3] Center 35 (4~66) winsize 63
5116 00:25:43.507896 [CA 4] Center 34 (4~65) winsize 62
5117 00:25:43.511488 [CA 5] Center 33 (3~64) winsize 62
5118 00:25:43.511873
5119 00:25:43.515415 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5120 00:25:43.515882
5121 00:25:43.518280 [CATrainingPosCal] consider 2 rank data
5122 00:25:43.521393 u2DelayCellTimex100 = 270/100 ps
5123 00:25:43.525309 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5124 00:25:43.527950 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5125 00:25:43.531689 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5126 00:25:43.534541 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5127 00:25:43.538228 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5128 00:25:43.541623 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5129 00:25:43.542131
5130 00:25:43.547858 CA PerBit enable=1, Macro0, CA PI delay=34
5131 00:25:43.548247
5132 00:25:43.551431 [CBTSetCACLKResult] CA Dly = 34
5133 00:25:43.551853 CS Dly: 7 (0~39)
5134 00:25:43.552364
5135 00:25:43.554755 ----->DramcWriteLeveling(PI) begin...
5136 00:25:43.555165 ==
5137 00:25:43.557882 Dram Type= 6, Freq= 0, CH_0, rank 0
5138 00:25:43.561425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5139 00:25:43.561870 ==
5140 00:25:43.564997 Write leveling (Byte 0): 29 => 29
5141 00:25:43.568001 Write leveling (Byte 1): 28 => 28
5142 00:25:43.572029 DramcWriteLeveling(PI) end<-----
5143 00:25:43.572511
5144 00:25:43.572825 ==
5145 00:25:43.574594 Dram Type= 6, Freq= 0, CH_0, rank 0
5146 00:25:43.581362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5147 00:25:43.581824 ==
5148 00:25:43.582184 [Gating] SW mode calibration
5149 00:25:43.591333 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5150 00:25:43.594558 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5151 00:25:43.598037 0 14 0 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
5152 00:25:43.604686 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5153 00:25:43.608243 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 00:25:43.611616 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 00:25:43.618674 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 00:25:43.621612 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 00:25:43.625404 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5158 00:25:43.631409 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5159 00:25:43.635182 0 15 0 | B1->B0 | 3434 2828 | 0 0 | (0 0) (0 0)
5160 00:25:43.638103 0 15 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5161 00:25:43.645063 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 00:25:43.648505 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 00:25:43.652080 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 00:25:43.658253 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 00:25:43.661449 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 00:25:43.665149 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5167 00:25:43.668408 1 0 0 | B1->B0 | 2f2f 3f3f | 0 0 | (0 0) (1 1)
5168 00:25:43.674974 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5169 00:25:43.678937 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 00:25:43.681941 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 00:25:43.688312 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 00:25:43.691493 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 00:25:43.694772 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 00:25:43.701574 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 00:25:43.704708 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5176 00:25:43.707934 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5177 00:25:43.714675 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 00:25:43.718131 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 00:25:43.721859 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 00:25:43.728431 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 00:25:43.732096 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 00:25:43.735123 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 00:25:43.742140 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 00:25:43.745403 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 00:25:43.748170 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 00:25:43.751689 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 00:25:43.758491 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 00:25:43.761496 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 00:25:43.765290 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 00:25:43.772083 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5191 00:25:43.774946 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5192 00:25:43.778376 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 00:25:43.781759 Total UI for P1: 0, mck2ui 16
5194 00:25:43.785604 best dqsien dly found for B0: ( 1, 2, 30)
5195 00:25:43.788645 Total UI for P1: 0, mck2ui 16
5196 00:25:43.791357 best dqsien dly found for B1: ( 1, 3, 0)
5197 00:25:43.794995 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5198 00:25:43.798346 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5199 00:25:43.798740
5200 00:25:43.805480 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5201 00:25:43.808348 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5202 00:25:43.808823 [Gating] SW calibration Done
5203 00:25:43.811684 ==
5204 00:25:43.814613 Dram Type= 6, Freq= 0, CH_0, rank 0
5205 00:25:43.818265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5206 00:25:43.818737 ==
5207 00:25:43.819045 RX Vref Scan: 0
5208 00:25:43.819327
5209 00:25:43.821770 RX Vref 0 -> 0, step: 1
5210 00:25:43.822205
5211 00:25:43.824706 RX Delay -80 -> 252, step: 8
5212 00:25:43.828523 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5213 00:25:43.831561 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5214 00:25:43.835356 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5215 00:25:43.842073 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5216 00:25:43.845049 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5217 00:25:43.848430 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5218 00:25:43.851431 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5219 00:25:43.854838 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5220 00:25:43.858737 iDelay=200, Bit 8, Center 79 (-8 ~ 167) 176
5221 00:25:43.861531 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5222 00:25:43.868377 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5223 00:25:43.872089 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5224 00:25:43.874950 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5225 00:25:43.878749 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5226 00:25:43.882115 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5227 00:25:43.885457 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5228 00:25:43.888969 ==
5229 00:25:43.891525 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 00:25:43.894992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 00:25:43.895380 ==
5232 00:25:43.895677 DQS Delay:
5233 00:25:43.898688 DQS0 = 0, DQS1 = 0
5234 00:25:43.899071 DQM Delay:
5235 00:25:43.901750 DQM0 = 98, DQM1 = 88
5236 00:25:43.902182 DQ Delay:
5237 00:25:43.905294 DQ0 =95, DQ1 =103, DQ2 =95, DQ3 =95
5238 00:25:43.908544 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5239 00:25:43.911764 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5240 00:25:43.915628 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5241 00:25:43.916127
5242 00:25:43.916432
5243 00:25:43.916704 ==
5244 00:25:43.918736 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 00:25:43.921742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 00:25:43.922276 ==
5247 00:25:43.922590
5248 00:25:43.922864
5249 00:25:43.924991 TX Vref Scan disable
5250 00:25:43.928821 == TX Byte 0 ==
5251 00:25:43.931690 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5252 00:25:43.935242 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5253 00:25:43.938868 == TX Byte 1 ==
5254 00:25:43.941654 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5255 00:25:43.945137 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5256 00:25:43.945602 ==
5257 00:25:43.948776 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 00:25:43.954664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 00:25:43.955054 ==
5260 00:25:43.955425
5261 00:25:43.955703
5262 00:25:43.955965 TX Vref Scan disable
5263 00:25:43.958765 == TX Byte 0 ==
5264 00:25:43.961962 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5265 00:25:43.965712 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5266 00:25:43.968803 == TX Byte 1 ==
5267 00:25:43.972596 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5268 00:25:43.975625 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5269 00:25:43.978989
5270 00:25:43.979457 [DATLAT]
5271 00:25:43.979764 Freq=933, CH0 RK0
5272 00:25:43.980047
5273 00:25:43.982912 DATLAT Default: 0xd
5274 00:25:43.983429 0, 0xFFFF, sum = 0
5275 00:25:43.985822 1, 0xFFFF, sum = 0
5276 00:25:43.986319 2, 0xFFFF, sum = 0
5277 00:25:43.988920 3, 0xFFFF, sum = 0
5278 00:25:43.989390 4, 0xFFFF, sum = 0
5279 00:25:43.992119 5, 0xFFFF, sum = 0
5280 00:25:43.992518 6, 0xFFFF, sum = 0
5281 00:25:43.995462 7, 0xFFFF, sum = 0
5282 00:25:43.995858 8, 0xFFFF, sum = 0
5283 00:25:43.998718 9, 0xFFFF, sum = 0
5284 00:25:43.999117 10, 0x0, sum = 1
5285 00:25:44.002100 11, 0x0, sum = 2
5286 00:25:44.002498 12, 0x0, sum = 3
5287 00:25:44.005630 13, 0x0, sum = 4
5288 00:25:44.006055 best_step = 11
5289 00:25:44.006366
5290 00:25:44.006646 ==
5291 00:25:44.008625 Dram Type= 6, Freq= 0, CH_0, rank 0
5292 00:25:44.015591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 00:25:44.015988 ==
5294 00:25:44.016289 RX Vref Scan: 1
5295 00:25:44.016571
5296 00:25:44.018835 RX Vref 0 -> 0, step: 1
5297 00:25:44.019222
5298 00:25:44.022043 RX Delay -61 -> 252, step: 4
5299 00:25:44.022437
5300 00:25:44.025529 Set Vref, RX VrefLevel [Byte0]: 54
5301 00:25:44.028625 [Byte1]: 51
5302 00:25:44.029017
5303 00:25:44.031945 Final RX Vref Byte 0 = 54 to rank0
5304 00:25:44.035502 Final RX Vref Byte 1 = 51 to rank0
5305 00:25:44.039155 Final RX Vref Byte 0 = 54 to rank1
5306 00:25:44.042418 Final RX Vref Byte 1 = 51 to rank1==
5307 00:25:44.045421 Dram Type= 6, Freq= 0, CH_0, rank 0
5308 00:25:44.048729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5309 00:25:44.049122 ==
5310 00:25:44.052324 DQS Delay:
5311 00:25:44.052712 DQS0 = 0, DQS1 = 0
5312 00:25:44.053017 DQM Delay:
5313 00:25:44.055176 DQM0 = 96, DQM1 = 87
5314 00:25:44.055433 DQ Delay:
5315 00:25:44.058895 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5316 00:25:44.061825 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =102
5317 00:25:44.065527 DQ8 =78, DQ9 =78, DQ10 =86, DQ11 =80
5318 00:25:44.068342 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =96
5319 00:25:44.068505
5320 00:25:44.068628
5321 00:25:44.078737 [DQSOSCAuto] RK0, (LSB)MR18= 0x1904, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 413 ps
5322 00:25:44.081711 CH0 RK0: MR19=505, MR18=1904
5323 00:25:44.085375 CH0_RK0: MR19=0x505, MR18=0x1904, DQSOSC=413, MR23=63, INC=63, DEC=42
5324 00:25:44.085478
5325 00:25:44.088984 ----->DramcWriteLeveling(PI) begin...
5326 00:25:44.091723 ==
5327 00:25:44.091832 Dram Type= 6, Freq= 0, CH_0, rank 1
5328 00:25:44.098366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5329 00:25:44.098506 ==
5330 00:25:44.101909 Write leveling (Byte 0): 31 => 31
5331 00:25:44.105349 Write leveling (Byte 1): 31 => 31
5332 00:25:44.108522 DramcWriteLeveling(PI) end<-----
5333 00:25:44.108692
5334 00:25:44.108781 ==
5335 00:25:44.112008 Dram Type= 6, Freq= 0, CH_0, rank 1
5336 00:25:44.114984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 00:25:44.115077 ==
5338 00:25:44.118796 [Gating] SW mode calibration
5339 00:25:44.125150 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5340 00:25:44.128471 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5341 00:25:44.135151 0 14 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
5342 00:25:44.138462 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5343 00:25:44.141969 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 00:25:44.148556 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 00:25:44.152400 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 00:25:44.155847 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 00:25:44.161810 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5348 00:25:44.165699 0 14 28 | B1->B0 | 3333 2b2b | 0 0 | (0 1) (1 1)
5349 00:25:44.169223 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5350 00:25:44.175831 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 00:25:44.178991 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 00:25:44.182517 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 00:25:44.189221 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 00:25:44.192199 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 00:25:44.195793 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 00:25:44.202624 0 15 28 | B1->B0 | 2828 3333 | 0 1 | (0 0) (0 0)
5357 00:25:44.205528 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
5358 00:25:44.209360 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 00:25:44.215814 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 00:25:44.219325 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 00:25:44.222426 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 00:25:44.225781 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 00:25:44.232305 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5364 00:25:44.235945 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5365 00:25:44.238847 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5366 00:25:44.245509 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 00:25:44.249336 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 00:25:44.252457 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 00:25:44.259154 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 00:25:44.262557 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 00:25:44.265547 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 00:25:44.272117 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 00:25:44.275680 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 00:25:44.279110 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 00:25:44.285716 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 00:25:44.288674 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 00:25:44.292282 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 00:25:44.299010 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 00:25:44.302019 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5380 00:25:44.305731 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5381 00:25:44.308757 Total UI for P1: 0, mck2ui 16
5382 00:25:44.312075 best dqsien dly found for B0: ( 1, 2, 24)
5383 00:25:44.315700 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5384 00:25:44.322618 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5385 00:25:44.325382 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 00:25:44.328565 Total UI for P1: 0, mck2ui 16
5387 00:25:44.332627 best dqsien dly found for B1: ( 1, 3, 0)
5388 00:25:44.335590 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5389 00:25:44.338989 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5390 00:25:44.339584
5391 00:25:44.341922 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5392 00:25:44.345151 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5393 00:25:44.348341 [Gating] SW calibration Done
5394 00:25:44.348657 ==
5395 00:25:44.351861 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 00:25:44.358560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 00:25:44.358781 ==
5398 00:25:44.358981 RX Vref Scan: 0
5399 00:25:44.359174
5400 00:25:44.362105 RX Vref 0 -> 0, step: 1
5401 00:25:44.362304
5402 00:25:44.365049 RX Delay -80 -> 252, step: 8
5403 00:25:44.368448 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5404 00:25:44.372167 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5405 00:25:44.375055 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5406 00:25:44.378546 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5407 00:25:44.381840 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5408 00:25:44.388707 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5409 00:25:44.392373 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5410 00:25:44.395112 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5411 00:25:44.398560 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5412 00:25:44.401611 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5413 00:25:44.405334 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5414 00:25:44.411993 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5415 00:25:44.414989 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5416 00:25:44.418663 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5417 00:25:44.422201 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5418 00:25:44.425321 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5419 00:25:44.425399 ==
5420 00:25:44.429074 Dram Type= 6, Freq= 0, CH_0, rank 1
5421 00:25:44.435351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5422 00:25:44.435445 ==
5423 00:25:44.435507 DQS Delay:
5424 00:25:44.439033 DQS0 = 0, DQS1 = 0
5425 00:25:44.439113 DQM Delay:
5426 00:25:44.439173 DQM0 = 96, DQM1 = 86
5427 00:25:44.441899 DQ Delay:
5428 00:25:44.445508 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5429 00:25:44.448532 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5430 00:25:44.451853 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5431 00:25:44.455298 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =95
5432 00:25:44.455400
5433 00:25:44.455492
5434 00:25:44.455581 ==
5435 00:25:44.458632 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 00:25:44.462063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 00:25:44.462141 ==
5438 00:25:44.462201
5439 00:25:44.462256
5440 00:25:44.465300 TX Vref Scan disable
5441 00:25:44.465408 == TX Byte 0 ==
5442 00:25:44.472106 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5443 00:25:44.475439 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5444 00:25:44.475528 == TX Byte 1 ==
5445 00:25:44.481978 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5446 00:25:44.485482 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5447 00:25:44.485597 ==
5448 00:25:44.488528 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 00:25:44.492009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 00:25:44.492139 ==
5451 00:25:44.492242
5452 00:25:44.492334
5453 00:25:44.495745 TX Vref Scan disable
5454 00:25:44.498890 == TX Byte 0 ==
5455 00:25:44.502428 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5456 00:25:44.505822 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5457 00:25:44.509278 == TX Byte 1 ==
5458 00:25:44.512356 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5459 00:25:44.516001 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5460 00:25:44.516353
5461 00:25:44.518995 [DATLAT]
5462 00:25:44.519350 Freq=933, CH0 RK1
5463 00:25:44.519707
5464 00:25:44.522684 DATLAT Default: 0xb
5465 00:25:44.523038 0, 0xFFFF, sum = 0
5466 00:25:44.525818 1, 0xFFFF, sum = 0
5467 00:25:44.526202 2, 0xFFFF, sum = 0
5468 00:25:44.529577 3, 0xFFFF, sum = 0
5469 00:25:44.529935 4, 0xFFFF, sum = 0
5470 00:25:44.532835 5, 0xFFFF, sum = 0
5471 00:25:44.533290 6, 0xFFFF, sum = 0
5472 00:25:44.536376 7, 0xFFFF, sum = 0
5473 00:25:44.536914 8, 0xFFFF, sum = 0
5474 00:25:44.539588 9, 0xFFFF, sum = 0
5475 00:25:44.539985 10, 0x0, sum = 1
5476 00:25:44.542703 11, 0x0, sum = 2
5477 00:25:44.543095 12, 0x0, sum = 3
5478 00:25:44.546345 13, 0x0, sum = 4
5479 00:25:44.546783 best_step = 11
5480 00:25:44.547062
5481 00:25:44.547343 ==
5482 00:25:44.549335 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 00:25:44.555997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 00:25:44.556383 ==
5485 00:25:44.556688 RX Vref Scan: 0
5486 00:25:44.557148
5487 00:25:44.559377 RX Vref 0 -> 0, step: 1
5488 00:25:44.559761
5489 00:25:44.562290 RX Delay -61 -> 252, step: 4
5490 00:25:44.565978 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5491 00:25:44.569054 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5492 00:25:44.572285 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5493 00:25:44.579004 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5494 00:25:44.582439 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5495 00:25:44.585692 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5496 00:25:44.588961 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5497 00:25:44.592206 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5498 00:25:44.599426 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5499 00:25:44.602540 iDelay=199, Bit 9, Center 76 (-13 ~ 166) 180
5500 00:25:44.605631 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5501 00:25:44.609321 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5502 00:25:44.612269 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5503 00:25:44.615861 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5504 00:25:44.622719 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5505 00:25:44.625978 iDelay=199, Bit 15, Center 96 (11 ~ 182) 172
5506 00:25:44.626507 ==
5507 00:25:44.629739 Dram Type= 6, Freq= 0, CH_0, rank 1
5508 00:25:44.633126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 00:25:44.633608 ==
5510 00:25:44.634039 DQS Delay:
5511 00:25:44.636199 DQS0 = 0, DQS1 = 0
5512 00:25:44.636678 DQM Delay:
5513 00:25:44.638973 DQM0 = 96, DQM1 = 87
5514 00:25:44.639361 DQ Delay:
5515 00:25:44.642694 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5516 00:25:44.645833 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5517 00:25:44.649589 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =80
5518 00:25:44.652757 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =96
5519 00:25:44.653232
5520 00:25:44.653535
5521 00:25:44.662651 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5522 00:25:44.663108 CH0 RK1: MR19=505, MR18=1F0D
5523 00:25:44.669706 CH0_RK1: MR19=0x505, MR18=0x1F0D, DQSOSC=412, MR23=63, INC=63, DEC=42
5524 00:25:44.672749 [RxdqsGatingPostProcess] freq 933
5525 00:25:44.679676 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5526 00:25:44.683236 best DQS0 dly(2T, 0.5T) = (0, 10)
5527 00:25:44.686493 best DQS1 dly(2T, 0.5T) = (0, 11)
5528 00:25:44.689530 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5529 00:25:44.690052 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5530 00:25:44.693146 best DQS0 dly(2T, 0.5T) = (0, 10)
5531 00:25:44.696359 best DQS1 dly(2T, 0.5T) = (0, 11)
5532 00:25:44.699777 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5533 00:25:44.702803 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5534 00:25:44.706378 Pre-setting of DQS Precalculation
5535 00:25:44.712943 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5536 00:25:44.713341 ==
5537 00:25:44.716748 Dram Type= 6, Freq= 0, CH_1, rank 0
5538 00:25:44.719576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5539 00:25:44.719973 ==
5540 00:25:44.726644 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5541 00:25:44.729385 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5542 00:25:44.733868 [CA 0] Center 36 (6~67) winsize 62
5543 00:25:44.736902 [CA 1] Center 36 (6~67) winsize 62
5544 00:25:44.740450 [CA 2] Center 34 (4~64) winsize 61
5545 00:25:44.743509 [CA 3] Center 33 (3~64) winsize 62
5546 00:25:44.747121 [CA 4] Center 33 (3~64) winsize 62
5547 00:25:44.750435 [CA 5] Center 33 (3~63) winsize 61
5548 00:25:44.750844
5549 00:25:44.753325 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5550 00:25:44.753715
5551 00:25:44.756990 [CATrainingPosCal] consider 1 rank data
5552 00:25:44.759824 u2DelayCellTimex100 = 270/100 ps
5553 00:25:44.763430 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5554 00:25:44.766706 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5555 00:25:44.774056 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5556 00:25:44.777083 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5557 00:25:44.780237 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5558 00:25:44.783642 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5559 00:25:44.784034
5560 00:25:44.787266 CA PerBit enable=1, Macro0, CA PI delay=33
5561 00:25:44.787784
5562 00:25:44.790480 [CBTSetCACLKResult] CA Dly = 33
5563 00:25:44.790876 CS Dly: 4 (0~35)
5564 00:25:44.791179 ==
5565 00:25:44.793702 Dram Type= 6, Freq= 0, CH_1, rank 1
5566 00:25:44.799981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 00:25:44.800396 ==
5568 00:25:44.803617 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5569 00:25:44.810464 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5570 00:25:44.813733 [CA 0] Center 36 (6~67) winsize 62
5571 00:25:44.816607 [CA 1] Center 36 (6~67) winsize 62
5572 00:25:44.820296 [CA 2] Center 33 (3~64) winsize 62
5573 00:25:44.823594 [CA 3] Center 33 (3~64) winsize 62
5574 00:25:44.826699 [CA 4] Center 34 (3~65) winsize 63
5575 00:25:44.830563 [CA 5] Center 33 (3~63) winsize 61
5576 00:25:44.831030
5577 00:25:44.833717 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5578 00:25:44.834145
5579 00:25:44.837500 [CATrainingPosCal] consider 2 rank data
5580 00:25:44.840600 u2DelayCellTimex100 = 270/100 ps
5581 00:25:44.843737 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5582 00:25:44.846756 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5583 00:25:44.850539 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5584 00:25:44.857036 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5585 00:25:44.860457 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5586 00:25:44.864063 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5587 00:25:44.864481
5588 00:25:44.866926 CA PerBit enable=1, Macro0, CA PI delay=33
5589 00:25:44.867321
5590 00:25:44.870525 [CBTSetCACLKResult] CA Dly = 33
5591 00:25:44.871043 CS Dly: 5 (0~38)
5592 00:25:44.871522
5593 00:25:44.873839 ----->DramcWriteLeveling(PI) begin...
5594 00:25:44.874369 ==
5595 00:25:44.877277 Dram Type= 6, Freq= 0, CH_1, rank 0
5596 00:25:44.884182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5597 00:25:44.884664 ==
5598 00:25:44.887004 Write leveling (Byte 0): 29 => 29
5599 00:25:44.890526 Write leveling (Byte 1): 29 => 29
5600 00:25:44.890919 DramcWriteLeveling(PI) end<-----
5601 00:25:44.893903
5602 00:25:44.894309 ==
5603 00:25:44.897250 Dram Type= 6, Freq= 0, CH_1, rank 0
5604 00:25:44.900680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5605 00:25:44.901170 ==
5606 00:25:44.903979 [Gating] SW mode calibration
5607 00:25:44.910594 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5608 00:25:44.913684 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5609 00:25:44.920876 0 14 0 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
5610 00:25:44.924119 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 00:25:44.927053 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 00:25:44.934144 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 00:25:44.937298 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 00:25:44.940914 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 00:25:44.947540 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 00:25:44.950879 0 14 28 | B1->B0 | 3131 3131 | 1 1 | (1 0) (1 0)
5617 00:25:44.953718 0 15 0 | B1->B0 | 2828 2626 | 0 0 | (1 1) (0 0)
5618 00:25:44.961095 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 00:25:44.964221 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 00:25:44.966952 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 00:25:44.974058 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 00:25:44.977346 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 00:25:44.980788 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 00:25:44.984132 0 15 28 | B1->B0 | 2b2b 2a2a | 0 0 | (0 0) (0 0)
5625 00:25:44.990497 1 0 0 | B1->B0 | 4545 4141 | 0 0 | (0 0) (0 0)
5626 00:25:44.993951 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 00:25:44.996974 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 00:25:45.003971 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 00:25:45.007212 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 00:25:45.010817 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 00:25:45.017186 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5632 00:25:45.021223 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5633 00:25:45.024099 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5634 00:25:45.030717 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 00:25:45.033821 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 00:25:45.037506 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 00:25:45.043962 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 00:25:45.047012 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 00:25:45.050933 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 00:25:45.057464 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 00:25:45.060486 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 00:25:45.063916 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 00:25:45.067378 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 00:25:45.074011 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 00:25:45.077702 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 00:25:45.080580 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 00:25:45.087361 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5648 00:25:45.091164 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5649 00:25:45.094246 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5650 00:25:45.096961 Total UI for P1: 0, mck2ui 16
5651 00:25:45.100909 best dqsien dly found for B0: ( 1, 2, 28)
5652 00:25:45.107392 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 00:25:45.107851 Total UI for P1: 0, mck2ui 16
5654 00:25:45.113453 best dqsien dly found for B1: ( 1, 2, 28)
5655 00:25:45.117393 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5656 00:25:45.120618 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5657 00:25:45.121015
5658 00:25:45.123504 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5659 00:25:45.127044 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5660 00:25:45.130078 [Gating] SW calibration Done
5661 00:25:45.130468 ==
5662 00:25:45.133605 Dram Type= 6, Freq= 0, CH_1, rank 0
5663 00:25:45.136985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5664 00:25:45.137375 ==
5665 00:25:45.140627 RX Vref Scan: 0
5666 00:25:45.141013
5667 00:25:45.141316 RX Vref 0 -> 0, step: 1
5668 00:25:45.141595
5669 00:25:45.143602 RX Delay -80 -> 252, step: 8
5670 00:25:45.146906 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5671 00:25:45.153444 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5672 00:25:45.156522 iDelay=208, Bit 2, Center 79 (-16 ~ 175) 192
5673 00:25:45.159930 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5674 00:25:45.163695 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5675 00:25:45.166553 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5676 00:25:45.170203 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5677 00:25:45.176863 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5678 00:25:45.180189 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5679 00:25:45.183830 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5680 00:25:45.186740 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5681 00:25:45.190266 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5682 00:25:45.193777 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5683 00:25:45.200004 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5684 00:25:45.203488 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5685 00:25:45.207115 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5686 00:25:45.207240 ==
5687 00:25:45.210195 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 00:25:45.213900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 00:25:45.213999 ==
5690 00:25:45.216627 DQS Delay:
5691 00:25:45.216702 DQS0 = 0, DQS1 = 0
5692 00:25:45.216761 DQM Delay:
5693 00:25:45.219999 DQM0 = 95, DQM1 = 89
5694 00:25:45.220074 DQ Delay:
5695 00:25:45.223229 DQ0 =99, DQ1 =91, DQ2 =79, DQ3 =95
5696 00:25:45.227237 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5697 00:25:45.229961 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5698 00:25:45.233977 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5699 00:25:45.234307
5700 00:25:45.234535
5701 00:25:45.234744 ==
5702 00:25:45.237012 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 00:25:45.243972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 00:25:45.244220 ==
5705 00:25:45.244371
5706 00:25:45.244507
5707 00:25:45.244638 TX Vref Scan disable
5708 00:25:45.247375 == TX Byte 0 ==
5709 00:25:45.250902 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5710 00:25:45.254255 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5711 00:25:45.258031 == TX Byte 1 ==
5712 00:25:45.261039 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5713 00:25:45.264188 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5714 00:25:45.267702 ==
5715 00:25:45.270997 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 00:25:45.274325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 00:25:45.274731 ==
5718 00:25:45.275032
5719 00:25:45.275303
5720 00:25:45.277836 TX Vref Scan disable
5721 00:25:45.278296 == TX Byte 0 ==
5722 00:25:45.284416 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5723 00:25:45.288042 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5724 00:25:45.288628 == TX Byte 1 ==
5725 00:25:45.294531 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5726 00:25:45.297758 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5727 00:25:45.298276
5728 00:25:45.298603 [DATLAT]
5729 00:25:45.301273 Freq=933, CH1 RK0
5730 00:25:45.301739
5731 00:25:45.302090 DATLAT Default: 0xd
5732 00:25:45.304451 0, 0xFFFF, sum = 0
5733 00:25:45.304935 1, 0xFFFF, sum = 0
5734 00:25:45.308091 2, 0xFFFF, sum = 0
5735 00:25:45.308576 3, 0xFFFF, sum = 0
5736 00:25:45.310820 4, 0xFFFF, sum = 0
5737 00:25:45.311239 5, 0xFFFF, sum = 0
5738 00:25:45.314553 6, 0xFFFF, sum = 0
5739 00:25:45.315041 7, 0xFFFF, sum = 0
5740 00:25:45.317725 8, 0xFFFF, sum = 0
5741 00:25:45.318246 9, 0xFFFF, sum = 0
5742 00:25:45.321307 10, 0x0, sum = 1
5743 00:25:45.321784 11, 0x0, sum = 2
5744 00:25:45.324824 12, 0x0, sum = 3
5745 00:25:45.325305 13, 0x0, sum = 4
5746 00:25:45.327443 best_step = 11
5747 00:25:45.327829
5748 00:25:45.328126 ==
5749 00:25:45.331258 Dram Type= 6, Freq= 0, CH_1, rank 0
5750 00:25:45.334314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 00:25:45.334721 ==
5752 00:25:45.337711 RX Vref Scan: 1
5753 00:25:45.338140
5754 00:25:45.338543 RX Vref 0 -> 0, step: 1
5755 00:25:45.338917
5756 00:25:45.341365 RX Delay -61 -> 252, step: 4
5757 00:25:45.341763
5758 00:25:45.344594 Set Vref, RX VrefLevel [Byte0]: 61
5759 00:25:45.348125 [Byte1]: 53
5760 00:25:45.351832
5761 00:25:45.352313 Final RX Vref Byte 0 = 61 to rank0
5762 00:25:45.354585 Final RX Vref Byte 1 = 53 to rank0
5763 00:25:45.358875 Final RX Vref Byte 0 = 61 to rank1
5764 00:25:45.361383 Final RX Vref Byte 1 = 53 to rank1==
5765 00:25:45.365244 Dram Type= 6, Freq= 0, CH_1, rank 0
5766 00:25:45.371554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 00:25:45.372031 ==
5768 00:25:45.372428 DQS Delay:
5769 00:25:45.372802 DQS0 = 0, DQS1 = 0
5770 00:25:45.374898 DQM Delay:
5771 00:25:45.375294 DQM0 = 97, DQM1 = 91
5772 00:25:45.378475 DQ Delay:
5773 00:25:45.381915 DQ0 =102, DQ1 =92, DQ2 =88, DQ3 =94
5774 00:25:45.385253 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =94
5775 00:25:45.388281 DQ8 =80, DQ9 =76, DQ10 =92, DQ11 =88
5776 00:25:45.392302 DQ12 =98, DQ13 =100, DQ14 =98, DQ15 =96
5777 00:25:45.392802
5778 00:25:45.393196
5779 00:25:45.398105 [DQSOSCAuto] RK0, (LSB)MR18= 0x17f4, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 414 ps
5780 00:25:45.401579 CH1 RK0: MR19=504, MR18=17F4
5781 00:25:45.408436 CH1_RK0: MR19=0x504, MR18=0x17F4, DQSOSC=414, MR23=63, INC=63, DEC=42
5782 00:25:45.408831
5783 00:25:45.411513 ----->DramcWriteLeveling(PI) begin...
5784 00:25:45.411906 ==
5785 00:25:45.414526 Dram Type= 6, Freq= 0, CH_1, rank 1
5786 00:25:45.418565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5787 00:25:45.419043 ==
5788 00:25:45.422090 Write leveling (Byte 0): 28 => 28
5789 00:25:45.425114 Write leveling (Byte 1): 28 => 28
5790 00:25:45.428459 DramcWriteLeveling(PI) end<-----
5791 00:25:45.428849
5792 00:25:45.429145 ==
5793 00:25:45.431438 Dram Type= 6, Freq= 0, CH_1, rank 1
5794 00:25:45.435161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5795 00:25:45.435644 ==
5796 00:25:45.437974 [Gating] SW mode calibration
5797 00:25:45.444917 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5798 00:25:45.451276 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5799 00:25:45.454876 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 00:25:45.457804 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 00:25:45.464500 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 00:25:45.467986 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 00:25:45.471003 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 00:25:45.478407 0 14 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5805 00:25:45.481217 0 14 24 | B1->B0 | 3232 2a2a | 0 1 | (0 1) (1 0)
5806 00:25:45.484710 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5807 00:25:45.491285 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 00:25:45.494100 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 00:25:45.497464 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 00:25:45.504163 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 00:25:45.507572 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 00:25:45.510916 0 15 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5813 00:25:45.517386 0 15 24 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
5814 00:25:45.520660 0 15 28 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
5815 00:25:45.524180 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 00:25:45.530870 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 00:25:45.533937 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 00:25:45.537527 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 00:25:45.544349 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 00:25:45.547296 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5821 00:25:45.550868 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5822 00:25:45.557724 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 00:25:45.561077 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5824 00:25:45.564013 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 00:25:45.567507 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 00:25:45.574241 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 00:25:45.577524 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 00:25:45.581449 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 00:25:45.587655 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 00:25:45.591364 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 00:25:45.594871 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 00:25:45.601060 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 00:25:45.604519 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 00:25:45.608369 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 00:25:45.614943 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 00:25:45.618174 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 00:25:45.621569 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5838 00:25:45.624630 Total UI for P1: 0, mck2ui 16
5839 00:25:45.628235 best dqsien dly found for B0: ( 1, 2, 22)
5840 00:25:45.631004 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 00:25:45.634659 Total UI for P1: 0, mck2ui 16
5842 00:25:45.637714 best dqsien dly found for B1: ( 1, 2, 24)
5843 00:25:45.641448 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5844 00:25:45.647987 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5845 00:25:45.648399
5846 00:25:45.651656 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5847 00:25:45.654741 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5848 00:25:45.658152 [Gating] SW calibration Done
5849 00:25:45.658509 ==
5850 00:25:45.661607 Dram Type= 6, Freq= 0, CH_1, rank 1
5851 00:25:45.664848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5852 00:25:45.665433 ==
5853 00:25:45.665957 RX Vref Scan: 0
5854 00:25:45.668287
5855 00:25:45.668889 RX Vref 0 -> 0, step: 1
5856 00:25:45.669239
5857 00:25:45.671449 RX Delay -80 -> 252, step: 8
5858 00:25:45.674725 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5859 00:25:45.678413 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5860 00:25:45.685120 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5861 00:25:45.688338 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5862 00:25:45.691352 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5863 00:25:45.694901 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5864 00:25:45.697852 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5865 00:25:45.701554 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5866 00:25:45.705181 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5867 00:25:45.711645 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5868 00:25:45.714817 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5869 00:25:45.718346 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5870 00:25:45.721532 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5871 00:25:45.725148 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5872 00:25:45.728126 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5873 00:25:45.735191 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5874 00:25:45.735562 ==
5875 00:25:45.738085 Dram Type= 6, Freq= 0, CH_1, rank 1
5876 00:25:45.741664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5877 00:25:45.742117 ==
5878 00:25:45.742517 DQS Delay:
5879 00:25:45.744827 DQS0 = 0, DQS1 = 0
5880 00:25:45.745226 DQM Delay:
5881 00:25:45.748169 DQM0 = 95, DQM1 = 90
5882 00:25:45.748666 DQ Delay:
5883 00:25:45.751916 DQ0 =99, DQ1 =87, DQ2 =87, DQ3 =95
5884 00:25:45.754896 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5885 00:25:45.758497 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5886 00:25:45.761494 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5887 00:25:45.761861
5888 00:25:45.762233
5889 00:25:45.762573 ==
5890 00:25:45.765021 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 00:25:45.768365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 00:25:45.768734 ==
5893 00:25:45.771356
5894 00:25:45.771757
5895 00:25:45.772124 TX Vref Scan disable
5896 00:25:45.775155 == TX Byte 0 ==
5897 00:25:45.778264 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5898 00:25:45.781396 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5899 00:25:45.785056 == TX Byte 1 ==
5900 00:25:45.788244 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5901 00:25:45.791789 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5902 00:25:45.792242 ==
5903 00:25:45.795197 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 00:25:45.801737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 00:25:45.802156 ==
5906 00:25:45.802520
5907 00:25:45.802859
5908 00:25:45.803191 TX Vref Scan disable
5909 00:25:45.806152 == TX Byte 0 ==
5910 00:25:45.809264 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5911 00:25:45.812404 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5912 00:25:45.815322 == TX Byte 1 ==
5913 00:25:45.819036 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5914 00:25:45.825543 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5915 00:25:45.825904
5916 00:25:45.826207 [DATLAT]
5917 00:25:45.826468 Freq=933, CH1 RK1
5918 00:25:45.826714
5919 00:25:45.828609 DATLAT Default: 0xb
5920 00:25:45.828970 0, 0xFFFF, sum = 0
5921 00:25:45.832217 1, 0xFFFF, sum = 0
5922 00:25:45.832477 2, 0xFFFF, sum = 0
5923 00:25:45.835197 3, 0xFFFF, sum = 0
5924 00:25:45.835463 4, 0xFFFF, sum = 0
5925 00:25:45.838815 5, 0xFFFF, sum = 0
5926 00:25:45.839013 6, 0xFFFF, sum = 0
5927 00:25:45.841769 7, 0xFFFF, sum = 0
5928 00:25:45.845596 8, 0xFFFF, sum = 0
5929 00:25:45.845760 9, 0xFFFF, sum = 0
5930 00:25:45.848940 10, 0x0, sum = 1
5931 00:25:45.849078 11, 0x0, sum = 2
5932 00:25:45.849186 12, 0x0, sum = 3
5933 00:25:45.851839 13, 0x0, sum = 4
5934 00:25:45.851958 best_step = 11
5935 00:25:45.852050
5936 00:25:45.852134 ==
5937 00:25:45.855405 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 00:25:45.862435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 00:25:45.862529 ==
5940 00:25:45.862601 RX Vref Scan: 0
5941 00:25:45.862668
5942 00:25:45.865248 RX Vref 0 -> 0, step: 1
5943 00:25:45.865340
5944 00:25:45.868472 RX Delay -61 -> 252, step: 4
5945 00:25:45.872328 iDelay=195, Bit 0, Center 98 (7 ~ 190) 184
5946 00:25:45.875232 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5947 00:25:45.881794 iDelay=195, Bit 2, Center 82 (-9 ~ 174) 184
5948 00:25:45.885147 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5949 00:25:45.888254 iDelay=195, Bit 4, Center 96 (7 ~ 186) 180
5950 00:25:45.891860 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5951 00:25:45.895297 iDelay=195, Bit 6, Center 104 (15 ~ 194) 180
5952 00:25:45.898844 iDelay=195, Bit 7, Center 90 (3 ~ 178) 176
5953 00:25:45.905567 iDelay=195, Bit 8, Center 80 (-13 ~ 174) 188
5954 00:25:45.908740 iDelay=195, Bit 9, Center 78 (-13 ~ 170) 184
5955 00:25:45.912440 iDelay=195, Bit 10, Center 92 (-1 ~ 186) 188
5956 00:25:45.915978 iDelay=195, Bit 11, Center 82 (-9 ~ 174) 184
5957 00:25:45.918939 iDelay=195, Bit 12, Center 96 (7 ~ 186) 180
5958 00:25:45.922291 iDelay=195, Bit 13, Center 96 (3 ~ 190) 188
5959 00:25:45.929387 iDelay=195, Bit 14, Center 100 (11 ~ 190) 180
5960 00:25:45.932342 iDelay=195, Bit 15, Center 98 (7 ~ 190) 184
5961 00:25:45.932488 ==
5962 00:25:45.935806 Dram Type= 6, Freq= 0, CH_1, rank 1
5963 00:25:45.939007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5964 00:25:45.939156 ==
5965 00:25:45.942403 DQS Delay:
5966 00:25:45.942550 DQS0 = 0, DQS1 = 0
5967 00:25:45.942622 DQM Delay:
5968 00:25:45.945749 DQM0 = 94, DQM1 = 90
5969 00:25:45.945901 DQ Delay:
5970 00:25:45.949163 DQ0 =98, DQ1 =90, DQ2 =82, DQ3 =94
5971 00:25:45.952530 DQ4 =96, DQ5 =104, DQ6 =104, DQ7 =90
5972 00:25:45.955985 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =82
5973 00:25:45.958982 DQ12 =96, DQ13 =96, DQ14 =100, DQ15 =98
5974 00:25:45.959151
5975 00:25:45.959240
5976 00:25:45.969106 [DQSOSCAuto] RK1, (LSB)MR18= 0xe17, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5977 00:25:45.969267 CH1 RK1: MR19=505, MR18=E17
5978 00:25:45.979937 CH1_RK1: MR19=0x505, MR18=0xE17, DQSOSC=414, MR23=63, INC=63, DEC=42
5979 00:25:45.980167 [RxdqsGatingPostProcess] freq 933
5980 00:25:45.985871 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5981 00:25:45.989817 best DQS0 dly(2T, 0.5T) = (0, 10)
5982 00:25:45.992595 best DQS1 dly(2T, 0.5T) = (0, 10)
5983 00:25:45.995811 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5984 00:25:45.999006 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5985 00:25:45.999473 best DQS0 dly(2T, 0.5T) = (0, 10)
5986 00:25:46.002488 best DQS1 dly(2T, 0.5T) = (0, 10)
5987 00:25:46.005765 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5988 00:25:46.009396 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5989 00:25:46.012473 Pre-setting of DQS Precalculation
5990 00:25:46.019602 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5991 00:25:46.026050 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5992 00:25:46.033249 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5993 00:25:46.033728
5994 00:25:46.034095
5995 00:25:46.036002 [Calibration Summary] 1866 Mbps
5996 00:25:46.036397 CH 0, Rank 0
5997 00:25:46.040028 SW Impedance : PASS
5998 00:25:46.042927 DUTY Scan : NO K
5999 00:25:46.043394 ZQ Calibration : PASS
6000 00:25:46.046535 Jitter Meter : NO K
6001 00:25:46.049349 CBT Training : PASS
6002 00:25:46.049817 Write leveling : PASS
6003 00:25:46.052997 RX DQS gating : PASS
6004 00:25:46.055724 RX DQ/DQS(RDDQC) : PASS
6005 00:25:46.056332 TX DQ/DQS : PASS
6006 00:25:46.059123 RX DATLAT : PASS
6007 00:25:46.062552 RX DQ/DQS(Engine): PASS
6008 00:25:46.063009 TX OE : NO K
6009 00:25:46.063448 All Pass.
6010 00:25:46.063890
6011 00:25:46.066204 CH 0, Rank 1
6012 00:25:46.066653 SW Impedance : PASS
6013 00:25:46.069239 DUTY Scan : NO K
6014 00:25:46.072631 ZQ Calibration : PASS
6015 00:25:46.073094 Jitter Meter : NO K
6016 00:25:46.076029 CBT Training : PASS
6017 00:25:46.079012 Write leveling : PASS
6018 00:25:46.079468 RX DQS gating : PASS
6019 00:25:46.082572 RX DQ/DQS(RDDQC) : PASS
6020 00:25:46.085465 TX DQ/DQS : PASS
6021 00:25:46.085788 RX DATLAT : PASS
6022 00:25:46.089080 RX DQ/DQS(Engine): PASS
6023 00:25:46.092408 TX OE : NO K
6024 00:25:46.092616 All Pass.
6025 00:25:46.092788
6026 00:25:46.092908 CH 1, Rank 0
6027 00:25:46.095327 SW Impedance : PASS
6028 00:25:46.098793 DUTY Scan : NO K
6029 00:25:46.098958 ZQ Calibration : PASS
6030 00:25:46.102307 Jitter Meter : NO K
6031 00:25:46.105779 CBT Training : PASS
6032 00:25:46.105937 Write leveling : PASS
6033 00:25:46.109039 RX DQS gating : PASS
6034 00:25:46.109165 RX DQ/DQS(RDDQC) : PASS
6035 00:25:46.112057 TX DQ/DQS : PASS
6036 00:25:46.115229 RX DATLAT : PASS
6037 00:25:46.115349 RX DQ/DQS(Engine): PASS
6038 00:25:46.118769 TX OE : NO K
6039 00:25:46.118870 All Pass.
6040 00:25:46.118961
6041 00:25:46.122412 CH 1, Rank 1
6042 00:25:46.122517 SW Impedance : PASS
6043 00:25:46.125759 DUTY Scan : NO K
6044 00:25:46.128967 ZQ Calibration : PASS
6045 00:25:46.129045 Jitter Meter : NO K
6046 00:25:46.132037 CBT Training : PASS
6047 00:25:46.135329 Write leveling : PASS
6048 00:25:46.135407 RX DQS gating : PASS
6049 00:25:46.138604 RX DQ/DQS(RDDQC) : PASS
6050 00:25:46.141972 TX DQ/DQS : PASS
6051 00:25:46.142092 RX DATLAT : PASS
6052 00:25:46.145292 RX DQ/DQS(Engine): PASS
6053 00:25:46.148600 TX OE : NO K
6054 00:25:46.148678 All Pass.
6055 00:25:46.148737
6056 00:25:46.148792 DramC Write-DBI off
6057 00:25:46.152247 PER_BANK_REFRESH: Hybrid Mode
6058 00:25:46.155573 TX_TRACKING: ON
6059 00:25:46.161994 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6060 00:25:46.165489 [FAST_K] Save calibration result to emmc
6061 00:25:46.172052 dramc_set_vcore_voltage set vcore to 650000
6062 00:25:46.172133 Read voltage for 400, 6
6063 00:25:46.172193 Vio18 = 0
6064 00:25:46.175686 Vcore = 650000
6065 00:25:46.175763 Vdram = 0
6066 00:25:46.175822 Vddq = 0
6067 00:25:46.179017 Vmddr = 0
6068 00:25:46.182680 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6069 00:25:46.189144 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6070 00:25:46.189223 MEM_TYPE=3, freq_sel=20
6071 00:25:46.192127 sv_algorithm_assistance_LP4_800
6072 00:25:46.199422 ============ PULL DRAM RESETB DOWN ============
6073 00:25:46.202301 ========== PULL DRAM RESETB DOWN end =========
6074 00:25:46.205402 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6075 00:25:46.208885 ===================================
6076 00:25:46.212382 LPDDR4 DRAM CONFIGURATION
6077 00:25:46.215288 ===================================
6078 00:25:46.219132 EX_ROW_EN[0] = 0x0
6079 00:25:46.219208 EX_ROW_EN[1] = 0x0
6080 00:25:46.222379 LP4Y_EN = 0x0
6081 00:25:46.222455 WORK_FSP = 0x0
6082 00:25:46.225516 WL = 0x2
6083 00:25:46.225593 RL = 0x2
6084 00:25:46.228746 BL = 0x2
6085 00:25:46.228823 RPST = 0x0
6086 00:25:46.232167 RD_PRE = 0x0
6087 00:25:46.232244 WR_PRE = 0x1
6088 00:25:46.235854 WR_PST = 0x0
6089 00:25:46.235931 DBI_WR = 0x0
6090 00:25:46.238845 DBI_RD = 0x0
6091 00:25:46.238922 OTF = 0x1
6092 00:25:46.242255 ===================================
6093 00:25:46.245238 ===================================
6094 00:25:46.248644 ANA top config
6095 00:25:46.251817 ===================================
6096 00:25:46.251894 DLL_ASYNC_EN = 0
6097 00:25:46.255287 ALL_SLAVE_EN = 1
6098 00:25:46.259117 NEW_RANK_MODE = 1
6099 00:25:46.261965 DLL_IDLE_MODE = 1
6100 00:25:46.265319 LP45_APHY_COMB_EN = 1
6101 00:25:46.265397 TX_ODT_DIS = 1
6102 00:25:46.268732 NEW_8X_MODE = 1
6103 00:25:46.271886 ===================================
6104 00:25:46.275342 ===================================
6105 00:25:46.278648 data_rate = 800
6106 00:25:46.282100 CKR = 1
6107 00:25:46.285125 DQ_P2S_RATIO = 4
6108 00:25:46.288898 ===================================
6109 00:25:46.288978 CA_P2S_RATIO = 4
6110 00:25:46.292272 DQ_CA_OPEN = 0
6111 00:25:46.295231 DQ_SEMI_OPEN = 1
6112 00:25:46.298959 CA_SEMI_OPEN = 1
6113 00:25:46.301942 CA_FULL_RATE = 0
6114 00:25:46.305489 DQ_CKDIV4_EN = 0
6115 00:25:46.305566 CA_CKDIV4_EN = 1
6116 00:25:46.308594 CA_PREDIV_EN = 0
6117 00:25:46.312255 PH8_DLY = 0
6118 00:25:46.315865 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6119 00:25:46.318951 DQ_AAMCK_DIV = 0
6120 00:25:46.321941 CA_AAMCK_DIV = 0
6121 00:25:46.322055 CA_ADMCK_DIV = 4
6122 00:25:46.325579 DQ_TRACK_CA_EN = 0
6123 00:25:46.328957 CA_PICK = 800
6124 00:25:46.332498 CA_MCKIO = 400
6125 00:25:46.335418 MCKIO_SEMI = 400
6126 00:25:46.338983 PLL_FREQ = 3016
6127 00:25:46.342219 DQ_UI_PI_RATIO = 32
6128 00:25:46.342309 CA_UI_PI_RATIO = 32
6129 00:25:46.345371 ===================================
6130 00:25:46.348672 ===================================
6131 00:25:46.352207 memory_type:LPDDR4
6132 00:25:46.355765 GP_NUM : 10
6133 00:25:46.355843 SRAM_EN : 1
6134 00:25:46.358560 MD32_EN : 0
6135 00:25:46.362292 ===================================
6136 00:25:46.365694 [ANA_INIT] >>>>>>>>>>>>>>
6137 00:25:46.368753 <<<<<< [CONFIGURE PHASE]: ANA_TX
6138 00:25:46.372297 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6139 00:25:46.375523 ===================================
6140 00:25:46.375600 data_rate = 800,PCW = 0X7400
6141 00:25:46.378591 ===================================
6142 00:25:46.382159 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6143 00:25:46.389059 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6144 00:25:46.398806 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6145 00:25:46.405861 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6146 00:25:46.408751 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6147 00:25:46.412312 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6148 00:25:46.415235 [ANA_INIT] flow start
6149 00:25:46.415312 [ANA_INIT] PLL >>>>>>>>
6150 00:25:46.418754 [ANA_INIT] PLL <<<<<<<<
6151 00:25:46.422337 [ANA_INIT] MIDPI >>>>>>>>
6152 00:25:46.422414 [ANA_INIT] MIDPI <<<<<<<<
6153 00:25:46.425358 [ANA_INIT] DLL >>>>>>>>
6154 00:25:46.428895 [ANA_INIT] flow end
6155 00:25:46.431915 ============ LP4 DIFF to SE enter ============
6156 00:25:46.435437 ============ LP4 DIFF to SE exit ============
6157 00:25:46.439120 [ANA_INIT] <<<<<<<<<<<<<
6158 00:25:46.442020 [Flow] Enable top DCM control >>>>>
6159 00:25:46.445651 [Flow] Enable top DCM control <<<<<
6160 00:25:46.449164 Enable DLL master slave shuffle
6161 00:25:46.452069 ==============================================================
6162 00:25:46.455605 Gating Mode config
6163 00:25:46.458792 ==============================================================
6164 00:25:46.462014 Config description:
6165 00:25:46.471913 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6166 00:25:46.479082 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6167 00:25:46.482051 SELPH_MODE 0: By rank 1: By Phase
6168 00:25:46.489031 ==============================================================
6169 00:25:46.492505 GAT_TRACK_EN = 0
6170 00:25:46.496008 RX_GATING_MODE = 2
6171 00:25:46.499286 RX_GATING_TRACK_MODE = 2
6172 00:25:46.502535 SELPH_MODE = 1
6173 00:25:46.502627 PICG_EARLY_EN = 1
6174 00:25:46.505695 VALID_LAT_VALUE = 1
6175 00:25:46.512177 ==============================================================
6176 00:25:46.516017 Enter into Gating configuration >>>>
6177 00:25:46.519020 Exit from Gating configuration <<<<
6178 00:25:46.522442 Enter into DVFS_PRE_config >>>>>
6179 00:25:46.532579 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6180 00:25:46.535731 Exit from DVFS_PRE_config <<<<<
6181 00:25:46.539234 Enter into PICG configuration >>>>
6182 00:25:46.542177 Exit from PICG configuration <<<<
6183 00:25:46.545785 [RX_INPUT] configuration >>>>>
6184 00:25:46.549248 [RX_INPUT] configuration <<<<<
6185 00:25:46.552260 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6186 00:25:46.559208 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6187 00:25:46.565841 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6188 00:25:46.572201 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6189 00:25:46.575421 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6190 00:25:46.582647 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6191 00:25:46.585530 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6192 00:25:46.592519 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6193 00:25:46.596098 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6194 00:25:46.598936 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6195 00:25:46.602560 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6196 00:25:46.608826 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6197 00:25:46.612371 ===================================
6198 00:25:46.612450 LPDDR4 DRAM CONFIGURATION
6199 00:25:46.615964 ===================================
6200 00:25:46.619000 EX_ROW_EN[0] = 0x0
6201 00:25:46.622713 EX_ROW_EN[1] = 0x0
6202 00:25:46.622788 LP4Y_EN = 0x0
6203 00:25:46.625632 WORK_FSP = 0x0
6204 00:25:46.625708 WL = 0x2
6205 00:25:46.629114 RL = 0x2
6206 00:25:46.629190 BL = 0x2
6207 00:25:46.632132 RPST = 0x0
6208 00:25:46.632208 RD_PRE = 0x0
6209 00:25:46.635602 WR_PRE = 0x1
6210 00:25:46.635679 WR_PST = 0x0
6211 00:25:46.638945 DBI_WR = 0x0
6212 00:25:46.639022 DBI_RD = 0x0
6213 00:25:46.642538 OTF = 0x1
6214 00:25:46.646037 ===================================
6215 00:25:46.649027 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6216 00:25:46.652560 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6217 00:25:46.659067 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6218 00:25:46.662440 ===================================
6219 00:25:46.662517 LPDDR4 DRAM CONFIGURATION
6220 00:25:46.665886 ===================================
6221 00:25:46.668918 EX_ROW_EN[0] = 0x10
6222 00:25:46.672474 EX_ROW_EN[1] = 0x0
6223 00:25:46.672550 LP4Y_EN = 0x0
6224 00:25:46.676010 WORK_FSP = 0x0
6225 00:25:46.676087 WL = 0x2
6226 00:25:46.679003 RL = 0x2
6227 00:25:46.679080 BL = 0x2
6228 00:25:46.682489 RPST = 0x0
6229 00:25:46.682565 RD_PRE = 0x0
6230 00:25:46.687034 WR_PRE = 0x1
6231 00:25:46.687112 WR_PST = 0x0
6232 00:25:46.689123 DBI_WR = 0x0
6233 00:25:46.689199 DBI_RD = 0x0
6234 00:25:46.692345 OTF = 0x1
6235 00:25:46.695895 ===================================
6236 00:25:46.699113 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6237 00:25:46.704911 nWR fixed to 30
6238 00:25:46.708369 [ModeRegInit_LP4] CH0 RK0
6239 00:25:46.708447 [ModeRegInit_LP4] CH0 RK1
6240 00:25:46.711381 [ModeRegInit_LP4] CH1 RK0
6241 00:25:46.715038 [ModeRegInit_LP4] CH1 RK1
6242 00:25:46.715115 match AC timing 19
6243 00:25:46.721621 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6244 00:25:46.725288 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6245 00:25:46.728092 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6246 00:25:46.734691 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6247 00:25:46.738209 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6248 00:25:46.738310 ==
6249 00:25:46.741473 Dram Type= 6, Freq= 0, CH_0, rank 0
6250 00:25:46.744564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6251 00:25:46.744645 ==
6252 00:25:46.751444 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6253 00:25:46.758292 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6254 00:25:46.761397 [CA 0] Center 36 (8~64) winsize 57
6255 00:25:46.765180 [CA 1] Center 36 (8~64) winsize 57
6256 00:25:46.765257 [CA 2] Center 36 (8~64) winsize 57
6257 00:25:46.768474 [CA 3] Center 36 (8~64) winsize 57
6258 00:25:46.771515 [CA 4] Center 36 (8~64) winsize 57
6259 00:25:46.775084 [CA 5] Center 36 (8~64) winsize 57
6260 00:25:46.775161
6261 00:25:46.778141 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6262 00:25:46.778218
6263 00:25:46.785213 [CATrainingPosCal] consider 1 rank data
6264 00:25:46.785292 u2DelayCellTimex100 = 270/100 ps
6265 00:25:46.791595 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 00:25:46.794918 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 00:25:46.798239 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 00:25:46.801210 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 00:25:46.804735 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 00:25:46.808101 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 00:25:46.808182
6272 00:25:46.811416 CA PerBit enable=1, Macro0, CA PI delay=36
6273 00:25:46.811502
6274 00:25:46.814712 [CBTSetCACLKResult] CA Dly = 36
6275 00:25:46.817715 CS Dly: 1 (0~32)
6276 00:25:46.817809 ==
6277 00:25:46.821661 Dram Type= 6, Freq= 0, CH_0, rank 1
6278 00:25:46.825146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 00:25:46.825224 ==
6280 00:25:46.828056 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6281 00:25:46.834493 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6282 00:25:46.838276 [CA 0] Center 36 (8~64) winsize 57
6283 00:25:46.841879 [CA 1] Center 36 (8~64) winsize 57
6284 00:25:46.844684 [CA 2] Center 36 (8~64) winsize 57
6285 00:25:46.848219 [CA 3] Center 36 (8~64) winsize 57
6286 00:25:46.851256 [CA 4] Center 36 (8~64) winsize 57
6287 00:25:46.854846 [CA 5] Center 36 (8~64) winsize 57
6288 00:25:46.854922
6289 00:25:46.858292 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6290 00:25:46.858370
6291 00:25:46.861226 [CATrainingPosCal] consider 2 rank data
6292 00:25:46.864503 u2DelayCellTimex100 = 270/100 ps
6293 00:25:46.868120 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 00:25:46.871635 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 00:25:46.874879 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 00:25:46.877988 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 00:25:46.881318 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 00:25:46.887968 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 00:25:46.888070
6300 00:25:46.891359 CA PerBit enable=1, Macro0, CA PI delay=36
6301 00:25:46.891435
6302 00:25:46.894981 [CBTSetCACLKResult] CA Dly = 36
6303 00:25:46.895082 CS Dly: 1 (0~32)
6304 00:25:46.895168
6305 00:25:46.897876 ----->DramcWriteLeveling(PI) begin...
6306 00:25:46.897977 ==
6307 00:25:46.901371 Dram Type= 6, Freq= 0, CH_0, rank 0
6308 00:25:46.904916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6309 00:25:46.907905 ==
6310 00:25:46.907982 Write leveling (Byte 0): 40 => 8
6311 00:25:46.911648 Write leveling (Byte 1): 32 => 0
6312 00:25:46.915020 DramcWriteLeveling(PI) end<-----
6313 00:25:46.915097
6314 00:25:46.915156 ==
6315 00:25:46.917859 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 00:25:46.925195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 00:25:46.925275 ==
6318 00:25:46.925333 [Gating] SW mode calibration
6319 00:25:46.934693 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6320 00:25:46.938356 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6321 00:25:46.941199 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6322 00:25:46.947929 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6323 00:25:46.951442 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6324 00:25:46.954461 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6325 00:25:46.961443 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 00:25:46.964976 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6327 00:25:46.968001 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6328 00:25:46.975052 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6329 00:25:46.978093 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6330 00:25:46.981311 Total UI for P1: 0, mck2ui 16
6331 00:25:46.985075 best dqsien dly found for B0: ( 0, 14, 24)
6332 00:25:46.988074 Total UI for P1: 0, mck2ui 16
6333 00:25:46.991560 best dqsien dly found for B1: ( 0, 14, 24)
6334 00:25:46.994910 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6335 00:25:46.998361 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6336 00:25:46.998437
6337 00:25:47.001790 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6338 00:25:47.004895 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6339 00:25:47.008624 [Gating] SW calibration Done
6340 00:25:47.008701 ==
6341 00:25:47.011612 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 00:25:47.015248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 00:25:47.015324 ==
6344 00:25:47.018321 RX Vref Scan: 0
6345 00:25:47.018395
6346 00:25:47.021807 RX Vref 0 -> 0, step: 1
6347 00:25:47.021905
6348 00:25:47.021995 RX Delay -410 -> 252, step: 16
6349 00:25:47.028406 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6350 00:25:47.031886 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6351 00:25:47.035247 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6352 00:25:47.038580 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6353 00:25:47.045170 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6354 00:25:47.048965 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6355 00:25:47.051839 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6356 00:25:47.055443 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6357 00:25:47.061927 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6358 00:25:47.065535 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6359 00:25:47.068478 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6360 00:25:47.071973 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6361 00:25:47.078497 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6362 00:25:47.082119 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6363 00:25:47.085238 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6364 00:25:47.088537 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6365 00:25:47.092000 ==
6366 00:25:47.095662 Dram Type= 6, Freq= 0, CH_0, rank 0
6367 00:25:47.098655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6368 00:25:47.098733 ==
6369 00:25:47.098793 DQS Delay:
6370 00:25:47.101920 DQS0 = 35, DQS1 = 51
6371 00:25:47.102058 DQM Delay:
6372 00:25:47.105829 DQM0 = 8, DQM1 = 10
6373 00:25:47.105930 DQ Delay:
6374 00:25:47.108801 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6375 00:25:47.112246 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6376 00:25:47.112325 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6377 00:25:47.115409 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6378 00:25:47.119174
6379 00:25:47.119250
6380 00:25:47.119310 ==
6381 00:25:47.122222 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 00:25:47.125828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 00:25:47.125932 ==
6384 00:25:47.126054
6385 00:25:47.126130
6386 00:25:47.129091 TX Vref Scan disable
6387 00:25:47.129169 == TX Byte 0 ==
6388 00:25:47.132260 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6389 00:25:47.139277 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6390 00:25:47.139357 == TX Byte 1 ==
6391 00:25:47.142423 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6392 00:25:47.148821 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6393 00:25:47.148902 ==
6394 00:25:47.152021 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 00:25:47.155397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 00:25:47.155475 ==
6397 00:25:47.155553
6398 00:25:47.155625
6399 00:25:47.159007 TX Vref Scan disable
6400 00:25:47.159085 == TX Byte 0 ==
6401 00:25:47.165462 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6402 00:25:47.168940 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6403 00:25:47.169019 == TX Byte 1 ==
6404 00:25:47.175344 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6405 00:25:47.178911 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6406 00:25:47.178989
6407 00:25:47.179067 [DATLAT]
6408 00:25:47.182015 Freq=400, CH0 RK0
6409 00:25:47.182094
6410 00:25:47.182173 DATLAT Default: 0xf
6411 00:25:47.185540 0, 0xFFFF, sum = 0
6412 00:25:47.185632 1, 0xFFFF, sum = 0
6413 00:25:47.189205 2, 0xFFFF, sum = 0
6414 00:25:47.189282 3, 0xFFFF, sum = 0
6415 00:25:47.192354 4, 0xFFFF, sum = 0
6416 00:25:47.192432 5, 0xFFFF, sum = 0
6417 00:25:47.195804 6, 0xFFFF, sum = 0
6418 00:25:47.195883 7, 0xFFFF, sum = 0
6419 00:25:47.198895 8, 0xFFFF, sum = 0
6420 00:25:47.198972 9, 0xFFFF, sum = 0
6421 00:25:47.202391 10, 0xFFFF, sum = 0
6422 00:25:47.202469 11, 0xFFFF, sum = 0
6423 00:25:47.205882 12, 0xFFFF, sum = 0
6424 00:25:47.205992 13, 0x0, sum = 1
6425 00:25:47.208876 14, 0x0, sum = 2
6426 00:25:47.208954 15, 0x0, sum = 3
6427 00:25:47.212317 16, 0x0, sum = 4
6428 00:25:47.212395 best_step = 14
6429 00:25:47.212455
6430 00:25:47.212510 ==
6431 00:25:47.215498 Dram Type= 6, Freq= 0, CH_0, rank 0
6432 00:25:47.222188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 00:25:47.222270 ==
6434 00:25:47.222348 RX Vref Scan: 1
6435 00:25:47.222422
6436 00:25:47.225375 RX Vref 0 -> 0, step: 1
6437 00:25:47.225454
6438 00:25:47.248159 RX Delay -343 -> 252, step: 8
6439 00:25:47.248274
6440 00:25:47.248356 Set Vref, RX VrefLevel [Byte0]: 54
6441 00:25:47.248430 [Byte1]: 51
6442 00:25:47.248501
6443 00:25:47.248572 Final RX Vref Byte 0 = 54 to rank0
6444 00:25:47.248642 Final RX Vref Byte 1 = 51 to rank0
6445 00:25:47.248710 Final RX Vref Byte 0 = 54 to rank1
6446 00:25:47.249150 Final RX Vref Byte 1 = 51 to rank1==
6447 00:25:47.252126 Dram Type= 6, Freq= 0, CH_0, rank 0
6448 00:25:47.255389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 00:25:47.259182 ==
6450 00:25:47.259261 DQS Delay:
6451 00:25:47.259340 DQS0 = 44, DQS1 = 60
6452 00:25:47.262293 DQM Delay:
6453 00:25:47.262372 DQM0 = 11, DQM1 = 14
6454 00:25:47.265399 DQ Delay:
6455 00:25:47.265478 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6456 00:25:47.268856 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6457 00:25:47.272171 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6458 00:25:47.275800 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =28
6459 00:25:47.275880
6460 00:25:47.275957
6461 00:25:47.285544 [DQSOSCAuto] RK0, (LSB)MR18= 0x8856, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6462 00:25:47.289167 CH0 RK0: MR19=C0C, MR18=8856
6463 00:25:47.292214 CH0_RK0: MR19=0xC0C, MR18=0x8856, DQSOSC=392, MR23=63, INC=384, DEC=256
6464 00:25:47.295909 ==
6465 00:25:47.299064 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 00:25:47.301913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 00:25:47.302021 ==
6468 00:25:47.305532 [Gating] SW mode calibration
6469 00:25:47.312045 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6470 00:25:47.315346 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6471 00:25:47.321969 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6472 00:25:47.325316 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6473 00:25:47.328700 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6474 00:25:47.335576 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6475 00:25:47.339028 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 00:25:47.342396 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6477 00:25:47.349330 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6478 00:25:47.352073 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6479 00:25:47.355326 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6480 00:25:47.359053 Total UI for P1: 0, mck2ui 16
6481 00:25:47.362527 best dqsien dly found for B0: ( 0, 14, 24)
6482 00:25:47.365833 Total UI for P1: 0, mck2ui 16
6483 00:25:47.368973 best dqsien dly found for B1: ( 0, 14, 24)
6484 00:25:47.372427 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6485 00:25:47.375831 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6486 00:25:47.375912
6487 00:25:47.378923 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6488 00:25:47.385423 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6489 00:25:47.385511 [Gating] SW calibration Done
6490 00:25:47.385589 ==
6491 00:25:47.388706 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 00:25:47.395726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 00:25:47.395810 ==
6494 00:25:47.395888 RX Vref Scan: 0
6495 00:25:47.395962
6496 00:25:47.398682 RX Vref 0 -> 0, step: 1
6497 00:25:47.398761
6498 00:25:47.402277 RX Delay -410 -> 252, step: 16
6499 00:25:47.405678 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6500 00:25:47.408671 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6501 00:25:47.415714 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6502 00:25:47.419092 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6503 00:25:47.421920 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6504 00:25:47.425522 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6505 00:25:47.431988 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6506 00:25:47.435423 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6507 00:25:47.439284 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6508 00:25:47.442313 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6509 00:25:47.449029 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6510 00:25:47.452354 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6511 00:25:47.456116 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6512 00:25:47.458864 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6513 00:25:47.465947 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6514 00:25:47.469403 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6515 00:25:47.469482 ==
6516 00:25:47.472828 Dram Type= 6, Freq= 0, CH_0, rank 1
6517 00:25:47.475602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 00:25:47.475678 ==
6519 00:25:47.479017 DQS Delay:
6520 00:25:47.479093 DQS0 = 43, DQS1 = 51
6521 00:25:47.479152 DQM Delay:
6522 00:25:47.482495 DQM0 = 11, DQM1 = 10
6523 00:25:47.482570 DQ Delay:
6524 00:25:47.485726 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6525 00:25:47.488849 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6526 00:25:47.492213 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6527 00:25:47.496020 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6528 00:25:47.496097
6529 00:25:47.496194
6530 00:25:47.496282 ==
6531 00:25:47.499121 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 00:25:47.502696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 00:25:47.502773 ==
6534 00:25:47.502830
6535 00:25:47.502883
6536 00:25:47.506207 TX Vref Scan disable
6537 00:25:47.509386 == TX Byte 0 ==
6538 00:25:47.512898 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6539 00:25:47.515849 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6540 00:25:47.515924 == TX Byte 1 ==
6541 00:25:47.522909 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6542 00:25:47.526286 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6543 00:25:47.526365 ==
6544 00:25:47.529393 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 00:25:47.532338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 00:25:47.532414 ==
6547 00:25:47.532471
6548 00:25:47.535703
6549 00:25:47.535780 TX Vref Scan disable
6550 00:25:47.539004 == TX Byte 0 ==
6551 00:25:47.542377 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6552 00:25:47.545879 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6553 00:25:47.549316 == TX Byte 1 ==
6554 00:25:47.552273 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6555 00:25:47.555553 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6556 00:25:47.555631
6557 00:25:47.555691 [DATLAT]
6558 00:25:47.558984 Freq=400, CH0 RK1
6559 00:25:47.559065
6560 00:25:47.559143 DATLAT Default: 0xe
6561 00:25:47.562555 0, 0xFFFF, sum = 0
6562 00:25:47.562636 1, 0xFFFF, sum = 0
6563 00:25:47.565464 2, 0xFFFF, sum = 0
6564 00:25:47.569170 3, 0xFFFF, sum = 0
6565 00:25:47.569252 4, 0xFFFF, sum = 0
6566 00:25:47.572349 5, 0xFFFF, sum = 0
6567 00:25:47.572430 6, 0xFFFF, sum = 0
6568 00:25:47.576075 7, 0xFFFF, sum = 0
6569 00:25:47.576156 8, 0xFFFF, sum = 0
6570 00:25:47.578974 9, 0xFFFF, sum = 0
6571 00:25:47.579056 10, 0xFFFF, sum = 0
6572 00:25:47.582280 11, 0xFFFF, sum = 0
6573 00:25:47.582361 12, 0xFFFF, sum = 0
6574 00:25:47.585813 13, 0x0, sum = 1
6575 00:25:47.585917 14, 0x0, sum = 2
6576 00:25:47.589223 15, 0x0, sum = 3
6577 00:25:47.589304 16, 0x0, sum = 4
6578 00:25:47.592128 best_step = 14
6579 00:25:47.592206
6580 00:25:47.592284 ==
6581 00:25:47.595713 Dram Type= 6, Freq= 0, CH_0, rank 1
6582 00:25:47.599383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 00:25:47.599463 ==
6584 00:25:47.599542 RX Vref Scan: 0
6585 00:25:47.599616
6586 00:25:47.602578 RX Vref 0 -> 0, step: 1
6587 00:25:47.602657
6588 00:25:47.605474 RX Delay -343 -> 252, step: 8
6589 00:25:47.612843 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6590 00:25:47.616178 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6591 00:25:47.619714 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6592 00:25:47.622747 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6593 00:25:47.629865 iDelay=217, Bit 4, Center -40 (-279 ~ 200) 480
6594 00:25:47.632819 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6595 00:25:47.636303 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6596 00:25:47.639874 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6597 00:25:47.646608 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6598 00:25:47.649642 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6599 00:25:47.652951 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6600 00:25:47.656363 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6601 00:25:47.662858 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6602 00:25:47.666372 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6603 00:25:47.670111 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6604 00:25:47.672936 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6605 00:25:47.676336 ==
6606 00:25:47.679775 Dram Type= 6, Freq= 0, CH_0, rank 1
6607 00:25:47.683212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6608 00:25:47.683294 ==
6609 00:25:47.683372 DQS Delay:
6610 00:25:47.686475 DQS0 = 48, DQS1 = 56
6611 00:25:47.686554 DQM Delay:
6612 00:25:47.689478 DQM0 = 12, DQM1 = 10
6613 00:25:47.689558 DQ Delay:
6614 00:25:47.692875 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6615 00:25:47.696376 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =20
6616 00:25:47.699859 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6617 00:25:47.703468 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =20
6618 00:25:47.703547
6619 00:25:47.703625
6620 00:25:47.710027 [DQSOSCAuto] RK1, (LSB)MR18= 0x9567, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6621 00:25:47.712844 CH0 RK1: MR19=C0C, MR18=9567
6622 00:25:47.719923 CH0_RK1: MR19=0xC0C, MR18=0x9567, DQSOSC=391, MR23=63, INC=386, DEC=257
6623 00:25:47.723180 [RxdqsGatingPostProcess] freq 400
6624 00:25:47.726572 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6625 00:25:47.729498 best DQS0 dly(2T, 0.5T) = (0, 10)
6626 00:25:47.733209 best DQS1 dly(2T, 0.5T) = (0, 10)
6627 00:25:47.736628 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6628 00:25:47.739677 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6629 00:25:47.743239 best DQS0 dly(2T, 0.5T) = (0, 10)
6630 00:25:47.746053 best DQS1 dly(2T, 0.5T) = (0, 10)
6631 00:25:47.749396 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6632 00:25:47.752816 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6633 00:25:47.756212 Pre-setting of DQS Precalculation
6634 00:25:47.759740 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6635 00:25:47.759818 ==
6636 00:25:47.762851 Dram Type= 6, Freq= 0, CH_1, rank 0
6637 00:25:47.769683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6638 00:25:47.769762 ==
6639 00:25:47.773229 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6640 00:25:47.779736 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6641 00:25:47.783191 [CA 0] Center 36 (8~64) winsize 57
6642 00:25:47.785928 [CA 1] Center 36 (8~64) winsize 57
6643 00:25:47.789818 [CA 2] Center 36 (8~64) winsize 57
6644 00:25:47.792954 [CA 3] Center 36 (8~64) winsize 57
6645 00:25:47.796530 [CA 4] Center 36 (8~64) winsize 57
6646 00:25:47.799533 [CA 5] Center 36 (8~64) winsize 57
6647 00:25:47.799609
6648 00:25:47.803110 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6649 00:25:47.803185
6650 00:25:47.806063 [CATrainingPosCal] consider 1 rank data
6651 00:25:47.810233 u2DelayCellTimex100 = 270/100 ps
6652 00:25:47.812821 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 00:25:47.816269 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 00:25:47.819586 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 00:25:47.823138 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 00:25:47.826545 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 00:25:47.829508 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 00:25:47.829583
6659 00:25:47.836388 CA PerBit enable=1, Macro0, CA PI delay=36
6660 00:25:47.836465
6661 00:25:47.836525 [CBTSetCACLKResult] CA Dly = 36
6662 00:25:47.839559 CS Dly: 1 (0~32)
6663 00:25:47.839636 ==
6664 00:25:47.842963 Dram Type= 6, Freq= 0, CH_1, rank 1
6665 00:25:47.846595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 00:25:47.846673 ==
6667 00:25:47.853088 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6668 00:25:47.859698 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6669 00:25:47.863148 [CA 0] Center 36 (8~64) winsize 57
6670 00:25:47.866695 [CA 1] Center 36 (8~64) winsize 57
6671 00:25:47.869999 [CA 2] Center 36 (8~64) winsize 57
6672 00:25:47.870076 [CA 3] Center 36 (8~64) winsize 57
6673 00:25:47.872881 [CA 4] Center 36 (8~64) winsize 57
6674 00:25:47.876481 [CA 5] Center 36 (8~64) winsize 57
6675 00:25:47.876559
6676 00:25:47.880002 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6677 00:25:47.883062
6678 00:25:47.886466 [CATrainingPosCal] consider 2 rank data
6679 00:25:47.886543 u2DelayCellTimex100 = 270/100 ps
6680 00:25:47.893151 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 00:25:47.896659 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 00:25:47.899627 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 00:25:47.903485 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 00:25:47.906437 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 00:25:47.909817 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 00:25:47.909950
6687 00:25:47.913131 CA PerBit enable=1, Macro0, CA PI delay=36
6688 00:25:47.913253
6689 00:25:47.916407 [CBTSetCACLKResult] CA Dly = 36
6690 00:25:47.919942 CS Dly: 1 (0~32)
6691 00:25:47.920064
6692 00:25:47.923404 ----->DramcWriteLeveling(PI) begin...
6693 00:25:47.923521 ==
6694 00:25:47.926177 Dram Type= 6, Freq= 0, CH_1, rank 0
6695 00:25:47.929600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6696 00:25:47.929705 ==
6697 00:25:47.933160 Write leveling (Byte 0): 40 => 8
6698 00:25:47.936171 Write leveling (Byte 1): 40 => 8
6699 00:25:47.939635 DramcWriteLeveling(PI) end<-----
6700 00:25:47.939744
6701 00:25:47.939827 ==
6702 00:25:47.943253 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 00:25:47.946720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 00:25:47.946812 ==
6705 00:25:47.949818 [Gating] SW mode calibration
6706 00:25:47.956402 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6707 00:25:47.963000 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6708 00:25:47.966248 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6709 00:25:47.969634 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6710 00:25:47.976229 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6711 00:25:47.979895 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6712 00:25:47.983230 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 00:25:47.989682 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6714 00:25:47.993103 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6715 00:25:47.996609 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6716 00:25:47.999823 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6717 00:25:48.003188 Total UI for P1: 0, mck2ui 16
6718 00:25:48.006125 best dqsien dly found for B0: ( 0, 14, 24)
6719 00:25:48.010362 Total UI for P1: 0, mck2ui 16
6720 00:25:48.013479 best dqsien dly found for B1: ( 0, 14, 24)
6721 00:25:48.016823 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6722 00:25:48.023789 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6723 00:25:48.024189
6724 00:25:48.026938 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6725 00:25:48.030008 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6726 00:25:48.033902 [Gating] SW calibration Done
6727 00:25:48.034415 ==
6728 00:25:48.037306 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 00:25:48.039951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 00:25:48.040314 ==
6731 00:25:48.040678 RX Vref Scan: 0
6732 00:25:48.040945
6733 00:25:48.043773 RX Vref 0 -> 0, step: 1
6734 00:25:48.044216
6735 00:25:48.047100 RX Delay -410 -> 252, step: 16
6736 00:25:48.049961 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6737 00:25:48.056967 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6738 00:25:48.059812 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6739 00:25:48.063387 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6740 00:25:48.066806 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6741 00:25:48.073710 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6742 00:25:48.077131 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6743 00:25:48.080544 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6744 00:25:48.083327 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6745 00:25:48.086767 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6746 00:25:48.093333 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6747 00:25:48.096760 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6748 00:25:48.100431 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6749 00:25:48.107124 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6750 00:25:48.109877 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6751 00:25:48.113497 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6752 00:25:48.113858 ==
6753 00:25:48.117174 Dram Type= 6, Freq= 0, CH_1, rank 0
6754 00:25:48.119915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6755 00:25:48.120276 ==
6756 00:25:48.123559 DQS Delay:
6757 00:25:48.123946 DQS0 = 51, DQS1 = 59
6758 00:25:48.127391 DQM Delay:
6759 00:25:48.127829 DQM0 = 19, DQM1 = 16
6760 00:25:48.130488 DQ Delay:
6761 00:25:48.130847 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6762 00:25:48.133455 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6763 00:25:48.136848 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6764 00:25:48.140262 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6765 00:25:48.140625
6766 00:25:48.140902
6767 00:25:48.143399 ==
6768 00:25:48.146861 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 00:25:48.150394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 00:25:48.150870 ==
6771 00:25:48.151164
6772 00:25:48.151437
6773 00:25:48.153258 TX Vref Scan disable
6774 00:25:48.153617 == TX Byte 0 ==
6775 00:25:48.156907 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 00:25:48.163452 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 00:25:48.163819 == TX Byte 1 ==
6778 00:25:48.166432 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6779 00:25:48.170068 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6780 00:25:48.173508 ==
6781 00:25:48.177120 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 00:25:48.179969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 00:25:48.180327 ==
6784 00:25:48.180601
6785 00:25:48.180853
6786 00:25:48.183855 TX Vref Scan disable
6787 00:25:48.184298 == TX Byte 0 ==
6788 00:25:48.186928 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6789 00:25:48.190498 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6790 00:25:48.194050 == TX Byte 1 ==
6791 00:25:48.196764 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6792 00:25:48.200458 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6793 00:25:48.200815
6794 00:25:48.203811 [DATLAT]
6795 00:25:48.204390 Freq=400, CH1 RK0
6796 00:25:48.204791
6797 00:25:48.207038 DATLAT Default: 0xf
6798 00:25:48.207394 0, 0xFFFF, sum = 0
6799 00:25:48.210033 1, 0xFFFF, sum = 0
6800 00:25:48.210401 2, 0xFFFF, sum = 0
6801 00:25:48.213561 3, 0xFFFF, sum = 0
6802 00:25:48.213923 4, 0xFFFF, sum = 0
6803 00:25:48.216665 5, 0xFFFF, sum = 0
6804 00:25:48.217030 6, 0xFFFF, sum = 0
6805 00:25:48.220589 7, 0xFFFF, sum = 0
6806 00:25:48.220950 8, 0xFFFF, sum = 0
6807 00:25:48.223562 9, 0xFFFF, sum = 0
6808 00:25:48.227003 10, 0xFFFF, sum = 0
6809 00:25:48.227363 11, 0xFFFF, sum = 0
6810 00:25:48.230073 12, 0xFFFF, sum = 0
6811 00:25:48.230435 13, 0x0, sum = 1
6812 00:25:48.233687 14, 0x0, sum = 2
6813 00:25:48.234056 15, 0x0, sum = 3
6814 00:25:48.234537 16, 0x0, sum = 4
6815 00:25:48.237251 best_step = 14
6816 00:25:48.237574
6817 00:25:48.237829 ==
6818 00:25:48.240072 Dram Type= 6, Freq= 0, CH_1, rank 0
6819 00:25:48.243984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 00:25:48.244403 ==
6821 00:25:48.247241 RX Vref Scan: 1
6822 00:25:48.247568
6823 00:25:48.247821 RX Vref 0 -> 0, step: 1
6824 00:25:48.250235
6825 00:25:48.250560 RX Delay -359 -> 252, step: 8
6826 00:25:48.250815
6827 00:25:48.254076 Set Vref, RX VrefLevel [Byte0]: 61
6828 00:25:48.257102 [Byte1]: 53
6829 00:25:48.262279
6830 00:25:48.262634 Final RX Vref Byte 0 = 61 to rank0
6831 00:25:48.265677 Final RX Vref Byte 1 = 53 to rank0
6832 00:25:48.268901 Final RX Vref Byte 0 = 61 to rank1
6833 00:25:48.272236 Final RX Vref Byte 1 = 53 to rank1==
6834 00:25:48.275614 Dram Type= 6, Freq= 0, CH_1, rank 0
6835 00:25:48.282455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 00:25:48.282885 ==
6837 00:25:48.283154 DQS Delay:
6838 00:25:48.283391 DQS0 = 48, DQS1 = 60
6839 00:25:48.285521 DQM Delay:
6840 00:25:48.285849 DQM0 = 10, DQM1 = 13
6841 00:25:48.289095 DQ Delay:
6842 00:25:48.291988 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =12
6843 00:25:48.292320 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6844 00:25:48.296079 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6845 00:25:48.298804 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6846 00:25:48.299131
6847 00:25:48.299398
6848 00:25:48.308682 [DQSOSCAuto] RK0, (LSB)MR18= 0x933a, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
6849 00:25:48.312197 CH1 RK0: MR19=C0C, MR18=933A
6850 00:25:48.319153 CH1_RK0: MR19=0xC0C, MR18=0x933A, DQSOSC=391, MR23=63, INC=386, DEC=257
6851 00:25:48.319513 ==
6852 00:25:48.322134 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 00:25:48.325362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 00:25:48.325779 ==
6855 00:25:48.329119 [Gating] SW mode calibration
6856 00:25:48.335774 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6857 00:25:48.339158 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6858 00:25:48.346118 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6859 00:25:48.349195 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6860 00:25:48.352422 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6861 00:25:48.359149 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6862 00:25:48.362500 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 00:25:48.365812 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6864 00:25:48.372166 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6865 00:25:48.375924 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6866 00:25:48.379420 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6867 00:25:48.382398 Total UI for P1: 0, mck2ui 16
6868 00:25:48.385900 best dqsien dly found for B0: ( 0, 14, 24)
6869 00:25:48.389362 Total UI for P1: 0, mck2ui 16
6870 00:25:48.392935 best dqsien dly found for B1: ( 0, 14, 24)
6871 00:25:48.395730 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6872 00:25:48.399024 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6873 00:25:48.399419
6874 00:25:48.406150 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6875 00:25:48.409308 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6876 00:25:48.409704 [Gating] SW calibration Done
6877 00:25:48.412179 ==
6878 00:25:48.412570 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 00:25:48.419425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 00:25:48.419839 ==
6881 00:25:48.420158 RX Vref Scan: 0
6882 00:25:48.420443
6883 00:25:48.422368 RX Vref 0 -> 0, step: 1
6884 00:25:48.422758
6885 00:25:48.426379 RX Delay -410 -> 252, step: 16
6886 00:25:48.429715 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6887 00:25:48.432370 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6888 00:25:48.439332 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6889 00:25:48.442378 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6890 00:25:48.445764 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6891 00:25:48.449479 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6892 00:25:48.456057 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6893 00:25:48.459689 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6894 00:25:48.462830 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6895 00:25:48.466050 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6896 00:25:48.472696 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6897 00:25:48.476488 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6898 00:25:48.479069 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6899 00:25:48.482632 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6900 00:25:48.489214 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6901 00:25:48.492872 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6902 00:25:48.493352 ==
6903 00:25:48.496022 Dram Type= 6, Freq= 0, CH_1, rank 1
6904 00:25:48.499156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 00:25:48.499637 ==
6906 00:25:48.502371 DQS Delay:
6907 00:25:48.502770 DQS0 = 51, DQS1 = 59
6908 00:25:48.505549 DQM Delay:
6909 00:25:48.505946 DQM0 = 17, DQM1 = 19
6910 00:25:48.506370 DQ Delay:
6911 00:25:48.508927 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6912 00:25:48.512418 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6913 00:25:48.515530 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6914 00:25:48.519306 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6915 00:25:48.519783
6916 00:25:48.520180
6917 00:25:48.520562 ==
6918 00:25:48.521908 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 00:25:48.529243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 00:25:48.529725 ==
6921 00:25:48.530204
6922 00:25:48.530581
6923 00:25:48.530943 TX Vref Scan disable
6924 00:25:48.532807 == TX Byte 0 ==
6925 00:25:48.535383 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6926 00:25:48.539093 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6927 00:25:48.542381 == TX Byte 1 ==
6928 00:25:48.545377 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6929 00:25:48.549020 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6930 00:25:48.549416 ==
6931 00:25:48.552528 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 00:25:48.559461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 00:25:48.559934 ==
6934 00:25:48.560241
6935 00:25:48.560521
6936 00:25:48.560789 TX Vref Scan disable
6937 00:25:48.562144 == TX Byte 0 ==
6938 00:25:48.565260 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6939 00:25:48.569244 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6940 00:25:48.571973 == TX Byte 1 ==
6941 00:25:48.575886 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6942 00:25:48.579179 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6943 00:25:48.579649
6944 00:25:48.582498 [DATLAT]
6945 00:25:48.582889 Freq=400, CH1 RK1
6946 00:25:48.583191
6947 00:25:48.585636 DATLAT Default: 0xe
6948 00:25:48.586154 0, 0xFFFF, sum = 0
6949 00:25:48.588951 1, 0xFFFF, sum = 0
6950 00:25:48.589356 2, 0xFFFF, sum = 0
6951 00:25:48.592740 3, 0xFFFF, sum = 0
6952 00:25:48.593214 4, 0xFFFF, sum = 0
6953 00:25:48.596187 5, 0xFFFF, sum = 0
6954 00:25:48.596667 6, 0xFFFF, sum = 0
6955 00:25:48.599212 7, 0xFFFF, sum = 0
6956 00:25:48.599611 8, 0xFFFF, sum = 0
6957 00:25:48.602610 9, 0xFFFF, sum = 0
6958 00:25:48.603010 10, 0xFFFF, sum = 0
6959 00:25:48.606355 11, 0xFFFF, sum = 0
6960 00:25:48.606831 12, 0xFFFF, sum = 0
6961 00:25:48.609053 13, 0x0, sum = 1
6962 00:25:48.609475 14, 0x0, sum = 2
6963 00:25:48.612832 15, 0x0, sum = 3
6964 00:25:48.613311 16, 0x0, sum = 4
6965 00:25:48.615910 best_step = 14
6966 00:25:48.616299
6967 00:25:48.616603 ==
6968 00:25:48.619218 Dram Type= 6, Freq= 0, CH_1, rank 1
6969 00:25:48.622278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6970 00:25:48.622681 ==
6971 00:25:48.625547 RX Vref Scan: 0
6972 00:25:48.626056
6973 00:25:48.626384 RX Vref 0 -> 0, step: 1
6974 00:25:48.626669
6975 00:25:48.628673 RX Delay -359 -> 252, step: 8
6976 00:25:48.637871 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6977 00:25:48.640270 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6978 00:25:48.644285 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6979 00:25:48.647581 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6980 00:25:48.653736 iDelay=217, Bit 4, Center -40 (-279 ~ 200) 480
6981 00:25:48.657077 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6982 00:25:48.660998 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6983 00:25:48.664152 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6984 00:25:48.670857 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6985 00:25:48.673872 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6986 00:25:48.677279 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6987 00:25:48.681003 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6988 00:25:48.687449 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6989 00:25:48.690826 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6990 00:25:48.694402 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6991 00:25:48.697584 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6992 00:25:48.698000 ==
6993 00:25:48.700753 Dram Type= 6, Freq= 0, CH_1, rank 1
6994 00:25:48.707714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6995 00:25:48.708176 ==
6996 00:25:48.708480 DQS Delay:
6997 00:25:48.711218 DQS0 = 52, DQS1 = 56
6998 00:25:48.711621 DQM Delay:
6999 00:25:48.714159 DQM0 = 13, DQM1 = 8
7000 00:25:48.714553 DQ Delay:
7001 00:25:48.717733 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7002 00:25:48.721147 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7003 00:25:48.721616 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
7004 00:25:48.727156 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
7005 00:25:48.727551
7006 00:25:48.727853
7007 00:25:48.734445 [DQSOSCAuto] RK1, (LSB)MR18= 0x768a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 394 ps
7008 00:25:48.737311 CH1 RK1: MR19=C0C, MR18=768A
7009 00:25:48.744513 CH1_RK1: MR19=0xC0C, MR18=0x768A, DQSOSC=392, MR23=63, INC=384, DEC=256
7010 00:25:48.747824 [RxdqsGatingPostProcess] freq 400
7011 00:25:48.751201 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7012 00:25:48.753911 best DQS0 dly(2T, 0.5T) = (0, 10)
7013 00:25:48.757611 best DQS1 dly(2T, 0.5T) = (0, 10)
7014 00:25:48.760705 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7015 00:25:48.764106 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7016 00:25:48.767621 best DQS0 dly(2T, 0.5T) = (0, 10)
7017 00:25:48.771145 best DQS1 dly(2T, 0.5T) = (0, 10)
7018 00:25:48.774077 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7019 00:25:48.777693 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7020 00:25:48.780624 Pre-setting of DQS Precalculation
7021 00:25:48.784440 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7022 00:25:48.790882 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7023 00:25:48.800874 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7024 00:25:48.801345
7025 00:25:48.801750
7026 00:25:48.804138 [Calibration Summary] 800 Mbps
7027 00:25:48.804543 CH 0, Rank 0
7028 00:25:48.807301 SW Impedance : PASS
7029 00:25:48.807702 DUTY Scan : NO K
7030 00:25:48.810427 ZQ Calibration : PASS
7031 00:25:48.810832 Jitter Meter : NO K
7032 00:25:48.813962 CBT Training : PASS
7033 00:25:48.817432 Write leveling : PASS
7034 00:25:48.817909 RX DQS gating : PASS
7035 00:25:48.820998 RX DQ/DQS(RDDQC) : PASS
7036 00:25:48.824526 TX DQ/DQS : PASS
7037 00:25:48.825008 RX DATLAT : PASS
7038 00:25:48.827468 RX DQ/DQS(Engine): PASS
7039 00:25:48.830932 TX OE : NO K
7040 00:25:48.831339 All Pass.
7041 00:25:48.831738
7042 00:25:48.832113 CH 0, Rank 1
7043 00:25:48.834078 SW Impedance : PASS
7044 00:25:48.837328 DUTY Scan : NO K
7045 00:25:48.837731 ZQ Calibration : PASS
7046 00:25:48.841501 Jitter Meter : NO K
7047 00:25:48.842019 CBT Training : PASS
7048 00:25:48.844707 Write leveling : NO K
7049 00:25:48.847448 RX DQS gating : PASS
7050 00:25:48.847852 RX DQ/DQS(RDDQC) : PASS
7051 00:25:48.851055 TX DQ/DQS : PASS
7052 00:25:48.854596 RX DATLAT : PASS
7053 00:25:48.855081 RX DQ/DQS(Engine): PASS
7054 00:25:48.858385 TX OE : NO K
7055 00:25:48.858867 All Pass.
7056 00:25:48.859270
7057 00:25:48.861826 CH 1, Rank 0
7058 00:25:48.862350 SW Impedance : PASS
7059 00:25:48.864707 DUTY Scan : NO K
7060 00:25:48.868079 ZQ Calibration : PASS
7061 00:25:48.868485 Jitter Meter : NO K
7062 00:25:48.871036 CBT Training : PASS
7063 00:25:48.874409 Write leveling : PASS
7064 00:25:48.874780 RX DQS gating : PASS
7065 00:25:48.877616 RX DQ/DQS(RDDQC) : PASS
7066 00:25:48.878119 TX DQ/DQS : PASS
7067 00:25:48.881609 RX DATLAT : PASS
7068 00:25:48.884684 RX DQ/DQS(Engine): PASS
7069 00:25:48.885122 TX OE : NO K
7070 00:25:48.888135 All Pass.
7071 00:25:48.888572
7072 00:25:48.888856 CH 1, Rank 1
7073 00:25:48.891674 SW Impedance : PASS
7074 00:25:48.892108 DUTY Scan : NO K
7075 00:25:48.894955 ZQ Calibration : PASS
7076 00:25:48.898105 Jitter Meter : NO K
7077 00:25:48.898548 CBT Training : PASS
7078 00:25:48.901276 Write leveling : NO K
7079 00:25:48.904615 RX DQS gating : PASS
7080 00:25:48.905055 RX DQ/DQS(RDDQC) : PASS
7081 00:25:48.907784 TX DQ/DQS : PASS
7082 00:25:48.910919 RX DATLAT : PASS
7083 00:25:48.911281 RX DQ/DQS(Engine): PASS
7084 00:25:48.914434 TX OE : NO K
7085 00:25:48.914798 All Pass.
7086 00:25:48.915075
7087 00:25:48.918252 DramC Write-DBI off
7088 00:25:48.921055 PER_BANK_REFRESH: Hybrid Mode
7089 00:25:48.921373 TX_TRACKING: ON
7090 00:25:48.931577 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7091 00:25:48.934568 [FAST_K] Save calibration result to emmc
7092 00:25:48.937848 dramc_set_vcore_voltage set vcore to 725000
7093 00:25:48.941911 Read voltage for 1600, 0
7094 00:25:48.942401 Vio18 = 0
7095 00:25:48.942689 Vcore = 725000
7096 00:25:48.945120 Vdram = 0
7097 00:25:48.945561 Vddq = 0
7098 00:25:48.945847 Vmddr = 0
7099 00:25:48.951846 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7100 00:25:48.954443 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7101 00:25:48.958360 MEM_TYPE=3, freq_sel=13
7102 00:25:48.961316 sv_algorithm_assistance_LP4_3733
7103 00:25:48.964873 ============ PULL DRAM RESETB DOWN ============
7104 00:25:48.968063 ========== PULL DRAM RESETB DOWN end =========
7105 00:25:48.974523 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7106 00:25:48.978183 ===================================
7107 00:25:48.978678 LPDDR4 DRAM CONFIGURATION
7108 00:25:48.981812 ===================================
7109 00:25:48.984830 EX_ROW_EN[0] = 0x0
7110 00:25:48.985299 EX_ROW_EN[1] = 0x0
7111 00:25:48.988358 LP4Y_EN = 0x0
7112 00:25:48.991241 WORK_FSP = 0x1
7113 00:25:48.991707 WL = 0x5
7114 00:25:48.994903 RL = 0x5
7115 00:25:48.995369 BL = 0x2
7116 00:25:48.998493 RPST = 0x0
7117 00:25:48.998962 RD_PRE = 0x0
7118 00:25:49.001025 WR_PRE = 0x1
7119 00:25:49.001417 WR_PST = 0x1
7120 00:25:49.004907 DBI_WR = 0x0
7121 00:25:49.005375 DBI_RD = 0x0
7122 00:25:49.007669 OTF = 0x1
7123 00:25:49.011134 ===================================
7124 00:25:49.014650 ===================================
7125 00:25:49.015034 ANA top config
7126 00:25:49.017674 ===================================
7127 00:25:49.021329 DLL_ASYNC_EN = 0
7128 00:25:49.024839 ALL_SLAVE_EN = 0
7129 00:25:49.025310 NEW_RANK_MODE = 1
7130 00:25:49.029014 DLL_IDLE_MODE = 1
7131 00:25:49.031130 LP45_APHY_COMB_EN = 1
7132 00:25:49.034494 TX_ODT_DIS = 0
7133 00:25:49.034881 NEW_8X_MODE = 1
7134 00:25:49.037919 ===================================
7135 00:25:49.041486 ===================================
7136 00:25:49.044683 data_rate = 3200
7137 00:25:49.048165 CKR = 1
7138 00:25:49.051147 DQ_P2S_RATIO = 8
7139 00:25:49.054738 ===================================
7140 00:25:49.058339 CA_P2S_RATIO = 8
7141 00:25:49.061656 DQ_CA_OPEN = 0
7142 00:25:49.062180 DQ_SEMI_OPEN = 0
7143 00:25:49.064341 CA_SEMI_OPEN = 0
7144 00:25:49.067883 CA_FULL_RATE = 0
7145 00:25:49.071454 DQ_CKDIV4_EN = 0
7146 00:25:49.074597 CA_CKDIV4_EN = 0
7147 00:25:49.078014 CA_PREDIV_EN = 0
7148 00:25:49.078498 PH8_DLY = 12
7149 00:25:49.081319 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7150 00:25:49.084620 DQ_AAMCK_DIV = 4
7151 00:25:49.088051 CA_AAMCK_DIV = 4
7152 00:25:49.091366 CA_ADMCK_DIV = 4
7153 00:25:49.095005 DQ_TRACK_CA_EN = 0
7154 00:25:49.095477 CA_PICK = 1600
7155 00:25:49.098702 CA_MCKIO = 1600
7156 00:25:49.101255 MCKIO_SEMI = 0
7157 00:25:49.105125 PLL_FREQ = 3068
7158 00:25:49.108182 DQ_UI_PI_RATIO = 32
7159 00:25:49.111426 CA_UI_PI_RATIO = 0
7160 00:25:49.115120 ===================================
7161 00:25:49.118089 ===================================
7162 00:25:49.121442 memory_type:LPDDR4
7163 00:25:49.121823 GP_NUM : 10
7164 00:25:49.124376 SRAM_EN : 1
7165 00:25:49.124762 MD32_EN : 0
7166 00:25:49.128290 ===================================
7167 00:25:49.131395 [ANA_INIT] >>>>>>>>>>>>>>
7168 00:25:49.134459 <<<<<< [CONFIGURE PHASE]: ANA_TX
7169 00:25:49.138022 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7170 00:25:49.141338 ===================================
7171 00:25:49.145376 data_rate = 3200,PCW = 0X7600
7172 00:25:49.148498 ===================================
7173 00:25:49.151263 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7174 00:25:49.154742 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7175 00:25:49.161637 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7176 00:25:49.164801 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7177 00:25:49.168208 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7178 00:25:49.171751 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7179 00:25:49.174505 [ANA_INIT] flow start
7180 00:25:49.178587 [ANA_INIT] PLL >>>>>>>>
7181 00:25:49.179057 [ANA_INIT] PLL <<<<<<<<
7182 00:25:49.181948 [ANA_INIT] MIDPI >>>>>>>>
7183 00:25:49.184746 [ANA_INIT] MIDPI <<<<<<<<
7184 00:25:49.188018 [ANA_INIT] DLL >>>>>>>>
7185 00:25:49.188409 [ANA_INIT] DLL <<<<<<<<
7186 00:25:49.191573 [ANA_INIT] flow end
7187 00:25:49.194970 ============ LP4 DIFF to SE enter ============
7188 00:25:49.198292 ============ LP4 DIFF to SE exit ============
7189 00:25:49.201504 [ANA_INIT] <<<<<<<<<<<<<
7190 00:25:49.205199 [Flow] Enable top DCM control >>>>>
7191 00:25:49.208213 [Flow] Enable top DCM control <<<<<
7192 00:25:49.211822 Enable DLL master slave shuffle
7193 00:25:49.214953 ==============================================================
7194 00:25:49.218073 Gating Mode config
7195 00:25:49.225131 ==============================================================
7196 00:25:49.225600 Config description:
7197 00:25:49.235148 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7198 00:25:49.241781 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7199 00:25:49.248039 SELPH_MODE 0: By rank 1: By Phase
7200 00:25:49.251682 ==============================================================
7201 00:25:49.254738 GAT_TRACK_EN = 1
7202 00:25:49.258415 RX_GATING_MODE = 2
7203 00:25:49.261599 RX_GATING_TRACK_MODE = 2
7204 00:25:49.264981 SELPH_MODE = 1
7205 00:25:49.268566 PICG_EARLY_EN = 1
7206 00:25:49.271583 VALID_LAT_VALUE = 1
7207 00:25:49.274502 ==============================================================
7208 00:25:49.278589 Enter into Gating configuration >>>>
7209 00:25:49.281490 Exit from Gating configuration <<<<
7210 00:25:49.284709 Enter into DVFS_PRE_config >>>>>
7211 00:25:49.294864 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7212 00:25:49.298209 Exit from DVFS_PRE_config <<<<<
7213 00:25:49.301554 Enter into PICG configuration >>>>
7214 00:25:49.304906 Exit from PICG configuration <<<<
7215 00:25:49.308103 [RX_INPUT] configuration >>>>>
7216 00:25:49.311347 [RX_INPUT] configuration <<<<<
7217 00:25:49.318311 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7218 00:25:49.325318 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7219 00:25:49.328228 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7220 00:25:49.334697 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7221 00:25:49.341729 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7222 00:25:49.347957 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7223 00:25:49.351323 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7224 00:25:49.354661 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7225 00:25:49.358027 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7226 00:25:49.364580 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7227 00:25:49.368188 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7228 00:25:49.371556 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7229 00:25:49.374319 ===================================
7230 00:25:49.377756 LPDDR4 DRAM CONFIGURATION
7231 00:25:49.381577 ===================================
7232 00:25:49.381684 EX_ROW_EN[0] = 0x0
7233 00:25:49.384366 EX_ROW_EN[1] = 0x0
7234 00:25:49.384473 LP4Y_EN = 0x0
7235 00:25:49.387636 WORK_FSP = 0x1
7236 00:25:49.387776 WL = 0x5
7237 00:25:49.391118 RL = 0x5
7238 00:25:49.391225 BL = 0x2
7239 00:25:49.394524 RPST = 0x0
7240 00:25:49.394635 RD_PRE = 0x0
7241 00:25:49.397915 WR_PRE = 0x1
7242 00:25:49.401512 WR_PST = 0x1
7243 00:25:49.401619 DBI_WR = 0x0
7244 00:25:49.404311 DBI_RD = 0x0
7245 00:25:49.404418 OTF = 0x1
7246 00:25:49.407923 ===================================
7247 00:25:49.411456 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7248 00:25:49.414383 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7249 00:25:49.421020 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7250 00:25:49.424546 ===================================
7251 00:25:49.428053 LPDDR4 DRAM CONFIGURATION
7252 00:25:49.430934 ===================================
7253 00:25:49.431028 EX_ROW_EN[0] = 0x10
7254 00:25:49.434435 EX_ROW_EN[1] = 0x0
7255 00:25:49.434510 LP4Y_EN = 0x0
7256 00:25:49.438062 WORK_FSP = 0x1
7257 00:25:49.438136 WL = 0x5
7258 00:25:49.440907 RL = 0x5
7259 00:25:49.440998 BL = 0x2
7260 00:25:49.444466 RPST = 0x0
7261 00:25:49.444561 RD_PRE = 0x0
7262 00:25:49.447941 WR_PRE = 0x1
7263 00:25:49.448032 WR_PST = 0x1
7264 00:25:49.450905 DBI_WR = 0x0
7265 00:25:49.450996 DBI_RD = 0x0
7266 00:25:49.454438 OTF = 0x1
7267 00:25:49.458038 ===================================
7268 00:25:49.464383 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7269 00:25:49.464487 ==
7270 00:25:49.468063 Dram Type= 6, Freq= 0, CH_0, rank 0
7271 00:25:49.471307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7272 00:25:49.471401 ==
7273 00:25:49.474334 [Duty_Offset_Calibration]
7274 00:25:49.474403 B0:2 B1:-1 CA:1
7275 00:25:49.474459
7276 00:25:49.477626 [DutyScan_Calibration_Flow] k_type=0
7277 00:25:49.488077
7278 00:25:49.488169 ==CLK 0==
7279 00:25:49.491667 Final CLK duty delay cell = -4
7280 00:25:49.494742 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7281 00:25:49.497817 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7282 00:25:49.501771 [-4] AVG Duty = 4922%(X100)
7283 00:25:49.501847
7284 00:25:49.504449 CH0 CLK Duty spec in!! Max-Min= 156%
7285 00:25:49.508136 [DutyScan_Calibration_Flow] ====Done====
7286 00:25:49.508212
7287 00:25:49.511451 [DutyScan_Calibration_Flow] k_type=1
7288 00:25:49.527561
7289 00:25:49.527643 ==DQS 0 ==
7290 00:25:49.530761 Final DQS duty delay cell = 0
7291 00:25:49.534240 [0] MAX Duty = 5125%(X100), DQS PI = 56
7292 00:25:49.537367 [0] MIN Duty = 5000%(X100), DQS PI = 14
7293 00:25:49.540958 [0] AVG Duty = 5062%(X100)
7294 00:25:49.541034
7295 00:25:49.541093 ==DQS 1 ==
7296 00:25:49.544554 Final DQS duty delay cell = -4
7297 00:25:49.547413 [-4] MAX Duty = 5093%(X100), DQS PI = 2
7298 00:25:49.550957 [-4] MIN Duty = 5000%(X100), DQS PI = 42
7299 00:25:49.554654 [-4] AVG Duty = 5046%(X100)
7300 00:25:49.554729
7301 00:25:49.557403 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7302 00:25:49.557478
7303 00:25:49.560914 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7304 00:25:49.564507 [DutyScan_Calibration_Flow] ====Done====
7305 00:25:49.564583
7306 00:25:49.567505 [DutyScan_Calibration_Flow] k_type=3
7307 00:25:49.584628
7308 00:25:49.584704 ==DQM 0 ==
7309 00:25:49.588332 Final DQM duty delay cell = 0
7310 00:25:49.591563 [0] MAX Duty = 5000%(X100), DQS PI = 20
7311 00:25:49.595148 [0] MIN Duty = 4875%(X100), DQS PI = 4
7312 00:25:49.595224 [0] AVG Duty = 4937%(X100)
7313 00:25:49.597978
7314 00:25:49.598075 ==DQM 1 ==
7315 00:25:49.601465 Final DQM duty delay cell = 0
7316 00:25:49.604980 [0] MAX Duty = 5218%(X100), DQS PI = 58
7317 00:25:49.608312 [0] MIN Duty = 4969%(X100), DQS PI = 18
7318 00:25:49.608388 [0] AVG Duty = 5093%(X100)
7319 00:25:49.611462
7320 00:25:49.614971 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7321 00:25:49.615048
7322 00:25:49.618383 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7323 00:25:49.621812 [DutyScan_Calibration_Flow] ====Done====
7324 00:25:49.621887
7325 00:25:49.625362 [DutyScan_Calibration_Flow] k_type=2
7326 00:25:49.642440
7327 00:25:49.642602 ==DQ 0 ==
7328 00:25:49.645679 Final DQ duty delay cell = 0
7329 00:25:49.649533 [0] MAX Duty = 5156%(X100), DQS PI = 0
7330 00:25:49.652492 [0] MIN Duty = 5031%(X100), DQS PI = 4
7331 00:25:49.652667 [0] AVG Duty = 5093%(X100)
7332 00:25:49.652758
7333 00:25:49.656071 ==DQ 1 ==
7334 00:25:49.659150 Final DQ duty delay cell = 0
7335 00:25:49.662559 [0] MAX Duty = 5000%(X100), DQS PI = 12
7336 00:25:49.665531 [0] MIN Duty = 4907%(X100), DQS PI = 18
7337 00:25:49.665739 [0] AVG Duty = 4953%(X100)
7338 00:25:49.665851
7339 00:25:49.669254 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7340 00:25:49.669480
7341 00:25:49.672617 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7342 00:25:49.679208 [DutyScan_Calibration_Flow] ====Done====
7343 00:25:49.679514 ==
7344 00:25:49.682426 Dram Type= 6, Freq= 0, CH_1, rank 0
7345 00:25:49.686058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7346 00:25:49.686421 ==
7347 00:25:49.689286 [Duty_Offset_Calibration]
7348 00:25:49.689749 B0:1 B1:1 CA:2
7349 00:25:49.690186
7350 00:25:49.692831 [DutyScan_Calibration_Flow] k_type=0
7351 00:25:49.702709
7352 00:25:49.703171 ==CLK 0==
7353 00:25:49.705896 Final CLK duty delay cell = 0
7354 00:25:49.709704 [0] MAX Duty = 5187%(X100), DQS PI = 24
7355 00:25:49.712298 [0] MIN Duty = 4969%(X100), DQS PI = 40
7356 00:25:49.712691 [0] AVG Duty = 5078%(X100)
7357 00:25:49.715917
7358 00:25:49.716307 CH1 CLK Duty spec in!! Max-Min= 218%
7359 00:25:49.722838 [DutyScan_Calibration_Flow] ====Done====
7360 00:25:49.723328
7361 00:25:49.725940 [DutyScan_Calibration_Flow] k_type=1
7362 00:25:49.742133
7363 00:25:49.742593 ==DQS 0 ==
7364 00:25:49.745900 Final DQS duty delay cell = 0
7365 00:25:49.748616 [0] MAX Duty = 5062%(X100), DQS PI = 20
7366 00:25:49.752310 [0] MIN Duty = 4813%(X100), DQS PI = 50
7367 00:25:49.755744 [0] AVG Duty = 4937%(X100)
7368 00:25:49.756133
7369 00:25:49.756448 ==DQS 1 ==
7370 00:25:49.758701 Final DQS duty delay cell = 0
7371 00:25:49.762383 [0] MAX Duty = 5031%(X100), DQS PI = 50
7372 00:25:49.765596 [0] MIN Duty = 4938%(X100), DQS PI = 0
7373 00:25:49.766015 [0] AVG Duty = 4984%(X100)
7374 00:25:49.769527
7375 00:25:49.772177 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7376 00:25:49.772570
7377 00:25:49.775544 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7378 00:25:49.779255 [DutyScan_Calibration_Flow] ====Done====
7379 00:25:49.779727
7380 00:25:49.782079 [DutyScan_Calibration_Flow] k_type=3
7381 00:25:49.799077
7382 00:25:49.799544 ==DQM 0 ==
7383 00:25:49.802173 Final DQM duty delay cell = 0
7384 00:25:49.805942 [0] MAX Duty = 5156%(X100), DQS PI = 20
7385 00:25:49.809422 [0] MIN Duty = 4844%(X100), DQS PI = 50
7386 00:25:49.812532 [0] AVG Duty = 5000%(X100)
7387 00:25:49.812918
7388 00:25:49.813216 ==DQM 1 ==
7389 00:25:49.815479 Final DQM duty delay cell = 0
7390 00:25:49.819212 [0] MAX Duty = 5125%(X100), DQS PI = 8
7391 00:25:49.822543 [0] MIN Duty = 4907%(X100), DQS PI = 22
7392 00:25:49.822933 [0] AVG Duty = 5016%(X100)
7393 00:25:49.825600
7394 00:25:49.829594 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7395 00:25:49.830121
7396 00:25:49.832659 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7397 00:25:49.835742 [DutyScan_Calibration_Flow] ====Done====
7398 00:25:49.836131
7399 00:25:49.838653 [DutyScan_Calibration_Flow] k_type=2
7400 00:25:49.855854
7401 00:25:49.856322 ==DQ 0 ==
7402 00:25:49.859550 Final DQ duty delay cell = 0
7403 00:25:49.862837 [0] MAX Duty = 5125%(X100), DQS PI = 20
7404 00:25:49.866212 [0] MIN Duty = 4907%(X100), DQS PI = 52
7405 00:25:49.866691 [0] AVG Duty = 5016%(X100)
7406 00:25:49.869569
7407 00:25:49.870088 ==DQ 1 ==
7408 00:25:49.872628 Final DQ duty delay cell = 0
7409 00:25:49.876002 [0] MAX Duty = 5093%(X100), DQS PI = 6
7410 00:25:49.878959 [0] MIN Duty = 5031%(X100), DQS PI = 0
7411 00:25:49.879347 [0] AVG Duty = 5062%(X100)
7412 00:25:49.879647
7413 00:25:49.882533 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7414 00:25:49.882916
7415 00:25:49.886299 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7416 00:25:49.892419 [DutyScan_Calibration_Flow] ====Done====
7417 00:25:49.896146 nWR fixed to 30
7418 00:25:49.896621 [ModeRegInit_LP4] CH0 RK0
7419 00:25:49.899235 [ModeRegInit_LP4] CH0 RK1
7420 00:25:49.902784 [ModeRegInit_LP4] CH1 RK0
7421 00:25:49.903264 [ModeRegInit_LP4] CH1 RK1
7422 00:25:49.905579 match AC timing 5
7423 00:25:49.909327 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7424 00:25:49.913424 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7425 00:25:49.919487 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7426 00:25:49.922896 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7427 00:25:49.929760 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7428 00:25:49.930292 [MiockJmeterHQA]
7429 00:25:49.930598
7430 00:25:49.932394 [DramcMiockJmeter] u1RxGatingPI = 0
7431 00:25:49.935738 0 : 4252, 4027
7432 00:25:49.936127 4 : 4253, 4027
7433 00:25:49.936434 8 : 4363, 4137
7434 00:25:49.938949 12 : 4253, 4026
7435 00:25:49.939344 16 : 4363, 4138
7436 00:25:49.942528 20 : 4253, 4026
7437 00:25:49.943003 24 : 4363, 4137
7438 00:25:49.945836 28 : 4253, 4026
7439 00:25:49.946333 32 : 4252, 4027
7440 00:25:49.946647 36 : 4250, 4027
7441 00:25:49.948973 40 : 4363, 4137
7442 00:25:49.949362 44 : 4361, 4138
7443 00:25:49.952765 48 : 4250, 4026
7444 00:25:49.953239 52 : 4250, 4027
7445 00:25:49.956238 56 : 4250, 4027
7446 00:25:49.956708 60 : 4250, 4026
7447 00:25:49.957022 64 : 4250, 4027
7448 00:25:49.959399 68 : 4360, 4137
7449 00:25:49.959873 72 : 4250, 4026
7450 00:25:49.962649 76 : 4250, 4027
7451 00:25:49.963122 80 : 4250, 4026
7452 00:25:49.966019 84 : 4250, 4027
7453 00:25:49.966498 88 : 4250, 4027
7454 00:25:49.969357 92 : 4361, 4137
7455 00:25:49.969866 96 : 4361, 3146
7456 00:25:49.970384 100 : 4253, 0
7457 00:25:49.972732 104 : 4360, 0
7458 00:25:49.973226 108 : 4250, 0
7459 00:25:49.975681 112 : 4250, 0
7460 00:25:49.976072 116 : 4250, 0
7461 00:25:49.976379 120 : 4250, 0
7462 00:25:49.979548 124 : 4250, 0
7463 00:25:49.980024 128 : 4250, 0
7464 00:25:49.980335 132 : 4250, 0
7465 00:25:49.982710 136 : 4361, 0
7466 00:25:49.983100 140 : 4360, 0
7467 00:25:49.986102 144 : 4250, 0
7468 00:25:49.986576 148 : 4249, 0
7469 00:25:49.986889 152 : 4361, 0
7470 00:25:49.989370 156 : 4250, 0
7471 00:25:49.989844 160 : 4250, 0
7472 00:25:49.992669 164 : 4250, 0
7473 00:25:49.993063 168 : 4250, 0
7474 00:25:49.993373 172 : 4250, 0
7475 00:25:49.996129 176 : 4250, 0
7476 00:25:49.996595 180 : 4249, 0
7477 00:25:49.999445 184 : 4250, 0
7478 00:25:49.999838 188 : 4361, 0
7479 00:25:50.000144 192 : 4360, 0
7480 00:25:50.002322 196 : 4361, 0
7481 00:25:50.002715 200 : 4250, 0
7482 00:25:50.003023 204 : 4250, 0
7483 00:25:50.005725 208 : 4250, 0
7484 00:25:50.006156 212 : 4250, 57
7485 00:25:50.009411 216 : 4360, 3958
7486 00:25:50.009880 220 : 4253, 4026
7487 00:25:50.012383 224 : 4250, 4027
7488 00:25:50.012776 228 : 4361, 4138
7489 00:25:50.015752 232 : 4250, 4027
7490 00:25:50.016147 236 : 4250, 4026
7491 00:25:50.019683 240 : 4250, 4027
7492 00:25:50.020075 244 : 4250, 4027
7493 00:25:50.020380 248 : 4250, 4027
7494 00:25:50.022645 252 : 4250, 4026
7495 00:25:50.023038 256 : 4363, 4137
7496 00:25:50.026139 260 : 4250, 4027
7497 00:25:50.026530 264 : 4250, 4027
7498 00:25:50.029435 268 : 4360, 4137
7499 00:25:50.029906 272 : 4250, 4026
7500 00:25:50.032953 276 : 4250, 4027
7501 00:25:50.033429 280 : 4361, 4138
7502 00:25:50.036387 284 : 4250, 4027
7503 00:25:50.036865 288 : 4250, 4026
7504 00:25:50.039181 292 : 4250, 4027
7505 00:25:50.039577 296 : 4250, 4027
7506 00:25:50.042427 300 : 4250, 4027
7507 00:25:50.042822 304 : 4250, 4026
7508 00:25:50.043131 308 : 4361, 4137
7509 00:25:50.045803 312 : 4250, 4027
7510 00:25:50.046236 316 : 4250, 4027
7511 00:25:50.049486 320 : 4360, 4137
7512 00:25:50.049877 324 : 4250, 4026
7513 00:25:50.052345 328 : 4250, 4027
7514 00:25:50.052810 332 : 4361, 3137
7515 00:25:50.055436 336 : 4250, 50
7516 00:25:50.055829
7517 00:25:50.056123 MIOCK jitter meter ch=0
7518 00:25:50.056401
7519 00:25:50.059152 1T = (336-100) = 236 dly cells
7520 00:25:50.065869 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7521 00:25:50.066383 ==
7522 00:25:50.069300 Dram Type= 6, Freq= 0, CH_0, rank 0
7523 00:25:50.072793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7524 00:25:50.073266 ==
7525 00:25:50.079336 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7526 00:25:50.082513 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7527 00:25:50.089093 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7528 00:25:50.092257 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7529 00:25:50.102176 [CA 0] Center 44 (14~75) winsize 62
7530 00:25:50.105340 [CA 1] Center 44 (14~75) winsize 62
7531 00:25:50.108716 [CA 2] Center 40 (11~69) winsize 59
7532 00:25:50.112446 [CA 3] Center 39 (10~69) winsize 60
7533 00:25:50.115777 [CA 4] Center 38 (8~68) winsize 61
7534 00:25:50.119106 [CA 5] Center 37 (7~67) winsize 61
7535 00:25:50.119492
7536 00:25:50.122609 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7537 00:25:50.122997
7538 00:25:50.125706 [CATrainingPosCal] consider 1 rank data
7539 00:25:50.129350 u2DelayCellTimex100 = 275/100 ps
7540 00:25:50.135562 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7541 00:25:50.139040 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7542 00:25:50.142514 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7543 00:25:50.146037 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7544 00:25:50.149300 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7545 00:25:50.152514 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7546 00:25:50.152903
7547 00:25:50.155961 CA PerBit enable=1, Macro0, CA PI delay=37
7548 00:25:50.156349
7549 00:25:50.158738 [CBTSetCACLKResult] CA Dly = 37
7550 00:25:50.162843 CS Dly: 11 (0~42)
7551 00:25:50.165665 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7552 00:25:50.169149 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7553 00:25:50.169618 ==
7554 00:25:50.172486 Dram Type= 6, Freq= 0, CH_0, rank 1
7555 00:25:50.175464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7556 00:25:50.179205 ==
7557 00:25:50.182943 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7558 00:25:50.186029 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7559 00:25:50.192757 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7560 00:25:50.196206 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7561 00:25:50.206446 [CA 0] Center 44 (14~75) winsize 62
7562 00:25:50.209726 [CA 1] Center 44 (14~75) winsize 62
7563 00:25:50.212480 [CA 2] Center 39 (10~69) winsize 60
7564 00:25:50.215902 [CA 3] Center 39 (10~69) winsize 60
7565 00:25:50.219291 [CA 4] Center 38 (8~68) winsize 61
7566 00:25:50.222787 [CA 5] Center 37 (7~67) winsize 61
7567 00:25:50.223177
7568 00:25:50.225959 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7569 00:25:50.226413
7570 00:25:50.229875 [CATrainingPosCal] consider 2 rank data
7571 00:25:50.233215 u2DelayCellTimex100 = 275/100 ps
7572 00:25:50.236525 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7573 00:25:50.242879 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7574 00:25:50.246512 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7575 00:25:50.249312 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7576 00:25:50.253060 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7577 00:25:50.256251 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7578 00:25:50.256637
7579 00:25:50.259378 CA PerBit enable=1, Macro0, CA PI delay=37
7580 00:25:50.259764
7581 00:25:50.262672 [CBTSetCACLKResult] CA Dly = 37
7582 00:25:50.266142 CS Dly: 11 (0~43)
7583 00:25:50.269938 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7584 00:25:50.273538 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7585 00:25:50.274040
7586 00:25:50.276384 ----->DramcWriteLeveling(PI) begin...
7587 00:25:50.276779 ==
7588 00:25:50.280019 Dram Type= 6, Freq= 0, CH_0, rank 0
7589 00:25:50.286520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7590 00:25:50.286988 ==
7591 00:25:50.290072 Write leveling (Byte 0): 33 => 33
7592 00:25:50.290560 Write leveling (Byte 1): 28 => 28
7593 00:25:50.293015 DramcWriteLeveling(PI) end<-----
7594 00:25:50.293481
7595 00:25:50.293783 ==
7596 00:25:50.296253 Dram Type= 6, Freq= 0, CH_0, rank 0
7597 00:25:50.302640 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7598 00:25:50.303105 ==
7599 00:25:50.306403 [Gating] SW mode calibration
7600 00:25:50.312960 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7601 00:25:50.316080 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7602 00:25:50.322788 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 00:25:50.326081 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 00:25:50.329151 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 00:25:50.336163 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 00:25:50.339264 1 4 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 00:25:50.342661 1 4 20 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7608 00:25:50.349719 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7609 00:25:50.353248 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7610 00:25:50.355925 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 00:25:50.362642 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7612 00:25:50.366334 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7613 00:25:50.369429 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7614 00:25:50.372767 1 5 16 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
7615 00:25:50.379493 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7616 00:25:50.382838 1 5 24 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
7617 00:25:50.385899 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 00:25:50.393103 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 00:25:50.395997 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 00:25:50.399570 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 00:25:50.406264 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7622 00:25:50.409244 1 6 16 | B1->B0 | 2323 3838 | 0 0 | (0 0) (1 1)
7623 00:25:50.412700 1 6 20 | B1->B0 | 2424 4444 | 0 0 | (0 0) (0 0)
7624 00:25:50.419155 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7625 00:25:50.422472 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 00:25:50.426191 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 00:25:50.432661 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 00:25:50.435993 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 00:25:50.439596 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7630 00:25:50.442849 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7631 00:25:50.449310 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7632 00:25:50.452826 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 00:25:50.456455 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 00:25:50.462814 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 00:25:50.466566 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 00:25:50.469738 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 00:25:50.475803 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 00:25:50.479339 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 00:25:50.482302 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 00:25:50.489464 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 00:25:50.492864 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 00:25:50.496092 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 00:25:50.503162 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 00:25:50.506468 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 00:25:50.509427 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 00:25:50.516271 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7647 00:25:50.519724 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7648 00:25:50.522564 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7649 00:25:50.525763 Total UI for P1: 0, mck2ui 16
7650 00:25:50.529019 best dqsien dly found for B0: ( 1, 9, 18)
7651 00:25:50.532689 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 00:25:50.536576 Total UI for P1: 0, mck2ui 16
7653 00:25:50.539255 best dqsien dly found for B1: ( 1, 9, 20)
7654 00:25:50.542894 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7655 00:25:50.549109 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7656 00:25:50.549511
7657 00:25:50.552366 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7658 00:25:50.555897 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7659 00:25:50.559851 [Gating] SW calibration Done
7660 00:25:50.560367 ==
7661 00:25:50.562730 Dram Type= 6, Freq= 0, CH_0, rank 0
7662 00:25:50.565866 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7663 00:25:50.566253 ==
7664 00:25:50.569169 RX Vref Scan: 0
7665 00:25:50.569553
7666 00:25:50.569851 RX Vref 0 -> 0, step: 1
7667 00:25:50.570182
7668 00:25:50.572727 RX Delay 0 -> 252, step: 8
7669 00:25:50.576249 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7670 00:25:50.579400 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7671 00:25:50.586126 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7672 00:25:50.589730 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7673 00:25:50.592521 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7674 00:25:50.596035 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7675 00:25:50.599804 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7676 00:25:50.605911 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7677 00:25:50.609738 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7678 00:25:50.612912 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7679 00:25:50.616512 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7680 00:25:50.619426 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7681 00:25:50.626270 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7682 00:25:50.629291 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7683 00:25:50.633077 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7684 00:25:50.635885 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7685 00:25:50.636276 ==
7686 00:25:50.639664 Dram Type= 6, Freq= 0, CH_0, rank 0
7687 00:25:50.642736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7688 00:25:50.646099 ==
7689 00:25:50.646494 DQS Delay:
7690 00:25:50.646794 DQS0 = 0, DQS1 = 0
7691 00:25:50.649641 DQM Delay:
7692 00:25:50.650071 DQM0 = 132, DQM1 = 123
7693 00:25:50.652715 DQ Delay:
7694 00:25:50.656253 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7695 00:25:50.659410 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7696 00:25:50.662796 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7697 00:25:50.666153 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7698 00:25:50.666540
7699 00:25:50.666864
7700 00:25:50.667180 ==
7701 00:25:50.669698 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 00:25:50.672710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 00:25:50.673065 ==
7704 00:25:50.673339
7705 00:25:50.676234
7706 00:25:50.676615 TX Vref Scan disable
7707 00:25:50.680081 == TX Byte 0 ==
7708 00:25:50.683036 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7709 00:25:50.686666 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7710 00:25:50.689846 == TX Byte 1 ==
7711 00:25:50.692988 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7712 00:25:50.696537 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7713 00:25:50.697012 ==
7714 00:25:50.699807 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 00:25:50.706059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 00:25:50.706421 ==
7717 00:25:50.718453
7718 00:25:50.721923 TX Vref early break, caculate TX vref
7719 00:25:50.725081 TX Vref=16, minBit 1, minWin=21, winSum=363
7720 00:25:50.728278 TX Vref=18, minBit 0, minWin=22, winSum=375
7721 00:25:50.731713 TX Vref=20, minBit 4, minWin=23, winSum=388
7722 00:25:50.734684 TX Vref=22, minBit 0, minWin=24, winSum=394
7723 00:25:50.738266 TX Vref=24, minBit 4, minWin=24, winSum=409
7724 00:25:50.741742 TX Vref=26, minBit 1, minWin=25, winSum=423
7725 00:25:50.748601 TX Vref=28, minBit 4, minWin=25, winSum=426
7726 00:25:50.752029 TX Vref=30, minBit 3, minWin=25, winSum=421
7727 00:25:50.755325 TX Vref=32, minBit 2, minWin=24, winSum=413
7728 00:25:50.758388 TX Vref=34, minBit 0, minWin=24, winSum=403
7729 00:25:50.765285 [TxChooseVref] Worse bit 4, Min win 25, Win sum 426, Final Vref 28
7730 00:25:50.765769
7731 00:25:50.768864 Final TX Range 0 Vref 28
7732 00:25:50.769349
7733 00:25:50.769697 ==
7734 00:25:50.771797 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 00:25:50.775383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 00:25:50.775866 ==
7737 00:25:50.776190
7738 00:25:50.776483
7739 00:25:50.778598 TX Vref Scan disable
7740 00:25:50.785567 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7741 00:25:50.786082 == TX Byte 0 ==
7742 00:25:50.788495 u2DelayCellOfst[0]=17 cells (5 PI)
7743 00:25:50.791811 u2DelayCellOfst[1]=21 cells (6 PI)
7744 00:25:50.795398 u2DelayCellOfst[2]=10 cells (3 PI)
7745 00:25:50.798946 u2DelayCellOfst[3]=14 cells (4 PI)
7746 00:25:50.802344 u2DelayCellOfst[4]=10 cells (3 PI)
7747 00:25:50.804949 u2DelayCellOfst[5]=0 cells (0 PI)
7748 00:25:50.805362 u2DelayCellOfst[6]=21 cells (6 PI)
7749 00:25:50.808471 u2DelayCellOfst[7]=21 cells (6 PI)
7750 00:25:50.815398 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7751 00:25:50.818552 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7752 00:25:50.819055 == TX Byte 1 ==
7753 00:25:50.822365 u2DelayCellOfst[8]=3 cells (1 PI)
7754 00:25:50.825598 u2DelayCellOfst[9]=0 cells (0 PI)
7755 00:25:50.829063 u2DelayCellOfst[10]=10 cells (3 PI)
7756 00:25:50.832251 u2DelayCellOfst[11]=3 cells (1 PI)
7757 00:25:50.835626 u2DelayCellOfst[12]=14 cells (4 PI)
7758 00:25:50.839024 u2DelayCellOfst[13]=14 cells (4 PI)
7759 00:25:50.842342 u2DelayCellOfst[14]=17 cells (5 PI)
7760 00:25:50.845551 u2DelayCellOfst[15]=14 cells (4 PI)
7761 00:25:50.848920 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7762 00:25:50.852257 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7763 00:25:50.855326 DramC Write-DBI on
7764 00:25:50.855726 ==
7765 00:25:50.858676 Dram Type= 6, Freq= 0, CH_0, rank 0
7766 00:25:50.862611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7767 00:25:50.863092 ==
7768 00:25:50.863398
7769 00:25:50.863677
7770 00:25:50.866109 TX Vref Scan disable
7771 00:25:50.868808 == TX Byte 0 ==
7772 00:25:50.871896 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7773 00:25:50.872285 == TX Byte 1 ==
7774 00:25:50.878681 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7775 00:25:50.879184 DramC Write-DBI off
7776 00:25:50.879581
7777 00:25:50.882154 [DATLAT]
7778 00:25:50.882631 Freq=1600, CH0 RK0
7779 00:25:50.883035
7780 00:25:50.885851 DATLAT Default: 0xf
7781 00:25:50.886388 0, 0xFFFF, sum = 0
7782 00:25:50.888805 1, 0xFFFF, sum = 0
7783 00:25:50.889293 2, 0xFFFF, sum = 0
7784 00:25:50.892067 3, 0xFFFF, sum = 0
7785 00:25:50.892473 4, 0xFFFF, sum = 0
7786 00:25:50.895927 5, 0xFFFF, sum = 0
7787 00:25:50.896415 6, 0xFFFF, sum = 0
7788 00:25:50.898663 7, 0xFFFF, sum = 0
7789 00:25:50.899065 8, 0xFFFF, sum = 0
7790 00:25:50.902614 9, 0xFFFF, sum = 0
7791 00:25:50.903102 10, 0xFFFF, sum = 0
7792 00:25:50.905196 11, 0xFFFF, sum = 0
7793 00:25:50.905612 12, 0xFFFF, sum = 0
7794 00:25:50.908380 13, 0xFFFF, sum = 0
7795 00:25:50.912177 14, 0x0, sum = 1
7796 00:25:50.912601 15, 0x0, sum = 2
7797 00:25:50.912999 16, 0x0, sum = 3
7798 00:25:50.914965 17, 0x0, sum = 4
7799 00:25:50.915369 best_step = 15
7800 00:25:50.915766
7801 00:25:50.916136 ==
7802 00:25:50.918400 Dram Type= 6, Freq= 0, CH_0, rank 0
7803 00:25:50.925384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7804 00:25:50.925868 ==
7805 00:25:50.926309 RX Vref Scan: 1
7806 00:25:50.926677
7807 00:25:50.929262 Set Vref Range= 24 -> 127
7808 00:25:50.929657
7809 00:25:50.932204 RX Vref 24 -> 127, step: 1
7810 00:25:50.932607
7811 00:25:50.932997 RX Delay 11 -> 252, step: 4
7812 00:25:50.935441
7813 00:25:50.935838 Set Vref, RX VrefLevel [Byte0]: 24
7814 00:25:50.938844 [Byte1]: 24
7815 00:25:50.943325
7816 00:25:50.943724 Set Vref, RX VrefLevel [Byte0]: 25
7817 00:25:50.946294 [Byte1]: 25
7818 00:25:50.950431
7819 00:25:50.950827 Set Vref, RX VrefLevel [Byte0]: 26
7820 00:25:50.954080 [Byte1]: 26
7821 00:25:50.958337
7822 00:25:50.958733 Set Vref, RX VrefLevel [Byte0]: 27
7823 00:25:50.961246 [Byte1]: 27
7824 00:25:50.965697
7825 00:25:50.966204 Set Vref, RX VrefLevel [Byte0]: 28
7826 00:25:50.969075 [Byte1]: 28
7827 00:25:50.973551
7828 00:25:50.974026 Set Vref, RX VrefLevel [Byte0]: 29
7829 00:25:50.976703 [Byte1]: 29
7830 00:25:50.981391
7831 00:25:50.981845 Set Vref, RX VrefLevel [Byte0]: 30
7832 00:25:50.984544 [Byte1]: 30
7833 00:25:50.988691
7834 00:25:50.989143 Set Vref, RX VrefLevel [Byte0]: 31
7835 00:25:50.991710 [Byte1]: 31
7836 00:25:50.996472
7837 00:25:50.996927 Set Vref, RX VrefLevel [Byte0]: 32
7838 00:25:51.000116 [Byte1]: 32
7839 00:25:51.004000
7840 00:25:51.004411 Set Vref, RX VrefLevel [Byte0]: 33
7841 00:25:51.007015 [Byte1]: 33
7842 00:25:51.011760
7843 00:25:51.012123 Set Vref, RX VrefLevel [Byte0]: 34
7844 00:25:51.015013 [Byte1]: 34
7845 00:25:51.018811
7846 00:25:51.019177 Set Vref, RX VrefLevel [Byte0]: 35
7847 00:25:51.022721 [Byte1]: 35
7848 00:25:51.026605
7849 00:25:51.026962 Set Vref, RX VrefLevel [Byte0]: 36
7850 00:25:51.030302 [Byte1]: 36
7851 00:25:51.034439
7852 00:25:51.034801 Set Vref, RX VrefLevel [Byte0]: 37
7853 00:25:51.037284 [Byte1]: 37
7854 00:25:51.041930
7855 00:25:51.042318 Set Vref, RX VrefLevel [Byte0]: 38
7856 00:25:51.045213 [Byte1]: 38
7857 00:25:51.049436
7858 00:25:51.049914 Set Vref, RX VrefLevel [Byte0]: 39
7859 00:25:51.052921 [Byte1]: 39
7860 00:25:51.056838
7861 00:25:51.057296 Set Vref, RX VrefLevel [Byte0]: 40
7862 00:25:51.060354 [Byte1]: 40
7863 00:25:51.065070
7864 00:25:51.065423 Set Vref, RX VrefLevel [Byte0]: 41
7865 00:25:51.068117 [Byte1]: 41
7866 00:25:51.072501
7867 00:25:51.072965 Set Vref, RX VrefLevel [Byte0]: 42
7868 00:25:51.076177 [Byte1]: 42
7869 00:25:51.080228
7870 00:25:51.080596 Set Vref, RX VrefLevel [Byte0]: 43
7871 00:25:51.083753 [Byte1]: 43
7872 00:25:51.087650
7873 00:25:51.088092 Set Vref, RX VrefLevel [Byte0]: 44
7874 00:25:51.090931 [Byte1]: 44
7875 00:25:51.095332
7876 00:25:51.095684 Set Vref, RX VrefLevel [Byte0]: 45
7877 00:25:51.098544 [Byte1]: 45
7878 00:25:51.102619
7879 00:25:51.102970 Set Vref, RX VrefLevel [Byte0]: 46
7880 00:25:51.106299 [Byte1]: 46
7881 00:25:51.110991
7882 00:25:51.111460 Set Vref, RX VrefLevel [Byte0]: 47
7883 00:25:51.113713 [Byte1]: 47
7884 00:25:51.118493
7885 00:25:51.118974 Set Vref, RX VrefLevel [Byte0]: 48
7886 00:25:51.121521 [Byte1]: 48
7887 00:25:51.126298
7888 00:25:51.126781 Set Vref, RX VrefLevel [Byte0]: 49
7889 00:25:51.128847 [Byte1]: 49
7890 00:25:51.133805
7891 00:25:51.134323 Set Vref, RX VrefLevel [Byte0]: 50
7892 00:25:51.136754 [Byte1]: 50
7893 00:25:51.141401
7894 00:25:51.141883 Set Vref, RX VrefLevel [Byte0]: 51
7895 00:25:51.144392 [Byte1]: 51
7896 00:25:51.149068
7897 00:25:51.149556 Set Vref, RX VrefLevel [Byte0]: 52
7898 00:25:51.151684 [Byte1]: 52
7899 00:25:51.156378
7900 00:25:51.156774 Set Vref, RX VrefLevel [Byte0]: 53
7901 00:25:51.159217 [Byte1]: 53
7902 00:25:51.164038
7903 00:25:51.164519 Set Vref, RX VrefLevel [Byte0]: 54
7904 00:25:51.167149 [Byte1]: 54
7905 00:25:51.171255
7906 00:25:51.171649 Set Vref, RX VrefLevel [Byte0]: 55
7907 00:25:51.175320 [Byte1]: 55
7908 00:25:51.178967
7909 00:25:51.179363 Set Vref, RX VrefLevel [Byte0]: 56
7910 00:25:51.182423 [Byte1]: 56
7911 00:25:51.186765
7912 00:25:51.187252 Set Vref, RX VrefLevel [Byte0]: 57
7913 00:25:51.190178 [Byte1]: 57
7914 00:25:51.194174
7915 00:25:51.194671 Set Vref, RX VrefLevel [Byte0]: 58
7916 00:25:51.197864 [Byte1]: 58
7917 00:25:51.202240
7918 00:25:51.202716 Set Vref, RX VrefLevel [Byte0]: 59
7919 00:25:51.205388 [Byte1]: 59
7920 00:25:51.210064
7921 00:25:51.210546 Set Vref, RX VrefLevel [Byte0]: 60
7922 00:25:51.213265 [Byte1]: 60
7923 00:25:51.217443
7924 00:25:51.217918 Set Vref, RX VrefLevel [Byte0]: 61
7925 00:25:51.220166 [Byte1]: 61
7926 00:25:51.224970
7927 00:25:51.225448 Set Vref, RX VrefLevel [Byte0]: 62
7928 00:25:51.228195 [Byte1]: 62
7929 00:25:51.232581
7930 00:25:51.233066 Set Vref, RX VrefLevel [Byte0]: 63
7931 00:25:51.236042 [Byte1]: 63
7932 00:25:51.239781
7933 00:25:51.240175 Set Vref, RX VrefLevel [Byte0]: 64
7934 00:25:51.243639 [Byte1]: 64
7935 00:25:51.247706
7936 00:25:51.248178 Set Vref, RX VrefLevel [Byte0]: 65
7937 00:25:51.251053 [Byte1]: 65
7938 00:25:51.255489
7939 00:25:51.255963 Set Vref, RX VrefLevel [Byte0]: 66
7940 00:25:51.258604 [Byte1]: 66
7941 00:25:51.262820
7942 00:25:51.263292 Set Vref, RX VrefLevel [Byte0]: 67
7943 00:25:51.265842 [Byte1]: 67
7944 00:25:51.270696
7945 00:25:51.271169 Set Vref, RX VrefLevel [Byte0]: 68
7946 00:25:51.273746 [Byte1]: 68
7947 00:25:51.278144
7948 00:25:51.278599 Set Vref, RX VrefLevel [Byte0]: 69
7949 00:25:51.281753 [Byte1]: 69
7950 00:25:51.285844
7951 00:25:51.286355 Set Vref, RX VrefLevel [Byte0]: 70
7952 00:25:51.289270 [Byte1]: 70
7953 00:25:51.293433
7954 00:25:51.293824 Set Vref, RX VrefLevel [Byte0]: 71
7955 00:25:51.296598 [Byte1]: 71
7956 00:25:51.301107
7957 00:25:51.301598 Set Vref, RX VrefLevel [Byte0]: 72
7958 00:25:51.304074 [Byte1]: 72
7959 00:25:51.308844
7960 00:25:51.309319 Set Vref, RX VrefLevel [Byte0]: 73
7961 00:25:51.311818 [Byte1]: 73
7962 00:25:51.316154
7963 00:25:51.316638 Set Vref, RX VrefLevel [Byte0]: 74
7964 00:25:51.319578 [Byte1]: 74
7965 00:25:51.324159
7966 00:25:51.324629 Set Vref, RX VrefLevel [Byte0]: 75
7967 00:25:51.326616 [Byte1]: 75
7968 00:25:51.331501
7969 00:25:51.331989 Set Vref, RX VrefLevel [Byte0]: 76
7970 00:25:51.334761 [Byte1]: 76
7971 00:25:51.338663
7972 00:25:51.339057 Final RX Vref Byte 0 = 61 to rank0
7973 00:25:51.342749 Final RX Vref Byte 1 = 63 to rank0
7974 00:25:51.345478 Final RX Vref Byte 0 = 61 to rank1
7975 00:25:51.349477 Final RX Vref Byte 1 = 63 to rank1==
7976 00:25:51.352265 Dram Type= 6, Freq= 0, CH_0, rank 0
7977 00:25:51.355818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7978 00:25:51.358956 ==
7979 00:25:51.359431 DQS Delay:
7980 00:25:51.359737 DQS0 = 0, DQS1 = 0
7981 00:25:51.362412 DQM Delay:
7982 00:25:51.362886 DQM0 = 130, DQM1 = 121
7983 00:25:51.365594 DQ Delay:
7984 00:25:51.369183 DQ0 =132, DQ1 =132, DQ2 =126, DQ3 =126
7985 00:25:51.372168 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7986 00:25:51.375728 DQ8 =110, DQ9 =108, DQ10 =122, DQ11 =116
7987 00:25:51.378906 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
7988 00:25:51.379301
7989 00:25:51.379602
7990 00:25:51.379878
7991 00:25:51.382917 [DramC_TX_OE_Calibration] TA2
7992 00:25:51.385640 Original DQ_B0 (3 6) =30, OEN = 27
7993 00:25:51.389326 Original DQ_B1 (3 6) =30, OEN = 27
7994 00:25:51.392262 24, 0x0, End_B0=24 End_B1=24
7995 00:25:51.392743 25, 0x0, End_B0=25 End_B1=25
7996 00:25:51.395474 26, 0x0, End_B0=26 End_B1=26
7997 00:25:51.399548 27, 0x0, End_B0=27 End_B1=27
7998 00:25:51.402116 28, 0x0, End_B0=28 End_B1=28
7999 00:25:51.402605 29, 0x0, End_B0=29 End_B1=29
8000 00:25:51.405759 30, 0x0, End_B0=30 End_B1=30
8001 00:25:51.409088 31, 0x4141, End_B0=30 End_B1=30
8002 00:25:51.412096 Byte0 end_step=30 best_step=27
8003 00:25:51.415991 Byte1 end_step=30 best_step=27
8004 00:25:51.418658 Byte0 TX OE(2T, 0.5T) = (3, 3)
8005 00:25:51.419056 Byte1 TX OE(2T, 0.5T) = (3, 3)
8006 00:25:51.419457
8007 00:25:51.419749
8008 00:25:51.428892 [DQSOSCAuto] RK0, (LSB)MR18= 0x170a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
8009 00:25:51.432366 CH0 RK0: MR19=303, MR18=170A
8010 00:25:51.438678 CH0_RK0: MR19=0x303, MR18=0x170A, DQSOSC=398, MR23=63, INC=23, DEC=15
8011 00:25:51.439147
8012 00:25:51.442168 ----->DramcWriteLeveling(PI) begin...
8013 00:25:51.442573 ==
8014 00:25:51.445916 Dram Type= 6, Freq= 0, CH_0, rank 1
8015 00:25:51.449334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8016 00:25:51.449819 ==
8017 00:25:51.451931 Write leveling (Byte 0): 33 => 33
8018 00:25:51.455758 Write leveling (Byte 1): 26 => 26
8019 00:25:51.458962 DramcWriteLeveling(PI) end<-----
8020 00:25:51.459365
8021 00:25:51.459759 ==
8022 00:25:51.462760 Dram Type= 6, Freq= 0, CH_0, rank 1
8023 00:25:51.465796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8024 00:25:51.466321 ==
8025 00:25:51.468877 [Gating] SW mode calibration
8026 00:25:51.475205 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8027 00:25:51.482142 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8028 00:25:51.485895 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 00:25:51.489350 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 00:25:51.495914 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 00:25:51.498654 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8032 00:25:51.502353 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8033 00:25:51.508903 1 4 20 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
8034 00:25:51.512829 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8035 00:25:51.515476 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8036 00:25:51.519027 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8037 00:25:51.525913 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8038 00:25:51.528761 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8039 00:25:51.532701 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
8040 00:25:51.538973 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8041 00:25:51.542460 1 5 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
8042 00:25:51.545589 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8043 00:25:51.552189 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8044 00:25:51.555940 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8045 00:25:51.559067 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 00:25:51.565834 1 6 8 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
8047 00:25:51.568811 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8048 00:25:51.572173 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8049 00:25:51.579267 1 6 20 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
8050 00:25:51.582732 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8051 00:25:51.585938 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 00:25:51.592793 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 00:25:51.596269 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 00:25:51.599140 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8055 00:25:51.602956 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8056 00:25:51.609561 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8057 00:25:51.613079 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8058 00:25:51.615796 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8059 00:25:51.622671 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 00:25:51.625920 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 00:25:51.629461 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 00:25:51.636271 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 00:25:51.639093 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 00:25:51.642551 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 00:25:51.649871 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 00:25:51.653279 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 00:25:51.656665 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 00:25:51.659660 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 00:25:51.666236 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 00:25:51.669687 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8071 00:25:51.672851 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8072 00:25:51.676083 Total UI for P1: 0, mck2ui 16
8073 00:25:51.679530 best dqsien dly found for B0: ( 1, 9, 8)
8074 00:25:51.685784 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8075 00:25:51.689105 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8076 00:25:51.692858 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 00:25:51.696380 Total UI for P1: 0, mck2ui 16
8078 00:25:51.699328 best dqsien dly found for B1: ( 1, 9, 18)
8079 00:25:51.702894 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8080 00:25:51.705823 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8081 00:25:51.706253
8082 00:25:51.712885 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8083 00:25:51.716396 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8084 00:25:51.719258 [Gating] SW calibration Done
8085 00:25:51.719644 ==
8086 00:25:51.722602 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 00:25:51.725971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 00:25:51.726404 ==
8089 00:25:51.726713 RX Vref Scan: 0
8090 00:25:51.727023
8091 00:25:51.729479 RX Vref 0 -> 0, step: 1
8092 00:25:51.729868
8093 00:25:51.733122 RX Delay 0 -> 252, step: 8
8094 00:25:51.735998 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8095 00:25:51.739500 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8096 00:25:51.742537 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8097 00:25:51.749566 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8098 00:25:51.752533 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8099 00:25:51.756506 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8100 00:25:51.759543 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8101 00:25:51.763379 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8102 00:25:51.769853 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8103 00:25:51.772985 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8104 00:25:51.776700 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8105 00:25:51.779289 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8106 00:25:51.783137 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8107 00:25:51.789883 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8108 00:25:51.792811 iDelay=200, Bit 14, Center 135 (72 ~ 199) 128
8109 00:25:51.796193 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8110 00:25:51.796600 ==
8111 00:25:51.799684 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 00:25:51.802724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 00:25:51.803118 ==
8114 00:25:51.806123 DQS Delay:
8115 00:25:51.806518 DQS0 = 0, DQS1 = 0
8116 00:25:51.809789 DQM Delay:
8117 00:25:51.810361 DQM0 = 131, DQM1 = 124
8118 00:25:51.810677 DQ Delay:
8119 00:25:51.812905 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =127
8120 00:25:51.819472 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8121 00:25:51.822963 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8122 00:25:51.825941 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8123 00:25:51.826374
8124 00:25:51.826679
8125 00:25:51.826960 ==
8126 00:25:51.829457 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 00:25:51.832994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 00:25:51.833387 ==
8129 00:25:51.833690
8130 00:25:51.833969
8131 00:25:51.836006 TX Vref Scan disable
8132 00:25:51.839348 == TX Byte 0 ==
8133 00:25:51.842826 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8134 00:25:51.846689 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8135 00:25:51.849802 == TX Byte 1 ==
8136 00:25:51.853091 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8137 00:25:51.856876 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8138 00:25:51.857358 ==
8139 00:25:51.859798 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 00:25:51.863355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 00:25:51.863853 ==
8142 00:25:51.879125
8143 00:25:51.882848 TX Vref early break, caculate TX vref
8144 00:25:51.886376 TX Vref=16, minBit 3, minWin=22, winSum=370
8145 00:25:51.889911 TX Vref=18, minBit 8, minWin=22, winSum=380
8146 00:25:51.892831 TX Vref=20, minBit 8, minWin=23, winSum=390
8147 00:25:51.896318 TX Vref=22, minBit 0, minWin=24, winSum=398
8148 00:25:51.899782 TX Vref=24, minBit 7, minWin=24, winSum=405
8149 00:25:51.906178 TX Vref=26, minBit 9, minWin=24, winSum=415
8150 00:25:51.909202 TX Vref=28, minBit 0, minWin=26, winSum=422
8151 00:25:51.912966 TX Vref=30, minBit 4, minWin=25, winSum=421
8152 00:25:51.916091 TX Vref=32, minBit 1, minWin=25, winSum=413
8153 00:25:51.919616 TX Vref=34, minBit 8, minWin=24, winSum=403
8154 00:25:51.922821 TX Vref=36, minBit 0, minWin=24, winSum=395
8155 00:25:51.929284 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 28
8156 00:25:51.929772
8157 00:25:51.932593 Final TX Range 0 Vref 28
8158 00:25:51.933074
8159 00:25:51.933477 ==
8160 00:25:51.935801 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 00:25:51.939538 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 00:25:51.939940 ==
8163 00:25:51.940332
8164 00:25:51.940701
8165 00:25:51.942513 TX Vref Scan disable
8166 00:25:51.949446 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8167 00:25:51.949850 == TX Byte 0 ==
8168 00:25:51.953174 u2DelayCellOfst[0]=14 cells (4 PI)
8169 00:25:51.955768 u2DelayCellOfst[1]=21 cells (6 PI)
8170 00:25:51.959300 u2DelayCellOfst[2]=10 cells (3 PI)
8171 00:25:51.962889 u2DelayCellOfst[3]=14 cells (4 PI)
8172 00:25:51.966480 u2DelayCellOfst[4]=10 cells (3 PI)
8173 00:25:51.970132 u2DelayCellOfst[5]=0 cells (0 PI)
8174 00:25:51.972674 u2DelayCellOfst[6]=21 cells (6 PI)
8175 00:25:51.976184 u2DelayCellOfst[7]=17 cells (5 PI)
8176 00:25:51.979304 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8177 00:25:51.982889 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8178 00:25:51.986417 == TX Byte 1 ==
8179 00:25:51.986905 u2DelayCellOfst[8]=0 cells (0 PI)
8180 00:25:51.989430 u2DelayCellOfst[9]=0 cells (0 PI)
8181 00:25:51.992887 u2DelayCellOfst[10]=3 cells (1 PI)
8182 00:25:51.996426 u2DelayCellOfst[11]=0 cells (0 PI)
8183 00:25:51.999971 u2DelayCellOfst[12]=10 cells (3 PI)
8184 00:25:52.002658 u2DelayCellOfst[13]=10 cells (3 PI)
8185 00:25:52.006568 u2DelayCellOfst[14]=14 cells (4 PI)
8186 00:25:52.009769 u2DelayCellOfst[15]=10 cells (3 PI)
8187 00:25:52.012878 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8188 00:25:52.020126 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8189 00:25:52.020616 DramC Write-DBI on
8190 00:25:52.021018 ==
8191 00:25:52.022686 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 00:25:52.026036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 00:25:52.026439 ==
8194 00:25:52.029344
8195 00:25:52.029739
8196 00:25:52.030255 TX Vref Scan disable
8197 00:25:52.032820 == TX Byte 0 ==
8198 00:25:52.036433 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8199 00:25:52.039620 == TX Byte 1 ==
8200 00:25:52.042433 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8201 00:25:52.045789 DramC Write-DBI off
8202 00:25:52.046220
8203 00:25:52.046523 [DATLAT]
8204 00:25:52.046806 Freq=1600, CH0 RK1
8205 00:25:52.047076
8206 00:25:52.049552 DATLAT Default: 0xf
8207 00:25:52.050068 0, 0xFFFF, sum = 0
8208 00:25:52.052670 1, 0xFFFF, sum = 0
8209 00:25:52.053065 2, 0xFFFF, sum = 0
8210 00:25:52.056412 3, 0xFFFF, sum = 0
8211 00:25:52.059053 4, 0xFFFF, sum = 0
8212 00:25:52.059447 5, 0xFFFF, sum = 0
8213 00:25:52.063118 6, 0xFFFF, sum = 0
8214 00:25:52.063607 7, 0xFFFF, sum = 0
8215 00:25:52.066292 8, 0xFFFF, sum = 0
8216 00:25:52.066774 9, 0xFFFF, sum = 0
8217 00:25:52.069526 10, 0xFFFF, sum = 0
8218 00:25:52.070052 11, 0xFFFF, sum = 0
8219 00:25:52.072891 12, 0xFFFF, sum = 0
8220 00:25:52.073363 13, 0xFFFF, sum = 0
8221 00:25:52.075883 14, 0x0, sum = 1
8222 00:25:52.076278 15, 0x0, sum = 2
8223 00:25:52.079296 16, 0x0, sum = 3
8224 00:25:52.079689 17, 0x0, sum = 4
8225 00:25:52.079999 best_step = 15
8226 00:25:52.082851
8227 00:25:52.083324 ==
8228 00:25:52.086561 Dram Type= 6, Freq= 0, CH_0, rank 1
8229 00:25:52.089462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8230 00:25:52.089850 ==
8231 00:25:52.090202 RX Vref Scan: 0
8232 00:25:52.090483
8233 00:25:52.092883 RX Vref 0 -> 0, step: 1
8234 00:25:52.093269
8235 00:25:52.096385 RX Delay 11 -> 252, step: 4
8236 00:25:52.099673 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8237 00:25:52.103462 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8238 00:25:52.109798 iDelay=191, Bit 2, Center 126 (71 ~ 182) 112
8239 00:25:52.113355 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8240 00:25:52.116119 iDelay=191, Bit 4, Center 128 (75 ~ 182) 108
8241 00:25:52.119808 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8242 00:25:52.123152 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8243 00:25:52.129638 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8244 00:25:52.133134 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8245 00:25:52.136752 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8246 00:25:52.139393 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8247 00:25:52.143561 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8248 00:25:52.150027 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8249 00:25:52.153345 iDelay=191, Bit 13, Center 126 (71 ~ 182) 112
8250 00:25:52.156619 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8251 00:25:52.159497 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8252 00:25:52.159890 ==
8253 00:25:52.163336 Dram Type= 6, Freq= 0, CH_0, rank 1
8254 00:25:52.169732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8255 00:25:52.170242 ==
8256 00:25:52.170551 DQS Delay:
8257 00:25:52.170832 DQS0 = 0, DQS1 = 0
8258 00:25:52.173098 DQM Delay:
8259 00:25:52.173569 DQM0 = 127, DQM1 = 122
8260 00:25:52.176701 DQ Delay:
8261 00:25:52.179674 DQ0 =126, DQ1 =130, DQ2 =126, DQ3 =126
8262 00:25:52.182760 DQ4 =128, DQ5 =116, DQ6 =134, DQ7 =136
8263 00:25:52.186570 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8264 00:25:52.189617 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130
8265 00:25:52.190130
8266 00:25:52.190445
8267 00:25:52.190725
8268 00:25:52.193393 [DramC_TX_OE_Calibration] TA2
8269 00:25:52.196472 Original DQ_B0 (3 6) =30, OEN = 27
8270 00:25:52.199814 Original DQ_B1 (3 6) =30, OEN = 27
8271 00:25:52.203223 24, 0x0, End_B0=24 End_B1=24
8272 00:25:52.203694 25, 0x0, End_B0=25 End_B1=25
8273 00:25:52.206033 26, 0x0, End_B0=26 End_B1=26
8274 00:25:52.210025 27, 0x0, End_B0=27 End_B1=27
8275 00:25:52.213501 28, 0x0, End_B0=28 End_B1=28
8276 00:25:52.213975 29, 0x0, End_B0=29 End_B1=29
8277 00:25:52.216180 30, 0x0, End_B0=30 End_B1=30
8278 00:25:52.219856 31, 0x5151, End_B0=30 End_B1=30
8279 00:25:52.223064 Byte0 end_step=30 best_step=27
8280 00:25:52.226484 Byte1 end_step=30 best_step=27
8281 00:25:52.229771 Byte0 TX OE(2T, 0.5T) = (3, 3)
8282 00:25:52.230218 Byte1 TX OE(2T, 0.5T) = (3, 3)
8283 00:25:52.230611
8284 00:25:52.233016
8285 00:25:52.239755 [DQSOSCAuto] RK1, (LSB)MR18= 0x180d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8286 00:25:52.242786 CH0 RK1: MR19=303, MR18=180D
8287 00:25:52.249447 CH0_RK1: MR19=0x303, MR18=0x180D, DQSOSC=397, MR23=63, INC=23, DEC=15
8288 00:25:52.249882 [RxdqsGatingPostProcess] freq 1600
8289 00:25:52.256353 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8290 00:25:52.259833 best DQS0 dly(2T, 0.5T) = (1, 1)
8291 00:25:52.262916 best DQS1 dly(2T, 0.5T) = (1, 1)
8292 00:25:52.266321 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8293 00:25:52.269249 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8294 00:25:52.272704 best DQS0 dly(2T, 0.5T) = (1, 1)
8295 00:25:52.276356 best DQS1 dly(2T, 0.5T) = (1, 1)
8296 00:25:52.279850 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8297 00:25:52.282983 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8298 00:25:52.283252 Pre-setting of DQS Precalculation
8299 00:25:52.289795 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8300 00:25:52.290087 ==
8301 00:25:52.293354 Dram Type= 6, Freq= 0, CH_1, rank 0
8302 00:25:52.296282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8303 00:25:52.296530 ==
8304 00:25:52.303244 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8305 00:25:52.306451 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8306 00:25:52.309832 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8307 00:25:52.316377 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8308 00:25:52.326123 [CA 0] Center 42 (13~71) winsize 59
8309 00:25:52.329442 [CA 1] Center 41 (12~71) winsize 60
8310 00:25:52.332742 [CA 2] Center 37 (9~66) winsize 58
8311 00:25:52.335728 [CA 3] Center 36 (7~65) winsize 59
8312 00:25:52.338939 [CA 4] Center 37 (8~67) winsize 60
8313 00:25:52.342220 [CA 5] Center 36 (6~66) winsize 61
8314 00:25:52.342608
8315 00:25:52.346213 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8316 00:25:52.346699
8317 00:25:52.349124 [CATrainingPosCal] consider 1 rank data
8318 00:25:52.352770 u2DelayCellTimex100 = 275/100 ps
8319 00:25:52.356223 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8320 00:25:52.362329 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8321 00:25:52.366117 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8322 00:25:52.369391 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8323 00:25:52.372536 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8324 00:25:52.376339 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8325 00:25:52.376803
8326 00:25:52.378986 CA PerBit enable=1, Macro0, CA PI delay=36
8327 00:25:52.379373
8328 00:25:52.382899 [CBTSetCACLKResult] CA Dly = 36
8329 00:25:52.383363 CS Dly: 9 (0~40)
8330 00:25:52.389288 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8331 00:25:52.392801 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8332 00:25:52.393262 ==
8333 00:25:52.396043 Dram Type= 6, Freq= 0, CH_1, rank 1
8334 00:25:52.399153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 00:25:52.399621 ==
8336 00:25:52.406020 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8337 00:25:52.409061 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8338 00:25:52.412872 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8339 00:25:52.419608 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8340 00:25:52.428933 [CA 0] Center 43 (14~72) winsize 59
8341 00:25:52.432382 [CA 1] Center 43 (14~72) winsize 59
8342 00:25:52.435708 [CA 2] Center 38 (9~67) winsize 59
8343 00:25:52.438661 [CA 3] Center 37 (8~67) winsize 60
8344 00:25:52.442866 [CA 4] Center 38 (9~68) winsize 60
8345 00:25:52.445972 [CA 5] Center 37 (8~66) winsize 59
8346 00:25:52.446510
8347 00:25:52.449215 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8348 00:25:52.449684
8349 00:25:52.452348 [CATrainingPosCal] consider 2 rank data
8350 00:25:52.455884 u2DelayCellTimex100 = 275/100 ps
8351 00:25:52.459352 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8352 00:25:52.465399 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8353 00:25:52.469218 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8354 00:25:52.472351 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8355 00:25:52.475531 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8356 00:25:52.478782 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8357 00:25:52.479184
8358 00:25:52.482099 CA PerBit enable=1, Macro0, CA PI delay=36
8359 00:25:52.482495
8360 00:25:52.486135 [CBTSetCACLKResult] CA Dly = 36
8361 00:25:52.486626 CS Dly: 10 (0~43)
8362 00:25:52.492338 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8363 00:25:52.495749 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8364 00:25:52.496243
8365 00:25:52.498636 ----->DramcWriteLeveling(PI) begin...
8366 00:25:52.499041 ==
8367 00:25:52.502509 Dram Type= 6, Freq= 0, CH_1, rank 0
8368 00:25:52.505836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 00:25:52.506278 ==
8370 00:25:52.508761 Write leveling (Byte 0): 24 => 24
8371 00:25:52.512133 Write leveling (Byte 1): 27 => 27
8372 00:25:52.515444 DramcWriteLeveling(PI) end<-----
8373 00:25:52.515844
8374 00:25:52.516342 ==
8375 00:25:52.519462 Dram Type= 6, Freq= 0, CH_1, rank 0
8376 00:25:52.525612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 00:25:52.526137 ==
8378 00:25:52.526648 [Gating] SW mode calibration
8379 00:25:52.535816 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8380 00:25:52.538681 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8381 00:25:52.542311 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 00:25:52.548741 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 00:25:52.552568 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 00:25:52.555830 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 00:25:52.562564 1 4 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8386 00:25:52.565712 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 00:25:52.568920 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 00:25:52.575271 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 00:25:52.579012 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 00:25:52.582604 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 00:25:52.588820 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8392 00:25:52.592336 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8393 00:25:52.595673 1 5 16 | B1->B0 | 2f2f 3434 | 0 0 | (1 0) (0 1)
8394 00:25:52.602412 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 00:25:52.605844 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 00:25:52.609458 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 00:25:52.615534 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 00:25:52.618841 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 00:25:52.622321 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 00:25:52.625707 1 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8401 00:25:52.632684 1 6 16 | B1->B0 | 3838 2a2a | 0 0 | (0 0) (0 0)
8402 00:25:52.635777 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 00:25:52.639079 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 00:25:52.645708 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 00:25:52.649012 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 00:25:52.652345 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 00:25:52.659206 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 00:25:52.662178 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 00:25:52.665794 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8410 00:25:52.672357 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 00:25:52.675778 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 00:25:52.679236 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 00:25:52.686019 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 00:25:52.689257 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 00:25:52.693018 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 00:25:52.698789 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 00:25:52.702206 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 00:25:52.705625 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 00:25:52.709431 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 00:25:52.715614 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 00:25:52.718906 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 00:25:52.722077 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 00:25:52.728697 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 00:25:52.732210 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 00:25:52.736102 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8426 00:25:52.742416 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8427 00:25:52.742825 Total UI for P1: 0, mck2ui 16
8428 00:25:52.748910 best dqsien dly found for B0: ( 1, 9, 16)
8429 00:25:52.752783 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 00:25:52.755715 Total UI for P1: 0, mck2ui 16
8431 00:25:52.759199 best dqsien dly found for B1: ( 1, 9, 18)
8432 00:25:52.762672 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8433 00:25:52.765388 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8434 00:25:52.765787
8435 00:25:52.769259 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8436 00:25:52.772752 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8437 00:25:52.776266 [Gating] SW calibration Done
8438 00:25:52.776751 ==
8439 00:25:52.779341 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 00:25:52.782359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 00:25:52.786359 ==
8442 00:25:52.786845 RX Vref Scan: 0
8443 00:25:52.787249
8444 00:25:52.789061 RX Vref 0 -> 0, step: 1
8445 00:25:52.789445
8446 00:25:52.789747 RX Delay 0 -> 252, step: 8
8447 00:25:52.795830 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8448 00:25:52.799556 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8449 00:25:52.802651 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8450 00:25:52.806312 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8451 00:25:52.809361 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8452 00:25:52.815742 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8453 00:25:52.819427 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8454 00:25:52.822710 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8455 00:25:52.826025 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8456 00:25:52.829040 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8457 00:25:52.835507 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8458 00:25:52.839437 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8459 00:25:52.842289 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8460 00:25:52.846111 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8461 00:25:52.849606 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8462 00:25:52.856171 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8463 00:25:52.856718 ==
8464 00:25:52.859586 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 00:25:52.862241 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 00:25:52.862693 ==
8467 00:25:52.863005 DQS Delay:
8468 00:25:52.866098 DQS0 = 0, DQS1 = 0
8469 00:25:52.866570 DQM Delay:
8470 00:25:52.869687 DQM0 = 134, DQM1 = 127
8471 00:25:52.870193 DQ Delay:
8472 00:25:52.872267 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8473 00:25:52.875782 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8474 00:25:52.879500 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8475 00:25:52.882284 DQ12 =139, DQ13 =131, DQ14 =135, DQ15 =131
8476 00:25:52.882692
8477 00:25:52.882996
8478 00:25:52.885977 ==
8479 00:25:52.888991 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 00:25:52.892983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8481 00:25:52.893461 ==
8482 00:25:52.893769
8483 00:25:52.894095
8484 00:25:52.895467 TX Vref Scan disable
8485 00:25:52.895857 == TX Byte 0 ==
8486 00:25:52.899222 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8487 00:25:52.906375 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8488 00:25:52.906766 == TX Byte 1 ==
8489 00:25:52.908999 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8490 00:25:52.915928 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8491 00:25:52.916318 ==
8492 00:25:52.918900 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 00:25:52.922466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 00:25:52.922855 ==
8495 00:25:52.935140
8496 00:25:52.938510 TX Vref early break, caculate TX vref
8497 00:25:52.941849 TX Vref=16, minBit 8, minWin=21, winSum=366
8498 00:25:52.945600 TX Vref=18, minBit 8, minWin=21, winSum=377
8499 00:25:52.948533 TX Vref=20, minBit 8, minWin=23, winSum=386
8500 00:25:52.952577 TX Vref=22, minBit 8, minWin=23, winSum=398
8501 00:25:52.955620 TX Vref=24, minBit 5, minWin=24, winSum=407
8502 00:25:52.962063 TX Vref=26, minBit 5, minWin=25, winSum=414
8503 00:25:52.966071 TX Vref=28, minBit 5, minWin=25, winSum=421
8504 00:25:52.968745 TX Vref=30, minBit 8, minWin=25, winSum=423
8505 00:25:52.972609 TX Vref=32, minBit 0, minWin=25, winSum=417
8506 00:25:52.975889 TX Vref=34, minBit 11, minWin=23, winSum=400
8507 00:25:52.982359 [TxChooseVref] Worse bit 8, Min win 25, Win sum 423, Final Vref 30
8508 00:25:52.982869
8509 00:25:52.985321 Final TX Range 0 Vref 30
8510 00:25:52.985710
8511 00:25:52.986041 ==
8512 00:25:52.988770 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 00:25:52.992309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8514 00:25:52.992699 ==
8515 00:25:52.993001
8516 00:25:52.993276
8517 00:25:52.995218 TX Vref Scan disable
8518 00:25:53.001932 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8519 00:25:53.002353 == TX Byte 0 ==
8520 00:25:53.005203 u2DelayCellOfst[0]=17 cells (5 PI)
8521 00:25:53.008552 u2DelayCellOfst[1]=10 cells (3 PI)
8522 00:25:53.012350 u2DelayCellOfst[2]=0 cells (0 PI)
8523 00:25:53.015526 u2DelayCellOfst[3]=7 cells (2 PI)
8524 00:25:53.018993 u2DelayCellOfst[4]=10 cells (3 PI)
8525 00:25:53.019386 u2DelayCellOfst[5]=17 cells (5 PI)
8526 00:25:53.022041 u2DelayCellOfst[6]=17 cells (5 PI)
8527 00:25:53.025702 u2DelayCellOfst[7]=7 cells (2 PI)
8528 00:25:53.031960 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8529 00:25:53.035449 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8530 00:25:53.035808 == TX Byte 1 ==
8531 00:25:53.038943 u2DelayCellOfst[8]=0 cells (0 PI)
8532 00:25:53.042168 u2DelayCellOfst[9]=3 cells (1 PI)
8533 00:25:53.045423 u2DelayCellOfst[10]=10 cells (3 PI)
8534 00:25:53.048909 u2DelayCellOfst[11]=7 cells (2 PI)
8535 00:25:53.052641 u2DelayCellOfst[12]=14 cells (4 PI)
8536 00:25:53.055546 u2DelayCellOfst[13]=17 cells (5 PI)
8537 00:25:53.059545 u2DelayCellOfst[14]=17 cells (5 PI)
8538 00:25:53.062641 u2DelayCellOfst[15]=17 cells (5 PI)
8539 00:25:53.065807 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8540 00:25:53.069303 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8541 00:25:53.072644 DramC Write-DBI on
8542 00:25:53.073036 ==
8543 00:25:53.075704 Dram Type= 6, Freq= 0, CH_1, rank 0
8544 00:25:53.079024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8545 00:25:53.079501 ==
8546 00:25:53.079808
8547 00:25:53.080086
8548 00:25:53.082613 TX Vref Scan disable
8549 00:25:53.085548 == TX Byte 0 ==
8550 00:25:53.089130 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8551 00:25:53.089668 == TX Byte 1 ==
8552 00:25:53.095593 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8553 00:25:53.096045 DramC Write-DBI off
8554 00:25:53.096349
8555 00:25:53.099172 [DATLAT]
8556 00:25:53.099607 Freq=1600, CH1 RK0
8557 00:25:53.099909
8558 00:25:53.102587 DATLAT Default: 0xf
8559 00:25:53.102975 0, 0xFFFF, sum = 0
8560 00:25:53.105941 1, 0xFFFF, sum = 0
8561 00:25:53.106449 2, 0xFFFF, sum = 0
8562 00:25:53.109115 3, 0xFFFF, sum = 0
8563 00:25:53.109510 4, 0xFFFF, sum = 0
8564 00:25:53.113108 5, 0xFFFF, sum = 0
8565 00:25:53.113601 6, 0xFFFF, sum = 0
8566 00:25:53.115752 7, 0xFFFF, sum = 0
8567 00:25:53.116281 8, 0xFFFF, sum = 0
8568 00:25:53.119305 9, 0xFFFF, sum = 0
8569 00:25:53.119701 10, 0xFFFF, sum = 0
8570 00:25:53.122247 11, 0xFFFF, sum = 0
8571 00:25:53.122686 12, 0xFFFF, sum = 0
8572 00:25:53.125468 13, 0xFFFF, sum = 0
8573 00:25:53.128929 14, 0x0, sum = 1
8574 00:25:53.129326 15, 0x0, sum = 2
8575 00:25:53.129634 16, 0x0, sum = 3
8576 00:25:53.132418 17, 0x0, sum = 4
8577 00:25:53.132813 best_step = 15
8578 00:25:53.133109
8579 00:25:53.133460 ==
8580 00:25:53.135713 Dram Type= 6, Freq= 0, CH_1, rank 0
8581 00:25:53.142332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8582 00:25:53.142726 ==
8583 00:25:53.143083 RX Vref Scan: 1
8584 00:25:53.143487
8585 00:25:53.145165 Set Vref Range= 24 -> 127
8586 00:25:53.145615
8587 00:25:53.148936 RX Vref 24 -> 127, step: 1
8588 00:25:53.149381
8589 00:25:53.153054 RX Delay 19 -> 252, step: 4
8590 00:25:53.153443
8591 00:25:53.155700 Set Vref, RX VrefLevel [Byte0]: 24
8592 00:25:53.156087 [Byte1]: 24
8593 00:25:53.160311
8594 00:25:53.160774 Set Vref, RX VrefLevel [Byte0]: 25
8595 00:25:53.163631 [Byte1]: 25
8596 00:25:53.167515
8597 00:25:53.168001 Set Vref, RX VrefLevel [Byte0]: 26
8598 00:25:53.170719 [Byte1]: 26
8599 00:25:53.175046
8600 00:25:53.175430 Set Vref, RX VrefLevel [Byte0]: 27
8601 00:25:53.178417 [Byte1]: 27
8602 00:25:53.182375
8603 00:25:53.182779 Set Vref, RX VrefLevel [Byte0]: 28
8604 00:25:53.186137 [Byte1]: 28
8605 00:25:53.189943
8606 00:25:53.190396 Set Vref, RX VrefLevel [Byte0]: 29
8607 00:25:53.193910 [Byte1]: 29
8608 00:25:53.197627
8609 00:25:53.198066 Set Vref, RX VrefLevel [Byte0]: 30
8610 00:25:53.201083 [Byte1]: 30
8611 00:25:53.205627
8612 00:25:53.206148 Set Vref, RX VrefLevel [Byte0]: 31
8613 00:25:53.208603 [Byte1]: 31
8614 00:25:53.212643
8615 00:25:53.213033 Set Vref, RX VrefLevel [Byte0]: 32
8616 00:25:53.216337 [Byte1]: 32
8617 00:25:53.220552
8618 00:25:53.221026 Set Vref, RX VrefLevel [Byte0]: 33
8619 00:25:53.223838 [Byte1]: 33
8620 00:25:53.227849
8621 00:25:53.228238 Set Vref, RX VrefLevel [Byte0]: 34
8622 00:25:53.231263 [Byte1]: 34
8623 00:25:53.235788
8624 00:25:53.236275 Set Vref, RX VrefLevel [Byte0]: 35
8625 00:25:53.239086 [Byte1]: 35
8626 00:25:53.243577
8627 00:25:53.244078 Set Vref, RX VrefLevel [Byte0]: 36
8628 00:25:53.246555 [Byte1]: 36
8629 00:25:53.250820
8630 00:25:53.251208 Set Vref, RX VrefLevel [Byte0]: 37
8631 00:25:53.254568 [Byte1]: 37
8632 00:25:53.258683
8633 00:25:53.259147 Set Vref, RX VrefLevel [Byte0]: 38
8634 00:25:53.262126 [Byte1]: 38
8635 00:25:53.266486
8636 00:25:53.266948 Set Vref, RX VrefLevel [Byte0]: 39
8637 00:25:53.268948 [Byte1]: 39
8638 00:25:53.273596
8639 00:25:53.274107 Set Vref, RX VrefLevel [Byte0]: 40
8640 00:25:53.277223 [Byte1]: 40
8641 00:25:53.281344
8642 00:25:53.281725 Set Vref, RX VrefLevel [Byte0]: 41
8643 00:25:53.284464 [Byte1]: 41
8644 00:25:53.289306
8645 00:25:53.289782 Set Vref, RX VrefLevel [Byte0]: 42
8646 00:25:53.291694 [Byte1]: 42
8647 00:25:53.296417
8648 00:25:53.296881 Set Vref, RX VrefLevel [Byte0]: 43
8649 00:25:53.299653 [Byte1]: 43
8650 00:25:53.303873
8651 00:25:53.304340 Set Vref, RX VrefLevel [Byte0]: 44
8652 00:25:53.307351 [Byte1]: 44
8653 00:25:53.311181
8654 00:25:53.311643 Set Vref, RX VrefLevel [Byte0]: 45
8655 00:25:53.314975 [Byte1]: 45
8656 00:25:53.319099
8657 00:25:53.319482 Set Vref, RX VrefLevel [Byte0]: 46
8658 00:25:53.322417 [Byte1]: 46
8659 00:25:53.326404
8660 00:25:53.326873 Set Vref, RX VrefLevel [Byte0]: 47
8661 00:25:53.330050 [Byte1]: 47
8662 00:25:53.333674
8663 00:25:53.334109 Set Vref, RX VrefLevel [Byte0]: 48
8664 00:25:53.337048 [Byte1]: 48
8665 00:25:53.341966
8666 00:25:53.342471 Set Vref, RX VrefLevel [Byte0]: 49
8667 00:25:53.345023 [Byte1]: 49
8668 00:25:53.348986
8669 00:25:53.349370 Set Vref, RX VrefLevel [Byte0]: 50
8670 00:25:53.352842 [Byte1]: 50
8671 00:25:53.356965
8672 00:25:53.357447 Set Vref, RX VrefLevel [Byte0]: 51
8673 00:25:53.359995 [Byte1]: 51
8674 00:25:53.364346
8675 00:25:53.364765 Set Vref, RX VrefLevel [Byte0]: 52
8676 00:25:53.368229 [Byte1]: 52
8677 00:25:53.372348
8678 00:25:53.372818 Set Vref, RX VrefLevel [Byte0]: 53
8679 00:25:53.375599 [Byte1]: 53
8680 00:25:53.379677
8681 00:25:53.380144 Set Vref, RX VrefLevel [Byte0]: 54
8682 00:25:53.382939 [Byte1]: 54
8683 00:25:53.386934
8684 00:25:53.390822 Set Vref, RX VrefLevel [Byte0]: 55
8685 00:25:53.391296 [Byte1]: 55
8686 00:25:53.394922
8687 00:25:53.395392 Set Vref, RX VrefLevel [Byte0]: 56
8688 00:25:53.398312 [Byte1]: 56
8689 00:25:53.402569
8690 00:25:53.403039 Set Vref, RX VrefLevel [Byte0]: 57
8691 00:25:53.405848 [Byte1]: 57
8692 00:25:53.410030
8693 00:25:53.410512 Set Vref, RX VrefLevel [Byte0]: 58
8694 00:25:53.413362 [Byte1]: 58
8695 00:25:53.417393
8696 00:25:53.417852 Set Vref, RX VrefLevel [Byte0]: 59
8697 00:25:53.420888 [Byte1]: 59
8698 00:25:53.425030
8699 00:25:53.425518 Set Vref, RX VrefLevel [Byte0]: 60
8700 00:25:53.428607 [Byte1]: 60
8701 00:25:53.432424
8702 00:25:53.432858 Set Vref, RX VrefLevel [Byte0]: 61
8703 00:25:53.435900 [Byte1]: 61
8704 00:25:53.440673
8705 00:25:53.441144 Set Vref, RX VrefLevel [Byte0]: 62
8706 00:25:53.443328 [Byte1]: 62
8707 00:25:53.447899
8708 00:25:53.448375 Set Vref, RX VrefLevel [Byte0]: 63
8709 00:25:53.451140 [Byte1]: 63
8710 00:25:53.455595
8711 00:25:53.456061 Set Vref, RX VrefLevel [Byte0]: 64
8712 00:25:53.458811 [Byte1]: 64
8713 00:25:53.463191
8714 00:25:53.463680 Set Vref, RX VrefLevel [Byte0]: 65
8715 00:25:53.466306 [Byte1]: 65
8716 00:25:53.470552
8717 00:25:53.471037 Set Vref, RX VrefLevel [Byte0]: 66
8718 00:25:53.473807 [Byte1]: 66
8719 00:25:53.477647
8720 00:25:53.478026 Set Vref, RX VrefLevel [Byte0]: 67
8721 00:25:53.481437 [Byte1]: 67
8722 00:25:53.485801
8723 00:25:53.486301 Set Vref, RX VrefLevel [Byte0]: 68
8724 00:25:53.489249 [Byte1]: 68
8725 00:25:53.493260
8726 00:25:53.493722 Set Vref, RX VrefLevel [Byte0]: 69
8727 00:25:53.496945 [Byte1]: 69
8728 00:25:53.501158
8729 00:25:53.501625 Set Vref, RX VrefLevel [Byte0]: 70
8730 00:25:53.504117 [Byte1]: 70
8731 00:25:53.508412
8732 00:25:53.508875 Set Vref, RX VrefLevel [Byte0]: 71
8733 00:25:53.511707 [Byte1]: 71
8734 00:25:53.516054
8735 00:25:53.516519 Set Vref, RX VrefLevel [Byte0]: 72
8736 00:25:53.519385 [Byte1]: 72
8737 00:25:53.523490
8738 00:25:53.523868 Set Vref, RX VrefLevel [Byte0]: 73
8739 00:25:53.526849 [Byte1]: 73
8740 00:25:53.531012
8741 00:25:53.531468 Set Vref, RX VrefLevel [Byte0]: 74
8742 00:25:53.533859 [Byte1]: 74
8743 00:25:53.538301
8744 00:25:53.538686 Final RX Vref Byte 0 = 54 to rank0
8745 00:25:53.541727 Final RX Vref Byte 1 = 56 to rank0
8746 00:25:53.544838 Final RX Vref Byte 0 = 54 to rank1
8747 00:25:53.548524 Final RX Vref Byte 1 = 56 to rank1==
8748 00:25:53.551984 Dram Type= 6, Freq= 0, CH_1, rank 0
8749 00:25:53.558546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8750 00:25:53.559016 ==
8751 00:25:53.559323 DQS Delay:
8752 00:25:53.559603 DQS0 = 0, DQS1 = 0
8753 00:25:53.562108 DQM Delay:
8754 00:25:53.562498 DQM0 = 130, DQM1 = 124
8755 00:25:53.565388 DQ Delay:
8756 00:25:53.568825 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8757 00:25:53.572033 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8758 00:25:53.575166 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120
8759 00:25:53.578462 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8760 00:25:53.578847
8761 00:25:53.579149
8762 00:25:53.579423
8763 00:25:53.582032 [DramC_TX_OE_Calibration] TA2
8764 00:25:53.585011 Original DQ_B0 (3 6) =30, OEN = 27
8765 00:25:53.588759 Original DQ_B1 (3 6) =30, OEN = 27
8766 00:25:53.591472 24, 0x0, End_B0=24 End_B1=24
8767 00:25:53.591905 25, 0x0, End_B0=25 End_B1=25
8768 00:25:53.594904 26, 0x0, End_B0=26 End_B1=26
8769 00:25:53.598745 27, 0x0, End_B0=27 End_B1=27
8770 00:25:53.602112 28, 0x0, End_B0=28 End_B1=28
8771 00:25:53.602589 29, 0x0, End_B0=29 End_B1=29
8772 00:25:53.605115 30, 0x0, End_B0=30 End_B1=30
8773 00:25:53.608652 31, 0x4141, End_B0=30 End_B1=30
8774 00:25:53.611875 Byte0 end_step=30 best_step=27
8775 00:25:53.614746 Byte1 end_step=30 best_step=27
8776 00:25:53.618601 Byte0 TX OE(2T, 0.5T) = (3, 3)
8777 00:25:53.619072 Byte1 TX OE(2T, 0.5T) = (3, 3)
8778 00:25:53.622223
8779 00:25:53.622694
8780 00:25:53.628890 [DQSOSCAuto] RK0, (LSB)MR18= 0x1802, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 397 ps
8781 00:25:53.631688 CH1 RK0: MR19=303, MR18=1802
8782 00:25:53.638834 CH1_RK0: MR19=0x303, MR18=0x1802, DQSOSC=397, MR23=63, INC=23, DEC=15
8783 00:25:53.639305
8784 00:25:53.642013 ----->DramcWriteLeveling(PI) begin...
8785 00:25:53.642546 ==
8786 00:25:53.645160 Dram Type= 6, Freq= 0, CH_1, rank 1
8787 00:25:53.648531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8788 00:25:53.649005 ==
8789 00:25:53.651832 Write leveling (Byte 0): 24 => 24
8790 00:25:53.655341 Write leveling (Byte 1): 25 => 25
8791 00:25:53.658159 DramcWriteLeveling(PI) end<-----
8792 00:25:53.658549
8793 00:25:53.658848 ==
8794 00:25:53.661905 Dram Type= 6, Freq= 0, CH_1, rank 1
8795 00:25:53.665341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8796 00:25:53.665813 ==
8797 00:25:53.668792 [Gating] SW mode calibration
8798 00:25:53.674889 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8799 00:25:53.681550 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8800 00:25:53.685267 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 00:25:53.688710 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 00:25:53.695177 1 4 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
8803 00:25:53.698787 1 4 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
8804 00:25:53.701799 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 00:25:53.709169 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8806 00:25:53.711853 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8807 00:25:53.715736 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8808 00:25:53.722054 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8809 00:25:53.725072 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8810 00:25:53.728609 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
8811 00:25:53.732444 1 5 12 | B1->B0 | 3030 2424 | 1 0 | (1 0) (0 0)
8812 00:25:53.738961 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 00:25:53.742504 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 00:25:53.745546 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 00:25:53.751606 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 00:25:53.755538 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 00:25:53.758675 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 00:25:53.765324 1 6 8 | B1->B0 | 2424 3939 | 0 0 | (0 0) (0 0)
8819 00:25:53.768851 1 6 12 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8820 00:25:53.771938 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 00:25:53.778940 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 00:25:53.782038 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 00:25:53.785604 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 00:25:53.792028 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 00:25:53.795551 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8826 00:25:53.798663 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8827 00:25:53.805408 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8828 00:25:53.809099 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8829 00:25:53.811981 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 00:25:53.815739 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 00:25:53.822846 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 00:25:53.825530 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 00:25:53.828340 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 00:25:53.835599 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 00:25:53.838777 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 00:25:53.842414 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 00:25:53.848685 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 00:25:53.851838 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 00:25:53.855545 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 00:25:53.862013 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 00:25:53.865207 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8842 00:25:53.869135 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8843 00:25:53.875053 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8844 00:25:53.875509 Total UI for P1: 0, mck2ui 16
8845 00:25:53.882072 best dqsien dly found for B0: ( 1, 9, 6)
8846 00:25:53.885977 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8847 00:25:53.888911 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 00:25:53.891842 Total UI for P1: 0, mck2ui 16
8849 00:25:53.895114 best dqsien dly found for B1: ( 1, 9, 14)
8850 00:25:53.899020 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8851 00:25:53.902407 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8852 00:25:53.902870
8853 00:25:53.905920 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8854 00:25:53.912303 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8855 00:25:53.912776 [Gating] SW calibration Done
8856 00:25:53.913097 ==
8857 00:25:53.915244 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 00:25:53.922507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 00:25:53.922981 ==
8860 00:25:53.923290 RX Vref Scan: 0
8861 00:25:53.923570
8862 00:25:53.925345 RX Vref 0 -> 0, step: 1
8863 00:25:53.925826
8864 00:25:53.928984 RX Delay 0 -> 252, step: 8
8865 00:25:53.931896 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8866 00:25:53.935475 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8867 00:25:53.939090 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8868 00:25:53.941975 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8869 00:25:53.949444 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8870 00:25:53.952683 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8871 00:25:53.955255 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8872 00:25:53.958773 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8873 00:25:53.962629 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8874 00:25:53.965792 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8875 00:25:53.972440 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8876 00:25:53.976153 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8877 00:25:53.979024 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8878 00:25:53.982118 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8879 00:25:53.989550 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8880 00:25:53.992347 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8881 00:25:53.992738 ==
8882 00:25:53.995564 Dram Type= 6, Freq= 0, CH_1, rank 1
8883 00:25:53.999067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8884 00:25:53.999457 ==
8885 00:25:53.999758 DQS Delay:
8886 00:25:54.002659 DQS0 = 0, DQS1 = 0
8887 00:25:54.003126 DQM Delay:
8888 00:25:54.006381 DQM0 = 132, DQM1 = 128
8889 00:25:54.006967 DQ Delay:
8890 00:25:54.008997 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =135
8891 00:25:54.012320 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =127
8892 00:25:54.015766 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =119
8893 00:25:54.022022 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8894 00:25:54.022418
8895 00:25:54.022721
8896 00:25:54.022997 ==
8897 00:25:54.025309 Dram Type= 6, Freq= 0, CH_1, rank 1
8898 00:25:54.029018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8899 00:25:54.029487 ==
8900 00:25:54.029787
8901 00:25:54.030101
8902 00:25:54.032615 TX Vref Scan disable
8903 00:25:54.033079 == TX Byte 0 ==
8904 00:25:54.038667 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8905 00:25:54.042576 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8906 00:25:54.043045 == TX Byte 1 ==
8907 00:25:54.049011 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8908 00:25:54.052532 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8909 00:25:54.052997 ==
8910 00:25:54.055212 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 00:25:54.058831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 00:25:54.059301 ==
8913 00:25:54.073395
8914 00:25:54.076988 TX Vref early break, caculate TX vref
8915 00:25:54.079894 TX Vref=16, minBit 5, minWin=23, winSum=383
8916 00:25:54.083313 TX Vref=18, minBit 15, minWin=23, winSum=397
8917 00:25:54.086972 TX Vref=20, minBit 0, minWin=25, winSum=406
8918 00:25:54.090143 TX Vref=22, minBit 5, minWin=24, winSum=408
8919 00:25:54.093731 TX Vref=24, minBit 6, minWin=25, winSum=420
8920 00:25:54.100025 TX Vref=26, minBit 0, minWin=26, winSum=425
8921 00:25:54.103623 TX Vref=28, minBit 0, minWin=25, winSum=430
8922 00:25:54.106488 TX Vref=30, minBit 0, minWin=25, winSum=430
8923 00:25:54.109862 TX Vref=32, minBit 0, minWin=25, winSum=421
8924 00:25:54.113682 TX Vref=34, minBit 0, minWin=25, winSum=416
8925 00:25:54.116693 TX Vref=36, minBit 0, minWin=24, winSum=403
8926 00:25:54.123089 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 26
8927 00:25:54.123559
8928 00:25:54.126604 Final TX Range 0 Vref 26
8929 00:25:54.127287
8930 00:25:54.127788 ==
8931 00:25:54.129669 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 00:25:54.133088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 00:25:54.133482 ==
8934 00:25:54.133786
8935 00:25:54.134106
8936 00:25:54.136734 TX Vref Scan disable
8937 00:25:54.143193 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8938 00:25:54.143659 == TX Byte 0 ==
8939 00:25:54.146374 u2DelayCellOfst[0]=17 cells (5 PI)
8940 00:25:54.150219 u2DelayCellOfst[1]=10 cells (3 PI)
8941 00:25:54.153150 u2DelayCellOfst[2]=0 cells (0 PI)
8942 00:25:54.156516 u2DelayCellOfst[3]=7 cells (2 PI)
8943 00:25:54.160110 u2DelayCellOfst[4]=7 cells (2 PI)
8944 00:25:54.163276 u2DelayCellOfst[5]=17 cells (5 PI)
8945 00:25:54.166689 u2DelayCellOfst[6]=17 cells (5 PI)
8946 00:25:54.170456 u2DelayCellOfst[7]=3 cells (1 PI)
8947 00:25:54.173176 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8948 00:25:54.176966 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8949 00:25:54.179568 == TX Byte 1 ==
8950 00:25:54.179967 u2DelayCellOfst[8]=0 cells (0 PI)
8951 00:25:54.182997 u2DelayCellOfst[9]=7 cells (2 PI)
8952 00:25:54.186892 u2DelayCellOfst[10]=14 cells (4 PI)
8953 00:25:54.189941 u2DelayCellOfst[11]=7 cells (2 PI)
8954 00:25:54.193470 u2DelayCellOfst[12]=17 cells (5 PI)
8955 00:25:54.196935 u2DelayCellOfst[13]=17 cells (5 PI)
8956 00:25:54.199686 u2DelayCellOfst[14]=21 cells (6 PI)
8957 00:25:54.203399 u2DelayCellOfst[15]=17 cells (5 PI)
8958 00:25:54.207082 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8959 00:25:54.213358 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8960 00:25:54.213822 DramC Write-DBI on
8961 00:25:54.214185 ==
8962 00:25:54.216512 Dram Type= 6, Freq= 0, CH_1, rank 1
8963 00:25:54.219938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8964 00:25:54.223029 ==
8965 00:25:54.223417
8966 00:25:54.223717
8967 00:25:54.223998 TX Vref Scan disable
8968 00:25:54.226508 == TX Byte 0 ==
8969 00:25:54.229768 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8970 00:25:54.233385 == TX Byte 1 ==
8971 00:25:54.236816 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8972 00:25:54.237319 DramC Write-DBI off
8973 00:25:54.239568
8974 00:25:54.239951 [DATLAT]
8975 00:25:54.240253 Freq=1600, CH1 RK1
8976 00:25:54.240534
8977 00:25:54.243200 DATLAT Default: 0xf
8978 00:25:54.243588 0, 0xFFFF, sum = 0
8979 00:25:54.246902 1, 0xFFFF, sum = 0
8980 00:25:54.247378 2, 0xFFFF, sum = 0
8981 00:25:54.250065 3, 0xFFFF, sum = 0
8982 00:25:54.250515 4, 0xFFFF, sum = 0
8983 00:25:54.253021 5, 0xFFFF, sum = 0
8984 00:25:54.256719 6, 0xFFFF, sum = 0
8985 00:25:54.257197 7, 0xFFFF, sum = 0
8986 00:25:54.259718 8, 0xFFFF, sum = 0
8987 00:25:54.260125 9, 0xFFFF, sum = 0
8988 00:25:54.263204 10, 0xFFFF, sum = 0
8989 00:25:54.263603 11, 0xFFFF, sum = 0
8990 00:25:54.266308 12, 0xFFFF, sum = 0
8991 00:25:54.266701 13, 0xFFFF, sum = 0
8992 00:25:54.269733 14, 0x0, sum = 1
8993 00:25:54.270287 15, 0x0, sum = 2
8994 00:25:54.273289 16, 0x0, sum = 3
8995 00:25:54.273680 17, 0x0, sum = 4
8996 00:25:54.276157 best_step = 15
8997 00:25:54.276542
8998 00:25:54.276841 ==
8999 00:25:54.280095 Dram Type= 6, Freq= 0, CH_1, rank 1
9000 00:25:54.283217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9001 00:25:54.283613 ==
9002 00:25:54.283918 RX Vref Scan: 0
9003 00:25:54.284197
9004 00:25:54.286180 RX Vref 0 -> 0, step: 1
9005 00:25:54.286569
9006 00:25:54.290154 RX Delay 19 -> 252, step: 4
9007 00:25:54.293507 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
9008 00:25:54.299612 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9009 00:25:54.303212 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9010 00:25:54.306766 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9011 00:25:54.309780 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
9012 00:25:54.313508 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9013 00:25:54.316618 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9014 00:25:54.323154 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
9015 00:25:54.326499 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9016 00:25:54.329838 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9017 00:25:54.333301 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9018 00:25:54.336430 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
9019 00:25:54.343147 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9020 00:25:54.346513 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9021 00:25:54.349596 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
9022 00:25:54.352997 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
9023 00:25:54.353393 ==
9024 00:25:54.356590 Dram Type= 6, Freq= 0, CH_1, rank 1
9025 00:25:54.362931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9026 00:25:54.363295 ==
9027 00:25:54.363578 DQS Delay:
9028 00:25:54.366273 DQS0 = 0, DQS1 = 0
9029 00:25:54.366679 DQM Delay:
9030 00:25:54.367169 DQM0 = 129, DQM1 = 125
9031 00:25:54.369960 DQ Delay:
9032 00:25:54.373074 DQ0 =132, DQ1 =126, DQ2 =118, DQ3 =126
9033 00:25:54.376314 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =126
9034 00:25:54.380301 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =116
9035 00:25:54.383181 DQ12 =132, DQ13 =134, DQ14 =136, DQ15 =134
9036 00:25:54.383724
9037 00:25:54.384042
9038 00:25:54.384319
9039 00:25:54.386540 [DramC_TX_OE_Calibration] TA2
9040 00:25:54.390309 Original DQ_B0 (3 6) =30, OEN = 27
9041 00:25:54.393675 Original DQ_B1 (3 6) =30, OEN = 27
9042 00:25:54.396800 24, 0x0, End_B0=24 End_B1=24
9043 00:25:54.397270 25, 0x0, End_B0=25 End_B1=25
9044 00:25:54.400022 26, 0x0, End_B0=26 End_B1=26
9045 00:25:54.403849 27, 0x0, End_B0=27 End_B1=27
9046 00:25:54.406084 28, 0x0, End_B0=28 End_B1=28
9047 00:25:54.409459 29, 0x0, End_B0=29 End_B1=29
9048 00:25:54.409860 30, 0x0, End_B0=30 End_B1=30
9049 00:25:54.413095 31, 0x4141, End_B0=30 End_B1=30
9050 00:25:54.416489 Byte0 end_step=30 best_step=27
9051 00:25:54.419354 Byte1 end_step=30 best_step=27
9052 00:25:54.422968 Byte0 TX OE(2T, 0.5T) = (3, 3)
9053 00:25:54.426148 Byte1 TX OE(2T, 0.5T) = (3, 3)
9054 00:25:54.426540
9055 00:25:54.426847
9056 00:25:54.433298 [DQSOSCAuto] RK1, (LSB)MR18= 0xe13, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
9057 00:25:54.436140 CH1 RK1: MR19=303, MR18=E13
9058 00:25:54.442882 CH1_RK1: MR19=0x303, MR18=0xE13, DQSOSC=400, MR23=63, INC=23, DEC=15
9059 00:25:54.446597 [RxdqsGatingPostProcess] freq 1600
9060 00:25:54.449952 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9061 00:25:54.452713 best DQS0 dly(2T, 0.5T) = (1, 1)
9062 00:25:54.456098 best DQS1 dly(2T, 0.5T) = (1, 1)
9063 00:25:54.459492 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9064 00:25:54.462735 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9065 00:25:54.466444 best DQS0 dly(2T, 0.5T) = (1, 1)
9066 00:25:54.469343 best DQS1 dly(2T, 0.5T) = (1, 1)
9067 00:25:54.472835 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9068 00:25:54.476447 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9069 00:25:54.476900 Pre-setting of DQS Precalculation
9070 00:25:54.483102 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9071 00:25:54.489867 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9072 00:25:54.496262 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9073 00:25:54.496690
9074 00:25:54.497045
9075 00:25:54.499664 [Calibration Summary] 3200 Mbps
9076 00:25:54.503220 CH 0, Rank 0
9077 00:25:54.503643 SW Impedance : PASS
9078 00:25:54.506671 DUTY Scan : NO K
9079 00:25:54.509944 ZQ Calibration : PASS
9080 00:25:54.510349 Jitter Meter : NO K
9081 00:25:54.513469 CBT Training : PASS
9082 00:25:54.513958 Write leveling : PASS
9083 00:25:54.516375 RX DQS gating : PASS
9084 00:25:54.519779 RX DQ/DQS(RDDQC) : PASS
9085 00:25:54.520218 TX DQ/DQS : PASS
9086 00:25:54.523143 RX DATLAT : PASS
9087 00:25:54.526638 RX DQ/DQS(Engine): PASS
9088 00:25:54.527068 TX OE : PASS
9089 00:25:54.529702 All Pass.
9090 00:25:54.530326
9091 00:25:54.530698 CH 0, Rank 1
9092 00:25:54.532914 SW Impedance : PASS
9093 00:25:54.533354 DUTY Scan : NO K
9094 00:25:54.536518 ZQ Calibration : PASS
9095 00:25:54.540129 Jitter Meter : NO K
9096 00:25:54.540538 CBT Training : PASS
9097 00:25:54.543013 Write leveling : PASS
9098 00:25:54.546578 RX DQS gating : PASS
9099 00:25:54.547014 RX DQ/DQS(RDDQC) : PASS
9100 00:25:54.549906 TX DQ/DQS : PASS
9101 00:25:54.550587 RX DATLAT : PASS
9102 00:25:54.553176 RX DQ/DQS(Engine): PASS
9103 00:25:54.556422 TX OE : PASS
9104 00:25:54.556867 All Pass.
9105 00:25:54.557187
9106 00:25:54.557527 CH 1, Rank 0
9107 00:25:54.560006 SW Impedance : PASS
9108 00:25:54.562944 DUTY Scan : NO K
9109 00:25:54.563391 ZQ Calibration : PASS
9110 00:25:54.566618 Jitter Meter : NO K
9111 00:25:54.569902 CBT Training : PASS
9112 00:25:54.570387 Write leveling : PASS
9113 00:25:54.573377 RX DQS gating : PASS
9114 00:25:54.576326 RX DQ/DQS(RDDQC) : PASS
9115 00:25:54.576777 TX DQ/DQS : PASS
9116 00:25:54.579769 RX DATLAT : PASS
9117 00:25:54.583473 RX DQ/DQS(Engine): PASS
9118 00:25:54.583938 TX OE : PASS
9119 00:25:54.584283 All Pass.
9120 00:25:54.586611
9121 00:25:54.587027 CH 1, Rank 1
9122 00:25:54.590106 SW Impedance : PASS
9123 00:25:54.590567 DUTY Scan : NO K
9124 00:25:54.593362 ZQ Calibration : PASS
9125 00:25:54.593877 Jitter Meter : NO K
9126 00:25:54.596651 CBT Training : PASS
9127 00:25:54.599920 Write leveling : PASS
9128 00:25:54.600360 RX DQS gating : PASS
9129 00:25:54.603300 RX DQ/DQS(RDDQC) : PASS
9130 00:25:54.606806 TX DQ/DQS : PASS
9131 00:25:54.607158 RX DATLAT : PASS
9132 00:25:54.610680 RX DQ/DQS(Engine): PASS
9133 00:25:54.613712 TX OE : PASS
9134 00:25:54.614183 All Pass.
9135 00:25:54.614462
9136 00:25:54.614712 DramC Write-DBI on
9137 00:25:54.616486 PER_BANK_REFRESH: Hybrid Mode
9138 00:25:54.619987 TX_TRACKING: ON
9139 00:25:54.627230 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9140 00:25:54.637115 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9141 00:25:54.643736 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9142 00:25:54.646956 [FAST_K] Save calibration result to emmc
9143 00:25:54.650443 sync common calibartion params.
9144 00:25:54.650892 sync cbt_mode0:1, 1:1
9145 00:25:54.653443 dram_init: ddr_geometry: 2
9146 00:25:54.656770 dram_init: ddr_geometry: 2
9147 00:25:54.660047 dram_init: ddr_geometry: 2
9148 00:25:54.660443 0:dram_rank_size:100000000
9149 00:25:54.663422 1:dram_rank_size:100000000
9150 00:25:54.670512 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9151 00:25:54.670909 DFS_SHUFFLE_HW_MODE: ON
9152 00:25:54.677040 dramc_set_vcore_voltage set vcore to 725000
9153 00:25:54.677501 Read voltage for 1600, 0
9154 00:25:54.680179 Vio18 = 0
9155 00:25:54.680568 Vcore = 725000
9156 00:25:54.680871 Vdram = 0
9157 00:25:54.681156 Vddq = 0
9158 00:25:54.684188 Vmddr = 0
9159 00:25:54.684656 switch to 3200 Mbps bootup
9160 00:25:54.687289 [DramcRunTimeConfig]
9161 00:25:54.687678 PHYPLL
9162 00:25:54.690216 DPM_CONTROL_AFTERK: ON
9163 00:25:54.690607 PER_BANK_REFRESH: ON
9164 00:25:54.693686 REFRESH_OVERHEAD_REDUCTION: ON
9165 00:25:54.697020 CMD_PICG_NEW_MODE: OFF
9166 00:25:54.697493 XRTWTW_NEW_MODE: ON
9167 00:25:54.700866 XRTRTR_NEW_MODE: ON
9168 00:25:54.701346 TX_TRACKING: ON
9169 00:25:54.703330 RDSEL_TRACKING: OFF
9170 00:25:54.706892 DQS Precalculation for DVFS: ON
9171 00:25:54.707362 RX_TRACKING: OFF
9172 00:25:54.710657 HW_GATING DBG: ON
9173 00:25:54.711122 ZQCS_ENABLE_LP4: ON
9174 00:25:54.713459 RX_PICG_NEW_MODE: ON
9175 00:25:54.713908 TX_PICG_NEW_MODE: ON
9176 00:25:54.716806 ENABLE_RX_DCM_DPHY: ON
9177 00:25:54.720131 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9178 00:25:54.723623 DUMMY_READ_FOR_TRACKING: OFF
9179 00:25:54.724005 !!! SPM_CONTROL_AFTERK: OFF
9180 00:25:54.727232 !!! SPM could not control APHY
9181 00:25:54.730753 IMPEDANCE_TRACKING: ON
9182 00:25:54.731138 TEMP_SENSOR: ON
9183 00:25:54.734043 HW_SAVE_FOR_SR: OFF
9184 00:25:54.737542 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9185 00:25:54.740153 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9186 00:25:54.743987 Read ODT Tracking: ON
9187 00:25:54.744451 Refresh Rate DeBounce: ON
9188 00:25:54.747072 DFS_NO_QUEUE_FLUSH: ON
9189 00:25:54.750258 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9190 00:25:54.753701 ENABLE_DFS_RUNTIME_MRW: OFF
9191 00:25:54.754197 DDR_RESERVE_NEW_MODE: ON
9192 00:25:54.757571 MR_CBT_SWITCH_FREQ: ON
9193 00:25:54.760028 =========================
9194 00:25:54.777809 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9195 00:25:54.781477 dram_init: ddr_geometry: 2
9196 00:25:54.799687 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9197 00:25:54.802513 dram_init: dram init end (result: 0)
9198 00:25:54.809718 DRAM-K: Full calibration passed in 24546 msecs
9199 00:25:54.812913 MRC: failed to locate region type 0.
9200 00:25:54.813379 DRAM rank0 size:0x100000000,
9201 00:25:54.816278 DRAM rank1 size=0x100000000
9202 00:25:54.826070 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9203 00:25:54.832813 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9204 00:25:54.839593 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9205 00:25:54.846203 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9206 00:25:54.849520 DRAM rank0 size:0x100000000,
9207 00:25:54.853012 DRAM rank1 size=0x100000000
9208 00:25:54.853476 CBMEM:
9209 00:25:54.856087 IMD: root @ 0xfffff000 254 entries.
9210 00:25:54.859525 IMD: root @ 0xffffec00 62 entries.
9211 00:25:54.862616 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9212 00:25:54.866054 WARNING: RO_VPD is uninitialized or empty.
9213 00:25:54.872945 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9214 00:25:54.879489 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9215 00:25:54.892225 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9216 00:25:54.903913 BS: romstage times (exec / console): total (unknown) / 24057 ms
9217 00:25:54.904385
9218 00:25:54.904692
9219 00:25:54.913734 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9220 00:25:54.917254 ARM64: Exception handlers installed.
9221 00:25:54.919794 ARM64: Testing exception
9222 00:25:54.923817 ARM64: Done test exception
9223 00:25:54.924299 Enumerating buses...
9224 00:25:54.926978 Show all devs... Before device enumeration.
9225 00:25:54.930323 Root Device: enabled 1
9226 00:25:54.933406 CPU_CLUSTER: 0: enabled 1
9227 00:25:54.933871 CPU: 00: enabled 1
9228 00:25:54.936923 Compare with tree...
9229 00:25:54.937314 Root Device: enabled 1
9230 00:25:54.939812 CPU_CLUSTER: 0: enabled 1
9231 00:25:54.943627 CPU: 00: enabled 1
9232 00:25:54.944095 Root Device scanning...
9233 00:25:54.946798 scan_static_bus for Root Device
9234 00:25:54.950444 CPU_CLUSTER: 0 enabled
9235 00:25:54.953371 scan_static_bus for Root Device done
9236 00:25:54.957171 scan_bus: bus Root Device finished in 8 msecs
9237 00:25:54.957640 done
9238 00:25:54.963632 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9239 00:25:54.966971 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9240 00:25:54.973536 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9241 00:25:54.977192 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9242 00:25:54.980192 Allocating resources...
9243 00:25:54.980582 Reading resources...
9244 00:25:54.986943 Root Device read_resources bus 0 link: 0
9245 00:25:54.987417 DRAM rank0 size:0x100000000,
9246 00:25:54.990313 DRAM rank1 size=0x100000000
9247 00:25:54.993427 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9248 00:25:54.996993 CPU: 00 missing read_resources
9249 00:25:55.000362 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9250 00:25:55.006458 Root Device read_resources bus 0 link: 0 done
9251 00:25:55.006847 Done reading resources.
9252 00:25:55.013526 Show resources in subtree (Root Device)...After reading.
9253 00:25:55.016787 Root Device child on link 0 CPU_CLUSTER: 0
9254 00:25:55.020356 CPU_CLUSTER: 0 child on link 0 CPU: 00
9255 00:25:55.030190 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9256 00:25:55.030828 CPU: 00
9257 00:25:55.033433 Root Device assign_resources, bus 0 link: 0
9258 00:25:55.036711 CPU_CLUSTER: 0 missing set_resources
9259 00:25:55.040010 Root Device assign_resources, bus 0 link: 0 done
9260 00:25:55.043813 Done setting resources.
9261 00:25:55.049849 Show resources in subtree (Root Device)...After assigning values.
9262 00:25:55.053428 Root Device child on link 0 CPU_CLUSTER: 0
9263 00:25:55.057183 CPU_CLUSTER: 0 child on link 0 CPU: 00
9264 00:25:55.066742 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9265 00:25:55.067239 CPU: 00
9266 00:25:55.069723 Done allocating resources.
9267 00:25:55.073867 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9268 00:25:55.076742 Enabling resources...
9269 00:25:55.077211 done.
9270 00:25:55.079926 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9271 00:25:55.083136 Initializing devices...
9272 00:25:55.086872 Root Device init
9273 00:25:55.087384 init hardware done!
9274 00:25:55.090590 0x00000018: ctrlr->caps
9275 00:25:55.091059 52.000 MHz: ctrlr->f_max
9276 00:25:55.093142 0.400 MHz: ctrlr->f_min
9277 00:25:55.097090 0x40ff8080: ctrlr->voltages
9278 00:25:55.097562 sclk: 390625
9279 00:25:55.100330 Bus Width = 1
9280 00:25:55.100797 sclk: 390625
9281 00:25:55.101095 Bus Width = 1
9282 00:25:55.103049 Early init status = 3
9283 00:25:55.106904 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9284 00:25:55.110988 in-header: 03 fc 00 00 01 00 00 00
9285 00:25:55.114417 in-data: 00
9286 00:25:55.117465 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9287 00:25:55.122092 in-header: 03 fd 00 00 00 00 00 00
9288 00:25:55.125262 in-data:
9289 00:25:55.128423 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9290 00:25:55.132193 in-header: 03 fc 00 00 01 00 00 00
9291 00:25:55.135584 in-data: 00
9292 00:25:55.138874 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9293 00:25:55.143765 in-header: 03 fd 00 00 00 00 00 00
9294 00:25:55.146883 in-data:
9295 00:25:55.150140 [SSUSB] Setting up USB HOST controller...
9296 00:25:55.153646 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9297 00:25:55.157336 [SSUSB] phy power-on done.
9298 00:25:55.160345 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9299 00:25:55.167448 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9300 00:25:55.170768 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9301 00:25:55.177040 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9302 00:25:55.184042 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9303 00:25:55.190796 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9304 00:25:55.197456 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9305 00:25:55.203636 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9306 00:25:55.204085 SPM: binary array size = 0x9dc
9307 00:25:55.210669 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9308 00:25:55.217173 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9309 00:25:55.223741 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9310 00:25:55.227174 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9311 00:25:55.230429 configure_display: Starting display init
9312 00:25:55.267208 anx7625_power_on_init: Init interface.
9313 00:25:55.270219 anx7625_disable_pd_protocol: Disabled PD feature.
9314 00:25:55.273766 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9315 00:25:55.301829 anx7625_start_dp_work: Secure OCM version=00
9316 00:25:55.304728 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9317 00:25:55.319298 sp_tx_get_edid_block: EDID Block = 1
9318 00:25:55.422534 Extracted contents:
9319 00:25:55.425180 header: 00 ff ff ff ff ff ff 00
9320 00:25:55.428617 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9321 00:25:55.431679 version: 01 04
9322 00:25:55.435617 basic params: 95 1f 11 78 0a
9323 00:25:55.438599 chroma info: 76 90 94 55 54 90 27 21 50 54
9324 00:25:55.442112 established: 00 00 00
9325 00:25:55.448611 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9326 00:25:55.451728 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9327 00:25:55.458567 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9328 00:25:55.465268 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9329 00:25:55.471619 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9330 00:25:55.475186 extensions: 00
9331 00:25:55.475569 checksum: fb
9332 00:25:55.475868
9333 00:25:55.478658 Manufacturer: IVO Model 57d Serial Number 0
9334 00:25:55.481567 Made week 0 of 2020
9335 00:25:55.481953 EDID version: 1.4
9336 00:25:55.485075 Digital display
9337 00:25:55.488517 6 bits per primary color channel
9338 00:25:55.488908 DisplayPort interface
9339 00:25:55.492012 Maximum image size: 31 cm x 17 cm
9340 00:25:55.495736 Gamma: 220%
9341 00:25:55.496200 Check DPMS levels
9342 00:25:55.498404 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9343 00:25:55.501810 First detailed timing is preferred timing
9344 00:25:55.505291 Established timings supported:
9345 00:25:55.508896 Standard timings supported:
9346 00:25:55.509376 Detailed timings
9347 00:25:55.514763 Hex of detail: 383680a07038204018303c0035ae10000019
9348 00:25:55.518553 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9349 00:25:55.525189 0780 0798 07c8 0820 hborder 0
9350 00:25:55.528658 0438 043b 0447 0458 vborder 0
9351 00:25:55.529160 -hsync -vsync
9352 00:25:55.532213 Did detailed timing
9353 00:25:55.534696 Hex of detail: 000000000000000000000000000000000000
9354 00:25:55.538497 Manufacturer-specified data, tag 0
9355 00:25:55.545061 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9356 00:25:55.545675 ASCII string: InfoVision
9357 00:25:55.551753 Hex of detail: 000000fe00523134304e574635205248200a
9358 00:25:55.555098 ASCII string: R140NWF5 RH
9359 00:25:55.555803 Checksum
9360 00:25:55.556352 Checksum: 0xfb (valid)
9361 00:25:55.561623 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9362 00:25:55.564850 DSI data_rate: 832800000 bps
9363 00:25:55.568100 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9364 00:25:55.571306 anx7625_parse_edid: pixelclock(138800).
9365 00:25:55.578158 hactive(1920), hsync(48), hfp(24), hbp(88)
9366 00:25:55.581203 vactive(1080), vsync(12), vfp(3), vbp(17)
9367 00:25:55.584449 anx7625_dsi_config: config dsi.
9368 00:25:55.591375 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9369 00:25:55.603918 anx7625_dsi_config: success to config DSI
9370 00:25:55.606928 anx7625_dp_start: MIPI phy setup OK.
9371 00:25:55.610389 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9372 00:25:55.614193 mtk_ddp_mode_set invalid vrefresh 60
9373 00:25:55.616909 main_disp_path_setup
9374 00:25:55.617116 ovl_layer_smi_id_en
9375 00:25:55.620934 ovl_layer_smi_id_en
9376 00:25:55.621142 ccorr_config
9377 00:25:55.621282 aal_config
9378 00:25:55.623637 gamma_config
9379 00:25:55.623846 postmask_config
9380 00:25:55.627510 dither_config
9381 00:25:55.630488 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9382 00:25:55.637348 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9383 00:25:55.640827 Root Device init finished in 551 msecs
9384 00:25:55.641138 CPU_CLUSTER: 0 init
9385 00:25:55.650547 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9386 00:25:55.653834 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9387 00:25:55.657486 APU_MBOX 0x190000b0 = 0x10001
9388 00:25:55.660645 APU_MBOX 0x190001b0 = 0x10001
9389 00:25:55.664392 APU_MBOX 0x190005b0 = 0x10001
9390 00:25:55.667210 APU_MBOX 0x190006b0 = 0x10001
9391 00:25:55.670678 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9392 00:25:55.682867 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9393 00:25:55.695466 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9394 00:25:55.701958 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9395 00:25:55.713741 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9396 00:25:55.722969 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9397 00:25:55.725845 CPU_CLUSTER: 0 init finished in 81 msecs
9398 00:25:55.729721 Devices initialized
9399 00:25:55.732879 Show all devs... After init.
9400 00:25:55.733343 Root Device: enabled 1
9401 00:25:55.736142 CPU_CLUSTER: 0: enabled 1
9402 00:25:55.739288 CPU: 00: enabled 1
9403 00:25:55.742866 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9404 00:25:55.746085 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9405 00:25:55.748909 ELOG: NV offset 0x57f000 size 0x1000
9406 00:25:55.755840 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9407 00:25:55.763317 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9408 00:25:55.766308 ELOG: Event(17) added with size 13 at 2024-06-21 00:25:55 UTC
9409 00:25:55.769447 out: cmd=0x121: 03 db 21 01 00 00 00 00
9410 00:25:55.774071 in-header: 03 e0 00 00 2c 00 00 00
9411 00:25:55.786974 in-data: 03 c7 6c 2c 25 06 00 00 0a 00 00 00 06 80 00 00 9c 46 35 2c 06 80 00 00 ff 34 69 2c 06 80 00 00 35 07 6b 2c 06 80 00 00 87 45 6c 2c
9412 00:25:55.793542 ELOG: Event(A1) added with size 10 at 2024-06-21 00:25:55 UTC
9413 00:25:55.800638 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9414 00:25:55.807484 ELOG: Event(A0) added with size 9 at 2024-06-21 00:25:55 UTC
9415 00:25:55.810617 elog_add_boot_reason: Logged dev mode boot
9416 00:25:55.813916 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9417 00:25:55.816862 Finalize devices...
9418 00:25:55.817247 Devices finalized
9419 00:25:55.823597 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9420 00:25:55.827305 Writing coreboot table at 0xffe64000
9421 00:25:55.830619 0. 000000000010a000-0000000000113fff: RAMSTAGE
9422 00:25:55.833733 1. 0000000040000000-00000000400fffff: RAM
9423 00:25:55.837432 2. 0000000040100000-000000004032afff: RAMSTAGE
9424 00:25:55.843385 3. 000000004032b000-00000000545fffff: RAM
9425 00:25:55.847067 4. 0000000054600000-000000005465ffff: BL31
9426 00:25:55.849974 5. 0000000054660000-00000000ffe63fff: RAM
9427 00:25:55.857569 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9428 00:25:55.860688 7. 0000000100000000-000000023fffffff: RAM
9429 00:25:55.861162 Passing 5 GPIOs to payload:
9430 00:25:55.867040 NAME | PORT | POLARITY | VALUE
9431 00:25:55.870078 EC in RW | 0x000000aa | low | undefined
9432 00:25:55.876815 EC interrupt | 0x00000005 | low | undefined
9433 00:25:55.880404 TPM interrupt | 0x000000ab | high | undefined
9434 00:25:55.883881 SD card detect | 0x00000011 | high | undefined
9435 00:25:55.890109 speaker enable | 0x00000093 | high | undefined
9436 00:25:55.893873 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9437 00:25:55.897287 in-header: 03 f9 00 00 02 00 00 00
9438 00:25:55.897755 in-data: 02 00
9439 00:25:55.900874 ADC[4]: Raw value=899852 ID=7
9440 00:25:55.903538 ADC[3]: Raw value=213336 ID=1
9441 00:25:55.903925 RAM Code: 0x71
9442 00:25:55.907439 ADC[6]: Raw value=74926 ID=0
9443 00:25:55.910489 ADC[5]: Raw value=211860 ID=1
9444 00:25:55.910874 SKU Code: 0x1
9445 00:25:55.917064 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d071
9446 00:25:55.920497 coreboot table: 964 bytes.
9447 00:25:55.923532 IMD ROOT 0. 0xfffff000 0x00001000
9448 00:25:55.926491 IMD SMALL 1. 0xffffe000 0x00001000
9449 00:25:55.929959 RO MCACHE 2. 0xffffc000 0x00001104
9450 00:25:55.933417 CONSOLE 3. 0xfff7c000 0x00080000
9451 00:25:55.937168 FMAP 4. 0xfff7b000 0x00000452
9452 00:25:55.940765 TIME STAMP 5. 0xfff7a000 0x00000910
9453 00:25:55.943545 VBOOT WORK 6. 0xfff66000 0x00014000
9454 00:25:55.947022 RAMOOPS 7. 0xffe66000 0x00100000
9455 00:25:55.950404 COREBOOT 8. 0xffe64000 0x00002000
9456 00:25:55.950891 IMD small region:
9457 00:25:55.953570 IMD ROOT 0. 0xffffec00 0x00000400
9458 00:25:55.956834 VPD 1. 0xffffeb80 0x0000006c
9459 00:25:55.960318 MMC STATUS 2. 0xffffeb60 0x00000004
9460 00:25:55.966608 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9461 00:25:55.967001 Probing TPM: done!
9462 00:25:55.973514 Connected to device vid:did:rid of 1ae0:0028:00
9463 00:25:55.980471 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9464 00:25:55.988222 Initialized TPM device CR50 revision 0
9465 00:25:55.988690 Checking cr50 for pending updates
9466 00:25:55.993574 Reading cr50 TPM mode
9467 00:25:56.002381 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9468 00:25:56.009399 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9469 00:25:56.049106 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9470 00:25:56.052705 Checking segment from ROM address 0x40100000
9471 00:25:56.055597 Checking segment from ROM address 0x4010001c
9472 00:25:56.062634 Loading segment from ROM address 0x40100000
9473 00:25:56.063103 code (compression=0)
9474 00:25:56.068691 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9475 00:25:56.079400 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9476 00:25:56.079867 it's not compressed!
9477 00:25:56.086405 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9478 00:25:56.089525 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9479 00:25:56.109601 Loading segment from ROM address 0x4010001c
9480 00:25:56.110113 Entry Point 0x80000000
9481 00:25:56.112518 Loaded segments
9482 00:25:56.116029 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9483 00:25:56.122812 Jumping to boot code at 0x80000000(0xffe64000)
9484 00:25:56.129394 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9485 00:25:56.136155 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9486 00:25:56.143821 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9487 00:25:56.146798 Checking segment from ROM address 0x40100000
9488 00:25:56.150200 Checking segment from ROM address 0x4010001c
9489 00:25:56.157170 Loading segment from ROM address 0x40100000
9490 00:25:56.157639 code (compression=1)
9491 00:25:56.163775 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9492 00:25:56.174127 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9493 00:25:56.174604 using LZMA
9494 00:25:56.182195 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9495 00:25:56.189086 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9496 00:25:56.192703 Loading segment from ROM address 0x4010001c
9497 00:25:56.193174 Entry Point 0x54601000
9498 00:25:56.195289 Loaded segments
9499 00:25:56.198471 NOTICE: MT8192 bl31_setup
9500 00:25:56.205768 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9501 00:25:56.209212 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9502 00:25:56.212755 WARNING: region 0:
9503 00:25:56.215376 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9504 00:25:56.215771 WARNING: region 1:
9505 00:25:56.222835 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9506 00:25:56.225514 WARNING: region 2:
9507 00:25:56.228870 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9508 00:25:56.232299 WARNING: region 3:
9509 00:25:56.235904 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9510 00:25:56.239456 WARNING: region 4:
9511 00:25:56.242512 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9512 00:25:56.245394 WARNING: region 5:
9513 00:25:56.248810 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9514 00:25:56.252640 WARNING: region 6:
9515 00:25:56.255882 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9516 00:25:56.256348 WARNING: region 7:
9517 00:25:56.262343 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9518 00:25:56.269053 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9519 00:25:56.272902 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9520 00:25:56.275835 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9521 00:25:56.282898 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9522 00:25:56.286149 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9523 00:25:56.290024 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9524 00:25:56.295985 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9525 00:25:56.299367 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9526 00:25:56.302539 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9527 00:25:56.309250 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9528 00:25:56.312716 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9529 00:25:56.316000 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9530 00:25:56.322867 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9531 00:25:56.325648 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9532 00:25:56.333157 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9533 00:25:56.336092 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9534 00:25:56.339437 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9535 00:25:56.346340 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9536 00:25:56.349513 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9537 00:25:56.353313 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9538 00:25:56.359880 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9539 00:25:56.362842 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9540 00:25:56.369450 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9541 00:25:56.373139 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9542 00:25:56.376565 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9543 00:25:56.382907 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9544 00:25:56.386550 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9545 00:25:56.392858 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9546 00:25:56.396107 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9547 00:25:56.399833 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9548 00:25:56.406370 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9549 00:25:56.409490 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9550 00:25:56.412995 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9551 00:25:56.419458 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9552 00:25:56.422776 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9553 00:25:56.426207 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9554 00:25:56.429282 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9555 00:25:56.436281 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9556 00:25:56.440000 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9557 00:25:56.442813 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9558 00:25:56.446330 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9559 00:25:56.449743 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9560 00:25:56.456523 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9561 00:25:56.459535 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9562 00:25:56.463261 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9563 00:25:56.469730 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9564 00:25:56.473234 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9565 00:25:56.476331 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9566 00:25:56.479974 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9567 00:25:56.486486 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9568 00:25:56.490178 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9569 00:25:56.497022 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9570 00:25:56.500485 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9571 00:25:56.502989 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9572 00:25:56.510535 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9573 00:25:56.513617 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9574 00:25:56.520311 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9575 00:25:56.523317 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9576 00:25:56.530726 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9577 00:25:56.533313 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9578 00:25:56.537197 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9579 00:25:56.543413 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9580 00:25:56.546464 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9581 00:25:56.553364 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9582 00:25:56.556927 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9583 00:25:56.563417 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9584 00:25:56.566857 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9585 00:25:56.570155 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9586 00:25:56.577061 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9587 00:25:56.580317 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9588 00:25:56.586872 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9589 00:25:56.589953 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9590 00:25:56.597422 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9591 00:25:56.600724 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9592 00:25:56.603373 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9593 00:25:56.610924 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9594 00:25:56.613808 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9595 00:25:56.620689 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9596 00:25:56.623525 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9597 00:25:56.630498 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9598 00:25:56.633637 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9599 00:25:56.637252 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9600 00:25:56.644294 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9601 00:25:56.647105 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9602 00:25:56.653620 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9603 00:25:56.657340 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9604 00:25:56.664098 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9605 00:25:56.667541 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9606 00:25:56.670570 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9607 00:25:56.677622 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9608 00:25:56.680766 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9609 00:25:56.687374 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9610 00:25:56.690656 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9611 00:25:56.694036 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9612 00:25:56.700986 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9613 00:25:56.703928 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9614 00:25:56.710678 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9615 00:25:56.714270 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9616 00:25:56.717836 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9617 00:25:56.720746 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9618 00:25:56.728080 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9619 00:25:56.730790 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9620 00:25:56.734098 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9621 00:25:56.741288 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9622 00:25:56.744650 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9623 00:25:56.750775 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9624 00:25:56.754170 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9625 00:25:56.757473 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9626 00:25:56.764687 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9627 00:25:56.767820 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9628 00:25:56.771208 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9629 00:25:56.777715 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9630 00:25:56.780888 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9631 00:25:56.787850 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9632 00:25:56.791069 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9633 00:25:56.794373 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9634 00:25:56.801668 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9635 00:25:56.804784 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9636 00:25:56.807799 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9637 00:25:56.814597 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9638 00:25:56.818399 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9639 00:25:56.821695 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9640 00:25:56.824545 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9641 00:25:56.828415 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9642 00:25:56.834968 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9643 00:25:56.838440 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9644 00:25:56.844933 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9645 00:25:56.848368 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9646 00:25:56.851774 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9647 00:25:56.858685 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9648 00:25:56.862058 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9649 00:25:56.865132 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9650 00:25:56.871709 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9651 00:25:56.875577 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9652 00:25:56.881614 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9653 00:25:56.884906 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9654 00:25:56.888589 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9655 00:25:56.895422 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9656 00:25:56.898891 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9657 00:25:56.905243 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9658 00:25:56.908993 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9659 00:25:56.912094 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9660 00:25:56.918666 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9661 00:25:56.922289 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9662 00:25:56.925380 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9663 00:25:56.931787 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9664 00:25:56.935342 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9665 00:25:56.942659 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9666 00:25:56.945748 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9667 00:25:56.949162 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9668 00:25:56.955715 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9669 00:25:56.958821 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9670 00:25:56.962717 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9671 00:25:56.969403 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9672 00:25:56.972202 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9673 00:25:56.978966 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9674 00:25:56.982607 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9675 00:25:56.985833 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9676 00:25:56.992385 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9677 00:25:56.995917 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9678 00:25:56.999251 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9679 00:25:57.005674 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9680 00:25:57.009500 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9681 00:25:57.015595 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9682 00:25:57.019213 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9683 00:25:57.022401 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9684 00:25:57.028957 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9685 00:25:57.032520 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9686 00:25:57.039004 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9687 00:25:57.042335 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9688 00:25:57.045457 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9689 00:25:57.052481 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9690 00:25:57.055672 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9691 00:25:57.058977 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9692 00:25:57.066164 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9693 00:25:57.069112 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9694 00:25:57.075677 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9695 00:25:57.078944 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9696 00:25:57.082383 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9697 00:25:57.089216 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9698 00:25:57.092573 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9699 00:25:57.099024 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9700 00:25:57.102198 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9701 00:25:57.105852 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9702 00:25:57.112229 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9703 00:25:57.116109 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9704 00:25:57.118671 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9705 00:25:57.125475 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9706 00:25:57.128773 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9707 00:25:57.135904 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9708 00:25:57.138745 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9709 00:25:57.146059 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9710 00:25:57.149171 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9711 00:25:57.152503 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9712 00:25:57.158733 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9713 00:25:57.162613 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9714 00:25:57.169110 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9715 00:25:57.172100 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9716 00:25:57.176100 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9717 00:25:57.182374 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9718 00:25:57.186147 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9719 00:25:57.192770 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9720 00:25:57.196263 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9721 00:25:57.199133 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9722 00:25:57.206197 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9723 00:25:57.209193 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9724 00:25:57.216160 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9725 00:25:57.219061 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9726 00:25:57.222319 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9727 00:25:57.228934 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9728 00:25:57.232560 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9729 00:25:57.239566 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9730 00:25:57.242451 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9731 00:25:57.249200 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9732 00:25:57.252203 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9733 00:25:57.255668 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9734 00:25:57.262378 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9735 00:25:57.265470 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9736 00:25:57.272152 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9737 00:25:57.275671 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9738 00:25:57.278856 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9739 00:25:57.285514 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9740 00:25:57.289187 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9741 00:25:57.295465 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9742 00:25:57.299080 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9743 00:25:57.305595 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9744 00:25:57.309128 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9745 00:25:57.312935 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9746 00:25:57.319187 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9747 00:25:57.322039 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9748 00:25:57.325505 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9749 00:25:57.328915 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9750 00:25:57.335898 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9751 00:25:57.338899 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9752 00:25:57.341769 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9753 00:25:57.349011 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9754 00:25:57.352373 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9755 00:25:57.355179 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9756 00:25:57.361688 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9757 00:25:57.365703 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9758 00:25:57.368724 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9759 00:25:57.375349 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9760 00:25:57.378369 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9761 00:25:57.381554 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9762 00:25:57.388628 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9763 00:25:57.391805 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9764 00:25:57.398865 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9765 00:25:57.402473 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9766 00:25:57.405543 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9767 00:25:57.412228 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9768 00:25:57.415441 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9769 00:25:57.418886 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9770 00:25:57.425567 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9771 00:25:57.428300 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9772 00:25:57.431909 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9773 00:25:57.438323 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9774 00:25:57.442012 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9775 00:25:57.448295 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9776 00:25:57.452036 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9777 00:25:57.455506 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9778 00:25:57.462138 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9779 00:25:57.465174 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9780 00:25:57.469079 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9781 00:25:57.474969 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9782 00:25:57.478719 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9783 00:25:57.481847 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9784 00:25:57.488432 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9785 00:25:57.491801 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9786 00:25:57.494933 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9787 00:25:57.501932 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9788 00:25:57.504832 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9789 00:25:57.508632 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9790 00:25:57.511728 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9791 00:25:57.515017 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9792 00:25:57.521567 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9793 00:25:57.525648 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9794 00:25:57.528746 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9795 00:25:57.535106 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9796 00:25:57.538823 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9797 00:25:57.541652 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9798 00:25:57.544969 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9799 00:25:57.551280 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9800 00:25:57.555000 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9801 00:25:57.561973 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9802 00:25:57.565085 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9803 00:25:57.568514 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9804 00:25:57.575032 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9805 00:25:57.578312 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9806 00:25:57.585013 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9807 00:25:57.588077 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9808 00:25:57.591939 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9809 00:25:57.598145 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9810 00:25:57.601498 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9811 00:25:57.608550 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9812 00:25:57.611527 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9813 00:25:57.617904 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9814 00:25:57.621362 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9815 00:25:57.624207 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9816 00:25:57.631193 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9817 00:25:57.634614 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9818 00:25:57.641174 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9819 00:25:57.644128 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9820 00:25:57.647731 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9821 00:25:57.654176 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9822 00:25:57.658148 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9823 00:25:57.664079 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9824 00:25:57.667380 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9825 00:25:57.671628 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9826 00:25:57.678244 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9827 00:25:57.680840 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9828 00:25:57.688135 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9829 00:25:57.690959 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9830 00:25:57.694131 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9831 00:25:57.700939 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9832 00:25:57.704489 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9833 00:25:57.710963 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9834 00:25:57.714013 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9835 00:25:57.717546 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9836 00:25:57.724276 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9837 00:25:57.727477 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9838 00:25:57.734424 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9839 00:25:57.737567 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9840 00:25:57.741101 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9841 00:25:57.747814 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9842 00:25:57.751029 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9843 00:25:57.757447 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9844 00:25:57.760756 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9845 00:25:57.767536 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9846 00:25:57.770686 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9847 00:25:57.774467 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9848 00:25:57.781036 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9849 00:25:57.784319 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9850 00:25:57.791053 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9851 00:25:57.794758 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9852 00:25:57.797240 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9853 00:25:57.804342 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9854 00:25:57.807517 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9855 00:25:57.811203 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9856 00:25:57.817440 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9857 00:25:57.820593 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9858 00:25:57.827691 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9859 00:25:57.830661 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9860 00:25:57.837584 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9861 00:25:57.840849 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9862 00:25:57.843950 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9863 00:25:57.850570 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9864 00:25:57.854043 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9865 00:25:57.860416 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9866 00:25:57.863864 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9867 00:25:57.867376 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9868 00:25:57.874016 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9869 00:25:57.877352 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9870 00:25:57.884552 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9871 00:25:57.887218 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9872 00:25:57.890602 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9873 00:25:57.897362 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9874 00:25:57.900883 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9875 00:25:57.907335 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9876 00:25:57.910710 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9877 00:25:57.917392 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9878 00:25:57.921416 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9879 00:25:57.924041 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9880 00:25:57.930524 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9881 00:25:57.934136 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9882 00:25:57.941110 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9883 00:25:57.943698 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9884 00:25:57.950680 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9885 00:25:57.953685 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9886 00:25:57.960251 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9887 00:25:57.963706 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9888 00:25:57.967226 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9889 00:25:57.973889 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9890 00:25:57.977286 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9891 00:25:57.983690 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9892 00:25:57.986851 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9893 00:25:57.993663 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9894 00:25:57.996982 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9895 00:25:58.000838 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9896 00:25:58.007151 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9897 00:25:58.010665 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9898 00:25:58.017140 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9899 00:25:58.020380 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9900 00:25:58.026864 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9901 00:25:58.030490 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9902 00:25:58.034052 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9903 00:25:58.040394 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9904 00:25:58.043742 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9905 00:25:58.050181 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9906 00:25:58.054076 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9907 00:25:58.060304 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9908 00:25:58.063746 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9909 00:25:58.067320 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9910 00:25:58.074067 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9911 00:25:58.077743 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9912 00:25:58.083927 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9913 00:25:58.086885 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9914 00:25:58.093898 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9915 00:25:58.097291 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9916 00:25:58.100710 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9917 00:25:58.107162 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9918 00:25:58.110525 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9919 00:25:58.117220 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9920 00:25:58.120058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9921 00:25:58.123485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9922 00:25:58.130606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9923 00:25:58.133656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9924 00:25:58.140759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9925 00:25:58.143920 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9926 00:25:58.150494 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9927 00:25:58.153634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9928 00:25:58.160249 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9929 00:25:58.163534 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9930 00:25:58.170116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9931 00:25:58.173539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9932 00:25:58.180137 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9933 00:25:58.183870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9934 00:25:58.190621 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9935 00:25:58.193692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9936 00:25:58.200280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9937 00:25:58.203601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9938 00:25:58.206948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9939 00:25:58.213219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9940 00:25:58.217087 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9941 00:25:58.223176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9942 00:25:58.226870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9943 00:25:58.233630 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9944 00:25:58.236437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9945 00:25:58.243713 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9946 00:25:58.247160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9947 00:25:58.253387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9948 00:25:58.256329 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9949 00:25:58.263855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9950 00:25:58.270659 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9951 00:25:58.273139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9952 00:25:58.276789 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9953 00:25:58.280395 INFO: [APUAPC] vio 0
9954 00:25:58.283148 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9955 00:25:58.289753 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9956 00:25:58.293574 INFO: [APUAPC] D0_APC_0: 0x400510
9957 00:25:58.296712 INFO: [APUAPC] D0_APC_1: 0x0
9958 00:25:58.297179 INFO: [APUAPC] D0_APC_2: 0x1540
9959 00:25:58.300255 INFO: [APUAPC] D0_APC_3: 0x0
9960 00:25:58.303529 INFO: [APUAPC] D1_APC_0: 0xffffffff
9961 00:25:58.306775 INFO: [APUAPC] D1_APC_1: 0xffffffff
9962 00:25:58.310204 INFO: [APUAPC] D1_APC_2: 0x3fffff
9963 00:25:58.313472 INFO: [APUAPC] D1_APC_3: 0x0
9964 00:25:58.316730 INFO: [APUAPC] D2_APC_0: 0xffffffff
9965 00:25:58.320139 INFO: [APUAPC] D2_APC_1: 0xffffffff
9966 00:25:58.323260 INFO: [APUAPC] D2_APC_2: 0x3fffff
9967 00:25:58.326631 INFO: [APUAPC] D2_APC_3: 0x0
9968 00:25:58.330250 INFO: [APUAPC] D3_APC_0: 0xffffffff
9969 00:25:58.333519 INFO: [APUAPC] D3_APC_1: 0xffffffff
9970 00:25:58.336438 INFO: [APUAPC] D3_APC_2: 0x3fffff
9971 00:25:58.340242 INFO: [APUAPC] D3_APC_3: 0x0
9972 00:25:58.343841 INFO: [APUAPC] D4_APC_0: 0xffffffff
9973 00:25:58.346475 INFO: [APUAPC] D4_APC_1: 0xffffffff
9974 00:25:58.350154 INFO: [APUAPC] D4_APC_2: 0x3fffff
9975 00:25:58.353564 INFO: [APUAPC] D4_APC_3: 0x0
9976 00:25:58.356497 INFO: [APUAPC] D5_APC_0: 0xffffffff
9977 00:25:58.359974 INFO: [APUAPC] D5_APC_1: 0xffffffff
9978 00:25:58.363586 INFO: [APUAPC] D5_APC_2: 0x3fffff
9979 00:25:58.366678 INFO: [APUAPC] D5_APC_3: 0x0
9980 00:25:58.369970 INFO: [APUAPC] D6_APC_0: 0xffffffff
9981 00:25:58.373092 INFO: [APUAPC] D6_APC_1: 0xffffffff
9982 00:25:58.376867 INFO: [APUAPC] D6_APC_2: 0x3fffff
9983 00:25:58.380202 INFO: [APUAPC] D6_APC_3: 0x0
9984 00:25:58.383030 INFO: [APUAPC] D7_APC_0: 0xffffffff
9985 00:25:58.386546 INFO: [APUAPC] D7_APC_1: 0xffffffff
9986 00:25:58.390044 INFO: [APUAPC] D7_APC_2: 0x3fffff
9987 00:25:58.392956 INFO: [APUAPC] D7_APC_3: 0x0
9988 00:25:58.396456 INFO: [APUAPC] D8_APC_0: 0xffffffff
9989 00:25:58.399947 INFO: [APUAPC] D8_APC_1: 0xffffffff
9990 00:25:58.403305 INFO: [APUAPC] D8_APC_2: 0x3fffff
9991 00:25:58.406460 INFO: [APUAPC] D8_APC_3: 0x0
9992 00:25:58.409819 INFO: [APUAPC] D9_APC_0: 0xffffffff
9993 00:25:58.412643 INFO: [APUAPC] D9_APC_1: 0xffffffff
9994 00:25:58.416626 INFO: [APUAPC] D9_APC_2: 0x3fffff
9995 00:25:58.420200 INFO: [APUAPC] D9_APC_3: 0x0
9996 00:25:58.423195 INFO: [APUAPC] D10_APC_0: 0xffffffff
9997 00:25:58.426664 INFO: [APUAPC] D10_APC_1: 0xffffffff
9998 00:25:58.430116 INFO: [APUAPC] D10_APC_2: 0x3fffff
9999 00:25:58.433447 INFO: [APUAPC] D10_APC_3: 0x0
10000 00:25:58.435973 INFO: [APUAPC] D11_APC_0: 0xffffffff
10001 00:25:58.439686 INFO: [APUAPC] D11_APC_1: 0xffffffff
10002 00:25:58.442820 INFO: [APUAPC] D11_APC_2: 0x3fffff
10003 00:25:58.446175 INFO: [APUAPC] D11_APC_3: 0x0
10004 00:25:58.449957 INFO: [APUAPC] D12_APC_0: 0xffffffff
10005 00:25:58.453356 INFO: [APUAPC] D12_APC_1: 0xffffffff
10006 00:25:58.456946 INFO: [APUAPC] D12_APC_2: 0x3fffff
10007 00:25:58.459568 INFO: [APUAPC] D12_APC_3: 0x0
10008 00:25:58.463303 INFO: [APUAPC] D13_APC_0: 0xffffffff
10009 00:25:58.466241 INFO: [APUAPC] D13_APC_1: 0xffffffff
10010 00:25:58.469575 INFO: [APUAPC] D13_APC_2: 0x3fffff
10011 00:25:58.472888 INFO: [APUAPC] D13_APC_3: 0x0
10012 00:25:58.476111 INFO: [APUAPC] D14_APC_0: 0xffffffff
10013 00:25:58.479918 INFO: [APUAPC] D14_APC_1: 0xffffffff
10014 00:25:58.482860 INFO: [APUAPC] D14_APC_2: 0x3fffff
10015 00:25:58.486220 INFO: [APUAPC] D14_APC_3: 0x0
10016 00:25:58.489569 INFO: [APUAPC] D15_APC_0: 0xffffffff
10017 00:25:58.493178 INFO: [APUAPC] D15_APC_1: 0xffffffff
10018 00:25:58.496605 INFO: [APUAPC] D15_APC_2: 0x3fffff
10019 00:25:58.500081 INFO: [APUAPC] D15_APC_3: 0x0
10020 00:25:58.500548 INFO: [APUAPC] APC_CON: 0x4
10021 00:25:58.502679 INFO: [NOCDAPC] D0_APC_0: 0x0
10022 00:25:58.506295 INFO: [NOCDAPC] D0_APC_1: 0x0
10023 00:25:58.509938 INFO: [NOCDAPC] D1_APC_0: 0x0
10024 00:25:58.512967 INFO: [NOCDAPC] D1_APC_1: 0xfff
10025 00:25:58.516317 INFO: [NOCDAPC] D2_APC_0: 0x0
10026 00:25:58.519974 INFO: [NOCDAPC] D2_APC_1: 0xfff
10027 00:25:58.522586 INFO: [NOCDAPC] D3_APC_0: 0x0
10028 00:25:58.526087 INFO: [NOCDAPC] D3_APC_1: 0xfff
10029 00:25:58.529324 INFO: [NOCDAPC] D4_APC_0: 0x0
10030 00:25:58.529719 INFO: [NOCDAPC] D4_APC_1: 0xfff
10031 00:25:58.533222 INFO: [NOCDAPC] D5_APC_0: 0x0
10032 00:25:58.536381 INFO: [NOCDAPC] D5_APC_1: 0xfff
10033 00:25:58.539315 INFO: [NOCDAPC] D6_APC_0: 0x0
10034 00:25:58.542967 INFO: [NOCDAPC] D6_APC_1: 0xfff
10035 00:25:58.545715 INFO: [NOCDAPC] D7_APC_0: 0x0
10036 00:25:58.549338 INFO: [NOCDAPC] D7_APC_1: 0xfff
10037 00:25:58.552795 INFO: [NOCDAPC] D8_APC_0: 0x0
10038 00:25:58.555785 INFO: [NOCDAPC] D8_APC_1: 0xfff
10039 00:25:58.559323 INFO: [NOCDAPC] D9_APC_0: 0x0
10040 00:25:58.562436 INFO: [NOCDAPC] D9_APC_1: 0xfff
10041 00:25:58.562826 INFO: [NOCDAPC] D10_APC_0: 0x0
10042 00:25:58.565895 INFO: [NOCDAPC] D10_APC_1: 0xfff
10043 00:25:58.569748 INFO: [NOCDAPC] D11_APC_0: 0x0
10044 00:25:58.573199 INFO: [NOCDAPC] D11_APC_1: 0xfff
10045 00:25:58.576537 INFO: [NOCDAPC] D12_APC_0: 0x0
10046 00:25:58.579590 INFO: [NOCDAPC] D12_APC_1: 0xfff
10047 00:25:58.582736 INFO: [NOCDAPC] D13_APC_0: 0x0
10048 00:25:58.586277 INFO: [NOCDAPC] D13_APC_1: 0xfff
10049 00:25:58.589319 INFO: [NOCDAPC] D14_APC_0: 0x0
10050 00:25:58.592573 INFO: [NOCDAPC] D14_APC_1: 0xfff
10051 00:25:58.596388 INFO: [NOCDAPC] D15_APC_0: 0x0
10052 00:25:58.599870 INFO: [NOCDAPC] D15_APC_1: 0xfff
10053 00:25:58.602729 INFO: [NOCDAPC] APC_CON: 0x4
10054 00:25:58.606191 INFO: [APUAPC] set_apusys_apc done
10055 00:25:58.609276 INFO: [DEVAPC] devapc_init done
10056 00:25:58.612310 INFO: GICv3 without legacy support detected.
10057 00:25:58.616301 INFO: ARM GICv3 driver initialized in EL3
10058 00:25:58.619410 INFO: Maximum SPI INTID supported: 639
10059 00:25:58.622883 INFO: BL31: Initializing runtime services
10060 00:25:58.629172 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10061 00:25:58.633137 INFO: SPM: enable CPC mode
10062 00:25:58.635591 INFO: mcdi ready for mcusys-off-idle and system suspend
10063 00:25:58.642485 INFO: BL31: Preparing for EL3 exit to normal world
10064 00:25:58.646177 INFO: Entry point address = 0x80000000
10065 00:25:58.649198 INFO: SPSR = 0x8
10066 00:25:58.653648
10067 00:25:58.654164
10068 00:25:58.654477
10069 00:25:58.656979 Starting depthcharge on Spherion...
10070 00:25:58.657377
10071 00:25:58.657692 Wipe memory regions:
10072 00:25:58.657974
10073 00:25:58.660397 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10074 00:25:58.660861 start: 2.2.4 bootloader-commands (timeout 00:04:24) [common]
10075 00:25:58.661224 Setting prompt string to ['asurada:']
10076 00:25:58.661591 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:24)
10077 00:25:58.662238 [0x00000040000000, 0x00000054600000)
10078 00:25:58.782903
10079 00:25:58.783369 [0x00000054660000, 0x00000080000000)
10080 00:25:59.043092
10081 00:25:59.043766 [0x000000821a7280, 0x000000ffe64000)
10082 00:25:59.787841
10083 00:25:59.788310 [0x00000100000000, 0x00000240000000)
10084 00:26:01.678024
10085 00:26:01.680668 Initializing XHCI USB controller at 0x11200000.
10086 00:26:02.719624
10087 00:26:02.723184 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10088 00:26:02.723656
10089 00:26:02.723964
10090 00:26:02.724675 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10092 00:26:02.825767 asurada: tftpboot 192.168.201.1 14479197/tftp-deploy-n9hju5wc/kernel/image.itb 14479197/tftp-deploy-n9hju5wc/kernel/cmdline
10093 00:26:02.826409 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10094 00:26:02.826788 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10095 00:26:02.831418 tftpboot 192.168.201.1 14479197/tftp-deploy-n9hju5wc/kernel/image.ittp-deploy-n9hju5wc/kernel/cmdline
10096 00:26:02.831812
10097 00:26:02.832112 Waiting for link
10098 00:26:02.990066
10099 00:26:02.990531 R8152: Initializing
10100 00:26:02.990842
10101 00:26:02.992981 Version 6 (ocp_data = 5c30)
10102 00:26:02.993452
10103 00:26:02.996180 R8152: Done initializing
10104 00:26:02.996567
10105 00:26:02.996867 Adding net device
10106 00:26:04.961062
10107 00:26:04.961538 done.
10108 00:26:04.961845
10109 00:26:04.962187 MAC: 00:24:32:30:78:52
10110 00:26:04.962533
10111 00:26:04.964519 Sending DHCP discover... done.
10112 00:26:04.964991
10113 00:26:04.968071 Waiting for reply... done.
10114 00:26:04.968534
10115 00:26:04.970529 Sending DHCP request... done.
10116 00:26:04.970915
10117 00:26:04.974374 Waiting for reply... done.
10118 00:26:04.974849
10119 00:26:04.975157 My ip is 192.168.201.14
10120 00:26:04.975439
10121 00:26:04.977393 The DHCP server ip is 192.168.201.1
10122 00:26:04.977783
10123 00:26:04.980601 TFTP server IP predefined by user: 192.168.201.1
10124 00:26:04.981073
10125 00:26:04.987181 Bootfile predefined by user: 14479197/tftp-deploy-n9hju5wc/kernel/image.itb
10126 00:26:04.987575
10127 00:26:04.990874 Sending tftp read request... done.
10128 00:26:04.991275
10129 00:26:05.001016 Waiting for the transfer...
10130 00:26:05.001506
10131 00:26:05.729707 00000000 ################################################################
10132 00:26:05.730223
10133 00:26:06.475551 00080000 ################################################################
10134 00:26:06.476016
10135 00:26:07.218405 00100000 ################################################################
10136 00:26:07.218870
10137 00:26:07.948618 00180000 ################################################################
10138 00:26:07.949150
10139 00:26:08.705159 00200000 ################################################################
10140 00:26:08.705637
10141 00:26:09.455427 00280000 ################################################################
10142 00:26:09.455909
10143 00:26:10.184345 00300000 ################################################################
10144 00:26:10.184768
10145 00:26:10.934480 00380000 ################################################################
10146 00:26:10.934941
10147 00:26:11.671550 00400000 ################################################################
10148 00:26:11.672055
10149 00:26:12.393646 00480000 ################################################################
10150 00:26:12.394153
10151 00:26:13.125230 00500000 ################################################################
10152 00:26:13.125748
10153 00:26:13.858668 00580000 ################################################################
10154 00:26:13.859176
10155 00:26:14.593067 00600000 ################################################################
10156 00:26:14.593581
10157 00:26:15.317750 00680000 ################################################################
10158 00:26:15.318411
10159 00:26:16.056525 00700000 ################################################################
10160 00:26:16.057116
10161 00:26:16.795985 00780000 ################################################################
10162 00:26:16.796450
10163 00:26:17.481048 00800000 ################################################################
10164 00:26:17.481177
10165 00:26:18.167654 00880000 ################################################################
10166 00:26:18.168117
10167 00:26:18.885802 00900000 ################################################################
10168 00:26:18.886309
10169 00:26:19.625312 00980000 ################################################################
10170 00:26:19.625812
10171 00:26:20.356189 00a00000 ################################################################
10172 00:26:20.356691
10173 00:26:21.070909 00a80000 ################################################################
10174 00:26:21.071060
10175 00:26:21.774173 00b00000 ################################################################
10176 00:26:21.774669
10177 00:26:22.489032 00b80000 ################################################################
10178 00:26:22.489537
10179 00:26:23.236041 00c00000 ################################################################
10180 00:26:23.236522
10181 00:26:23.969538 00c80000 ################################################################
10182 00:26:23.970073
10183 00:26:24.707172 00d00000 ################################################################
10184 00:26:24.707699
10185 00:26:25.392611 00d80000 ################################################################
10186 00:26:25.392776
10187 00:26:26.114542 00e00000 ################################################################
10188 00:26:26.115008
10189 00:26:26.853092 00e80000 ################################################################
10190 00:26:26.853683
10191 00:26:27.591438 00f00000 ################################################################
10192 00:26:27.591897
10193 00:26:28.328771 00f80000 ################################################################
10194 00:26:28.329238
10195 00:26:29.070186 01000000 ################################################################
10196 00:26:29.070659
10197 00:26:29.806371 01080000 ################################################################
10198 00:26:29.806860
10199 00:26:30.514574 01100000 ################################################################
10200 00:26:30.515057
10201 00:26:31.257285 01180000 ################################################################
10202 00:26:31.257764
10203 00:26:32.003848 01200000 ################################################################
10204 00:26:32.004320
10205 00:26:32.723456 01280000 ################################################################
10206 00:26:32.723924
10207 00:26:33.439615 01300000 ################################################################
10208 00:26:33.440396
10209 00:26:34.184419 01380000 ################################################################
10210 00:26:34.184931
10211 00:26:34.924992 01400000 ################################################################
10212 00:26:34.925653
10213 00:26:35.683845 01480000 ################################################################
10214 00:26:35.684348
10215 00:26:36.400779 01500000 ################################################################
10216 00:26:36.401281
10217 00:26:37.125366 01580000 ################################################################
10218 00:26:37.125890
10219 00:26:37.857577 01600000 ################################################################
10220 00:26:37.858106
10221 00:26:38.564944 01680000 ################################################################
10222 00:26:38.565076
10223 00:26:39.277290 01700000 ################################################################
10224 00:26:39.277789
10225 00:26:40.011110 01780000 ################################################################
10226 00:26:40.011596
10227 00:26:40.729893 01800000 ################################################################
10228 00:26:40.730417
10229 00:26:41.465607 01880000 ################################################################
10230 00:26:41.466141
10231 00:26:42.181954 01900000 ################################################################
10232 00:26:42.182623
10233 00:26:42.788028 01980000 ################################################################
10234 00:26:42.788158
10235 00:26:43.355868 01a00000 ################################################################
10236 00:26:43.355998
10237 00:26:43.942879 01a80000 ################################################################
10238 00:26:43.943037
10239 00:26:44.522360 01b00000 ################################################################
10240 00:26:44.522486
10241 00:26:45.102765 01b80000 ################################################################
10242 00:26:45.102897
10243 00:26:45.687125 01c00000 ################################################################
10244 00:26:45.687252
10245 00:26:46.268898 01c80000 ################################################################
10246 00:26:46.269025
10247 00:26:46.865406 01d00000 ################################################################
10248 00:26:46.865532
10249 00:26:47.449943 01d80000 ################################################################
10250 00:26:47.450080
10251 00:26:47.967995 01e00000 ######################################################### done.
10252 00:26:47.968117
10253 00:26:47.971441 The bootfile was 31923610 bytes long.
10254 00:26:47.971519
10255 00:26:47.974396 Sending tftp read request... done.
10256 00:26:47.974472
10257 00:26:47.974530 Waiting for the transfer...
10258 00:26:47.974591
10259 00:26:47.978304 00000000 # done.
10260 00:26:47.978382
10261 00:26:47.984411 Command line loaded dynamically from TFTP file: 14479197/tftp-deploy-n9hju5wc/kernel/cmdline
10262 00:26:47.984495
10263 00:26:48.007980 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14479197/extract-nfsrootfs-dddnrq79,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10264 00:26:48.008159
10265 00:26:48.008283 Loading FIT.
10266 00:26:48.008400
10267 00:26:48.011455 Image ramdisk-1 has 18749430 bytes.
10268 00:26:48.011531
10269 00:26:48.014905 Image fdt-1 has 47258 bytes.
10270 00:26:48.014981
10271 00:26:48.017930 Image kernel-1 has 13124896 bytes.
10272 00:26:48.018045
10273 00:26:48.028040 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10274 00:26:48.028118
10275 00:26:48.044710 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10276 00:26:48.044795
10277 00:26:48.048097 Choosing best match conf-1 for compat google,spherion-rev2.
10278 00:26:48.053884
10279 00:26:48.058719 Connected to device vid:did:rid of 1ae0:0028:00
10280 00:26:48.065053
10281 00:26:48.068572 tpm_get_response: command 0x17b, return code 0x0
10282 00:26:48.068648
10283 00:26:48.071934 ec_init: CrosEC protocol v3 supported (256, 248)
10284 00:26:48.076077
10285 00:26:48.079097 tpm_cleanup: add release locality here.
10286 00:26:48.079175
10287 00:26:48.079235 Shutting down all USB controllers.
10288 00:26:48.082885
10289 00:26:48.082961 Removing current net device
10290 00:26:48.083020
10291 00:26:48.089393 Exiting depthcharge with code 4 at timestamp: 78777236
10292 00:26:48.089493
10293 00:26:48.092537 LZMA decompressing kernel-1 to 0x821a6718
10294 00:26:48.092612
10295 00:26:48.095984 LZMA decompressing kernel-1 to 0x40000000
10296 00:26:49.712403
10297 00:26:49.712521 jumping to kernel
10298 00:26:49.713007 end: 2.2.4 bootloader-commands (duration 00:00:51) [common]
10299 00:26:49.713098 start: 2.2.5 auto-login-action (timeout 00:03:33) [common]
10300 00:26:49.713167 Setting prompt string to ['Linux version [0-9]']
10301 00:26:49.713228 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10302 00:26:49.713289 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10303 00:26:49.794357
10304 00:26:49.797691 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10305 00:26:49.801425 start: 2.2.5.1 login-action (timeout 00:03:33) [common]
10306 00:26:49.801520 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10307 00:26:49.801588 Setting prompt string to []
10308 00:26:49.801657 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10309 00:26:49.801723 Using line separator: #'\n'#
10310 00:26:49.801777 No login prompt set.
10311 00:26:49.801833 Parsing kernel messages
10312 00:26:49.801883 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10313 00:26:49.801986 [login-action] Waiting for messages, (timeout 00:03:33)
10314 00:26:49.802086 Waiting using forced prompt support (timeout 00:01:46)
10315 00:26:49.821042 [ 0.000000] Linux version 6.1.94-cip23 (KernelCI@build-j239242-arm64-gcc-10-defconfig-arm64-chromebook-c5lwc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024
10316 00:26:49.824716 [ 0.000000] random: crng init done
10317 00:26:49.831203 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10318 00:26:49.834775 [ 0.000000] efi: UEFI not found.
10319 00:26:49.841072 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10320 00:26:49.847724 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10321 00:26:49.857643 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10322 00:26:49.867816 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10323 00:26:49.874176 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10324 00:26:49.880925 [ 0.000000] printk: bootconsole [mtk8250] enabled
10325 00:26:49.887471 [ 0.000000] NUMA: No NUMA configuration found
10326 00:26:49.894549 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10327 00:26:49.897846 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10328 00:26:49.900694 [ 0.000000] Zone ranges:
10329 00:26:49.907617 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10330 00:26:49.910934 [ 0.000000] DMA32 empty
10331 00:26:49.917269 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10332 00:26:49.920806 [ 0.000000] Movable zone start for each node
10333 00:26:49.923999 [ 0.000000] Early memory node ranges
10334 00:26:49.930767 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10335 00:26:49.937296 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10336 00:26:49.943807 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10337 00:26:49.947355 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10338 00:26:49.953853 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10339 00:26:49.960907 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10340 00:26:50.019391 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10341 00:26:50.025939 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10342 00:26:50.032541 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10343 00:26:50.036106 [ 0.000000] psci: probing for conduit method from DT.
10344 00:26:50.042992 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10345 00:26:50.046173 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10346 00:26:50.053118 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10347 00:26:50.056107 [ 0.000000] psci: SMC Calling Convention v1.2
10348 00:26:50.062608 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10349 00:26:50.066116 [ 0.000000] Detected VIPT I-cache on CPU0
10350 00:26:50.072643 [ 0.000000] CPU features: detected: GIC system register CPU interface
10351 00:26:50.079874 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10352 00:26:50.086270 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10353 00:26:50.092781 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10354 00:26:50.099449 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10355 00:26:50.106030 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10356 00:26:50.113095 [ 0.000000] alternatives: applying boot alternatives
10357 00:26:50.115664 [ 0.000000] Fallback order for Node 0: 0
10358 00:26:50.122874 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10359 00:26:50.125716 [ 0.000000] Policy zone: Normal
10360 00:26:50.149194 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14479197/extract-nfsrootfs-dddnrq79,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10361 00:26:50.162714 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10362 00:26:50.172751 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10363 00:26:50.182694 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10364 00:26:50.189108 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10365 00:26:50.192498 <6>[ 0.000000] software IO TLB: area num 8.
10366 00:26:50.249531 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10367 00:26:50.399121 <6>[ 0.000000] Memory: 7945752K/8385536K available (18112K kernel code, 4120K rwdata, 22648K rodata, 8512K init, 616K bss, 407016K reserved, 32768K cma-reserved)
10368 00:26:50.405469 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10369 00:26:50.412305 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10370 00:26:50.415408 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10371 00:26:50.422413 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10372 00:26:50.428828 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10373 00:26:50.432422 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10374 00:26:50.443054 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10375 00:26:50.449197 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10376 00:26:50.452442 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10377 00:26:50.460319 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10378 00:26:50.463730 <6>[ 0.000000] GICv3: 608 SPIs implemented
10379 00:26:50.470159 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10380 00:26:50.473196 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10381 00:26:50.476709 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10382 00:26:50.486906 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10383 00:26:50.497039 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10384 00:26:50.509940 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10385 00:26:50.516901 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10386 00:26:50.525767 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10387 00:26:50.538884 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10388 00:26:50.545721 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10389 00:26:50.552171 <6>[ 0.009178] Console: colour dummy device 80x25
10390 00:26:50.562171 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10391 00:26:50.568858 <6>[ 0.024415] pid_max: default: 32768 minimum: 301
10392 00:26:50.572298 <6>[ 0.029317] LSM: Security Framework initializing
10393 00:26:50.578747 <6>[ 0.034285] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10394 00:26:50.588889 <6>[ 0.042100] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10395 00:26:50.595265 <6>[ 0.051557] cblist_init_generic: Setting adjustable number of callback queues.
10396 00:26:50.601961 <6>[ 0.059000] cblist_init_generic: Setting shift to 3 and lim to 1.
10397 00:26:50.611967 <6>[ 0.065377] cblist_init_generic: Setting adjustable number of callback queues.
10398 00:26:50.618256 <6>[ 0.072804] cblist_init_generic: Setting shift to 3 and lim to 1.
10399 00:26:50.621794 <6>[ 0.079205] rcu: Hierarchical SRCU implementation.
10400 00:26:50.628390 <6>[ 0.084221] rcu: Max phase no-delay instances is 1000.
10401 00:26:50.635499 <6>[ 0.091291] EFI services will not be available.
10402 00:26:50.638351 <6>[ 0.096245] smp: Bringing up secondary CPUs ...
10403 00:26:50.646770 <6>[ 0.101295] Detected VIPT I-cache on CPU1
10404 00:26:50.653631 <6>[ 0.101367] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10405 00:26:50.660058 <6>[ 0.101397] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10406 00:26:50.663664 <6>[ 0.101729] Detected VIPT I-cache on CPU2
10407 00:26:50.669872 <6>[ 0.101777] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10408 00:26:50.676560 <6>[ 0.101792] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10409 00:26:50.683430 <6>[ 0.102052] Detected VIPT I-cache on CPU3
10410 00:26:50.690470 <6>[ 0.102098] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10411 00:26:50.696846 <6>[ 0.102112] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10412 00:26:50.700392 <6>[ 0.102413] CPU features: detected: Spectre-v4
10413 00:26:50.707150 <6>[ 0.102419] CPU features: detected: Spectre-BHB
10414 00:26:50.710158 <6>[ 0.102424] Detected PIPT I-cache on CPU4
10415 00:26:50.716696 <6>[ 0.102482] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10416 00:26:50.723778 <6>[ 0.102503] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10417 00:26:50.726598 <6>[ 0.102795] Detected PIPT I-cache on CPU5
10418 00:26:50.736535 <6>[ 0.102857] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10419 00:26:50.743812 <6>[ 0.102874] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10420 00:26:50.746775 <6>[ 0.103156] Detected PIPT I-cache on CPU6
10421 00:26:50.753451 <6>[ 0.103220] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10422 00:26:50.759815 <6>[ 0.103236] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10423 00:26:50.763430 <6>[ 0.103532] Detected PIPT I-cache on CPU7
10424 00:26:50.770381 <6>[ 0.103597] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10425 00:26:50.780203 <6>[ 0.103613] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10426 00:26:50.783770 <6>[ 0.103661] smp: Brought up 1 node, 8 CPUs
10427 00:26:50.787080 <6>[ 0.244971] SMP: Total of 8 processors activated.
10428 00:26:50.793630 <6>[ 0.249893] CPU features: detected: 32-bit EL0 Support
10429 00:26:50.803629 <6>[ 0.255289] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10430 00:26:50.809880 <6>[ 0.264091] CPU features: detected: Common not Private translations
10431 00:26:50.813415 <6>[ 0.270567] CPU features: detected: CRC32 instructions
10432 00:26:50.820431 <6>[ 0.275951] CPU features: detected: RCpc load-acquire (LDAPR)
10433 00:26:50.826841 <6>[ 0.281949] CPU features: detected: LSE atomic instructions
10434 00:26:50.830387 <6>[ 0.287767] CPU features: detected: Privileged Access Never
10435 00:26:50.836586 <6>[ 0.293547] CPU features: detected: RAS Extension Support
10436 00:26:50.843117 <6>[ 0.299155] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10437 00:26:50.849841 <6>[ 0.306376] CPU: All CPU(s) started at EL2
10438 00:26:50.853552 <6>[ 0.310719] alternatives: applying system-wide alternatives
10439 00:26:50.864204 <6>[ 0.321578] devtmpfs: initialized
10440 00:26:50.877074 <6>[ 0.330567] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10441 00:26:50.886991 <6>[ 0.340530] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10442 00:26:50.893330 <6>[ 0.348762] pinctrl core: initialized pinctrl subsystem
10443 00:26:50.896716 <6>[ 0.355436] DMI not present or invalid.
10444 00:26:50.903552 <6>[ 0.359850] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10445 00:26:50.913106 <6>[ 0.366745] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10446 00:26:50.920188 <6>[ 0.374327] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10447 00:26:50.929813 <6>[ 0.382566] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10448 00:26:50.933275 <6>[ 0.390808] audit: initializing netlink subsys (disabled)
10449 00:26:50.943574 <5>[ 0.396501] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10450 00:26:50.949979 <6>[ 0.397208] thermal_sys: Registered thermal governor 'step_wise'
10451 00:26:50.956897 <6>[ 0.404469] thermal_sys: Registered thermal governor 'power_allocator'
10452 00:26:50.959718 <6>[ 0.410722] cpuidle: using governor menu
10453 00:26:50.966565 <6>[ 0.421680] NET: Registered PF_QIPCRTR protocol family
10454 00:26:50.972986 <6>[ 0.427167] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10455 00:26:50.976450 <6>[ 0.434271] ASID allocator initialised with 32768 entries
10456 00:26:50.984039 <6>[ 0.440847] Serial: AMBA PL011 UART driver
10457 00:26:50.992537 <4>[ 0.449673] Trying to register duplicate clock ID: 134
10458 00:26:51.051131 <6>[ 0.511239] KASLR enabled
10459 00:26:51.065358 <6>[ 0.519004] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10460 00:26:51.072017 <6>[ 0.526021] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10461 00:26:51.078770 <6>[ 0.532510] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10462 00:26:51.085108 <6>[ 0.539515] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10463 00:26:51.091360 <6>[ 0.546001] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10464 00:26:51.098524 <6>[ 0.553004] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10465 00:26:51.104863 <6>[ 0.559492] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10466 00:26:51.111744 <6>[ 0.566498] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10467 00:26:51.114742 <6>[ 0.574027] ACPI: Interpreter disabled.
10468 00:26:51.123487 <6>[ 0.580460] iommu: Default domain type: Translated
10469 00:26:51.130168 <6>[ 0.585572] iommu: DMA domain TLB invalidation policy: strict mode
10470 00:26:51.133656 <5>[ 0.592236] SCSI subsystem initialized
10471 00:26:51.139905 <6>[ 0.596400] usbcore: registered new interface driver usbfs
10472 00:26:51.146630 <6>[ 0.602132] usbcore: registered new interface driver hub
10473 00:26:51.149759 <6>[ 0.607684] usbcore: registered new device driver usb
10474 00:26:51.156623 <6>[ 0.613784] pps_core: LinuxPPS API ver. 1 registered
10475 00:26:51.167087 <6>[ 0.618980] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10476 00:26:51.170578 <6>[ 0.628328] PTP clock support registered
10477 00:26:51.173521 <6>[ 0.632572] EDAC MC: Ver: 3.0.0
10478 00:26:51.181039 <6>[ 0.637731] FPGA manager framework
10479 00:26:51.183914 <6>[ 0.641416] Advanced Linux Sound Architecture Driver Initialized.
10480 00:26:51.188049 <6>[ 0.648191] vgaarb: loaded
10481 00:26:51.194420 <6>[ 0.651357] clocksource: Switched to clocksource arch_sys_counter
10482 00:26:51.201193 <5>[ 0.657798] VFS: Disk quotas dquot_6.6.0
10483 00:26:51.207565 <6>[ 0.661982] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10484 00:26:51.211203 <6>[ 0.669172] pnp: PnP ACPI: disabled
10485 00:26:51.218736 <6>[ 0.675853] NET: Registered PF_INET protocol family
10486 00:26:51.228597 <6>[ 0.681446] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10487 00:26:51.240195 <6>[ 0.693775] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10488 00:26:51.249985 <6>[ 0.702591] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10489 00:26:51.256504 <6>[ 0.710565] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10490 00:26:51.263484 <6>[ 0.719266] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10491 00:26:51.275214 <6>[ 0.729026] TCP: Hash tables configured (established 65536 bind 65536)
10492 00:26:51.282412 <6>[ 0.735892] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10493 00:26:51.288592 <6>[ 0.743093] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10494 00:26:51.295633 <6>[ 0.750794] NET: Registered PF_UNIX/PF_LOCAL protocol family
10495 00:26:51.302114 <6>[ 0.756948] RPC: Registered named UNIX socket transport module.
10496 00:26:51.304986 <6>[ 0.763102] RPC: Registered udp transport module.
10497 00:26:51.311876 <6>[ 0.768035] RPC: Registered tcp transport module.
10498 00:26:51.318561 <6>[ 0.772966] RPC: Registered tcp NFSv4.1 backchannel transport module.
10499 00:26:51.321702 <6>[ 0.779634] PCI: CLS 0 bytes, default 64
10500 00:26:51.324654 <6>[ 0.783954] Unpacking initramfs...
10501 00:26:51.342586 <6>[ 0.795946] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10502 00:26:51.352160 <6>[ 0.804621] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10503 00:26:51.355605 <6>[ 0.813484] kvm [1]: IPA Size Limit: 40 bits
10504 00:26:51.362180 <6>[ 0.818011] kvm [1]: GICv3: no GICV resource entry
10505 00:26:51.365303 <6>[ 0.823033] kvm [1]: disabling GICv2 emulation
10506 00:26:51.372080 <6>[ 0.827721] kvm [1]: GIC system register CPU interface enabled
10507 00:26:51.378554 <6>[ 0.835424] kvm [1]: vgic interrupt IRQ18
10508 00:26:51.382145 <6>[ 0.839797] kvm [1]: VHE mode initialized successfully
10509 00:26:51.389019 <5>[ 0.846187] Initialise system trusted keyrings
10510 00:26:51.395976 <6>[ 0.850990] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10511 00:26:51.403747 <6>[ 0.860917] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10512 00:26:51.410713 <5>[ 0.867297] NFS: Registering the id_resolver key type
10513 00:26:51.414234 <5>[ 0.872597] Key type id_resolver registered
10514 00:26:51.420628 <5>[ 0.877010] Key type id_legacy registered
10515 00:26:51.427054 <6>[ 0.881289] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10516 00:26:51.433759 <6>[ 0.888214] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10517 00:26:51.440275 <6>[ 0.895923] 9p: Installing v9fs 9p2000 file system support
10518 00:26:51.476837 <5>[ 0.933659] Key type asymmetric registered
10519 00:26:51.479700 <5>[ 0.937990] Asymmetric key parser 'x509' registered
10520 00:26:51.489899 <6>[ 0.943129] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10521 00:26:51.493350 <6>[ 0.950742] io scheduler mq-deadline registered
10522 00:26:51.496692 <6>[ 0.955536] io scheduler kyber registered
10523 00:26:51.515638 <6>[ 0.972368] EINJ: ACPI disabled.
10524 00:26:51.548271 <4>[ 0.998453] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10525 00:26:51.558288 <4>[ 1.009089] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10526 00:26:51.573024 <6>[ 1.029956] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10527 00:26:51.580912 <6>[ 1.037971] printk: console [ttyS0] disabled
10528 00:26:51.608717 <6>[ 1.062605] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10529 00:26:51.615687 <6>[ 1.072078] printk: console [ttyS0] enabled
10530 00:26:51.618682 <6>[ 1.072078] printk: console [ttyS0] enabled
10531 00:26:51.625472 <6>[ 1.080978] printk: bootconsole [mtk8250] disabled
10532 00:26:51.628988 <6>[ 1.080978] printk: bootconsole [mtk8250] disabled
10533 00:26:51.635635 <6>[ 1.092038] SuperH (H)SCI(F) driver initialized
10534 00:26:51.638903 <6>[ 1.097334] msm_serial: driver initialized
10535 00:26:51.652635 <6>[ 1.106276] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10536 00:26:51.662658 <6>[ 1.114826] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10537 00:26:51.669107 <6>[ 1.123374] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10538 00:26:51.679197 <6>[ 1.132002] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10539 00:26:51.685588 <6>[ 1.140709] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10540 00:26:51.695543 <6>[ 1.149423] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10541 00:26:51.705331 <6>[ 1.157963] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10542 00:26:51.712258 <6>[ 1.166777] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10543 00:26:51.722088 <6>[ 1.175320] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10544 00:26:51.734117 <6>[ 1.190931] loop: module loaded
10545 00:26:51.740538 <6>[ 1.196664] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10546 00:26:51.762902 <4>[ 1.219979] mtk-pmic-keys: Failed to locate of_node [id: -1]
10547 00:26:51.769459 <6>[ 1.226767] megasas: 07.719.03.00-rc1
10548 00:26:51.779405 <6>[ 1.236314] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10549 00:26:51.789649 <6>[ 1.246755] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10550 00:26:51.806719 <6>[ 1.263512] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10551 00:26:51.862865 <6>[ 1.313751] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10552 00:26:52.115676 <6>[ 1.572684] Freeing initrd memory: 18304K
10553 00:26:52.127189 <6>[ 1.584189] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10554 00:26:52.138084 <6>[ 1.594953] tun: Universal TUN/TAP device driver, 1.6
10555 00:26:52.141464 <6>[ 1.601000] thunder_xcv, ver 1.0
10556 00:26:52.144781 <6>[ 1.604506] thunder_bgx, ver 1.0
10557 00:26:52.147530 <6>[ 1.607999] nicpf, ver 1.0
10558 00:26:52.158202 <6>[ 1.612000] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10559 00:26:52.161585 <6>[ 1.619477] hns3: Copyright (c) 2017 Huawei Corporation.
10560 00:26:52.165243 <6>[ 1.625083] hclge is initializing
10561 00:26:52.171527 <6>[ 1.628657] e1000: Intel(R) PRO/1000 Network Driver
10562 00:26:52.178556 <6>[ 1.633787] e1000: Copyright (c) 1999-2006 Intel Corporation.
10563 00:26:52.181659 <6>[ 1.639801] e1000e: Intel(R) PRO/1000 Network Driver
10564 00:26:52.187983 <6>[ 1.645016] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10565 00:26:52.195030 <6>[ 1.651202] igb: Intel(R) Gigabit Ethernet Network Driver
10566 00:26:52.201978 <6>[ 1.656852] igb: Copyright (c) 2007-2014 Intel Corporation.
10567 00:26:52.208436 <6>[ 1.662691] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10568 00:26:52.211480 <6>[ 1.669208] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10569 00:26:52.218470 <6>[ 1.675669] sky2: driver version 1.30
10570 00:26:52.225053 <6>[ 1.680590] usbcore: registered new device driver r8152-cfgselector
10571 00:26:52.232219 <6>[ 1.687125] usbcore: registered new interface driver r8152
10572 00:26:52.235313 <6>[ 1.692933] VFIO - User Level meta-driver version: 0.3
10573 00:26:52.243964 <6>[ 1.701154] usbcore: registered new interface driver usb-storage
10574 00:26:52.250678 <6>[ 1.707596] usbcore: registered new device driver onboard-usb-hub
10575 00:26:52.259748 <6>[ 1.716752] mt6397-rtc mt6359-rtc: registered as rtc0
10576 00:26:52.269707 <6>[ 1.722219] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-21T00:26:52 UTC (1718929612)
10577 00:26:52.273292 <6>[ 1.731786] i2c_dev: i2c /dev entries driver
10578 00:26:52.286768 <4>[ 1.743819] cpu cpu0: supply cpu not found, using dummy regulator
10579 00:26:52.293204 <4>[ 1.750247] cpu cpu1: supply cpu not found, using dummy regulator
10580 00:26:52.299950 <4>[ 1.756654] cpu cpu2: supply cpu not found, using dummy regulator
10581 00:26:52.306715 <4>[ 1.763053] cpu cpu3: supply cpu not found, using dummy regulator
10582 00:26:52.313711 <4>[ 1.769468] cpu cpu4: supply cpu not found, using dummy regulator
10583 00:26:52.320320 <4>[ 1.775870] cpu cpu5: supply cpu not found, using dummy regulator
10584 00:26:52.327024 <4>[ 1.782265] cpu cpu6: supply cpu not found, using dummy regulator
10585 00:26:52.333107 <4>[ 1.788662] cpu cpu7: supply cpu not found, using dummy regulator
10586 00:26:52.352081 <6>[ 1.809318] cpu cpu0: EM: created perf domain
10587 00:26:52.355421 <6>[ 1.814250] cpu cpu4: EM: created perf domain
10588 00:26:52.362824 <6>[ 1.819825] sdhci: Secure Digital Host Controller Interface driver
10589 00:26:52.369183 <6>[ 1.826255] sdhci: Copyright(c) Pierre Ossman
10590 00:26:52.376442 <6>[ 1.831213] Synopsys Designware Multimedia Card Interface Driver
10591 00:26:52.382620 <6>[ 1.837849] sdhci-pltfm: SDHCI platform and OF driver helper
10592 00:26:52.385957 <6>[ 1.837992] mmc0: CQHCI version 5.10
10593 00:26:52.392851 <6>[ 1.847862] ledtrig-cpu: registered to indicate activity on CPUs
10594 00:26:52.399451 <6>[ 1.854801] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10595 00:26:52.406185 <6>[ 1.861848] usbcore: registered new interface driver usbhid
10596 00:26:52.409390 <6>[ 1.867669] usbhid: USB HID core driver
10597 00:26:52.416354 <6>[ 1.871875] spi_master spi0: will run message pump with realtime priority
10598 00:26:52.460382 <6>[ 1.910750] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10599 00:26:52.478673 <6>[ 1.925841] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10600 00:26:52.482145 <6>[ 1.932359] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10601 00:26:52.489401 <6>[ 1.946670] cros-ec-spi spi0.0: Chrome EC device registered
10602 00:26:52.496426 <6>[ 1.952662] mmc0: Command Queue Engine enabled
10603 00:26:52.502789 <6>[ 1.957398] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10604 00:26:52.506306 <6>[ 1.964928] mmcblk0: mmc0:0001 DA4128 116 GiB
10605 00:26:52.516436 <6>[ 1.973771] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10606 00:26:52.524214 <6>[ 1.981224] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10607 00:26:52.533934 <6>[ 1.985187] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10608 00:26:52.537182 <6>[ 1.987202] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10609 00:26:52.544170 <6>[ 1.996971] NET: Registered PF_PACKET protocol family
10610 00:26:52.550503 <6>[ 2.001665] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10611 00:26:52.554533 <6>[ 2.006358] 9pnet: Installing 9P2000 support
10612 00:26:52.560996 <5>[ 2.017374] Key type dns_resolver registered
10613 00:26:52.564696 <6>[ 2.022346] registered taskstats version 1
10614 00:26:52.570685 <5>[ 2.026730] Loading compiled-in X.509 certificates
10615 00:26:52.598233 <4>[ 2.048497] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10616 00:26:52.608172 <4>[ 2.059236] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10617 00:26:52.622801 <6>[ 2.079752] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10618 00:26:52.629701 <6>[ 2.086680] xhci-mtk 11200000.usb: xHCI Host Controller
10619 00:26:52.636225 <6>[ 2.092224] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10620 00:26:52.646177 <6>[ 2.100073] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10621 00:26:52.652797 <6>[ 2.109526] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10622 00:26:52.659499 <6>[ 2.115733] xhci-mtk 11200000.usb: xHCI Host Controller
10623 00:26:52.666119 <6>[ 2.121237] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10624 00:26:52.672792 <6>[ 2.128897] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10625 00:26:52.679348 <6>[ 2.136699] hub 1-0:1.0: USB hub found
10626 00:26:52.683054 <6>[ 2.140726] hub 1-0:1.0: 1 port detected
10627 00:26:52.692491 <6>[ 2.145022] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10628 00:26:52.695961 <6>[ 2.153735] hub 2-0:1.0: USB hub found
10629 00:26:52.699292 <6>[ 2.157756] hub 2-0:1.0: 1 port detected
10630 00:26:52.707529 <6>[ 2.164531] mtk-msdc 11f70000.mmc: Got CD GPIO
10631 00:26:52.719774 <6>[ 2.173545] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10632 00:26:52.726153 <6>[ 2.181924] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10633 00:26:52.736305 <6>[ 2.190264] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10634 00:26:52.743211 <6>[ 2.198606] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10635 00:26:52.753060 <6>[ 2.206944] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10636 00:26:52.759969 <6>[ 2.215282] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10637 00:26:52.769609 <6>[ 2.223620] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10638 00:26:52.776596 <6>[ 2.231958] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10639 00:26:52.786474 <6>[ 2.240300] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10640 00:26:52.793099 <6>[ 2.248638] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10641 00:26:52.803371 <6>[ 2.256975] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10642 00:26:52.813248 <6>[ 2.265327] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10643 00:26:52.819836 <6>[ 2.273665] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10644 00:26:52.829678 <6>[ 2.282003] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10645 00:26:52.836756 <6>[ 2.290340] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10646 00:26:52.843206 <6>[ 2.299046] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10647 00:26:52.849881 <6>[ 2.306225] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10648 00:26:52.856456 <6>[ 2.312995] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10649 00:26:52.862889 <6>[ 2.319802] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10650 00:26:52.869976 <6>[ 2.326726] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10651 00:26:52.879795 <6>[ 2.333607] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10652 00:26:52.889670 <6>[ 2.342746] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10653 00:26:52.899997 <6>[ 2.351864] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10654 00:26:52.909870 <6>[ 2.361158] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10655 00:26:52.916354 <6>[ 2.370628] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10656 00:26:52.925940 <6>[ 2.380095] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10657 00:26:52.936067 <6>[ 2.389215] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10658 00:26:52.946134 <6>[ 2.398681] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10659 00:26:52.956040 <6>[ 2.407803] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10660 00:26:52.965528 <6>[ 2.417097] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10661 00:26:52.975826 <6>[ 2.427257] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10662 00:26:52.985427 <6>[ 2.438833] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10663 00:26:52.992519 <6>[ 2.449975] Trying to probe devices needed for running init ...
10664 00:26:53.003324 <3>[ 2.457232] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10665 00:26:53.113437 <6>[ 2.567639] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10666 00:26:53.268368 <6>[ 2.725764] hub 1-1:1.0: USB hub found
10667 00:26:53.271902 <6>[ 2.730313] hub 1-1:1.0: 4 ports detected
10668 00:26:53.283191 <6>[ 2.740398] hub 1-1:1.0: USB hub found
10669 00:26:53.286318 <6>[ 2.744715] hub 1-1:1.0: 4 ports detected
10670 00:26:53.394218 <6>[ 2.848003] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10671 00:26:53.420681 <6>[ 2.877751] hub 2-1:1.0: USB hub found
10672 00:26:53.424346 <6>[ 2.882276] hub 2-1:1.0: 3 ports detected
10673 00:26:53.435047 <6>[ 2.892483] hub 2-1:1.0: USB hub found
10674 00:26:53.438953 <6>[ 2.896935] hub 2-1:1.0: 3 ports detected
10675 00:26:53.605749 <6>[ 3.059675] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10676 00:26:53.737950 <6>[ 3.195415] hub 1-1.4:1.0: USB hub found
10677 00:26:53.741377 <6>[ 3.200074] hub 1-1.4:1.0: 2 ports detected
10678 00:26:53.755679 <6>[ 3.213075] hub 1-1.4:1.0: USB hub found
10679 00:26:53.759249 <6>[ 3.217655] hub 1-1.4:1.0: 2 ports detected
10680 00:26:53.817703 <6>[ 3.271887] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10681 00:26:53.925944 <6>[ 3.380307] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10682 00:26:53.963134 <4>[ 3.417155] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10683 00:26:53.973086 <4>[ 3.426287] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10684 00:26:54.007707 <6>[ 3.465206] r8152 2-1.3:1.0 eth0: v1.12.13
10685 00:26:54.061671 <6>[ 3.515641] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10686 00:26:54.257340 <6>[ 3.711671] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10687 00:26:55.737516 <6>[ 5.194835] r8152 2-1.3:1.0 eth0: carrier on
10688 00:26:58.049700 <5>[ 5.219457] Sending DHCP requests .., OK
10689 00:26:58.056221 <6>[ 7.511820] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10690 00:26:58.059869 <6>[ 7.520115] IP-Config: Complete:
10691 00:26:58.072864 <6>[ 7.523615] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10692 00:26:58.079777 <6>[ 7.534336] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10693 00:26:58.086578 <6>[ 7.542955] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10694 00:26:58.093135 <6>[ 7.542965] nameserver0=192.168.201.1
10695 00:26:58.096507 <6>[ 7.555128] clk: Disabling unused clocks
10696 00:26:58.099987 <6>[ 7.560640] ALSA device list:
10697 00:26:58.103308 <6>[ 7.563896] No soundcards found.
10698 00:26:58.113719 <6>[ 7.571491] Freeing unused kernel memory: 8512K
10699 00:26:58.117142 <6>[ 7.576495] Run /init as init process
10700 00:26:58.127542 Loading, please wait...
10701 00:26:58.162530 Starting systemd-udevd version 252.22-1~deb12u1
10702 00:26:58.400696 <6>[ 7.854990] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10703 00:26:58.413484 <6>[ 7.867825] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10704 00:26:58.419763 <6>[ 7.868062] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10705 00:26:58.430504 <6>[ 7.875672] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10706 00:26:58.436757 <6>[ 7.876002] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10707 00:26:58.443489 <6>[ 7.876011] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10708 00:26:58.453394 <4>[ 7.876279] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10709 00:26:58.459789 <6>[ 7.877039] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10710 00:26:58.469852 <6>[ 7.877045] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10711 00:26:58.476555 <6>[ 7.877586] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10712 00:26:58.486560 <6>[ 7.877615] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10713 00:26:58.493573 <6>[ 7.877629] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10714 00:26:58.503653 <6>[ 7.877650] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10715 00:26:58.510128 <3>[ 7.907488] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 00:26:58.519868 <6>[ 7.916377] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10717 00:26:58.522915 <6>[ 7.927852] remoteproc remoteproc0: scp is available
10718 00:26:58.533225 <3>[ 7.932672] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 00:26:58.536023 <6>[ 7.940601] remoteproc remoteproc0: powering up scp
10720 00:26:58.546411 <4>[ 7.941628] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10721 00:26:58.552745 <4>[ 7.942165] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10722 00:26:58.559610 <3>[ 7.948245] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 00:26:58.569542 <6>[ 7.956062] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10724 00:26:58.573349 <6>[ 7.959162] mc: Linux media interface: v0.10
10725 00:26:58.580222 <3>[ 7.985471] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 00:26:58.587060 <6>[ 7.987282] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10727 00:26:58.593566 <6>[ 7.992015] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10728 00:26:58.600628 <6>[ 7.993190] videodev: Linux video capture interface: v2.00
10729 00:26:58.610095 <3>[ 7.995321] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10730 00:26:58.616941 <4>[ 8.013017] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10731 00:26:58.624670 <4>[ 8.013017] Fallback method does not support PEC.
10732 00:26:58.630621 <3>[ 8.015202] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10733 00:26:58.641023 <3>[ 8.040326] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10734 00:26:58.647286 <3>[ 8.044308] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10735 00:26:58.657190 <3>[ 8.044313] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10736 00:26:58.664199 <3>[ 8.044376] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10737 00:26:58.670662 <3>[ 8.044490] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 00:26:58.680540 <3>[ 8.044499] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 00:26:58.686899 <3>[ 8.044509] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 00:26:58.696974 <3>[ 8.044742] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 00:26:58.704051 <3>[ 8.044762] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10742 00:26:58.714190 <3>[ 8.044767] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 00:26:58.720667 <3>[ 8.044778] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 00:26:58.726993 <3>[ 8.044789] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 00:26:58.737010 <3>[ 8.044845] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10746 00:26:58.743542 <6>[ 8.048618] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10747 00:26:58.753541 <6>[ 8.055993] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10748 00:26:58.757021 <6>[ 8.058224] pci_bus 0000:00: root bus resource [bus 00-ff]
10749 00:26:58.767039 <6>[ 8.080070] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10750 00:26:58.776903 <6>[ 8.085631] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10751 00:26:58.787243 <6>[ 8.085633] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10752 00:26:58.790230 <6>[ 8.085663] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10753 00:26:58.800533 <3>[ 8.087106] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10754 00:26:58.810558 <6>[ 8.094244] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10755 00:26:58.816966 <6>[ 8.102501] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10756 00:26:58.823936 <6>[ 8.121867] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10757 00:26:58.833895 <6>[ 8.126749] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10758 00:26:58.836571 <6>[ 8.127433] pci 0000:00:00.0: supports D1 D2
10759 00:26:58.843090 <6>[ 8.127438] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10760 00:26:58.853631 <6>[ 8.128776] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10761 00:26:58.859808 <6>[ 8.128853] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10762 00:26:58.866824 <6>[ 8.128877] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10763 00:26:58.873139 <6>[ 8.128893] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10764 00:26:58.879698 <6>[ 8.128908] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10765 00:26:58.886689 <6>[ 8.129013] pci 0000:01:00.0: supports D1 D2
10766 00:26:58.892982 <6>[ 8.129014] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10767 00:26:58.899632 <6>[ 8.143539] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10768 00:26:58.906635 <6>[ 8.145900] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10769 00:26:58.916235 <6>[ 8.147638] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10770 00:26:58.922860 <6>[ 8.151099] remoteproc remoteproc0: remote processor scp is now up
10771 00:26:58.929906 <6>[ 8.159213] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10772 00:26:58.933190 <6>[ 8.159816] Bluetooth: Core ver 2.22
10773 00:26:58.939550 <6>[ 8.159901] NET: Registered PF_BLUETOOTH protocol family
10774 00:26:58.946188 <6>[ 8.159904] Bluetooth: HCI device and connection manager initialized
10775 00:26:58.953019 <6>[ 8.159932] Bluetooth: HCI socket layer initialized
10776 00:26:58.956159 <6>[ 8.159942] Bluetooth: L2CAP socket layer initialized
10777 00:26:58.962702 <6>[ 8.159955] Bluetooth: SCO socket layer initialized
10778 00:26:58.969648 <6>[ 8.177034] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10779 00:26:58.976409 <6>[ 8.183420] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10780 00:26:58.985793 <6>[ 8.183433] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10781 00:26:58.992833 <6>[ 8.183445] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10782 00:26:59.005915 <6>[ 8.193145] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10783 00:26:59.012395 <6>[ 8.199601] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10784 00:26:59.019390 <6>[ 8.206695] usbcore: registered new interface driver uvcvideo
10785 00:26:59.025812 <6>[ 8.215773] pci 0000:00:00.0: PCI bridge to [bus 01]
10786 00:26:59.032407 <6>[ 8.216765] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10787 00:26:59.035733 <6>[ 8.232042] usbcore: registered new interface driver btusb
10788 00:26:59.045685 <4>[ 8.232915] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10789 00:26:59.052552 <3>[ 8.232927] Bluetooth: hci0: Failed to load firmware file (-2)
10790 00:26:59.058890 <3>[ 8.232932] Bluetooth: hci0: Failed to set up firmware (-2)
10791 00:26:59.068855 <4>[ 8.232937] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10792 00:26:59.079307 <6>[ 8.238698] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10793 00:26:59.085214 <6>[ 8.540489] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10794 00:26:59.092386 <6>[ 8.547297] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10795 00:26:59.095187 <6>[ 8.553721] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10796 00:26:59.112028 <5>[ 8.566867] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10797 00:26:59.138141 <5>[ 8.592575] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10798 00:26:59.144649 <5>[ 8.600000] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10799 00:26:59.154569 <4>[ 8.608440] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10800 00:26:59.157794 <6>[ 8.617332] cfg80211: failed to load regulatory.db
10801 00:26:59.208665 <6>[ 8.663005] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10802 00:26:59.215045 <6>[ 8.670540] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10803 00:26:59.238973 <6>[ 8.697210] mt7921e 0000:01:00.0: ASIC revision: 79610010
10804 00:26:59.341337 <6>[ 8.795919] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10805 00:26:59.344698 <6>[ 8.795919]
10806 00:26:59.351755 Begin: Loading essential drivers ... done.
10807 00:26:59.355051 Begin: Running /scripts/init-premount ... done.
10808 00:26:59.361957 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10809 00:26:59.371591 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10810 00:26:59.375155 Device /sys/class/net/eth0 found
10811 00:26:59.375236 done.
10812 00:26:59.381799 Begin: Waiting up to 180 secs for any network device to become available ... done.
10813 00:26:59.429598 IP-Config: eth0 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10814 00:26:59.436323 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10815 00:26:59.443092 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10816 00:26:59.449643 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10817 00:26:59.456627 host : mt8192-asurada-spherion-r0-cbg-3
10818 00:26:59.463072 domain : lava-rack
10819 00:26:59.465893 rootserver: 192.168.201.1 rootpath:
10820 00:26:59.465969 filename :
10821 00:26:59.485136 done.
10822 00:26:59.493922 Begin: Running /scripts/nfs-bottom ... done.
10823 00:26:59.508737 Begin: Running /scripts/init-bottom ... done.
10824 00:26:59.609740 <6>[ 9.064574] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10825 00:27:00.873999 <6>[ 10.331945] NET: Registered PF_INET6 protocol family
10826 00:27:00.880747 <6>[ 10.338880] Segment Routing with IPv6
10827 00:27:00.883917 <6>[ 10.342853] In-situ OAM (IOAM) with IPv6
10828 00:27:01.059826 <30>[ 10.491069] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10829 00:27:01.066293 <30>[ 10.524231] systemd[1]: Detected architecture arm64.
10830 00:27:01.074327
10831 00:27:01.077633 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10832 00:27:01.077777
10833 00:27:01.103083 <30>[ 10.561407] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10834 00:27:02.290806 <30>[ 11.745397] systemd[1]: Queued start job for default target graphical.target.
10835 00:27:02.334430 <30>[ 11.788863] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10836 00:27:02.341299 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10837 00:27:02.362555 <30>[ 11.817485] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10838 00:27:02.372857 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10839 00:27:02.390926 <30>[ 11.845415] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10840 00:27:02.400935 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10841 00:27:02.419476 <30>[ 11.873890] systemd[1]: Created slice user.slice - User and Session Slice.
10842 00:27:02.425968 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10843 00:27:02.449173 <30>[ 11.900530] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10844 00:27:02.459021 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10845 00:27:02.476636 <30>[ 11.927898] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10846 00:27:02.483769 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10847 00:27:02.511607 <30>[ 11.956335] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10848 00:27:02.521944 <30>[ 11.976239] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10849 00:27:02.528047 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10850 00:27:02.545593 <30>[ 12.000067] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10851 00:27:02.552197 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10852 00:27:02.572592 <30>[ 12.027771] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10853 00:27:02.582370 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10854 00:27:02.597847 <30>[ 12.056186] systemd[1]: Reached target paths.target - Path Units.
10855 00:27:02.607800 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10856 00:27:02.625201 <30>[ 12.080122] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10857 00:27:02.631694 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10858 00:27:02.645417 <30>[ 12.103636] systemd[1]: Reached target slices.target - Slice Units.
10859 00:27:02.655630 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10860 00:27:02.670322 <30>[ 12.128000] systemd[1]: Reached target swap.target - Swaps.
10861 00:27:02.676707 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10862 00:27:02.697325 <30>[ 12.151736] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10863 00:27:02.707423 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10864 00:27:02.726308 <30>[ 12.180619] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10865 00:27:02.735592 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10866 00:27:02.757307 <30>[ 12.211960] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10867 00:27:02.767141 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10868 00:27:02.786601 <30>[ 12.241209] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10869 00:27:02.796623 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10870 00:27:02.814304 <30>[ 12.268275] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10871 00:27:02.820617 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10872 00:27:02.839094 <30>[ 12.293477] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10873 00:27:02.848960 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10874 00:27:02.870200 <30>[ 12.324387] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10875 00:27:02.879766 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10876 00:27:02.897748 <30>[ 12.352172] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10877 00:27:02.907295 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10878 00:27:02.957163 <30>[ 12.412139] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10879 00:27:02.963971 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10880 00:27:02.983287 <30>[ 12.438112] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10881 00:27:02.989865 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10882 00:27:03.012957 <30>[ 12.467824] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10883 00:27:03.019600 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10884 00:27:03.044062 <30>[ 12.492088] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10885 00:27:03.075447 <30>[ 12.514405] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10886 00:27:03.075856 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10887 00:27:03.094822 <30>[ 12.549611] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10888 00:27:03.104193 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10889 00:27:03.126338 <30>[ 12.581282] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10890 00:27:03.136444 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10891 00:27:03.158444 <30>[ 12.613303] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10892 00:27:03.164997 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10893 00:27:03.175110 <6>[ 12.629559] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10894 00:27:03.189167 <30>[ 12.643926] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10895 00:27:03.199181 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10896 00:27:03.222368 <30>[ 12.677442] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10897 00:27:03.229534 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10898 00:27:03.254740 <30>[ 12.709288] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10899 00:27:03.265083 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop..<6>[ 12.723265] fuse: init (API version 7.37)
10900 00:27:03.265483 .
10901 00:27:03.322203 <30>[ 12.776558] systemd[1]: Starting systemd-journald.service - Journal Service...
10902 00:27:03.328692 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10903 00:27:03.363477 <30>[ 12.818836] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10904 00:27:03.369966 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10905 00:27:03.397860 <30>[ 12.849683] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10906 00:27:03.404643 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10907 00:27:03.429263 <30>[ 12.884315] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10908 00:27:03.439433 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10909 00:27:03.461782 <30>[ 12.916863] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10910 00:27:03.468265 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10911 00:27:03.496039 <30>[ 12.949822] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10912 00:27:03.505399 [[0;32m OK [<3>[ 12.958257] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 00:27:03.512248 0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10914 00:27:03.530237 <30>[ 12.984422] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10915 00:27:03.540399 [[0;32m OK [<3>[ 12.992705] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 00:27:03.546831 0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10917 00:27:03.565534 <30>[ 13.019975] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10918 00:27:03.571879 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10919 00:27:03.584415 <3>[ 13.038653] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 00:27:03.594370 <30>[ 13.048271] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10921 00:27:03.600731 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10922 00:27:03.613965 <3>[ 13.068764] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 00:27:03.624288 <30>[ 13.078967] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10924 00:27:03.634134 <30>[ 13.087135] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10925 00:27:03.640953 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10926 00:27:03.655170 <30>[ 13.112330] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10927 00:27:03.665024 <3>[ 13.112780] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 00:27:03.686137 <30>[ 13.139843] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10929 00:27:03.697456 <3>[ 13.152324] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 00:27:03.710329 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10931 00:27:03.729522 <3>[ 13.183450] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 00:27:03.735980 <30>[ 13.184601] systemd[1]: modprobe@drm.service: Deactivated successfully.
10933 00:27:03.746762 <30>[ 13.199893] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10934 00:27:03.760376 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m -<3>[ 13.212728] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 00:27:03.760840 Load Kernel Module drm.
10936 00:27:03.779973 <30>[ 13.237167] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10937 00:27:03.790148 <3>[ 13.242736] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 00:27:03.800154 <30>[ 13.245365] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10939 00:27:03.806827 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10940 00:27:03.820667 <3>[ 13.275750] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 00:27:03.830804 <30>[ 13.285815] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10942 00:27:03.838137 <30>[ 13.293601] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10943 00:27:03.851908 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m <3>[ 13.306866] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 00:27:03.855274 - Load Kernel Module fuse.
10945 00:27:03.871208 <30>[ 13.328809] systemd[1]: modprobe@loop.service: Deactivated successfully.
10946 00:27:03.882014 <30>[ 13.336371] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10947 00:27:03.889029 <3>[ 13.340869] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 00:27:03.898824 <3>[ 13.341710] power_supply sbs-5-000b: driver failed to report `status' property: -6
10949 00:27:03.912359 <4>[ 13.341724] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10950 00:27:03.922080 <3>[ 13.341727] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10951 00:27:03.928678 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10952 00:27:03.950350 <30>[ 13.404639] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10953 00:27:03.959577 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10954 00:27:03.982272 <30>[ 13.433243] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10955 00:27:03.988809 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10956 00:27:04.006238 <30>[ 13.460169] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10957 00:27:04.015806 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10958 00:27:04.033595 <30>[ 13.488450] systemd[1]: Started systemd-journald.service - Journal Service.
10959 00:27:04.040254 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10960 00:27:04.061369 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10961 00:27:04.079637 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10962 00:27:04.133821 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10963 00:27:04.155739 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10964 00:27:04.178356 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10965 00:27:04.202794 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10966 00:27:04.231916 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10967 00:27:04.254086 <46>[ 13.708774] systemd-journald[308]: Received client request to flush runtime journal.
10968 00:27:04.260399 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10969 00:27:04.300750 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10970 00:27:04.318054 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10971 00:27:04.342666 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10972 00:27:04.366552 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10973 00:27:05.362202 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10974 00:27:05.409783 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10975 00:27:05.668195 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10976 00:27:05.783351 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10977 00:27:05.801081 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10978 00:27:05.816809 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10979 00:27:05.880954 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10980 00:27:05.903920 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10981 00:27:06.166017 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10982 00:27:06.238565 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10983 00:27:06.305098 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10984 00:27:06.552579 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10985 00:27:06.621636 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10986 00:27:06.643434 [[0;32m OK [0m] Finished [0<6>[ 16.100452] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10987 00:27:06.649895 ;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10988 00:27:06.701908 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10989 00:27:06.821027 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10990 00:27:06.848569 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10991 00:27:06.868541 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10992 00:27:06.903660 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10993 00:27:06.940887 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10994 00:27:06.967178 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10995 00:27:06.988461 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10996 00:27:07.042988 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10997 00:27:07.089769 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10998 00:27:07.110243 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10999 00:27:07.129204 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11000 00:27:07.153093 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11001 00:27:07.173377 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11002 00:27:07.201894 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11003 00:27:07.241105 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11004 00:27:07.257261 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11005 00:27:07.281400 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11006 00:27:07.305130 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11007 00:27:07.325149 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11008 00:27:07.344404 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11009 00:27:07.361225 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11010 00:27:07.377885 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11011 00:27:07.435323 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11012 00:27:07.470047 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11013 00:27:07.558604 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11014 00:27:07.584079 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11015 00:27:07.650150 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11016 00:27:07.713531 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11017 00:27:07.739565 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11018 00:27:07.757143 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11019 00:27:07.819144 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11020 00:27:07.860720 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11021 00:27:07.952578 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11022 00:27:07.972475 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11023 00:27:07.990555 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11024 00:27:08.051978 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11025 00:27:08.103262 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11026 00:27:08.210886
11027 00:27:08.214712 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11028 00:27:08.215116
11029 00:27:08.217619 debian-bookworm-arm64 login: root (automatic login)
11030 00:27:08.218050
11031 00:27:08.505602 Linux debian-bookworm-arm64 6.1.94-cip23 #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024 aarch64
11032 00:27:08.506246
11033 00:27:08.512026 The programs included with the Debian GNU/Linux system are free software;
11034 00:27:08.518502 the exact distribution terms for each program are described in the
11035 00:27:08.522190 individual files in /usr/share/doc/*/copyright.
11036 00:27:08.522269
11037 00:27:08.528605 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11038 00:27:08.532127 permitted by applicable law.
11039 00:27:08.645702 Matched prompt #10: / #
11041 00:27:08.646787 Setting prompt string to ['/ #']
11042 00:27:08.647193 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11044 00:27:08.648084 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11045 00:27:08.648487 start: 2.2.6 expect-shell-connection (timeout 00:03:14) [common]
11046 00:27:08.648808 Setting prompt string to ['/ #']
11047 00:27:08.649086 Forcing a shell prompt, looking for ['/ #']
11049 00:27:08.699938 / #
11050 00:27:08.700602 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11051 00:27:08.701014 Waiting using forced prompt support (timeout 00:02:30)
11052 00:27:08.706567
11053 00:27:08.707461 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11054 00:27:08.708028 start: 2.2.7 export-device-env (timeout 00:03:14) [common]
11056 00:27:08.809208 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14479197/extract-nfsrootfs-dddnrq79'
11057 00:27:08.815201 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14479197/extract-nfsrootfs-dddnrq79'
11059 00:27:08.916742 / # export NFS_SERVER_IP='192.168.201.1'
11060 00:27:08.923505 export NFS_SERVER_IP='192.168.201.1'
11061 00:27:08.924440 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11062 00:27:08.924955 end: 2.2 depthcharge-retry (duration 00:01:46) [common]
11063 00:27:08.925448 end: 2 depthcharge-action (duration 00:01:46) [common]
11064 00:27:08.926031 start: 3 lava-test-retry (timeout 00:30:00) [common]
11065 00:27:08.926645 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11066 00:27:08.927043 Using namespace: common
11068 00:27:09.028153 / # #
11069 00:27:09.028802 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11070 00:27:09.034015 #
11071 00:27:09.034285 Using /lava-14479197
11073 00:27:09.134704 / # export SHELL=/bin/sh
11074 00:27:09.140225 export SHELL=/bin/sh
11076 00:27:09.241103 / # . /lava-14479197/environment
11077 00:27:09.247429 . /lava-14479197/environment
11079 00:27:09.355702 / # /lava-14479197/bin/lava-test-runner /lava-14479197/0
11080 00:27:09.356384 Test shell timeout: 10s (minimum of the action and connection timeout)
11081 00:27:09.362550 /lava-14479197/bin/lava-test-runner /lava-14479197/0
11082 00:27:09.663498 + export TESTRUN_ID=0_lc-compliance
11083 00:27:09.670135 + cd /lava-14479197/0/tests/0_lc-compliance
11084 00:27:09.670552 + cat uuid
11085 00:27:09.682953 + UUID=14479197_1.6.2.3.1
11086 00:27:09.683345 + set +x
11087 00:27:09.689867 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 14479197_1.6.2.3.1>
11088 00:27:09.690571 Received signal: <STARTRUN> 0_lc-compliance 14479197_1.6.2.3.1
11089 00:27:09.690918 Starting test lava.0_lc-compliance (14479197_1.6.2.3.1)
11090 00:27:09.691291 Skipping test definition patterns.
11091 00:27:09.692787 + /usr/bin/lc-compliance-parser.sh
11092 00:27:11.367938 [0:00:20.704351769] [411] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-01935edb
11093 00:27:11.370696 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11094 00:27:11.390339 [0:00:20.727490308] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11095 00:27:11.452331 [0:00:20.789460846] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11096 00:27:11.471081 [==========] Running 120 tests from 1 test suite.
11097 00:27:11.505790 [0:00:20.842684539] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11098 00:27:11.559606 [0:00:20.896690539] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11099 00:27:11.570027 [----------] Global test environment set-up.
11100 00:27:11.670056 [----------] 120 tests from CaptureTests/SingleStream
11101 00:27:11.760867 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11102 00:27:11.838139 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11103 00:27:11.838979 Received signal: <TESTSET> START CaptureTests/SingleStream
11104 00:27:11.839493 Starting test_set CaptureTests/SingleStream
11105 00:27:11.840909 Camera needs 4 requests, can't test only 1
11106 00:27:11.925781 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11107 00:27:11.987158 [0:00:21.324510769] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11108 00:27:12.020423
11109 00:27:12.123536 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (63 ms)
11110 00:27:12.239738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11111 00:27:12.240168 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11113 00:27:12.258912 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11114 00:27:12.326564 Camera needs 4 requests, can't test only 2
11115 00:27:12.438454 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11116 00:27:12.530043
11117 00:27:12.640810 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (53 ms)
11118 00:27:12.681384 [0:00:22.018596462] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11119 00:27:12.764723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11120 00:27:12.765388 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11122 00:27:12.785327 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11123 00:27:12.852305 Camera needs 4 requests, can't test only 3
11124 00:27:12.953910 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11125 00:27:13.048260
11126 00:27:13.153808 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (53 ms)
11127 00:27:13.273237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11128 00:27:13.273919 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11130 00:27:13.294716 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11131 00:27:13.363339 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (426 ms)
11132 00:27:13.486904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11133 00:27:13.487579 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11135 00:27:13.509202 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11136 00:27:13.579450 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (693 ms)
11137 00:27:13.695287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11138 00:27:13.695956 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11140 00:27:13.716273 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11141 00:27:13.927229 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1255 ms)
11142 00:27:13.937117 [0:00:23.274235539] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11143 00:27:14.052709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11144 00:27:14.053389 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11146 00:27:14.074115 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11147 00:27:15.744079 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1816 ms)
11148 00:27:15.753684 [0:00:25.091270462] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11149 00:27:15.860111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11150 00:27:15.860779 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11152 00:27:15.878320 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11153 00:27:18.472360 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (2728 ms)
11154 00:27:18.482170 [0:00:27.819806924] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11155 00:27:18.600968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11156 00:27:18.601664 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11158 00:27:18.623419 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11159 00:27:22.670026 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (4198 ms)
11160 00:27:22.680289 [0:00:32.018013309] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11161 00:27:22.802256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11162 00:27:22.802936 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11164 00:27:22.823461 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11165 00:27:28.503318 <6>[ 37.967614] vpu: disabling
11166 00:27:28.506375 <6>[ 37.970714] vproc2: disabling
11167 00:27:28.509728 <6>[ 37.974037] vproc1: disabling
11168 00:27:28.512669 <6>[ 37.977347] vaud18: disabling
11169 00:27:28.519129 <6>[ 37.980856] vsram_others: disabling
11170 00:27:28.522727 <6>[ 37.984823] va09: disabling
11171 00:27:28.525768 <6>[ 37.987988] vsram_md: disabling
11172 00:27:28.529220 <6>[ 37.991553] Vgpu: disabling
11173 00:27:29.246673 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (6577 ms)
11174 00:27:29.256557 [0:00:38.596074617] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11175 00:27:29.314041 [0:00:38.653823232] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11176 00:27:29.351741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11177 00:27:29.351997 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11179 00:27:29.367680 [0:00:38.707218386] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11180 00:27:29.371200 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11181 00:27:29.419214 [0:00:38.758852924] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11182 00:27:29.422894 Camera needs 4 requests, can't test only 1
11183 00:27:29.510124 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11184 00:27:29.593251
11185 00:27:29.679075 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (58 ms)
11186 00:27:29.772800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11187 00:27:29.773078 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11189 00:27:29.788995 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11190 00:27:29.845528 Camera needs 4 requests, can't test only 2
11191 00:27:29.924851 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11192 00:27:30.003174
11193 00:27:30.089502 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (54 ms)
11194 00:27:30.111571 [0:00:39.451035386] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11195 00:27:30.190101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11196 00:27:30.190371 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11198 00:27:30.206249 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11199 00:27:30.260617 Camera needs 4 requests, can't test only 3
11200 00:27:30.344874 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11201 00:27:30.423825
11202 00:27:30.507908 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (51 ms)
11203 00:27:30.611272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11204 00:27:30.611585 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11206 00:27:30.627747 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11207 00:27:30.683712 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (691 ms)
11208 00:27:30.779668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11209 00:27:30.779933 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11211 00:27:30.798475 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11212 00:27:31.008706 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (905 ms)
11213 00:27:31.021722 [0:00:40.358206155] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11214 00:27:31.113156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11215 00:27:31.113488 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11217 00:27:31.131904 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11218 00:27:32.266074 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1257 ms)
11219 00:27:32.279508 [0:00:41.615775540] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11220 00:27:32.369179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11221 00:27:32.369490 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11223 00:27:32.387148 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11224 00:27:34.084855 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1818 ms)
11225 00:27:34.098671 [0:00:43.434975232] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11226 00:27:34.209788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11227 00:27:34.210565 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11229 00:27:34.230965 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11230 00:27:36.813901 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (2729 ms)
11231 00:27:36.827119 [0:00:46.162864309] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11232 00:27:36.928492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11233 00:27:36.929163 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11235 00:27:36.949660 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11236 00:27:41.010076 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (4196 ms)
11237 00:27:41.022957 [0:00:50.359351310] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11238 00:27:41.145759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11239 00:27:41.146502 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11241 00:27:41.166920 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11242 00:27:47.586097 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (6576 ms)
11243 00:27:47.599243 [0:00:56.936283156] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11244 00:27:47.650718 [0:00:56.991430848] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11245 00:27:47.706036 [0:00:57.047552310] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11246 00:27:47.713096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11247 00:27:47.713750 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11249 00:27:47.732129 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11250 00:27:47.762698 [0:00:57.103589233] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11251 00:27:47.801412 Camera needs 4 requests, can't test only 1
11252 00:27:47.895437 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11253 00:27:47.986579
11254 00:27:48.083601 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (55 ms)
11255 00:27:48.195034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11256 00:27:48.195715 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11258 00:27:48.211161 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11259 00:27:48.267311 Camera needs 4 requests, can't test only 2
11260 00:27:48.359508 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11261 00:27:48.457369 [0:00:57.798348233] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11262 00:27:48.457811
11263 00:27:48.553490 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (55 ms)
11264 00:27:48.674324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11265 00:27:48.675007 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11267 00:27:48.694980 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11268 00:27:48.762663 Camera needs 4 requests, can't test only 3
11269 00:27:48.857172 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11270 00:27:48.950010
11271 00:27:49.051012 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (56 ms)
11272 00:27:49.167593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11273 00:27:49.168322 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11275 00:27:49.187435 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11276 00:27:49.254695 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (694 ms)
11277 00:27:49.364032 [0:00:58.705393310] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11278 00:27:49.371823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11279 00:27:49.372463 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11281 00:27:49.394097 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11282 00:27:49.459196 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (907 ms)
11283 00:27:49.570770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11284 00:27:49.571470 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11286 00:27:49.590478 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11287 00:27:50.610847 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1255 ms)
11288 00:27:50.623912 [0:00:59.961040079] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11289 00:27:50.728585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11290 00:27:50.729265 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11292 00:27:50.746590 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11293 00:27:52.426541 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1815 ms)
11294 00:27:52.439588 [0:01:01.776933695] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11295 00:27:52.555983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11296 00:27:52.556680 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11298 00:27:52.577813 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11299 00:27:55.154784 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (2728 ms)
11300 00:27:55.167778 [0:01:04.505718003] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11301 00:27:55.281927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11302 00:27:55.282751 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11304 00:27:55.303913 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11305 00:27:59.350630 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (4196 ms)
11306 00:27:59.363397 [0:01:08.702284311] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11307 00:27:59.449390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11308 00:27:59.449740 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11310 00:27:59.468267 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11311 00:28:05.926247 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (6576 ms)
11312 00:28:05.939847 [0:01:15.279124157] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11313 00:28:05.991133 [0:01:15.334650773] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11314 00:28:06.030322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11315 00:28:06.030609 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11317 00:28:06.045990 [0:01:15.389929003] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11318 00:28:06.049251 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11319 00:28:06.100069 [0:01:15.444146003] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11320 00:28:06.103602 Camera needs 4 requests, can't test only 1
11321 00:28:06.180784 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11322 00:28:06.258565
11323 00:28:06.342375 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (55 ms)
11324 00:28:06.439138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11325 00:28:06.439439 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11327 00:28:06.457428 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11328 00:28:06.514330 Camera needs 4 requests, can't test only 2
11329 00:28:06.589351 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11330 00:28:06.673343
11331 00:28:06.757458 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (55 ms)
11332 00:28:06.794977 [0:01:16.138666465] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11333 00:28:06.854675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11334 00:28:06.854976 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11336 00:28:06.871899 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11337 00:28:06.927068 Camera needs 4 requests, can't test only 3
11338 00:28:07.010652 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11339 00:28:07.093154
11340 00:28:07.181522 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (55 ms)
11341 00:28:07.287204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11342 00:28:07.287491 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11344 00:28:07.304157 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11345 00:28:07.357407 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (694 ms)
11346 00:28:07.457544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11347 00:28:07.457830 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11349 00:28:07.474198 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11350 00:28:07.693194 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (906 ms)
11351 00:28:07.706412 [0:01:17.046137080] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11352 00:28:07.796896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11353 00:28:07.797191 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11355 00:28:07.813506 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11356 00:28:08.950699 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1257 ms)
11357 00:28:08.963965 [0:01:18.303779542] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11358 00:28:09.051690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11359 00:28:09.051986 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11361 00:28:09.068469 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11362 00:28:10.768261 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (1817 ms)
11363 00:28:10.781655 [0:01:20.121806619] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11364 00:28:10.873651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11365 00:28:10.873961 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11367 00:28:10.891645 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11368 00:28:13.496218 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (2728 ms)
11369 00:28:13.509513 [0:01:22.849876850] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11370 00:28:13.595242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11371 00:28:13.595522 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11373 00:28:13.611857 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11374 00:28:17.691656 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (4196 ms)
11375 00:28:17.704934 [0:01:27.045846389] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11376 00:28:17.786983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11377 00:28:17.787268 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11379 00:28:17.804267 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11380 00:28:24.267267 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (6576 ms)
11381 00:28:24.280766 [0:01:33.622420774] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11382 00:28:24.333567 [0:01:33.679335774] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11383 00:28:24.374241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11384 00:28:24.374526 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11386 00:28:24.389736 [0:01:33.735383774] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11387 00:28:24.392786 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11388 00:28:24.443981 [0:01:33.790213389] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11389 00:28:24.447413 Camera needs 4 requests, can't test only 1
11390 00:28:24.524813 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11391 00:28:24.604776
11392 00:28:24.697913 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (56 ms)
11393 00:28:24.802956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11394 00:28:24.803321 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11396 00:28:24.820734 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11397 00:28:24.878902 Camera needs 4 requests, can't test only 2
11398 00:28:24.966195 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11399 00:28:25.042723
11400 00:28:25.129919 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (56 ms)
11401 00:28:25.233673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11402 00:28:25.233978 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11404 00:28:25.250579 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11405 00:28:25.308525 Camera needs 4 requests, can't test only 3
11406 00:28:25.394990 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11407 00:28:25.478445
11408 00:28:25.567657 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (55 ms)
11409 00:28:25.666474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11410 00:28:25.666760 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11412 00:28:25.686975 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11413 00:28:26.514313 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (2077 ms)
11414 00:28:26.527319 [0:01:35.869004543] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11415 00:28:26.613841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11416 00:28:26.614145 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11418 00:28:26.632454 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11419 00:28:29.229070 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (2715 ms)
11420 00:28:29.242257 [0:01:38.586227928] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11421 00:28:29.329019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11422 00:28:29.329320 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11424 00:28:29.347421 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11425 00:28:32.990199 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (3761 ms)
11426 00:28:33.003394 [0:01:42.347664313] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11427 00:28:33.088069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11428 00:28:33.088366 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11430 00:28:33.104494 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11431 00:28:38.428125 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (5438 ms)
11432 00:28:38.441311 [0:01:47.786206005] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11433 00:28:38.553131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11434 00:28:38.553824 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11436 00:28:38.573485 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11437 00:28:46.601691 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (8174 ms)
11438 00:28:46.615056 [0:01:55.960828698] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11439 00:28:46.736954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11440 00:28:46.737680 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11442 00:28:46.760056 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11443 00:28:59.183574 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (12581 ms)
11444 00:28:59.196510 [0:02:08.543751699] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11445 00:28:59.284977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11446 00:28:59.285266 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11448 00:28:59.301082 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11449 00:29:18.904986 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (19723 ms)
11450 00:29:18.918146 [0:02:28.268318623] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11451 00:29:18.969707 [0:02:28.321961546] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11452 00:29:19.018454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11453 00:29:19.019108 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11455 00:29:19.031838 [0:02:28.380389392] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11456 00:29:19.040123 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11457 00:29:19.083608 [0:02:28.435095777] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11458 00:29:19.108801 Camera needs 4 requests, can't test only 1
11459 00:29:19.201213 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11460 00:29:19.284485
11461 00:29:19.376218 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (53 ms)
11462 00:29:19.468828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11463 00:29:19.469151 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11465 00:29:19.482667 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11466 00:29:19.538294 Camera needs 4 requests, can't test only 2
11467 00:29:19.613331 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11468 00:29:19.693418
11469 00:29:19.799384 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (56 ms)
11470 00:29:19.919755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11471 00:29:19.920537 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11473 00:29:19.937526 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11474 00:29:20.008580 Camera needs 4 requests, can't test only 3
11475 00:29:20.113525 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11476 00:29:20.215962
11477 00:29:20.329399 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (56 ms)
11478 00:29:20.450166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11479 00:29:20.450876 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11481 00:29:20.469490 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11482 00:29:21.154558 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (2076 ms)
11483 00:29:21.164380 [0:02:30.512229162] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11484 00:29:21.277549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11485 00:29:21.278331 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11487 00:29:21.296322 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11488 00:29:23.864230 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (2709 ms)
11489 00:29:23.874430 [0:02:33.224260700] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11490 00:29:23.989128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11491 00:29:23.989869 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11493 00:29:24.006325 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11494 00:29:27.625586 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (3761 ms)
11495 00:29:27.635030 [0:02:36.985910547] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11496 00:29:27.742823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11497 00:29:27.743731 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11499 00:29:27.759391 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11500 00:29:33.066598 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (5441 ms)
11501 00:29:33.076154 [0:02:42.427241932] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11502 00:29:33.186521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11503 00:29:33.187234 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11505 00:29:33.205074 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11506 00:29:41.241159 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (8175 ms)
11507 00:29:41.250331 [0:02:50.602454163] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11508 00:29:41.369188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11509 00:29:41.369937 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11511 00:29:41.389106 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11512 00:29:53.822550 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (12582 ms)
11513 00:29:53.832279 [0:03:03.185470471] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11514 00:29:53.963252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11515 00:29:53.964020 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11517 00:29:53.982384 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11518 00:30:13.543355 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (19723 ms)
11519 00:30:13.553111 [0:03:22.909353011] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11520 00:30:13.604173 [0:03:22.962621473] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11521 00:30:13.658290 [0:03:23.016783165] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11522 00:30:13.674998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11523 00:30:13.675727 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11525 00:30:13.693914 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11526 00:30:13.714121 [0:03:23.071981626] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11527 00:30:13.766633 Camera needs 4 requests, can't test only 1
11528 00:30:13.871108 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11529 00:30:13.974367
11530 00:30:14.088146 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (53 ms)
11531 00:30:14.212510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11532 00:30:14.213263 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11534 00:30:14.231046 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11535 00:30:14.300804 Camera needs 4 requests, can't test only 2
11536 00:30:14.406950 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11537 00:30:14.508407
11538 00:30:14.613860 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (54 ms)
11539 00:30:14.734961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11540 00:30:14.735657 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11542 00:30:14.753077 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11543 00:30:14.823144 Camera needs 4 requests, can't test only 3
11544 00:30:14.927010 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11545 00:30:15.030148
11546 00:30:15.146526 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (54 ms)
11547 00:30:15.268772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11548 00:30:15.269473 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11550 00:30:15.287985 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11551 00:30:15.786875 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (2078 ms)
11552 00:30:15.797229 [0:03:25.151151473] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11553 00:30:15.911046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11554 00:30:15.911749 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11556 00:30:15.930434 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11557 00:30:18.497558 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (2710 ms)
11558 00:30:18.507371 [0:03:27.863616550] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11559 00:30:18.617335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11560 00:30:18.617839 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11562 00:30:18.633939 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11563 00:30:22.258373 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (3761 ms)
11564 00:30:22.268234 [0:03:31.625396858] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11565 00:30:22.361267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11566 00:30:22.361587 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11568 00:30:22.377151 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11569 00:30:27.699148 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (5441 ms)
11570 00:30:27.708983 [0:03:37.066963396] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11571 00:30:27.799220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11572 00:30:27.799515 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11574 00:30:27.813684 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11575 00:30:35.873435 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (8174 ms)
11576 00:30:35.883509 [0:03:45.241687089] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11577 00:30:35.995336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11578 00:30:35.996033 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11580 00:30:36.014244 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11581 00:30:48.453741 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (12582 ms)
11582 00:30:48.463614 [0:03:57.823898936] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11583 00:30:48.575709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11584 00:30:48.576380 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11586 00:30:48.594082 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11587 00:31:08.175539 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (19722 ms)
11588 00:31:08.185044 [0:04:17.548412784] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11589 00:31:08.237209 [0:04:17.602163168] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11590 00:31:08.291397 [0:04:17.656165322] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11591 00:31:08.301529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11592 00:31:08.302209 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11594 00:31:08.320489 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11595 00:31:08.345797 [0:04:17.710645707] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11596 00:31:08.388296 Camera needs 4 requests, can't test only 1
11597 00:31:08.481152 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11598 00:31:08.572315
11599 00:31:08.678797 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (54 ms)
11600 00:31:08.795075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11601 00:31:08.795822 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11603 00:31:08.813169 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11604 00:31:08.877493 Camera needs 4 requests, can't test only 2
11605 00:31:08.972442 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11606 00:31:09.062824
11607 00:31:09.162464 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (54 ms)
11608 00:31:09.276822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11609 00:31:09.277594 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11611 00:31:09.292813 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11612 00:31:09.355857 Camera needs 4 requests, can't test only 3
11613 00:31:09.451499 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11614 00:31:09.536809
11615 00:31:09.621871 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (53 ms)
11616 00:31:09.712518 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11618 00:31:09.715483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11619 00:31:09.731276 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11620 00:31:10.418300 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (2078 ms)
11621 00:31:10.427927 [0:04:19.789021630] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11622 00:31:10.520849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11623 00:31:10.521124 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11625 00:31:10.535053 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11626 00:31:13.128608 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (2710 ms)
11627 00:31:13.138206 [0:04:22.501165399] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11628 00:31:13.246199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11629 00:31:13.246918 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11631 00:31:13.264501 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11632 00:31:16.889551 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (3761 ms)
11633 00:31:16.899484 [0:04:26.262786092] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11634 00:31:17.010845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11635 00:31:17.011521 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11637 00:31:17.026753 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11638 00:31:22.330369 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (5441 ms)
11639 00:31:22.340376 [0:04:31.704031554] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11640 00:31:22.443542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11641 00:31:22.444234 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11643 00:31:22.461482 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11644 00:31:30.504219 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (8174 ms)
11645 00:31:30.513800 [0:04:39.878816554] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11646 00:31:30.633435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11647 00:31:30.634475 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11649 00:31:30.652655 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11650 00:31:43.084978 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (12582 ms)
11651 00:31:43.094670 [0:04:52.461824555] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11652 00:31:43.183455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11653 00:31:43.183730 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11655 00:31:43.199555 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11656 00:32:02.807550 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (19724 ms)
11657 00:32:02.817248 [0:05:12.186554018] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11658 00:32:02.932243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11659 00:32:02.932991 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11661 00:32:02.948232 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11662 00:32:03.222011 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (415 ms)
11663 00:32:03.232212 [0:05:12.603951479] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11664 00:32:03.349523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11665 00:32:03.350262 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11667 00:32:03.371779 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11668 00:32:03.712139 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (489 ms)
11669 00:32:03.721565 [0:05:13.091943402] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11670 00:32:03.832367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11671 00:32:03.833091 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11673 00:32:03.853755 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11674 00:32:04.267863 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (555 ms)
11675 00:32:04.277496 [0:05:13.647666787] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11676 00:32:04.394784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11677 00:32:04.395496 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11679 00:32:04.415837 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11680 00:32:04.963602 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (695 ms)
11681 00:32:04.973771 [0:05:14.343957633] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11682 00:32:05.085683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11683 00:32:05.086630 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11685 00:32:05.105530 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11686 00:32:05.870570 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (906 ms)
11687 00:32:05.882995 [0:05:15.250722710] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11688 00:32:05.994268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11689 00:32:05.994966 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11691 00:32:06.016733 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11692 00:32:07.125250 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1255 ms)
11693 00:32:07.138473 [0:05:16.506185941] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11694 00:32:07.256064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11695 00:32:07.256780 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11697 00:32:07.280429 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11698 00:32:08.941648 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (1816 ms)
11699 00:32:08.954505 [0:05:18.322598479] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11700 00:32:09.081963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11701 00:32:09.082716 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11703 00:32:09.102319 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11704 00:32:11.667808 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (2726 ms)
11705 00:32:11.681006 [0:05:21.048930403] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11706 00:32:11.794052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11707 00:32:11.794761 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11709 00:32:11.816223 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11710 00:32:15.864109 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (4196 ms)
11711 00:32:15.877119 [0:05:25.245931172] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11712 00:32:15.985971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11713 00:32:15.986684 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11715 00:32:16.007253 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11716 00:32:22.441081 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (6577 ms)
11717 00:32:22.454099 [0:05:31.823751019] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11718 00:32:22.565891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11719 00:32:22.566180 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11721 00:32:22.584407 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11722 00:32:22.860259 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (415 ms)
11723 00:32:22.869934 [0:05:32.239349865] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11724 00:32:22.980591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11725 00:32:22.981273 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11727 00:32:22.999473 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11728 00:32:23.346400 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (486 ms)
11729 00:32:23.356348 [0:05:32.725984326] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11730 00:32:23.468493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11731 00:32:23.469328 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11733 00:32:23.485727 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11734 00:32:23.902652 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (555 ms)
11735 00:32:23.912528 [0:05:33.282041403] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11736 00:32:24.024259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11737 00:32:24.024967 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11739 00:32:24.041515 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11740 00:32:24.598204 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (695 ms)
11741 00:32:24.608198 [0:05:33.977948019] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11742 00:32:24.708010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11743 00:32:24.708304 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11745 00:32:24.722304 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11746 00:32:25.506397 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (908 ms)
11747 00:32:25.516345 [0:05:34.886163173] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11748 00:32:25.623850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11749 00:32:25.624526 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11751 00:32:25.640324 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11752 00:32:26.762715 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1256 ms)
11753 00:32:26.773047 [0:05:36.142620019] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11754 00:32:26.885025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11755 00:32:26.885745 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11757 00:32:26.903482 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11758 00:32:28.578616 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (1815 ms)
11759 00:32:28.588766 [0:05:37.958479558] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11760 00:32:28.700857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11761 00:32:28.701687 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11763 00:32:28.717129 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11764 00:32:31.306337 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (2727 ms)
11765 00:32:31.316400 [0:05:40.686737865] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11766 00:32:31.419882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11767 00:32:31.420162 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11769 00:32:31.433501 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11770 00:32:35.503141 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (4196 ms)
11771 00:32:35.513141 [0:05:44.883551019] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11772 00:32:35.623674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11773 00:32:35.624343 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11775 00:32:35.641924 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11776 00:32:42.078889 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (6576 ms)
11777 00:32:42.089077 [0:05:51.460573328] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11778 00:32:42.196199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11779 00:32:42.196917 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11781 00:32:42.212635 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11782 00:32:42.495521 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (416 ms)
11783 00:32:42.505288 [0:05:51.877016097] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11784 00:32:42.610718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11785 00:32:42.611394 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11787 00:32:42.628093 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11788 00:32:42.982159 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (486 ms)
11789 00:32:42.991698 [0:05:52.363650174] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11790 00:32:43.102909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11791 00:32:43.103583 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11793 00:32:43.120712 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11794 00:32:43.538393 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (556 ms)
11795 00:32:43.548814 [0:05:52.920228097] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11796 00:32:43.656991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11797 00:32:43.657665 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11799 00:32:43.672897 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11800 00:32:44.235143 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (696 ms)
11801 00:32:44.244908 [0:05:53.616809328] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11802 00:32:44.337805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11803 00:32:44.338095 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11805 00:32:44.351845 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11806 00:32:45.143193 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (908 ms)
11807 00:32:45.152678 [0:05:54.524922866] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11808 00:32:45.263561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11809 00:32:45.264284 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11811 00:32:45.279977 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11812 00:32:46.399786 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1256 ms)
11813 00:32:46.409301 [0:05:55.781554789] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11814 00:32:46.527172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11815 00:32:46.527893 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11817 00:32:46.545764 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11818 00:32:48.215555 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (1816 ms)
11819 00:32:48.226112 [0:05:57.598371174] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11820 00:32:48.341908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11821 00:32:48.342687 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11823 00:32:48.361470 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11824 00:32:50.942414 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (2726 ms)
11825 00:32:50.951681 [0:06:00.324804713] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11826 00:32:51.064104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11827 00:32:51.064782 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11829 00:32:51.081402 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11830 00:32:55.137089 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (4195 ms)
11831 00:32:55.147213 [0:06:04.520795021] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11832 00:32:55.265007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11833 00:32:55.265712 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11835 00:32:55.284840 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11836 00:33:01.712338 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (6576 ms)
11837 00:33:01.722518 [0:06:11.097587252] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11838 00:33:01.815024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11839 00:33:01.815345 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11841 00:33:01.829155 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11842 00:33:02.124673 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (415 ms)
11843 00:33:02.137766 [0:06:11.512898713] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11844 00:33:02.227683 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11846 00:33:02.230984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11847 00:33:02.245719 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11848 00:33:02.613454 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (485 ms)
11849 00:33:02.623316 [0:06:11.998543483] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11850 00:33:02.713047 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11852 00:33:02.716449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11853 00:33:02.729432 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11854 00:33:03.168525 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (555 ms)
11855 00:33:03.178729 [0:06:12.553884175] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11856 00:33:03.267801 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11858 00:33:03.270465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11859 00:33:03.285007 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11860 00:33:03.861135 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (695 ms)
11861 00:33:03.874392 [0:06:13.249528637] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11862 00:33:03.963933 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11864 00:33:03.967058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11865 00:33:03.982409 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11866 00:33:04.770504 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (906 ms)
11867 00:33:04.780257 [0:06:14.155485560] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11868 00:33:04.868344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11869 00:33:04.868650 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11871 00:33:04.885875 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11872 00:33:06.025565 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1255 ms)
11873 00:33:06.035942 [0:06:15.411062560] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11874 00:33:06.122042 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11876 00:33:06.124705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11877 00:33:06.139583 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11878 00:33:07.841693 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (1815 ms)
11879 00:33:07.851067 [0:06:17.226348714] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11880 00:33:07.949120 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11882 00:33:07.952595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11883 00:33:07.966417 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11884 00:33:10.566964 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (2725 ms)
11885 00:33:10.576783 [0:06:19.952194945] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11886 00:33:10.693747 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11888 00:33:10.697157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11889 00:33:10.711720 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11890 00:33:14.761732 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (4195 ms)
11891 00:33:14.771612 [0:06:24.147807483] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11892 00:33:14.863362 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11894 00:33:14.865837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11895 00:33:14.882088 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11896 00:33:21.337332 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (6576 ms)
11897 00:33:21.427257 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11899 00:33:21.430821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11900 00:33:21.443767 [----------] 120 tests from CaptureTests/SingleStream (369998 ms total)
11901 00:33:21.521574
11902 00:33:21.600982 [----------] Global test environment tear-down
11903 00:33:21.683363 [==========] 120 tests from 1 test suite ran. (369998 ms total)
11904 00:33:21.762779 <LAVA_SIGNAL_TESTSET STOP>
11905 00:33:21.763076 Received signal: <TESTSET> STOP
11906 00:33:21.763151 Closing test_set CaptureTests/SingleStream
11907 00:33:21.766328 + set +x
11908 00:33:21.769756 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 14479197_1.6.2.3.1>
11909 00:33:21.770011 Received signal: <ENDRUN> 0_lc-compliance 14479197_1.6.2.3.1
11910 00:33:21.770128 Ending use of test pattern.
11911 00:33:21.770199 Ending test lava.0_lc-compliance (14479197_1.6.2.3.1), duration 372.08
11913 00:33:21.772693 <LAVA_TEST_RUNNER EXIT>
11914 00:33:21.772966 ok: lava_test_shell seems to have completed
11915 00:33:21.774852 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11916 00:33:21.775047 end: 3.1 lava-test-shell (duration 00:06:13) [common]
11917 00:33:21.775159 end: 3 lava-test-retry (duration 00:06:13) [common]
11918 00:33:21.775276 start: 4 finalize (timeout 00:10:00) [common]
11919 00:33:21.775380 start: 4.1 power-off (timeout 00:00:30) [common]
11920 00:33:21.775516 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
11921 00:33:21.976735 >> Command sent successfully.
11922 00:33:21.980147 Returned 0 in 0 seconds
11923 00:33:22.080493 end: 4.1 power-off (duration 00:00:00) [common]
11925 00:33:22.080989 start: 4.2 read-feedback (timeout 00:10:00) [common]
11926 00:33:22.081244 Listened to connection for namespace 'common' for up to 1s
11927 00:33:23.082098 Finalising connection for namespace 'common'
11928 00:33:23.082255 Disconnecting from shell: Finalise
11929 00:33:23.082362 / #
11930 00:33:23.182661 end: 4.2 read-feedback (duration 00:00:01) [common]
11931 00:33:23.182814 end: 4 finalize (duration 00:00:01) [common]
11932 00:33:23.182928 Cleaning after the job
11933 00:33:23.183042 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479197/tftp-deploy-n9hju5wc/ramdisk
11934 00:33:23.185256 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479197/tftp-deploy-n9hju5wc/kernel
11935 00:33:23.196587 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479197/tftp-deploy-n9hju5wc/dtb
11936 00:33:23.196813 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479197/tftp-deploy-n9hju5wc/nfsrootfs
11937 00:33:23.238740 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479197/tftp-deploy-n9hju5wc/modules
11938 00:33:23.244602 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14479197
11939 00:33:23.512702 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14479197
11940 00:33:23.512871 Job finished correctly