Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 29
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 00:21:18.435492 lava-dispatcher, installed at version: 2024.03
2 00:21:18.435760 start: 0 validate
3 00:21:18.435950 Start time: 2024-06-21 00:21:18.435945+00:00 (UTC)
4 00:21:18.436100 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:21:18.436319 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 00:21:18.697310 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:21:18.697509 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:21:18.956515 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:21:18.956763 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:21:34.530583 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:21:34.531163 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:21:35.043546 validate duration: 16.61
14 00:21:35.044784 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:21:35.045272 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:21:35.045692 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:21:35.046348 Not decompressing ramdisk as can be used compressed.
18 00:21:35.046781 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 00:21:35.047117 saving as /var/lib/lava/dispatcher/tmp/14479176/tftp-deploy-325ei7s0/ramdisk/rootfs.cpio.gz
20 00:21:35.047442 total size: 28105535 (26 MB)
21 00:21:39.073063 progress 0 % (0 MB)
22 00:21:39.081096 progress 5 % (1 MB)
23 00:21:39.088929 progress 10 % (2 MB)
24 00:21:39.097210 progress 15 % (4 MB)
25 00:21:39.104751 progress 20 % (5 MB)
26 00:21:39.112026 progress 25 % (6 MB)
27 00:21:39.119189 progress 30 % (8 MB)
28 00:21:39.126465 progress 35 % (9 MB)
29 00:21:39.133599 progress 40 % (10 MB)
30 00:21:39.140601 progress 45 % (12 MB)
31 00:21:39.147753 progress 50 % (13 MB)
32 00:21:39.154919 progress 55 % (14 MB)
33 00:21:39.162101 progress 60 % (16 MB)
34 00:21:39.169340 progress 65 % (17 MB)
35 00:21:39.176496 progress 70 % (18 MB)
36 00:21:39.183708 progress 75 % (20 MB)
37 00:21:39.190861 progress 80 % (21 MB)
38 00:21:39.198054 progress 85 % (22 MB)
39 00:21:39.205196 progress 90 % (24 MB)
40 00:21:39.212385 progress 95 % (25 MB)
41 00:21:39.219996 progress 100 % (26 MB)
42 00:21:39.220260 26 MB downloaded in 4.17 s (6.42 MB/s)
43 00:21:39.220450 end: 1.1.1 http-download (duration 00:00:04) [common]
45 00:21:39.220669 end: 1.1 download-retry (duration 00:00:04) [common]
46 00:21:39.220749 start: 1.2 download-retry (timeout 00:09:56) [common]
47 00:21:39.220826 start: 1.2.1 http-download (timeout 00:09:56) [common]
48 00:21:39.220960 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:21:39.221022 saving as /var/lib/lava/dispatcher/tmp/14479176/tftp-deploy-325ei7s0/kernel/Image
50 00:21:39.221076 total size: 54813184 (52 MB)
51 00:21:39.221131 No compression specified
52 00:21:39.222130 progress 0 % (0 MB)
53 00:21:39.236805 progress 5 % (2 MB)
54 00:21:39.251149 progress 10 % (5 MB)
55 00:21:39.265517 progress 15 % (7 MB)
56 00:21:39.279662 progress 20 % (10 MB)
57 00:21:39.293417 progress 25 % (13 MB)
58 00:21:39.306957 progress 30 % (15 MB)
59 00:21:39.320736 progress 35 % (18 MB)
60 00:21:39.334675 progress 40 % (20 MB)
61 00:21:39.348450 progress 45 % (23 MB)
62 00:21:39.362431 progress 50 % (26 MB)
63 00:21:39.376341 progress 55 % (28 MB)
64 00:21:39.390142 progress 60 % (31 MB)
65 00:21:39.404275 progress 65 % (34 MB)
66 00:21:39.417920 progress 70 % (36 MB)
67 00:21:39.431707 progress 75 % (39 MB)
68 00:21:39.445377 progress 80 % (41 MB)
69 00:21:39.458908 progress 85 % (44 MB)
70 00:21:39.472623 progress 90 % (47 MB)
71 00:21:39.486389 progress 95 % (49 MB)
72 00:21:39.499911 progress 100 % (52 MB)
73 00:21:39.500144 52 MB downloaded in 0.28 s (187.32 MB/s)
74 00:21:39.500295 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:21:39.500505 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:21:39.500672 start: 1.3 download-retry (timeout 00:09:56) [common]
78 00:21:39.500767 start: 1.3.1 http-download (timeout 00:09:56) [common]
79 00:21:39.500910 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:21:39.500972 saving as /var/lib/lava/dispatcher/tmp/14479176/tftp-deploy-325ei7s0/dtb/mt8192-asurada-spherion-r0.dtb
81 00:21:39.501025 total size: 47258 (0 MB)
82 00:21:39.501078 No compression specified
83 00:21:39.508333 progress 69 % (0 MB)
84 00:21:39.508642 progress 100 % (0 MB)
85 00:21:39.508789 0 MB downloaded in 0.01 s (5.81 MB/s)
86 00:21:39.508905 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:21:39.509104 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:21:39.509180 start: 1.4 download-retry (timeout 00:09:56) [common]
90 00:21:39.509255 start: 1.4.1 http-download (timeout 00:09:56) [common]
91 00:21:39.509364 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:21:39.509425 saving as /var/lib/lava/dispatcher/tmp/14479176/tftp-deploy-325ei7s0/modules/modules.tar
93 00:21:39.509477 total size: 8618924 (8 MB)
94 00:21:39.509529 Using unxz to decompress xz
95 00:21:39.510883 progress 0 % (0 MB)
96 00:21:39.530395 progress 5 % (0 MB)
97 00:21:39.554378 progress 10 % (0 MB)
98 00:21:39.578924 progress 15 % (1 MB)
99 00:21:39.603722 progress 20 % (1 MB)
100 00:21:39.629338 progress 25 % (2 MB)
101 00:21:39.654547 progress 30 % (2 MB)
102 00:21:39.679739 progress 35 % (2 MB)
103 00:21:39.704595 progress 40 % (3 MB)
104 00:21:39.729402 progress 45 % (3 MB)
105 00:21:39.753181 progress 50 % (4 MB)
106 00:21:39.777513 progress 55 % (4 MB)
107 00:21:39.801758 progress 60 % (4 MB)
108 00:21:39.825657 progress 65 % (5 MB)
109 00:21:39.853546 progress 70 % (5 MB)
110 00:21:39.879185 progress 75 % (6 MB)
111 00:21:39.903339 progress 80 % (6 MB)
112 00:21:39.927366 progress 85 % (7 MB)
113 00:21:39.951654 progress 90 % (7 MB)
114 00:21:39.978796 progress 95 % (7 MB)
115 00:21:40.007347 progress 100 % (8 MB)
116 00:21:40.011819 8 MB downloaded in 0.50 s (16.36 MB/s)
117 00:21:40.012031 end: 1.4.1 http-download (duration 00:00:01) [common]
119 00:21:40.012402 end: 1.4 download-retry (duration 00:00:01) [common]
120 00:21:40.012523 start: 1.5 prepare-tftp-overlay (timeout 00:09:55) [common]
121 00:21:40.012636 start: 1.5.1 extract-nfsrootfs (timeout 00:09:55) [common]
122 00:21:40.012743 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:21:40.012854 start: 1.5.2 lava-overlay (timeout 00:09:55) [common]
124 00:21:40.013070 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm
125 00:21:40.013248 makedir: /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin
126 00:21:40.013381 makedir: /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/tests
127 00:21:40.013512 makedir: /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/results
128 00:21:40.013648 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-add-keys
129 00:21:40.013824 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-add-sources
130 00:21:40.014004 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-background-process-start
131 00:21:40.014177 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-background-process-stop
132 00:21:40.014377 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-common-functions
133 00:21:40.014547 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-echo-ipv4
134 00:21:40.014723 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-install-packages
135 00:21:40.014889 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-installed-packages
136 00:21:40.015051 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-os-build
137 00:21:40.015222 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-probe-channel
138 00:21:40.015398 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-probe-ip
139 00:21:40.015558 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-target-ip
140 00:21:40.015716 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-target-mac
141 00:21:40.015873 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-target-storage
142 00:21:40.016033 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-test-case
143 00:21:40.016192 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-test-event
144 00:21:40.016348 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-test-feedback
145 00:21:40.016502 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-test-raise
146 00:21:40.016661 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-test-reference
147 00:21:40.016817 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-test-runner
148 00:21:40.016982 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-test-set
149 00:21:40.017145 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-test-shell
150 00:21:40.017333 Updating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-install-packages (oe)
151 00:21:40.017523 Updating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/bin/lava-installed-packages (oe)
152 00:21:40.017678 Creating /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/environment
153 00:21:40.017805 LAVA metadata
154 00:21:40.017901 - LAVA_JOB_ID=14479176
155 00:21:40.018001 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:21:40.018149 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:55) [common]
157 00:21:40.018237 skipped lava-vland-overlay
158 00:21:40.018337 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:21:40.018443 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:55) [common]
160 00:21:40.018530 skipped lava-multinode-overlay
161 00:21:40.018629 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:21:40.018734 start: 1.5.2.3 test-definition (timeout 00:09:55) [common]
163 00:21:40.018830 Loading test definitions
164 00:21:40.018941 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:55) [common]
165 00:21:40.019031 Using /lava-14479176 at stage 0
166 00:21:40.019471 uuid=14479176_1.5.2.3.1 testdef=None
167 00:21:40.019587 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:21:40.019699 start: 1.5.2.3.2 test-overlay (timeout 00:09:55) [common]
169 00:21:40.020334 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:21:40.020645 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:55) [common]
172 00:21:40.021505 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:21:40.021838 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:55) [common]
175 00:21:40.022636 runner path: /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 14479176_1.5.2.3.1
176 00:21:40.022835 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:21:40.023144 Creating lava-test-runner.conf files
179 00:21:40.023230 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14479176/lava-overlay-4l3abdvm/lava-14479176/0 for stage 0
180 00:21:40.023344 - 0_v4l2-compliance-mtk-vcodec-enc
181 00:21:40.023472 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:21:40.023585 start: 1.5.2.4 compress-overlay (timeout 00:09:55) [common]
183 00:21:40.032166 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:21:40.032319 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:55) [common]
185 00:21:40.032444 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:21:40.032564 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:21:40.032680 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:55) [common]
188 00:21:40.928809 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 00:21:40.928936 start: 1.5.4 extract-modules (timeout 00:09:54) [common]
190 00:21:40.929013 extracting modules file /var/lib/lava/dispatcher/tmp/14479176/tftp-deploy-325ei7s0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479176/extract-overlay-ramdisk-rb_4y7by/ramdisk
191 00:21:41.165320 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:21:41.165446 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
193 00:21:41.165521 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14479176/compress-overlay-qlsaoqid/overlay-1.5.2.4.tar.gz to ramdisk
194 00:21:41.165583 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14479176/compress-overlay-qlsaoqid/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14479176/extract-overlay-ramdisk-rb_4y7by/ramdisk
195 00:21:41.172067 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:21:41.172170 start: 1.5.6 configure-preseed-file (timeout 00:09:54) [common]
197 00:21:41.172251 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:21:41.172330 start: 1.5.7 compress-ramdisk (timeout 00:09:54) [common]
199 00:21:41.172396 Building ramdisk /var/lib/lava/dispatcher/tmp/14479176/extract-overlay-ramdisk-rb_4y7by/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14479176/extract-overlay-ramdisk-rb_4y7by/ramdisk
200 00:21:41.802473 >> 276034 blocks
201 00:21:46.048724 rename /var/lib/lava/dispatcher/tmp/14479176/extract-overlay-ramdisk-rb_4y7by/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14479176/tftp-deploy-325ei7s0/ramdisk/ramdisk.cpio.gz
202 00:21:46.048906 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 00:21:46.048999 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 00:21:46.049077 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 00:21:46.049156 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14479176/tftp-deploy-325ei7s0/kernel/Image']
206 00:22:00.764440 Returned 0 in 14 seconds
207 00:22:00.864946 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14479176/tftp-deploy-325ei7s0/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14479176/tftp-deploy-325ei7s0/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14479176/tftp-deploy-325ei7s0/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14479176/tftp-deploy-325ei7s0/kernel/image.itb
208 00:22:01.549601 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:22:01.549721 output: Created: Fri Jun 21 01:22:01 2024
210 00:22:01.549808 output: Image 0 (kernel-1)
211 00:22:01.549863 output: Description:
212 00:22:01.549919 output: Created: Fri Jun 21 01:22:01 2024
213 00:22:01.549973 output: Type: Kernel Image
214 00:22:01.550054 output: Compression: lzma compressed
215 00:22:01.550108 output: Data Size: 13124896 Bytes = 12817.28 KiB = 12.52 MiB
216 00:22:01.550159 output: Architecture: AArch64
217 00:22:01.550208 output: OS: Linux
218 00:22:01.550258 output: Load Address: 0x00000000
219 00:22:01.550306 output: Entry Point: 0x00000000
220 00:22:01.550357 output: Hash algo: crc32
221 00:22:01.550407 output: Hash value: ab2f7826
222 00:22:01.550454 output: Image 1 (fdt-1)
223 00:22:01.550506 output: Description: mt8192-asurada-spherion-r0
224 00:22:01.550559 output: Created: Fri Jun 21 01:22:01 2024
225 00:22:01.550611 output: Type: Flat Device Tree
226 00:22:01.550665 output: Compression: uncompressed
227 00:22:01.550719 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 00:22:01.550774 output: Architecture: AArch64
229 00:22:01.550828 output: Hash algo: crc32
230 00:22:01.550880 output: Hash value: 0f8e4d2e
231 00:22:01.550952 output: Image 2 (ramdisk-1)
232 00:22:01.551015 output: Description: unavailable
233 00:22:01.551065 output: Created: Fri Jun 21 01:22:01 2024
234 00:22:01.551114 output: Type: RAMDisk Image
235 00:22:01.551161 output: Compression: uncompressed
236 00:22:01.551228 output: Data Size: 41222833 Bytes = 40256.67 KiB = 39.31 MiB
237 00:22:01.551278 output: Architecture: AArch64
238 00:22:01.551325 output: OS: Linux
239 00:22:01.551372 output: Load Address: unavailable
240 00:22:01.551435 output: Entry Point: unavailable
241 00:22:01.551497 output: Hash algo: crc32
242 00:22:01.551544 output: Hash value: 04068bc5
243 00:22:01.551591 output: Default Configuration: 'conf-1'
244 00:22:01.551638 output: Configuration 0 (conf-1)
245 00:22:01.551685 output: Description: mt8192-asurada-spherion-r0
246 00:22:01.551732 output: Kernel: kernel-1
247 00:22:01.551779 output: Init Ramdisk: ramdisk-1
248 00:22:01.551827 output: FDT: fdt-1
249 00:22:01.551874 output: Loadables: kernel-1
250 00:22:01.551940 output:
251 00:22:01.552093 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 00:22:01.552173 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 00:22:01.552260 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 00:22:01.552342 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:33) [common]
255 00:22:01.552409 No LXC device requested
256 00:22:01.552481 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:22:01.552556 start: 1.7 deploy-device-env (timeout 00:09:33) [common]
258 00:22:01.552631 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:22:01.552714 Checking files for TFTP limit of 4294967296 bytes.
260 00:22:01.553176 end: 1 tftp-deploy (duration 00:00:27) [common]
261 00:22:01.553288 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:22:01.553385 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:22:01.553490 substitutions:
264 00:22:01.553548 - {DTB}: 14479176/tftp-deploy-325ei7s0/dtb/mt8192-asurada-spherion-r0.dtb
265 00:22:01.553606 - {INITRD}: 14479176/tftp-deploy-325ei7s0/ramdisk/ramdisk.cpio.gz
266 00:22:01.553656 - {KERNEL}: 14479176/tftp-deploy-325ei7s0/kernel/Image
267 00:22:01.553706 - {LAVA_MAC}: None
268 00:22:01.553773 - {PRESEED_CONFIG}: None
269 00:22:01.553824 - {PRESEED_LOCAL}: None
270 00:22:01.553873 - {RAMDISK}: 14479176/tftp-deploy-325ei7s0/ramdisk/ramdisk.cpio.gz
271 00:22:01.553930 - {ROOT_PART}: None
272 00:22:01.553986 - {ROOT}: None
273 00:22:01.554053 - {SERVER_IP}: 192.168.201.1
274 00:22:01.554101 - {TEE}: None
275 00:22:01.554150 Parsed boot commands:
276 00:22:01.554197 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:22:01.554344 Parsed boot commands: tftpboot 192.168.201.1 14479176/tftp-deploy-325ei7s0/kernel/image.itb 14479176/tftp-deploy-325ei7s0/kernel/cmdline
278 00:22:01.554424 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:22:01.554498 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:22:01.554593 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:22:01.554685 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:22:01.554746 Not connected, no need to disconnect.
283 00:22:01.554811 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:22:01.554884 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:22:01.554941 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 00:22:01.558466 Setting prompt string to ['lava-test: # ']
287 00:22:01.558827 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:22:01.558927 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:22:01.559021 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:22:01.559106 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:22:01.559297 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
292 00:22:08.185657 >> Command sent successfully.
293 00:22:08.189653 Returned 0 in 6 seconds
294 00:22:08.290001 end: 2.2.2.1 pdu-reboot (duration 00:00:07) [common]
296 00:22:08.290335 end: 2.2.2 reset-device (duration 00:00:07) [common]
297 00:22:08.290425 start: 2.2.3 depthcharge-start (timeout 00:04:53) [common]
298 00:22:08.290514 Setting prompt string to 'Starting depthcharge on Spherion...'
299 00:22:08.290575 Changing prompt to 'Starting depthcharge on Spherion...'
300 00:22:08.290640 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 00:22:08.291000 [Enter `^Ec?' for help]
302 00:22:08.291070
303 00:22:08.291155
304 00:22:08.291215 F0: 102B 0000
305 00:22:08.291270
306 00:22:08.291325 F3: 1001 0000 [0200]
307 00:22:08.291398
308 00:22:08.291472 F3: 1001 0000
309 00:22:08.291536
310 00:22:08.291592 F7: 102D 0000
311 00:22:08.291649
312 00:22:08.291707 F1: 0000 0000
313 00:22:08.291783
314 00:22:08.291865 V0: 0000 0000 [0001]
315 00:22:08.291944
316 00:22:08.292030 00: 0007 8000
317 00:22:08.292086
318 00:22:08.292139 01: 0000 0000
319 00:22:08.292190
320 00:22:08.292239 BP: 0C00 0209 [0000]
321 00:22:08.292288
322 00:22:08.292336 G0: 1182 0000
323 00:22:08.292384
324 00:22:08.292462 EC: 0000 0021 [4000]
325 00:22:08.292538
326 00:22:08.292617 S7: 0000 0000 [0000]
327 00:22:08.292698
328 00:22:08.292809 CC: 0000 0000 [0001]
329 00:22:08.292920
330 00:22:08.293030 T0: 0000 0040 [010F]
331 00:22:08.293109
332 00:22:08.293186 Jump to BL
333 00:22:08.293267
334 00:22:08.301415
335 00:22:08.301502
336 00:22:08.308930 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 00:22:08.312563 ARM64: Exception handlers installed.
338 00:22:08.315560 ARM64: Testing exception
339 00:22:08.319099 ARM64: Done test exception
340 00:22:08.325831 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 00:22:08.336255 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 00:22:08.343016 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 00:22:08.352943 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 00:22:08.359893 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 00:22:08.366091 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 00:22:08.378190 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 00:22:08.384825 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 00:22:08.404167 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 00:22:08.407592 WDT: Last reset was cold boot
350 00:22:08.410967 SPI1(PAD0) initialized at 2873684 Hz
351 00:22:08.414416 SPI5(PAD0) initialized at 992727 Hz
352 00:22:08.418130 VBOOT: Loading verstage.
353 00:22:08.424403 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 00:22:08.427879 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 00:22:08.431014 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 00:22:08.434261 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 00:22:08.441684 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 00:22:08.448464 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 00:22:08.459418 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
360 00:22:08.459530
361 00:22:08.459592
362 00:22:08.469007 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 00:22:08.472784 ARM64: Exception handlers installed.
364 00:22:08.475883 ARM64: Testing exception
365 00:22:08.475968 ARM64: Done test exception
366 00:22:08.482664 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 00:22:08.485776 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 00:22:08.499982 Probing TPM: . done!
369 00:22:08.500073 TPM ready after 0 ms
370 00:22:08.507098 Connected to device vid:did:rid of 1ae0:0028:00
371 00:22:08.513655 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 00:22:08.517381 Initialized TPM device CR50 revision 0
373 00:22:08.567161 tlcl_send_startup: Startup return code is 0
374 00:22:08.567273 TPM: setup succeeded
375 00:22:08.578468 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 00:22:08.587121 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 00:22:08.597552 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 00:22:08.605947 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 00:22:08.609477 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 00:22:08.613152 in-header: 03 07 00 00 08 00 00 00
381 00:22:08.616199 in-data: aa e4 47 04 13 02 00 00
382 00:22:08.619880 Chrome EC: UHEPI supported
383 00:22:08.626404 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 00:22:08.629515 in-header: 03 c9 00 00 08 00 00 00
385 00:22:08.633055 in-data: 04 00 20 08 00 00 00 00
386 00:22:08.636440 Phase 1
387 00:22:08.639777 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 00:22:08.646236 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 00:22:08.649788 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 00:22:08.653258 Recovery requested (1009000e)
391 00:22:08.656456 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 00:22:08.666436 tlcl_extend: response is 0
393 00:22:08.676208 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 00:22:08.679956 tlcl_extend: response is 0
395 00:22:08.686704 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 00:22:08.707131 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
397 00:22:08.713397 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 00:22:08.713503
399 00:22:08.713591
400 00:22:08.723653 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 00:22:08.727234 ARM64: Exception handlers installed.
402 00:22:08.731003 ARM64: Testing exception
403 00:22:08.731080 ARM64: Done test exception
404 00:22:08.752252 pmic_efuse_setting: Set efuses in 11 msecs
405 00:22:08.755821 pmwrap_interface_init: Select PMIF_VLD_RDY
406 00:22:08.762449 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 00:22:08.765660 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 00:22:08.772173 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 00:22:08.775844 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 00:22:08.782665 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 00:22:08.786161 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 00:22:08.789327 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 00:22:08.796070 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 00:22:08.799671 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 00:22:08.806333 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 00:22:08.809537 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 00:22:08.812504 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 00:22:08.819470 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 00:22:08.826251 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 00:22:08.829258 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 00:22:08.836330 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 00:22:08.843373 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 00:22:08.846274 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 00:22:08.852921 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 00:22:08.859444 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 00:22:08.863133 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 00:22:08.869831 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 00:22:08.876543 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 00:22:08.879411 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 00:22:08.886257 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 00:22:08.893265 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 00:22:08.896379 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 00:22:08.903255 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 00:22:08.906126 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 00:22:08.909820 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 00:22:08.916521 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 00:22:08.922994 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 00:22:08.926585 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 00:22:08.933407 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 00:22:08.936496 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 00:22:08.940214 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 00:22:08.946536 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 00:22:08.950078 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 00:22:08.956819 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 00:22:08.960130 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 00:22:08.963707 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 00:22:08.970389 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 00:22:08.974083 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 00:22:08.977351 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 00:22:08.980970 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 00:22:08.987255 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 00:22:08.990627 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 00:22:08.993896 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 00:22:09.001103 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 00:22:09.004256 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 00:22:09.007759 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 00:22:09.013803 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 00:22:09.024302 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 00:22:09.027369 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 00:22:09.037647 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 00:22:09.044489 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 00:22:09.050972 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 00:22:09.054395 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 00:22:09.057812 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:22:09.065180 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x32
466 00:22:09.072224 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 00:22:09.075477 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 00:22:09.078567 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 00:22:09.090146 [RTC]rtc_get_frequency_meter,154: input=15, output=790
470 00:22:09.099470 [RTC]rtc_get_frequency_meter,154: input=23, output=979
471 00:22:09.108711 [RTC]rtc_get_frequency_meter,154: input=19, output=884
472 00:22:09.118207 [RTC]rtc_get_frequency_meter,154: input=17, output=837
473 00:22:09.127601 [RTC]rtc_get_frequency_meter,154: input=16, output=815
474 00:22:09.137173 [RTC]rtc_get_frequency_meter,154: input=15, output=791
475 00:22:09.147126 [RTC]rtc_get_frequency_meter,154: input=16, output=814
476 00:22:09.150155 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
477 00:22:09.157767 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
478 00:22:09.161295 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 00:22:09.164602 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 00:22:09.167798 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 00:22:09.174420 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 00:22:09.174498 ADC[4]: Raw value=902066 ID=7
483 00:22:09.177608 ADC[3]: Raw value=213336 ID=1
484 00:22:09.181183 RAM Code: 0x71
485 00:22:09.184372 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 00:22:09.190869 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 00:22:09.198169 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 00:22:09.204291 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 00:22:09.208000 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 00:22:09.210949 in-header: 03 07 00 00 08 00 00 00
491 00:22:09.214794 in-data: aa e4 47 04 13 02 00 00
492 00:22:09.218283 Chrome EC: UHEPI supported
493 00:22:09.225038 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 00:22:09.227827 in-header: 03 c9 00 00 08 00 00 00
495 00:22:09.231479 in-data: 04 00 20 08 00 00 00 00
496 00:22:09.234515 MRC: failed to locate region type 0.
497 00:22:09.241790 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 00:22:09.244760 DRAM-K: Running full calibration
499 00:22:09.251387 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 00:22:09.251460 header.status = 0x0
501 00:22:09.255177 header.version = 0x6 (expected: 0x6)
502 00:22:09.258224 header.size = 0xd00 (expected: 0xd00)
503 00:22:09.261900 header.flags = 0x0
504 00:22:09.268345 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 00:22:09.284490 read SPI 0x72590 0x1c583: 12504 us, 9284 KB/s, 74.272 Mbps
506 00:22:09.291633 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 00:22:09.294596 dram_init: ddr_geometry: 2
508 00:22:09.298174 [EMI] MDL number = 2
509 00:22:09.298250 [EMI] Get MDL freq = 0
510 00:22:09.301550 dram_init: ddr_type: 0
511 00:22:09.301626 is_discrete_lpddr4: 1
512 00:22:09.304606 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 00:22:09.304681
514 00:22:09.304739
515 00:22:09.308400 [Bian_co] ETT version 0.0.0.1
516 00:22:09.315064 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 00:22:09.315139
518 00:22:09.318132 dramc_set_vcore_voltage set vcore to 650000
519 00:22:09.318208 Read voltage for 800, 4
520 00:22:09.321688 Vio18 = 0
521 00:22:09.321764 Vcore = 650000
522 00:22:09.321822 Vdram = 0
523 00:22:09.325288 Vddq = 0
524 00:22:09.325364 Vmddr = 0
525 00:22:09.328173 dram_init: config_dvfs: 1
526 00:22:09.331824 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 00:22:09.338619 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 00:22:09.341795 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
529 00:22:09.345217 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
530 00:22:09.348870 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
531 00:22:09.351926 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
532 00:22:09.355496 MEM_TYPE=3, freq_sel=18
533 00:22:09.358516 sv_algorithm_assistance_LP4_1600
534 00:22:09.362315 ============ PULL DRAM RESETB DOWN ============
535 00:22:09.365309 ========== PULL DRAM RESETB DOWN end =========
536 00:22:09.371889 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 00:22:09.375382 ===================================
538 00:22:09.375458 LPDDR4 DRAM CONFIGURATION
539 00:22:09.379069 ===================================
540 00:22:09.382285 EX_ROW_EN[0] = 0x0
541 00:22:09.382361 EX_ROW_EN[1] = 0x0
542 00:22:09.385874 LP4Y_EN = 0x0
543 00:22:09.385973 WORK_FSP = 0x0
544 00:22:09.388842 WL = 0x2
545 00:22:09.392471 RL = 0x2
546 00:22:09.392547 BL = 0x2
547 00:22:09.395575 RPST = 0x0
548 00:22:09.395641 RD_PRE = 0x0
549 00:22:09.399200 WR_PRE = 0x1
550 00:22:09.399320 WR_PST = 0x0
551 00:22:09.402744 DBI_WR = 0x0
552 00:22:09.402889 DBI_RD = 0x0
553 00:22:09.405490 OTF = 0x1
554 00:22:09.409498 ===================================
555 00:22:09.412562 ===================================
556 00:22:09.412668 ANA top config
557 00:22:09.415688 ===================================
558 00:22:09.419547 DLL_ASYNC_EN = 0
559 00:22:09.419650 ALL_SLAVE_EN = 1
560 00:22:09.422484 NEW_RANK_MODE = 1
561 00:22:09.426121 DLL_IDLE_MODE = 1
562 00:22:09.429274 LP45_APHY_COMB_EN = 1
563 00:22:09.432892 TX_ODT_DIS = 1
564 00:22:09.433011 NEW_8X_MODE = 1
565 00:22:09.435929 ===================================
566 00:22:09.439607 ===================================
567 00:22:09.442962 data_rate = 1600
568 00:22:09.445887 CKR = 1
569 00:22:09.449376 DQ_P2S_RATIO = 8
570 00:22:09.453045 ===================================
571 00:22:09.455996 CA_P2S_RATIO = 8
572 00:22:09.456097 DQ_CA_OPEN = 0
573 00:22:09.459699 DQ_SEMI_OPEN = 0
574 00:22:09.463299 CA_SEMI_OPEN = 0
575 00:22:09.466368 CA_FULL_RATE = 0
576 00:22:09.469652 DQ_CKDIV4_EN = 1
577 00:22:09.469752 CA_CKDIV4_EN = 1
578 00:22:09.473359 CA_PREDIV_EN = 0
579 00:22:09.476438 PH8_DLY = 0
580 00:22:09.479822 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 00:22:09.483415 DQ_AAMCK_DIV = 4
582 00:22:09.486476 CA_AAMCK_DIV = 4
583 00:22:09.486583 CA_ADMCK_DIV = 4
584 00:22:09.489714 DQ_TRACK_CA_EN = 0
585 00:22:09.493221 CA_PICK = 800
586 00:22:09.496987 CA_MCKIO = 800
587 00:22:09.499955 MCKIO_SEMI = 0
588 00:22:09.503543 PLL_FREQ = 3068
589 00:22:09.503652 DQ_UI_PI_RATIO = 32
590 00:22:09.506696 CA_UI_PI_RATIO = 0
591 00:22:09.510278 ===================================
592 00:22:09.513598 ===================================
593 00:22:09.516950 memory_type:LPDDR4
594 00:22:09.520634 GP_NUM : 10
595 00:22:09.520730 SRAM_EN : 1
596 00:22:09.523618 MD32_EN : 0
597 00:22:09.526735 ===================================
598 00:22:09.526840 [ANA_INIT] >>>>>>>>>>>>>>
599 00:22:09.530466 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 00:22:09.533970 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 00:22:09.537127 ===================================
602 00:22:09.540306 data_rate = 1600,PCW = 0X7600
603 00:22:09.544030 ===================================
604 00:22:09.547648 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 00:22:09.554214 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 00:22:09.557321 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 00:22:09.563694 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 00:22:09.567398 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 00:22:09.570579 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 00:22:09.570684 [ANA_INIT] flow start
611 00:22:09.574286 [ANA_INIT] PLL >>>>>>>>
612 00:22:09.577562 [ANA_INIT] PLL <<<<<<<<
613 00:22:09.580650 [ANA_INIT] MIDPI >>>>>>>>
614 00:22:09.580750 [ANA_INIT] MIDPI <<<<<<<<
615 00:22:09.584252 [ANA_INIT] DLL >>>>>>>>
616 00:22:09.584349 [ANA_INIT] flow end
617 00:22:09.590701 ============ LP4 DIFF to SE enter ============
618 00:22:09.594463 ============ LP4 DIFF to SE exit ============
619 00:22:09.597457 [ANA_INIT] <<<<<<<<<<<<<
620 00:22:09.601015 [Flow] Enable top DCM control >>>>>
621 00:22:09.604005 [Flow] Enable top DCM control <<<<<
622 00:22:09.604105 Enable DLL master slave shuffle
623 00:22:09.610867 ==============================================================
624 00:22:09.614608 Gating Mode config
625 00:22:09.617601 ==============================================================
626 00:22:09.620985 Config description:
627 00:22:09.631112 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 00:22:09.637978 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 00:22:09.640993 SELPH_MODE 0: By rank 1: By Phase
630 00:22:09.647691 ==============================================================
631 00:22:09.651385 GAT_TRACK_EN = 1
632 00:22:09.654854 RX_GATING_MODE = 2
633 00:22:09.654964 RX_GATING_TRACK_MODE = 2
634 00:22:09.657914 SELPH_MODE = 1
635 00:22:09.661609 PICG_EARLY_EN = 1
636 00:22:09.664728 VALID_LAT_VALUE = 1
637 00:22:09.671428 ==============================================================
638 00:22:09.674457 Enter into Gating configuration >>>>
639 00:22:09.677946 Exit from Gating configuration <<<<
640 00:22:09.681326 Enter into DVFS_PRE_config >>>>>
641 00:22:09.691019 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 00:22:09.694629 Exit from DVFS_PRE_config <<<<<
643 00:22:09.697978 Enter into PICG configuration >>>>
644 00:22:09.701151 Exit from PICG configuration <<<<
645 00:22:09.704901 [RX_INPUT] configuration >>>>>
646 00:22:09.707887 [RX_INPUT] configuration <<<<<
647 00:22:09.711551 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 00:22:09.717712 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 00:22:09.724414 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 00:22:09.727979 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 00:22:09.734902 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 00:22:09.741416 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 00:22:09.744914 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 00:22:09.747857 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 00:22:09.754652 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 00:22:09.757709 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 00:22:09.761321 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 00:22:09.768093 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 00:22:09.771196 ===================================
660 00:22:09.771271 LPDDR4 DRAM CONFIGURATION
661 00:22:09.774828 ===================================
662 00:22:09.777978 EX_ROW_EN[0] = 0x0
663 00:22:09.780980 EX_ROW_EN[1] = 0x0
664 00:22:09.781055 LP4Y_EN = 0x0
665 00:22:09.784776 WORK_FSP = 0x0
666 00:22:09.784850 WL = 0x2
667 00:22:09.788352 RL = 0x2
668 00:22:09.788426 BL = 0x2
669 00:22:09.791327 RPST = 0x0
670 00:22:09.791401 RD_PRE = 0x0
671 00:22:09.794780 WR_PRE = 0x1
672 00:22:09.794854 WR_PST = 0x0
673 00:22:09.797767 DBI_WR = 0x0
674 00:22:09.797841 DBI_RD = 0x0
675 00:22:09.801535 OTF = 0x1
676 00:22:09.804741 ===================================
677 00:22:09.808025 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 00:22:09.811283 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 00:22:09.814525 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 00:22:09.817876 ===================================
681 00:22:09.821090 LPDDR4 DRAM CONFIGURATION
682 00:22:09.824696 ===================================
683 00:22:09.827723 EX_ROW_EN[0] = 0x10
684 00:22:09.827798 EX_ROW_EN[1] = 0x0
685 00:22:09.831503 LP4Y_EN = 0x0
686 00:22:09.831577 WORK_FSP = 0x0
687 00:22:09.834407 WL = 0x2
688 00:22:09.834481 RL = 0x2
689 00:22:09.837815 BL = 0x2
690 00:22:09.837913 RPST = 0x0
691 00:22:09.841573 RD_PRE = 0x0
692 00:22:09.841671 WR_PRE = 0x1
693 00:22:09.844635 WR_PST = 0x0
694 00:22:09.848027 DBI_WR = 0x0
695 00:22:09.848125 DBI_RD = 0x0
696 00:22:09.851122 OTF = 0x1
697 00:22:09.854658 ===================================
698 00:22:09.857719 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 00:22:09.863000 nWR fixed to 40
700 00:22:09.866593 [ModeRegInit_LP4] CH0 RK0
701 00:22:09.866664 [ModeRegInit_LP4] CH0 RK1
702 00:22:09.870329 [ModeRegInit_LP4] CH1 RK0
703 00:22:09.873324 [ModeRegInit_LP4] CH1 RK1
704 00:22:09.873389 match AC timing 13
705 00:22:09.880038 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 00:22:09.883288 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 00:22:09.886788 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 00:22:09.893526 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 00:22:09.896484 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 00:22:09.896559 [EMI DOE] emi_dcm 0
711 00:22:09.903121 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 00:22:09.903286 ==
713 00:22:09.906791 Dram Type= 6, Freq= 0, CH_0, rank 0
714 00:22:09.909705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 00:22:09.909814 ==
716 00:22:09.916612 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 00:22:09.920214 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 00:22:09.930702 [CA 0] Center 37 (7~68) winsize 62
719 00:22:09.934258 [CA 1] Center 37 (6~68) winsize 63
720 00:22:09.937370 [CA 2] Center 35 (5~66) winsize 62
721 00:22:09.940828 [CA 3] Center 34 (4~65) winsize 62
722 00:22:09.944325 [CA 4] Center 34 (3~65) winsize 63
723 00:22:09.947315 [CA 5] Center 33 (3~64) winsize 62
724 00:22:09.947389
725 00:22:09.950902 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 00:22:09.950976
727 00:22:09.954235 [CATrainingPosCal] consider 1 rank data
728 00:22:09.957787 u2DelayCellTimex100 = 270/100 ps
729 00:22:09.960798 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 00:22:09.965013 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 00:22:09.968116 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
732 00:22:09.971826 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 00:22:09.974855 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
734 00:22:09.981644 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 00:22:09.981744
736 00:22:09.985235 CA PerBit enable=1, Macro0, CA PI delay=33
737 00:22:09.985310
738 00:22:09.988295 [CBTSetCACLKResult] CA Dly = 33
739 00:22:09.988370 CS Dly: 5 (0~36)
740 00:22:09.988428 ==
741 00:22:09.991352 Dram Type= 6, Freq= 0, CH_0, rank 1
742 00:22:09.995148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 00:22:09.998181 ==
744 00:22:10.001848 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 00:22:10.008317 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 00:22:10.017243 [CA 0] Center 37 (6~68) winsize 63
747 00:22:10.020092 [CA 1] Center 37 (6~68) winsize 63
748 00:22:10.023594 [CA 2] Center 35 (5~66) winsize 62
749 00:22:10.027152 [CA 3] Center 35 (4~66) winsize 63
750 00:22:10.030138 [CA 4] Center 34 (4~65) winsize 62
751 00:22:10.033704 [CA 5] Center 33 (3~64) winsize 62
752 00:22:10.033778
753 00:22:10.036991 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 00:22:10.037066
755 00:22:10.040503 [CATrainingPosCal] consider 2 rank data
756 00:22:10.043745 u2DelayCellTimex100 = 270/100 ps
757 00:22:10.047230 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 00:22:10.050133 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
759 00:22:10.056840 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
760 00:22:10.060196 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 00:22:10.063809 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
762 00:22:10.066806 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 00:22:10.066904
764 00:22:10.070621 CA PerBit enable=1, Macro0, CA PI delay=33
765 00:22:10.070697
766 00:22:10.073923 [CBTSetCACLKResult] CA Dly = 33
767 00:22:10.074021 CS Dly: 5 (0~37)
768 00:22:10.074094
769 00:22:10.077136 ----->DramcWriteLeveling(PI) begin...
770 00:22:10.080264 ==
771 00:22:10.080339 Dram Type= 6, Freq= 0, CH_0, rank 0
772 00:22:10.087250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 00:22:10.087327 ==
774 00:22:10.090398 Write leveling (Byte 0): 27 => 27
775 00:22:10.094200 Write leveling (Byte 1): 27 => 27
776 00:22:10.097129 DramcWriteLeveling(PI) end<-----
777 00:22:10.097203
778 00:22:10.097260 ==
779 00:22:10.100666 Dram Type= 6, Freq= 0, CH_0, rank 0
780 00:22:10.103779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 00:22:10.103854 ==
782 00:22:10.106863 [Gating] SW mode calibration
783 00:22:10.113868 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 00:22:10.116754 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 00:22:10.123561 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 00:22:10.127200 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 00:22:10.130572 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
788 00:22:10.137331 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 00:22:10.140322 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:22:10.143443 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:22:10.150506 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:22:10.153911 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:22:10.156963 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 00:22:10.164050 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 00:22:10.166895 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 00:22:10.170361 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 00:22:10.176995 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 00:22:10.180647 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 00:22:10.183936 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 00:22:10.190604 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 00:22:10.193551 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 00:22:10.197279 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 00:22:10.200308 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 00:22:10.206985 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 00:22:10.210707 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 00:22:10.213829 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 00:22:10.220542 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 00:22:10.223907 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 00:22:10.227152 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 00:22:10.233853 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 00:22:10.236956 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 00:22:10.240794 0 9 12 | B1->B0 | 2727 2f2f | 0 0 | (0 0) (0 0)
813 00:22:10.247491 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 00:22:10.250569 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 00:22:10.254216 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 00:22:10.260853 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 00:22:10.264405 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 00:22:10.267098 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 00:22:10.270709 0 10 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
820 00:22:10.277010 0 10 12 | B1->B0 | 3030 2626 | 0 0 | (0 1) (0 0)
821 00:22:10.280579 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 00:22:10.283530 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 00:22:10.290641 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 00:22:10.293772 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 00:22:10.297292 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 00:22:10.303991 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 00:22:10.307122 0 11 8 | B1->B0 | 2525 2b2b | 1 1 | (0 0) (0 0)
828 00:22:10.310308 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
829 00:22:10.317434 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 00:22:10.320574 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 00:22:10.323559 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 00:22:10.330411 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 00:22:10.334207 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 00:22:10.337095 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 00:22:10.343548 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
836 00:22:10.347224 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 00:22:10.350307 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 00:22:10.356980 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 00:22:10.360505 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 00:22:10.363702 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 00:22:10.370132 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 00:22:10.373748 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 00:22:10.377384 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 00:22:10.380168 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 00:22:10.387224 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 00:22:10.390828 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 00:22:10.394198 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 00:22:10.400645 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 00:22:10.403918 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 00:22:10.407535 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 00:22:10.413784 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
852 00:22:10.417539 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 00:22:10.420500 Total UI for P1: 0, mck2ui 16
854 00:22:10.423633 best dqsien dly found for B0: ( 0, 14, 8)
855 00:22:10.427516 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 00:22:10.430491 Total UI for P1: 0, mck2ui 16
857 00:22:10.433917 best dqsien dly found for B1: ( 0, 14, 10)
858 00:22:10.436950 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
859 00:22:10.440485 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 00:22:10.440561
861 00:22:10.444124 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 00:22:10.450343 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 00:22:10.450427 [Gating] SW calibration Done
864 00:22:10.454096 ==
865 00:22:10.454173 Dram Type= 6, Freq= 0, CH_0, rank 0
866 00:22:10.460537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 00:22:10.460627 ==
868 00:22:10.460688 RX Vref Scan: 0
869 00:22:10.460772
870 00:22:10.463761 RX Vref 0 -> 0, step: 1
871 00:22:10.463858
872 00:22:10.467409 RX Delay -130 -> 252, step: 16
873 00:22:10.470563 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 00:22:10.473696 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 00:22:10.477421 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 00:22:10.484090 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 00:22:10.487220 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 00:22:10.490583 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 00:22:10.494065 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
880 00:22:10.497355 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 00:22:10.504143 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 00:22:10.507574 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 00:22:10.510840 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 00:22:10.513801 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 00:22:10.517006 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 00:22:10.524052 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 00:22:10.527302 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 00:22:10.530539 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 00:22:10.530625 ==
890 00:22:10.534193 Dram Type= 6, Freq= 0, CH_0, rank 0
891 00:22:10.537363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 00:22:10.537448 ==
893 00:22:10.541053 DQS Delay:
894 00:22:10.541146 DQS0 = 0, DQS1 = 0
895 00:22:10.543880 DQM Delay:
896 00:22:10.543949 DQM0 = 85, DQM1 = 78
897 00:22:10.544004 DQ Delay:
898 00:22:10.547092 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 00:22:10.550588 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
900 00:22:10.554191 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
901 00:22:10.557337 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 00:22:10.557403
903 00:22:10.557458
904 00:22:10.557537 ==
905 00:22:10.560883 Dram Type= 6, Freq= 0, CH_0, rank 0
906 00:22:10.567679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 00:22:10.567747 ==
908 00:22:10.567803
909 00:22:10.567855
910 00:22:10.567906 TX Vref Scan disable
911 00:22:10.571284 == TX Byte 0 ==
912 00:22:10.574401 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
913 00:22:10.578125 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
914 00:22:10.581279 == TX Byte 1 ==
915 00:22:10.584349 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
916 00:22:10.587948 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
917 00:22:10.591155 ==
918 00:22:10.594192 Dram Type= 6, Freq= 0, CH_0, rank 0
919 00:22:10.597534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 00:22:10.597610 ==
921 00:22:10.610192 TX Vref=22, minBit 7, minWin=26, winSum=434
922 00:22:10.613638 TX Vref=24, minBit 0, minWin=27, winSum=439
923 00:22:10.616892 TX Vref=26, minBit 0, minWin=27, winSum=446
924 00:22:10.620229 TX Vref=28, minBit 5, minWin=27, winSum=452
925 00:22:10.623297 TX Vref=30, minBit 9, minWin=27, winSum=453
926 00:22:10.627134 TX Vref=32, minBit 3, minWin=27, winSum=449
927 00:22:10.633854 [TxChooseVref] Worse bit 9, Min win 27, Win sum 453, Final Vref 30
928 00:22:10.633953
929 00:22:10.636976 Final TX Range 1 Vref 30
930 00:22:10.637052
931 00:22:10.637109 ==
932 00:22:10.640673 Dram Type= 6, Freq= 0, CH_0, rank 0
933 00:22:10.643691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 00:22:10.643792 ==
935 00:22:10.643877
936 00:22:10.643960
937 00:22:10.647339 TX Vref Scan disable
938 00:22:10.650211 == TX Byte 0 ==
939 00:22:10.653545 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
940 00:22:10.657283 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
941 00:22:10.660344 == TX Byte 1 ==
942 00:22:10.663905 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
943 00:22:10.666973 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
944 00:22:10.667042
945 00:22:10.670630 [DATLAT]
946 00:22:10.670700 Freq=800, CH0 RK0
947 00:22:10.670756
948 00:22:10.673559 DATLAT Default: 0xa
949 00:22:10.673620 0, 0xFFFF, sum = 0
950 00:22:10.677348 1, 0xFFFF, sum = 0
951 00:22:10.677410 2, 0xFFFF, sum = 0
952 00:22:10.680422 3, 0xFFFF, sum = 0
953 00:22:10.680503 4, 0xFFFF, sum = 0
954 00:22:10.684096 5, 0xFFFF, sum = 0
955 00:22:10.684175 6, 0xFFFF, sum = 0
956 00:22:10.687466 7, 0xFFFF, sum = 0
957 00:22:10.687568 8, 0xFFFF, sum = 0
958 00:22:10.690366 9, 0x0, sum = 1
959 00:22:10.690442 10, 0x0, sum = 2
960 00:22:10.693891 11, 0x0, sum = 3
961 00:22:10.694014 12, 0x0, sum = 4
962 00:22:10.697597 best_step = 10
963 00:22:10.697673
964 00:22:10.697731 ==
965 00:22:10.700805 Dram Type= 6, Freq= 0, CH_0, rank 0
966 00:22:10.703835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 00:22:10.703916 ==
968 00:22:10.707438 RX Vref Scan: 1
969 00:22:10.707517
970 00:22:10.707575 Set Vref Range= 32 -> 127
971 00:22:10.707629
972 00:22:10.710442 RX Vref 32 -> 127, step: 1
973 00:22:10.710517
974 00:22:10.713654 RX Delay -95 -> 252, step: 8
975 00:22:10.713728
976 00:22:10.717312 Set Vref, RX VrefLevel [Byte0]: 32
977 00:22:10.720782 [Byte1]: 32
978 00:22:10.720878
979 00:22:10.724055 Set Vref, RX VrefLevel [Byte0]: 33
980 00:22:10.727682 [Byte1]: 33
981 00:22:10.727752
982 00:22:10.730660 Set Vref, RX VrefLevel [Byte0]: 34
983 00:22:10.734210 [Byte1]: 34
984 00:22:10.738197
985 00:22:10.738271 Set Vref, RX VrefLevel [Byte0]: 35
986 00:22:10.741240 [Byte1]: 35
987 00:22:10.745465
988 00:22:10.745542 Set Vref, RX VrefLevel [Byte0]: 36
989 00:22:10.748647 [Byte1]: 36
990 00:22:10.753401
991 00:22:10.753498 Set Vref, RX VrefLevel [Byte0]: 37
992 00:22:10.756468 [Byte1]: 37
993 00:22:10.761041
994 00:22:10.761114 Set Vref, RX VrefLevel [Byte0]: 38
995 00:22:10.764283 [Byte1]: 38
996 00:22:10.768141
997 00:22:10.768217 Set Vref, RX VrefLevel [Byte0]: 39
998 00:22:10.771700 [Byte1]: 39
999 00:22:10.776088
1000 00:22:10.776194 Set Vref, RX VrefLevel [Byte0]: 40
1001 00:22:10.779299 [Byte1]: 40
1002 00:22:10.783444
1003 00:22:10.783518 Set Vref, RX VrefLevel [Byte0]: 41
1004 00:22:10.787296 [Byte1]: 41
1005 00:22:10.791123
1006 00:22:10.791197 Set Vref, RX VrefLevel [Byte0]: 42
1007 00:22:10.794215 [Byte1]: 42
1008 00:22:10.798477
1009 00:22:10.798552 Set Vref, RX VrefLevel [Byte0]: 43
1010 00:22:10.802097 [Byte1]: 43
1011 00:22:10.806254
1012 00:22:10.806329 Set Vref, RX VrefLevel [Byte0]: 44
1013 00:22:10.809736 [Byte1]: 44
1014 00:22:10.813968
1015 00:22:10.814083 Set Vref, RX VrefLevel [Byte0]: 45
1016 00:22:10.817428 [Byte1]: 45
1017 00:22:10.821394
1018 00:22:10.821468 Set Vref, RX VrefLevel [Byte0]: 46
1019 00:22:10.824865 [Byte1]: 46
1020 00:22:10.829024
1021 00:22:10.829101 Set Vref, RX VrefLevel [Byte0]: 47
1022 00:22:10.832548 [Byte1]: 47
1023 00:22:10.836682
1024 00:22:10.836757 Set Vref, RX VrefLevel [Byte0]: 48
1025 00:22:10.840346 [Byte1]: 48
1026 00:22:10.844376
1027 00:22:10.844450 Set Vref, RX VrefLevel [Byte0]: 49
1028 00:22:10.847773 [Byte1]: 49
1029 00:22:10.851978
1030 00:22:10.852053 Set Vref, RX VrefLevel [Byte0]: 50
1031 00:22:10.855004 [Byte1]: 50
1032 00:22:10.859859
1033 00:22:10.859933 Set Vref, RX VrefLevel [Byte0]: 51
1034 00:22:10.862937 [Byte1]: 51
1035 00:22:10.867163
1036 00:22:10.867237 Set Vref, RX VrefLevel [Byte0]: 52
1037 00:22:10.870582 [Byte1]: 52
1038 00:22:10.874917
1039 00:22:10.874992 Set Vref, RX VrefLevel [Byte0]: 53
1040 00:22:10.877886 [Byte1]: 53
1041 00:22:10.882226
1042 00:22:10.882300 Set Vref, RX VrefLevel [Byte0]: 54
1043 00:22:10.885878 [Byte1]: 54
1044 00:22:10.890141
1045 00:22:10.890215 Set Vref, RX VrefLevel [Byte0]: 55
1046 00:22:10.893216 [Byte1]: 55
1047 00:22:10.897364
1048 00:22:10.897438 Set Vref, RX VrefLevel [Byte0]: 56
1049 00:22:10.901046 [Byte1]: 56
1050 00:22:10.905392
1051 00:22:10.905466 Set Vref, RX VrefLevel [Byte0]: 57
1052 00:22:10.908396 [Byte1]: 57
1053 00:22:10.912525
1054 00:22:10.912599 Set Vref, RX VrefLevel [Byte0]: 58
1055 00:22:10.916112 [Byte1]: 58
1056 00:22:10.920327
1057 00:22:10.920401 Set Vref, RX VrefLevel [Byte0]: 59
1058 00:22:10.923925 [Byte1]: 59
1059 00:22:10.928314
1060 00:22:10.928388 Set Vref, RX VrefLevel [Byte0]: 60
1061 00:22:10.931249 [Byte1]: 60
1062 00:22:10.935434
1063 00:22:10.935507 Set Vref, RX VrefLevel [Byte0]: 61
1064 00:22:10.939385 [Byte1]: 61
1065 00:22:10.943057
1066 00:22:10.943131 Set Vref, RX VrefLevel [Byte0]: 62
1067 00:22:10.946195 [Byte1]: 62
1068 00:22:10.950568
1069 00:22:10.950643 Set Vref, RX VrefLevel [Byte0]: 63
1070 00:22:10.954030 [Byte1]: 63
1071 00:22:10.958100
1072 00:22:10.958174 Set Vref, RX VrefLevel [Byte0]: 64
1073 00:22:10.961651 [Byte1]: 64
1074 00:22:10.965585
1075 00:22:10.965659 Set Vref, RX VrefLevel [Byte0]: 65
1076 00:22:10.969294 [Byte1]: 65
1077 00:22:10.973584
1078 00:22:10.973657 Set Vref, RX VrefLevel [Byte0]: 66
1079 00:22:10.976561 [Byte1]: 66
1080 00:22:10.981019
1081 00:22:10.981093 Set Vref, RX VrefLevel [Byte0]: 67
1082 00:22:10.984435 [Byte1]: 67
1083 00:22:10.988764
1084 00:22:10.988857 Set Vref, RX VrefLevel [Byte0]: 68
1085 00:22:10.991974 [Byte1]: 68
1086 00:22:10.996302
1087 00:22:10.996378 Set Vref, RX VrefLevel [Byte0]: 69
1088 00:22:10.999344 [Byte1]: 69
1089 00:22:11.003547
1090 00:22:11.003620 Set Vref, RX VrefLevel [Byte0]: 70
1091 00:22:11.007242 [Byte1]: 70
1092 00:22:11.011574
1093 00:22:11.011659 Set Vref, RX VrefLevel [Byte0]: 71
1094 00:22:11.014682 [Byte1]: 71
1095 00:22:11.018934
1096 00:22:11.019010 Set Vref, RX VrefLevel [Byte0]: 72
1097 00:22:11.022727 [Byte1]: 72
1098 00:22:11.026431
1099 00:22:11.026524 Set Vref, RX VrefLevel [Byte0]: 73
1100 00:22:11.029918 [Byte1]: 73
1101 00:22:11.034231
1102 00:22:11.034310 Set Vref, RX VrefLevel [Byte0]: 74
1103 00:22:11.037797 [Byte1]: 74
1104 00:22:11.041544
1105 00:22:11.041624 Set Vref, RX VrefLevel [Byte0]: 75
1106 00:22:11.045379 [Byte1]: 75
1107 00:22:11.049441
1108 00:22:11.049511 Set Vref, RX VrefLevel [Byte0]: 76
1109 00:22:11.052475 [Byte1]: 76
1110 00:22:11.056975
1111 00:22:11.057045 Set Vref, RX VrefLevel [Byte0]: 77
1112 00:22:11.060148 [Byte1]: 77
1113 00:22:11.064338
1114 00:22:11.064405 Set Vref, RX VrefLevel [Byte0]: 78
1115 00:22:11.068147 [Byte1]: 78
1116 00:22:11.071815
1117 00:22:11.075403 Final RX Vref Byte 0 = 61 to rank0
1118 00:22:11.075492 Final RX Vref Byte 1 = 63 to rank0
1119 00:22:11.078784 Final RX Vref Byte 0 = 61 to rank1
1120 00:22:11.082178 Final RX Vref Byte 1 = 63 to rank1==
1121 00:22:11.085236 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 00:22:11.091922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 00:22:11.092071 ==
1124 00:22:11.092135 DQS Delay:
1125 00:22:11.092247 DQS0 = 0, DQS1 = 0
1126 00:22:11.095263 DQM Delay:
1127 00:22:11.095371 DQM0 = 87, DQM1 = 79
1128 00:22:11.099155 DQ Delay:
1129 00:22:11.102340 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1130 00:22:11.102429 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =96
1131 00:22:11.105504 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1132 00:22:11.108627 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1133 00:22:11.112576
1134 00:22:11.112645
1135 00:22:11.118745 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1136 00:22:11.122177 CH0 RK0: MR19=606, MR18=2C14
1137 00:22:11.128820 CH0_RK0: MR19=0x606, MR18=0x2C14, DQSOSC=398, MR23=63, INC=93, DEC=62
1138 00:22:11.128900
1139 00:22:11.132456 ----->DramcWriteLeveling(PI) begin...
1140 00:22:11.132534 ==
1141 00:22:11.135462 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 00:22:11.139061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 00:22:11.139139 ==
1144 00:22:11.142533 Write leveling (Byte 0): 31 => 31
1145 00:22:11.146090 Write leveling (Byte 1): 30 => 30
1146 00:22:11.149194 DramcWriteLeveling(PI) end<-----
1147 00:22:11.149296
1148 00:22:11.149359 ==
1149 00:22:11.152259 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 00:22:11.156001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 00:22:11.156072 ==
1152 00:22:11.159165 [Gating] SW mode calibration
1153 00:22:11.165921 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 00:22:11.172944 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 00:22:11.176035 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 00:22:11.179221 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1157 00:22:11.182834 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 00:22:11.226981 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 00:22:11.227286 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 00:22:11.227388 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 00:22:11.227471 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 00:22:11.227615 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 00:22:11.227778 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 00:22:11.227865 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 00:22:11.227947 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 00:22:11.228038 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 00:22:11.228115 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 00:22:11.261475 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 00:22:11.262216 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 00:22:11.262500 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 00:22:11.262637 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 00:22:11.262699 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1173 00:22:11.262764 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1174 00:22:11.263471 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 00:22:11.266014 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 00:22:11.269796 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 00:22:11.272790 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 00:22:11.276466 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 00:22:11.279448 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 00:22:11.286528 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 00:22:11.289784 0 9 8 | B1->B0 | 2323 3030 | 1 0 | (1 1) (0 0)
1182 00:22:11.292793 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (1 1) (1 1)
1183 00:22:11.299619 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 00:22:11.303330 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 00:22:11.306456 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 00:22:11.312890 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 00:22:11.316321 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 00:22:11.319753 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 0) (1 0)
1189 00:22:11.326364 0 10 8 | B1->B0 | 3030 2525 | 0 0 | (0 1) (0 0)
1190 00:22:11.329660 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 00:22:11.333042 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 00:22:11.339688 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 00:22:11.342715 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 00:22:11.346335 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 00:22:11.349673 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 00:22:11.356253 0 11 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1197 00:22:11.359892 0 11 8 | B1->B0 | 2c2c 4040 | 0 1 | (0 0) (0 0)
1198 00:22:11.362941 0 11 12 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
1199 00:22:11.369978 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 00:22:11.373099 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 00:22:11.376841 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 00:22:11.383509 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 00:22:11.386516 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 00:22:11.389566 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 00:22:11.396412 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1206 00:22:11.399858 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 00:22:11.403473 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 00:22:11.410393 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 00:22:11.413360 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 00:22:11.416578 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 00:22:11.420198 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 00:22:11.426433 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 00:22:11.430119 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 00:22:11.433090 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 00:22:11.439888 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 00:22:11.443071 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 00:22:11.446845 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 00:22:11.453170 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 00:22:11.456893 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1220 00:22:11.460146 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1221 00:22:11.466897 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1222 00:22:11.466976 Total UI for P1: 0, mck2ui 16
1223 00:22:11.473494 best dqsien dly found for B0: ( 0, 14, 2)
1224 00:22:11.476498 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 00:22:11.480154 Total UI for P1: 0, mck2ui 16
1226 00:22:11.483117 best dqsien dly found for B1: ( 0, 14, 8)
1227 00:22:11.486833 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1228 00:22:11.489880 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1229 00:22:11.489960
1230 00:22:11.493475 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1231 00:22:11.496569 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 00:22:11.500209 [Gating] SW calibration Done
1233 00:22:11.500287 ==
1234 00:22:11.503640 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 00:22:11.506512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 00:22:11.506591 ==
1237 00:22:11.510210 RX Vref Scan: 0
1238 00:22:11.510317
1239 00:22:11.513380 RX Vref 0 -> 0, step: 1
1240 00:22:11.513456
1241 00:22:11.513513 RX Delay -130 -> 252, step: 16
1242 00:22:11.519975 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1243 00:22:11.523700 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1244 00:22:11.526811 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1245 00:22:11.529850 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1246 00:22:11.533564 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1247 00:22:11.540132 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1248 00:22:11.543563 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1249 00:22:11.546604 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1250 00:22:11.550143 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1251 00:22:11.553153 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1252 00:22:11.560104 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1253 00:22:11.563449 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1254 00:22:11.566744 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1255 00:22:11.570232 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1256 00:22:11.573466 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1257 00:22:11.580084 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1258 00:22:11.580160 ==
1259 00:22:11.583546 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 00:22:11.586713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 00:22:11.586791 ==
1262 00:22:11.586849 DQS Delay:
1263 00:22:11.590167 DQS0 = 0, DQS1 = 0
1264 00:22:11.590241 DQM Delay:
1265 00:22:11.593197 DQM0 = 86, DQM1 = 73
1266 00:22:11.593272 DQ Delay:
1267 00:22:11.596973 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1268 00:22:11.600053 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1269 00:22:11.603342 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1270 00:22:11.606873 DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85
1271 00:22:11.606948
1272 00:22:11.607005
1273 00:22:11.607057 ==
1274 00:22:11.609876 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 00:22:11.613634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 00:22:11.613711 ==
1277 00:22:11.616732
1278 00:22:11.616806
1279 00:22:11.616863 TX Vref Scan disable
1280 00:22:11.620243 == TX Byte 0 ==
1281 00:22:11.623184 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1282 00:22:11.627387 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1283 00:22:11.629836 == TX Byte 1 ==
1284 00:22:11.633581 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1285 00:22:11.637369 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1286 00:22:11.637487 ==
1287 00:22:11.640149 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 00:22:11.647039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 00:22:11.647125 ==
1290 00:22:11.658629 TX Vref=22, minBit 3, minWin=27, winSum=445
1291 00:22:11.661652 TX Vref=24, minBit 9, minWin=27, winSum=449
1292 00:22:11.665210 TX Vref=26, minBit 9, minWin=27, winSum=452
1293 00:22:11.668547 TX Vref=28, minBit 5, minWin=28, winSum=459
1294 00:22:11.671918 TX Vref=30, minBit 5, minWin=28, winSum=460
1295 00:22:11.678472 TX Vref=32, minBit 12, minWin=27, winSum=457
1296 00:22:11.681916 [TxChooseVref] Worse bit 5, Min win 28, Win sum 460, Final Vref 30
1297 00:22:11.682040
1298 00:22:11.685033 Final TX Range 1 Vref 30
1299 00:22:11.685132
1300 00:22:11.685257 ==
1301 00:22:11.688674 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 00:22:11.692024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 00:22:11.692144 ==
1304 00:22:11.694898
1305 00:22:11.694999
1306 00:22:11.695085 TX Vref Scan disable
1307 00:22:11.698680 == TX Byte 0 ==
1308 00:22:11.701721 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1309 00:22:11.708531 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1310 00:22:11.708607 == TX Byte 1 ==
1311 00:22:11.711720 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1312 00:22:11.718854 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1313 00:22:11.718931
1314 00:22:11.718991 [DATLAT]
1315 00:22:11.719046 Freq=800, CH0 RK1
1316 00:22:11.719099
1317 00:22:11.721914 DATLAT Default: 0xa
1318 00:22:11.722005 0, 0xFFFF, sum = 0
1319 00:22:11.724842 1, 0xFFFF, sum = 0
1320 00:22:11.724945 2, 0xFFFF, sum = 0
1321 00:22:11.728589 3, 0xFFFF, sum = 0
1322 00:22:11.728684 4, 0xFFFF, sum = 0
1323 00:22:11.731870 5, 0xFFFF, sum = 0
1324 00:22:11.735047 6, 0xFFFF, sum = 0
1325 00:22:11.735112 7, 0xFFFF, sum = 0
1326 00:22:11.738718 8, 0xFFFF, sum = 0
1327 00:22:11.738782 9, 0x0, sum = 1
1328 00:22:11.738836 10, 0x0, sum = 2
1329 00:22:11.741899 11, 0x0, sum = 3
1330 00:22:11.741993 12, 0x0, sum = 4
1331 00:22:11.744955 best_step = 10
1332 00:22:11.745022
1333 00:22:11.745083 ==
1334 00:22:11.748366 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 00:22:11.752055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 00:22:11.752143 ==
1337 00:22:11.755112 RX Vref Scan: 0
1338 00:22:11.755179
1339 00:22:11.755244 RX Vref 0 -> 0, step: 1
1340 00:22:11.755310
1341 00:22:11.758342 RX Delay -95 -> 252, step: 8
1342 00:22:11.765043 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1343 00:22:11.768691 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1344 00:22:11.771791 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1345 00:22:11.775415 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1346 00:22:11.778280 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1347 00:22:11.785275 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1348 00:22:11.788295 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1349 00:22:11.792138 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1350 00:22:11.795314 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1351 00:22:11.798459 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1352 00:22:11.805446 iDelay=209, Bit 10, Center 76 (-31 ~ 184) 216
1353 00:22:11.808277 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1354 00:22:11.811678 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1355 00:22:11.815608 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1356 00:22:11.818760 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1357 00:22:11.825219 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1358 00:22:11.825302 ==
1359 00:22:11.828655 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 00:22:11.832248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 00:22:11.832326 ==
1362 00:22:11.832387 DQS Delay:
1363 00:22:11.835298 DQS0 = 0, DQS1 = 0
1364 00:22:11.835385 DQM Delay:
1365 00:22:11.838431 DQM0 = 87, DQM1 = 78
1366 00:22:11.838516 DQ Delay:
1367 00:22:11.842234 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1368 00:22:11.845417 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1369 00:22:11.848363 DQ8 =68, DQ9 =68, DQ10 =76, DQ11 =72
1370 00:22:11.852193 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1371 00:22:11.852289
1372 00:22:11.852379
1373 00:22:11.858776 [DQSOSCAuto] RK1, (LSB)MR18= 0x341d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1374 00:22:11.862013 CH0 RK1: MR19=606, MR18=341D
1375 00:22:11.868672 CH0_RK1: MR19=0x606, MR18=0x341D, DQSOSC=396, MR23=63, INC=94, DEC=62
1376 00:22:11.872005 [RxdqsGatingPostProcess] freq 800
1377 00:22:11.878793 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 00:22:11.878871 Pre-setting of DQS Precalculation
1379 00:22:11.885515 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 00:22:11.885596 ==
1381 00:22:11.888468 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 00:22:11.892044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 00:22:11.892133 ==
1384 00:22:11.899099 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 00:22:11.905280 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 00:22:11.913260 [CA 0] Center 36 (6~66) winsize 61
1387 00:22:11.916705 [CA 1] Center 36 (6~66) winsize 61
1388 00:22:11.920471 [CA 2] Center 34 (4~65) winsize 62
1389 00:22:11.923243 [CA 3] Center 33 (3~64) winsize 62
1390 00:22:11.926950 [CA 4] Center 34 (4~65) winsize 62
1391 00:22:11.929930 [CA 5] Center 33 (3~64) winsize 62
1392 00:22:11.930027
1393 00:22:11.933446 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1394 00:22:11.933518
1395 00:22:11.937052 [CATrainingPosCal] consider 1 rank data
1396 00:22:11.940025 u2DelayCellTimex100 = 270/100 ps
1397 00:22:11.943707 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1398 00:22:11.946643 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1399 00:22:11.953536 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1400 00:22:11.956691 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1401 00:22:11.960297 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1402 00:22:11.963382 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1403 00:22:11.963477
1404 00:22:11.966467 CA PerBit enable=1, Macro0, CA PI delay=33
1405 00:22:11.966544
1406 00:22:11.970406 [CBTSetCACLKResult] CA Dly = 33
1407 00:22:11.970483 CS Dly: 5 (0~36)
1408 00:22:11.970542 ==
1409 00:22:11.973877 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 00:22:11.979979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 00:22:11.980069 ==
1412 00:22:11.983696 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 00:22:11.989692 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 00:22:11.999386 [CA 0] Center 36 (6~66) winsize 61
1415 00:22:12.002905 [CA 1] Center 36 (6~66) winsize 61
1416 00:22:12.006273 [CA 2] Center 34 (4~64) winsize 61
1417 00:22:12.009308 [CA 3] Center 33 (3~64) winsize 62
1418 00:22:12.013012 [CA 4] Center 34 (4~65) winsize 62
1419 00:22:12.015944 [CA 5] Center 33 (3~64) winsize 62
1420 00:22:12.016022
1421 00:22:12.019683 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1422 00:22:12.019768
1423 00:22:12.022639 [CATrainingPosCal] consider 2 rank data
1424 00:22:12.026283 u2DelayCellTimex100 = 270/100 ps
1425 00:22:12.029229 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1426 00:22:12.033104 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1427 00:22:12.039716 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1428 00:22:12.042688 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1429 00:22:12.046154 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1430 00:22:12.049604 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1431 00:22:12.049707
1432 00:22:12.052749 CA PerBit enable=1, Macro0, CA PI delay=33
1433 00:22:12.052828
1434 00:22:12.056398 [CBTSetCACLKResult] CA Dly = 33
1435 00:22:12.056475 CS Dly: 5 (0~36)
1436 00:22:12.056536
1437 00:22:12.059381 ----->DramcWriteLeveling(PI) begin...
1438 00:22:12.059460 ==
1439 00:22:12.062626 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 00:22:12.069304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 00:22:12.069391 ==
1442 00:22:12.073057 Write leveling (Byte 0): 27 => 27
1443 00:22:12.075968 Write leveling (Byte 1): 28 => 28
1444 00:22:12.076045 DramcWriteLeveling(PI) end<-----
1445 00:22:12.079751
1446 00:22:12.079828 ==
1447 00:22:12.082962 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 00:22:12.086106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 00:22:12.086189 ==
1450 00:22:12.089321 [Gating] SW mode calibration
1451 00:22:12.096567 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 00:22:12.099780 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 00:22:12.106668 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 00:22:12.109633 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1455 00:22:12.113133 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1456 00:22:12.119399 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 00:22:12.122927 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 00:22:12.125917 0 6 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1459 00:22:12.132536 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 00:22:12.136260 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 00:22:12.139308 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 00:22:12.146127 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 00:22:12.149233 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 00:22:12.152976 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 00:22:12.159359 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1466 00:22:12.162898 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1467 00:22:12.166201 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1468 00:22:12.172776 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 00:22:12.176197 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 00:22:12.179256 0 8 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1471 00:22:12.183204 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1472 00:22:12.189958 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 00:22:12.192964 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 00:22:12.196125 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 00:22:12.203317 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 00:22:12.206195 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 00:22:12.209418 0 9 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1478 00:22:12.216329 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 00:22:12.219789 0 9 8 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
1480 00:22:12.223190 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 00:22:12.229645 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 00:22:12.233189 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 00:22:12.236682 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 00:22:12.242789 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 00:22:12.246345 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1486 00:22:12.249539 0 10 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1487 00:22:12.253144 0 10 8 | B1->B0 | 2727 2e2e | 0 0 | (1 0) (1 1)
1488 00:22:12.259881 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 00:22:12.262902 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 00:22:12.266648 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 00:22:12.273481 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 00:22:12.276492 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 00:22:12.280042 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 00:22:12.286380 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1495 00:22:12.290368 0 11 8 | B1->B0 | 3838 3a3a | 0 0 | (0 0) (1 1)
1496 00:22:12.293264 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 00:22:12.300076 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 00:22:12.303183 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 00:22:12.306744 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 00:22:12.310351 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 00:22:12.317229 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 00:22:12.320189 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 00:22:12.323798 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1504 00:22:12.330231 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1505 00:22:12.333720 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 00:22:12.336625 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 00:22:12.343414 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 00:22:12.346848 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 00:22:12.349976 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 00:22:12.356574 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 00:22:12.360392 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 00:22:12.363488 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 00:22:12.370096 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 00:22:12.373702 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 00:22:12.376674 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 00:22:12.383517 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 00:22:12.387201 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 00:22:12.390223 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1519 00:22:12.393906 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1520 00:22:12.400297 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 00:22:12.403608 Total UI for P1: 0, mck2ui 16
1522 00:22:12.406918 best dqsien dly found for B0: ( 0, 14, 6)
1523 00:22:12.410269 Total UI for P1: 0, mck2ui 16
1524 00:22:12.413619 best dqsien dly found for B1: ( 0, 14, 8)
1525 00:22:12.417292 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1526 00:22:12.420359 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1527 00:22:12.420439
1528 00:22:12.424036 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1529 00:22:12.427146 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1530 00:22:12.430230 [Gating] SW calibration Done
1531 00:22:12.430309 ==
1532 00:22:12.433891 Dram Type= 6, Freq= 0, CH_1, rank 0
1533 00:22:12.436853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1534 00:22:12.436985 ==
1535 00:22:12.440393 RX Vref Scan: 0
1536 00:22:12.440471
1537 00:22:12.440548 RX Vref 0 -> 0, step: 1
1538 00:22:12.440621
1539 00:22:12.443790 RX Delay -130 -> 252, step: 16
1540 00:22:12.447252 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1541 00:22:12.453733 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1542 00:22:12.456799 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1543 00:22:12.460370 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1544 00:22:12.464076 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1545 00:22:12.467124 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1546 00:22:12.473764 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1547 00:22:12.476811 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1548 00:22:12.480355 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1549 00:22:12.483481 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1550 00:22:12.487120 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1551 00:22:12.493695 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1552 00:22:12.496817 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1553 00:22:12.500396 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1554 00:22:12.503485 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1555 00:22:12.507121 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1556 00:22:12.510641 ==
1557 00:22:12.513603 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 00:22:12.517307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 00:22:12.517385 ==
1560 00:22:12.517444 DQS Delay:
1561 00:22:12.520254 DQS0 = 0, DQS1 = 0
1562 00:22:12.520330 DQM Delay:
1563 00:22:12.523820 DQM0 = 83, DQM1 = 77
1564 00:22:12.523896 DQ Delay:
1565 00:22:12.527228 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1566 00:22:12.530386 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1567 00:22:12.534147 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1568 00:22:12.537166 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1569 00:22:12.537292
1570 00:22:12.537437
1571 00:22:12.537538 ==
1572 00:22:12.540298 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 00:22:12.544425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 00:22:12.544588 ==
1575 00:22:12.544649
1576 00:22:12.544747
1577 00:22:12.547191 TX Vref Scan disable
1578 00:22:12.550334 == TX Byte 0 ==
1579 00:22:12.553879 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1580 00:22:12.557334 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1581 00:22:12.560421 == TX Byte 1 ==
1582 00:22:12.563914 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1583 00:22:12.567140 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1584 00:22:12.567216 ==
1585 00:22:12.570589 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 00:22:12.573642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 00:22:12.573718 ==
1588 00:22:12.588267 TX Vref=22, minBit 0, minWin=27, winSum=440
1589 00:22:12.591345 TX Vref=24, minBit 4, minWin=27, winSum=444
1590 00:22:12.594897 TX Vref=26, minBit 8, minWin=27, winSum=446
1591 00:22:12.597930 TX Vref=28, minBit 15, minWin=27, winSum=450
1592 00:22:12.601583 TX Vref=30, minBit 0, minWin=28, winSum=453
1593 00:22:12.608356 TX Vref=32, minBit 11, minWin=27, winSum=453
1594 00:22:12.611336 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 30
1595 00:22:12.611412
1596 00:22:12.614977 Final TX Range 1 Vref 30
1597 00:22:12.615053
1598 00:22:12.615111 ==
1599 00:22:12.618249 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 00:22:12.621443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 00:22:12.621519 ==
1602 00:22:12.621576
1603 00:22:12.624533
1604 00:22:12.624608 TX Vref Scan disable
1605 00:22:12.628249 == TX Byte 0 ==
1606 00:22:12.631277 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1607 00:22:12.634959 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1608 00:22:12.637813 == TX Byte 1 ==
1609 00:22:12.641363 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1610 00:22:12.647857 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1611 00:22:12.647935
1612 00:22:12.648012 [DATLAT]
1613 00:22:12.648084 Freq=800, CH1 RK0
1614 00:22:12.648155
1615 00:22:12.651191 DATLAT Default: 0xa
1616 00:22:12.651269 0, 0xFFFF, sum = 0
1617 00:22:12.654829 1, 0xFFFF, sum = 0
1618 00:22:12.654908 2, 0xFFFF, sum = 0
1619 00:22:12.658038 3, 0xFFFF, sum = 0
1620 00:22:12.658130 4, 0xFFFF, sum = 0
1621 00:22:12.661262 5, 0xFFFF, sum = 0
1622 00:22:12.664743 6, 0xFFFF, sum = 0
1623 00:22:12.664823 7, 0xFFFF, sum = 0
1624 00:22:12.667893 8, 0xFFFF, sum = 0
1625 00:22:12.667982 9, 0x0, sum = 1
1626 00:22:12.668061 10, 0x0, sum = 2
1627 00:22:12.671733 11, 0x0, sum = 3
1628 00:22:12.671813 12, 0x0, sum = 4
1629 00:22:12.674778 best_step = 10
1630 00:22:12.674857
1631 00:22:12.674950 ==
1632 00:22:12.678345 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 00:22:12.681370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 00:22:12.681449 ==
1635 00:22:12.684520 RX Vref Scan: 1
1636 00:22:12.684598
1637 00:22:12.684674 Set Vref Range= 32 -> 127
1638 00:22:12.687996
1639 00:22:12.688075 RX Vref 32 -> 127, step: 1
1640 00:22:12.688152
1641 00:22:12.691293 RX Delay -95 -> 252, step: 8
1642 00:22:12.691371
1643 00:22:12.694896 Set Vref, RX VrefLevel [Byte0]: 32
1644 00:22:12.697920 [Byte1]: 32
1645 00:22:12.698088
1646 00:22:12.701580 Set Vref, RX VrefLevel [Byte0]: 33
1647 00:22:12.704570 [Byte1]: 33
1648 00:22:12.708294
1649 00:22:12.708372 Set Vref, RX VrefLevel [Byte0]: 34
1650 00:22:12.711893 [Byte1]: 34
1651 00:22:12.716231
1652 00:22:12.716309 Set Vref, RX VrefLevel [Byte0]: 35
1653 00:22:12.719116 [Byte1]: 35
1654 00:22:12.723758
1655 00:22:12.723833 Set Vref, RX VrefLevel [Byte0]: 36
1656 00:22:12.726771 [Byte1]: 36
1657 00:22:12.731141
1658 00:22:12.731216 Set Vref, RX VrefLevel [Byte0]: 37
1659 00:22:12.734949 [Byte1]: 37
1660 00:22:12.738970
1661 00:22:12.739045 Set Vref, RX VrefLevel [Byte0]: 38
1662 00:22:12.741901 [Byte1]: 38
1663 00:22:12.746239
1664 00:22:12.746316 Set Vref, RX VrefLevel [Byte0]: 39
1665 00:22:12.749873 [Byte1]: 39
1666 00:22:12.754456
1667 00:22:12.754531 Set Vref, RX VrefLevel [Byte0]: 40
1668 00:22:12.757403 [Byte1]: 40
1669 00:22:12.761688
1670 00:22:12.761786 Set Vref, RX VrefLevel [Byte0]: 41
1671 00:22:12.765137 [Byte1]: 41
1672 00:22:12.769443
1673 00:22:12.769507 Set Vref, RX VrefLevel [Byte0]: 42
1674 00:22:12.772292 [Byte1]: 42
1675 00:22:12.776797
1676 00:22:12.776893 Set Vref, RX VrefLevel [Byte0]: 43
1677 00:22:12.780056 [Byte1]: 43
1678 00:22:12.784388
1679 00:22:12.784463 Set Vref, RX VrefLevel [Byte0]: 44
1680 00:22:12.787842 [Byte1]: 44
1681 00:22:12.791822
1682 00:22:12.791898 Set Vref, RX VrefLevel [Byte0]: 45
1683 00:22:12.795460 [Byte1]: 45
1684 00:22:12.799848
1685 00:22:12.799928 Set Vref, RX VrefLevel [Byte0]: 46
1686 00:22:12.802906 [Byte1]: 46
1687 00:22:12.807206
1688 00:22:12.807284 Set Vref, RX VrefLevel [Byte0]: 47
1689 00:22:12.810367 [Byte1]: 47
1690 00:22:12.814607
1691 00:22:12.814686 Set Vref, RX VrefLevel [Byte0]: 48
1692 00:22:12.818324 [Byte1]: 48
1693 00:22:12.822558
1694 00:22:12.822633 Set Vref, RX VrefLevel [Byte0]: 49
1695 00:22:12.825531 [Byte1]: 49
1696 00:22:12.829656
1697 00:22:12.829732 Set Vref, RX VrefLevel [Byte0]: 50
1698 00:22:12.833451 [Byte1]: 50
1699 00:22:12.837796
1700 00:22:12.837885 Set Vref, RX VrefLevel [Byte0]: 51
1701 00:22:12.840778 [Byte1]: 51
1702 00:22:12.845350
1703 00:22:12.845432 Set Vref, RX VrefLevel [Byte0]: 52
1704 00:22:12.848567 [Byte1]: 52
1705 00:22:12.852778
1706 00:22:12.852846 Set Vref, RX VrefLevel [Byte0]: 53
1707 00:22:12.855794 [Byte1]: 53
1708 00:22:12.860189
1709 00:22:12.860264 Set Vref, RX VrefLevel [Byte0]: 54
1710 00:22:12.863774 [Byte1]: 54
1711 00:22:12.868011
1712 00:22:12.868087 Set Vref, RX VrefLevel [Byte0]: 55
1713 00:22:12.871162 [Byte1]: 55
1714 00:22:12.875356
1715 00:22:12.875432 Set Vref, RX VrefLevel [Byte0]: 56
1716 00:22:12.878767 [Byte1]: 56
1717 00:22:12.883469
1718 00:22:12.883544 Set Vref, RX VrefLevel [Byte0]: 57
1719 00:22:12.886349 [Byte1]: 57
1720 00:22:12.890585
1721 00:22:12.890679 Set Vref, RX VrefLevel [Byte0]: 58
1722 00:22:12.894207 [Byte1]: 58
1723 00:22:12.898158
1724 00:22:12.898233 Set Vref, RX VrefLevel [Byte0]: 59
1725 00:22:12.901431 [Byte1]: 59
1726 00:22:12.905908
1727 00:22:12.906010 Set Vref, RX VrefLevel [Byte0]: 60
1728 00:22:12.909055 [Byte1]: 60
1729 00:22:12.913394
1730 00:22:12.913493 Set Vref, RX VrefLevel [Byte0]: 61
1731 00:22:12.916664 [Byte1]: 61
1732 00:22:12.921392
1733 00:22:12.921491 Set Vref, RX VrefLevel [Byte0]: 62
1734 00:22:12.924521 [Byte1]: 62
1735 00:22:12.928652
1736 00:22:12.928751 Set Vref, RX VrefLevel [Byte0]: 63
1737 00:22:12.932203 [Byte1]: 63
1738 00:22:12.936352
1739 00:22:12.936483 Set Vref, RX VrefLevel [Byte0]: 64
1740 00:22:12.939426 [Byte1]: 64
1741 00:22:12.943857
1742 00:22:12.943933 Set Vref, RX VrefLevel [Byte0]: 65
1743 00:22:12.947381 [Byte1]: 65
1744 00:22:12.951599
1745 00:22:12.951676 Set Vref, RX VrefLevel [Byte0]: 66
1746 00:22:12.954730 [Byte1]: 66
1747 00:22:12.958926
1748 00:22:12.959001 Set Vref, RX VrefLevel [Byte0]: 67
1749 00:22:12.962537 [Byte1]: 67
1750 00:22:12.966859
1751 00:22:12.966939 Set Vref, RX VrefLevel [Byte0]: 68
1752 00:22:12.969839 [Byte1]: 68
1753 00:22:12.974073
1754 00:22:12.974146 Set Vref, RX VrefLevel [Byte0]: 69
1755 00:22:12.977711 [Byte1]: 69
1756 00:22:12.981947
1757 00:22:12.982051 Set Vref, RX VrefLevel [Byte0]: 70
1758 00:22:12.985215 [Byte1]: 70
1759 00:22:12.989755
1760 00:22:12.989829 Set Vref, RX VrefLevel [Byte0]: 71
1761 00:22:12.992798 [Byte1]: 71
1762 00:22:12.997126
1763 00:22:12.997201 Set Vref, RX VrefLevel [Byte0]: 72
1764 00:22:13.000563 [Byte1]: 72
1765 00:22:13.004494
1766 00:22:13.004570 Set Vref, RX VrefLevel [Byte0]: 73
1767 00:22:13.008233 [Byte1]: 73
1768 00:22:13.012460
1769 00:22:13.012527 Set Vref, RX VrefLevel [Byte0]: 74
1770 00:22:13.015407 [Byte1]: 74
1771 00:22:13.019787
1772 00:22:13.019860 Set Vref, RX VrefLevel [Byte0]: 75
1773 00:22:13.022951 [Byte1]: 75
1774 00:22:13.027803
1775 00:22:13.027881 Set Vref, RX VrefLevel [Byte0]: 76
1776 00:22:13.030752 [Byte1]: 76
1777 00:22:13.035404
1778 00:22:13.035504 Set Vref, RX VrefLevel [Byte0]: 77
1779 00:22:13.038138 [Byte1]: 77
1780 00:22:13.042942
1781 00:22:13.043009 Final RX Vref Byte 0 = 61 to rank0
1782 00:22:13.046185 Final RX Vref Byte 1 = 57 to rank0
1783 00:22:13.049288 Final RX Vref Byte 0 = 61 to rank1
1784 00:22:13.052814 Final RX Vref Byte 1 = 57 to rank1==
1785 00:22:13.056269 Dram Type= 6, Freq= 0, CH_1, rank 0
1786 00:22:13.059183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1787 00:22:13.062894 ==
1788 00:22:13.062972 DQS Delay:
1789 00:22:13.063049 DQS0 = 0, DQS1 = 0
1790 00:22:13.065948 DQM Delay:
1791 00:22:13.066071 DQM0 = 82, DQM1 = 74
1792 00:22:13.069572 DQ Delay:
1793 00:22:13.072714 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =84
1794 00:22:13.072789 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =76
1795 00:22:13.076378 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1796 00:22:13.079365 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1797 00:22:13.082958
1798 00:22:13.083032
1799 00:22:13.089136 [DQSOSCAuto] RK0, (LSB)MR18= 0x3106, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
1800 00:22:13.092873 CH1 RK0: MR19=606, MR18=3106
1801 00:22:13.099371 CH1_RK0: MR19=0x606, MR18=0x3106, DQSOSC=397, MR23=63, INC=93, DEC=62
1802 00:22:13.099470
1803 00:22:13.102736 ----->DramcWriteLeveling(PI) begin...
1804 00:22:13.102819 ==
1805 00:22:13.105892 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 00:22:13.109236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1807 00:22:13.109305 ==
1808 00:22:13.112792 Write leveling (Byte 0): 28 => 28
1809 00:22:13.116306 Write leveling (Byte 1): 28 => 28
1810 00:22:13.119364 DramcWriteLeveling(PI) end<-----
1811 00:22:13.119439
1812 00:22:13.119497 ==
1813 00:22:13.122999 Dram Type= 6, Freq= 0, CH_1, rank 1
1814 00:22:13.126157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1815 00:22:13.126234 ==
1816 00:22:13.129532 [Gating] SW mode calibration
1817 00:22:13.136189 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1818 00:22:13.142652 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1819 00:22:13.145864 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1820 00:22:13.149269 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
1821 00:22:13.155906 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 00:22:13.159431 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 00:22:13.162710 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 00:22:13.169514 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 00:22:13.172516 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 00:22:13.176190 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 00:22:13.183085 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 00:22:13.186025 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 00:22:13.189302 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 00:22:13.192813 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 00:22:13.199427 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 00:22:13.203170 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 00:22:13.205890 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 00:22:13.212803 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 00:22:13.216111 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1836 00:22:13.219773 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1837 00:22:13.226507 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 00:22:13.229432 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 00:22:13.232644 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 00:22:13.239259 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 00:22:13.242540 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 00:22:13.246453 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 00:22:13.252590 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 00:22:13.256191 0 9 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1845 00:22:13.259494 0 9 8 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
1846 00:22:13.265968 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 00:22:13.269512 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 00:22:13.272574 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 00:22:13.279311 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 00:22:13.282764 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 00:22:13.286434 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
1852 00:22:13.289565 0 10 4 | B1->B0 | 3232 2727 | 0 0 | (0 1) (1 0)
1853 00:22:13.296281 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1854 00:22:13.299447 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 00:22:13.303057 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 00:22:13.309686 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 00:22:13.312551 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 00:22:13.316117 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 00:22:13.322658 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1860 00:22:13.326110 0 11 4 | B1->B0 | 2a2a 3939 | 0 1 | (0 0) (0 0)
1861 00:22:13.329518 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
1862 00:22:13.336271 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 00:22:13.339335 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 00:22:13.343015 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 00:22:13.349177 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 00:22:13.352648 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 00:22:13.355873 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 00:22:13.362964 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1869 00:22:13.366394 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1870 00:22:13.369148 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 00:22:13.376004 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 00:22:13.379432 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 00:22:13.382976 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 00:22:13.386018 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 00:22:13.392854 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 00:22:13.396476 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 00:22:13.399590 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 00:22:13.406101 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 00:22:13.409840 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 00:22:13.413123 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 00:22:13.419504 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 00:22:13.422946 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 00:22:13.425956 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1884 00:22:13.432617 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1885 00:22:13.436172 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 00:22:13.439314 Total UI for P1: 0, mck2ui 16
1887 00:22:13.442807 best dqsien dly found for B0: ( 0, 14, 2)
1888 00:22:13.445929 Total UI for P1: 0, mck2ui 16
1889 00:22:13.449595 best dqsien dly found for B1: ( 0, 14, 6)
1890 00:22:13.452519 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1891 00:22:13.456249 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1892 00:22:13.456349
1893 00:22:13.459191 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1894 00:22:13.462846 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1895 00:22:13.466100 [Gating] SW calibration Done
1896 00:22:13.466200 ==
1897 00:22:13.468909 Dram Type= 6, Freq= 0, CH_1, rank 1
1898 00:22:13.472429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1899 00:22:13.472540 ==
1900 00:22:13.475857 RX Vref Scan: 0
1901 00:22:13.475956
1902 00:22:13.478804 RX Vref 0 -> 0, step: 1
1903 00:22:13.478903
1904 00:22:13.481996 RX Delay -130 -> 252, step: 16
1905 00:22:13.485643 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1906 00:22:13.488886 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1907 00:22:13.492394 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1908 00:22:13.495391 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1909 00:22:13.502329 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1910 00:22:13.505774 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1911 00:22:13.508843 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1912 00:22:13.512439 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1913 00:22:13.515684 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1914 00:22:13.522201 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1915 00:22:13.525627 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1916 00:22:13.528546 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1917 00:22:13.532193 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1918 00:22:13.535272 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1919 00:22:13.541851 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1920 00:22:13.545243 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1921 00:22:13.545349 ==
1922 00:22:13.548334 Dram Type= 6, Freq= 0, CH_1, rank 1
1923 00:22:13.552020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1924 00:22:13.552096 ==
1925 00:22:13.555162 DQS Delay:
1926 00:22:13.555235 DQS0 = 0, DQS1 = 0
1927 00:22:13.555296 DQM Delay:
1928 00:22:13.558799 DQM0 = 80, DQM1 = 77
1929 00:22:13.558863 DQ Delay:
1930 00:22:13.561870 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1931 00:22:13.565613 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =69
1932 00:22:13.568515 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1933 00:22:13.571947 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1934 00:22:13.572023
1935 00:22:13.572082
1936 00:22:13.572138 ==
1937 00:22:13.575297 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 00:22:13.582174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 00:22:13.582254 ==
1940 00:22:13.582314
1941 00:22:13.582368
1942 00:22:13.582420 TX Vref Scan disable
1943 00:22:13.585212 == TX Byte 0 ==
1944 00:22:13.588833 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1945 00:22:13.592349 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1946 00:22:13.595350 == TX Byte 1 ==
1947 00:22:13.598769 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1948 00:22:13.605092 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1949 00:22:13.605167 ==
1950 00:22:13.608758 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 00:22:13.611761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 00:22:13.611860 ==
1953 00:22:13.624669 TX Vref=22, minBit 11, minWin=27, winSum=446
1954 00:22:13.627590 TX Vref=24, minBit 0, minWin=27, winSum=445
1955 00:22:13.631261 TX Vref=26, minBit 12, minWin=27, winSum=447
1956 00:22:13.634123 TX Vref=28, minBit 1, minWin=27, winSum=449
1957 00:22:13.637690 TX Vref=30, minBit 1, minWin=27, winSum=449
1958 00:22:13.644340 TX Vref=32, minBit 0, minWin=28, winSum=451
1959 00:22:13.647879 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 32
1960 00:22:13.647958
1961 00:22:13.651408 Final TX Range 1 Vref 32
1962 00:22:13.651508
1963 00:22:13.651596 ==
1964 00:22:13.654983 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 00:22:13.657779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 00:22:13.657856 ==
1967 00:22:13.657915
1968 00:22:13.661463
1969 00:22:13.661529 TX Vref Scan disable
1970 00:22:13.664245 == TX Byte 0 ==
1971 00:22:13.667919 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1972 00:22:13.670994 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1973 00:22:13.674473 == TX Byte 1 ==
1974 00:22:13.677847 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1975 00:22:13.681487 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1976 00:22:13.681563
1977 00:22:13.684415 [DATLAT]
1978 00:22:13.684490 Freq=800, CH1 RK1
1979 00:22:13.684550
1980 00:22:13.687851 DATLAT Default: 0xa
1981 00:22:13.687927 0, 0xFFFF, sum = 0
1982 00:22:13.691282 1, 0xFFFF, sum = 0
1983 00:22:13.691360 2, 0xFFFF, sum = 0
1984 00:22:13.694271 3, 0xFFFF, sum = 0
1985 00:22:13.694352 4, 0xFFFF, sum = 0
1986 00:22:13.697865 5, 0xFFFF, sum = 0
1987 00:22:13.697966 6, 0xFFFF, sum = 0
1988 00:22:13.701511 7, 0xFFFF, sum = 0
1989 00:22:13.701612 8, 0xFFFF, sum = 0
1990 00:22:13.704336 9, 0x0, sum = 1
1991 00:22:13.704412 10, 0x0, sum = 2
1992 00:22:13.707944 11, 0x0, sum = 3
1993 00:22:13.708044 12, 0x0, sum = 4
1994 00:22:13.710843 best_step = 10
1995 00:22:13.710933
1996 00:22:13.711015 ==
1997 00:22:13.714260 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 00:22:13.717792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 00:22:13.717891 ==
2000 00:22:13.720925 RX Vref Scan: 0
2001 00:22:13.721000
2002 00:22:13.721057 RX Vref 0 -> 0, step: 1
2003 00:22:13.721112
2004 00:22:13.724593 RX Delay -95 -> 252, step: 8
2005 00:22:13.731276 iDelay=201, Bit 0, Center 84 (-31 ~ 200) 232
2006 00:22:13.734240 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2007 00:22:13.737828 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2008 00:22:13.741460 iDelay=201, Bit 3, Center 76 (-39 ~ 192) 232
2009 00:22:13.744424 iDelay=201, Bit 4, Center 84 (-31 ~ 200) 232
2010 00:22:13.751161 iDelay=201, Bit 5, Center 92 (-15 ~ 200) 216
2011 00:22:13.754326 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2012 00:22:13.758168 iDelay=201, Bit 7, Center 76 (-39 ~ 192) 232
2013 00:22:13.761103 iDelay=201, Bit 8, Center 64 (-55 ~ 184) 240
2014 00:22:13.764399 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2015 00:22:13.771133 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2016 00:22:13.774170 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2017 00:22:13.777752 iDelay=201, Bit 12, Center 80 (-31 ~ 192) 224
2018 00:22:13.781141 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2019 00:22:13.784679 iDelay=201, Bit 14, Center 84 (-31 ~ 200) 232
2020 00:22:13.790846 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2021 00:22:13.790925 ==
2022 00:22:13.794277 Dram Type= 6, Freq= 0, CH_1, rank 1
2023 00:22:13.797537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2024 00:22:13.797613 ==
2025 00:22:13.797671 DQS Delay:
2026 00:22:13.800960 DQS0 = 0, DQS1 = 0
2027 00:22:13.801035 DQM Delay:
2028 00:22:13.804694 DQM0 = 80, DQM1 = 75
2029 00:22:13.804769 DQ Delay:
2030 00:22:13.807627 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2031 00:22:13.810950 DQ4 =84, DQ5 =92, DQ6 =88, DQ7 =76
2032 00:22:13.814595 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2033 00:22:13.817594 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2034 00:22:13.817669
2035 00:22:13.817730
2036 00:22:13.824794 [DQSOSCAuto] RK1, (LSB)MR18= 0x252f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
2037 00:22:13.827826 CH1 RK1: MR19=606, MR18=252F
2038 00:22:13.834502 CH1_RK1: MR19=0x606, MR18=0x252F, DQSOSC=397, MR23=63, INC=93, DEC=62
2039 00:22:13.837594 [RxdqsGatingPostProcess] freq 800
2040 00:22:13.844646 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2041 00:22:13.844718 Pre-setting of DQS Precalculation
2042 00:22:13.851376 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2043 00:22:13.857977 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2044 00:22:13.864224 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2045 00:22:13.864297
2046 00:22:13.864356
2047 00:22:13.867615 [Calibration Summary] 1600 Mbps
2048 00:22:13.871013 CH 0, Rank 0
2049 00:22:13.871084 SW Impedance : PASS
2050 00:22:13.874187 DUTY Scan : NO K
2051 00:22:13.877801 ZQ Calibration : PASS
2052 00:22:13.877870 Jitter Meter : NO K
2053 00:22:13.881343 CBT Training : PASS
2054 00:22:13.884356 Write leveling : PASS
2055 00:22:13.884431 RX DQS gating : PASS
2056 00:22:13.887787 RX DQ/DQS(RDDQC) : PASS
2057 00:22:13.887864 TX DQ/DQS : PASS
2058 00:22:13.891194 RX DATLAT : PASS
2059 00:22:13.894348 RX DQ/DQS(Engine): PASS
2060 00:22:13.894424 TX OE : NO K
2061 00:22:13.897956 All Pass.
2062 00:22:13.898123
2063 00:22:13.898208 CH 0, Rank 1
2064 00:22:13.901114 SW Impedance : PASS
2065 00:22:13.901189 DUTY Scan : NO K
2066 00:22:13.904450 ZQ Calibration : PASS
2067 00:22:13.907844 Jitter Meter : NO K
2068 00:22:13.907920 CBT Training : PASS
2069 00:22:13.911276 Write leveling : PASS
2070 00:22:13.914269 RX DQS gating : PASS
2071 00:22:13.914369 RX DQ/DQS(RDDQC) : PASS
2072 00:22:13.917698 TX DQ/DQS : PASS
2073 00:22:13.921268 RX DATLAT : PASS
2074 00:22:13.921367 RX DQ/DQS(Engine): PASS
2075 00:22:13.924258 TX OE : NO K
2076 00:22:13.924356 All Pass.
2077 00:22:13.924449
2078 00:22:13.927802 CH 1, Rank 0
2079 00:22:13.927878 SW Impedance : PASS
2080 00:22:13.931479 DUTY Scan : NO K
2081 00:22:13.931554 ZQ Calibration : PASS
2082 00:22:13.934435 Jitter Meter : NO K
2083 00:22:13.937958 CBT Training : PASS
2084 00:22:13.938072 Write leveling : PASS
2085 00:22:13.940902 RX DQS gating : PASS
2086 00:22:13.944702 RX DQ/DQS(RDDQC) : PASS
2087 00:22:13.944819 TX DQ/DQS : PASS
2088 00:22:13.947667 RX DATLAT : PASS
2089 00:22:13.951336 RX DQ/DQS(Engine): PASS
2090 00:22:13.951411 TX OE : NO K
2091 00:22:13.954270 All Pass.
2092 00:22:13.954381
2093 00:22:13.954477 CH 1, Rank 1
2094 00:22:13.958030 SW Impedance : PASS
2095 00:22:13.958121 DUTY Scan : NO K
2096 00:22:13.961097 ZQ Calibration : PASS
2097 00:22:13.964769 Jitter Meter : NO K
2098 00:22:13.964844 CBT Training : PASS
2099 00:22:13.967845 Write leveling : PASS
2100 00:22:13.967920 RX DQS gating : PASS
2101 00:22:13.971485 RX DQ/DQS(RDDQC) : PASS
2102 00:22:13.974560 TX DQ/DQS : PASS
2103 00:22:13.974636 RX DATLAT : PASS
2104 00:22:13.977885 RX DQ/DQS(Engine): PASS
2105 00:22:13.981367 TX OE : NO K
2106 00:22:13.981443 All Pass.
2107 00:22:13.981501
2108 00:22:13.984423 DramC Write-DBI off
2109 00:22:13.984499 PER_BANK_REFRESH: Hybrid Mode
2110 00:22:13.987967 TX_TRACKING: ON
2111 00:22:13.990941 [GetDramInforAfterCalByMRR] Vendor 6.
2112 00:22:13.994304 [GetDramInforAfterCalByMRR] Revision 606.
2113 00:22:13.997556 [GetDramInforAfterCalByMRR] Revision 2 0.
2114 00:22:13.997655 MR0 0x3b3b
2115 00:22:14.001364 MR8 0x5151
2116 00:22:14.004367 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2117 00:22:14.004449
2118 00:22:14.004517 MR0 0x3b3b
2119 00:22:14.004593 MR8 0x5151
2120 00:22:14.011519 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2121 00:22:14.011617
2122 00:22:14.017688 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2123 00:22:14.020960 [FAST_K] Save calibration result to emmc
2124 00:22:14.024840 [FAST_K] Save calibration result to emmc
2125 00:22:14.027642 dram_init: config_dvfs: 1
2126 00:22:14.031341 dramc_set_vcore_voltage set vcore to 662500
2127 00:22:14.034694 Read voltage for 1200, 2
2128 00:22:14.034771 Vio18 = 0
2129 00:22:14.038262 Vcore = 662500
2130 00:22:14.038339 Vdram = 0
2131 00:22:14.038398 Vddq = 0
2132 00:22:14.041227 Vmddr = 0
2133 00:22:14.044365 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2134 00:22:14.051480 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2135 00:22:14.051558 MEM_TYPE=3, freq_sel=15
2136 00:22:14.054440 sv_algorithm_assistance_LP4_1600
2137 00:22:14.057588 ============ PULL DRAM RESETB DOWN ============
2138 00:22:14.064342 ========== PULL DRAM RESETB DOWN end =========
2139 00:22:14.068223 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2140 00:22:14.071219 ===================================
2141 00:22:14.074800 LPDDR4 DRAM CONFIGURATION
2142 00:22:14.077874 ===================================
2143 00:22:14.077975 EX_ROW_EN[0] = 0x0
2144 00:22:14.081466 EX_ROW_EN[1] = 0x0
2145 00:22:14.081572 LP4Y_EN = 0x0
2146 00:22:14.084975 WORK_FSP = 0x0
2147 00:22:14.085041 WL = 0x4
2148 00:22:14.087975 RL = 0x4
2149 00:22:14.088059 BL = 0x2
2150 00:22:14.091640 RPST = 0x0
2151 00:22:14.094575 RD_PRE = 0x0
2152 00:22:14.094646 WR_PRE = 0x1
2153 00:22:14.098410 WR_PST = 0x0
2154 00:22:14.098485 DBI_WR = 0x0
2155 00:22:14.101619 DBI_RD = 0x0
2156 00:22:14.101693 OTF = 0x1
2157 00:22:14.104890 ===================================
2158 00:22:14.107697 ===================================
2159 00:22:14.111366 ANA top config
2160 00:22:14.114423 ===================================
2161 00:22:14.114499 DLL_ASYNC_EN = 0
2162 00:22:14.118191 ALL_SLAVE_EN = 0
2163 00:22:14.121305 NEW_RANK_MODE = 1
2164 00:22:14.124827 DLL_IDLE_MODE = 1
2165 00:22:14.124895 LP45_APHY_COMB_EN = 1
2166 00:22:14.128456 TX_ODT_DIS = 1
2167 00:22:14.131132 NEW_8X_MODE = 1
2168 00:22:14.134720 ===================================
2169 00:22:14.137961 ===================================
2170 00:22:14.141163 data_rate = 2400
2171 00:22:14.144465 CKR = 1
2172 00:22:14.144540 DQ_P2S_RATIO = 8
2173 00:22:14.147850 ===================================
2174 00:22:14.151309 CA_P2S_RATIO = 8
2175 00:22:14.154384 DQ_CA_OPEN = 0
2176 00:22:14.158076 DQ_SEMI_OPEN = 0
2177 00:22:14.161627 CA_SEMI_OPEN = 0
2178 00:22:14.164754 CA_FULL_RATE = 0
2179 00:22:14.164830 DQ_CKDIV4_EN = 0
2180 00:22:14.167812 CA_CKDIV4_EN = 0
2181 00:22:14.171605 CA_PREDIV_EN = 0
2182 00:22:14.174617 PH8_DLY = 17
2183 00:22:14.178325 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2184 00:22:14.181399 DQ_AAMCK_DIV = 4
2185 00:22:14.181476 CA_AAMCK_DIV = 4
2186 00:22:14.184533 CA_ADMCK_DIV = 4
2187 00:22:14.188024 DQ_TRACK_CA_EN = 0
2188 00:22:14.191582 CA_PICK = 1200
2189 00:22:14.194492 CA_MCKIO = 1200
2190 00:22:14.197671 MCKIO_SEMI = 0
2191 00:22:14.201404 PLL_FREQ = 2366
2192 00:22:14.201480 DQ_UI_PI_RATIO = 32
2193 00:22:14.204492 CA_UI_PI_RATIO = 0
2194 00:22:14.208100 ===================================
2195 00:22:14.211421 ===================================
2196 00:22:14.214690 memory_type:LPDDR4
2197 00:22:14.217975 GP_NUM : 10
2198 00:22:14.218086 SRAM_EN : 1
2199 00:22:14.221659 MD32_EN : 0
2200 00:22:14.224764 ===================================
2201 00:22:14.224837 [ANA_INIT] >>>>>>>>>>>>>>
2202 00:22:14.228347 <<<<<< [CONFIGURE PHASE]: ANA_TX
2203 00:22:14.231462 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2204 00:22:14.234535 ===================================
2205 00:22:14.238157 data_rate = 2400,PCW = 0X5b00
2206 00:22:14.241286 ===================================
2207 00:22:14.244476 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2208 00:22:14.251447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2209 00:22:14.258283 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2210 00:22:14.261114 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2211 00:22:14.265045 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2212 00:22:14.267816 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2213 00:22:14.271610 [ANA_INIT] flow start
2214 00:22:14.271686 [ANA_INIT] PLL >>>>>>>>
2215 00:22:14.274860 [ANA_INIT] PLL <<<<<<<<
2216 00:22:14.278346 [ANA_INIT] MIDPI >>>>>>>>
2217 00:22:14.278423 [ANA_INIT] MIDPI <<<<<<<<
2218 00:22:14.281388 [ANA_INIT] DLL >>>>>>>>
2219 00:22:14.285171 [ANA_INIT] DLL <<<<<<<<
2220 00:22:14.285264 [ANA_INIT] flow end
2221 00:22:14.288314 ============ LP4 DIFF to SE enter ============
2222 00:22:14.294911 ============ LP4 DIFF to SE exit ============
2223 00:22:14.294989 [ANA_INIT] <<<<<<<<<<<<<
2224 00:22:14.297884 [Flow] Enable top DCM control >>>>>
2225 00:22:14.301562 [Flow] Enable top DCM control <<<<<
2226 00:22:14.304663 Enable DLL master slave shuffle
2227 00:22:14.311390 ==============================================================
2228 00:22:14.311468 Gating Mode config
2229 00:22:14.317882 ==============================================================
2230 00:22:14.321237 Config description:
2231 00:22:14.331710 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2232 00:22:14.338447 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2233 00:22:14.341467 SELPH_MODE 0: By rank 1: By Phase
2234 00:22:14.348268 ==============================================================
2235 00:22:14.351357 GAT_TRACK_EN = 1
2236 00:22:14.351435 RX_GATING_MODE = 2
2237 00:22:14.354708 RX_GATING_TRACK_MODE = 2
2238 00:22:14.358134 SELPH_MODE = 1
2239 00:22:14.361349 PICG_EARLY_EN = 1
2240 00:22:14.364655 VALID_LAT_VALUE = 1
2241 00:22:14.371861 ==============================================================
2242 00:22:14.374763 Enter into Gating configuration >>>>
2243 00:22:14.378265 Exit from Gating configuration <<<<
2244 00:22:14.381828 Enter into DVFS_PRE_config >>>>>
2245 00:22:14.391605 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2246 00:22:14.394719 Exit from DVFS_PRE_config <<<<<
2247 00:22:14.398293 Enter into PICG configuration >>>>
2248 00:22:14.401873 Exit from PICG configuration <<<<
2249 00:22:14.405235 [RX_INPUT] configuration >>>>>
2250 00:22:14.405312 [RX_INPUT] configuration <<<<<
2251 00:22:14.411893 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2252 00:22:14.418105 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2253 00:22:14.421771 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2254 00:22:14.428333 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2255 00:22:14.434904 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2256 00:22:14.441764 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2257 00:22:14.444646 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2258 00:22:14.448353 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2259 00:22:14.454940 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2260 00:22:14.458647 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2261 00:22:14.461732 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2262 00:22:14.465333 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2263 00:22:14.468558 ===================================
2264 00:22:14.472083 LPDDR4 DRAM CONFIGURATION
2265 00:22:14.475218 ===================================
2266 00:22:14.478732 EX_ROW_EN[0] = 0x0
2267 00:22:14.478824 EX_ROW_EN[1] = 0x0
2268 00:22:14.481616 LP4Y_EN = 0x0
2269 00:22:14.481715 WORK_FSP = 0x0
2270 00:22:14.485073 WL = 0x4
2271 00:22:14.485139 RL = 0x4
2272 00:22:14.488533 BL = 0x2
2273 00:22:14.488624 RPST = 0x0
2274 00:22:14.492107 RD_PRE = 0x0
2275 00:22:14.492201 WR_PRE = 0x1
2276 00:22:14.495085 WR_PST = 0x0
2277 00:22:14.495152 DBI_WR = 0x0
2278 00:22:14.498684 DBI_RD = 0x0
2279 00:22:14.498750 OTF = 0x1
2280 00:22:14.502425 ===================================
2281 00:22:14.508946 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2282 00:22:14.511757 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2283 00:22:14.515270 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2284 00:22:14.518346 ===================================
2285 00:22:14.522133 LPDDR4 DRAM CONFIGURATION
2286 00:22:14.525211 ===================================
2287 00:22:14.528881 EX_ROW_EN[0] = 0x10
2288 00:22:14.528956 EX_ROW_EN[1] = 0x0
2289 00:22:14.531998 LP4Y_EN = 0x0
2290 00:22:14.532074 WORK_FSP = 0x0
2291 00:22:14.535460 WL = 0x4
2292 00:22:14.535535 RL = 0x4
2293 00:22:14.538864 BL = 0x2
2294 00:22:14.538940 RPST = 0x0
2295 00:22:14.542206 RD_PRE = 0x0
2296 00:22:14.542287 WR_PRE = 0x1
2297 00:22:14.545615 WR_PST = 0x0
2298 00:22:14.545691 DBI_WR = 0x0
2299 00:22:14.548859 DBI_RD = 0x0
2300 00:22:14.548926 OTF = 0x1
2301 00:22:14.552198 ===================================
2302 00:22:14.558404 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2303 00:22:14.558482 ==
2304 00:22:14.562061 Dram Type= 6, Freq= 0, CH_0, rank 0
2305 00:22:14.565293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2306 00:22:14.568311 ==
2307 00:22:14.568380 [Duty_Offset_Calibration]
2308 00:22:14.572060 B0:2 B1:-1 CA:1
2309 00:22:14.572136
2310 00:22:14.575021 [DutyScan_Calibration_Flow] k_type=0
2311 00:22:14.582997
2312 00:22:14.583076 ==CLK 0==
2313 00:22:14.586448 Final CLK duty delay cell = -4
2314 00:22:14.589438 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2315 00:22:14.592702 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2316 00:22:14.596621 [-4] AVG Duty = 4953%(X100)
2317 00:22:14.596718
2318 00:22:14.599934 CH0 CLK Duty spec in!! Max-Min= 156%
2319 00:22:14.603131 [DutyScan_Calibration_Flow] ====Done====
2320 00:22:14.603212
2321 00:22:14.606169 [DutyScan_Calibration_Flow] k_type=1
2322 00:22:14.621638
2323 00:22:14.621716 ==DQS 0 ==
2324 00:22:14.625373 Final DQS duty delay cell = 0
2325 00:22:14.628252 [0] MAX Duty = 5156%(X100), DQS PI = 48
2326 00:22:14.631990 [0] MIN Duty = 4969%(X100), DQS PI = 14
2327 00:22:14.632067 [0] AVG Duty = 5062%(X100)
2328 00:22:14.634967
2329 00:22:14.635043 ==DQS 1 ==
2330 00:22:14.638623 Final DQS duty delay cell = -4
2331 00:22:14.641652 [-4] MAX Duty = 5093%(X100), DQS PI = 6
2332 00:22:14.644944 [-4] MIN Duty = 5000%(X100), DQS PI = 48
2333 00:22:14.648330 [-4] AVG Duty = 5046%(X100)
2334 00:22:14.648473
2335 00:22:14.651709 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2336 00:22:14.651785
2337 00:22:14.654936 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2338 00:22:14.658308 [DutyScan_Calibration_Flow] ====Done====
2339 00:22:14.658384
2340 00:22:14.661844 [DutyScan_Calibration_Flow] k_type=3
2341 00:22:14.678537
2342 00:22:14.678618 ==DQM 0 ==
2343 00:22:14.682141 Final DQM duty delay cell = 0
2344 00:22:14.685232 [0] MAX Duty = 5000%(X100), DQS PI = 54
2345 00:22:14.688687 [0] MIN Duty = 4907%(X100), DQS PI = 2
2346 00:22:14.688764 [0] AVG Duty = 4953%(X100)
2347 00:22:14.692115
2348 00:22:14.692192 ==DQM 1 ==
2349 00:22:14.695461 Final DQM duty delay cell = 0
2350 00:22:14.698394 [0] MAX Duty = 5156%(X100), DQS PI = 62
2351 00:22:14.702115 [0] MIN Duty = 4969%(X100), DQS PI = 10
2352 00:22:14.702191 [0] AVG Duty = 5062%(X100)
2353 00:22:14.705609
2354 00:22:14.708662 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2355 00:22:14.708738
2356 00:22:14.712129 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2357 00:22:14.715083 [DutyScan_Calibration_Flow] ====Done====
2358 00:22:14.715167
2359 00:22:14.718660 [DutyScan_Calibration_Flow] k_type=2
2360 00:22:14.734268
2361 00:22:14.734348 ==DQ 0 ==
2362 00:22:14.737347 Final DQ duty delay cell = -4
2363 00:22:14.741001 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2364 00:22:14.744062 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2365 00:22:14.747658 [-4] AVG Duty = 4969%(X100)
2366 00:22:14.747740
2367 00:22:14.747799 ==DQ 1 ==
2368 00:22:14.750623 Final DQ duty delay cell = 0
2369 00:22:14.753925 [0] MAX Duty = 5031%(X100), DQS PI = 26
2370 00:22:14.757300 [0] MIN Duty = 4907%(X100), DQS PI = 46
2371 00:22:14.757396 [0] AVG Duty = 4969%(X100)
2372 00:22:14.760931
2373 00:22:14.764461 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2374 00:22:14.764592
2375 00:22:14.767410 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2376 00:22:14.770607 [DutyScan_Calibration_Flow] ====Done====
2377 00:22:14.770697 ==
2378 00:22:14.774273 Dram Type= 6, Freq= 0, CH_1, rank 0
2379 00:22:14.777331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2380 00:22:14.777408 ==
2381 00:22:14.781010 [Duty_Offset_Calibration]
2382 00:22:14.781117 B0:1 B1:1 CA:2
2383 00:22:14.781202
2384 00:22:14.784027 [DutyScan_Calibration_Flow] k_type=0
2385 00:22:14.794545
2386 00:22:14.794635 ==CLK 0==
2387 00:22:14.798177 Final CLK duty delay cell = 0
2388 00:22:14.801452 [0] MAX Duty = 5156%(X100), DQS PI = 24
2389 00:22:14.804497 [0] MIN Duty = 4938%(X100), DQS PI = 40
2390 00:22:14.804588 [0] AVG Duty = 5047%(X100)
2391 00:22:14.808095
2392 00:22:14.811059 CH1 CLK Duty spec in!! Max-Min= 218%
2393 00:22:14.814546 [DutyScan_Calibration_Flow] ====Done====
2394 00:22:14.814637
2395 00:22:14.818028 [DutyScan_Calibration_Flow] k_type=1
2396 00:22:14.834160
2397 00:22:14.834257 ==DQS 0 ==
2398 00:22:14.837609 Final DQS duty delay cell = 0
2399 00:22:14.840743 [0] MAX Duty = 5031%(X100), DQS PI = 18
2400 00:22:14.843720 [0] MIN Duty = 4813%(X100), DQS PI = 50
2401 00:22:14.846938 [0] AVG Duty = 4922%(X100)
2402 00:22:14.847037
2403 00:22:14.847119 ==DQS 1 ==
2404 00:22:14.850587 Final DQS duty delay cell = 0
2405 00:22:14.853752 [0] MAX Duty = 5062%(X100), DQS PI = 36
2406 00:22:14.857360 [0] MIN Duty = 4907%(X100), DQS PI = 16
2407 00:22:14.860293 [0] AVG Duty = 4984%(X100)
2408 00:22:14.860382
2409 00:22:14.863708 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2410 00:22:14.863777
2411 00:22:14.867009 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2412 00:22:14.870461 [DutyScan_Calibration_Flow] ====Done====
2413 00:22:14.870530
2414 00:22:14.873802 [DutyScan_Calibration_Flow] k_type=3
2415 00:22:14.890440
2416 00:22:14.890529 ==DQM 0 ==
2417 00:22:14.893944 Final DQM duty delay cell = 0
2418 00:22:14.897043 [0] MAX Duty = 5093%(X100), DQS PI = 16
2419 00:22:14.900809 [0] MIN Duty = 4876%(X100), DQS PI = 50
2420 00:22:14.904004 [0] AVG Duty = 4984%(X100)
2421 00:22:14.904094
2422 00:22:14.904184 ==DQM 1 ==
2423 00:22:14.906836 Final DQM duty delay cell = 0
2424 00:22:14.910940 [0] MAX Duty = 5125%(X100), DQS PI = 0
2425 00:22:14.913698 [0] MIN Duty = 4969%(X100), DQS PI = 4
2426 00:22:14.913764 [0] AVG Duty = 5047%(X100)
2427 00:22:14.917162
2428 00:22:14.920840 CH1 DQM 0 Duty spec in!! Max-Min= 217%
2429 00:22:14.920915
2430 00:22:14.923668 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2431 00:22:14.927221 [DutyScan_Calibration_Flow] ====Done====
2432 00:22:14.927306
2433 00:22:14.930861 [DutyScan_Calibration_Flow] k_type=2
2434 00:22:14.947151
2435 00:22:14.947226 ==DQ 0 ==
2436 00:22:14.950301 Final DQ duty delay cell = 0
2437 00:22:14.953344 [0] MAX Duty = 5093%(X100), DQS PI = 18
2438 00:22:14.957089 [0] MIN Duty = 4969%(X100), DQS PI = 0
2439 00:22:14.957161 [0] AVG Duty = 5031%(X100)
2440 00:22:14.957219
2441 00:22:14.960134 ==DQ 1 ==
2442 00:22:14.963950 Final DQ duty delay cell = 0
2443 00:22:14.966775 [0] MAX Duty = 5093%(X100), DQS PI = 10
2444 00:22:14.970482 [0] MIN Duty = 5000%(X100), DQS PI = 2
2445 00:22:14.970560 [0] AVG Duty = 5046%(X100)
2446 00:22:14.970618
2447 00:22:14.973446 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2448 00:22:14.973521
2449 00:22:14.976676 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2450 00:22:14.983577 [DutyScan_Calibration_Flow] ====Done====
2451 00:22:14.986645 nWR fixed to 30
2452 00:22:14.986732 [ModeRegInit_LP4] CH0 RK0
2453 00:22:14.990409 [ModeRegInit_LP4] CH0 RK1
2454 00:22:14.993417 [ModeRegInit_LP4] CH1 RK0
2455 00:22:14.993515 [ModeRegInit_LP4] CH1 RK1
2456 00:22:14.997131 match AC timing 7
2457 00:22:15.000205 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2458 00:22:15.003481 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2459 00:22:15.009810 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2460 00:22:15.013245 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2461 00:22:15.019961 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2462 00:22:15.020066 ==
2463 00:22:15.023689 Dram Type= 6, Freq= 0, CH_0, rank 0
2464 00:22:15.026754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2465 00:22:15.026831 ==
2466 00:22:15.033669 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2467 00:22:15.037158 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2468 00:22:15.047090 [CA 0] Center 40 (10~71) winsize 62
2469 00:22:15.050129 [CA 1] Center 39 (9~70) winsize 62
2470 00:22:15.053616 [CA 2] Center 36 (6~67) winsize 62
2471 00:22:15.056617 [CA 3] Center 36 (5~67) winsize 63
2472 00:22:15.060399 [CA 4] Center 35 (5~65) winsize 61
2473 00:22:15.063585 [CA 5] Center 35 (5~65) winsize 61
2474 00:22:15.063661
2475 00:22:15.066614 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2476 00:22:15.066690
2477 00:22:15.070343 [CATrainingPosCal] consider 1 rank data
2478 00:22:15.073386 u2DelayCellTimex100 = 270/100 ps
2479 00:22:15.076924 CA0 delay=40 (10~71),Diff = 5 PI (24 cell)
2480 00:22:15.080521 CA1 delay=39 (9~70),Diff = 4 PI (19 cell)
2481 00:22:15.086971 CA2 delay=36 (6~67),Diff = 1 PI (4 cell)
2482 00:22:15.090404 CA3 delay=36 (5~67),Diff = 1 PI (4 cell)
2483 00:22:15.093912 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
2484 00:22:15.097151 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
2485 00:22:15.097227
2486 00:22:15.100131 CA PerBit enable=1, Macro0, CA PI delay=35
2487 00:22:15.100207
2488 00:22:15.103854 [CBTSetCACLKResult] CA Dly = 35
2489 00:22:15.103930 CS Dly: 7 (0~38)
2490 00:22:15.103990 ==
2491 00:22:15.106778 Dram Type= 6, Freq= 0, CH_0, rank 1
2492 00:22:15.113557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2493 00:22:15.113633 ==
2494 00:22:15.116811 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2495 00:22:15.123412 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2496 00:22:15.132917 [CA 0] Center 39 (9~70) winsize 62
2497 00:22:15.135975 [CA 1] Center 39 (9~70) winsize 62
2498 00:22:15.139077 [CA 2] Center 36 (6~67) winsize 62
2499 00:22:15.142487 [CA 3] Center 35 (5~66) winsize 62
2500 00:22:15.145668 [CA 4] Center 34 (4~65) winsize 62
2501 00:22:15.149087 [CA 5] Center 34 (4~64) winsize 61
2502 00:22:15.149162
2503 00:22:15.152584 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2504 00:22:15.152661
2505 00:22:15.155647 [CATrainingPosCal] consider 2 rank data
2506 00:22:15.159282 u2DelayCellTimex100 = 270/100 ps
2507 00:22:15.162317 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2508 00:22:15.165959 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2509 00:22:15.172582 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2510 00:22:15.176235 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2511 00:22:15.179098 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2512 00:22:15.182705 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
2513 00:22:15.182773
2514 00:22:15.185734 CA PerBit enable=1, Macro0, CA PI delay=34
2515 00:22:15.185801
2516 00:22:15.189172 [CBTSetCACLKResult] CA Dly = 34
2517 00:22:15.189245 CS Dly: 8 (0~41)
2518 00:22:15.189320
2519 00:22:15.192863 ----->DramcWriteLeveling(PI) begin...
2520 00:22:15.196303 ==
2521 00:22:15.199058 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 00:22:15.202702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 00:22:15.202810 ==
2524 00:22:15.205881 Write leveling (Byte 0): 32 => 32
2525 00:22:15.209455 Write leveling (Byte 1): 29 => 29
2526 00:22:15.212964 DramcWriteLeveling(PI) end<-----
2527 00:22:15.213062
2528 00:22:15.213156 ==
2529 00:22:15.216056 Dram Type= 6, Freq= 0, CH_0, rank 0
2530 00:22:15.219604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2531 00:22:15.219680 ==
2532 00:22:15.222457 [Gating] SW mode calibration
2533 00:22:15.229655 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2534 00:22:15.232450 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2535 00:22:15.239497 0 15 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
2536 00:22:15.242617 0 15 4 | B1->B0 | 2525 3131 | 1 1 | (0 0) (1 1)
2537 00:22:15.246145 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 00:22:15.252706 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 00:22:15.255717 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 00:22:15.259732 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 00:22:15.266344 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 00:22:15.269446 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2543 00:22:15.273262 1 0 0 | B1->B0 | 3333 2e2e | 1 0 | (1 0) (0 1)
2544 00:22:15.279839 1 0 4 | B1->B0 | 2727 2323 | 1 0 | (1 0) (1 0)
2545 00:22:15.283449 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 00:22:15.286377 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 00:22:15.289583 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 00:22:15.296155 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 00:22:15.299956 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 00:22:15.302953 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 00:22:15.309745 1 1 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2552 00:22:15.313357 1 1 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2553 00:22:15.316439 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 00:22:15.322966 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 00:22:15.326724 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 00:22:15.329596 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 00:22:15.336063 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 00:22:15.339441 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 00:22:15.342969 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2560 00:22:15.349758 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2561 00:22:15.353071 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 00:22:15.355987 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 00:22:15.362813 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 00:22:15.366242 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 00:22:15.369773 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 00:22:15.375924 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 00:22:15.379567 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 00:22:15.383223 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 00:22:15.389803 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 00:22:15.392911 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 00:22:15.396300 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 00:22:15.399317 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 00:22:15.405927 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 00:22:15.409734 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 00:22:15.412688 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2576 00:22:15.419708 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 00:22:15.423204 Total UI for P1: 0, mck2ui 16
2578 00:22:15.426201 best dqsien dly found for B0: ( 1, 4, 0)
2579 00:22:15.426333 Total UI for P1: 0, mck2ui 16
2580 00:22:15.432890 best dqsien dly found for B1: ( 1, 4, 2)
2581 00:22:15.436348 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2582 00:22:15.439429 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2583 00:22:15.439519
2584 00:22:15.442897 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2585 00:22:15.446283 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2586 00:22:15.449882 [Gating] SW calibration Done
2587 00:22:15.450001 ==
2588 00:22:15.452923 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 00:22:15.456012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 00:22:15.456078 ==
2591 00:22:15.459516 RX Vref Scan: 0
2592 00:22:15.459584
2593 00:22:15.459639 RX Vref 0 -> 0, step: 1
2594 00:22:15.459706
2595 00:22:15.463027 RX Delay -40 -> 252, step: 8
2596 00:22:15.466094 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2597 00:22:15.472716 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2598 00:22:15.476212 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2599 00:22:15.479984 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2600 00:22:15.482966 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2601 00:22:15.486041 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2602 00:22:15.489441 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2603 00:22:15.496269 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2604 00:22:15.499770 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2605 00:22:15.503342 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2606 00:22:15.506379 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2607 00:22:15.509937 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2608 00:22:15.516640 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2609 00:22:15.519782 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2610 00:22:15.523296 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2611 00:22:15.526227 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2612 00:22:15.526303 ==
2613 00:22:15.529977 Dram Type= 6, Freq= 0, CH_0, rank 0
2614 00:22:15.536188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2615 00:22:15.536265 ==
2616 00:22:15.536323 DQS Delay:
2617 00:22:15.536376 DQS0 = 0, DQS1 = 0
2618 00:22:15.539811 DQM Delay:
2619 00:22:15.539887 DQM0 = 116, DQM1 = 108
2620 00:22:15.543295 DQ Delay:
2621 00:22:15.546318 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2622 00:22:15.549780 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2623 00:22:15.553215 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2624 00:22:15.556142 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2625 00:22:15.556232
2626 00:22:15.556322
2627 00:22:15.556401 ==
2628 00:22:15.559875 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 00:22:15.562876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 00:22:15.562941 ==
2631 00:22:15.566398
2632 00:22:15.566461
2633 00:22:15.566529 TX Vref Scan disable
2634 00:22:15.569355 == TX Byte 0 ==
2635 00:22:15.573062 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2636 00:22:15.576140 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2637 00:22:15.579391 == TX Byte 1 ==
2638 00:22:15.583054 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2639 00:22:15.586109 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2640 00:22:15.586178 ==
2641 00:22:15.589931 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 00:22:15.596503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 00:22:15.596599 ==
2644 00:22:15.606890 TX Vref=22, minBit 1, minWin=25, winSum=421
2645 00:22:15.610398 TX Vref=24, minBit 1, minWin=25, winSum=423
2646 00:22:15.613977 TX Vref=26, minBit 1, minWin=26, winSum=431
2647 00:22:15.617127 TX Vref=28, minBit 7, minWin=26, winSum=438
2648 00:22:15.620138 TX Vref=30, minBit 1, minWin=26, winSum=437
2649 00:22:15.623831 TX Vref=32, minBit 4, minWin=26, winSum=434
2650 00:22:15.630529 [TxChooseVref] Worse bit 7, Min win 26, Win sum 438, Final Vref 28
2651 00:22:15.630605
2652 00:22:15.633962 Final TX Range 1 Vref 28
2653 00:22:15.634059
2654 00:22:15.634118 ==
2655 00:22:15.636989 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 00:22:15.640486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2657 00:22:15.640568 ==
2658 00:22:15.640656
2659 00:22:15.640754
2660 00:22:15.643931 TX Vref Scan disable
2661 00:22:15.646989 == TX Byte 0 ==
2662 00:22:15.650706 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2663 00:22:15.653896 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2664 00:22:15.657307 == TX Byte 1 ==
2665 00:22:15.660616 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2666 00:22:15.663656 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2667 00:22:15.663732
2668 00:22:15.667160 [DATLAT]
2669 00:22:15.667236 Freq=1200, CH0 RK0
2670 00:22:15.667295
2671 00:22:15.670237 DATLAT Default: 0xd
2672 00:22:15.670314 0, 0xFFFF, sum = 0
2673 00:22:15.674016 1, 0xFFFF, sum = 0
2674 00:22:15.674107 2, 0xFFFF, sum = 0
2675 00:22:15.677069 3, 0xFFFF, sum = 0
2676 00:22:15.677146 4, 0xFFFF, sum = 0
2677 00:22:15.680098 5, 0xFFFF, sum = 0
2678 00:22:15.680175 6, 0xFFFF, sum = 0
2679 00:22:15.683873 7, 0xFFFF, sum = 0
2680 00:22:15.683949 8, 0xFFFF, sum = 0
2681 00:22:15.687249 9, 0xFFFF, sum = 0
2682 00:22:15.690368 10, 0xFFFF, sum = 0
2683 00:22:15.690446 11, 0xFFFF, sum = 0
2684 00:22:15.693995 12, 0x0, sum = 1
2685 00:22:15.694090 13, 0x0, sum = 2
2686 00:22:15.694150 14, 0x0, sum = 3
2687 00:22:15.696969 15, 0x0, sum = 4
2688 00:22:15.697046 best_step = 13
2689 00:22:15.697106
2690 00:22:15.697160 ==
2691 00:22:15.700680 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 00:22:15.707349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 00:22:15.707426 ==
2694 00:22:15.707483 RX Vref Scan: 1
2695 00:22:15.707538
2696 00:22:15.710281 Set Vref Range= 32 -> 127
2697 00:22:15.710357
2698 00:22:15.713758 RX Vref 32 -> 127, step: 1
2699 00:22:15.713855
2700 00:22:15.717505 RX Delay -21 -> 252, step: 4
2701 00:22:15.717574
2702 00:22:15.720489 Set Vref, RX VrefLevel [Byte0]: 32
2703 00:22:15.723584 [Byte1]: 32
2704 00:22:15.723659
2705 00:22:15.727268 Set Vref, RX VrefLevel [Byte0]: 33
2706 00:22:15.730170 [Byte1]: 33
2707 00:22:15.730251
2708 00:22:15.733797 Set Vref, RX VrefLevel [Byte0]: 34
2709 00:22:15.736709 [Byte1]: 34
2710 00:22:15.740927
2711 00:22:15.741006 Set Vref, RX VrefLevel [Byte0]: 35
2712 00:22:15.744470 [Byte1]: 35
2713 00:22:15.748979
2714 00:22:15.749073 Set Vref, RX VrefLevel [Byte0]: 36
2715 00:22:15.752303 [Byte1]: 36
2716 00:22:15.756689
2717 00:22:15.756782 Set Vref, RX VrefLevel [Byte0]: 37
2718 00:22:15.760169 [Byte1]: 37
2719 00:22:15.764714
2720 00:22:15.764793 Set Vref, RX VrefLevel [Byte0]: 38
2721 00:22:15.768193 [Byte1]: 38
2722 00:22:15.773102
2723 00:22:15.773180 Set Vref, RX VrefLevel [Byte0]: 39
2724 00:22:15.776157 [Byte1]: 39
2725 00:22:15.780489
2726 00:22:15.780567 Set Vref, RX VrefLevel [Byte0]: 40
2727 00:22:15.783961 [Byte1]: 40
2728 00:22:15.788773
2729 00:22:15.788851 Set Vref, RX VrefLevel [Byte0]: 41
2730 00:22:15.791840 [Byte1]: 41
2731 00:22:15.796373
2732 00:22:15.796465 Set Vref, RX VrefLevel [Byte0]: 42
2733 00:22:15.800147 [Byte1]: 42
2734 00:22:15.804711
2735 00:22:15.804790 Set Vref, RX VrefLevel [Byte0]: 43
2736 00:22:15.807843 [Byte1]: 43
2737 00:22:15.812644
2738 00:22:15.812722 Set Vref, RX VrefLevel [Byte0]: 44
2739 00:22:15.815719 [Byte1]: 44
2740 00:22:15.820447
2741 00:22:15.820525 Set Vref, RX VrefLevel [Byte0]: 45
2742 00:22:15.823738 [Byte1]: 45
2743 00:22:15.828670
2744 00:22:15.828778 Set Vref, RX VrefLevel [Byte0]: 46
2745 00:22:15.831738 [Byte1]: 46
2746 00:22:15.836464
2747 00:22:15.836541 Set Vref, RX VrefLevel [Byte0]: 47
2748 00:22:15.839431 [Byte1]: 47
2749 00:22:15.843950
2750 00:22:15.844049 Set Vref, RX VrefLevel [Byte0]: 48
2751 00:22:15.847420 [Byte1]: 48
2752 00:22:15.852140
2753 00:22:15.852219 Set Vref, RX VrefLevel [Byte0]: 49
2754 00:22:15.855209 [Byte1]: 49
2755 00:22:15.860227
2756 00:22:15.860375 Set Vref, RX VrefLevel [Byte0]: 50
2757 00:22:15.863338 [Byte1]: 50
2758 00:22:15.867930
2759 00:22:15.868008 Set Vref, RX VrefLevel [Byte0]: 51
2760 00:22:15.871348 [Byte1]: 51
2761 00:22:15.875968
2762 00:22:15.876046 Set Vref, RX VrefLevel [Byte0]: 52
2763 00:22:15.879168 [Byte1]: 52
2764 00:22:15.883965
2765 00:22:15.884042 Set Vref, RX VrefLevel [Byte0]: 53
2766 00:22:15.887053 [Byte1]: 53
2767 00:22:15.891973
2768 00:22:15.892050 Set Vref, RX VrefLevel [Byte0]: 54
2769 00:22:15.894973 [Byte1]: 54
2770 00:22:15.899943
2771 00:22:15.900021 Set Vref, RX VrefLevel [Byte0]: 55
2772 00:22:15.902848 [Byte1]: 55
2773 00:22:15.907614
2774 00:22:15.907692 Set Vref, RX VrefLevel [Byte0]: 56
2775 00:22:15.910699 [Byte1]: 56
2776 00:22:15.915659
2777 00:22:15.915737 Set Vref, RX VrefLevel [Byte0]: 57
2778 00:22:15.919123 [Byte1]: 57
2779 00:22:15.923319
2780 00:22:15.923397 Set Vref, RX VrefLevel [Byte0]: 58
2781 00:22:15.926963 [Byte1]: 58
2782 00:22:15.931185
2783 00:22:15.931258 Set Vref, RX VrefLevel [Byte0]: 59
2784 00:22:15.934858 [Byte1]: 59
2785 00:22:15.939004
2786 00:22:15.939082 Set Vref, RX VrefLevel [Byte0]: 60
2787 00:22:15.942748 [Byte1]: 60
2788 00:22:15.947016
2789 00:22:15.947116 Set Vref, RX VrefLevel [Byte0]: 61
2790 00:22:15.950738 [Byte1]: 61
2791 00:22:15.955234
2792 00:22:15.955312 Set Vref, RX VrefLevel [Byte0]: 62
2793 00:22:15.958415 [Byte1]: 62
2794 00:22:15.963271
2795 00:22:15.963348 Set Vref, RX VrefLevel [Byte0]: 63
2796 00:22:15.966542 [Byte1]: 63
2797 00:22:15.971225
2798 00:22:15.971305 Set Vref, RX VrefLevel [Byte0]: 64
2799 00:22:15.974220 [Byte1]: 64
2800 00:22:15.979245
2801 00:22:15.979324 Set Vref, RX VrefLevel [Byte0]: 65
2802 00:22:15.982105 [Byte1]: 65
2803 00:22:15.986843
2804 00:22:15.986921 Set Vref, RX VrefLevel [Byte0]: 66
2805 00:22:15.989853 [Byte1]: 66
2806 00:22:15.994839
2807 00:22:15.994966 Set Vref, RX VrefLevel [Byte0]: 67
2808 00:22:15.998339 [Byte1]: 67
2809 00:22:16.002660
2810 00:22:16.002740 Set Vref, RX VrefLevel [Byte0]: 68
2811 00:22:16.006128 [Byte1]: 68
2812 00:22:16.010760
2813 00:22:16.010841 Set Vref, RX VrefLevel [Byte0]: 69
2814 00:22:16.014243 [Byte1]: 69
2815 00:22:16.018571
2816 00:22:16.018649 Final RX Vref Byte 0 = 52 to rank0
2817 00:22:16.021791 Final RX Vref Byte 1 = 51 to rank0
2818 00:22:16.025551 Final RX Vref Byte 0 = 52 to rank1
2819 00:22:16.028465 Final RX Vref Byte 1 = 51 to rank1==
2820 00:22:16.031640 Dram Type= 6, Freq= 0, CH_0, rank 0
2821 00:22:16.038452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2822 00:22:16.038532 ==
2823 00:22:16.038610 DQS Delay:
2824 00:22:16.038682 DQS0 = 0, DQS1 = 0
2825 00:22:16.042130 DQM Delay:
2826 00:22:16.042208 DQM0 = 115, DQM1 = 104
2827 00:22:16.045123 DQ Delay:
2828 00:22:16.048713 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2829 00:22:16.051783 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2830 00:22:16.055381 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2831 00:22:16.058818 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
2832 00:22:16.058896
2833 00:22:16.058974
2834 00:22:16.065812 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 409 ps
2835 00:22:16.068708 CH0 RK0: MR19=403, MR18=1F0
2836 00:22:16.075635 CH0_RK0: MR19=0x403, MR18=0x1F0, DQSOSC=409, MR23=63, INC=39, DEC=26
2837 00:22:16.075714
2838 00:22:16.078555 ----->DramcWriteLeveling(PI) begin...
2839 00:22:16.078634 ==
2840 00:22:16.082295 Dram Type= 6, Freq= 0, CH_0, rank 1
2841 00:22:16.085297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2842 00:22:16.085386 ==
2843 00:22:16.089171 Write leveling (Byte 0): 32 => 32
2844 00:22:16.092067 Write leveling (Byte 1): 29 => 29
2845 00:22:16.095744 DramcWriteLeveling(PI) end<-----
2846 00:22:16.095845
2847 00:22:16.095907 ==
2848 00:22:16.098698 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 00:22:16.102358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2850 00:22:16.102429 ==
2851 00:22:16.105391 [Gating] SW mode calibration
2852 00:22:16.112290 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2853 00:22:16.118886 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2854 00:22:16.122183 0 15 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
2855 00:22:16.128622 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (1 1) (1 1)
2856 00:22:16.132174 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 00:22:16.135870 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 00:22:16.139124 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 00:22:16.145445 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 00:22:16.149174 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 00:22:16.152222 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
2862 00:22:16.159448 1 0 0 | B1->B0 | 2e2e 2828 | 0 1 | (0 0) (0 0)
2863 00:22:16.162365 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 00:22:16.165559 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 00:22:16.172343 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 00:22:16.175964 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 00:22:16.179131 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 00:22:16.185841 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
2869 00:22:16.189225 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2870 00:22:16.192780 1 1 0 | B1->B0 | 3535 4040 | 0 0 | (0 0) (0 0)
2871 00:22:16.199049 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 00:22:16.202851 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 00:22:16.205616 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 00:22:16.212393 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 00:22:16.215584 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 00:22:16.219377 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 00:22:16.225853 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2878 00:22:16.229264 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2879 00:22:16.232812 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 00:22:16.235898 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 00:22:16.242246 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 00:22:16.245804 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 00:22:16.249494 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 00:22:16.256168 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 00:22:16.259253 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 00:22:16.262276 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 00:22:16.269327 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 00:22:16.272192 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 00:22:16.275830 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 00:22:16.282678 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 00:22:16.285741 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 00:22:16.289332 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 00:22:16.295772 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2894 00:22:16.299294 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2895 00:22:16.302180 Total UI for P1: 0, mck2ui 16
2896 00:22:16.305573 best dqsien dly found for B0: ( 1, 3, 28)
2897 00:22:16.308863 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 00:22:16.312443 Total UI for P1: 0, mck2ui 16
2899 00:22:16.315503 best dqsien dly found for B1: ( 1, 4, 0)
2900 00:22:16.319086 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2901 00:22:16.322220 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2902 00:22:16.322287
2903 00:22:16.325873 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2904 00:22:16.332390 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2905 00:22:16.332489 [Gating] SW calibration Done
2906 00:22:16.332574 ==
2907 00:22:16.335501 Dram Type= 6, Freq= 0, CH_0, rank 1
2908 00:22:16.342166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2909 00:22:16.342239 ==
2910 00:22:16.342312 RX Vref Scan: 0
2911 00:22:16.342370
2912 00:22:16.345436 RX Vref 0 -> 0, step: 1
2913 00:22:16.345502
2914 00:22:16.348977 RX Delay -40 -> 252, step: 8
2915 00:22:16.352055 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2916 00:22:16.355789 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2917 00:22:16.359234 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2918 00:22:16.362418 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2919 00:22:16.369240 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2920 00:22:16.371950 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2921 00:22:16.375780 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2922 00:22:16.378938 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2923 00:22:16.382466 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2924 00:22:16.388746 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2925 00:22:16.392239 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2926 00:22:16.395786 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2927 00:22:16.399101 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2928 00:22:16.401939 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2929 00:22:16.409152 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2930 00:22:16.412034 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2931 00:22:16.412102 ==
2932 00:22:16.415375 Dram Type= 6, Freq= 0, CH_0, rank 1
2933 00:22:16.418801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2934 00:22:16.418868 ==
2935 00:22:16.422505 DQS Delay:
2936 00:22:16.422582 DQS0 = 0, DQS1 = 0
2937 00:22:16.422647 DQM Delay:
2938 00:22:16.425659 DQM0 = 115, DQM1 = 105
2939 00:22:16.425750 DQ Delay:
2940 00:22:16.428899 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2941 00:22:16.432460 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2942 00:22:16.435541 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =95
2943 00:22:16.442355 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2944 00:22:16.442484
2945 00:22:16.442603
2946 00:22:16.442712 ==
2947 00:22:16.445430 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 00:22:16.448892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 00:22:16.448972 ==
2950 00:22:16.449035
2951 00:22:16.449089
2952 00:22:16.452447 TX Vref Scan disable
2953 00:22:16.452523 == TX Byte 0 ==
2954 00:22:16.459074 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2955 00:22:16.462597 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2956 00:22:16.462673 == TX Byte 1 ==
2957 00:22:16.469173 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2958 00:22:16.472258 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2959 00:22:16.472334 ==
2960 00:22:16.475679 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 00:22:16.478807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 00:22:16.478944 ==
2963 00:22:16.491630 TX Vref=22, minBit 5, minWin=25, winSum=425
2964 00:22:16.494490 TX Vref=24, minBit 5, minWin=25, winSum=426
2965 00:22:16.498115 TX Vref=26, minBit 1, minWin=26, winSum=432
2966 00:22:16.501636 TX Vref=28, minBit 1, minWin=26, winSum=433
2967 00:22:16.504596 TX Vref=30, minBit 3, minWin=26, winSum=436
2968 00:22:16.511214 TX Vref=32, minBit 12, minWin=26, winSum=437
2969 00:22:16.515101 [TxChooseVref] Worse bit 12, Min win 26, Win sum 437, Final Vref 32
2970 00:22:16.515178
2971 00:22:16.517892 Final TX Range 1 Vref 32
2972 00:22:16.517990
2973 00:22:16.518065 ==
2974 00:22:16.521437 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 00:22:16.524812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 00:22:16.524889 ==
2977 00:22:16.528344
2978 00:22:16.528420
2979 00:22:16.528479 TX Vref Scan disable
2980 00:22:16.531401 == TX Byte 0 ==
2981 00:22:16.535058 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2982 00:22:16.538191 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2983 00:22:16.541630 == TX Byte 1 ==
2984 00:22:16.545062 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2985 00:22:16.548047 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2986 00:22:16.548126
2987 00:22:16.551871 [DATLAT]
2988 00:22:16.551947 Freq=1200, CH0 RK1
2989 00:22:16.552005
2990 00:22:16.554906 DATLAT Default: 0xd
2991 00:22:16.554982 0, 0xFFFF, sum = 0
2992 00:22:16.558685 1, 0xFFFF, sum = 0
2993 00:22:16.558762 2, 0xFFFF, sum = 0
2994 00:22:16.561862 3, 0xFFFF, sum = 0
2995 00:22:16.561938 4, 0xFFFF, sum = 0
2996 00:22:16.565011 5, 0xFFFF, sum = 0
2997 00:22:16.565083 6, 0xFFFF, sum = 0
2998 00:22:16.568688 7, 0xFFFF, sum = 0
2999 00:22:16.568757 8, 0xFFFF, sum = 0
3000 00:22:16.571606 9, 0xFFFF, sum = 0
3001 00:22:16.575232 10, 0xFFFF, sum = 0
3002 00:22:16.575299 11, 0xFFFF, sum = 0
3003 00:22:16.578254 12, 0x0, sum = 1
3004 00:22:16.578331 13, 0x0, sum = 2
3005 00:22:16.578390 14, 0x0, sum = 3
3006 00:22:16.581697 15, 0x0, sum = 4
3007 00:22:16.581773 best_step = 13
3008 00:22:16.581831
3009 00:22:16.584882 ==
3010 00:22:16.584958 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 00:22:16.591686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 00:22:16.591766 ==
3013 00:22:16.591825 RX Vref Scan: 0
3014 00:22:16.591879
3015 00:22:16.594742 RX Vref 0 -> 0, step: 1
3016 00:22:16.594817
3017 00:22:16.598331 RX Delay -21 -> 252, step: 4
3018 00:22:16.601338 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3019 00:22:16.608254 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3020 00:22:16.611653 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3021 00:22:16.615098 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3022 00:22:16.617846 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3023 00:22:16.621361 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3024 00:22:16.624909 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3025 00:22:16.631235 iDelay=195, Bit 7, Center 120 (51 ~ 190) 140
3026 00:22:16.635137 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3027 00:22:16.638124 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3028 00:22:16.641700 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3029 00:22:16.644689 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3030 00:22:16.651667 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3031 00:22:16.654701 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3032 00:22:16.658394 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3033 00:22:16.661584 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3034 00:22:16.661652 ==
3035 00:22:16.665011 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 00:22:16.671544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 00:22:16.671620 ==
3038 00:22:16.671679 DQS Delay:
3039 00:22:16.671734 DQS0 = 0, DQS1 = 0
3040 00:22:16.674610 DQM Delay:
3041 00:22:16.674674 DQM0 = 113, DQM1 = 104
3042 00:22:16.678237 DQ Delay:
3043 00:22:16.681698 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3044 00:22:16.684959 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =120
3045 00:22:16.688512 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3046 00:22:16.691710 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =114
3047 00:22:16.691815
3048 00:22:16.691892
3049 00:22:16.698258 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
3050 00:22:16.701235 CH0 RK1: MR19=403, MR18=3F4
3051 00:22:16.707832 CH0_RK1: MR19=0x403, MR18=0x3F4, DQSOSC=408, MR23=63, INC=39, DEC=26
3052 00:22:16.711528 [RxdqsGatingPostProcess] freq 1200
3053 00:22:16.718068 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3054 00:22:16.718146 best DQS0 dly(2T, 0.5T) = (0, 12)
3055 00:22:16.721646 best DQS1 dly(2T, 0.5T) = (0, 12)
3056 00:22:16.724426 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3057 00:22:16.727832 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3058 00:22:16.731928 best DQS0 dly(2T, 0.5T) = (0, 11)
3059 00:22:16.734886 best DQS1 dly(2T, 0.5T) = (0, 12)
3060 00:22:16.738284 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3061 00:22:16.741114 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3062 00:22:16.744731 Pre-setting of DQS Precalculation
3063 00:22:16.748228 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3064 00:22:16.751661 ==
3065 00:22:16.754640 Dram Type= 6, Freq= 0, CH_1, rank 0
3066 00:22:16.758331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3067 00:22:16.758402 ==
3068 00:22:16.761549 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3069 00:22:16.768385 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3070 00:22:16.777049 [CA 0] Center 38 (8~68) winsize 61
3071 00:22:16.780698 [CA 1] Center 38 (8~68) winsize 61
3072 00:22:16.783793 [CA 2] Center 35 (5~65) winsize 61
3073 00:22:16.787476 [CA 3] Center 34 (4~65) winsize 62
3074 00:22:16.790468 [CA 4] Center 34 (4~65) winsize 62
3075 00:22:16.793657 [CA 5] Center 34 (4~64) winsize 61
3076 00:22:16.793764
3077 00:22:16.796883 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3078 00:22:16.796958
3079 00:22:16.800740 [CATrainingPosCal] consider 1 rank data
3080 00:22:16.803735 u2DelayCellTimex100 = 270/100 ps
3081 00:22:16.807466 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3082 00:22:16.810555 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3083 00:22:16.817455 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3084 00:22:16.820581 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3085 00:22:16.823668 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3086 00:22:16.827415 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3087 00:22:16.827485
3088 00:22:16.830575 CA PerBit enable=1, Macro0, CA PI delay=34
3089 00:22:16.830674
3090 00:22:16.834242 [CBTSetCACLKResult] CA Dly = 34
3091 00:22:16.834314 CS Dly: 6 (0~37)
3092 00:22:16.834371 ==
3093 00:22:16.837390 Dram Type= 6, Freq= 0, CH_1, rank 1
3094 00:22:16.843978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3095 00:22:16.844059 ==
3096 00:22:16.847048 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3097 00:22:16.853762 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3098 00:22:16.862947 [CA 0] Center 38 (8~68) winsize 61
3099 00:22:16.866079 [CA 1] Center 38 (9~68) winsize 60
3100 00:22:16.869234 [CA 2] Center 34 (4~65) winsize 62
3101 00:22:16.873171 [CA 3] Center 34 (3~65) winsize 63
3102 00:22:16.876196 [CA 4] Center 34 (4~65) winsize 62
3103 00:22:16.879225 [CA 5] Center 33 (3~64) winsize 62
3104 00:22:16.879298
3105 00:22:16.882816 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3106 00:22:16.882894
3107 00:22:16.886089 [CATrainingPosCal] consider 2 rank data
3108 00:22:16.889306 u2DelayCellTimex100 = 270/100 ps
3109 00:22:16.892927 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3110 00:22:16.896222 CA1 delay=38 (9~68),Diff = 4 PI (19 cell)
3111 00:22:16.902465 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3112 00:22:16.906129 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3113 00:22:16.909357 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3114 00:22:16.912942 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3115 00:22:16.913042
3116 00:22:16.915970 CA PerBit enable=1, Macro0, CA PI delay=34
3117 00:22:16.916050
3118 00:22:16.919680 [CBTSetCACLKResult] CA Dly = 34
3119 00:22:16.919758 CS Dly: 7 (0~40)
3120 00:22:16.919834
3121 00:22:16.922798 ----->DramcWriteLeveling(PI) begin...
3122 00:22:16.926566 ==
3123 00:22:16.926653 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 00:22:16.932835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3125 00:22:16.932914 ==
3126 00:22:16.936159 Write leveling (Byte 0): 27 => 27
3127 00:22:16.939755 Write leveling (Byte 1): 29 => 29
3128 00:22:16.939833 DramcWriteLeveling(PI) end<-----
3129 00:22:16.939955
3130 00:22:16.943207 ==
3131 00:22:16.946397 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 00:22:16.949741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 00:22:16.949832 ==
3134 00:22:16.952862 [Gating] SW mode calibration
3135 00:22:16.960164 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3136 00:22:16.963044 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3137 00:22:16.970268 0 15 0 | B1->B0 | 2c2c 2525 | 0 1 | (0 0) (1 1)
3138 00:22:16.973210 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 00:22:16.976888 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 00:22:16.983210 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 00:22:16.986779 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 00:22:16.990482 0 15 20 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
3143 00:22:16.993485 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 00:22:17.000222 0 15 28 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
3145 00:22:17.003313 1 0 0 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
3146 00:22:17.006653 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 00:22:17.013030 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3148 00:22:17.016459 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 00:22:17.020115 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 00:22:17.026770 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 00:22:17.029954 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 00:22:17.033709 1 0 28 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
3153 00:22:17.039909 1 1 0 | B1->B0 | 4646 3c3c | 0 0 | (0 0) (1 1)
3154 00:22:17.043795 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 00:22:17.046840 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 00:22:17.053444 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 00:22:17.056629 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 00:22:17.060382 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 00:22:17.066949 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 00:22:17.070013 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3161 00:22:17.073428 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 00:22:17.076814 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 00:22:17.084087 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 00:22:17.087146 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 00:22:17.090114 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 00:22:17.096898 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 00:22:17.100466 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 00:22:17.103677 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 00:22:17.110371 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 00:22:17.113758 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 00:22:17.116928 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 00:22:17.123439 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 00:22:17.126740 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 00:22:17.130206 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 00:22:17.136937 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 00:22:17.140085 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3177 00:22:17.143363 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3178 00:22:17.150210 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 00:22:17.150290 Total UI for P1: 0, mck2ui 16
3180 00:22:17.156562 best dqsien dly found for B0: ( 1, 3, 30)
3181 00:22:17.156656 Total UI for P1: 0, mck2ui 16
3182 00:22:17.160261 best dqsien dly found for B1: ( 1, 4, 0)
3183 00:22:17.166729 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3184 00:22:17.169906 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3185 00:22:17.170067
3186 00:22:17.173285 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3187 00:22:17.177082 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3188 00:22:17.179940 [Gating] SW calibration Done
3189 00:22:17.180018 ==
3190 00:22:17.183338 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 00:22:17.186721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 00:22:17.186800 ==
3193 00:22:17.186895 RX Vref Scan: 0
3194 00:22:17.189960
3195 00:22:17.190075 RX Vref 0 -> 0, step: 1
3196 00:22:17.190151
3197 00:22:17.193296 RX Delay -40 -> 252, step: 8
3198 00:22:17.196687 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3199 00:22:17.200437 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3200 00:22:17.206559 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3201 00:22:17.210460 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3202 00:22:17.213455 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3203 00:22:17.217207 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3204 00:22:17.220120 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3205 00:22:17.226872 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3206 00:22:17.230028 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3207 00:22:17.233671 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3208 00:22:17.236682 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3209 00:22:17.240138 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3210 00:22:17.246941 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3211 00:22:17.250026 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3212 00:22:17.253188 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3213 00:22:17.256949 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3214 00:22:17.257026 ==
3215 00:22:17.260176 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 00:22:17.263275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 00:22:17.266957 ==
3218 00:22:17.267032 DQS Delay:
3219 00:22:17.267091 DQS0 = 0, DQS1 = 0
3220 00:22:17.269955 DQM Delay:
3221 00:22:17.270058 DQM0 = 117, DQM1 = 109
3222 00:22:17.273675 DQ Delay:
3223 00:22:17.277026 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =119
3224 00:22:17.280293 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3225 00:22:17.283715 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3226 00:22:17.286645 DQ12 =119, DQ13 =115, DQ14 =115, DQ15 =115
3227 00:22:17.286723
3228 00:22:17.286782
3229 00:22:17.286837 ==
3230 00:22:17.290352 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 00:22:17.293659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 00:22:17.293754 ==
3233 00:22:17.293858
3234 00:22:17.293940
3235 00:22:17.297008 TX Vref Scan disable
3236 00:22:17.300030 == TX Byte 0 ==
3237 00:22:17.303374 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3238 00:22:17.307088 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3239 00:22:17.309893 == TX Byte 1 ==
3240 00:22:17.313395 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3241 00:22:17.316596 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3242 00:22:17.316685 ==
3243 00:22:17.320164 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 00:22:17.323679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 00:22:17.326831 ==
3246 00:22:17.336898 TX Vref=22, minBit 2, minWin=25, winSum=419
3247 00:22:17.340112 TX Vref=24, minBit 1, minWin=25, winSum=419
3248 00:22:17.343705 TX Vref=26, minBit 0, minWin=26, winSum=425
3249 00:22:17.347095 TX Vref=28, minBit 1, minWin=26, winSum=427
3250 00:22:17.350152 TX Vref=30, minBit 7, minWin=26, winSum=433
3251 00:22:17.353414 TX Vref=32, minBit 1, minWin=26, winSum=430
3252 00:22:17.360233 [TxChooseVref] Worse bit 7, Min win 26, Win sum 433, Final Vref 30
3253 00:22:17.360310
3254 00:22:17.363472 Final TX Range 1 Vref 30
3255 00:22:17.363547
3256 00:22:17.363605 ==
3257 00:22:17.367131 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 00:22:17.370313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 00:22:17.370389 ==
3260 00:22:17.370447
3261 00:22:17.373419
3262 00:22:17.373493 TX Vref Scan disable
3263 00:22:17.377098 == TX Byte 0 ==
3264 00:22:17.380147 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3265 00:22:17.383704 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3266 00:22:17.387272 == TX Byte 1 ==
3267 00:22:17.390149 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3268 00:22:17.393986 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3269 00:22:17.394091
3270 00:22:17.397070 [DATLAT]
3271 00:22:17.397145 Freq=1200, CH1 RK0
3272 00:22:17.397203
3273 00:22:17.400737 DATLAT Default: 0xd
3274 00:22:17.400830 0, 0xFFFF, sum = 0
3275 00:22:17.403850 1, 0xFFFF, sum = 0
3276 00:22:17.403928 2, 0xFFFF, sum = 0
3277 00:22:17.406988 3, 0xFFFF, sum = 0
3278 00:22:17.407064 4, 0xFFFF, sum = 0
3279 00:22:17.410721 5, 0xFFFF, sum = 0
3280 00:22:17.410844 6, 0xFFFF, sum = 0
3281 00:22:17.414127 7, 0xFFFF, sum = 0
3282 00:22:17.414204 8, 0xFFFF, sum = 0
3283 00:22:17.416930 9, 0xFFFF, sum = 0
3284 00:22:17.417006 10, 0xFFFF, sum = 0
3285 00:22:17.420510 11, 0xFFFF, sum = 0
3286 00:22:17.420587 12, 0x0, sum = 1
3287 00:22:17.423607 13, 0x0, sum = 2
3288 00:22:17.423683 14, 0x0, sum = 3
3289 00:22:17.427170 15, 0x0, sum = 4
3290 00:22:17.427271 best_step = 13
3291 00:22:17.427369
3292 00:22:17.427452 ==
3293 00:22:17.430420 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 00:22:17.437250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 00:22:17.437326 ==
3296 00:22:17.437384 RX Vref Scan: 1
3297 00:22:17.437438
3298 00:22:17.440954 Set Vref Range= 32 -> 127
3299 00:22:17.441029
3300 00:22:17.444205 RX Vref 32 -> 127, step: 1
3301 00:22:17.444279
3302 00:22:17.444337 RX Delay -21 -> 252, step: 4
3303 00:22:17.447157
3304 00:22:17.447232 Set Vref, RX VrefLevel [Byte0]: 32
3305 00:22:17.450761 [Byte1]: 32
3306 00:22:17.454932
3307 00:22:17.455021 Set Vref, RX VrefLevel [Byte0]: 33
3308 00:22:17.458652 [Byte1]: 33
3309 00:22:17.462937
3310 00:22:17.463036 Set Vref, RX VrefLevel [Byte0]: 34
3311 00:22:17.466200 [Byte1]: 34
3312 00:22:17.471155
3313 00:22:17.471229 Set Vref, RX VrefLevel [Byte0]: 35
3314 00:22:17.474293 [Byte1]: 35
3315 00:22:17.479254
3316 00:22:17.479334 Set Vref, RX VrefLevel [Byte0]: 36
3317 00:22:17.482506 [Byte1]: 36
3318 00:22:17.486742
3319 00:22:17.486817 Set Vref, RX VrefLevel [Byte0]: 37
3320 00:22:17.490255 [Byte1]: 37
3321 00:22:17.494560
3322 00:22:17.494635 Set Vref, RX VrefLevel [Byte0]: 38
3323 00:22:17.498213 [Byte1]: 38
3324 00:22:17.502656
3325 00:22:17.502729 Set Vref, RX VrefLevel [Byte0]: 39
3326 00:22:17.506059 [Byte1]: 39
3327 00:22:17.510345
3328 00:22:17.510420 Set Vref, RX VrefLevel [Byte0]: 40
3329 00:22:17.514121 [Byte1]: 40
3330 00:22:17.518593
3331 00:22:17.518699 Set Vref, RX VrefLevel [Byte0]: 41
3332 00:22:17.521642 [Byte1]: 41
3333 00:22:17.526618
3334 00:22:17.526696 Set Vref, RX VrefLevel [Byte0]: 42
3335 00:22:17.530220 [Byte1]: 42
3336 00:22:17.534500
3337 00:22:17.534574 Set Vref, RX VrefLevel [Byte0]: 43
3338 00:22:17.537770 [Byte1]: 43
3339 00:22:17.542360
3340 00:22:17.542447 Set Vref, RX VrefLevel [Byte0]: 44
3341 00:22:17.545579 [Byte1]: 44
3342 00:22:17.549914
3343 00:22:17.550012 Set Vref, RX VrefLevel [Byte0]: 45
3344 00:22:17.553555 [Byte1]: 45
3345 00:22:17.557779
3346 00:22:17.557860 Set Vref, RX VrefLevel [Byte0]: 46
3347 00:22:17.561400 [Byte1]: 46
3348 00:22:17.565742
3349 00:22:17.565807 Set Vref, RX VrefLevel [Byte0]: 47
3350 00:22:17.569600 [Byte1]: 47
3351 00:22:17.573845
3352 00:22:17.573933 Set Vref, RX VrefLevel [Byte0]: 48
3353 00:22:17.577185 [Byte1]: 48
3354 00:22:17.581873
3355 00:22:17.581964 Set Vref, RX VrefLevel [Byte0]: 49
3356 00:22:17.584952 [Byte1]: 49
3357 00:22:17.589900
3358 00:22:17.590014 Set Vref, RX VrefLevel [Byte0]: 50
3359 00:22:17.592972 [Byte1]: 50
3360 00:22:17.597849
3361 00:22:17.597928 Set Vref, RX VrefLevel [Byte0]: 51
3362 00:22:17.600862 [Byte1]: 51
3363 00:22:17.605791
3364 00:22:17.605865 Set Vref, RX VrefLevel [Byte0]: 52
3365 00:22:17.608744 [Byte1]: 52
3366 00:22:17.613270
3367 00:22:17.613346 Set Vref, RX VrefLevel [Byte0]: 53
3368 00:22:17.617247 [Byte1]: 53
3369 00:22:17.621256
3370 00:22:17.621332 Set Vref, RX VrefLevel [Byte0]: 54
3371 00:22:17.625066 [Byte1]: 54
3372 00:22:17.629374
3373 00:22:17.629450 Set Vref, RX VrefLevel [Byte0]: 55
3374 00:22:17.632501 [Byte1]: 55
3375 00:22:17.637426
3376 00:22:17.637510 Set Vref, RX VrefLevel [Byte0]: 56
3377 00:22:17.640491 [Byte1]: 56
3378 00:22:17.645247
3379 00:22:17.645324 Set Vref, RX VrefLevel [Byte0]: 57
3380 00:22:17.648851 [Byte1]: 57
3381 00:22:17.652916
3382 00:22:17.652994 Set Vref, RX VrefLevel [Byte0]: 58
3383 00:22:17.656397 [Byte1]: 58
3384 00:22:17.660858
3385 00:22:17.660936 Set Vref, RX VrefLevel [Byte0]: 59
3386 00:22:17.664432 [Byte1]: 59
3387 00:22:17.668834
3388 00:22:17.668913 Set Vref, RX VrefLevel [Byte0]: 60
3389 00:22:17.672441 [Byte1]: 60
3390 00:22:17.676921
3391 00:22:17.676998 Set Vref, RX VrefLevel [Byte0]: 61
3392 00:22:17.680548 [Byte1]: 61
3393 00:22:17.684870
3394 00:22:17.684948 Set Vref, RX VrefLevel [Byte0]: 62
3395 00:22:17.688071 [Byte1]: 62
3396 00:22:17.692500
3397 00:22:17.692577 Set Vref, RX VrefLevel [Byte0]: 63
3398 00:22:17.696083 [Byte1]: 63
3399 00:22:17.700781
3400 00:22:17.700860 Set Vref, RX VrefLevel [Byte0]: 64
3401 00:22:17.703885 [Byte1]: 64
3402 00:22:17.708850
3403 00:22:17.708928 Set Vref, RX VrefLevel [Byte0]: 65
3404 00:22:17.712001 [Byte1]: 65
3405 00:22:17.716386
3406 00:22:17.716487 Set Vref, RX VrefLevel [Byte0]: 66
3407 00:22:17.719973 [Byte1]: 66
3408 00:22:17.724414
3409 00:22:17.724485 Set Vref, RX VrefLevel [Byte0]: 67
3410 00:22:17.727860 [Byte1]: 67
3411 00:22:17.732139
3412 00:22:17.732217 Final RX Vref Byte 0 = 55 to rank0
3413 00:22:17.735846 Final RX Vref Byte 1 = 50 to rank0
3414 00:22:17.738798 Final RX Vref Byte 0 = 55 to rank1
3415 00:22:17.742373 Final RX Vref Byte 1 = 50 to rank1==
3416 00:22:17.745416 Dram Type= 6, Freq= 0, CH_1, rank 0
3417 00:22:17.749293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3418 00:22:17.752292 ==
3419 00:22:17.752369 DQS Delay:
3420 00:22:17.752429 DQS0 = 0, DQS1 = 0
3421 00:22:17.756009 DQM Delay:
3422 00:22:17.756087 DQM0 = 115, DQM1 = 108
3423 00:22:17.758945 DQ Delay:
3424 00:22:17.762427 DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =112
3425 00:22:17.765862 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =112
3426 00:22:17.769377 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3427 00:22:17.772866 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =114
3428 00:22:17.772967
3429 00:22:17.773064
3430 00:22:17.779122 [DQSOSCAuto] RK0, (LSB)MR18= 0xfee2, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
3431 00:22:17.782274 CH1 RK0: MR19=303, MR18=FEE2
3432 00:22:17.789006 CH1_RK0: MR19=0x303, MR18=0xFEE2, DQSOSC=410, MR23=63, INC=39, DEC=26
3433 00:22:17.789080
3434 00:22:17.792778 ----->DramcWriteLeveling(PI) begin...
3435 00:22:17.792877 ==
3436 00:22:17.795869 Dram Type= 6, Freq= 0, CH_1, rank 1
3437 00:22:17.799347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3438 00:22:17.799441 ==
3439 00:22:17.802167 Write leveling (Byte 0): 26 => 26
3440 00:22:17.805807 Write leveling (Byte 1): 28 => 28
3441 00:22:17.808961 DramcWriteLeveling(PI) end<-----
3442 00:22:17.809050
3443 00:22:17.809109 ==
3444 00:22:17.812634 Dram Type= 6, Freq= 0, CH_1, rank 1
3445 00:22:17.818931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3446 00:22:17.819021 ==
3447 00:22:17.819105 [Gating] SW mode calibration
3448 00:22:17.829419 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3449 00:22:17.832482 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3450 00:22:17.835556 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3451 00:22:17.842585 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 00:22:17.845652 0 15 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3453 00:22:17.849133 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 00:22:17.856115 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 00:22:17.859217 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3456 00:22:17.862314 0 15 24 | B1->B0 | 3434 2727 | 0 0 | (0 0) (0 1)
3457 00:22:17.868952 0 15 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
3458 00:22:17.872662 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 00:22:17.875618 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 00:22:17.882877 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 00:22:17.886199 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 00:22:17.889574 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 00:22:17.892467 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3464 00:22:17.899335 1 0 24 | B1->B0 | 2525 3f3f | 0 0 | (0 0) (0 0)
3465 00:22:17.902478 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3466 00:22:17.906181 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 00:22:17.912822 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 00:22:17.915923 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 00:22:17.919617 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 00:22:17.925939 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 00:22:17.929553 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3472 00:22:17.932566 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3473 00:22:17.939263 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3474 00:22:17.942826 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 00:22:17.946412 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 00:22:17.952996 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 00:22:17.956129 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 00:22:17.959212 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 00:22:17.966044 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 00:22:17.969596 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 00:22:17.972629 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 00:22:17.976398 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 00:22:17.983029 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 00:22:17.986624 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 00:22:17.989650 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 00:22:17.996153 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 00:22:17.999605 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3488 00:22:18.003070 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3489 00:22:18.009668 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3490 00:22:18.009767 Total UI for P1: 0, mck2ui 16
3491 00:22:18.016133 best dqsien dly found for B0: ( 1, 3, 22)
3492 00:22:18.019812 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 00:22:18.023068 Total UI for P1: 0, mck2ui 16
3494 00:22:18.026797 best dqsien dly found for B1: ( 1, 3, 26)
3495 00:22:18.029785 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3496 00:22:18.033517 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3497 00:22:18.033613
3498 00:22:18.036373 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3499 00:22:18.039986 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3500 00:22:18.043086 [Gating] SW calibration Done
3501 00:22:18.043188 ==
3502 00:22:18.046156 Dram Type= 6, Freq= 0, CH_1, rank 1
3503 00:22:18.049865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3504 00:22:18.049968 ==
3505 00:22:18.053298 RX Vref Scan: 0
3506 00:22:18.053389
3507 00:22:18.056241 RX Vref 0 -> 0, step: 1
3508 00:22:18.056333
3509 00:22:18.056416 RX Delay -40 -> 252, step: 8
3510 00:22:18.063139 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3511 00:22:18.066789 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3512 00:22:18.069891 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3513 00:22:18.072973 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3514 00:22:18.076639 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3515 00:22:18.083551 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3516 00:22:18.086660 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3517 00:22:18.090323 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3518 00:22:18.093344 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3519 00:22:18.096888 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3520 00:22:18.100043 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3521 00:22:18.106651 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3522 00:22:18.110185 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3523 00:22:18.113329 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3524 00:22:18.116636 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3525 00:22:18.122894 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3526 00:22:18.122969 ==
3527 00:22:18.126523 Dram Type= 6, Freq= 0, CH_1, rank 1
3528 00:22:18.129732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3529 00:22:18.129825 ==
3530 00:22:18.129907 DQS Delay:
3531 00:22:18.133442 DQS0 = 0, DQS1 = 0
3532 00:22:18.133536 DQM Delay:
3533 00:22:18.136516 DQM0 = 113, DQM1 = 110
3534 00:22:18.136607 DQ Delay:
3535 00:22:18.140126 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =111
3536 00:22:18.143211 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =111
3537 00:22:18.146248 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3538 00:22:18.149923 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3539 00:22:18.150047
3540 00:22:18.150137
3541 00:22:18.150221 ==
3542 00:22:18.153487 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 00:22:18.160050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 00:22:18.160161 ==
3545 00:22:18.160280
3546 00:22:18.160370
3547 00:22:18.160466 TX Vref Scan disable
3548 00:22:18.163732 == TX Byte 0 ==
3549 00:22:18.166873 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3550 00:22:18.173612 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3551 00:22:18.173704 == TX Byte 1 ==
3552 00:22:18.176729 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3553 00:22:18.180459 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3554 00:22:18.183455 ==
3555 00:22:18.186589 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 00:22:18.190308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 00:22:18.190402 ==
3558 00:22:18.201309 TX Vref=22, minBit 1, minWin=25, winSum=414
3559 00:22:18.204708 TX Vref=24, minBit 2, minWin=25, winSum=424
3560 00:22:18.207764 TX Vref=26, minBit 0, minWin=26, winSum=427
3561 00:22:18.211551 TX Vref=28, minBit 0, minWin=26, winSum=427
3562 00:22:18.214422 TX Vref=30, minBit 4, minWin=26, winSum=430
3563 00:22:18.220854 TX Vref=32, minBit 13, minWin=26, winSum=432
3564 00:22:18.224264 [TxChooseVref] Worse bit 13, Min win 26, Win sum 432, Final Vref 32
3565 00:22:18.224344
3566 00:22:18.227744 Final TX Range 1 Vref 32
3567 00:22:18.227822
3568 00:22:18.227898 ==
3569 00:22:18.231417 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 00:22:18.234895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 00:22:18.234975 ==
3572 00:22:18.237848
3573 00:22:18.237966
3574 00:22:18.238057 TX Vref Scan disable
3575 00:22:18.240986 == TX Byte 0 ==
3576 00:22:18.244649 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3577 00:22:18.247661 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3578 00:22:18.251249 == TX Byte 1 ==
3579 00:22:18.254304 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3580 00:22:18.257751 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3581 00:22:18.261471
3582 00:22:18.261574 [DATLAT]
3583 00:22:18.261651 Freq=1200, CH1 RK1
3584 00:22:18.261723
3585 00:22:18.264460 DATLAT Default: 0xd
3586 00:22:18.264537 0, 0xFFFF, sum = 0
3587 00:22:18.267751 1, 0xFFFF, sum = 0
3588 00:22:18.267847 2, 0xFFFF, sum = 0
3589 00:22:18.271417 3, 0xFFFF, sum = 0
3590 00:22:18.271517 4, 0xFFFF, sum = 0
3591 00:22:18.274565 5, 0xFFFF, sum = 0
3592 00:22:18.278151 6, 0xFFFF, sum = 0
3593 00:22:18.278223 7, 0xFFFF, sum = 0
3594 00:22:18.281157 8, 0xFFFF, sum = 0
3595 00:22:18.281232 9, 0xFFFF, sum = 0
3596 00:22:18.284264 10, 0xFFFF, sum = 0
3597 00:22:18.284373 11, 0xFFFF, sum = 0
3598 00:22:18.287998 12, 0x0, sum = 1
3599 00:22:18.288151 13, 0x0, sum = 2
3600 00:22:18.291253 14, 0x0, sum = 3
3601 00:22:18.291355 15, 0x0, sum = 4
3602 00:22:18.291448 best_step = 13
3603 00:22:18.291536
3604 00:22:18.294340 ==
3605 00:22:18.297956 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 00:22:18.301158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 00:22:18.301236 ==
3608 00:22:18.301312 RX Vref Scan: 0
3609 00:22:18.301382
3610 00:22:18.304340 RX Vref 0 -> 0, step: 1
3611 00:22:18.304417
3612 00:22:18.308026 RX Delay -21 -> 252, step: 4
3613 00:22:18.311646 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3614 00:22:18.314789 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3615 00:22:18.321386 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3616 00:22:18.324610 iDelay=191, Bit 3, Center 110 (43 ~ 178) 136
3617 00:22:18.328265 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3618 00:22:18.331322 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3619 00:22:18.334475 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3620 00:22:18.341348 iDelay=191, Bit 7, Center 110 (43 ~ 178) 136
3621 00:22:18.344659 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3622 00:22:18.348196 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3623 00:22:18.351455 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3624 00:22:18.354666 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3625 00:22:18.361347 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3626 00:22:18.364867 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3627 00:22:18.368373 iDelay=191, Bit 14, Center 116 (51 ~ 182) 132
3628 00:22:18.371328 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3629 00:22:18.371404 ==
3630 00:22:18.375033 Dram Type= 6, Freq= 0, CH_1, rank 1
3631 00:22:18.381467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3632 00:22:18.381548 ==
3633 00:22:18.381607 DQS Delay:
3634 00:22:18.381661 DQS0 = 0, DQS1 = 0
3635 00:22:18.385049 DQM Delay:
3636 00:22:18.385125 DQM0 = 113, DQM1 = 109
3637 00:22:18.388063 DQ Delay:
3638 00:22:18.391674 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =110
3639 00:22:18.394809 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3640 00:22:18.397943 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =102
3641 00:22:18.401567 DQ12 =114, DQ13 =120, DQ14 =116, DQ15 =116
3642 00:22:18.401643
3643 00:22:18.401775
3644 00:22:18.408489 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa01, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3645 00:22:18.411475 CH1 RK1: MR19=304, MR18=FA01
3646 00:22:18.418066 CH1_RK1: MR19=0x304, MR18=0xFA01, DQSOSC=409, MR23=63, INC=39, DEC=26
3647 00:22:18.421721 [RxdqsGatingPostProcess] freq 1200
3648 00:22:18.428137 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3649 00:22:18.431235 best DQS0 dly(2T, 0.5T) = (0, 11)
3650 00:22:18.431305 best DQS1 dly(2T, 0.5T) = (0, 12)
3651 00:22:18.435085 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3652 00:22:18.438140 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3653 00:22:18.441431 best DQS0 dly(2T, 0.5T) = (0, 11)
3654 00:22:18.444490 best DQS1 dly(2T, 0.5T) = (0, 11)
3655 00:22:18.448180 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3656 00:22:18.451164 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3657 00:22:18.454387 Pre-setting of DQS Precalculation
3658 00:22:18.461198 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3659 00:22:18.468236 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3660 00:22:18.474853 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3661 00:22:18.474934
3662 00:22:18.475000
3663 00:22:18.478422 [Calibration Summary] 2400 Mbps
3664 00:22:18.478514 CH 0, Rank 0
3665 00:22:18.481606 SW Impedance : PASS
3666 00:22:18.484648 DUTY Scan : NO K
3667 00:22:18.484731 ZQ Calibration : PASS
3668 00:22:18.488333 Jitter Meter : NO K
3669 00:22:18.488428 CBT Training : PASS
3670 00:22:18.491313 Write leveling : PASS
3671 00:22:18.494996 RX DQS gating : PASS
3672 00:22:18.495069 RX DQ/DQS(RDDQC) : PASS
3673 00:22:18.498205 TX DQ/DQS : PASS
3674 00:22:18.501252 RX DATLAT : PASS
3675 00:22:18.501353 RX DQ/DQS(Engine): PASS
3676 00:22:18.504900 TX OE : NO K
3677 00:22:18.504998 All Pass.
3678 00:22:18.505080
3679 00:22:18.508104 CH 0, Rank 1
3680 00:22:18.508203 SW Impedance : PASS
3681 00:22:18.511454 DUTY Scan : NO K
3682 00:22:18.515142 ZQ Calibration : PASS
3683 00:22:18.515233 Jitter Meter : NO K
3684 00:22:18.518381 CBT Training : PASS
3685 00:22:18.521307 Write leveling : PASS
3686 00:22:18.521378 RX DQS gating : PASS
3687 00:22:18.524814 RX DQ/DQS(RDDQC) : PASS
3688 00:22:18.524881 TX DQ/DQS : PASS
3689 00:22:18.528544 RX DATLAT : PASS
3690 00:22:18.531494 RX DQ/DQS(Engine): PASS
3691 00:22:18.531561 TX OE : NO K
3692 00:22:18.534669 All Pass.
3693 00:22:18.534737
3694 00:22:18.534792 CH 1, Rank 0
3695 00:22:18.538349 SW Impedance : PASS
3696 00:22:18.538444 DUTY Scan : NO K
3697 00:22:18.541424 ZQ Calibration : PASS
3698 00:22:18.544563 Jitter Meter : NO K
3699 00:22:18.544665 CBT Training : PASS
3700 00:22:18.548158 Write leveling : PASS
3701 00:22:18.551251 RX DQS gating : PASS
3702 00:22:18.551319 RX DQ/DQS(RDDQC) : PASS
3703 00:22:18.554900 TX DQ/DQS : PASS
3704 00:22:18.557851 RX DATLAT : PASS
3705 00:22:18.557918 RX DQ/DQS(Engine): PASS
3706 00:22:18.561387 TX OE : NO K
3707 00:22:18.561457 All Pass.
3708 00:22:18.561512
3709 00:22:18.564922 CH 1, Rank 1
3710 00:22:18.565029 SW Impedance : PASS
3711 00:22:18.567880 DUTY Scan : NO K
3712 00:22:18.571623 ZQ Calibration : PASS
3713 00:22:18.571718 Jitter Meter : NO K
3714 00:22:18.574844 CBT Training : PASS
3715 00:22:18.574935 Write leveling : PASS
3716 00:22:18.578283 RX DQS gating : PASS
3717 00:22:18.581732 RX DQ/DQS(RDDQC) : PASS
3718 00:22:18.581800 TX DQ/DQS : PASS
3719 00:22:18.584897 RX DATLAT : PASS
3720 00:22:18.587947 RX DQ/DQS(Engine): PASS
3721 00:22:18.588013 TX OE : NO K
3722 00:22:18.591397 All Pass.
3723 00:22:18.591480
3724 00:22:18.591537 DramC Write-DBI off
3725 00:22:18.594643 PER_BANK_REFRESH: Hybrid Mode
3726 00:22:18.594714 TX_TRACKING: ON
3727 00:22:18.604940 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3728 00:22:18.608222 [FAST_K] Save calibration result to emmc
3729 00:22:18.611812 dramc_set_vcore_voltage set vcore to 650000
3730 00:22:18.614898 Read voltage for 600, 5
3731 00:22:18.614993 Vio18 = 0
3732 00:22:18.617971 Vcore = 650000
3733 00:22:18.618096 Vdram = 0
3734 00:22:18.618180 Vddq = 0
3735 00:22:18.618261 Vmddr = 0
3736 00:22:18.624804 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3737 00:22:18.631494 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3738 00:22:18.631562 MEM_TYPE=3, freq_sel=19
3739 00:22:18.635239 sv_algorithm_assistance_LP4_1600
3740 00:22:18.638462 ============ PULL DRAM RESETB DOWN ============
3741 00:22:18.645335 ========== PULL DRAM RESETB DOWN end =========
3742 00:22:18.648449 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3743 00:22:18.651369 ===================================
3744 00:22:18.655119 LPDDR4 DRAM CONFIGURATION
3745 00:22:18.658371 ===================================
3746 00:22:18.658444 EX_ROW_EN[0] = 0x0
3747 00:22:18.661515 EX_ROW_EN[1] = 0x0
3748 00:22:18.661579 LP4Y_EN = 0x0
3749 00:22:18.665018 WORK_FSP = 0x0
3750 00:22:18.665081 WL = 0x2
3751 00:22:18.668599 RL = 0x2
3752 00:22:18.668664 BL = 0x2
3753 00:22:18.671505 RPST = 0x0
3754 00:22:18.675157 RD_PRE = 0x0
3755 00:22:18.675220 WR_PRE = 0x1
3756 00:22:18.678754 WR_PST = 0x0
3757 00:22:18.678852 DBI_WR = 0x0
3758 00:22:18.681523 DBI_RD = 0x0
3759 00:22:18.681588 OTF = 0x1
3760 00:22:18.685028 ===================================
3761 00:22:18.688194 ===================================
3762 00:22:18.688282 ANA top config
3763 00:22:18.691844 ===================================
3764 00:22:18.695049 DLL_ASYNC_EN = 0
3765 00:22:18.698598 ALL_SLAVE_EN = 1
3766 00:22:18.701721 NEW_RANK_MODE = 1
3767 00:22:18.705195 DLL_IDLE_MODE = 1
3768 00:22:18.705264 LP45_APHY_COMB_EN = 1
3769 00:22:18.708534 TX_ODT_DIS = 1
3770 00:22:18.711713 NEW_8X_MODE = 1
3771 00:22:18.715082 ===================================
3772 00:22:18.718403 ===================================
3773 00:22:18.721935 data_rate = 1200
3774 00:22:18.724991 CKR = 1
3775 00:22:18.725082 DQ_P2S_RATIO = 8
3776 00:22:18.728192 ===================================
3777 00:22:18.732060 CA_P2S_RATIO = 8
3778 00:22:18.734946 DQ_CA_OPEN = 0
3779 00:22:18.738610 DQ_SEMI_OPEN = 0
3780 00:22:18.741556 CA_SEMI_OPEN = 0
3781 00:22:18.744872 CA_FULL_RATE = 0
3782 00:22:18.744984 DQ_CKDIV4_EN = 1
3783 00:22:18.748654 CA_CKDIV4_EN = 1
3784 00:22:18.751591 CA_PREDIV_EN = 0
3785 00:22:18.755462 PH8_DLY = 0
3786 00:22:18.758505 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3787 00:22:18.758581 DQ_AAMCK_DIV = 4
3788 00:22:18.761503 CA_AAMCK_DIV = 4
3789 00:22:18.765268 CA_ADMCK_DIV = 4
3790 00:22:18.768803 DQ_TRACK_CA_EN = 0
3791 00:22:18.773681 CA_PICK = 600
3792 00:22:18.774818 CA_MCKIO = 600
3793 00:22:18.778529 MCKIO_SEMI = 0
3794 00:22:18.778606 PLL_FREQ = 2288
3795 00:22:18.781892 DQ_UI_PI_RATIO = 32
3796 00:22:18.784929 CA_UI_PI_RATIO = 0
3797 00:22:18.788331 ===================================
3798 00:22:18.791620 ===================================
3799 00:22:18.794819 memory_type:LPDDR4
3800 00:22:18.794923 GP_NUM : 10
3801 00:22:18.798748 SRAM_EN : 1
3802 00:22:18.801634 MD32_EN : 0
3803 00:22:18.805388 ===================================
3804 00:22:18.805465 [ANA_INIT] >>>>>>>>>>>>>>
3805 00:22:18.808420 <<<<<< [CONFIGURE PHASE]: ANA_TX
3806 00:22:18.812285 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3807 00:22:18.815152 ===================================
3808 00:22:18.818569 data_rate = 1200,PCW = 0X5800
3809 00:22:18.821864 ===================================
3810 00:22:18.825290 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3811 00:22:18.832036 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3812 00:22:18.835035 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3813 00:22:18.841859 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3814 00:22:18.844994 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3815 00:22:18.848780 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3816 00:22:18.848883 [ANA_INIT] flow start
3817 00:22:18.851783 [ANA_INIT] PLL >>>>>>>>
3818 00:22:18.855233 [ANA_INIT] PLL <<<<<<<<
3819 00:22:18.858310 [ANA_INIT] MIDPI >>>>>>>>
3820 00:22:18.858387 [ANA_INIT] MIDPI <<<<<<<<
3821 00:22:18.861601 [ANA_INIT] DLL >>>>>>>>
3822 00:22:18.861700 [ANA_INIT] flow end
3823 00:22:18.868820 ============ LP4 DIFF to SE enter ============
3824 00:22:18.871765 ============ LP4 DIFF to SE exit ============
3825 00:22:18.875309 [ANA_INIT] <<<<<<<<<<<<<
3826 00:22:18.878449 [Flow] Enable top DCM control >>>>>
3827 00:22:18.881490 [Flow] Enable top DCM control <<<<<
3828 00:22:18.885356 Enable DLL master slave shuffle
3829 00:22:18.888359 ==============================================================
3830 00:22:18.891486 Gating Mode config
3831 00:22:18.895187 ==============================================================
3832 00:22:18.898096 Config description:
3833 00:22:18.908070 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3834 00:22:18.914976 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3835 00:22:18.918131 SELPH_MODE 0: By rank 1: By Phase
3836 00:22:18.924660 ==============================================================
3837 00:22:18.928172 GAT_TRACK_EN = 1
3838 00:22:18.931518 RX_GATING_MODE = 2
3839 00:22:18.935129 RX_GATING_TRACK_MODE = 2
3840 00:22:18.938425 SELPH_MODE = 1
3841 00:22:18.938498 PICG_EARLY_EN = 1
3842 00:22:18.941699 VALID_LAT_VALUE = 1
3843 00:22:18.948532 ==============================================================
3844 00:22:18.951504 Enter into Gating configuration >>>>
3845 00:22:18.954758 Exit from Gating configuration <<<<
3846 00:22:18.958232 Enter into DVFS_PRE_config >>>>>
3847 00:22:18.968455 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3848 00:22:18.971553 Exit from DVFS_PRE_config <<<<<
3849 00:22:18.974746 Enter into PICG configuration >>>>
3850 00:22:18.978537 Exit from PICG configuration <<<<
3851 00:22:18.981439 [RX_INPUT] configuration >>>>>
3852 00:22:18.985206 [RX_INPUT] configuration <<<<<
3853 00:22:18.988334 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3854 00:22:18.995250 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3855 00:22:19.001605 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3856 00:22:19.008758 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3857 00:22:19.011799 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3858 00:22:19.018424 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3859 00:22:19.022009 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3860 00:22:19.028240 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3861 00:22:19.031745 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3862 00:22:19.035363 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3863 00:22:19.038275 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3864 00:22:19.045000 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3865 00:22:19.048748 ===================================
3866 00:22:19.048847 LPDDR4 DRAM CONFIGURATION
3867 00:22:19.051764 ===================================
3868 00:22:19.055372 EX_ROW_EN[0] = 0x0
3869 00:22:19.058472 EX_ROW_EN[1] = 0x0
3870 00:22:19.058558 LP4Y_EN = 0x0
3871 00:22:19.061686 WORK_FSP = 0x0
3872 00:22:19.061775 WL = 0x2
3873 00:22:19.065283 RL = 0x2
3874 00:22:19.065349 BL = 0x2
3875 00:22:19.068293 RPST = 0x0
3876 00:22:19.068381 RD_PRE = 0x0
3877 00:22:19.071928 WR_PRE = 0x1
3878 00:22:19.072022 WR_PST = 0x0
3879 00:22:19.074981 DBI_WR = 0x0
3880 00:22:19.075071 DBI_RD = 0x0
3881 00:22:19.078658 OTF = 0x1
3882 00:22:19.081623 ===================================
3883 00:22:19.085490 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3884 00:22:19.088432 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3885 00:22:19.095375 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3886 00:22:19.098442 ===================================
3887 00:22:19.098544 LPDDR4 DRAM CONFIGURATION
3888 00:22:19.102282 ===================================
3889 00:22:19.105233 EX_ROW_EN[0] = 0x10
3890 00:22:19.105325 EX_ROW_EN[1] = 0x0
3891 00:22:19.108294 LP4Y_EN = 0x0
3892 00:22:19.111982 WORK_FSP = 0x0
3893 00:22:19.112074 WL = 0x2
3894 00:22:19.115442 RL = 0x2
3895 00:22:19.115534 BL = 0x2
3896 00:22:19.118534 RPST = 0x0
3897 00:22:19.118626 RD_PRE = 0x0
3898 00:22:19.122071 WR_PRE = 0x1
3899 00:22:19.122164 WR_PST = 0x0
3900 00:22:19.125072 DBI_WR = 0x0
3901 00:22:19.125163 DBI_RD = 0x0
3902 00:22:19.128923 OTF = 0x1
3903 00:22:19.132253 ===================================
3904 00:22:19.135384 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3905 00:22:19.141053 nWR fixed to 30
3906 00:22:19.143977 [ModeRegInit_LP4] CH0 RK0
3907 00:22:19.144057 [ModeRegInit_LP4] CH0 RK1
3908 00:22:19.147298 [ModeRegInit_LP4] CH1 RK0
3909 00:22:19.150918 [ModeRegInit_LP4] CH1 RK1
3910 00:22:19.151014 match AC timing 17
3911 00:22:19.157469 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3912 00:22:19.161017 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3913 00:22:19.164072 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3914 00:22:19.170971 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3915 00:22:19.173979 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3916 00:22:19.174103 ==
3917 00:22:19.177506 Dram Type= 6, Freq= 0, CH_0, rank 0
3918 00:22:19.181063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3919 00:22:19.181136 ==
3920 00:22:19.187676 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3921 00:22:19.194287 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3922 00:22:19.197443 [CA 0] Center 36 (6~66) winsize 61
3923 00:22:19.201051 [CA 1] Center 36 (6~66) winsize 61
3924 00:22:19.204196 [CA 2] Center 34 (4~65) winsize 62
3925 00:22:19.207889 [CA 3] Center 34 (4~65) winsize 62
3926 00:22:19.210876 [CA 4] Center 33 (3~64) winsize 62
3927 00:22:19.214153 [CA 5] Center 33 (3~64) winsize 62
3928 00:22:19.214222
3929 00:22:19.217616 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3930 00:22:19.217708
3931 00:22:19.220647 [CATrainingPosCal] consider 1 rank data
3932 00:22:19.224193 u2DelayCellTimex100 = 270/100 ps
3933 00:22:19.227222 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3934 00:22:19.230977 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3935 00:22:19.234102 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3936 00:22:19.237248 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3937 00:22:19.240855 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3938 00:22:19.244399 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3939 00:22:19.244473
3940 00:22:19.247359 CA PerBit enable=1, Macro0, CA PI delay=33
3941 00:22:19.250790
3942 00:22:19.250880 [CBTSetCACLKResult] CA Dly = 33
3943 00:22:19.254148 CS Dly: 4 (0~35)
3944 00:22:19.254271 ==
3945 00:22:19.257785 Dram Type= 6, Freq= 0, CH_0, rank 1
3946 00:22:19.260879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3947 00:22:19.260948 ==
3948 00:22:19.267524 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3949 00:22:19.274334 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3950 00:22:19.278078 [CA 0] Center 36 (6~66) winsize 61
3951 00:22:19.281368 [CA 1] Center 36 (6~66) winsize 61
3952 00:22:19.284291 [CA 2] Center 34 (4~65) winsize 62
3953 00:22:19.287581 [CA 3] Center 34 (4~65) winsize 62
3954 00:22:19.291106 [CA 4] Center 33 (3~64) winsize 62
3955 00:22:19.294724 [CA 5] Center 33 (3~64) winsize 62
3956 00:22:19.294816
3957 00:22:19.297871 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3958 00:22:19.297965
3959 00:22:19.300933 [CATrainingPosCal] consider 2 rank data
3960 00:22:19.304584 u2DelayCellTimex100 = 270/100 ps
3961 00:22:19.308160 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3962 00:22:19.311444 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3963 00:22:19.314437 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3964 00:22:19.318328 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3965 00:22:19.321268 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3966 00:22:19.324288 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3967 00:22:19.324399
3968 00:22:19.327902 CA PerBit enable=1, Macro0, CA PI delay=33
3969 00:22:19.327994
3970 00:22:19.331453 [CBTSetCACLKResult] CA Dly = 33
3971 00:22:19.334573 CS Dly: 5 (0~37)
3972 00:22:19.334646
3973 00:22:19.338211 ----->DramcWriteLeveling(PI) begin...
3974 00:22:19.338281 ==
3975 00:22:19.341463 Dram Type= 6, Freq= 0, CH_0, rank 0
3976 00:22:19.344677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3977 00:22:19.344774 ==
3978 00:22:19.348268 Write leveling (Byte 0): 32 => 32
3979 00:22:19.351468 Write leveling (Byte 1): 29 => 29
3980 00:22:19.354565 DramcWriteLeveling(PI) end<-----
3981 00:22:19.354674
3982 00:22:19.354756 ==
3983 00:22:19.358172 Dram Type= 6, Freq= 0, CH_0, rank 0
3984 00:22:19.361144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3985 00:22:19.361215 ==
3986 00:22:19.365019 [Gating] SW mode calibration
3987 00:22:19.371573 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3988 00:22:19.378455 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3989 00:22:19.381538 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3990 00:22:19.385258 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 00:22:19.391251 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3992 00:22:19.394946 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3993 00:22:19.398316 0 9 16 | B1->B0 | 3030 2a2a | 1 0 | (1 1) (0 0)
3994 00:22:19.404585 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 00:22:19.408465 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 00:22:19.411355 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 00:22:19.418223 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 00:22:19.421343 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 00:22:19.425084 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 00:22:19.431771 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 00:22:19.434701 0 10 16 | B1->B0 | 3232 3e3e | 0 0 | (0 0) (1 1)
4002 00:22:19.438261 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4003 00:22:19.444884 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 00:22:19.447989 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 00:22:19.451733 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 00:22:19.458493 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 00:22:19.461616 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 00:22:19.464611 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 00:22:19.468094 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4010 00:22:19.474624 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 00:22:19.478202 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 00:22:19.481267 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 00:22:19.488011 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 00:22:19.491870 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 00:22:19.495043 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 00:22:19.501840 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 00:22:19.504833 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 00:22:19.508371 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 00:22:19.514688 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 00:22:19.518032 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 00:22:19.521648 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 00:22:19.528581 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 00:22:19.531628 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 00:22:19.535207 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4025 00:22:19.541617 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4026 00:22:19.541698 Total UI for P1: 0, mck2ui 16
4027 00:22:19.545224 best dqsien dly found for B0: ( 0, 13, 12)
4028 00:22:19.551858 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 00:22:19.554992 Total UI for P1: 0, mck2ui 16
4030 00:22:19.558457 best dqsien dly found for B1: ( 0, 13, 16)
4031 00:22:19.561635 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4032 00:22:19.564689 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4033 00:22:19.564802
4034 00:22:19.568580 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4035 00:22:19.571541 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4036 00:22:19.574967 [Gating] SW calibration Done
4037 00:22:19.575044 ==
4038 00:22:19.578384 Dram Type= 6, Freq= 0, CH_0, rank 0
4039 00:22:19.581494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4040 00:22:19.581573 ==
4041 00:22:19.585108 RX Vref Scan: 0
4042 00:22:19.585185
4043 00:22:19.588134 RX Vref 0 -> 0, step: 1
4044 00:22:19.588224
4045 00:22:19.588284 RX Delay -230 -> 252, step: 16
4046 00:22:19.594866 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4047 00:22:19.598017 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4048 00:22:19.601750 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4049 00:22:19.604956 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4050 00:22:19.611640 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4051 00:22:19.614741 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4052 00:22:19.617892 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4053 00:22:19.621557 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4054 00:22:19.625016 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4055 00:22:19.631354 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4056 00:22:19.634946 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4057 00:22:19.638616 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4058 00:22:19.641652 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4059 00:22:19.648121 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4060 00:22:19.651549 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4061 00:22:19.655137 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4062 00:22:19.655241 ==
4063 00:22:19.658203 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 00:22:19.661875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 00:22:19.661952 ==
4066 00:22:19.664800 DQS Delay:
4067 00:22:19.664876 DQS0 = 0, DQS1 = 0
4068 00:22:19.668598 DQM Delay:
4069 00:22:19.668674 DQM0 = 47, DQM1 = 36
4070 00:22:19.668732 DQ Delay:
4071 00:22:19.671688 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4072 00:22:19.674852 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4073 00:22:19.678560 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4074 00:22:19.681895 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4075 00:22:19.682032
4076 00:22:19.682096
4077 00:22:19.684934 ==
4078 00:22:19.685036 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 00:22:19.691737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 00:22:19.691814 ==
4081 00:22:19.691873
4082 00:22:19.691927
4083 00:22:19.695317 TX Vref Scan disable
4084 00:22:19.695394 == TX Byte 0 ==
4085 00:22:19.698528 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4086 00:22:19.704758 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4087 00:22:19.704835 == TX Byte 1 ==
4088 00:22:19.708450 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4089 00:22:19.715243 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4090 00:22:19.715323 ==
4091 00:22:19.718243 Dram Type= 6, Freq= 0, CH_0, rank 0
4092 00:22:19.721943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4093 00:22:19.722036 ==
4094 00:22:19.722109
4095 00:22:19.722164
4096 00:22:19.725181 TX Vref Scan disable
4097 00:22:19.728175 == TX Byte 0 ==
4098 00:22:19.731872 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4099 00:22:19.735351 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4100 00:22:19.738760 == TX Byte 1 ==
4101 00:22:19.741910 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4102 00:22:19.745205 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4103 00:22:19.745281
4104 00:22:19.748437 [DATLAT]
4105 00:22:19.748551 Freq=600, CH0 RK0
4106 00:22:19.748609
4107 00:22:19.752109 DATLAT Default: 0x9
4108 00:22:19.752197 0, 0xFFFF, sum = 0
4109 00:22:19.755033 1, 0xFFFF, sum = 0
4110 00:22:19.755109 2, 0xFFFF, sum = 0
4111 00:22:19.758597 3, 0xFFFF, sum = 0
4112 00:22:19.758699 4, 0xFFFF, sum = 0
4113 00:22:19.761547 5, 0xFFFF, sum = 0
4114 00:22:19.761642 6, 0xFFFF, sum = 0
4115 00:22:19.764981 7, 0xFFFF, sum = 0
4116 00:22:19.765058 8, 0x0, sum = 1
4117 00:22:19.768606 9, 0x0, sum = 2
4118 00:22:19.768719 10, 0x0, sum = 3
4119 00:22:19.771629 11, 0x0, sum = 4
4120 00:22:19.771735 best_step = 9
4121 00:22:19.771793
4122 00:22:19.771847 ==
4123 00:22:19.775449 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 00:22:19.778400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 00:22:19.778466 ==
4126 00:22:19.781718 RX Vref Scan: 1
4127 00:22:19.781785
4128 00:22:19.785164 RX Vref 0 -> 0, step: 1
4129 00:22:19.785229
4130 00:22:19.785286 RX Delay -195 -> 252, step: 8
4131 00:22:19.785339
4132 00:22:19.788655 Set Vref, RX VrefLevel [Byte0]: 52
4133 00:22:19.791576 [Byte1]: 51
4134 00:22:19.796300
4135 00:22:19.796377 Final RX Vref Byte 0 = 52 to rank0
4136 00:22:19.799880 Final RX Vref Byte 1 = 51 to rank0
4137 00:22:19.802982 Final RX Vref Byte 0 = 52 to rank1
4138 00:22:19.806704 Final RX Vref Byte 1 = 51 to rank1==
4139 00:22:19.809742 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 00:22:19.816772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 00:22:19.816856 ==
4142 00:22:19.816917 DQS Delay:
4143 00:22:19.816975 DQS0 = 0, DQS1 = 0
4144 00:22:19.819642 DQM Delay:
4145 00:22:19.819718 DQM0 = 42, DQM1 = 33
4146 00:22:19.823340 DQ Delay:
4147 00:22:19.826295 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4148 00:22:19.826369 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4149 00:22:19.829547 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4150 00:22:19.833468 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4151 00:22:19.836254
4152 00:22:19.836325
4153 00:22:19.843111 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a28, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 395 ps
4154 00:22:19.846149 CH0 RK0: MR19=808, MR18=4A28
4155 00:22:19.853087 CH0_RK0: MR19=0x808, MR18=0x4A28, DQSOSC=395, MR23=63, INC=168, DEC=112
4156 00:22:19.853169
4157 00:22:19.856250 ----->DramcWriteLeveling(PI) begin...
4158 00:22:19.856329 ==
4159 00:22:19.859823 Dram Type= 6, Freq= 0, CH_0, rank 1
4160 00:22:19.862826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 00:22:19.862905 ==
4162 00:22:19.866374 Write leveling (Byte 0): 35 => 35
4163 00:22:19.869772 Write leveling (Byte 1): 31 => 31
4164 00:22:19.872749 DramcWriteLeveling(PI) end<-----
4165 00:22:19.872827
4166 00:22:19.872887 ==
4167 00:22:19.876520 Dram Type= 6, Freq= 0, CH_0, rank 1
4168 00:22:19.879582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 00:22:19.879661 ==
4170 00:22:19.882767 [Gating] SW mode calibration
4171 00:22:19.889595 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4172 00:22:19.896035 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4173 00:22:19.899734 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4174 00:22:19.903009 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 00:22:19.909429 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 00:22:19.912532 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
4177 00:22:19.916150 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4178 00:22:19.923074 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 00:22:19.925975 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 00:22:19.929704 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 00:22:19.935952 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 00:22:19.939646 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 00:22:19.942685 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 00:22:19.949530 0 10 12 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
4185 00:22:19.952574 0 10 16 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
4186 00:22:19.956434 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 00:22:19.963212 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 00:22:19.966232 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 00:22:19.969833 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 00:22:19.976367 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 00:22:19.979660 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 00:22:19.983100 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4193 00:22:19.986353 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 00:22:19.993219 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 00:22:19.996227 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 00:22:19.999683 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 00:22:20.006197 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 00:22:20.009766 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 00:22:20.013320 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 00:22:20.019412 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 00:22:20.023099 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 00:22:20.026134 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 00:22:20.032769 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 00:22:20.036478 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 00:22:20.039541 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 00:22:20.046180 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 00:22:20.049715 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 00:22:20.052891 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4209 00:22:20.056725 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4210 00:22:20.059848 Total UI for P1: 0, mck2ui 16
4211 00:22:20.062895 best dqsien dly found for B0: ( 0, 13, 12)
4212 00:22:20.070201 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 00:22:20.070270 Total UI for P1: 0, mck2ui 16
4214 00:22:20.076937 best dqsien dly found for B1: ( 0, 13, 16)
4215 00:22:20.079945 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4216 00:22:20.083043 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4217 00:22:20.083132
4218 00:22:20.086384 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4219 00:22:20.089688 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4220 00:22:20.093370 [Gating] SW calibration Done
4221 00:22:20.093465 ==
4222 00:22:20.096438 Dram Type= 6, Freq= 0, CH_0, rank 1
4223 00:22:20.099755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4224 00:22:20.099847 ==
4225 00:22:20.103401 RX Vref Scan: 0
4226 00:22:20.103465
4227 00:22:20.103519 RX Vref 0 -> 0, step: 1
4228 00:22:20.106251
4229 00:22:20.106313 RX Delay -230 -> 252, step: 16
4230 00:22:20.113336 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4231 00:22:20.116336 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4232 00:22:20.120035 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4233 00:22:20.123116 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4234 00:22:20.126377 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4235 00:22:20.133185 iDelay=218, Bit 5, Center 33 (-118 ~ 185) 304
4236 00:22:20.136859 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4237 00:22:20.139902 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4238 00:22:20.143605 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4239 00:22:20.150183 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4240 00:22:20.153286 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4241 00:22:20.157001 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4242 00:22:20.160049 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4243 00:22:20.163211 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4244 00:22:20.169697 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4245 00:22:20.173487 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4246 00:22:20.173563 ==
4247 00:22:20.176601 Dram Type= 6, Freq= 0, CH_0, rank 1
4248 00:22:20.179871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 00:22:20.179947 ==
4250 00:22:20.183485 DQS Delay:
4251 00:22:20.183560 DQS0 = 0, DQS1 = 0
4252 00:22:20.186583 DQM Delay:
4253 00:22:20.186658 DQM0 = 42, DQM1 = 34
4254 00:22:20.186717 DQ Delay:
4255 00:22:20.189713 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4256 00:22:20.193279 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4257 00:22:20.196641 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =25
4258 00:22:20.199648 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4259 00:22:20.199757
4260 00:22:20.199843
4261 00:22:20.199922 ==
4262 00:22:20.203309 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 00:22:20.209993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 00:22:20.210083 ==
4265 00:22:20.210141
4266 00:22:20.210209
4267 00:22:20.210273 TX Vref Scan disable
4268 00:22:20.214199 == TX Byte 0 ==
4269 00:22:20.216799 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4270 00:22:20.224085 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4271 00:22:20.224154 == TX Byte 1 ==
4272 00:22:20.226980 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4273 00:22:20.230438 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4274 00:22:20.234163 ==
4275 00:22:20.237186 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 00:22:20.240284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 00:22:20.240410 ==
4278 00:22:20.240481
4279 00:22:20.240535
4280 00:22:20.244099 TX Vref Scan disable
4281 00:22:20.244186 == TX Byte 0 ==
4282 00:22:20.250890 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4283 00:22:20.253761 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4284 00:22:20.253829 == TX Byte 1 ==
4285 00:22:20.260776 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4286 00:22:20.263873 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4287 00:22:20.263940
4288 00:22:20.263996 [DATLAT]
4289 00:22:20.267473 Freq=600, CH0 RK1
4290 00:22:20.267540
4291 00:22:20.267594 DATLAT Default: 0x9
4292 00:22:20.270530 0, 0xFFFF, sum = 0
4293 00:22:20.270593 1, 0xFFFF, sum = 0
4294 00:22:20.273959 2, 0xFFFF, sum = 0
4295 00:22:20.274052 3, 0xFFFF, sum = 0
4296 00:22:20.277242 4, 0xFFFF, sum = 0
4297 00:22:20.277307 5, 0xFFFF, sum = 0
4298 00:22:20.280959 6, 0xFFFF, sum = 0
4299 00:22:20.281022 7, 0xFFFF, sum = 0
4300 00:22:20.283872 8, 0x0, sum = 1
4301 00:22:20.283941 9, 0x0, sum = 2
4302 00:22:20.287551 10, 0x0, sum = 3
4303 00:22:20.287620 11, 0x0, sum = 4
4304 00:22:20.290572 best_step = 9
4305 00:22:20.290653
4306 00:22:20.290710 ==
4307 00:22:20.293817 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 00:22:20.297405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 00:22:20.297477 ==
4310 00:22:20.301151 RX Vref Scan: 0
4311 00:22:20.301222
4312 00:22:20.301279 RX Vref 0 -> 0, step: 1
4313 00:22:20.301334
4314 00:22:20.303949 RX Delay -195 -> 252, step: 8
4315 00:22:20.311117 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4316 00:22:20.314322 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4317 00:22:20.317453 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4318 00:22:20.320802 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4319 00:22:20.327395 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4320 00:22:20.331193 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4321 00:22:20.334692 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4322 00:22:20.337663 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4323 00:22:20.341176 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4324 00:22:20.347453 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4325 00:22:20.351170 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4326 00:22:20.354274 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4327 00:22:20.357899 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4328 00:22:20.364568 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4329 00:22:20.368212 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4330 00:22:20.371489 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4331 00:22:20.371580 ==
4332 00:22:20.374468 Dram Type= 6, Freq= 0, CH_0, rank 1
4333 00:22:20.378061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 00:22:20.378132 ==
4335 00:22:20.381191 DQS Delay:
4336 00:22:20.381255 DQS0 = 0, DQS1 = 0
4337 00:22:20.384371 DQM Delay:
4338 00:22:20.384458 DQM0 = 39, DQM1 = 32
4339 00:22:20.384540 DQ Delay:
4340 00:22:20.388056 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4341 00:22:20.391636 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =44
4342 00:22:20.394673 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =24
4343 00:22:20.397845 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4344 00:22:20.397952
4345 00:22:20.398068
4346 00:22:20.408239 [DQSOSCAuto] RK1, (LSB)MR18= 0x5235, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4347 00:22:20.411109 CH0 RK1: MR19=808, MR18=5235
4348 00:22:20.414565 CH0_RK1: MR19=0x808, MR18=0x5235, DQSOSC=394, MR23=63, INC=168, DEC=112
4349 00:22:20.417658 [RxdqsGatingPostProcess] freq 600
4350 00:22:20.424367 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4351 00:22:20.428260 Pre-setting of DQS Precalculation
4352 00:22:20.431326 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4353 00:22:20.431390 ==
4354 00:22:20.434351 Dram Type= 6, Freq= 0, CH_1, rank 0
4355 00:22:20.441262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4356 00:22:20.441329 ==
4357 00:22:20.445112 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4358 00:22:20.451010 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4359 00:22:20.454999 [CA 0] Center 35 (5~66) winsize 62
4360 00:22:20.457783 [CA 1] Center 35 (5~66) winsize 62
4361 00:22:20.461284 [CA 2] Center 34 (4~65) winsize 62
4362 00:22:20.464777 [CA 3] Center 33 (3~64) winsize 62
4363 00:22:20.467828 [CA 4] Center 34 (3~65) winsize 63
4364 00:22:20.471460 [CA 5] Center 33 (3~64) winsize 62
4365 00:22:20.471526
4366 00:22:20.474778 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4367 00:22:20.474930
4368 00:22:20.477682 [CATrainingPosCal] consider 1 rank data
4369 00:22:20.481231 u2DelayCellTimex100 = 270/100 ps
4370 00:22:20.484391 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4371 00:22:20.488171 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4372 00:22:20.491111 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4373 00:22:20.497786 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4374 00:22:20.501253 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4375 00:22:20.504922 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4376 00:22:20.504991
4377 00:22:20.507810 CA PerBit enable=1, Macro0, CA PI delay=33
4378 00:22:20.507883
4379 00:22:20.511503 [CBTSetCACLKResult] CA Dly = 33
4380 00:22:20.511574 CS Dly: 5 (0~36)
4381 00:22:20.511631 ==
4382 00:22:20.514541 Dram Type= 6, Freq= 0, CH_1, rank 1
4383 00:22:20.521223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4384 00:22:20.521296 ==
4385 00:22:20.524812 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4386 00:22:20.531040 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4387 00:22:20.534875 [CA 0] Center 35 (5~66) winsize 62
4388 00:22:20.537921 [CA 1] Center 36 (6~66) winsize 61
4389 00:22:20.541675 [CA 2] Center 34 (3~65) winsize 63
4390 00:22:20.544768 [CA 3] Center 34 (3~65) winsize 63
4391 00:22:20.547869 [CA 4] Center 34 (3~65) winsize 63
4392 00:22:20.551535 [CA 5] Center 33 (3~64) winsize 62
4393 00:22:20.551612
4394 00:22:20.554748 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4395 00:22:20.554828
4396 00:22:20.557720 [CATrainingPosCal] consider 2 rank data
4397 00:22:20.561485 u2DelayCellTimex100 = 270/100 ps
4398 00:22:20.564516 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4399 00:22:20.568004 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4400 00:22:20.574688 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4401 00:22:20.577840 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4402 00:22:20.581580 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4403 00:22:20.584782 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4404 00:22:20.584862
4405 00:22:20.588256 CA PerBit enable=1, Macro0, CA PI delay=33
4406 00:22:20.588323
4407 00:22:20.591382 [CBTSetCACLKResult] CA Dly = 33
4408 00:22:20.591456 CS Dly: 5 (0~37)
4409 00:22:20.591513
4410 00:22:20.594283 ----->DramcWriteLeveling(PI) begin...
4411 00:22:20.598026 ==
4412 00:22:20.598123 Dram Type= 6, Freq= 0, CH_1, rank 0
4413 00:22:20.604688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 00:22:20.604763 ==
4415 00:22:20.607768 Write leveling (Byte 0): 28 => 28
4416 00:22:20.611238 Write leveling (Byte 1): 32 => 32
4417 00:22:20.611313 DramcWriteLeveling(PI) end<-----
4418 00:22:20.614910
4419 00:22:20.614982 ==
4420 00:22:20.617935 Dram Type= 6, Freq= 0, CH_1, rank 0
4421 00:22:20.621148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 00:22:20.621236 ==
4423 00:22:20.624820 [Gating] SW mode calibration
4424 00:22:20.631406 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4425 00:22:20.635044 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4426 00:22:20.641481 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4427 00:22:20.644776 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4428 00:22:20.648335 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4429 00:22:20.655015 0 9 12 | B1->B0 | 3333 3333 | 0 0 | (0 0) (0 0)
4430 00:22:20.658095 0 9 16 | B1->B0 | 2a2a 2525 | 0 0 | (1 1) (1 0)
4431 00:22:20.661860 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 00:22:20.668046 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 00:22:20.671515 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 00:22:20.674716 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 00:22:20.681722 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 00:22:20.684515 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 00:22:20.687871 0 10 12 | B1->B0 | 2424 2929 | 1 1 | (0 0) (0 0)
4438 00:22:20.691327 0 10 16 | B1->B0 | 3b3b 3d3d | 0 1 | (0 0) (0 0)
4439 00:22:20.698235 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 00:22:20.701281 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 00:22:20.704957 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 00:22:20.711752 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 00:22:20.714700 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 00:22:20.718267 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 00:22:20.724867 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4446 00:22:20.727986 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 00:22:20.731572 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 00:22:20.738233 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 00:22:20.741327 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 00:22:20.744882 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 00:22:20.751392 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 00:22:20.755068 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 00:22:20.758416 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 00:22:20.764620 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 00:22:20.768171 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 00:22:20.771895 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 00:22:20.778009 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 00:22:20.781788 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 00:22:20.784797 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 00:22:20.788471 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 00:22:20.795049 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4462 00:22:20.798466 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 00:22:20.801907 Total UI for P1: 0, mck2ui 16
4464 00:22:20.805037 best dqsien dly found for B0: ( 0, 13, 12)
4465 00:22:20.808117 Total UI for P1: 0, mck2ui 16
4466 00:22:20.811844 best dqsien dly found for B1: ( 0, 13, 14)
4467 00:22:20.815005 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4468 00:22:20.818120 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4469 00:22:20.818187
4470 00:22:20.821748 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4471 00:22:20.824876 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4472 00:22:20.828467 [Gating] SW calibration Done
4473 00:22:20.828535 ==
4474 00:22:20.831793 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 00:22:20.838573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 00:22:20.838645 ==
4477 00:22:20.838706 RX Vref Scan: 0
4478 00:22:20.838762
4479 00:22:20.841540 RX Vref 0 -> 0, step: 1
4480 00:22:20.841609
4481 00:22:20.844602 RX Delay -230 -> 252, step: 16
4482 00:22:20.848265 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4483 00:22:20.851682 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4484 00:22:20.854742 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4485 00:22:20.861636 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4486 00:22:20.864797 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4487 00:22:20.868639 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4488 00:22:20.871703 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4489 00:22:20.875344 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4490 00:22:20.881573 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4491 00:22:20.885223 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4492 00:22:20.888198 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4493 00:22:20.891759 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4494 00:22:20.898462 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4495 00:22:20.901502 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4496 00:22:20.905130 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4497 00:22:20.908318 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4498 00:22:20.908387 ==
4499 00:22:20.911742 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 00:22:20.917961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 00:22:20.918057 ==
4502 00:22:20.918117 DQS Delay:
4503 00:22:20.921694 DQS0 = 0, DQS1 = 0
4504 00:22:20.921785 DQM Delay:
4505 00:22:20.921867 DQM0 = 45, DQM1 = 32
4506 00:22:20.924727 DQ Delay:
4507 00:22:20.928393 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4508 00:22:20.931518 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =41
4509 00:22:20.934962 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4510 00:22:20.938473 DQ12 =49, DQ13 =41, DQ14 =33, DQ15 =33
4511 00:22:20.938544
4512 00:22:20.938602
4513 00:22:20.938657 ==
4514 00:22:20.941469 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 00:22:20.944956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 00:22:20.945027 ==
4517 00:22:20.945088
4518 00:22:20.945142
4519 00:22:20.948471 TX Vref Scan disable
4520 00:22:20.948539 == TX Byte 0 ==
4521 00:22:20.955467 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4522 00:22:20.958353 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4523 00:22:20.958426 == TX Byte 1 ==
4524 00:22:20.964820 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4525 00:22:20.968093 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4526 00:22:20.968208 ==
4527 00:22:20.971666 Dram Type= 6, Freq= 0, CH_1, rank 0
4528 00:22:20.974690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4529 00:22:20.974763 ==
4530 00:22:20.974822
4531 00:22:20.974880
4532 00:22:20.978534 TX Vref Scan disable
4533 00:22:20.981425 == TX Byte 0 ==
4534 00:22:20.985311 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4535 00:22:20.988257 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4536 00:22:20.991953 == TX Byte 1 ==
4537 00:22:20.995088 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4538 00:22:20.998128 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4539 00:22:21.002041
4540 00:22:21.002143 [DATLAT]
4541 00:22:21.002233 Freq=600, CH1 RK0
4542 00:22:21.002318
4543 00:22:21.005093 DATLAT Default: 0x9
4544 00:22:21.005158 0, 0xFFFF, sum = 0
4545 00:22:21.008197 1, 0xFFFF, sum = 0
4546 00:22:21.008271 2, 0xFFFF, sum = 0
4547 00:22:21.011873 3, 0xFFFF, sum = 0
4548 00:22:21.011946 4, 0xFFFF, sum = 0
4549 00:22:21.015373 5, 0xFFFF, sum = 0
4550 00:22:21.015445 6, 0xFFFF, sum = 0
4551 00:22:21.018359 7, 0xFFFF, sum = 0
4552 00:22:21.018429 8, 0x0, sum = 1
4553 00:22:21.021883 9, 0x0, sum = 2
4554 00:22:21.021979 10, 0x0, sum = 3
4555 00:22:21.025016 11, 0x0, sum = 4
4556 00:22:21.025086 best_step = 9
4557 00:22:21.025147
4558 00:22:21.025201 ==
4559 00:22:21.028650 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 00:22:21.034930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 00:22:21.035002 ==
4562 00:22:21.035060 RX Vref Scan: 1
4563 00:22:21.035119
4564 00:22:21.038593 RX Vref 0 -> 0, step: 1
4565 00:22:21.038661
4566 00:22:21.042181 RX Delay -195 -> 252, step: 8
4567 00:22:21.042274
4568 00:22:21.045375 Set Vref, RX VrefLevel [Byte0]: 55
4569 00:22:21.048227 [Byte1]: 50
4570 00:22:21.048295
4571 00:22:21.051643 Final RX Vref Byte 0 = 55 to rank0
4572 00:22:21.055019 Final RX Vref Byte 1 = 50 to rank0
4573 00:22:21.058786 Final RX Vref Byte 0 = 55 to rank1
4574 00:22:21.061596 Final RX Vref Byte 1 = 50 to rank1==
4575 00:22:21.065150 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 00:22:21.068418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 00:22:21.068504 ==
4578 00:22:21.072151 DQS Delay:
4579 00:22:21.072234 DQS0 = 0, DQS1 = 0
4580 00:22:21.072306 DQM Delay:
4581 00:22:21.075233 DQM0 = 41, DQM1 = 33
4582 00:22:21.075303 DQ Delay:
4583 00:22:21.078468 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4584 00:22:21.082198 DQ4 =44, DQ5 =52, DQ6 =52, DQ7 =36
4585 00:22:21.085296 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4586 00:22:21.088853 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =40
4587 00:22:21.088966
4588 00:22:21.089061
4589 00:22:21.098400 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a0e, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 395 ps
4590 00:22:21.098494 CH1 RK0: MR19=808, MR18=4A0E
4591 00:22:21.105303 CH1_RK0: MR19=0x808, MR18=0x4A0E, DQSOSC=395, MR23=63, INC=168, DEC=112
4592 00:22:21.105385
4593 00:22:21.108337 ----->DramcWriteLeveling(PI) begin...
4594 00:22:21.108412 ==
4595 00:22:21.112131 Dram Type= 6, Freq= 0, CH_1, rank 1
4596 00:22:21.118352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 00:22:21.118434 ==
4598 00:22:21.121854 Write leveling (Byte 0): 30 => 30
4599 00:22:21.125360 Write leveling (Byte 1): 29 => 29
4600 00:22:21.125437 DramcWriteLeveling(PI) end<-----
4601 00:22:21.125497
4602 00:22:21.128432 ==
4603 00:22:21.128508 Dram Type= 6, Freq= 0, CH_1, rank 1
4604 00:22:21.135277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4605 00:22:21.135355 ==
4606 00:22:21.139063 [Gating] SW mode calibration
4607 00:22:21.145707 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4608 00:22:21.148653 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4609 00:22:21.155613 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4610 00:22:21.158683 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4611 00:22:21.161966 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
4612 00:22:21.168658 0 9 12 | B1->B0 | 3030 2f2f | 1 1 | (1 1) (1 0)
4613 00:22:21.172317 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4614 00:22:21.175202 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 00:22:21.178587 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 00:22:21.185238 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4617 00:22:21.188983 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 00:22:21.192015 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 00:22:21.198881 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4620 00:22:21.202335 0 10 12 | B1->B0 | 3030 3c3c | 0 1 | (1 1) (1 1)
4621 00:22:21.205427 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
4622 00:22:21.212283 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 00:22:21.215468 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 00:22:21.218527 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 00:22:21.225292 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 00:22:21.228884 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 00:22:21.232500 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 00:22:21.239124 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4629 00:22:21.242198 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 00:22:21.245879 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 00:22:21.248778 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 00:22:21.255747 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 00:22:21.258704 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 00:22:21.265558 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 00:22:21.268624 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 00:22:21.272176 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 00:22:21.275675 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 00:22:21.282430 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 00:22:21.285572 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 00:22:21.288817 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 00:22:21.295880 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 00:22:21.298622 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 00:22:21.302278 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 00:22:21.308910 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4645 00:22:21.311989 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4646 00:22:21.315694 Total UI for P1: 0, mck2ui 16
4647 00:22:21.318920 best dqsien dly found for B0: ( 0, 13, 12)
4648 00:22:21.322041 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 00:22:21.325836 Total UI for P1: 0, mck2ui 16
4650 00:22:21.328947 best dqsien dly found for B1: ( 0, 13, 16)
4651 00:22:21.332425 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4652 00:22:21.335679 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4653 00:22:21.335756
4654 00:22:21.342366 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4655 00:22:21.345428 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4656 00:22:21.345505 [Gating] SW calibration Done
4657 00:22:21.349225 ==
4658 00:22:21.352157 Dram Type= 6, Freq= 0, CH_1, rank 1
4659 00:22:21.355229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 00:22:21.355331 ==
4661 00:22:21.355417 RX Vref Scan: 0
4662 00:22:21.355500
4663 00:22:21.358898 RX Vref 0 -> 0, step: 1
4664 00:22:21.358976
4665 00:22:21.362102 RX Delay -230 -> 252, step: 16
4666 00:22:21.365165 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4667 00:22:21.368800 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4668 00:22:21.375720 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4669 00:22:21.378780 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4670 00:22:21.381874 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4671 00:22:21.385795 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4672 00:22:21.388608 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4673 00:22:21.395552 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4674 00:22:21.398860 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4675 00:22:21.402022 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4676 00:22:21.405164 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4677 00:22:21.412071 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4678 00:22:21.415260 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4679 00:22:21.418523 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4680 00:22:21.421825 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4681 00:22:21.428728 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4682 00:22:21.428828 ==
4683 00:22:21.432410 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 00:22:21.435465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 00:22:21.435564 ==
4686 00:22:21.435680 DQS Delay:
4687 00:22:21.438522 DQS0 = 0, DQS1 = 0
4688 00:22:21.438601 DQM Delay:
4689 00:22:21.442190 DQM0 = 41, DQM1 = 36
4690 00:22:21.442254 DQ Delay:
4691 00:22:21.445327 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4692 00:22:21.448874 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4693 00:22:21.451846 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4694 00:22:21.455748 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4695 00:22:21.455842
4696 00:22:21.455928
4697 00:22:21.456007 ==
4698 00:22:21.458623 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 00:22:21.462318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 00:22:21.462383 ==
4701 00:22:21.462515
4702 00:22:21.462587
4703 00:22:21.465553 TX Vref Scan disable
4704 00:22:21.469227 == TX Byte 0 ==
4705 00:22:21.472341 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4706 00:22:21.475411 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4707 00:22:21.479088 == TX Byte 1 ==
4708 00:22:21.482155 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4709 00:22:21.485410 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4710 00:22:21.485477 ==
4711 00:22:21.489242 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 00:22:21.495253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 00:22:21.495323 ==
4714 00:22:21.495380
4715 00:22:21.495464
4716 00:22:21.495548 TX Vref Scan disable
4717 00:22:21.499578 == TX Byte 0 ==
4718 00:22:21.502623 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4719 00:22:21.509605 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4720 00:22:21.509705 == TX Byte 1 ==
4721 00:22:21.513174 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4722 00:22:21.519651 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4723 00:22:21.519727
4724 00:22:21.519787 [DATLAT]
4725 00:22:21.519848 Freq=600, CH1 RK1
4726 00:22:21.519914
4727 00:22:21.522501 DATLAT Default: 0x9
4728 00:22:21.522568 0, 0xFFFF, sum = 0
4729 00:22:21.526225 1, 0xFFFF, sum = 0
4730 00:22:21.526299 2, 0xFFFF, sum = 0
4731 00:22:21.529304 3, 0xFFFF, sum = 0
4732 00:22:21.533090 4, 0xFFFF, sum = 0
4733 00:22:21.533162 5, 0xFFFF, sum = 0
4734 00:22:21.536283 6, 0xFFFF, sum = 0
4735 00:22:21.536350 7, 0xFFFF, sum = 0
4736 00:22:21.539506 8, 0x0, sum = 1
4737 00:22:21.539570 9, 0x0, sum = 2
4738 00:22:21.539625 10, 0x0, sum = 3
4739 00:22:21.542567 11, 0x0, sum = 4
4740 00:22:21.542637 best_step = 9
4741 00:22:21.542692
4742 00:22:21.542743 ==
4743 00:22:21.546137 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 00:22:21.552753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 00:22:21.552827 ==
4746 00:22:21.552889 RX Vref Scan: 0
4747 00:22:21.552945
4748 00:22:21.556229 RX Vref 0 -> 0, step: 1
4749 00:22:21.556294
4750 00:22:21.559308 RX Delay -179 -> 252, step: 8
4751 00:22:21.562829 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4752 00:22:21.569041 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4753 00:22:21.572727 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4754 00:22:21.575966 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4755 00:22:21.579136 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4756 00:22:21.582878 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4757 00:22:21.589594 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4758 00:22:21.592645 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4759 00:22:21.596363 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4760 00:22:21.599424 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4761 00:22:21.606237 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4762 00:22:21.609394 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4763 00:22:21.613126 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4764 00:22:21.616107 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4765 00:22:21.619348 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4766 00:22:21.626293 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4767 00:22:21.626372 ==
4768 00:22:21.629852 Dram Type= 6, Freq= 0, CH_1, rank 1
4769 00:22:21.632861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4770 00:22:21.632940 ==
4771 00:22:21.633001 DQS Delay:
4772 00:22:21.636395 DQS0 = 0, DQS1 = 0
4773 00:22:21.636473 DQM Delay:
4774 00:22:21.639762 DQM0 = 38, DQM1 = 33
4775 00:22:21.639840 DQ Delay:
4776 00:22:21.643122 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4777 00:22:21.646002 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4778 00:22:21.649324 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4779 00:22:21.652742 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4780 00:22:21.652845
4781 00:22:21.652932
4782 00:22:21.662644 [DQSOSCAuto] RK1, (LSB)MR18= 0x424f, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 397 ps
4783 00:22:21.662724 CH1 RK1: MR19=808, MR18=424F
4784 00:22:21.669253 CH1_RK1: MR19=0x808, MR18=0x424F, DQSOSC=394, MR23=63, INC=168, DEC=112
4785 00:22:21.672884 [RxdqsGatingPostProcess] freq 600
4786 00:22:21.679471 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4787 00:22:21.682758 Pre-setting of DQS Precalculation
4788 00:22:21.685829 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4789 00:22:21.692810 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4790 00:22:21.698940 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4791 00:22:21.702660
4792 00:22:21.702740
4793 00:22:21.702800 [Calibration Summary] 1200 Mbps
4794 00:22:21.705715 CH 0, Rank 0
4795 00:22:21.705816 SW Impedance : PASS
4796 00:22:21.709574 DUTY Scan : NO K
4797 00:22:21.712421 ZQ Calibration : PASS
4798 00:22:21.712491 Jitter Meter : NO K
4799 00:22:21.716192 CBT Training : PASS
4800 00:22:21.719385 Write leveling : PASS
4801 00:22:21.719463 RX DQS gating : PASS
4802 00:22:21.722506 RX DQ/DQS(RDDQC) : PASS
4803 00:22:21.725789 TX DQ/DQS : PASS
4804 00:22:21.725892 RX DATLAT : PASS
4805 00:22:21.729506 RX DQ/DQS(Engine): PASS
4806 00:22:21.732425 TX OE : NO K
4807 00:22:21.732503 All Pass.
4808 00:22:21.732564
4809 00:22:21.732619 CH 0, Rank 1
4810 00:22:21.736003 SW Impedance : PASS
4811 00:22:21.739175 DUTY Scan : NO K
4812 00:22:21.739279 ZQ Calibration : PASS
4813 00:22:21.742309 Jitter Meter : NO K
4814 00:22:21.742405 CBT Training : PASS
4815 00:22:21.745912 Write leveling : PASS
4816 00:22:21.748849 RX DQS gating : PASS
4817 00:22:21.748927 RX DQ/DQS(RDDQC) : PASS
4818 00:22:21.752652 TX DQ/DQS : PASS
4819 00:22:21.755604 RX DATLAT : PASS
4820 00:22:21.755683 RX DQ/DQS(Engine): PASS
4821 00:22:21.759119 TX OE : NO K
4822 00:22:21.759196 All Pass.
4823 00:22:21.759255
4824 00:22:21.762207 CH 1, Rank 0
4825 00:22:21.762284 SW Impedance : PASS
4826 00:22:21.765864 DUTY Scan : NO K
4827 00:22:21.769525 ZQ Calibration : PASS
4828 00:22:21.769602 Jitter Meter : NO K
4829 00:22:21.772168 CBT Training : PASS
4830 00:22:21.775941 Write leveling : PASS
4831 00:22:21.776015 RX DQS gating : PASS
4832 00:22:21.779139 RX DQ/DQS(RDDQC) : PASS
4833 00:22:21.782522 TX DQ/DQS : PASS
4834 00:22:21.782596 RX DATLAT : PASS
4835 00:22:21.785861 RX DQ/DQS(Engine): PASS
4836 00:22:21.785951 TX OE : NO K
4837 00:22:21.789150 All Pass.
4838 00:22:21.789223
4839 00:22:21.789280 CH 1, Rank 1
4840 00:22:21.792261 SW Impedance : PASS
4841 00:22:21.795436 DUTY Scan : NO K
4842 00:22:21.795499 ZQ Calibration : PASS
4843 00:22:21.799080 Jitter Meter : NO K
4844 00:22:21.799156 CBT Training : PASS
4845 00:22:21.802183 Write leveling : PASS
4846 00:22:21.805851 RX DQS gating : PASS
4847 00:22:21.805930 RX DQ/DQS(RDDQC) : PASS
4848 00:22:21.809074 TX DQ/DQS : PASS
4849 00:22:21.812221 RX DATLAT : PASS
4850 00:22:21.812297 RX DQ/DQS(Engine): PASS
4851 00:22:21.815725 TX OE : NO K
4852 00:22:21.815846 All Pass.
4853 00:22:21.815936
4854 00:22:21.818674 DramC Write-DBI off
4855 00:22:21.822463 PER_BANK_REFRESH: Hybrid Mode
4856 00:22:21.822538 TX_TRACKING: ON
4857 00:22:21.832386 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4858 00:22:21.835460 [FAST_K] Save calibration result to emmc
4859 00:22:21.838973 dramc_set_vcore_voltage set vcore to 662500
4860 00:22:21.842133 Read voltage for 933, 3
4861 00:22:21.842209 Vio18 = 0
4862 00:22:21.842267 Vcore = 662500
4863 00:22:21.845216 Vdram = 0
4864 00:22:21.845291 Vddq = 0
4865 00:22:21.845350 Vmddr = 0
4866 00:22:21.852573 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4867 00:22:21.855748 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4868 00:22:21.858706 MEM_TYPE=3, freq_sel=17
4869 00:22:21.862569 sv_algorithm_assistance_LP4_1600
4870 00:22:21.865813 ============ PULL DRAM RESETB DOWN ============
4871 00:22:21.868731 ========== PULL DRAM RESETB DOWN end =========
4872 00:22:21.875854 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4873 00:22:21.879444 ===================================
4874 00:22:21.879520 LPDDR4 DRAM CONFIGURATION
4875 00:22:21.882313 ===================================
4876 00:22:21.886012 EX_ROW_EN[0] = 0x0
4877 00:22:21.888960 EX_ROW_EN[1] = 0x0
4878 00:22:21.889035 LP4Y_EN = 0x0
4879 00:22:21.892210 WORK_FSP = 0x0
4880 00:22:21.892286 WL = 0x3
4881 00:22:21.895965 RL = 0x3
4882 00:22:21.896041 BL = 0x2
4883 00:22:21.899049 RPST = 0x0
4884 00:22:21.899124 RD_PRE = 0x0
4885 00:22:21.902121 WR_PRE = 0x1
4886 00:22:21.902200 WR_PST = 0x0
4887 00:22:21.905412 DBI_WR = 0x0
4888 00:22:21.905506 DBI_RD = 0x0
4889 00:22:21.908843 OTF = 0x1
4890 00:22:21.912553 ===================================
4891 00:22:21.915790 ===================================
4892 00:22:21.915866 ANA top config
4893 00:22:21.918708 ===================================
4894 00:22:21.922417 DLL_ASYNC_EN = 0
4895 00:22:21.925968 ALL_SLAVE_EN = 1
4896 00:22:21.926084 NEW_RANK_MODE = 1
4897 00:22:21.929008 DLL_IDLE_MODE = 1
4898 00:22:21.932134 LP45_APHY_COMB_EN = 1
4899 00:22:21.935854 TX_ODT_DIS = 1
4900 00:22:21.938965 NEW_8X_MODE = 1
4901 00:22:21.939043 ===================================
4902 00:22:21.942339 ===================================
4903 00:22:21.946049 data_rate = 1866
4904 00:22:21.949255 CKR = 1
4905 00:22:21.952295 DQ_P2S_RATIO = 8
4906 00:22:21.955867 ===================================
4907 00:22:21.959020 CA_P2S_RATIO = 8
4908 00:22:21.962799 DQ_CA_OPEN = 0
4909 00:22:21.962927 DQ_SEMI_OPEN = 0
4910 00:22:21.965932 CA_SEMI_OPEN = 0
4911 00:22:21.969657 CA_FULL_RATE = 0
4912 00:22:21.972665 DQ_CKDIV4_EN = 1
4913 00:22:21.976324 CA_CKDIV4_EN = 1
4914 00:22:21.979348 CA_PREDIV_EN = 0
4915 00:22:21.979424 PH8_DLY = 0
4916 00:22:21.982579 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4917 00:22:21.986581 DQ_AAMCK_DIV = 4
4918 00:22:21.989564 CA_AAMCK_DIV = 4
4919 00:22:21.992753 CA_ADMCK_DIV = 4
4920 00:22:21.996407 DQ_TRACK_CA_EN = 0
4921 00:22:21.996483 CA_PICK = 933
4922 00:22:21.999485 CA_MCKIO = 933
4923 00:22:22.002676 MCKIO_SEMI = 0
4924 00:22:22.006180 PLL_FREQ = 3732
4925 00:22:22.009508 DQ_UI_PI_RATIO = 32
4926 00:22:22.012804 CA_UI_PI_RATIO = 0
4927 00:22:22.016200 ===================================
4928 00:22:22.019199 ===================================
4929 00:22:22.019346 memory_type:LPDDR4
4930 00:22:22.022824 GP_NUM : 10
4931 00:22:22.026108 SRAM_EN : 1
4932 00:22:22.026183 MD32_EN : 0
4933 00:22:22.029844 ===================================
4934 00:22:22.032630 [ANA_INIT] >>>>>>>>>>>>>>
4935 00:22:22.036273 <<<<<< [CONFIGURE PHASE]: ANA_TX
4936 00:22:22.039366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4937 00:22:22.042526 ===================================
4938 00:22:22.046244 data_rate = 1866,PCW = 0X8f00
4939 00:22:22.049221 ===================================
4940 00:22:22.052944 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4941 00:22:22.056056 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4942 00:22:22.062714 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4943 00:22:22.066319 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4944 00:22:22.069380 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4945 00:22:22.073252 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4946 00:22:22.076286 [ANA_INIT] flow start
4947 00:22:22.079733 [ANA_INIT] PLL >>>>>>>>
4948 00:22:22.079807 [ANA_INIT] PLL <<<<<<<<
4949 00:22:22.083095 [ANA_INIT] MIDPI >>>>>>>>
4950 00:22:22.086098 [ANA_INIT] MIDPI <<<<<<<<
4951 00:22:22.086164 [ANA_INIT] DLL >>>>>>>>
4952 00:22:22.089661 [ANA_INIT] flow end
4953 00:22:22.092898 ============ LP4 DIFF to SE enter ============
4954 00:22:22.096054 ============ LP4 DIFF to SE exit ============
4955 00:22:22.099785 [ANA_INIT] <<<<<<<<<<<<<
4956 00:22:22.102891 [Flow] Enable top DCM control >>>>>
4957 00:22:22.106113 [Flow] Enable top DCM control <<<<<
4958 00:22:22.109906 Enable DLL master slave shuffle
4959 00:22:22.116089 ==============================================================
4960 00:22:22.116177 Gating Mode config
4961 00:22:22.123077 ==============================================================
4962 00:22:22.123201 Config description:
4963 00:22:22.133243 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4964 00:22:22.139768 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4965 00:22:22.146224 SELPH_MODE 0: By rank 1: By Phase
4966 00:22:22.149743 ==============================================================
4967 00:22:22.152765 GAT_TRACK_EN = 1
4968 00:22:22.156240 RX_GATING_MODE = 2
4969 00:22:22.159549 RX_GATING_TRACK_MODE = 2
4970 00:22:22.162642 SELPH_MODE = 1
4971 00:22:22.166215 PICG_EARLY_EN = 1
4972 00:22:22.169706 VALID_LAT_VALUE = 1
4973 00:22:22.176133 ==============================================================
4974 00:22:22.179850 Enter into Gating configuration >>>>
4975 00:22:22.179926 Exit from Gating configuration <<<<
4976 00:22:22.182923 Enter into DVFS_PRE_config >>>>>
4977 00:22:22.196271 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4978 00:22:22.199376 Exit from DVFS_PRE_config <<<<<
4979 00:22:22.203261 Enter into PICG configuration >>>>
4980 00:22:22.206235 Exit from PICG configuration <<<<
4981 00:22:22.206312 [RX_INPUT] configuration >>>>>
4982 00:22:22.209880 [RX_INPUT] configuration <<<<<
4983 00:22:22.216312 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4984 00:22:22.220008 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4985 00:22:22.226622 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4986 00:22:22.233098 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4987 00:22:22.239811 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4988 00:22:22.246251 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4989 00:22:22.249860 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4990 00:22:22.252809 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4991 00:22:22.256233 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4992 00:22:22.263316 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4993 00:22:22.266346 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4994 00:22:22.270087 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4995 00:22:22.272877 ===================================
4996 00:22:22.276488 LPDDR4 DRAM CONFIGURATION
4997 00:22:22.279758 ===================================
4998 00:22:22.282770 EX_ROW_EN[0] = 0x0
4999 00:22:22.282840 EX_ROW_EN[1] = 0x0
5000 00:22:22.286484 LP4Y_EN = 0x0
5001 00:22:22.286550 WORK_FSP = 0x0
5002 00:22:22.289495 WL = 0x3
5003 00:22:22.289591 RL = 0x3
5004 00:22:22.293095 BL = 0x2
5005 00:22:22.293162 RPST = 0x0
5006 00:22:22.296238 RD_PRE = 0x0
5007 00:22:22.296311 WR_PRE = 0x1
5008 00:22:22.299798 WR_PST = 0x0
5009 00:22:22.299867 DBI_WR = 0x0
5010 00:22:22.302916 DBI_RD = 0x0
5011 00:22:22.302980 OTF = 0x1
5012 00:22:22.306267 ===================================
5013 00:22:22.309914 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5014 00:22:22.316697 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5015 00:22:22.319788 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5016 00:22:22.322939 ===================================
5017 00:22:22.326546 LPDDR4 DRAM CONFIGURATION
5018 00:22:22.329838 ===================================
5019 00:22:22.329949 EX_ROW_EN[0] = 0x10
5020 00:22:22.333266 EX_ROW_EN[1] = 0x0
5021 00:22:22.336204 LP4Y_EN = 0x0
5022 00:22:22.336270 WORK_FSP = 0x0
5023 00:22:22.339927 WL = 0x3
5024 00:22:22.339992 RL = 0x3
5025 00:22:22.343021 BL = 0x2
5026 00:22:22.343109 RPST = 0x0
5027 00:22:22.346158 RD_PRE = 0x0
5028 00:22:22.346225 WR_PRE = 0x1
5029 00:22:22.349755 WR_PST = 0x0
5030 00:22:22.349854 DBI_WR = 0x0
5031 00:22:22.353097 DBI_RD = 0x0
5032 00:22:22.353161 OTF = 0x1
5033 00:22:22.356488 ===================================
5034 00:22:22.362680 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5035 00:22:22.366962 nWR fixed to 30
5036 00:22:22.370509 [ModeRegInit_LP4] CH0 RK0
5037 00:22:22.370585 [ModeRegInit_LP4] CH0 RK1
5038 00:22:22.373581 [ModeRegInit_LP4] CH1 RK0
5039 00:22:22.376781 [ModeRegInit_LP4] CH1 RK1
5040 00:22:22.376886 match AC timing 9
5041 00:22:22.383671 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5042 00:22:22.387282 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5043 00:22:22.390403 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5044 00:22:22.397150 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5045 00:22:22.400597 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5046 00:22:22.400692 ==
5047 00:22:22.403518 Dram Type= 6, Freq= 0, CH_0, rank 0
5048 00:22:22.406730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5049 00:22:22.406811 ==
5050 00:22:22.413489 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5051 00:22:22.420445 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5052 00:22:22.423556 [CA 0] Center 38 (8~69) winsize 62
5053 00:22:22.427181 [CA 1] Center 37 (7~68) winsize 62
5054 00:22:22.430263 [CA 2] Center 35 (5~66) winsize 62
5055 00:22:22.433344 [CA 3] Center 35 (4~66) winsize 63
5056 00:22:22.437153 [CA 4] Center 34 (4~65) winsize 62
5057 00:22:22.440147 [CA 5] Center 34 (4~64) winsize 61
5058 00:22:22.440237
5059 00:22:22.443542 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5060 00:22:22.443618
5061 00:22:22.447251 [CATrainingPosCal] consider 1 rank data
5062 00:22:22.450274 u2DelayCellTimex100 = 270/100 ps
5063 00:22:22.453512 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5064 00:22:22.457072 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5065 00:22:22.460452 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5066 00:22:22.463376 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5067 00:22:22.467262 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5068 00:22:22.470271 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5069 00:22:22.470338
5070 00:22:22.476903 CA PerBit enable=1, Macro0, CA PI delay=34
5071 00:22:22.476979
5072 00:22:22.477038 [CBTSetCACLKResult] CA Dly = 34
5073 00:22:22.480657 CS Dly: 6 (0~37)
5074 00:22:22.480756 ==
5075 00:22:22.483961 Dram Type= 6, Freq= 0, CH_0, rank 1
5076 00:22:22.486788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5077 00:22:22.486865 ==
5078 00:22:22.493904 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5079 00:22:22.500423 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5080 00:22:22.503547 [CA 0] Center 38 (8~69) winsize 62
5081 00:22:22.507186 [CA 1] Center 38 (7~69) winsize 63
5082 00:22:22.510630 [CA 2] Center 35 (5~66) winsize 62
5083 00:22:22.513633 [CA 3] Center 35 (5~65) winsize 61
5084 00:22:22.516710 [CA 4] Center 34 (3~65) winsize 63
5085 00:22:22.520474 [CA 5] Center 33 (3~64) winsize 62
5086 00:22:22.520550
5087 00:22:22.523683 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5088 00:22:22.523772
5089 00:22:22.526646 [CATrainingPosCal] consider 2 rank data
5090 00:22:22.530414 u2DelayCellTimex100 = 270/100 ps
5091 00:22:22.533756 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5092 00:22:22.536771 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5093 00:22:22.540638 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5094 00:22:22.543691 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5095 00:22:22.547334 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5096 00:22:22.550131 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5097 00:22:22.550219
5098 00:22:22.553716 CA PerBit enable=1, Macro0, CA PI delay=34
5099 00:22:22.556753
5100 00:22:22.556841 [CBTSetCACLKResult] CA Dly = 34
5101 00:22:22.560597 CS Dly: 7 (0~39)
5102 00:22:22.560687
5103 00:22:22.563743 ----->DramcWriteLeveling(PI) begin...
5104 00:22:22.563819 ==
5105 00:22:22.567309 Dram Type= 6, Freq= 0, CH_0, rank 0
5106 00:22:22.570305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5107 00:22:22.570375 ==
5108 00:22:22.573901 Write leveling (Byte 0): 30 => 30
5109 00:22:22.576812 Write leveling (Byte 1): 29 => 29
5110 00:22:22.580492 DramcWriteLeveling(PI) end<-----
5111 00:22:22.580569
5112 00:22:22.580644 ==
5113 00:22:22.583531 Dram Type= 6, Freq= 0, CH_0, rank 0
5114 00:22:22.587336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 00:22:22.587432 ==
5116 00:22:22.590444 [Gating] SW mode calibration
5117 00:22:22.597037 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5118 00:22:22.603635 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5119 00:22:22.606972 0 14 0 | B1->B0 | 2323 3232 | 1 0 | (0 0) (0 0)
5120 00:22:22.613926 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5121 00:22:22.617399 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 00:22:22.620449 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 00:22:22.627274 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 00:22:22.630346 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 00:22:22.634214 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 00:22:22.637311 0 14 28 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
5127 00:22:22.644122 0 15 0 | B1->B0 | 3030 2a2a | 1 0 | (1 1) (0 0)
5128 00:22:22.647192 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5129 00:22:22.650294 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 00:22:22.657302 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 00:22:22.660440 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 00:22:22.664173 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 00:22:22.670244 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 00:22:22.673640 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5135 00:22:22.677003 1 0 0 | B1->B0 | 2d2d 3f3f | 1 1 | (0 0) (0 0)
5136 00:22:22.683841 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 00:22:22.686848 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 00:22:22.690528 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 00:22:22.697418 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 00:22:22.700706 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 00:22:22.703697 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 00:22:22.710652 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 00:22:22.713899 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5144 00:22:22.717563 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 00:22:22.720382 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 00:22:22.727187 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 00:22:22.730541 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 00:22:22.734152 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 00:22:22.740883 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 00:22:22.744228 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 00:22:22.747265 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 00:22:22.753956 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 00:22:22.757274 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 00:22:22.760738 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 00:22:22.767445 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 00:22:22.770606 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 00:22:22.774256 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 00:22:22.780690 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 00:22:22.783754 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5160 00:22:22.787490 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 00:22:22.790553 Total UI for P1: 0, mck2ui 16
5162 00:22:22.794142 best dqsien dly found for B0: ( 1, 3, 0)
5163 00:22:22.797105 Total UI for P1: 0, mck2ui 16
5164 00:22:22.800885 best dqsien dly found for B1: ( 1, 3, 2)
5165 00:22:22.804238 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5166 00:22:22.807207 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5167 00:22:22.807302
5168 00:22:22.810717 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5169 00:22:22.814120 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5170 00:22:22.817662 [Gating] SW calibration Done
5171 00:22:22.817756 ==
5172 00:22:22.821006 Dram Type= 6, Freq= 0, CH_0, rank 0
5173 00:22:22.824133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5174 00:22:22.827813 ==
5175 00:22:22.827911 RX Vref Scan: 0
5176 00:22:22.828015
5177 00:22:22.830706 RX Vref 0 -> 0, step: 1
5178 00:22:22.830801
5179 00:22:22.834205 RX Delay -80 -> 252, step: 8
5180 00:22:22.837425 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5181 00:22:22.840687 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5182 00:22:22.844100 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5183 00:22:22.847824 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5184 00:22:22.850953 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5185 00:22:22.857061 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5186 00:22:22.860825 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5187 00:22:22.863867 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5188 00:22:22.867458 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5189 00:22:22.870542 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5190 00:22:22.874234 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5191 00:22:22.881084 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5192 00:22:22.884110 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5193 00:22:22.887402 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5194 00:22:22.891107 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5195 00:22:22.894225 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5196 00:22:22.894300 ==
5197 00:22:22.897645 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 00:22:22.904567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 00:22:22.904694 ==
5200 00:22:22.904758 DQS Delay:
5201 00:22:22.904816 DQS0 = 0, DQS1 = 0
5202 00:22:22.907587 DQM Delay:
5203 00:22:22.907652 DQM0 = 99, DQM1 = 87
5204 00:22:22.910623 DQ Delay:
5205 00:22:22.914352 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5206 00:22:22.917354 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5207 00:22:22.921163 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5208 00:22:22.924042 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5209 00:22:22.924113
5210 00:22:22.924170
5211 00:22:22.924224 ==
5212 00:22:22.927904 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 00:22:22.930954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 00:22:22.931033 ==
5215 00:22:22.931100
5216 00:22:22.931154
5217 00:22:22.934044 TX Vref Scan disable
5218 00:22:22.934108 == TX Byte 0 ==
5219 00:22:22.940886 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5220 00:22:22.944211 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5221 00:22:22.944287 == TX Byte 1 ==
5222 00:22:22.950909 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5223 00:22:22.954361 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5224 00:22:22.954435 ==
5225 00:22:22.957510 Dram Type= 6, Freq= 0, CH_0, rank 0
5226 00:22:22.960630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5227 00:22:22.960706 ==
5228 00:22:22.960764
5229 00:22:22.960819
5230 00:22:22.964125 TX Vref Scan disable
5231 00:22:22.967176 == TX Byte 0 ==
5232 00:22:22.970880 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5233 00:22:22.974273 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5234 00:22:22.977719 == TX Byte 1 ==
5235 00:22:22.980956 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5236 00:22:22.983957 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5237 00:22:22.984057
5238 00:22:22.987738 [DATLAT]
5239 00:22:22.987829 Freq=933, CH0 RK0
5240 00:22:22.987902
5241 00:22:22.990666 DATLAT Default: 0xd
5242 00:22:22.990770 0, 0xFFFF, sum = 0
5243 00:22:22.994254 1, 0xFFFF, sum = 0
5244 00:22:22.994345 2, 0xFFFF, sum = 0
5245 00:22:22.997468 3, 0xFFFF, sum = 0
5246 00:22:22.997545 4, 0xFFFF, sum = 0
5247 00:22:23.001166 5, 0xFFFF, sum = 0
5248 00:22:23.001294 6, 0xFFFF, sum = 0
5249 00:22:23.004245 7, 0xFFFF, sum = 0
5250 00:22:23.004320 8, 0xFFFF, sum = 0
5251 00:22:23.007755 9, 0xFFFF, sum = 0
5252 00:22:23.007830 10, 0x0, sum = 1
5253 00:22:23.010929 11, 0x0, sum = 2
5254 00:22:23.011003 12, 0x0, sum = 3
5255 00:22:23.013931 13, 0x0, sum = 4
5256 00:22:23.014043 best_step = 11
5257 00:22:23.014104
5258 00:22:23.014159 ==
5259 00:22:23.017502 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 00:22:23.024277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 00:22:23.024379 ==
5262 00:22:23.024465 RX Vref Scan: 1
5263 00:22:23.024548
5264 00:22:23.027822 RX Vref 0 -> 0, step: 1
5265 00:22:23.027888
5266 00:22:23.031004 RX Delay -61 -> 252, step: 4
5267 00:22:23.031077
5268 00:22:23.033905 Set Vref, RX VrefLevel [Byte0]: 52
5269 00:22:23.037737 [Byte1]: 51
5270 00:22:23.037838
5271 00:22:23.040829 Final RX Vref Byte 0 = 52 to rank0
5272 00:22:23.043968 Final RX Vref Byte 1 = 51 to rank0
5273 00:22:23.047315 Final RX Vref Byte 0 = 52 to rank1
5274 00:22:23.050631 Final RX Vref Byte 1 = 51 to rank1==
5275 00:22:23.054515 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 00:22:23.057495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 00:22:23.057574 ==
5278 00:22:23.061082 DQS Delay:
5279 00:22:23.061159 DQS0 = 0, DQS1 = 0
5280 00:22:23.061218 DQM Delay:
5281 00:22:23.064053 DQM0 = 97, DQM1 = 87
5282 00:22:23.064129 DQ Delay:
5283 00:22:23.067534 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =96
5284 00:22:23.070777 DQ4 =100, DQ5 =86, DQ6 =106, DQ7 =104
5285 00:22:23.074441 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =80
5286 00:22:23.077469 DQ12 =92, DQ13 =92, DQ14 =100, DQ15 =100
5287 00:22:23.077550
5288 00:22:23.077619
5289 00:22:23.087473 [DQSOSCAuto] RK0, (LSB)MR18= 0x15ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5290 00:22:23.091414 CH0 RK0: MR19=504, MR18=15FF
5291 00:22:23.094369 CH0_RK0: MR19=0x504, MR18=0x15FF, DQSOSC=415, MR23=63, INC=62, DEC=41
5292 00:22:23.094450
5293 00:22:23.097903 ----->DramcWriteLeveling(PI) begin...
5294 00:22:23.100876 ==
5295 00:22:23.100969 Dram Type= 6, Freq= 0, CH_0, rank 1
5296 00:22:23.107808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5297 00:22:23.107915 ==
5298 00:22:23.111400 Write leveling (Byte 0): 33 => 33
5299 00:22:23.114351 Write leveling (Byte 1): 29 => 29
5300 00:22:23.117484 DramcWriteLeveling(PI) end<-----
5301 00:22:23.117575
5302 00:22:23.117661 ==
5303 00:22:23.121191 Dram Type= 6, Freq= 0, CH_0, rank 1
5304 00:22:23.124543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 00:22:23.124634 ==
5306 00:22:23.127861 [Gating] SW mode calibration
5307 00:22:23.134557 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5308 00:22:23.137776 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5309 00:22:23.144574 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5310 00:22:23.147665 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 00:22:23.151363 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 00:22:23.157834 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 00:22:23.160983 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 00:22:23.164182 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 00:22:23.170841 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5316 00:22:23.174570 0 14 28 | B1->B0 | 3333 3030 | 0 0 | (0 1) (1 1)
5317 00:22:23.177563 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5318 00:22:23.184173 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 00:22:23.187572 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 00:22:23.191208 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 00:22:23.197481 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 00:22:23.201043 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 00:22:23.204436 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 00:22:23.210862 0 15 28 | B1->B0 | 2929 3535 | 0 0 | (0 0) (0 0)
5325 00:22:23.214019 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5326 00:22:23.217959 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 00:22:23.220933 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 00:22:23.227554 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 00:22:23.230956 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 00:22:23.234750 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 00:22:23.241338 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5332 00:22:23.244382 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5333 00:22:23.248267 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5334 00:22:23.254535 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5335 00:22:23.258197 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 00:22:23.261326 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 00:22:23.268082 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 00:22:23.271162 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 00:22:23.275014 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 00:22:23.281290 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 00:22:23.284877 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 00:22:23.287915 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 00:22:23.291351 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 00:22:23.298007 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 00:22:23.301463 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 00:22:23.304828 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 00:22:23.311369 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 00:22:23.314674 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5349 00:22:23.318307 Total UI for P1: 0, mck2ui 16
5350 00:22:23.322047 best dqsien dly found for B0: ( 1, 2, 26)
5351 00:22:23.325082 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 00:22:23.328195 Total UI for P1: 0, mck2ui 16
5353 00:22:23.331843 best dqsien dly found for B1: ( 1, 2, 28)
5354 00:22:23.334855 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5355 00:22:23.338752 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5356 00:22:23.338829
5357 00:22:23.341662 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5358 00:22:23.348577 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5359 00:22:23.348652 [Gating] SW calibration Done
5360 00:22:23.348711 ==
5361 00:22:23.351522 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 00:22:23.358377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 00:22:23.358456 ==
5364 00:22:23.358516 RX Vref Scan: 0
5365 00:22:23.358570
5366 00:22:23.361516 RX Vref 0 -> 0, step: 1
5367 00:22:23.361591
5368 00:22:23.365255 RX Delay -80 -> 252, step: 8
5369 00:22:23.368277 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5370 00:22:23.371920 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5371 00:22:23.374907 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5372 00:22:23.378659 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5373 00:22:23.381722 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5374 00:22:23.388448 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5375 00:22:23.391722 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5376 00:22:23.395480 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5377 00:22:23.398621 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5378 00:22:23.401754 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5379 00:22:23.408436 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5380 00:22:23.412279 iDelay=200, Bit 11, Center 75 (-16 ~ 167) 184
5381 00:22:23.415008 iDelay=200, Bit 12, Center 87 (-8 ~ 183) 192
5382 00:22:23.418672 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5383 00:22:23.421864 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5384 00:22:23.425121 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5385 00:22:23.428292 ==
5386 00:22:23.428409 Dram Type= 6, Freq= 0, CH_0, rank 1
5387 00:22:23.435560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 00:22:23.435676 ==
5389 00:22:23.435756 DQS Delay:
5390 00:22:23.438461 DQS0 = 0, DQS1 = 0
5391 00:22:23.438601 DQM Delay:
5392 00:22:23.442133 DQM0 = 97, DQM1 = 86
5393 00:22:23.442289 DQ Delay:
5394 00:22:23.445619 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5395 00:22:23.448888 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5396 00:22:23.452103 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =75
5397 00:22:23.455142 DQ12 =87, DQ13 =95, DQ14 =95, DQ15 =95
5398 00:22:23.455315
5399 00:22:23.455437
5400 00:22:23.455577 ==
5401 00:22:23.459048 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 00:22:23.462034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 00:22:23.462272 ==
5404 00:22:23.462469
5405 00:22:23.462633
5406 00:22:23.465134 TX Vref Scan disable
5407 00:22:23.468979 == TX Byte 0 ==
5408 00:22:23.472189 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5409 00:22:23.475355 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5410 00:22:23.479061 == TX Byte 1 ==
5411 00:22:23.482054 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5412 00:22:23.485709 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5413 00:22:23.486157 ==
5414 00:22:23.488816 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 00:22:23.492565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 00:22:23.492962 ==
5417 00:22:23.495417
5418 00:22:23.495881
5419 00:22:23.496251 TX Vref Scan disable
5420 00:22:23.499161 == TX Byte 0 ==
5421 00:22:23.502340 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5422 00:22:23.505865 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5423 00:22:23.509072 == TX Byte 1 ==
5424 00:22:23.512088 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5425 00:22:23.515784 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5426 00:22:23.518901
5427 00:22:23.519287 [DATLAT]
5428 00:22:23.519586 Freq=933, CH0 RK1
5429 00:22:23.519866
5430 00:22:23.522681 DATLAT Default: 0xb
5431 00:22:23.523066 0, 0xFFFF, sum = 0
5432 00:22:23.525635 1, 0xFFFF, sum = 0
5433 00:22:23.526069 2, 0xFFFF, sum = 0
5434 00:22:23.529357 3, 0xFFFF, sum = 0
5435 00:22:23.529844 4, 0xFFFF, sum = 0
5436 00:22:23.532306 5, 0xFFFF, sum = 0
5437 00:22:23.532775 6, 0xFFFF, sum = 0
5438 00:22:23.535593 7, 0xFFFF, sum = 0
5439 00:22:23.539223 8, 0xFFFF, sum = 0
5440 00:22:23.539730 9, 0xFFFF, sum = 0
5441 00:22:23.540171 10, 0x0, sum = 1
5442 00:22:23.542310 11, 0x0, sum = 2
5443 00:22:23.542700 12, 0x0, sum = 3
5444 00:22:23.545604 13, 0x0, sum = 4
5445 00:22:23.546032 best_step = 11
5446 00:22:23.546347
5447 00:22:23.546669 ==
5448 00:22:23.548821 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 00:22:23.555061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 00:22:23.555142 ==
5451 00:22:23.555200 RX Vref Scan: 0
5452 00:22:23.555255
5453 00:22:23.558548 RX Vref 0 -> 0, step: 1
5454 00:22:23.558623
5455 00:22:23.561919 RX Delay -61 -> 252, step: 4
5456 00:22:23.565557 iDelay=195, Bit 0, Center 96 (3 ~ 190) 188
5457 00:22:23.568517 iDelay=195, Bit 1, Center 96 (3 ~ 190) 188
5458 00:22:23.575368 iDelay=195, Bit 2, Center 92 (-1 ~ 186) 188
5459 00:22:23.578629 iDelay=195, Bit 3, Center 94 (-1 ~ 190) 192
5460 00:22:23.582428 iDelay=195, Bit 4, Center 96 (7 ~ 186) 180
5461 00:22:23.585550 iDelay=195, Bit 5, Center 84 (-9 ~ 178) 188
5462 00:22:23.588602 iDelay=195, Bit 6, Center 102 (11 ~ 194) 184
5463 00:22:23.592352 iDelay=195, Bit 7, Center 102 (11 ~ 194) 184
5464 00:22:23.598558 iDelay=195, Bit 8, Center 80 (-9 ~ 170) 180
5465 00:22:23.602347 iDelay=195, Bit 9, Center 78 (-9 ~ 166) 176
5466 00:22:23.605526 iDelay=195, Bit 10, Center 88 (-1 ~ 178) 180
5467 00:22:23.608665 iDelay=195, Bit 11, Center 78 (-9 ~ 166) 176
5468 00:22:23.611776 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5469 00:22:23.615526 iDelay=195, Bit 13, Center 92 (3 ~ 182) 180
5470 00:22:23.622302 iDelay=195, Bit 14, Center 98 (11 ~ 186) 176
5471 00:22:23.625518 iDelay=195, Bit 15, Center 96 (11 ~ 182) 172
5472 00:22:23.625617 ==
5473 00:22:23.628590 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 00:22:23.631760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 00:22:23.631838 ==
5476 00:22:23.635452 DQS Delay:
5477 00:22:23.635555 DQS0 = 0, DQS1 = 0
5478 00:22:23.635642 DQM Delay:
5479 00:22:23.638482 DQM0 = 95, DQM1 = 88
5480 00:22:23.638574 DQ Delay:
5481 00:22:23.641717 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5482 00:22:23.645285 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =102
5483 00:22:23.648467 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =78
5484 00:22:23.652078 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =96
5485 00:22:23.652168
5486 00:22:23.652249
5487 00:22:23.662175 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps
5488 00:22:23.662269 CH0 RK1: MR19=505, MR18=1E0C
5489 00:22:23.668642 CH0_RK1: MR19=0x505, MR18=0x1E0C, DQSOSC=412, MR23=63, INC=63, DEC=42
5490 00:22:23.672408 [RxdqsGatingPostProcess] freq 933
5491 00:22:23.679012 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5492 00:22:23.682335 best DQS0 dly(2T, 0.5T) = (0, 11)
5493 00:22:23.685230 best DQS1 dly(2T, 0.5T) = (0, 11)
5494 00:22:23.688816 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5495 00:22:23.692042 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5496 00:22:23.695733 best DQS0 dly(2T, 0.5T) = (0, 10)
5497 00:22:23.695808 best DQS1 dly(2T, 0.5T) = (0, 10)
5498 00:22:23.699148 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5499 00:22:23.702226 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5500 00:22:23.705700 Pre-setting of DQS Precalculation
5501 00:22:23.712425 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5502 00:22:23.712535 ==
5503 00:22:23.715544 Dram Type= 6, Freq= 0, CH_1, rank 0
5504 00:22:23.718876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5505 00:22:23.718952 ==
5506 00:22:23.725618 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5507 00:22:23.732348 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5508 00:22:23.735551 [CA 0] Center 36 (6~67) winsize 62
5509 00:22:23.739296 [CA 1] Center 36 (6~67) winsize 62
5510 00:22:23.742335 [CA 2] Center 34 (4~64) winsize 61
5511 00:22:23.745366 [CA 3] Center 33 (3~64) winsize 62
5512 00:22:23.748739 [CA 4] Center 34 (4~64) winsize 61
5513 00:22:23.748833 [CA 5] Center 33 (3~64) winsize 62
5514 00:22:23.752203
5515 00:22:23.755437 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5516 00:22:23.755508
5517 00:22:23.758978 [CATrainingPosCal] consider 1 rank data
5518 00:22:23.761839 u2DelayCellTimex100 = 270/100 ps
5519 00:22:23.765503 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5520 00:22:23.768586 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5521 00:22:23.771788 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5522 00:22:23.775595 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5523 00:22:23.778523 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5524 00:22:23.782109 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5525 00:22:23.782211
5526 00:22:23.785182 CA PerBit enable=1, Macro0, CA PI delay=33
5527 00:22:23.785252
5528 00:22:23.789019 [CBTSetCACLKResult] CA Dly = 33
5529 00:22:23.791885 CS Dly: 5 (0~36)
5530 00:22:23.791951 ==
5531 00:22:23.795404 Dram Type= 6, Freq= 0, CH_1, rank 1
5532 00:22:23.798351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 00:22:23.798417 ==
5534 00:22:23.805357 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5535 00:22:23.812068 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5536 00:22:23.815308 [CA 0] Center 36 (6~67) winsize 62
5537 00:22:23.818792 [CA 1] Center 37 (7~67) winsize 61
5538 00:22:23.821778 [CA 2] Center 33 (3~64) winsize 62
5539 00:22:23.825321 [CA 3] Center 33 (3~64) winsize 62
5540 00:22:23.828603 [CA 4] Center 34 (4~64) winsize 61
5541 00:22:23.832175 [CA 5] Center 33 (2~64) winsize 63
5542 00:22:23.832247
5543 00:22:23.835314 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5544 00:22:23.835380
5545 00:22:23.838603 [CATrainingPosCal] consider 2 rank data
5546 00:22:23.841682 u2DelayCellTimex100 = 270/100 ps
5547 00:22:23.845482 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5548 00:22:23.848725 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5549 00:22:23.851951 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5550 00:22:23.855148 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5551 00:22:23.858808 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5552 00:22:23.861886 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5553 00:22:23.861958
5554 00:22:23.865022 CA PerBit enable=1, Macro0, CA PI delay=33
5555 00:22:23.868564
5556 00:22:23.868635 [CBTSetCACLKResult] CA Dly = 33
5557 00:22:23.871758 CS Dly: 5 (0~37)
5558 00:22:23.871852
5559 00:22:23.875506 ----->DramcWriteLeveling(PI) begin...
5560 00:22:23.875597 ==
5561 00:22:23.878630 Dram Type= 6, Freq= 0, CH_1, rank 0
5562 00:22:23.881835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 00:22:23.881899 ==
5564 00:22:23.885578 Write leveling (Byte 0): 23 => 23
5565 00:22:23.888556 Write leveling (Byte 1): 27 => 27
5566 00:22:23.892229 DramcWriteLeveling(PI) end<-----
5567 00:22:23.892298
5568 00:22:23.892355 ==
5569 00:22:23.895459 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 00:22:23.898546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 00:22:23.898612 ==
5572 00:22:23.902403 [Gating] SW mode calibration
5573 00:22:23.908550 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5574 00:22:23.915484 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5575 00:22:23.918543 0 14 0 | B1->B0 | 2f2f 3232 | 1 1 | (1 1) (1 1)
5576 00:22:23.925325 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 00:22:23.928768 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 00:22:23.932123 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 00:22:23.934990 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 00:22:23.941854 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 00:22:23.945226 0 14 24 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 0)
5582 00:22:23.948619 0 14 28 | B1->B0 | 3131 3030 | 0 0 | (0 1) (0 1)
5583 00:22:23.955327 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
5584 00:22:23.958438 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 00:22:23.962017 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 00:22:23.968458 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 00:22:23.972221 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 00:22:23.975296 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 00:22:23.982323 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 00:22:23.985440 0 15 28 | B1->B0 | 3131 2828 | 1 0 | (0 0) (0 0)
5591 00:22:23.988539 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5592 00:22:23.995252 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 00:22:23.998743 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 00:22:24.001932 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 00:22:24.008734 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 00:22:24.011784 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 00:22:24.015482 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 00:22:24.018694 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5599 00:22:24.025240 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 00:22:24.029112 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 00:22:24.032280 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 00:22:24.038948 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 00:22:24.041940 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 00:22:24.045329 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 00:22:24.051851 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 00:22:24.055007 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 00:22:24.058674 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 00:22:24.065299 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 00:22:24.068984 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 00:22:24.071732 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 00:22:24.078411 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 00:22:24.081635 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 00:22:24.085038 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 00:22:24.091988 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5615 00:22:24.095103 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5616 00:22:24.098808 Total UI for P1: 0, mck2ui 16
5617 00:22:24.101873 best dqsien dly found for B0: ( 1, 2, 28)
5618 00:22:24.105313 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 00:22:24.108344 Total UI for P1: 0, mck2ui 16
5620 00:22:24.112101 best dqsien dly found for B1: ( 1, 2, 30)
5621 00:22:24.115210 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5622 00:22:24.118374 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5623 00:22:24.118444
5624 00:22:24.122139 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5625 00:22:24.128702 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5626 00:22:24.128775 [Gating] SW calibration Done
5627 00:22:24.128834 ==
5628 00:22:24.131940 Dram Type= 6, Freq= 0, CH_1, rank 0
5629 00:22:24.138212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5630 00:22:24.138313 ==
5631 00:22:24.138399 RX Vref Scan: 0
5632 00:22:24.138463
5633 00:22:24.141888 RX Vref 0 -> 0, step: 1
5634 00:22:24.141956
5635 00:22:24.144989 RX Delay -80 -> 252, step: 8
5636 00:22:24.148550 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5637 00:22:24.152238 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5638 00:22:24.155164 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5639 00:22:24.158239 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5640 00:22:24.165254 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5641 00:22:24.168724 iDelay=200, Bit 5, Center 107 (16 ~ 199) 184
5642 00:22:24.171790 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5643 00:22:24.175424 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5644 00:22:24.178606 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5645 00:22:24.181689 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5646 00:22:24.188247 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5647 00:22:24.191670 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5648 00:22:24.195371 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5649 00:22:24.198345 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5650 00:22:24.201737 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5651 00:22:24.208506 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5652 00:22:24.208587 ==
5653 00:22:24.211744 Dram Type= 6, Freq= 0, CH_1, rank 0
5654 00:22:24.215564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5655 00:22:24.215640 ==
5656 00:22:24.215699 DQS Delay:
5657 00:22:24.218748 DQS0 = 0, DQS1 = 0
5658 00:22:24.218832 DQM Delay:
5659 00:22:24.221800 DQM0 = 95, DQM1 = 88
5660 00:22:24.221890 DQ Delay:
5661 00:22:24.225587 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =95
5662 00:22:24.228652 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5663 00:22:24.232221 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5664 00:22:24.235181 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5665 00:22:24.235248
5666 00:22:24.235304
5667 00:22:24.235356 ==
5668 00:22:24.239075 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 00:22:24.242077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 00:22:24.242166 ==
5671 00:22:24.242227
5672 00:22:24.242281
5673 00:22:24.245251 TX Vref Scan disable
5674 00:22:24.248774 == TX Byte 0 ==
5675 00:22:24.251906 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5676 00:22:24.255341 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5677 00:22:24.258858 == TX Byte 1 ==
5678 00:22:24.262352 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5679 00:22:24.265461 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5680 00:22:24.265538 ==
5681 00:22:24.269076 Dram Type= 6, Freq= 0, CH_1, rank 0
5682 00:22:24.272285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5683 00:22:24.275306 ==
5684 00:22:24.275402
5685 00:22:24.275486
5686 00:22:24.275566 TX Vref Scan disable
5687 00:22:24.278902 == TX Byte 0 ==
5688 00:22:24.282077 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5689 00:22:24.285853 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5690 00:22:24.288881 == TX Byte 1 ==
5691 00:22:24.292143 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5692 00:22:24.298878 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5693 00:22:24.298954
5694 00:22:24.299013 [DATLAT]
5695 00:22:24.299067 Freq=933, CH1 RK0
5696 00:22:24.299120
5697 00:22:24.302184 DATLAT Default: 0xd
5698 00:22:24.302260 0, 0xFFFF, sum = 0
5699 00:22:24.305773 1, 0xFFFF, sum = 0
5700 00:22:24.305851 2, 0xFFFF, sum = 0
5701 00:22:24.308888 3, 0xFFFF, sum = 0
5702 00:22:24.312366 4, 0xFFFF, sum = 0
5703 00:22:24.312443 5, 0xFFFF, sum = 0
5704 00:22:24.315355 6, 0xFFFF, sum = 0
5705 00:22:24.315422 7, 0xFFFF, sum = 0
5706 00:22:24.318608 8, 0xFFFF, sum = 0
5707 00:22:24.318685 9, 0xFFFF, sum = 0
5708 00:22:24.322327 10, 0x0, sum = 1
5709 00:22:24.322404 11, 0x0, sum = 2
5710 00:22:24.322465 12, 0x0, sum = 3
5711 00:22:24.325321 13, 0x0, sum = 4
5712 00:22:24.325398 best_step = 11
5713 00:22:24.325457
5714 00:22:24.328663 ==
5715 00:22:24.328739 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 00:22:24.335617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 00:22:24.335700 ==
5718 00:22:24.335759 RX Vref Scan: 1
5719 00:22:24.335845
5720 00:22:24.339029 RX Vref 0 -> 0, step: 1
5721 00:22:24.339119
5722 00:22:24.342019 RX Delay -69 -> 252, step: 4
5723 00:22:24.342098
5724 00:22:24.345713 Set Vref, RX VrefLevel [Byte0]: 55
5725 00:22:24.348745 [Byte1]: 50
5726 00:22:24.348820
5727 00:22:24.352512 Final RX Vref Byte 0 = 55 to rank0
5728 00:22:24.355741 Final RX Vref Byte 1 = 50 to rank0
5729 00:22:24.358802 Final RX Vref Byte 0 = 55 to rank1
5730 00:22:24.362228 Final RX Vref Byte 1 = 50 to rank1==
5731 00:22:24.365765 Dram Type= 6, Freq= 0, CH_1, rank 0
5732 00:22:24.368723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 00:22:24.368796 ==
5734 00:22:24.372647 DQS Delay:
5735 00:22:24.372726 DQS0 = 0, DQS1 = 0
5736 00:22:24.375621 DQM Delay:
5737 00:22:24.375696 DQM0 = 98, DQM1 = 90
5738 00:22:24.375755 DQ Delay:
5739 00:22:24.379285 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =96
5740 00:22:24.382195 DQ4 =98, DQ5 =108, DQ6 =108, DQ7 =94
5741 00:22:24.385736 DQ8 =78, DQ9 =78, DQ10 =92, DQ11 =86
5742 00:22:24.388935 DQ12 =98, DQ13 =98, DQ14 =96, DQ15 =96
5743 00:22:24.389010
5744 00:22:24.389067
5745 00:22:24.398829 [DQSOSCAuto] RK0, (LSB)MR18= 0x19f5, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 413 ps
5746 00:22:24.402683 CH1 RK0: MR19=504, MR18=19F5
5747 00:22:24.408713 CH1_RK0: MR19=0x504, MR18=0x19F5, DQSOSC=413, MR23=63, INC=63, DEC=42
5748 00:22:24.408805
5749 00:22:24.412389 ----->DramcWriteLeveling(PI) begin...
5750 00:22:24.412466 ==
5751 00:22:24.415588 Dram Type= 6, Freq= 0, CH_1, rank 1
5752 00:22:24.418852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 00:22:24.418929 ==
5754 00:22:24.422532 Write leveling (Byte 0): 25 => 25
5755 00:22:24.425694 Write leveling (Byte 1): 27 => 27
5756 00:22:24.428845 DramcWriteLeveling(PI) end<-----
5757 00:22:24.428921
5758 00:22:24.428979 ==
5759 00:22:24.432545 Dram Type= 6, Freq= 0, CH_1, rank 1
5760 00:22:24.435426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 00:22:24.435503 ==
5762 00:22:24.439079 [Gating] SW mode calibration
5763 00:22:24.445503 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5764 00:22:24.452396 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5765 00:22:24.455725 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 00:22:24.458746 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 00:22:24.465337 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 00:22:24.468885 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 00:22:24.472359 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5770 00:22:24.475578 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5771 00:22:24.482178 0 14 24 | B1->B0 | 3333 2f2f | 0 1 | (0 0) (1 0)
5772 00:22:24.485363 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5773 00:22:24.488987 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5774 00:22:24.495721 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 00:22:24.498776 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 00:22:24.502457 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 00:22:24.508713 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5778 00:22:24.512482 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5779 00:22:24.515530 0 15 24 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
5780 00:22:24.522320 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
5781 00:22:24.525551 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 00:22:24.529185 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 00:22:24.535554 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 00:22:24.539420 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 00:22:24.542519 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 00:22:24.548790 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5787 00:22:24.552461 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5788 00:22:24.555613 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5789 00:22:24.562813 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 00:22:24.565663 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 00:22:24.569094 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 00:22:24.572510 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 00:22:24.579209 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 00:22:24.582703 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 00:22:24.586088 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 00:22:24.592577 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 00:22:24.595957 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 00:22:24.599026 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 00:22:24.606158 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 00:22:24.609413 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 00:22:24.612578 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 00:22:24.619525 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 00:22:24.622535 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5804 00:22:24.626367 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 00:22:24.629408 Total UI for P1: 0, mck2ui 16
5806 00:22:24.632575 best dqsien dly found for B0: ( 1, 2, 24)
5807 00:22:24.636354 Total UI for P1: 0, mck2ui 16
5808 00:22:24.639523 best dqsien dly found for B1: ( 1, 2, 26)
5809 00:22:24.642562 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5810 00:22:24.646390 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5811 00:22:24.646462
5812 00:22:24.649463 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5813 00:22:24.653070 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5814 00:22:24.656240 [Gating] SW calibration Done
5815 00:22:24.656340 ==
5816 00:22:24.659358 Dram Type= 6, Freq= 0, CH_1, rank 1
5817 00:22:24.666211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 00:22:24.666284 ==
5819 00:22:24.666341 RX Vref Scan: 0
5820 00:22:24.666396
5821 00:22:24.669153 RX Vref 0 -> 0, step: 1
5822 00:22:24.669228
5823 00:22:24.672844 RX Delay -80 -> 252, step: 8
5824 00:22:24.675964 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5825 00:22:24.679555 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5826 00:22:24.682770 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5827 00:22:24.685864 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5828 00:22:24.689593 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5829 00:22:24.696335 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5830 00:22:24.699332 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5831 00:22:24.702664 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5832 00:22:24.705968 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5833 00:22:24.709624 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5834 00:22:24.713151 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5835 00:22:24.719439 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5836 00:22:24.722688 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5837 00:22:24.726035 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5838 00:22:24.729247 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5839 00:22:24.732543 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5840 00:22:24.732614 ==
5841 00:22:24.736220 Dram Type= 6, Freq= 0, CH_1, rank 1
5842 00:22:24.743233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5843 00:22:24.743310 ==
5844 00:22:24.743370 DQS Delay:
5845 00:22:24.746315 DQS0 = 0, DQS1 = 0
5846 00:22:24.746379 DQM Delay:
5847 00:22:24.746433 DQM0 = 94, DQM1 = 88
5848 00:22:24.749433 DQ Delay:
5849 00:22:24.753131 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5850 00:22:24.756313 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5851 00:22:24.759327 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5852 00:22:24.763085 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5853 00:22:24.763154
5854 00:22:24.763212
5855 00:22:24.763266 ==
5856 00:22:24.766230 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 00:22:24.769915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 00:22:24.770039 ==
5859 00:22:24.770102
5860 00:22:24.770156
5861 00:22:24.772929 TX Vref Scan disable
5862 00:22:24.773019 == TX Byte 0 ==
5863 00:22:24.779382 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5864 00:22:24.783067 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5865 00:22:24.783138 == TX Byte 1 ==
5866 00:22:24.789908 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5867 00:22:24.793056 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5868 00:22:24.793145 ==
5869 00:22:24.796142 Dram Type= 6, Freq= 0, CH_1, rank 1
5870 00:22:24.800066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5871 00:22:24.800158 ==
5872 00:22:24.800243
5873 00:22:24.800325
5874 00:22:24.803045 TX Vref Scan disable
5875 00:22:24.806233 == TX Byte 0 ==
5876 00:22:24.809953 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5877 00:22:24.813105 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5878 00:22:24.816134 == TX Byte 1 ==
5879 00:22:24.819667 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5880 00:22:24.823178 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5881 00:22:24.823274
5882 00:22:24.826199 [DATLAT]
5883 00:22:24.826272 Freq=933, CH1 RK1
5884 00:22:24.826330
5885 00:22:24.829585 DATLAT Default: 0xb
5886 00:22:24.829676 0, 0xFFFF, sum = 0
5887 00:22:24.832992 1, 0xFFFF, sum = 0
5888 00:22:24.833087 2, 0xFFFF, sum = 0
5889 00:22:24.836266 3, 0xFFFF, sum = 0
5890 00:22:24.836365 4, 0xFFFF, sum = 0
5891 00:22:24.840154 5, 0xFFFF, sum = 0
5892 00:22:24.840250 6, 0xFFFF, sum = 0
5893 00:22:24.843064 7, 0xFFFF, sum = 0
5894 00:22:24.843158 8, 0xFFFF, sum = 0
5895 00:22:24.846554 9, 0xFFFF, sum = 0
5896 00:22:24.846653 10, 0x0, sum = 1
5897 00:22:24.849751 11, 0x0, sum = 2
5898 00:22:24.849847 12, 0x0, sum = 3
5899 00:22:24.852903 13, 0x0, sum = 4
5900 00:22:24.852997 best_step = 11
5901 00:22:24.853080
5902 00:22:24.853164 ==
5903 00:22:24.856296 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 00:22:24.859570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 00:22:24.863196 ==
5906 00:22:24.863292 RX Vref Scan: 0
5907 00:22:24.863377
5908 00:22:24.866441 RX Vref 0 -> 0, step: 1
5909 00:22:24.866539
5910 00:22:24.869554 RX Delay -61 -> 252, step: 4
5911 00:22:24.873284 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5912 00:22:24.876516 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5913 00:22:24.880063 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5914 00:22:24.886502 iDelay=199, Bit 3, Center 90 (-1 ~ 182) 184
5915 00:22:24.889964 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5916 00:22:24.893523 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5917 00:22:24.896573 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5918 00:22:24.900341 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5919 00:22:24.903437 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5920 00:22:24.910294 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5921 00:22:24.913337 iDelay=199, Bit 10, Center 92 (3 ~ 182) 180
5922 00:22:24.916594 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5923 00:22:24.920152 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5924 00:22:24.923165 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5925 00:22:24.930315 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5926 00:22:24.933512 iDelay=199, Bit 15, Center 100 (11 ~ 190) 180
5927 00:22:24.933600 ==
5928 00:22:24.937183 Dram Type= 6, Freq= 0, CH_1, rank 1
5929 00:22:24.939856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5930 00:22:24.939928 ==
5931 00:22:24.943284 DQS Delay:
5932 00:22:24.943348 DQS0 = 0, DQS1 = 0
5933 00:22:24.943402 DQM Delay:
5934 00:22:24.946841 DQM0 = 94, DQM1 = 91
5935 00:22:24.946902 DQ Delay:
5936 00:22:24.949939 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =90
5937 00:22:24.953125 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =90
5938 00:22:24.956777 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =84
5939 00:22:24.959813 DQ12 =98, DQ13 =100, DQ14 =100, DQ15 =100
5940 00:22:24.959902
5941 00:22:24.959983
5942 00:22:24.969927 [DQSOSCAuto] RK1, (LSB)MR18= 0x121b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
5943 00:22:24.970036 CH1 RK1: MR19=505, MR18=121B
5944 00:22:24.976681 CH1_RK1: MR19=0x505, MR18=0x121B, DQSOSC=413, MR23=63, INC=63, DEC=42
5945 00:22:24.980048 [RxdqsGatingPostProcess] freq 933
5946 00:22:24.986863 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5947 00:22:24.990175 best DQS0 dly(2T, 0.5T) = (0, 10)
5948 00:22:24.993892 best DQS1 dly(2T, 0.5T) = (0, 10)
5949 00:22:24.996810 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5950 00:22:25.000226 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5951 00:22:25.003312 best DQS0 dly(2T, 0.5T) = (0, 10)
5952 00:22:25.003388 best DQS1 dly(2T, 0.5T) = (0, 10)
5953 00:22:25.007156 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5954 00:22:25.010166 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5955 00:22:25.013254 Pre-setting of DQS Precalculation
5956 00:22:25.020036 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5957 00:22:25.026873 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5958 00:22:25.033680 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5959 00:22:25.033783
5960 00:22:25.033868
5961 00:22:25.036910 [Calibration Summary] 1866 Mbps
5962 00:22:25.036999 CH 0, Rank 0
5963 00:22:25.039993 SW Impedance : PASS
5964 00:22:25.043610 DUTY Scan : NO K
5965 00:22:25.043675 ZQ Calibration : PASS
5966 00:22:25.046673 Jitter Meter : NO K
5967 00:22:25.050106 CBT Training : PASS
5968 00:22:25.050212 Write leveling : PASS
5969 00:22:25.053780 RX DQS gating : PASS
5970 00:22:25.056990 RX DQ/DQS(RDDQC) : PASS
5971 00:22:25.057090 TX DQ/DQS : PASS
5972 00:22:25.060107 RX DATLAT : PASS
5973 00:22:25.063750 RX DQ/DQS(Engine): PASS
5974 00:22:25.063822 TX OE : NO K
5975 00:22:25.066879 All Pass.
5976 00:22:25.066955
5977 00:22:25.067012 CH 0, Rank 1
5978 00:22:25.070749 SW Impedance : PASS
5979 00:22:25.070825 DUTY Scan : NO K
5980 00:22:25.073704 ZQ Calibration : PASS
5981 00:22:25.073781 Jitter Meter : NO K
5982 00:22:25.076882 CBT Training : PASS
5983 00:22:25.080590 Write leveling : PASS
5984 00:22:25.080667 RX DQS gating : PASS
5985 00:22:25.083726 RX DQ/DQS(RDDQC) : PASS
5986 00:22:25.087007 TX DQ/DQS : PASS
5987 00:22:25.087083 RX DATLAT : PASS
5988 00:22:25.090584 RX DQ/DQS(Engine): PASS
5989 00:22:25.093398 TX OE : NO K
5990 00:22:25.093474 All Pass.
5991 00:22:25.093532
5992 00:22:25.093585 CH 1, Rank 0
5993 00:22:25.096817 SW Impedance : PASS
5994 00:22:25.100350 DUTY Scan : NO K
5995 00:22:25.100425 ZQ Calibration : PASS
5996 00:22:25.103712 Jitter Meter : NO K
5997 00:22:25.107233 CBT Training : PASS
5998 00:22:25.107323 Write leveling : PASS
5999 00:22:25.110439 RX DQS gating : PASS
6000 00:22:25.110516 RX DQ/DQS(RDDQC) : PASS
6001 00:22:25.113765 TX DQ/DQS : PASS
6002 00:22:25.117123 RX DATLAT : PASS
6003 00:22:25.117199 RX DQ/DQS(Engine): PASS
6004 00:22:25.120193 TX OE : NO K
6005 00:22:25.120269 All Pass.
6006 00:22:25.120328
6007 00:22:25.123878 CH 1, Rank 1
6008 00:22:25.123954 SW Impedance : PASS
6009 00:22:25.126903 DUTY Scan : NO K
6010 00:22:25.130629 ZQ Calibration : PASS
6011 00:22:25.130705 Jitter Meter : NO K
6012 00:22:25.133654 CBT Training : PASS
6013 00:22:25.137189 Write leveling : PASS
6014 00:22:25.137272 RX DQS gating : PASS
6015 00:22:25.140228 RX DQ/DQS(RDDQC) : PASS
6016 00:22:25.143886 TX DQ/DQS : PASS
6017 00:22:25.143962 RX DATLAT : PASS
6018 00:22:25.146979 RX DQ/DQS(Engine): PASS
6019 00:22:25.150179 TX OE : NO K
6020 00:22:25.150255 All Pass.
6021 00:22:25.150313
6022 00:22:25.150367 DramC Write-DBI off
6023 00:22:25.153810 PER_BANK_REFRESH: Hybrid Mode
6024 00:22:25.156832 TX_TRACKING: ON
6025 00:22:25.164058 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6026 00:22:25.167262 [FAST_K] Save calibration result to emmc
6027 00:22:25.173901 dramc_set_vcore_voltage set vcore to 650000
6028 00:22:25.173978 Read voltage for 400, 6
6029 00:22:25.174076 Vio18 = 0
6030 00:22:25.176961 Vcore = 650000
6031 00:22:25.177035 Vdram = 0
6032 00:22:25.177093 Vddq = 0
6033 00:22:25.180680 Vmddr = 0
6034 00:22:25.183762 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6035 00:22:25.190437 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6036 00:22:25.190530 MEM_TYPE=3, freq_sel=20
6037 00:22:25.194123 sv_algorithm_assistance_LP4_800
6038 00:22:25.200322 ============ PULL DRAM RESETB DOWN ============
6039 00:22:25.203893 ========== PULL DRAM RESETB DOWN end =========
6040 00:22:25.207001 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6041 00:22:25.210390 ===================================
6042 00:22:25.213812 LPDDR4 DRAM CONFIGURATION
6043 00:22:25.217355 ===================================
6044 00:22:25.217425 EX_ROW_EN[0] = 0x0
6045 00:22:25.220544 EX_ROW_EN[1] = 0x0
6046 00:22:25.223741 LP4Y_EN = 0x0
6047 00:22:25.223816 WORK_FSP = 0x0
6048 00:22:25.227054 WL = 0x2
6049 00:22:25.227130 RL = 0x2
6050 00:22:25.230503 BL = 0x2
6051 00:22:25.230579 RPST = 0x0
6052 00:22:25.233796 RD_PRE = 0x0
6053 00:22:25.233897 WR_PRE = 0x1
6054 00:22:25.236968 WR_PST = 0x0
6055 00:22:25.237044 DBI_WR = 0x0
6056 00:22:25.240387 DBI_RD = 0x0
6057 00:22:25.240477 OTF = 0x1
6058 00:22:25.244024 ===================================
6059 00:22:25.247025 ===================================
6060 00:22:25.250598 ANA top config
6061 00:22:25.253743 ===================================
6062 00:22:25.253811 DLL_ASYNC_EN = 0
6063 00:22:25.257575 ALL_SLAVE_EN = 1
6064 00:22:25.260670 NEW_RANK_MODE = 1
6065 00:22:25.263774 DLL_IDLE_MODE = 1
6066 00:22:25.267292 LP45_APHY_COMB_EN = 1
6067 00:22:25.267391 TX_ODT_DIS = 1
6068 00:22:25.270824 NEW_8X_MODE = 1
6069 00:22:25.273934 ===================================
6070 00:22:25.277056 ===================================
6071 00:22:25.280236 data_rate = 800
6072 00:22:25.284080 CKR = 1
6073 00:22:25.287187 DQ_P2S_RATIO = 4
6074 00:22:25.290547 ===================================
6075 00:22:25.290617 CA_P2S_RATIO = 4
6076 00:22:25.294125 DQ_CA_OPEN = 0
6077 00:22:25.297158 DQ_SEMI_OPEN = 1
6078 00:22:25.300269 CA_SEMI_OPEN = 1
6079 00:22:25.304114 CA_FULL_RATE = 0
6080 00:22:25.307238 DQ_CKDIV4_EN = 0
6081 00:22:25.307314 CA_CKDIV4_EN = 1
6082 00:22:25.311139 CA_PREDIV_EN = 0
6083 00:22:25.314225 PH8_DLY = 0
6084 00:22:25.317453 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6085 00:22:25.320355 DQ_AAMCK_DIV = 0
6086 00:22:25.320437 CA_AAMCK_DIV = 0
6087 00:22:25.324031 CA_ADMCK_DIV = 4
6088 00:22:25.327652 DQ_TRACK_CA_EN = 0
6089 00:22:25.330596 CA_PICK = 800
6090 00:22:25.334006 CA_MCKIO = 400
6091 00:22:25.337499 MCKIO_SEMI = 400
6092 00:22:25.341128 PLL_FREQ = 3016
6093 00:22:25.341204 DQ_UI_PI_RATIO = 32
6094 00:22:25.343916 CA_UI_PI_RATIO = 32
6095 00:22:25.347246 ===================================
6096 00:22:25.350599 ===================================
6097 00:22:25.353950 memory_type:LPDDR4
6098 00:22:25.357373 GP_NUM : 10
6099 00:22:25.357471 SRAM_EN : 1
6100 00:22:25.360492 MD32_EN : 0
6101 00:22:25.364263 ===================================
6102 00:22:25.367362 [ANA_INIT] >>>>>>>>>>>>>>
6103 00:22:25.367451 <<<<<< [CONFIGURE PHASE]: ANA_TX
6104 00:22:25.371076 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6105 00:22:25.374251 ===================================
6106 00:22:25.377242 data_rate = 800,PCW = 0X7400
6107 00:22:25.380596 ===================================
6108 00:22:25.384340 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6109 00:22:25.390724 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6110 00:22:25.400990 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6111 00:22:25.407362 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6112 00:22:25.410919 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6113 00:22:25.414012 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6114 00:22:25.414142 [ANA_INIT] flow start
6115 00:22:25.417178 [ANA_INIT] PLL >>>>>>>>
6116 00:22:25.420946 [ANA_INIT] PLL <<<<<<<<
6117 00:22:25.421038 [ANA_INIT] MIDPI >>>>>>>>
6118 00:22:25.423963 [ANA_INIT] MIDPI <<<<<<<<
6119 00:22:25.427572 [ANA_INIT] DLL >>>>>>>>
6120 00:22:25.427648 [ANA_INIT] flow end
6121 00:22:25.433643 ============ LP4 DIFF to SE enter ============
6122 00:22:25.436974 ============ LP4 DIFF to SE exit ============
6123 00:22:25.440552 [ANA_INIT] <<<<<<<<<<<<<
6124 00:22:25.443982 [Flow] Enable top DCM control >>>>>
6125 00:22:25.447100 [Flow] Enable top DCM control <<<<<
6126 00:22:25.447177 Enable DLL master slave shuffle
6127 00:22:25.454202 ==============================================================
6128 00:22:25.457173 Gating Mode config
6129 00:22:25.460706 ==============================================================
6130 00:22:25.464021 Config description:
6131 00:22:25.473539 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6132 00:22:25.480451 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6133 00:22:25.484000 SELPH_MODE 0: By rank 1: By Phase
6134 00:22:25.490440 ==============================================================
6135 00:22:25.493611 GAT_TRACK_EN = 0
6136 00:22:25.497486 RX_GATING_MODE = 2
6137 00:22:25.500542 RX_GATING_TRACK_MODE = 2
6138 00:22:25.504233 SELPH_MODE = 1
6139 00:22:25.504334 PICG_EARLY_EN = 1
6140 00:22:25.507195 VALID_LAT_VALUE = 1
6141 00:22:25.514016 ==============================================================
6142 00:22:25.517109 Enter into Gating configuration >>>>
6143 00:22:25.520894 Exit from Gating configuration <<<<
6144 00:22:25.523952 Enter into DVFS_PRE_config >>>>>
6145 00:22:25.534246 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6146 00:22:25.537335 Exit from DVFS_PRE_config <<<<<
6147 00:22:25.540317 Enter into PICG configuration >>>>
6148 00:22:25.543944 Exit from PICG configuration <<<<
6149 00:22:25.547042 [RX_INPUT] configuration >>>>>
6150 00:22:25.550476 [RX_INPUT] configuration <<<<<
6151 00:22:25.554104 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6152 00:22:25.560780 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6153 00:22:25.567162 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6154 00:22:25.574177 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6155 00:22:25.577142 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6156 00:22:25.584059 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6157 00:22:25.587656 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6158 00:22:25.593857 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6159 00:22:25.597433 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6160 00:22:25.601161 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6161 00:22:25.604113 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6162 00:22:25.610584 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6163 00:22:25.614290 ===================================
6164 00:22:25.614381 LPDDR4 DRAM CONFIGURATION
6165 00:22:25.617401 ===================================
6166 00:22:25.620664 EX_ROW_EN[0] = 0x0
6167 00:22:25.624296 EX_ROW_EN[1] = 0x0
6168 00:22:25.624389 LP4Y_EN = 0x0
6169 00:22:25.627601 WORK_FSP = 0x0
6170 00:22:25.627677 WL = 0x2
6171 00:22:25.630508 RL = 0x2
6172 00:22:25.630574 BL = 0x2
6173 00:22:25.634170 RPST = 0x0
6174 00:22:25.634241 RD_PRE = 0x0
6175 00:22:25.637226 WR_PRE = 0x1
6176 00:22:25.637293 WR_PST = 0x0
6177 00:22:25.640794 DBI_WR = 0x0
6178 00:22:25.640857 DBI_RD = 0x0
6179 00:22:25.644242 OTF = 0x1
6180 00:22:25.647225 ===================================
6181 00:22:25.651027 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6182 00:22:25.654012 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6183 00:22:25.660439 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6184 00:22:25.664138 ===================================
6185 00:22:25.664231 LPDDR4 DRAM CONFIGURATION
6186 00:22:25.667846 ===================================
6187 00:22:25.670749 EX_ROW_EN[0] = 0x10
6188 00:22:25.670825 EX_ROW_EN[1] = 0x0
6189 00:22:25.674154 LP4Y_EN = 0x0
6190 00:22:25.677442 WORK_FSP = 0x0
6191 00:22:25.677518 WL = 0x2
6192 00:22:25.681016 RL = 0x2
6193 00:22:25.681092 BL = 0x2
6194 00:22:25.684393 RPST = 0x0
6195 00:22:25.684468 RD_PRE = 0x0
6196 00:22:25.687514 WR_PRE = 0x1
6197 00:22:25.687590 WR_PST = 0x0
6198 00:22:25.690677 DBI_WR = 0x0
6199 00:22:25.690752 DBI_RD = 0x0
6200 00:22:25.694256 OTF = 0x1
6201 00:22:25.697289 ===================================
6202 00:22:25.703855 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6203 00:22:25.707364 nWR fixed to 30
6204 00:22:25.707480 [ModeRegInit_LP4] CH0 RK0
6205 00:22:25.710485 [ModeRegInit_LP4] CH0 RK1
6206 00:22:25.714117 [ModeRegInit_LP4] CH1 RK0
6207 00:22:25.714193 [ModeRegInit_LP4] CH1 RK1
6208 00:22:25.717067 match AC timing 19
6209 00:22:25.720705 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6210 00:22:25.723622 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6211 00:22:25.730473 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6212 00:22:25.733657 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6213 00:22:25.740423 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6214 00:22:25.740500 ==
6215 00:22:25.744168 Dram Type= 6, Freq= 0, CH_0, rank 0
6216 00:22:25.747128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6217 00:22:25.747205 ==
6218 00:22:25.754455 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6219 00:22:25.757528 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6220 00:22:25.760701 [CA 0] Center 36 (8~64) winsize 57
6221 00:22:25.764153 [CA 1] Center 36 (8~64) winsize 57
6222 00:22:25.767555 [CA 2] Center 36 (8~64) winsize 57
6223 00:22:25.771147 [CA 3] Center 36 (8~64) winsize 57
6224 00:22:25.774372 [CA 4] Center 36 (8~64) winsize 57
6225 00:22:25.777247 [CA 5] Center 36 (8~64) winsize 57
6226 00:22:25.777367
6227 00:22:25.780756 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6228 00:22:25.780833
6229 00:22:25.784190 [CATrainingPosCal] consider 1 rank data
6230 00:22:25.787733 u2DelayCellTimex100 = 270/100 ps
6231 00:22:25.790722 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 00:22:25.794304 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 00:22:25.797266 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 00:22:25.801032 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 00:22:25.804103 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 00:22:25.810725 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 00:22:25.810799
6238 00:22:25.814257 CA PerBit enable=1, Macro0, CA PI delay=36
6239 00:22:25.814333
6240 00:22:25.817847 [CBTSetCACLKResult] CA Dly = 36
6241 00:22:25.817952 CS Dly: 1 (0~32)
6242 00:22:25.818046 ==
6243 00:22:25.821177 Dram Type= 6, Freq= 0, CH_0, rank 1
6244 00:22:25.824106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6245 00:22:25.827813 ==
6246 00:22:25.830871 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6247 00:22:25.837468 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6248 00:22:25.840767 [CA 0] Center 36 (8~64) winsize 57
6249 00:22:25.844325 [CA 1] Center 36 (8~64) winsize 57
6250 00:22:25.847367 [CA 2] Center 36 (8~64) winsize 57
6251 00:22:25.851100 [CA 3] Center 36 (8~64) winsize 57
6252 00:22:25.853998 [CA 4] Center 36 (8~64) winsize 57
6253 00:22:25.857680 [CA 5] Center 36 (8~64) winsize 57
6254 00:22:25.857782
6255 00:22:25.860914 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6256 00:22:25.861012
6257 00:22:25.864132 [CATrainingPosCal] consider 2 rank data
6258 00:22:25.867422 u2DelayCellTimex100 = 270/100 ps
6259 00:22:25.870884 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 00:22:25.874310 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 00:22:25.877680 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 00:22:25.881275 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 00:22:25.884388 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 00:22:25.887589 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 00:22:25.887673
6266 00:22:25.891117 CA PerBit enable=1, Macro0, CA PI delay=36
6267 00:22:25.891198
6268 00:22:25.894440 [CBTSetCACLKResult] CA Dly = 36
6269 00:22:25.897822 CS Dly: 1 (0~32)
6270 00:22:25.897893
6271 00:22:25.901221 ----->DramcWriteLeveling(PI) begin...
6272 00:22:25.901302 ==
6273 00:22:25.904875 Dram Type= 6, Freq= 0, CH_0, rank 0
6274 00:22:25.908128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6275 00:22:25.908204 ==
6276 00:22:25.911178 Write leveling (Byte 0): 40 => 8
6277 00:22:25.915171 Write leveling (Byte 1): 32 => 0
6278 00:22:25.917881 DramcWriteLeveling(PI) end<-----
6279 00:22:25.917957
6280 00:22:25.918046 ==
6281 00:22:25.921608 Dram Type= 6, Freq= 0, CH_0, rank 0
6282 00:22:25.924897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6283 00:22:25.925037 ==
6284 00:22:25.927805 [Gating] SW mode calibration
6285 00:22:25.934382 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6286 00:22:25.941052 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6287 00:22:25.944839 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6288 00:22:25.947833 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6289 00:22:25.954436 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6290 00:22:25.957910 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6291 00:22:25.961567 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 00:22:25.967938 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 00:22:25.971794 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6294 00:22:25.974853 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6295 00:22:25.978105 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6296 00:22:25.981563 Total UI for P1: 0, mck2ui 16
6297 00:22:25.984971 best dqsien dly found for B0: ( 0, 14, 24)
6298 00:22:25.988376 Total UI for P1: 0, mck2ui 16
6299 00:22:25.991382 best dqsien dly found for B1: ( 0, 14, 24)
6300 00:22:25.994967 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6301 00:22:26.001339 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6302 00:22:26.001415
6303 00:22:26.004945 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6304 00:22:26.008334 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6305 00:22:26.011740 [Gating] SW calibration Done
6306 00:22:26.011842 ==
6307 00:22:26.014768 Dram Type= 6, Freq= 0, CH_0, rank 0
6308 00:22:26.017853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6309 00:22:26.017954 ==
6310 00:22:26.018046 RX Vref Scan: 0
6311 00:22:26.021689
6312 00:22:26.021779 RX Vref 0 -> 0, step: 1
6313 00:22:26.021860
6314 00:22:26.024832 RX Delay -410 -> 252, step: 16
6315 00:22:26.028511 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6316 00:22:26.034727 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6317 00:22:26.038118 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6318 00:22:26.041632 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6319 00:22:26.044718 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6320 00:22:26.051474 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6321 00:22:26.055177 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6322 00:22:26.058190 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6323 00:22:26.061763 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6324 00:22:26.064872 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6325 00:22:26.071776 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6326 00:22:26.074962 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6327 00:22:26.078082 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6328 00:22:26.084794 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6329 00:22:26.088476 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6330 00:22:26.091468 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6331 00:22:26.091544 ==
6332 00:22:26.095037 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 00:22:26.098540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 00:22:26.098619 ==
6335 00:22:26.101601 DQS Delay:
6336 00:22:26.101700 DQS0 = 35, DQS1 = 51
6337 00:22:26.105212 DQM Delay:
6338 00:22:26.105303 DQM0 = 7, DQM1 = 10
6339 00:22:26.108421 DQ Delay:
6340 00:22:26.108523 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6341 00:22:26.111421 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6342 00:22:26.114938 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6343 00:22:26.118268 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6344 00:22:26.118343
6345 00:22:26.118401
6346 00:22:26.118455 ==
6347 00:22:26.121586 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 00:22:26.128331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 00:22:26.128407 ==
6350 00:22:26.128496
6351 00:22:26.128548
6352 00:22:26.128599 TX Vref Scan disable
6353 00:22:26.131569 == TX Byte 0 ==
6354 00:22:26.135318 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6355 00:22:26.138303 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6356 00:22:26.141837 == TX Byte 1 ==
6357 00:22:26.144944 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6358 00:22:26.148583 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6359 00:22:26.148651 ==
6360 00:22:26.151421 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 00:22:26.157964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 00:22:26.158078 ==
6363 00:22:26.158137
6364 00:22:26.158190
6365 00:22:26.158241 TX Vref Scan disable
6366 00:22:26.161504 == TX Byte 0 ==
6367 00:22:26.165266 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6368 00:22:26.168101 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6369 00:22:26.171906 == TX Byte 1 ==
6370 00:22:26.175010 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6371 00:22:26.178169 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6372 00:22:26.178244
6373 00:22:26.181829 [DATLAT]
6374 00:22:26.181904 Freq=400, CH0 RK0
6375 00:22:26.181962
6376 00:22:26.184755 DATLAT Default: 0xf
6377 00:22:26.184830 0, 0xFFFF, sum = 0
6378 00:22:26.188655 1, 0xFFFF, sum = 0
6379 00:22:26.188761 2, 0xFFFF, sum = 0
6380 00:22:26.191629 3, 0xFFFF, sum = 0
6381 00:22:26.191704 4, 0xFFFF, sum = 0
6382 00:22:26.195243 5, 0xFFFF, sum = 0
6383 00:22:26.195320 6, 0xFFFF, sum = 0
6384 00:22:26.198244 7, 0xFFFF, sum = 0
6385 00:22:26.198314 8, 0xFFFF, sum = 0
6386 00:22:26.201738 9, 0xFFFF, sum = 0
6387 00:22:26.201817 10, 0xFFFF, sum = 0
6388 00:22:26.204941 11, 0xFFFF, sum = 0
6389 00:22:26.208125 12, 0xFFFF, sum = 0
6390 00:22:26.208209 13, 0x0, sum = 1
6391 00:22:26.211682 14, 0x0, sum = 2
6392 00:22:26.211761 15, 0x0, sum = 3
6393 00:22:26.211821 16, 0x0, sum = 4
6394 00:22:26.215417 best_step = 14
6395 00:22:26.215492
6396 00:22:26.215555 ==
6397 00:22:26.218533 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 00:22:26.221477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 00:22:26.221567 ==
6400 00:22:26.225081 RX Vref Scan: 1
6401 00:22:26.225169
6402 00:22:26.225258 RX Vref 0 -> 0, step: 1
6403 00:22:26.228379
6404 00:22:26.228467 RX Delay -343 -> 252, step: 8
6405 00:22:26.228546
6406 00:22:26.231907 Set Vref, RX VrefLevel [Byte0]: 52
6407 00:22:26.234922 [Byte1]: 51
6408 00:22:26.239931
6409 00:22:26.239996 Final RX Vref Byte 0 = 52 to rank0
6410 00:22:26.243607 Final RX Vref Byte 1 = 51 to rank0
6411 00:22:26.246639 Final RX Vref Byte 0 = 52 to rank1
6412 00:22:26.250386 Final RX Vref Byte 1 = 51 to rank1==
6413 00:22:26.253539 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 00:22:26.256557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 00:22:26.260081 ==
6416 00:22:26.260156 DQS Delay:
6417 00:22:26.260214 DQS0 = 44, DQS1 = 60
6418 00:22:26.263471 DQM Delay:
6419 00:22:26.263562 DQM0 = 11, DQM1 = 14
6420 00:22:26.266868 DQ Delay:
6421 00:22:26.270364 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6422 00:22:26.270440 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6423 00:22:26.273412 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =12
6424 00:22:26.277203 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6425 00:22:26.277277
6426 00:22:26.277335
6427 00:22:26.287245 [DQSOSCAuto] RK0, (LSB)MR18= 0x925f, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6428 00:22:26.290356 CH0 RK0: MR19=C0C, MR18=925F
6429 00:22:26.297171 CH0_RK0: MR19=0xC0C, MR18=0x925F, DQSOSC=391, MR23=63, INC=386, DEC=257
6430 00:22:26.297246 ==
6431 00:22:26.300326 Dram Type= 6, Freq= 0, CH_0, rank 1
6432 00:22:26.303538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 00:22:26.303606 ==
6434 00:22:26.306983 [Gating] SW mode calibration
6435 00:22:26.313695 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6436 00:22:26.316703 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6437 00:22:26.323381 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6438 00:22:26.326575 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6439 00:22:26.330369 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6440 00:22:26.337081 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6441 00:22:26.339785 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 00:22:26.343157 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 00:22:26.349900 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 00:22:26.353553 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6445 00:22:26.356631 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6446 00:22:26.360369 Total UI for P1: 0, mck2ui 16
6447 00:22:26.363454 best dqsien dly found for B0: ( 0, 14, 24)
6448 00:22:26.366676 Total UI for P1: 0, mck2ui 16
6449 00:22:26.370254 best dqsien dly found for B1: ( 0, 14, 24)
6450 00:22:26.373443 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6451 00:22:26.376482 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6452 00:22:26.376556
6453 00:22:26.383103 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6454 00:22:26.386614 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6455 00:22:26.390257 [Gating] SW calibration Done
6456 00:22:26.390355 ==
6457 00:22:26.393407 Dram Type= 6, Freq= 0, CH_0, rank 1
6458 00:22:26.396546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6459 00:22:26.396660 ==
6460 00:22:26.396746 RX Vref Scan: 0
6461 00:22:26.396855
6462 00:22:26.400299 RX Vref 0 -> 0, step: 1
6463 00:22:26.400386
6464 00:22:26.403414 RX Delay -410 -> 252, step: 16
6465 00:22:26.406539 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6466 00:22:26.413439 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6467 00:22:26.416409 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6468 00:22:26.420000 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6469 00:22:26.423577 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6470 00:22:26.427136 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6471 00:22:26.433436 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6472 00:22:26.437226 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6473 00:22:26.440280 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6474 00:22:26.443305 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6475 00:22:26.450388 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6476 00:22:26.453716 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6477 00:22:26.456886 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6478 00:22:26.459999 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6479 00:22:26.467174 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6480 00:22:26.470246 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6481 00:22:26.470319 ==
6482 00:22:26.473360 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 00:22:26.477050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 00:22:26.477124 ==
6485 00:22:26.480256 DQS Delay:
6486 00:22:26.480326 DQS0 = 43, DQS1 = 51
6487 00:22:26.483495 DQM Delay:
6488 00:22:26.483563 DQM0 = 12, DQM1 = 10
6489 00:22:26.483638 DQ Delay:
6490 00:22:26.486926 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6491 00:22:26.490248 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6492 00:22:26.493285 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6493 00:22:26.496620 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6494 00:22:26.496689
6495 00:22:26.496763
6496 00:22:26.496832 ==
6497 00:22:26.500246 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 00:22:26.503356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 00:22:26.506627 ==
6500 00:22:26.506696
6501 00:22:26.506772
6502 00:22:26.506864 TX Vref Scan disable
6503 00:22:26.510391 == TX Byte 0 ==
6504 00:22:26.513221 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6505 00:22:26.517061 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6506 00:22:26.520122 == TX Byte 1 ==
6507 00:22:26.523380 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6508 00:22:26.526746 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6509 00:22:26.526820 ==
6510 00:22:26.530224 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 00:22:26.533370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 00:22:26.537134 ==
6513 00:22:26.537204
6514 00:22:26.537277
6515 00:22:26.537346 TX Vref Scan disable
6516 00:22:26.540406 == TX Byte 0 ==
6517 00:22:26.543379 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6518 00:22:26.546631 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6519 00:22:26.550293 == TX Byte 1 ==
6520 00:22:26.553372 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6521 00:22:26.557161 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6522 00:22:26.557237
6523 00:22:26.557313 [DATLAT]
6524 00:22:26.560166 Freq=400, CH0 RK1
6525 00:22:26.560237
6526 00:22:26.563332 DATLAT Default: 0xe
6527 00:22:26.563402 0, 0xFFFF, sum = 0
6528 00:22:26.567107 1, 0xFFFF, sum = 0
6529 00:22:26.567175 2, 0xFFFF, sum = 0
6530 00:22:26.570175 3, 0xFFFF, sum = 0
6531 00:22:26.570243 4, 0xFFFF, sum = 0
6532 00:22:26.573495 5, 0xFFFF, sum = 0
6533 00:22:26.573565 6, 0xFFFF, sum = 0
6534 00:22:26.576796 7, 0xFFFF, sum = 0
6535 00:22:26.576892 8, 0xFFFF, sum = 0
6536 00:22:26.580096 9, 0xFFFF, sum = 0
6537 00:22:26.580183 10, 0xFFFF, sum = 0
6538 00:22:26.583321 11, 0xFFFF, sum = 0
6539 00:22:26.583391 12, 0xFFFF, sum = 0
6540 00:22:26.586864 13, 0x0, sum = 1
6541 00:22:26.586944 14, 0x0, sum = 2
6542 00:22:26.590046 15, 0x0, sum = 3
6543 00:22:26.590116 16, 0x0, sum = 4
6544 00:22:26.593835 best_step = 14
6545 00:22:26.593931
6546 00:22:26.594062 ==
6547 00:22:26.596861 Dram Type= 6, Freq= 0, CH_0, rank 1
6548 00:22:26.600357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6549 00:22:26.600430 ==
6550 00:22:26.603663 RX Vref Scan: 0
6551 00:22:26.603783
6552 00:22:26.603842 RX Vref 0 -> 0, step: 1
6553 00:22:26.603915
6554 00:22:26.606846 RX Delay -343 -> 252, step: 8
6555 00:22:26.614471 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6556 00:22:26.617944 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6557 00:22:26.621032 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6558 00:22:26.624963 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6559 00:22:26.631172 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6560 00:22:26.634802 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6561 00:22:26.638254 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6562 00:22:26.641222 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6563 00:22:26.648157 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6564 00:22:26.651335 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6565 00:22:26.654546 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6566 00:22:26.658111 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6567 00:22:26.664906 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6568 00:22:26.668270 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6569 00:22:26.671352 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6570 00:22:26.674971 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6571 00:22:26.677925 ==
6572 00:22:26.681670 Dram Type= 6, Freq= 0, CH_0, rank 1
6573 00:22:26.684686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6574 00:22:26.684759 ==
6575 00:22:26.684817 DQS Delay:
6576 00:22:26.687872 DQS0 = 48, DQS1 = 60
6577 00:22:26.687936 DQM Delay:
6578 00:22:26.691246 DQM0 = 13, DQM1 = 12
6579 00:22:26.691316 DQ Delay:
6580 00:22:26.694773 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6581 00:22:26.698164 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6582 00:22:26.701305 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6583 00:22:26.705150 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6584 00:22:26.705245
6585 00:22:26.705319
6586 00:22:26.711726 [DQSOSCAuto] RK1, (LSB)MR18= 0x996b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6587 00:22:26.714529 CH0 RK1: MR19=C0C, MR18=996B
6588 00:22:26.721233 CH0_RK1: MR19=0xC0C, MR18=0x996B, DQSOSC=390, MR23=63, INC=388, DEC=258
6589 00:22:26.724687 [RxdqsGatingPostProcess] freq 400
6590 00:22:26.727917 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6591 00:22:26.731617 best DQS0 dly(2T, 0.5T) = (0, 10)
6592 00:22:26.734731 best DQS1 dly(2T, 0.5T) = (0, 10)
6593 00:22:26.737904 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6594 00:22:26.741520 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6595 00:22:26.744948 best DQS0 dly(2T, 0.5T) = (0, 10)
6596 00:22:26.748032 best DQS1 dly(2T, 0.5T) = (0, 10)
6597 00:22:26.751740 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6598 00:22:26.754849 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6599 00:22:26.757961 Pre-setting of DQS Precalculation
6600 00:22:26.761818 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6601 00:22:26.761911 ==
6602 00:22:26.764932 Dram Type= 6, Freq= 0, CH_1, rank 0
6603 00:22:26.771461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6604 00:22:26.771536 ==
6605 00:22:26.774588 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6606 00:22:26.781428 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6607 00:22:26.785273 [CA 0] Center 36 (8~64) winsize 57
6608 00:22:26.788090 [CA 1] Center 36 (8~64) winsize 57
6609 00:22:26.791771 [CA 2] Center 36 (8~64) winsize 57
6610 00:22:26.794910 [CA 3] Center 36 (8~64) winsize 57
6611 00:22:26.797873 [CA 4] Center 36 (8~64) winsize 57
6612 00:22:26.801645 [CA 5] Center 36 (8~64) winsize 57
6613 00:22:26.801720
6614 00:22:26.805369 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6615 00:22:26.805444
6616 00:22:26.808296 [CATrainingPosCal] consider 1 rank data
6617 00:22:26.811161 u2DelayCellTimex100 = 270/100 ps
6618 00:22:26.814916 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 00:22:26.817908 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 00:22:26.821595 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 00:22:26.824721 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 00:22:26.828281 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 00:22:26.831351 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 00:22:26.831420
6625 00:22:26.837922 CA PerBit enable=1, Macro0, CA PI delay=36
6626 00:22:26.838038
6627 00:22:26.838098 [CBTSetCACLKResult] CA Dly = 36
6628 00:22:26.841626 CS Dly: 1 (0~32)
6629 00:22:26.841727 ==
6630 00:22:26.844521 Dram Type= 6, Freq= 0, CH_1, rank 1
6631 00:22:26.848359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6632 00:22:26.848435 ==
6633 00:22:26.854780 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6634 00:22:26.861606 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6635 00:22:26.864784 [CA 0] Center 36 (8~64) winsize 57
6636 00:22:26.868436 [CA 1] Center 36 (8~64) winsize 57
6637 00:22:26.868512 [CA 2] Center 36 (8~64) winsize 57
6638 00:22:26.871637 [CA 3] Center 36 (8~64) winsize 57
6639 00:22:26.874682 [CA 4] Center 36 (8~64) winsize 57
6640 00:22:26.878514 [CA 5] Center 36 (8~64) winsize 57
6641 00:22:26.878622
6642 00:22:26.881555 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6643 00:22:26.881630
6644 00:22:26.888434 [CATrainingPosCal] consider 2 rank data
6645 00:22:26.888510 u2DelayCellTimex100 = 270/100 ps
6646 00:22:26.895137 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 00:22:26.898199 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 00:22:26.901958 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 00:22:26.905204 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 00:22:26.908423 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 00:22:26.912045 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 00:22:26.912141
6653 00:22:26.915024 CA PerBit enable=1, Macro0, CA PI delay=36
6654 00:22:26.915122
6655 00:22:26.918465 [CBTSetCACLKResult] CA Dly = 36
6656 00:22:26.918534 CS Dly: 1 (0~32)
6657 00:22:26.921766
6658 00:22:26.924883 ----->DramcWriteLeveling(PI) begin...
6659 00:22:26.924960 ==
6660 00:22:26.928393 Dram Type= 6, Freq= 0, CH_1, rank 0
6661 00:22:26.931546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6662 00:22:26.931622 ==
6663 00:22:26.935299 Write leveling (Byte 0): 40 => 8
6664 00:22:26.938370 Write leveling (Byte 1): 40 => 8
6665 00:22:26.941570 DramcWriteLeveling(PI) end<-----
6666 00:22:26.941646
6667 00:22:26.941705 ==
6668 00:22:26.945005 Dram Type= 6, Freq= 0, CH_1, rank 0
6669 00:22:26.948504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 00:22:26.948581 ==
6671 00:22:26.951615 [Gating] SW mode calibration
6672 00:22:26.958508 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6673 00:22:26.961650 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6674 00:22:26.968514 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6675 00:22:26.971607 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6676 00:22:26.975349 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6677 00:22:26.981577 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6678 00:22:26.985198 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 00:22:26.988309 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 00:22:26.995185 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6681 00:22:26.998634 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6682 00:22:27.001795 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6683 00:22:27.005087 Total UI for P1: 0, mck2ui 16
6684 00:22:27.008267 best dqsien dly found for B0: ( 0, 14, 24)
6685 00:22:27.012064 Total UI for P1: 0, mck2ui 16
6686 00:22:27.015072 best dqsien dly found for B1: ( 0, 14, 24)
6687 00:22:27.018261 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6688 00:22:27.022066 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6689 00:22:27.022134
6690 00:22:27.028707 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6691 00:22:27.031794 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6692 00:22:27.031866 [Gating] SW calibration Done
6693 00:22:27.035237 ==
6694 00:22:27.038308 Dram Type= 6, Freq= 0, CH_1, rank 0
6695 00:22:27.042024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6696 00:22:27.042104 ==
6697 00:22:27.042165 RX Vref Scan: 0
6698 00:22:27.042220
6699 00:22:27.045421 RX Vref 0 -> 0, step: 1
6700 00:22:27.045487
6701 00:22:27.048799 RX Delay -410 -> 252, step: 16
6702 00:22:27.051916 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6703 00:22:27.055367 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6704 00:22:27.061855 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6705 00:22:27.065162 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6706 00:22:27.068647 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6707 00:22:27.072072 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6708 00:22:27.078564 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6709 00:22:27.082188 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6710 00:22:27.085419 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6711 00:22:27.088874 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6712 00:22:27.095074 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6713 00:22:27.098743 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6714 00:22:27.101877 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6715 00:22:27.105505 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6716 00:22:27.111932 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6717 00:22:27.115593 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6718 00:22:27.115678 ==
6719 00:22:27.118626 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 00:22:27.121790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 00:22:27.121910 ==
6722 00:22:27.125551 DQS Delay:
6723 00:22:27.125659 DQS0 = 51, DQS1 = 59
6724 00:22:27.128568 DQM Delay:
6725 00:22:27.128658 DQM0 = 19, DQM1 = 17
6726 00:22:27.128748 DQ Delay:
6727 00:22:27.132342 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6728 00:22:27.135641 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6729 00:22:27.138640 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6730 00:22:27.142292 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6731 00:22:27.142381
6732 00:22:27.142461
6733 00:22:27.142549 ==
6734 00:22:27.145443 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 00:22:27.152583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 00:22:27.152652 ==
6737 00:22:27.152707
6738 00:22:27.152760
6739 00:22:27.152810 TX Vref Scan disable
6740 00:22:27.155716 == TX Byte 0 ==
6741 00:22:27.158937 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6742 00:22:27.162225 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6743 00:22:27.165547 == TX Byte 1 ==
6744 00:22:27.169048 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6745 00:22:27.171965 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6746 00:22:27.172088 ==
6747 00:22:27.175305 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 00:22:27.182408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 00:22:27.182508 ==
6750 00:22:27.182594
6751 00:22:27.182748
6752 00:22:27.182836 TX Vref Scan disable
6753 00:22:27.185360 == TX Byte 0 ==
6754 00:22:27.189015 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6755 00:22:27.192261 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6756 00:22:27.195267 == TX Byte 1 ==
6757 00:22:27.198949 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6758 00:22:27.202272 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6759 00:22:27.202342
6760 00:22:27.205912 [DATLAT]
6761 00:22:27.206043 Freq=400, CH1 RK0
6762 00:22:27.206132
6763 00:22:27.208846 DATLAT Default: 0xf
6764 00:22:27.208964 0, 0xFFFF, sum = 0
6765 00:22:27.212123 1, 0xFFFF, sum = 0
6766 00:22:27.212222 2, 0xFFFF, sum = 0
6767 00:22:27.215693 3, 0xFFFF, sum = 0
6768 00:22:27.215795 4, 0xFFFF, sum = 0
6769 00:22:27.218864 5, 0xFFFF, sum = 0
6770 00:22:27.218954 6, 0xFFFF, sum = 0
6771 00:22:27.222181 7, 0xFFFF, sum = 0
6772 00:22:27.222274 8, 0xFFFF, sum = 0
6773 00:22:27.225749 9, 0xFFFF, sum = 0
6774 00:22:27.225825 10, 0xFFFF, sum = 0
6775 00:22:27.228875 11, 0xFFFF, sum = 0
6776 00:22:27.228944 12, 0xFFFF, sum = 0
6777 00:22:27.231971 13, 0x0, sum = 1
6778 00:22:27.232039 14, 0x0, sum = 2
6779 00:22:27.235770 15, 0x0, sum = 3
6780 00:22:27.235833 16, 0x0, sum = 4
6781 00:22:27.238985 best_step = 14
6782 00:22:27.239060
6783 00:22:27.239118 ==
6784 00:22:27.242241 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 00:22:27.245314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 00:22:27.245391 ==
6787 00:22:27.249012 RX Vref Scan: 1
6788 00:22:27.249088
6789 00:22:27.249161 RX Vref 0 -> 0, step: 1
6790 00:22:27.249220
6791 00:22:27.251987 RX Delay -359 -> 252, step: 8
6792 00:22:27.252062
6793 00:22:27.255605 Set Vref, RX VrefLevel [Byte0]: 55
6794 00:22:27.258852 [Byte1]: 50
6795 00:22:27.263555
6796 00:22:27.263681 Final RX Vref Byte 0 = 55 to rank0
6797 00:22:27.266796 Final RX Vref Byte 1 = 50 to rank0
6798 00:22:27.270462 Final RX Vref Byte 0 = 55 to rank1
6799 00:22:27.273426 Final RX Vref Byte 1 = 50 to rank1==
6800 00:22:27.276531 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 00:22:27.283612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 00:22:27.283688 ==
6803 00:22:27.283746 DQS Delay:
6804 00:22:27.286860 DQS0 = 48, DQS1 = 60
6805 00:22:27.286928 DQM Delay:
6806 00:22:27.286983 DQM0 = 12, DQM1 = 12
6807 00:22:27.290488 DQ Delay:
6808 00:22:27.294199 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6809 00:22:27.294299 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6810 00:22:27.296742 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6811 00:22:27.299867 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6812 00:22:27.299969
6813 00:22:27.303447
6814 00:22:27.309869 [DQSOSCAuto] RK0, (LSB)MR18= 0x8b30, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6815 00:22:27.313284 CH1 RK0: MR19=C0C, MR18=8B30
6816 00:22:27.320020 CH1_RK0: MR19=0xC0C, MR18=0x8B30, DQSOSC=392, MR23=63, INC=384, DEC=256
6817 00:22:27.320098 ==
6818 00:22:27.323162 Dram Type= 6, Freq= 0, CH_1, rank 1
6819 00:22:27.326870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 00:22:27.326969 ==
6821 00:22:27.329887 [Gating] SW mode calibration
6822 00:22:27.336776 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6823 00:22:27.343673 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6824 00:22:27.347033 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6825 00:22:27.350043 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6826 00:22:27.353158 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6827 00:22:27.359949 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6828 00:22:27.363610 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 00:22:27.366698 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6830 00:22:27.373389 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6831 00:22:27.377109 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6832 00:22:27.380298 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6833 00:22:27.383448 Total UI for P1: 0, mck2ui 16
6834 00:22:27.386556 best dqsien dly found for B0: ( 0, 14, 24)
6835 00:22:27.390349 Total UI for P1: 0, mck2ui 16
6836 00:22:27.393458 best dqsien dly found for B1: ( 0, 14, 24)
6837 00:22:27.397092 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6838 00:22:27.400081 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6839 00:22:27.400175
6840 00:22:27.406817 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6841 00:22:27.410276 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6842 00:22:27.410374 [Gating] SW calibration Done
6843 00:22:27.413636 ==
6844 00:22:27.416673 Dram Type= 6, Freq= 0, CH_1, rank 1
6845 00:22:27.420420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6846 00:22:27.420518 ==
6847 00:22:27.420614 RX Vref Scan: 0
6848 00:22:27.420701
6849 00:22:27.423927 RX Vref 0 -> 0, step: 1
6850 00:22:27.424016
6851 00:22:27.427133 RX Delay -410 -> 252, step: 16
6852 00:22:27.430176 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6853 00:22:27.433639 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6854 00:22:27.440315 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6855 00:22:27.443588 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6856 00:22:27.447284 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6857 00:22:27.450485 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6858 00:22:27.457180 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6859 00:22:27.460382 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6860 00:22:27.463487 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6861 00:22:27.467163 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6862 00:22:27.473861 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6863 00:22:27.476849 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6864 00:22:27.480605 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6865 00:22:27.483804 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6866 00:22:27.490619 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6867 00:22:27.493693 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6868 00:22:27.493787 ==
6869 00:22:27.497474 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 00:22:27.500591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 00:22:27.500686 ==
6872 00:22:27.503559 DQS Delay:
6873 00:22:27.503623 DQS0 = 43, DQS1 = 59
6874 00:22:27.503676 DQM Delay:
6875 00:22:27.507261 DQM0 = 9, DQM1 = 17
6876 00:22:27.507324 DQ Delay:
6877 00:22:27.510174 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6878 00:22:27.513799 DQ4 =8, DQ5 =16, DQ6 =24, DQ7 =8
6879 00:22:27.517476 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6880 00:22:27.520508 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6881 00:22:27.520601
6882 00:22:27.520659
6883 00:22:27.520710 ==
6884 00:22:27.523852 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 00:22:27.527518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 00:22:27.527580 ==
6887 00:22:27.527634
6888 00:22:27.530623
6889 00:22:27.530684 TX Vref Scan disable
6890 00:22:27.533740 == TX Byte 0 ==
6891 00:22:27.537379 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6892 00:22:27.540817 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6893 00:22:27.543990 == TX Byte 1 ==
6894 00:22:27.547291 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6895 00:22:27.550504 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6896 00:22:27.550574 ==
6897 00:22:27.554152 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 00:22:27.557293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 00:22:27.557364 ==
6900 00:22:27.557421
6901 00:22:27.560529
6902 00:22:27.560595 TX Vref Scan disable
6903 00:22:27.564201 == TX Byte 0 ==
6904 00:22:27.567296 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6905 00:22:27.570437 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6906 00:22:27.574075 == TX Byte 1 ==
6907 00:22:27.577742 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6908 00:22:27.580672 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6909 00:22:27.580773
6910 00:22:27.580867 [DATLAT]
6911 00:22:27.584365 Freq=400, CH1 RK1
6912 00:22:27.584457
6913 00:22:27.584544 DATLAT Default: 0xe
6914 00:22:27.587589 0, 0xFFFF, sum = 0
6915 00:22:27.587684 1, 0xFFFF, sum = 0
6916 00:22:27.590644 2, 0xFFFF, sum = 0
6917 00:22:27.590749 3, 0xFFFF, sum = 0
6918 00:22:27.594214 4, 0xFFFF, sum = 0
6919 00:22:27.594314 5, 0xFFFF, sum = 0
6920 00:22:27.597352 6, 0xFFFF, sum = 0
6921 00:22:27.600428 7, 0xFFFF, sum = 0
6922 00:22:27.600519 8, 0xFFFF, sum = 0
6923 00:22:27.604192 9, 0xFFFF, sum = 0
6924 00:22:27.604286 10, 0xFFFF, sum = 0
6925 00:22:27.607303 11, 0xFFFF, sum = 0
6926 00:22:27.607400 12, 0xFFFF, sum = 0
6927 00:22:27.610954 13, 0x0, sum = 1
6928 00:22:27.611054 14, 0x0, sum = 2
6929 00:22:27.614002 15, 0x0, sum = 3
6930 00:22:27.614173 16, 0x0, sum = 4
6931 00:22:27.614270 best_step = 14
6932 00:22:27.617540
6933 00:22:27.617643 ==
6934 00:22:27.620723 Dram Type= 6, Freq= 0, CH_1, rank 1
6935 00:22:27.624254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6936 00:22:27.624350 ==
6937 00:22:27.624445 RX Vref Scan: 0
6938 00:22:27.624528
6939 00:22:27.627377 RX Vref 0 -> 0, step: 1
6940 00:22:27.627466
6941 00:22:27.630754 RX Delay -359 -> 252, step: 8
6942 00:22:27.637483 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6943 00:22:27.641164 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6944 00:22:27.644233 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6945 00:22:27.647846 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6946 00:22:27.654371 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6947 00:22:27.657536 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6948 00:22:27.661191 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6949 00:22:27.664544 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6950 00:22:27.671263 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6951 00:22:27.674651 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6952 00:22:27.677826 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6953 00:22:27.681187 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6954 00:22:27.688340 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6955 00:22:27.691354 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6956 00:22:27.694495 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6957 00:22:27.698279 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6958 00:22:27.701446 ==
6959 00:22:27.701603 Dram Type= 6, Freq= 0, CH_1, rank 1
6960 00:22:27.708251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6961 00:22:27.708328 ==
6962 00:22:27.708430 DQS Delay:
6963 00:22:27.711361 DQS0 = 52, DQS1 = 60
6964 00:22:27.711438 DQM Delay:
6965 00:22:27.714480 DQM0 = 12, DQM1 = 12
6966 00:22:27.714558 DQ Delay:
6967 00:22:27.718218 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6968 00:22:27.721145 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6969 00:22:27.724728 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6970 00:22:27.728328 DQ12 =16, DQ13 =20, DQ14 =20, DQ15 =20
6971 00:22:27.728420
6972 00:22:27.728479
6973 00:22:27.734973 [DQSOSCAuto] RK1, (LSB)MR18= 0x7b8e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 394 ps
6974 00:22:27.738361 CH1 RK1: MR19=C0C, MR18=7B8E
6975 00:22:27.744501 CH1_RK1: MR19=0xC0C, MR18=0x7B8E, DQSOSC=392, MR23=63, INC=384, DEC=256
6976 00:22:27.748245 [RxdqsGatingPostProcess] freq 400
6977 00:22:27.751367 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6978 00:22:27.754841 best DQS0 dly(2T, 0.5T) = (0, 10)
6979 00:22:27.757785 best DQS1 dly(2T, 0.5T) = (0, 10)
6980 00:22:27.761488 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6981 00:22:27.764694 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6982 00:22:27.767704 best DQS0 dly(2T, 0.5T) = (0, 10)
6983 00:22:27.771458 best DQS1 dly(2T, 0.5T) = (0, 10)
6984 00:22:27.774544 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6985 00:22:27.778092 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6986 00:22:27.781514 Pre-setting of DQS Precalculation
6987 00:22:27.784865 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6988 00:22:27.791216 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6989 00:22:27.801587 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6990 00:22:27.801706
6991 00:22:27.801771
6992 00:22:27.801826 [Calibration Summary] 800 Mbps
6993 00:22:27.804777 CH 0, Rank 0
6994 00:22:27.804854 SW Impedance : PASS
6995 00:22:27.808021 DUTY Scan : NO K
6996 00:22:27.811825 ZQ Calibration : PASS
6997 00:22:27.811903 Jitter Meter : NO K
6998 00:22:27.814889 CBT Training : PASS
6999 00:22:27.817937 Write leveling : PASS
7000 00:22:27.818052 RX DQS gating : PASS
7001 00:22:27.821785 RX DQ/DQS(RDDQC) : PASS
7002 00:22:27.824752 TX DQ/DQS : PASS
7003 00:22:27.824828 RX DATLAT : PASS
7004 00:22:27.828213 RX DQ/DQS(Engine): PASS
7005 00:22:27.831510 TX OE : NO K
7006 00:22:27.831586 All Pass.
7007 00:22:27.831644
7008 00:22:27.831699 CH 0, Rank 1
7009 00:22:27.835088 SW Impedance : PASS
7010 00:22:27.838603 DUTY Scan : NO K
7011 00:22:27.838695 ZQ Calibration : PASS
7012 00:22:27.841563 Jitter Meter : NO K
7013 00:22:27.845552 CBT Training : PASS
7014 00:22:27.845627 Write leveling : NO K
7015 00:22:27.848540 RX DQS gating : PASS
7016 00:22:27.848643 RX DQ/DQS(RDDQC) : PASS
7017 00:22:27.851615 TX DQ/DQS : PASS
7018 00:22:27.854722 RX DATLAT : PASS
7019 00:22:27.854803 RX DQ/DQS(Engine): PASS
7020 00:22:27.858341 TX OE : NO K
7021 00:22:27.858418 All Pass.
7022 00:22:27.858477
7023 00:22:27.861350 CH 1, Rank 0
7024 00:22:27.861427 SW Impedance : PASS
7025 00:22:27.865196 DUTY Scan : NO K
7026 00:22:27.868148 ZQ Calibration : PASS
7027 00:22:27.868224 Jitter Meter : NO K
7028 00:22:27.871728 CBT Training : PASS
7029 00:22:27.874966 Write leveling : PASS
7030 00:22:27.875042 RX DQS gating : PASS
7031 00:22:27.878527 RX DQ/DQS(RDDQC) : PASS
7032 00:22:27.881538 TX DQ/DQS : PASS
7033 00:22:27.881615 RX DATLAT : PASS
7034 00:22:27.885236 RX DQ/DQS(Engine): PASS
7035 00:22:27.885312 TX OE : NO K
7036 00:22:27.888397 All Pass.
7037 00:22:27.888499
7038 00:22:27.888586 CH 1, Rank 1
7039 00:22:27.891389 SW Impedance : PASS
7040 00:22:27.891468 DUTY Scan : NO K
7041 00:22:27.894980 ZQ Calibration : PASS
7042 00:22:27.898613 Jitter Meter : NO K
7043 00:22:27.898689 CBT Training : PASS
7044 00:22:27.901879 Write leveling : NO K
7045 00:22:27.904836 RX DQS gating : PASS
7046 00:22:27.904913 RX DQ/DQS(RDDQC) : PASS
7047 00:22:27.908326 TX DQ/DQS : PASS
7048 00:22:27.911896 RX DATLAT : PASS
7049 00:22:27.911973 RX DQ/DQS(Engine): PASS
7050 00:22:27.915254 TX OE : NO K
7051 00:22:27.915330 All Pass.
7052 00:22:27.915389
7053 00:22:27.918757 DramC Write-DBI off
7054 00:22:27.921731 PER_BANK_REFRESH: Hybrid Mode
7055 00:22:27.921807 TX_TRACKING: ON
7056 00:22:27.931772 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7057 00:22:27.934903 [FAST_K] Save calibration result to emmc
7058 00:22:27.938521 dramc_set_vcore_voltage set vcore to 725000
7059 00:22:27.941957 Read voltage for 1600, 0
7060 00:22:27.942072 Vio18 = 0
7061 00:22:27.942132 Vcore = 725000
7062 00:22:27.945322 Vdram = 0
7063 00:22:27.945397 Vddq = 0
7064 00:22:27.945457 Vmddr = 0
7065 00:22:27.951714 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7066 00:22:27.955418 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7067 00:22:27.958559 MEM_TYPE=3, freq_sel=13
7068 00:22:27.961546 sv_algorithm_assistance_LP4_3733
7069 00:22:27.965241 ============ PULL DRAM RESETB DOWN ============
7070 00:22:27.968281 ========== PULL DRAM RESETB DOWN end =========
7071 00:22:27.975121 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7072 00:22:27.978752 ===================================
7073 00:22:27.978829 LPDDR4 DRAM CONFIGURATION
7074 00:22:27.981662 ===================================
7075 00:22:27.985588 EX_ROW_EN[0] = 0x0
7076 00:22:27.988615 EX_ROW_EN[1] = 0x0
7077 00:22:27.988691 LP4Y_EN = 0x0
7078 00:22:27.991664 WORK_FSP = 0x1
7079 00:22:27.991740 WL = 0x5
7080 00:22:27.995344 RL = 0x5
7081 00:22:27.995420 BL = 0x2
7082 00:22:27.998428 RPST = 0x0
7083 00:22:27.998504 RD_PRE = 0x0
7084 00:22:28.001623 WR_PRE = 0x1
7085 00:22:28.001699 WR_PST = 0x1
7086 00:22:28.005058 DBI_WR = 0x0
7087 00:22:28.005134 DBI_RD = 0x0
7088 00:22:28.008544 OTF = 0x1
7089 00:22:28.011776 ===================================
7090 00:22:28.015332 ===================================
7091 00:22:28.015410 ANA top config
7092 00:22:28.018398 ===================================
7093 00:22:28.022064 DLL_ASYNC_EN = 0
7094 00:22:28.025520 ALL_SLAVE_EN = 0
7095 00:22:28.025622 NEW_RANK_MODE = 1
7096 00:22:28.028892 DLL_IDLE_MODE = 1
7097 00:22:28.032023 LP45_APHY_COMB_EN = 1
7098 00:22:28.035750 TX_ODT_DIS = 0
7099 00:22:28.035826 NEW_8X_MODE = 1
7100 00:22:28.038889 ===================================
7101 00:22:28.042015 ===================================
7102 00:22:28.045726 data_rate = 3200
7103 00:22:28.048795 CKR = 1
7104 00:22:28.052360 DQ_P2S_RATIO = 8
7105 00:22:28.055596 ===================================
7106 00:22:28.059046 CA_P2S_RATIO = 8
7107 00:22:28.062259 DQ_CA_OPEN = 0
7108 00:22:28.062336 DQ_SEMI_OPEN = 0
7109 00:22:28.065753 CA_SEMI_OPEN = 0
7110 00:22:28.068820 CA_FULL_RATE = 0
7111 00:22:28.071952 DQ_CKDIV4_EN = 0
7112 00:22:28.075554 CA_CKDIV4_EN = 0
7113 00:22:28.078662 CA_PREDIV_EN = 0
7114 00:22:28.078728 PH8_DLY = 12
7115 00:22:28.082506 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7116 00:22:28.085548 DQ_AAMCK_DIV = 4
7117 00:22:28.089202 CA_AAMCK_DIV = 4
7118 00:22:28.092218 CA_ADMCK_DIV = 4
7119 00:22:28.092284 DQ_TRACK_CA_EN = 0
7120 00:22:28.095912 CA_PICK = 1600
7121 00:22:28.098944 CA_MCKIO = 1600
7122 00:22:28.102464 MCKIO_SEMI = 0
7123 00:22:28.105514 PLL_FREQ = 3068
7124 00:22:28.109118 DQ_UI_PI_RATIO = 32
7125 00:22:28.112045 CA_UI_PI_RATIO = 0
7126 00:22:28.115599 ===================================
7127 00:22:28.119067 ===================================
7128 00:22:28.119146 memory_type:LPDDR4
7129 00:22:28.122213 GP_NUM : 10
7130 00:22:28.125936 SRAM_EN : 1
7131 00:22:28.126055 MD32_EN : 0
7132 00:22:28.129098 ===================================
7133 00:22:28.132675 [ANA_INIT] >>>>>>>>>>>>>>
7134 00:22:28.135414 <<<<<< [CONFIGURE PHASE]: ANA_TX
7135 00:22:28.138878 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7136 00:22:28.142366 ===================================
7137 00:22:28.145487 data_rate = 3200,PCW = 0X7600
7138 00:22:28.148674 ===================================
7139 00:22:28.152446 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7140 00:22:28.155564 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7141 00:22:28.162162 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7142 00:22:28.165439 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7143 00:22:28.168972 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7144 00:22:28.172512 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7145 00:22:28.175747 [ANA_INIT] flow start
7146 00:22:28.179011 [ANA_INIT] PLL >>>>>>>>
7147 00:22:28.179087 [ANA_INIT] PLL <<<<<<<<
7148 00:22:28.182245 [ANA_INIT] MIDPI >>>>>>>>
7149 00:22:28.185526 [ANA_INIT] MIDPI <<<<<<<<
7150 00:22:28.185602 [ANA_INIT] DLL >>>>>>>>
7151 00:22:28.189111 [ANA_INIT] DLL <<<<<<<<
7152 00:22:28.192245 [ANA_INIT] flow end
7153 00:22:28.195486 ============ LP4 DIFF to SE enter ============
7154 00:22:28.199042 ============ LP4 DIFF to SE exit ============
7155 00:22:28.202120 [ANA_INIT] <<<<<<<<<<<<<
7156 00:22:28.205779 [Flow] Enable top DCM control >>>>>
7157 00:22:28.208910 [Flow] Enable top DCM control <<<<<
7158 00:22:28.212580 Enable DLL master slave shuffle
7159 00:22:28.215552 ==============================================================
7160 00:22:28.219128 Gating Mode config
7161 00:22:28.225775 ==============================================================
7162 00:22:28.225853 Config description:
7163 00:22:28.235674 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7164 00:22:28.242438 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7165 00:22:28.245942 SELPH_MODE 0: By rank 1: By Phase
7166 00:22:28.252647 ==============================================================
7167 00:22:28.255746 GAT_TRACK_EN = 1
7168 00:22:28.258818 RX_GATING_MODE = 2
7169 00:22:28.262509 RX_GATING_TRACK_MODE = 2
7170 00:22:28.265733 SELPH_MODE = 1
7171 00:22:28.268765 PICG_EARLY_EN = 1
7172 00:22:28.272455 VALID_LAT_VALUE = 1
7173 00:22:28.275594 ==============================================================
7174 00:22:28.278781 Enter into Gating configuration >>>>
7175 00:22:28.282445 Exit from Gating configuration <<<<
7176 00:22:28.285951 Enter into DVFS_PRE_config >>>>>
7177 00:22:28.295881 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7178 00:22:28.298998 Exit from DVFS_PRE_config <<<<<
7179 00:22:28.302122 Enter into PICG configuration >>>>
7180 00:22:28.306143 Exit from PICG configuration <<<<
7181 00:22:28.308974 [RX_INPUT] configuration >>>>>
7182 00:22:28.312491 [RX_INPUT] configuration <<<<<
7183 00:22:28.319263 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7184 00:22:28.322272 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7185 00:22:28.329068 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7186 00:22:28.335765 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7187 00:22:28.342603 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7188 00:22:28.345729 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7189 00:22:28.352695 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7190 00:22:28.355635 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7191 00:22:28.359102 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7192 00:22:28.362706 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7193 00:22:28.369416 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7194 00:22:28.372546 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7195 00:22:28.375790 ===================================
7196 00:22:28.378887 LPDDR4 DRAM CONFIGURATION
7197 00:22:28.382559 ===================================
7198 00:22:28.382636 EX_ROW_EN[0] = 0x0
7199 00:22:28.385789 EX_ROW_EN[1] = 0x0
7200 00:22:28.385866 LP4Y_EN = 0x0
7201 00:22:28.388776 WORK_FSP = 0x1
7202 00:22:28.388852 WL = 0x5
7203 00:22:28.392551 RL = 0x5
7204 00:22:28.392628 BL = 0x2
7205 00:22:28.395609 RPST = 0x0
7206 00:22:28.395685 RD_PRE = 0x0
7207 00:22:28.399272 WR_PRE = 0x1
7208 00:22:28.402255 WR_PST = 0x1
7209 00:22:28.402331 DBI_WR = 0x0
7210 00:22:28.405601 DBI_RD = 0x0
7211 00:22:28.405678 OTF = 0x1
7212 00:22:28.409524 ===================================
7213 00:22:28.412447 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7214 00:22:28.415722 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7215 00:22:28.422288 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7216 00:22:28.425578 ===================================
7217 00:22:28.429165 LPDDR4 DRAM CONFIGURATION
7218 00:22:28.429243 ===================================
7219 00:22:28.432685 EX_ROW_EN[0] = 0x10
7220 00:22:28.435849 EX_ROW_EN[1] = 0x0
7221 00:22:28.435926 LP4Y_EN = 0x0
7222 00:22:28.439516 WORK_FSP = 0x1
7223 00:22:28.439592 WL = 0x5
7224 00:22:28.442568 RL = 0x5
7225 00:22:28.442645 BL = 0x2
7226 00:22:28.445653 RPST = 0x0
7227 00:22:28.445730 RD_PRE = 0x0
7228 00:22:28.449390 WR_PRE = 0x1
7229 00:22:28.449466 WR_PST = 0x1
7230 00:22:28.452608 DBI_WR = 0x0
7231 00:22:28.452685 DBI_RD = 0x0
7232 00:22:28.455686 OTF = 0x1
7233 00:22:28.459378 ===================================
7234 00:22:28.465906 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7235 00:22:28.466040 ==
7236 00:22:28.469325 Dram Type= 6, Freq= 0, CH_0, rank 0
7237 00:22:28.472402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7238 00:22:28.472499 ==
7239 00:22:28.475803 [Duty_Offset_Calibration]
7240 00:22:28.475873 B0:2 B1:-1 CA:1
7241 00:22:28.475930
7242 00:22:28.479329 [DutyScan_Calibration_Flow] k_type=0
7243 00:22:28.489279
7244 00:22:28.489378 ==CLK 0==
7245 00:22:28.492586 Final CLK duty delay cell = -4
7246 00:22:28.495723 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7247 00:22:28.499306 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7248 00:22:28.502455 [-4] AVG Duty = 4937%(X100)
7249 00:22:28.502522
7250 00:22:28.505558 CH0 CLK Duty spec in!! Max-Min= 187%
7251 00:22:28.509425 [DutyScan_Calibration_Flow] ====Done====
7252 00:22:28.509497
7253 00:22:28.512445 [DutyScan_Calibration_Flow] k_type=1
7254 00:22:28.528601
7255 00:22:28.528688 ==DQS 0 ==
7256 00:22:28.532032 Final DQS duty delay cell = 0
7257 00:22:28.535307 [0] MAX Duty = 5125%(X100), DQS PI = 56
7258 00:22:28.538408 [0] MIN Duty = 5000%(X100), DQS PI = 14
7259 00:22:28.538484 [0] AVG Duty = 5062%(X100)
7260 00:22:28.541839
7261 00:22:28.541940 ==DQS 1 ==
7262 00:22:28.544981 Final DQS duty delay cell = -4
7263 00:22:28.548285 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7264 00:22:28.552108 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7265 00:22:28.555282 [-4] AVG Duty = 5046%(X100)
7266 00:22:28.555372
7267 00:22:28.558960 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7268 00:22:28.559037
7269 00:22:28.561957 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7270 00:22:28.565209 [DutyScan_Calibration_Flow] ====Done====
7271 00:22:28.565284
7272 00:22:28.568772 [DutyScan_Calibration_Flow] k_type=3
7273 00:22:28.585948
7274 00:22:28.586071 ==DQM 0 ==
7275 00:22:28.589129 Final DQM duty delay cell = 0
7276 00:22:28.592293 [0] MAX Duty = 5000%(X100), DQS PI = 18
7277 00:22:28.596120 [0] MIN Duty = 4844%(X100), DQS PI = 8
7278 00:22:28.596216 [0] AVG Duty = 4922%(X100)
7279 00:22:28.599056
7280 00:22:28.599181 ==DQM 1 ==
7281 00:22:28.602192 Final DQM duty delay cell = 0
7282 00:22:28.606016 [0] MAX Duty = 5187%(X100), DQS PI = 58
7283 00:22:28.609171 [0] MIN Duty = 4969%(X100), DQS PI = 18
7284 00:22:28.609238 [0] AVG Duty = 5078%(X100)
7285 00:22:28.612747
7286 00:22:28.615830 CH0 DQM 0 Duty spec in!! Max-Min= 156%
7287 00:22:28.615928
7288 00:22:28.619584 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7289 00:22:28.623018 [DutyScan_Calibration_Flow] ====Done====
7290 00:22:28.623087
7291 00:22:28.626080 [DutyScan_Calibration_Flow] k_type=2
7292 00:22:28.642795
7293 00:22:28.642901 ==DQ 0 ==
7294 00:22:28.646491 Final DQ duty delay cell = 0
7295 00:22:28.649839 [0] MAX Duty = 5187%(X100), DQS PI = 56
7296 00:22:28.653097 [0] MIN Duty = 5031%(X100), DQS PI = 12
7297 00:22:28.653164 [0] AVG Duty = 5109%(X100)
7298 00:22:28.653220
7299 00:22:28.656247 ==DQ 1 ==
7300 00:22:28.659866 Final DQ duty delay cell = 0
7301 00:22:28.663027 [0] MAX Duty = 5000%(X100), DQS PI = 0
7302 00:22:28.666291 [0] MIN Duty = 4907%(X100), DQS PI = 18
7303 00:22:28.666364 [0] AVG Duty = 4953%(X100)
7304 00:22:28.666423
7305 00:22:28.669724 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7306 00:22:28.669792
7307 00:22:28.673462 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7308 00:22:28.679945 [DutyScan_Calibration_Flow] ====Done====
7309 00:22:28.680020 ==
7310 00:22:28.683084 Dram Type= 6, Freq= 0, CH_1, rank 0
7311 00:22:28.686402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7312 00:22:28.686478 ==
7313 00:22:28.689998 [Duty_Offset_Calibration]
7314 00:22:28.690111 B0:1 B1:1 CA:2
7315 00:22:28.690175
7316 00:22:28.692830 [DutyScan_Calibration_Flow] k_type=0
7317 00:22:28.702700
7318 00:22:28.702776 ==CLK 0==
7319 00:22:28.706471 Final CLK duty delay cell = 0
7320 00:22:28.709597 [0] MAX Duty = 5187%(X100), DQS PI = 24
7321 00:22:28.712768 [0] MIN Duty = 4969%(X100), DQS PI = 42
7322 00:22:28.712844 [0] AVG Duty = 5078%(X100)
7323 00:22:28.716564
7324 00:22:28.719571 CH1 CLK Duty spec in!! Max-Min= 218%
7325 00:22:28.722655 [DutyScan_Calibration_Flow] ====Done====
7326 00:22:28.722744
7327 00:22:28.726309 [DutyScan_Calibration_Flow] k_type=1
7328 00:22:28.742732
7329 00:22:28.742808 ==DQS 0 ==
7330 00:22:28.745747 Final DQS duty delay cell = 0
7331 00:22:28.749532 [0] MAX Duty = 5062%(X100), DQS PI = 22
7332 00:22:28.752690 [0] MIN Duty = 4813%(X100), DQS PI = 50
7333 00:22:28.756263 [0] AVG Duty = 4937%(X100)
7334 00:22:28.756334
7335 00:22:28.756391 ==DQS 1 ==
7336 00:22:28.759349 Final DQS duty delay cell = 0
7337 00:22:28.763136 [0] MAX Duty = 5031%(X100), DQS PI = 52
7338 00:22:28.765926 [0] MIN Duty = 4938%(X100), DQS PI = 12
7339 00:22:28.766027 [0] AVG Duty = 4984%(X100)
7340 00:22:28.769353
7341 00:22:28.772815 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7342 00:22:28.772891
7343 00:22:28.776003 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7344 00:22:28.779519 [DutyScan_Calibration_Flow] ====Done====
7345 00:22:28.779595
7346 00:22:28.782606 [DutyScan_Calibration_Flow] k_type=3
7347 00:22:28.799764
7348 00:22:28.799844 ==DQM 0 ==
7349 00:22:28.803092 Final DQM duty delay cell = 0
7350 00:22:28.806186 [0] MAX Duty = 5156%(X100), DQS PI = 20
7351 00:22:28.809639 [0] MIN Duty = 4844%(X100), DQS PI = 50
7352 00:22:28.812721 [0] AVG Duty = 5000%(X100)
7353 00:22:28.812816
7354 00:22:28.812899 ==DQM 1 ==
7355 00:22:28.816422 Final DQM duty delay cell = 0
7356 00:22:28.819718 [0] MAX Duty = 5156%(X100), DQS PI = 60
7357 00:22:28.822710 [0] MIN Duty = 4907%(X100), DQS PI = 18
7358 00:22:28.826498 [0] AVG Duty = 5031%(X100)
7359 00:22:28.826593
7360 00:22:28.829372 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7361 00:22:28.829513
7362 00:22:28.833025 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7363 00:22:28.836093 [DutyScan_Calibration_Flow] ====Done====
7364 00:22:28.836164
7365 00:22:28.839655 [DutyScan_Calibration_Flow] k_type=2
7366 00:22:28.856310
7367 00:22:28.856385 ==DQ 0 ==
7368 00:22:28.860062 Final DQ duty delay cell = 0
7369 00:22:28.863289 [0] MAX Duty = 5156%(X100), DQS PI = 20
7370 00:22:28.866381 [0] MIN Duty = 4907%(X100), DQS PI = 52
7371 00:22:28.866488 [0] AVG Duty = 5031%(X100)
7372 00:22:28.866563
7373 00:22:28.869971 ==DQ 1 ==
7374 00:22:28.873093 Final DQ duty delay cell = 0
7375 00:22:28.876166 [0] MAX Duty = 5093%(X100), DQS PI = 8
7376 00:22:28.879891 [0] MIN Duty = 5031%(X100), DQS PI = 0
7377 00:22:28.879967 [0] AVG Duty = 5062%(X100)
7378 00:22:28.880025
7379 00:22:28.883028 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7380 00:22:28.883098
7381 00:22:28.886746 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7382 00:22:28.892800 [DutyScan_Calibration_Flow] ====Done====
7383 00:22:28.896232 nWR fixed to 30
7384 00:22:28.896309 [ModeRegInit_LP4] CH0 RK0
7385 00:22:28.899527 [ModeRegInit_LP4] CH0 RK1
7386 00:22:28.903053 [ModeRegInit_LP4] CH1 RK0
7387 00:22:28.903128 [ModeRegInit_LP4] CH1 RK1
7388 00:22:28.906511 match AC timing 5
7389 00:22:28.909779 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7390 00:22:28.913349 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7391 00:22:28.920277 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7392 00:22:28.923570 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7393 00:22:28.929731 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7394 00:22:28.929808 [MiockJmeterHQA]
7395 00:22:28.929883
7396 00:22:28.933511 [DramcMiockJmeter] u1RxGatingPI = 0
7397 00:22:28.933589 0 : 4253, 4026
7398 00:22:28.936458 4 : 4253, 4026
7399 00:22:28.936535 8 : 4257, 4032
7400 00:22:28.939438 12 : 4255, 4030
7401 00:22:28.939537 16 : 4252, 4027
7402 00:22:28.943148 20 : 4253, 4026
7403 00:22:28.943225 24 : 4252, 4027
7404 00:22:28.946237 28 : 4366, 4140
7405 00:22:28.946313 32 : 4368, 4140
7406 00:22:28.946384 36 : 4255, 4029
7407 00:22:28.950001 40 : 4366, 4140
7408 00:22:28.950094 44 : 4252, 4027
7409 00:22:28.953013 48 : 4253, 4026
7410 00:22:28.953114 52 : 4255, 4029
7411 00:22:28.956720 56 : 4253, 4029
7412 00:22:28.956812 60 : 4252, 4029
7413 00:22:28.956913 64 : 4255, 4029
7414 00:22:28.959930 68 : 4255, 4029
7415 00:22:28.960037 72 : 4365, 4140
7416 00:22:28.963114 76 : 4253, 4029
7417 00:22:28.963215 80 : 4250, 4027
7418 00:22:28.966232 84 : 4360, 4137
7419 00:22:28.966299 88 : 4252, 4027
7420 00:22:28.970175 92 : 4250, 4027
7421 00:22:28.970252 96 : 4363, 3218
7422 00:22:28.970310 100 : 4255, 0
7423 00:22:28.973114 104 : 4254, 0
7424 00:22:28.973190 108 : 4250, 0
7425 00:22:28.976106 112 : 4253, 0
7426 00:22:28.976199 116 : 4253, 0
7427 00:22:28.976271 120 : 4253, 0
7428 00:22:28.979574 124 : 4252, 0
7429 00:22:28.979651 128 : 4255, 0
7430 00:22:28.979711 132 : 4360, 0
7431 00:22:28.983484 136 : 4253, 0
7432 00:22:28.983561 140 : 4253, 0
7433 00:22:28.986420 144 : 4361, 0
7434 00:22:28.986497 148 : 4253, 0
7435 00:22:28.986556 152 : 4249, 0
7436 00:22:28.989576 156 : 4255, 0
7437 00:22:28.989688 160 : 4252, 0
7438 00:22:28.993315 164 : 4360, 0
7439 00:22:28.993391 168 : 4366, 0
7440 00:22:28.993450 172 : 4360, 0
7441 00:22:28.996514 176 : 4252, 0
7442 00:22:28.996591 180 : 4255, 0
7443 00:22:28.996650 184 : 4253, 0
7444 00:22:28.999717 188 : 4250, 0
7445 00:22:28.999808 192 : 4258, 0
7446 00:22:29.002867 196 : 4253, 0
7447 00:22:29.002984 200 : 4250, 0
7448 00:22:29.003074 204 : 4249, 0
7449 00:22:29.006361 208 : 4360, 0
7450 00:22:29.006435 212 : 4250, 155
7451 00:22:29.009498 216 : 4250, 3828
7452 00:22:29.009576 220 : 4257, 4032
7453 00:22:29.013235 224 : 4363, 4137
7454 00:22:29.013316 228 : 4363, 4138
7455 00:22:29.016300 232 : 4363, 4139
7456 00:22:29.016375 236 : 4250, 4027
7457 00:22:29.019287 240 : 4368, 4142
7458 00:22:29.019361 244 : 4250, 4027
7459 00:22:29.022775 248 : 4361, 4137
7460 00:22:29.022841 252 : 4250, 4027
7461 00:22:29.022897 256 : 4255, 4030
7462 00:22:29.026159 260 : 4250, 4027
7463 00:22:29.026229 264 : 4253, 4029
7464 00:22:29.029460 268 : 4250, 4027
7465 00:22:29.029530 272 : 4254, 4032
7466 00:22:29.032759 276 : 4255, 4029
7467 00:22:29.032831 280 : 4250, 4027
7468 00:22:29.036182 284 : 4363, 4140
7469 00:22:29.036252 288 : 4250, 4027
7470 00:22:29.039337 292 : 4365, 4139
7471 00:22:29.039421 296 : 4252, 4029
7472 00:22:29.042796 300 : 4250, 4027
7473 00:22:29.042875 304 : 4250, 4027
7474 00:22:29.046049 308 : 4253, 4029
7475 00:22:29.046131 312 : 4360, 4137
7476 00:22:29.046193 316 : 4360, 4137
7477 00:22:29.049454 320 : 4252, 4030
7478 00:22:29.049564 324 : 4258, 4032
7479 00:22:29.052579 328 : 4255, 4029
7480 00:22:29.052651 332 : 4249, 2628
7481 00:22:29.056373 336 : 4253, 11
7482 00:22:29.056472
7483 00:22:29.056564 MIOCK jitter meter ch=0
7484 00:22:29.056638
7485 00:22:29.059477 1T = (336-100) = 236 dly cells
7486 00:22:29.066477 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7487 00:22:29.066556 ==
7488 00:22:29.069562 Dram Type= 6, Freq= 0, CH_0, rank 0
7489 00:22:29.072711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7490 00:22:29.072789 ==
7491 00:22:29.079170 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7492 00:22:29.082742 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7493 00:22:29.086402 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7494 00:22:29.092635 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7495 00:22:29.103071 [CA 0] Center 44 (14~75) winsize 62
7496 00:22:29.106138 [CA 1] Center 44 (14~74) winsize 61
7497 00:22:29.109726 [CA 2] Center 39 (10~68) winsize 59
7498 00:22:29.112681 [CA 3] Center 39 (10~68) winsize 59
7499 00:22:29.115896 [CA 4] Center 37 (7~67) winsize 61
7500 00:22:29.119399 [CA 5] Center 37 (7~67) winsize 61
7501 00:22:29.119500
7502 00:22:29.123092 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7503 00:22:29.123169
7504 00:22:29.126254 [CATrainingPosCal] consider 1 rank data
7505 00:22:29.129404 u2DelayCellTimex100 = 275/100 ps
7506 00:22:29.133128 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7507 00:22:29.139765 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7508 00:22:29.142647 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7509 00:22:29.146442 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7510 00:22:29.149347 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7511 00:22:29.152813 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7512 00:22:29.152919
7513 00:22:29.156180 CA PerBit enable=1, Macro0, CA PI delay=37
7514 00:22:29.156287
7515 00:22:29.159673 [CBTSetCACLKResult] CA Dly = 37
7516 00:22:29.162839 CS Dly: 11 (0~42)
7517 00:22:29.166181 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7518 00:22:29.169188 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7519 00:22:29.169257 ==
7520 00:22:29.172960 Dram Type= 6, Freq= 0, CH_0, rank 1
7521 00:22:29.176044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7522 00:22:29.179641 ==
7523 00:22:29.182795 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7524 00:22:29.186294 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7525 00:22:29.192941 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7526 00:22:29.196082 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7527 00:22:29.206735 [CA 0] Center 43 (13~74) winsize 62
7528 00:22:29.209888 [CA 1] Center 43 (13~74) winsize 62
7529 00:22:29.213488 [CA 2] Center 39 (10~69) winsize 60
7530 00:22:29.216530 [CA 3] Center 38 (9~68) winsize 60
7531 00:22:29.220255 [CA 4] Center 37 (7~67) winsize 61
7532 00:22:29.223258 [CA 5] Center 37 (7~67) winsize 61
7533 00:22:29.223384
7534 00:22:29.226736 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7535 00:22:29.226818
7536 00:22:29.229760 [CATrainingPosCal] consider 2 rank data
7537 00:22:29.233679 u2DelayCellTimex100 = 275/100 ps
7538 00:22:29.236756 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7539 00:22:29.243270 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7540 00:22:29.246822 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7541 00:22:29.249911 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7542 00:22:29.253478 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7543 00:22:29.256736 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7544 00:22:29.256850
7545 00:22:29.260336 CA PerBit enable=1, Macro0, CA PI delay=37
7546 00:22:29.260444
7547 00:22:29.263423 [CBTSetCACLKResult] CA Dly = 37
7548 00:22:29.266394 CS Dly: 12 (0~44)
7549 00:22:29.270103 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7550 00:22:29.273335 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7551 00:22:29.273406
7552 00:22:29.276784 ----->DramcWriteLeveling(PI) begin...
7553 00:22:29.276855 ==
7554 00:22:29.279896 Dram Type= 6, Freq= 0, CH_0, rank 0
7555 00:22:29.283584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7556 00:22:29.286684 ==
7557 00:22:29.286762 Write leveling (Byte 0): 33 => 33
7558 00:22:29.290238 Write leveling (Byte 1): 27 => 27
7559 00:22:29.293187 DramcWriteLeveling(PI) end<-----
7560 00:22:29.293280
7561 00:22:29.293355 ==
7562 00:22:29.296742 Dram Type= 6, Freq= 0, CH_0, rank 0
7563 00:22:29.303637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7564 00:22:29.303715 ==
7565 00:22:29.303792 [Gating] SW mode calibration
7566 00:22:29.313790 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7567 00:22:29.316864 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7568 00:22:29.320113 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 00:22:29.326898 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7570 00:22:29.330469 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 00:22:29.333379 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7572 00:22:29.340059 1 4 16 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
7573 00:22:29.343186 1 4 20 | B1->B0 | 2322 3333 | 1 0 | (1 0) (0 0)
7574 00:22:29.346917 1 4 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7575 00:22:29.353349 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7576 00:22:29.356578 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7577 00:22:29.360444 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7578 00:22:29.367060 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7579 00:22:29.370160 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7580 00:22:29.373223 1 5 16 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
7581 00:22:29.379821 1 5 20 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
7582 00:22:29.383305 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7583 00:22:29.386559 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 00:22:29.393255 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 00:22:29.396842 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 00:22:29.400374 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 00:22:29.406951 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 00:22:29.410067 1 6 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7589 00:22:29.413380 1 6 20 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7590 00:22:29.416998 1 6 24 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
7591 00:22:29.423195 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7592 00:22:29.426801 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7593 00:22:29.429936 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7594 00:22:29.436780 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7595 00:22:29.440143 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7596 00:22:29.443292 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 00:22:29.450157 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7598 00:22:29.453344 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7599 00:22:29.456933 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 00:22:29.463559 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 00:22:29.466513 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 00:22:29.470230 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 00:22:29.476842 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 00:22:29.480003 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 00:22:29.483154 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 00:22:29.490191 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 00:22:29.493113 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 00:22:29.496859 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 00:22:29.503266 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 00:22:29.506673 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 00:22:29.509731 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 00:22:29.513660 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7613 00:22:29.520116 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7614 00:22:29.523324 Total UI for P1: 0, mck2ui 16
7615 00:22:29.526784 best dqsien dly found for B0: ( 1, 9, 16)
7616 00:22:29.529818 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 00:22:29.533641 Total UI for P1: 0, mck2ui 16
7618 00:22:29.536812 best dqsien dly found for B1: ( 1, 9, 20)
7619 00:22:29.539970 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7620 00:22:29.543642 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7621 00:22:29.543718
7622 00:22:29.546588 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7623 00:22:29.550286 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7624 00:22:29.553538 [Gating] SW calibration Done
7625 00:22:29.553643 ==
7626 00:22:29.556568 Dram Type= 6, Freq= 0, CH_0, rank 0
7627 00:22:29.563334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7628 00:22:29.563412 ==
7629 00:22:29.563469 RX Vref Scan: 0
7630 00:22:29.563522
7631 00:22:29.566921 RX Vref 0 -> 0, step: 1
7632 00:22:29.566995
7633 00:22:29.569797 RX Delay 0 -> 252, step: 8
7634 00:22:29.573567 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7635 00:22:29.576800 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7636 00:22:29.580280 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7637 00:22:29.583405 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7638 00:22:29.589747 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7639 00:22:29.593441 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7640 00:22:29.596435 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7641 00:22:29.599940 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7642 00:22:29.603071 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7643 00:22:29.609866 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7644 00:22:29.613420 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7645 00:22:29.616487 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7646 00:22:29.620114 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7647 00:22:29.623498 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7648 00:22:29.630190 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7649 00:22:29.633421 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7650 00:22:29.633546 ==
7651 00:22:29.636474 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 00:22:29.640344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 00:22:29.640454 ==
7654 00:22:29.640512 DQS Delay:
7655 00:22:29.643569 DQS0 = 0, DQS1 = 0
7656 00:22:29.643633 DQM Delay:
7657 00:22:29.646682 DQM0 = 132, DQM1 = 123
7658 00:22:29.646817 DQ Delay:
7659 00:22:29.650223 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7660 00:22:29.653714 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7661 00:22:29.656798 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7662 00:22:29.660057 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7663 00:22:29.663620
7664 00:22:29.663695
7665 00:22:29.663783 ==
7666 00:22:29.666736 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 00:22:29.669970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7668 00:22:29.670069 ==
7669 00:22:29.670128
7670 00:22:29.670181
7671 00:22:29.673486 TX Vref Scan disable
7672 00:22:29.673560 == TX Byte 0 ==
7673 00:22:29.680219 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7674 00:22:29.683787 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7675 00:22:29.683862 == TX Byte 1 ==
7676 00:22:29.689942 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7677 00:22:29.693662 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7678 00:22:29.693738 ==
7679 00:22:29.696773 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 00:22:29.699941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 00:22:29.700035 ==
7682 00:22:29.715366
7683 00:22:29.719044 TX Vref early break, caculate TX vref
7684 00:22:29.722114 TX Vref=16, minBit 7, minWin=21, winSum=358
7685 00:22:29.725185 TX Vref=18, minBit 2, minWin=22, winSum=370
7686 00:22:29.728666 TX Vref=20, minBit 0, minWin=23, winSum=382
7687 00:22:29.732169 TX Vref=22, minBit 0, minWin=24, winSum=392
7688 00:22:29.735684 TX Vref=24, minBit 5, minWin=24, winSum=401
7689 00:22:29.741812 TX Vref=26, minBit 4, minWin=24, winSum=409
7690 00:22:29.745645 TX Vref=28, minBit 4, minWin=25, winSum=420
7691 00:22:29.748713 TX Vref=30, minBit 0, minWin=25, winSum=419
7692 00:22:29.751925 TX Vref=32, minBit 2, minWin=24, winSum=407
7693 00:22:29.755685 TX Vref=34, minBit 3, minWin=24, winSum=401
7694 00:22:29.759118 TX Vref=36, minBit 4, minWin=22, winSum=388
7695 00:22:29.765421 [TxChooseVref] Worse bit 4, Min win 25, Win sum 420, Final Vref 28
7696 00:22:29.765498
7697 00:22:29.769126 Final TX Range 0 Vref 28
7698 00:22:29.769206
7699 00:22:29.769264 ==
7700 00:22:29.772232 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 00:22:29.775318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 00:22:29.775394 ==
7703 00:22:29.775452
7704 00:22:29.775543
7705 00:22:29.778945 TX Vref Scan disable
7706 00:22:29.786156 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7707 00:22:29.786232 == TX Byte 0 ==
7708 00:22:29.789058 u2DelayCellOfst[0]=17 cells (5 PI)
7709 00:22:29.792583 u2DelayCellOfst[1]=21 cells (6 PI)
7710 00:22:29.796056 u2DelayCellOfst[2]=14 cells (4 PI)
7711 00:22:29.799484 u2DelayCellOfst[3]=17 cells (5 PI)
7712 00:22:29.802449 u2DelayCellOfst[4]=10 cells (3 PI)
7713 00:22:29.805549 u2DelayCellOfst[5]=0 cells (0 PI)
7714 00:22:29.809255 u2DelayCellOfst[6]=21 cells (6 PI)
7715 00:22:29.809330 u2DelayCellOfst[7]=21 cells (6 PI)
7716 00:22:29.815677 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7717 00:22:29.819328 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7718 00:22:29.819408 == TX Byte 1 ==
7719 00:22:29.822361 u2DelayCellOfst[8]=0 cells (0 PI)
7720 00:22:29.826033 u2DelayCellOfst[9]=0 cells (0 PI)
7721 00:22:29.829289 u2DelayCellOfst[10]=7 cells (2 PI)
7722 00:22:29.832360 u2DelayCellOfst[11]=0 cells (0 PI)
7723 00:22:29.835993 u2DelayCellOfst[12]=10 cells (3 PI)
7724 00:22:29.839092 u2DelayCellOfst[13]=10 cells (3 PI)
7725 00:22:29.842608 u2DelayCellOfst[14]=14 cells (4 PI)
7726 00:22:29.846169 u2DelayCellOfst[15]=10 cells (3 PI)
7727 00:22:29.849313 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7728 00:22:29.855864 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7729 00:22:29.855937 DramC Write-DBI on
7730 00:22:29.855994 ==
7731 00:22:29.858947 Dram Type= 6, Freq= 0, CH_0, rank 0
7732 00:22:29.862638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7733 00:22:29.862710 ==
7734 00:22:29.862775
7735 00:22:29.865902
7736 00:22:29.866012 TX Vref Scan disable
7737 00:22:29.869128 == TX Byte 0 ==
7738 00:22:29.872789 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7739 00:22:29.875810 == TX Byte 1 ==
7740 00:22:29.878840 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7741 00:22:29.878915 DramC Write-DBI off
7742 00:22:29.882722
7743 00:22:29.882798 [DATLAT]
7744 00:22:29.882856 Freq=1600, CH0 RK0
7745 00:22:29.882911
7746 00:22:29.885773 DATLAT Default: 0xf
7747 00:22:29.885848 0, 0xFFFF, sum = 0
7748 00:22:29.889470 1, 0xFFFF, sum = 0
7749 00:22:29.889561 2, 0xFFFF, sum = 0
7750 00:22:29.892718 3, 0xFFFF, sum = 0
7751 00:22:29.892820 4, 0xFFFF, sum = 0
7752 00:22:29.895812 5, 0xFFFF, sum = 0
7753 00:22:29.895888 6, 0xFFFF, sum = 0
7754 00:22:29.899554 7, 0xFFFF, sum = 0
7755 00:22:29.902595 8, 0xFFFF, sum = 0
7756 00:22:29.902677 9, 0xFFFF, sum = 0
7757 00:22:29.906112 10, 0xFFFF, sum = 0
7758 00:22:29.906200 11, 0xFFFF, sum = 0
7759 00:22:29.909349 12, 0xFFFF, sum = 0
7760 00:22:29.909426 13, 0xFFFF, sum = 0
7761 00:22:29.912440 14, 0x0, sum = 1
7762 00:22:29.912509 15, 0x0, sum = 2
7763 00:22:29.915865 16, 0x0, sum = 3
7764 00:22:29.915936 17, 0x0, sum = 4
7765 00:22:29.915993 best_step = 15
7766 00:22:29.918945
7767 00:22:29.919019 ==
7768 00:22:29.922438 Dram Type= 6, Freq= 0, CH_0, rank 0
7769 00:22:29.925868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7770 00:22:29.925967 ==
7771 00:22:29.926068 RX Vref Scan: 1
7772 00:22:29.926124
7773 00:22:29.929555 Set Vref Range= 24 -> 127
7774 00:22:29.929631
7775 00:22:29.932605 RX Vref 24 -> 127, step: 1
7776 00:22:29.932795
7777 00:22:29.936237 RX Delay 11 -> 252, step: 4
7778 00:22:29.936312
7779 00:22:29.939209 Set Vref, RX VrefLevel [Byte0]: 24
7780 00:22:29.942794 [Byte1]: 24
7781 00:22:29.942869
7782 00:22:29.945812 Set Vref, RX VrefLevel [Byte0]: 25
7783 00:22:29.949482 [Byte1]: 25
7784 00:22:29.949566
7785 00:22:29.952433 Set Vref, RX VrefLevel [Byte0]: 26
7786 00:22:29.955774 [Byte1]: 26
7787 00:22:29.959233
7788 00:22:29.959309 Set Vref, RX VrefLevel [Byte0]: 27
7789 00:22:29.962740 [Byte1]: 27
7790 00:22:29.967113
7791 00:22:29.967181 Set Vref, RX VrefLevel [Byte0]: 28
7792 00:22:29.970134 [Byte1]: 28
7793 00:22:29.974715
7794 00:22:29.974789 Set Vref, RX VrefLevel [Byte0]: 29
7795 00:22:29.977647 [Byte1]: 29
7796 00:22:29.981917
7797 00:22:29.982040 Set Vref, RX VrefLevel [Byte0]: 30
7798 00:22:29.985663 [Byte1]: 30
7799 00:22:29.990170
7800 00:22:29.990245 Set Vref, RX VrefLevel [Byte0]: 31
7801 00:22:29.993176 [Byte1]: 31
7802 00:22:29.997548
7803 00:22:29.997622 Set Vref, RX VrefLevel [Byte0]: 32
7804 00:22:30.000643 [Byte1]: 32
7805 00:22:30.004921
7806 00:22:30.004995 Set Vref, RX VrefLevel [Byte0]: 33
7807 00:22:30.008114 [Byte1]: 33
7808 00:22:30.013070
7809 00:22:30.013145 Set Vref, RX VrefLevel [Byte0]: 34
7810 00:22:30.015836 [Byte1]: 34
7811 00:22:30.020261
7812 00:22:30.020335 Set Vref, RX VrefLevel [Byte0]: 35
7813 00:22:30.023238 [Byte1]: 35
7814 00:22:30.028065
7815 00:22:30.028162 Set Vref, RX VrefLevel [Byte0]: 36
7816 00:22:30.031282 [Byte1]: 36
7817 00:22:30.035791
7818 00:22:30.035865 Set Vref, RX VrefLevel [Byte0]: 37
7819 00:22:30.039002 [Byte1]: 37
7820 00:22:30.043241
7821 00:22:30.043329 Set Vref, RX VrefLevel [Byte0]: 38
7822 00:22:30.046389 [Byte1]: 38
7823 00:22:30.050564
7824 00:22:30.050632 Set Vref, RX VrefLevel [Byte0]: 39
7825 00:22:30.054307 [Byte1]: 39
7826 00:22:30.058409
7827 00:22:30.058484 Set Vref, RX VrefLevel [Byte0]: 40
7828 00:22:30.061688 [Byte1]: 40
7829 00:22:30.066094
7830 00:22:30.066175 Set Vref, RX VrefLevel [Byte0]: 41
7831 00:22:30.068982 [Byte1]: 41
7832 00:22:30.073417
7833 00:22:30.073487 Set Vref, RX VrefLevel [Byte0]: 42
7834 00:22:30.077223 [Byte1]: 42
7835 00:22:30.081212
7836 00:22:30.081278 Set Vref, RX VrefLevel [Byte0]: 43
7837 00:22:30.084185 [Byte1]: 43
7838 00:22:30.088848
7839 00:22:30.088923 Set Vref, RX VrefLevel [Byte0]: 44
7840 00:22:30.091984 [Byte1]: 44
7841 00:22:30.096359
7842 00:22:30.096433 Set Vref, RX VrefLevel [Byte0]: 45
7843 00:22:30.099529 [Byte1]: 45
7844 00:22:30.103808
7845 00:22:30.103882 Set Vref, RX VrefLevel [Byte0]: 46
7846 00:22:30.107030 [Byte1]: 46
7847 00:22:30.111422
7848 00:22:30.111537 Set Vref, RX VrefLevel [Byte0]: 47
7849 00:22:30.114586 [Byte1]: 47
7850 00:22:30.119455
7851 00:22:30.119530 Set Vref, RX VrefLevel [Byte0]: 48
7852 00:22:30.122533 [Byte1]: 48
7853 00:22:30.126684
7854 00:22:30.126754 Set Vref, RX VrefLevel [Byte0]: 49
7855 00:22:30.130325 [Byte1]: 49
7856 00:22:30.134373
7857 00:22:30.134444 Set Vref, RX VrefLevel [Byte0]: 50
7858 00:22:30.137915 [Byte1]: 50
7859 00:22:30.142071
7860 00:22:30.142182 Set Vref, RX VrefLevel [Byte0]: 51
7861 00:22:30.145020 [Byte1]: 51
7862 00:22:30.149727
7863 00:22:30.149826 Set Vref, RX VrefLevel [Byte0]: 52
7864 00:22:30.152731 [Byte1]: 52
7865 00:22:30.157108
7866 00:22:30.157186 Set Vref, RX VrefLevel [Byte0]: 53
7867 00:22:30.160229 [Byte1]: 53
7868 00:22:30.165085
7869 00:22:30.165183 Set Vref, RX VrefLevel [Byte0]: 54
7870 00:22:30.167938 [Byte1]: 54
7871 00:22:30.172663
7872 00:22:30.172741 Set Vref, RX VrefLevel [Byte0]: 55
7873 00:22:30.175722 [Byte1]: 55
7874 00:22:30.179965
7875 00:22:30.180039 Set Vref, RX VrefLevel [Byte0]: 56
7876 00:22:30.183708 [Byte1]: 56
7877 00:22:30.187605
7878 00:22:30.187679 Set Vref, RX VrefLevel [Byte0]: 57
7879 00:22:30.191279 [Byte1]: 57
7880 00:22:30.195457
7881 00:22:30.195529 Set Vref, RX VrefLevel [Byte0]: 58
7882 00:22:30.198589 [Byte1]: 58
7883 00:22:30.203072
7884 00:22:30.203153 Set Vref, RX VrefLevel [Byte0]: 59
7885 00:22:30.206003 [Byte1]: 59
7886 00:22:30.210525
7887 00:22:30.210597 Set Vref, RX VrefLevel [Byte0]: 60
7888 00:22:30.214017 [Byte1]: 60
7889 00:22:30.218362
7890 00:22:30.218438 Set Vref, RX VrefLevel [Byte0]: 61
7891 00:22:30.221486 [Byte1]: 61
7892 00:22:30.225715
7893 00:22:30.225785 Set Vref, RX VrefLevel [Byte0]: 62
7894 00:22:30.228720 [Byte1]: 62
7895 00:22:30.233621
7896 00:22:30.233763 Set Vref, RX VrefLevel [Byte0]: 63
7897 00:22:30.236533 [Byte1]: 63
7898 00:22:30.240846
7899 00:22:30.240944 Set Vref, RX VrefLevel [Byte0]: 64
7900 00:22:30.244456 [Byte1]: 64
7901 00:22:30.248433
7902 00:22:30.248533 Set Vref, RX VrefLevel [Byte0]: 65
7903 00:22:30.251993 [Byte1]: 65
7904 00:22:30.256227
7905 00:22:30.256321 Set Vref, RX VrefLevel [Byte0]: 66
7906 00:22:30.259699 [Byte1]: 66
7907 00:22:30.263469
7908 00:22:30.267133 Set Vref, RX VrefLevel [Byte0]: 67
7909 00:22:30.267209 [Byte1]: 67
7910 00:22:30.271329
7911 00:22:30.271406 Set Vref, RX VrefLevel [Byte0]: 68
7912 00:22:30.274593 [Byte1]: 68
7913 00:22:30.279286
7914 00:22:30.279366 Set Vref, RX VrefLevel [Byte0]: 69
7915 00:22:30.282164 [Byte1]: 69
7916 00:22:30.286615
7917 00:22:30.286705 Set Vref, RX VrefLevel [Byte0]: 70
7918 00:22:30.290331 [Byte1]: 70
7919 00:22:30.293923
7920 00:22:30.294046 Set Vref, RX VrefLevel [Byte0]: 71
7921 00:22:30.297692 [Byte1]: 71
7922 00:22:30.301789
7923 00:22:30.301882 Set Vref, RX VrefLevel [Byte0]: 72
7924 00:22:30.305005 [Byte1]: 72
7925 00:22:30.309437
7926 00:22:30.309528 Set Vref, RX VrefLevel [Byte0]: 73
7927 00:22:30.312659 [Byte1]: 73
7928 00:22:30.317028
7929 00:22:30.317117 Set Vref, RX VrefLevel [Byte0]: 74
7930 00:22:30.320185 [Byte1]: 74
7931 00:22:30.324618
7932 00:22:30.324714 Set Vref, RX VrefLevel [Byte0]: 75
7933 00:22:30.328242 [Byte1]: 75
7934 00:22:30.332118
7935 00:22:30.332211 Final RX Vref Byte 0 = 62 to rank0
7936 00:22:30.335812 Final RX Vref Byte 1 = 60 to rank0
7937 00:22:30.338840 Final RX Vref Byte 0 = 62 to rank1
7938 00:22:30.342649 Final RX Vref Byte 1 = 60 to rank1==
7939 00:22:30.345721 Dram Type= 6, Freq= 0, CH_0, rank 0
7940 00:22:30.352416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7941 00:22:30.352484 ==
7942 00:22:30.352539 DQS Delay:
7943 00:22:30.352592 DQS0 = 0, DQS1 = 0
7944 00:22:30.355283 DQM Delay:
7945 00:22:30.355358 DQM0 = 129, DQM1 = 121
7946 00:22:30.358693 DQ Delay:
7947 00:22:30.362192 DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126
7948 00:22:30.365647 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7949 00:22:30.369195 DQ8 =110, DQ9 =108, DQ10 =122, DQ11 =116
7950 00:22:30.372265 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
7951 00:22:30.372341
7952 00:22:30.372400
7953 00:22:30.372454
7954 00:22:30.375357 [DramC_TX_OE_Calibration] TA2
7955 00:22:30.378734 Original DQ_B0 (3 6) =30, OEN = 27
7956 00:22:30.382180 Original DQ_B1 (3 6) =30, OEN = 27
7957 00:22:30.385745 24, 0x0, End_B0=24 End_B1=24
7958 00:22:30.385821 25, 0x0, End_B0=25 End_B1=25
7959 00:22:30.389224 26, 0x0, End_B0=26 End_B1=26
7960 00:22:30.392156 27, 0x0, End_B0=27 End_B1=27
7961 00:22:30.395745 28, 0x0, End_B0=28 End_B1=28
7962 00:22:30.395821 29, 0x0, End_B0=29 End_B1=29
7963 00:22:30.398940 30, 0x0, End_B0=30 End_B1=30
7964 00:22:30.402717 31, 0x5151, End_B0=30 End_B1=30
7965 00:22:30.405705 Byte0 end_step=30 best_step=27
7966 00:22:30.409403 Byte1 end_step=30 best_step=27
7967 00:22:30.412355 Byte0 TX OE(2T, 0.5T) = (3, 3)
7968 00:22:30.412430 Byte1 TX OE(2T, 0.5T) = (3, 3)
7969 00:22:30.412488
7970 00:22:30.412540
7971 00:22:30.422303 [DQSOSCAuto] RK0, (LSB)MR18= 0x1408, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7972 00:22:30.425419 CH0 RK0: MR19=303, MR18=1408
7973 00:22:30.429354 CH0_RK0: MR19=0x303, MR18=0x1408, DQSOSC=399, MR23=63, INC=23, DEC=15
7974 00:22:30.433065
7975 00:22:30.436046 ----->DramcWriteLeveling(PI) begin...
7976 00:22:30.436122 ==
7977 00:22:30.439126 Dram Type= 6, Freq= 0, CH_0, rank 1
7978 00:22:30.442812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7979 00:22:30.442887 ==
7980 00:22:30.445916 Write leveling (Byte 0): 32 => 32
7981 00:22:30.449073 Write leveling (Byte 1): 27 => 27
7982 00:22:30.452709 DramcWriteLeveling(PI) end<-----
7983 00:22:30.452784
7984 00:22:30.452841 ==
7985 00:22:30.455934 Dram Type= 6, Freq= 0, CH_0, rank 1
7986 00:22:30.459570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 00:22:30.459646 ==
7988 00:22:30.462449 [Gating] SW mode calibration
7989 00:22:30.469361 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7990 00:22:30.475659 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7991 00:22:30.479208 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 00:22:30.482371 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 00:22:30.488873 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 00:22:30.492522 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7995 00:22:30.495957 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7996 00:22:30.502244 1 4 20 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
7997 00:22:30.505977 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 00:22:30.509082 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 00:22:30.512456 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 00:22:30.519320 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8001 00:22:30.522584 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8002 00:22:30.525608 1 5 12 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
8003 00:22:30.532421 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8004 00:22:30.536459 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8005 00:22:30.538905 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 00:22:30.545647 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 00:22:30.549429 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 00:22:30.552477 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8009 00:22:30.559280 1 6 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
8010 00:22:30.562350 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8011 00:22:30.565552 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8012 00:22:30.572688 1 6 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8013 00:22:30.575494 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 00:22:30.579210 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 00:22:30.586037 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 00:22:30.589376 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 00:22:30.592386 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 00:22:30.595870 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8019 00:22:30.602588 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8020 00:22:30.606099 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8021 00:22:30.609150 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 00:22:30.615876 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 00:22:30.619405 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 00:22:30.622622 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 00:22:30.629450 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 00:22:30.632451 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 00:22:30.636212 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 00:22:30.642889 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 00:22:30.645874 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 00:22:30.649825 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 00:22:30.655919 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 00:22:30.659595 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8033 00:22:30.662525 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8034 00:22:30.669646 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8035 00:22:30.669745 Total UI for P1: 0, mck2ui 16
8036 00:22:30.672720 best dqsien dly found for B0: ( 1, 9, 6)
8037 00:22:30.679322 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8038 00:22:30.682654 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8039 00:22:30.686245 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 00:22:30.689396 Total UI for P1: 0, mck2ui 16
8041 00:22:30.692848 best dqsien dly found for B1: ( 1, 9, 20)
8042 00:22:30.696150 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8043 00:22:30.699652 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8044 00:22:30.699736
8045 00:22:30.706003 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8046 00:22:30.709520 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8047 00:22:30.713095 [Gating] SW calibration Done
8048 00:22:30.713167 ==
8049 00:22:30.716459 Dram Type= 6, Freq= 0, CH_0, rank 1
8050 00:22:30.719691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 00:22:30.719796 ==
8052 00:22:30.719882 RX Vref Scan: 0
8053 00:22:30.719979
8054 00:22:30.723131 RX Vref 0 -> 0, step: 1
8055 00:22:30.723206
8056 00:22:30.725950 RX Delay 0 -> 252, step: 8
8057 00:22:30.729608 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8058 00:22:30.732862 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8059 00:22:30.736526 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8060 00:22:30.742674 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8061 00:22:30.746393 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8062 00:22:30.749479 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8063 00:22:30.753131 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8064 00:22:30.756330 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8065 00:22:30.763078 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8066 00:22:30.766220 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8067 00:22:30.769482 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8068 00:22:30.772769 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8069 00:22:30.776576 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8070 00:22:30.782744 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8071 00:22:30.786287 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8072 00:22:30.789795 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8073 00:22:30.789894 ==
8074 00:22:30.792901 Dram Type= 6, Freq= 0, CH_0, rank 1
8075 00:22:30.796107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8076 00:22:30.796203 ==
8077 00:22:30.799551 DQS Delay:
8078 00:22:30.799635 DQS0 = 0, DQS1 = 0
8079 00:22:30.802915 DQM Delay:
8080 00:22:30.802987 DQM0 = 131, DQM1 = 124
8081 00:22:30.803061 DQ Delay:
8082 00:22:30.809774 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8083 00:22:30.812607 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8084 00:22:30.816360 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8085 00:22:30.819952 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8086 00:22:30.820048
8087 00:22:30.820136
8088 00:22:30.820221 ==
8089 00:22:30.822808 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 00:22:30.826439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 00:22:30.826508 ==
8092 00:22:30.826565
8093 00:22:30.826622
8094 00:22:30.829773 TX Vref Scan disable
8095 00:22:30.832934 == TX Byte 0 ==
8096 00:22:30.836313 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8097 00:22:30.839796 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8098 00:22:30.842968 == TX Byte 1 ==
8099 00:22:30.846571 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8100 00:22:30.849714 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8101 00:22:30.849820 ==
8102 00:22:30.853377 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 00:22:30.856537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 00:22:30.856633 ==
8105 00:22:30.872669
8106 00:22:30.875702 TX Vref early break, caculate TX vref
8107 00:22:30.878792 TX Vref=16, minBit 0, minWin=22, winSum=370
8108 00:22:30.882277 TX Vref=18, minBit 1, minWin=23, winSum=383
8109 00:22:30.885359 TX Vref=20, minBit 8, minWin=23, winSum=392
8110 00:22:30.889186 TX Vref=22, minBit 7, minWin=24, winSum=405
8111 00:22:30.892714 TX Vref=24, minBit 0, minWin=25, winSum=411
8112 00:22:30.899280 TX Vref=26, minBit 4, minWin=25, winSum=418
8113 00:22:30.902405 TX Vref=28, minBit 4, minWin=25, winSum=423
8114 00:22:30.905995 TX Vref=30, minBit 4, minWin=25, winSum=420
8115 00:22:30.908883 TX Vref=32, minBit 1, minWin=25, winSum=414
8116 00:22:30.912273 TX Vref=34, minBit 0, minWin=24, winSum=402
8117 00:22:30.915573 TX Vref=36, minBit 1, minWin=24, winSum=394
8118 00:22:30.922152 [TxChooseVref] Worse bit 4, Min win 25, Win sum 423, Final Vref 28
8119 00:22:30.922230
8120 00:22:30.925837 Final TX Range 0 Vref 28
8121 00:22:30.925934
8122 00:22:30.926018 ==
8123 00:22:30.928887 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 00:22:30.932481 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 00:22:30.932554 ==
8126 00:22:30.932614
8127 00:22:30.932666
8128 00:22:30.935390 TX Vref Scan disable
8129 00:22:30.942170 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8130 00:22:30.942242 == TX Byte 0 ==
8131 00:22:30.945400 u2DelayCellOfst[0]=14 cells (4 PI)
8132 00:22:30.948756 u2DelayCellOfst[1]=21 cells (6 PI)
8133 00:22:30.952211 u2DelayCellOfst[2]=10 cells (3 PI)
8134 00:22:30.955907 u2DelayCellOfst[3]=14 cells (4 PI)
8135 00:22:30.958869 u2DelayCellOfst[4]=10 cells (3 PI)
8136 00:22:30.962055 u2DelayCellOfst[5]=0 cells (0 PI)
8137 00:22:30.965690 u2DelayCellOfst[6]=21 cells (6 PI)
8138 00:22:30.968789 u2DelayCellOfst[7]=21 cells (6 PI)
8139 00:22:30.971950 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8140 00:22:30.975781 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8141 00:22:30.978878 == TX Byte 1 ==
8142 00:22:30.982096 u2DelayCellOfst[8]=0 cells (0 PI)
8143 00:22:30.982194 u2DelayCellOfst[9]=0 cells (0 PI)
8144 00:22:30.985731 u2DelayCellOfst[10]=7 cells (2 PI)
8145 00:22:30.988755 u2DelayCellOfst[11]=0 cells (0 PI)
8146 00:22:30.991978 u2DelayCellOfst[12]=10 cells (3 PI)
8147 00:22:30.995673 u2DelayCellOfst[13]=10 cells (3 PI)
8148 00:22:30.998675 u2DelayCellOfst[14]=14 cells (4 PI)
8149 00:22:31.002232 u2DelayCellOfst[15]=10 cells (3 PI)
8150 00:22:31.005706 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8151 00:22:31.011988 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8152 00:22:31.012087 DramC Write-DBI on
8153 00:22:31.012177 ==
8154 00:22:31.015905 Dram Type= 6, Freq= 0, CH_0, rank 1
8155 00:22:31.018869 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8156 00:22:31.022381 ==
8157 00:22:31.022464
8158 00:22:31.022542
8159 00:22:31.022634 TX Vref Scan disable
8160 00:22:31.025780 == TX Byte 0 ==
8161 00:22:31.028935 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8162 00:22:31.032732 == TX Byte 1 ==
8163 00:22:31.035686 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8164 00:22:31.038927 DramC Write-DBI off
8165 00:22:31.039002
8166 00:22:31.039078 [DATLAT]
8167 00:22:31.039170 Freq=1600, CH0 RK1
8168 00:22:31.039262
8169 00:22:31.042740 DATLAT Default: 0xf
8170 00:22:31.042811 0, 0xFFFF, sum = 0
8171 00:22:31.045677 1, 0xFFFF, sum = 0
8172 00:22:31.045773 2, 0xFFFF, sum = 0
8173 00:22:31.049294 3, 0xFFFF, sum = 0
8174 00:22:31.052365 4, 0xFFFF, sum = 0
8175 00:22:31.052466 5, 0xFFFF, sum = 0
8176 00:22:31.055758 6, 0xFFFF, sum = 0
8177 00:22:31.055859 7, 0xFFFF, sum = 0
8178 00:22:31.059209 8, 0xFFFF, sum = 0
8179 00:22:31.059311 9, 0xFFFF, sum = 0
8180 00:22:31.062138 10, 0xFFFF, sum = 0
8181 00:22:31.062238 11, 0xFFFF, sum = 0
8182 00:22:31.066003 12, 0xFFFF, sum = 0
8183 00:22:31.066084 13, 0xFFFF, sum = 0
8184 00:22:31.069352 14, 0x0, sum = 1
8185 00:22:31.069451 15, 0x0, sum = 2
8186 00:22:31.072366 16, 0x0, sum = 3
8187 00:22:31.072464 17, 0x0, sum = 4
8188 00:22:31.076167 best_step = 15
8189 00:22:31.076256
8190 00:22:31.076339 ==
8191 00:22:31.079169 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 00:22:31.082325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 00:22:31.082415 ==
8194 00:22:31.082497 RX Vref Scan: 0
8195 00:22:31.082577
8196 00:22:31.086032 RX Vref 0 -> 0, step: 1
8197 00:22:31.086116
8198 00:22:31.089074 RX Delay 11 -> 252, step: 4
8199 00:22:31.092719 iDelay=191, Bit 0, Center 128 (75 ~ 182) 108
8200 00:22:31.098940 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8201 00:22:31.102474 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8202 00:22:31.106107 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8203 00:22:31.108968 iDelay=191, Bit 4, Center 128 (75 ~ 182) 108
8204 00:22:31.112736 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8205 00:22:31.115826 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8206 00:22:31.122643 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8207 00:22:31.125665 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8208 00:22:31.128884 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8209 00:22:31.132499 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8210 00:22:31.136070 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8211 00:22:31.142375 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8212 00:22:31.145929 iDelay=191, Bit 13, Center 126 (71 ~ 182) 112
8213 00:22:31.148905 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8214 00:22:31.152641 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8215 00:22:31.152733 ==
8216 00:22:31.155894 Dram Type= 6, Freq= 0, CH_0, rank 1
8217 00:22:31.162654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8218 00:22:31.162749 ==
8219 00:22:31.162833 DQS Delay:
8220 00:22:31.166156 DQS0 = 0, DQS1 = 0
8221 00:22:31.166259 DQM Delay:
8222 00:22:31.166357 DQM0 = 128, DQM1 = 122
8223 00:22:31.169090 DQ Delay:
8224 00:22:31.172530 DQ0 =128, DQ1 =130, DQ2 =124, DQ3 =126
8225 00:22:31.175635 DQ4 =128, DQ5 =116, DQ6 =136, DQ7 =136
8226 00:22:31.179374 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8227 00:22:31.182905 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130
8228 00:22:31.182982
8229 00:22:31.183081
8230 00:22:31.183170
8231 00:22:31.186159 [DramC_TX_OE_Calibration] TA2
8232 00:22:31.189185 Original DQ_B0 (3 6) =30, OEN = 27
8233 00:22:31.192954 Original DQ_B1 (3 6) =30, OEN = 27
8234 00:22:31.196144 24, 0x0, End_B0=24 End_B1=24
8235 00:22:31.196251 25, 0x0, End_B0=25 End_B1=25
8236 00:22:31.199098 26, 0x0, End_B0=26 End_B1=26
8237 00:22:31.202956 27, 0x0, End_B0=27 End_B1=27
8238 00:22:31.206072 28, 0x0, End_B0=28 End_B1=28
8239 00:22:31.209063 29, 0x0, End_B0=29 End_B1=29
8240 00:22:31.209142 30, 0x0, End_B0=30 End_B1=30
8241 00:22:31.212551 31, 0x4141, End_B0=30 End_B1=30
8242 00:22:31.216208 Byte0 end_step=30 best_step=27
8243 00:22:31.219466 Byte1 end_step=30 best_step=27
8244 00:22:31.222661 Byte0 TX OE(2T, 0.5T) = (3, 3)
8245 00:22:31.222757 Byte1 TX OE(2T, 0.5T) = (3, 3)
8246 00:22:31.226245
8247 00:22:31.226327
8248 00:22:31.233038 [DQSOSCAuto] RK1, (LSB)MR18= 0x180d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8249 00:22:31.236127 CH0 RK1: MR19=303, MR18=180D
8250 00:22:31.242927 CH0_RK1: MR19=0x303, MR18=0x180D, DQSOSC=397, MR23=63, INC=23, DEC=15
8251 00:22:31.246145 [RxdqsGatingPostProcess] freq 1600
8252 00:22:31.249368 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8253 00:22:31.252706 best DQS0 dly(2T, 0.5T) = (1, 1)
8254 00:22:31.256166 best DQS1 dly(2T, 0.5T) = (1, 1)
8255 00:22:31.259458 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8256 00:22:31.263005 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8257 00:22:31.265946 best DQS0 dly(2T, 0.5T) = (1, 1)
8258 00:22:31.269627 best DQS1 dly(2T, 0.5T) = (1, 1)
8259 00:22:31.272651 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8260 00:22:31.276403 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8261 00:22:31.276491 Pre-setting of DQS Precalculation
8262 00:22:31.282815 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8263 00:22:31.282917 ==
8264 00:22:31.286356 Dram Type= 6, Freq= 0, CH_1, rank 0
8265 00:22:31.289640 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8266 00:22:31.289739 ==
8267 00:22:31.295878 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8268 00:22:31.299208 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8269 00:22:31.302880 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8270 00:22:31.309730 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8271 00:22:31.318746 [CA 0] Center 42 (13~71) winsize 59
8272 00:22:31.322388 [CA 1] Center 42 (13~71) winsize 59
8273 00:22:31.325498 [CA 2] Center 37 (8~66) winsize 59
8274 00:22:31.329244 [CA 3] Center 36 (7~65) winsize 59
8275 00:22:31.332464 [CA 4] Center 37 (8~67) winsize 60
8276 00:22:31.335535 [CA 5] Center 36 (6~66) winsize 61
8277 00:22:31.335602
8278 00:22:31.338843 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8279 00:22:31.338913
8280 00:22:31.342440 [CATrainingPosCal] consider 1 rank data
8281 00:22:31.345520 u2DelayCellTimex100 = 275/100 ps
8282 00:22:31.348722 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8283 00:22:31.355734 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8284 00:22:31.359020 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8285 00:22:31.362289 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8286 00:22:31.365831 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8287 00:22:31.369079 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8288 00:22:31.369185
8289 00:22:31.372113 CA PerBit enable=1, Macro0, CA PI delay=36
8290 00:22:31.372219
8291 00:22:31.375852 [CBTSetCACLKResult] CA Dly = 36
8292 00:22:31.375978 CS Dly: 9 (0~40)
8293 00:22:31.381971 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8294 00:22:31.385769 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8295 00:22:31.385865 ==
8296 00:22:31.388861 Dram Type= 6, Freq= 0, CH_1, rank 1
8297 00:22:31.392769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8298 00:22:31.392846 ==
8299 00:22:31.399132 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8300 00:22:31.402434 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8301 00:22:31.405714 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8302 00:22:31.412350 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8303 00:22:31.422324 [CA 0] Center 43 (14~72) winsize 59
8304 00:22:31.425175 [CA 1] Center 43 (14~72) winsize 59
8305 00:22:31.428793 [CA 2] Center 38 (10~67) winsize 58
8306 00:22:31.431971 [CA 3] Center 37 (8~67) winsize 60
8307 00:22:31.435755 [CA 4] Center 38 (8~68) winsize 61
8308 00:22:31.438841 [CA 5] Center 37 (8~66) winsize 59
8309 00:22:31.438914
8310 00:22:31.442499 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8311 00:22:31.442597
8312 00:22:31.445605 [CATrainingPosCal] consider 2 rank data
8313 00:22:31.449179 u2DelayCellTimex100 = 275/100 ps
8314 00:22:31.452140 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8315 00:22:31.458915 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8316 00:22:31.461899 CA2 delay=38 (10~66),Diff = 2 PI (7 cell)
8317 00:22:31.465400 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8318 00:22:31.468998 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8319 00:22:31.472163 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8320 00:22:31.472259
8321 00:22:31.475435 CA PerBit enable=1, Macro0, CA PI delay=36
8322 00:22:31.475532
8323 00:22:31.478985 [CBTSetCACLKResult] CA Dly = 36
8324 00:22:31.482112 CS Dly: 10 (0~43)
8325 00:22:31.485717 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8326 00:22:31.488863 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8327 00:22:31.488933
8328 00:22:31.491953 ----->DramcWriteLeveling(PI) begin...
8329 00:22:31.492023 ==
8330 00:22:31.495690 Dram Type= 6, Freq= 0, CH_1, rank 0
8331 00:22:31.498842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 00:22:31.501861 ==
8333 00:22:31.501933 Write leveling (Byte 0): 26 => 26
8334 00:22:31.505744 Write leveling (Byte 1): 28 => 28
8335 00:22:31.508827 DramcWriteLeveling(PI) end<-----
8336 00:22:31.508915
8337 00:22:31.508974 ==
8338 00:22:31.511778 Dram Type= 6, Freq= 0, CH_1, rank 0
8339 00:22:31.518742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8340 00:22:31.518851 ==
8341 00:22:31.518949 [Gating] SW mode calibration
8342 00:22:31.528755 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8343 00:22:31.531794 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8344 00:22:31.538541 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 00:22:31.541735 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 00:22:31.545302 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 00:22:31.548604 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 00:22:31.555480 1 4 16 | B1->B0 | 2626 2727 | 1 0 | (1 1) (0 0)
8349 00:22:31.558649 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 00:22:31.561700 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 00:22:31.568347 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 00:22:31.572160 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 00:22:31.575228 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 00:22:31.582222 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8355 00:22:31.585531 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8356 00:22:31.588332 1 5 16 | B1->B0 | 2d2d 3232 | 0 0 | (0 1) (1 0)
8357 00:22:31.595455 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 00:22:31.598462 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 00:22:31.601580 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 00:22:31.608212 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 00:22:31.611924 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 00:22:31.615071 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 00:22:31.621660 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 00:22:31.625505 1 6 16 | B1->B0 | 3c3c 3737 | 0 0 | (0 0) (1 1)
8365 00:22:31.628448 1 6 20 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8366 00:22:31.631815 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 00:22:31.638672 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 00:22:31.642022 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 00:22:31.645333 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 00:22:31.651999 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 00:22:31.655723 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 00:22:31.658836 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8373 00:22:31.665609 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 00:22:31.668545 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 00:22:31.671953 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 00:22:31.678606 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 00:22:31.682352 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 00:22:31.685457 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 00:22:31.691945 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 00:22:31.695477 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 00:22:31.699006 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 00:22:31.705440 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 00:22:31.709038 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 00:22:31.712046 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 00:22:31.715705 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 00:22:31.721886 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 00:22:31.725694 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 00:22:31.728772 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8389 00:22:31.731890 Total UI for P1: 0, mck2ui 16
8390 00:22:31.735602 best dqsien dly found for B0: ( 1, 9, 14)
8391 00:22:31.742160 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8392 00:22:31.745574 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 00:22:31.749190 Total UI for P1: 0, mck2ui 16
8394 00:22:31.752025 best dqsien dly found for B1: ( 1, 9, 18)
8395 00:22:31.755613 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8396 00:22:31.759163 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8397 00:22:31.759242
8398 00:22:31.762520 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8399 00:22:31.765606 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8400 00:22:31.768772 [Gating] SW calibration Done
8401 00:22:31.768869 ==
8402 00:22:31.772513 Dram Type= 6, Freq= 0, CH_1, rank 0
8403 00:22:31.775568 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8404 00:22:31.779106 ==
8405 00:22:31.779205 RX Vref Scan: 0
8406 00:22:31.779291
8407 00:22:31.781977 RX Vref 0 -> 0, step: 1
8408 00:22:31.782052
8409 00:22:31.782107 RX Delay 0 -> 252, step: 8
8410 00:22:31.789166 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8411 00:22:31.792849 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8412 00:22:31.795751 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8413 00:22:31.799348 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8414 00:22:31.802290 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8415 00:22:31.809232 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8416 00:22:31.812800 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8417 00:22:31.815816 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8418 00:22:31.819524 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8419 00:22:31.822536 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8420 00:22:31.826222 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8421 00:22:31.832443 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8422 00:22:31.836132 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8423 00:22:31.839204 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8424 00:22:31.842959 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8425 00:22:31.849506 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8426 00:22:31.849594 ==
8427 00:22:31.852434 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 00:22:31.856167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 00:22:31.856246 ==
8430 00:22:31.856305 DQS Delay:
8431 00:22:31.859271 DQS0 = 0, DQS1 = 0
8432 00:22:31.859349 DQM Delay:
8433 00:22:31.862703 DQM0 = 134, DQM1 = 127
8434 00:22:31.862783 DQ Delay:
8435 00:22:31.866123 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8436 00:22:31.869506 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8437 00:22:31.872553 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8438 00:22:31.876317 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8439 00:22:31.876395
8440 00:22:31.876454
8441 00:22:31.876509 ==
8442 00:22:31.879302 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 00:22:31.885976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 00:22:31.886061 ==
8445 00:22:31.886121
8446 00:22:31.886177
8447 00:22:31.889577 TX Vref Scan disable
8448 00:22:31.889655 == TX Byte 0 ==
8449 00:22:31.892544 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8450 00:22:31.899332 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8451 00:22:31.899411 == TX Byte 1 ==
8452 00:22:31.902353 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8453 00:22:31.909239 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8454 00:22:31.909317 ==
8455 00:22:31.912375 Dram Type= 6, Freq= 0, CH_1, rank 0
8456 00:22:31.916043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8457 00:22:31.916122 ==
8458 00:22:31.928434
8459 00:22:31.932140 TX Vref early break, caculate TX vref
8460 00:22:31.935253 TX Vref=16, minBit 8, minWin=20, winSum=358
8461 00:22:31.938390 TX Vref=18, minBit 8, minWin=21, winSum=372
8462 00:22:31.942013 TX Vref=20, minBit 8, minWin=22, winSum=384
8463 00:22:31.945218 TX Vref=22, minBit 5, minWin=23, winSum=394
8464 00:22:31.948468 TX Vref=24, minBit 8, minWin=23, winSum=405
8465 00:22:31.954862 TX Vref=26, minBit 0, minWin=24, winSum=411
8466 00:22:31.958313 TX Vref=28, minBit 1, minWin=25, winSum=419
8467 00:22:31.961889 TX Vref=30, minBit 8, minWin=24, winSum=416
8468 00:22:31.965173 TX Vref=32, minBit 11, minWin=24, winSum=411
8469 00:22:31.968599 TX Vref=34, minBit 11, minWin=23, winSum=397
8470 00:22:31.975312 [TxChooseVref] Worse bit 1, Min win 25, Win sum 419, Final Vref 28
8471 00:22:31.975391
8472 00:22:31.978270 Final TX Range 0 Vref 28
8473 00:22:31.978346
8474 00:22:31.978405 ==
8475 00:22:31.981800 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 00:22:31.984943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 00:22:31.985021 ==
8478 00:22:31.985081
8479 00:22:31.985137
8480 00:22:31.988392 TX Vref Scan disable
8481 00:22:31.994983 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8482 00:22:31.995063 == TX Byte 0 ==
8483 00:22:31.998915 u2DelayCellOfst[0]=17 cells (5 PI)
8484 00:22:32.001704 u2DelayCellOfst[1]=10 cells (3 PI)
8485 00:22:32.005037 u2DelayCellOfst[2]=0 cells (0 PI)
8486 00:22:32.008731 u2DelayCellOfst[3]=7 cells (2 PI)
8487 00:22:32.011943 u2DelayCellOfst[4]=7 cells (2 PI)
8488 00:22:32.015094 u2DelayCellOfst[5]=21 cells (6 PI)
8489 00:22:32.015172 u2DelayCellOfst[6]=17 cells (5 PI)
8490 00:22:32.018259 u2DelayCellOfst[7]=7 cells (2 PI)
8491 00:22:32.025708 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8492 00:22:32.028618 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8493 00:22:32.028720 == TX Byte 1 ==
8494 00:22:32.032279 u2DelayCellOfst[8]=0 cells (0 PI)
8495 00:22:32.035230 u2DelayCellOfst[9]=3 cells (1 PI)
8496 00:22:32.038796 u2DelayCellOfst[10]=10 cells (3 PI)
8497 00:22:32.041922 u2DelayCellOfst[11]=7 cells (2 PI)
8498 00:22:32.045829 u2DelayCellOfst[12]=14 cells (4 PI)
8499 00:22:32.048808 u2DelayCellOfst[13]=14 cells (4 PI)
8500 00:22:32.052519 u2DelayCellOfst[14]=17 cells (5 PI)
8501 00:22:32.055585 u2DelayCellOfst[15]=17 cells (5 PI)
8502 00:22:32.058787 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8503 00:22:32.062530 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8504 00:22:32.065499 DramC Write-DBI on
8505 00:22:32.065600 ==
8506 00:22:32.069118 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 00:22:32.072229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 00:22:32.072307 ==
8509 00:22:32.072367
8510 00:22:32.072423
8511 00:22:32.075671 TX Vref Scan disable
8512 00:22:32.079234 == TX Byte 0 ==
8513 00:22:32.082221 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8514 00:22:32.082317 == TX Byte 1 ==
8515 00:22:32.088977 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8516 00:22:32.089048 DramC Write-DBI off
8517 00:22:32.089106
8518 00:22:32.092445 [DATLAT]
8519 00:22:32.092529 Freq=1600, CH1 RK0
8520 00:22:32.092591
8521 00:22:32.095678 DATLAT Default: 0xf
8522 00:22:32.095783 0, 0xFFFF, sum = 0
8523 00:22:32.098796 1, 0xFFFF, sum = 0
8524 00:22:32.098869 2, 0xFFFF, sum = 0
8525 00:22:32.102743 3, 0xFFFF, sum = 0
8526 00:22:32.102816 4, 0xFFFF, sum = 0
8527 00:22:32.105735 5, 0xFFFF, sum = 0
8528 00:22:32.105801 6, 0xFFFF, sum = 0
8529 00:22:32.108830 7, 0xFFFF, sum = 0
8530 00:22:32.108895 8, 0xFFFF, sum = 0
8531 00:22:32.112440 9, 0xFFFF, sum = 0
8532 00:22:32.112518 10, 0xFFFF, sum = 0
8533 00:22:32.115600 11, 0xFFFF, sum = 0
8534 00:22:32.115679 12, 0xFFFF, sum = 0
8535 00:22:32.119383 13, 0xFFFF, sum = 0
8536 00:22:32.119461 14, 0x0, sum = 1
8537 00:22:32.122506 15, 0x0, sum = 2
8538 00:22:32.122583 16, 0x0, sum = 3
8539 00:22:32.125682 17, 0x0, sum = 4
8540 00:22:32.125783 best_step = 15
8541 00:22:32.125868
8542 00:22:32.125947 ==
8543 00:22:32.129292 Dram Type= 6, Freq= 0, CH_1, rank 0
8544 00:22:32.135873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8545 00:22:32.135950 ==
8546 00:22:32.136008 RX Vref Scan: 1
8547 00:22:32.136061
8548 00:22:32.139087 Set Vref Range= 24 -> 127
8549 00:22:32.139163
8550 00:22:32.142318 RX Vref 24 -> 127, step: 1
8551 00:22:32.142393
8552 00:22:32.142451 RX Delay 19 -> 252, step: 4
8553 00:22:32.146040
8554 00:22:32.146116 Set Vref, RX VrefLevel [Byte0]: 24
8555 00:22:32.149153 [Byte1]: 24
8556 00:22:32.153402
8557 00:22:32.153477 Set Vref, RX VrefLevel [Byte0]: 25
8558 00:22:32.156418 [Byte1]: 25
8559 00:22:32.160825
8560 00:22:32.160901 Set Vref, RX VrefLevel [Byte0]: 26
8561 00:22:32.163823 [Byte1]: 26
8562 00:22:32.168236
8563 00:22:32.168311 Set Vref, RX VrefLevel [Byte0]: 27
8564 00:22:32.171750 [Byte1]: 27
8565 00:22:32.175903
8566 00:22:32.175978 Set Vref, RX VrefLevel [Byte0]: 28
8567 00:22:32.179035 [Byte1]: 28
8568 00:22:32.183645
8569 00:22:32.183722 Set Vref, RX VrefLevel [Byte0]: 29
8570 00:22:32.186606 [Byte1]: 29
8571 00:22:32.190833
8572 00:22:32.190909 Set Vref, RX VrefLevel [Byte0]: 30
8573 00:22:32.194556 [Byte1]: 30
8574 00:22:32.198728
8575 00:22:32.198803 Set Vref, RX VrefLevel [Byte0]: 31
8576 00:22:32.202071 [Byte1]: 31
8577 00:22:32.206341
8578 00:22:32.206440 Set Vref, RX VrefLevel [Byte0]: 32
8579 00:22:32.209444 [Byte1]: 32
8580 00:22:32.213723
8581 00:22:32.213845 Set Vref, RX VrefLevel [Byte0]: 33
8582 00:22:32.216832 [Byte1]: 33
8583 00:22:32.221007
8584 00:22:32.221099 Set Vref, RX VrefLevel [Byte0]: 34
8585 00:22:32.224741 [Byte1]: 34
8586 00:22:32.229016
8587 00:22:32.229091 Set Vref, RX VrefLevel [Byte0]: 35
8588 00:22:32.232217 [Byte1]: 35
8589 00:22:32.236385
8590 00:22:32.236478 Set Vref, RX VrefLevel [Byte0]: 36
8591 00:22:32.239878 [Byte1]: 36
8592 00:22:32.244198
8593 00:22:32.244274 Set Vref, RX VrefLevel [Byte0]: 37
8594 00:22:32.247283 [Byte1]: 37
8595 00:22:32.251741
8596 00:22:32.251817 Set Vref, RX VrefLevel [Byte0]: 38
8597 00:22:32.255325 [Byte1]: 38
8598 00:22:32.259368
8599 00:22:32.259445 Set Vref, RX VrefLevel [Byte0]: 39
8600 00:22:32.262550 [Byte1]: 39
8601 00:22:32.267087
8602 00:22:32.267157 Set Vref, RX VrefLevel [Byte0]: 40
8603 00:22:32.270236 [Byte1]: 40
8604 00:22:32.274448
8605 00:22:32.274515 Set Vref, RX VrefLevel [Byte0]: 41
8606 00:22:32.277515 [Byte1]: 41
8607 00:22:32.281565
8608 00:22:32.281679 Set Vref, RX VrefLevel [Byte0]: 42
8609 00:22:32.285279 [Byte1]: 42
8610 00:22:32.289329
8611 00:22:32.289405 Set Vref, RX VrefLevel [Byte0]: 43
8612 00:22:32.292810 [Byte1]: 43
8613 00:22:32.297078
8614 00:22:32.297154 Set Vref, RX VrefLevel [Byte0]: 44
8615 00:22:32.300259 [Byte1]: 44
8616 00:22:32.304558
8617 00:22:32.304633 Set Vref, RX VrefLevel [Byte0]: 45
8618 00:22:32.308164 [Byte1]: 45
8619 00:22:32.312154
8620 00:22:32.312230 Set Vref, RX VrefLevel [Byte0]: 46
8621 00:22:32.315712 [Byte1]: 46
8622 00:22:32.319589
8623 00:22:32.319665 Set Vref, RX VrefLevel [Byte0]: 47
8624 00:22:32.322980 [Byte1]: 47
8625 00:22:32.327335
8626 00:22:32.327411 Set Vref, RX VrefLevel [Byte0]: 48
8627 00:22:32.330852 [Byte1]: 48
8628 00:22:32.334667
8629 00:22:32.334742 Set Vref, RX VrefLevel [Byte0]: 49
8630 00:22:32.338442 [Byte1]: 49
8631 00:22:32.342203
8632 00:22:32.342270 Set Vref, RX VrefLevel [Byte0]: 50
8633 00:22:32.345706 [Byte1]: 50
8634 00:22:32.350043
8635 00:22:32.350109 Set Vref, RX VrefLevel [Byte0]: 51
8636 00:22:32.353130 [Byte1]: 51
8637 00:22:32.357600
8638 00:22:32.357701 Set Vref, RX VrefLevel [Byte0]: 52
8639 00:22:32.360675 [Byte1]: 52
8640 00:22:32.365304
8641 00:22:32.365371 Set Vref, RX VrefLevel [Byte0]: 53
8642 00:22:32.368619 [Byte1]: 53
8643 00:22:32.372863
8644 00:22:32.372929 Set Vref, RX VrefLevel [Byte0]: 54
8645 00:22:32.376021 [Byte1]: 54
8646 00:22:32.380416
8647 00:22:32.380480 Set Vref, RX VrefLevel [Byte0]: 55
8648 00:22:32.383539 [Byte1]: 55
8649 00:22:32.387688
8650 00:22:32.387764 Set Vref, RX VrefLevel [Byte0]: 56
8651 00:22:32.391468 [Byte1]: 56
8652 00:22:32.395670
8653 00:22:32.395743 Set Vref, RX VrefLevel [Byte0]: 57
8654 00:22:32.399063 [Byte1]: 57
8655 00:22:32.402727
8656 00:22:32.402795 Set Vref, RX VrefLevel [Byte0]: 58
8657 00:22:32.406464 [Byte1]: 58
8658 00:22:32.411016
8659 00:22:32.411091 Set Vref, RX VrefLevel [Byte0]: 59
8660 00:22:32.414027 [Byte1]: 59
8661 00:22:32.418307
8662 00:22:32.418385 Set Vref, RX VrefLevel [Byte0]: 60
8663 00:22:32.421350 [Byte1]: 60
8664 00:22:32.425641
8665 00:22:32.425720 Set Vref, RX VrefLevel [Byte0]: 61
8666 00:22:32.429174 [Byte1]: 61
8667 00:22:32.432982
8668 00:22:32.433082 Set Vref, RX VrefLevel [Byte0]: 62
8669 00:22:32.436891 [Byte1]: 62
8670 00:22:32.441213
8671 00:22:32.441285 Set Vref, RX VrefLevel [Byte0]: 63
8672 00:22:32.444225 [Byte1]: 63
8673 00:22:32.448256
8674 00:22:32.448351 Set Vref, RX VrefLevel [Byte0]: 64
8675 00:22:32.451716 [Byte1]: 64
8676 00:22:32.456285
8677 00:22:32.456362 Set Vref, RX VrefLevel [Byte0]: 65
8678 00:22:32.459445 [Byte1]: 65
8679 00:22:32.463612
8680 00:22:32.463688 Set Vref, RX VrefLevel [Byte0]: 66
8681 00:22:32.466645 [Byte1]: 66
8682 00:22:32.471457
8683 00:22:32.471534 Set Vref, RX VrefLevel [Byte0]: 67
8684 00:22:32.474364 [Byte1]: 67
8685 00:22:32.478654
8686 00:22:32.478747 Set Vref, RX VrefLevel [Byte0]: 68
8687 00:22:32.481925 [Byte1]: 68
8688 00:22:32.486232
8689 00:22:32.486319 Set Vref, RX VrefLevel [Byte0]: 69
8690 00:22:32.489750 [Byte1]: 69
8691 00:22:32.494037
8692 00:22:32.494114 Set Vref, RX VrefLevel [Byte0]: 70
8693 00:22:32.497225 [Byte1]: 70
8694 00:22:32.501447
8695 00:22:32.501527 Set Vref, RX VrefLevel [Byte0]: 71
8696 00:22:32.504961 [Byte1]: 71
8697 00:22:32.509233
8698 00:22:32.509309 Set Vref, RX VrefLevel [Byte0]: 72
8699 00:22:32.512432 [Byte1]: 72
8700 00:22:32.516791
8701 00:22:32.516867 Set Vref, RX VrefLevel [Byte0]: 73
8702 00:22:32.520273 [Byte1]: 73
8703 00:22:32.524581
8704 00:22:32.524657 Set Vref, RX VrefLevel [Byte0]: 74
8705 00:22:32.527513 [Byte1]: 74
8706 00:22:32.531719
8707 00:22:32.531809 Set Vref, RX VrefLevel [Byte0]: 75
8708 00:22:32.535352 [Byte1]: 75
8709 00:22:32.539489
8710 00:22:32.539589 Final RX Vref Byte 0 = 57 to rank0
8711 00:22:32.542996 Final RX Vref Byte 1 = 56 to rank0
8712 00:22:32.545911 Final RX Vref Byte 0 = 57 to rank1
8713 00:22:32.549080 Final RX Vref Byte 1 = 56 to rank1==
8714 00:22:32.552690 Dram Type= 6, Freq= 0, CH_1, rank 0
8715 00:22:32.559432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8716 00:22:32.559511 ==
8717 00:22:32.559570 DQS Delay:
8718 00:22:32.559625 DQS0 = 0, DQS1 = 0
8719 00:22:32.562550 DQM Delay:
8720 00:22:32.562626 DQM0 = 131, DQM1 = 124
8721 00:22:32.566281 DQ Delay:
8722 00:22:32.569300 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =130
8723 00:22:32.573003 DQ4 =130, DQ5 =142, DQ6 =144, DQ7 =128
8724 00:22:32.576021 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8725 00:22:32.579252 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8726 00:22:32.579391
8727 00:22:32.579492
8728 00:22:32.579574
8729 00:22:32.582985 [DramC_TX_OE_Calibration] TA2
8730 00:22:32.585749 Original DQ_B0 (3 6) =30, OEN = 27
8731 00:22:32.589557 Original DQ_B1 (3 6) =30, OEN = 27
8732 00:22:32.592791 24, 0x0, End_B0=24 End_B1=24
8733 00:22:32.592869 25, 0x0, End_B0=25 End_B1=25
8734 00:22:32.596064 26, 0x0, End_B0=26 End_B1=26
8735 00:22:32.599752 27, 0x0, End_B0=27 End_B1=27
8736 00:22:32.602697 28, 0x0, End_B0=28 End_B1=28
8737 00:22:32.602776 29, 0x0, End_B0=29 End_B1=29
8738 00:22:32.606035 30, 0x0, End_B0=30 End_B1=30
8739 00:22:32.609344 31, 0x4141, End_B0=30 End_B1=30
8740 00:22:32.613015 Byte0 end_step=30 best_step=27
8741 00:22:32.616019 Byte1 end_step=30 best_step=27
8742 00:22:32.619743 Byte0 TX OE(2T, 0.5T) = (3, 3)
8743 00:22:32.619820 Byte1 TX OE(2T, 0.5T) = (3, 3)
8744 00:22:32.619879
8745 00:22:32.619934
8746 00:22:32.629523 [DQSOSCAuto] RK0, (LSB)MR18= 0x14ff, (MSB)MR19= 0x302, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
8747 00:22:32.633075 CH1 RK0: MR19=302, MR18=14FF
8748 00:22:32.636253 CH1_RK0: MR19=0x302, MR18=0x14FF, DQSOSC=399, MR23=63, INC=23, DEC=15
8749 00:22:32.639772
8750 00:22:32.642890 ----->DramcWriteLeveling(PI) begin...
8751 00:22:32.642969 ==
8752 00:22:32.646414 Dram Type= 6, Freq= 0, CH_1, rank 1
8753 00:22:32.649316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8754 00:22:32.649394 ==
8755 00:22:32.652998 Write leveling (Byte 0): 27 => 27
8756 00:22:32.656438 Write leveling (Byte 1): 27 => 27
8757 00:22:32.659985 DramcWriteLeveling(PI) end<-----
8758 00:22:32.660061
8759 00:22:32.660120 ==
8760 00:22:32.663038 Dram Type= 6, Freq= 0, CH_1, rank 1
8761 00:22:32.666197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8762 00:22:32.666274 ==
8763 00:22:32.669803 [Gating] SW mode calibration
8764 00:22:32.676186 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8765 00:22:32.682950 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8766 00:22:32.686176 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 00:22:32.689942 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 00:22:32.692851 1 4 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8769 00:22:32.699686 1 4 12 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
8770 00:22:32.703429 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 00:22:32.706590 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 00:22:32.713144 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 00:22:32.716505 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 00:22:32.720083 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 00:22:32.727036 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8776 00:22:32.729942 1 5 8 | B1->B0 | 3333 2626 | 1 1 | (1 1) (1 0)
8777 00:22:32.733582 1 5 12 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
8778 00:22:32.740299 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8779 00:22:32.743242 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 00:22:32.746542 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 00:22:32.753155 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 00:22:32.756776 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 00:22:32.759798 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8784 00:22:32.763233 1 6 8 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
8785 00:22:32.769852 1 6 12 | B1->B0 | 3434 4646 | 0 0 | (1 1) (0 0)
8786 00:22:32.773003 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 00:22:32.776856 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 00:22:32.783529 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 00:22:32.786509 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 00:22:32.790102 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 00:22:32.796897 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8792 00:22:32.799724 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8793 00:22:32.803503 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8794 00:22:32.810220 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 00:22:32.813415 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 00:22:32.816635 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 00:22:32.823213 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 00:22:32.826674 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 00:22:32.830289 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 00:22:32.836799 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 00:22:32.840143 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 00:22:32.843561 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 00:22:32.850273 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 00:22:32.853453 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 00:22:32.856993 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 00:22:32.860057 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 00:22:32.867155 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 00:22:32.869904 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8809 00:22:32.873510 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8810 00:22:32.876965 Total UI for P1: 0, mck2ui 16
8811 00:22:32.879985 best dqsien dly found for B0: ( 1, 9, 8)
8812 00:22:32.886787 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8813 00:22:32.890165 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 00:22:32.893178 Total UI for P1: 0, mck2ui 16
8815 00:22:32.896988 best dqsien dly found for B1: ( 1, 9, 14)
8816 00:22:32.900290 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8817 00:22:32.903885 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8818 00:22:32.903962
8819 00:22:32.906768 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8820 00:22:32.909943 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8821 00:22:32.913820 [Gating] SW calibration Done
8822 00:22:32.913919 ==
8823 00:22:32.917026 Dram Type= 6, Freq= 0, CH_1, rank 1
8824 00:22:32.920244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 00:22:32.923801 ==
8826 00:22:32.923877 RX Vref Scan: 0
8827 00:22:32.923935
8828 00:22:32.926939 RX Vref 0 -> 0, step: 1
8829 00:22:32.927016
8830 00:22:32.927075 RX Delay 0 -> 252, step: 8
8831 00:22:32.933762 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8832 00:22:32.936809 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8833 00:22:32.940501 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8834 00:22:32.943414 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8835 00:22:32.946823 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8836 00:22:32.953522 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8837 00:22:32.956676 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8838 00:22:32.960406 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8839 00:22:32.963841 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8840 00:22:32.966765 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8841 00:22:32.973399 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8842 00:22:32.977030 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8843 00:22:32.980575 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8844 00:22:32.983492 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8845 00:22:32.987354 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8846 00:22:32.994089 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8847 00:22:32.994166 ==
8848 00:22:32.997018 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 00:22:33.000666 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 00:22:33.000743 ==
8851 00:22:33.000801 DQS Delay:
8852 00:22:33.003787 DQS0 = 0, DQS1 = 0
8853 00:22:33.003863 DQM Delay:
8854 00:22:33.006832 DQM0 = 132, DQM1 = 127
8855 00:22:33.006909 DQ Delay:
8856 00:22:33.010539 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8857 00:22:33.014012 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =127
8858 00:22:33.017208 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8859 00:22:33.020355 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8860 00:22:33.020432
8861 00:22:33.020491
8862 00:22:33.023956 ==
8863 00:22:33.024033 Dram Type= 6, Freq= 0, CH_1, rank 1
8864 00:22:33.030250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8865 00:22:33.030327 ==
8866 00:22:33.030385
8867 00:22:33.030439
8868 00:22:33.033907 TX Vref Scan disable
8869 00:22:33.033990 == TX Byte 0 ==
8870 00:22:33.037077 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8871 00:22:33.043934 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8872 00:22:33.044010 == TX Byte 1 ==
8873 00:22:33.046851 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8874 00:22:33.053523 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8875 00:22:33.053599 ==
8876 00:22:33.057233 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 00:22:33.060285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 00:22:33.060362 ==
8879 00:22:33.074068
8880 00:22:33.077276 TX Vref early break, caculate TX vref
8881 00:22:33.080868 TX Vref=16, minBit 0, minWin=23, winSum=378
8882 00:22:33.083999 TX Vref=18, minBit 6, minWin=23, winSum=384
8883 00:22:33.087635 TX Vref=20, minBit 9, minWin=23, winSum=393
8884 00:22:33.090687 TX Vref=22, minBit 6, minWin=24, winSum=408
8885 00:22:33.094223 TX Vref=24, minBit 0, minWin=25, winSum=411
8886 00:22:33.100899 TX Vref=26, minBit 15, minWin=25, winSum=419
8887 00:22:33.104183 TX Vref=28, minBit 0, minWin=25, winSum=421
8888 00:22:33.107424 TX Vref=30, minBit 0, minWin=26, winSum=424
8889 00:22:33.110997 TX Vref=32, minBit 0, minWin=23, winSum=410
8890 00:22:33.113840 TX Vref=34, minBit 0, minWin=24, winSum=404
8891 00:22:33.117415 TX Vref=36, minBit 0, minWin=23, winSum=400
8892 00:22:33.124154 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 30
8893 00:22:33.124232
8894 00:22:33.127276 Final TX Range 0 Vref 30
8895 00:22:33.127352
8896 00:22:33.127410 ==
8897 00:22:33.130919 Dram Type= 6, Freq= 0, CH_1, rank 1
8898 00:22:33.133824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8899 00:22:33.133903 ==
8900 00:22:33.133963
8901 00:22:33.134041
8902 00:22:33.136996 TX Vref Scan disable
8903 00:22:33.143945 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8904 00:22:33.144022 == TX Byte 0 ==
8905 00:22:33.147279 u2DelayCellOfst[0]=21 cells (6 PI)
8906 00:22:33.150188 u2DelayCellOfst[1]=14 cells (4 PI)
8907 00:22:33.153963 u2DelayCellOfst[2]=0 cells (0 PI)
8908 00:22:33.157459 u2DelayCellOfst[3]=10 cells (3 PI)
8909 00:22:33.160475 u2DelayCellOfst[4]=14 cells (4 PI)
8910 00:22:33.164167 u2DelayCellOfst[5]=21 cells (6 PI)
8911 00:22:33.167184 u2DelayCellOfst[6]=21 cells (6 PI)
8912 00:22:33.170648 u2DelayCellOfst[7]=10 cells (3 PI)
8913 00:22:33.173646 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8914 00:22:33.176863 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8915 00:22:33.180510 == TX Byte 1 ==
8916 00:22:33.183534 u2DelayCellOfst[8]=0 cells (0 PI)
8917 00:22:33.186858 u2DelayCellOfst[9]=3 cells (1 PI)
8918 00:22:33.186935 u2DelayCellOfst[10]=10 cells (3 PI)
8919 00:22:33.190717 u2DelayCellOfst[11]=7 cells (2 PI)
8920 00:22:33.193919 u2DelayCellOfst[12]=14 cells (4 PI)
8921 00:22:33.196917 u2DelayCellOfst[13]=14 cells (4 PI)
8922 00:22:33.200666 u2DelayCellOfst[14]=17 cells (5 PI)
8923 00:22:33.203748 u2DelayCellOfst[15]=14 cells (4 PI)
8924 00:22:33.207345 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8925 00:22:33.213653 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8926 00:22:33.213754 DramC Write-DBI on
8927 00:22:33.213839 ==
8928 00:22:33.217339 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 00:22:33.223788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 00:22:33.223872 ==
8931 00:22:33.223932
8932 00:22:33.223986
8933 00:22:33.224038 TX Vref Scan disable
8934 00:22:33.227424 == TX Byte 0 ==
8935 00:22:33.231103 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8936 00:22:33.234193 == TX Byte 1 ==
8937 00:22:33.237967 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8938 00:22:33.238080 DramC Write-DBI off
8939 00:22:33.241018
8940 00:22:33.241094 [DATLAT]
8941 00:22:33.241152 Freq=1600, CH1 RK1
8942 00:22:33.241207
8943 00:22:33.244132 DATLAT Default: 0xf
8944 00:22:33.244208 0, 0xFFFF, sum = 0
8945 00:22:33.247831 1, 0xFFFF, sum = 0
8946 00:22:33.247923 2, 0xFFFF, sum = 0
8947 00:22:33.251084 3, 0xFFFF, sum = 0
8948 00:22:33.251191 4, 0xFFFF, sum = 0
8949 00:22:33.254228 5, 0xFFFF, sum = 0
8950 00:22:33.254305 6, 0xFFFF, sum = 0
8951 00:22:33.257920 7, 0xFFFF, sum = 0
8952 00:22:33.258019 8, 0xFFFF, sum = 0
8953 00:22:33.260881 9, 0xFFFF, sum = 0
8954 00:22:33.264718 10, 0xFFFF, sum = 0
8955 00:22:33.264795 11, 0xFFFF, sum = 0
8956 00:22:33.267728 12, 0xFFFF, sum = 0
8957 00:22:33.267805 13, 0xFFFF, sum = 0
8958 00:22:33.270988 14, 0x0, sum = 1
8959 00:22:33.271077 15, 0x0, sum = 2
8960 00:22:33.274692 16, 0x0, sum = 3
8961 00:22:33.274769 17, 0x0, sum = 4
8962 00:22:33.274830 best_step = 15
8963 00:22:33.277561
8964 00:22:33.277636 ==
8965 00:22:33.280953 Dram Type= 6, Freq= 0, CH_1, rank 1
8966 00:22:33.284776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8967 00:22:33.284852 ==
8968 00:22:33.284911 RX Vref Scan: 0
8969 00:22:33.284965
8970 00:22:33.287711 RX Vref 0 -> 0, step: 1
8971 00:22:33.287786
8972 00:22:33.291390 RX Delay 11 -> 252, step: 4
8973 00:22:33.294406 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8974 00:22:33.298039 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8975 00:22:33.304339 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8976 00:22:33.307660 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8977 00:22:33.311548 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8978 00:22:33.314954 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8979 00:22:33.317819 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8980 00:22:33.324701 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8981 00:22:33.327664 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8982 00:22:33.331165 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8983 00:22:33.335084 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8984 00:22:33.338212 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
8985 00:22:33.344975 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8986 00:22:33.347981 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8987 00:22:33.351118 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8988 00:22:33.354692 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
8989 00:22:33.354761 ==
8990 00:22:33.357870 Dram Type= 6, Freq= 0, CH_1, rank 1
8991 00:22:33.364378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8992 00:22:33.364451 ==
8993 00:22:33.364509 DQS Delay:
8994 00:22:33.364564 DQS0 = 0, DQS1 = 0
8995 00:22:33.367648 DQM Delay:
8996 00:22:33.367717 DQM0 = 129, DQM1 = 126
8997 00:22:33.371357 DQ Delay:
8998 00:22:33.374355 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
8999 00:22:33.378001 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =124
9000 00:22:33.381096 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9001 00:22:33.384610 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134
9002 00:22:33.384682
9003 00:22:33.384740
9004 00:22:33.384794
9005 00:22:33.388158 [DramC_TX_OE_Calibration] TA2
9006 00:22:33.391419 Original DQ_B0 (3 6) =30, OEN = 27
9007 00:22:33.395052 Original DQ_B1 (3 6) =30, OEN = 27
9008 00:22:33.398012 24, 0x0, End_B0=24 End_B1=24
9009 00:22:33.398080 25, 0x0, End_B0=25 End_B1=25
9010 00:22:33.401264 26, 0x0, End_B0=26 End_B1=26
9011 00:22:33.405006 27, 0x0, End_B0=27 End_B1=27
9012 00:22:33.407990 28, 0x0, End_B0=28 End_B1=28
9013 00:22:33.408088 29, 0x0, End_B0=29 End_B1=29
9014 00:22:33.411602 30, 0x0, End_B0=30 End_B1=30
9015 00:22:33.415123 31, 0x4141, End_B0=30 End_B1=30
9016 00:22:33.418001 Byte0 end_step=30 best_step=27
9017 00:22:33.421377 Byte1 end_step=30 best_step=27
9018 00:22:33.424636 Byte0 TX OE(2T, 0.5T) = (3, 3)
9019 00:22:33.424713 Byte1 TX OE(2T, 0.5T) = (3, 3)
9020 00:22:33.424772
9021 00:22:33.424826
9022 00:22:33.434482 [DQSOSCAuto] RK1, (LSB)MR18= 0xf15, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
9023 00:22:33.438131 CH1 RK1: MR19=303, MR18=F15
9024 00:22:33.441585 CH1_RK1: MR19=0x303, MR18=0xF15, DQSOSC=399, MR23=63, INC=23, DEC=15
9025 00:22:33.444729 [RxdqsGatingPostProcess] freq 1600
9026 00:22:33.451541 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9027 00:22:33.454642 best DQS0 dly(2T, 0.5T) = (1, 1)
9028 00:22:33.458292 best DQS1 dly(2T, 0.5T) = (1, 1)
9029 00:22:33.461425 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9030 00:22:33.465058 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9031 00:22:33.467929 best DQS0 dly(2T, 0.5T) = (1, 1)
9032 00:22:33.468032 best DQS1 dly(2T, 0.5T) = (1, 1)
9033 00:22:33.471698 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9034 00:22:33.474976 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9035 00:22:33.478171 Pre-setting of DQS Precalculation
9036 00:22:33.484726 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9037 00:22:33.491356 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9038 00:22:33.497936 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9039 00:22:33.498067
9040 00:22:33.498127
9041 00:22:33.501668 [Calibration Summary] 3200 Mbps
9042 00:22:33.501744 CH 0, Rank 0
9043 00:22:33.505102 SW Impedance : PASS
9044 00:22:33.508399 DUTY Scan : NO K
9045 00:22:33.508477 ZQ Calibration : PASS
9046 00:22:33.511694 Jitter Meter : NO K
9047 00:22:33.514938 CBT Training : PASS
9048 00:22:33.515014 Write leveling : PASS
9049 00:22:33.518377 RX DQS gating : PASS
9050 00:22:33.521787 RX DQ/DQS(RDDQC) : PASS
9051 00:22:33.521901 TX DQ/DQS : PASS
9052 00:22:33.524870 RX DATLAT : PASS
9053 00:22:33.528456 RX DQ/DQS(Engine): PASS
9054 00:22:33.528532 TX OE : PASS
9055 00:22:33.528590 All Pass.
9056 00:22:33.531335
9057 00:22:33.531411 CH 0, Rank 1
9058 00:22:33.534968 SW Impedance : PASS
9059 00:22:33.535045 DUTY Scan : NO K
9060 00:22:33.538395 ZQ Calibration : PASS
9061 00:22:33.538471 Jitter Meter : NO K
9062 00:22:33.541419 CBT Training : PASS
9063 00:22:33.544963 Write leveling : PASS
9064 00:22:33.545079 RX DQS gating : PASS
9065 00:22:33.547885 RX DQ/DQS(RDDQC) : PASS
9066 00:22:33.551358 TX DQ/DQS : PASS
9067 00:22:33.551446 RX DATLAT : PASS
9068 00:22:33.555106 RX DQ/DQS(Engine): PASS
9069 00:22:33.558274 TX OE : PASS
9070 00:22:33.558351 All Pass.
9071 00:22:33.558410
9072 00:22:33.558465 CH 1, Rank 0
9073 00:22:33.561180 SW Impedance : PASS
9074 00:22:33.564917 DUTY Scan : NO K
9075 00:22:33.564994 ZQ Calibration : PASS
9076 00:22:33.567932 Jitter Meter : NO K
9077 00:22:33.571525 CBT Training : PASS
9078 00:22:33.571601 Write leveling : PASS
9079 00:22:33.574289 RX DQS gating : PASS
9080 00:22:33.577995 RX DQ/DQS(RDDQC) : PASS
9081 00:22:33.578084 TX DQ/DQS : PASS
9082 00:22:33.581143 RX DATLAT : PASS
9083 00:22:33.584448 RX DQ/DQS(Engine): PASS
9084 00:22:33.584524 TX OE : PASS
9085 00:22:33.584612 All Pass.
9086 00:22:33.588020
9087 00:22:33.588096 CH 1, Rank 1
9088 00:22:33.588155 SW Impedance : PASS
9089 00:22:33.591237 DUTY Scan : NO K
9090 00:22:33.594792 ZQ Calibration : PASS
9091 00:22:33.594868 Jitter Meter : NO K
9092 00:22:33.597603 CBT Training : PASS
9093 00:22:33.601338 Write leveling : PASS
9094 00:22:33.601415 RX DQS gating : PASS
9095 00:22:33.604746 RX DQ/DQS(RDDQC) : PASS
9096 00:22:33.607850 TX DQ/DQS : PASS
9097 00:22:33.607927 RX DATLAT : PASS
9098 00:22:33.610900 RX DQ/DQS(Engine): PASS
9099 00:22:33.614532 TX OE : PASS
9100 00:22:33.614610 All Pass.
9101 00:22:33.614669
9102 00:22:33.614725 DramC Write-DBI on
9103 00:22:33.617598 PER_BANK_REFRESH: Hybrid Mode
9104 00:22:33.621346 TX_TRACKING: ON
9105 00:22:33.628181 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9106 00:22:33.637987 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9107 00:22:33.644670 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9108 00:22:33.648120 [FAST_K] Save calibration result to emmc
9109 00:22:33.651476 sync common calibartion params.
9110 00:22:33.654211 sync cbt_mode0:1, 1:1
9111 00:22:33.654318 dram_init: ddr_geometry: 2
9112 00:22:33.657951 dram_init: ddr_geometry: 2
9113 00:22:33.661605 dram_init: ddr_geometry: 2
9114 00:22:33.661704 0:dram_rank_size:100000000
9115 00:22:33.664695 1:dram_rank_size:100000000
9116 00:22:33.671365 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9117 00:22:33.671481 DFS_SHUFFLE_HW_MODE: ON
9118 00:22:33.678057 dramc_set_vcore_voltage set vcore to 725000
9119 00:22:33.678151 Read voltage for 1600, 0
9120 00:22:33.681128 Vio18 = 0
9121 00:22:33.681199 Vcore = 725000
9122 00:22:33.681257 Vdram = 0
9123 00:22:33.684803 Vddq = 0
9124 00:22:33.684867 Vmddr = 0
9125 00:22:33.687952 switch to 3200 Mbps bootup
9126 00:22:33.688031 [DramcRunTimeConfig]
9127 00:22:33.688089 PHYPLL
9128 00:22:33.691229 DPM_CONTROL_AFTERK: ON
9129 00:22:33.691306 PER_BANK_REFRESH: ON
9130 00:22:33.694896 REFRESH_OVERHEAD_REDUCTION: ON
9131 00:22:33.697919 CMD_PICG_NEW_MODE: OFF
9132 00:22:33.698021 XRTWTW_NEW_MODE: ON
9133 00:22:33.701367 XRTRTR_NEW_MODE: ON
9134 00:22:33.701442 TX_TRACKING: ON
9135 00:22:33.704833 RDSEL_TRACKING: OFF
9136 00:22:33.708053 DQS Precalculation for DVFS: ON
9137 00:22:33.708129 RX_TRACKING: OFF
9138 00:22:33.711727 HW_GATING DBG: ON
9139 00:22:33.711803 ZQCS_ENABLE_LP4: ON
9140 00:22:33.714778 RX_PICG_NEW_MODE: ON
9141 00:22:33.714854 TX_PICG_NEW_MODE: ON
9142 00:22:33.717733 ENABLE_RX_DCM_DPHY: ON
9143 00:22:33.721533 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9144 00:22:33.724611 DUMMY_READ_FOR_TRACKING: OFF
9145 00:22:33.728411 !!! SPM_CONTROL_AFTERK: OFF
9146 00:22:33.728491 !!! SPM could not control APHY
9147 00:22:33.731334 IMPEDANCE_TRACKING: ON
9148 00:22:33.731410 TEMP_SENSOR: ON
9149 00:22:33.734927 HW_SAVE_FOR_SR: OFF
9150 00:22:33.737862 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9151 00:22:33.740891 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9152 00:22:33.744591 Read ODT Tracking: ON
9153 00:22:33.744698 Refresh Rate DeBounce: ON
9154 00:22:33.748359 DFS_NO_QUEUE_FLUSH: ON
9155 00:22:33.751459 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9156 00:22:33.755118 ENABLE_DFS_RUNTIME_MRW: OFF
9157 00:22:33.755202 DDR_RESERVE_NEW_MODE: ON
9158 00:22:33.758156 MR_CBT_SWITCH_FREQ: ON
9159 00:22:33.761151 =========================
9160 00:22:33.778711 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9161 00:22:33.781915 dram_init: ddr_geometry: 2
9162 00:22:33.800430 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9163 00:22:33.803520 dram_init: dram init end (result: 0)
9164 00:22:33.810190 DRAM-K: Full calibration passed in 24554 msecs
9165 00:22:33.813426 MRC: failed to locate region type 0.
9166 00:22:33.813502 DRAM rank0 size:0x100000000,
9167 00:22:33.817356 DRAM rank1 size=0x100000000
9168 00:22:33.827260 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9169 00:22:33.833791 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9170 00:22:33.840707 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9171 00:22:33.847053 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9172 00:22:33.850234 DRAM rank0 size:0x100000000,
9173 00:22:33.853934 DRAM rank1 size=0x100000000
9174 00:22:33.854036 CBMEM:
9175 00:22:33.857012 IMD: root @ 0xfffff000 254 entries.
9176 00:22:33.860103 IMD: root @ 0xffffec00 62 entries.
9177 00:22:33.863567 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9178 00:22:33.867262 WARNING: RO_VPD is uninitialized or empty.
9179 00:22:33.873792 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9180 00:22:33.880600 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9181 00:22:33.893289 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9182 00:22:33.904908 BS: romstage times (exec / console): total (unknown) / 24065 ms
9183 00:22:33.904987
9184 00:22:33.905047
9185 00:22:33.914763 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9186 00:22:33.917817 ARM64: Exception handlers installed.
9187 00:22:33.921364 ARM64: Testing exception
9188 00:22:33.924748 ARM64: Done test exception
9189 00:22:33.924842 Enumerating buses...
9190 00:22:33.927931 Show all devs... Before device enumeration.
9191 00:22:33.931594 Root Device: enabled 1
9192 00:22:33.934544 CPU_CLUSTER: 0: enabled 1
9193 00:22:33.934620 CPU: 00: enabled 1
9194 00:22:33.938257 Compare with tree...
9195 00:22:33.938333 Root Device: enabled 1
9196 00:22:33.941229 CPU_CLUSTER: 0: enabled 1
9197 00:22:33.944971 CPU: 00: enabled 1
9198 00:22:33.945048 Root Device scanning...
9199 00:22:33.948138 scan_static_bus for Root Device
9200 00:22:33.951525 CPU_CLUSTER: 0 enabled
9201 00:22:33.954709 scan_static_bus for Root Device done
9202 00:22:33.958067 scan_bus: bus Root Device finished in 8 msecs
9203 00:22:33.958144 done
9204 00:22:33.964621 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9205 00:22:33.968267 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9206 00:22:33.974760 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9207 00:22:33.977794 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9208 00:22:33.981488 Allocating resources...
9209 00:22:33.981564 Reading resources...
9210 00:22:33.987830 Root Device read_resources bus 0 link: 0
9211 00:22:33.987941 DRAM rank0 size:0x100000000,
9212 00:22:33.991055 DRAM rank1 size=0x100000000
9213 00:22:33.994812 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9214 00:22:33.997853 CPU: 00 missing read_resources
9215 00:22:34.001322 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9216 00:22:34.007982 Root Device read_resources bus 0 link: 0 done
9217 00:22:34.008058 Done reading resources.
9218 00:22:34.014602 Show resources in subtree (Root Device)...After reading.
9219 00:22:34.017644 Root Device child on link 0 CPU_CLUSTER: 0
9220 00:22:34.020770 CPU_CLUSTER: 0 child on link 0 CPU: 00
9221 00:22:34.031086 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9222 00:22:34.031165 CPU: 00
9223 00:22:34.034455 Root Device assign_resources, bus 0 link: 0
9224 00:22:34.037876 CPU_CLUSTER: 0 missing set_resources
9225 00:22:34.040996 Root Device assign_resources, bus 0 link: 0 done
9226 00:22:34.044392 Done setting resources.
9227 00:22:34.051412 Show resources in subtree (Root Device)...After assigning values.
9228 00:22:34.054709 Root Device child on link 0 CPU_CLUSTER: 0
9229 00:22:34.058177 CPU_CLUSTER: 0 child on link 0 CPU: 00
9230 00:22:34.068169 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9231 00:22:34.068270 CPU: 00
9232 00:22:34.071414 Done allocating resources.
9233 00:22:34.074601 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9234 00:22:34.078287 Enabling resources...
9235 00:22:34.078379 done.
9236 00:22:34.081075 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9237 00:22:34.084823 Initializing devices...
9238 00:22:34.087994 Root Device init
9239 00:22:34.088062 init hardware done!
9240 00:22:34.091277 0x00000018: ctrlr->caps
9241 00:22:34.091345 52.000 MHz: ctrlr->f_max
9242 00:22:34.094842 0.400 MHz: ctrlr->f_min
9243 00:22:34.097941 0x40ff8080: ctrlr->voltages
9244 00:22:34.098056 sclk: 390625
9245 00:22:34.101187 Bus Width = 1
9246 00:22:34.101277 sclk: 390625
9247 00:22:34.101363 Bus Width = 1
9248 00:22:34.104837 Early init status = 3
9249 00:22:34.108035 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9250 00:22:34.112319 in-header: 03 fc 00 00 01 00 00 00
9251 00:22:34.115318 in-data: 00
9252 00:22:34.118877 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9253 00:22:34.123243 in-header: 03 fd 00 00 00 00 00 00
9254 00:22:34.126919 in-data:
9255 00:22:34.130036 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9256 00:22:34.133891 in-header: 03 fc 00 00 01 00 00 00
9257 00:22:34.136963 in-data: 00
9258 00:22:34.140277 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9259 00:22:34.146074 in-header: 03 fd 00 00 00 00 00 00
9260 00:22:34.149718 in-data:
9261 00:22:34.152673 [SSUSB] Setting up USB HOST controller...
9262 00:22:34.156530 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9263 00:22:34.159675 [SSUSB] phy power-on done.
9264 00:22:34.162872 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9265 00:22:34.169655 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9266 00:22:34.172975 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9267 00:22:34.179353 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9268 00:22:34.186150 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9269 00:22:34.192876 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9270 00:22:34.199791 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9271 00:22:34.206482 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9272 00:22:34.206563 SPM: binary array size = 0x9dc
9273 00:22:34.213345 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9274 00:22:34.220115 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9275 00:22:34.226163 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9276 00:22:34.229742 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9277 00:22:34.232713 configure_display: Starting display init
9278 00:22:34.269625 anx7625_power_on_init: Init interface.
9279 00:22:34.272708 anx7625_disable_pd_protocol: Disabled PD feature.
9280 00:22:34.275755 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9281 00:22:34.304124 anx7625_start_dp_work: Secure OCM version=00
9282 00:22:34.307306 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9283 00:22:34.321952 sp_tx_get_edid_block: EDID Block = 1
9284 00:22:34.424707 Extracted contents:
9285 00:22:34.427852 header: 00 ff ff ff ff ff ff 00
9286 00:22:34.430848 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9287 00:22:34.434690 version: 01 04
9288 00:22:34.437728 basic params: 95 1f 11 78 0a
9289 00:22:34.440899 chroma info: 76 90 94 55 54 90 27 21 50 54
9290 00:22:34.444063 established: 00 00 00
9291 00:22:34.451102 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9292 00:22:34.454158 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9293 00:22:34.460903 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9294 00:22:34.467687 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9295 00:22:34.473956 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9296 00:22:34.477829 extensions: 00
9297 00:22:34.477898 checksum: fb
9298 00:22:34.477957
9299 00:22:34.480913 Manufacturer: IVO Model 57d Serial Number 0
9300 00:22:34.484602 Made week 0 of 2020
9301 00:22:34.484680 EDID version: 1.4
9302 00:22:34.487979 Digital display
9303 00:22:34.491155 6 bits per primary color channel
9304 00:22:34.491273 DisplayPort interface
9305 00:22:34.494130 Maximum image size: 31 cm x 17 cm
9306 00:22:34.498041 Gamma: 220%
9307 00:22:34.498140 Check DPMS levels
9308 00:22:34.501217 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9309 00:22:34.504438 First detailed timing is preferred timing
9310 00:22:34.507411 Established timings supported:
9311 00:22:34.510985 Standard timings supported:
9312 00:22:34.511065 Detailed timings
9313 00:22:34.517906 Hex of detail: 383680a07038204018303c0035ae10000019
9314 00:22:34.521223 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9315 00:22:34.527509 0780 0798 07c8 0820 hborder 0
9316 00:22:34.530648 0438 043b 0447 0458 vborder 0
9317 00:22:34.530736 -hsync -vsync
9318 00:22:34.534401 Did detailed timing
9319 00:22:34.537662 Hex of detail: 000000000000000000000000000000000000
9320 00:22:34.540902 Manufacturer-specified data, tag 0
9321 00:22:34.547416 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9322 00:22:34.547519 ASCII string: InfoVision
9323 00:22:34.554066 Hex of detail: 000000fe00523134304e574635205248200a
9324 00:22:34.557250 ASCII string: R140NWF5 RH
9325 00:22:34.557357 Checksum
9326 00:22:34.557444 Checksum: 0xfb (valid)
9327 00:22:34.564109 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9328 00:22:34.567383 DSI data_rate: 832800000 bps
9329 00:22:34.571035 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9330 00:22:34.574295 anx7625_parse_edid: pixelclock(138800).
9331 00:22:34.580708 hactive(1920), hsync(48), hfp(24), hbp(88)
9332 00:22:34.584431 vactive(1080), vsync(12), vfp(3), vbp(17)
9333 00:22:34.587518 anx7625_dsi_config: config dsi.
9334 00:22:34.593934 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9335 00:22:34.606685 anx7625_dsi_config: success to config DSI
9336 00:22:34.609861 anx7625_dp_start: MIPI phy setup OK.
9337 00:22:34.613068 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9338 00:22:34.616307 mtk_ddp_mode_set invalid vrefresh 60
9339 00:22:34.619959 main_disp_path_setup
9340 00:22:34.620037 ovl_layer_smi_id_en
9341 00:22:34.623017 ovl_layer_smi_id_en
9342 00:22:34.623104 ccorr_config
9343 00:22:34.623164 aal_config
9344 00:22:34.626681 gamma_config
9345 00:22:34.626758 postmask_config
9346 00:22:34.630055 dither_config
9347 00:22:34.632852 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9348 00:22:34.639775 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9349 00:22:34.643343 Root Device init finished in 553 msecs
9350 00:22:34.643417 CPU_CLUSTER: 0 init
9351 00:22:34.653209 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9352 00:22:34.656241 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9353 00:22:34.660053 APU_MBOX 0x190000b0 = 0x10001
9354 00:22:34.663054 APU_MBOX 0x190001b0 = 0x10001
9355 00:22:34.666733 APU_MBOX 0x190005b0 = 0x10001
9356 00:22:34.669905 APU_MBOX 0x190006b0 = 0x10001
9357 00:22:34.673036 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9358 00:22:34.685514 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9359 00:22:34.697901 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9360 00:22:34.704714 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9361 00:22:34.716098 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9362 00:22:34.725625 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9363 00:22:34.729032 CPU_CLUSTER: 0 init finished in 81 msecs
9364 00:22:34.732059 Devices initialized
9365 00:22:34.735229 Show all devs... After init.
9366 00:22:34.735327 Root Device: enabled 1
9367 00:22:34.738934 CPU_CLUSTER: 0: enabled 1
9368 00:22:34.742183 CPU: 00: enabled 1
9369 00:22:34.745370 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9370 00:22:34.748779 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9371 00:22:34.751725 ELOG: NV offset 0x57f000 size 0x1000
9372 00:22:34.758546 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9373 00:22:34.765203 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9374 00:22:34.768217 ELOG: Event(17) added with size 13 at 2024-06-21 00:22:34 UTC
9375 00:22:34.775084 out: cmd=0x121: 03 db 21 01 00 00 00 00
9376 00:22:34.778334 in-header: 03 0f 00 00 2c 00 00 00
9377 00:22:34.791597 in-data: 71 b6 69 2c 23 06 00 00 0a 00 00 00 06 80 00 00 b3 02 32 2c 06 80 00 00 a3 9b 33 2c 06 80 00 00 9c 46 35 2c 06 80 00 00 ff 34 69 2c
9378 00:22:34.795254 ELOG: Event(A1) added with size 10 at 2024-06-21 00:22:34 UTC
9379 00:22:34.801696 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9380 00:22:34.808106 ELOG: Event(A0) added with size 9 at 2024-06-21 00:22:34 UTC
9381 00:22:34.811606 elog_add_boot_reason: Logged dev mode boot
9382 00:22:34.817852 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9383 00:22:34.817951 Finalize devices...
9384 00:22:34.821574 Devices finalized
9385 00:22:34.824672 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9386 00:22:34.828512 Writing coreboot table at 0xffe64000
9387 00:22:34.834634 0. 000000000010a000-0000000000113fff: RAMSTAGE
9388 00:22:34.837762 1. 0000000040000000-00000000400fffff: RAM
9389 00:22:34.841032 2. 0000000040100000-000000004032afff: RAMSTAGE
9390 00:22:34.845100 3. 000000004032b000-00000000545fffff: RAM
9391 00:22:34.847886 4. 0000000054600000-000000005465ffff: BL31
9392 00:22:34.851363 5. 0000000054660000-00000000ffe63fff: RAM
9393 00:22:34.858375 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9394 00:22:34.861157 7. 0000000100000000-000000023fffffff: RAM
9395 00:22:34.864810 Passing 5 GPIOs to payload:
9396 00:22:34.868235 NAME | PORT | POLARITY | VALUE
9397 00:22:34.874352 EC in RW | 0x000000aa | low | undefined
9398 00:22:34.878339 EC interrupt | 0x00000005 | low | undefined
9399 00:22:34.881289 TPM interrupt | 0x000000ab | high | undefined
9400 00:22:34.888127 SD card detect | 0x00000011 | high | undefined
9401 00:22:34.891167 speaker enable | 0x00000093 | high | undefined
9402 00:22:34.894265 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9403 00:22:34.897998 in-header: 03 f9 00 00 02 00 00 00
9404 00:22:34.901084 in-data: 02 00
9405 00:22:34.904654 ADC[4]: Raw value=899114 ID=7
9406 00:22:34.904733 ADC[3]: Raw value=213336 ID=1
9407 00:22:34.908002 RAM Code: 0x71
9408 00:22:34.911143 ADC[6]: Raw value=74557 ID=0
9409 00:22:34.911253 ADC[5]: Raw value=212229 ID=1
9410 00:22:34.914313 SKU Code: 0x1
9411 00:22:34.921448 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ea54
9412 00:22:34.921553 coreboot table: 964 bytes.
9413 00:22:34.924340 IMD ROOT 0. 0xfffff000 0x00001000
9414 00:22:34.927697 IMD SMALL 1. 0xffffe000 0x00001000
9415 00:22:34.931563 RO MCACHE 2. 0xffffc000 0x00001104
9416 00:22:34.934609 CONSOLE 3. 0xfff7c000 0x00080000
9417 00:22:34.937786 FMAP 4. 0xfff7b000 0x00000452
9418 00:22:34.941080 TIME STAMP 5. 0xfff7a000 0x00000910
9419 00:22:34.944765 VBOOT WORK 6. 0xfff66000 0x00014000
9420 00:22:34.947783 RAMOOPS 7. 0xffe66000 0x00100000
9421 00:22:34.951019 COREBOOT 8. 0xffe64000 0x00002000
9422 00:22:34.954755 IMD small region:
9423 00:22:34.957878 IMD ROOT 0. 0xffffec00 0x00000400
9424 00:22:34.961326 VPD 1. 0xffffeb80 0x0000006c
9425 00:22:34.964950 MMC STATUS 2. 0xffffeb60 0x00000004
9426 00:22:34.967851 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9427 00:22:34.971583 Probing TPM: done!
9428 00:22:34.974554 Connected to device vid:did:rid of 1ae0:0028:00
9429 00:22:34.985127 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9430 00:22:34.988595 Initialized TPM device CR50 revision 0
9431 00:22:34.991712 Checking cr50 for pending updates
9432 00:22:34.995751 Reading cr50 TPM mode
9433 00:22:35.004564 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9434 00:22:35.010917 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9435 00:22:35.051066 read SPI 0x3990ec 0x4f1b0: 34857 us, 9295 KB/s, 74.360 Mbps
9436 00:22:35.054382 Checking segment from ROM address 0x40100000
9437 00:22:35.058208 Checking segment from ROM address 0x4010001c
9438 00:22:35.064669 Loading segment from ROM address 0x40100000
9439 00:22:35.064747 code (compression=0)
9440 00:22:35.071328 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9441 00:22:35.081608 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9442 00:22:35.081692 it's not compressed!
9443 00:22:35.088293 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9444 00:22:35.091152 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9445 00:22:35.111582 Loading segment from ROM address 0x4010001c
9446 00:22:35.111666 Entry Point 0x80000000
9447 00:22:35.114991 Loaded segments
9448 00:22:35.118620 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9449 00:22:35.125230 Jumping to boot code at 0x80000000(0xffe64000)
9450 00:22:35.131880 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9451 00:22:35.138823 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9452 00:22:35.145796 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9453 00:22:35.149813 Checking segment from ROM address 0x40100000
9454 00:22:35.152998 Checking segment from ROM address 0x4010001c
9455 00:22:35.159583 Loading segment from ROM address 0x40100000
9456 00:22:35.159659 code (compression=1)
9457 00:22:35.166298 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9458 00:22:35.176032 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9459 00:22:35.176146 using LZMA
9460 00:22:35.184441 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9461 00:22:35.191410 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9462 00:22:35.194438 Loading segment from ROM address 0x4010001c
9463 00:22:35.194542 Entry Point 0x54601000
9464 00:22:35.198105 Loaded segments
9465 00:22:35.201323 NOTICE: MT8192 bl31_setup
9466 00:22:35.208021 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9467 00:22:35.211556 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9468 00:22:35.214579 WARNING: region 0:
9469 00:22:35.218447 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9470 00:22:35.218551 WARNING: region 1:
9471 00:22:35.224706 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9472 00:22:35.224844 WARNING: region 2:
9473 00:22:35.231521 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9474 00:22:35.234830 WARNING: region 3:
9475 00:22:35.238396 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9476 00:22:35.241666 WARNING: region 4:
9477 00:22:35.244955 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9478 00:22:35.248199 WARNING: region 5:
9479 00:22:35.252021 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9480 00:22:35.255257 WARNING: region 6:
9481 00:22:35.258490 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 00:22:35.258568 WARNING: region 7:
9483 00:22:35.265268 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9484 00:22:35.271772 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9485 00:22:35.274755 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9486 00:22:35.278725 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9487 00:22:35.281896 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9488 00:22:35.288533 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9489 00:22:35.292222 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9490 00:22:35.298567 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9491 00:22:35.301952 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9492 00:22:35.304940 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9493 00:22:35.311778 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9494 00:22:35.315533 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9495 00:22:35.318397 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9496 00:22:35.325358 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9497 00:22:35.328574 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9498 00:22:35.335612 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9499 00:22:35.338856 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9500 00:22:35.342308 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9501 00:22:35.349044 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9502 00:22:35.352037 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9503 00:22:35.355052 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9504 00:22:35.362074 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9505 00:22:35.365329 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9506 00:22:35.372315 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9507 00:22:35.375627 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9508 00:22:35.378782 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9509 00:22:35.385674 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9510 00:22:35.388882 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9511 00:22:35.392276 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9512 00:22:35.399191 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9513 00:22:35.402522 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9514 00:22:35.408915 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9515 00:22:35.412284 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9516 00:22:35.415778 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9517 00:22:35.418775 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9518 00:22:35.425585 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9519 00:22:35.429279 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9520 00:22:35.432357 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9521 00:22:35.435584 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9522 00:22:35.442420 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9523 00:22:35.446185 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9524 00:22:35.449132 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9525 00:22:35.452338 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9526 00:22:35.459149 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9527 00:22:35.462521 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9528 00:22:35.465763 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9529 00:22:35.469616 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9530 00:22:35.475902 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9531 00:22:35.479658 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9532 00:22:35.482791 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9533 00:22:35.489715 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9534 00:22:35.492785 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9535 00:22:35.499772 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9536 00:22:35.502777 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9537 00:22:35.505998 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9538 00:22:35.513020 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9539 00:22:35.516033 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9540 00:22:35.523015 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9541 00:22:35.526015 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9542 00:22:35.529540 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9543 00:22:35.536608 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9544 00:22:35.539552 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9545 00:22:35.546549 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9546 00:22:35.549651 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9547 00:22:35.556468 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9548 00:22:35.559610 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9549 00:22:35.566413 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9550 00:22:35.569603 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9551 00:22:35.573588 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9552 00:22:35.579913 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9553 00:22:35.583133 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9554 00:22:35.590282 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9555 00:22:35.593502 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9556 00:22:35.596802 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9557 00:22:35.603069 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9558 00:22:35.606806 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9559 00:22:35.613533 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9560 00:22:35.616666 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9561 00:22:35.623410 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9562 00:22:35.627002 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9563 00:22:35.630103 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9564 00:22:35.636629 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9565 00:22:35.640379 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9566 00:22:35.646961 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9567 00:22:35.650574 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9568 00:22:35.657361 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9569 00:22:35.660337 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9570 00:22:35.663999 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9571 00:22:35.670352 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9572 00:22:35.674061 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9573 00:22:35.680559 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9574 00:22:35.683736 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9575 00:22:35.687447 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9576 00:22:35.693827 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9577 00:22:35.697197 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9578 00:22:35.703943 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9579 00:22:35.707573 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9580 00:22:35.710603 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9581 00:22:35.717510 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9582 00:22:35.720734 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9583 00:22:35.723974 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9584 00:22:35.727155 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9585 00:22:35.734312 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9586 00:22:35.737483 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9587 00:22:35.743867 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9588 00:22:35.747579 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9589 00:22:35.750771 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9590 00:22:35.757626 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9591 00:22:35.761307 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9592 00:22:35.767834 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9593 00:22:35.770931 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9594 00:22:35.774700 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9595 00:22:35.781477 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9596 00:22:35.784517 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9597 00:22:35.790977 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9598 00:22:35.794641 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9599 00:22:35.797650 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9600 00:22:35.800874 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9601 00:22:35.807593 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9602 00:22:35.811250 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9603 00:22:35.814301 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9604 00:22:35.821024 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9605 00:22:35.824051 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9606 00:22:35.827878 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9607 00:22:35.831086 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9608 00:22:35.837863 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9609 00:22:35.841275 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9610 00:22:35.844529 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9611 00:22:35.851198 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9612 00:22:35.854530 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9613 00:22:35.861262 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9614 00:22:35.864338 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9615 00:22:35.867847 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9616 00:22:35.874801 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9617 00:22:35.878498 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9618 00:22:35.884497 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9619 00:22:35.888303 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9620 00:22:35.891283 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9621 00:22:35.898275 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9622 00:22:35.901599 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9623 00:22:35.904742 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9624 00:22:35.911697 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9625 00:22:35.914756 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9626 00:22:35.921973 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9627 00:22:35.924862 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9628 00:22:35.928550 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9629 00:22:35.935086 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9630 00:22:35.938809 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9631 00:22:35.941842 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9632 00:22:35.948408 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9633 00:22:35.951899 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9634 00:22:35.958765 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9635 00:22:35.961897 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9636 00:22:35.965058 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9637 00:22:35.971785 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9638 00:22:35.975297 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9639 00:22:35.978937 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9640 00:22:35.985143 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9641 00:22:35.988923 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9642 00:22:35.992420 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9643 00:22:35.998762 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9644 00:22:36.002422 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9645 00:22:36.008693 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9646 00:22:36.012380 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9647 00:22:36.015584 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9648 00:22:36.022295 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9649 00:22:36.025683 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9650 00:22:36.032213 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9651 00:22:36.035780 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9652 00:22:36.039077 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9653 00:22:36.045706 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9654 00:22:36.048647 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9655 00:22:36.055945 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9656 00:22:36.058920 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9657 00:22:36.062493 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9658 00:22:36.068683 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9659 00:22:36.072482 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9660 00:22:36.075567 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9661 00:22:36.082383 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9662 00:22:36.085470 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9663 00:22:36.092368 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9664 00:22:36.095761 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9665 00:22:36.098639 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9666 00:22:36.105697 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9667 00:22:36.109069 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9668 00:22:36.115365 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9669 00:22:36.119058 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9670 00:22:36.122201 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9671 00:22:36.129034 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9672 00:22:36.132012 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9673 00:22:36.139226 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9674 00:22:36.142238 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9675 00:22:36.145472 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9676 00:22:36.152280 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9677 00:22:36.155329 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9678 00:22:36.162327 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9679 00:22:36.165851 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9680 00:22:36.168826 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9681 00:22:36.175740 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9682 00:22:36.178807 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9683 00:22:36.185471 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9684 00:22:36.188553 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9685 00:22:36.192126 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9686 00:22:36.198852 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9687 00:22:36.202423 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9688 00:22:36.208755 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9689 00:22:36.212356 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9690 00:22:36.219048 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9691 00:22:36.221918 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9692 00:22:36.225641 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9693 00:22:36.232365 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9694 00:22:36.235422 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9695 00:22:36.241943 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9696 00:22:36.245217 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9697 00:22:36.248397 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9698 00:22:36.255126 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9699 00:22:36.258811 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9700 00:22:36.265215 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9701 00:22:36.268722 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9702 00:22:36.275563 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9703 00:22:36.278551 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9704 00:22:36.281630 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9705 00:22:36.288598 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9706 00:22:36.291550 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9707 00:22:36.298505 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9708 00:22:36.301634 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9709 00:22:36.305557 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9710 00:22:36.312384 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9711 00:22:36.315238 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9712 00:22:36.321899 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9713 00:22:36.325428 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9714 00:22:36.328507 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9715 00:22:36.331734 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9716 00:22:36.335112 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9717 00:22:36.341840 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9718 00:22:36.345281 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9719 00:22:36.348197 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9720 00:22:36.355233 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9721 00:22:36.358318 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9722 00:22:36.362024 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9723 00:22:36.368318 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9724 00:22:36.372246 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9725 00:22:36.378357 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9726 00:22:36.382141 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9727 00:22:36.385146 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9728 00:22:36.391976 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9729 00:22:36.395696 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9730 00:22:36.398818 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9731 00:22:36.405691 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9732 00:22:36.408512 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9733 00:22:36.412350 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9734 00:22:36.418605 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9735 00:22:36.421920 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9736 00:22:36.428952 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9737 00:22:36.432019 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9738 00:22:36.435543 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9739 00:22:36.441839 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9740 00:22:36.445756 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9741 00:22:36.448935 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9742 00:22:36.455527 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9743 00:22:36.459103 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9744 00:22:36.462250 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9745 00:22:36.469141 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9746 00:22:36.472281 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9747 00:22:36.475881 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9748 00:22:36.482239 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9749 00:22:36.485515 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9750 00:22:36.492107 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9751 00:22:36.495847 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9752 00:22:36.498567 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9753 00:22:36.502362 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9754 00:22:36.508428 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9755 00:22:36.511987 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9756 00:22:36.515635 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9757 00:22:36.518731 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9758 00:22:36.525611 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9759 00:22:36.528544 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9760 00:22:36.532196 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9761 00:22:36.535298 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9762 00:22:36.542185 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9763 00:22:36.545334 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9764 00:22:36.548590 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9765 00:22:36.551581 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9766 00:22:36.558600 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9767 00:22:36.561730 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9768 00:22:36.568761 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9769 00:22:36.571611 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9770 00:22:36.578481 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9771 00:22:36.581627 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9772 00:22:36.584740 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9773 00:22:36.591637 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9774 00:22:36.594817 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9775 00:22:36.601423 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9776 00:22:36.605024 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9777 00:22:36.608182 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9778 00:22:36.615027 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9779 00:22:36.618692 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9780 00:22:36.625078 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9781 00:22:36.628285 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9782 00:22:36.631972 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9783 00:22:36.638604 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9784 00:22:36.641742 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9785 00:22:36.648429 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9786 00:22:36.652184 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9787 00:22:36.655365 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9788 00:22:36.661704 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9789 00:22:36.664968 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9790 00:22:36.671519 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9791 00:22:36.675074 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9792 00:22:36.678760 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9793 00:22:36.685342 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9794 00:22:36.688737 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9795 00:22:36.695219 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9796 00:22:36.698337 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9797 00:22:36.702097 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9798 00:22:36.708459 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9799 00:22:36.711921 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9800 00:22:36.718417 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9801 00:22:36.721769 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9802 00:22:36.725503 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9803 00:22:36.731691 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9804 00:22:36.735589 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9805 00:22:36.741808 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9806 00:22:36.745332 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9807 00:22:36.748644 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9808 00:22:36.755034 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9809 00:22:36.758371 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9810 00:22:36.765199 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9811 00:22:36.768497 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9812 00:22:36.771617 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9813 00:22:36.778438 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9814 00:22:36.781905 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9815 00:22:36.788545 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9816 00:22:36.792088 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9817 00:22:36.795047 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9818 00:22:36.801800 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9819 00:22:36.805127 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9820 00:22:36.812105 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9821 00:22:36.815171 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9822 00:22:36.818781 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9823 00:22:36.825511 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9824 00:22:36.828480 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9825 00:22:36.834975 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9826 00:22:36.838765 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9827 00:22:36.842119 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9828 00:22:36.848728 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9829 00:22:36.851959 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9830 00:22:36.858956 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9831 00:22:36.861847 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9832 00:22:36.865221 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9833 00:22:36.871885 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9834 00:22:36.875049 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9835 00:22:36.882041 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9836 00:22:36.885452 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9837 00:22:36.888389 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9838 00:22:36.895309 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9839 00:22:36.898988 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9840 00:22:36.905047 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9841 00:22:36.908543 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9842 00:22:36.915520 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9843 00:22:36.918420 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9844 00:22:36.925153 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9845 00:22:36.928264 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9846 00:22:36.932127 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9847 00:22:36.938446 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9848 00:22:36.941801 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9849 00:22:36.948251 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9850 00:22:36.952090 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9851 00:22:36.958533 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9852 00:22:36.961768 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9853 00:22:36.964816 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9854 00:22:36.971808 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9855 00:22:36.975437 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9856 00:22:36.981636 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9857 00:22:36.985252 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9858 00:22:36.991515 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9859 00:22:36.995046 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9860 00:22:36.998376 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9861 00:22:37.005035 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9862 00:22:37.008532 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9863 00:22:37.015131 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9864 00:22:37.018258 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9865 00:22:37.025075 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9866 00:22:37.028124 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9867 00:22:37.031692 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9868 00:22:37.037941 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9869 00:22:37.041597 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9870 00:22:37.047968 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9871 00:22:37.051470 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9872 00:22:37.058266 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9873 00:22:37.061348 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9874 00:22:37.064954 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9875 00:22:37.071246 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9876 00:22:37.074862 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9877 00:22:37.081115 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9878 00:22:37.084705 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9879 00:22:37.091445 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9880 00:22:37.094589 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9881 00:22:37.098355 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9882 00:22:37.104958 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9883 00:22:37.108378 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9884 00:22:37.114678 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9885 00:22:37.117915 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9886 00:22:37.121331 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9887 00:22:37.127951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9888 00:22:37.131606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9889 00:22:37.138423 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9890 00:22:37.141444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9891 00:22:37.148123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9892 00:22:37.151259 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9893 00:22:37.157891 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9894 00:22:37.161517 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9895 00:22:37.168176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9896 00:22:37.171806 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9897 00:22:37.177937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9898 00:22:37.181648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9899 00:22:37.188081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9900 00:22:37.191472 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9901 00:22:37.194578 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9902 00:22:37.201558 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9903 00:22:37.204704 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9904 00:22:37.211010 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9905 00:22:37.214622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9906 00:22:37.221202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9907 00:22:37.224339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9908 00:22:37.231347 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9909 00:22:37.234600 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9910 00:22:37.241224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9911 00:22:37.244314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9912 00:22:37.251247 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9913 00:22:37.254250 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9914 00:22:37.261108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9915 00:22:37.264252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9916 00:22:37.271308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9917 00:22:37.274789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9918 00:22:37.280818 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9919 00:22:37.280896 INFO: [APUAPC] vio 0
9920 00:22:37.287833 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9921 00:22:37.291628 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9922 00:22:37.294677 INFO: [APUAPC] D0_APC_0: 0x400510
9923 00:22:37.298280 INFO: [APUAPC] D0_APC_1: 0x0
9924 00:22:37.301385 INFO: [APUAPC] D0_APC_2: 0x1540
9925 00:22:37.304693 INFO: [APUAPC] D0_APC_3: 0x0
9926 00:22:37.307732 INFO: [APUAPC] D1_APC_0: 0xffffffff
9927 00:22:37.311670 INFO: [APUAPC] D1_APC_1: 0xffffffff
9928 00:22:37.314701 INFO: [APUAPC] D1_APC_2: 0x3fffff
9929 00:22:37.317609 INFO: [APUAPC] D1_APC_3: 0x0
9930 00:22:37.321269 INFO: [APUAPC] D2_APC_0: 0xffffffff
9931 00:22:37.325018 INFO: [APUAPC] D2_APC_1: 0xffffffff
9932 00:22:37.328111 INFO: [APUAPC] D2_APC_2: 0x3fffff
9933 00:22:37.331363 INFO: [APUAPC] D2_APC_3: 0x0
9934 00:22:37.334375 INFO: [APUAPC] D3_APC_0: 0xffffffff
9935 00:22:37.338117 INFO: [APUAPC] D3_APC_1: 0xffffffff
9936 00:22:37.341150 INFO: [APUAPC] D3_APC_2: 0x3fffff
9937 00:22:37.341253 INFO: [APUAPC] D3_APC_3: 0x0
9938 00:22:37.344490 INFO: [APUAPC] D4_APC_0: 0xffffffff
9939 00:22:37.351430 INFO: [APUAPC] D4_APC_1: 0xffffffff
9940 00:22:37.354378 INFO: [APUAPC] D4_APC_2: 0x3fffff
9941 00:22:37.354454 INFO: [APUAPC] D4_APC_3: 0x0
9942 00:22:37.357858 INFO: [APUAPC] D5_APC_0: 0xffffffff
9943 00:22:37.361011 INFO: [APUAPC] D5_APC_1: 0xffffffff
9944 00:22:37.364302 INFO: [APUAPC] D5_APC_2: 0x3fffff
9945 00:22:37.368035 INFO: [APUAPC] D5_APC_3: 0x0
9946 00:22:37.371257 INFO: [APUAPC] D6_APC_0: 0xffffffff
9947 00:22:37.374325 INFO: [APUAPC] D6_APC_1: 0xffffffff
9948 00:22:37.378160 INFO: [APUAPC] D6_APC_2: 0x3fffff
9949 00:22:37.381254 INFO: [APUAPC] D6_APC_3: 0x0
9950 00:22:37.384601 INFO: [APUAPC] D7_APC_0: 0xffffffff
9951 00:22:37.388299 INFO: [APUAPC] D7_APC_1: 0xffffffff
9952 00:22:37.391160 INFO: [APUAPC] D7_APC_2: 0x3fffff
9953 00:22:37.394850 INFO: [APUAPC] D7_APC_3: 0x0
9954 00:22:37.397856 INFO: [APUAPC] D8_APC_0: 0xffffffff
9955 00:22:37.401485 INFO: [APUAPC] D8_APC_1: 0xffffffff
9956 00:22:37.404549 INFO: [APUAPC] D8_APC_2: 0x3fffff
9957 00:22:37.408307 INFO: [APUAPC] D8_APC_3: 0x0
9958 00:22:37.411631 INFO: [APUAPC] D9_APC_0: 0xffffffff
9959 00:22:37.414986 INFO: [APUAPC] D9_APC_1: 0xffffffff
9960 00:22:37.418170 INFO: [APUAPC] D9_APC_2: 0x3fffff
9961 00:22:37.421275 INFO: [APUAPC] D9_APC_3: 0x0
9962 00:22:37.424965 INFO: [APUAPC] D10_APC_0: 0xffffffff
9963 00:22:37.427991 INFO: [APUAPC] D10_APC_1: 0xffffffff
9964 00:22:37.431578 INFO: [APUAPC] D10_APC_2: 0x3fffff
9965 00:22:37.434822 INFO: [APUAPC] D10_APC_3: 0x0
9966 00:22:37.437899 INFO: [APUAPC] D11_APC_0: 0xffffffff
9967 00:22:37.441187 INFO: [APUAPC] D11_APC_1: 0xffffffff
9968 00:22:37.444941 INFO: [APUAPC] D11_APC_2: 0x3fffff
9969 00:22:37.447978 INFO: [APUAPC] D11_APC_3: 0x0
9970 00:22:37.451803 INFO: [APUAPC] D12_APC_0: 0xffffffff
9971 00:22:37.454772 INFO: [APUAPC] D12_APC_1: 0xffffffff
9972 00:22:37.458481 INFO: [APUAPC] D12_APC_2: 0x3fffff
9973 00:22:37.461376 INFO: [APUAPC] D12_APC_3: 0x0
9974 00:22:37.465075 INFO: [APUAPC] D13_APC_0: 0xffffffff
9975 00:22:37.468043 INFO: [APUAPC] D13_APC_1: 0xffffffff
9976 00:22:37.471304 INFO: [APUAPC] D13_APC_2: 0x3fffff
9977 00:22:37.475112 INFO: [APUAPC] D13_APC_3: 0x0
9978 00:22:37.478204 INFO: [APUAPC] D14_APC_0: 0xffffffff
9979 00:22:37.481326 INFO: [APUAPC] D14_APC_1: 0xffffffff
9980 00:22:37.485123 INFO: [APUAPC] D14_APC_2: 0x3fffff
9981 00:22:37.488361 INFO: [APUAPC] D14_APC_3: 0x0
9982 00:22:37.491565 INFO: [APUAPC] D15_APC_0: 0xffffffff
9983 00:22:37.495059 INFO: [APUAPC] D15_APC_1: 0xffffffff
9984 00:22:37.497935 INFO: [APUAPC] D15_APC_2: 0x3fffff
9985 00:22:37.501424 INFO: [APUAPC] D15_APC_3: 0x0
9986 00:22:37.504778 INFO: [APUAPC] APC_CON: 0x4
9987 00:22:37.508187 INFO: [NOCDAPC] D0_APC_0: 0x0
9988 00:22:37.508287 INFO: [NOCDAPC] D0_APC_1: 0x0
9989 00:22:37.511520 INFO: [NOCDAPC] D1_APC_0: 0x0
9990 00:22:37.515016 INFO: [NOCDAPC] D1_APC_1: 0xfff
9991 00:22:37.518184 INFO: [NOCDAPC] D2_APC_0: 0x0
9992 00:22:37.521387 INFO: [NOCDAPC] D2_APC_1: 0xfff
9993 00:22:37.525151 INFO: [NOCDAPC] D3_APC_0: 0x0
9994 00:22:37.528247 INFO: [NOCDAPC] D3_APC_1: 0xfff
9995 00:22:37.531879 INFO: [NOCDAPC] D4_APC_0: 0x0
9996 00:22:37.534806 INFO: [NOCDAPC] D4_APC_1: 0xfff
9997 00:22:37.534882 INFO: [NOCDAPC] D5_APC_0: 0x0
9998 00:22:37.538291 INFO: [NOCDAPC] D5_APC_1: 0xfff
9999 00:22:37.541837 INFO: [NOCDAPC] D6_APC_0: 0x0
10000 00:22:37.544936 INFO: [NOCDAPC] D6_APC_1: 0xfff
10001 00:22:37.548202 INFO: [NOCDAPC] D7_APC_0: 0x0
10002 00:22:37.551686 INFO: [NOCDAPC] D7_APC_1: 0xfff
10003 00:22:37.554798 INFO: [NOCDAPC] D8_APC_0: 0x0
10004 00:22:37.558484 INFO: [NOCDAPC] D8_APC_1: 0xfff
10005 00:22:37.561650 INFO: [NOCDAPC] D9_APC_0: 0x0
10006 00:22:37.565294 INFO: [NOCDAPC] D9_APC_1: 0xfff
10007 00:22:37.568234 INFO: [NOCDAPC] D10_APC_0: 0x0
10008 00:22:37.571622 INFO: [NOCDAPC] D10_APC_1: 0xfff
10009 00:22:37.571698 INFO: [NOCDAPC] D11_APC_0: 0x0
10010 00:22:37.575013 INFO: [NOCDAPC] D11_APC_1: 0xfff
10011 00:22:37.578168 INFO: [NOCDAPC] D12_APC_0: 0x0
10012 00:22:37.581877 INFO: [NOCDAPC] D12_APC_1: 0xfff
10013 00:22:37.585005 INFO: [NOCDAPC] D13_APC_0: 0x0
10014 00:22:37.588184 INFO: [NOCDAPC] D13_APC_1: 0xfff
10015 00:22:37.591919 INFO: [NOCDAPC] D14_APC_0: 0x0
10016 00:22:37.594905 INFO: [NOCDAPC] D14_APC_1: 0xfff
10017 00:22:37.598775 INFO: [NOCDAPC] D15_APC_0: 0x0
10018 00:22:37.601853 INFO: [NOCDAPC] D15_APC_1: 0xfff
10019 00:22:37.604938 INFO: [NOCDAPC] APC_CON: 0x4
10020 00:22:37.607983 INFO: [APUAPC] set_apusys_apc done
10021 00:22:37.611499 INFO: [DEVAPC] devapc_init done
10022 00:22:37.614824 INFO: GICv3 without legacy support detected.
10023 00:22:37.618108 INFO: ARM GICv3 driver initialized in EL3
10024 00:22:37.621343 INFO: Maximum SPI INTID supported: 639
10025 00:22:37.624683 INFO: BL31: Initializing runtime services
10026 00:22:37.631786 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10027 00:22:37.634869 INFO: SPM: enable CPC mode
10028 00:22:37.641569 INFO: mcdi ready for mcusys-off-idle and system suspend
10029 00:22:37.645055 INFO: BL31: Preparing for EL3 exit to normal world
10030 00:22:37.648219 INFO: Entry point address = 0x80000000
10031 00:22:37.651562 INFO: SPSR = 0x8
10032 00:22:37.656156
10033 00:22:37.656233
10034 00:22:37.656293
10035 00:22:37.657066 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10036 00:22:37.657159 start: 2.2.4 bootloader-commands (timeout 00:04:24) [common]
10037 00:22:37.657239 Setting prompt string to ['asurada:']
10038 00:22:37.657310 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:24)
10039 00:22:37.659361 Starting depthcharge on Spherion...
10040 00:22:37.659431
10041 00:22:37.659487 Wipe memory regions:
10042 00:22:37.659541
10043 00:22:37.662570 [0x00000040000000, 0x00000054600000)
10044 00:22:37.785178
10045 00:22:37.785285 [0x00000054660000, 0x00000080000000)
10046 00:22:38.045800
10047 00:22:38.045919 [0x000000821a7280, 0x000000ffe64000)
10048 00:22:38.790694
10049 00:22:38.790814 [0x00000100000000, 0x00000240000000)
10050 00:22:40.680816
10051 00:22:40.683693 Initializing XHCI USB controller at 0x11200000.
10052 00:22:41.722081
10053 00:22:41.724997 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10054 00:22:41.725079
10055 00:22:41.725139
10056 00:22:41.725406 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10058 00:22:41.825695 asurada: tftpboot 192.168.201.1 14479176/tftp-deploy-325ei7s0/kernel/image.itb 14479176/tftp-deploy-325ei7s0/kernel/cmdline
10059 00:22:41.825881 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10060 00:22:41.825960 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10061 00:22:41.829926 tftpboot 192.168.201.1 14479176/tftp-deploy-325ei7s0/kernel/image.itp-deploy-325ei7s0/kernel/cmdline
10062 00:22:41.830045
10063 00:22:41.830105 Waiting for link
10064 00:22:41.988312
10065 00:22:41.988461 R8152: Initializing
10066 00:22:41.988520
10067 00:22:41.991635 Version 6 (ocp_data = 5c30)
10068 00:22:41.991710
10069 00:22:41.994707 R8152: Done initializing
10070 00:22:41.994782
10071 00:22:41.994841 Adding net device
10072 00:22:44.026379
10073 00:22:44.026496 done.
10074 00:22:44.026556
10075 00:22:44.026611 MAC: 00:24:32:30:78:52
10076 00:22:44.026672
10077 00:22:44.029972 Sending DHCP discover... done.
10078 00:22:44.030072
10079 00:22:47.085118 Waiting for reply... done.
10080 00:22:47.085238
10081 00:22:47.085345 Sending DHCP request... done.
10082 00:22:47.088464
10083 00:22:47.088554 Waiting for reply... done.
10084 00:22:47.088611
10085 00:22:47.092368 My ip is 192.168.201.14
10086 00:22:47.092457
10087 00:22:47.095339 The DHCP server ip is 192.168.201.1
10088 00:22:47.095413
10089 00:22:47.098284 TFTP server IP predefined by user: 192.168.201.1
10090 00:22:47.098374
10091 00:22:47.105273 Bootfile predefined by user: 14479176/tftp-deploy-325ei7s0/kernel/image.itb
10092 00:22:47.105364
10093 00:22:47.108551 Sending tftp read request... done.
10094 00:22:47.108622
10095 00:22:47.111960 Waiting for the transfer...
10096 00:22:47.112038
10097 00:22:47.659391 00000000 ################################################################
10098 00:22:47.659517
10099 00:22:48.197410 00080000 ################################################################
10100 00:22:48.197538
10101 00:22:48.729471 00100000 ################################################################
10102 00:22:48.729587
10103 00:22:49.270257 00180000 ################################################################
10104 00:22:49.270377
10105 00:22:49.817035 00200000 ################################################################
10106 00:22:49.817245
10107 00:22:50.366633 00280000 ################################################################
10108 00:22:50.366791
10109 00:22:50.914275 00300000 ################################################################
10110 00:22:50.914403
10111 00:22:51.456716 00380000 ################################################################
10112 00:22:51.456841
10113 00:22:52.005629 00400000 ################################################################
10114 00:22:52.005742
10115 00:22:52.558521 00480000 ################################################################
10116 00:22:52.558701
10117 00:22:53.095924 00500000 ################################################################
10118 00:22:53.096060
10119 00:22:53.646157 00580000 ################################################################
10120 00:22:53.646292
10121 00:22:54.191770 00600000 ################################################################
10122 00:22:54.191920
10123 00:22:54.731928 00680000 ################################################################
10124 00:22:54.732069
10125 00:22:55.296907 00700000 ################################################################
10126 00:22:55.297030
10127 00:22:55.842427 00780000 ################################################################
10128 00:22:55.842545
10129 00:22:56.392295 00800000 ################################################################
10130 00:22:56.392406
10131 00:22:56.941814 00880000 ################################################################
10132 00:22:56.941937
10133 00:22:57.494326 00900000 ################################################################
10134 00:22:57.494486
10135 00:22:58.039663 00980000 ################################################################
10136 00:22:58.039776
10137 00:22:58.586465 00a00000 ################################################################
10138 00:22:58.586583
10139 00:22:59.153795 00a80000 ################################################################
10140 00:22:59.153928
10141 00:22:59.718102 00b00000 ################################################################
10142 00:22:59.718226
10143 00:23:00.272516 00b80000 ################################################################
10144 00:23:00.272630
10145 00:23:00.829281 00c00000 ################################################################
10146 00:23:00.829389
10147 00:23:01.378561 00c80000 ################################################################
10148 00:23:01.378700
10149 00:23:01.937768 00d00000 ################################################################
10150 00:23:01.937913
10151 00:23:02.490123 00d80000 ################################################################
10152 00:23:02.490244
10153 00:23:03.042806 00e00000 ################################################################
10154 00:23:03.042970
10155 00:23:03.582047 00e80000 ################################################################
10156 00:23:03.582180
10157 00:23:04.131754 00f00000 ################################################################
10158 00:23:04.131919
10159 00:23:04.700900 00f80000 ################################################################
10160 00:23:04.701040
10161 00:23:05.259155 01000000 ################################################################
10162 00:23:05.259300
10163 00:23:05.807640 01080000 ################################################################
10164 00:23:05.807792
10165 00:23:06.350829 01100000 ################################################################
10166 00:23:06.350944
10167 00:23:06.908343 01180000 ################################################################
10168 00:23:06.908482
10169 00:23:07.475785 01200000 ################################################################
10170 00:23:07.475935
10171 00:23:08.026270 01280000 ################################################################
10172 00:23:08.026417
10173 00:23:08.589040 01300000 ################################################################
10174 00:23:08.589158
10175 00:23:09.144644 01380000 ################################################################
10176 00:23:09.144767
10177 00:23:09.691147 01400000 ################################################################
10178 00:23:09.691274
10179 00:23:10.239221 01480000 ################################################################
10180 00:23:10.239348
10181 00:23:10.791951 01500000 ################################################################
10182 00:23:10.792128
10183 00:23:11.340955 01580000 ################################################################
10184 00:23:11.341106
10185 00:23:11.887002 01600000 ################################################################
10186 00:23:11.887129
10187 00:23:12.435039 01680000 ################################################################
10188 00:23:12.435154
10189 00:23:12.991919 01700000 ################################################################
10190 00:23:12.992064
10191 00:23:13.534442 01780000 ################################################################
10192 00:23:13.534570
10193 00:23:14.079199 01800000 ################################################################
10194 00:23:14.079369
10195 00:23:14.630440 01880000 ################################################################
10196 00:23:14.630564
10197 00:23:15.180333 01900000 ################################################################
10198 00:23:15.180471
10199 00:23:15.729675 01980000 ################################################################
10200 00:23:15.729808
10201 00:23:16.258986 01a00000 ################################################################
10202 00:23:16.259147
10203 00:23:16.795139 01a80000 ################################################################
10204 00:23:16.795265
10205 00:23:17.330546 01b00000 ################################################################
10206 00:23:17.330685
10207 00:23:17.889643 01b80000 ################################################################
10208 00:23:17.889771
10209 00:23:18.438410 01c00000 ################################################################
10210 00:23:18.438522
10211 00:23:18.998907 01c80000 ################################################################
10212 00:23:18.999060
10213 00:23:19.561630 01d00000 ################################################################
10214 00:23:19.561763
10215 00:23:20.128565 01d80000 ################################################################
10216 00:23:20.128717
10217 00:23:20.685912 01e00000 ################################################################
10218 00:23:20.686083
10219 00:23:21.249465 01e80000 ################################################################
10220 00:23:21.249587
10221 00:23:21.797104 01f00000 ################################################################
10222 00:23:21.797229
10223 00:23:22.353094 01f80000 ################################################################
10224 00:23:22.353218
10225 00:23:22.916940 02000000 ################################################################
10226 00:23:22.917065
10227 00:23:23.471010 02080000 ################################################################
10228 00:23:23.471128
10229 00:23:24.028064 02100000 ################################################################
10230 00:23:24.028201
10231 00:23:24.575963 02180000 ################################################################
10232 00:23:24.576094
10233 00:23:25.139770 02200000 ################################################################
10234 00:23:25.139892
10235 00:23:25.699437 02280000 ################################################################
10236 00:23:25.699564
10237 00:23:26.241374 02300000 ################################################################
10238 00:23:26.241502
10239 00:23:26.798765 02380000 ################################################################
10240 00:23:26.798887
10241 00:23:27.341044 02400000 ################################################################
10242 00:23:27.341171
10243 00:23:27.870468 02480000 ################################################################
10244 00:23:27.870599
10245 00:23:28.438714 02500000 ################################################################
10246 00:23:28.438834
10247 00:23:28.999907 02580000 ################################################################
10248 00:23:29.000047
10249 00:23:29.539657 02600000 ################################################################
10250 00:23:29.539783
10251 00:23:30.096540 02680000 ################################################################
10252 00:23:30.096690
10253 00:23:30.649203 02700000 ################################################################
10254 00:23:30.649350
10255 00:23:31.214598 02780000 ################################################################
10256 00:23:31.214718
10257 00:23:31.779624 02800000 ################################################################
10258 00:23:31.779751
10259 00:23:32.328157 02880000 ################################################################
10260 00:23:32.328284
10261 00:23:32.866207 02900000 ################################################################
10262 00:23:32.866338
10263 00:23:33.397876 02980000 ################################################################
10264 00:23:33.398037
10265 00:23:33.956682 02a00000 ################################################################
10266 00:23:33.956820
10267 00:23:34.511683 02a80000 ################################################################
10268 00:23:34.511805
10269 00:23:35.053304 02b00000 ################################################################
10270 00:23:35.053442
10271 00:23:35.600829 02b80000 ################################################################
10272 00:23:35.600954
10273 00:23:36.166235 02c00000 ################################################################
10274 00:23:36.166373
10275 00:23:36.768496 02c80000 ################################################################
10276 00:23:36.768996
10277 00:23:37.378878 02d00000 ################################################################
10278 00:23:37.378993
10279 00:23:37.995555 02d80000 ################################################################
10280 00:23:37.995676
10281 00:23:38.569360 02e00000 ################################################################
10282 00:23:38.569567
10283 00:23:39.135888 02e80000 ################################################################
10284 00:23:39.136070
10285 00:23:39.722670 02f00000 ################################################################
10286 00:23:39.722814
10287 00:23:40.288596 02f80000 ################################################################
10288 00:23:40.288713
10289 00:23:40.877290 03000000 ################################################################
10290 00:23:40.877528
10291 00:23:41.495913 03080000 ################################################################
10292 00:23:41.496026
10293 00:23:42.142677 03100000 ################################################################
10294 00:23:42.143145
10295 00:23:42.801260 03180000 ################################################################
10296 00:23:42.801390
10297 00:23:43.458228 03200000 ################################################################
10298 00:23:43.458696
10299 00:23:44.044834 03280000 ################################################################
10300 00:23:44.044990
10301 00:23:44.684213 03300000 ################################################################
10302 00:23:44.684340
10303 00:23:45.168026 03380000 ################################################# done.
10304 00:23:45.171200
10305 00:23:45.171609 The bootfile was 54397014 bytes long.
10306 00:23:45.171916
10307 00:23:45.174490 Sending tftp read request... done.
10308 00:23:45.174905
10309 00:23:45.181729 Waiting for the transfer...
10310 00:23:45.182154
10311 00:23:45.182532 00000000 # done.
10312 00:23:45.182829
10313 00:23:45.188245 Command line loaded dynamically from TFTP file: 14479176/tftp-deploy-325ei7s0/kernel/cmdline
10314 00:23:45.188650
10315 00:23:45.202083 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10316 00:23:45.202496
10317 00:23:45.204832 Loading FIT.
10318 00:23:45.205217
10319 00:23:45.208302 Image ramdisk-1 has 41222833 bytes.
10320 00:23:45.208689
10321 00:23:45.211954 Image fdt-1 has 47258 bytes.
10322 00:23:45.212383
10323 00:23:45.212733 Image kernel-1 has 13124896 bytes.
10324 00:23:45.213019
10325 00:23:45.221850 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10326 00:23:45.222288
10327 00:23:45.238277 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10328 00:23:45.238721
10329 00:23:45.245321 Choosing best match conf-1 for compat google,spherion-rev2.
10330 00:23:45.249039
10331 00:23:45.253896 Connected to device vid:did:rid of 1ae0:0028:00
10332 00:23:45.261848
10333 00:23:45.265492 tpm_get_response: command 0x17b, return code 0x0
10334 00:23:45.265881
10335 00:23:45.268452 ec_init: CrosEC protocol v3 supported (256, 248)
10336 00:23:45.272460
10337 00:23:45.276215 tpm_cleanup: add release locality here.
10338 00:23:45.276605
10339 00:23:45.276964 Shutting down all USB controllers.
10340 00:23:45.279360
10341 00:23:45.279750 Removing current net device
10342 00:23:45.280050
10343 00:23:45.285797 Exiting depthcharge with code 4 at timestamp: 96980802
10344 00:23:45.286236
10345 00:23:45.289306 LZMA decompressing kernel-1 to 0x821a6718
10346 00:23:45.289695
10347 00:23:45.292850 LZMA decompressing kernel-1 to 0x40000000
10348 00:23:46.908929
10349 00:23:46.909076 jumping to kernel
10350 00:23:46.909635 end: 2.2.4 bootloader-commands (duration 00:01:09) [common]
10351 00:23:46.909743 start: 2.2.5 auto-login-action (timeout 00:03:15) [common]
10352 00:23:46.909822 Setting prompt string to ['Linux version [0-9]']
10353 00:23:46.909892 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10354 00:23:46.909965 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10355 00:23:46.991474
10356 00:23:46.994273 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10357 00:23:46.997891 start: 2.2.5.1 login-action (timeout 00:03:15) [common]
10358 00:23:46.998417 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10359 00:23:46.998756 Setting prompt string to []
10360 00:23:46.999109 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10361 00:23:46.999436 Using line separator: #'\n'#
10362 00:23:46.999704 No login prompt set.
10363 00:23:47.000048 Parsing kernel messages
10364 00:23:47.000314 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10365 00:23:47.000807 [login-action] Waiting for messages, (timeout 00:03:15)
10366 00:23:47.001121 Waiting using forced prompt support (timeout 00:01:37)
10367 00:23:47.017831 [ 0.000000] Linux version 6.1.94-cip23 (KernelCI@build-j239242-arm64-gcc-10-defconfig-arm64-chromebook-c5lwc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024
10368 00:23:47.020995 [ 0.000000] random: crng init done
10369 00:23:47.024601 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10370 00:23:47.027605 [ 0.000000] efi: UEFI not found.
10371 00:23:47.037743 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10372 00:23:47.044391 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10373 00:23:47.054127 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10374 00:23:47.064200 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10375 00:23:47.070916 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10376 00:23:47.074576 [ 0.000000] printk: bootconsole [mtk8250] enabled
10377 00:23:47.082799 [ 0.000000] NUMA: No NUMA configuration found
10378 00:23:47.089259 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10379 00:23:47.095840 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10380 00:23:47.096285 [ 0.000000] Zone ranges:
10381 00:23:47.102381 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10382 00:23:47.106093 [ 0.000000] DMA32 empty
10383 00:23:47.112644 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10384 00:23:47.116176 [ 0.000000] Movable zone start for each node
10385 00:23:47.119471 [ 0.000000] Early memory node ranges
10386 00:23:47.126214 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10387 00:23:47.132329 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10388 00:23:47.139198 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10389 00:23:47.146055 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10390 00:23:47.152780 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10391 00:23:47.159101 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10392 00:23:47.215665 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10393 00:23:47.222092 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10394 00:23:47.228705 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10395 00:23:47.231842 [ 0.000000] psci: probing for conduit method from DT.
10396 00:23:47.238590 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10397 00:23:47.241661 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10398 00:23:47.248606 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10399 00:23:47.251851 [ 0.000000] psci: SMC Calling Convention v1.2
10400 00:23:47.258665 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10401 00:23:47.262077 [ 0.000000] Detected VIPT I-cache on CPU0
10402 00:23:47.268677 [ 0.000000] CPU features: detected: GIC system register CPU interface
10403 00:23:47.275355 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10404 00:23:47.282130 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10405 00:23:47.288972 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10406 00:23:47.295598 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10407 00:23:47.302123 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10408 00:23:47.308775 [ 0.000000] alternatives: applying boot alternatives
10409 00:23:47.312258 [ 0.000000] Fallback order for Node 0: 0
10410 00:23:47.318686 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10411 00:23:47.322168 [ 0.000000] Policy zone: Normal
10412 00:23:47.338788 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10413 00:23:47.348567 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10414 00:23:47.360179 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10415 00:23:47.369900 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10416 00:23:47.376671 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10417 00:23:47.379702 <6>[ 0.000000] software IO TLB: area num 8.
10418 00:23:47.435865 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10419 00:23:47.585780 <6>[ 0.000000] Memory: 7923800K/8385536K available (18112K kernel code, 4120K rwdata, 22648K rodata, 8512K init, 616K bss, 428968K reserved, 32768K cma-reserved)
10420 00:23:47.592484 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10421 00:23:47.598766 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10422 00:23:47.602243 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10423 00:23:47.608797 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10424 00:23:47.615527 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10425 00:23:47.619180 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10426 00:23:47.628983 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10427 00:23:47.635435 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10428 00:23:47.639013 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10429 00:23:47.646577 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10430 00:23:47.650219 <6>[ 0.000000] GICv3: 608 SPIs implemented
10431 00:23:47.656328 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10432 00:23:47.659997 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10433 00:23:47.663058 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10434 00:23:47.673124 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10435 00:23:47.682898 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10436 00:23:47.696202 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10437 00:23:47.703166 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10438 00:23:47.711922 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10439 00:23:47.725504 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10440 00:23:47.732176 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10441 00:23:47.739152 <6>[ 0.009229] Console: colour dummy device 80x25
10442 00:23:47.749119 <6>[ 0.013988] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10443 00:23:47.752736 <6>[ 0.024430] pid_max: default: 32768 minimum: 301
10444 00:23:47.759256 <6>[ 0.029302] LSM: Security Framework initializing
10445 00:23:47.765951 <6>[ 0.034239] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10446 00:23:47.775695 <6>[ 0.042053] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10447 00:23:47.782498 <6>[ 0.051473] cblist_init_generic: Setting adjustable number of callback queues.
10448 00:23:47.789150 <6>[ 0.058917] cblist_init_generic: Setting shift to 3 and lim to 1.
10449 00:23:47.799399 <6>[ 0.065256] cblist_init_generic: Setting adjustable number of callback queues.
10450 00:23:47.802509 <6>[ 0.072729] cblist_init_generic: Setting shift to 3 and lim to 1.
10451 00:23:47.809130 <6>[ 0.079131] rcu: Hierarchical SRCU implementation.
10452 00:23:47.815531 <6>[ 0.084146] rcu: Max phase no-delay instances is 1000.
10453 00:23:47.819334 <6>[ 0.091203] EFI services will not be available.
10454 00:23:47.826105 <6>[ 0.096159] smp: Bringing up secondary CPUs ...
10455 00:23:47.833396 <6>[ 0.101211] Detected VIPT I-cache on CPU1
10456 00:23:47.839944 <6>[ 0.101282] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10457 00:23:47.846358 <6>[ 0.101314] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10458 00:23:47.849897 <6>[ 0.101645] Detected VIPT I-cache on CPU2
10459 00:23:47.856842 <6>[ 0.101693] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10460 00:23:47.863636 <6>[ 0.101709] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10461 00:23:47.870436 <6>[ 0.101962] Detected VIPT I-cache on CPU3
10462 00:23:47.877239 <6>[ 0.102008] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10463 00:23:47.883625 <6>[ 0.102022] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10464 00:23:47.886881 <6>[ 0.102327] CPU features: detected: Spectre-v4
10465 00:23:47.893562 <6>[ 0.102333] CPU features: detected: Spectre-BHB
10466 00:23:47.896551 <6>[ 0.102338] Detected PIPT I-cache on CPU4
10467 00:23:47.903699 <6>[ 0.102394] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10468 00:23:47.910033 <6>[ 0.102410] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10469 00:23:47.913590 <6>[ 0.102703] Detected PIPT I-cache on CPU5
10470 00:23:47.923875 <6>[ 0.102765] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10471 00:23:47.930318 <6>[ 0.102782] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10472 00:23:47.933676 <6>[ 0.103063] Detected PIPT I-cache on CPU6
10473 00:23:47.939709 <6>[ 0.103122] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10474 00:23:47.947094 <6>[ 0.103137] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10475 00:23:47.950175 <6>[ 0.103421] Detected PIPT I-cache on CPU7
10476 00:23:47.959794 <6>[ 0.103479] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10477 00:23:47.966415 <6>[ 0.103495] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10478 00:23:47.969856 <6>[ 0.103542] smp: Brought up 1 node, 8 CPUs
10479 00:23:47.973368 <6>[ 0.244992] SMP: Total of 8 processors activated.
10480 00:23:47.980006 <6>[ 0.249913] CPU features: detected: 32-bit EL0 Support
10481 00:23:47.989699 <6>[ 0.255276] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10482 00:23:47.996593 <6>[ 0.264132] CPU features: detected: Common not Private translations
10483 00:23:47.999538 <6>[ 0.270608] CPU features: detected: CRC32 instructions
10484 00:23:48.006213 <6>[ 0.275959] CPU features: detected: RCpc load-acquire (LDAPR)
10485 00:23:48.012916 <6>[ 0.281919] CPU features: detected: LSE atomic instructions
10486 00:23:48.019867 <6>[ 0.287701] CPU features: detected: Privileged Access Never
10487 00:23:48.023292 <6>[ 0.293481] CPU features: detected: RAS Extension Support
10488 00:23:48.030007 <6>[ 0.299090] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10489 00:23:48.036543 <6>[ 0.306308] CPU: All CPU(s) started at EL2
10490 00:23:48.039743 <6>[ 0.310651] alternatives: applying system-wide alternatives
10491 00:23:48.051131 <6>[ 0.321515] devtmpfs: initialized
10492 00:23:48.063548 <6>[ 0.330439] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10493 00:23:48.073126 <6>[ 0.340400] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10494 00:23:48.079894 <6>[ 0.348416] pinctrl core: initialized pinctrl subsystem
10495 00:23:48.083056 <6>[ 0.355084] DMI not present or invalid.
10496 00:23:48.089780 <6>[ 0.359497] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10497 00:23:48.099846 <6>[ 0.366352] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10498 00:23:48.105899 <6>[ 0.373933] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10499 00:23:48.115879 <6>[ 0.382151] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10500 00:23:48.119650 <6>[ 0.390396] audit: initializing netlink subsys (disabled)
10501 00:23:48.129511 <5>[ 0.396090] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10502 00:23:48.136021 <6>[ 0.396807] thermal_sys: Registered thermal governor 'step_wise'
10503 00:23:48.142797 <6>[ 0.404061] thermal_sys: Registered thermal governor 'power_allocator'
10504 00:23:48.146347 <6>[ 0.410315] cpuidle: using governor menu
10505 00:23:48.152875 <6>[ 0.421273] NET: Registered PF_QIPCRTR protocol family
10506 00:23:48.159645 <6>[ 0.426750] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10507 00:23:48.162661 <6>[ 0.433853] ASID allocator initialised with 32768 entries
10508 00:23:48.170084 <6>[ 0.440431] Serial: AMBA PL011 UART driver
10509 00:23:48.179074 <4>[ 0.449264] Trying to register duplicate clock ID: 134
10510 00:23:48.236317 <6>[ 0.510573] KASLR enabled
10511 00:23:48.251188 <6>[ 0.518327] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10512 00:23:48.257794 <6>[ 0.525343] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10513 00:23:48.264422 <6>[ 0.531833] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10514 00:23:48.271104 <6>[ 0.538841] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10515 00:23:48.277808 <6>[ 0.545328] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10516 00:23:48.284234 <6>[ 0.552333] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10517 00:23:48.290764 <6>[ 0.558820] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10518 00:23:48.297410 <6>[ 0.565827] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10519 00:23:48.300700 <6>[ 0.573266] ACPI: Interpreter disabled.
10520 00:23:48.309138 <6>[ 0.579695] iommu: Default domain type: Translated
10521 00:23:48.315387 <6>[ 0.584808] iommu: DMA domain TLB invalidation policy: strict mode
10522 00:23:48.319184 <5>[ 0.591471] SCSI subsystem initialized
10523 00:23:48.325815 <6>[ 0.595641] usbcore: registered new interface driver usbfs
10524 00:23:48.332650 <6>[ 0.601373] usbcore: registered new interface driver hub
10525 00:23:48.335667 <6>[ 0.606925] usbcore: registered new device driver usb
10526 00:23:48.342456 <6>[ 0.613019] pps_core: LinuxPPS API ver. 1 registered
10527 00:23:48.352198 <6>[ 0.618213] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10528 00:23:48.355601 <6>[ 0.627560] PTP clock support registered
10529 00:23:48.358946 <6>[ 0.631803] EDAC MC: Ver: 3.0.0
10530 00:23:48.366645 <6>[ 0.636963] FPGA manager framework
10531 00:23:48.369954 <6>[ 0.640646] Advanced Linux Sound Architecture Driver Initialized.
10532 00:23:48.373470 <6>[ 0.647433] vgaarb: loaded
10533 00:23:48.380358 <6>[ 0.650582] clocksource: Switched to clocksource arch_sys_counter
10534 00:23:48.387510 <5>[ 0.657021] VFS: Disk quotas dquot_6.6.0
10535 00:23:48.393917 <6>[ 0.661205] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10536 00:23:48.397271 <6>[ 0.668397] pnp: PnP ACPI: disabled
10537 00:23:48.404573 <6>[ 0.675108] NET: Registered PF_INET protocol family
10538 00:23:48.415156 <6>[ 0.680715] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10539 00:23:48.426184 <6>[ 0.693062] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10540 00:23:48.436262 <6>[ 0.701876] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10541 00:23:48.442975 <6>[ 0.709847] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10542 00:23:48.449605 <6>[ 0.718544] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10543 00:23:48.461290 <6>[ 0.728299] TCP: Hash tables configured (established 65536 bind 65536)
10544 00:23:48.467947 <6>[ 0.735170] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10545 00:23:48.474524 <6>[ 0.742368] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10546 00:23:48.481636 <6>[ 0.750075] NET: Registered PF_UNIX/PF_LOCAL protocol family
10547 00:23:48.488346 <6>[ 0.756223] RPC: Registered named UNIX socket transport module.
10548 00:23:48.491479 <6>[ 0.762377] RPC: Registered udp transport module.
10549 00:23:48.497953 <6>[ 0.767312] RPC: Registered tcp transport module.
10550 00:23:48.504794 <6>[ 0.772243] RPC: Registered tcp NFSv4.1 backchannel transport module.
10551 00:23:48.508075 <6>[ 0.778911] PCI: CLS 0 bytes, default 64
10552 00:23:48.511012 <6>[ 0.783240] Unpacking initramfs...
10553 00:23:48.535750 <6>[ 0.802687] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10554 00:23:48.545539 <6>[ 0.811351] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10555 00:23:48.548572 <6>[ 0.820192] kvm [1]: IPA Size Limit: 40 bits
10556 00:23:48.555316 <6>[ 0.824720] kvm [1]: GICv3: no GICV resource entry
10557 00:23:48.558488 <6>[ 0.829740] kvm [1]: disabling GICv2 emulation
10558 00:23:48.565408 <6>[ 0.834431] kvm [1]: GIC system register CPU interface enabled
10559 00:23:48.568669 <6>[ 0.840588] kvm [1]: vgic interrupt IRQ18
10560 00:23:48.575308 <6>[ 0.844964] kvm [1]: VHE mode initialized successfully
10561 00:23:48.581688 <5>[ 0.851355] Initialise system trusted keyrings
10562 00:23:48.588613 <6>[ 0.856131] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10563 00:23:48.595296 <6>[ 0.866134] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10564 00:23:48.601890 <5>[ 0.872501] NFS: Registering the id_resolver key type
10565 00:23:48.605724 <5>[ 0.877799] Key type id_resolver registered
10566 00:23:48.612168 <5>[ 0.882214] Key type id_legacy registered
10567 00:23:48.618885 <6>[ 0.886499] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10568 00:23:48.625320 <6>[ 0.893420] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10569 00:23:48.631843 <6>[ 0.901119] 9p: Installing v9fs 9p2000 file system support
10570 00:23:48.667493 <5>[ 0.938455] Key type asymmetric registered
10571 00:23:48.671030 <5>[ 0.942786] Asymmetric key parser 'x509' registered
10572 00:23:48.681210 <6>[ 0.947949] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10573 00:23:48.684251 <6>[ 0.955563] io scheduler mq-deadline registered
10574 00:23:48.687735 <6>[ 0.960342] io scheduler kyber registered
10575 00:23:48.706980 <6>[ 0.977269] EINJ: ACPI disabled.
10576 00:23:48.739739 <4>[ 1.003187] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10577 00:23:48.749605 <4>[ 1.013798] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10578 00:23:48.763972 <6>[ 1.034481] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10579 00:23:48.772217 <6>[ 1.042352] printk: console [ttyS0] disabled
10580 00:23:48.799800 <6>[ 1.066980] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10581 00:23:48.806807 <6>[ 1.076453] printk: console [ttyS0] enabled
10582 00:23:48.809844 <6>[ 1.076453] printk: console [ttyS0] enabled
10583 00:23:48.816770 <6>[ 1.085349] printk: bootconsole [mtk8250] disabled
10584 00:23:48.819698 <6>[ 1.085349] printk: bootconsole [mtk8250] disabled
10585 00:23:48.826283 <6>[ 1.096364] SuperH (H)SCI(F) driver initialized
10586 00:23:48.829950 <6>[ 1.101626] msm_serial: driver initialized
10587 00:23:48.843785 <6>[ 1.110529] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10588 00:23:48.853667 <6>[ 1.119080] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10589 00:23:48.860462 <6>[ 1.127621] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10590 00:23:48.870155 <6>[ 1.136248] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10591 00:23:48.876709 <6>[ 1.144954] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10592 00:23:48.886948 <6>[ 1.153672] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10593 00:23:48.896683 <6>[ 1.162212] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10594 00:23:48.903429 <6>[ 1.171005] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10595 00:23:48.913407 <6>[ 1.179547] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10596 00:23:48.924186 <6>[ 1.194711] loop: module loaded
10597 00:23:48.930921 <6>[ 1.200694] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10598 00:23:48.953520 <4>[ 1.223888] mtk-pmic-keys: Failed to locate of_node [id: -1]
10599 00:23:48.960321 <6>[ 1.230630] megasas: 07.719.03.00-rc1
10600 00:23:48.970143 <6>[ 1.240339] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10601 00:23:48.979961 <6>[ 1.249970] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10602 00:23:48.996525 <6>[ 1.266649] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10603 00:23:49.053243 <6>[ 1.316740] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10604 00:23:50.229875 <6>[ 2.500951] Freeing initrd memory: 40252K
10605 00:23:50.241894 <6>[ 2.512542] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10606 00:23:50.252693 <6>[ 2.523712] tun: Universal TUN/TAP device driver, 1.6
10607 00:23:50.256470 <6>[ 2.529777] thunder_xcv, ver 1.0
10608 00:23:50.259663 <6>[ 2.533282] thunder_bgx, ver 1.0
10609 00:23:50.262847 <6>[ 2.536782] nicpf, ver 1.0
10610 00:23:50.273582 <6>[ 2.540803] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10611 00:23:50.276439 <6>[ 2.548279] hns3: Copyright (c) 2017 Huawei Corporation.
10612 00:23:50.279904 <6>[ 2.553870] hclge is initializing
10613 00:23:50.286771 <6>[ 2.557450] e1000: Intel(R) PRO/1000 Network Driver
10614 00:23:50.293324 <6>[ 2.562580] e1000: Copyright (c) 1999-2006 Intel Corporation.
10615 00:23:50.297054 <6>[ 2.568591] e1000e: Intel(R) PRO/1000 Network Driver
10616 00:23:50.303220 <6>[ 2.573807] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10617 00:23:50.309861 <6>[ 2.579990] igb: Intel(R) Gigabit Ethernet Network Driver
10618 00:23:50.316764 <6>[ 2.585639] igb: Copyright (c) 2007-2014 Intel Corporation.
10619 00:23:50.323274 <6>[ 2.591475] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10620 00:23:50.327114 <6>[ 2.597992] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10621 00:23:50.334114 <6>[ 2.604452] sky2: driver version 1.30
10622 00:23:50.341050 <6>[ 2.609375] usbcore: registered new device driver r8152-cfgselector
10623 00:23:50.347510 <6>[ 2.615913] usbcore: registered new interface driver r8152
10624 00:23:50.350445 <6>[ 2.621735] VFIO - User Level meta-driver version: 0.3
10625 00:23:50.359643 <6>[ 2.629976] usbcore: registered new interface driver usb-storage
10626 00:23:50.365759 <6>[ 2.636428] usbcore: registered new device driver onboard-usb-hub
10627 00:23:50.374956 <6>[ 2.645578] mt6397-rtc mt6359-rtc: registered as rtc0
10628 00:23:50.384811 <6>[ 2.651041] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-21T00:23:50 UTC (1718929430)
10629 00:23:50.388339 <6>[ 2.660602] i2c_dev: i2c /dev entries driver
10630 00:23:50.401806 <4>[ 2.672597] cpu cpu0: supply cpu not found, using dummy regulator
10631 00:23:50.408195 <4>[ 2.679021] cpu cpu1: supply cpu not found, using dummy regulator
10632 00:23:50.415011 <4>[ 2.685428] cpu cpu2: supply cpu not found, using dummy regulator
10633 00:23:50.421729 <4>[ 2.691831] cpu cpu3: supply cpu not found, using dummy regulator
10634 00:23:50.428260 <4>[ 2.698227] cpu cpu4: supply cpu not found, using dummy regulator
10635 00:23:50.434971 <4>[ 2.704643] cpu cpu5: supply cpu not found, using dummy regulator
10636 00:23:50.441492 <4>[ 2.711037] cpu cpu6: supply cpu not found, using dummy regulator
10637 00:23:50.447830 <4>[ 2.717437] cpu cpu7: supply cpu not found, using dummy regulator
10638 00:23:50.467097 <6>[ 2.738072] cpu cpu0: EM: created perf domain
10639 00:23:50.470644 <6>[ 2.743011] cpu cpu4: EM: created perf domain
10640 00:23:50.478195 <6>[ 2.748640] sdhci: Secure Digital Host Controller Interface driver
10641 00:23:50.484622 <6>[ 2.755073] sdhci: Copyright(c) Pierre Ossman
10642 00:23:50.491483 <6>[ 2.760026] Synopsys Designware Multimedia Card Interface Driver
10643 00:23:50.497862 <6>[ 2.766680] sdhci-pltfm: SDHCI platform and OF driver helper
10644 00:23:50.501559 <6>[ 2.766754] mmc0: CQHCI version 5.10
10645 00:23:50.508115 <6>[ 2.776730] ledtrig-cpu: registered to indicate activity on CPUs
10646 00:23:50.514193 <6>[ 2.783863] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10647 00:23:50.520688 <6>[ 2.790911] usbcore: registered new interface driver usbhid
10648 00:23:50.524477 <6>[ 2.796734] usbhid: USB HID core driver
10649 00:23:50.531511 <6>[ 2.800948] spi_master spi0: will run message pump with realtime priority
10650 00:23:50.576564 <6>[ 2.840598] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10651 00:23:50.595831 <6>[ 2.856440] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10652 00:23:50.599112 <6>[ 2.867749] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17014
10653 00:23:50.608122 <6>[ 2.878221] cros-ec-spi spi0.0: Chrome EC device registered
10654 00:23:50.614795 <6>[ 2.884258] mmc0: Command Queue Engine enabled
10655 00:23:50.621167 <6>[ 2.889014] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10656 00:23:50.624494 <6>[ 2.896708] mmcblk0: mmc0:0001 DA4128 116 GiB
10657 00:23:50.637121 <6>[ 2.907683] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10658 00:23:50.647523 <6>[ 2.911628] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10659 00:23:50.653591 <6>[ 2.915138] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10660 00:23:50.657317 <6>[ 2.924228] NET: Registered PF_PACKET protocol family
10661 00:23:50.663306 <6>[ 2.928856] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10662 00:23:50.667119 <6>[ 2.933491] 9pnet: Installing 9P2000 support
10663 00:23:50.673263 <6>[ 2.939330] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10664 00:23:50.680128 <5>[ 2.943200] Key type dns_resolver registered
10665 00:23:50.683181 <6>[ 2.954636] registered taskstats version 1
10666 00:23:50.689679 <5>[ 2.959011] Loading compiled-in X.509 certificates
10667 00:23:50.719319 <4>[ 2.983232] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10668 00:23:50.729653 <4>[ 2.993943] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10669 00:23:50.743779 <6>[ 3.014293] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10670 00:23:50.750498 <6>[ 3.021253] xhci-mtk 11200000.usb: xHCI Host Controller
10671 00:23:50.757130 <6>[ 3.026823] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10672 00:23:50.767178 <6>[ 3.034738] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10673 00:23:50.773693 <6>[ 3.044174] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10674 00:23:50.780471 <6>[ 3.050382] xhci-mtk 11200000.usb: xHCI Host Controller
10675 00:23:50.787534 <6>[ 3.055886] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10676 00:23:50.793427 <6>[ 3.063543] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10677 00:23:50.800342 <6>[ 3.071369] hub 1-0:1.0: USB hub found
10678 00:23:50.803783 <6>[ 3.075395] hub 1-0:1.0: 1 port detected
10679 00:23:50.814131 <6>[ 3.079698] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10680 00:23:50.817107 <6>[ 3.088423] hub 2-0:1.0: USB hub found
10681 00:23:50.820600 <6>[ 3.092453] hub 2-0:1.0: 1 port detected
10682 00:23:50.828629 <6>[ 3.099511] mtk-msdc 11f70000.mmc: Got CD GPIO
10683 00:23:50.842705 <6>[ 3.110071] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10684 00:23:50.852695 <6>[ 3.118453] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10685 00:23:50.859250 <6>[ 3.126796] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10686 00:23:50.869695 <6>[ 3.135139] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10687 00:23:50.875919 <6>[ 3.143478] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10688 00:23:50.886155 <6>[ 3.151819] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10689 00:23:50.892732 <6>[ 3.160157] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10690 00:23:50.903045 <6>[ 3.168495] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10691 00:23:50.909236 <6>[ 3.176845] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10692 00:23:50.919080 <6>[ 3.185183] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10693 00:23:50.926064 <6>[ 3.193521] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10694 00:23:50.935992 <6>[ 3.201866] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10695 00:23:50.942727 <6>[ 3.210204] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10696 00:23:50.952474 <6>[ 3.218542] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10697 00:23:50.958727 <6>[ 3.226880] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10698 00:23:50.965866 <6>[ 3.235592] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10699 00:23:50.971998 <6>[ 3.242759] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10700 00:23:50.979139 <6>[ 3.249528] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10701 00:23:50.988926 <6>[ 3.256325] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10702 00:23:50.995880 <6>[ 3.263261] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10703 00:23:51.002694 <6>[ 3.270151] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10704 00:23:51.012553 <6>[ 3.279287] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10705 00:23:51.022390 <6>[ 3.288409] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10706 00:23:51.032177 <6>[ 3.297702] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10707 00:23:51.042264 <6>[ 3.307169] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10708 00:23:51.049009 <6>[ 3.316636] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10709 00:23:51.058849 <6>[ 3.325756] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10710 00:23:51.068989 <6>[ 3.335222] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10711 00:23:51.078705 <6>[ 3.344341] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10712 00:23:51.088863 <6>[ 3.353634] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10713 00:23:51.098842 <6>[ 3.363795] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10714 00:23:51.108567 <6>[ 3.375282] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10715 00:23:51.235248 <6>[ 3.502854] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10716 00:23:51.389932 <6>[ 3.660717] hub 1-1:1.0: USB hub found
10717 00:23:51.393479 <6>[ 3.665257] hub 1-1:1.0: 4 ports detected
10718 00:23:51.404991 <6>[ 3.675671] hub 1-1:1.0: USB hub found
10719 00:23:51.408605 <6>[ 3.680008] hub 1-1:1.0: 4 ports detected
10720 00:23:51.515492 <6>[ 3.783083] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10721 00:23:51.542298 <6>[ 3.812670] hub 2-1:1.0: USB hub found
10722 00:23:51.544960 <6>[ 3.817165] hub 2-1:1.0: 3 ports detected
10723 00:23:51.556840 <6>[ 3.827559] hub 2-1:1.0: USB hub found
10724 00:23:51.560282 <6>[ 3.831940] hub 2-1:1.0: 3 ports detected
10725 00:23:51.727525 <6>[ 3.994902] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10726 00:23:51.859986 <6>[ 4.130873] hub 1-1.4:1.0: USB hub found
10727 00:23:51.863705 <6>[ 4.135537] hub 1-1.4:1.0: 2 ports detected
10728 00:23:51.876669 <6>[ 4.147217] hub 1-1.4:1.0: USB hub found
10729 00:23:51.879709 <6>[ 4.151823] hub 1-1.4:1.0: 2 ports detected
10730 00:23:51.939257 <6>[ 4.207094] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10731 00:23:52.047916 <6>[ 4.315536] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10732 00:23:52.085029 <4>[ 4.352139] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10733 00:23:52.094845 <4>[ 4.361273] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10734 00:23:52.133633 <6>[ 4.404337] r8152 2-1.3:1.0 eth0: v1.12.13
10735 00:23:52.175313 <6>[ 4.442690] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10736 00:23:52.367163 <6>[ 4.634740] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10737 00:23:54.034764 <6>[ 6.305601] r8152 2-1.3:1.0 eth0: carrier on
10738 00:23:54.076188 <5>[ 6.330681] Sending DHCP requests ., OK
10739 00:23:54.082517 <6>[ 6.350917] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10740 00:23:54.085591 <6>[ 6.359217] IP-Config: Complete:
10741 00:23:54.098900 <6>[ 6.362718] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10742 00:23:54.105051 <6>[ 6.373446] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10743 00:23:54.111935 <6>[ 6.382065] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10744 00:23:54.118742 <6>[ 6.382075] nameserver0=192.168.201.1
10745 00:23:54.122158 <6>[ 6.394178] clk: Disabling unused clocks
10746 00:23:54.125792 <6>[ 6.399722] ALSA device list:
10747 00:23:54.129378 <6>[ 6.402985] No soundcards found.
10748 00:23:54.139776 <6>[ 6.410516] Freeing unused kernel memory: 8512K
10749 00:23:54.143277 <6>[ 6.415525] Run /init as init process
10750 00:23:54.176629 <6>[ 6.447404] NET: Registered PF_INET6 protocol family
10751 00:23:54.183259 <6>[ 6.454333] Segment Routing with IPv6
10752 00:23:54.186545 <6>[ 6.458291] In-situ OAM (IOAM) with IPv6
10753 00:23:54.231951 <30>[ 6.476682] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10754 00:23:54.238579 <30>[ 6.509750] systemd[1]: Detected architecture arm64.
10755 00:23:54.238977
10756 00:23:54.245365 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10757 00:23:54.245757
10758 00:23:54.259804 <30>[ 6.531006] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10759 00:23:54.385573 <30>[ 6.652831] systemd[1]: Queued start job for default target graphical.target.
10760 00:23:54.429219 <30>[ 6.696623] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10761 00:23:54.435853 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10762 00:23:54.456052 <30>[ 6.723520] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10763 00:23:54.462468 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10764 00:23:54.483998 <30>[ 6.751992] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10765 00:23:54.494351 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10766 00:23:54.512386 <30>[ 6.780297] systemd[1]: Created slice user.slice - User and Session Slice.
10767 00:23:54.519711 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10768 00:23:54.543477 <30>[ 6.807592] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10769 00:23:54.550094 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10770 00:23:54.570906 <30>[ 6.835164] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10771 00:23:54.577450 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10772 00:23:54.605760 <30>[ 6.863448] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10773 00:23:54.615628 <30>[ 6.883352] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10774 00:23:54.621967 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10775 00:23:54.638989 <30>[ 6.906905] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10776 00:23:54.645848 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10777 00:23:54.663122 <30>[ 6.930949] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10778 00:23:54.672934 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10779 00:23:54.688228 <30>[ 6.958962] systemd[1]: Reached target paths.target - Path Units.
10780 00:23:54.697606 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10781 00:23:54.715505 <30>[ 6.983321] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10782 00:23:54.722653 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10783 00:23:54.735848 <30>[ 7.006867] systemd[1]: Reached target slices.target - Slice Units.
10784 00:23:54.745569 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10785 00:23:54.760390 <30>[ 7.031382] systemd[1]: Reached target swap.target - Swaps.
10786 00:23:54.766974 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10787 00:23:54.787808 <30>[ 7.055385] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10788 00:23:54.797688 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10789 00:23:54.815869 <30>[ 7.083819] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10790 00:23:54.826086 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10791 00:23:54.845346 <30>[ 7.112905] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10792 00:23:54.855478 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10793 00:23:54.871662 <30>[ 7.139520] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10794 00:23:54.881585 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10795 00:23:54.899313 <30>[ 7.167498] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10796 00:23:54.906033 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10797 00:23:54.923515 <30>[ 7.191579] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10798 00:23:54.933419 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10799 00:23:54.952742 <30>[ 7.220288] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10800 00:23:54.962545 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10801 00:23:54.979860 <30>[ 7.247354] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10802 00:23:54.986263 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10803 00:23:55.039264 <30>[ 7.307211] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10804 00:23:55.046212 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10805 00:23:55.064952 <30>[ 7.332815] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10806 00:23:55.071903 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10807 00:23:55.094392 <30>[ 7.361810] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10808 00:23:55.100579 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10809 00:23:55.126113 <30>[ 7.387458] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10810 00:23:55.139730 <30>[ 7.407450] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10811 00:23:55.149366 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10812 00:23:55.172725 <30>[ 7.440356] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10813 00:23:55.179006 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10814 00:23:55.231715 <30>[ 7.499521] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10815 00:23:55.241714 Startin<6>[ 7.508947] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10816 00:23:55.248162 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10817 00:23:55.272979 <30>[ 7.540433] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10818 00:23:55.279221 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10819 00:23:55.304585 <30>[ 7.572091] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10820 00:23:55.311029 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10821 00:23:55.336536 <30>[ 7.604117] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10822 00:23:55.342581 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10823 00:23:55.399584 <30>[ 7.667322] systemd[1]: Starting systemd-journald.service - Journal Service...
10824 00:23:55.405561 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10825 00:23:55.425986 <30>[ 7.694271] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10826 00:23:55.433019 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10827 00:23:55.459573 <30>[ 7.724447] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10828 00:23:55.466135 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10829 00:23:55.492079 <30>[ 7.760158] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10830 00:23:55.501829 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10831 00:23:55.552280 <30>[ 7.820157] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10832 00:23:55.562090 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10833 00:23:55.583884 <30>[ 7.851402] systemd[1]: Started systemd-journald.service - Journal Service.
10834 00:23:55.590372 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10835 00:23:55.609551 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10836 00:23:55.628104 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10837 00:23:55.647805 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10838 00:23:55.664116 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10839 00:23:55.684929 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10840 00:23:55.706589 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10841 00:23:55.726650 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10842 00:23:55.746288 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10843 00:23:55.766107 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10844 00:23:55.789440 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10845 00:23:55.809215 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10846 00:23:55.830313 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10847 00:23:55.851906 See 'systemctl status systemd-remount-fs.service' for details.
10848 00:23:55.862934 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10849 00:23:55.881910 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10850 00:23:55.943466 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10851 00:23:55.968661 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10852 00:23:55.978816 <46>[ 8.247267] systemd-journald[192]: Received client request to flush runtime journal.
10853 00:23:55.997302 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10854 00:23:56.020868 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10855 00:23:56.044776 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10856 00:23:56.073969 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10857 00:23:56.092540 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10858 00:23:56.112669 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10859 00:23:56.132486 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10860 00:23:56.152598 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10861 00:23:56.203653 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10862 00:23:56.226282 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10863 00:23:56.246925 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10864 00:23:56.266847 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10865 00:23:56.327758 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10866 00:23:56.356889 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10867 00:23:56.382173 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10868 00:23:56.428080 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10869 00:23:56.451938 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10870 00:23:56.475720 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10871 00:23:56.514628 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10872 00:23:56.546913 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10873 00:23:56.570931 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10874 00:23:56.672202 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10875 00:23:56.696065 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10876 00:23:56.715823 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10877 00:23:56.737181 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10878 00:23:56.756203 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10879 00:23:56.762743 <6>[ 9.030155] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10880 00:23:56.779843 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bu<3>[ 9.045882] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10881 00:23:56.786449 s System Message<6>[ 9.047482] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10882 00:23:56.796732 <6>[ 9.050019] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10883 00:23:56.796926 Bus Socket.
10884 00:23:56.803221 <6>[ 9.050046] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10885 00:23:56.813417 <4>[ 9.050276] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10886 00:23:56.823816 <6>[ 9.050976] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10887 00:23:56.830582 <6>[ 9.050981] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10888 00:23:56.837055 <6>[ 9.051182] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10889 00:23:56.846846 <6>[ 9.051196] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10890 00:23:56.853729 <6>[ 9.051201] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10891 00:23:56.863745 <6>[ 9.051213] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10892 00:23:56.870279 <3>[ 9.064836] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10893 00:23:56.879758 <6>[ 9.072623] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10894 00:23:56.886464 <3>[ 9.081295] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10895 00:23:56.896577 <6>[ 9.082318] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10896 00:23:56.900171 <6>[ 9.085038] remoteproc remoteproc0: scp is available
10897 00:23:56.906192 <6>[ 9.085319] remoteproc remoteproc0: powering up scp
10898 00:23:56.913106 <6>[ 9.085324] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10899 00:23:56.919684 <6>[ 9.085341] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10900 00:23:56.929657 <6>[ 9.090312] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10901 00:23:56.936199 <3>[ 9.098427] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10902 00:23:56.939777 <6>[ 9.102779] mc: Linux media interface: v0.10
10903 00:23:56.949697 <4>[ 9.120898] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10904 00:23:56.956318 <3>[ 9.122004] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10905 00:23:56.962733 <6>[ 9.127639] videodev: Linux video capture interface: v2.00
10906 00:23:56.969011 <4>[ 9.135606] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10907 00:23:56.976267 <3>[ 9.138940] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10908 00:23:56.986375 <3>[ 9.138951] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10909 00:23:56.993030 <3>[ 9.138959] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10910 00:23:57.003261 <3>[ 9.152532] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10911 00:23:57.009714 <6>[ 9.176358] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10912 00:23:57.016627 <3>[ 9.176711] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10913 00:23:57.026229 <4>[ 9.200587] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10914 00:23:57.029631 <4>[ 9.200587] Fallback method does not support PEC.
10915 00:23:57.040159 <3>[ 9.204550] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10916 00:23:57.047420 <3>[ 9.204554] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10917 00:23:57.054155 <3>[ 9.204684] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10918 00:23:57.063955 <6>[ 9.208237] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10919 00:23:57.071450 <6>[ 9.218379] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10920 00:23:57.078461 <6>[ 9.224479] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10921 00:23:57.085084 <6>[ 9.224488] remoteproc remoteproc0: remote processor scp is now up
10922 00:23:57.094581 <3>[ 9.227758] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10923 00:23:57.102216 <3>[ 9.227769] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10924 00:23:57.108973 <3>[ 9.227780] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10925 00:23:57.119253 <3>[ 9.227788] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10926 00:23:57.126689 <3>[ 9.227963] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10927 00:23:57.133702 <6>[ 9.230555] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10928 00:23:57.140656 <6>[ 9.230561] pci_bus 0000:00: root bus resource [bus 00-ff]
10929 00:23:57.147169 <6>[ 9.230566] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10930 00:23:57.154211 <6>[ 9.230569] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10931 00:23:57.160879 <6>[ 9.230599] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10932 00:23:57.171285 <6>[ 9.230614] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10933 00:23:57.174717 <6>[ 9.230689] pci 0000:00:00.0: supports D1 D2
10934 00:23:57.180968 <6>[ 9.230691] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10935 00:23:57.191087 <6>[ 9.231849] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10936 00:23:57.194680 <6>[ 9.231940] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10937 00:23:57.202123 <6>[ 9.231966] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10938 00:23:57.211716 <6>[ 9.231983] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10939 00:23:57.219202 <6>[ 9.231998] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10940 00:23:57.222245 <6>[ 9.232106] pci 0000:01:00.0: supports D1 D2
10941 00:23:57.228972 <6>[ 9.232108] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10942 00:23:57.238798 <6>[ 9.235077] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10943 00:23:57.245803 <6>[ 9.240104] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10944 00:23:57.252264 <3>[ 9.264499] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 00:23:57.261912 <6>[ 9.270697] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10946 00:23:57.272163 <6>[ 9.274251] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10947 00:23:57.282023 <6>[ 9.287214] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10948 00:23:57.288439 <6>[ 9.293908] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10949 00:23:57.295705 <6>[ 9.293918] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10950 00:23:57.305020 <6>[ 9.293931] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10951 00:23:57.315162 <6>[ 9.308026] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10952 00:23:57.321691 <6>[ 9.315640] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10953 00:23:57.331600 <3>[ 9.316542] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 00:23:57.337931 <3>[ 9.319039] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10955 00:23:57.347710 <3>[ 9.352413] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 00:23:57.351282 <6>[ 9.355616] pci 0000:00:00.0: PCI bridge to [bus 01]
10957 00:23:57.354548 <6>[ 9.362620] Bluetooth: Core ver 2.22
10958 00:23:57.364558 <6>[ 9.370128] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10959 00:23:57.371924 <6>[ 9.371446] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10960 00:23:57.382287 <6>[ 9.372716] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10961 00:23:57.389320 <6>[ 9.372929] usbcore: registered new interface driver uvcvideo
10962 00:23:57.396091 <6>[ 9.378417] NET: Registered PF_BLUETOOTH protocol family
10963 00:23:57.403164 <6>[ 9.386530] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10964 00:23:57.410086 <3>[ 9.391119] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 00:23:57.420415 <3>[ 9.391903] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10966 00:23:57.427248 <6>[ 9.394383] Bluetooth: HCI device and connection manager initialized
10967 00:23:57.430839 <6>[ 9.394396] Bluetooth: HCI socket layer initialized
10968 00:23:57.437703 <6>[ 9.394948] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10969 00:23:57.444835 <6>[ 9.403126] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10970 00:23:57.450931 <3>[ 9.406259] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 00:23:57.458241 <6>[ 9.409330] Bluetooth: L2CAP socket layer initialized
10972 00:23:57.461080 <6>[ 9.409341] Bluetooth: SCO socket layer initialized
10973 00:23:57.467865 <6>[ 9.415486] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10974 00:23:57.478162 <3>[ 9.428825] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 00:23:57.484568 <5>[ 9.448540] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10976 00:23:57.491131 <6>[ 9.472508] usbcore: registered new interface driver btusb
10977 00:23:57.501167 <4>[ 9.473444] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10978 00:23:57.507922 <3>[ 9.473462] Bluetooth: hci0: Failed to load firmware file (-2)
10979 00:23:57.514671 <3>[ 9.473469] Bluetooth: hci0: Failed to set up firmware (-2)
10980 00:23:57.524483 <4>[ 9.473476] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10981 00:23:57.531374 <3>[ 9.475681] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10982 00:23:57.541162 <3>[ 9.497729] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 00:23:57.547834 <5>[ 9.498053] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10984 00:23:57.557330 <5>[ 9.498290] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10985 00:23:57.563989 <4>[ 9.498353] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10986 00:23:57.570721 <6>[ 9.498358] cfg80211: failed to load regulatory.db
10987 00:23:57.577390 <6>[ 9.616774] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10988 00:23:57.584365 <6>[ 9.854341] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10989 00:23:57.590376 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10990 00:23:57.606946 <6>[ 9.878498] mt7921e 0000:01:00.0: ASIC revision: 79610010
10991 00:23:57.639321 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10992 00:23:57.655283 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10993 00:23:57.671598 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10994 00:23:57.715689 <6>[ 9.983842] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10995 00:23:57.718873 <6>[ 9.983842]
10996 00:23:57.725867 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10997 00:23:57.746258 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10998 00:23:57.778231 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10999 00:23:57.827490 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11000 00:23:57.850265 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11001 00:23:57.866741 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11002 00:23:57.879644 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11003 00:23:57.900256 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11004 00:23:57.945641 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11005 00:23:57.969667 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11006 00:23:57.984660 <6>[ 10.252843] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11007 00:23:58.001814 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11008 00:23:58.024792 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11009 00:23:58.079398 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11010 00:23:58.097668 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11011 00:23:58.114723 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11012 00:23:58.131101 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11013 00:23:58.147403 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11014 00:23:58.203014 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11015 00:23:58.228669 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11016 00:23:58.251151 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11017 00:23:58.291985 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11018 00:23:58.326569
11019 00:23:58.330190 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11020 00:23:58.330591
11021 00:23:58.333235 debian-bookworm-arm64 login: root (automatic login)
11022 00:23:58.333713
11023 00:23:58.347892 Linux debian-bookworm-arm64 6.1.94-cip23 #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024 aarch64
11024 00:23:58.348285
11025 00:23:58.354761 The programs included with the Debian GNU/Linux system are free software;
11026 00:23:58.361418 the exact distribution terms for each program are described in the
11027 00:23:58.364113 individual files in /usr/share/doc/*/copyright.
11028 00:23:58.364735
11029 00:23:58.371089 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11030 00:23:58.373800 permitted by applicable law.
11031 00:23:58.375709 Matched prompt #10: / #
11033 00:23:58.376690 Setting prompt string to ['/ #']
11034 00:23:58.377154 end: 2.2.5.1 login-action (duration 00:00:11) [common]
11036 00:23:58.378169 end: 2.2.5 auto-login-action (duration 00:00:11) [common]
11037 00:23:58.378632 start: 2.2.6 expect-shell-connection (timeout 00:03:03) [common]
11038 00:23:58.378968 Setting prompt string to ['/ #']
11039 00:23:58.379297 Forcing a shell prompt, looking for ['/ #']
11041 00:23:58.430028 / #
11042 00:23:58.430879 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11043 00:23:58.431358 Waiting using forced prompt support (timeout 00:02:30)
11044 00:23:58.436381
11045 00:23:58.437332 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11046 00:23:58.438012 start: 2.2.7 export-device-env (timeout 00:03:03) [common]
11047 00:23:58.438482 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11048 00:23:58.438902 end: 2.2 depthcharge-retry (duration 00:01:57) [common]
11049 00:23:58.439341 end: 2 depthcharge-action (duration 00:01:57) [common]
11050 00:23:58.439762 start: 3 lava-test-retry (timeout 00:07:37) [common]
11051 00:23:58.440236 start: 3.1 lava-test-shell (timeout 00:07:37) [common]
11052 00:23:58.440577 Using namespace: common
11054 00:23:58.541606 / # #
11055 00:23:58.542263 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11056 00:23:58.547576 #
11057 00:23:58.548351 Using /lava-14479176
11059 00:23:58.649605 / # export SHELL=/bin/sh
11060 00:23:58.656205 export SHELL=/bin/sh
11062 00:23:58.757531 / # . /lava-14479176/environment
11063 00:23:58.762642 . /lava-14479176/environment
11065 00:23:58.863430 / # /lava-14479176/bin/lava-test-runner /lava-14479176/0
11066 00:23:58.864064 Test shell timeout: 10s (minimum of the action and connection timeout)
11067 00:23:58.865318 /lava-14479176/bin/lava-test-runner /lava-14479176/0<6>[ 11.124634] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11068 00:23:58.869520
11069 00:23:58.914433 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11070 00:23:58.914832 + cd /lava-14479176/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11071 00:23:58.915140 + cat uuid
11072 00:23:58.915419 + UUID=14479176_1.5.2.3.1
11073 00:23:58.915693 + set +x
11074 00:23:58.916482 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 14479176_1.5.2.3.1>
11075 00:23:58.917186 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 14479176_1.5.2.3.1
11076 00:23:58.917569 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (14479176_1.5.2.3.1)
11077 00:23:58.917963 Skipping test definition patterns.
11078 00:23:58.919952 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11079 00:23:58.926465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11080 00:23:58.926965 device: /dev/video2
11081 00:23:58.927592 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11083 00:23:58.936371 <4>[ 11.204678] use of bytesused == 0 is deprecated and will be removed in the future,
11084 00:23:58.939907 <4>[ 11.212521] use the actual size instead.
11085 00:23:58.955861 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11086 00:23:58.966509 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11087 00:23:58.971902
11088 00:23:58.984592 Compliance test for mtk-vcodec-enc device /dev/video2:
11089 00:23:58.992007
11090 00:23:59.005283 Driver Info:
11091 00:23:59.016762 Driver name : mtk-vcodec-enc
11092 00:23:59.030444 Card type : MT8192 video encoder
11093 00:23:59.044258 Bus info : platform:17020000.vcodec
11094 00:23:59.055176 Driver version : 6.1.94
11095 00:23:59.069525 Capabilities : 0x84204000
11096 00:23:59.080376 Video Memory-to-Memory Multiplanar
11097 00:23:59.091241 Streaming
11098 00:23:59.106459 Extended Pix Format
11099 00:23:59.117588 Device Capabilities
11100 00:23:59.128401 Device Caps : 0x04204000
11101 00:23:59.144077 Video Memory-to-Memory Multiplanar
11102 00:23:59.155679 Streaming
11103 00:23:59.167358 Extended Pix Format
11104 00:23:59.179428 Detected Stateful Encoder
11105 00:23:59.191842
11106 00:23:59.205241 Required ioctls:
11107 00:23:59.220242 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11108 00:23:59.220812 test VIDIOC_QUERYCAP: OK
11109 00:23:59.221588 Received signal: <TESTSET> START Required-ioctls
11110 00:23:59.222125 Starting test_set Required-ioctls
11111 00:23:59.244877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11112 00:23:59.245767 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11114 00:23:59.247994 test invalid ioctls: OK
11115 00:23:59.270585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11116 00:23:59.271200
11117 00:23:59.272013 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11119 00:23:59.281301 Allow for multiple opens:
11120 00:23:59.289154 <LAVA_SIGNAL_TESTSET STOP>
11121 00:23:59.289935 Received signal: <TESTSET> STOP
11122 00:23:59.290365 Closing test_set Required-ioctls
11123 00:23:59.300809 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11124 00:23:59.301608 Received signal: <TESTSET> START Allow-for-multiple-opens
11125 00:23:59.302144 Starting test_set Allow-for-multiple-opens
11126 00:23:59.303981 test second /dev/video2 open: OK
11127 00:23:59.325473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11128 00:23:59.326310 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11130 00:23:59.328270 test VIDIOC_QUERYCAP: OK
11131 00:23:59.349321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11132 00:23:59.350147 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11134 00:23:59.352839 test VIDIOC_G/S_PRIORITY: OK
11135 00:23:59.375030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11136 00:23:59.375900 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11138 00:23:59.378178 test for unlimited opens: OK
11139 00:23:59.398505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11140 00:23:59.399015
11141 00:23:59.399854 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11143 00:23:59.411883 Debug ioctls:
11144 00:23:59.420335 <LAVA_SIGNAL_TESTSET STOP>
11145 00:23:59.421056 Received signal: <TESTSET> STOP
11146 00:23:59.421402 Closing test_set Allow-for-multiple-opens
11147 00:23:59.429889 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11148 00:23:59.430585 Received signal: <TESTSET> START Debug-ioctls
11149 00:23:59.430967 Starting test_set Debug-ioctls
11150 00:23:59.432685 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11151 00:23:59.452466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11152 00:23:59.453095 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11154 00:23:59.458646 test VIDIOC_LOG_STATUS: OK (Not Supported)
11155 00:23:59.477971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11156 00:23:59.478497
11157 00:23:59.479040 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11159 00:23:59.489736 Input ioctls:
11160 00:23:59.495791 <LAVA_SIGNAL_TESTSET STOP>
11161 00:23:59.496496 Received signal: <TESTSET> STOP
11162 00:23:59.496825 Closing test_set Debug-ioctls
11163 00:23:59.505119 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11164 00:23:59.505741 Received signal: <TESTSET> START Input-ioctls
11165 00:23:59.506107 Starting test_set Input-ioctls
11166 00:23:59.508705 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11167 00:23:59.535202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11168 00:23:59.535896 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11170 00:23:59.538523 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11171 00:23:59.561368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11172 00:23:59.562023 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11174 00:23:59.567909 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11175 00:23:59.584465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11176 00:23:59.585091 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11178 00:23:59.591007 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11179 00:23:59.609092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11180 00:23:59.609719 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11182 00:23:59.612280 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11183 00:23:59.632792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11184 00:23:59.633418 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11186 00:23:59.636383 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11187 00:23:59.661411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11188 00:23:59.662082 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11190 00:23:59.664716 Inputs: 0 Audio Inputs: 0 Tuners: 0
11191 00:23:59.672462
11192 00:23:59.689627 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11193 00:23:59.716991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11194 00:23:59.717648 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11196 00:23:59.723646 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11197 00:23:59.743163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11198 00:23:59.743856 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11200 00:23:59.749458 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11201 00:23:59.767684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11202 00:23:59.768301 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11204 00:23:59.774196 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11205 00:23:59.791826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11206 00:23:59.792520 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11208 00:23:59.798216 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11209 00:23:59.817225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11210 00:23:59.817613
11211 00:23:59.818144 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11213 00:23:59.835546 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11214 00:23:59.857065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11215 00:23:59.857688 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11217 00:23:59.863844 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11218 00:23:59.886778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11219 00:23:59.887401 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11221 00:23:59.889713 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11222 00:23:59.908368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11223 00:23:59.909069 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11225 00:23:59.911521 test VIDIOC_G/S_EDID: OK (Not Supported)
11226 00:23:59.932634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11227 00:23:59.933022
11228 00:23:59.933546 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11230 00:23:59.943888 Control ioctls:
11231 00:23:59.951814 <LAVA_SIGNAL_TESTSET STOP>
11232 00:23:59.952425 Received signal: <TESTSET> STOP
11233 00:23:59.952780 Closing test_set Input-ioctls
11234 00:23:59.962037 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11235 00:23:59.962654 Received signal: <TESTSET> START Control-ioctls
11236 00:23:59.962969 Starting test_set Control-ioctls
11237 00:23:59.964882 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11238 00:23:59.994922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11239 00:23:59.995322 test VIDIOC_QUERYCTRL: OK
11240 00:23:59.995915 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11242 00:24:00.017621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11243 00:24:00.018274 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11245 00:24:00.020885 test VIDIOC_G/S_CTRL: OK
11246 00:24:00.042230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11247 00:24:00.042473 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11249 00:24:00.045360 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11250 00:24:00.068266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11251 00:24:00.068958 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11253 00:24:00.074792 fail: v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11254 00:24:00.082952 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11255 00:24:00.105975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11256 00:24:00.106697 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11258 00:24:00.109510 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11259 00:24:00.127112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11260 00:24:00.127743 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11262 00:24:00.130165 Standard Controls: 16 Private Controls: 0
11263 00:24:00.136673
11264 00:24:00.148312 Format ioctls:
11265 00:24:00.155963 <LAVA_SIGNAL_TESTSET STOP>
11266 00:24:00.156605 Received signal: <TESTSET> STOP
11267 00:24:00.156992 Closing test_set Control-ioctls
11268 00:24:00.165866 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11269 00:24:00.166534 Received signal: <TESTSET> START Format-ioctls
11270 00:24:00.166857 Starting test_set Format-ioctls
11271 00:24:00.168748 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11272 00:24:00.194112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11273 00:24:00.194829 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11275 00:24:00.197722 test VIDIOC_G/S_PARM: OK
11276 00:24:00.216688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11277 00:24:00.217314 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11279 00:24:00.220265 test VIDIOC_G_FBUF: OK (Not Supported)
11280 00:24:00.242075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11281 00:24:00.242770 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11283 00:24:00.244882 test VIDIOC_G_FMT: OK
11284 00:24:00.266630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11285 00:24:00.267255 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11287 00:24:00.269664 test VIDIOC_TRY_FMT: OK
11288 00:24:00.290865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11289 00:24:00.291492 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11291 00:24:00.297975 fail: v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11292 00:24:00.301466 test VIDIOC_S_FMT: FAIL
11293 00:24:00.326725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11294 00:24:00.326968 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11296 00:24:00.330055 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11297 00:24:00.353380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11298 00:24:00.353630 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11300 00:24:00.356964 test Cropping: OK
11301 00:24:00.377677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11302 00:24:00.378405 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11304 00:24:00.381118 test Composing: OK (Not Supported)
11305 00:24:00.400805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11306 00:24:00.401063 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11308 00:24:00.404216 test Scaling: OK (Not Supported)
11309 00:24:00.430275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11310 00:24:00.430742
11311 00:24:00.431274 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11313 00:24:00.440775 Codec ioctls:
11314 00:24:00.448248 <LAVA_SIGNAL_TESTSET STOP>
11315 00:24:00.448870 Received signal: <TESTSET> STOP
11316 00:24:00.449226 Closing test_set Format-ioctls
11317 00:24:00.460193 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11318 00:24:00.460888 Received signal: <TESTSET> START Codec-ioctls
11319 00:24:00.461207 Starting test_set Codec-ioctls
11320 00:24:00.463918 test VIDIOC_(TRY_)ENCODER_CMD: OK
11321 00:24:00.486909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11322 00:24:00.487611 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11324 00:24:00.492928 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11325 00:24:00.510884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11326 00:24:00.511580 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11328 00:24:00.517228 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11329 00:24:00.539419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11330 00:24:00.539818
11331 00:24:00.540353 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11333 00:24:00.551921 Buffer ioctls:
11334 00:24:00.560315 <LAVA_SIGNAL_TESTSET STOP>
11335 00:24:00.560936 Received signal: <TESTSET> STOP
11336 00:24:00.561246 Closing test_set Codec-ioctls
11337 00:24:00.572890 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11338 00:24:00.573578 Received signal: <TESTSET> START Buffer-ioctls
11339 00:24:00.573897 Starting test_set Buffer-ioctls
11340 00:24:00.575824 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11341 00:24:00.599722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11342 00:24:00.600352 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11344 00:24:00.603165 test CREATE_BUFS maximum buffers: OK
11345 00:24:00.626550 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11347 00:24:00.629351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11348 00:24:00.629744 test VIDIOC_EXPBUF: OK
11349 00:24:00.651026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11350 00:24:00.651730 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11352 00:24:00.653907 test Requests: OK (Not Supported)
11353 00:24:00.679450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11354 00:24:00.679863
11355 00:24:00.680744 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11357 00:24:00.689239 Test input 0:
11358 00:24:00.698199
11359 00:24:00.709501 Streaming ioctls:
11360 00:24:00.716032 <LAVA_SIGNAL_TESTSET STOP>
11361 00:24:00.716656 Received signal: <TESTSET> STOP
11362 00:24:00.716973 Closing test_set Buffer-ioctls
11363 00:24:00.725389 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11364 00:24:00.726061 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11365 00:24:00.726401 Starting test_set Streaming-ioctls_Test-input-0
11366 00:24:00.729018 test read/write: OK (Not Supported)
11367 00:24:00.751292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11368 00:24:00.751925 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11370 00:24:00.757161 fail: v4l2-test-buffers.cpp(2829): node->streamon(q.g_type())
11371 00:24:00.764597 fail: v4l2-test-buffers.cpp(2876): testBlockingDQBuf(node, q)
11372 00:24:00.773015 test blocking wait: FAIL
11373 00:24:00.798217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11374 00:24:00.798889 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11376 00:24:00.804560 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11377 00:24:00.810015 test MMAP (select): FAIL
11378 00:24:00.838286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11379 00:24:00.838911 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11381 00:24:00.844910 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11382 00:24:00.847856 test MMAP (epoll): FAIL
11383 00:24:00.877913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11384 00:24:00.878594 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11386 00:24:00.884506 fail: v4l2-test-buffers.cpp(1633): ret && ret != ENOTTY (got 22)
11387 00:24:00.891022 fail: v4l2-test-buffers.cpp(1764): setupUserPtr(node, q)
11388 00:24:00.898388 test USERPTR (select): FAIL
11389 00:24:00.922997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11390 00:24:00.923627 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11392 00:24:00.926443 test DMABUF: Cannot test, specify --expbuf-device
11393 00:24:00.932669
11394 00:24:00.949739 Total for mtk-vcodec-enc device /dev/video2: 51, Succeeded: 45, Failed: 6, Warnings: 0
11395 00:24:00.953193 <LAVA_TEST_RUNNER EXIT>
11396 00:24:00.953809 ok: lava_test_shell seems to have completed
11397 00:24:00.954189 Marking unfinished test run as failed
11399 00:24:00.958179 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls
Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11400 00:24:00.958769 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11401 00:24:00.959167 end: 3 lava-test-retry (duration 00:00:03) [common]
11402 00:24:00.959566 start: 4 finalize (timeout 00:07:34) [common]
11403 00:24:00.959972 start: 4.1 power-off (timeout 00:00:30) [common]
11404 00:24:00.960630 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
11405 00:24:01.222999 >> Command sent successfully.
11406 00:24:01.236786 Returned 0 in 0 seconds
11407 00:24:01.338023 end: 4.1 power-off (duration 00:00:00) [common]
11409 00:24:01.339286 start: 4.2 read-feedback (timeout 00:07:34) [common]
11410 00:24:01.340300 Listened to connection for namespace 'common' for up to 1s
11411 00:24:02.341044 Finalising connection for namespace 'common'
11412 00:24:02.341596 Disconnecting from shell: Finalise
11413 00:24:02.341957 / #
11414 00:24:02.442747 end: 4.2 read-feedback (duration 00:00:01) [common]
11415 00:24:02.443439 end: 4 finalize (duration 00:00:01) [common]
11416 00:24:02.444091 Cleaning after the job
11417 00:24:02.444557 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479176/tftp-deploy-325ei7s0/ramdisk
11418 00:24:02.463580 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479176/tftp-deploy-325ei7s0/kernel
11419 00:24:02.476481 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479176/tftp-deploy-325ei7s0/dtb
11420 00:24:02.476663 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479176/tftp-deploy-325ei7s0/modules
11421 00:24:02.482174 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14479176
11422 00:24:02.540817 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14479176
11423 00:24:02.540957 Job finished correctly