Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 26
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 00:25:19.219440 lava-dispatcher, installed at version: 2024.03
2 00:25:19.219662 start: 0 validate
3 00:25:19.219782 Start time: 2024-06-21 00:25:19.219774+00:00 (UTC)
4 00:25:19.219914 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:25:19.220052 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 00:25:19.493197 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:25:19.493355 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:25:19.751398 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:25:19.751663 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:25:20.007724 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:25:20.007940 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:25:20.266486 validate duration: 1.05
14 00:25:20.266841 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:25:20.266981 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:25:20.267101 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:25:20.267287 Not decompressing ramdisk as can be used compressed.
18 00:25:20.267418 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 00:25:20.267520 saving as /var/lib/lava/dispatcher/tmp/14479209/tftp-deploy-tqaqu76_/ramdisk/rootfs.cpio.gz
20 00:25:20.267617 total size: 28105535 (26 MB)
21 00:25:20.268974 progress 0 % (0 MB)
22 00:25:20.276427 progress 5 % (1 MB)
23 00:25:20.283943 progress 10 % (2 MB)
24 00:25:20.291282 progress 15 % (4 MB)
25 00:25:20.298496 progress 20 % (5 MB)
26 00:25:20.305821 progress 25 % (6 MB)
27 00:25:20.313018 progress 30 % (8 MB)
28 00:25:20.320320 progress 35 % (9 MB)
29 00:25:20.327966 progress 40 % (10 MB)
30 00:25:20.335313 progress 45 % (12 MB)
31 00:25:20.342859 progress 50 % (13 MB)
32 00:25:20.350417 progress 55 % (14 MB)
33 00:25:20.358152 progress 60 % (16 MB)
34 00:25:20.365641 progress 65 % (17 MB)
35 00:25:20.373018 progress 70 % (18 MB)
36 00:25:20.380209 progress 75 % (20 MB)
37 00:25:20.387513 progress 80 % (21 MB)
38 00:25:20.394754 progress 85 % (22 MB)
39 00:25:20.401975 progress 90 % (24 MB)
40 00:25:20.409179 progress 95 % (25 MB)
41 00:25:20.416279 progress 100 % (26 MB)
42 00:25:20.416507 26 MB downloaded in 0.15 s (180.03 MB/s)
43 00:25:20.416673 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:25:20.416902 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:25:20.416985 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:25:20.417063 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:25:20.417197 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:25:20.417259 saving as /var/lib/lava/dispatcher/tmp/14479209/tftp-deploy-tqaqu76_/kernel/Image
50 00:25:20.417315 total size: 54813184 (52 MB)
51 00:25:20.417370 No compression specified
52 00:25:20.418412 progress 0 % (0 MB)
53 00:25:20.432100 progress 5 % (2 MB)
54 00:25:20.445944 progress 10 % (5 MB)
55 00:25:20.459589 progress 15 % (7 MB)
56 00:25:20.473542 progress 20 % (10 MB)
57 00:25:20.487446 progress 25 % (13 MB)
58 00:25:20.501112 progress 30 % (15 MB)
59 00:25:20.515015 progress 35 % (18 MB)
60 00:25:20.528891 progress 40 % (20 MB)
61 00:25:20.542673 progress 45 % (23 MB)
62 00:25:20.556581 progress 50 % (26 MB)
63 00:25:20.570514 progress 55 % (28 MB)
64 00:25:20.584290 progress 60 % (31 MB)
65 00:25:20.598179 progress 65 % (34 MB)
66 00:25:20.611846 progress 70 % (36 MB)
67 00:25:20.625716 progress 75 % (39 MB)
68 00:25:20.639591 progress 80 % (41 MB)
69 00:25:20.653528 progress 85 % (44 MB)
70 00:25:20.670058 progress 90 % (47 MB)
71 00:25:20.685571 progress 95 % (49 MB)
72 00:25:20.699048 progress 100 % (52 MB)
73 00:25:20.699289 52 MB downloaded in 0.28 s (185.39 MB/s)
74 00:25:20.699442 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:25:20.699658 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:25:20.699742 start: 1.3 download-retry (timeout 00:10:00) [common]
78 00:25:20.699820 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 00:25:20.699952 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:25:20.700015 saving as /var/lib/lava/dispatcher/tmp/14479209/tftp-deploy-tqaqu76_/dtb/mt8192-asurada-spherion-r0.dtb
81 00:25:20.700070 total size: 47258 (0 MB)
82 00:25:20.700125 No compression specified
83 00:25:20.701130 progress 69 % (0 MB)
84 00:25:20.701394 progress 100 % (0 MB)
85 00:25:20.701543 0 MB downloaded in 0.00 s (30.66 MB/s)
86 00:25:20.701658 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:25:20.701865 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:25:20.701944 start: 1.4 download-retry (timeout 00:10:00) [common]
90 00:25:20.702021 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 00:25:20.702128 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:25:20.702191 saving as /var/lib/lava/dispatcher/tmp/14479209/tftp-deploy-tqaqu76_/modules/modules.tar
93 00:25:20.702245 total size: 8618924 (8 MB)
94 00:25:20.702301 Using unxz to decompress xz
95 00:25:20.703588 progress 0 % (0 MB)
96 00:25:20.722932 progress 5 % (0 MB)
97 00:25:20.746880 progress 10 % (0 MB)
98 00:25:20.773849 progress 15 % (1 MB)
99 00:25:20.798719 progress 20 % (1 MB)
100 00:25:20.824559 progress 25 % (2 MB)
101 00:25:20.849149 progress 30 % (2 MB)
102 00:25:20.873940 progress 35 % (2 MB)
103 00:25:20.897830 progress 40 % (3 MB)
104 00:25:20.922191 progress 45 % (3 MB)
105 00:25:20.946502 progress 50 % (4 MB)
106 00:25:20.971665 progress 55 % (4 MB)
107 00:25:20.996924 progress 60 % (4 MB)
108 00:25:21.020930 progress 65 % (5 MB)
109 00:25:21.049656 progress 70 % (5 MB)
110 00:25:21.075045 progress 75 % (6 MB)
111 00:25:21.099244 progress 80 % (6 MB)
112 00:25:21.122763 progress 85 % (7 MB)
113 00:25:21.146427 progress 90 % (7 MB)
114 00:25:21.173289 progress 95 % (7 MB)
115 00:25:21.202378 progress 100 % (8 MB)
116 00:25:21.206873 8 MB downloaded in 0.50 s (16.29 MB/s)
117 00:25:21.207067 end: 1.4.1 http-download (duration 00:00:01) [common]
119 00:25:21.207284 end: 1.4 download-retry (duration 00:00:01) [common]
120 00:25:21.207364 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:25:21.207443 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:25:21.207524 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:25:21.207630 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:25:21.207823 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9
125 00:25:21.207975 makedir: /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin
126 00:25:21.208115 makedir: /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/tests
127 00:25:21.208235 makedir: /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/results
128 00:25:21.208347 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-add-keys
129 00:25:21.208506 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-add-sources
130 00:25:21.208671 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-background-process-start
131 00:25:21.208823 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-background-process-stop
132 00:25:21.208977 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-common-functions
133 00:25:21.209145 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-echo-ipv4
134 00:25:21.209263 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-install-packages
135 00:25:21.209375 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-installed-packages
136 00:25:21.209488 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-os-build
137 00:25:21.209614 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-probe-channel
138 00:25:21.209728 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-probe-ip
139 00:25:21.209839 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-target-ip
140 00:25:21.209959 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-target-mac
141 00:25:21.210081 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-target-storage
142 00:25:21.210198 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-test-case
143 00:25:21.210309 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-test-event
144 00:25:21.210419 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-test-feedback
145 00:25:21.210530 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-test-raise
146 00:25:21.210672 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-test-reference
147 00:25:21.210832 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-test-runner
148 00:25:21.210974 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-test-set
149 00:25:21.211124 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-test-shell
150 00:25:21.211267 Updating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-install-packages (oe)
151 00:25:21.211433 Updating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/bin/lava-installed-packages (oe)
152 00:25:21.211574 Creating /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/environment
153 00:25:21.211695 LAVA metadata
154 00:25:21.211762 - LAVA_JOB_ID=14479209
155 00:25:21.211819 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:25:21.211910 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:25:21.211968 skipped lava-vland-overlay
158 00:25:21.212035 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:25:21.212106 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:25:21.212186 skipped lava-multinode-overlay
161 00:25:21.212283 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:25:21.212381 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:25:21.212470 Loading test definitions
164 00:25:21.212574 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:25:21.212682 Using /lava-14479209 at stage 0
166 00:25:21.213096 uuid=14479209_1.5.2.3.1 testdef=None
167 00:25:21.213215 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:25:21.213321 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:25:21.213866 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:25:21.214072 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:25:21.214885 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:25:21.215251 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:25:21.216068 runner path: /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/0/tests/0_v4l2-compliance-uvc test_uuid 14479209_1.5.2.3.1
176 00:25:21.216254 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:25:21.216583 Creating lava-test-runner.conf files
179 00:25:21.216682 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14479209/lava-overlay-ctufajy9/lava-14479209/0 for stage 0
180 00:25:21.216796 - 0_v4l2-compliance-uvc
181 00:25:21.216888 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:25:21.216973 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 00:25:21.224140 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:25:21.224237 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 00:25:21.224316 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:25:21.224393 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:25:21.224474 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 00:25:22.144980 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 00:25:22.145164 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 00:25:22.145286 extracting modules file /var/lib/lava/dispatcher/tmp/14479209/tftp-deploy-tqaqu76_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479209/extract-overlay-ramdisk-ismk1zm3/ramdisk
191 00:25:22.381718 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:25:22.381858 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 00:25:22.381941 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14479209/compress-overlay-s3018bwh/overlay-1.5.2.4.tar.gz to ramdisk
194 00:25:22.382002 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14479209/compress-overlay-s3018bwh/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14479209/extract-overlay-ramdisk-ismk1zm3/ramdisk
195 00:25:22.389863 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:25:22.390009 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 00:25:22.390120 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:25:22.390225 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 00:25:22.390319 Building ramdisk /var/lib/lava/dispatcher/tmp/14479209/extract-overlay-ramdisk-ismk1zm3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14479209/extract-overlay-ramdisk-ismk1zm3/ramdisk
200 00:25:23.018213 >> 276033 blocks
201 00:25:27.449154 rename /var/lib/lava/dispatcher/tmp/14479209/extract-overlay-ramdisk-ismk1zm3/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14479209/tftp-deploy-tqaqu76_/ramdisk/ramdisk.cpio.gz
202 00:25:27.449328 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 00:25:27.449419 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 00:25:27.449499 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 00:25:27.449577 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14479209/tftp-deploy-tqaqu76_/kernel/Image']
206 00:25:41.604703 Returned 0 in 14 seconds
207 00:25:41.705258 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14479209/tftp-deploy-tqaqu76_/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14479209/tftp-deploy-tqaqu76_/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14479209/tftp-deploy-tqaqu76_/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14479209/tftp-deploy-tqaqu76_/kernel/image.itb
208 00:25:42.431174 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:25:42.431290 output: Created: Fri Jun 21 01:25:42 2024
210 00:25:42.431353 output: Image 0 (kernel-1)
211 00:25:42.431409 output: Description:
212 00:25:42.431465 output: Created: Fri Jun 21 01:25:42 2024
213 00:25:42.431521 output: Type: Kernel Image
214 00:25:42.431577 output: Compression: lzma compressed
215 00:25:42.431637 output: Data Size: 13124896 Bytes = 12817.28 KiB = 12.52 MiB
216 00:25:42.431689 output: Architecture: AArch64
217 00:25:42.431744 output: OS: Linux
218 00:25:42.431799 output: Load Address: 0x00000000
219 00:25:42.431852 output: Entry Point: 0x00000000
220 00:25:42.431905 output: Hash algo: crc32
221 00:25:42.431958 output: Hash value: ab2f7826
222 00:25:42.432013 output: Image 1 (fdt-1)
223 00:25:42.432064 output: Description: mt8192-asurada-spherion-r0
224 00:25:42.432115 output: Created: Fri Jun 21 01:25:42 2024
225 00:25:42.432165 output: Type: Flat Device Tree
226 00:25:42.432213 output: Compression: uncompressed
227 00:25:42.432260 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 00:25:42.432309 output: Architecture: AArch64
229 00:25:42.432357 output: Hash algo: crc32
230 00:25:42.432404 output: Hash value: 0f8e4d2e
231 00:25:42.432451 output: Image 2 (ramdisk-1)
232 00:25:42.432498 output: Description: unavailable
233 00:25:42.432545 output: Created: Fri Jun 21 01:25:42 2024
234 00:25:42.432592 output: Type: RAMDisk Image
235 00:25:42.432639 output: Compression: uncompressed
236 00:25:42.432729 output: Data Size: 41225997 Bytes = 40259.76 KiB = 39.32 MiB
237 00:25:42.432777 output: Architecture: AArch64
238 00:25:42.432824 output: OS: Linux
239 00:25:42.432871 output: Load Address: unavailable
240 00:25:42.432918 output: Entry Point: unavailable
241 00:25:42.432965 output: Hash algo: crc32
242 00:25:42.433013 output: Hash value: ab4a6044
243 00:25:42.433060 output: Default Configuration: 'conf-1'
244 00:25:42.433107 output: Configuration 0 (conf-1)
245 00:25:42.433155 output: Description: mt8192-asurada-spherion-r0
246 00:25:42.433202 output: Kernel: kernel-1
247 00:25:42.433250 output: Init Ramdisk: ramdisk-1
248 00:25:42.433298 output: FDT: fdt-1
249 00:25:42.433346 output: Loadables: kernel-1
250 00:25:42.433393 output:
251 00:25:42.433528 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 00:25:42.433610 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 00:25:42.433696 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 00:25:42.433776 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 00:25:42.433873 No LXC device requested
256 00:25:42.433944 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:25:42.434018 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 00:25:42.434089 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:25:42.434148 Checking files for TFTP limit of 4294967296 bytes.
260 00:25:42.434654 end: 1 tftp-deploy (duration 00:00:22) [common]
261 00:25:42.434753 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:25:42.434834 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:25:42.434940 substitutions:
264 00:25:42.434999 - {DTB}: 14479209/tftp-deploy-tqaqu76_/dtb/mt8192-asurada-spherion-r0.dtb
265 00:25:42.435058 - {INITRD}: 14479209/tftp-deploy-tqaqu76_/ramdisk/ramdisk.cpio.gz
266 00:25:42.435113 - {KERNEL}: 14479209/tftp-deploy-tqaqu76_/kernel/Image
267 00:25:42.435165 - {LAVA_MAC}: None
268 00:25:42.435215 - {PRESEED_CONFIG}: None
269 00:25:42.435268 - {PRESEED_LOCAL}: None
270 00:25:42.435333 - {RAMDISK}: 14479209/tftp-deploy-tqaqu76_/ramdisk/ramdisk.cpio.gz
271 00:25:42.435394 - {ROOT_PART}: None
272 00:25:42.435446 - {ROOT}: None
273 00:25:42.435497 - {SERVER_IP}: 192.168.201.1
274 00:25:42.435546 - {TEE}: None
275 00:25:42.435595 Parsed boot commands:
276 00:25:42.435643 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:25:42.435787 Parsed boot commands: tftpboot 192.168.201.1 14479209/tftp-deploy-tqaqu76_/kernel/image.itb 14479209/tftp-deploy-tqaqu76_/kernel/cmdline
278 00:25:42.435868 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:25:42.435944 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:25:42.436027 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:25:42.436100 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:25:42.436159 Not connected, no need to disconnect.
283 00:25:42.436226 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:25:42.436299 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:25:42.436357 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 00:25:42.439316 Setting prompt string to ['lava-test: # ']
287 00:25:42.439634 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:25:42.439729 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:25:42.439820 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:25:42.439950 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:25:42.440159 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-8']
292 00:25:56.244437 Returned 0 in 13 seconds
293 00:25:56.345008 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 00:25:56.345298 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 00:25:56.345409 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 00:25:56.345496 Setting prompt string to 'Starting depthcharge on Spherion...'
298 00:25:56.345560 Changing prompt to 'Starting depthcharge on Spherion...'
299 00:25:56.345625 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 00:25:56.345982 [Enter `^Ec?' for help]
301 00:25:56.346056
302 00:25:56.346116
303 00:25:56.346173 F0: 102B 0000
304 00:25:56.346230
305 00:25:56.346286 F3: 1001 0000 [0200]
306 00:25:56.346342
307 00:25:56.346399 F3: 1001 0000
308 00:25:56.346455
309 00:25:56.346511 F7: 102D 0000
310 00:25:56.346569
311 00:25:56.346631 F1: 0000 0000
312 00:25:56.346688
313 00:25:56.346743 V0: 0000 0000 [0001]
314 00:25:56.346796
315 00:25:56.346845 00: 0007 8000
316 00:25:56.346896
317 00:25:56.346946 01: 0000 0000
318 00:25:56.346996
319 00:25:56.347045 BP: 0C00 0209 [0000]
320 00:25:56.347094
321 00:25:56.347143 G0: 1182 0000
322 00:25:56.347191
323 00:25:56.347241 EC: 0000 0021 [4000]
324 00:25:56.347290
325 00:25:56.347339 S7: 0000 0000 [0000]
326 00:25:56.347388
327 00:25:56.347436 CC: 0000 0000 [0001]
328 00:25:56.347485
329 00:25:56.347534 T0: 0000 0040 [010F]
330 00:25:56.347583
331 00:25:56.347631 Jump to BL
332 00:25:56.347680
333 00:25:56.347729
334 00:25:56.347777
335 00:25:56.347826 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 00:25:56.347879 ARM64: Exception handlers installed.
337 00:25:56.347930 ARM64: Testing exception
338 00:25:56.347979 ARM64: Done test exception
339 00:25:56.348029 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 00:25:56.348079 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 00:25:56.348130 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 00:25:56.348180 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 00:25:56.348235 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 00:25:56.348286 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 00:25:56.348336 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 00:25:56.348387 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 00:25:56.348436 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 00:25:56.348486 WDT: Last reset was cold boot
349 00:25:56.348536 SPI1(PAD0) initialized at 2873684 Hz
350 00:25:56.348585 SPI5(PAD0) initialized at 992727 Hz
351 00:25:56.348635 VBOOT: Loading verstage.
352 00:25:56.348694 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 00:25:56.348744 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 00:25:56.348794 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 00:25:56.348845 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 00:25:56.348894 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 00:25:56.348944 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 00:25:56.348995 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
359 00:25:56.349045
360 00:25:56.349094
361 00:25:56.349143 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 00:25:56.349194 ARM64: Exception handlers installed.
363 00:25:56.349243 ARM64: Testing exception
364 00:25:56.349292 ARM64: Done test exception
365 00:25:56.349342 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 00:25:56.349392 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 00:25:56.349442 Probing TPM: . done!
368 00:25:56.349491 TPM ready after 0 ms
369 00:25:56.349542 Connected to device vid:did:rid of 1ae0:0028:00
370 00:25:56.349592 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
371 00:25:56.349643 Initialized TPM device CR50 revision 0
372 00:25:56.349693 tlcl_send_startup: Startup return code is 0
373 00:25:56.349742 TPM: setup succeeded
374 00:25:56.349792 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 00:25:56.349842 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 00:25:56.349892 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 00:25:56.349943 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 00:25:56.349992 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 00:25:56.350043 in-header: 03 07 00 00 08 00 00 00
380 00:25:56.350093 in-data: aa e4 47 04 13 02 00 00
381 00:25:56.350143 Chrome EC: UHEPI supported
382 00:25:56.350192 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 00:25:56.350242 in-header: 03 a9 00 00 08 00 00 00
384 00:25:56.350292 in-data: 84 60 60 08 00 00 00 00
385 00:25:56.350341 Phase 1
386 00:25:56.350390 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 00:25:56.350440 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 00:25:56.350490 VB2:vb2_check_recovery() Recovery was requested manually
389 00:25:56.350540 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 00:25:56.350590 Recovery requested (1009000e)
391 00:25:56.350639 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 00:25:56.350689 tlcl_extend: response is 0
393 00:25:56.350739 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 00:25:56.350788 tlcl_extend: response is 0
395 00:25:56.350838 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 00:25:56.350887 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
397 00:25:56.350937 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 00:25:56.350987
399 00:25:56.351035
400 00:25:56.351084 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 00:25:56.351135 ARM64: Exception handlers installed.
402 00:25:56.351185 ARM64: Testing exception
403 00:25:56.351237 ARM64: Done test exception
404 00:25:56.351286 pmic_efuse_setting: Set efuses in 11 msecs
405 00:25:56.351335 pmwrap_interface_init: Select PMIF_VLD_RDY
406 00:25:56.351383 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 00:25:56.351433 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 00:25:56.351676 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 00:25:56.351747 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 00:25:56.351848 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 00:25:56.351947 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 00:25:56.352048 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 00:25:56.352147 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 00:25:56.352245 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 00:25:56.352343 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 00:25:56.352441 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 00:25:56.352539 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 00:25:56.352625 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 00:25:56.352724 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 00:25:56.352806 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 00:25:56.352886 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 00:25:56.352966 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 00:25:56.353045 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 00:25:56.353124 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 00:25:56.353203 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 00:25:56.353282 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 00:25:56.353361 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 00:25:56.353440 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 00:25:56.353519 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 00:25:56.353598 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 00:25:56.353677 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 00:25:56.353756 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 00:25:56.353834 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 00:25:56.353913 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 00:25:56.353991 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 00:25:56.354070 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 00:25:56.354148 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 00:25:56.354227 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 00:25:56.354305 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 00:25:56.354384 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 00:25:56.354462 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 00:25:56.354541 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 00:25:56.354619 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 00:25:56.354697 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 00:25:56.354775 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 00:25:56.354853 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 00:25:56.354931 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 00:25:56.355009 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 00:25:56.355087 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 00:25:56.355166 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 00:25:56.355247 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 00:25:56.355326 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 00:25:56.355404 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 00:25:56.355482 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 00:25:56.355560 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 00:25:56.355638 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 00:25:56.355718 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 00:25:56.355798 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 00:25:56.355877 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 00:25:56.355956 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 00:25:56.356036 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 00:25:56.356115 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 00:25:56.356194 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 00:25:56.356272 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:25:56.356351 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x39
466 00:25:56.356429 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 00:25:56.356508 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 00:25:56.356586 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 00:25:56.356668 [RTC]rtc_get_frequency_meter,154: input=15, output=794
470 00:25:56.356721 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
471 00:25:56.356771 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
472 00:25:56.356821 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
473 00:25:56.356872 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
474 00:25:56.356922 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
475 00:25:56.356972 ADC[4]: Raw value=897780 ID=7
476 00:25:56.357029 ADC[3]: Raw value=213070 ID=1
477 00:25:56.357081 RAM Code: 0x71
478 00:25:56.357131 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
479 00:25:56.357181 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
480 00:25:56.357422 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
481 00:25:56.357483 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
482 00:25:56.357534 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
483 00:25:56.357585 in-header: 03 07 00 00 08 00 00 00
484 00:25:56.357635 in-data: aa e4 47 04 13 02 00 00
485 00:25:56.357684 Chrome EC: UHEPI supported
486 00:25:56.357734 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
487 00:25:56.357784 in-header: 03 a9 00 00 08 00 00 00
488 00:25:56.357833 in-data: 84 60 60 08 00 00 00 00
489 00:25:56.357883 MRC: failed to locate region type 0.
490 00:25:56.357932 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
491 00:25:56.357982 DRAM-K: Running full calibration
492 00:25:56.358032 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
493 00:25:56.358081 header.status = 0x0
494 00:25:56.358130 header.version = 0x6 (expected: 0x6)
495 00:25:56.358183 header.size = 0xd00 (expected: 0xd00)
496 00:25:56.358234 header.flags = 0x0
497 00:25:56.358283 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
498 00:25:56.358333 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
499 00:25:56.358383 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
500 00:25:56.358433 dram_init: ddr_geometry: 2
501 00:25:56.358481 [EMI] MDL number = 2
502 00:25:56.358530 [EMI] Get MDL freq = 0
503 00:25:56.358579 dram_init: ddr_type: 0
504 00:25:56.358628 is_discrete_lpddr4: 1
505 00:25:56.358677 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
506 00:25:56.358727
507 00:25:56.358776
508 00:25:56.358824 [Bian_co] ETT version 0.0.0.1
509 00:25:56.358874 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
510 00:25:56.358923
511 00:25:56.358975 dramc_set_vcore_voltage set vcore to 650000
512 00:25:56.359025 Read voltage for 800, 4
513 00:25:56.359074 Vio18 = 0
514 00:25:56.359123 Vcore = 650000
515 00:25:56.359171 Vdram = 0
516 00:25:56.359220 Vddq = 0
517 00:25:56.359269 Vmddr = 0
518 00:25:56.359318 dram_init: config_dvfs: 1
519 00:25:56.359368 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
520 00:25:56.359418 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
521 00:25:56.359467 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
522 00:25:56.359517 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
523 00:25:56.359567 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
524 00:25:56.359616 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
525 00:25:56.359665 MEM_TYPE=3, freq_sel=18
526 00:25:56.359714 sv_algorithm_assistance_LP4_1600
527 00:25:56.359764 ============ PULL DRAM RESETB DOWN ============
528 00:25:56.359819 ========== PULL DRAM RESETB DOWN end =========
529 00:25:56.359869 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
530 00:25:56.359919 ===================================
531 00:25:56.359969 LPDDR4 DRAM CONFIGURATION
532 00:25:56.360017 ===================================
533 00:25:56.360067 EX_ROW_EN[0] = 0x0
534 00:25:56.360116 EX_ROW_EN[1] = 0x0
535 00:25:56.360165 LP4Y_EN = 0x0
536 00:25:56.360214 WORK_FSP = 0x0
537 00:25:56.360263 WL = 0x2
538 00:25:56.360314 RL = 0x2
539 00:25:56.360362 BL = 0x2
540 00:25:56.360411 RPST = 0x0
541 00:25:56.360460 RD_PRE = 0x0
542 00:25:56.360509 WR_PRE = 0x1
543 00:25:56.360558 WR_PST = 0x0
544 00:25:56.360607 DBI_WR = 0x0
545 00:25:56.360663 DBI_RD = 0x0
546 00:25:56.360714 OTF = 0x1
547 00:25:56.360764 ===================================
548 00:25:56.360814 ===================================
549 00:25:56.360864 ANA top config
550 00:25:56.360913 ===================================
551 00:25:56.360962 DLL_ASYNC_EN = 0
552 00:25:56.361012 ALL_SLAVE_EN = 1
553 00:25:56.361061 NEW_RANK_MODE = 1
554 00:25:56.361111 DLL_IDLE_MODE = 1
555 00:25:56.361160 LP45_APHY_COMB_EN = 1
556 00:25:56.361209 TX_ODT_DIS = 1
557 00:25:56.361259 NEW_8X_MODE = 1
558 00:25:56.361308 ===================================
559 00:25:56.361357 ===================================
560 00:25:56.361407 data_rate = 1600
561 00:25:56.361456 CKR = 1
562 00:25:56.361505 DQ_P2S_RATIO = 8
563 00:25:56.361554 ===================================
564 00:25:56.361603 CA_P2S_RATIO = 8
565 00:25:56.361653 DQ_CA_OPEN = 0
566 00:25:56.361709 DQ_SEMI_OPEN = 0
567 00:25:56.361759 CA_SEMI_OPEN = 0
568 00:25:56.361808 CA_FULL_RATE = 0
569 00:25:56.361861 DQ_CKDIV4_EN = 1
570 00:25:56.361915 CA_CKDIV4_EN = 1
571 00:25:56.361965 CA_PREDIV_EN = 0
572 00:25:56.362014 PH8_DLY = 0
573 00:25:56.362063 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
574 00:25:56.362111 DQ_AAMCK_DIV = 4
575 00:25:56.362161 CA_AAMCK_DIV = 4
576 00:25:56.362210 CA_ADMCK_DIV = 4
577 00:25:56.362259 DQ_TRACK_CA_EN = 0
578 00:25:56.362308 CA_PICK = 800
579 00:25:56.362357 CA_MCKIO = 800
580 00:25:56.362406 MCKIO_SEMI = 0
581 00:25:56.362455 PLL_FREQ = 3068
582 00:25:56.362504 DQ_UI_PI_RATIO = 32
583 00:25:56.362553 CA_UI_PI_RATIO = 0
584 00:25:56.362603 ===================================
585 00:25:56.362652 ===================================
586 00:25:56.362702 memory_type:LPDDR4
587 00:25:56.362751 GP_NUM : 10
588 00:25:56.362800 SRAM_EN : 1
589 00:25:56.362849 MD32_EN : 0
590 00:25:56.362899 ===================================
591 00:25:56.362948 [ANA_INIT] >>>>>>>>>>>>>>
592 00:25:56.362996 <<<<<< [CONFIGURE PHASE]: ANA_TX
593 00:25:56.363051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
594 00:25:56.363101 ===================================
595 00:25:56.363151 data_rate = 1600,PCW = 0X7600
596 00:25:56.363200 ===================================
597 00:25:56.363249 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
598 00:25:56.363298 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
599 00:25:56.363348 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 00:25:56.363602 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
601 00:25:56.363702 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
602 00:25:56.363800 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
603 00:25:56.363900 [ANA_INIT] flow start
604 00:25:56.363998 [ANA_INIT] PLL >>>>>>>>
605 00:25:56.364096 [ANA_INIT] PLL <<<<<<<<
606 00:25:56.364193 [ANA_INIT] MIDPI >>>>>>>>
607 00:25:56.364291 [ANA_INIT] MIDPI <<<<<<<<
608 00:25:56.364388 [ANA_INIT] DLL >>>>>>>>
609 00:25:56.364475 [ANA_INIT] flow end
610 00:25:56.364554 ============ LP4 DIFF to SE enter ============
611 00:25:56.364633 ============ LP4 DIFF to SE exit ============
612 00:25:56.364722 [ANA_INIT] <<<<<<<<<<<<<
613 00:25:56.364800 [Flow] Enable top DCM control >>>>>
614 00:25:56.364878 [Flow] Enable top DCM control <<<<<
615 00:25:56.364955 Enable DLL master slave shuffle
616 00:25:56.365033 ==============================================================
617 00:25:56.365112 Gating Mode config
618 00:25:56.365190 ==============================================================
619 00:25:56.365268 Config description:
620 00:25:56.365348 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
621 00:25:56.365428 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
622 00:25:56.365508 SELPH_MODE 0: By rank 1: By Phase
623 00:25:56.365592 ==============================================================
624 00:25:56.365673 GAT_TRACK_EN = 1
625 00:25:56.365751 RX_GATING_MODE = 2
626 00:25:56.365829 RX_GATING_TRACK_MODE = 2
627 00:25:56.365907 SELPH_MODE = 1
628 00:25:56.365985 PICG_EARLY_EN = 1
629 00:25:56.366062 VALID_LAT_VALUE = 1
630 00:25:56.366141 ==============================================================
631 00:25:56.366220 Enter into Gating configuration >>>>
632 00:25:56.366298 Exit from Gating configuration <<<<
633 00:25:56.366376 Enter into DVFS_PRE_config >>>>>
634 00:25:56.366456 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
635 00:25:56.366538 Exit from DVFS_PRE_config <<<<<
636 00:25:56.366616 Enter into PICG configuration >>>>
637 00:25:56.366694 Exit from PICG configuration <<<<
638 00:25:56.366772 [RX_INPUT] configuration >>>>>
639 00:25:56.366849 [RX_INPUT] configuration <<<<<
640 00:25:56.366927 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
641 00:25:56.367006 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
642 00:25:56.367085 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
643 00:25:56.367150 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
644 00:25:56.367230 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
645 00:25:56.367310 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
646 00:25:56.367389 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
647 00:25:56.367474 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
648 00:25:56.367553 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
649 00:25:56.367632 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
650 00:25:56.367711 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
651 00:25:56.367789 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
652 00:25:56.367867 ===================================
653 00:25:56.367945 LPDDR4 DRAM CONFIGURATION
654 00:25:56.368023 ===================================
655 00:25:56.368103 EX_ROW_EN[0] = 0x0
656 00:25:56.368181 EX_ROW_EN[1] = 0x0
657 00:25:56.368258 LP4Y_EN = 0x0
658 00:25:56.368335 WORK_FSP = 0x0
659 00:25:56.368412 WL = 0x2
660 00:25:56.368489 RL = 0x2
661 00:25:56.368566 BL = 0x2
662 00:25:56.368647 RPST = 0x0
663 00:25:56.368702 RD_PRE = 0x0
664 00:25:56.368751 WR_PRE = 0x1
665 00:25:56.368800 WR_PST = 0x0
666 00:25:56.368849 DBI_WR = 0x0
667 00:25:56.368899 DBI_RD = 0x0
668 00:25:56.368947 OTF = 0x1
669 00:25:56.368997 ===================================
670 00:25:56.369046 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
671 00:25:56.369095 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
672 00:25:56.369144 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
673 00:25:56.369195 ===================================
674 00:25:56.369244 LPDDR4 DRAM CONFIGURATION
675 00:25:56.369293 ===================================
676 00:25:56.369342 EX_ROW_EN[0] = 0x10
677 00:25:56.369392 EX_ROW_EN[1] = 0x0
678 00:25:56.369441 LP4Y_EN = 0x0
679 00:25:56.369490 WORK_FSP = 0x0
680 00:25:56.369539 WL = 0x2
681 00:25:56.369588 RL = 0x2
682 00:25:56.369637 BL = 0x2
683 00:25:56.369685 RPST = 0x0
684 00:25:56.369733 RD_PRE = 0x0
685 00:25:56.369782 WR_PRE = 0x1
686 00:25:56.369830 WR_PST = 0x0
687 00:25:56.369879 DBI_WR = 0x0
688 00:25:56.369928 DBI_RD = 0x0
689 00:25:56.369977 OTF = 0x1
690 00:25:56.370026 ===================================
691 00:25:56.370076 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
692 00:25:56.370125 nWR fixed to 40
693 00:25:56.370176 [ModeRegInit_LP4] CH0 RK0
694 00:25:56.370225 [ModeRegInit_LP4] CH0 RK1
695 00:25:56.370274 [ModeRegInit_LP4] CH1 RK0
696 00:25:56.370323 [ModeRegInit_LP4] CH1 RK1
697 00:25:56.370372 match AC timing 13
698 00:25:56.370421 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
699 00:25:56.370470 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
700 00:25:56.370520 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
701 00:25:56.370570 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
702 00:25:56.370620 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
703 00:25:56.370669 [EMI DOE] emi_dcm 0
704 00:25:56.370718 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
705 00:25:56.370767 ==
706 00:25:56.370817 Dram Type= 6, Freq= 0, CH_0, rank 0
707 00:25:56.370867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
708 00:25:56.370916 ==
709 00:25:56.371162 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
710 00:25:56.371219 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
711 00:25:56.371271 [CA 0] Center 38 (7~69) winsize 63
712 00:25:56.371321 [CA 1] Center 37 (7~68) winsize 62
713 00:25:56.371376 [CA 2] Center 35 (5~66) winsize 62
714 00:25:56.371426 [CA 3] Center 35 (5~66) winsize 62
715 00:25:56.371476 [CA 4] Center 34 (4~65) winsize 62
716 00:25:56.371525 [CA 5] Center 34 (4~65) winsize 62
717 00:25:56.371574
718 00:25:56.371624 [CmdBusTrainingLP45] Vref(ca) range 1: 32
719 00:25:56.371673
720 00:25:56.371722 [CATrainingPosCal] consider 1 rank data
721 00:25:56.371772 u2DelayCellTimex100 = 270/100 ps
722 00:25:56.371821 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
723 00:25:56.371871 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
724 00:25:56.371920 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
725 00:25:56.371969 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
726 00:25:56.372019 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
727 00:25:56.372068 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
728 00:25:56.372116
729 00:25:56.372165 CA PerBit enable=1, Macro0, CA PI delay=34
730 00:25:56.372214
731 00:25:56.372262 [CBTSetCACLKResult] CA Dly = 34
732 00:25:56.372312 CS Dly: 6 (0~37)
733 00:25:56.372361 ==
734 00:25:56.372410 Dram Type= 6, Freq= 0, CH_0, rank 1
735 00:25:56.372459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
736 00:25:56.372509 ==
737 00:25:56.372558 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
738 00:25:56.372608 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
739 00:25:56.372672 [CA 0] Center 38 (7~69) winsize 63
740 00:25:56.372728 [CA 1] Center 38 (7~69) winsize 63
741 00:25:56.372778 [CA 2] Center 35 (5~66) winsize 62
742 00:25:56.372828 [CA 3] Center 35 (5~66) winsize 62
743 00:25:56.372878 [CA 4] Center 34 (4~65) winsize 62
744 00:25:56.372928 [CA 5] Center 34 (4~65) winsize 62
745 00:25:56.372977
746 00:25:56.373026 [CmdBusTrainingLP45] Vref(ca) range 1: 34
747 00:25:56.373075
748 00:25:56.373125 [CATrainingPosCal] consider 2 rank data
749 00:25:56.373174 u2DelayCellTimex100 = 270/100 ps
750 00:25:56.373224 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
751 00:25:56.373274 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
752 00:25:56.373323 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
753 00:25:56.373373 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
754 00:25:56.373423 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
755 00:25:56.373472 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
756 00:25:56.373521
757 00:25:56.373570 CA PerBit enable=1, Macro0, CA PI delay=34
758 00:25:56.373620
759 00:25:56.373669 [CBTSetCACLKResult] CA Dly = 34
760 00:25:56.373718 CS Dly: 6 (0~38)
761 00:25:56.373768
762 00:25:56.373817 ----->DramcWriteLeveling(PI) begin...
763 00:25:56.373870 ==
764 00:25:56.373919 Dram Type= 6, Freq= 0, CH_0, rank 0
765 00:25:56.373969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
766 00:25:56.374019 ==
767 00:25:56.374068 Write leveling (Byte 0): 30 => 30
768 00:25:56.374117 Write leveling (Byte 1): 31 => 31
769 00:25:56.374167 DramcWriteLeveling(PI) end<-----
770 00:25:56.374215
771 00:25:56.374265 ==
772 00:25:56.374314 Dram Type= 6, Freq= 0, CH_0, rank 0
773 00:25:56.374364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 00:25:56.374414 ==
775 00:25:56.374463 [Gating] SW mode calibration
776 00:25:56.374512 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
777 00:25:56.374563 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
778 00:25:56.374613 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
779 00:25:56.374662 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 00:25:56.374712 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
781 00:25:56.374761 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
782 00:25:56.374810 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
783 00:25:56.374863 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 00:25:56.374914 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 00:25:56.374964 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 00:25:56.375013 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 00:25:56.375062 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 00:25:56.375111 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 00:25:56.375160 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:25:56.375210 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:25:56.375259 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:25:56.375308 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:25:56.375357 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 00:25:56.375407 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 00:25:56.375456 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
796 00:25:56.375506 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
797 00:25:56.375555 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
798 00:25:56.375604 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 00:25:56.375654 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 00:25:56.375703 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 00:25:56.375752 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 00:25:56.375801 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 00:25:56.375850 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 00:25:56.375899 0 9 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
805 00:25:56.375948 0 9 12 | B1->B0 | 2828 3131 | 0 0 | (0 0) (1 1)
806 00:25:56.375997 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
807 00:25:56.376047 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 00:25:56.376096 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 00:25:56.376146 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 00:25:56.376195 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 00:25:56.376245 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 00:25:56.376294 0 10 8 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
813 00:25:56.376343 0 10 12 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
814 00:25:56.376392 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 00:25:56.376651 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 00:25:56.376756 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 00:25:56.376853 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 00:25:56.376953 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 00:25:56.377052 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 00:25:56.377150 0 11 8 | B1->B0 | 2525 2d2d | 0 1 | (0 0) (0 0)
821 00:25:56.377248 0 11 12 | B1->B0 | 3232 4040 | 0 0 | (0 0) (0 0)
822 00:25:56.377346 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
823 00:25:56.377444 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 00:25:56.377541 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 00:25:56.377639 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 00:25:56.377724 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 00:25:56.377811 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 00:25:56.377893 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
829 00:25:56.377971 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
830 00:25:56.378050 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
831 00:25:56.378128 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 00:25:56.378206 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 00:25:56.378281 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 00:25:56.378332 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 00:25:56.378382 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 00:25:56.378431 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 00:25:56.378480 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 00:25:56.378530 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 00:25:56.378579 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 00:25:56.378628 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 00:25:56.378678 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 00:25:56.378728 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 00:25:56.378777 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 00:25:56.378826 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
845 00:25:56.378875 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
846 00:25:56.378924 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 00:25:56.378974 Total UI for P1: 0, mck2ui 16
848 00:25:56.379023 best dqsien dly found for B0: ( 0, 14, 10)
849 00:25:56.379073 Total UI for P1: 0, mck2ui 16
850 00:25:56.379122 best dqsien dly found for B1: ( 0, 14, 12)
851 00:25:56.379171 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
852 00:25:56.379220 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
853 00:25:56.379269
854 00:25:56.379317 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
855 00:25:56.379367 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
856 00:25:56.379416 [Gating] SW calibration Done
857 00:25:56.379466 ==
858 00:25:56.379515 Dram Type= 6, Freq= 0, CH_0, rank 0
859 00:25:56.379565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
860 00:25:56.379614 ==
861 00:25:56.379663 RX Vref Scan: 0
862 00:25:56.379712
863 00:25:56.379761 RX Vref 0 -> 0, step: 1
864 00:25:56.379810
865 00:25:56.379859 RX Delay -130 -> 252, step: 16
866 00:25:56.379909 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
867 00:25:56.379958 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
868 00:25:56.380007 iDelay=206, Bit 2, Center 77 (-50 ~ 205) 256
869 00:25:56.380056 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
870 00:25:56.380105 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
871 00:25:56.380154 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
872 00:25:56.380203 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
873 00:25:56.380252 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
874 00:25:56.380301 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
875 00:25:56.380350 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
876 00:25:56.380400 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
877 00:25:56.380449 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
878 00:25:56.380498 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
879 00:25:56.380547 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
880 00:25:56.380597 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
881 00:25:56.380651 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
882 00:25:56.380703 ==
883 00:25:56.380753 Dram Type= 6, Freq= 0, CH_0, rank 0
884 00:25:56.380803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
885 00:25:56.380854 ==
886 00:25:56.380902 DQS Delay:
887 00:25:56.380952 DQS0 = 0, DQS1 = 0
888 00:25:56.381001 DQM Delay:
889 00:25:56.381050 DQM0 = 78, DQM1 = 69
890 00:25:56.381100 DQ Delay:
891 00:25:56.381148 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
892 00:25:56.381198 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =85
893 00:25:56.381247 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
894 00:25:56.381317 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
895 00:25:56.381396
896 00:25:56.381454
897 00:25:56.381505 ==
898 00:25:56.381555 Dram Type= 6, Freq= 0, CH_0, rank 0
899 00:25:56.381604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
900 00:25:56.381653 ==
901 00:25:56.381702
902 00:25:56.381750
903 00:25:56.381798 TX Vref Scan disable
904 00:25:56.381848 == TX Byte 0 ==
905 00:25:56.381897 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
906 00:25:56.381947 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
907 00:25:56.381997 == TX Byte 1 ==
908 00:25:56.382046 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
909 00:25:56.382095 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
910 00:25:56.382144 ==
911 00:25:56.382193 Dram Type= 6, Freq= 0, CH_0, rank 0
912 00:25:56.382242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 00:25:56.382292 ==
914 00:25:56.382341 TX Vref=22, minBit 5, minWin=26, winSum=429
915 00:25:56.382391 TX Vref=24, minBit 11, minWin=26, winSum=434
916 00:25:56.382441 TX Vref=26, minBit 1, minWin=27, winSum=440
917 00:25:56.382490 TX Vref=28, minBit 5, minWin=27, winSum=442
918 00:25:56.382540 TX Vref=30, minBit 2, minWin=27, winSum=441
919 00:25:56.382589 TX Vref=32, minBit 1, minWin=27, winSum=440
920 00:25:56.382637 [TxChooseVref] Worse bit 5, Min win 27, Win sum 442, Final Vref 28
921 00:25:56.382686
922 00:25:56.382735 Final TX Range 1 Vref 28
923 00:25:56.382785
924 00:25:56.382833 ==
925 00:25:56.382882 Dram Type= 6, Freq= 0, CH_0, rank 0
926 00:25:56.383127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 00:25:56.383215 ==
928 00:25:56.383293
929 00:25:56.383370
930 00:25:56.383453 TX Vref Scan disable
931 00:25:56.383507 == TX Byte 0 ==
932 00:25:56.383557 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
933 00:25:56.383608 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
934 00:25:56.383658 == TX Byte 1 ==
935 00:25:56.383707 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
936 00:25:56.383756 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
937 00:25:56.383805
938 00:25:56.383854 [DATLAT]
939 00:25:56.383904 Freq=800, CH0 RK0
940 00:25:56.383953
941 00:25:56.384002 DATLAT Default: 0xa
942 00:25:56.384051 0, 0xFFFF, sum = 0
943 00:25:56.384102 1, 0xFFFF, sum = 0
944 00:25:56.384152 2, 0xFFFF, sum = 0
945 00:25:56.384202 3, 0xFFFF, sum = 0
946 00:25:56.384254 4, 0xFFFF, sum = 0
947 00:25:56.384305 5, 0xFFFF, sum = 0
948 00:25:56.384355 6, 0xFFFF, sum = 0
949 00:25:56.384421 7, 0xFFFF, sum = 0
950 00:25:56.384475 8, 0xFFFF, sum = 0
951 00:25:56.384526 9, 0x0, sum = 1
952 00:25:56.384575 10, 0x0, sum = 2
953 00:25:56.384626 11, 0x0, sum = 3
954 00:25:56.384685 12, 0x0, sum = 4
955 00:25:56.384737 best_step = 10
956 00:25:56.384789
957 00:25:56.384839 ==
958 00:25:56.384889 Dram Type= 6, Freq= 0, CH_0, rank 0
959 00:25:56.384939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 00:25:56.384989 ==
961 00:25:56.385038 RX Vref Scan: 1
962 00:25:56.385087
963 00:25:56.385136 Set Vref Range= 32 -> 127
964 00:25:56.385185
965 00:25:56.385234 RX Vref 32 -> 127, step: 1
966 00:25:56.385284
967 00:25:56.385332 RX Delay -111 -> 252, step: 8
968 00:25:56.385382
969 00:25:56.385431 Set Vref, RX VrefLevel [Byte0]: 32
970 00:25:56.385480 [Byte1]: 32
971 00:25:56.385529
972 00:25:56.385577 Set Vref, RX VrefLevel [Byte0]: 33
973 00:25:56.385626 [Byte1]: 33
974 00:25:56.385675
975 00:25:56.385724 Set Vref, RX VrefLevel [Byte0]: 34
976 00:25:56.385774 [Byte1]: 34
977 00:25:56.385823
978 00:25:56.385872 Set Vref, RX VrefLevel [Byte0]: 35
979 00:25:56.385921 [Byte1]: 35
980 00:25:56.385970
981 00:25:56.386018 Set Vref, RX VrefLevel [Byte0]: 36
982 00:25:56.386067 [Byte1]: 36
983 00:25:56.386116
984 00:25:56.386164 Set Vref, RX VrefLevel [Byte0]: 37
985 00:25:56.386214 [Byte1]: 37
986 00:25:56.386264
987 00:25:56.386313 Set Vref, RX VrefLevel [Byte0]: 38
988 00:25:56.386362 [Byte1]: 38
989 00:25:56.386411
990 00:25:56.386460 Set Vref, RX VrefLevel [Byte0]: 39
991 00:25:56.386508 [Byte1]: 39
992 00:25:56.386557
993 00:25:56.386605 Set Vref, RX VrefLevel [Byte0]: 40
994 00:25:56.386654 [Byte1]: 40
995 00:25:56.386703
996 00:25:56.386753 Set Vref, RX VrefLevel [Byte0]: 41
997 00:25:56.386802 [Byte1]: 41
998 00:25:56.386850
999 00:25:56.386898 Set Vref, RX VrefLevel [Byte0]: 42
1000 00:25:56.386947 [Byte1]: 42
1001 00:25:56.386996
1002 00:25:56.387045 Set Vref, RX VrefLevel [Byte0]: 43
1003 00:25:56.387094 [Byte1]: 43
1004 00:25:56.387142
1005 00:25:56.387191 Set Vref, RX VrefLevel [Byte0]: 44
1006 00:25:56.387240 [Byte1]: 44
1007 00:25:56.387289
1008 00:25:56.387338 Set Vref, RX VrefLevel [Byte0]: 45
1009 00:25:56.387395 [Byte1]: 45
1010 00:25:56.387448
1011 00:25:56.387498 Set Vref, RX VrefLevel [Byte0]: 46
1012 00:25:56.387548 [Byte1]: 46
1013 00:25:56.387597
1014 00:25:56.387646 Set Vref, RX VrefLevel [Byte0]: 47
1015 00:25:56.387696 [Byte1]: 47
1016 00:25:56.387745
1017 00:25:56.387795 Set Vref, RX VrefLevel [Byte0]: 48
1018 00:25:56.387845 [Byte1]: 48
1019 00:25:56.387893
1020 00:25:56.387942 Set Vref, RX VrefLevel [Byte0]: 49
1021 00:25:56.387991 [Byte1]: 49
1022 00:25:56.388042
1023 00:25:56.388098 Set Vref, RX VrefLevel [Byte0]: 50
1024 00:25:56.388149 [Byte1]: 50
1025 00:25:56.388198
1026 00:25:56.388247 Set Vref, RX VrefLevel [Byte0]: 51
1027 00:25:56.388297 [Byte1]: 51
1028 00:25:56.388346
1029 00:25:56.388395 Set Vref, RX VrefLevel [Byte0]: 52
1030 00:25:56.388444 [Byte1]: 52
1031 00:25:56.388493
1032 00:25:56.388542 Set Vref, RX VrefLevel [Byte0]: 53
1033 00:25:56.388591 [Byte1]: 53
1034 00:25:56.388640
1035 00:25:56.388699 Set Vref, RX VrefLevel [Byte0]: 54
1036 00:25:56.388753 [Byte1]: 54
1037 00:25:56.388804
1038 00:25:56.388853 Set Vref, RX VrefLevel [Byte0]: 55
1039 00:25:56.388907 [Byte1]: 55
1040 00:25:56.388978
1041 00:25:56.389029 Set Vref, RX VrefLevel [Byte0]: 56
1042 00:25:56.389079 [Byte1]: 56
1043 00:25:56.389128
1044 00:25:56.389177 Set Vref, RX VrefLevel [Byte0]: 57
1045 00:25:56.389227 [Byte1]: 57
1046 00:25:56.389275
1047 00:25:56.389324 Set Vref, RX VrefLevel [Byte0]: 58
1048 00:25:56.389374 [Byte1]: 58
1049 00:25:56.389423
1050 00:25:56.389472 Set Vref, RX VrefLevel [Byte0]: 59
1051 00:25:56.389521 [Byte1]: 59
1052 00:25:56.389569
1053 00:25:56.389617 Set Vref, RX VrefLevel [Byte0]: 60
1054 00:25:56.389666 [Byte1]: 60
1055 00:25:56.389715
1056 00:25:56.389771 Set Vref, RX VrefLevel [Byte0]: 61
1057 00:25:56.389822 [Byte1]: 61
1058 00:25:56.389871
1059 00:25:56.389942 Set Vref, RX VrefLevel [Byte0]: 62
1060 00:25:56.389993 [Byte1]: 62
1061 00:25:56.390042
1062 00:25:56.390092 Set Vref, RX VrefLevel [Byte0]: 63
1063 00:25:56.390141 [Byte1]: 63
1064 00:25:56.390190
1065 00:25:56.390239 Set Vref, RX VrefLevel [Byte0]: 64
1066 00:25:56.390288 [Byte1]: 64
1067 00:25:56.390337
1068 00:25:56.390387 Set Vref, RX VrefLevel [Byte0]: 65
1069 00:25:56.390435 [Byte1]: 65
1070 00:25:56.390484
1071 00:25:56.390533 Set Vref, RX VrefLevel [Byte0]: 66
1072 00:25:56.390582 [Byte1]: 66
1073 00:25:56.390631
1074 00:25:56.390680 Set Vref, RX VrefLevel [Byte0]: 67
1075 00:25:56.390729 [Byte1]: 67
1076 00:25:56.390778
1077 00:25:56.390826 Set Vref, RX VrefLevel [Byte0]: 68
1078 00:25:56.390875 [Byte1]: 68
1079 00:25:56.390924
1080 00:25:56.390972 Set Vref, RX VrefLevel [Byte0]: 69
1081 00:25:56.391021 [Byte1]: 69
1082 00:25:56.391069
1083 00:25:56.391119 Set Vref, RX VrefLevel [Byte0]: 70
1084 00:25:56.391168 [Byte1]: 70
1085 00:25:56.391218
1086 00:25:56.391274 Set Vref, RX VrefLevel [Byte0]: 71
1087 00:25:56.391325 [Byte1]: 71
1088 00:25:56.391374
1089 00:25:56.391452 Set Vref, RX VrefLevel [Byte0]: 72
1090 00:25:56.391526 [Byte1]: 72
1091 00:25:56.391577
1092 00:25:56.391626 Set Vref, RX VrefLevel [Byte0]: 73
1093 00:25:56.391677 [Byte1]: 73
1094 00:25:56.391727
1095 00:25:56.391777 Set Vref, RX VrefLevel [Byte0]: 74
1096 00:25:56.391826 [Byte1]: 74
1097 00:25:56.391875
1098 00:25:56.392120 Set Vref, RX VrefLevel [Byte0]: 75
1099 00:25:56.392219 [Byte1]: 75
1100 00:25:56.392317
1101 00:25:56.392415 Set Vref, RX VrefLevel [Byte0]: 76
1102 00:25:56.392513 [Byte1]: 76
1103 00:25:56.392610
1104 00:25:56.392717 Set Vref, RX VrefLevel [Byte0]: 77
1105 00:25:56.392815 [Byte1]: 77
1106 00:25:56.392912
1107 00:25:56.393008 Set Vref, RX VrefLevel [Byte0]: 78
1108 00:25:56.393087 [Byte1]: 78
1109 00:25:56.393165
1110 00:25:56.393242 Set Vref, RX VrefLevel [Byte0]: 79
1111 00:25:56.393321 [Byte1]: 79
1112 00:25:56.393397
1113 00:25:56.393475 Set Vref, RX VrefLevel [Byte0]: 80
1114 00:25:56.393553 [Byte1]: 80
1115 00:25:56.393636
1116 00:25:56.393714 Final RX Vref Byte 0 = 60 to rank0
1117 00:25:56.393792 Final RX Vref Byte 1 = 60 to rank0
1118 00:25:56.393871 Final RX Vref Byte 0 = 60 to rank1
1119 00:25:56.393948 Final RX Vref Byte 1 = 60 to rank1==
1120 00:25:56.394027 Dram Type= 6, Freq= 0, CH_0, rank 0
1121 00:25:56.394106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1122 00:25:56.394184 ==
1123 00:25:56.394261 DQS Delay:
1124 00:25:56.394338 DQS0 = 0, DQS1 = 0
1125 00:25:56.394416 DQM Delay:
1126 00:25:56.394493 DQM0 = 82, DQM1 = 67
1127 00:25:56.394573 DQ Delay:
1128 00:25:56.394640 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1129 00:25:56.394694 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1130 00:25:56.394745 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1131 00:25:56.394795 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1132 00:25:56.394845
1133 00:25:56.394894
1134 00:25:56.394943 [DQSOSCAuto] RK0, (LSB)MR18= 0x2928, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1135 00:25:56.394994 CH0 RK0: MR19=606, MR18=2928
1136 00:25:56.395044 CH0_RK0: MR19=0x606, MR18=0x2928, DQSOSC=399, MR23=63, INC=92, DEC=61
1137 00:25:56.395093
1138 00:25:56.395141 ----->DramcWriteLeveling(PI) begin...
1139 00:25:56.395192 ==
1140 00:25:56.395241 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 00:25:56.395292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 00:25:56.395341 ==
1143 00:25:56.395390 Write leveling (Byte 0): 33 => 33
1144 00:25:56.395440 Write leveling (Byte 1): 29 => 29
1145 00:25:56.395490 DramcWriteLeveling(PI) end<-----
1146 00:25:56.395539
1147 00:25:56.395587 ==
1148 00:25:56.395636 Dram Type= 6, Freq= 0, CH_0, rank 1
1149 00:25:56.395686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1150 00:25:56.395736 ==
1151 00:25:56.395785 [Gating] SW mode calibration
1152 00:25:56.395834 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1153 00:25:56.395884 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1154 00:25:56.395934 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1155 00:25:56.395984 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1156 00:25:56.396033 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1157 00:25:56.396082 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 00:25:56.396131 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 00:25:56.396181 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 00:25:56.396230 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 00:25:56.396279 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 00:25:56.396328 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 00:25:56.396378 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 00:25:56.396426 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 00:25:56.396475 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 00:25:56.396524 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 00:25:56.396574 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 00:25:56.396623 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 00:25:56.396682 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 00:25:56.396732 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 00:25:56.396782 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1172 00:25:56.396832 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1173 00:25:56.396880 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1174 00:25:56.396929 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 00:25:56.396979 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 00:25:56.397029 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 00:25:56.397079 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 00:25:56.397129 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 00:25:56.397179 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 00:25:56.397229 0 9 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
1181 00:25:56.397278 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (1 1) (1 1)
1182 00:25:56.397328 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 00:25:56.397377 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 00:25:56.397427 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 00:25:56.397477 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 00:25:56.397526 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 00:25:56.397575 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 0)
1188 00:25:56.397624 0 10 8 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (0 0)
1189 00:25:56.397673 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 00:25:56.397722 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 00:25:56.397771 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 00:25:56.397820 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 00:25:56.397869 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 00:25:56.397919 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 00:25:56.397974 0 11 4 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (1 1)
1196 00:25:56.398025 0 11 8 | B1->B0 | 2b2b 4040 | 0 1 | (1 1) (0 0)
1197 00:25:56.398074 0 11 12 | B1->B0 | 4342 4646 | 1 0 | (0 0) (0 0)
1198 00:25:56.398124 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 00:25:56.398173 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 00:25:56.398223 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 00:25:56.398272 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 00:25:56.398521 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 00:25:56.398578 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1204 00:25:56.398628 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1205 00:25:56.398678 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 00:25:56.398728 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 00:25:56.398778 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 00:25:56.398828 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 00:25:56.398878 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 00:25:56.398927 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 00:25:56.398977 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 00:25:56.399026 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 00:25:56.399076 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 00:25:56.399125 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 00:25:56.399175 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 00:25:56.399224 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 00:25:56.399273 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 00:25:56.399323 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 00:25:56.399372 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 00:25:56.399422 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1221 00:25:56.399471 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 00:25:56.399521 Total UI for P1: 0, mck2ui 16
1223 00:25:56.399571 best dqsien dly found for B0: ( 0, 14, 8)
1224 00:25:56.399621 Total UI for P1: 0, mck2ui 16
1225 00:25:56.399671 best dqsien dly found for B1: ( 0, 14, 10)
1226 00:25:56.399721 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1227 00:25:56.399771 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1228 00:25:56.399820
1229 00:25:56.399869 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1230 00:25:56.399919 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1231 00:25:56.399968 [Gating] SW calibration Done
1232 00:25:56.400017 ==
1233 00:25:56.400067 Dram Type= 6, Freq= 0, CH_0, rank 1
1234 00:25:56.400116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1235 00:25:56.400166 ==
1236 00:25:56.400215 RX Vref Scan: 0
1237 00:25:56.400264
1238 00:25:56.400313 RX Vref 0 -> 0, step: 1
1239 00:25:56.400363
1240 00:25:56.400410 RX Delay -130 -> 252, step: 16
1241 00:25:56.400460 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1242 00:25:56.400530 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1243 00:25:56.400611 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1244 00:25:56.400683 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1245 00:25:56.400751 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1246 00:25:56.400827 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1247 00:25:56.400880 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1248 00:25:56.400931 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1249 00:25:56.400980 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1250 00:25:56.401030 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1251 00:25:56.401079 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1252 00:25:56.401128 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1253 00:25:56.401178 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1254 00:25:56.401227 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1255 00:25:56.401276 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1256 00:25:56.401325 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1257 00:25:56.401374 ==
1258 00:25:56.401423 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 00:25:56.401473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1260 00:25:56.401522 ==
1261 00:25:56.401572 DQS Delay:
1262 00:25:56.401625 DQS0 = 0, DQS1 = 0
1263 00:25:56.401676 DQM Delay:
1264 00:25:56.401725 DQM0 = 81, DQM1 = 69
1265 00:25:56.401775 DQ Delay:
1266 00:25:56.401824 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =69
1267 00:25:56.401873 DQ4 =85, DQ5 =61, DQ6 =93, DQ7 =93
1268 00:25:56.401922 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1269 00:25:56.401972 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1270 00:25:56.402020
1271 00:25:56.402069
1272 00:25:56.402117 ==
1273 00:25:56.402165 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 00:25:56.402214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 00:25:56.402263 ==
1276 00:25:56.402312
1277 00:25:56.402361
1278 00:25:56.402409 TX Vref Scan disable
1279 00:25:56.402458 == TX Byte 0 ==
1280 00:25:56.402508 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1281 00:25:56.402557 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1282 00:25:56.402607 == TX Byte 1 ==
1283 00:25:56.402657 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1284 00:25:56.402706 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1285 00:25:56.402755 ==
1286 00:25:56.402804 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 00:25:56.402854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 00:25:56.402903 ==
1289 00:25:56.402952 TX Vref=22, minBit 1, minWin=27, winSum=438
1290 00:25:56.403001 TX Vref=24, minBit 2, minWin=26, winSum=441
1291 00:25:56.403051 TX Vref=26, minBit 1, minWin=27, winSum=441
1292 00:25:56.403101 TX Vref=28, minBit 1, minWin=27, winSum=442
1293 00:25:56.403151 TX Vref=30, minBit 9, minWin=27, winSum=446
1294 00:25:56.403199 TX Vref=32, minBit 9, minWin=27, winSum=444
1295 00:25:56.403248 [TxChooseVref] Worse bit 9, Min win 27, Win sum 446, Final Vref 30
1296 00:25:56.403298
1297 00:25:56.403346 Final TX Range 1 Vref 30
1298 00:25:56.403394
1299 00:25:56.403443 ==
1300 00:25:56.403491 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 00:25:56.403539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 00:25:56.403588 ==
1303 00:25:56.403636
1304 00:25:56.403684
1305 00:25:56.403732 TX Vref Scan disable
1306 00:25:56.403780 == TX Byte 0 ==
1307 00:25:56.403830 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1308 00:25:56.403879 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1309 00:25:56.403929 == TX Byte 1 ==
1310 00:25:56.403978 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1311 00:25:56.404027 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1312 00:25:56.404075
1313 00:25:56.404123 [DATLAT]
1314 00:25:56.404170 Freq=800, CH0 RK1
1315 00:25:56.404219
1316 00:25:56.404266 DATLAT Default: 0xa
1317 00:25:56.404315 0, 0xFFFF, sum = 0
1318 00:25:56.404365 1, 0xFFFF, sum = 0
1319 00:25:56.404414 2, 0xFFFF, sum = 0
1320 00:25:56.404464 3, 0xFFFF, sum = 0
1321 00:25:56.404513 4, 0xFFFF, sum = 0
1322 00:25:56.404568 5, 0xFFFF, sum = 0
1323 00:25:56.404653 6, 0xFFFF, sum = 0
1324 00:25:56.404707 7, 0xFFFF, sum = 0
1325 00:25:56.404757 8, 0xFFFF, sum = 0
1326 00:25:56.404806 9, 0x0, sum = 1
1327 00:25:56.404855 10, 0x0, sum = 2
1328 00:25:56.404904 11, 0x0, sum = 3
1329 00:25:56.404953 12, 0x0, sum = 4
1330 00:25:56.405002 best_step = 10
1331 00:25:56.405051
1332 00:25:56.405099 ==
1333 00:25:56.405343 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 00:25:56.405442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 00:25:56.405540 ==
1336 00:25:56.405636 RX Vref Scan: 0
1337 00:25:56.405733
1338 00:25:56.405829 RX Vref 0 -> 0, step: 1
1339 00:25:56.405920
1340 00:25:56.406001 RX Delay -111 -> 252, step: 8
1341 00:25:56.406080 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1342 00:25:56.406159 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1343 00:25:56.406218 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1344 00:25:56.406268 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1345 00:25:56.406319 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1346 00:25:56.406369 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1347 00:25:56.406418 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1348 00:25:56.406467 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1349 00:25:56.406515 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1350 00:25:56.406564 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1351 00:25:56.406612 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1352 00:25:56.406661 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1353 00:25:56.406709 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1354 00:25:56.406757 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1355 00:25:56.406806 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1356 00:25:56.406854 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1357 00:25:56.406903 ==
1358 00:25:56.406951 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 00:25:56.407000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 00:25:56.407050 ==
1361 00:25:56.407098 DQS Delay:
1362 00:25:56.407145 DQS0 = 0, DQS1 = 0
1363 00:25:56.407194 DQM Delay:
1364 00:25:56.407242 DQM0 = 79, DQM1 = 70
1365 00:25:56.407290 DQ Delay:
1366 00:25:56.407339 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1367 00:25:56.407387 DQ4 =80, DQ5 =64, DQ6 =92, DQ7 =88
1368 00:25:56.407436 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1369 00:25:56.407485 DQ12 =72, DQ13 =72, DQ14 =80, DQ15 =80
1370 00:25:56.407533
1371 00:25:56.407580
1372 00:25:56.407628 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
1373 00:25:56.407678 CH0 RK1: MR19=606, MR18=4C27
1374 00:25:56.407727 CH0_RK1: MR19=0x606, MR18=0x4C27, DQSOSC=390, MR23=63, INC=97, DEC=64
1375 00:25:56.407776 [RxdqsGatingPostProcess] freq 800
1376 00:25:56.407825 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1377 00:25:56.407875 Pre-setting of DQS Precalculation
1378 00:25:56.407925 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1379 00:25:56.407974 ==
1380 00:25:56.408021 Dram Type= 6, Freq= 0, CH_1, rank 0
1381 00:25:56.408069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 00:25:56.408117 ==
1383 00:25:56.408166 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1384 00:25:56.408215 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1385 00:25:56.408263 [CA 0] Center 36 (6~67) winsize 62
1386 00:25:56.408311 [CA 1] Center 36 (6~67) winsize 62
1387 00:25:56.408360 [CA 2] Center 34 (5~64) winsize 60
1388 00:25:56.408408 [CA 3] Center 34 (4~64) winsize 61
1389 00:25:56.408457 [CA 4] Center 34 (4~64) winsize 61
1390 00:25:56.408505 [CA 5] Center 34 (4~64) winsize 61
1391 00:25:56.408553
1392 00:25:56.408601 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1393 00:25:56.408660
1394 00:25:56.408784 [CATrainingPosCal] consider 1 rank data
1395 00:25:56.408860 u2DelayCellTimex100 = 270/100 ps
1396 00:25:56.408935 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1397 00:25:56.409011 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 00:25:56.409087 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1399 00:25:56.409195 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1400 00:25:56.409270 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1401 00:25:56.409345 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1402 00:25:56.409420
1403 00:25:56.409495 CA PerBit enable=1, Macro0, CA PI delay=34
1404 00:25:56.409587
1405 00:25:56.409678 [CBTSetCACLKResult] CA Dly = 34
1406 00:25:56.409753 CS Dly: 5 (0~36)
1407 00:25:56.409827 ==
1408 00:25:56.409906 Dram Type= 6, Freq= 0, CH_1, rank 1
1409 00:25:56.410000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 00:25:56.410090 ==
1411 00:25:56.410166 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1412 00:25:56.410243 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1413 00:25:56.410351 [CA 0] Center 36 (6~67) winsize 62
1414 00:25:56.410426 [CA 1] Center 36 (6~67) winsize 62
1415 00:25:56.410503 [CA 2] Center 34 (4~65) winsize 62
1416 00:25:56.410578 [CA 3] Center 33 (3~64) winsize 62
1417 00:25:56.410653 [CA 4] Center 34 (4~65) winsize 62
1418 00:25:56.410760 [CA 5] Center 33 (3~64) winsize 62
1419 00:25:56.410834
1420 00:25:56.410909 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1421 00:25:56.410984
1422 00:25:56.411093 [CATrainingPosCal] consider 2 rank data
1423 00:25:56.411168 u2DelayCellTimex100 = 270/100 ps
1424 00:25:56.411243 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1425 00:25:56.411318 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 00:25:56.411393 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1427 00:25:56.411487 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1428 00:25:56.411576 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1429 00:25:56.411653 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1430 00:25:56.411727
1431 00:25:56.411803 CA PerBit enable=1, Macro0, CA PI delay=34
1432 00:25:56.411911
1433 00:25:56.411962 [CBTSetCACLKResult] CA Dly = 34
1434 00:25:56.412011 CS Dly: 6 (0~38)
1435 00:25:56.412059
1436 00:25:56.412107 ----->DramcWriteLeveling(PI) begin...
1437 00:25:56.412157 ==
1438 00:25:56.412219 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 00:25:56.412267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 00:25:56.412314 ==
1441 00:25:56.412378 Write leveling (Byte 0): 27 => 27
1442 00:25:56.412441 Write leveling (Byte 1): 32 => 32
1443 00:25:56.412490 DramcWriteLeveling(PI) end<-----
1444 00:25:56.412538
1445 00:25:56.412585 ==
1446 00:25:56.412633 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 00:25:56.412720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 00:25:56.412784 ==
1449 00:25:56.412832 [Gating] SW mode calibration
1450 00:25:56.412881 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1451 00:25:56.412930 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1452 00:25:56.412980 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1453 00:25:56.413042 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 00:25:56.413105 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1455 00:25:56.413348 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 00:25:56.413403 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 00:25:56.413470 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 00:25:56.413533 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 00:25:56.413581 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 00:25:56.413629 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 00:25:56.413677 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 00:25:56.413725 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 00:25:56.413791 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 00:25:56.413853 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 00:25:56.413900 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 00:25:56.413947 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 00:25:56.413995 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 00:25:56.414043 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 00:25:56.414091 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1470 00:25:56.414156 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1471 00:25:56.414219 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 00:25:56.414267 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 00:25:56.414313 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 00:25:56.414361 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 00:25:56.414408 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 00:25:56.414473 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 00:25:56.414540 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 00:25:56.414588 0 9 8 | B1->B0 | 2525 2a2a | 0 0 | (0 0) (0 0)
1479 00:25:56.414636 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 00:25:56.414684 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 00:25:56.414732 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 00:25:56.414779 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 00:25:56.414844 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 00:25:56.414907 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 00:25:56.414956 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
1486 00:25:56.415003 0 10 8 | B1->B0 | 2f2f 2d2d | 0 1 | (0 1) (1 0)
1487 00:25:56.415050 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 00:25:56.415098 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 00:25:56.415146 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 00:25:56.415221 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 00:25:56.415285 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 00:25:56.415332 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 00:25:56.415380 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1494 00:25:56.415428 0 11 8 | B1->B0 | 3838 3737 | 0 0 | (0 0) (0 0)
1495 00:25:56.415475 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 00:25:56.415523 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 00:25:56.415588 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 00:25:56.415649 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 00:25:56.415697 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 00:25:56.415744 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 00:25:56.415792 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 00:25:56.415839 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1503 00:25:56.415887 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 00:25:56.415967 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 00:25:56.416015 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 00:25:56.416063 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 00:25:56.416110 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 00:25:56.416157 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 00:25:56.416204 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 00:25:56.416251 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 00:25:56.416315 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 00:25:56.416378 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 00:25:56.416426 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 00:25:56.416474 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 00:25:56.416522 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 00:25:56.416570 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 00:25:56.416618 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 00:25:56.416733 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1519 00:25:56.416810 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1520 00:25:56.416886 Total UI for P1: 0, mck2ui 16
1521 00:25:56.416956 best dqsien dly found for B1: ( 0, 14, 8)
1522 00:25:56.417007 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 00:25:56.417056 Total UI for P1: 0, mck2ui 16
1524 00:25:56.417104 best dqsien dly found for B0: ( 0, 14, 10)
1525 00:25:56.417155 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
1526 00:25:56.417204 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1527 00:25:56.417252
1528 00:25:56.417299 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
1529 00:25:56.417347 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1530 00:25:56.417395 [Gating] SW calibration Done
1531 00:25:56.417442 ==
1532 00:25:56.417490 Dram Type= 6, Freq= 0, CH_1, rank 0
1533 00:25:56.417537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1534 00:25:56.417589 ==
1535 00:25:56.417663 RX Vref Scan: 0
1536 00:25:56.417731
1537 00:25:56.417778 RX Vref 0 -> 0, step: 1
1538 00:25:56.417825
1539 00:25:56.417872 RX Delay -130 -> 252, step: 16
1540 00:25:56.417919 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1541 00:25:56.417967 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1542 00:25:56.418015 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1543 00:25:56.418100 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1544 00:25:56.418340 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1545 00:25:56.418433 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1546 00:25:56.418528 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1547 00:25:56.418623 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1548 00:25:56.418718 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1549 00:25:56.418811 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1550 00:25:56.418906 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1551 00:25:56.418999 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1552 00:25:56.419093 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1553 00:25:56.419186 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1554 00:25:56.419294 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1555 00:25:56.419405 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1556 00:25:56.419505 ==
1557 00:25:56.419587 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 00:25:56.419638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 00:25:56.419687 ==
1560 00:25:56.419764 DQS Delay:
1561 00:25:56.419812 DQS0 = 0, DQS1 = 0
1562 00:25:56.419861 DQM Delay:
1563 00:25:56.419909 DQM0 = 81, DQM1 = 71
1564 00:25:56.419957 DQ Delay:
1565 00:25:56.420020 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1566 00:25:56.420084 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1567 00:25:56.420132 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1568 00:25:56.420178 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1569 00:25:56.420226
1570 00:25:56.420272
1571 00:25:56.420319 ==
1572 00:25:56.420366 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 00:25:56.420429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 00:25:56.420494 ==
1575 00:25:56.420541
1576 00:25:56.420587
1577 00:25:56.420634 TX Vref Scan disable
1578 00:25:56.420718 == TX Byte 0 ==
1579 00:25:56.420766 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1580 00:25:56.420844 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1581 00:25:56.420895 == TX Byte 1 ==
1582 00:25:56.420943 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1583 00:25:56.420991 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1584 00:25:56.421038 ==
1585 00:25:56.421086 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 00:25:56.421165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 00:25:56.421213 ==
1588 00:25:56.421261 TX Vref=22, minBit 1, minWin=27, winSum=438
1589 00:25:56.421309 TX Vref=24, minBit 1, minWin=27, winSum=442
1590 00:25:56.421356 TX Vref=26, minBit 4, minWin=27, winSum=445
1591 00:25:56.421403 TX Vref=28, minBit 5, minWin=27, winSum=449
1592 00:25:56.421452 TX Vref=30, minBit 5, minWin=27, winSum=449
1593 00:25:56.421499 TX Vref=32, minBit 5, minWin=27, winSum=448
1594 00:25:56.421547 [TxChooseVref] Worse bit 5, Min win 27, Win sum 449, Final Vref 28
1595 00:25:56.421594
1596 00:25:56.421641 Final TX Range 1 Vref 28
1597 00:25:56.421689
1598 00:25:56.421737 ==
1599 00:25:56.421784 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 00:25:56.421832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 00:25:56.421880 ==
1602 00:25:56.421928
1603 00:25:56.421976
1604 00:25:56.422023 TX Vref Scan disable
1605 00:25:56.422071 == TX Byte 0 ==
1606 00:25:56.422118 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1607 00:25:56.422166 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1608 00:25:56.422214 == TX Byte 1 ==
1609 00:25:56.422261 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1610 00:25:56.422309 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1611 00:25:56.422357
1612 00:25:56.422404 [DATLAT]
1613 00:25:56.422451 Freq=800, CH1 RK0
1614 00:25:56.422498
1615 00:25:56.422545 DATLAT Default: 0xa
1616 00:25:56.422593 0, 0xFFFF, sum = 0
1617 00:25:56.422641 1, 0xFFFF, sum = 0
1618 00:25:56.422690 2, 0xFFFF, sum = 0
1619 00:25:56.422738 3, 0xFFFF, sum = 0
1620 00:25:56.422785 4, 0xFFFF, sum = 0
1621 00:25:56.422833 5, 0xFFFF, sum = 0
1622 00:25:56.422882 6, 0xFFFF, sum = 0
1623 00:25:56.422929 7, 0xFFFF, sum = 0
1624 00:25:56.422977 8, 0xFFFF, sum = 0
1625 00:25:56.423026 9, 0x0, sum = 1
1626 00:25:56.423073 10, 0x0, sum = 2
1627 00:25:56.423121 11, 0x0, sum = 3
1628 00:25:56.423169 12, 0x0, sum = 4
1629 00:25:56.423268 best_step = 10
1630 00:25:56.423319
1631 00:25:56.423367 ==
1632 00:25:56.423415 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 00:25:56.423464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 00:25:56.423514 ==
1635 00:25:56.423563 RX Vref Scan: 1
1636 00:25:56.423611
1637 00:25:56.423658 Set Vref Range= 32 -> 127
1638 00:25:56.423707
1639 00:25:56.423755 RX Vref 32 -> 127, step: 1
1640 00:25:56.423805
1641 00:25:56.423853 RX Delay -111 -> 252, step: 8
1642 00:25:56.423901
1643 00:25:56.423950 Set Vref, RX VrefLevel [Byte0]: 32
1644 00:25:56.423999 [Byte1]: 32
1645 00:25:56.424048
1646 00:25:56.424097 Set Vref, RX VrefLevel [Byte0]: 33
1647 00:25:56.424146 [Byte1]: 33
1648 00:25:56.424194
1649 00:25:56.424243 Set Vref, RX VrefLevel [Byte0]: 34
1650 00:25:56.424293 [Byte1]: 34
1651 00:25:56.424342
1652 00:25:56.424390 Set Vref, RX VrefLevel [Byte0]: 35
1653 00:25:56.424438 [Byte1]: 35
1654 00:25:56.424487
1655 00:25:56.424535 Set Vref, RX VrefLevel [Byte0]: 36
1656 00:25:56.424583 [Byte1]: 36
1657 00:25:56.424631
1658 00:25:56.424693 Set Vref, RX VrefLevel [Byte0]: 37
1659 00:25:56.424743 [Byte1]: 37
1660 00:25:56.424791
1661 00:25:56.424840 Set Vref, RX VrefLevel [Byte0]: 38
1662 00:25:56.424888 [Byte1]: 38
1663 00:25:56.424936
1664 00:25:56.424984 Set Vref, RX VrefLevel [Byte0]: 39
1665 00:25:56.425032 [Byte1]: 39
1666 00:25:56.425080
1667 00:25:56.425128 Set Vref, RX VrefLevel [Byte0]: 40
1668 00:25:56.425176 [Byte1]: 40
1669 00:25:56.425223
1670 00:25:56.425271 Set Vref, RX VrefLevel [Byte0]: 41
1671 00:25:56.425320 [Byte1]: 41
1672 00:25:56.425368
1673 00:25:56.425416 Set Vref, RX VrefLevel [Byte0]: 42
1674 00:25:56.425464 [Byte1]: 42
1675 00:25:56.425512
1676 00:25:56.425560 Set Vref, RX VrefLevel [Byte0]: 43
1677 00:25:56.425608 [Byte1]: 43
1678 00:25:56.425656
1679 00:25:56.425703 Set Vref, RX VrefLevel [Byte0]: 44
1680 00:25:56.425751 [Byte1]: 44
1681 00:25:56.425801
1682 00:25:56.425849 Set Vref, RX VrefLevel [Byte0]: 45
1683 00:25:56.425898 [Byte1]: 45
1684 00:25:56.425946
1685 00:25:56.425994 Set Vref, RX VrefLevel [Byte0]: 46
1686 00:25:56.426043 [Byte1]: 46
1687 00:25:56.426091
1688 00:25:56.426139 Set Vref, RX VrefLevel [Byte0]: 47
1689 00:25:56.426189 [Byte1]: 47
1690 00:25:56.426237
1691 00:25:56.426285 Set Vref, RX VrefLevel [Byte0]: 48
1692 00:25:56.426334 [Byte1]: 48
1693 00:25:56.426382
1694 00:25:56.426430 Set Vref, RX VrefLevel [Byte0]: 49
1695 00:25:56.426478 [Byte1]: 49
1696 00:25:56.426527
1697 00:25:56.426575 Set Vref, RX VrefLevel [Byte0]: 50
1698 00:25:56.426623 [Byte1]: 50
1699 00:25:56.426671
1700 00:25:56.426718 Set Vref, RX VrefLevel [Byte0]: 51
1701 00:25:56.426767 [Byte1]: 51
1702 00:25:56.426816
1703 00:25:56.427057 Set Vref, RX VrefLevel [Byte0]: 52
1704 00:25:56.427116 [Byte1]: 52
1705 00:25:56.427166
1706 00:25:56.427215 Set Vref, RX VrefLevel [Byte0]: 53
1707 00:25:56.427264 [Byte1]: 53
1708 00:25:56.427312
1709 00:25:56.427361 Set Vref, RX VrefLevel [Byte0]: 54
1710 00:25:56.427410 [Byte1]: 54
1711 00:25:56.427459
1712 00:25:56.427507 Set Vref, RX VrefLevel [Byte0]: 55
1713 00:25:56.427556 [Byte1]: 55
1714 00:25:56.427605
1715 00:25:56.427653 Set Vref, RX VrefLevel [Byte0]: 56
1716 00:25:56.427702 [Byte1]: 56
1717 00:25:56.427750
1718 00:25:56.427812 Set Vref, RX VrefLevel [Byte0]: 57
1719 00:25:56.427860 [Byte1]: 57
1720 00:25:56.427941
1721 00:25:56.428004 Set Vref, RX VrefLevel [Byte0]: 58
1722 00:25:56.428068 [Byte1]: 58
1723 00:25:56.428115
1724 00:25:56.428162 Set Vref, RX VrefLevel [Byte0]: 59
1725 00:25:56.428216 [Byte1]: 59
1726 00:25:56.428320
1727 00:25:56.428406 Set Vref, RX VrefLevel [Byte0]: 60
1728 00:25:56.428485 [Byte1]: 60
1729 00:25:56.428561
1730 00:25:56.428638 Set Vref, RX VrefLevel [Byte0]: 61
1731 00:25:56.428739 [Byte1]: 61
1732 00:25:56.428814
1733 00:25:56.428889 Set Vref, RX VrefLevel [Byte0]: 62
1734 00:25:56.428964 [Byte1]: 62
1735 00:25:56.429014
1736 00:25:56.429062 Set Vref, RX VrefLevel [Byte0]: 63
1737 00:25:56.429110 [Byte1]: 63
1738 00:25:56.429158
1739 00:25:56.429205 Set Vref, RX VrefLevel [Byte0]: 64
1740 00:25:56.429253 [Byte1]: 64
1741 00:25:56.429300
1742 00:25:56.429347 Set Vref, RX VrefLevel [Byte0]: 65
1743 00:25:56.429395 [Byte1]: 65
1744 00:25:56.429442
1745 00:25:56.429489 Set Vref, RX VrefLevel [Byte0]: 66
1746 00:25:56.429536 [Byte1]: 66
1747 00:25:56.429584
1748 00:25:56.429631 Set Vref, RX VrefLevel [Byte0]: 67
1749 00:25:56.429679 [Byte1]: 67
1750 00:25:56.429726
1751 00:25:56.429773 Set Vref, RX VrefLevel [Byte0]: 68
1752 00:25:56.429821 [Byte1]: 68
1753 00:25:56.429868
1754 00:25:56.429916 Set Vref, RX VrefLevel [Byte0]: 69
1755 00:25:56.429963 [Byte1]: 69
1756 00:25:56.430010
1757 00:25:56.430058 Set Vref, RX VrefLevel [Byte0]: 70
1758 00:25:56.430105 [Byte1]: 70
1759 00:25:56.430152
1760 00:25:56.430199 Set Vref, RX VrefLevel [Byte0]: 71
1761 00:25:56.430246 [Byte1]: 71
1762 00:25:56.430293
1763 00:25:56.430339 Set Vref, RX VrefLevel [Byte0]: 72
1764 00:25:56.430387 [Byte1]: 72
1765 00:25:56.430435
1766 00:25:56.430482 Set Vref, RX VrefLevel [Byte0]: 73
1767 00:25:56.430529 [Byte1]: 73
1768 00:25:56.430576
1769 00:25:56.430623 Final RX Vref Byte 0 = 60 to rank0
1770 00:25:56.430671 Final RX Vref Byte 1 = 57 to rank0
1771 00:25:56.430719 Final RX Vref Byte 0 = 60 to rank1
1772 00:25:56.430767 Final RX Vref Byte 1 = 57 to rank1==
1773 00:25:56.430816 Dram Type= 6, Freq= 0, CH_1, rank 0
1774 00:25:56.430865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1775 00:25:56.430912 ==
1776 00:25:56.430960 DQS Delay:
1777 00:25:56.431007 DQS0 = 0, DQS1 = 0
1778 00:25:56.431054 DQM Delay:
1779 00:25:56.431102 DQM0 = 81, DQM1 = 71
1780 00:25:56.431150 DQ Delay:
1781 00:25:56.431197 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1782 00:25:56.431244 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1783 00:25:56.431292 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1784 00:25:56.431340 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1785 00:25:56.431387
1786 00:25:56.431434
1787 00:25:56.431482 [DQSOSCAuto] RK0, (LSB)MR18= 0x111a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
1788 00:25:56.431531 CH1 RK0: MR19=606, MR18=111A
1789 00:25:56.431578 CH1_RK0: MR19=0x606, MR18=0x111A, DQSOSC=403, MR23=63, INC=90, DEC=60
1790 00:25:56.431625
1791 00:25:56.431671 ----->DramcWriteLeveling(PI) begin...
1792 00:25:56.431720 ==
1793 00:25:56.431768 Dram Type= 6, Freq= 0, CH_1, rank 1
1794 00:25:56.431816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1795 00:25:56.431864 ==
1796 00:25:56.431911 Write leveling (Byte 0): 27 => 27
1797 00:25:56.431959 Write leveling (Byte 1): 27 => 27
1798 00:25:56.432006 DramcWriteLeveling(PI) end<-----
1799 00:25:56.432053
1800 00:25:56.432099 ==
1801 00:25:56.432146 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 00:25:56.432194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 00:25:56.432242 ==
1804 00:25:56.432290 [Gating] SW mode calibration
1805 00:25:56.432338 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1806 00:25:56.432386 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1807 00:25:56.432435 0 6 0 | B1->B0 | 2323 2323 | 0 1 | (1 1) (1 1)
1808 00:25:56.432482 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1809 00:25:56.432529 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 00:25:56.432576 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 00:25:56.432624 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 00:25:56.432713 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 00:25:56.432762 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 00:25:56.432809 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 00:25:56.432857 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 00:25:56.432904 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 00:25:56.432952 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 00:25:56.433000 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 00:25:56.433046 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 00:25:56.433094 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 00:25:56.433142 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 00:25:56.433189 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 00:25:56.433237 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 00:25:56.433285 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1825 00:25:56.433332 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1826 00:25:56.433379 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 00:25:56.433426 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 00:25:56.433473 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 00:25:56.433521 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 00:25:56.433569 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 00:25:56.433616 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 00:25:56.433854 0 9 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
1833 00:25:56.433973 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1834 00:25:56.434025 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 00:25:56.434074 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 00:25:56.434123 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 00:25:56.434172 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 00:25:56.434236 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 00:25:56.434318 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 00:25:56.434412 0 10 4 | B1->B0 | 3333 2d2d | 1 0 | (1 1) (0 0)
1841 00:25:56.434507 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
1842 00:25:56.434601 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 00:25:56.434695 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 00:25:56.434787 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 00:25:56.434879 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 00:25:56.434972 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 00:25:56.435049 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 00:25:56.435125 0 11 4 | B1->B0 | 2626 3535 | 0 0 | (0 0) (0 0)
1849 00:25:56.435204 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1850 00:25:56.435281 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 00:25:56.435356 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 00:25:56.435432 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 00:25:56.435508 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 00:25:56.435584 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 00:25:56.435660 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1856 00:25:56.435736 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1857 00:25:56.435812 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1858 00:25:56.435887 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 00:25:56.435963 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 00:25:56.436038 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 00:25:56.436114 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 00:25:56.436190 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 00:25:56.436266 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 00:25:56.436341 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 00:25:56.436416 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 00:25:56.436492 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 00:25:56.436586 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 00:25:56.436686 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 00:25:56.436763 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 00:25:56.436839 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 00:25:56.436915 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 00:25:56.436990 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1873 00:25:56.437066 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1874 00:25:56.437142 Total UI for P1: 0, mck2ui 16
1875 00:25:56.437222 best dqsien dly found for B0: ( 0, 14, 4)
1876 00:25:56.437297 Total UI for P1: 0, mck2ui 16
1877 00:25:56.437373 best dqsien dly found for B1: ( 0, 14, 4)
1878 00:25:56.437449 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1879 00:25:56.437525 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1880 00:25:56.437600
1881 00:25:56.437675 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1882 00:25:56.437751 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1883 00:25:56.437826 [Gating] SW calibration Done
1884 00:25:56.437892 ==
1885 00:25:56.437941 Dram Type= 6, Freq= 0, CH_1, rank 1
1886 00:25:56.437990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1887 00:25:56.438039 ==
1888 00:25:56.438087 RX Vref Scan: 0
1889 00:25:56.438134
1890 00:25:56.438180 RX Vref 0 -> 0, step: 1
1891 00:25:56.438228
1892 00:25:56.438275 RX Delay -130 -> 252, step: 16
1893 00:25:56.438323 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1894 00:25:56.438372 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1895 00:25:56.438419 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1896 00:25:56.438467 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1897 00:25:56.438514 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1898 00:25:56.438562 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1899 00:25:56.438609 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1900 00:25:56.438657 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1901 00:25:56.438704 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1902 00:25:56.438752 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1903 00:25:56.438800 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1904 00:25:56.438847 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1905 00:25:56.438894 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1906 00:25:56.438941 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1907 00:25:56.438989 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1908 00:25:56.439053 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1909 00:25:56.439114 ==
1910 00:25:56.439162 Dram Type= 6, Freq= 0, CH_1, rank 1
1911 00:25:56.439210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1912 00:25:56.439261 ==
1913 00:25:56.439310 DQS Delay:
1914 00:25:56.439392 DQS0 = 0, DQS1 = 0
1915 00:25:56.439440 DQM Delay:
1916 00:25:56.439502 DQM0 = 78, DQM1 = 73
1917 00:25:56.439551 DQ Delay:
1918 00:25:56.439599 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1919 00:25:56.702716 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1920 00:25:56.702882 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1921 00:25:56.702989 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1922 00:25:56.703091
1923 00:25:56.703188
1924 00:25:56.703287 ==
1925 00:25:56.703383 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 00:25:56.703482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 00:25:56.703582 ==
1928 00:25:56.703678
1929 00:25:56.703761
1930 00:25:56.703841 TX Vref Scan disable
1931 00:25:56.703920 == TX Byte 0 ==
1932 00:25:56.704000 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1933 00:25:56.704081 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1934 00:25:56.704159 == TX Byte 1 ==
1935 00:25:56.704237 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1936 00:25:56.704316 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1937 00:25:56.704393 ==
1938 00:25:56.704682 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 00:25:56.704766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 00:25:56.704847 ==
1941 00:25:56.704926 TX Vref=22, minBit 11, minWin=27, winSum=449
1942 00:25:56.705006 TX Vref=24, minBit 9, minWin=27, winSum=452
1943 00:25:56.705085 TX Vref=26, minBit 5, minWin=27, winSum=455
1944 00:25:56.705163 TX Vref=28, minBit 1, minWin=27, winSum=457
1945 00:25:56.705241 TX Vref=30, minBit 5, minWin=27, winSum=459
1946 00:25:56.705319 TX Vref=32, minBit 0, minWin=28, winSum=458
1947 00:25:56.705398 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 32
1948 00:25:56.705475
1949 00:25:56.705552 Final TX Range 1 Vref 32
1950 00:25:56.705630
1951 00:25:56.705714 ==
1952 00:25:56.705791 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 00:25:56.705870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 00:25:56.705947 ==
1955 00:25:56.706024
1956 00:25:56.706099
1957 00:25:56.706175 TX Vref Scan disable
1958 00:25:56.706252 == TX Byte 0 ==
1959 00:25:56.706329 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1960 00:25:56.706407 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1961 00:25:56.706485 == TX Byte 1 ==
1962 00:25:56.706562 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1963 00:25:56.706639 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1964 00:25:56.706716
1965 00:25:56.706792 [DATLAT]
1966 00:25:56.706869 Freq=800, CH1 RK1
1967 00:25:56.706946
1968 00:25:56.707023 DATLAT Default: 0xa
1969 00:25:56.707101 0, 0xFFFF, sum = 0
1970 00:25:56.707180 1, 0xFFFF, sum = 0
1971 00:25:56.707260 2, 0xFFFF, sum = 0
1972 00:25:56.707339 3, 0xFFFF, sum = 0
1973 00:25:56.707419 4, 0xFFFF, sum = 0
1974 00:25:56.707497 5, 0xFFFF, sum = 0
1975 00:25:56.707577 6, 0xFFFF, sum = 0
1976 00:25:56.707657 7, 0xFFFF, sum = 0
1977 00:25:56.707736 8, 0xFFFF, sum = 0
1978 00:25:56.707816 9, 0x0, sum = 1
1979 00:25:56.707895 10, 0x0, sum = 2
1980 00:25:56.707974 11, 0x0, sum = 3
1981 00:25:56.708053 12, 0x0, sum = 4
1982 00:25:56.708133 best_step = 10
1983 00:25:56.708210
1984 00:25:56.708286 ==
1985 00:25:56.708363 Dram Type= 6, Freq= 0, CH_1, rank 1
1986 00:25:56.708442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1987 00:25:56.708519 ==
1988 00:25:56.708596 RX Vref Scan: 0
1989 00:25:56.708678
1990 00:25:56.708731 RX Vref 0 -> 0, step: 1
1991 00:25:56.708780
1992 00:25:56.708830 RX Delay -111 -> 252, step: 8
1993 00:25:56.708880 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1994 00:25:56.708930 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1995 00:25:56.708980 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
1996 00:25:56.709029 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1997 00:25:56.709078 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
1998 00:25:56.709128 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
1999 00:25:56.709176 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2000 00:25:56.709225 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2001 00:25:56.709274 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2002 00:25:56.709323 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2003 00:25:56.709373 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2004 00:25:56.709422 iDelay=209, Bit 11, Center 72 (-47 ~ 192) 240
2005 00:25:56.709471 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2006 00:25:56.709520 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2007 00:25:56.709570 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2008 00:25:56.709619 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2009 00:25:56.709703 ==
2010 00:25:56.709781 Dram Type= 6, Freq= 0, CH_1, rank 1
2011 00:25:56.709860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2012 00:25:56.709937 ==
2013 00:25:56.710014 DQS Delay:
2014 00:25:56.710091 DQS0 = 0, DQS1 = 0
2015 00:25:56.710168 DQM Delay:
2016 00:25:56.710238 DQM0 = 77, DQM1 = 74
2017 00:25:56.710290 DQ Delay:
2018 00:25:56.710340 DQ0 =84, DQ1 =72, DQ2 =64, DQ3 =72
2019 00:25:56.710390 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2020 00:25:56.710439 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =72
2021 00:25:56.710489 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2022 00:25:56.710539
2023 00:25:56.710587
2024 00:25:56.710636 [DQSOSCAuto] RK1, (LSB)MR18= 0x2138, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2025 00:25:56.710687 CH1 RK1: MR19=606, MR18=2138
2026 00:25:56.710737 CH1_RK1: MR19=0x606, MR18=0x2138, DQSOSC=395, MR23=63, INC=94, DEC=63
2027 00:25:56.710788 [RxdqsGatingPostProcess] freq 800
2028 00:25:56.710837 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2029 00:25:56.710886 Pre-setting of DQS Precalculation
2030 00:25:56.710936 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2031 00:25:56.710986 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2032 00:25:56.711037 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2033 00:25:56.711086
2034 00:25:56.711135
2035 00:25:56.711184 [Calibration Summary] 1600 Mbps
2036 00:25:56.711234 CH 0, Rank 0
2037 00:25:56.711284 SW Impedance : PASS
2038 00:25:56.711333 DUTY Scan : NO K
2039 00:25:56.711383 ZQ Calibration : PASS
2040 00:25:56.711432 Jitter Meter : NO K
2041 00:25:56.711481 CBT Training : PASS
2042 00:25:56.711531 Write leveling : PASS
2043 00:25:56.711579 RX DQS gating : PASS
2044 00:25:56.711629 RX DQ/DQS(RDDQC) : PASS
2045 00:25:56.711696 TX DQ/DQS : PASS
2046 00:25:56.711748 RX DATLAT : PASS
2047 00:25:56.711797 RX DQ/DQS(Engine): PASS
2048 00:25:56.711846 TX OE : NO K
2049 00:25:56.711896 All Pass.
2050 00:25:56.711945
2051 00:25:56.711994 CH 0, Rank 1
2052 00:25:56.712043 SW Impedance : PASS
2053 00:25:56.712091 DUTY Scan : NO K
2054 00:25:56.712140 ZQ Calibration : PASS
2055 00:25:56.712189 Jitter Meter : NO K
2056 00:25:56.712238 CBT Training : PASS
2057 00:25:56.712287 Write leveling : PASS
2058 00:25:56.712336 RX DQS gating : PASS
2059 00:25:56.712385 RX DQ/DQS(RDDQC) : PASS
2060 00:25:56.712434 TX DQ/DQS : PASS
2061 00:25:56.712483 RX DATLAT : PASS
2062 00:25:56.712532 RX DQ/DQS(Engine): PASS
2063 00:25:56.712581 TX OE : NO K
2064 00:25:56.712630 All Pass.
2065 00:25:56.712688
2066 00:25:56.712737 CH 1, Rank 0
2067 00:25:56.712787 SW Impedance : PASS
2068 00:25:56.712836 DUTY Scan : NO K
2069 00:25:56.712885 ZQ Calibration : PASS
2070 00:25:56.712935 Jitter Meter : NO K
2071 00:25:56.712984 CBT Training : PASS
2072 00:25:56.713032 Write leveling : PASS
2073 00:25:56.713081 RX DQS gating : PASS
2074 00:25:56.713130 RX DQ/DQS(RDDQC) : PASS
2075 00:25:56.713179 TX DQ/DQS : PASS
2076 00:25:56.713227 RX DATLAT : PASS
2077 00:25:56.713276 RX DQ/DQS(Engine): PASS
2078 00:25:56.713338 TX OE : NO K
2079 00:25:56.713428 All Pass.
2080 00:25:56.713516
2081 00:25:56.713609 CH 1, Rank 1
2082 00:25:56.713701 SW Impedance : PASS
2083 00:25:56.713795 DUTY Scan : NO K
2084 00:25:56.713891 ZQ Calibration : PASS
2085 00:25:56.713981 Jitter Meter : NO K
2086 00:25:56.714074 CBT Training : PASS
2087 00:25:56.714169 Write leveling : PASS
2088 00:25:56.714466 RX DQS gating : PASS
2089 00:25:56.714570 RX DQ/DQS(RDDQC) : PASS
2090 00:25:56.714669 TX DQ/DQS : PASS
2091 00:25:56.714765 RX DATLAT : PASS
2092 00:25:56.714862 RX DQ/DQS(Engine): PASS
2093 00:25:56.714959 TX OE : NO K
2094 00:25:56.715053 All Pass.
2095 00:25:56.715150
2096 00:25:56.715243 DramC Write-DBI off
2097 00:25:56.715337 PER_BANK_REFRESH: Hybrid Mode
2098 00:25:56.715431 TX_TRACKING: ON
2099 00:25:56.715526 [GetDramInforAfterCalByMRR] Vendor 6.
2100 00:25:56.715622 [GetDramInforAfterCalByMRR] Revision 606.
2101 00:25:56.715723 [GetDramInforAfterCalByMRR] Revision 2 0.
2102 00:25:56.715820 MR0 0x3b3b
2103 00:25:56.715912 MR8 0x5151
2104 00:25:56.716001 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2105 00:25:56.716093
2106 00:25:56.716187 MR0 0x3b3b
2107 00:25:56.716280 MR8 0x5151
2108 00:25:56.716368 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2109 00:25:56.716461
2110 00:25:56.716556 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2111 00:25:56.716659 [FAST_K] Save calibration result to emmc
2112 00:25:56.716752 [FAST_K] Save calibration result to emmc
2113 00:25:56.716849 dram_init: config_dvfs: 1
2114 00:25:56.716940 dramc_set_vcore_voltage set vcore to 662500
2115 00:25:56.717038 Read voltage for 1200, 2
2116 00:25:56.717129 Vio18 = 0
2117 00:25:56.717226 Vcore = 662500
2118 00:25:56.717323 Vdram = 0
2119 00:25:56.717419 Vddq = 0
2120 00:25:56.717516 Vmddr = 0
2121 00:25:56.717611 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2122 00:25:56.717707 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2123 00:25:56.717803 MEM_TYPE=3, freq_sel=15
2124 00:25:56.717895 sv_algorithm_assistance_LP4_1600
2125 00:25:56.717986 ============ PULL DRAM RESETB DOWN ============
2126 00:25:56.718081 ========== PULL DRAM RESETB DOWN end =========
2127 00:25:56.718176 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2128 00:25:56.718274 ===================================
2129 00:25:56.718368 LPDDR4 DRAM CONFIGURATION
2130 00:25:56.718463 ===================================
2131 00:25:56.718558 EX_ROW_EN[0] = 0x0
2132 00:25:56.718651 EX_ROW_EN[1] = 0x0
2133 00:25:56.718744 LP4Y_EN = 0x0
2134 00:25:56.718839 WORK_FSP = 0x0
2135 00:25:56.718936 WL = 0x4
2136 00:25:56.719029 RL = 0x4
2137 00:25:56.719117 BL = 0x2
2138 00:25:56.719213 RPST = 0x0
2139 00:25:56.719305 RD_PRE = 0x0
2140 00:25:56.719396 WR_PRE = 0x1
2141 00:25:56.719491 WR_PST = 0x0
2142 00:25:56.719583 DBI_WR = 0x0
2143 00:25:56.719676 DBI_RD = 0x0
2144 00:25:56.719764 OTF = 0x1
2145 00:25:56.719861 ===================================
2146 00:25:56.719953 ===================================
2147 00:25:56.720050 ANA top config
2148 00:25:56.720145 ===================================
2149 00:25:56.720234 DLL_ASYNC_EN = 0
2150 00:25:56.720331 ALL_SLAVE_EN = 0
2151 00:25:56.720427 NEW_RANK_MODE = 1
2152 00:25:56.720520 DLL_IDLE_MODE = 1
2153 00:25:56.720611 LP45_APHY_COMB_EN = 1
2154 00:25:56.720709 TX_ODT_DIS = 1
2155 00:25:56.720806 NEW_8X_MODE = 1
2156 00:25:56.720902 ===================================
2157 00:25:56.720996 ===================================
2158 00:25:56.721087 data_rate = 2400
2159 00:25:56.721183 CKR = 1
2160 00:25:56.721277 DQ_P2S_RATIO = 8
2161 00:25:56.721371 ===================================
2162 00:25:56.721464 CA_P2S_RATIO = 8
2163 00:25:56.721556 DQ_CA_OPEN = 0
2164 00:25:56.721650 DQ_SEMI_OPEN = 0
2165 00:25:56.721749 CA_SEMI_OPEN = 0
2166 00:25:56.721845 CA_FULL_RATE = 0
2167 00:25:56.721938 DQ_CKDIV4_EN = 0
2168 00:25:56.722030 CA_CKDIV4_EN = 0
2169 00:25:56.722123 CA_PREDIV_EN = 0
2170 00:25:56.722219 PH8_DLY = 17
2171 00:25:56.722314 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2172 00:25:56.722407 DQ_AAMCK_DIV = 4
2173 00:25:56.722498 CA_AAMCK_DIV = 4
2174 00:25:56.722588 CA_ADMCK_DIV = 4
2175 00:25:56.722681 DQ_TRACK_CA_EN = 0
2176 00:25:56.722777 CA_PICK = 1200
2177 00:25:56.722872 CA_MCKIO = 1200
2178 00:25:56.722965 MCKIO_SEMI = 0
2179 00:25:56.723057 PLL_FREQ = 2366
2180 00:25:56.723151 DQ_UI_PI_RATIO = 32
2181 00:25:56.723248 CA_UI_PI_RATIO = 0
2182 00:25:56.723342 ===================================
2183 00:25:56.723438 ===================================
2184 00:25:56.723530 memory_type:LPDDR4
2185 00:25:56.723626 GP_NUM : 10
2186 00:25:56.723724 SRAM_EN : 1
2187 00:25:56.723819 MD32_EN : 0
2188 00:25:56.723913 ===================================
2189 00:25:56.724009 [ANA_INIT] >>>>>>>>>>>>>>
2190 00:25:56.724106 <<<<<< [CONFIGURE PHASE]: ANA_TX
2191 00:25:56.724202 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2192 00:25:56.724295 ===================================
2193 00:25:56.724384 data_rate = 2400,PCW = 0X5b00
2194 00:25:56.724480 ===================================
2195 00:25:56.724573 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2196 00:25:56.724674 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2197 00:25:56.724771 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2198 00:25:56.724864 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2199 00:25:56.724962 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2200 00:25:56.725054 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2201 00:25:56.725147 [ANA_INIT] flow start
2202 00:25:56.725237 [ANA_INIT] PLL >>>>>>>>
2203 00:25:56.725334 [ANA_INIT] PLL <<<<<<<<
2204 00:25:56.725429 [ANA_INIT] MIDPI >>>>>>>>
2205 00:25:56.725524 [ANA_INIT] MIDPI <<<<<<<<
2206 00:25:56.725613 [ANA_INIT] DLL >>>>>>>>
2207 00:25:56.725714 [ANA_INIT] DLL <<<<<<<<
2208 00:25:56.725807 [ANA_INIT] flow end
2209 00:25:56.725901 ============ LP4 DIFF to SE enter ============
2210 00:25:56.725995 ============ LP4 DIFF to SE exit ============
2211 00:25:56.726091 [ANA_INIT] <<<<<<<<<<<<<
2212 00:25:56.726188 [Flow] Enable top DCM control >>>>>
2213 00:25:56.726283 [Flow] Enable top DCM control <<<<<
2214 00:25:56.726377 Enable DLL master slave shuffle
2215 00:25:56.726471 ==============================================================
2216 00:25:56.726568 Gating Mode config
2217 00:25:56.726665 ==============================================================
2218 00:25:56.726966 Config description:
2219 00:25:56.727069 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2220 00:25:56.727171 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2221 00:25:56.727273 SELPH_MODE 0: By rank 1: By Phase
2222 00:25:56.727370 ==============================================================
2223 00:25:56.727469 GAT_TRACK_EN = 1
2224 00:25:56.727566 RX_GATING_MODE = 2
2225 00:25:56.727662 RX_GATING_TRACK_MODE = 2
2226 00:25:56.727753 SELPH_MODE = 1
2227 00:25:56.727835 PICG_EARLY_EN = 1
2228 00:25:56.727914 VALID_LAT_VALUE = 1
2229 00:25:56.727994 ==============================================================
2230 00:25:56.728073 Enter into Gating configuration >>>>
2231 00:25:56.728151 Exit from Gating configuration <<<<
2232 00:25:56.728228 Enter into DVFS_PRE_config >>>>>
2233 00:25:56.728309 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2234 00:25:56.728388 Exit from DVFS_PRE_config <<<<<
2235 00:25:56.728466 Enter into PICG configuration >>>>
2236 00:25:56.728543 Exit from PICG configuration <<<<
2237 00:25:56.728621 [RX_INPUT] configuration >>>>>
2238 00:25:56.728708 [RX_INPUT] configuration <<<<<
2239 00:25:56.728793 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2240 00:25:56.728884 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2241 00:25:56.728980 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2242 00:25:56.729075 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2243 00:25:56.729168 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2244 00:25:56.729260 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2245 00:25:56.729352 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2246 00:25:56.729447 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2247 00:25:56.729540 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2248 00:25:56.729631 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2249 00:25:56.729722 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2250 00:25:56.729818 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2251 00:25:56.729911 ===================================
2252 00:25:56.730005 LPDDR4 DRAM CONFIGURATION
2253 00:25:56.730097 ===================================
2254 00:25:56.730186 EX_ROW_EN[0] = 0x0
2255 00:25:56.730283 EX_ROW_EN[1] = 0x0
2256 00:25:56.730375 LP4Y_EN = 0x0
2257 00:25:56.730469 WORK_FSP = 0x0
2258 00:25:56.730560 WL = 0x4
2259 00:25:56.730648 RL = 0x4
2260 00:25:56.730735 BL = 0x2
2261 00:25:56.730825 RPST = 0x0
2262 00:25:56.730917 RD_PRE = 0x0
2263 00:25:56.731009 WR_PRE = 0x1
2264 00:25:56.731103 WR_PST = 0x0
2265 00:25:56.731197 DBI_WR = 0x0
2266 00:25:56.731292 DBI_RD = 0x0
2267 00:25:56.731381 OTF = 0x1
2268 00:25:56.731471 ===================================
2269 00:25:56.731566 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2270 00:25:56.731658 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2271 00:25:56.731748 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2272 00:25:56.731843 ===================================
2273 00:25:56.731938 LPDDR4 DRAM CONFIGURATION
2274 00:25:56.732033 ===================================
2275 00:25:56.732126 EX_ROW_EN[0] = 0x10
2276 00:25:56.732219 EX_ROW_EN[1] = 0x0
2277 00:25:56.732314 LP4Y_EN = 0x0
2278 00:25:56.732404 WORK_FSP = 0x0
2279 00:25:56.732496 WL = 0x4
2280 00:25:56.732587 RL = 0x4
2281 00:25:56.732688 BL = 0x2
2282 00:25:56.732785 RPST = 0x0
2283 00:25:56.732875 RD_PRE = 0x0
2284 00:25:56.732970 WR_PRE = 0x1
2285 00:25:56.733064 WR_PST = 0x0
2286 00:25:56.733158 DBI_WR = 0x0
2287 00:25:56.733253 DBI_RD = 0x0
2288 00:25:56.733343 OTF = 0x1
2289 00:25:56.733435 ===================================
2290 00:25:56.733526 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2291 00:25:56.733623 ==
2292 00:25:56.733714 Dram Type= 6, Freq= 0, CH_0, rank 0
2293 00:25:56.733809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2294 00:25:56.733906 ==
2295 00:25:56.734002 [Duty_Offset_Calibration]
2296 00:25:56.734096 B0:2 B1:0 CA:3
2297 00:25:56.734188
2298 00:25:56.734281 [DutyScan_Calibration_Flow] k_type=0
2299 00:25:56.734376
2300 00:25:56.734465 ==CLK 0==
2301 00:25:56.734560 Final CLK duty delay cell = 0
2302 00:25:56.734656 [0] MAX Duty = 5031%(X100), DQS PI = 12
2303 00:25:56.734751 [0] MIN Duty = 4906%(X100), DQS PI = 54
2304 00:25:56.734847 [0] AVG Duty = 4968%(X100)
2305 00:25:56.734936
2306 00:25:56.735028 CH0 CLK Duty spec in!! Max-Min= 125%
2307 00:25:56.735122 [DutyScan_Calibration_Flow] ====Done====
2308 00:25:56.735217
2309 00:25:56.735307 [DutyScan_Calibration_Flow] k_type=1
2310 00:25:56.735402
2311 00:25:56.735497 ==DQS 0 ==
2312 00:25:56.735587 Final DQS duty delay cell = 0
2313 00:25:56.735680 [0] MAX Duty = 5062%(X100), DQS PI = 12
2314 00:25:56.735775 [0] MIN Duty = 4907%(X100), DQS PI = 2
2315 00:25:56.735871 [0] AVG Duty = 4984%(X100)
2316 00:25:56.735961
2317 00:25:56.736053 ==DQS 1 ==
2318 00:25:56.736146 Final DQS duty delay cell = -4
2319 00:25:56.736241 [-4] MAX Duty = 4969%(X100), DQS PI = 6
2320 00:25:56.736332 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2321 00:25:56.736426 [-4] AVG Duty = 4922%(X100)
2322 00:25:56.736521
2323 00:25:56.736611 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2324 00:25:56.736712
2325 00:25:56.736807 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2326 00:25:56.736899 [DutyScan_Calibration_Flow] ====Done====
2327 00:25:56.736991
2328 00:25:56.737081 [DutyScan_Calibration_Flow] k_type=3
2329 00:25:56.737173
2330 00:25:56.737263 ==DQM 0 ==
2331 00:25:56.737353 Final DQM duty delay cell = 0
2332 00:25:56.737449 [0] MAX Duty = 5124%(X100), DQS PI = 12
2333 00:25:56.737545 [0] MIN Duty = 4876%(X100), DQS PI = 48
2334 00:25:56.737638 [0] AVG Duty = 5000%(X100)
2335 00:25:56.737732
2336 00:25:56.737823 ==DQM 1 ==
2337 00:25:56.737921 Final DQM duty delay cell = 4
2338 00:25:56.738018 [4] MAX Duty = 5124%(X100), DQS PI = 50
2339 00:25:56.738112 [4] MIN Duty = 5000%(X100), DQS PI = 12
2340 00:25:56.738207 [4] AVG Duty = 5062%(X100)
2341 00:25:56.738298
2342 00:25:56.738393 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2343 00:25:56.738489
2344 00:25:56.738792 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2345 00:25:56.738896 [DutyScan_Calibration_Flow] ====Done====
2346 00:25:56.738996
2347 00:25:56.739093 [DutyScan_Calibration_Flow] k_type=2
2348 00:25:56.739189
2349 00:25:56.739285 ==DQ 0 ==
2350 00:25:56.739375 Final DQ duty delay cell = -4
2351 00:25:56.739472 [-4] MAX Duty = 5000%(X100), DQS PI = 16
2352 00:25:56.739568 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2353 00:25:56.739663 [-4] AVG Duty = 4953%(X100)
2354 00:25:56.739754
2355 00:25:56.739845 ==DQ 1 ==
2356 00:25:56.739939 Final DQ duty delay cell = -4
2357 00:25:56.740036 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2358 00:25:56.740128 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2359 00:25:56.740222 [-4] AVG Duty = 4922%(X100)
2360 00:25:56.740318
2361 00:25:56.740411 CH0 DQ 0 Duty spec in!! Max-Min= 93%
2362 00:25:56.740503
2363 00:25:56.740594 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2364 00:25:56.740692 [DutyScan_Calibration_Flow] ====Done====
2365 00:25:56.740784 ==
2366 00:25:56.740875 Dram Type= 6, Freq= 0, CH_1, rank 0
2367 00:25:56.740968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2368 00:25:56.741061 ==
2369 00:25:56.741153 [Duty_Offset_Calibration]
2370 00:25:56.741247 B0:1 B1:-2 CA:0
2371 00:25:56.741341
2372 00:25:56.741433 [DutyScan_Calibration_Flow] k_type=0
2373 00:25:56.741523
2374 00:25:56.741617 ==CLK 0==
2375 00:25:56.741712 Final CLK duty delay cell = 0
2376 00:25:56.741811 [0] MAX Duty = 5031%(X100), DQS PI = 16
2377 00:25:56.741909 [0] MIN Duty = 4844%(X100), DQS PI = 58
2378 00:25:56.742001 [0] AVG Duty = 4937%(X100)
2379 00:25:56.742093
2380 00:25:56.742184 CH1 CLK Duty spec in!! Max-Min= 187%
2381 00:25:56.742279 [DutyScan_Calibration_Flow] ====Done====
2382 00:25:56.742372
2383 00:25:56.742466 [DutyScan_Calibration_Flow] k_type=1
2384 00:25:56.742557
2385 00:25:56.742649 ==DQS 0 ==
2386 00:25:56.742739 Final DQS duty delay cell = -4
2387 00:25:56.742836 [-4] MAX Duty = 4969%(X100), DQS PI = 8
2388 00:25:56.742930 [-4] MIN Duty = 4876%(X100), DQS PI = 50
2389 00:25:56.743022 [-4] AVG Duty = 4922%(X100)
2390 00:25:56.743112
2391 00:25:56.743204 ==DQS 1 ==
2392 00:25:56.743296 Final DQS duty delay cell = 0
2393 00:25:56.743391 [0] MAX Duty = 5062%(X100), DQS PI = 0
2394 00:25:56.743483 [0] MIN Duty = 4875%(X100), DQS PI = 26
2395 00:25:56.743579 [0] AVG Duty = 4968%(X100)
2396 00:25:56.743674
2397 00:25:56.743767 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2398 00:25:56.743862
2399 00:25:56.743953 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2400 00:25:56.744047 [DutyScan_Calibration_Flow] ====Done====
2401 00:25:56.744140
2402 00:25:56.744235 [DutyScan_Calibration_Flow] k_type=3
2403 00:25:56.744327
2404 00:25:56.744422 ==DQM 0 ==
2405 00:25:56.744517 Final DQM duty delay cell = 0
2406 00:25:56.744612 [0] MAX Duty = 5000%(X100), DQS PI = 22
2407 00:25:56.744716 [0] MIN Duty = 4844%(X100), DQS PI = 52
2408 00:25:56.744807 [0] AVG Duty = 4922%(X100)
2409 00:25:56.744903
2410 00:25:56.744994 ==DQM 1 ==
2411 00:25:56.745088 Final DQM duty delay cell = 0
2412 00:25:56.745180 [0] MAX Duty = 5031%(X100), DQS PI = 36
2413 00:25:56.745273 [0] MIN Duty = 4907%(X100), DQS PI = 0
2414 00:25:56.745364 [0] AVG Duty = 4969%(X100)
2415 00:25:56.745456
2416 00:25:56.745549 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2417 00:25:56.745645
2418 00:25:56.745734 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2419 00:25:56.745826 [DutyScan_Calibration_Flow] ====Done====
2420 00:25:56.745916
2421 00:25:56.746010 [DutyScan_Calibration_Flow] k_type=2
2422 00:25:56.746103
2423 00:25:56.746198 ==DQ 0 ==
2424 00:25:56.746294 Final DQ duty delay cell = 0
2425 00:25:56.746388 [0] MAX Duty = 5062%(X100), DQS PI = 12
2426 00:25:56.746483 [0] MIN Duty = 4938%(X100), DQS PI = 54
2427 00:25:56.746573 [0] AVG Duty = 5000%(X100)
2428 00:25:56.746667
2429 00:25:56.746762 ==DQ 1 ==
2430 00:25:56.746855 Final DQ duty delay cell = 0
2431 00:25:56.746953 [0] MAX Duty = 5125%(X100), DQS PI = 36
2432 00:25:56.747044 [0] MIN Duty = 4938%(X100), DQS PI = 26
2433 00:25:56.747136 [0] AVG Duty = 5031%(X100)
2434 00:25:56.747227
2435 00:25:56.747320 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2436 00:25:56.747411
2437 00:25:56.747505 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2438 00:25:56.747596 [DutyScan_Calibration_Flow] ====Done====
2439 00:25:56.747688 nWR fixed to 30
2440 00:25:56.747780 [ModeRegInit_LP4] CH0 RK0
2441 00:25:56.747874 [ModeRegInit_LP4] CH0 RK1
2442 00:25:56.747969 [ModeRegInit_LP4] CH1 RK0
2443 00:25:56.748064 [ModeRegInit_LP4] CH1 RK1
2444 00:25:56.748160 match AC timing 7
2445 00:25:56.748253 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2446 00:25:56.748349 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2447 00:25:56.748442 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2448 00:25:56.748535 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2449 00:25:56.748625 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2450 00:25:56.748718 ==
2451 00:25:56.748812 Dram Type= 6, Freq= 0, CH_0, rank 0
2452 00:25:56.748904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2453 00:25:56.748996 ==
2454 00:25:56.749086 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2455 00:25:56.749185 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2456 00:25:56.749282 [CA 0] Center 40 (10~71) winsize 62
2457 00:25:56.749376 [CA 1] Center 39 (9~70) winsize 62
2458 00:25:56.749471 [CA 2] Center 36 (6~66) winsize 61
2459 00:25:56.749563 [CA 3] Center 35 (5~66) winsize 62
2460 00:25:56.749659 [CA 4] Center 34 (4~65) winsize 62
2461 00:25:56.749754 [CA 5] Center 33 (3~63) winsize 61
2462 00:25:56.749845
2463 00:25:56.749938 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2464 00:25:56.750029
2465 00:25:56.750123 [CATrainingPosCal] consider 1 rank data
2466 00:25:56.750219 u2DelayCellTimex100 = 270/100 ps
2467 00:25:56.750314 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2468 00:25:56.750411 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2469 00:25:56.750503 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2470 00:25:56.750596 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2471 00:25:56.750687 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2472 00:25:56.750780 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2473 00:25:56.750874
2474 00:25:56.750969 CA PerBit enable=1, Macro0, CA PI delay=33
2475 00:25:56.751061
2476 00:25:56.751150 [CBTSetCACLKResult] CA Dly = 33
2477 00:25:56.751242 CS Dly: 7 (0~38)
2478 00:25:56.751337 ==
2479 00:25:56.751431 Dram Type= 6, Freq= 0, CH_0, rank 1
2480 00:25:56.751526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2481 00:25:56.751618 ==
2482 00:25:56.751712 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2483 00:25:56.751806 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2484 00:25:56.751900 [CA 0] Center 40 (10~70) winsize 61
2485 00:25:56.751995 [CA 1] Center 39 (9~70) winsize 62
2486 00:25:56.752091 [CA 2] Center 35 (5~66) winsize 62
2487 00:25:56.752182 [CA 3] Center 35 (5~66) winsize 62
2488 00:25:56.752278 [CA 4] Center 34 (4~65) winsize 62
2489 00:25:56.752589 [CA 5] Center 33 (3~63) winsize 61
2490 00:25:56.752697
2491 00:25:56.752793 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2492 00:25:56.752882
2493 00:25:56.752973 [CATrainingPosCal] consider 2 rank data
2494 00:25:56.753070 u2DelayCellTimex100 = 270/100 ps
2495 00:25:56.753160 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2496 00:25:56.753249 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2497 00:25:56.753342 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2498 00:25:56.753435 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2499 00:25:56.753524 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2500 00:25:56.753620 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2501 00:25:56.753714
2502 00:25:56.753808 CA PerBit enable=1, Macro0, CA PI delay=33
2503 00:25:56.753902
2504 00:25:56.753995 [CBTSetCACLKResult] CA Dly = 33
2505 00:25:56.754085 CS Dly: 7 (0~39)
2506 00:25:56.754175
2507 00:25:56.754268 ----->DramcWriteLeveling(PI) begin...
2508 00:25:56.754357 ==
2509 00:25:56.754445 Dram Type= 6, Freq= 0, CH_0, rank 0
2510 00:25:56.754536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2511 00:25:56.754628 ==
2512 00:25:56.754723 Write leveling (Byte 0): 32 => 32
2513 00:25:56.754819 Write leveling (Byte 1): 30 => 30
2514 00:25:56.754913 DramcWriteLeveling(PI) end<-----
2515 00:25:56.755005
2516 00:25:56.755092 ==
2517 00:25:56.755187 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 00:25:56.755279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 00:25:56.755373 ==
2520 00:25:56.755464 [Gating] SW mode calibration
2521 00:25:56.755560 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2522 00:25:56.755656 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2523 00:25:56.755750 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 00:25:56.755840 0 15 4 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (0 0)
2525 00:25:56.755937 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 00:25:56.756027 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 00:25:56.756121 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 00:25:56.756211 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 00:25:56.756307 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 00:25:56.756405 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2531 00:25:56.756501 1 0 0 | B1->B0 | 3232 2a2a | 1 0 | (1 0) (1 0)
2532 00:25:56.756591 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2533 00:25:56.756689 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 00:25:56.756780 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 00:25:56.756877 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 00:25:56.756968 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 00:25:56.757063 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 00:25:56.757160 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 00:25:56.757255 1 1 0 | B1->B0 | 2b2b 3a39 | 0 1 | (0 0) (0 0)
2540 00:25:56.757353 1 1 4 | B1->B0 | 4444 4545 | 0 0 | (0 0) (0 0)
2541 00:25:56.757444 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 00:25:56.757536 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 00:25:56.757631 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 00:25:56.757729 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 00:25:56.757820 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 00:25:56.757914 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2547 00:25:56.758008 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2548 00:25:56.758100 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2549 00:25:56.758190 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 00:25:56.758283 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 00:25:56.758376 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 00:25:56.758467 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 00:25:56.758559 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 00:25:56.758650 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 00:25:56.758743 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 00:25:56.758834 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 00:25:56.758925 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 00:25:56.759018 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 00:25:56.759108 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 00:25:56.759203 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 00:25:56.759295 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 00:25:56.759389 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2563 00:25:56.759485 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2564 00:25:56.759576 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2565 00:25:56.759671 Total UI for P1: 0, mck2ui 16
2566 00:25:56.759768 best dqsien dly found for B0: ( 1, 3, 30)
2567 00:25:56.759867 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2568 00:25:56.759958 Total UI for P1: 0, mck2ui 16
2569 00:25:56.760052 best dqsien dly found for B1: ( 1, 4, 4)
2570 00:25:56.760145 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2571 00:25:56.760237 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2572 00:25:56.760329
2573 00:25:56.760423 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2574 00:25:56.760521 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2575 00:25:56.760612 [Gating] SW calibration Done
2576 00:25:56.760717 ==
2577 00:25:56.760813 Dram Type= 6, Freq= 0, CH_0, rank 0
2578 00:25:56.760911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2579 00:25:56.761003 ==
2580 00:25:56.761099 RX Vref Scan: 0
2581 00:25:56.761192
2582 00:25:56.761282 RX Vref 0 -> 0, step: 1
2583 00:25:56.761374
2584 00:25:56.761468 RX Delay -40 -> 252, step: 8
2585 00:25:56.761564 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2586 00:25:56.761659 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2587 00:25:56.761756 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2588 00:25:56.761847 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2589 00:25:56.761940 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2590 00:25:56.762034 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2591 00:25:56.762125 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2592 00:25:56.762219 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2593 00:25:56.762521 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2594 00:25:56.762628 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2595 00:25:56.762727 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2596 00:25:56.762824 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2597 00:25:56.762922 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2598 00:25:56.763021 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2599 00:25:56.763114 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2600 00:25:56.763196 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2601 00:25:56.763276 ==
2602 00:25:56.763360 Dram Type= 6, Freq= 0, CH_0, rank 0
2603 00:25:56.763440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2604 00:25:56.763518 ==
2605 00:25:56.763597 DQS Delay:
2606 00:25:56.763674 DQS0 = 0, DQS1 = 0
2607 00:25:56.763751 DQM Delay:
2608 00:25:56.763829 DQM0 = 112, DQM1 = 102
2609 00:25:56.763906 DQ Delay:
2610 00:25:56.763984 DQ0 =111, DQ1 =115, DQ2 =111, DQ3 =107
2611 00:25:56.764062 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2612 00:25:56.764139 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
2613 00:25:56.764218 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2614 00:25:56.764295
2615 00:25:56.764371
2616 00:25:56.764447 ==
2617 00:25:56.764523 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 00:25:56.764601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 00:25:56.764687 ==
2620 00:25:56.764765
2621 00:25:56.764841
2622 00:25:56.764917 TX Vref Scan disable
2623 00:25:56.764994 == TX Byte 0 ==
2624 00:25:56.765071 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2625 00:25:56.765149 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2626 00:25:56.765226 == TX Byte 1 ==
2627 00:25:56.765303 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2628 00:25:56.765381 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2629 00:25:56.765457 ==
2630 00:25:56.765533 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 00:25:56.765611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 00:25:56.765687 ==
2633 00:25:56.765764 TX Vref=22, minBit 1, minWin=25, winSum=415
2634 00:25:56.765843 TX Vref=24, minBit 1, minWin=26, winSum=424
2635 00:25:56.765920 TX Vref=26, minBit 7, minWin=26, winSum=430
2636 00:25:56.765998 TX Vref=28, minBit 4, minWin=26, winSum=433
2637 00:25:56.766075 TX Vref=30, minBit 8, minWin=26, winSum=431
2638 00:25:56.766127 TX Vref=32, minBit 8, minWin=26, winSum=428
2639 00:25:56.766176 [TxChooseVref] Worse bit 4, Min win 26, Win sum 433, Final Vref 28
2640 00:25:56.766225
2641 00:25:56.766274 Final TX Range 1 Vref 28
2642 00:25:56.766323
2643 00:25:56.766371 ==
2644 00:25:56.766419 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 00:25:56.766468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 00:25:56.766517 ==
2647 00:25:56.766565
2648 00:25:56.766613
2649 00:25:56.766660 TX Vref Scan disable
2650 00:25:56.766708 == TX Byte 0 ==
2651 00:25:56.766756 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2652 00:25:56.766805 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2653 00:25:56.766854 == TX Byte 1 ==
2654 00:25:56.766902 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2655 00:25:56.766951 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2656 00:25:56.766999
2657 00:25:56.767047 [DATLAT]
2658 00:25:56.767096 Freq=1200, CH0 RK0
2659 00:25:56.767143
2660 00:25:56.767191 DATLAT Default: 0xd
2661 00:25:56.767239 0, 0xFFFF, sum = 0
2662 00:25:56.767289 1, 0xFFFF, sum = 0
2663 00:25:56.767339 2, 0xFFFF, sum = 0
2664 00:25:56.767388 3, 0xFFFF, sum = 0
2665 00:25:56.767437 4, 0xFFFF, sum = 0
2666 00:25:56.767486 5, 0xFFFF, sum = 0
2667 00:25:56.767534 6, 0xFFFF, sum = 0
2668 00:25:56.767582 7, 0xFFFF, sum = 0
2669 00:25:56.767630 8, 0xFFFF, sum = 0
2670 00:25:56.767678 9, 0xFFFF, sum = 0
2671 00:25:56.767727 10, 0xFFFF, sum = 0
2672 00:25:56.767775 11, 0xFFFF, sum = 0
2673 00:25:56.767824 12, 0x0, sum = 1
2674 00:25:56.767874 13, 0x0, sum = 2
2675 00:25:56.767959 14, 0x0, sum = 3
2676 00:25:56.768039 15, 0x0, sum = 4
2677 00:25:56.768118 best_step = 13
2678 00:25:56.768184
2679 00:25:56.768234 ==
2680 00:25:56.768283 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 00:25:56.768333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 00:25:56.768383 ==
2683 00:25:56.768432 RX Vref Scan: 1
2684 00:25:56.768479
2685 00:25:56.768527 Set Vref Range= 32 -> 127
2686 00:25:56.768575
2687 00:25:56.768623 RX Vref 32 -> 127, step: 1
2688 00:25:56.768679
2689 00:25:56.768729 RX Delay -37 -> 252, step: 4
2690 00:25:56.768777
2691 00:25:56.768826 Set Vref, RX VrefLevel [Byte0]: 32
2692 00:25:56.768875 [Byte1]: 32
2693 00:25:56.768924
2694 00:25:56.768972 Set Vref, RX VrefLevel [Byte0]: 33
2695 00:25:56.769020 [Byte1]: 33
2696 00:25:56.769069
2697 00:25:56.769117 Set Vref, RX VrefLevel [Byte0]: 34
2698 00:25:56.769166 [Byte1]: 34
2699 00:25:56.769214
2700 00:25:56.769263 Set Vref, RX VrefLevel [Byte0]: 35
2701 00:25:56.769311 [Byte1]: 35
2702 00:25:56.769360
2703 00:25:56.769408 Set Vref, RX VrefLevel [Byte0]: 36
2704 00:25:56.769456 [Byte1]: 36
2705 00:25:56.769504
2706 00:25:56.769552 Set Vref, RX VrefLevel [Byte0]: 37
2707 00:25:56.769601 [Byte1]: 37
2708 00:25:56.769649
2709 00:25:56.769696 Set Vref, RX VrefLevel [Byte0]: 38
2710 00:25:56.769744 [Byte1]: 38
2711 00:25:56.769792
2712 00:25:56.769840 Set Vref, RX VrefLevel [Byte0]: 39
2713 00:25:56.769888 [Byte1]: 39
2714 00:25:56.769936
2715 00:25:56.769984 Set Vref, RX VrefLevel [Byte0]: 40
2716 00:25:56.770032 [Byte1]: 40
2717 00:25:56.770081
2718 00:25:56.770129 Set Vref, RX VrefLevel [Byte0]: 41
2719 00:25:56.770178 [Byte1]: 41
2720 00:25:56.770225
2721 00:25:56.770273 Set Vref, RX VrefLevel [Byte0]: 42
2722 00:25:56.770322 [Byte1]: 42
2723 00:25:56.770370
2724 00:25:56.770418 Set Vref, RX VrefLevel [Byte0]: 43
2725 00:25:56.770467 [Byte1]: 43
2726 00:25:56.770515
2727 00:25:56.770564 Set Vref, RX VrefLevel [Byte0]: 44
2728 00:25:56.770612 [Byte1]: 44
2729 00:25:56.770660
2730 00:25:56.770708 Set Vref, RX VrefLevel [Byte0]: 45
2731 00:25:56.770757 [Byte1]: 45
2732 00:25:56.770805
2733 00:25:56.770853 Set Vref, RX VrefLevel [Byte0]: 46
2734 00:25:56.770901 [Byte1]: 46
2735 00:25:56.770950
2736 00:25:56.770998 Set Vref, RX VrefLevel [Byte0]: 47
2737 00:25:56.771046 [Byte1]: 47
2738 00:25:56.771094
2739 00:25:56.771142 Set Vref, RX VrefLevel [Byte0]: 48
2740 00:25:56.771190 [Byte1]: 48
2741 00:25:56.771238
2742 00:25:56.771286 Set Vref, RX VrefLevel [Byte0]: 49
2743 00:25:56.771334 [Byte1]: 49
2744 00:25:56.771383
2745 00:25:56.771432 Set Vref, RX VrefLevel [Byte0]: 50
2746 00:25:56.771480 [Byte1]: 50
2747 00:25:56.771527
2748 00:25:56.771574 Set Vref, RX VrefLevel [Byte0]: 51
2749 00:25:56.771623 [Byte1]: 51
2750 00:25:56.771671
2751 00:25:56.771718 Set Vref, RX VrefLevel [Byte0]: 52
2752 00:25:56.771767 [Byte1]: 52
2753 00:25:56.771814
2754 00:25:56.772058 Set Vref, RX VrefLevel [Byte0]: 53
2755 00:25:56.772143 [Byte1]: 53
2756 00:25:56.772223
2757 00:25:56.772297 Set Vref, RX VrefLevel [Byte0]: 54
2758 00:25:56.772348 [Byte1]: 54
2759 00:25:56.772398
2760 00:25:56.772447 Set Vref, RX VrefLevel [Byte0]: 55
2761 00:25:56.772496 [Byte1]: 55
2762 00:25:56.772544
2763 00:25:56.772592 Set Vref, RX VrefLevel [Byte0]: 56
2764 00:25:56.772641 [Byte1]: 56
2765 00:25:56.772699
2766 00:25:56.772748 Set Vref, RX VrefLevel [Byte0]: 57
2767 00:25:56.772797 [Byte1]: 57
2768 00:25:56.772845
2769 00:25:56.772894 Set Vref, RX VrefLevel [Byte0]: 58
2770 00:25:56.772943 [Byte1]: 58
2771 00:25:56.772992
2772 00:25:56.773039 Set Vref, RX VrefLevel [Byte0]: 59
2773 00:25:56.773089 [Byte1]: 59
2774 00:25:56.773137
2775 00:25:56.773186 Set Vref, RX VrefLevel [Byte0]: 60
2776 00:25:56.773235 [Byte1]: 60
2777 00:25:56.773284
2778 00:25:56.773332 Set Vref, RX VrefLevel [Byte0]: 61
2779 00:25:56.773381 [Byte1]: 61
2780 00:25:56.773429
2781 00:25:56.773478 Set Vref, RX VrefLevel [Byte0]: 62
2782 00:25:56.773527 [Byte1]: 62
2783 00:25:56.773575
2784 00:25:56.773622 Set Vref, RX VrefLevel [Byte0]: 63
2785 00:25:56.773672 [Byte1]: 63
2786 00:25:56.773721
2787 00:25:56.773770 Set Vref, RX VrefLevel [Byte0]: 64
2788 00:25:56.773819 [Byte1]: 64
2789 00:25:56.773867
2790 00:25:56.773915 Set Vref, RX VrefLevel [Byte0]: 65
2791 00:25:56.773963 [Byte1]: 65
2792 00:25:56.774011
2793 00:25:56.774058 Set Vref, RX VrefLevel [Byte0]: 66
2794 00:25:56.774107 [Byte1]: 66
2795 00:25:56.774154
2796 00:25:56.774202 Set Vref, RX VrefLevel [Byte0]: 67
2797 00:25:56.774251 [Byte1]: 67
2798 00:25:56.774299
2799 00:25:56.774347 Set Vref, RX VrefLevel [Byte0]: 68
2800 00:25:56.774395 [Byte1]: 68
2801 00:25:56.774443
2802 00:25:56.774492 Set Vref, RX VrefLevel [Byte0]: 69
2803 00:25:56.774540 [Byte1]: 69
2804 00:25:56.774587
2805 00:25:56.774635 Set Vref, RX VrefLevel [Byte0]: 70
2806 00:25:56.774683 [Byte1]: 70
2807 00:25:56.774732
2808 00:25:56.774780 Set Vref, RX VrefLevel [Byte0]: 71
2809 00:25:56.774829 [Byte1]: 71
2810 00:25:56.774877
2811 00:25:56.774925 Set Vref, RX VrefLevel [Byte0]: 72
2812 00:25:56.774973 [Byte1]: 72
2813 00:25:56.775021
2814 00:25:56.775070 Set Vref, RX VrefLevel [Byte0]: 73
2815 00:25:56.775118 [Byte1]: 73
2816 00:25:56.775167
2817 00:25:56.775215 Final RX Vref Byte 0 = 62 to rank0
2818 00:25:56.775264 Final RX Vref Byte 1 = 49 to rank0
2819 00:25:56.775313 Final RX Vref Byte 0 = 62 to rank1
2820 00:25:56.775361 Final RX Vref Byte 1 = 49 to rank1==
2821 00:25:56.775410 Dram Type= 6, Freq= 0, CH_0, rank 0
2822 00:25:56.775458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2823 00:25:56.775507 ==
2824 00:25:56.775555 DQS Delay:
2825 00:25:56.775603 DQS0 = 0, DQS1 = 0
2826 00:25:56.775651 DQM Delay:
2827 00:25:56.775700 DQM0 = 112, DQM1 = 100
2828 00:25:56.775749 DQ Delay:
2829 00:25:56.775798 DQ0 =110, DQ1 =112, DQ2 =114, DQ3 =106
2830 00:25:56.775846 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2831 00:25:56.775894 DQ8 =90, DQ9 =84, DQ10 =100, DQ11 =92
2832 00:25:56.775943 DQ12 =106, DQ13 =106, DQ14 =114, DQ15 =108
2833 00:25:56.775990
2834 00:25:56.776037
2835 00:25:56.776085 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbfb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2836 00:25:56.776134 CH0 RK0: MR19=303, MR18=FBFB
2837 00:25:56.776183 CH0_RK0: MR19=0x303, MR18=0xFBFB, DQSOSC=412, MR23=63, INC=38, DEC=25
2838 00:25:56.776236
2839 00:25:56.776319 ----->DramcWriteLeveling(PI) begin...
2840 00:25:56.776398 ==
2841 00:25:56.776475 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 00:25:56.776559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 00:25:56.776637 ==
2844 00:25:56.776698 Write leveling (Byte 0): 31 => 31
2845 00:25:56.776747 Write leveling (Byte 1): 31 => 31
2846 00:25:56.776796 DramcWriteLeveling(PI) end<-----
2847 00:25:56.776845
2848 00:25:56.776894 ==
2849 00:25:56.776943 Dram Type= 6, Freq= 0, CH_0, rank 1
2850 00:25:56.776992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2851 00:25:56.777040 ==
2852 00:25:56.777088 [Gating] SW mode calibration
2853 00:25:56.777137 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2854 00:25:56.777187 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2855 00:25:56.777235 0 15 0 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
2856 00:25:56.777284 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 00:25:56.777334 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 00:25:56.777382 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 00:25:56.777431 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 00:25:56.777479 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 00:25:56.777528 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2862 00:25:56.777577 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2863 00:25:56.777625 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
2864 00:25:56.777673 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 00:25:56.777723 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 00:25:56.777772 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 00:25:56.777821 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 00:25:56.777870 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 00:25:56.777918 1 0 24 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
2870 00:25:56.777966 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2871 00:25:56.778015 1 1 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2872 00:25:56.778064 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 00:25:56.778112 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 00:25:56.778160 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 00:25:56.778209 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 00:25:56.778257 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 00:25:56.778306 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2878 00:25:56.778354 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2879 00:25:56.778403 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2880 00:25:56.778451 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 00:25:56.778687 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 00:25:56.778741 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 00:25:56.778791 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 00:25:56.778841 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 00:25:56.778889 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 00:25:56.778939 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 00:25:56.778988 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 00:25:56.779036 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 00:25:56.779085 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 00:25:56.779133 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 00:25:56.779182 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 00:25:56.779231 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 00:25:56.779280 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 00:25:56.779328 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2895 00:25:56.779377 Total UI for P1: 0, mck2ui 16
2896 00:25:56.779426 best dqsien dly found for B0: ( 1, 3, 26)
2897 00:25:56.779474 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 00:25:56.779522 Total UI for P1: 0, mck2ui 16
2899 00:25:56.779573 best dqsien dly found for B1: ( 1, 3, 30)
2900 00:25:56.779622 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2901 00:25:56.779671 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2902 00:25:56.779720
2903 00:25:56.779769 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2904 00:25:56.779818 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2905 00:25:56.779867 [Gating] SW calibration Done
2906 00:25:56.779915 ==
2907 00:25:56.779963 Dram Type= 6, Freq= 0, CH_0, rank 1
2908 00:25:56.780012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2909 00:25:56.780061 ==
2910 00:25:56.780110 RX Vref Scan: 0
2911 00:25:56.780159
2912 00:25:56.780206 RX Vref 0 -> 0, step: 1
2913 00:25:56.780255
2914 00:25:56.780303 RX Delay -40 -> 252, step: 8
2915 00:25:56.780352 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2916 00:25:56.780406 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2917 00:25:56.780489 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2918 00:25:56.780568 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2919 00:25:56.780651 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2920 00:25:56.780717 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2921 00:25:56.780768 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2922 00:25:56.780818 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2923 00:25:56.780867 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2924 00:25:56.780915 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2925 00:25:56.780964 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2926 00:25:56.781013 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2927 00:25:56.781062 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2928 00:25:56.781110 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2929 00:25:56.781159 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2930 00:25:56.781207 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2931 00:25:56.781256 ==
2932 00:25:56.781304 Dram Type= 6, Freq= 0, CH_0, rank 1
2933 00:25:56.781353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2934 00:25:56.781403 ==
2935 00:25:56.781451 DQS Delay:
2936 00:25:56.781500 DQS0 = 0, DQS1 = 0
2937 00:25:56.781548 DQM Delay:
2938 00:25:56.912195 DQM0 = 111, DQM1 = 101
2939 00:25:56.912309 DQ Delay:
2940 00:25:56.912370 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2941 00:25:56.912427 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2942 00:25:56.912481 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2943 00:25:56.912532 DQ12 =107, DQ13 =111, DQ14 =111, DQ15 =107
2944 00:25:56.912583
2945 00:25:56.912633
2946 00:25:56.912729 ==
2947 00:25:56.912818 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 00:25:56.912909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 00:25:56.913006 ==
2950 00:25:56.913101
2951 00:25:56.913194
2952 00:25:56.913288 TX Vref Scan disable
2953 00:25:56.913383 == TX Byte 0 ==
2954 00:25:56.913478 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2955 00:25:56.913576 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2956 00:25:56.913668 == TX Byte 1 ==
2957 00:25:56.913761 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2958 00:25:56.913858 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2959 00:25:56.913951 ==
2960 00:25:56.914048 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 00:25:56.914146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 00:25:56.914242 ==
2963 00:25:56.914340 TX Vref=22, minBit 2, minWin=26, winSum=426
2964 00:25:56.914432 TX Vref=24, minBit 1, minWin=26, winSum=428
2965 00:25:56.914528 TX Vref=26, minBit 8, minWin=26, winSum=435
2966 00:25:56.914622 TX Vref=28, minBit 5, minWin=26, winSum=437
2967 00:25:56.914718 TX Vref=30, minBit 5, minWin=26, winSum=441
2968 00:25:56.914816 TX Vref=32, minBit 8, minWin=26, winSum=438
2969 00:25:56.914912 [TxChooseVref] Worse bit 5, Min win 26, Win sum 441, Final Vref 30
2970 00:25:56.915009
2971 00:25:56.915100 Final TX Range 1 Vref 30
2972 00:25:56.915193
2973 00:25:56.915284 ==
2974 00:25:56.915378 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 00:25:56.915472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 00:25:56.915568 ==
2977 00:25:56.915663
2978 00:25:56.915756
2979 00:25:56.915851 TX Vref Scan disable
2980 00:25:56.915942 == TX Byte 0 ==
2981 00:25:56.916034 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2982 00:25:56.916126 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2983 00:25:56.916220 == TX Byte 1 ==
2984 00:25:56.916316 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2985 00:25:56.916415 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2986 00:25:56.916511
2987 00:25:56.916607 [DATLAT]
2988 00:25:56.916703 Freq=1200, CH0 RK1
2989 00:25:56.916797
2990 00:25:56.916888 DATLAT Default: 0xd
2991 00:25:56.916982 0, 0xFFFF, sum = 0
2992 00:25:56.917079 1, 0xFFFF, sum = 0
2993 00:25:56.917178 2, 0xFFFF, sum = 0
2994 00:25:56.917275 3, 0xFFFF, sum = 0
2995 00:25:56.917373 4, 0xFFFF, sum = 0
2996 00:25:56.917465 5, 0xFFFF, sum = 0
2997 00:25:56.917565 6, 0xFFFF, sum = 0
2998 00:25:56.917664 7, 0xFFFF, sum = 0
2999 00:25:56.917759 8, 0xFFFF, sum = 0
3000 00:25:56.917862 9, 0xFFFF, sum = 0
3001 00:25:56.917961 10, 0xFFFF, sum = 0
3002 00:25:56.918056 11, 0xFFFF, sum = 0
3003 00:25:56.918151 12, 0x0, sum = 1
3004 00:25:56.918248 13, 0x0, sum = 2
3005 00:25:56.918342 14, 0x0, sum = 3
3006 00:25:56.918440 15, 0x0, sum = 4
3007 00:25:56.918537 best_step = 13
3008 00:25:56.918630
3009 00:25:56.918725 ==
3010 00:25:56.918816 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 00:25:56.918910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 00:25:56.919005 ==
3013 00:25:56.919101 RX Vref Scan: 0
3014 00:25:56.919192
3015 00:25:56.919285 RX Vref 0 -> 0, step: 1
3016 00:25:56.919378
3017 00:25:56.919472 RX Delay -37 -> 252, step: 4
3018 00:25:56.919786 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3019 00:25:56.919890 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3020 00:25:56.919991 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3021 00:25:56.920087 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3022 00:25:56.920186 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3023 00:25:56.920277 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3024 00:25:56.920368 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3025 00:25:56.920463 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3026 00:25:56.920557 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3027 00:25:56.920655 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3028 00:25:56.920745 iDelay=195, Bit 10, Center 102 (31 ~ 174) 144
3029 00:25:56.920839 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3030 00:25:56.920931 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3031 00:25:56.921026 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3032 00:25:56.921120 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3033 00:25:56.921215 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3034 00:25:56.921312 ==
3035 00:25:56.921402 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 00:25:56.921496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 00:25:56.921589 ==
3038 00:25:56.921681 DQS Delay:
3039 00:25:56.921778 DQS0 = 0, DQS1 = 0
3040 00:25:56.921874 DQM Delay:
3041 00:25:56.921975 DQM0 = 111, DQM1 = 100
3042 00:25:56.922073 DQ Delay:
3043 00:25:56.922169 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3044 00:25:56.922267 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3045 00:25:56.922358 DQ8 =90, DQ9 =84, DQ10 =102, DQ11 =92
3046 00:25:56.922454 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =108
3047 00:25:56.922549
3048 00:25:56.922644
3049 00:25:56.922741 [DQSOSCAuto] RK1, (LSB)MR18= 0x13fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 402 ps
3050 00:25:56.922834 CH0 RK1: MR19=403, MR18=13FB
3051 00:25:56.922930 CH0_RK1: MR19=0x403, MR18=0x13FB, DQSOSC=402, MR23=63, INC=40, DEC=27
3052 00:25:56.923022 [RxdqsGatingPostProcess] freq 1200
3053 00:25:56.923118 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3054 00:25:56.923216 best DQS0 dly(2T, 0.5T) = (0, 11)
3055 00:25:56.923311 best DQS1 dly(2T, 0.5T) = (0, 12)
3056 00:25:56.923408 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3057 00:25:56.923499 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3058 00:25:56.923593 best DQS0 dly(2T, 0.5T) = (0, 11)
3059 00:25:56.923688 best DQS1 dly(2T, 0.5T) = (0, 11)
3060 00:25:56.923783 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3061 00:25:56.923879 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3062 00:25:56.923974 Pre-setting of DQS Precalculation
3063 00:25:56.924070 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3064 00:25:56.924166 ==
3065 00:25:56.924262 Dram Type= 6, Freq= 0, CH_1, rank 0
3066 00:25:56.924354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3067 00:25:56.924451 ==
3068 00:25:56.924542 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3069 00:25:56.924641 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3070 00:25:56.924740 [CA 0] Center 37 (7~67) winsize 61
3071 00:25:56.924834 [CA 1] Center 37 (7~68) winsize 62
3072 00:25:56.924931 [CA 2] Center 34 (4~64) winsize 61
3073 00:25:56.925024 [CA 3] Center 34 (4~64) winsize 61
3074 00:25:56.925117 [CA 4] Center 34 (4~64) winsize 61
3075 00:25:56.925208 [CA 5] Center 33 (3~63) winsize 61
3076 00:25:56.925301
3077 00:25:56.925390 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3078 00:25:56.925484
3079 00:25:56.925576 [CATrainingPosCal] consider 1 rank data
3080 00:25:56.925667 u2DelayCellTimex100 = 270/100 ps
3081 00:25:56.925763 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3082 00:25:56.925859 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3083 00:25:56.925955 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3084 00:25:56.926051 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3085 00:25:56.926142 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3086 00:25:56.926237 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3087 00:25:56.926330
3088 00:25:56.926423 CA PerBit enable=1, Macro0, CA PI delay=33
3089 00:25:56.926521
3090 00:25:56.926612 [CBTSetCACLKResult] CA Dly = 33
3091 00:25:56.926706 CS Dly: 5 (0~36)
3092 00:25:56.926798 ==
3093 00:25:56.926890 Dram Type= 6, Freq= 0, CH_1, rank 1
3094 00:25:56.926981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3095 00:25:56.927078 ==
3096 00:25:56.927174 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3097 00:25:56.927269 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3098 00:25:56.927367 [CA 0] Center 37 (7~67) winsize 61
3099 00:25:56.927460 [CA 1] Center 37 (7~68) winsize 62
3100 00:25:56.927555 [CA 2] Center 34 (4~65) winsize 62
3101 00:25:56.927652 [CA 3] Center 33 (3~64) winsize 62
3102 00:25:56.927741 [CA 4] Center 34 (4~64) winsize 61
3103 00:25:56.927836 [CA 5] Center 33 (3~63) winsize 61
3104 00:25:56.927931
3105 00:25:56.928023 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3106 00:25:56.928118
3107 00:25:56.928209 [CATrainingPosCal] consider 2 rank data
3108 00:25:56.928303 u2DelayCellTimex100 = 270/100 ps
3109 00:25:56.928401 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3110 00:25:56.928496 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3111 00:25:56.928592 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3112 00:25:56.928689 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3113 00:25:56.928786 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3114 00:25:56.928883 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3115 00:25:56.928971
3116 00:25:56.929066 CA PerBit enable=1, Macro0, CA PI delay=33
3117 00:25:56.929164
3118 00:25:56.929390 [CBTSetCACLKResult] CA Dly = 33
3119 00:25:56.929485 CS Dly: 6 (0~39)
3120 00:25:56.929578
3121 00:25:56.929667 ----->DramcWriteLeveling(PI) begin...
3122 00:25:56.929757 ==
3123 00:25:56.929827 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 00:25:56.929897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3125 00:25:56.929965 ==
3126 00:25:56.930052 Write leveling (Byte 0): 26 => 26
3127 00:25:56.930139 Write leveling (Byte 1): 28 => 28
3128 00:25:56.930224 DramcWriteLeveling(PI) end<-----
3129 00:25:56.930310
3130 00:25:56.930396 ==
3131 00:25:56.930482 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 00:25:56.930568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 00:25:56.930654 ==
3134 00:25:56.930740 [Gating] SW mode calibration
3135 00:25:56.930825 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3136 00:25:56.930912 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3137 00:25:56.931190 0 15 0 | B1->B0 | 3030 2929 | 0 0 | (0 0) (0 0)
3138 00:25:56.931276 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 00:25:56.931370 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 00:25:56.931469 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 00:25:56.931562 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 00:25:56.931654 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 00:25:56.931749 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3144 00:25:56.931845 0 15 28 | B1->B0 | 2727 2a2a | 0 0 | (0 1) (0 1)
3145 00:25:56.931939 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 00:25:56.932033 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 00:25:56.932127 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 00:25:56.932218 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 00:25:56.932310 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 00:25:56.932406 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 00:25:56.932498 1 0 24 | B1->B0 | 2929 2424 | 1 0 | (0 0) (0 0)
3152 00:25:56.932593 1 0 28 | B1->B0 | 3b3b 3434 | 0 0 | (0 0) (0 0)
3153 00:25:56.932694 1 1 0 | B1->B0 | 4545 4141 | 0 0 | (0 0) (0 0)
3154 00:25:56.932788 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 00:25:56.932885 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 00:25:56.932977 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 00:25:56.933074 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 00:25:56.933172 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 00:25:56.933263 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 00:25:56.933356 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3161 00:25:56.933447 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 00:25:56.933541 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 00:25:56.933634 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 00:25:56.933725 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 00:25:56.933823 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 00:25:56.933916 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 00:25:56.934008 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 00:25:56.934103 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 00:25:56.934200 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 00:25:56.934295 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 00:25:56.934393 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 00:25:56.934484 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 00:25:56.934580 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 00:25:56.934673 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 00:25:56.934767 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 00:25:56.934864 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3177 00:25:56.934955 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 00:25:56.935049 Total UI for P1: 0, mck2ui 16
3179 00:25:56.935144 best dqsien dly found for B0: ( 1, 3, 28)
3180 00:25:56.935241 Total UI for P1: 0, mck2ui 16
3181 00:25:56.935339 best dqsien dly found for B1: ( 1, 3, 28)
3182 00:25:56.935434 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3183 00:25:56.935532 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3184 00:25:56.935622
3185 00:25:56.935717 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3186 00:25:56.935811 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3187 00:25:56.935907 [Gating] SW calibration Done
3188 00:25:56.936003 ==
3189 00:25:56.936095 Dram Type= 6, Freq= 0, CH_1, rank 0
3190 00:25:56.936192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3191 00:25:56.936285 ==
3192 00:25:56.936381 RX Vref Scan: 0
3193 00:25:56.936478
3194 00:25:56.936573 RX Vref 0 -> 0, step: 1
3195 00:25:56.936675
3196 00:25:56.936766 RX Delay -40 -> 252, step: 8
3197 00:25:56.936862 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3198 00:25:56.936958 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3199 00:25:56.937052 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3200 00:25:56.937144 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3201 00:25:56.937240 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3202 00:25:56.937335 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3203 00:25:56.937432 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3204 00:25:56.937529 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3205 00:25:56.937624 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3206 00:25:56.937722 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3207 00:25:56.937814 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3208 00:25:56.937912 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3209 00:25:56.938009 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3210 00:25:56.938105 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3211 00:25:56.938202 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3212 00:25:56.938294 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3213 00:25:56.938390 ==
3214 00:25:56.938483 Dram Type= 6, Freq= 0, CH_1, rank 0
3215 00:25:56.938581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3216 00:25:56.938678 ==
3217 00:25:56.938773 DQS Delay:
3218 00:25:56.938868 DQS0 = 0, DQS1 = 0
3219 00:25:56.938959 DQM Delay:
3220 00:25:56.939054 DQM0 = 113, DQM1 = 106
3221 00:25:56.939148 DQ Delay:
3222 00:25:56.939244 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =115
3223 00:25:56.939341 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3224 00:25:56.939436 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3225 00:25:56.939534 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3226 00:25:56.939625
3227 00:25:56.939718
3228 00:25:56.939810 ==
3229 00:25:56.939905 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 00:25:56.940004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 00:25:56.940096 ==
3232 00:25:56.940191
3233 00:25:56.940282
3234 00:25:56.940376 TX Vref Scan disable
3235 00:25:56.940473 == TX Byte 0 ==
3236 00:25:56.940564 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3237 00:25:56.940664 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3238 00:25:56.940759 == TX Byte 1 ==
3239 00:25:56.940853 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3240 00:25:56.940944 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3241 00:25:56.941034 ==
3242 00:25:56.941128 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 00:25:56.941425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 00:25:56.941523 ==
3245 00:25:56.941623 TX Vref=22, minBit 10, minWin=24, winSum=411
3246 00:25:56.941723 TX Vref=24, minBit 8, minWin=25, winSum=414
3247 00:25:56.941822 TX Vref=26, minBit 9, minWin=25, winSum=419
3248 00:25:56.941919 TX Vref=28, minBit 9, minWin=25, winSum=422
3249 00:25:56.942014 TX Vref=30, minBit 9, minWin=25, winSum=423
3250 00:25:56.942112 TX Vref=32, minBit 9, minWin=25, winSum=425
3251 00:25:56.942207 [TxChooseVref] Worse bit 9, Min win 25, Win sum 425, Final Vref 32
3252 00:25:56.942301
3253 00:25:56.942394 Final TX Range 1 Vref 32
3254 00:25:56.942484
3255 00:25:56.942579 ==
3256 00:25:56.942675 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 00:25:56.942768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 00:25:56.942863 ==
3259 00:25:56.942958
3260 00:25:56.943052
3261 00:25:56.943144 TX Vref Scan disable
3262 00:25:56.943240 == TX Byte 0 ==
3263 00:25:56.943335 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3264 00:25:56.943429 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3265 00:25:56.943519 == TX Byte 1 ==
3266 00:25:56.943614 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3267 00:25:56.943710 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3268 00:25:56.943803
3269 00:25:56.943894 [DATLAT]
3270 00:25:56.943985 Freq=1200, CH1 RK0
3271 00:25:56.944074
3272 00:25:56.944169 DATLAT Default: 0xd
3273 00:25:56.944259 0, 0xFFFF, sum = 0
3274 00:25:56.944354 1, 0xFFFF, sum = 0
3275 00:25:56.944452 2, 0xFFFF, sum = 0
3276 00:25:56.944544 3, 0xFFFF, sum = 0
3277 00:25:56.944649 4, 0xFFFF, sum = 0
3278 00:25:56.944749 5, 0xFFFF, sum = 0
3279 00:25:56.944844 6, 0xFFFF, sum = 0
3280 00:25:56.944938 7, 0xFFFF, sum = 0
3281 00:25:56.945035 8, 0xFFFF, sum = 0
3282 00:25:56.945128 9, 0xFFFF, sum = 0
3283 00:25:56.945226 10, 0xFFFF, sum = 0
3284 00:25:56.945325 11, 0xFFFF, sum = 0
3285 00:25:56.945420 12, 0x0, sum = 1
3286 00:25:56.945512 13, 0x0, sum = 2
3287 00:25:56.945609 14, 0x0, sum = 3
3288 00:25:56.945703 15, 0x0, sum = 4
3289 00:25:56.945797 best_step = 13
3290 00:25:56.945886
3291 00:25:56.945983 ==
3292 00:25:56.946079 Dram Type= 6, Freq= 0, CH_1, rank 0
3293 00:25:56.946177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3294 00:25:56.946270 ==
3295 00:25:56.946364 RX Vref Scan: 1
3296 00:25:56.946458
3297 00:25:56.946550 Set Vref Range= 32 -> 127
3298 00:25:56.946640
3299 00:25:56.946732 RX Vref 32 -> 127, step: 1
3300 00:25:56.946825
3301 00:25:56.946920 RX Delay -21 -> 252, step: 4
3302 00:25:56.947012
3303 00:25:56.947102 Set Vref, RX VrefLevel [Byte0]: 32
3304 00:25:56.947192 [Byte1]: 32
3305 00:25:56.947288
3306 00:25:56.947378 Set Vref, RX VrefLevel [Byte0]: 33
3307 00:25:56.947473 [Byte1]: 33
3308 00:25:56.947565
3309 00:25:56.947660 Set Vref, RX VrefLevel [Byte0]: 34
3310 00:25:56.947756 [Byte1]: 34
3311 00:25:56.947847
3312 00:25:56.947941 Set Vref, RX VrefLevel [Byte0]: 35
3313 00:25:56.948033 [Byte1]: 35
3314 00:25:56.948128
3315 00:25:56.948223 Set Vref, RX VrefLevel [Byte0]: 36
3316 00:25:56.948317 [Byte1]: 36
3317 00:25:56.948411
3318 00:25:56.948502 Set Vref, RX VrefLevel [Byte0]: 37
3319 00:25:56.948598 [Byte1]: 37
3320 00:25:56.948699
3321 00:25:56.948794 Set Vref, RX VrefLevel [Byte0]: 38
3322 00:25:56.948887 [Byte1]: 38
3323 00:25:56.948978
3324 00:25:56.949067 Set Vref, RX VrefLevel [Byte0]: 39
3325 00:25:56.949164 [Byte1]: 39
3326 00:25:56.949260
3327 00:25:56.949349 Set Vref, RX VrefLevel [Byte0]: 40
3328 00:25:56.949441 [Byte1]: 40
3329 00:25:56.949530
3330 00:25:56.949626 Set Vref, RX VrefLevel [Byte0]: 41
3331 00:25:56.949715 [Byte1]: 41
3332 00:25:56.949810
3333 00:25:56.949901 Set Vref, RX VrefLevel [Byte0]: 42
3334 00:25:56.949997 [Byte1]: 42
3335 00:25:56.950090
3336 00:25:56.950178 Set Vref, RX VrefLevel [Byte0]: 43
3337 00:25:56.950272 [Byte1]: 43
3338 00:25:56.950362
3339 00:25:56.950456 Set Vref, RX VrefLevel [Byte0]: 44
3340 00:25:56.950550 [Byte1]: 44
3341 00:25:56.950644
3342 00:25:56.950740 Set Vref, RX VrefLevel [Byte0]: 45
3343 00:25:56.950830 [Byte1]: 45
3344 00:25:56.950922
3345 00:25:56.951013 Set Vref, RX VrefLevel [Byte0]: 46
3346 00:25:56.951108 [Byte1]: 46
3347 00:25:56.951199
3348 00:25:56.951294 Set Vref, RX VrefLevel [Byte0]: 47
3349 00:25:56.951390 [Byte1]: 47
3350 00:25:56.951483
3351 00:25:56.951577 Set Vref, RX VrefLevel [Byte0]: 48
3352 00:25:56.951667 [Byte1]: 48
3353 00:25:56.951761
3354 00:25:56.951855 Set Vref, RX VrefLevel [Byte0]: 49
3355 00:25:56.951947 [Byte1]: 49
3356 00:25:56.952041
3357 00:25:56.952130 Set Vref, RX VrefLevel [Byte0]: 50
3358 00:25:56.952220 [Byte1]: 50
3359 00:25:56.952307
3360 00:25:56.952400 Set Vref, RX VrefLevel [Byte0]: 51
3361 00:25:56.952497 [Byte1]: 51
3362 00:25:56.952592
3363 00:25:56.952688 Set Vref, RX VrefLevel [Byte0]: 52
3364 00:25:56.952783 [Byte1]: 52
3365 00:25:56.952878
3366 00:25:56.952968 Set Vref, RX VrefLevel [Byte0]: 53
3367 00:25:56.953063 [Byte1]: 53
3368 00:25:56.953158
3369 00:25:56.953250 Set Vref, RX VrefLevel [Byte0]: 54
3370 00:25:56.953341 [Byte1]: 54
3371 00:25:56.953432
3372 00:25:56.953528 Set Vref, RX VrefLevel [Byte0]: 55
3373 00:25:56.953620 [Byte1]: 55
3374 00:25:56.953714
3375 00:25:56.953808 Set Vref, RX VrefLevel [Byte0]: 56
3376 00:25:56.953900 [Byte1]: 56
3377 00:25:56.953993
3378 00:25:56.954081 Set Vref, RX VrefLevel [Byte0]: 57
3379 00:25:56.954177 [Byte1]: 57
3380 00:25:56.954273
3381 00:25:56.954363 Set Vref, RX VrefLevel [Byte0]: 58
3382 00:25:56.954457 [Byte1]: 58
3383 00:25:56.954552
3384 00:25:56.954644 Set Vref, RX VrefLevel [Byte0]: 59
3385 00:25:56.954734 [Byte1]: 59
3386 00:25:56.954830
3387 00:25:56.954925 Set Vref, RX VrefLevel [Byte0]: 60
3388 00:25:56.955017 [Byte1]: 60
3389 00:25:56.955109
3390 00:25:56.955205 Set Vref, RX VrefLevel [Byte0]: 61
3391 00:25:56.955296 [Byte1]: 61
3392 00:25:56.955387
3393 00:25:56.955477 Set Vref, RX VrefLevel [Byte0]: 62
3394 00:25:56.955572 [Byte1]: 62
3395 00:25:56.955668
3396 00:25:56.955758 Set Vref, RX VrefLevel [Byte0]: 63
3397 00:25:56.955853 [Byte1]: 63
3398 00:25:56.955947
3399 00:25:56.956043 Set Vref, RX VrefLevel [Byte0]: 64
3400 00:25:56.956130 [Byte1]: 64
3401 00:25:56.956224
3402 00:25:56.956319 Final RX Vref Byte 0 = 60 to rank0
3403 00:25:56.956415 Final RX Vref Byte 1 = 50 to rank0
3404 00:25:56.956509 Final RX Vref Byte 0 = 60 to rank1
3405 00:25:56.956601 Final RX Vref Byte 1 = 50 to rank1==
3406 00:25:56.956703 Dram Type= 6, Freq= 0, CH_1, rank 0
3407 00:25:56.956786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3408 00:25:56.956866 ==
3409 00:25:56.956944 DQS Delay:
3410 00:25:56.957215 DQS0 = 0, DQS1 = 0
3411 00:25:56.957297 DQM Delay:
3412 00:25:56.957375 DQM0 = 114, DQM1 = 106
3413 00:25:56.957452 DQ Delay:
3414 00:25:56.957530 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =112
3415 00:25:56.957608 DQ4 =112, DQ5 =122, DQ6 =124, DQ7 =112
3416 00:25:56.957686 DQ8 =94, DQ9 =98, DQ10 =104, DQ11 =100
3417 00:25:56.957764 DQ12 =116, DQ13 =110, DQ14 =116, DQ15 =112
3418 00:25:56.957840
3419 00:25:56.957916
3420 00:25:56.957994 [DQSOSCAuto] RK0, (LSB)MR18= 0xf2f9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 415 ps
3421 00:25:56.958074 CH1 RK0: MR19=303, MR18=F2F9
3422 00:25:56.958152 CH1_RK0: MR19=0x303, MR18=0xF2F9, DQSOSC=412, MR23=63, INC=38, DEC=25
3423 00:25:56.958229
3424 00:25:56.958305 ----->DramcWriteLeveling(PI) begin...
3425 00:25:56.958383 ==
3426 00:25:56.958460 Dram Type= 6, Freq= 0, CH_1, rank 1
3427 00:25:56.958537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3428 00:25:56.958613 ==
3429 00:25:56.958690 Write leveling (Byte 0): 23 => 23
3430 00:25:56.958767 Write leveling (Byte 1): 28 => 28
3431 00:25:56.958844 DramcWriteLeveling(PI) end<-----
3432 00:25:56.958920
3433 00:25:56.958996 ==
3434 00:25:56.959072 Dram Type= 6, Freq= 0, CH_1, rank 1
3435 00:25:56.959149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3436 00:25:56.959226 ==
3437 00:25:56.959303 [Gating] SW mode calibration
3438 00:25:56.959381 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3439 00:25:56.959460 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3440 00:25:56.959537 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 00:25:56.959615 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 00:25:56.959692 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 00:25:56.959769 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 00:25:56.959856 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 00:25:56.959936 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3446 00:25:56.960014 0 15 24 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
3447 00:25:56.960091 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3448 00:25:56.960169 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 00:25:56.960246 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 00:25:56.960324 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 00:25:56.960401 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 00:25:56.960479 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 00:25:56.960556 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3454 00:25:56.960634 1 0 24 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
3455 00:25:56.960724 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3456 00:25:56.960802 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 00:25:56.960881 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 00:25:56.960959 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 00:25:56.961036 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 00:25:56.961114 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 00:25:56.961191 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3462 00:25:56.961268 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3463 00:25:56.961346 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 00:25:56.961423 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 00:25:56.961501 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 00:25:56.961578 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 00:25:56.961656 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 00:25:56.961733 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 00:25:56.961810 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 00:25:56.961887 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 00:25:56.961966 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 00:25:56.962017 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 00:25:56.962067 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 00:25:56.962116 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 00:25:56.962165 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 00:25:56.962214 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 00:25:56.962263 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 00:25:56.962312 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3479 00:25:56.962361 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3480 00:25:56.962410 Total UI for P1: 0, mck2ui 16
3481 00:25:56.962459 best dqsien dly found for B0: ( 1, 3, 24)
3482 00:25:56.962508 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 00:25:56.962558 Total UI for P1: 0, mck2ui 16
3484 00:25:56.962606 best dqsien dly found for B1: ( 1, 3, 26)
3485 00:25:56.962655 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3486 00:25:56.962704 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3487 00:25:56.962753
3488 00:25:56.962802 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3489 00:25:56.962851 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3490 00:25:56.962899 [Gating] SW calibration Done
3491 00:25:56.962947 ==
3492 00:25:56.962997 Dram Type= 6, Freq= 0, CH_1, rank 1
3493 00:25:56.963046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 00:25:56.963094 ==
3495 00:25:56.963143 RX Vref Scan: 0
3496 00:25:56.963191
3497 00:25:56.963239 RX Vref 0 -> 0, step: 1
3498 00:25:56.963288
3499 00:25:56.963336 RX Delay -40 -> 252, step: 8
3500 00:25:56.963385 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
3501 00:25:56.963435 iDelay=200, Bit 1, Center 103 (32 ~ 175) 144
3502 00:25:56.963498 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3503 00:25:56.963564 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3504 00:25:56.963614 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3505 00:25:56.963672 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3506 00:25:56.963731 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3507 00:25:56.963786 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3508 00:25:56.963855 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3509 00:25:56.963909 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3510 00:25:56.963959 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3511 00:25:56.964007 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3512 00:25:56.964246 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3513 00:25:56.964300 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3514 00:25:56.964350 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3515 00:25:56.964399 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3516 00:25:56.964448 ==
3517 00:25:56.964496 Dram Type= 6, Freq= 0, CH_1, rank 1
3518 00:25:56.964545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3519 00:25:56.964594 ==
3520 00:25:56.964649 DQS Delay:
3521 00:25:56.964701 DQS0 = 0, DQS1 = 0
3522 00:25:56.964750 DQM Delay:
3523 00:25:56.964799 DQM0 = 109, DQM1 = 107
3524 00:25:56.964847 DQ Delay:
3525 00:25:56.964896 DQ0 =111, DQ1 =103, DQ2 =99, DQ3 =107
3526 00:25:56.964944 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3527 00:25:56.964992 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3528 00:25:56.965040 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3529 00:25:56.965090
3530 00:25:56.965138
3531 00:25:56.965185 ==
3532 00:25:56.965234 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 00:25:56.965283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 00:25:56.965332 ==
3535 00:25:56.965379
3536 00:25:56.965427
3537 00:25:56.965474 TX Vref Scan disable
3538 00:25:56.965522 == TX Byte 0 ==
3539 00:25:56.965570 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3540 00:25:56.965619 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3541 00:25:56.965667 == TX Byte 1 ==
3542 00:25:56.965715 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3543 00:25:56.965764 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3544 00:25:56.965812 ==
3545 00:25:56.965860 Dram Type= 6, Freq= 0, CH_1, rank 1
3546 00:25:56.965931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3547 00:25:56.966011 ==
3548 00:25:56.966064 TX Vref=22, minBit 1, minWin=25, winSum=420
3549 00:25:56.966114 TX Vref=24, minBit 0, minWin=26, winSum=424
3550 00:25:56.966163 TX Vref=26, minBit 0, minWin=26, winSum=433
3551 00:25:56.966213 TX Vref=28, minBit 1, minWin=26, winSum=431
3552 00:25:56.966262 TX Vref=30, minBit 8, minWin=25, winSum=429
3553 00:25:56.966317 TX Vref=32, minBit 1, minWin=26, winSum=429
3554 00:25:56.966375 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 26
3555 00:25:56.966425
3556 00:25:56.966473 Final TX Range 1 Vref 26
3557 00:25:56.966523
3558 00:25:56.966571 ==
3559 00:25:56.966619 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 00:25:56.966668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 00:25:56.966717 ==
3562 00:25:56.966765
3563 00:25:56.966813
3564 00:25:56.966861 TX Vref Scan disable
3565 00:25:56.966910 == TX Byte 0 ==
3566 00:25:56.966959 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3567 00:25:56.967008 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3568 00:25:56.967057 == TX Byte 1 ==
3569 00:25:56.967106 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3570 00:25:56.967155 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3571 00:25:56.967204
3572 00:25:56.967251 [DATLAT]
3573 00:25:56.967301 Freq=1200, CH1 RK1
3574 00:25:56.967350
3575 00:25:56.967398 DATLAT Default: 0xd
3576 00:25:56.967446 0, 0xFFFF, sum = 0
3577 00:25:56.967496 1, 0xFFFF, sum = 0
3578 00:25:56.967545 2, 0xFFFF, sum = 0
3579 00:25:56.967594 3, 0xFFFF, sum = 0
3580 00:25:56.967642 4, 0xFFFF, sum = 0
3581 00:25:56.967691 5, 0xFFFF, sum = 0
3582 00:25:56.967739 6, 0xFFFF, sum = 0
3583 00:25:56.967788 7, 0xFFFF, sum = 0
3584 00:25:56.967837 8, 0xFFFF, sum = 0
3585 00:25:56.967887 9, 0xFFFF, sum = 0
3586 00:25:56.967936 10, 0xFFFF, sum = 0
3587 00:25:56.967984 11, 0xFFFF, sum = 0
3588 00:25:56.968033 12, 0x0, sum = 1
3589 00:25:56.968082 13, 0x0, sum = 2
3590 00:25:56.968130 14, 0x0, sum = 3
3591 00:25:56.968178 15, 0x0, sum = 4
3592 00:25:56.968227 best_step = 13
3593 00:25:56.968275
3594 00:25:56.968322 ==
3595 00:25:56.968370 Dram Type= 6, Freq= 0, CH_1, rank 1
3596 00:25:56.968418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3597 00:25:56.968466 ==
3598 00:25:56.968514 RX Vref Scan: 0
3599 00:25:56.968562
3600 00:25:56.968610 RX Vref 0 -> 0, step: 1
3601 00:25:56.968666
3602 00:25:56.968716 RX Delay -21 -> 252, step: 4
3603 00:25:56.968765 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3604 00:25:56.968814 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3605 00:25:56.968863 iDelay=195, Bit 2, Center 102 (31 ~ 174) 144
3606 00:25:56.968911 iDelay=195, Bit 3, Center 110 (43 ~ 178) 136
3607 00:25:56.968960 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3608 00:25:56.969008 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3609 00:25:56.969056 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3610 00:25:56.969104 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3611 00:25:56.969152 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3612 00:25:56.969201 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3613 00:25:56.969251 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3614 00:25:56.969300 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3615 00:25:56.969349 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3616 00:25:56.969397 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3617 00:25:56.969446 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3618 00:25:56.969494 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3619 00:25:56.969542 ==
3620 00:25:56.969590 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 00:25:56.969640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 00:25:56.969688 ==
3623 00:25:56.969736 DQS Delay:
3624 00:25:56.969784 DQS0 = 0, DQS1 = 0
3625 00:25:56.969832 DQM Delay:
3626 00:25:56.969880 DQM0 = 112, DQM1 = 109
3627 00:25:56.969929 DQ Delay:
3628 00:25:56.969977 DQ0 =114, DQ1 =108, DQ2 =102, DQ3 =110
3629 00:25:56.970026 DQ4 =110, DQ5 =120, DQ6 =122, DQ7 =110
3630 00:25:56.970075 DQ8 =96, DQ9 =100, DQ10 =112, DQ11 =102
3631 00:25:56.970124 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =116
3632 00:25:56.970173
3633 00:25:56.970220
3634 00:25:56.970269 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb0b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3635 00:25:56.970319 CH1 RK1: MR19=304, MR18=FB0B
3636 00:25:56.970368 CH1_RK1: MR19=0x304, MR18=0xFB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
3637 00:25:56.970416 [RxdqsGatingPostProcess] freq 1200
3638 00:25:56.970464 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3639 00:25:56.970512 best DQS0 dly(2T, 0.5T) = (0, 11)
3640 00:25:56.970560 best DQS1 dly(2T, 0.5T) = (0, 11)
3641 00:25:56.970609 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3642 00:25:56.970658 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3643 00:25:56.970706 best DQS0 dly(2T, 0.5T) = (0, 11)
3644 00:25:56.970754 best DQS1 dly(2T, 0.5T) = (0, 11)
3645 00:25:56.970802 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3646 00:25:56.970850 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3647 00:25:56.970898 Pre-setting of DQS Precalculation
3648 00:25:56.970947 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3649 00:25:56.970996 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3650 00:25:56.971236 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3651 00:25:56.971293
3652 00:25:56.971342
3653 00:25:56.971392 [Calibration Summary] 2400 Mbps
3654 00:25:56.971441 CH 0, Rank 0
3655 00:25:56.971490 SW Impedance : PASS
3656 00:25:56.971539 DUTY Scan : NO K
3657 00:25:56.971588 ZQ Calibration : PASS
3658 00:25:56.971636 Jitter Meter : NO K
3659 00:25:56.971685 CBT Training : PASS
3660 00:25:56.971733 Write leveling : PASS
3661 00:25:56.971782 RX DQS gating : PASS
3662 00:25:56.971830 RX DQ/DQS(RDDQC) : PASS
3663 00:25:56.971879 TX DQ/DQS : PASS
3664 00:25:56.971941 RX DATLAT : PASS
3665 00:25:56.971990 RX DQ/DQS(Engine): PASS
3666 00:25:56.972038 TX OE : NO K
3667 00:25:56.972087 All Pass.
3668 00:25:56.972135
3669 00:25:56.972184 CH 0, Rank 1
3670 00:25:56.972232 SW Impedance : PASS
3671 00:25:56.972280 DUTY Scan : NO K
3672 00:25:56.972329 ZQ Calibration : PASS
3673 00:25:56.972377 Jitter Meter : NO K
3674 00:25:56.972425 CBT Training : PASS
3675 00:25:56.972473 Write leveling : PASS
3676 00:25:56.972520 RX DQS gating : PASS
3677 00:25:56.972568 RX DQ/DQS(RDDQC) : PASS
3678 00:25:56.972616 TX DQ/DQS : PASS
3679 00:25:56.972674 RX DATLAT : PASS
3680 00:25:56.972723 RX DQ/DQS(Engine): PASS
3681 00:25:56.972772 TX OE : NO K
3682 00:25:56.972819 All Pass.
3683 00:25:56.972868
3684 00:25:56.972916 CH 1, Rank 0
3685 00:25:56.972964 SW Impedance : PASS
3686 00:25:56.973012 DUTY Scan : NO K
3687 00:25:56.973059 ZQ Calibration : PASS
3688 00:25:56.973107 Jitter Meter : NO K
3689 00:25:56.973155 CBT Training : PASS
3690 00:25:56.973203 Write leveling : PASS
3691 00:25:56.973252 RX DQS gating : PASS
3692 00:25:56.973300 RX DQ/DQS(RDDQC) : PASS
3693 00:25:56.973348 TX DQ/DQS : PASS
3694 00:25:56.973396 RX DATLAT : PASS
3695 00:25:56.973444 RX DQ/DQS(Engine): PASS
3696 00:25:56.973492 TX OE : NO K
3697 00:25:56.973542 All Pass.
3698 00:25:56.973590
3699 00:25:56.973639 CH 1, Rank 1
3700 00:25:56.973687 SW Impedance : PASS
3701 00:25:56.973736 DUTY Scan : NO K
3702 00:25:56.973785 ZQ Calibration : PASS
3703 00:25:56.973833 Jitter Meter : NO K
3704 00:25:56.973885 CBT Training : PASS
3705 00:25:56.973938 Write leveling : PASS
3706 00:25:56.973986 RX DQS gating : PASS
3707 00:25:56.974034 RX DQ/DQS(RDDQC) : PASS
3708 00:25:56.974082 TX DQ/DQS : PASS
3709 00:25:56.974130 RX DATLAT : PASS
3710 00:25:56.974178 RX DQ/DQS(Engine): PASS
3711 00:25:56.974227 TX OE : NO K
3712 00:25:56.974276 All Pass.
3713 00:25:56.974324
3714 00:25:56.974372 DramC Write-DBI off
3715 00:25:56.974421 PER_BANK_REFRESH: Hybrid Mode
3716 00:25:56.974470 TX_TRACKING: ON
3717 00:25:56.974519 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3718 00:25:56.974569 [FAST_K] Save calibration result to emmc
3719 00:25:56.974618 dramc_set_vcore_voltage set vcore to 650000
3720 00:25:56.974667 Read voltage for 600, 5
3721 00:25:56.974716 Vio18 = 0
3722 00:25:56.974765 Vcore = 650000
3723 00:25:56.974813 Vdram = 0
3724 00:25:56.974861 Vddq = 0
3725 00:25:56.974909 Vmddr = 0
3726 00:25:56.974957 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3727 00:25:56.975006 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3728 00:25:56.975055 MEM_TYPE=3, freq_sel=19
3729 00:25:56.975103 sv_algorithm_assistance_LP4_1600
3730 00:25:56.975152 ============ PULL DRAM RESETB DOWN ============
3731 00:25:56.975201 ========== PULL DRAM RESETB DOWN end =========
3732 00:25:56.975249 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3733 00:25:56.975298 ===================================
3734 00:25:56.975346 LPDDR4 DRAM CONFIGURATION
3735 00:25:56.975395 ===================================
3736 00:25:56.975444 EX_ROW_EN[0] = 0x0
3737 00:25:56.975491 EX_ROW_EN[1] = 0x0
3738 00:25:56.975541 LP4Y_EN = 0x0
3739 00:25:56.975590 WORK_FSP = 0x0
3740 00:25:56.975638 WL = 0x2
3741 00:25:56.975687 RL = 0x2
3742 00:25:56.975735 BL = 0x2
3743 00:25:56.975783 RPST = 0x0
3744 00:25:56.975832 RD_PRE = 0x0
3745 00:25:56.975880 WR_PRE = 0x1
3746 00:25:56.975928 WR_PST = 0x0
3747 00:25:56.975975 DBI_WR = 0x0
3748 00:25:56.976022 DBI_RD = 0x0
3749 00:25:56.976070 OTF = 0x1
3750 00:25:56.976119 ===================================
3751 00:25:56.976168 ===================================
3752 00:25:56.976216 ANA top config
3753 00:25:56.976264 ===================================
3754 00:25:56.976312 DLL_ASYNC_EN = 0
3755 00:25:56.976361 ALL_SLAVE_EN = 1
3756 00:25:56.976409 NEW_RANK_MODE = 1
3757 00:25:56.976457 DLL_IDLE_MODE = 1
3758 00:25:56.976505 LP45_APHY_COMB_EN = 1
3759 00:25:56.976552 TX_ODT_DIS = 1
3760 00:25:56.976601 NEW_8X_MODE = 1
3761 00:25:56.976656 ===================================
3762 00:25:56.976707 ===================================
3763 00:25:56.976755 data_rate = 1200
3764 00:25:56.976802 CKR = 1
3765 00:25:56.976850 DQ_P2S_RATIO = 8
3766 00:25:56.976898 ===================================
3767 00:25:56.976947 CA_P2S_RATIO = 8
3768 00:25:56.976994 DQ_CA_OPEN = 0
3769 00:25:56.977043 DQ_SEMI_OPEN = 0
3770 00:25:56.977091 CA_SEMI_OPEN = 0
3771 00:25:56.977139 CA_FULL_RATE = 0
3772 00:25:56.977187 DQ_CKDIV4_EN = 1
3773 00:25:56.977235 CA_CKDIV4_EN = 1
3774 00:25:56.977283 CA_PREDIV_EN = 0
3775 00:25:56.977331 PH8_DLY = 0
3776 00:25:56.977380 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3777 00:25:56.977428 DQ_AAMCK_DIV = 4
3778 00:25:56.977475 CA_AAMCK_DIV = 4
3779 00:25:56.977524 CA_ADMCK_DIV = 4
3780 00:25:56.977572 DQ_TRACK_CA_EN = 0
3781 00:25:56.977621 CA_PICK = 600
3782 00:25:56.977670 CA_MCKIO = 600
3783 00:25:56.977718 MCKIO_SEMI = 0
3784 00:25:56.977766 PLL_FREQ = 2288
3785 00:25:56.977815 DQ_UI_PI_RATIO = 32
3786 00:25:56.977864 CA_UI_PI_RATIO = 0
3787 00:25:56.977912 ===================================
3788 00:25:56.977960 ===================================
3789 00:25:56.978009 memory_type:LPDDR4
3790 00:25:56.978057 GP_NUM : 10
3791 00:25:56.978106 SRAM_EN : 1
3792 00:25:56.978154 MD32_EN : 0
3793 00:25:56.978201 ===================================
3794 00:25:56.978250 [ANA_INIT] >>>>>>>>>>>>>>
3795 00:25:56.978298 <<<<<< [CONFIGURE PHASE]: ANA_TX
3796 00:25:56.978348 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3797 00:25:56.978396 ===================================
3798 00:25:56.978445 data_rate = 1200,PCW = 0X5800
3799 00:25:56.978677 ===================================
3800 00:25:56.978732 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3801 00:25:56.978782 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3802 00:25:56.978831 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3803 00:25:56.978881 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3804 00:25:56.978930 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3805 00:25:56.978978 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3806 00:25:56.979026 [ANA_INIT] flow start
3807 00:25:56.979074 [ANA_INIT] PLL >>>>>>>>
3808 00:25:56.979122 [ANA_INIT] PLL <<<<<<<<
3809 00:25:56.979170 [ANA_INIT] MIDPI >>>>>>>>
3810 00:25:56.979218 [ANA_INIT] MIDPI <<<<<<<<
3811 00:25:56.979266 [ANA_INIT] DLL >>>>>>>>
3812 00:25:56.979314 [ANA_INIT] flow end
3813 00:25:56.979362 ============ LP4 DIFF to SE enter ============
3814 00:25:56.979410 ============ LP4 DIFF to SE exit ============
3815 00:25:56.979458 [ANA_INIT] <<<<<<<<<<<<<
3816 00:25:56.979506 [Flow] Enable top DCM control >>>>>
3817 00:25:56.979555 [Flow] Enable top DCM control <<<<<
3818 00:25:56.979603 Enable DLL master slave shuffle
3819 00:25:56.979652 ==============================================================
3820 00:25:56.979701 Gating Mode config
3821 00:25:56.979749 ==============================================================
3822 00:25:56.979798 Config description:
3823 00:25:56.979847 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3824 00:25:56.979897 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3825 00:25:56.979946 SELPH_MODE 0: By rank 1: By Phase
3826 00:25:56.979996 ==============================================================
3827 00:25:56.980045 GAT_TRACK_EN = 1
3828 00:25:56.980093 RX_GATING_MODE = 2
3829 00:25:56.980142 RX_GATING_TRACK_MODE = 2
3830 00:25:56.980190 SELPH_MODE = 1
3831 00:25:56.980238 PICG_EARLY_EN = 1
3832 00:25:56.980286 VALID_LAT_VALUE = 1
3833 00:25:56.980334 ==============================================================
3834 00:25:56.980383 Enter into Gating configuration >>>>
3835 00:25:56.980431 Exit from Gating configuration <<<<
3836 00:25:56.980480 Enter into DVFS_PRE_config >>>>>
3837 00:25:56.980529 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3838 00:25:56.980579 Exit from DVFS_PRE_config <<<<<
3839 00:25:56.980627 Enter into PICG configuration >>>>
3840 00:25:56.980686 Exit from PICG configuration <<<<
3841 00:25:56.980735 [RX_INPUT] configuration >>>>>
3842 00:25:56.980784 [RX_INPUT] configuration <<<<<
3843 00:25:56.980843 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3844 00:25:56.986679 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3845 00:25:56.993660 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3846 00:25:56.996555 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3847 00:25:57.003308 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3848 00:25:57.009810 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3849 00:25:57.013374 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3850 00:25:57.019956 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3851 00:25:57.023387 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3852 00:25:57.026348 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3853 00:25:57.029854 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3854 00:25:57.036471 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3855 00:25:57.040000 ===================================
3856 00:25:57.040095 LPDDR4 DRAM CONFIGURATION
3857 00:25:57.043079 ===================================
3858 00:25:57.046115 EX_ROW_EN[0] = 0x0
3859 00:25:57.049568 EX_ROW_EN[1] = 0x0
3860 00:25:57.049645 LP4Y_EN = 0x0
3861 00:25:57.053098 WORK_FSP = 0x0
3862 00:25:57.053183 WL = 0x2
3863 00:25:57.056559 RL = 0x2
3864 00:25:57.056657 BL = 0x2
3865 00:25:57.059488 RPST = 0x0
3866 00:25:57.059578 RD_PRE = 0x0
3867 00:25:57.063019 WR_PRE = 0x1
3868 00:25:57.063115 WR_PST = 0x0
3869 00:25:57.066573 DBI_WR = 0x0
3870 00:25:57.066640 DBI_RD = 0x0
3871 00:25:57.069422 OTF = 0x1
3872 00:25:57.072768 ===================================
3873 00:25:57.076360 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3874 00:25:57.079363 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3875 00:25:57.085867 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3876 00:25:57.089721 ===================================
3877 00:25:57.089798 LPDDR4 DRAM CONFIGURATION
3878 00:25:57.092436 ===================================
3879 00:25:57.095952 EX_ROW_EN[0] = 0x10
3880 00:25:57.099435 EX_ROW_EN[1] = 0x0
3881 00:25:57.099513 LP4Y_EN = 0x0
3882 00:25:57.102748 WORK_FSP = 0x0
3883 00:25:57.102825 WL = 0x2
3884 00:25:57.105984 RL = 0x2
3885 00:25:57.106089 BL = 0x2
3886 00:25:57.109599 RPST = 0x0
3887 00:25:57.109674 RD_PRE = 0x0
3888 00:25:57.112479 WR_PRE = 0x1
3889 00:25:57.112556 WR_PST = 0x0
3890 00:25:57.115891 DBI_WR = 0x0
3891 00:25:57.115967 DBI_RD = 0x0
3892 00:25:57.119529 OTF = 0x1
3893 00:25:57.122926 ===================================
3894 00:25:57.129039 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3895 00:25:57.132471 nWR fixed to 30
3896 00:25:57.132575 [ModeRegInit_LP4] CH0 RK0
3897 00:25:57.136093 [ModeRegInit_LP4] CH0 RK1
3898 00:25:57.139127 [ModeRegInit_LP4] CH1 RK0
3899 00:25:57.142689 [ModeRegInit_LP4] CH1 RK1
3900 00:25:57.142771 match AC timing 17
3901 00:25:57.146208 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3902 00:25:57.152456 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3903 00:25:57.155989 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3904 00:25:57.162386 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3905 00:25:57.165847 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3906 00:25:57.165950 ==
3907 00:25:57.168815 Dram Type= 6, Freq= 0, CH_0, rank 0
3908 00:25:57.172346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3909 00:25:57.172424 ==
3910 00:25:57.179070 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3911 00:25:57.185582 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3912 00:25:57.189161 [CA 0] Center 37 (7~67) winsize 61
3913 00:25:57.191997 [CA 1] Center 36 (6~67) winsize 62
3914 00:25:57.195331 [CA 2] Center 35 (5~65) winsize 61
3915 00:25:57.198604 [CA 3] Center 35 (5~65) winsize 61
3916 00:25:57.202132 [CA 4] Center 34 (4~65) winsize 62
3917 00:25:57.205234 [CA 5] Center 34 (4~64) winsize 61
3918 00:25:57.205315
3919 00:25:57.208808 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3920 00:25:57.208916
3921 00:25:57.211871 [CATrainingPosCal] consider 1 rank data
3922 00:25:57.215402 u2DelayCellTimex100 = 270/100 ps
3923 00:25:57.218903 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3924 00:25:57.222315 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3925 00:25:57.225776 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3926 00:25:57.228496 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3927 00:25:57.231940 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3928 00:25:57.235450 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3929 00:25:57.235567
3930 00:25:57.241798 CA PerBit enable=1, Macro0, CA PI delay=34
3931 00:25:57.241900
3932 00:25:57.241995 [CBTSetCACLKResult] CA Dly = 34
3933 00:25:57.245280 CS Dly: 4 (0~35)
3934 00:25:57.245358 ==
3935 00:25:57.248797 Dram Type= 6, Freq= 0, CH_0, rank 1
3936 00:25:57.251706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3937 00:25:57.251786 ==
3938 00:25:57.258441 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3939 00:25:57.265153 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3940 00:25:57.268491 [CA 0] Center 37 (7~67) winsize 61
3941 00:25:57.271902 [CA 1] Center 37 (7~67) winsize 61
3942 00:25:57.274886 [CA 2] Center 35 (5~65) winsize 61
3943 00:25:57.278474 [CA 3] Center 35 (5~65) winsize 61
3944 00:25:57.281781 [CA 4] Center 34 (3~65) winsize 63
3945 00:25:57.284666 [CA 5] Center 34 (3~65) winsize 63
3946 00:25:57.284739
3947 00:25:57.288285 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3948 00:25:57.288386
3949 00:25:57.291880 [CATrainingPosCal] consider 2 rank data
3950 00:25:57.294843 u2DelayCellTimex100 = 270/100 ps
3951 00:25:57.298345 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3952 00:25:57.301532 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3953 00:25:57.304922 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3954 00:25:57.308401 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3955 00:25:57.311397 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3956 00:25:57.318021 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3957 00:25:57.318100
3958 00:25:57.321488 CA PerBit enable=1, Macro0, CA PI delay=34
3959 00:25:57.321566
3960 00:25:57.324865 [CBTSetCACLKResult] CA Dly = 34
3961 00:25:57.324944 CS Dly: 5 (0~37)
3962 00:25:57.325004
3963 00:25:57.327958 ----->DramcWriteLeveling(PI) begin...
3964 00:25:57.328037 ==
3965 00:25:57.331451 Dram Type= 6, Freq= 0, CH_0, rank 0
3966 00:25:57.337823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3967 00:25:57.337928 ==
3968 00:25:57.341361 Write leveling (Byte 0): 31 => 31
3969 00:25:57.341441 Write leveling (Byte 1): 30 => 30
3970 00:25:57.344801 DramcWriteLeveling(PI) end<-----
3971 00:25:57.344876
3972 00:25:57.344939 ==
3973 00:25:57.347638 Dram Type= 6, Freq= 0, CH_0, rank 0
3974 00:25:57.354106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3975 00:25:57.354203 ==
3976 00:25:57.357463 [Gating] SW mode calibration
3977 00:25:57.364345 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3978 00:25:57.367484 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3979 00:25:57.374059 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3980 00:25:57.377735 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3981 00:25:57.380855 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3982 00:25:57.387708 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
3983 00:25:57.390635 0 9 16 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
3984 00:25:57.394110 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 00:25:57.400686 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 00:25:57.404150 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 00:25:57.407523 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 00:25:57.413808 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 00:25:57.417394 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 00:25:57.420366 0 10 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
3991 00:25:57.427293 0 10 16 | B1->B0 | 2b2b 3b3b | 0 0 | (0 0) (0 0)
3992 00:25:57.430241 0 10 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3993 00:25:57.433854 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 00:25:57.440415 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 00:25:57.443413 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 00:25:57.446919 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 00:25:57.453307 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 00:25:57.456881 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 00:25:57.460126 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4000 00:25:57.466774 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 00:25:57.470144 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 00:25:57.473637 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 00:25:57.480090 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 00:25:57.483122 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 00:25:57.486395 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 00:25:57.492965 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 00:25:57.496580 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 00:25:57.499733 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 00:25:57.506264 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 00:25:57.509739 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 00:25:57.513329 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 00:25:57.519378 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 00:25:57.522859 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 00:25:57.526340 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 00:25:57.532861 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4016 00:25:57.532987 Total UI for P1: 0, mck2ui 16
4017 00:25:57.535829 best dqsien dly found for B0: ( 0, 13, 14)
4018 00:25:57.542887 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 00:25:57.545908 Total UI for P1: 0, mck2ui 16
4020 00:25:57.549377 best dqsien dly found for B1: ( 0, 13, 18)
4021 00:25:57.552284 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4022 00:25:57.555779 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4023 00:25:57.555881
4024 00:25:57.559388 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4025 00:25:57.562309 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4026 00:25:57.565863 [Gating] SW calibration Done
4027 00:25:57.565981 ==
4028 00:25:57.569295 Dram Type= 6, Freq= 0, CH_0, rank 0
4029 00:25:57.572559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4030 00:25:57.576059 ==
4031 00:25:57.576138 RX Vref Scan: 0
4032 00:25:57.576210
4033 00:25:57.578953 RX Vref 0 -> 0, step: 1
4034 00:25:57.579032
4035 00:25:57.582475 RX Delay -230 -> 252, step: 16
4036 00:25:57.585441 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4037 00:25:57.588918 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4038 00:25:57.592156 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4039 00:25:57.598815 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4040 00:25:57.602386 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4041 00:25:57.605238 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4042 00:25:57.608568 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4043 00:25:57.612239 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4044 00:25:57.618615 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4045 00:25:57.622105 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4046 00:25:57.625346 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4047 00:25:57.628443 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4048 00:25:57.635315 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4049 00:25:57.638936 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4050 00:25:57.641970 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4051 00:25:57.645312 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4052 00:25:57.645387 ==
4053 00:25:57.648806 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 00:25:57.655318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 00:25:57.655394 ==
4056 00:25:57.655454 DQS Delay:
4057 00:25:57.658123 DQS0 = 0, DQS1 = 0
4058 00:25:57.658205 DQM Delay:
4059 00:25:57.661858 DQM0 = 38, DQM1 = 29
4060 00:25:57.661928 DQ Delay:
4061 00:25:57.664776 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4062 00:25:57.668446 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4063 00:25:57.671358 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4064 00:25:57.674797 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4065 00:25:57.674896
4066 00:25:57.674986
4067 00:25:57.675046 ==
4068 00:25:57.678203 Dram Type= 6, Freq= 0, CH_0, rank 0
4069 00:25:57.681309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4070 00:25:57.681380 ==
4071 00:25:57.681439
4072 00:25:57.681493
4073 00:25:57.684564 TX Vref Scan disable
4074 00:25:57.688326 == TX Byte 0 ==
4075 00:25:57.691339 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4076 00:25:57.694922 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4077 00:25:57.697874 == TX Byte 1 ==
4078 00:25:57.701332 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4079 00:25:57.704326 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4080 00:25:57.704404 ==
4081 00:25:57.707826 Dram Type= 6, Freq= 0, CH_0, rank 0
4082 00:25:57.714450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4083 00:25:57.714581 ==
4084 00:25:57.714688
4085 00:25:57.714791
4086 00:25:57.714885 TX Vref Scan disable
4087 00:25:57.718708 == TX Byte 0 ==
4088 00:25:57.721871 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4089 00:25:57.728640 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4090 00:25:57.728761 == TX Byte 1 ==
4091 00:25:57.731788 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4092 00:25:57.738456 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4093 00:25:57.738573
4094 00:25:57.738679 [DATLAT]
4095 00:25:57.738777 Freq=600, CH0 RK0
4096 00:25:57.738879
4097 00:25:57.741564 DATLAT Default: 0x9
4098 00:25:57.741685 0, 0xFFFF, sum = 0
4099 00:25:57.745026 1, 0xFFFF, sum = 0
4100 00:25:57.748556 2, 0xFFFF, sum = 0
4101 00:25:57.748667 3, 0xFFFF, sum = 0
4102 00:25:57.751631 4, 0xFFFF, sum = 0
4103 00:25:57.751711 5, 0xFFFF, sum = 0
4104 00:25:57.755037 6, 0xFFFF, sum = 0
4105 00:25:57.755155 7, 0xFFFF, sum = 0
4106 00:25:57.758610 8, 0x0, sum = 1
4107 00:25:57.758726 9, 0x0, sum = 2
4108 00:25:57.758832 10, 0x0, sum = 3
4109 00:25:57.761517 11, 0x0, sum = 4
4110 00:25:57.761619 best_step = 9
4111 00:25:57.761713
4112 00:25:57.761798 ==
4113 00:25:57.765012 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 00:25:57.771413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 00:25:57.771516 ==
4116 00:25:57.771611 RX Vref Scan: 1
4117 00:25:57.771697
4118 00:25:57.774948 RX Vref 0 -> 0, step: 1
4119 00:25:57.775051
4120 00:25:57.778607 RX Delay -195 -> 252, step: 8
4121 00:25:57.778687
4122 00:25:57.781519 Set Vref, RX VrefLevel [Byte0]: 62
4123 00:25:57.784984 [Byte1]: 49
4124 00:25:57.785088
4125 00:25:57.787837 Final RX Vref Byte 0 = 62 to rank0
4126 00:25:57.791693 Final RX Vref Byte 1 = 49 to rank0
4127 00:25:57.794679 Final RX Vref Byte 0 = 62 to rank1
4128 00:25:57.798327 Final RX Vref Byte 1 = 49 to rank1==
4129 00:25:57.801147 Dram Type= 6, Freq= 0, CH_0, rank 0
4130 00:25:57.804800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 00:25:57.804916 ==
4132 00:25:57.808331 DQS Delay:
4133 00:25:57.808446 DQS0 = 0, DQS1 = 0
4134 00:25:57.811201 DQM Delay:
4135 00:25:57.811309 DQM0 = 35, DQM1 = 28
4136 00:25:57.811408 DQ Delay:
4137 00:25:57.814711 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =28
4138 00:25:57.817711 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =48
4139 00:25:57.821104 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4140 00:25:57.824728 DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36
4141 00:25:57.824841
4142 00:25:57.824945
4143 00:25:57.834674 [DQSOSCAuto] RK0, (LSB)MR18= 0x4140, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4144 00:25:57.837895 CH0 RK0: MR19=808, MR18=4140
4145 00:25:57.844309 CH0_RK0: MR19=0x808, MR18=0x4140, DQSOSC=397, MR23=63, INC=166, DEC=110
4146 00:25:57.844415
4147 00:25:57.847689 ----->DramcWriteLeveling(PI) begin...
4148 00:25:57.847763 ==
4149 00:25:57.851233 Dram Type= 6, Freq= 0, CH_0, rank 1
4150 00:25:57.854270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 00:25:57.854375 ==
4152 00:25:57.857502 Write leveling (Byte 0): 33 => 33
4153 00:25:57.861014 Write leveling (Byte 1): 32 => 32
4154 00:25:57.863966 DramcWriteLeveling(PI) end<-----
4155 00:25:57.864069
4156 00:25:57.864162 ==
4157 00:25:57.867468 Dram Type= 6, Freq= 0, CH_0, rank 1
4158 00:25:57.870925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 00:25:57.871026 ==
4160 00:25:57.873928 [Gating] SW mode calibration
4161 00:25:57.880560 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4162 00:25:57.887702 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4163 00:25:57.890716 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4164 00:25:57.894219 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4165 00:25:57.900947 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4166 00:25:57.903927 0 9 12 | B1->B0 | 3333 3131 | 1 0 | (1 1) (0 1)
4167 00:25:57.907582 0 9 16 | B1->B0 | 2c2c 2323 | 1 0 | (1 1) (0 0)
4168 00:25:57.914064 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 00:25:57.917379 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 00:25:57.920833 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 00:25:57.927293 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 00:25:57.930845 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 00:25:57.934214 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 00:25:57.940599 0 10 12 | B1->B0 | 2d2d 3232 | 0 0 | (0 0) (0 0)
4175 00:25:57.944178 0 10 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4176 00:25:57.947103 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 00:25:57.953960 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 00:25:57.957185 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 00:25:57.960069 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 00:25:57.966806 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 00:25:57.970247 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 00:25:57.973622 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 00:25:57.980095 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4184 00:25:57.983594 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 00:25:57.987061 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 00:25:57.993662 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 00:25:57.996589 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 00:25:58.000290 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 00:25:58.006671 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 00:25:58.009968 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 00:25:58.013573 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 00:25:58.019901 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 00:25:58.023269 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 00:25:58.026748 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 00:25:58.033450 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 00:25:58.036419 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 00:25:58.039664 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 00:25:58.046592 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4199 00:25:58.049596 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4200 00:25:58.053128 Total UI for P1: 0, mck2ui 16
4201 00:25:58.056665 best dqsien dly found for B0: ( 0, 13, 12)
4202 00:25:58.059735 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 00:25:58.063092 Total UI for P1: 0, mck2ui 16
4204 00:25:58.066493 best dqsien dly found for B1: ( 0, 13, 16)
4205 00:25:58.069930 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4206 00:25:58.072877 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4207 00:25:58.072990
4208 00:25:58.076406 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4209 00:25:58.083089 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4210 00:25:58.083173 [Gating] SW calibration Done
4211 00:25:58.083234 ==
4212 00:25:58.086234 Dram Type= 6, Freq= 0, CH_0, rank 1
4213 00:25:58.093170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4214 00:25:58.093248 ==
4215 00:25:58.093308 RX Vref Scan: 0
4216 00:25:58.093365
4217 00:25:58.096537 RX Vref 0 -> 0, step: 1
4218 00:25:58.096613
4219 00:25:58.099708 RX Delay -230 -> 252, step: 16
4220 00:25:58.102629 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4221 00:25:58.106136 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4222 00:25:58.112465 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4223 00:25:58.115814 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4224 00:25:58.119353 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4225 00:25:58.122774 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4226 00:25:58.125762 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4227 00:25:58.132592 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4228 00:25:58.135697 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4229 00:25:58.139118 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4230 00:25:58.142601 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4231 00:25:58.149051 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4232 00:25:58.152602 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4233 00:25:58.155667 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4234 00:25:58.159303 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4235 00:25:58.165704 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4236 00:25:58.165788 ==
4237 00:25:58.168653 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 00:25:58.172248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 00:25:58.172328 ==
4240 00:25:58.172389 DQS Delay:
4241 00:25:58.175571 DQS0 = 0, DQS1 = 0
4242 00:25:58.175650 DQM Delay:
4243 00:25:58.178612 DQM0 = 36, DQM1 = 29
4244 00:25:58.178690 DQ Delay:
4245 00:25:58.182170 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4246 00:25:58.185165 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4247 00:25:58.188675 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4248 00:25:58.192201 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4249 00:25:58.192279
4250 00:25:58.192339
4251 00:25:58.192395 ==
4252 00:25:58.195650 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 00:25:58.198462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 00:25:58.198541 ==
4255 00:25:58.198601
4256 00:25:58.201838
4257 00:25:58.201917 TX Vref Scan disable
4258 00:25:58.205264 == TX Byte 0 ==
4259 00:25:58.208774 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4260 00:25:58.211891 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4261 00:25:58.215569 == TX Byte 1 ==
4262 00:25:58.218583 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4263 00:25:58.221785 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4264 00:25:58.221901 ==
4265 00:25:58.225486 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 00:25:58.231614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 00:25:58.231733 ==
4268 00:25:58.231839
4269 00:25:58.231940
4270 00:25:58.232031 TX Vref Scan disable
4271 00:25:58.236162 == TX Byte 0 ==
4272 00:25:58.239683 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4273 00:25:58.243275 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4274 00:25:58.246219 == TX Byte 1 ==
4275 00:25:58.249540 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4276 00:25:58.256628 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4277 00:25:58.256749
4278 00:25:58.256853 [DATLAT]
4279 00:25:58.256956 Freq=600, CH0 RK1
4280 00:25:58.257056
4281 00:25:58.259650 DATLAT Default: 0x9
4282 00:25:58.259758 0, 0xFFFF, sum = 0
4283 00:25:58.263168 1, 0xFFFF, sum = 0
4284 00:25:58.263283 2, 0xFFFF, sum = 0
4285 00:25:58.266179 3, 0xFFFF, sum = 0
4286 00:25:58.269632 4, 0xFFFF, sum = 0
4287 00:25:58.269744 5, 0xFFFF, sum = 0
4288 00:25:58.272589 6, 0xFFFF, sum = 0
4289 00:25:58.272714 7, 0xFFFF, sum = 0
4290 00:25:58.276140 8, 0x0, sum = 1
4291 00:25:58.276253 9, 0x0, sum = 2
4292 00:25:58.276357 10, 0x0, sum = 3
4293 00:25:58.279423 11, 0x0, sum = 4
4294 00:25:58.279534 best_step = 9
4295 00:25:58.279634
4296 00:25:58.279732 ==
4297 00:25:58.282965 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 00:25:58.289519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 00:25:58.289632 ==
4300 00:25:58.289735 RX Vref Scan: 0
4301 00:25:58.289839
4302 00:25:58.293004 RX Vref 0 -> 0, step: 1
4303 00:25:58.293113
4304 00:25:58.295876 RX Delay -195 -> 252, step: 8
4305 00:25:58.299484 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4306 00:25:58.305884 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4307 00:25:58.309508 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4308 00:25:58.312295 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4309 00:25:58.315609 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4310 00:25:58.322427 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4311 00:25:58.325615 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4312 00:25:58.328873 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4313 00:25:58.332239 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4314 00:25:58.335882 iDelay=205, Bit 9, Center 8 (-147 ~ 164) 312
4315 00:25:58.342524 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4316 00:25:58.345480 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4317 00:25:58.348913 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4318 00:25:58.352424 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4319 00:25:58.359179 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4320 00:25:58.362134 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4321 00:25:58.362236 ==
4322 00:25:58.365701 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 00:25:58.369102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 00:25:58.369198 ==
4325 00:25:58.372076 DQS Delay:
4326 00:25:58.372168 DQS0 = 0, DQS1 = 0
4327 00:25:58.372263 DQM Delay:
4328 00:25:58.375700 DQM0 = 33, DQM1 = 27
4329 00:25:58.375795 DQ Delay:
4330 00:25:58.378662 DQ0 =28, DQ1 =36, DQ2 =32, DQ3 =28
4331 00:25:58.382110 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4332 00:25:58.385368 DQ8 =20, DQ9 =8, DQ10 =28, DQ11 =20
4333 00:25:58.388923 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4334 00:25:58.389016
4335 00:25:58.389101
4336 00:25:58.398970 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d3c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4337 00:25:58.402408 CH0 RK1: MR19=808, MR18=6D3C
4338 00:25:58.405380 CH0_RK1: MR19=0x808, MR18=0x6D3C, DQSOSC=389, MR23=63, INC=173, DEC=115
4339 00:25:58.408898 [RxdqsGatingPostProcess] freq 600
4340 00:25:58.415509 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4341 00:25:58.418984 Pre-setting of DQS Precalculation
4342 00:25:58.421873 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4343 00:25:58.421976 ==
4344 00:25:58.425373 Dram Type= 6, Freq= 0, CH_1, rank 0
4345 00:25:58.431908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 00:25:58.431988 ==
4347 00:25:58.435391 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4348 00:25:58.441706 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4349 00:25:58.445267 [CA 0] Center 35 (5~66) winsize 62
4350 00:25:58.448576 [CA 1] Center 35 (5~66) winsize 62
4351 00:25:58.451703 [CA 2] Center 34 (4~65) winsize 62
4352 00:25:58.454920 [CA 3] Center 34 (4~65) winsize 62
4353 00:25:58.458720 [CA 4] Center 34 (4~65) winsize 62
4354 00:25:58.461726 [CA 5] Center 34 (4~64) winsize 61
4355 00:25:58.461792
4356 00:25:58.465240 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4357 00:25:58.465306
4358 00:25:58.468270 [CATrainingPosCal] consider 1 rank data
4359 00:25:58.471646 u2DelayCellTimex100 = 270/100 ps
4360 00:25:58.475346 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4361 00:25:58.478273 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4362 00:25:58.484874 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4363 00:25:58.488401 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4364 00:25:58.491708 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4365 00:25:58.495221 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4366 00:25:58.495317
4367 00:25:58.498201 CA PerBit enable=1, Macro0, CA PI delay=34
4368 00:25:58.498270
4369 00:25:58.501736 [CBTSetCACLKResult] CA Dly = 34
4370 00:25:58.501802 CS Dly: 5 (0~36)
4371 00:25:58.504672 ==
4372 00:25:58.504740 Dram Type= 6, Freq= 0, CH_1, rank 1
4373 00:25:58.511612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 00:25:58.511681 ==
4375 00:25:58.514555 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4376 00:25:58.521133 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4377 00:25:58.525000 [CA 0] Center 36 (6~66) winsize 61
4378 00:25:58.528556 [CA 1] Center 36 (6~66) winsize 61
4379 00:25:58.531473 [CA 2] Center 34 (4~65) winsize 62
4380 00:25:58.535118 [CA 3] Center 34 (3~65) winsize 63
4381 00:25:58.538394 [CA 4] Center 34 (4~65) winsize 62
4382 00:25:58.541721 [CA 5] Center 33 (3~64) winsize 62
4383 00:25:58.541790
4384 00:25:58.545089 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4385 00:25:58.545160
4386 00:25:58.548577 [CATrainingPosCal] consider 2 rank data
4387 00:25:58.551620 u2DelayCellTimex100 = 270/100 ps
4388 00:25:58.555225 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4389 00:25:58.561639 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4390 00:25:58.565087 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4391 00:25:58.568036 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4392 00:25:58.571322 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4393 00:25:58.574828 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4394 00:25:58.574941
4395 00:25:58.578189 CA PerBit enable=1, Macro0, CA PI delay=34
4396 00:25:58.578287
4397 00:25:58.581625 [CBTSetCACLKResult] CA Dly = 34
4398 00:25:58.581697 CS Dly: 5 (0~36)
4399 00:25:58.584748
4400 00:25:58.588133 ----->DramcWriteLeveling(PI) begin...
4401 00:25:58.588225 ==
4402 00:25:58.591684 Dram Type= 6, Freq= 0, CH_1, rank 0
4403 00:25:58.594689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 00:25:58.594783 ==
4405 00:25:58.597851 Write leveling (Byte 0): 28 => 28
4406 00:25:58.601363 Write leveling (Byte 1): 32 => 32
4407 00:25:58.604993 DramcWriteLeveling(PI) end<-----
4408 00:25:58.605086
4409 00:25:58.605170 ==
4410 00:25:58.608562 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 00:25:58.611462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 00:25:58.611555 ==
4413 00:25:58.614833 [Gating] SW mode calibration
4414 00:25:58.621324 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4415 00:25:58.627732 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4416 00:25:58.631322 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4417 00:25:58.634899 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4418 00:25:58.641285 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4419 00:25:58.644892 0 9 12 | B1->B0 | 3030 3030 | 1 1 | (1 1) (1 1)
4420 00:25:58.648110 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4421 00:25:58.654365 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 00:25:58.657965 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 00:25:58.660975 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 00:25:58.667902 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 00:25:58.671362 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 00:25:58.674264 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 00:25:58.677877 0 10 12 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 0)
4428 00:25:58.684100 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4429 00:25:58.687765 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 00:25:58.690889 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 00:25:58.697472 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 00:25:58.700741 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 00:25:58.704161 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 00:25:58.710430 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 00:25:58.713881 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4436 00:25:58.717228 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 00:25:58.723690 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 00:25:58.727140 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 00:25:58.730635 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 00:25:58.736984 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 00:25:58.740612 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 00:25:58.743598 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 00:25:58.750584 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 00:25:58.753478 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 00:25:58.756799 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 00:25:58.763680 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 00:25:58.767232 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 00:25:58.770231 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 00:25:58.776590 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 00:25:58.780255 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 00:25:58.783198 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4452 00:25:58.789686 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4453 00:25:58.793277 Total UI for P1: 0, mck2ui 16
4454 00:25:58.796623 best dqsien dly found for B0: ( 0, 13, 12)
4455 00:25:58.799977 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 00:25:58.803104 Total UI for P1: 0, mck2ui 16
4457 00:25:58.806146 best dqsien dly found for B1: ( 0, 13, 14)
4458 00:25:58.809897 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4459 00:25:58.813100 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4460 00:25:58.813170
4461 00:25:58.816298 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4462 00:25:58.823410 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4463 00:25:58.823510 [Gating] SW calibration Done
4464 00:25:58.823606 ==
4465 00:25:58.826100 Dram Type= 6, Freq= 0, CH_1, rank 0
4466 00:25:58.833113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4467 00:25:58.833191 ==
4468 00:25:58.833251 RX Vref Scan: 0
4469 00:25:58.833307
4470 00:25:58.836475 RX Vref 0 -> 0, step: 1
4471 00:25:58.836560
4472 00:25:58.839424 RX Delay -230 -> 252, step: 16
4473 00:25:58.842993 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4474 00:25:58.846687 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4475 00:25:58.849615 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4476 00:25:58.856471 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4477 00:25:58.859413 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4478 00:25:58.862823 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4479 00:25:58.866052 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4480 00:25:58.872900 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4481 00:25:58.876189 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4482 00:25:58.879345 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4483 00:25:58.882868 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4484 00:25:58.886405 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4485 00:25:58.892964 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4486 00:25:58.895922 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4487 00:25:58.899534 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4488 00:25:58.905868 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4489 00:25:58.905969 ==
4490 00:25:58.909245 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 00:25:58.912459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 00:25:58.912578 ==
4493 00:25:58.912688 DQS Delay:
4494 00:25:58.915660 DQS0 = 0, DQS1 = 0
4495 00:25:58.915769 DQM Delay:
4496 00:25:58.919032 DQM0 = 39, DQM1 = 29
4497 00:25:58.919145 DQ Delay:
4498 00:25:58.922596 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4499 00:25:58.925696 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4500 00:25:58.928883 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4501 00:25:58.932425 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4502 00:25:58.932532
4503 00:25:58.932640
4504 00:25:58.932746 ==
4505 00:25:58.935550 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 00:25:58.938759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 00:25:58.938870 ==
4508 00:25:58.938979
4509 00:25:58.942002
4510 00:25:58.942114 TX Vref Scan disable
4511 00:25:58.945463 == TX Byte 0 ==
4512 00:25:58.948958 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4513 00:25:58.952003 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4514 00:25:58.955523 == TX Byte 1 ==
4515 00:25:58.958458 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4516 00:25:58.962079 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4517 00:25:58.962193 ==
4518 00:25:58.965571 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 00:25:58.971864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 00:25:58.971976 ==
4521 00:25:58.972074
4522 00:25:58.972174
4523 00:25:58.972274 TX Vref Scan disable
4524 00:25:58.976521 == TX Byte 0 ==
4525 00:25:58.979802 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4526 00:25:58.986374 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4527 00:25:58.986483 == TX Byte 1 ==
4528 00:25:58.989820 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4529 00:25:58.996410 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4530 00:25:58.996525
4531 00:25:58.996630 [DATLAT]
4532 00:25:58.996739 Freq=600, CH1 RK0
4533 00:25:58.996836
4534 00:25:58.999994 DATLAT Default: 0x9
4535 00:25:59.000104 0, 0xFFFF, sum = 0
4536 00:25:59.003070 1, 0xFFFF, sum = 0
4537 00:25:59.003183 2, 0xFFFF, sum = 0
4538 00:25:59.006638 3, 0xFFFF, sum = 0
4539 00:25:59.009671 4, 0xFFFF, sum = 0
4540 00:25:59.009782 5, 0xFFFF, sum = 0
4541 00:25:59.013049 6, 0xFFFF, sum = 0
4542 00:25:59.013125 7, 0xFFFF, sum = 0
4543 00:25:59.016477 8, 0x0, sum = 1
4544 00:25:59.016572 9, 0x0, sum = 2
4545 00:25:59.016666 10, 0x0, sum = 3
4546 00:25:59.019462 11, 0x0, sum = 4
4547 00:25:59.019552 best_step = 9
4548 00:25:59.019636
4549 00:25:59.019715 ==
4550 00:25:59.022745 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 00:25:59.029735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 00:25:59.029808 ==
4553 00:25:59.029866 RX Vref Scan: 1
4554 00:25:59.029920
4555 00:25:59.032743 RX Vref 0 -> 0, step: 1
4556 00:25:59.032808
4557 00:25:59.036287 RX Delay -195 -> 252, step: 8
4558 00:25:59.036388
4559 00:25:59.039307 Set Vref, RX VrefLevel [Byte0]: 60
4560 00:25:59.043058 [Byte1]: 50
4561 00:25:59.043153
4562 00:25:59.046202 Final RX Vref Byte 0 = 60 to rank0
4563 00:25:59.049651 Final RX Vref Byte 1 = 50 to rank0
4564 00:25:59.052575 Final RX Vref Byte 0 = 60 to rank1
4565 00:25:59.056379 Final RX Vref Byte 1 = 50 to rank1==
4566 00:25:59.059322 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 00:25:59.062809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 00:25:59.062906 ==
4569 00:25:59.065771 DQS Delay:
4570 00:25:59.065863 DQS0 = 0, DQS1 = 0
4571 00:25:59.069305 DQM Delay:
4572 00:25:59.069393 DQM0 = 38, DQM1 = 28
4573 00:25:59.069474 DQ Delay:
4574 00:25:59.072288 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4575 00:25:59.075854 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4576 00:25:59.079317 DQ8 =12, DQ9 =16, DQ10 =32, DQ11 =20
4577 00:25:59.082649 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4578 00:25:59.082711
4579 00:25:59.085854
4580 00:25:59.092499 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a36, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 401 ps
4581 00:25:59.095567 CH1 RK0: MR19=808, MR18=2A36
4582 00:25:59.102052 CH1_RK0: MR19=0x808, MR18=0x2A36, DQSOSC=399, MR23=63, INC=164, DEC=109
4583 00:25:59.102125
4584 00:25:59.105583 ----->DramcWriteLeveling(PI) begin...
4585 00:25:59.105651 ==
4586 00:25:59.108667 Dram Type= 6, Freq= 0, CH_1, rank 1
4587 00:25:59.112185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 00:25:59.112262 ==
4589 00:25:59.115774 Write leveling (Byte 0): 30 => 30
4590 00:25:59.118612 Write leveling (Byte 1): 29 => 29
4591 00:25:59.122200 DramcWriteLeveling(PI) end<-----
4592 00:25:59.122287
4593 00:25:59.122380 ==
4594 00:25:59.125641 Dram Type= 6, Freq= 0, CH_1, rank 1
4595 00:25:59.128454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 00:25:59.128532 ==
4597 00:25:59.132186 [Gating] SW mode calibration
4598 00:25:59.138374 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4599 00:25:59.145625 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4600 00:25:59.148569 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4601 00:25:59.151932 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4602 00:25:59.158454 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4603 00:25:59.161885 0 9 12 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 0)
4604 00:25:59.164955 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4605 00:25:59.172042 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 00:25:59.175164 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 00:25:59.179139 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 00:25:59.185076 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 00:25:59.188641 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 00:25:59.191596 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4611 00:25:59.198380 0 10 12 | B1->B0 | 2b2b 3b3b | 0 0 | (0 0) (0 0)
4612 00:25:59.201574 0 10 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4613 00:25:59.204769 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 00:25:59.211611 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 00:25:59.215121 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 00:25:59.218113 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 00:25:59.225010 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 00:25:59.228087 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 00:25:59.231530 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4620 00:25:59.237917 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 00:25:59.241324 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 00:25:59.245013 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 00:25:59.251532 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 00:25:59.254429 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 00:25:59.258432 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 00:25:59.264986 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 00:25:59.267975 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 00:25:59.271563 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 00:25:59.277716 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 00:25:59.281393 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 00:25:59.284524 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 00:25:59.291343 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 00:25:59.294262 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 00:25:59.297849 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 00:25:59.301392 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4636 00:25:59.307839 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 00:25:59.311381 Total UI for P1: 0, mck2ui 16
4638 00:25:59.314605 best dqsien dly found for B0: ( 0, 13, 12)
4639 00:25:59.317900 Total UI for P1: 0, mck2ui 16
4640 00:25:59.320987 best dqsien dly found for B1: ( 0, 13, 12)
4641 00:25:59.324564 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4642 00:25:59.327479 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4643 00:25:59.327576
4644 00:25:59.331002 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4645 00:25:59.334583 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4646 00:25:59.337645 [Gating] SW calibration Done
4647 00:25:59.337737 ==
4648 00:25:59.341225 Dram Type= 6, Freq= 0, CH_1, rank 1
4649 00:25:59.344130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 00:25:59.344222 ==
4651 00:25:59.347666 RX Vref Scan: 0
4652 00:25:59.347766
4653 00:25:59.350583 RX Vref 0 -> 0, step: 1
4654 00:25:59.350715
4655 00:25:59.350820 RX Delay -230 -> 252, step: 16
4656 00:25:59.357716 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4657 00:25:59.360599 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4658 00:25:59.364078 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4659 00:25:59.367676 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4660 00:25:59.374338 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4661 00:25:59.377359 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4662 00:25:59.380858 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4663 00:25:59.383884 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4664 00:25:59.390563 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4665 00:25:59.393893 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4666 00:25:59.397102 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4667 00:25:59.400579 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4668 00:25:59.406974 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4669 00:25:59.410408 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4670 00:25:59.413951 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4671 00:25:59.416986 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4672 00:25:59.417101 ==
4673 00:25:59.420535 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 00:25:59.426802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 00:25:59.426916 ==
4676 00:25:59.427019 DQS Delay:
4677 00:25:59.427122 DQS0 = 0, DQS1 = 0
4678 00:25:59.430050 DQM Delay:
4679 00:25:59.430161 DQM0 = 36, DQM1 = 30
4680 00:25:59.433442 DQ Delay:
4681 00:25:59.437043 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4682 00:25:59.440001 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4683 00:25:59.443573 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4684 00:25:59.446555 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4685 00:25:59.446667
4686 00:25:59.446772
4687 00:25:59.446874 ==
4688 00:25:59.450244 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 00:25:59.453321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 00:25:59.453435 ==
4691 00:25:59.453535
4692 00:25:59.453636
4693 00:25:59.456872 TX Vref Scan disable
4694 00:25:59.456985 == TX Byte 0 ==
4695 00:25:59.463374 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4696 00:25:59.466387 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4697 00:25:59.469633 == TX Byte 1 ==
4698 00:25:59.473173 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4699 00:25:59.476712 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4700 00:25:59.476792 ==
4701 00:25:59.479619 Dram Type= 6, Freq= 0, CH_1, rank 1
4702 00:25:59.483331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4703 00:25:59.483427 ==
4704 00:25:59.486350
4705 00:25:59.486438
4706 00:25:59.486520 TX Vref Scan disable
4707 00:25:59.490264 == TX Byte 0 ==
4708 00:25:59.493167 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4709 00:25:59.499956 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4710 00:25:59.500089 == TX Byte 1 ==
4711 00:25:59.503703 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4712 00:25:59.509636 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4713 00:25:59.509750
4714 00:25:59.509841 [DATLAT]
4715 00:25:59.509925 Freq=600, CH1 RK1
4716 00:25:59.510008
4717 00:25:59.513108 DATLAT Default: 0x9
4718 00:25:59.516159 0, 0xFFFF, sum = 0
4719 00:25:59.516258 1, 0xFFFF, sum = 0
4720 00:25:59.519834 2, 0xFFFF, sum = 0
4721 00:25:59.519934 3, 0xFFFF, sum = 0
4722 00:25:59.522873 4, 0xFFFF, sum = 0
4723 00:25:59.522979 5, 0xFFFF, sum = 0
4724 00:25:59.526299 6, 0xFFFF, sum = 0
4725 00:25:59.526413 7, 0xFFFF, sum = 0
4726 00:25:59.529843 8, 0x0, sum = 1
4727 00:25:59.529991 9, 0x0, sum = 2
4728 00:25:59.530082 10, 0x0, sum = 3
4729 00:25:59.533331 11, 0x0, sum = 4
4730 00:25:59.533471 best_step = 9
4731 00:25:59.533570
4732 00:25:59.536266 ==
4733 00:25:59.536361 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 00:25:59.542956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 00:25:59.543087 ==
4736 00:25:59.543190 RX Vref Scan: 0
4737 00:25:59.543277
4738 00:25:59.546096 RX Vref 0 -> 0, step: 1
4739 00:25:59.546192
4740 00:25:59.549564 RX Delay -195 -> 252, step: 8
4741 00:25:59.556463 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4742 00:25:59.559444 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4743 00:25:59.563008 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4744 00:25:59.566023 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4745 00:25:59.569510 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4746 00:25:59.576002 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4747 00:25:59.579330 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4748 00:25:59.582554 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4749 00:25:59.586074 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4750 00:25:59.592451 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4751 00:25:59.595853 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4752 00:25:59.599371 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4753 00:25:59.602373 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4754 00:25:59.609308 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4755 00:25:59.612623 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4756 00:25:59.616047 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4757 00:25:59.616145 ==
4758 00:25:59.619133 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 00:25:59.622485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 00:25:59.622558 ==
4761 00:25:59.626020 DQS Delay:
4762 00:25:59.626132 DQS0 = 0, DQS1 = 0
4763 00:25:59.628962 DQM Delay:
4764 00:25:59.629072 DQM0 = 36, DQM1 = 30
4765 00:25:59.629176 DQ Delay:
4766 00:25:59.632557 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4767 00:25:59.635494 DQ4 =32, DQ5 =44, DQ6 =48, DQ7 =36
4768 00:25:59.638995 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20
4769 00:25:59.641970 DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =36
4770 00:25:59.642079
4771 00:25:59.642180
4772 00:25:59.652087 [DQSOSCAuto] RK1, (LSB)MR18= 0x3656, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4773 00:25:59.655441 CH1 RK1: MR19=808, MR18=3656
4774 00:25:59.662046 CH1_RK1: MR19=0x808, MR18=0x3656, DQSOSC=393, MR23=63, INC=169, DEC=113
4775 00:25:59.662163 [RxdqsGatingPostProcess] freq 600
4776 00:25:59.668484 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4777 00:25:59.671837 Pre-setting of DQS Precalculation
4778 00:25:59.675435 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4779 00:25:59.685431 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4780 00:25:59.691774 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4781 00:25:59.691872
4782 00:25:59.691960
4783 00:25:59.695418 [Calibration Summary] 1200 Mbps
4784 00:25:59.695485 CH 0, Rank 0
4785 00:25:59.698839 SW Impedance : PASS
4786 00:25:59.698917 DUTY Scan : NO K
4787 00:25:59.701844 ZQ Calibration : PASS
4788 00:25:59.705345 Jitter Meter : NO K
4789 00:25:59.705416 CBT Training : PASS
4790 00:25:59.708327 Write leveling : PASS
4791 00:25:59.711902 RX DQS gating : PASS
4792 00:25:59.711998 RX DQ/DQS(RDDQC) : PASS
4793 00:25:59.714955 TX DQ/DQS : PASS
4794 00:25:59.718383 RX DATLAT : PASS
4795 00:25:59.718454 RX DQ/DQS(Engine): PASS
4796 00:25:59.721328 TX OE : NO K
4797 00:25:59.721407 All Pass.
4798 00:25:59.721467
4799 00:25:59.724671 CH 0, Rank 1
4800 00:25:59.724749 SW Impedance : PASS
4801 00:25:59.728426 DUTY Scan : NO K
4802 00:25:59.731634 ZQ Calibration : PASS
4803 00:25:59.731726 Jitter Meter : NO K
4804 00:25:59.735006 CBT Training : PASS
4805 00:25:59.738030 Write leveling : PASS
4806 00:25:59.738120 RX DQS gating : PASS
4807 00:25:59.741612 RX DQ/DQS(RDDQC) : PASS
4808 00:25:59.744552 TX DQ/DQS : PASS
4809 00:25:59.744651 RX DATLAT : PASS
4810 00:25:59.748278 RX DQ/DQS(Engine): PASS
4811 00:25:59.751360 TX OE : NO K
4812 00:25:59.751451 All Pass.
4813 00:25:59.751533
4814 00:25:59.751621 CH 1, Rank 0
4815 00:25:59.754851 SW Impedance : PASS
4816 00:25:59.757746 DUTY Scan : NO K
4817 00:25:59.757822 ZQ Calibration : PASS
4818 00:25:59.761286 Jitter Meter : NO K
4819 00:25:59.764288 CBT Training : PASS
4820 00:25:59.764384 Write leveling : PASS
4821 00:25:59.767796 RX DQS gating : PASS
4822 00:25:59.767862 RX DQ/DQS(RDDQC) : PASS
4823 00:25:59.771165 TX DQ/DQS : PASS
4824 00:25:59.774411 RX DATLAT : PASS
4825 00:25:59.774501 RX DQ/DQS(Engine): PASS
4826 00:25:59.777863 TX OE : NO K
4827 00:25:59.777989 All Pass.
4828 00:25:59.778093
4829 00:25:59.781001 CH 1, Rank 1
4830 00:25:59.781116 SW Impedance : PASS
4831 00:25:59.784152 DUTY Scan : NO K
4832 00:25:59.787653 ZQ Calibration : PASS
4833 00:25:59.787755 Jitter Meter : NO K
4834 00:25:59.791029 CBT Training : PASS
4835 00:25:59.794461 Write leveling : PASS
4836 00:25:59.794575 RX DQS gating : PASS
4837 00:25:59.797315 RX DQ/DQS(RDDQC) : PASS
4838 00:25:59.800554 TX DQ/DQS : PASS
4839 00:25:59.800670 RX DATLAT : PASS
4840 00:25:59.803932 RX DQ/DQS(Engine): PASS
4841 00:25:59.807481 TX OE : NO K
4842 00:25:59.807593 All Pass.
4843 00:25:59.807691
4844 00:25:59.810395 DramC Write-DBI off
4845 00:25:59.810503 PER_BANK_REFRESH: Hybrid Mode
4846 00:25:59.814068 TX_TRACKING: ON
4847 00:25:59.820492 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4848 00:25:59.827494 [FAST_K] Save calibration result to emmc
4849 00:25:59.830495 dramc_set_vcore_voltage set vcore to 662500
4850 00:25:59.830607 Read voltage for 933, 3
4851 00:25:59.833920 Vio18 = 0
4852 00:25:59.834031 Vcore = 662500
4853 00:25:59.834131 Vdram = 0
4854 00:25:59.837297 Vddq = 0
4855 00:25:59.837409 Vmddr = 0
4856 00:25:59.840499 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4857 00:25:59.847327 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4858 00:25:59.850273 MEM_TYPE=3, freq_sel=17
4859 00:25:59.853783 sv_algorithm_assistance_LP4_1600
4860 00:25:59.857362 ============ PULL DRAM RESETB DOWN ============
4861 00:25:59.860317 ========== PULL DRAM RESETB DOWN end =========
4862 00:25:59.863860 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4863 00:25:59.867425 ===================================
4864 00:25:59.870416 LPDDR4 DRAM CONFIGURATION
4865 00:25:59.873993 ===================================
4866 00:25:59.877028 EX_ROW_EN[0] = 0x0
4867 00:25:59.877136 EX_ROW_EN[1] = 0x0
4868 00:25:59.880625 LP4Y_EN = 0x0
4869 00:25:59.880742 WORK_FSP = 0x0
4870 00:25:59.883887 WL = 0x3
4871 00:25:59.883998 RL = 0x3
4872 00:25:59.887213 BL = 0x2
4873 00:25:59.887326 RPST = 0x0
4874 00:25:59.890537 RD_PRE = 0x0
4875 00:25:59.893753 WR_PRE = 0x1
4876 00:25:59.893860 WR_PST = 0x0
4877 00:25:59.896817 DBI_WR = 0x0
4878 00:25:59.896924 DBI_RD = 0x0
4879 00:25:59.899888 OTF = 0x1
4880 00:25:59.903724 ===================================
4881 00:25:59.906598 ===================================
4882 00:25:59.906709 ANA top config
4883 00:25:59.909924 ===================================
4884 00:25:59.913682 DLL_ASYNC_EN = 0
4885 00:25:59.916557 ALL_SLAVE_EN = 1
4886 00:25:59.916684 NEW_RANK_MODE = 1
4887 00:25:59.920088 DLL_IDLE_MODE = 1
4888 00:25:59.923616 LP45_APHY_COMB_EN = 1
4889 00:25:59.926649 TX_ODT_DIS = 1
4890 00:25:59.926759 NEW_8X_MODE = 1
4891 00:25:59.930101 ===================================
4892 00:25:59.933532 ===================================
4893 00:25:59.936551 data_rate = 1866
4894 00:25:59.940210 CKR = 1
4895 00:25:59.943087 DQ_P2S_RATIO = 8
4896 00:25:59.946388 ===================================
4897 00:25:59.950130 CA_P2S_RATIO = 8
4898 00:25:59.953348 DQ_CA_OPEN = 0
4899 00:25:59.953510 DQ_SEMI_OPEN = 0
4900 00:25:59.956842 CA_SEMI_OPEN = 0
4901 00:25:59.959795 CA_FULL_RATE = 0
4902 00:25:59.963397 DQ_CKDIV4_EN = 1
4903 00:25:59.966262 CA_CKDIV4_EN = 1
4904 00:25:59.969537 CA_PREDIV_EN = 0
4905 00:25:59.969606 PH8_DLY = 0
4906 00:25:59.973211 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4907 00:25:59.976769 DQ_AAMCK_DIV = 4
4908 00:25:59.979739 CA_AAMCK_DIV = 4
4909 00:25:59.983272 CA_ADMCK_DIV = 4
4910 00:25:59.986160 DQ_TRACK_CA_EN = 0
4911 00:25:59.989600 CA_PICK = 933
4912 00:25:59.989665 CA_MCKIO = 933
4913 00:25:59.992953 MCKIO_SEMI = 0
4914 00:25:59.996445 PLL_FREQ = 3732
4915 00:25:59.999350 DQ_UI_PI_RATIO = 32
4916 00:26:00.002808 CA_UI_PI_RATIO = 0
4917 00:26:00.005974 ===================================
4918 00:26:00.009665 ===================================
4919 00:26:00.012774 memory_type:LPDDR4
4920 00:26:00.012842 GP_NUM : 10
4921 00:26:00.015953 SRAM_EN : 1
4922 00:26:00.016023 MD32_EN : 0
4923 00:26:00.019228 ===================================
4924 00:26:00.022943 [ANA_INIT] >>>>>>>>>>>>>>
4925 00:26:00.026361 <<<<<< [CONFIGURE PHASE]: ANA_TX
4926 00:26:00.029103 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4927 00:26:00.032726 ===================================
4928 00:26:00.036347 data_rate = 1866,PCW = 0X8f00
4929 00:26:00.039364 ===================================
4930 00:26:00.042948 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4931 00:26:00.045901 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4932 00:26:00.053037 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4933 00:26:00.059592 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4934 00:26:00.062782 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4935 00:26:00.066273 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4936 00:26:00.066341 [ANA_INIT] flow start
4937 00:26:00.069275 [ANA_INIT] PLL >>>>>>>>
4938 00:26:00.072796 [ANA_INIT] PLL <<<<<<<<
4939 00:26:00.072858 [ANA_INIT] MIDPI >>>>>>>>
4940 00:26:00.075595 [ANA_INIT] MIDPI <<<<<<<<
4941 00:26:00.079202 [ANA_INIT] DLL >>>>>>>>
4942 00:26:00.079266 [ANA_INIT] flow end
4943 00:26:00.085744 ============ LP4 DIFF to SE enter ============
4944 00:26:00.089342 ============ LP4 DIFF to SE exit ============
4945 00:26:00.089410 [ANA_INIT] <<<<<<<<<<<<<
4946 00:26:00.092778 [Flow] Enable top DCM control >>>>>
4947 00:26:00.096184 [Flow] Enable top DCM control <<<<<
4948 00:26:00.098968 Enable DLL master slave shuffle
4949 00:26:00.105897 ==============================================================
4950 00:26:00.108911 Gating Mode config
4951 00:26:00.112366 ==============================================================
4952 00:26:00.115629 Config description:
4953 00:26:00.125820 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4954 00:26:00.132244 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4955 00:26:00.135535 SELPH_MODE 0: By rank 1: By Phase
4956 00:26:00.142301 ==============================================================
4957 00:26:00.145248 GAT_TRACK_EN = 1
4958 00:26:00.148815 RX_GATING_MODE = 2
4959 00:26:00.152426 RX_GATING_TRACK_MODE = 2
4960 00:26:00.152518 SELPH_MODE = 1
4961 00:26:00.155374 PICG_EARLY_EN = 1
4962 00:26:00.159025 VALID_LAT_VALUE = 1
4963 00:26:00.165363 ==============================================================
4964 00:26:00.168620 Enter into Gating configuration >>>>
4965 00:26:00.172197 Exit from Gating configuration <<<<
4966 00:26:00.175629 Enter into DVFS_PRE_config >>>>>
4967 00:26:00.185638 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4968 00:26:00.188536 Exit from DVFS_PRE_config <<<<<
4969 00:26:00.192061 Enter into PICG configuration >>>>
4970 00:26:00.195618 Exit from PICG configuration <<<<
4971 00:26:00.198437 [RX_INPUT] configuration >>>>>
4972 00:26:00.201884 [RX_INPUT] configuration <<<<<
4973 00:26:00.205359 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4974 00:26:00.211899 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4975 00:26:00.218345 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4976 00:26:00.225303 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4977 00:26:00.231663 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4978 00:26:00.235053 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4979 00:26:00.241644 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4980 00:26:00.244786 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4981 00:26:00.248131 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4982 00:26:00.251632 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4983 00:26:00.258160 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4984 00:26:00.261155 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4985 00:26:00.264678 ===================================
4986 00:26:00.268217 LPDDR4 DRAM CONFIGURATION
4987 00:26:00.271088 ===================================
4988 00:26:00.271164 EX_ROW_EN[0] = 0x0
4989 00:26:00.274538 EX_ROW_EN[1] = 0x0
4990 00:26:00.274634 LP4Y_EN = 0x0
4991 00:26:00.277903 WORK_FSP = 0x0
4992 00:26:00.277983 WL = 0x3
4993 00:26:00.281115 RL = 0x3
4994 00:26:00.281209 BL = 0x2
4995 00:26:00.284822 RPST = 0x0
4996 00:26:00.284890 RD_PRE = 0x0
4997 00:26:00.287873 WR_PRE = 0x1
4998 00:26:00.287977 WR_PST = 0x0
4999 00:26:00.291371 DBI_WR = 0x0
5000 00:26:00.294366 DBI_RD = 0x0
5001 00:26:00.294471 OTF = 0x1
5002 00:26:00.297993 ===================================
5003 00:26:00.300949 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5004 00:26:00.304378 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5005 00:26:00.311450 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5006 00:26:00.314408 ===================================
5007 00:26:00.318020 LPDDR4 DRAM CONFIGURATION
5008 00:26:00.320909 ===================================
5009 00:26:00.320988 EX_ROW_EN[0] = 0x10
5010 00:26:00.324434 EX_ROW_EN[1] = 0x0
5011 00:26:00.324536 LP4Y_EN = 0x0
5012 00:26:00.327765 WORK_FSP = 0x0
5013 00:26:00.327843 WL = 0x3
5014 00:26:00.331208 RL = 0x3
5015 00:26:00.331285 BL = 0x2
5016 00:26:00.334672 RPST = 0x0
5017 00:26:00.334775 RD_PRE = 0x0
5018 00:26:00.337547 WR_PRE = 0x1
5019 00:26:00.337625 WR_PST = 0x0
5020 00:26:00.341029 DBI_WR = 0x0
5021 00:26:00.341108 DBI_RD = 0x0
5022 00:26:00.344563 OTF = 0x1
5023 00:26:00.347487 ===================================
5024 00:26:00.354058 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5025 00:26:00.357436 nWR fixed to 30
5026 00:26:00.361057 [ModeRegInit_LP4] CH0 RK0
5027 00:26:00.361136 [ModeRegInit_LP4] CH0 RK1
5028 00:26:00.364112 [ModeRegInit_LP4] CH1 RK0
5029 00:26:00.367632 [ModeRegInit_LP4] CH1 RK1
5030 00:26:00.367709 match AC timing 9
5031 00:26:00.374167 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5032 00:26:00.377173 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5033 00:26:00.380714 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5034 00:26:00.387212 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5035 00:26:00.390711 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5036 00:26:00.390791 ==
5037 00:26:00.393909 Dram Type= 6, Freq= 0, CH_0, rank 0
5038 00:26:00.397017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5039 00:26:00.397119 ==
5040 00:26:00.403598 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5041 00:26:00.410478 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5042 00:26:00.413743 [CA 0] Center 38 (8~69) winsize 62
5043 00:26:00.417134 [CA 1] Center 38 (8~69) winsize 62
5044 00:26:00.420153 [CA 2] Center 35 (5~66) winsize 62
5045 00:26:00.423713 [CA 3] Center 34 (4~65) winsize 62
5046 00:26:00.427202 [CA 4] Center 34 (3~65) winsize 63
5047 00:26:00.430608 [CA 5] Center 33 (3~64) winsize 62
5048 00:26:00.430680
5049 00:26:00.433505 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5050 00:26:00.433569
5051 00:26:00.436977 [CATrainingPosCal] consider 1 rank data
5052 00:26:00.440495 u2DelayCellTimex100 = 270/100 ps
5053 00:26:00.443460 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5054 00:26:00.446963 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5055 00:26:00.450019 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5056 00:26:00.453383 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5057 00:26:00.460094 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5058 00:26:00.463513 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5059 00:26:00.463609
5060 00:26:00.466440 CA PerBit enable=1, Macro0, CA PI delay=33
5061 00:26:00.466519
5062 00:26:00.470086 [CBTSetCACLKResult] CA Dly = 33
5063 00:26:00.470164 CS Dly: 7 (0~38)
5064 00:26:00.470225 ==
5065 00:26:00.473009 Dram Type= 6, Freq= 0, CH_0, rank 1
5066 00:26:00.480104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5067 00:26:00.480183 ==
5068 00:26:00.483553 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5069 00:26:00.490077 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5070 00:26:00.493060 [CA 0] Center 38 (8~69) winsize 62
5071 00:26:00.496546 [CA 1] Center 38 (8~69) winsize 62
5072 00:26:00.499559 [CA 2] Center 35 (5~66) winsize 62
5073 00:26:00.503031 [CA 3] Center 35 (5~66) winsize 62
5074 00:26:00.506006 [CA 4] Center 34 (4~65) winsize 62
5075 00:26:00.509341 [CA 5] Center 33 (3~64) winsize 62
5076 00:26:00.509419
5077 00:26:00.512584 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5078 00:26:00.512672
5079 00:26:00.516178 [CATrainingPosCal] consider 2 rank data
5080 00:26:00.519332 u2DelayCellTimex100 = 270/100 ps
5081 00:26:00.522472 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5082 00:26:00.526041 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5083 00:26:00.532796 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5084 00:26:00.536039 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5085 00:26:00.539537 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5086 00:26:00.542318 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5087 00:26:00.542396
5088 00:26:00.545882 CA PerBit enable=1, Macro0, CA PI delay=33
5089 00:26:00.545960
5090 00:26:00.549372 [CBTSetCACLKResult] CA Dly = 33
5091 00:26:00.549451 CS Dly: 7 (0~39)
5092 00:26:00.552272
5093 00:26:00.555750 ----->DramcWriteLeveling(PI) begin...
5094 00:26:00.555829 ==
5095 00:26:00.559154 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 00:26:00.562730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 00:26:00.562809 ==
5098 00:26:00.565620 Write leveling (Byte 0): 29 => 29
5099 00:26:00.568955 Write leveling (Byte 1): 29 => 29
5100 00:26:00.572423 DramcWriteLeveling(PI) end<-----
5101 00:26:00.572515
5102 00:26:00.572602 ==
5103 00:26:00.575418 Dram Type= 6, Freq= 0, CH_0, rank 0
5104 00:26:00.579001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 00:26:00.579078 ==
5106 00:26:00.582064 [Gating] SW mode calibration
5107 00:26:00.589095 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5108 00:26:00.595730 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5109 00:26:00.598668 0 14 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5110 00:26:00.602321 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5111 00:26:00.608804 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 00:26:00.612378 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 00:26:00.615267 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 00:26:00.621724 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 00:26:00.625199 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 00:26:00.628488 0 14 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5117 00:26:00.635447 0 15 0 | B1->B0 | 3434 2b2b | 1 0 | (0 1) (0 1)
5118 00:26:00.638364 0 15 4 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
5119 00:26:00.641745 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 00:26:00.648239 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 00:26:00.651608 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 00:26:00.655037 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 00:26:00.661677 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 00:26:00.665123 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 00:26:00.667955 1 0 0 | B1->B0 | 2d2d 3b3b | 0 0 | (0 0) (0 0)
5126 00:26:00.674896 1 0 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5127 00:26:00.677897 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 00:26:00.681465 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 00:26:00.687977 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 00:26:00.691088 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 00:26:00.694633 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 00:26:00.701146 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 00:26:00.704650 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5134 00:26:00.707619 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 00:26:00.714175 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 00:26:00.717754 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 00:26:00.720737 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 00:26:00.727375 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 00:26:00.730934 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 00:26:00.734465 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 00:26:00.741079 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 00:26:00.743944 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 00:26:00.747181 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 00:26:00.754065 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 00:26:00.757306 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 00:26:00.760987 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 00:26:00.764156 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 00:26:00.770608 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5149 00:26:00.773997 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5150 00:26:00.777339 Total UI for P1: 0, mck2ui 16
5151 00:26:00.780762 best dqsien dly found for B0: ( 1, 2, 28)
5152 00:26:00.783810 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 00:26:00.787175 Total UI for P1: 0, mck2ui 16
5154 00:26:00.790502 best dqsien dly found for B1: ( 1, 3, 0)
5155 00:26:00.793943 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5156 00:26:00.796966 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5157 00:26:00.800483
5158 00:26:00.804065 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5159 00:26:00.807002 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5160 00:26:00.810418 [Gating] SW calibration Done
5161 00:26:00.810482 ==
5162 00:26:00.813951 Dram Type= 6, Freq= 0, CH_0, rank 0
5163 00:26:00.816903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5164 00:26:00.816997 ==
5165 00:26:00.817106 RX Vref Scan: 0
5166 00:26:00.820491
5167 00:26:00.820614 RX Vref 0 -> 0, step: 1
5168 00:26:00.820709
5169 00:26:00.823903 RX Delay -80 -> 252, step: 8
5170 00:26:00.826862 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5171 00:26:00.830419 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5172 00:26:00.836877 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5173 00:26:00.840387 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5174 00:26:00.843439 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5175 00:26:00.846932 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5176 00:26:00.849936 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5177 00:26:00.853455 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5178 00:26:00.860190 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5179 00:26:00.863583 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5180 00:26:00.866599 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5181 00:26:00.870343 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5182 00:26:00.873711 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5183 00:26:00.879938 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5184 00:26:00.883268 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5185 00:26:00.886452 iDelay=208, Bit 15, Center 87 (-16 ~ 191) 208
5186 00:26:00.886524 ==
5187 00:26:00.889738 Dram Type= 6, Freq= 0, CH_0, rank 0
5188 00:26:00.893378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5189 00:26:00.893455 ==
5190 00:26:00.896511 DQS Delay:
5191 00:26:00.896587 DQS0 = 0, DQS1 = 0
5192 00:26:00.899771 DQM Delay:
5193 00:26:00.899849 DQM0 = 93, DQM1 = 82
5194 00:26:00.902960 DQ Delay:
5195 00:26:00.903036 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5196 00:26:00.906484 DQ4 =91, DQ5 =79, DQ6 =99, DQ7 =107
5197 00:26:00.909931 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5198 00:26:00.912824 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =87
5199 00:26:00.912900
5200 00:26:00.916474
5201 00:26:00.916587 ==
5202 00:26:00.919986 Dram Type= 6, Freq= 0, CH_0, rank 0
5203 00:26:00.922938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5204 00:26:00.923014 ==
5205 00:26:00.923073
5206 00:26:00.923126
5207 00:26:00.926429 TX Vref Scan disable
5208 00:26:00.926504 == TX Byte 0 ==
5209 00:26:00.932994 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5210 00:26:00.936542 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5211 00:26:00.936650 == TX Byte 1 ==
5212 00:26:00.942792 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5213 00:26:00.946348 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5214 00:26:00.946424 ==
5215 00:26:00.949822 Dram Type= 6, Freq= 0, CH_0, rank 0
5216 00:26:00.952817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5217 00:26:00.952893 ==
5218 00:26:00.952952
5219 00:26:00.953005
5220 00:26:00.956359 TX Vref Scan disable
5221 00:26:00.959339 == TX Byte 0 ==
5222 00:26:00.962704 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5223 00:26:00.966065 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5224 00:26:00.969458 == TX Byte 1 ==
5225 00:26:00.972648 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5226 00:26:00.976072 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5227 00:26:00.976172
5228 00:26:00.979551 [DATLAT]
5229 00:26:00.979620 Freq=933, CH0 RK0
5230 00:26:00.979677
5231 00:26:00.982920 DATLAT Default: 0xd
5232 00:26:00.983014 0, 0xFFFF, sum = 0
5233 00:26:00.985785 1, 0xFFFF, sum = 0
5234 00:26:00.985860 2, 0xFFFF, sum = 0
5235 00:26:00.989251 3, 0xFFFF, sum = 0
5236 00:26:00.989320 4, 0xFFFF, sum = 0
5237 00:26:00.992593 5, 0xFFFF, sum = 0
5238 00:26:00.992707 6, 0xFFFF, sum = 0
5239 00:26:00.996023 7, 0xFFFF, sum = 0
5240 00:26:00.996131 8, 0xFFFF, sum = 0
5241 00:26:00.999040 9, 0xFFFF, sum = 0
5242 00:26:00.999109 10, 0x0, sum = 1
5243 00:26:01.002560 11, 0x0, sum = 2
5244 00:26:01.002652 12, 0x0, sum = 3
5245 00:26:01.005849 13, 0x0, sum = 4
5246 00:26:01.005949 best_step = 11
5247 00:26:01.006042
5248 00:26:01.006125 ==
5249 00:26:01.009146 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 00:26:01.016001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 00:26:01.016100 ==
5252 00:26:01.016182 RX Vref Scan: 1
5253 00:26:01.016268
5254 00:26:01.019085 RX Vref 0 -> 0, step: 1
5255 00:26:01.019151
5256 00:26:01.022414 RX Delay -69 -> 252, step: 4
5257 00:26:01.022490
5258 00:26:01.026021 Set Vref, RX VrefLevel [Byte0]: 62
5259 00:26:01.028949 [Byte1]: 49
5260 00:26:01.029015
5261 00:26:01.032477 Final RX Vref Byte 0 = 62 to rank0
5262 00:26:01.036082 Final RX Vref Byte 1 = 49 to rank0
5263 00:26:01.039027 Final RX Vref Byte 0 = 62 to rank1
5264 00:26:01.042525 Final RX Vref Byte 1 = 49 to rank1==
5265 00:26:01.045471 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 00:26:01.048916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 00:26:01.048985 ==
5268 00:26:01.052541 DQS Delay:
5269 00:26:01.052621 DQS0 = 0, DQS1 = 0
5270 00:26:01.052700 DQM Delay:
5271 00:26:01.055637 DQM0 = 95, DQM1 = 83
5272 00:26:01.055711 DQ Delay:
5273 00:26:01.059154 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5274 00:26:01.062173 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5275 00:26:01.065731 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =76
5276 00:26:01.069120 DQ12 =88, DQ13 =88, DQ14 =96, DQ15 =90
5277 00:26:01.069198
5278 00:26:01.069256
5279 00:26:01.078947 [DQSOSCAuto] RK0, (LSB)MR18= 0x1716, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 414 ps
5280 00:26:01.082249 CH0 RK0: MR19=505, MR18=1716
5281 00:26:01.085369 CH0_RK0: MR19=0x505, MR18=0x1716, DQSOSC=414, MR23=63, INC=63, DEC=42
5282 00:26:01.085441
5283 00:26:01.091840 ----->DramcWriteLeveling(PI) begin...
5284 00:26:01.091914 ==
5285 00:26:01.095263 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 00:26:01.098663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 00:26:01.098763 ==
5288 00:26:01.102133 Write leveling (Byte 0): 33 => 33
5289 00:26:01.105646 Write leveling (Byte 1): 29 => 29
5290 00:26:01.108664 DramcWriteLeveling(PI) end<-----
5291 00:26:01.108740
5292 00:26:01.108802 ==
5293 00:26:01.112026 Dram Type= 6, Freq= 0, CH_0, rank 1
5294 00:26:01.115021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 00:26:01.115109 ==
5296 00:26:01.118539 [Gating] SW mode calibration
5297 00:26:01.124739 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5298 00:26:01.131440 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5299 00:26:01.135087 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5300 00:26:01.138427 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 00:26:01.144984 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 00:26:01.147866 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 00:26:01.151256 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 00:26:01.158234 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 00:26:01.161250 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 00:26:01.164770 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
5307 00:26:01.171124 0 15 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
5308 00:26:01.174500 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 00:26:01.178031 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 00:26:01.184466 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 00:26:01.187975 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 00:26:01.190930 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 00:26:01.197826 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 00:26:01.201351 0 15 28 | B1->B0 | 2424 3535 | 0 0 | (0 0) (0 0)
5315 00:26:01.204867 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5316 00:26:01.210954 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 00:26:01.214702 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 00:26:01.217684 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 00:26:01.224653 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 00:26:01.227693 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 00:26:01.231238 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 00:26:01.234261 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5323 00:26:01.241186 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 00:26:01.244517 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 00:26:01.247683 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 00:26:01.254571 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 00:26:01.257602 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 00:26:01.261155 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 00:26:01.267601 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 00:26:01.271222 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 00:26:01.274082 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 00:26:01.281002 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 00:26:01.283970 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 00:26:01.287465 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 00:26:01.294098 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 00:26:01.297750 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 00:26:01.300761 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 00:26:01.307597 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 00:26:01.310832 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5340 00:26:01.314348 Total UI for P1: 0, mck2ui 16
5341 00:26:01.317430 best dqsien dly found for B0: ( 1, 2, 30)
5342 00:26:01.320544 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 00:26:01.324208 Total UI for P1: 0, mck2ui 16
5344 00:26:01.327437 best dqsien dly found for B1: ( 1, 3, 0)
5345 00:26:01.330463 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5346 00:26:01.334043 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5347 00:26:01.334119
5348 00:26:01.340488 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5349 00:26:01.344141 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5350 00:26:01.344215 [Gating] SW calibration Done
5351 00:26:01.344273 ==
5352 00:26:01.347243 Dram Type= 6, Freq= 0, CH_0, rank 1
5353 00:26:01.353823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 00:26:01.353899 ==
5355 00:26:01.353957 RX Vref Scan: 0
5356 00:26:01.354010
5357 00:26:01.356965 RX Vref 0 -> 0, step: 1
5358 00:26:01.357039
5359 00:26:01.360516 RX Delay -80 -> 252, step: 8
5360 00:26:01.363558 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5361 00:26:01.367042 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5362 00:26:01.370097 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5363 00:26:01.377127 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5364 00:26:01.380076 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5365 00:26:01.383575 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5366 00:26:01.386902 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5367 00:26:01.389907 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5368 00:26:01.396432 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5369 00:26:01.400002 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5370 00:26:01.403071 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5371 00:26:01.406532 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5372 00:26:01.410129 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5373 00:26:01.416782 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5374 00:26:01.419539 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5375 00:26:01.422893 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5376 00:26:01.423016 ==
5377 00:26:01.426620 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 00:26:01.429527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 00:26:01.429604 ==
5380 00:26:01.432918 DQS Delay:
5381 00:26:01.433026 DQS0 = 0, DQS1 = 0
5382 00:26:01.436158 DQM Delay:
5383 00:26:01.436249 DQM0 = 92, DQM1 = 83
5384 00:26:01.436353 DQ Delay:
5385 00:26:01.439378 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =91
5386 00:26:01.442688 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =103
5387 00:26:01.445986 DQ8 =75, DQ9 =63, DQ10 =87, DQ11 =79
5388 00:26:01.449470 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =87
5389 00:26:01.449610
5390 00:26:01.449672
5391 00:26:01.452978 ==
5392 00:26:01.456055 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 00:26:01.459624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 00:26:01.459701 ==
5395 00:26:01.459760
5396 00:26:01.459815
5397 00:26:01.462637 TX Vref Scan disable
5398 00:26:01.462713 == TX Byte 0 ==
5399 00:26:01.466390 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5400 00:26:01.472773 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5401 00:26:01.472862 == TX Byte 1 ==
5402 00:26:01.476086 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5403 00:26:01.482814 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5404 00:26:01.482887 ==
5405 00:26:01.485729 Dram Type= 6, Freq= 0, CH_0, rank 1
5406 00:26:01.489300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5407 00:26:01.489377 ==
5408 00:26:01.489437
5409 00:26:01.489529
5410 00:26:01.492701 TX Vref Scan disable
5411 00:26:01.495701 == TX Byte 0 ==
5412 00:26:01.499298 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5413 00:26:01.502377 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5414 00:26:01.505886 == TX Byte 1 ==
5415 00:26:01.508815 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5416 00:26:01.512283 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5417 00:26:01.512379
5418 00:26:01.515881 [DATLAT]
5419 00:26:01.515974 Freq=933, CH0 RK1
5420 00:26:01.516067
5421 00:26:01.518836 DATLAT Default: 0xb
5422 00:26:01.518934 0, 0xFFFF, sum = 0
5423 00:26:01.522372 1, 0xFFFF, sum = 0
5424 00:26:01.522470 2, 0xFFFF, sum = 0
5425 00:26:01.525331 3, 0xFFFF, sum = 0
5426 00:26:01.525425 4, 0xFFFF, sum = 0
5427 00:26:01.528605 5, 0xFFFF, sum = 0
5428 00:26:01.528687 6, 0xFFFF, sum = 0
5429 00:26:01.532303 7, 0xFFFF, sum = 0
5430 00:26:01.532415 8, 0xFFFF, sum = 0
5431 00:26:01.535113 9, 0xFFFF, sum = 0
5432 00:26:01.535216 10, 0x0, sum = 1
5433 00:26:01.538649 11, 0x0, sum = 2
5434 00:26:01.538747 12, 0x0, sum = 3
5435 00:26:01.542128 13, 0x0, sum = 4
5436 00:26:01.542221 best_step = 11
5437 00:26:01.542305
5438 00:26:01.542394 ==
5439 00:26:01.545406 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 00:26:01.551916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 00:26:01.552013 ==
5442 00:26:01.552099 RX Vref Scan: 0
5443 00:26:01.552181
5444 00:26:01.554773 RX Vref 0 -> 0, step: 1
5445 00:26:01.554837
5446 00:26:01.558366 RX Delay -77 -> 252, step: 4
5447 00:26:01.561948 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5448 00:26:01.568550 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5449 00:26:01.571630 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5450 00:26:01.575129 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5451 00:26:01.578030 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5452 00:26:01.581447 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5453 00:26:01.584660 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5454 00:26:01.591662 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5455 00:26:01.594833 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5456 00:26:01.598027 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5457 00:26:01.601668 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5458 00:26:01.604648 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5459 00:26:01.611181 iDelay=199, Bit 12, Center 88 (-5 ~ 182) 188
5460 00:26:01.614673 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5461 00:26:01.618238 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5462 00:26:01.621191 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5463 00:26:01.621260 ==
5464 00:26:01.624783 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 00:26:01.631283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 00:26:01.631384 ==
5467 00:26:01.631471 DQS Delay:
5468 00:26:01.631553 DQS0 = 0, DQS1 = 0
5469 00:26:01.634238 DQM Delay:
5470 00:26:01.634302 DQM0 = 91, DQM1 = 84
5471 00:26:01.637526 DQ Delay:
5472 00:26:01.640863 DQ0 =88, DQ1 =94, DQ2 =88, DQ3 =88
5473 00:26:01.644062 DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =102
5474 00:26:01.647678 DQ8 =76, DQ9 =68, DQ10 =86, DQ11 =76
5475 00:26:01.651027 DQ12 =88, DQ13 =90, DQ14 =96, DQ15 =92
5476 00:26:01.651118
5477 00:26:01.651203
5478 00:26:01.657417 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d10, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 407 ps
5479 00:26:01.660860 CH0 RK1: MR19=505, MR18=2D10
5480 00:26:01.667230 CH0_RK1: MR19=0x505, MR18=0x2D10, DQSOSC=407, MR23=63, INC=65, DEC=43
5481 00:26:01.670832 [RxdqsGatingPostProcess] freq 933
5482 00:26:01.673765 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5483 00:26:01.677508 best DQS0 dly(2T, 0.5T) = (0, 10)
5484 00:26:01.680407 best DQS1 dly(2T, 0.5T) = (0, 11)
5485 00:26:01.684002 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5486 00:26:01.686960 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5487 00:26:01.690515 best DQS0 dly(2T, 0.5T) = (0, 10)
5488 00:26:01.693942 best DQS1 dly(2T, 0.5T) = (0, 11)
5489 00:26:01.696850 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5490 00:26:01.700498 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5491 00:26:01.703826 Pre-setting of DQS Precalculation
5492 00:26:01.707344 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5493 00:26:01.710390 ==
5494 00:26:01.710466 Dram Type= 6, Freq= 0, CH_1, rank 0
5495 00:26:01.717021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 00:26:01.717098 ==
5497 00:26:01.720482 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5498 00:26:01.727002 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5499 00:26:01.730507 [CA 0] Center 37 (7~68) winsize 62
5500 00:26:01.734035 [CA 1] Center 37 (7~68) winsize 62
5501 00:26:01.736998 [CA 2] Center 34 (5~64) winsize 60
5502 00:26:01.740634 [CA 3] Center 34 (4~64) winsize 61
5503 00:26:01.743600 [CA 4] Center 35 (5~65) winsize 61
5504 00:26:01.747089 [CA 5] Center 34 (4~64) winsize 61
5505 00:26:01.747170
5506 00:26:01.750729 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5507 00:26:01.750805
5508 00:26:01.753907 [CATrainingPosCal] consider 1 rank data
5509 00:26:01.757122 u2DelayCellTimex100 = 270/100 ps
5510 00:26:01.760614 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5511 00:26:01.766952 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5512 00:26:01.770563 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5513 00:26:01.773505 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5514 00:26:01.777104 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5515 00:26:01.780153 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5516 00:26:01.780229
5517 00:26:01.783746 CA PerBit enable=1, Macro0, CA PI delay=34
5518 00:26:01.783822
5519 00:26:01.786792 [CBTSetCACLKResult] CA Dly = 34
5520 00:26:01.786868 CS Dly: 6 (0~37)
5521 00:26:01.790385 ==
5522 00:26:01.790461 Dram Type= 6, Freq= 0, CH_1, rank 1
5523 00:26:01.796661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5524 00:26:01.796753 ==
5525 00:26:01.800280 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5526 00:26:01.806792 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5527 00:26:01.810473 [CA 0] Center 37 (7~68) winsize 62
5528 00:26:01.813865 [CA 1] Center 37 (7~68) winsize 62
5529 00:26:01.816748 [CA 2] Center 35 (5~65) winsize 61
5530 00:26:01.820334 [CA 3] Center 34 (4~64) winsize 61
5531 00:26:01.823291 [CA 4] Center 35 (5~65) winsize 61
5532 00:26:01.826862 [CA 5] Center 34 (4~64) winsize 61
5533 00:26:01.826953
5534 00:26:01.830351 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5535 00:26:01.830428
5536 00:26:01.833470 [CATrainingPosCal] consider 2 rank data
5537 00:26:01.836897 u2DelayCellTimex100 = 270/100 ps
5538 00:26:01.840500 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5539 00:26:01.846908 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5540 00:26:01.849924 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5541 00:26:01.853442 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5542 00:26:01.856796 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5543 00:26:01.860492 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5544 00:26:01.860554
5545 00:26:01.863716 CA PerBit enable=1, Macro0, CA PI delay=34
5546 00:26:01.863792
5547 00:26:01.866797 [CBTSetCACLKResult] CA Dly = 34
5548 00:26:01.866874 CS Dly: 7 (0~39)
5549 00:26:01.870082
5550 00:26:01.873528 ----->DramcWriteLeveling(PI) begin...
5551 00:26:01.873624 ==
5552 00:26:01.876834 Dram Type= 6, Freq= 0, CH_1, rank 0
5553 00:26:01.879784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 00:26:01.879875 ==
5555 00:26:01.883349 Write leveling (Byte 0): 24 => 24
5556 00:26:01.886418 Write leveling (Byte 1): 29 => 29
5557 00:26:01.889968 DramcWriteLeveling(PI) end<-----
5558 00:26:01.890043
5559 00:26:01.890210 ==
5560 00:26:01.893503 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 00:26:01.896498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 00:26:01.896575 ==
5563 00:26:01.899972 [Gating] SW mode calibration
5564 00:26:01.906378 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5565 00:26:01.912872 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5566 00:26:01.916379 0 14 0 | B1->B0 | 2e2e 3131 | 1 0 | (1 1) (0 0)
5567 00:26:01.919990 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 00:26:01.926522 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 00:26:01.929958 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 00:26:01.932882 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 00:26:01.939572 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 00:26:01.942954 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 00:26:01.946520 0 14 28 | B1->B0 | 2e2e 2f2f | 0 0 | (0 1) (0 1)
5574 00:26:01.952933 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 00:26:01.956370 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 00:26:01.959861 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 00:26:01.966086 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 00:26:01.969458 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 00:26:01.972715 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 00:26:01.976521 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 00:26:01.982701 0 15 28 | B1->B0 | 3131 3030 | 0 0 | (0 0) (0 0)
5582 00:26:01.986057 1 0 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5583 00:26:01.989623 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 00:26:01.995972 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 00:26:01.999443 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 00:26:02.002936 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 00:26:02.009779 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 00:26:02.012655 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 00:26:02.016309 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5590 00:26:02.022869 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5591 00:26:02.026319 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 00:26:02.029286 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 00:26:02.036212 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 00:26:02.039193 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 00:26:02.042794 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 00:26:02.049090 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 00:26:02.052627 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 00:26:02.056050 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 00:26:02.062427 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 00:26:02.065688 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 00:26:02.068826 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 00:26:02.075911 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 00:26:02.078999 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 00:26:02.082373 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5605 00:26:02.089071 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5606 00:26:02.092268 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 00:26:02.095574 Total UI for P1: 0, mck2ui 16
5608 00:26:02.098940 best dqsien dly found for B0: ( 1, 2, 28)
5609 00:26:02.102475 Total UI for P1: 0, mck2ui 16
5610 00:26:02.105921 best dqsien dly found for B1: ( 1, 2, 26)
5611 00:26:02.108928 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5612 00:26:02.112276 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5613 00:26:02.112344
5614 00:26:02.115234 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5615 00:26:02.118793 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5616 00:26:02.122298 [Gating] SW calibration Done
5617 00:26:02.122375 ==
5618 00:26:02.125318 Dram Type= 6, Freq= 0, CH_1, rank 0
5619 00:26:02.128840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5620 00:26:02.131710 ==
5621 00:26:02.131784 RX Vref Scan: 0
5622 00:26:02.131844
5623 00:26:02.135139 RX Vref 0 -> 0, step: 1
5624 00:26:02.135234
5625 00:26:02.138712 RX Delay -80 -> 252, step: 8
5626 00:26:02.141672 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5627 00:26:02.145293 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5628 00:26:02.148284 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5629 00:26:02.151857 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5630 00:26:02.154878 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5631 00:26:02.162040 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5632 00:26:02.164955 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5633 00:26:02.168422 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5634 00:26:02.171435 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5635 00:26:02.174818 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5636 00:26:02.181416 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5637 00:26:02.184571 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5638 00:26:02.188104 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5639 00:26:02.191380 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5640 00:26:02.194755 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5641 00:26:02.201388 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5642 00:26:02.201464 ==
5643 00:26:02.204600 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 00:26:02.207716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 00:26:02.207838 ==
5646 00:26:02.207896 DQS Delay:
5647 00:26:02.210917 DQS0 = 0, DQS1 = 0
5648 00:26:02.210992 DQM Delay:
5649 00:26:02.214623 DQM0 = 95, DQM1 = 86
5650 00:26:02.214743 DQ Delay:
5651 00:26:02.218041 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5652 00:26:02.221034 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5653 00:26:02.224626 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5654 00:26:02.227693 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5655 00:26:02.227787
5656 00:26:02.227847
5657 00:26:02.227916 ==
5658 00:26:02.231263 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 00:26:02.234835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 00:26:02.237753 ==
5661 00:26:02.237850
5662 00:26:02.237934
5663 00:26:02.238033 TX Vref Scan disable
5664 00:26:02.241115 == TX Byte 0 ==
5665 00:26:02.244561 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5666 00:26:02.247525 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5667 00:26:02.251091 == TX Byte 1 ==
5668 00:26:02.254120 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5669 00:26:02.257658 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5670 00:26:02.257734 ==
5671 00:26:02.261302 Dram Type= 6, Freq= 0, CH_1, rank 0
5672 00:26:02.267914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5673 00:26:02.267997 ==
5674 00:26:02.268058
5675 00:26:02.268112
5676 00:26:02.270822 TX Vref Scan disable
5677 00:26:02.270897 == TX Byte 0 ==
5678 00:26:02.277191 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5679 00:26:02.280786 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5680 00:26:02.280854 == TX Byte 1 ==
5681 00:26:02.287388 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5682 00:26:02.290265 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5683 00:26:02.290335
5684 00:26:02.290392 [DATLAT]
5685 00:26:02.293696 Freq=933, CH1 RK0
5686 00:26:02.293761
5687 00:26:02.293815 DATLAT Default: 0xd
5688 00:26:02.297121 0, 0xFFFF, sum = 0
5689 00:26:02.297198 1, 0xFFFF, sum = 0
5690 00:26:02.300424 2, 0xFFFF, sum = 0
5691 00:26:02.300500 3, 0xFFFF, sum = 0
5692 00:26:02.303625 4, 0xFFFF, sum = 0
5693 00:26:02.303701 5, 0xFFFF, sum = 0
5694 00:26:02.307192 6, 0xFFFF, sum = 0
5695 00:26:02.310462 7, 0xFFFF, sum = 0
5696 00:26:02.310538 8, 0xFFFF, sum = 0
5697 00:26:02.313554 9, 0xFFFF, sum = 0
5698 00:26:02.313629 10, 0x0, sum = 1
5699 00:26:02.316893 11, 0x0, sum = 2
5700 00:26:02.316969 12, 0x0, sum = 3
5701 00:26:02.317029 13, 0x0, sum = 4
5702 00:26:02.320530 best_step = 11
5703 00:26:02.320618
5704 00:26:02.320700 ==
5705 00:26:02.323357 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 00:26:02.326680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 00:26:02.326756 ==
5708 00:26:02.329984 RX Vref Scan: 1
5709 00:26:02.330060
5710 00:26:02.333742 RX Vref 0 -> 0, step: 1
5711 00:26:02.333819
5712 00:26:02.333934 RX Delay -69 -> 252, step: 4
5713 00:26:02.334017
5714 00:26:02.336482 Set Vref, RX VrefLevel [Byte0]: 60
5715 00:26:02.339940 [Byte1]: 50
5716 00:26:02.344493
5717 00:26:02.344584 Final RX Vref Byte 0 = 60 to rank0
5718 00:26:02.347964 Final RX Vref Byte 1 = 50 to rank0
5719 00:26:02.351556 Final RX Vref Byte 0 = 60 to rank1
5720 00:26:02.354423 Final RX Vref Byte 1 = 50 to rank1==
5721 00:26:02.357983 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 00:26:02.364506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 00:26:02.364582 ==
5724 00:26:02.364640 DQS Delay:
5725 00:26:02.364758 DQS0 = 0, DQS1 = 0
5726 00:26:02.368054 DQM Delay:
5727 00:26:02.368129 DQM0 = 95, DQM1 = 88
5728 00:26:02.371066 DQ Delay:
5729 00:26:02.374581 DQ0 =102, DQ1 =92, DQ2 =84, DQ3 =90
5730 00:26:02.378133 DQ4 =94, DQ5 =106, DQ6 =106, DQ7 =92
5731 00:26:02.381087 DQ8 =78, DQ9 =80, DQ10 =88, DQ11 =80
5732 00:26:02.384677 DQ12 =100, DQ13 =92, DQ14 =96, DQ15 =96
5733 00:26:02.384766
5734 00:26:02.384823
5735 00:26:02.391223 [DQSOSCAuto] RK0, (LSB)MR18= 0xff08, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5736 00:26:02.394761 CH1 RK0: MR19=405, MR18=FF08
5737 00:26:02.401025 CH1_RK0: MR19=0x405, MR18=0xFF08, DQSOSC=419, MR23=63, INC=61, DEC=41
5738 00:26:02.401130
5739 00:26:02.404561 ----->DramcWriteLeveling(PI) begin...
5740 00:26:02.404685 ==
5741 00:26:02.407896 Dram Type= 6, Freq= 0, CH_1, rank 1
5742 00:26:02.411251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 00:26:02.411327 ==
5744 00:26:02.414641 Write leveling (Byte 0): 27 => 27
5745 00:26:02.417538 Write leveling (Byte 1): 29 => 29
5746 00:26:02.420933 DramcWriteLeveling(PI) end<-----
5747 00:26:02.421008
5748 00:26:02.421066 ==
5749 00:26:02.424550 Dram Type= 6, Freq= 0, CH_1, rank 1
5750 00:26:02.427629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 00:26:02.427705 ==
5752 00:26:02.431080 [Gating] SW mode calibration
5753 00:26:02.437506 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5754 00:26:02.444232 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5755 00:26:02.447204 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 00:26:02.454117 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 00:26:02.457503 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 00:26:02.460458 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 00:26:02.467236 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 00:26:02.470785 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5761 00:26:02.473778 0 14 24 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (1 0)
5762 00:26:02.480313 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5763 00:26:02.483795 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5764 00:26:02.487225 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 00:26:02.493851 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 00:26:02.496822 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 00:26:02.500291 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 00:26:02.506838 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 00:26:02.510376 0 15 24 | B1->B0 | 2828 3535 | 0 0 | (0 0) (0 0)
5770 00:26:02.513386 0 15 28 | B1->B0 | 3434 4343 | 0 0 | (0 0) (0 0)
5771 00:26:02.520068 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 00:26:02.523830 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 00:26:02.526626 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 00:26:02.533689 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 00:26:02.536752 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 00:26:02.540349 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 00:26:02.543416 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 00:26:02.549886 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5779 00:26:02.553287 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 00:26:02.556574 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 00:26:02.563128 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 00:26:02.566779 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 00:26:02.569750 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 00:26:02.576548 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 00:26:02.580024 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 00:26:02.583318 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 00:26:02.590032 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 00:26:02.592991 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 00:26:02.596487 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 00:26:02.603119 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 00:26:02.606481 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 00:26:02.609386 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 00:26:02.615996 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5794 00:26:02.619543 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 00:26:02.622973 Total UI for P1: 0, mck2ui 16
5796 00:26:02.626364 best dqsien dly found for B0: ( 1, 2, 24)
5797 00:26:02.629632 Total UI for P1: 0, mck2ui 16
5798 00:26:02.632687 best dqsien dly found for B1: ( 1, 2, 26)
5799 00:26:02.636334 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5800 00:26:02.639262 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5801 00:26:02.639356
5802 00:26:02.642820 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5803 00:26:02.646273 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5804 00:26:02.649242 [Gating] SW calibration Done
5805 00:26:02.649334 ==
5806 00:26:02.652859 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 00:26:02.659291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 00:26:02.659393 ==
5809 00:26:02.659478 RX Vref Scan: 0
5810 00:26:02.659575
5811 00:26:02.662572 RX Vref 0 -> 0, step: 1
5812 00:26:02.662643
5813 00:26:02.665959 RX Delay -80 -> 252, step: 8
5814 00:26:02.669447 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5815 00:26:02.672345 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5816 00:26:02.675754 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5817 00:26:02.679171 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5818 00:26:02.685818 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5819 00:26:02.688872 iDelay=208, Bit 5, Center 99 (0 ~ 199) 200
5820 00:26:02.691996 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5821 00:26:02.695347 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5822 00:26:02.699266 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5823 00:26:02.705506 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5824 00:26:02.708912 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5825 00:26:02.712355 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5826 00:26:02.715366 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5827 00:26:02.718339 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5828 00:26:02.725281 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5829 00:26:02.728638 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5830 00:26:02.728761 ==
5831 00:26:02.731683 Dram Type= 6, Freq= 0, CH_1, rank 1
5832 00:26:02.735138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5833 00:26:02.735229 ==
5834 00:26:02.735311 DQS Delay:
5835 00:26:02.738481 DQS0 = 0, DQS1 = 0
5836 00:26:02.738571 DQM Delay:
5837 00:26:02.741563 DQM0 = 92, DQM1 = 88
5838 00:26:02.741635 DQ Delay:
5839 00:26:02.745207 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =91
5840 00:26:02.748525 DQ4 =91, DQ5 =99, DQ6 =103, DQ7 =91
5841 00:26:02.751534 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5842 00:26:02.755073 DQ12 =91, DQ13 =99, DQ14 =95, DQ15 =91
5843 00:26:02.755166
5844 00:26:02.755251
5845 00:26:02.755331 ==
5846 00:26:02.758608 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 00:26:02.761529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 00:26:02.764994 ==
5849 00:26:02.765102
5850 00:26:02.765191
5851 00:26:02.765274 TX Vref Scan disable
5852 00:26:02.768486 == TX Byte 0 ==
5853 00:26:02.771283 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5854 00:26:02.774856 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5855 00:26:02.777876 == TX Byte 1 ==
5856 00:26:02.781246 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5857 00:26:02.788178 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5858 00:26:02.788273 ==
5859 00:26:02.791141 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 00:26:02.794620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 00:26:02.794716 ==
5862 00:26:02.794809
5863 00:26:02.794896
5864 00:26:02.798059 TX Vref Scan disable
5865 00:26:02.798150 == TX Byte 0 ==
5866 00:26:02.804480 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5867 00:26:02.807773 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5868 00:26:02.807922 == TX Byte 1 ==
5869 00:26:02.814233 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5870 00:26:02.817397 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5871 00:26:02.817516
5872 00:26:02.817617 [DATLAT]
5873 00:26:02.820922 Freq=933, CH1 RK1
5874 00:26:02.821075
5875 00:26:02.821175 DATLAT Default: 0xb
5876 00:26:02.824504 0, 0xFFFF, sum = 0
5877 00:26:02.824617 1, 0xFFFF, sum = 0
5878 00:26:02.827545 2, 0xFFFF, sum = 0
5879 00:26:02.831045 3, 0xFFFF, sum = 0
5880 00:26:02.831167 4, 0xFFFF, sum = 0
5881 00:26:02.833947 5, 0xFFFF, sum = 0
5882 00:26:02.834073 6, 0xFFFF, sum = 0
5883 00:26:02.837484 7, 0xFFFF, sum = 0
5884 00:26:02.837621 8, 0xFFFF, sum = 0
5885 00:26:02.840514 9, 0xFFFF, sum = 0
5886 00:26:02.840615 10, 0x0, sum = 1
5887 00:26:02.844081 11, 0x0, sum = 2
5888 00:26:02.844184 12, 0x0, sum = 3
5889 00:26:02.847591 13, 0x0, sum = 4
5890 00:26:02.847689 best_step = 11
5891 00:26:02.847772
5892 00:26:02.847851 ==
5893 00:26:02.850751 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 00:26:02.853942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 00:26:02.854036 ==
5896 00:26:02.857317 RX Vref Scan: 0
5897 00:26:02.857421
5898 00:26:02.860815 RX Vref 0 -> 0, step: 1
5899 00:26:02.860966
5900 00:26:02.861068 RX Delay -69 -> 252, step: 4
5901 00:26:02.868511 iDelay=203, Bit 0, Center 94 (-5 ~ 194) 200
5902 00:26:02.871980 iDelay=203, Bit 1, Center 86 (-5 ~ 178) 184
5903 00:26:02.875458 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5904 00:26:02.878416 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5905 00:26:02.881870 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5906 00:26:02.888292 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5907 00:26:02.891870 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5908 00:26:02.894882 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5909 00:26:02.898475 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5910 00:26:02.901534 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5911 00:26:02.905150 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5912 00:26:02.911840 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5913 00:26:02.915047 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5914 00:26:02.918426 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5915 00:26:02.921527 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5916 00:26:02.925268 iDelay=203, Bit 15, Center 94 (-1 ~ 190) 192
5917 00:26:02.925346 ==
5918 00:26:02.928373 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 00:26:02.934700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 00:26:02.934777 ==
5921 00:26:02.934837 DQS Delay:
5922 00:26:02.938185 DQS0 = 0, DQS1 = 0
5923 00:26:02.938262 DQM Delay:
5924 00:26:02.938321 DQM0 = 91, DQM1 = 89
5925 00:26:02.941868 DQ Delay:
5926 00:26:02.944792 DQ0 =94, DQ1 =86, DQ2 =82, DQ3 =90
5927 00:26:02.948366 DQ4 =90, DQ5 =100, DQ6 =102, DQ7 =90
5928 00:26:02.951348 DQ8 =76, DQ9 =82, DQ10 =92, DQ11 =82
5929 00:26:02.954924 DQ12 =98, DQ13 =98, DQ14 =96, DQ15 =94
5930 00:26:02.955017
5931 00:26:02.955105
5932 00:26:02.961625 [DQSOSCAuto] RK1, (LSB)MR18= 0x1024, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
5933 00:26:02.964736 CH1 RK1: MR19=505, MR18=1024
5934 00:26:02.971697 CH1_RK1: MR19=0x505, MR18=0x1024, DQSOSC=410, MR23=63, INC=64, DEC=42
5935 00:26:02.974413 [RxdqsGatingPostProcess] freq 933
5936 00:26:02.977850 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5937 00:26:02.981273 best DQS0 dly(2T, 0.5T) = (0, 10)
5938 00:26:02.984767 best DQS1 dly(2T, 0.5T) = (0, 10)
5939 00:26:02.988184 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5940 00:26:02.991652 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5941 00:26:02.994510 best DQS0 dly(2T, 0.5T) = (0, 10)
5942 00:26:02.998038 best DQS1 dly(2T, 0.5T) = (0, 10)
5943 00:26:03.000984 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5944 00:26:03.004508 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5945 00:26:03.007553 Pre-setting of DQS Precalculation
5946 00:26:03.011019 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5947 00:26:03.021154 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5948 00:26:03.028019 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5949 00:26:03.028096
5950 00:26:03.028154
5951 00:26:03.031322 [Calibration Summary] 1866 Mbps
5952 00:26:03.031397 CH 0, Rank 0
5953 00:26:03.034410 SW Impedance : PASS
5954 00:26:03.034487 DUTY Scan : NO K
5955 00:26:03.037554 ZQ Calibration : PASS
5956 00:26:03.040838 Jitter Meter : NO K
5957 00:26:03.040915 CBT Training : PASS
5958 00:26:03.044143 Write leveling : PASS
5959 00:26:03.047544 RX DQS gating : PASS
5960 00:26:03.047620 RX DQ/DQS(RDDQC) : PASS
5961 00:26:03.051137 TX DQ/DQS : PASS
5962 00:26:03.053973 RX DATLAT : PASS
5963 00:26:03.054048 RX DQ/DQS(Engine): PASS
5964 00:26:03.057544 TX OE : NO K
5965 00:26:03.057622 All Pass.
5966 00:26:03.057680
5967 00:26:03.061040 CH 0, Rank 1
5968 00:26:03.061117 SW Impedance : PASS
5969 00:26:03.064362 DUTY Scan : NO K
5970 00:26:03.067572 ZQ Calibration : PASS
5971 00:26:03.067648 Jitter Meter : NO K
5972 00:26:03.070834 CBT Training : PASS
5973 00:26:03.074454 Write leveling : PASS
5974 00:26:03.074568 RX DQS gating : PASS
5975 00:26:03.077353 RX DQ/DQS(RDDQC) : PASS
5976 00:26:03.080735 TX DQ/DQS : PASS
5977 00:26:03.080845 RX DATLAT : PASS
5978 00:26:03.084179 RX DQ/DQS(Engine): PASS
5979 00:26:03.084290 TX OE : NO K
5980 00:26:03.087188 All Pass.
5981 00:26:03.087303
5982 00:26:03.087405 CH 1, Rank 0
5983 00:26:03.090836 SW Impedance : PASS
5984 00:26:03.093803 DUTY Scan : NO K
5985 00:26:03.093913 ZQ Calibration : PASS
5986 00:26:03.097258 Jitter Meter : NO K
5987 00:26:03.097369 CBT Training : PASS
5988 00:26:03.100813 Write leveling : PASS
5989 00:26:03.103848 RX DQS gating : PASS
5990 00:26:03.103956 RX DQ/DQS(RDDQC) : PASS
5991 00:26:03.107402 TX DQ/DQS : PASS
5992 00:26:03.110417 RX DATLAT : PASS
5993 00:26:03.110527 RX DQ/DQS(Engine): PASS
5994 00:26:03.114019 TX OE : NO K
5995 00:26:03.114129 All Pass.
5996 00:26:03.114237
5997 00:26:03.116901 CH 1, Rank 1
5998 00:26:03.117011 SW Impedance : PASS
5999 00:26:03.120333 DUTY Scan : NO K
6000 00:26:03.123649 ZQ Calibration : PASS
6001 00:26:03.123758 Jitter Meter : NO K
6002 00:26:03.127249 CBT Training : PASS
6003 00:26:03.130091 Write leveling : PASS
6004 00:26:03.130204 RX DQS gating : PASS
6005 00:26:03.133750 RX DQ/DQS(RDDQC) : PASS
6006 00:26:03.137256 TX DQ/DQS : PASS
6007 00:26:03.137375 RX DATLAT : PASS
6008 00:26:03.140014 RX DQ/DQS(Engine): PASS
6009 00:26:03.143348 TX OE : NO K
6010 00:26:03.143457 All Pass.
6011 00:26:03.143591
6012 00:26:03.143691 DramC Write-DBI off
6013 00:26:03.146587 PER_BANK_REFRESH: Hybrid Mode
6014 00:26:03.150327 TX_TRACKING: ON
6015 00:26:03.156885 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6016 00:26:03.160148 [FAST_K] Save calibration result to emmc
6017 00:26:03.166554 dramc_set_vcore_voltage set vcore to 650000
6018 00:26:03.166672 Read voltage for 400, 6
6019 00:26:03.169910 Vio18 = 0
6020 00:26:03.170019 Vcore = 650000
6021 00:26:03.170128 Vdram = 0
6022 00:26:03.173324 Vddq = 0
6023 00:26:03.173436 Vmddr = 0
6024 00:26:03.176762 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6025 00:26:03.183129 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6026 00:26:03.186596 MEM_TYPE=3, freq_sel=20
6027 00:26:03.186704 sv_algorithm_assistance_LP4_800
6028 00:26:03.193484 ============ PULL DRAM RESETB DOWN ============
6029 00:26:03.196456 ========== PULL DRAM RESETB DOWN end =========
6030 00:26:03.200009 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6031 00:26:03.203487 ===================================
6032 00:26:03.206482 LPDDR4 DRAM CONFIGURATION
6033 00:26:03.210018 ===================================
6034 00:26:03.213038 EX_ROW_EN[0] = 0x0
6035 00:26:03.213149 EX_ROW_EN[1] = 0x0
6036 00:26:03.216577 LP4Y_EN = 0x0
6037 00:26:03.216691 WORK_FSP = 0x0
6038 00:26:03.219584 WL = 0x2
6039 00:26:03.219692 RL = 0x2
6040 00:26:03.223097 BL = 0x2
6041 00:26:03.223215 RPST = 0x0
6042 00:26:03.226512 RD_PRE = 0x0
6043 00:26:03.226621 WR_PRE = 0x1
6044 00:26:03.229488 WR_PST = 0x0
6045 00:26:03.229604 DBI_WR = 0x0
6046 00:26:03.233016 DBI_RD = 0x0
6047 00:26:03.235985 OTF = 0x1
6048 00:26:03.239627 ===================================
6049 00:26:03.242633 ===================================
6050 00:26:03.242733 ANA top config
6051 00:26:03.246043 ===================================
6052 00:26:03.249416 DLL_ASYNC_EN = 0
6053 00:26:03.249493 ALL_SLAVE_EN = 1
6054 00:26:03.252955 NEW_RANK_MODE = 1
6055 00:26:03.256338 DLL_IDLE_MODE = 1
6056 00:26:03.259721 LP45_APHY_COMB_EN = 1
6057 00:26:03.262491 TX_ODT_DIS = 1
6058 00:26:03.262568 NEW_8X_MODE = 1
6059 00:26:03.266299 ===================================
6060 00:26:03.269071 ===================================
6061 00:26:03.272452 data_rate = 800
6062 00:26:03.275820 CKR = 1
6063 00:26:03.279401 DQ_P2S_RATIO = 4
6064 00:26:03.282738 ===================================
6065 00:26:03.285908 CA_P2S_RATIO = 4
6066 00:26:03.289278 DQ_CA_OPEN = 0
6067 00:26:03.289414 DQ_SEMI_OPEN = 1
6068 00:26:03.292742 CA_SEMI_OPEN = 1
6069 00:26:03.295630 CA_FULL_RATE = 0
6070 00:26:03.299071 DQ_CKDIV4_EN = 0
6071 00:26:03.302553 CA_CKDIV4_EN = 1
6072 00:26:03.305642 CA_PREDIV_EN = 0
6073 00:26:03.305758 PH8_DLY = 0
6074 00:26:03.309072 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6075 00:26:03.312626 DQ_AAMCK_DIV = 0
6076 00:26:03.315745 CA_AAMCK_DIV = 0
6077 00:26:03.319093 CA_ADMCK_DIV = 4
6078 00:26:03.322018 DQ_TRACK_CA_EN = 0
6079 00:26:03.322137 CA_PICK = 800
6080 00:26:03.325611 CA_MCKIO = 400
6081 00:26:03.328429 MCKIO_SEMI = 400
6082 00:26:03.331786 PLL_FREQ = 3016
6083 00:26:03.335320 DQ_UI_PI_RATIO = 32
6084 00:26:03.338996 CA_UI_PI_RATIO = 32
6085 00:26:03.342054 ===================================
6086 00:26:03.345558 ===================================
6087 00:26:03.348551 memory_type:LPDDR4
6088 00:26:03.348685 GP_NUM : 10
6089 00:26:03.352014 SRAM_EN : 1
6090 00:26:03.352133 MD32_EN : 0
6091 00:26:03.355463 ===================================
6092 00:26:03.358373 [ANA_INIT] >>>>>>>>>>>>>>
6093 00:26:03.361834 <<<<<< [CONFIGURE PHASE]: ANA_TX
6094 00:26:03.365394 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6095 00:26:03.368672 ===================================
6096 00:26:03.371879 data_rate = 800,PCW = 0X7400
6097 00:26:03.375177 ===================================
6098 00:26:03.378470 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6099 00:26:03.385075 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6100 00:26:03.395003 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6101 00:26:03.398196 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6102 00:26:03.401734 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6103 00:26:03.405147 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6104 00:26:03.408042 [ANA_INIT] flow start
6105 00:26:03.411593 [ANA_INIT] PLL >>>>>>>>
6106 00:26:03.411695 [ANA_INIT] PLL <<<<<<<<
6107 00:26:03.415037 [ANA_INIT] MIDPI >>>>>>>>
6108 00:26:03.418043 [ANA_INIT] MIDPI <<<<<<<<
6109 00:26:03.421510 [ANA_INIT] DLL >>>>>>>>
6110 00:26:03.421586 [ANA_INIT] flow end
6111 00:26:03.424468 ============ LP4 DIFF to SE enter ============
6112 00:26:03.431424 ============ LP4 DIFF to SE exit ============
6113 00:26:03.431501 [ANA_INIT] <<<<<<<<<<<<<
6114 00:26:03.434844 [Flow] Enable top DCM control >>>>>
6115 00:26:03.437882 [Flow] Enable top DCM control <<<<<
6116 00:26:03.441444 Enable DLL master slave shuffle
6117 00:26:03.448015 ==============================================================
6118 00:26:03.448092 Gating Mode config
6119 00:26:03.454545 ==============================================================
6120 00:26:03.457970 Config description:
6121 00:26:03.467816 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6122 00:26:03.474243 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6123 00:26:03.477585 SELPH_MODE 0: By rank 1: By Phase
6124 00:26:03.484431 ==============================================================
6125 00:26:03.487617 GAT_TRACK_EN = 0
6126 00:26:03.490885 RX_GATING_MODE = 2
6127 00:26:03.494449 RX_GATING_TRACK_MODE = 2
6128 00:26:03.494526 SELPH_MODE = 1
6129 00:26:03.497400 PICG_EARLY_EN = 1
6130 00:26:03.500620 VALID_LAT_VALUE = 1
6131 00:26:03.507722 ==============================================================
6132 00:26:03.510864 Enter into Gating configuration >>>>
6133 00:26:03.513841 Exit from Gating configuration <<<<
6134 00:26:03.517303 Enter into DVFS_PRE_config >>>>>
6135 00:26:03.527380 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6136 00:26:03.530376 Exit from DVFS_PRE_config <<<<<
6137 00:26:03.533917 Enter into PICG configuration >>>>
6138 00:26:03.537391 Exit from PICG configuration <<<<
6139 00:26:03.540804 [RX_INPUT] configuration >>>>>
6140 00:26:03.543691 [RX_INPUT] configuration <<<<<
6141 00:26:03.547320 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6142 00:26:03.553703 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6143 00:26:03.560114 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6144 00:26:03.566983 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6145 00:26:03.573275 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6146 00:26:03.576795 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6147 00:26:03.583532 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6148 00:26:03.586472 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6149 00:26:03.589897 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6150 00:26:03.593343 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6151 00:26:03.599999 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6152 00:26:03.603523 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6153 00:26:03.606508 ===================================
6154 00:26:03.609948 LPDDR4 DRAM CONFIGURATION
6155 00:26:03.613268 ===================================
6156 00:26:03.613491 EX_ROW_EN[0] = 0x0
6157 00:26:03.616494 EX_ROW_EN[1] = 0x0
6158 00:26:03.616609 LP4Y_EN = 0x0
6159 00:26:03.619820 WORK_FSP = 0x0
6160 00:26:03.619931 WL = 0x2
6161 00:26:03.622921 RL = 0x2
6162 00:26:03.623040 BL = 0x2
6163 00:26:03.626281 RPST = 0x0
6164 00:26:03.629372 RD_PRE = 0x0
6165 00:26:03.629491 WR_PRE = 0x1
6166 00:26:03.632874 WR_PST = 0x0
6167 00:26:03.632990 DBI_WR = 0x0
6168 00:26:03.636456 DBI_RD = 0x0
6169 00:26:03.636574 OTF = 0x1
6170 00:26:03.639356 ===================================
6171 00:26:03.642739 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6172 00:26:03.649349 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6173 00:26:03.653000 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6174 00:26:03.655986 ===================================
6175 00:26:03.659669 LPDDR4 DRAM CONFIGURATION
6176 00:26:03.662581 ===================================
6177 00:26:03.662699 EX_ROW_EN[0] = 0x10
6178 00:26:03.665992 EX_ROW_EN[1] = 0x0
6179 00:26:03.666102 LP4Y_EN = 0x0
6180 00:26:03.669644 WORK_FSP = 0x0
6181 00:26:03.669764 WL = 0x2
6182 00:26:03.672550 RL = 0x2
6183 00:26:03.672702 BL = 0x2
6184 00:26:03.675967 RPST = 0x0
6185 00:26:03.679445 RD_PRE = 0x0
6186 00:26:03.679556 WR_PRE = 0x1
6187 00:26:03.682409 WR_PST = 0x0
6188 00:26:03.682531 DBI_WR = 0x0
6189 00:26:03.685828 DBI_RD = 0x0
6190 00:26:03.685934 OTF = 0x1
6191 00:26:03.689451 ===================================
6192 00:26:03.695938 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6193 00:26:03.699390 nWR fixed to 30
6194 00:26:03.702801 [ModeRegInit_LP4] CH0 RK0
6195 00:26:03.702911 [ModeRegInit_LP4] CH0 RK1
6196 00:26:03.706074 [ModeRegInit_LP4] CH1 RK0
6197 00:26:03.709541 [ModeRegInit_LP4] CH1 RK1
6198 00:26:03.709637 match AC timing 19
6199 00:26:03.716409 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6200 00:26:03.719410 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6201 00:26:03.723043 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6202 00:26:03.729308 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6203 00:26:03.732613 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6204 00:26:03.732727 ==
6205 00:26:03.735973 Dram Type= 6, Freq= 0, CH_0, rank 0
6206 00:26:03.739399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6207 00:26:03.739466 ==
6208 00:26:03.746244 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6209 00:26:03.752758 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6210 00:26:03.755740 [CA 0] Center 36 (8~64) winsize 57
6211 00:26:03.759326 [CA 1] Center 36 (8~64) winsize 57
6212 00:26:03.762357 [CA 2] Center 36 (8~64) winsize 57
6213 00:26:03.765869 [CA 3] Center 36 (8~64) winsize 57
6214 00:26:03.765935 [CA 4] Center 36 (8~64) winsize 57
6215 00:26:03.769341 [CA 5] Center 36 (8~64) winsize 57
6216 00:26:03.769406
6217 00:26:03.775616 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6218 00:26:03.775685
6219 00:26:03.778998 [CATrainingPosCal] consider 1 rank data
6220 00:26:03.782377 u2DelayCellTimex100 = 270/100 ps
6221 00:26:03.785798 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 00:26:03.789230 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 00:26:03.792628 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 00:26:03.795613 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 00:26:03.799233 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 00:26:03.802103 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 00:26:03.802213
6228 00:26:03.805672 CA PerBit enable=1, Macro0, CA PI delay=36
6229 00:26:03.805782
6230 00:26:03.808985 [CBTSetCACLKResult] CA Dly = 36
6231 00:26:03.812417 CS Dly: 1 (0~32)
6232 00:26:03.812521 ==
6233 00:26:03.815804 Dram Type= 6, Freq= 0, CH_0, rank 1
6234 00:26:03.819067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6235 00:26:03.819180 ==
6236 00:26:03.825492 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6237 00:26:03.831851 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6238 00:26:03.831974 [CA 0] Center 36 (8~64) winsize 57
6239 00:26:03.835416 [CA 1] Center 36 (8~64) winsize 57
6240 00:26:03.838905 [CA 2] Center 36 (8~64) winsize 57
6241 00:26:03.841757 [CA 3] Center 36 (8~64) winsize 57
6242 00:26:03.845106 [CA 4] Center 36 (8~64) winsize 57
6243 00:26:03.848426 [CA 5] Center 36 (8~64) winsize 57
6244 00:26:03.848545
6245 00:26:03.851779 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6246 00:26:03.851886
6247 00:26:03.855400 [CATrainingPosCal] consider 2 rank data
6248 00:26:03.858378 u2DelayCellTimex100 = 270/100 ps
6249 00:26:03.861890 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 00:26:03.868465 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 00:26:03.871906 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 00:26:03.874868 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 00:26:03.878347 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 00:26:03.881933 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 00:26:03.882011
6256 00:26:03.884795 CA PerBit enable=1, Macro0, CA PI delay=36
6257 00:26:03.884871
6258 00:26:03.888144 [CBTSetCACLKResult] CA Dly = 36
6259 00:26:03.891489 CS Dly: 1 (0~32)
6260 00:26:03.891583
6261 00:26:03.894861 ----->DramcWriteLeveling(PI) begin...
6262 00:26:03.894983 ==
6263 00:26:03.898501 Dram Type= 6, Freq= 0, CH_0, rank 0
6264 00:26:03.901473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 00:26:03.901624 ==
6266 00:26:03.904931 Write leveling (Byte 0): 40 => 8
6267 00:26:03.907903 Write leveling (Byte 1): 40 => 8
6268 00:26:03.911293 DramcWriteLeveling(PI) end<-----
6269 00:26:03.911387
6270 00:26:03.911477 ==
6271 00:26:03.914731 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 00:26:03.917632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 00:26:03.917778 ==
6274 00:26:03.921079 [Gating] SW mode calibration
6275 00:26:03.927890 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6276 00:26:03.934169 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6277 00:26:03.937643 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6278 00:26:03.941172 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6279 00:26:03.947506 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6280 00:26:03.950917 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 00:26:03.954475 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 00:26:03.960900 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 00:26:03.964400 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 00:26:03.968001 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 00:26:03.974614 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6286 00:26:03.974691 Total UI for P1: 0, mck2ui 16
6287 00:26:03.977683 best dqsien dly found for B0: ( 0, 14, 24)
6288 00:26:03.981249 Total UI for P1: 0, mck2ui 16
6289 00:26:03.984582 best dqsien dly found for B1: ( 0, 14, 24)
6290 00:26:03.990962 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6291 00:26:03.994507 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6292 00:26:03.994584
6293 00:26:03.997874 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6294 00:26:04.001077 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6295 00:26:04.004233 [Gating] SW calibration Done
6296 00:26:04.004352 ==
6297 00:26:04.007877 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 00:26:04.010777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 00:26:04.010887 ==
6300 00:26:04.014269 RX Vref Scan: 0
6301 00:26:04.014383
6302 00:26:04.014494 RX Vref 0 -> 0, step: 1
6303 00:26:04.014591
6304 00:26:04.017691 RX Delay -410 -> 252, step: 16
6305 00:26:04.021212 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6306 00:26:04.027714 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6307 00:26:04.030761 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6308 00:26:04.034086 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6309 00:26:04.040476 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6310 00:26:04.044280 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6311 00:26:04.047176 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6312 00:26:04.050586 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6313 00:26:04.057688 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6314 00:26:04.060251 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6315 00:26:04.064049 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6316 00:26:04.066989 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6317 00:26:04.073976 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6318 00:26:04.076941 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6319 00:26:04.080339 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6320 00:26:04.083990 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6321 00:26:04.086965 ==
6322 00:26:04.087080 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 00:26:04.093388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 00:26:04.093502 ==
6325 00:26:04.093615 DQS Delay:
6326 00:26:04.097033 DQS0 = 59, DQS1 = 59
6327 00:26:04.097141 DQM Delay:
6328 00:26:04.099975 DQM0 = 18, DQM1 = 10
6329 00:26:04.100083 DQ Delay:
6330 00:26:04.103542 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6331 00:26:04.106869 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6332 00:26:04.110206 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6333 00:26:04.113644 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6334 00:26:04.113753
6335 00:26:04.113812
6336 00:26:04.113866 ==
6337 00:26:04.117133 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 00:26:04.120470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 00:26:04.120547 ==
6340 00:26:04.120605
6341 00:26:04.120682
6342 00:26:04.123367 TX Vref Scan disable
6343 00:26:04.123443 == TX Byte 0 ==
6344 00:26:04.129807 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6345 00:26:04.133430 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6346 00:26:04.133506 == TX Byte 1 ==
6347 00:26:04.139974 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 00:26:04.143335 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 00:26:04.143409 ==
6350 00:26:04.146642 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 00:26:04.150020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 00:26:04.150132 ==
6353 00:26:04.150232
6354 00:26:04.150331
6355 00:26:04.153218 TX Vref Scan disable
6356 00:26:04.153329 == TX Byte 0 ==
6357 00:26:04.159690 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6358 00:26:04.163272 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6359 00:26:04.163349 == TX Byte 1 ==
6360 00:26:04.169922 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6361 00:26:04.173278 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6362 00:26:04.173382
6363 00:26:04.173475 [DATLAT]
6364 00:26:04.176279 Freq=400, CH0 RK0
6365 00:26:04.176379
6366 00:26:04.176464 DATLAT Default: 0xf
6367 00:26:04.179848 0, 0xFFFF, sum = 0
6368 00:26:04.179925 1, 0xFFFF, sum = 0
6369 00:26:04.183339 2, 0xFFFF, sum = 0
6370 00:26:04.183432 3, 0xFFFF, sum = 0
6371 00:26:04.186352 4, 0xFFFF, sum = 0
6372 00:26:04.186444 5, 0xFFFF, sum = 0
6373 00:26:04.189770 6, 0xFFFF, sum = 0
6374 00:26:04.189847 7, 0xFFFF, sum = 0
6375 00:26:04.193214 8, 0xFFFF, sum = 0
6376 00:26:04.196635 9, 0xFFFF, sum = 0
6377 00:26:04.196737 10, 0xFFFF, sum = 0
6378 00:26:04.199563 11, 0xFFFF, sum = 0
6379 00:26:04.199640 12, 0xFFFF, sum = 0
6380 00:26:04.203127 13, 0x0, sum = 1
6381 00:26:04.203205 14, 0x0, sum = 2
6382 00:26:04.206122 15, 0x0, sum = 3
6383 00:26:04.206202 16, 0x0, sum = 4
6384 00:26:04.206264 best_step = 14
6385 00:26:04.206321
6386 00:26:04.209561 ==
6387 00:26:04.213092 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 00:26:04.216420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 00:26:04.216499 ==
6390 00:26:04.216560 RX Vref Scan: 1
6391 00:26:04.216617
6392 00:26:04.219414 RX Vref 0 -> 0, step: 1
6393 00:26:04.219492
6394 00:26:04.222668 RX Delay -359 -> 252, step: 8
6395 00:26:04.222746
6396 00:26:04.226183 Set Vref, RX VrefLevel [Byte0]: 62
6397 00:26:04.229083 [Byte1]: 49
6398 00:26:04.233398
6399 00:26:04.233476 Final RX Vref Byte 0 = 62 to rank0
6400 00:26:04.236852 Final RX Vref Byte 1 = 49 to rank0
6401 00:26:04.239888 Final RX Vref Byte 0 = 62 to rank1
6402 00:26:04.243384 Final RX Vref Byte 1 = 49 to rank1==
6403 00:26:04.246301 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 00:26:04.253178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 00:26:04.253261 ==
6406 00:26:04.253327 DQS Delay:
6407 00:26:04.256149 DQS0 = 60, DQS1 = 68
6408 00:26:04.256226 DQM Delay:
6409 00:26:04.256319 DQM0 = 13, DQM1 = 13
6410 00:26:04.259606 DQ Delay:
6411 00:26:04.263107 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6412 00:26:04.266392 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6413 00:26:04.266482 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6414 00:26:04.273140 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6415 00:26:04.273218
6416 00:26:04.273278
6417 00:26:04.279273 [DQSOSCAuto] RK0, (LSB)MR18= 0x8381, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6418 00:26:04.282864 CH0 RK0: MR19=C0C, MR18=8381
6419 00:26:04.289258 CH0_RK0: MR19=0xC0C, MR18=0x8381, DQSOSC=393, MR23=63, INC=382, DEC=254
6420 00:26:04.289337 ==
6421 00:26:04.292890 Dram Type= 6, Freq= 0, CH_0, rank 1
6422 00:26:04.296284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 00:26:04.296361 ==
6424 00:26:04.299062 [Gating] SW mode calibration
6425 00:26:04.306238 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6426 00:26:04.312778 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6427 00:26:04.315777 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6428 00:26:04.319271 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6429 00:26:04.326112 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6430 00:26:04.329442 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 00:26:04.332686 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 00:26:04.339027 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 00:26:04.342576 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 00:26:04.345670 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 00:26:04.352607 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6436 00:26:04.352710 Total UI for P1: 0, mck2ui 16
6437 00:26:04.358965 best dqsien dly found for B0: ( 0, 14, 24)
6438 00:26:04.359041 Total UI for P1: 0, mck2ui 16
6439 00:26:04.365749 best dqsien dly found for B1: ( 0, 14, 24)
6440 00:26:04.368814 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6441 00:26:04.372149 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6442 00:26:04.372225
6443 00:26:04.375497 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6444 00:26:04.378594 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6445 00:26:04.382109 [Gating] SW calibration Done
6446 00:26:04.382185 ==
6447 00:26:04.385110 Dram Type= 6, Freq= 0, CH_0, rank 1
6448 00:26:04.388768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 00:26:04.388845 ==
6450 00:26:04.392009 RX Vref Scan: 0
6451 00:26:04.392085
6452 00:26:04.392144 RX Vref 0 -> 0, step: 1
6453 00:26:04.392199
6454 00:26:04.395509 RX Delay -410 -> 252, step: 16
6455 00:26:04.401956 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6456 00:26:04.405397 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6457 00:26:04.408405 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6458 00:26:04.412010 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6459 00:26:04.418636 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6460 00:26:04.421601 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6461 00:26:04.424883 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6462 00:26:04.428454 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6463 00:26:04.434832 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6464 00:26:04.438234 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6465 00:26:04.441478 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6466 00:26:04.445383 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6467 00:26:04.451389 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6468 00:26:04.455018 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6469 00:26:04.458415 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6470 00:26:04.464846 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6471 00:26:04.464918 ==
6472 00:26:04.468231 Dram Type= 6, Freq= 0, CH_0, rank 1
6473 00:26:04.471751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 00:26:04.471821 ==
6475 00:26:04.471884 DQS Delay:
6476 00:26:04.474724 DQS0 = 59, DQS1 = 59
6477 00:26:04.474791 DQM Delay:
6478 00:26:04.478291 DQM0 = 17, DQM1 = 10
6479 00:26:04.478355 DQ Delay:
6480 00:26:04.481639 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6481 00:26:04.484611 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6482 00:26:04.488109 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6483 00:26:04.491373 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6484 00:26:04.491467
6485 00:26:04.491558
6486 00:26:04.491628 ==
6487 00:26:04.494463 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 00:26:04.498025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 00:26:04.498101 ==
6490 00:26:04.498160
6491 00:26:04.498215
6492 00:26:04.501241 TX Vref Scan disable
6493 00:26:04.504372 == TX Byte 0 ==
6494 00:26:04.507610 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6495 00:26:04.511166 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6496 00:26:04.511243 == TX Byte 1 ==
6497 00:26:04.517807 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6498 00:26:04.521349 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6499 00:26:04.521442 ==
6500 00:26:04.524337 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 00:26:04.527752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 00:26:04.527847 ==
6503 00:26:04.527909
6504 00:26:04.527961
6505 00:26:04.531159 TX Vref Scan disable
6506 00:26:04.534795 == TX Byte 0 ==
6507 00:26:04.537784 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6508 00:26:04.541325 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6509 00:26:04.541420 == TX Byte 1 ==
6510 00:26:04.547508 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6511 00:26:04.550814 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6512 00:26:04.550917
6513 00:26:04.550999 [DATLAT]
6514 00:26:04.554228 Freq=400, CH0 RK1
6515 00:26:04.554323
6516 00:26:04.554406 DATLAT Default: 0xe
6517 00:26:04.557722 0, 0xFFFF, sum = 0
6518 00:26:04.557789 1, 0xFFFF, sum = 0
6519 00:26:04.561176 2, 0xFFFF, sum = 0
6520 00:26:04.561259 3, 0xFFFF, sum = 0
6521 00:26:04.563985 4, 0xFFFF, sum = 0
6522 00:26:04.567598 5, 0xFFFF, sum = 0
6523 00:26:04.567705 6, 0xFFFF, sum = 0
6524 00:26:04.571134 7, 0xFFFF, sum = 0
6525 00:26:04.571199 8, 0xFFFF, sum = 0
6526 00:26:04.573961 9, 0xFFFF, sum = 0
6527 00:26:04.574027 10, 0xFFFF, sum = 0
6528 00:26:04.577549 11, 0xFFFF, sum = 0
6529 00:26:04.577612 12, 0xFFFF, sum = 0
6530 00:26:04.581014 13, 0x0, sum = 1
6531 00:26:04.581079 14, 0x0, sum = 2
6532 00:26:04.583934 15, 0x0, sum = 3
6533 00:26:04.583999 16, 0x0, sum = 4
6534 00:26:04.587343 best_step = 14
6535 00:26:04.587440
6536 00:26:04.587521 ==
6537 00:26:04.590735 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 00:26:04.593843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 00:26:04.593920 ==
6540 00:26:04.593991 RX Vref Scan: 0
6541 00:26:04.597404
6542 00:26:04.597481 RX Vref 0 -> 0, step: 1
6543 00:26:04.597536
6544 00:26:04.600769 RX Delay -359 -> 252, step: 8
6545 00:26:04.607912 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6546 00:26:04.611656 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6547 00:26:04.614856 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6548 00:26:04.621409 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6549 00:26:04.624466 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6550 00:26:04.627963 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6551 00:26:04.630872 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6552 00:26:04.637881 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6553 00:26:04.640878 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6554 00:26:04.644381 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6555 00:26:04.647423 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6556 00:26:04.654365 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6557 00:26:04.657788 iDelay=217, Bit 12, Center -52 (-303 ~ 200) 504
6558 00:26:04.661100 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6559 00:26:04.664551 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6560 00:26:04.670981 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6561 00:26:04.671049 ==
6562 00:26:04.673977 Dram Type= 6, Freq= 0, CH_0, rank 1
6563 00:26:04.677402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6564 00:26:04.677471 ==
6565 00:26:04.677527 DQS Delay:
6566 00:26:04.680926 DQS0 = 60, DQS1 = 72
6567 00:26:04.680989 DQM Delay:
6568 00:26:04.684043 DQM0 = 11, DQM1 = 17
6569 00:26:04.684138 DQ Delay:
6570 00:26:04.687538 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6571 00:26:04.690671 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6572 00:26:04.694138 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6573 00:26:04.697650 DQ12 =20, DQ13 =28, DQ14 =28, DQ15 =24
6574 00:26:04.697726
6575 00:26:04.697785
6576 00:26:04.704083 [DQSOSCAuto] RK1, (LSB)MR18= 0xce83, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6577 00:26:04.707545 CH0 RK1: MR19=C0C, MR18=CE83
6578 00:26:04.713822 CH0_RK1: MR19=0xC0C, MR18=0xCE83, DQSOSC=384, MR23=63, INC=400, DEC=267
6579 00:26:04.717378 [RxdqsGatingPostProcess] freq 400
6580 00:26:04.723884 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6581 00:26:04.727059 best DQS0 dly(2T, 0.5T) = (0, 10)
6582 00:26:04.727137 best DQS1 dly(2T, 0.5T) = (0, 10)
6583 00:26:04.730309 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6584 00:26:04.733903 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6585 00:26:04.736799 best DQS0 dly(2T, 0.5T) = (0, 10)
6586 00:26:04.740396 best DQS1 dly(2T, 0.5T) = (0, 10)
6587 00:26:04.743891 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6588 00:26:04.746792 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6589 00:26:04.750472 Pre-setting of DQS Precalculation
6590 00:26:04.756752 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6591 00:26:04.756831 ==
6592 00:26:04.760287 Dram Type= 6, Freq= 0, CH_1, rank 0
6593 00:26:04.763750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 00:26:04.763829 ==
6595 00:26:04.769990 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6596 00:26:04.776751 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6597 00:26:04.776831 [CA 0] Center 36 (8~64) winsize 57
6598 00:26:04.780180 [CA 1] Center 36 (8~64) winsize 57
6599 00:26:04.783071 [CA 2] Center 36 (8~64) winsize 57
6600 00:26:04.786629 [CA 3] Center 36 (8~64) winsize 57
6601 00:26:04.789579 [CA 4] Center 36 (8~64) winsize 57
6602 00:26:04.793152 [CA 5] Center 36 (8~64) winsize 57
6603 00:26:04.793231
6604 00:26:04.796533 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6605 00:26:04.796612
6606 00:26:04.800096 [CATrainingPosCal] consider 1 rank data
6607 00:26:04.803074 u2DelayCellTimex100 = 270/100 ps
6608 00:26:04.806624 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 00:26:04.813032 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 00:26:04.816372 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 00:26:04.819953 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 00:26:04.822923 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 00:26:04.826503 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 00:26:04.826579
6615 00:26:04.829921 CA PerBit enable=1, Macro0, CA PI delay=36
6616 00:26:04.829997
6617 00:26:04.833292 [CBTSetCACLKResult] CA Dly = 36
6618 00:26:04.833368 CS Dly: 1 (0~32)
6619 00:26:04.836125 ==
6620 00:26:04.839502 Dram Type= 6, Freq= 0, CH_1, rank 1
6621 00:26:04.843079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 00:26:04.843155 ==
6623 00:26:04.846067 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6624 00:26:04.853008 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6625 00:26:04.855878 [CA 0] Center 36 (8~64) winsize 57
6626 00:26:04.859366 [CA 1] Center 36 (8~64) winsize 57
6627 00:26:04.862852 [CA 2] Center 36 (8~64) winsize 57
6628 00:26:04.865794 [CA 3] Center 36 (8~64) winsize 57
6629 00:26:04.869343 [CA 4] Center 36 (8~64) winsize 57
6630 00:26:04.872800 [CA 5] Center 36 (8~64) winsize 57
6631 00:26:04.872877
6632 00:26:04.876281 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6633 00:26:04.876357
6634 00:26:04.879415 [CATrainingPosCal] consider 2 rank data
6635 00:26:04.882316 u2DelayCellTimex100 = 270/100 ps
6636 00:26:04.885693 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 00:26:04.889242 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 00:26:04.892308 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 00:26:04.898722 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 00:26:04.902518 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 00:26:04.905418 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 00:26:04.905510
6643 00:26:04.908936 CA PerBit enable=1, Macro0, CA PI delay=36
6644 00:26:04.909004
6645 00:26:04.912546 [CBTSetCACLKResult] CA Dly = 36
6646 00:26:04.912655 CS Dly: 1 (0~32)
6647 00:26:04.912731
6648 00:26:04.915366 ----->DramcWriteLeveling(PI) begin...
6649 00:26:04.915428 ==
6650 00:26:04.918738 Dram Type= 6, Freq= 0, CH_1, rank 0
6651 00:26:04.925759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 00:26:04.925828 ==
6653 00:26:04.928579 Write leveling (Byte 0): 40 => 8
6654 00:26:04.932124 Write leveling (Byte 1): 40 => 8
6655 00:26:04.932189 DramcWriteLeveling(PI) end<-----
6656 00:26:04.935149
6657 00:26:04.935211 ==
6658 00:26:04.938448 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 00:26:04.941905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 00:26:04.941971 ==
6661 00:26:04.945515 [Gating] SW mode calibration
6662 00:26:04.952027 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6663 00:26:04.954885 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6664 00:26:04.961809 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6665 00:26:04.965280 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6666 00:26:04.968204 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6667 00:26:04.975250 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 00:26:04.978161 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 00:26:04.981591 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 00:26:04.988091 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 00:26:04.991332 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 00:26:04.994777 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6673 00:26:04.998426 Total UI for P1: 0, mck2ui 16
6674 00:26:05.001377 best dqsien dly found for B0: ( 0, 14, 24)
6675 00:26:05.004908 Total UI for P1: 0, mck2ui 16
6676 00:26:05.008281 best dqsien dly found for B1: ( 0, 14, 24)
6677 00:26:05.011266 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6678 00:26:05.017715 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6679 00:26:05.017784
6680 00:26:05.021194 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6681 00:26:05.024550 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6682 00:26:05.028080 [Gating] SW calibration Done
6683 00:26:05.028151 ==
6684 00:26:05.031155 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 00:26:05.034195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 00:26:05.034260 ==
6687 00:26:05.037770 RX Vref Scan: 0
6688 00:26:05.037832
6689 00:26:05.037889 RX Vref 0 -> 0, step: 1
6690 00:26:05.037941
6691 00:26:05.041280 RX Delay -410 -> 252, step: 16
6692 00:26:05.044243 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6693 00:26:05.050753 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6694 00:26:05.054371 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6695 00:26:05.057896 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6696 00:26:05.060864 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6697 00:26:05.067448 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6698 00:26:05.070754 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6699 00:26:05.073965 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6700 00:26:05.080497 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6701 00:26:05.084068 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6702 00:26:05.087129 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6703 00:26:05.090711 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6704 00:26:05.097310 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6705 00:26:05.100531 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6706 00:26:05.104010 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6707 00:26:05.107603 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6708 00:26:05.107680 ==
6709 00:26:05.110458 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 00:26:05.117324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 00:26:05.117401 ==
6712 00:26:05.117461 DQS Delay:
6713 00:26:05.120793 DQS0 = 51, DQS1 = 59
6714 00:26:05.120886 DQM Delay:
6715 00:26:05.123740 DQM0 = 12, DQM1 = 10
6716 00:26:05.123815 DQ Delay:
6717 00:26:05.126958 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6718 00:26:05.130536 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6719 00:26:05.130605 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6720 00:26:05.133962 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6721 00:26:05.134029
6722 00:26:05.137030
6723 00:26:05.137094 ==
6724 00:26:05.140638 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 00:26:05.143606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 00:26:05.143674 ==
6727 00:26:05.143731
6728 00:26:05.143783
6729 00:26:05.147090 TX Vref Scan disable
6730 00:26:05.147180 == TX Byte 0 ==
6731 00:26:05.150748 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6732 00:26:05.157345 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6733 00:26:05.157422 == TX Byte 1 ==
6734 00:26:05.160272 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 00:26:05.166877 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 00:26:05.166953 ==
6737 00:26:05.170483 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 00:26:05.173863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 00:26:05.173962 ==
6740 00:26:05.174048
6741 00:26:05.174129
6742 00:26:05.176626 TX Vref Scan disable
6743 00:26:05.176701 == TX Byte 0 ==
6744 00:26:05.183819 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6745 00:26:05.186762 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6746 00:26:05.186839 == TX Byte 1 ==
6747 00:26:05.190109 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6748 00:26:05.197111 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6749 00:26:05.197217
6750 00:26:05.197303 [DATLAT]
6751 00:26:05.200276 Freq=400, CH1 RK0
6752 00:26:05.200351
6753 00:26:05.200409 DATLAT Default: 0xf
6754 00:26:05.203385 0, 0xFFFF, sum = 0
6755 00:26:05.203462 1, 0xFFFF, sum = 0
6756 00:26:05.206559 2, 0xFFFF, sum = 0
6757 00:26:05.206636 3, 0xFFFF, sum = 0
6758 00:26:05.210111 4, 0xFFFF, sum = 0
6759 00:26:05.210189 5, 0xFFFF, sum = 0
6760 00:26:05.213296 6, 0xFFFF, sum = 0
6761 00:26:05.213373 7, 0xFFFF, sum = 0
6762 00:26:05.216801 8, 0xFFFF, sum = 0
6763 00:26:05.216896 9, 0xFFFF, sum = 0
6764 00:26:05.220005 10, 0xFFFF, sum = 0
6765 00:26:05.220083 11, 0xFFFF, sum = 0
6766 00:26:05.223430 12, 0xFFFF, sum = 0
6767 00:26:05.223509 13, 0x0, sum = 1
6768 00:26:05.227002 14, 0x0, sum = 2
6769 00:26:05.227081 15, 0x0, sum = 3
6770 00:26:05.229873 16, 0x0, sum = 4
6771 00:26:05.229981 best_step = 14
6772 00:26:05.230039
6773 00:26:05.230094 ==
6774 00:26:05.233344 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 00:26:05.239884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 00:26:05.239961 ==
6777 00:26:05.240021 RX Vref Scan: 1
6778 00:26:05.240076
6779 00:26:05.243401 RX Vref 0 -> 0, step: 1
6780 00:26:05.243478
6781 00:26:05.246364 RX Delay -359 -> 252, step: 8
6782 00:26:05.246440
6783 00:26:05.249935 Set Vref, RX VrefLevel [Byte0]: 60
6784 00:26:05.253534 [Byte1]: 50
6785 00:26:05.253611
6786 00:26:05.256483 Final RX Vref Byte 0 = 60 to rank0
6787 00:26:05.260046 Final RX Vref Byte 1 = 50 to rank0
6788 00:26:05.262926 Final RX Vref Byte 0 = 60 to rank1
6789 00:26:05.266500 Final RX Vref Byte 1 = 50 to rank1==
6790 00:26:05.269932 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 00:26:05.273059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 00:26:05.276578 ==
6793 00:26:05.276703 DQS Delay:
6794 00:26:05.276765 DQS0 = 56, DQS1 = 68
6795 00:26:05.280035 DQM Delay:
6796 00:26:05.280128 DQM0 = 12, DQM1 = 15
6797 00:26:05.282842 DQ Delay:
6798 00:26:05.282918 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6799 00:26:05.286388 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6800 00:26:05.290005 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6801 00:26:05.293013 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =24
6802 00:26:05.293089
6803 00:26:05.293148
6804 00:26:05.302937 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c6f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
6805 00:26:05.306397 CH1 RK0: MR19=C0C, MR18=5C6F
6806 00:26:05.312772 CH1_RK0: MR19=0xC0C, MR18=0x5C6F, DQSOSC=395, MR23=63, INC=378, DEC=252
6807 00:26:05.312849 ==
6808 00:26:05.315996 Dram Type= 6, Freq= 0, CH_1, rank 1
6809 00:26:05.319301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 00:26:05.319379 ==
6811 00:26:05.322774 [Gating] SW mode calibration
6812 00:26:05.329303 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6813 00:26:05.332968 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6814 00:26:05.339429 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6815 00:26:05.342503 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6816 00:26:05.346108 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6817 00:26:05.352549 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6818 00:26:05.356113 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 00:26:05.359659 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 00:26:05.366163 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6821 00:26:05.369181 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 00:26:05.372598 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6823 00:26:05.375614 Total UI for P1: 0, mck2ui 16
6824 00:26:05.379264 best dqsien dly found for B0: ( 0, 14, 24)
6825 00:26:05.382713 Total UI for P1: 0, mck2ui 16
6826 00:26:05.386072 best dqsien dly found for B1: ( 0, 14, 24)
6827 00:26:05.389006 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6828 00:26:05.392547 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6829 00:26:05.392624
6830 00:26:05.399063 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6831 00:26:05.402515 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6832 00:26:05.405925 [Gating] SW calibration Done
6833 00:26:05.406003 ==
6834 00:26:05.409040 Dram Type= 6, Freq= 0, CH_1, rank 1
6835 00:26:05.412413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 00:26:05.412492 ==
6837 00:26:05.412553 RX Vref Scan: 0
6838 00:26:05.412609
6839 00:26:05.415900 RX Vref 0 -> 0, step: 1
6840 00:26:05.415977
6841 00:26:05.419189 RX Delay -410 -> 252, step: 16
6842 00:26:05.422114 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6843 00:26:05.428661 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6844 00:26:05.431965 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6845 00:26:05.435824 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6846 00:26:05.439032 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6847 00:26:05.445687 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6848 00:26:05.448941 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6849 00:26:05.452200 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6850 00:26:05.455410 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6851 00:26:05.462019 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6852 00:26:05.465605 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6853 00:26:05.468574 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6854 00:26:05.472178 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6855 00:26:05.478776 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6856 00:26:05.481776 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6857 00:26:05.485277 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6858 00:26:05.485355 ==
6859 00:26:05.488533 Dram Type= 6, Freq= 0, CH_1, rank 1
6860 00:26:05.495451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 00:26:05.495530 ==
6862 00:26:05.495591 DQS Delay:
6863 00:26:05.498432 DQS0 = 59, DQS1 = 59
6864 00:26:05.498532 DQM Delay:
6865 00:26:05.498598 DQM0 = 19, DQM1 = 14
6866 00:26:05.501920 DQ Delay:
6867 00:26:05.505399 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6868 00:26:05.508262 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6869 00:26:05.508353 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6870 00:26:05.511746 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6871 00:26:05.515464
6872 00:26:05.515538
6873 00:26:05.515596 ==
6874 00:26:05.518367 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 00:26:05.521879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 00:26:05.521955 ==
6877 00:26:05.522014
6878 00:26:05.522068
6879 00:26:05.525340 TX Vref Scan disable
6880 00:26:05.525415 == TX Byte 0 ==
6881 00:26:05.528173 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6882 00:26:05.534906 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6883 00:26:05.534982 == TX Byte 1 ==
6884 00:26:05.538177 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6885 00:26:05.544877 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6886 00:26:05.544956 ==
6887 00:26:05.548298 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 00:26:05.551758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 00:26:05.551832 ==
6890 00:26:05.551925
6891 00:26:05.552017
6892 00:26:05.554602 TX Vref Scan disable
6893 00:26:05.554671 == TX Byte 0 ==
6894 00:26:05.561244 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6895 00:26:05.564659 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6896 00:26:05.564748 == TX Byte 1 ==
6897 00:26:05.571233 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6898 00:26:05.574896 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6899 00:26:05.574970
6900 00:26:05.575043 [DATLAT]
6901 00:26:05.577888 Freq=400, CH1 RK1
6902 00:26:05.577953
6903 00:26:05.578032 DATLAT Default: 0xe
6904 00:26:05.581470 0, 0xFFFF, sum = 0
6905 00:26:05.581541 1, 0xFFFF, sum = 0
6906 00:26:05.584450 2, 0xFFFF, sum = 0
6907 00:26:05.584522 3, 0xFFFF, sum = 0
6908 00:26:05.587973 4, 0xFFFF, sum = 0
6909 00:26:05.588043 5, 0xFFFF, sum = 0
6910 00:26:05.590976 6, 0xFFFF, sum = 0
6911 00:26:05.591048 7, 0xFFFF, sum = 0
6912 00:26:05.594454 8, 0xFFFF, sum = 0
6913 00:26:05.594543 9, 0xFFFF, sum = 0
6914 00:26:05.597918 10, 0xFFFF, sum = 0
6915 00:26:05.597992 11, 0xFFFF, sum = 0
6916 00:26:05.600938 12, 0xFFFF, sum = 0
6917 00:26:05.601009 13, 0x0, sum = 1
6918 00:26:05.604461 14, 0x0, sum = 2
6919 00:26:05.604532 15, 0x0, sum = 3
6920 00:26:05.607916 16, 0x0, sum = 4
6921 00:26:05.607987 best_step = 14
6922 00:26:05.608059
6923 00:26:05.608126 ==
6924 00:26:05.610921 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 00:26:05.617859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 00:26:05.617929 ==
6927 00:26:05.618006 RX Vref Scan: 0
6928 00:26:05.618075
6929 00:26:05.620838 RX Vref 0 -> 0, step: 1
6930 00:26:05.620903
6931 00:26:05.624350 RX Delay -359 -> 252, step: 8
6932 00:26:05.630851 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6933 00:26:05.634398 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6934 00:26:05.637479 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6935 00:26:05.643990 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6936 00:26:05.647376 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6937 00:26:05.650419 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6938 00:26:05.653715 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6939 00:26:05.657406 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
6940 00:26:05.663681 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6941 00:26:05.667401 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6942 00:26:05.670332 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6943 00:26:05.677024 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6944 00:26:05.680333 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6945 00:26:05.683705 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6946 00:26:05.687007 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6947 00:26:05.694078 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6948 00:26:05.694151 ==
6949 00:26:05.697017 Dram Type= 6, Freq= 0, CH_1, rank 1
6950 00:26:05.700487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6951 00:26:05.700580 ==
6952 00:26:05.700698 DQS Delay:
6953 00:26:05.703927 DQS0 = 60, DQS1 = 64
6954 00:26:05.703994 DQM Delay:
6955 00:26:05.706937 DQM0 = 13, DQM1 = 10
6956 00:26:05.707024 DQ Delay:
6957 00:26:05.710469 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6958 00:26:05.713859 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =12
6959 00:26:05.717140 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6960 00:26:05.720103 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6961 00:26:05.720170
6962 00:26:05.720241
6963 00:26:05.727199 [DQSOSCAuto] RK1, (LSB)MR18= 0x82b1, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
6964 00:26:05.730153 CH1 RK1: MR19=C0C, MR18=82B1
6965 00:26:05.737139 CH1_RK1: MR19=0xC0C, MR18=0x82B1, DQSOSC=387, MR23=63, INC=394, DEC=262
6966 00:26:05.740218 [RxdqsGatingPostProcess] freq 400
6967 00:26:05.746701 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6968 00:26:05.750087 best DQS0 dly(2T, 0.5T) = (0, 10)
6969 00:26:05.750174 best DQS1 dly(2T, 0.5T) = (0, 10)
6970 00:26:05.753593 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6971 00:26:05.756863 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6972 00:26:05.760087 best DQS0 dly(2T, 0.5T) = (0, 10)
6973 00:26:05.763294 best DQS1 dly(2T, 0.5T) = (0, 10)
6974 00:26:05.766401 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6975 00:26:05.770021 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6976 00:26:05.773594 Pre-setting of DQS Precalculation
6977 00:26:05.779852 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6978 00:26:05.786736 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6979 00:26:05.792970 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6980 00:26:05.793158
6981 00:26:05.793296
6982 00:26:05.796451 [Calibration Summary] 800 Mbps
6983 00:26:05.796534 CH 0, Rank 0
6984 00:26:05.799867 SW Impedance : PASS
6985 00:26:05.802757 DUTY Scan : NO K
6986 00:26:05.802828 ZQ Calibration : PASS
6987 00:26:05.806166 Jitter Meter : NO K
6988 00:26:05.809820 CBT Training : PASS
6989 00:26:05.809897 Write leveling : PASS
6990 00:26:05.813345 RX DQS gating : PASS
6991 00:26:05.816291 RX DQ/DQS(RDDQC) : PASS
6992 00:26:05.816369 TX DQ/DQS : PASS
6993 00:26:05.819648 RX DATLAT : PASS
6994 00:26:05.823145 RX DQ/DQS(Engine): PASS
6995 00:26:05.823279 TX OE : NO K
6996 00:26:05.823367 All Pass.
6997 00:26:05.826116
6998 00:26:05.826232 CH 0, Rank 1
6999 00:26:05.829674 SW Impedance : PASS
7000 00:26:05.829781 DUTY Scan : NO K
7001 00:26:05.832584 ZQ Calibration : PASS
7002 00:26:05.832691 Jitter Meter : NO K
7003 00:26:05.836053 CBT Training : PASS
7004 00:26:05.839609 Write leveling : NO K
7005 00:26:05.839713 RX DQS gating : PASS
7006 00:26:05.842989 RX DQ/DQS(RDDQC) : PASS
7007 00:26:05.845856 TX DQ/DQS : PASS
7008 00:26:05.846022 RX DATLAT : PASS
7009 00:26:05.849427 RX DQ/DQS(Engine): PASS
7010 00:26:05.852909 TX OE : NO K
7011 00:26:05.852998 All Pass.
7012 00:26:05.853059
7013 00:26:05.853114 CH 1, Rank 0
7014 00:26:05.855738 SW Impedance : PASS
7015 00:26:05.859142 DUTY Scan : NO K
7016 00:26:05.859237 ZQ Calibration : PASS
7017 00:26:05.862695 Jitter Meter : NO K
7018 00:26:05.865664 CBT Training : PASS
7019 00:26:05.865762 Write leveling : PASS
7020 00:26:05.868953 RX DQS gating : PASS
7021 00:26:05.872285 RX DQ/DQS(RDDQC) : PASS
7022 00:26:05.872383 TX DQ/DQS : PASS
7023 00:26:05.875596 RX DATLAT : PASS
7024 00:26:05.878851 RX DQ/DQS(Engine): PASS
7025 00:26:05.878922 TX OE : NO K
7026 00:26:05.882802 All Pass.
7027 00:26:05.882867
7028 00:26:05.882921 CH 1, Rank 1
7029 00:26:05.885853 SW Impedance : PASS
7030 00:26:05.885916 DUTY Scan : NO K
7031 00:26:05.888662 ZQ Calibration : PASS
7032 00:26:05.892241 Jitter Meter : NO K
7033 00:26:05.892337 CBT Training : PASS
7034 00:26:05.895393 Write leveling : NO K
7035 00:26:05.895496 RX DQS gating : PASS
7036 00:26:05.898695 RX DQ/DQS(RDDQC) : PASS
7037 00:26:05.901925 TX DQ/DQS : PASS
7038 00:26:05.902004 RX DATLAT : PASS
7039 00:26:05.905325 RX DQ/DQS(Engine): PASS
7040 00:26:05.908656 TX OE : NO K
7041 00:26:05.908773 All Pass.
7042 00:26:05.908875
7043 00:26:05.912093 DramC Write-DBI off
7044 00:26:05.915140 PER_BANK_REFRESH: Hybrid Mode
7045 00:26:05.915255 TX_TRACKING: ON
7046 00:26:05.924959 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7047 00:26:05.928427 [FAST_K] Save calibration result to emmc
7048 00:26:05.931951 dramc_set_vcore_voltage set vcore to 725000
7049 00:26:05.934964 Read voltage for 1600, 0
7050 00:26:05.935076 Vio18 = 0
7051 00:26:05.935180 Vcore = 725000
7052 00:26:05.938568 Vdram = 0
7053 00:26:05.938680 Vddq = 0
7054 00:26:05.938780 Vmddr = 0
7055 00:26:05.945119 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7056 00:26:05.948535 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7057 00:26:05.951956 MEM_TYPE=3, freq_sel=13
7058 00:26:05.954873 sv_algorithm_assistance_LP4_3733
7059 00:26:05.958317 ============ PULL DRAM RESETB DOWN ============
7060 00:26:05.961696 ========== PULL DRAM RESETB DOWN end =========
7061 00:26:05.967983 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7062 00:26:05.971418 ===================================
7063 00:26:05.971535 LPDDR4 DRAM CONFIGURATION
7064 00:26:05.974923 ===================================
7065 00:26:05.978423 EX_ROW_EN[0] = 0x0
7066 00:26:05.981411 EX_ROW_EN[1] = 0x0
7067 00:26:05.981526 LP4Y_EN = 0x0
7068 00:26:05.985034 WORK_FSP = 0x1
7069 00:26:05.985144 WL = 0x5
7070 00:26:05.987980 RL = 0x5
7071 00:26:05.988092 BL = 0x2
7072 00:26:05.991371 RPST = 0x0
7073 00:26:05.991481 RD_PRE = 0x0
7074 00:26:05.995021 WR_PRE = 0x1
7075 00:26:05.995132 WR_PST = 0x1
7076 00:26:05.998220 DBI_WR = 0x0
7077 00:26:05.998334 DBI_RD = 0x0
7078 00:26:06.001295 OTF = 0x1
7079 00:26:06.004866 ===================================
7080 00:26:06.007965 ===================================
7081 00:26:06.008073 ANA top config
7082 00:26:06.011083 ===================================
7083 00:26:06.014614 DLL_ASYNC_EN = 0
7084 00:26:06.018114 ALL_SLAVE_EN = 0
7085 00:26:06.021319 NEW_RANK_MODE = 1
7086 00:26:06.021425 DLL_IDLE_MODE = 1
7087 00:26:06.024836 LP45_APHY_COMB_EN = 1
7088 00:26:06.027772 TX_ODT_DIS = 0
7089 00:26:06.031119 NEW_8X_MODE = 1
7090 00:26:06.034601 ===================================
7091 00:26:06.038189 ===================================
7092 00:26:06.041282 data_rate = 3200
7093 00:26:06.041361 CKR = 1
7094 00:26:06.044225 DQ_P2S_RATIO = 8
7095 00:26:06.047845 ===================================
7096 00:26:06.050806 CA_P2S_RATIO = 8
7097 00:26:06.054159 DQ_CA_OPEN = 0
7098 00:26:06.057576 DQ_SEMI_OPEN = 0
7099 00:26:06.060971 CA_SEMI_OPEN = 0
7100 00:26:06.061074 CA_FULL_RATE = 0
7101 00:26:06.064310 DQ_CKDIV4_EN = 0
7102 00:26:06.067589 CA_CKDIV4_EN = 0
7103 00:26:06.071188 CA_PREDIV_EN = 0
7104 00:26:06.074000 PH8_DLY = 12
7105 00:26:06.077527 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7106 00:26:06.077642 DQ_AAMCK_DIV = 4
7107 00:26:06.080939 CA_AAMCK_DIV = 4
7108 00:26:06.084193 CA_ADMCK_DIV = 4
7109 00:26:06.087690 DQ_TRACK_CA_EN = 0
7110 00:26:06.090633 CA_PICK = 1600
7111 00:26:06.094106 CA_MCKIO = 1600
7112 00:26:06.097110 MCKIO_SEMI = 0
7113 00:26:06.097224 PLL_FREQ = 3068
7114 00:26:06.100540 DQ_UI_PI_RATIO = 32
7115 00:26:06.103891 CA_UI_PI_RATIO = 0
7116 00:26:06.107308 ===================================
7117 00:26:06.110822 ===================================
7118 00:26:06.113725 memory_type:LPDDR4
7119 00:26:06.117549 GP_NUM : 10
7120 00:26:06.117663 SRAM_EN : 1
7121 00:26:06.120295 MD32_EN : 0
7122 00:26:06.123697 ===================================
7123 00:26:06.123817 [ANA_INIT] >>>>>>>>>>>>>>
7124 00:26:06.127245 <<<<<< [CONFIGURE PHASE]: ANA_TX
7125 00:26:06.130761 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7126 00:26:06.133711 ===================================
7127 00:26:06.137259 data_rate = 3200,PCW = 0X7600
7128 00:26:06.140359 ===================================
7129 00:26:06.143947 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7130 00:26:06.150528 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7131 00:26:06.153968 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7132 00:26:06.160491 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7133 00:26:06.163736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7134 00:26:06.167120 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7135 00:26:06.170437 [ANA_INIT] flow start
7136 00:26:06.170531 [ANA_INIT] PLL >>>>>>>>
7137 00:26:06.173315 [ANA_INIT] PLL <<<<<<<<
7138 00:26:06.176785 [ANA_INIT] MIDPI >>>>>>>>
7139 00:26:06.176879 [ANA_INIT] MIDPI <<<<<<<<
7140 00:26:06.180364 [ANA_INIT] DLL >>>>>>>>
7141 00:26:06.183325 [ANA_INIT] DLL <<<<<<<<
7142 00:26:06.183391 [ANA_INIT] flow end
7143 00:26:06.189899 ============ LP4 DIFF to SE enter ============
7144 00:26:06.193528 ============ LP4 DIFF to SE exit ============
7145 00:26:06.196345 [ANA_INIT] <<<<<<<<<<<<<
7146 00:26:06.199928 [Flow] Enable top DCM control >>>>>
7147 00:26:06.203341 [Flow] Enable top DCM control <<<<<
7148 00:26:06.203461 Enable DLL master slave shuffle
7149 00:26:06.210063 ==============================================================
7150 00:26:06.213439 Gating Mode config
7151 00:26:06.216502 ==============================================================
7152 00:26:06.220172 Config description:
7153 00:26:06.229856 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7154 00:26:06.236482 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7155 00:26:06.239602 SELPH_MODE 0: By rank 1: By Phase
7156 00:26:06.246413 ==============================================================
7157 00:26:06.249431 GAT_TRACK_EN = 1
7158 00:26:06.253281 RX_GATING_MODE = 2
7159 00:26:06.256182 RX_GATING_TRACK_MODE = 2
7160 00:26:06.259653 SELPH_MODE = 1
7161 00:26:06.259732 PICG_EARLY_EN = 1
7162 00:26:06.263199 VALID_LAT_VALUE = 1
7163 00:26:06.269427 ==============================================================
7164 00:26:06.272606 Enter into Gating configuration >>>>
7165 00:26:06.276364 Exit from Gating configuration <<<<
7166 00:26:06.279406 Enter into DVFS_PRE_config >>>>>
7167 00:26:06.289412 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7168 00:26:06.292884 Exit from DVFS_PRE_config <<<<<
7169 00:26:06.296145 Enter into PICG configuration >>>>
7170 00:26:06.299044 Exit from PICG configuration <<<<
7171 00:26:06.302611 [RX_INPUT] configuration >>>>>
7172 00:26:06.305602 [RX_INPUT] configuration <<<<<
7173 00:26:06.308931 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7174 00:26:06.315897 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7175 00:26:06.322206 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7176 00:26:06.329250 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7177 00:26:06.335583 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7178 00:26:06.342357 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7179 00:26:06.345515 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7180 00:26:06.348756 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7181 00:26:06.351926 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7182 00:26:06.358924 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7183 00:26:06.362278 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7184 00:26:06.365217 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7185 00:26:06.368877 ===================================
7186 00:26:06.372366 LPDDR4 DRAM CONFIGURATION
7187 00:26:06.375115 ===================================
7188 00:26:06.375191 EX_ROW_EN[0] = 0x0
7189 00:26:06.378661 EX_ROW_EN[1] = 0x0
7190 00:26:06.378737 LP4Y_EN = 0x0
7191 00:26:06.382153 WORK_FSP = 0x1
7192 00:26:06.385309 WL = 0x5
7193 00:26:06.385385 RL = 0x5
7194 00:26:06.388423 BL = 0x2
7195 00:26:06.388499 RPST = 0x0
7196 00:26:06.391887 RD_PRE = 0x0
7197 00:26:06.391963 WR_PRE = 0x1
7198 00:26:06.395367 WR_PST = 0x1
7199 00:26:06.395442 DBI_WR = 0x0
7200 00:26:06.398361 DBI_RD = 0x0
7201 00:26:06.398468 OTF = 0x1
7202 00:26:06.401684 ===================================
7203 00:26:06.404972 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7204 00:26:06.411511 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7205 00:26:06.414790 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7206 00:26:06.418323 ===================================
7207 00:26:06.421765 LPDDR4 DRAM CONFIGURATION
7208 00:26:06.425119 ===================================
7209 00:26:06.425196 EX_ROW_EN[0] = 0x10
7210 00:26:06.428240 EX_ROW_EN[1] = 0x0
7211 00:26:06.428316 LP4Y_EN = 0x0
7212 00:26:06.431792 WORK_FSP = 0x1
7213 00:26:06.434661 WL = 0x5
7214 00:26:06.434736 RL = 0x5
7215 00:26:06.438141 BL = 0x2
7216 00:26:06.438217 RPST = 0x0
7217 00:26:06.441665 RD_PRE = 0x0
7218 00:26:06.441741 WR_PRE = 0x1
7219 00:26:06.445278 WR_PST = 0x1
7220 00:26:06.445355 DBI_WR = 0x0
7221 00:26:06.448107 DBI_RD = 0x0
7222 00:26:06.448206 OTF = 0x1
7223 00:26:06.451390 ===================================
7224 00:26:06.458104 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7225 00:26:06.458196 ==
7226 00:26:06.461392 Dram Type= 6, Freq= 0, CH_0, rank 0
7227 00:26:06.464519 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7228 00:26:06.464620 ==
7229 00:26:06.468150 [Duty_Offset_Calibration]
7230 00:26:06.471481 B0:2 B1:0 CA:3
7231 00:26:06.471562
7232 00:26:06.474701 [DutyScan_Calibration_Flow] k_type=0
7233 00:26:06.482931
7234 00:26:06.483008 ==CLK 0==
7235 00:26:06.486410 Final CLK duty delay cell = 0
7236 00:26:06.489753 [0] MAX Duty = 5031%(X100), DQS PI = 12
7237 00:26:06.492848 [0] MIN Duty = 4907%(X100), DQS PI = 6
7238 00:26:06.496406 [0] AVG Duty = 4969%(X100)
7239 00:26:06.496482
7240 00:26:06.499373 CH0 CLK Duty spec in!! Max-Min= 124%
7241 00:26:06.502958 [DutyScan_Calibration_Flow] ====Done====
7242 00:26:06.503061
7243 00:26:06.505877 [DutyScan_Calibration_Flow] k_type=1
7244 00:26:06.522805
7245 00:26:06.522891 ==DQS 0 ==
7246 00:26:06.526335 Final DQS duty delay cell = 0
7247 00:26:06.529224 [0] MAX Duty = 5094%(X100), DQS PI = 28
7248 00:26:06.532818 [0] MIN Duty = 4875%(X100), DQS PI = 50
7249 00:26:06.536262 [0] AVG Duty = 4984%(X100)
7250 00:26:06.536341
7251 00:26:06.536406 ==DQS 1 ==
7252 00:26:06.538999 Final DQS duty delay cell = 0
7253 00:26:06.542561 [0] MAX Duty = 5156%(X100), DQS PI = 32
7254 00:26:06.546081 [0] MIN Duty = 5062%(X100), DQS PI = 0
7255 00:26:06.549014 [0] AVG Duty = 5109%(X100)
7256 00:26:06.549093
7257 00:26:06.552598 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7258 00:26:06.552723
7259 00:26:06.556087 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7260 00:26:06.559421 [DutyScan_Calibration_Flow] ====Done====
7261 00:26:06.559497
7262 00:26:06.562648 [DutyScan_Calibration_Flow] k_type=3
7263 00:26:06.580337
7264 00:26:06.580414 ==DQM 0 ==
7265 00:26:06.583592 Final DQM duty delay cell = 0
7266 00:26:06.586993 [0] MAX Duty = 5125%(X100), DQS PI = 12
7267 00:26:06.590444 [0] MIN Duty = 4844%(X100), DQS PI = 48
7268 00:26:06.593814 [0] AVG Duty = 4984%(X100)
7269 00:26:06.593890
7270 00:26:06.593949 ==DQM 1 ==
7271 00:26:06.597089 Final DQM duty delay cell = 4
7272 00:26:06.600316 [4] MAX Duty = 5187%(X100), DQS PI = 62
7273 00:26:06.603568 [4] MIN Duty = 5000%(X100), DQS PI = 38
7274 00:26:06.607073 [4] AVG Duty = 5093%(X100)
7275 00:26:06.607156
7276 00:26:06.610615 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7277 00:26:06.610692
7278 00:26:06.613576 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7279 00:26:06.616836 [DutyScan_Calibration_Flow] ====Done====
7280 00:26:06.616912
7281 00:26:06.620317 [DutyScan_Calibration_Flow] k_type=2
7282 00:26:06.636776
7283 00:26:06.636850 ==DQ 0 ==
7284 00:26:06.640254 Final DQ duty delay cell = -4
7285 00:26:06.643202 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7286 00:26:06.646678 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7287 00:26:06.649588 [-4] AVG Duty = 4938%(X100)
7288 00:26:06.649687
7289 00:26:06.649770 ==DQ 1 ==
7290 00:26:06.653149 Final DQ duty delay cell = 0
7291 00:26:06.656566 [0] MAX Duty = 5156%(X100), DQS PI = 60
7292 00:26:06.659568 [0] MIN Duty = 5000%(X100), DQS PI = 16
7293 00:26:06.663048 [0] AVG Duty = 5078%(X100)
7294 00:26:06.663143
7295 00:26:06.666364 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7296 00:26:06.666522
7297 00:26:06.669540 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7298 00:26:06.672969 [DutyScan_Calibration_Flow] ====Done====
7299 00:26:06.673045 ==
7300 00:26:06.676498 Dram Type= 6, Freq= 0, CH_1, rank 0
7301 00:26:06.679923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7302 00:26:06.679999 ==
7303 00:26:06.683285 [Duty_Offset_Calibration]
7304 00:26:06.683364 B0:1 B1:-2 CA:1
7305 00:26:06.683423
7306 00:26:06.686260 [DutyScan_Calibration_Flow] k_type=0
7307 00:26:06.697467
7308 00:26:06.697542 ==CLK 0==
7309 00:26:06.700308 Final CLK duty delay cell = 0
7310 00:26:06.703839 [0] MAX Duty = 5031%(X100), DQS PI = 50
7311 00:26:06.707161 [0] MIN Duty = 4875%(X100), DQS PI = 26
7312 00:26:06.710526 [0] AVG Duty = 4953%(X100)
7313 00:26:06.710603
7314 00:26:06.713901 CH1 CLK Duty spec in!! Max-Min= 156%
7315 00:26:06.717311 [DutyScan_Calibration_Flow] ====Done====
7316 00:26:06.717419
7317 00:26:06.720503 [DutyScan_Calibration_Flow] k_type=1
7318 00:26:06.736283
7319 00:26:06.736359 ==DQS 0 ==
7320 00:26:06.739696 Final DQS duty delay cell = -4
7321 00:26:06.742576 [-4] MAX Duty = 4938%(X100), DQS PI = 58
7322 00:26:06.746261 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7323 00:26:06.749082 [-4] AVG Duty = 4891%(X100)
7324 00:26:06.749157
7325 00:26:06.749214 ==DQS 1 ==
7326 00:26:06.752544 Final DQS duty delay cell = 0
7327 00:26:06.756032 [0] MAX Duty = 5093%(X100), DQS PI = 26
7328 00:26:06.758952 [0] MIN Duty = 4813%(X100), DQS PI = 58
7329 00:26:06.762583 [0] AVG Duty = 4953%(X100)
7330 00:26:06.762658
7331 00:26:06.766105 CH1 DQS 0 Duty spec in!! Max-Min= 94%
7332 00:26:06.766180
7333 00:26:06.769081 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7334 00:26:06.772501 [DutyScan_Calibration_Flow] ====Done====
7335 00:26:06.772600
7336 00:26:06.775813 [DutyScan_Calibration_Flow] k_type=3
7337 00:26:06.793228
7338 00:26:06.793302 ==DQM 0 ==
7339 00:26:06.796415 Final DQM duty delay cell = 0
7340 00:26:06.799529 [0] MAX Duty = 5000%(X100), DQS PI = 60
7341 00:26:06.802754 [0] MIN Duty = 4844%(X100), DQS PI = 22
7342 00:26:06.806273 [0] AVG Duty = 4922%(X100)
7343 00:26:06.806349
7344 00:26:06.806407 ==DQM 1 ==
7345 00:26:06.809553 Final DQM duty delay cell = 0
7346 00:26:06.812997 [0] MAX Duty = 5062%(X100), DQS PI = 4
7347 00:26:06.816370 [0] MIN Duty = 4875%(X100), DQS PI = 36
7348 00:26:06.819589 [0] AVG Duty = 4968%(X100)
7349 00:26:06.819668
7350 00:26:06.823123 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7351 00:26:06.823199
7352 00:26:06.826170 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7353 00:26:06.829481 [DutyScan_Calibration_Flow] ====Done====
7354 00:26:06.829609
7355 00:26:06.832665 [DutyScan_Calibration_Flow] k_type=2
7356 00:26:06.850099
7357 00:26:06.850179 ==DQ 0 ==
7358 00:26:06.852936 Final DQ duty delay cell = 0
7359 00:26:06.856351 [0] MAX Duty = 5062%(X100), DQS PI = 0
7360 00:26:06.859956 [0] MIN Duty = 4938%(X100), DQS PI = 24
7361 00:26:06.860033 [0] AVG Duty = 5000%(X100)
7362 00:26:06.860093
7363 00:26:06.862989 ==DQ 1 ==
7364 00:26:06.866517 Final DQ duty delay cell = 0
7365 00:26:06.870018 [0] MAX Duty = 5125%(X100), DQS PI = 2
7366 00:26:06.872974 [0] MIN Duty = 4907%(X100), DQS PI = 58
7367 00:26:06.873050 [0] AVG Duty = 5016%(X100)
7368 00:26:06.873109
7369 00:26:06.876539 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7370 00:26:06.876638
7371 00:26:06.883334 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7372 00:26:06.886581 [DutyScan_Calibration_Flow] ====Done====
7373 00:26:06.890071 nWR fixed to 30
7374 00:26:06.890148 [ModeRegInit_LP4] CH0 RK0
7375 00:26:06.893003 [ModeRegInit_LP4] CH0 RK1
7376 00:26:06.896555 [ModeRegInit_LP4] CH1 RK0
7377 00:26:06.896630 [ModeRegInit_LP4] CH1 RK1
7378 00:26:06.899995 match AC timing 5
7379 00:26:06.903019 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7380 00:26:06.906359 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7381 00:26:06.912983 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7382 00:26:06.915965 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7383 00:26:06.922934 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7384 00:26:06.923021 [MiockJmeterHQA]
7385 00:26:06.923084
7386 00:26:06.926044 [DramcMiockJmeter] u1RxGatingPI = 0
7387 00:26:06.929287 0 : 4262, 4032
7388 00:26:06.929365 4 : 4257, 4032
7389 00:26:06.929426 8 : 4368, 4143
7390 00:26:06.932721 12 : 4255, 4030
7391 00:26:06.932798 16 : 4257, 4029
7392 00:26:06.936310 20 : 4365, 4140
7393 00:26:06.936388 24 : 4257, 4029
7394 00:26:06.939330 28 : 4257, 4029
7395 00:26:06.939407 32 : 4368, 4140
7396 00:26:06.942534 36 : 4255, 4029
7397 00:26:06.942611 40 : 4255, 4029
7398 00:26:06.942693 44 : 4260, 4032
7399 00:26:06.946231 48 : 4367, 4140
7400 00:26:06.946388 52 : 4257, 4029
7401 00:26:06.949512 56 : 4365, 4140
7402 00:26:06.949589 60 : 4366, 4140
7403 00:26:06.952757 64 : 4250, 4027
7404 00:26:06.952834 68 : 4250, 4027
7405 00:26:06.955967 72 : 4366, 4140
7406 00:26:06.956051 76 : 4252, 4026
7407 00:26:06.956120 80 : 4255, 4029
7408 00:26:06.959304 84 : 4258, 4031
7409 00:26:06.959381 88 : 4368, 4142
7410 00:26:06.962394 92 : 4252, 4029
7411 00:26:06.962471 96 : 4257, 4032
7412 00:26:06.965984 100 : 4363, 4140
7413 00:26:06.966062 104 : 4255, 3442
7414 00:26:06.969002 108 : 4255, 0
7415 00:26:06.969089 112 : 4254, 0
7416 00:26:06.969153 116 : 4257, 0
7417 00:26:06.972581 120 : 4255, 0
7418 00:26:06.972684 124 : 4253, 0
7419 00:26:06.975515 128 : 4255, 0
7420 00:26:06.975594 132 : 4257, 0
7421 00:26:06.975655 136 : 4253, 0
7422 00:26:06.978984 140 : 4252, 0
7423 00:26:06.979060 144 : 4368, 0
7424 00:26:06.979120 148 : 4252, 0
7425 00:26:06.982480 152 : 4363, 0
7426 00:26:06.982556 156 : 4253, 0
7427 00:26:06.985381 160 : 4249, 0
7428 00:26:06.985458 164 : 4253, 0
7429 00:26:06.985518 168 : 4253, 0
7430 00:26:06.988844 172 : 4254, 0
7431 00:26:06.988922 176 : 4252, 0
7432 00:26:06.992553 180 : 4252, 0
7433 00:26:06.992660 184 : 4252, 0
7434 00:26:06.992723 188 : 4253, 0
7435 00:26:06.995903 192 : 4365, 0
7436 00:26:06.995979 196 : 4253, 0
7437 00:26:06.998854 200 : 4363, 0
7438 00:26:06.998930 204 : 4363, 0
7439 00:26:06.998990 208 : 4252, 0
7440 00:26:07.002394 212 : 4363, 0
7441 00:26:07.002470 216 : 4366, 0
7442 00:26:07.002530 220 : 4255, 0
7443 00:26:07.005237 224 : 4252, 0
7444 00:26:07.005314 228 : 4253, 0
7445 00:26:07.008612 232 : 4252, 0
7446 00:26:07.008705 236 : 4252, 880
7447 00:26:07.012131 240 : 4255, 4029
7448 00:26:07.012230 244 : 4252, 4029
7449 00:26:07.012319 248 : 4253, 4029
7450 00:26:07.015600 252 : 4257, 4031
7451 00:26:07.015694 256 : 4365, 4139
7452 00:26:07.018906 260 : 4366, 4140
7453 00:26:07.019000 264 : 4253, 4029
7454 00:26:07.022285 268 : 4255, 4029
7455 00:26:07.022378 272 : 4365, 4140
7456 00:26:07.025343 276 : 4252, 4029
7457 00:26:07.025420 280 : 4252, 4029
7458 00:26:07.028525 284 : 4253, 4029
7459 00:26:07.028627 288 : 4254, 4030
7460 00:26:07.031895 292 : 4255, 4029
7461 00:26:07.031971 296 : 4252, 4029
7462 00:26:07.035561 300 : 4253, 4029
7463 00:26:07.035653 304 : 4257, 4032
7464 00:26:07.035715 308 : 4255, 4029
7465 00:26:07.038748 312 : 4252, 4029
7466 00:26:07.038825 316 : 4361, 4137
7467 00:26:07.042074 320 : 4255, 4029
7468 00:26:07.042150 324 : 4253, 4029
7469 00:26:07.045663 328 : 4255, 4029
7470 00:26:07.045754 332 : 4253, 4029
7471 00:26:07.048547 336 : 4253, 4029
7472 00:26:07.048668 340 : 4257, 4031
7473 00:26:07.051887 344 : 4365, 4140
7474 00:26:07.051964 348 : 4253, 4029
7475 00:26:07.055285 352 : 4252, 4011
7476 00:26:07.055362 356 : 4257, 2687
7477 00:26:07.058981 360 : 4365, 0
7478 00:26:07.059058
7479 00:26:07.059117 MIOCK jitter meter ch=0
7480 00:26:07.059172
7481 00:26:07.061799 1T = (360-108) = 252 dly cells
7482 00:26:07.068664 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7483 00:26:07.068775 ==
7484 00:26:07.071611 Dram Type= 6, Freq= 0, CH_0, rank 0
7485 00:26:07.075175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7486 00:26:07.075335 ==
7487 00:26:07.081592 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7488 00:26:07.085208 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7489 00:26:07.088166 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7490 00:26:07.095133 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7491 00:26:07.104360 [CA 0] Center 44 (14~75) winsize 62
7492 00:26:07.107907 [CA 1] Center 43 (13~74) winsize 62
7493 00:26:07.111370 [CA 2] Center 40 (11~69) winsize 59
7494 00:26:07.114411 [CA 3] Center 39 (10~68) winsize 59
7495 00:26:07.117893 [CA 4] Center 37 (8~67) winsize 60
7496 00:26:07.121498 [CA 5] Center 37 (7~67) winsize 61
7497 00:26:07.121574
7498 00:26:07.124458 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7499 00:26:07.124592
7500 00:26:07.127740 [CATrainingPosCal] consider 1 rank data
7501 00:26:07.131117 u2DelayCellTimex100 = 258/100 ps
7502 00:26:07.137668 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7503 00:26:07.141141 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7504 00:26:07.144292 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7505 00:26:07.147967 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7506 00:26:07.150854 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7507 00:26:07.154167 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7508 00:26:07.154244
7509 00:26:07.157681 CA PerBit enable=1, Macro0, CA PI delay=37
7510 00:26:07.157762
7511 00:26:07.161052 [CBTSetCACLKResult] CA Dly = 37
7512 00:26:07.164390 CS Dly: 11 (0~42)
7513 00:26:07.167778 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7514 00:26:07.170993 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7515 00:26:07.171090 ==
7516 00:26:07.174272 Dram Type= 6, Freq= 0, CH_0, rank 1
7517 00:26:07.180762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7518 00:26:07.180834 ==
7519 00:26:07.184266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7520 00:26:07.187855 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7521 00:26:07.194206 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7522 00:26:07.200766 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7523 00:26:07.208569 [CA 0] Center 44 (14~75) winsize 62
7524 00:26:07.211813 [CA 1] Center 43 (13~74) winsize 62
7525 00:26:07.215077 [CA 2] Center 39 (10~69) winsize 60
7526 00:26:07.218498 [CA 3] Center 39 (10~69) winsize 60
7527 00:26:07.221440 [CA 4] Center 37 (8~67) winsize 60
7528 00:26:07.225013 [CA 5] Center 37 (7~67) winsize 61
7529 00:26:07.225090
7530 00:26:07.228407 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7531 00:26:07.228483
7532 00:26:07.234701 [CATrainingPosCal] consider 2 rank data
7533 00:26:07.234778 u2DelayCellTimex100 = 258/100 ps
7534 00:26:07.241323 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7535 00:26:07.245070 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7536 00:26:07.248087 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7537 00:26:07.251483 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7538 00:26:07.254878 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7539 00:26:07.257986 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7540 00:26:07.258083
7541 00:26:07.261313 CA PerBit enable=1, Macro0, CA PI delay=37
7542 00:26:07.261404
7543 00:26:07.264687 [CBTSetCACLKResult] CA Dly = 37
7544 00:26:07.268024 CS Dly: 11 (0~43)
7545 00:26:07.271484 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7546 00:26:07.274423 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7547 00:26:07.274513
7548 00:26:07.277747 ----->DramcWriteLeveling(PI) begin...
7549 00:26:07.277814 ==
7550 00:26:07.281479 Dram Type= 6, Freq= 0, CH_0, rank 0
7551 00:26:07.288234 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7552 00:26:07.288346 ==
7553 00:26:07.291100 Write leveling (Byte 0): 37 => 37
7554 00:26:07.294631 Write leveling (Byte 1): 27 => 27
7555 00:26:07.297556 DramcWriteLeveling(PI) end<-----
7556 00:26:07.297663
7557 00:26:07.297763 ==
7558 00:26:07.301097 Dram Type= 6, Freq= 0, CH_0, rank 0
7559 00:26:07.304778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7560 00:26:07.304887 ==
7561 00:26:07.307675 [Gating] SW mode calibration
7562 00:26:07.314343 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7563 00:26:07.317665 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7564 00:26:07.324401 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 00:26:07.327785 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 00:26:07.330733 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 00:26:07.337939 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 00:26:07.340905 1 4 16 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
7569 00:26:07.344487 1 4 20 | B1->B0 | 2322 3333 | 1 1 | (0 0) (1 1)
7570 00:26:07.350880 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7571 00:26:07.354432 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7572 00:26:07.357401 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7573 00:26:07.364244 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7574 00:26:07.367411 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7575 00:26:07.371127 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7576 00:26:07.377205 1 5 16 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
7577 00:26:07.380800 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7578 00:26:07.384178 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7579 00:26:07.390687 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7580 00:26:07.393975 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 00:26:07.397580 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 00:26:07.404110 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 00:26:07.407112 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 00:26:07.410724 1 6 16 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
7585 00:26:07.417326 1 6 20 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
7586 00:26:07.420257 1 6 24 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
7587 00:26:07.423728 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 00:26:07.430281 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 00:26:07.433894 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 00:26:07.437430 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7591 00:26:07.443904 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7592 00:26:07.447378 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7593 00:26:07.450292 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7594 00:26:07.453728 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7595 00:26:07.460778 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 00:26:07.463687 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 00:26:07.467176 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 00:26:07.473881 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 00:26:07.477236 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 00:26:07.480525 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 00:26:07.487278 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 00:26:07.490278 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 00:26:07.493446 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 00:26:07.500132 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 00:26:07.503790 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 00:26:07.506676 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 00:26:07.513682 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7608 00:26:07.516734 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7609 00:26:07.520198 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7610 00:26:07.523675 Total UI for P1: 0, mck2ui 16
7611 00:26:07.526551 best dqsien dly found for B0: ( 1, 9, 14)
7612 00:26:07.533064 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 00:26:07.533141 Total UI for P1: 0, mck2ui 16
7614 00:26:07.539641 best dqsien dly found for B1: ( 1, 9, 20)
7615 00:26:07.542948 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7616 00:26:07.546310 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7617 00:26:07.546383
7618 00:26:07.549928 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7619 00:26:07.553400 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7620 00:26:07.556425 [Gating] SW calibration Done
7621 00:26:07.556519 ==
7622 00:26:07.559887 Dram Type= 6, Freq= 0, CH_0, rank 0
7623 00:26:07.563201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7624 00:26:07.563280 ==
7625 00:26:07.566239 RX Vref Scan: 0
7626 00:26:07.566348
7627 00:26:07.569738 RX Vref 0 -> 0, step: 1
7628 00:26:07.569847
7629 00:26:07.569947 RX Delay 0 -> 252, step: 8
7630 00:26:07.576078 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7631 00:26:07.579584 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7632 00:26:07.582918 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7633 00:26:07.586444 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7634 00:26:07.589334 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7635 00:26:07.592737 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7636 00:26:07.599321 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7637 00:26:07.602653 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7638 00:26:07.606298 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7639 00:26:07.609470 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7640 00:26:07.613113 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7641 00:26:07.619481 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7642 00:26:07.622953 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7643 00:26:07.626494 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7644 00:26:07.629346 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7645 00:26:07.635817 iDelay=192, Bit 15, Center 127 (72 ~ 183) 112
7646 00:26:07.635911 ==
7647 00:26:07.639402 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 00:26:07.642712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 00:26:07.642811 ==
7650 00:26:07.642883 DQS Delay:
7651 00:26:07.645902 DQS0 = 0, DQS1 = 0
7652 00:26:07.645991 DQM Delay:
7653 00:26:07.649286 DQM0 = 128, DQM1 = 123
7654 00:26:07.649436 DQ Delay:
7655 00:26:07.652740 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7656 00:26:07.655852 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7657 00:26:07.659352 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7658 00:26:07.662743 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =127
7659 00:26:07.662833
7660 00:26:07.662913
7661 00:26:07.665713 ==
7662 00:26:07.669139 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 00:26:07.672593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 00:26:07.672712 ==
7665 00:26:07.672771
7666 00:26:07.672824
7667 00:26:07.675852 TX Vref Scan disable
7668 00:26:07.675982 == TX Byte 0 ==
7669 00:26:07.682353 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7670 00:26:07.685744 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7671 00:26:07.685857 == TX Byte 1 ==
7672 00:26:07.692274 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7673 00:26:07.695640 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7674 00:26:07.695743 ==
7675 00:26:07.699104 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 00:26:07.702401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 00:26:07.702467 ==
7678 00:26:07.716891
7679 00:26:07.719930 TX Vref early break, caculate TX vref
7680 00:26:07.723171 TX Vref=16, minBit 8, minWin=21, winSum=366
7681 00:26:07.726739 TX Vref=18, minBit 11, minWin=21, winSum=374
7682 00:26:07.729711 TX Vref=20, minBit 8, minWin=22, winSum=383
7683 00:26:07.733345 TX Vref=22, minBit 8, minWin=23, winSum=396
7684 00:26:07.736254 TX Vref=24, minBit 8, minWin=23, winSum=402
7685 00:26:07.743211 TX Vref=26, minBit 8, minWin=24, winSum=409
7686 00:26:07.746777 TX Vref=28, minBit 8, minWin=23, winSum=408
7687 00:26:07.749713 TX Vref=30, minBit 8, minWin=24, winSum=404
7688 00:26:07.752930 TX Vref=32, minBit 8, minWin=22, winSum=391
7689 00:26:07.756264 TX Vref=34, minBit 8, minWin=22, winSum=383
7690 00:26:07.762890 [TxChooseVref] Worse bit 8, Min win 24, Win sum 409, Final Vref 26
7691 00:26:07.762969
7692 00:26:07.766287 Final TX Range 0 Vref 26
7693 00:26:07.766364
7694 00:26:07.766423 ==
7695 00:26:07.769785 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 00:26:07.773269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 00:26:07.773347 ==
7698 00:26:07.773408
7699 00:26:07.773463
7700 00:26:07.776244 TX Vref Scan disable
7701 00:26:07.783079 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7702 00:26:07.783156 == TX Byte 0 ==
7703 00:26:07.786287 u2DelayCellOfst[0]=11 cells (3 PI)
7704 00:26:07.789517 u2DelayCellOfst[1]=15 cells (4 PI)
7705 00:26:07.792803 u2DelayCellOfst[2]=7 cells (2 PI)
7706 00:26:07.796151 u2DelayCellOfst[3]=11 cells (3 PI)
7707 00:26:07.799756 u2DelayCellOfst[4]=7 cells (2 PI)
7708 00:26:07.802659 u2DelayCellOfst[5]=0 cells (0 PI)
7709 00:26:07.806217 u2DelayCellOfst[6]=15 cells (4 PI)
7710 00:26:07.809522 u2DelayCellOfst[7]=15 cells (4 PI)
7711 00:26:07.812773 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7712 00:26:07.815896 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7713 00:26:07.819104 == TX Byte 1 ==
7714 00:26:07.822643 u2DelayCellOfst[8]=0 cells (0 PI)
7715 00:26:07.822723 u2DelayCellOfst[9]=0 cells (0 PI)
7716 00:26:07.826144 u2DelayCellOfst[10]=7 cells (2 PI)
7717 00:26:07.829114 u2DelayCellOfst[11]=3 cells (1 PI)
7718 00:26:07.832463 u2DelayCellOfst[12]=11 cells (3 PI)
7719 00:26:07.835621 u2DelayCellOfst[13]=11 cells (3 PI)
7720 00:26:07.839226 u2DelayCellOfst[14]=15 cells (4 PI)
7721 00:26:07.842213 u2DelayCellOfst[15]=11 cells (3 PI)
7722 00:26:07.845824 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7723 00:26:07.852224 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7724 00:26:07.852315 DramC Write-DBI on
7725 00:26:07.852404 ==
7726 00:26:07.855658 Dram Type= 6, Freq= 0, CH_0, rank 0
7727 00:26:07.862150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7728 00:26:07.862226 ==
7729 00:26:07.862286
7730 00:26:07.862339
7731 00:26:07.862391 TX Vref Scan disable
7732 00:26:07.866220 == TX Byte 0 ==
7733 00:26:07.869770 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
7734 00:26:07.872863 == TX Byte 1 ==
7735 00:26:07.876304 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7736 00:26:07.876379 DramC Write-DBI off
7737 00:26:07.879838
7738 00:26:07.879913 [DATLAT]
7739 00:26:07.879971 Freq=1600, CH0 RK0
7740 00:26:07.880026
7741 00:26:07.882750 DATLAT Default: 0xf
7742 00:26:07.882825 0, 0xFFFF, sum = 0
7743 00:26:07.886241 1, 0xFFFF, sum = 0
7744 00:26:07.886318 2, 0xFFFF, sum = 0
7745 00:26:07.889655 3, 0xFFFF, sum = 0
7746 00:26:07.892784 4, 0xFFFF, sum = 0
7747 00:26:07.892861 5, 0xFFFF, sum = 0
7748 00:26:07.896247 6, 0xFFFF, sum = 0
7749 00:26:07.896324 7, 0xFFFF, sum = 0
7750 00:26:07.899476 8, 0xFFFF, sum = 0
7751 00:26:07.899553 9, 0xFFFF, sum = 0
7752 00:26:07.902480 10, 0xFFFF, sum = 0
7753 00:26:07.902557 11, 0xFFFF, sum = 0
7754 00:26:07.905991 12, 0xFFFF, sum = 0
7755 00:26:07.906068 13, 0xEFFF, sum = 0
7756 00:26:07.909512 14, 0x0, sum = 1
7757 00:26:07.909591 15, 0x0, sum = 2
7758 00:26:07.912431 16, 0x0, sum = 3
7759 00:26:07.912555 17, 0x0, sum = 4
7760 00:26:07.915928 best_step = 15
7761 00:26:07.916004
7762 00:26:07.916062 ==
7763 00:26:07.919173 Dram Type= 6, Freq= 0, CH_0, rank 0
7764 00:26:07.922516 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7765 00:26:07.922593 ==
7766 00:26:07.925744 RX Vref Scan: 1
7767 00:26:07.925840
7768 00:26:07.925900 Set Vref Range= 24 -> 127
7769 00:26:07.925955
7770 00:26:07.929102 RX Vref 24 -> 127, step: 1
7771 00:26:07.929204
7772 00:26:07.932151 RX Delay 11 -> 252, step: 4
7773 00:26:07.932285
7774 00:26:07.935755 Set Vref, RX VrefLevel [Byte0]: 24
7775 00:26:07.939173 [Byte1]: 24
7776 00:26:07.939249
7777 00:26:07.942118 Set Vref, RX VrefLevel [Byte0]: 25
7778 00:26:07.945564 [Byte1]: 25
7779 00:26:07.949350
7780 00:26:07.949447 Set Vref, RX VrefLevel [Byte0]: 26
7781 00:26:07.952095 [Byte1]: 26
7782 00:26:07.956852
7783 00:26:07.956919 Set Vref, RX VrefLevel [Byte0]: 27
7784 00:26:07.959932 [Byte1]: 27
7785 00:26:07.964239
7786 00:26:07.964362 Set Vref, RX VrefLevel [Byte0]: 28
7787 00:26:07.967352 [Byte1]: 28
7788 00:26:07.972021
7789 00:26:07.972103 Set Vref, RX VrefLevel [Byte0]: 29
7790 00:26:07.974946 [Byte1]: 29
7791 00:26:07.979690
7792 00:26:07.979779 Set Vref, RX VrefLevel [Byte0]: 30
7793 00:26:07.982525 [Byte1]: 30
7794 00:26:07.987220
7795 00:26:07.987314 Set Vref, RX VrefLevel [Byte0]: 31
7796 00:26:07.990139 [Byte1]: 31
7797 00:26:07.994858
7798 00:26:07.994921 Set Vref, RX VrefLevel [Byte0]: 32
7799 00:26:07.998281 [Byte1]: 32
7800 00:26:08.002343
7801 00:26:08.002406 Set Vref, RX VrefLevel [Byte0]: 33
7802 00:26:08.005392 [Byte1]: 33
7803 00:26:08.009850
7804 00:26:08.009915 Set Vref, RX VrefLevel [Byte0]: 34
7805 00:26:08.013354 [Byte1]: 34
7806 00:26:08.017547
7807 00:26:08.017616 Set Vref, RX VrefLevel [Byte0]: 35
7808 00:26:08.020998 [Byte1]: 35
7809 00:26:08.025383
7810 00:26:08.025478 Set Vref, RX VrefLevel [Byte0]: 36
7811 00:26:08.028525 [Byte1]: 36
7812 00:26:08.032868
7813 00:26:08.032960 Set Vref, RX VrefLevel [Byte0]: 37
7814 00:26:08.036149 [Byte1]: 37
7815 00:26:08.040112
7816 00:26:08.040201 Set Vref, RX VrefLevel [Byte0]: 38
7817 00:26:08.043626 [Byte1]: 38
7818 00:26:08.048251
7819 00:26:08.048344 Set Vref, RX VrefLevel [Byte0]: 39
7820 00:26:08.051068 [Byte1]: 39
7821 00:26:08.055725
7822 00:26:08.055823 Set Vref, RX VrefLevel [Byte0]: 40
7823 00:26:08.058685 [Byte1]: 40
7824 00:26:08.063093
7825 00:26:08.063168 Set Vref, RX VrefLevel [Byte0]: 41
7826 00:26:08.066443 [Byte1]: 41
7827 00:26:08.070712
7828 00:26:08.070817 Set Vref, RX VrefLevel [Byte0]: 42
7829 00:26:08.074074 [Byte1]: 42
7830 00:26:08.078726
7831 00:26:08.078839 Set Vref, RX VrefLevel [Byte0]: 43
7832 00:26:08.081761 [Byte1]: 43
7833 00:26:08.085782
7834 00:26:08.085893 Set Vref, RX VrefLevel [Byte0]: 44
7835 00:26:08.089392 [Byte1]: 44
7836 00:26:08.093981
7837 00:26:08.094092 Set Vref, RX VrefLevel [Byte0]: 45
7838 00:26:08.096961 [Byte1]: 45
7839 00:26:08.101681
7840 00:26:08.101789 Set Vref, RX VrefLevel [Byte0]: 46
7841 00:26:08.104496 [Byte1]: 46
7842 00:26:08.108972
7843 00:26:08.109082 Set Vref, RX VrefLevel [Byte0]: 47
7844 00:26:08.112308 [Byte1]: 47
7845 00:26:08.116669
7846 00:26:08.116794 Set Vref, RX VrefLevel [Byte0]: 48
7847 00:26:08.119608 [Byte1]: 48
7848 00:26:08.124350
7849 00:26:08.124459 Set Vref, RX VrefLevel [Byte0]: 49
7850 00:26:08.127328 [Byte1]: 49
7851 00:26:08.131798
7852 00:26:08.131905 Set Vref, RX VrefLevel [Byte0]: 50
7853 00:26:08.134835 [Byte1]: 50
7854 00:26:08.139345
7855 00:26:08.139456 Set Vref, RX VrefLevel [Byte0]: 51
7856 00:26:08.142547 [Byte1]: 51
7857 00:26:08.146692
7858 00:26:08.146801 Set Vref, RX VrefLevel [Byte0]: 52
7859 00:26:08.150043 [Byte1]: 52
7860 00:26:08.154753
7861 00:26:08.154864 Set Vref, RX VrefLevel [Byte0]: 53
7862 00:26:08.157735 [Byte1]: 53
7863 00:26:08.161968
7864 00:26:08.162072 Set Vref, RX VrefLevel [Byte0]: 54
7865 00:26:08.165607 [Byte1]: 54
7866 00:26:08.169802
7867 00:26:08.169909 Set Vref, RX VrefLevel [Byte0]: 55
7868 00:26:08.173386 [Byte1]: 55
7869 00:26:08.177392
7870 00:26:08.177502 Set Vref, RX VrefLevel [Byte0]: 56
7871 00:26:08.180634 [Byte1]: 56
7872 00:26:08.185284
7873 00:26:08.185395 Set Vref, RX VrefLevel [Byte0]: 57
7874 00:26:08.188185 [Byte1]: 57
7875 00:26:08.192466
7876 00:26:08.192543 Set Vref, RX VrefLevel [Byte0]: 58
7877 00:26:08.195784 [Byte1]: 58
7878 00:26:08.200158
7879 00:26:08.200234 Set Vref, RX VrefLevel [Byte0]: 59
7880 00:26:08.203590 [Byte1]: 59
7881 00:26:08.207705
7882 00:26:08.207782 Set Vref, RX VrefLevel [Byte0]: 60
7883 00:26:08.211281 [Byte1]: 60
7884 00:26:08.215222
7885 00:26:08.215332 Set Vref, RX VrefLevel [Byte0]: 61
7886 00:26:08.218477 [Byte1]: 61
7887 00:26:08.223259
7888 00:26:08.223368 Set Vref, RX VrefLevel [Byte0]: 62
7889 00:26:08.226118 [Byte1]: 62
7890 00:26:08.230820
7891 00:26:08.230932 Set Vref, RX VrefLevel [Byte0]: 63
7892 00:26:08.234254 [Byte1]: 63
7893 00:26:08.238230
7894 00:26:08.238333 Set Vref, RX VrefLevel [Byte0]: 64
7895 00:26:08.241776 [Byte1]: 64
7896 00:26:08.245894
7897 00:26:08.246008 Set Vref, RX VrefLevel [Byte0]: 65
7898 00:26:08.249294 [Byte1]: 65
7899 00:26:08.253606
7900 00:26:08.253716 Set Vref, RX VrefLevel [Byte0]: 66
7901 00:26:08.256685 [Byte1]: 66
7902 00:26:08.260885
7903 00:26:08.260994 Set Vref, RX VrefLevel [Byte0]: 67
7904 00:26:08.264313 [Byte1]: 67
7905 00:26:08.268954
7906 00:26:08.269019 Set Vref, RX VrefLevel [Byte0]: 68
7907 00:26:08.271808 [Byte1]: 68
7908 00:26:08.276485
7909 00:26:08.276553 Set Vref, RX VrefLevel [Byte0]: 69
7910 00:26:08.279484 [Byte1]: 69
7911 00:26:08.284295
7912 00:26:08.284362 Set Vref, RX VrefLevel [Byte0]: 70
7913 00:26:08.287320 [Byte1]: 70
7914 00:26:08.291426
7915 00:26:08.291486 Set Vref, RX VrefLevel [Byte0]: 71
7916 00:26:08.294824 [Byte1]: 71
7917 00:26:08.299383
7918 00:26:08.299447 Set Vref, RX VrefLevel [Byte0]: 72
7919 00:26:08.302470 [Byte1]: 72
7920 00:26:08.306562
7921 00:26:08.306626 Set Vref, RX VrefLevel [Byte0]: 73
7922 00:26:08.310356 [Byte1]: 73
7923 00:26:08.314552
7924 00:26:08.314655 Set Vref, RX VrefLevel [Byte0]: 74
7925 00:26:08.317524 [Byte1]: 74
7926 00:26:08.322121
7927 00:26:08.322192 Set Vref, RX VrefLevel [Byte0]: 75
7928 00:26:08.325384 [Byte1]: 75
7929 00:26:08.329777
7930 00:26:08.329850 Set Vref, RX VrefLevel [Byte0]: 76
7931 00:26:08.332924 [Byte1]: 76
7932 00:26:08.337483
7933 00:26:08.337556 Final RX Vref Byte 0 = 65 to rank0
7934 00:26:08.340325 Final RX Vref Byte 1 = 58 to rank0
7935 00:26:08.343872 Final RX Vref Byte 0 = 65 to rank1
7936 00:26:08.347358 Final RX Vref Byte 1 = 58 to rank1==
7937 00:26:08.350250 Dram Type= 6, Freq= 0, CH_0, rank 0
7938 00:26:08.357261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7939 00:26:08.357334 ==
7940 00:26:08.357396 DQS Delay:
7941 00:26:08.360193 DQS0 = 0, DQS1 = 0
7942 00:26:08.360286 DQM Delay:
7943 00:26:08.360379 DQM0 = 126, DQM1 = 119
7944 00:26:08.363666 DQ Delay:
7945 00:26:08.366895 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7946 00:26:08.370112 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7947 00:26:08.373344 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7948 00:26:08.376849 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
7949 00:26:08.376918
7950 00:26:08.376978
7951 00:26:08.377032
7952 00:26:08.379888 [DramC_TX_OE_Calibration] TA2
7953 00:26:08.383373 Original DQ_B0 (3 6) =30, OEN = 27
7954 00:26:08.386950 Original DQ_B1 (3 6) =30, OEN = 27
7955 00:26:08.389921 24, 0x0, End_B0=24 End_B1=24
7956 00:26:08.389988 25, 0x0, End_B0=25 End_B1=25
7957 00:26:08.393511 26, 0x0, End_B0=26 End_B1=26
7958 00:26:08.396508 27, 0x0, End_B0=27 End_B1=27
7959 00:26:08.399982 28, 0x0, End_B0=28 End_B1=28
7960 00:26:08.403471 29, 0x0, End_B0=29 End_B1=29
7961 00:26:08.403568 30, 0x0, End_B0=30 End_B1=30
7962 00:26:08.406933 31, 0x4141, End_B0=30 End_B1=30
7963 00:26:08.409910 Byte0 end_step=30 best_step=27
7964 00:26:08.413285 Byte1 end_step=30 best_step=27
7965 00:26:08.416570 Byte0 TX OE(2T, 0.5T) = (3, 3)
7966 00:26:08.419683 Byte1 TX OE(2T, 0.5T) = (3, 3)
7967 00:26:08.419748
7968 00:26:08.419803
7969 00:26:08.426464 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
7970 00:26:08.430118 CH0 RK0: MR19=303, MR18=1414
7971 00:26:08.436366 CH0_RK0: MR19=0x303, MR18=0x1414, DQSOSC=399, MR23=63, INC=23, DEC=15
7972 00:26:08.436442
7973 00:26:08.439631 ----->DramcWriteLeveling(PI) begin...
7974 00:26:08.439700 ==
7975 00:26:08.443315 Dram Type= 6, Freq= 0, CH_0, rank 1
7976 00:26:08.446391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7977 00:26:08.446476 ==
7978 00:26:08.449835 Write leveling (Byte 0): 33 => 33
7979 00:26:08.453281 Write leveling (Byte 1): 30 => 30
7980 00:26:08.456293 DramcWriteLeveling(PI) end<-----
7981 00:26:08.456366
7982 00:26:08.456422 ==
7983 00:26:08.459786 Dram Type= 6, Freq= 0, CH_0, rank 1
7984 00:26:08.463242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7985 00:26:08.463311 ==
7986 00:26:08.466082 [Gating] SW mode calibration
7987 00:26:08.473031 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7988 00:26:08.479650 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7989 00:26:08.483070 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7990 00:26:08.489437 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7991 00:26:08.493088 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 00:26:08.495958 1 4 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
7993 00:26:08.502427 1 4 16 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
7994 00:26:08.505811 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7995 00:26:08.509446 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 00:26:08.516016 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 00:26:08.518964 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 00:26:08.522515 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 00:26:08.529075 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8000 00:26:08.532333 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 1)
8001 00:26:08.535799 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8002 00:26:08.542245 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8003 00:26:08.545295 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 00:26:08.548448 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 00:26:08.555103 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 00:26:08.558312 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 00:26:08.562045 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8008 00:26:08.568768 1 6 12 | B1->B0 | 2323 4242 | 0 1 | (0 0) (0 0)
8009 00:26:08.571584 1 6 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
8010 00:26:08.575096 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 00:26:08.581616 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 00:26:08.584945 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 00:26:08.588267 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 00:26:08.595152 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 00:26:08.598214 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 00:26:08.601691 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8017 00:26:08.608050 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8018 00:26:08.611492 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8019 00:26:08.614873 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 00:26:08.621296 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 00:26:08.624873 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 00:26:08.628348 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 00:26:08.634731 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 00:26:08.638492 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 00:26:08.641295 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 00:26:08.644849 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 00:26:08.651617 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 00:26:08.654494 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 00:26:08.657984 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 00:26:08.665012 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 00:26:08.667811 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 00:26:08.671006 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8033 00:26:08.677687 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8034 00:26:08.681252 Total UI for P1: 0, mck2ui 16
8035 00:26:08.684785 best dqsien dly found for B0: ( 1, 9, 12)
8036 00:26:08.687695 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8037 00:26:08.691013 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 00:26:08.694498 Total UI for P1: 0, mck2ui 16
8039 00:26:08.698236 best dqsien dly found for B1: ( 1, 9, 18)
8040 00:26:08.701227 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8041 00:26:08.704221 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8042 00:26:08.704291
8043 00:26:08.711451 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8044 00:26:08.714428 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8045 00:26:08.717404 [Gating] SW calibration Done
8046 00:26:08.717477 ==
8047 00:26:08.720956 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 00:26:08.724225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 00:26:08.724331 ==
8050 00:26:08.724431 RX Vref Scan: 0
8051 00:26:08.727781
8052 00:26:08.727868 RX Vref 0 -> 0, step: 1
8053 00:26:08.727952
8054 00:26:08.730767 RX Delay 0 -> 252, step: 8
8055 00:26:08.734213 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8056 00:26:08.737691 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8057 00:26:08.743810 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8058 00:26:08.747512 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8059 00:26:08.750446 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8060 00:26:08.754002 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8061 00:26:08.757292 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8062 00:26:08.764178 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8063 00:26:08.767041 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8064 00:26:08.770633 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8065 00:26:08.773907 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8066 00:26:08.776954 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8067 00:26:08.783758 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8068 00:26:08.787367 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8069 00:26:08.790108 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8070 00:26:08.793350 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8071 00:26:08.793420 ==
8072 00:26:08.796839 Dram Type= 6, Freq= 0, CH_0, rank 1
8073 00:26:08.803548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8074 00:26:08.803635 ==
8075 00:26:08.803714 DQS Delay:
8076 00:26:08.806854 DQS0 = 0, DQS1 = 0
8077 00:26:08.806940 DQM Delay:
8078 00:26:08.810089 DQM0 = 127, DQM1 = 122
8079 00:26:08.810173 DQ Delay:
8080 00:26:08.813351 DQ0 =127, DQ1 =127, DQ2 =123, DQ3 =123
8081 00:26:08.816881 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8082 00:26:08.819798 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8083 00:26:08.823451 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8084 00:26:08.823525
8085 00:26:08.823592
8086 00:26:08.823649 ==
8087 00:26:08.826413 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 00:26:08.833345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 00:26:08.833431 ==
8090 00:26:08.833508
8091 00:26:08.833568
8092 00:26:08.833626 TX Vref Scan disable
8093 00:26:08.836867 == TX Byte 0 ==
8094 00:26:08.839857 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8095 00:26:08.846817 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8096 00:26:08.846894 == TX Byte 1 ==
8097 00:26:08.849702 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8098 00:26:08.856722 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8099 00:26:08.856805 ==
8100 00:26:08.860025 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 00:26:08.862793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 00:26:08.862865 ==
8103 00:26:08.877030
8104 00:26:08.880529 TX Vref early break, caculate TX vref
8105 00:26:08.883389 TX Vref=16, minBit 0, minWin=22, winSum=369
8106 00:26:08.886796 TX Vref=18, minBit 0, minWin=22, winSum=374
8107 00:26:08.890227 TX Vref=20, minBit 0, minWin=23, winSum=385
8108 00:26:08.893336 TX Vref=22, minBit 0, minWin=23, winSum=397
8109 00:26:08.896729 TX Vref=24, minBit 0, minWin=25, winSum=408
8110 00:26:08.903287 TX Vref=26, minBit 0, minWin=25, winSum=410
8111 00:26:08.907066 TX Vref=28, minBit 1, minWin=25, winSum=415
8112 00:26:08.910041 TX Vref=30, minBit 1, minWin=25, winSum=410
8113 00:26:08.913036 TX Vref=32, minBit 3, minWin=24, winSum=403
8114 00:26:08.916258 TX Vref=34, minBit 13, minWin=23, winSum=395
8115 00:26:08.923223 TX Vref=36, minBit 13, minWin=23, winSum=387
8116 00:26:08.926615 [TxChooseVref] Worse bit 1, Min win 25, Win sum 415, Final Vref 28
8117 00:26:08.926716
8118 00:26:08.929548 Final TX Range 0 Vref 28
8119 00:26:08.929625
8120 00:26:08.929688 ==
8121 00:26:08.932987 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 00:26:08.936655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 00:26:08.939634 ==
8124 00:26:08.939701
8125 00:26:08.939760
8126 00:26:08.939814 TX Vref Scan disable
8127 00:26:08.946102 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8128 00:26:08.946210 == TX Byte 0 ==
8129 00:26:08.949673 u2DelayCellOfst[0]=11 cells (3 PI)
8130 00:26:08.953137 u2DelayCellOfst[1]=15 cells (4 PI)
8131 00:26:08.956017 u2DelayCellOfst[2]=11 cells (3 PI)
8132 00:26:08.959455 u2DelayCellOfst[3]=11 cells (3 PI)
8133 00:26:08.962596 u2DelayCellOfst[4]=7 cells (2 PI)
8134 00:26:08.966010 u2DelayCellOfst[5]=0 cells (0 PI)
8135 00:26:08.969406 u2DelayCellOfst[6]=18 cells (5 PI)
8136 00:26:08.972562 u2DelayCellOfst[7]=18 cells (5 PI)
8137 00:26:08.976121 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8138 00:26:08.979552 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8139 00:26:08.982639 == TX Byte 1 ==
8140 00:26:08.985892 u2DelayCellOfst[8]=0 cells (0 PI)
8141 00:26:08.989214 u2DelayCellOfst[9]=0 cells (0 PI)
8142 00:26:08.992654 u2DelayCellOfst[10]=3 cells (1 PI)
8143 00:26:08.995602 u2DelayCellOfst[11]=3 cells (1 PI)
8144 00:26:08.999120 u2DelayCellOfst[12]=11 cells (3 PI)
8145 00:26:09.002250 u2DelayCellOfst[13]=11 cells (3 PI)
8146 00:26:09.005443 u2DelayCellOfst[14]=15 cells (4 PI)
8147 00:26:09.005512 u2DelayCellOfst[15]=11 cells (3 PI)
8148 00:26:09.012129 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8149 00:26:09.015676 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8150 00:26:09.019262 DramC Write-DBI on
8151 00:26:09.019339 ==
8152 00:26:09.022146 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 00:26:09.025673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 00:26:09.025750 ==
8155 00:26:09.025811
8156 00:26:09.025865
8157 00:26:09.028999 TX Vref Scan disable
8158 00:26:09.029077 == TX Byte 0 ==
8159 00:26:09.035371 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8160 00:26:09.035450 == TX Byte 1 ==
8161 00:26:09.038842 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8162 00:26:09.042015 DramC Write-DBI off
8163 00:26:09.042107
8164 00:26:09.042171 [DATLAT]
8165 00:26:09.045420 Freq=1600, CH0 RK1
8166 00:26:09.045492
8167 00:26:09.045563 DATLAT Default: 0xf
8168 00:26:09.048871 0, 0xFFFF, sum = 0
8169 00:26:09.048994 1, 0xFFFF, sum = 0
8170 00:26:09.051943 2, 0xFFFF, sum = 0
8171 00:26:09.052039 3, 0xFFFF, sum = 0
8172 00:26:09.055488 4, 0xFFFF, sum = 0
8173 00:26:09.058467 5, 0xFFFF, sum = 0
8174 00:26:09.058563 6, 0xFFFF, sum = 0
8175 00:26:09.062006 7, 0xFFFF, sum = 0
8176 00:26:09.062077 8, 0xFFFF, sum = 0
8177 00:26:09.065515 9, 0xFFFF, sum = 0
8178 00:26:09.065597 10, 0xFFFF, sum = 0
8179 00:26:09.068752 11, 0xFFFF, sum = 0
8180 00:26:09.068842 12, 0xFFFF, sum = 0
8181 00:26:09.072066 13, 0xCFFF, sum = 0
8182 00:26:09.072141 14, 0x0, sum = 1
8183 00:26:09.075507 15, 0x0, sum = 2
8184 00:26:09.075580 16, 0x0, sum = 3
8185 00:26:09.078668 17, 0x0, sum = 4
8186 00:26:09.078740 best_step = 15
8187 00:26:09.078814
8188 00:26:09.078870 ==
8189 00:26:09.082187 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 00:26:09.085574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 00:26:09.088749 ==
8192 00:26:09.088821 RX Vref Scan: 0
8193 00:26:09.088908
8194 00:26:09.091957 RX Vref 0 -> 0, step: 1
8195 00:26:09.092066
8196 00:26:09.092152 RX Delay 3 -> 252, step: 4
8197 00:26:09.099071 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8198 00:26:09.102174 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8199 00:26:09.105714 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8200 00:26:09.109153 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8201 00:26:09.112268 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8202 00:26:09.119054 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8203 00:26:09.122069 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8204 00:26:09.125541 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8205 00:26:09.129044 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8206 00:26:09.132543 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8207 00:26:09.139075 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8208 00:26:09.142603 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8209 00:26:09.145365 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8210 00:26:09.149093 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8211 00:26:09.155723 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8212 00:26:09.158740 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8213 00:26:09.158815 ==
8214 00:26:09.162313 Dram Type= 6, Freq= 0, CH_0, rank 1
8215 00:26:09.165324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 00:26:09.165410 ==
8217 00:26:09.165494 DQS Delay:
8218 00:26:09.168904 DQS0 = 0, DQS1 = 0
8219 00:26:09.169006 DQM Delay:
8220 00:26:09.171896 DQM0 = 124, DQM1 = 118
8221 00:26:09.171986 DQ Delay:
8222 00:26:09.175355 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8223 00:26:09.178517 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8224 00:26:09.182189 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
8225 00:26:09.188813 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8226 00:26:09.188920
8227 00:26:09.188983
8228 00:26:09.189043
8229 00:26:09.191945 [DramC_TX_OE_Calibration] TA2
8230 00:26:09.192017 Original DQ_B0 (3 6) =30, OEN = 27
8231 00:26:09.194951 Original DQ_B1 (3 6) =30, OEN = 27
8232 00:26:09.198424 24, 0x0, End_B0=24 End_B1=24
8233 00:26:09.201793 25, 0x0, End_B0=25 End_B1=25
8234 00:26:09.205280 26, 0x0, End_B0=26 End_B1=26
8235 00:26:09.208705 27, 0x0, End_B0=27 End_B1=27
8236 00:26:09.208798 28, 0x0, End_B0=28 End_B1=28
8237 00:26:09.211675 29, 0x0, End_B0=29 End_B1=29
8238 00:26:09.215061 30, 0x0, End_B0=30 End_B1=30
8239 00:26:09.218229 31, 0x4141, End_B0=30 End_B1=30
8240 00:26:09.221495 Byte0 end_step=30 best_step=27
8241 00:26:09.221568 Byte1 end_step=30 best_step=27
8242 00:26:09.224999 Byte0 TX OE(2T, 0.5T) = (3, 3)
8243 00:26:09.228324 Byte1 TX OE(2T, 0.5T) = (3, 3)
8244 00:26:09.228402
8245 00:26:09.228462
8246 00:26:09.238183 [DQSOSCAuto] RK1, (LSB)MR18= 0x2311, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8247 00:26:09.238262 CH0 RK1: MR19=303, MR18=2311
8248 00:26:09.244757 CH0_RK1: MR19=0x303, MR18=0x2311, DQSOSC=392, MR23=63, INC=24, DEC=16
8249 00:26:09.248652 [RxdqsGatingPostProcess] freq 1600
8250 00:26:09.254986 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8251 00:26:09.258198 best DQS0 dly(2T, 0.5T) = (1, 1)
8252 00:26:09.261619 best DQS1 dly(2T, 0.5T) = (1, 1)
8253 00:26:09.264986 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8254 00:26:09.268525 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8255 00:26:09.268642 best DQS0 dly(2T, 0.5T) = (1, 1)
8256 00:26:09.271622 best DQS1 dly(2T, 0.5T) = (1, 1)
8257 00:26:09.275190 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8258 00:26:09.278274 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8259 00:26:09.281743 Pre-setting of DQS Precalculation
8260 00:26:09.287838 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8261 00:26:09.287986 ==
8262 00:26:09.291381 Dram Type= 6, Freq= 0, CH_1, rank 0
8263 00:26:09.294517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 00:26:09.294691 ==
8265 00:26:09.301535 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8266 00:26:09.304543 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8267 00:26:09.307846 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8268 00:26:09.314447 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8269 00:26:09.323605 [CA 0] Center 41 (12~70) winsize 59
8270 00:26:09.326872 [CA 1] Center 42 (12~72) winsize 61
8271 00:26:09.330063 [CA 2] Center 37 (8~66) winsize 59
8272 00:26:09.333577 [CA 3] Center 36 (7~66) winsize 60
8273 00:26:09.336537 [CA 4] Center 37 (8~67) winsize 60
8274 00:26:09.340003 [CA 5] Center 36 (7~65) winsize 59
8275 00:26:09.340170
8276 00:26:09.343467 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8277 00:26:09.343570
8278 00:26:09.346333 [CATrainingPosCal] consider 1 rank data
8279 00:26:09.349836 u2DelayCellTimex100 = 258/100 ps
8280 00:26:09.356249 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8281 00:26:09.359784 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8282 00:26:09.363101 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8283 00:26:09.366458 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8284 00:26:09.369801 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8285 00:26:09.373231 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8286 00:26:09.373368
8287 00:26:09.376286 CA PerBit enable=1, Macro0, CA PI delay=36
8288 00:26:09.376410
8289 00:26:09.379744 [CBTSetCACLKResult] CA Dly = 36
8290 00:26:09.382750 CS Dly: 9 (0~40)
8291 00:26:09.386253 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8292 00:26:09.389209 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8293 00:26:09.389350 ==
8294 00:26:09.392668 Dram Type= 6, Freq= 0, CH_1, rank 1
8295 00:26:09.399512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8296 00:26:09.399642 ==
8297 00:26:09.402603 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8298 00:26:09.406208 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8299 00:26:09.412560 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8300 00:26:09.418958 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8301 00:26:09.426801 [CA 0] Center 41 (12~71) winsize 60
8302 00:26:09.429775 [CA 1] Center 42 (12~72) winsize 61
8303 00:26:09.433568 [CA 2] Center 38 (9~68) winsize 60
8304 00:26:09.436581 [CA 3] Center 36 (7~66) winsize 60
8305 00:26:09.440112 [CA 4] Center 38 (8~68) winsize 61
8306 00:26:09.443179 [CA 5] Center 37 (7~67) winsize 61
8307 00:26:09.443262
8308 00:26:09.446635 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8309 00:26:09.446712
8310 00:26:09.449527 [CATrainingPosCal] consider 2 rank data
8311 00:26:09.453181 u2DelayCellTimex100 = 258/100 ps
8312 00:26:09.456690 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8313 00:26:09.463282 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8314 00:26:09.466140 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8315 00:26:09.469619 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8316 00:26:09.472935 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8317 00:26:09.476460 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8318 00:26:09.476531
8319 00:26:09.479252 CA PerBit enable=1, Macro0, CA PI delay=36
8320 00:26:09.479327
8321 00:26:09.482744 [CBTSetCACLKResult] CA Dly = 36
8322 00:26:09.486436 CS Dly: 10 (0~43)
8323 00:26:09.489397 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8324 00:26:09.492825 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8325 00:26:09.492899
8326 00:26:09.495819 ----->DramcWriteLeveling(PI) begin...
8327 00:26:09.495889 ==
8328 00:26:09.499388 Dram Type= 6, Freq= 0, CH_1, rank 0
8329 00:26:09.505775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8330 00:26:09.505915 ==
8331 00:26:09.509304 Write leveling (Byte 0): 24 => 24
8332 00:26:09.512445 Write leveling (Byte 1): 29 => 29
8333 00:26:09.512533 DramcWriteLeveling(PI) end<-----
8334 00:26:09.512626
8335 00:26:09.516132 ==
8336 00:26:09.519608 Dram Type= 6, Freq= 0, CH_1, rank 0
8337 00:26:09.522650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 00:26:09.522724 ==
8339 00:26:09.525996 [Gating] SW mode calibration
8340 00:26:09.532494 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8341 00:26:09.535631 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8342 00:26:09.542541 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 00:26:09.545415 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 00:26:09.548821 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 00:26:09.555229 1 4 12 | B1->B0 | 2525 2322 | 0 1 | (0 0) (0 0)
8346 00:26:09.558882 1 4 16 | B1->B0 | 3434 3333 | 1 1 | (0 0) (1 1)
8347 00:26:09.562440 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 00:26:09.568890 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 00:26:09.572269 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 00:26:09.575489 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 00:26:09.581977 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 00:26:09.585386 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 00:26:09.588423 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8354 00:26:09.594924 1 5 16 | B1->B0 | 2525 2525 | 0 0 | (1 0) (1 0)
8355 00:26:09.598389 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8356 00:26:09.601988 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 00:26:09.608419 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 00:26:09.611900 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 00:26:09.614757 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 00:26:09.621492 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 00:26:09.624663 1 6 12 | B1->B0 | 2b2b 2929 | 0 0 | (0 0) (0 0)
8362 00:26:09.628155 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 00:26:09.634518 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 00:26:09.637882 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 00:26:09.641033 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 00:26:09.648232 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 00:26:09.651596 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 00:26:09.654843 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 00:26:09.661320 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 00:26:09.664606 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8371 00:26:09.667465 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8372 00:26:09.674390 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 00:26:09.677785 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 00:26:09.681247 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 00:26:09.687278 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 00:26:09.690751 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 00:26:09.694406 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 00:26:09.700819 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 00:26:09.704319 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 00:26:09.707734 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 00:26:09.714137 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 00:26:09.717605 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 00:26:09.720597 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 00:26:09.727010 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 00:26:09.730863 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8386 00:26:09.733812 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8387 00:26:09.740846 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8388 00:26:09.740918 Total UI for P1: 0, mck2ui 16
8389 00:26:09.747260 best dqsien dly found for B0: ( 1, 9, 14)
8390 00:26:09.750434 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 00:26:09.753566 Total UI for P1: 0, mck2ui 16
8392 00:26:09.756816 best dqsien dly found for B1: ( 1, 9, 18)
8393 00:26:09.760432 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8394 00:26:09.763450 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8395 00:26:09.763514
8396 00:26:09.766854 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8397 00:26:09.770092 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8398 00:26:09.773676 [Gating] SW calibration Done
8399 00:26:09.773783 ==
8400 00:26:09.776856 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 00:26:09.780079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 00:26:09.783447 ==
8403 00:26:09.783543 RX Vref Scan: 0
8404 00:26:09.783628
8405 00:26:09.786663 RX Vref 0 -> 0, step: 1
8406 00:26:09.786761
8407 00:26:09.786857 RX Delay 0 -> 252, step: 8
8408 00:26:09.793285 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8409 00:26:09.796599 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8410 00:26:09.800121 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8411 00:26:09.803218 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8412 00:26:09.809711 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8413 00:26:09.813385 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8414 00:26:09.816315 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8415 00:26:09.819819 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8416 00:26:09.823371 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8417 00:26:09.829717 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8418 00:26:09.832776 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8419 00:26:09.836267 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8420 00:26:09.839532 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8421 00:26:09.842767 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8422 00:26:09.849431 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8423 00:26:09.852878 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8424 00:26:09.853003 ==
8425 00:26:09.856231 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 00:26:09.859857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 00:26:09.859950 ==
8428 00:26:09.862853 DQS Delay:
8429 00:26:09.862944 DQS0 = 0, DQS1 = 0
8430 00:26:09.863003 DQM Delay:
8431 00:26:09.866284 DQM0 = 131, DQM1 = 126
8432 00:26:09.866388 DQ Delay:
8433 00:26:09.869826 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8434 00:26:09.872710 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8435 00:26:09.876168 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8436 00:26:09.882622 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8437 00:26:09.882713
8438 00:26:09.882772
8439 00:26:09.882826 ==
8440 00:26:09.886313 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 00:26:09.889399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 00:26:09.889476 ==
8443 00:26:09.889536
8444 00:26:09.889590
8445 00:26:09.892582 TX Vref Scan disable
8446 00:26:09.892666 == TX Byte 0 ==
8447 00:26:09.899383 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8448 00:26:09.902795 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8449 00:26:09.902872 == TX Byte 1 ==
8450 00:26:09.909501 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8451 00:26:09.912855 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8452 00:26:09.912935 ==
8453 00:26:09.915810 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 00:26:09.919303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 00:26:09.919380 ==
8456 00:26:09.934771
8457 00:26:09.937768 TX Vref early break, caculate TX vref
8458 00:26:09.941378 TX Vref=16, minBit 11, minWin=20, winSum=356
8459 00:26:09.944281 TX Vref=18, minBit 8, minWin=21, winSum=368
8460 00:26:09.947652 TX Vref=20, minBit 1, minWin=22, winSum=378
8461 00:26:09.950904 TX Vref=22, minBit 8, minWin=23, winSum=388
8462 00:26:09.954657 TX Vref=24, minBit 9, minWin=24, winSum=398
8463 00:26:09.960873 TX Vref=26, minBit 11, minWin=24, winSum=407
8464 00:26:09.964345 TX Vref=28, minBit 0, minWin=25, winSum=415
8465 00:26:09.967555 TX Vref=30, minBit 1, minWin=24, winSum=409
8466 00:26:09.971043 TX Vref=32, minBit 1, minWin=23, winSum=403
8467 00:26:09.974345 TX Vref=34, minBit 0, minWin=23, winSum=394
8468 00:26:09.980890 TX Vref=36, minBit 1, minWin=22, winSum=378
8469 00:26:09.983937 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 28
8470 00:26:09.984043
8471 00:26:09.987232 Final TX Range 0 Vref 28
8472 00:26:09.987314
8473 00:26:09.987375 ==
8474 00:26:09.990759 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 00:26:09.994105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 00:26:09.994208 ==
8477 00:26:09.996970
8478 00:26:09.997082
8479 00:26:09.997185 TX Vref Scan disable
8480 00:26:10.003688 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8481 00:26:10.003818 == TX Byte 0 ==
8482 00:26:10.007148 u2DelayCellOfst[0]=18 cells (5 PI)
8483 00:26:10.010583 u2DelayCellOfst[1]=15 cells (4 PI)
8484 00:26:10.013618 u2DelayCellOfst[2]=0 cells (0 PI)
8485 00:26:10.017252 u2DelayCellOfst[3]=7 cells (2 PI)
8486 00:26:10.020416 u2DelayCellOfst[4]=7 cells (2 PI)
8487 00:26:10.023680 u2DelayCellOfst[5]=22 cells (6 PI)
8488 00:26:10.027348 u2DelayCellOfst[6]=22 cells (6 PI)
8489 00:26:10.030252 u2DelayCellOfst[7]=7 cells (2 PI)
8490 00:26:10.033647 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8491 00:26:10.037324 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8492 00:26:10.040276 == TX Byte 1 ==
8493 00:26:10.043598 u2DelayCellOfst[8]=0 cells (0 PI)
8494 00:26:10.047273 u2DelayCellOfst[9]=11 cells (3 PI)
8495 00:26:10.050600 u2DelayCellOfst[10]=18 cells (5 PI)
8496 00:26:10.053516 u2DelayCellOfst[11]=11 cells (3 PI)
8497 00:26:10.056905 u2DelayCellOfst[12]=18 cells (5 PI)
8498 00:26:10.057012 u2DelayCellOfst[13]=26 cells (7 PI)
8499 00:26:10.060207 u2DelayCellOfst[14]=22 cells (6 PI)
8500 00:26:10.063422 u2DelayCellOfst[15]=22 cells (6 PI)
8501 00:26:10.070175 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8502 00:26:10.073698 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8503 00:26:10.073788 DramC Write-DBI on
8504 00:26:10.076897 ==
8505 00:26:10.079954 Dram Type= 6, Freq= 0, CH_1, rank 0
8506 00:26:10.083321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8507 00:26:10.083404 ==
8508 00:26:10.083465
8509 00:26:10.083520
8510 00:26:10.086206 TX Vref Scan disable
8511 00:26:10.086269 == TX Byte 0 ==
8512 00:26:10.092898 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8513 00:26:10.092977 == TX Byte 1 ==
8514 00:26:10.096817 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8515 00:26:10.099924 DramC Write-DBI off
8516 00:26:10.100001
8517 00:26:10.100061 [DATLAT]
8518 00:26:10.103379 Freq=1600, CH1 RK0
8519 00:26:10.103457
8520 00:26:10.103516 DATLAT Default: 0xf
8521 00:26:10.106243 0, 0xFFFF, sum = 0
8522 00:26:10.106351 1, 0xFFFF, sum = 0
8523 00:26:10.109817 2, 0xFFFF, sum = 0
8524 00:26:10.109919 3, 0xFFFF, sum = 0
8525 00:26:10.112823 4, 0xFFFF, sum = 0
8526 00:26:10.116206 5, 0xFFFF, sum = 0
8527 00:26:10.116310 6, 0xFFFF, sum = 0
8528 00:26:10.119835 7, 0xFFFF, sum = 0
8529 00:26:10.119926 8, 0xFFFF, sum = 0
8530 00:26:10.123025 9, 0xFFFF, sum = 0
8531 00:26:10.123127 10, 0xFFFF, sum = 0
8532 00:26:10.126458 11, 0xFFFF, sum = 0
8533 00:26:10.126559 12, 0xFFFF, sum = 0
8534 00:26:10.129594 13, 0x8FFF, sum = 0
8535 00:26:10.129681 14, 0x0, sum = 1
8536 00:26:10.133016 15, 0x0, sum = 2
8537 00:26:10.133127 16, 0x0, sum = 3
8538 00:26:10.136257 17, 0x0, sum = 4
8539 00:26:10.136361 best_step = 15
8540 00:26:10.136458
8541 00:26:10.136542 ==
8542 00:26:10.139622 Dram Type= 6, Freq= 0, CH_1, rank 0
8543 00:26:10.142572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8544 00:26:10.146100 ==
8545 00:26:10.146188 RX Vref Scan: 1
8546 00:26:10.146251
8547 00:26:10.149619 Set Vref Range= 24 -> 127
8548 00:26:10.149709
8549 00:26:10.152517 RX Vref 24 -> 127, step: 1
8550 00:26:10.152614
8551 00:26:10.152694 RX Delay 11 -> 252, step: 4
8552 00:26:10.152751
8553 00:26:10.155942 Set Vref, RX VrefLevel [Byte0]: 24
8554 00:26:10.158987 [Byte1]: 24
8555 00:26:10.163190
8556 00:26:10.163267 Set Vref, RX VrefLevel [Byte0]: 25
8557 00:26:10.166172 [Byte1]: 25
8558 00:26:10.170555
8559 00:26:10.170633 Set Vref, RX VrefLevel [Byte0]: 26
8560 00:26:10.174255 [Byte1]: 26
8561 00:26:10.178068
8562 00:26:10.178148 Set Vref, RX VrefLevel [Byte0]: 27
8563 00:26:10.181386 [Byte1]: 27
8564 00:26:10.185800
8565 00:26:10.185879 Set Vref, RX VrefLevel [Byte0]: 28
8566 00:26:10.189389 [Byte1]: 28
8567 00:26:10.193526
8568 00:26:10.193603 Set Vref, RX VrefLevel [Byte0]: 29
8569 00:26:10.197136 [Byte1]: 29
8570 00:26:10.201407
8571 00:26:10.201486 Set Vref, RX VrefLevel [Byte0]: 30
8572 00:26:10.204750 [Byte1]: 30
8573 00:26:10.208871
8574 00:26:10.208950 Set Vref, RX VrefLevel [Byte0]: 31
8575 00:26:10.211770 [Byte1]: 31
8576 00:26:10.216447
8577 00:26:10.216572 Set Vref, RX VrefLevel [Byte0]: 32
8578 00:26:10.219416 [Byte1]: 32
8579 00:26:10.224202
8580 00:26:10.224299 Set Vref, RX VrefLevel [Byte0]: 33
8581 00:26:10.227154 [Byte1]: 33
8582 00:26:10.231685
8583 00:26:10.231790 Set Vref, RX VrefLevel [Byte0]: 34
8584 00:26:10.234929 [Byte1]: 34
8585 00:26:10.239158
8586 00:26:10.239237 Set Vref, RX VrefLevel [Byte0]: 35
8587 00:26:10.242398 [Byte1]: 35
8588 00:26:10.246773
8589 00:26:10.246873 Set Vref, RX VrefLevel [Byte0]: 36
8590 00:26:10.250022 [Byte1]: 36
8591 00:26:10.254635
8592 00:26:10.254736 Set Vref, RX VrefLevel [Byte0]: 37
8593 00:26:10.257447 [Byte1]: 37
8594 00:26:10.262083
8595 00:26:10.262155 Set Vref, RX VrefLevel [Byte0]: 38
8596 00:26:10.265538 [Byte1]: 38
8597 00:26:10.269597
8598 00:26:10.269668 Set Vref, RX VrefLevel [Byte0]: 39
8599 00:26:10.273060 [Byte1]: 39
8600 00:26:10.277238
8601 00:26:10.277316 Set Vref, RX VrefLevel [Byte0]: 40
8602 00:26:10.280483 [Byte1]: 40
8603 00:26:10.284760
8604 00:26:10.284855 Set Vref, RX VrefLevel [Byte0]: 41
8605 00:26:10.288245 [Byte1]: 41
8606 00:26:10.292663
8607 00:26:10.292734 Set Vref, RX VrefLevel [Byte0]: 42
8608 00:26:10.295852 [Byte1]: 42
8609 00:26:10.300193
8610 00:26:10.300267 Set Vref, RX VrefLevel [Byte0]: 43
8611 00:26:10.303249 [Byte1]: 43
8612 00:26:10.307794
8613 00:26:10.307897 Set Vref, RX VrefLevel [Byte0]: 44
8614 00:26:10.311249 [Byte1]: 44
8615 00:26:10.315527
8616 00:26:10.315605 Set Vref, RX VrefLevel [Byte0]: 45
8617 00:26:10.318866 [Byte1]: 45
8618 00:26:10.323043
8619 00:26:10.323120 Set Vref, RX VrefLevel [Byte0]: 46
8620 00:26:10.325951 [Byte1]: 46
8621 00:26:10.330781
8622 00:26:10.330859 Set Vref, RX VrefLevel [Byte0]: 47
8623 00:26:10.333671 [Byte1]: 47
8624 00:26:10.337896
8625 00:26:10.337973 Set Vref, RX VrefLevel [Byte0]: 48
8626 00:26:10.341347 [Byte1]: 48
8627 00:26:10.345938
8628 00:26:10.346040 Set Vref, RX VrefLevel [Byte0]: 49
8629 00:26:10.349242 [Byte1]: 49
8630 00:26:10.353713
8631 00:26:10.353793 Set Vref, RX VrefLevel [Byte0]: 50
8632 00:26:10.356528 [Byte1]: 50
8633 00:26:10.360950
8634 00:26:10.361047 Set Vref, RX VrefLevel [Byte0]: 51
8635 00:26:10.364265 [Byte1]: 51
8636 00:26:10.368748
8637 00:26:10.368826 Set Vref, RX VrefLevel [Byte0]: 52
8638 00:26:10.371856 [Byte1]: 52
8639 00:26:10.376072
8640 00:26:10.376182 Set Vref, RX VrefLevel [Byte0]: 53
8641 00:26:10.379615 [Byte1]: 53
8642 00:26:10.383724
8643 00:26:10.383795 Set Vref, RX VrefLevel [Byte0]: 54
8644 00:26:10.387029 [Byte1]: 54
8645 00:26:10.391356
8646 00:26:10.391426 Set Vref, RX VrefLevel [Byte0]: 55
8647 00:26:10.394673 [Byte1]: 55
8648 00:26:10.399260
8649 00:26:10.399354 Set Vref, RX VrefLevel [Byte0]: 56
8650 00:26:10.402448 [Byte1]: 56
8651 00:26:10.406842
8652 00:26:10.406944 Set Vref, RX VrefLevel [Byte0]: 57
8653 00:26:10.409759 [Byte1]: 57
8654 00:26:10.414488
8655 00:26:10.414561 Set Vref, RX VrefLevel [Byte0]: 58
8656 00:26:10.417410 [Byte1]: 58
8657 00:26:10.421840
8658 00:26:10.421911 Set Vref, RX VrefLevel [Byte0]: 59
8659 00:26:10.424977 [Byte1]: 59
8660 00:26:10.429581
8661 00:26:10.429653 Set Vref, RX VrefLevel [Byte0]: 60
8662 00:26:10.432540 [Byte1]: 60
8663 00:26:10.437348
8664 00:26:10.437427 Set Vref, RX VrefLevel [Byte0]: 61
8665 00:26:10.440347 [Byte1]: 61
8666 00:26:10.444937
8667 00:26:10.445015 Set Vref, RX VrefLevel [Byte0]: 62
8668 00:26:10.447905 [Byte1]: 62
8669 00:26:10.452275
8670 00:26:10.452370 Set Vref, RX VrefLevel [Byte0]: 63
8671 00:26:10.455561 [Byte1]: 63
8672 00:26:10.459840
8673 00:26:10.459911 Set Vref, RX VrefLevel [Byte0]: 64
8674 00:26:10.463304 [Byte1]: 64
8675 00:26:10.467324
8676 00:26:10.467398 Set Vref, RX VrefLevel [Byte0]: 65
8677 00:26:10.470657 [Byte1]: 65
8678 00:26:10.475208
8679 00:26:10.475347 Set Vref, RX VrefLevel [Byte0]: 66
8680 00:26:10.478642 [Byte1]: 66
8681 00:26:10.482779
8682 00:26:10.482900 Set Vref, RX VrefLevel [Byte0]: 67
8683 00:26:10.486067 [Byte1]: 67
8684 00:26:10.490615
8685 00:26:10.490726 Set Vref, RX VrefLevel [Byte0]: 68
8686 00:26:10.493503 [Byte1]: 68
8687 00:26:10.497921
8688 00:26:10.498050 Set Vref, RX VrefLevel [Byte0]: 69
8689 00:26:10.501037 [Byte1]: 69
8690 00:26:10.505736
8691 00:26:10.505835 Set Vref, RX VrefLevel [Byte0]: 70
8692 00:26:10.509180 [Byte1]: 70
8693 00:26:10.513216
8694 00:26:10.513294 Final RX Vref Byte 0 = 58 to rank0
8695 00:26:10.516681 Final RX Vref Byte 1 = 53 to rank0
8696 00:26:10.519607 Final RX Vref Byte 0 = 58 to rank1
8697 00:26:10.523133 Final RX Vref Byte 1 = 53 to rank1==
8698 00:26:10.526521 Dram Type= 6, Freq= 0, CH_1, rank 0
8699 00:26:10.533080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8700 00:26:10.533160 ==
8701 00:26:10.533221 DQS Delay:
8702 00:26:10.536562 DQS0 = 0, DQS1 = 0
8703 00:26:10.536641 DQM Delay:
8704 00:26:10.536710 DQM0 = 131, DQM1 = 123
8705 00:26:10.539573 DQ Delay:
8706 00:26:10.543071 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =126
8707 00:26:10.546535 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8708 00:26:10.549475 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8709 00:26:10.552906 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8710 00:26:10.552985
8711 00:26:10.553045
8712 00:26:10.553100
8713 00:26:10.556448 [DramC_TX_OE_Calibration] TA2
8714 00:26:10.559361 Original DQ_B0 (3 6) =30, OEN = 27
8715 00:26:10.562707 Original DQ_B1 (3 6) =30, OEN = 27
8716 00:26:10.566033 24, 0x0, End_B0=24 End_B1=24
8717 00:26:10.566112 25, 0x0, End_B0=25 End_B1=25
8718 00:26:10.569694 26, 0x0, End_B0=26 End_B1=26
8719 00:26:10.572431 27, 0x0, End_B0=27 End_B1=27
8720 00:26:10.575974 28, 0x0, End_B0=28 End_B1=28
8721 00:26:10.579589 29, 0x0, End_B0=29 End_B1=29
8722 00:26:10.579667 30, 0x0, End_B0=30 End_B1=30
8723 00:26:10.582546 31, 0x4141, End_B0=30 End_B1=30
8724 00:26:10.585934 Byte0 end_step=30 best_step=27
8725 00:26:10.589400 Byte1 end_step=30 best_step=27
8726 00:26:10.592594 Byte0 TX OE(2T, 0.5T) = (3, 3)
8727 00:26:10.595775 Byte1 TX OE(2T, 0.5T) = (3, 3)
8728 00:26:10.595854
8729 00:26:10.595915
8730 00:26:10.602859 [DQSOSCAuto] RK0, (LSB)MR18= 0xc10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
8731 00:26:10.605770 CH1 RK0: MR19=303, MR18=C10
8732 00:26:10.612815 CH1_RK0: MR19=0x303, MR18=0xC10, DQSOSC=401, MR23=63, INC=22, DEC=15
8733 00:26:10.612893
8734 00:26:10.616034 ----->DramcWriteLeveling(PI) begin...
8735 00:26:10.616111 ==
8736 00:26:10.619327 Dram Type= 6, Freq= 0, CH_1, rank 1
8737 00:26:10.622355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8738 00:26:10.622482 ==
8739 00:26:10.625783 Write leveling (Byte 0): 24 => 24
8740 00:26:10.629251 Write leveling (Byte 1): 28 => 28
8741 00:26:10.632255 DramcWriteLeveling(PI) end<-----
8742 00:26:10.632332
8743 00:26:10.632391 ==
8744 00:26:10.635643 Dram Type= 6, Freq= 0, CH_1, rank 1
8745 00:26:10.638886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8746 00:26:10.638962 ==
8747 00:26:10.642651 [Gating] SW mode calibration
8748 00:26:10.648999 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8749 00:26:10.655563 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8750 00:26:10.659336 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 00:26:10.662197 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 00:26:10.668807 1 4 8 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
8753 00:26:10.672745 1 4 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
8754 00:26:10.675507 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8755 00:26:10.682417 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8756 00:26:10.685818 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 00:26:10.688833 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 00:26:10.695382 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 00:26:10.698928 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8760 00:26:10.702377 1 5 8 | B1->B0 | 3434 2525 | 0 0 | (0 1) (1 0)
8761 00:26:10.708932 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
8762 00:26:10.711850 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 00:26:10.715333 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 00:26:10.721908 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 00:26:10.725219 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 00:26:10.728801 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 00:26:10.735252 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8768 00:26:10.738841 1 6 8 | B1->B0 | 2828 4646 | 0 0 | (1 1) (0 0)
8769 00:26:10.741806 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8770 00:26:10.748346 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 00:26:10.751929 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8772 00:26:10.755330 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 00:26:10.761993 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 00:26:10.764882 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 00:26:10.768369 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 00:26:10.775013 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8777 00:26:10.778010 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8778 00:26:10.781631 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 00:26:10.788304 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 00:26:10.791539 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 00:26:10.794753 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 00:26:10.801666 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 00:26:10.804618 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 00:26:10.808115 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 00:26:10.815208 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 00:26:10.818025 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 00:26:10.821421 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 00:26:10.828214 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 00:26:10.831260 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 00:26:10.834399 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 00:26:10.841165 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 00:26:10.844779 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8793 00:26:10.848150 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8794 00:26:10.854316 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 00:26:10.854396 Total UI for P1: 0, mck2ui 16
8796 00:26:10.857865 best dqsien dly found for B0: ( 1, 9, 10)
8797 00:26:10.861075 Total UI for P1: 0, mck2ui 16
8798 00:26:10.864446 best dqsien dly found for B1: ( 1, 9, 12)
8799 00:26:10.870881 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8800 00:26:10.874347 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8801 00:26:10.874424
8802 00:26:10.877862 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8803 00:26:10.880842 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8804 00:26:10.884129 [Gating] SW calibration Done
8805 00:26:10.884205 ==
8806 00:26:10.887705 Dram Type= 6, Freq= 0, CH_1, rank 1
8807 00:26:10.890656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8808 00:26:10.890733 ==
8809 00:26:10.894121 RX Vref Scan: 0
8810 00:26:10.894197
8811 00:26:10.894255 RX Vref 0 -> 0, step: 1
8812 00:26:10.894310
8813 00:26:10.897520 RX Delay 0 -> 252, step: 8
8814 00:26:10.900525 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8815 00:26:10.907052 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8816 00:26:10.910552 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8817 00:26:10.914281 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8818 00:26:10.917323 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8819 00:26:10.920893 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8820 00:26:10.927305 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8821 00:26:10.930285 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8822 00:26:10.933792 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8823 00:26:10.937479 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8824 00:26:10.940399 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8825 00:26:10.946937 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8826 00:26:10.950386 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8827 00:26:10.953677 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8828 00:26:10.957413 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8829 00:26:10.960326 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8830 00:26:10.963929 ==
8831 00:26:10.964005 Dram Type= 6, Freq= 0, CH_1, rank 1
8832 00:26:10.970211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8833 00:26:10.970288 ==
8834 00:26:10.970346 DQS Delay:
8835 00:26:10.973927 DQS0 = 0, DQS1 = 0
8836 00:26:10.974004 DQM Delay:
8837 00:26:10.976891 DQM0 = 132, DQM1 = 128
8838 00:26:10.976981 DQ Delay:
8839 00:26:10.980541 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8840 00:26:10.983364 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =131
8841 00:26:10.986762 DQ8 =111, DQ9 =115, DQ10 =135, DQ11 =123
8842 00:26:10.990254 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8843 00:26:10.990330
8844 00:26:10.990388
8845 00:26:10.990459 ==
8846 00:26:10.993289 Dram Type= 6, Freq= 0, CH_1, rank 1
8847 00:26:11.000246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8848 00:26:11.000323 ==
8849 00:26:11.000382
8850 00:26:11.000436
8851 00:26:11.000488 TX Vref Scan disable
8852 00:26:11.003794 == TX Byte 0 ==
8853 00:26:11.007114 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8854 00:26:11.013533 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8855 00:26:11.013658 == TX Byte 1 ==
8856 00:26:11.017102 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8857 00:26:11.023549 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8858 00:26:11.023661 ==
8859 00:26:11.027037 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 00:26:11.029954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 00:26:11.030062 ==
8862 00:26:11.044131
8863 00:26:11.047116 TX Vref early break, caculate TX vref
8864 00:26:11.050215 TX Vref=16, minBit 0, minWin=23, winSum=386
8865 00:26:11.053853 TX Vref=18, minBit 0, minWin=23, winSum=396
8866 00:26:11.057379 TX Vref=20, minBit 5, minWin=24, winSum=401
8867 00:26:11.060324 TX Vref=22, minBit 0, minWin=24, winSum=405
8868 00:26:11.064020 TX Vref=24, minBit 0, minWin=24, winSum=415
8869 00:26:11.070329 TX Vref=26, minBit 0, minWin=25, winSum=418
8870 00:26:11.073902 TX Vref=28, minBit 0, minWin=26, winSum=427
8871 00:26:11.077112 TX Vref=30, minBit 1, minWin=25, winSum=424
8872 00:26:11.080329 TX Vref=32, minBit 1, minWin=24, winSum=411
8873 00:26:11.083393 TX Vref=34, minBit 5, minWin=23, winSum=406
8874 00:26:11.086822 TX Vref=36, minBit 5, minWin=23, winSum=395
8875 00:26:11.093567 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
8876 00:26:11.093677
8877 00:26:11.096706 Final TX Range 0 Vref 28
8878 00:26:11.096819
8879 00:26:11.096919 ==
8880 00:26:11.100010 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 00:26:11.103380 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 00:26:11.103529 ==
8883 00:26:11.103592
8884 00:26:11.106582
8885 00:26:11.106647 TX Vref Scan disable
8886 00:26:11.113313 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8887 00:26:11.113410 == TX Byte 0 ==
8888 00:26:11.116575 u2DelayCellOfst[0]=18 cells (5 PI)
8889 00:26:11.119794 u2DelayCellOfst[1]=15 cells (4 PI)
8890 00:26:11.123066 u2DelayCellOfst[2]=0 cells (0 PI)
8891 00:26:11.126545 u2DelayCellOfst[3]=7 cells (2 PI)
8892 00:26:11.130159 u2DelayCellOfst[4]=7 cells (2 PI)
8893 00:26:11.133091 u2DelayCellOfst[5]=22 cells (6 PI)
8894 00:26:11.136534 u2DelayCellOfst[6]=22 cells (6 PI)
8895 00:26:11.139486 u2DelayCellOfst[7]=7 cells (2 PI)
8896 00:26:11.143097 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8897 00:26:11.146059 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8898 00:26:11.149678 == TX Byte 1 ==
8899 00:26:11.153305 u2DelayCellOfst[8]=0 cells (0 PI)
8900 00:26:11.156410 u2DelayCellOfst[9]=7 cells (2 PI)
8901 00:26:11.159394 u2DelayCellOfst[10]=15 cells (4 PI)
8902 00:26:11.163004 u2DelayCellOfst[11]=3 cells (1 PI)
8903 00:26:11.163095 u2DelayCellOfst[12]=18 cells (5 PI)
8904 00:26:11.166458 u2DelayCellOfst[13]=18 cells (5 PI)
8905 00:26:11.169265 u2DelayCellOfst[14]=18 cells (5 PI)
8906 00:26:11.172614 u2DelayCellOfst[15]=22 cells (6 PI)
8907 00:26:11.179497 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8908 00:26:11.182533 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8909 00:26:11.182603 DramC Write-DBI on
8910 00:26:11.186017 ==
8911 00:26:11.189461 Dram Type= 6, Freq= 0, CH_1, rank 1
8912 00:26:11.192413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8913 00:26:11.192510 ==
8914 00:26:11.192599
8915 00:26:11.192722
8916 00:26:11.195861 TX Vref Scan disable
8917 00:26:11.195948 == TX Byte 0 ==
8918 00:26:11.202465 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8919 00:26:11.202536 == TX Byte 1 ==
8920 00:26:11.205899 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8921 00:26:11.209229 DramC Write-DBI off
8922 00:26:11.209297
8923 00:26:11.209353 [DATLAT]
8924 00:26:11.212267 Freq=1600, CH1 RK1
8925 00:26:11.212334
8926 00:26:11.212386 DATLAT Default: 0xf
8927 00:26:11.215493 0, 0xFFFF, sum = 0
8928 00:26:11.215602 1, 0xFFFF, sum = 0
8929 00:26:11.219250 2, 0xFFFF, sum = 0
8930 00:26:11.219342 3, 0xFFFF, sum = 0
8931 00:26:11.222089 4, 0xFFFF, sum = 0
8932 00:26:11.222196 5, 0xFFFF, sum = 0
8933 00:26:11.225505 6, 0xFFFF, sum = 0
8934 00:26:11.228739 7, 0xFFFF, sum = 0
8935 00:26:11.228841 8, 0xFFFF, sum = 0
8936 00:26:11.232121 9, 0xFFFF, sum = 0
8937 00:26:11.232218 10, 0xFFFF, sum = 0
8938 00:26:11.235638 11, 0xFFFF, sum = 0
8939 00:26:11.235707 12, 0xFFFF, sum = 0
8940 00:26:11.239056 13, 0x8FFF, sum = 0
8941 00:26:11.239159 14, 0x0, sum = 1
8942 00:26:11.242005 15, 0x0, sum = 2
8943 00:26:11.242082 16, 0x0, sum = 3
8944 00:26:11.245281 17, 0x0, sum = 4
8945 00:26:11.245348 best_step = 15
8946 00:26:11.245405
8947 00:26:11.245458 ==
8948 00:26:11.248306 Dram Type= 6, Freq= 0, CH_1, rank 1
8949 00:26:11.251921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8950 00:26:11.255593 ==
8951 00:26:11.255689 RX Vref Scan: 0
8952 00:26:11.255759
8953 00:26:11.258429 RX Vref 0 -> 0, step: 1
8954 00:26:11.258516
8955 00:26:11.258583 RX Delay 3 -> 252, step: 4
8956 00:26:11.266130 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8957 00:26:11.269127 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8958 00:26:11.272441 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8959 00:26:11.275868 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8960 00:26:11.279132 iDelay=195, Bit 4, Center 122 (67 ~ 178) 112
8961 00:26:11.286014 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8962 00:26:11.289096 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8963 00:26:11.292516 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8964 00:26:11.296047 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8965 00:26:11.298910 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
8966 00:26:11.305860 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8967 00:26:11.309083 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8968 00:26:11.312322 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8969 00:26:11.315883 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
8970 00:26:11.322179 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8971 00:26:11.325612 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8972 00:26:11.325679 ==
8973 00:26:11.329060 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 00:26:11.332549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 00:26:11.332641 ==
8976 00:26:11.332720 DQS Delay:
8977 00:26:11.335462 DQS0 = 0, DQS1 = 0
8978 00:26:11.335574 DQM Delay:
8979 00:26:11.338986 DQM0 = 130, DQM1 = 125
8980 00:26:11.339048 DQ Delay:
8981 00:26:11.342045 DQ0 =134, DQ1 =130, DQ2 =118, DQ3 =128
8982 00:26:11.345469 DQ4 =122, DQ5 =140, DQ6 =142, DQ7 =128
8983 00:26:11.348711 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =120
8984 00:26:11.355377 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =136
8985 00:26:11.355451
8986 00:26:11.355516
8987 00:26:11.355568
8988 00:26:11.358704 [DramC_TX_OE_Calibration] TA2
8989 00:26:11.358767 Original DQ_B0 (3 6) =30, OEN = 27
8990 00:26:11.362128 Original DQ_B1 (3 6) =30, OEN = 27
8991 00:26:11.365158 24, 0x0, End_B0=24 End_B1=24
8992 00:26:11.368573 25, 0x0, End_B0=25 End_B1=25
8993 00:26:11.372282 26, 0x0, End_B0=26 End_B1=26
8994 00:26:11.375018 27, 0x0, End_B0=27 End_B1=27
8995 00:26:11.375085 28, 0x0, End_B0=28 End_B1=28
8996 00:26:11.378432 29, 0x0, End_B0=29 End_B1=29
8997 00:26:11.381904 30, 0x0, End_B0=30 End_B1=30
8998 00:26:11.385280 31, 0x4141, End_B0=30 End_B1=30
8999 00:26:11.388234 Byte0 end_step=30 best_step=27
9000 00:26:11.388298 Byte1 end_step=30 best_step=27
9001 00:26:11.391700 Byte0 TX OE(2T, 0.5T) = (3, 3)
9002 00:26:11.395105 Byte1 TX OE(2T, 0.5T) = (3, 3)
9003 00:26:11.395173
9004 00:26:11.395227
9005 00:26:11.404610 [DQSOSCAuto] RK1, (LSB)MR18= 0x101c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9006 00:26:11.404701 CH1 RK1: MR19=303, MR18=101C
9007 00:26:11.411483 CH1_RK1: MR19=0x303, MR18=0x101C, DQSOSC=395, MR23=63, INC=23, DEC=15
9008 00:26:11.414604 [RxdqsGatingPostProcess] freq 1600
9009 00:26:11.421573 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9010 00:26:11.424533 best DQS0 dly(2T, 0.5T) = (1, 1)
9011 00:26:11.427974 best DQS1 dly(2T, 0.5T) = (1, 1)
9012 00:26:11.431542 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9013 00:26:11.434925 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9014 00:26:11.437842 best DQS0 dly(2T, 0.5T) = (1, 1)
9015 00:26:11.437912 best DQS1 dly(2T, 0.5T) = (1, 1)
9016 00:26:11.441325 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9017 00:26:11.444825 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9018 00:26:11.448284 Pre-setting of DQS Precalculation
9019 00:26:11.454858 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9020 00:26:11.461272 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9021 00:26:11.468045 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9022 00:26:11.468132
9023 00:26:11.468188
9024 00:26:11.471604 [Calibration Summary] 3200 Mbps
9025 00:26:11.471672 CH 0, Rank 0
9026 00:26:11.474810 SW Impedance : PASS
9027 00:26:11.477971 DUTY Scan : NO K
9028 00:26:11.478035 ZQ Calibration : PASS
9029 00:26:11.481115 Jitter Meter : NO K
9030 00:26:11.484557 CBT Training : PASS
9031 00:26:11.484638 Write leveling : PASS
9032 00:26:11.488038 RX DQS gating : PASS
9033 00:26:11.490948 RX DQ/DQS(RDDQC) : PASS
9034 00:26:11.491025 TX DQ/DQS : PASS
9035 00:26:11.494704 RX DATLAT : PASS
9036 00:26:11.497956 RX DQ/DQS(Engine): PASS
9037 00:26:11.498052 TX OE : PASS
9038 00:26:11.501287 All Pass.
9039 00:26:11.501359
9040 00:26:11.501414 CH 0, Rank 1
9041 00:26:11.504246 SW Impedance : PASS
9042 00:26:11.504324 DUTY Scan : NO K
9043 00:26:11.507765 ZQ Calibration : PASS
9044 00:26:11.510813 Jitter Meter : NO K
9045 00:26:11.510892 CBT Training : PASS
9046 00:26:11.514354 Write leveling : PASS
9047 00:26:11.514432 RX DQS gating : PASS
9048 00:26:11.517255 RX DQ/DQS(RDDQC) : PASS
9049 00:26:11.521080 TX DQ/DQS : PASS
9050 00:26:11.521158 RX DATLAT : PASS
9051 00:26:11.524237 RX DQ/DQS(Engine): PASS
9052 00:26:11.527754 TX OE : PASS
9053 00:26:11.527832 All Pass.
9054 00:26:11.527893
9055 00:26:11.527948 CH 1, Rank 0
9056 00:26:11.530803 SW Impedance : PASS
9057 00:26:11.534250 DUTY Scan : NO K
9058 00:26:11.534327 ZQ Calibration : PASS
9059 00:26:11.537779 Jitter Meter : NO K
9060 00:26:11.541250 CBT Training : PASS
9061 00:26:11.541328 Write leveling : PASS
9062 00:26:11.544786 RX DQS gating : PASS
9063 00:26:11.547890 RX DQ/DQS(RDDQC) : PASS
9064 00:26:11.547967 TX DQ/DQS : PASS
9065 00:26:11.551397 RX DATLAT : PASS
9066 00:26:11.551475 RX DQ/DQS(Engine): PASS
9067 00:26:11.554317 TX OE : PASS
9068 00:26:11.554395 All Pass.
9069 00:26:11.554455
9070 00:26:11.557862 CH 1, Rank 1
9071 00:26:11.560815 SW Impedance : PASS
9072 00:26:11.560892 DUTY Scan : NO K
9073 00:26:11.564229 ZQ Calibration : PASS
9074 00:26:11.564306 Jitter Meter : NO K
9075 00:26:11.567826 CBT Training : PASS
9076 00:26:11.570780 Write leveling : PASS
9077 00:26:11.570857 RX DQS gating : PASS
9078 00:26:11.574145 RX DQ/DQS(RDDQC) : PASS
9079 00:26:11.577527 TX DQ/DQS : PASS
9080 00:26:11.577605 RX DATLAT : PASS
9081 00:26:11.580895 RX DQ/DQS(Engine): PASS
9082 00:26:11.583889 TX OE : PASS
9083 00:26:11.583966 All Pass.
9084 00:26:11.584026
9085 00:26:11.587328 DramC Write-DBI on
9086 00:26:11.587406 PER_BANK_REFRESH: Hybrid Mode
9087 00:26:11.590782 TX_TRACKING: ON
9088 00:26:11.600425 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9089 00:26:11.607027 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9090 00:26:11.613589 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9091 00:26:11.616946 [FAST_K] Save calibration result to emmc
9092 00:26:11.620400 sync common calibartion params.
9093 00:26:11.623688 sync cbt_mode0:1, 1:1
9094 00:26:11.623757 dram_init: ddr_geometry: 2
9095 00:26:11.626860 dram_init: ddr_geometry: 2
9096 00:26:11.630297 dram_init: ddr_geometry: 2
9097 00:26:11.633358 0:dram_rank_size:100000000
9098 00:26:11.633435 1:dram_rank_size:100000000
9099 00:26:11.640002 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9100 00:26:11.643812 DFS_SHUFFLE_HW_MODE: ON
9101 00:26:11.646685 dramc_set_vcore_voltage set vcore to 725000
9102 00:26:11.650201 Read voltage for 1600, 0
9103 00:26:11.650267 Vio18 = 0
9104 00:26:11.650322 Vcore = 725000
9105 00:26:11.653704 Vdram = 0
9106 00:26:11.653773 Vddq = 0
9107 00:26:11.653830 Vmddr = 0
9108 00:26:11.656529 switch to 3200 Mbps bootup
9109 00:26:11.656622 [DramcRunTimeConfig]
9110 00:26:11.659975 PHYPLL
9111 00:26:11.660037 DPM_CONTROL_AFTERK: ON
9112 00:26:11.663638 PER_BANK_REFRESH: ON
9113 00:26:11.666541 REFRESH_OVERHEAD_REDUCTION: ON
9114 00:26:11.666603 CMD_PICG_NEW_MODE: OFF
9115 00:26:11.669951 XRTWTW_NEW_MODE: ON
9116 00:26:11.670019 XRTRTR_NEW_MODE: ON
9117 00:26:11.673610 TX_TRACKING: ON
9118 00:26:11.673672 RDSEL_TRACKING: OFF
9119 00:26:11.676488 DQS Precalculation for DVFS: ON
9120 00:26:11.679910 RX_TRACKING: OFF
9121 00:26:11.679978 HW_GATING DBG: ON
9122 00:26:11.683336 ZQCS_ENABLE_LP4: ON
9123 00:26:11.683422 RX_PICG_NEW_MODE: ON
9124 00:26:11.686761 TX_PICG_NEW_MODE: ON
9125 00:26:11.686823 ENABLE_RX_DCM_DPHY: ON
9126 00:26:11.690265 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9127 00:26:11.693260 DUMMY_READ_FOR_TRACKING: OFF
9128 00:26:11.696354 !!! SPM_CONTROL_AFTERK: OFF
9129 00:26:11.700022 !!! SPM could not control APHY
9130 00:26:11.700084 IMPEDANCE_TRACKING: ON
9131 00:26:11.703058 TEMP_SENSOR: ON
9132 00:26:11.703119 HW_SAVE_FOR_SR: OFF
9133 00:26:11.706515 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9134 00:26:11.709975 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9135 00:26:11.712982 Read ODT Tracking: ON
9136 00:26:11.716303 Refresh Rate DeBounce: ON
9137 00:26:11.716365 DFS_NO_QUEUE_FLUSH: ON
9138 00:26:11.719420 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9139 00:26:11.722773 ENABLE_DFS_RUNTIME_MRW: OFF
9140 00:26:11.726189 DDR_RESERVE_NEW_MODE: ON
9141 00:26:11.726254 MR_CBT_SWITCH_FREQ: ON
9142 00:26:11.729601 =========================
9143 00:26:11.748445 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9144 00:26:11.751706 dram_init: ddr_geometry: 2
9145 00:26:11.770167 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9146 00:26:11.773165 dram_init: dram init end (result: 0)
9147 00:26:11.779798 DRAM-K: Full calibration passed in 24534 msecs
9148 00:26:11.783247 MRC: failed to locate region type 0.
9149 00:26:11.783316 DRAM rank0 size:0x100000000,
9150 00:26:11.786770 DRAM rank1 size=0x100000000
9151 00:26:11.796400 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9152 00:26:11.803502 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9153 00:26:11.810033 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9154 00:26:11.816415 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9155 00:26:11.819710 DRAM rank0 size:0x100000000,
9156 00:26:11.822883 DRAM rank1 size=0x100000000
9157 00:26:11.822950 CBMEM:
9158 00:26:11.826480 IMD: root @ 0xfffff000 254 entries.
9159 00:26:11.829519 IMD: root @ 0xffffec00 62 entries.
9160 00:26:11.833068 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9161 00:26:11.839473 WARNING: RO_VPD is uninitialized or empty.
9162 00:26:11.842960 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9163 00:26:11.849899 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9164 00:26:11.862776 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9165 00:26:11.874430 BS: romstage times (exec / console): total (unknown) / 24006 ms
9166 00:26:11.874503
9167 00:26:11.874568
9168 00:26:11.884060 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9169 00:26:11.887461 ARM64: Exception handlers installed.
9170 00:26:11.890754 ARM64: Testing exception
9171 00:26:11.894244 ARM64: Done test exception
9172 00:26:11.894311 Enumerating buses...
9173 00:26:11.897216 Show all devs... Before device enumeration.
9174 00:26:11.900519 Root Device: enabled 1
9175 00:26:11.904041 CPU_CLUSTER: 0: enabled 1
9176 00:26:11.904111 CPU: 00: enabled 1
9177 00:26:11.907098 Compare with tree...
9178 00:26:11.907161 Root Device: enabled 1
9179 00:26:11.910764 CPU_CLUSTER: 0: enabled 1
9180 00:26:11.913745 CPU: 00: enabled 1
9181 00:26:11.913807 Root Device scanning...
9182 00:26:11.917324 scan_static_bus for Root Device
9183 00:26:11.920220 CPU_CLUSTER: 0 enabled
9184 00:26:11.923548 scan_static_bus for Root Device done
9185 00:26:11.926841 scan_bus: bus Root Device finished in 8 msecs
9186 00:26:11.926918 done
9187 00:26:11.933788 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9188 00:26:11.937152 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9189 00:26:11.943618 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9190 00:26:11.947026 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9191 00:26:11.949980 Allocating resources...
9192 00:26:11.953544 Reading resources...
9193 00:26:11.956980 Root Device read_resources bus 0 link: 0
9194 00:26:11.960007 DRAM rank0 size:0x100000000,
9195 00:26:11.960073 DRAM rank1 size=0x100000000
9196 00:26:11.963621 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9197 00:26:11.966586 CPU: 00 missing read_resources
9198 00:26:11.973101 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9199 00:26:11.976543 Root Device read_resources bus 0 link: 0 done
9200 00:26:11.976635 Done reading resources.
9201 00:26:11.982999 Show resources in subtree (Root Device)...After reading.
9202 00:26:11.986313 Root Device child on link 0 CPU_CLUSTER: 0
9203 00:26:11.989905 CPU_CLUSTER: 0 child on link 0 CPU: 00
9204 00:26:11.999827 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9205 00:26:11.999897 CPU: 00
9206 00:26:12.002922 Root Device assign_resources, bus 0 link: 0
9207 00:26:12.006529 CPU_CLUSTER: 0 missing set_resources
9208 00:26:12.012994 Root Device assign_resources, bus 0 link: 0 done
9209 00:26:12.013062 Done setting resources.
9210 00:26:12.019782 Show resources in subtree (Root Device)...After assigning values.
9211 00:26:12.022726 Root Device child on link 0 CPU_CLUSTER: 0
9212 00:26:12.026265 CPU_CLUSTER: 0 child on link 0 CPU: 00
9213 00:26:12.036295 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9214 00:26:12.036410 CPU: 00
9215 00:26:12.039793 Done allocating resources.
9216 00:26:12.046343 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9217 00:26:12.046427 Enabling resources...
9218 00:26:12.046483 done.
9219 00:26:12.052878 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9220 00:26:12.052977 Initializing devices...
9221 00:26:12.056053 Root Device init
9222 00:26:12.059626 init hardware done!
9223 00:26:12.059702 0x00000018: ctrlr->caps
9224 00:26:12.062618 52.000 MHz: ctrlr->f_max
9225 00:26:12.066088 0.400 MHz: ctrlr->f_min
9226 00:26:12.066180 0x40ff8080: ctrlr->voltages
9227 00:26:12.069638 sclk: 390625
9228 00:26:12.069712 Bus Width = 1
9229 00:26:12.069770 sclk: 390625
9230 00:26:12.072436 Bus Width = 1
9231 00:26:12.072554 Early init status = 3
9232 00:26:12.078984 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9233 00:26:12.082532 in-header: 03 fc 00 00 01 00 00 00
9234 00:26:12.086001 in-data: 00
9235 00:26:12.088834 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9236 00:26:12.092835 in-header: 03 fd 00 00 00 00 00 00
9237 00:26:12.096419 in-data:
9238 00:26:12.099339 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9239 00:26:12.102899 in-header: 03 fc 00 00 01 00 00 00
9240 00:26:12.106372 in-data: 00
9241 00:26:12.109652 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9242 00:26:12.114744 in-header: 03 fd 00 00 00 00 00 00
9243 00:26:12.117894 in-data:
9244 00:26:12.120981 [SSUSB] Setting up USB HOST controller...
9245 00:26:12.124399 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9246 00:26:12.127463 [SSUSB] phy power-on done.
9247 00:26:12.130960 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9248 00:26:12.137904 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9249 00:26:12.140679 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9250 00:26:12.147603 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9251 00:26:12.154361 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9252 00:26:12.160950 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9253 00:26:12.167335 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9254 00:26:12.174338 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9255 00:26:12.177410 SPM: binary array size = 0x9dc
9256 00:26:12.180958 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9257 00:26:12.187310 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9258 00:26:12.194040 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9259 00:26:12.200262 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9260 00:26:12.203681 configure_display: Starting display init
9261 00:26:12.237542 anx7625_power_on_init: Init interface.
9262 00:26:12.240907 anx7625_disable_pd_protocol: Disabled PD feature.
9263 00:26:12.244486 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9264 00:26:12.271919 anx7625_start_dp_work: Secure OCM version=00
9265 00:26:12.275474 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9266 00:26:12.290211 sp_tx_get_edid_block: EDID Block = 1
9267 00:26:12.393016 Extracted contents:
9268 00:26:12.396026 header: 00 ff ff ff ff ff ff 00
9269 00:26:12.399146 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9270 00:26:12.402578 version: 01 04
9271 00:26:12.405851 basic params: 95 1f 11 78 0a
9272 00:26:12.409335 chroma info: 76 90 94 55 54 90 27 21 50 54
9273 00:26:12.412261 established: 00 00 00
9274 00:26:12.419287 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9275 00:26:12.425485 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9276 00:26:12.428821 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9277 00:26:12.435454 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9278 00:26:12.441705 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9279 00:26:12.445123 extensions: 00
9280 00:26:12.445200 checksum: fb
9281 00:26:12.445259
9282 00:26:12.451977 Manufacturer: IVO Model 57d Serial Number 0
9283 00:26:12.452069 Made week 0 of 2020
9284 00:26:12.454931 EDID version: 1.4
9285 00:26:12.455044 Digital display
9286 00:26:12.458358 6 bits per primary color channel
9287 00:26:12.461913 DisplayPort interface
9288 00:26:12.461988 Maximum image size: 31 cm x 17 cm
9289 00:26:12.465316 Gamma: 220%
9290 00:26:12.465392 Check DPMS levels
9291 00:26:12.471964 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9292 00:26:12.475009 First detailed timing is preferred timing
9293 00:26:12.475105 Established timings supported:
9294 00:26:12.478324 Standard timings supported:
9295 00:26:12.482020 Detailed timings
9296 00:26:12.484959 Hex of detail: 383680a07038204018303c0035ae10000019
9297 00:26:12.491823 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9298 00:26:12.495004 0780 0798 07c8 0820 hborder 0
9299 00:26:12.498237 0438 043b 0447 0458 vborder 0
9300 00:26:12.501562 -hsync -vsync
9301 00:26:12.501637 Did detailed timing
9302 00:26:12.508180 Hex of detail: 000000000000000000000000000000000000
9303 00:26:12.511187 Manufacturer-specified data, tag 0
9304 00:26:12.514779 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9305 00:26:12.517819 ASCII string: InfoVision
9306 00:26:12.521238 Hex of detail: 000000fe00523134304e574635205248200a
9307 00:26:12.524269 ASCII string: R140NWF5 RH
9308 00:26:12.524363 Checksum
9309 00:26:12.527888 Checksum: 0xfb (valid)
9310 00:26:12.531463 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9311 00:26:12.534252 DSI data_rate: 832800000 bps
9312 00:26:12.541402 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9313 00:26:12.544252 anx7625_parse_edid: pixelclock(138800).
9314 00:26:12.547544 hactive(1920), hsync(48), hfp(24), hbp(88)
9315 00:26:12.551101 vactive(1080), vsync(12), vfp(3), vbp(17)
9316 00:26:12.554495 anx7625_dsi_config: config dsi.
9317 00:26:12.560923 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9318 00:26:12.574554 anx7625_dsi_config: success to config DSI
9319 00:26:12.577994 anx7625_dp_start: MIPI phy setup OK.
9320 00:26:12.581525 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9321 00:26:12.584576 mtk_ddp_mode_set invalid vrefresh 60
9322 00:26:12.588206 main_disp_path_setup
9323 00:26:12.588282 ovl_layer_smi_id_en
9324 00:26:12.591088 ovl_layer_smi_id_en
9325 00:26:12.591209 ccorr_config
9326 00:26:12.591314 aal_config
9327 00:26:12.594543 gamma_config
9328 00:26:12.594655 postmask_config
9329 00:26:12.597907 dither_config
9330 00:26:12.601203 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9331 00:26:12.607796 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9332 00:26:12.610805 Root Device init finished in 551 msecs
9333 00:26:12.614443 CPU_CLUSTER: 0 init
9334 00:26:12.620974 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9335 00:26:12.624225 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9336 00:26:12.627573 APU_MBOX 0x190000b0 = 0x10001
9337 00:26:12.630957 APU_MBOX 0x190001b0 = 0x10001
9338 00:26:12.634459 APU_MBOX 0x190005b0 = 0x10001
9339 00:26:12.637400 APU_MBOX 0x190006b0 = 0x10001
9340 00:26:12.643943 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9341 00:26:12.653698 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9342 00:26:12.666516 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9343 00:26:12.673225 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9344 00:26:12.684294 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9345 00:26:12.693740 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9346 00:26:12.696776 CPU_CLUSTER: 0 init finished in 81 msecs
9347 00:26:12.700252 Devices initialized
9348 00:26:12.703533 Show all devs... After init.
9349 00:26:12.703645 Root Device: enabled 1
9350 00:26:12.706732 CPU_CLUSTER: 0: enabled 1
9351 00:26:12.709955 CPU: 00: enabled 1
9352 00:26:12.713400 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9353 00:26:12.716979 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9354 00:26:12.719929 ELOG: NV offset 0x57f000 size 0x1000
9355 00:26:12.726976 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9356 00:26:12.733654 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9357 00:26:12.736862 ELOG: Event(17) added with size 13 at 2024-06-21 00:26:12 UTC
9358 00:26:12.740009 out: cmd=0x121: 03 db 21 01 00 00 00 00
9359 00:26:12.743678 in-header: 03 91 00 00 2c 00 00 00
9360 00:26:12.757016 in-data: ac 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9361 00:26:12.763645 ELOG: Event(A1) added with size 10 at 2024-06-21 00:26:12 UTC
9362 00:26:12.770069 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9363 00:26:12.776539 ELOG: Event(A0) added with size 9 at 2024-06-21 00:26:12 UTC
9364 00:26:12.780218 elog_add_boot_reason: Logged dev mode boot
9365 00:26:12.783097 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9366 00:26:12.786440 Finalize devices...
9367 00:26:12.786553 Devices finalized
9368 00:26:12.793148 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9369 00:26:12.796765 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9370 00:26:12.799739 in-header: 03 07 00 00 08 00 00 00
9371 00:26:12.803246 in-data: aa e4 47 04 13 02 00 00
9372 00:26:12.806787 Chrome EC: UHEPI supported
9373 00:26:12.812802 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9374 00:26:12.816258 in-header: 03 a9 00 00 08 00 00 00
9375 00:26:12.819893 in-data: 84 60 60 08 00 00 00 00
9376 00:26:12.822904 ELOG: Event(91) added with size 10 at 2024-06-21 00:26:13 UTC
9377 00:26:12.829454 Chrome EC: clear events_b mask to 0x0000000020004000
9378 00:26:12.836602 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9379 00:26:12.839572 in-header: 03 fd 00 00 00 00 00 00
9380 00:26:12.839737 in-data:
9381 00:26:12.846389 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9382 00:26:12.849774 Writing coreboot table at 0xffe64000
9383 00:26:12.852855 0. 000000000010a000-0000000000113fff: RAMSTAGE
9384 00:26:12.856522 1. 0000000040000000-00000000400fffff: RAM
9385 00:26:12.862684 2. 0000000040100000-000000004032afff: RAMSTAGE
9386 00:26:12.866224 3. 000000004032b000-00000000545fffff: RAM
9387 00:26:12.869573 4. 0000000054600000-000000005465ffff: BL31
9388 00:26:12.872713 5. 0000000054660000-00000000ffe63fff: RAM
9389 00:26:12.879430 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9390 00:26:12.883186 7. 0000000100000000-000000023fffffff: RAM
9391 00:26:12.883296 Passing 5 GPIOs to payload:
9392 00:26:12.889676 NAME | PORT | POLARITY | VALUE
9393 00:26:12.893059 EC in RW | 0x000000aa | low | undefined
9394 00:26:12.899731 EC interrupt | 0x00000005 | low | undefined
9395 00:26:12.902745 TPM interrupt | 0x000000ab | high | undefined
9396 00:26:12.906373 SD card detect | 0x00000011 | high | undefined
9397 00:26:12.912935 speaker enable | 0x00000093 | high | undefined
9398 00:26:12.915992 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9399 00:26:12.919430 in-header: 03 f9 00 00 02 00 00 00
9400 00:26:12.919505 in-data: 02 00
9401 00:26:12.922820 ADC[4]: Raw value=897040 ID=7
9402 00:26:12.926005 ADC[3]: Raw value=213440 ID=1
9403 00:26:12.929394 RAM Code: 0x71
9404 00:26:12.929470 ADC[6]: Raw value=74722 ID=0
9405 00:26:12.932348 ADC[5]: Raw value=211590 ID=1
9406 00:26:12.935920 SKU Code: 0x1
9407 00:26:12.938910 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 1821
9408 00:26:12.942515 coreboot table: 964 bytes.
9409 00:26:12.945868 IMD ROOT 0. 0xfffff000 0x00001000
9410 00:26:12.949110 IMD SMALL 1. 0xffffe000 0x00001000
9411 00:26:12.952618 RO MCACHE 2. 0xffffc000 0x00001104
9412 00:26:12.955573 CONSOLE 3. 0xfff7c000 0x00080000
9413 00:26:12.958929 FMAP 4. 0xfff7b000 0x00000452
9414 00:26:12.962295 TIME STAMP 5. 0xfff7a000 0x00000910
9415 00:26:12.965288 VBOOT WORK 6. 0xfff66000 0x00014000
9416 00:26:12.968832 RAMOOPS 7. 0xffe66000 0x00100000
9417 00:26:12.972538 COREBOOT 8. 0xffe64000 0x00002000
9418 00:26:12.972629 IMD small region:
9419 00:26:12.975448 IMD ROOT 0. 0xffffec00 0x00000400
9420 00:26:12.978968 VPD 1. 0xffffeb80 0x0000006c
9421 00:26:12.985579 MMC STATUS 2. 0xffffeb60 0x00000004
9422 00:26:12.988809 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9423 00:26:12.995339 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9424 00:26:13.035536 read SPI 0x3990ec 0x4f1b0: 34861 us, 9294 KB/s, 74.352 Mbps
9425 00:26:13.038878 Checking segment from ROM address 0x40100000
9426 00:26:13.042399 Checking segment from ROM address 0x4010001c
9427 00:26:13.048894 Loading segment from ROM address 0x40100000
9428 00:26:13.048971 code (compression=0)
9429 00:26:13.058722 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9430 00:26:13.065304 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9431 00:26:13.065382 it's not compressed!
9432 00:26:13.071805 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9433 00:26:13.078359 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9434 00:26:13.095989 Loading segment from ROM address 0x4010001c
9435 00:26:13.096067 Entry Point 0x80000000
9436 00:26:13.099208 Loaded segments
9437 00:26:13.102476 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9438 00:26:13.109148 Jumping to boot code at 0x80000000(0xffe64000)
9439 00:26:13.115662 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9440 00:26:13.122155 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9441 00:26:13.130373 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9442 00:26:13.133361 Checking segment from ROM address 0x40100000
9443 00:26:13.136948 Checking segment from ROM address 0x4010001c
9444 00:26:13.143569 Loading segment from ROM address 0x40100000
9445 00:26:13.143645 code (compression=1)
9446 00:26:13.149933 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9447 00:26:13.160085 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9448 00:26:13.160170 using LZMA
9449 00:26:13.168868 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9450 00:26:13.175546 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9451 00:26:13.178546 Loading segment from ROM address 0x4010001c
9452 00:26:13.178613 Entry Point 0x54601000
9453 00:26:13.182047 Loaded segments
9454 00:26:13.184924 NOTICE: MT8192 bl31_setup
9455 00:26:13.192395 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9456 00:26:13.195323 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9457 00:26:13.198724 WARNING: region 0:
9458 00:26:13.201952 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9459 00:26:13.202029 WARNING: region 1:
9460 00:26:13.208785 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9461 00:26:13.211803 WARNING: region 2:
9462 00:26:13.215247 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9463 00:26:13.218748 WARNING: region 3:
9464 00:26:13.225213 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9465 00:26:13.225291 WARNING: region 4:
9466 00:26:13.231725 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9467 00:26:13.231812 WARNING: region 5:
9468 00:26:13.235297 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9469 00:26:13.238049 WARNING: region 6:
9470 00:26:13.241605 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 00:26:13.245286 WARNING: region 7:
9472 00:26:13.247986 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 00:26:13.254761 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9474 00:26:13.258369 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9475 00:26:13.265115 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9476 00:26:13.268097 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9477 00:26:13.271563 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9478 00:26:13.278103 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9479 00:26:13.281224 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9480 00:26:13.284885 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9481 00:26:13.291311 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9482 00:26:13.294127 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9483 00:26:13.300932 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9484 00:26:13.304351 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9485 00:26:13.307647 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9486 00:26:13.314030 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9487 00:26:13.317567 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9488 00:26:13.320812 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9489 00:26:13.327796 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9490 00:26:13.331018 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9491 00:26:13.337423 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9492 00:26:13.340603 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9493 00:26:13.344177 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9494 00:26:13.350833 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9495 00:26:13.353755 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9496 00:26:13.360797 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9497 00:26:13.363907 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9498 00:26:13.366956 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9499 00:26:13.373841 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9500 00:26:13.377363 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9501 00:26:13.383817 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9502 00:26:13.387169 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9503 00:26:13.393536 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9504 00:26:13.396946 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9505 00:26:13.400322 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9506 00:26:13.403879 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9507 00:26:13.410258 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9508 00:26:13.413531 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9509 00:26:13.416979 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9510 00:26:13.419964 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9511 00:26:13.426780 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9512 00:26:13.430321 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9513 00:26:13.433251 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9514 00:26:13.436895 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9515 00:26:13.443398 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9516 00:26:13.446875 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9517 00:26:13.449701 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9518 00:26:13.456769 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9519 00:26:13.459634 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9520 00:26:13.463098 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9521 00:26:13.466337 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9522 00:26:13.472855 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9523 00:26:13.476063 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9524 00:26:13.482784 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9525 00:26:13.486274 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9526 00:26:13.492674 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9527 00:26:13.496158 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9528 00:26:13.502537 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9529 00:26:13.505904 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9530 00:26:13.509357 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9531 00:26:13.515999 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9532 00:26:13.519353 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9533 00:26:13.525806 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9534 00:26:13.529154 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9535 00:26:13.536229 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9536 00:26:13.539031 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9537 00:26:13.545818 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9538 00:26:13.549385 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9539 00:26:13.552359 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9540 00:26:13.558891 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9541 00:26:13.562547 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9542 00:26:13.569199 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9543 00:26:13.572291 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9544 00:26:13.578987 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9545 00:26:13.582094 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9546 00:26:13.585611 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9547 00:26:13.592052 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9548 00:26:13.595502 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9549 00:26:13.602054 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9550 00:26:13.605022 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9551 00:26:13.611921 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9552 00:26:13.615496 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9553 00:26:13.621899 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9554 00:26:13.625280 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9555 00:26:13.632020 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9556 00:26:13.634904 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9557 00:26:13.638473 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9558 00:26:13.644749 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9559 00:26:13.648302 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9560 00:26:13.654802 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9561 00:26:13.658301 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9562 00:26:13.664853 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9563 00:26:13.667946 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9564 00:26:13.671343 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9565 00:26:13.678291 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9566 00:26:13.681478 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9567 00:26:13.687808 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9568 00:26:13.691371 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9569 00:26:13.698135 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9570 00:26:13.701118 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9571 00:26:13.704748 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9572 00:26:13.707799 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9573 00:26:13.714420 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9574 00:26:13.717772 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9575 00:26:13.720844 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9576 00:26:13.727881 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9577 00:26:13.730796 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9578 00:26:13.737305 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9579 00:26:13.740748 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9580 00:26:13.744235 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9581 00:26:13.750957 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9582 00:26:13.753935 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9583 00:26:13.760962 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9584 00:26:13.763779 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9585 00:26:13.770814 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9586 00:26:13.773710 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9587 00:26:13.777302 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9588 00:26:13.783547 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9589 00:26:13.786850 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9590 00:26:13.790668 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9591 00:26:13.797205 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9592 00:26:13.800779 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9593 00:26:13.803522 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9594 00:26:13.806803 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9595 00:26:13.813483 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9596 00:26:13.816801 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9597 00:26:13.820562 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9598 00:26:13.826687 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9599 00:26:13.830121 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9600 00:26:13.833565 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9601 00:26:13.840305 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9602 00:26:13.843434 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9603 00:26:13.850366 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9604 00:26:13.853181 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9605 00:26:13.856718 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9606 00:26:13.863250 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9607 00:26:13.866831 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9608 00:26:13.873738 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9609 00:26:13.876726 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9610 00:26:13.880287 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9611 00:26:13.886821 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9612 00:26:13.889844 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9613 00:26:13.893364 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9614 00:26:13.899942 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9615 00:26:13.903641 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9616 00:26:13.909958 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9617 00:26:13.913154 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9618 00:26:13.916906 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9619 00:26:13.923278 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9620 00:26:13.926645 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9621 00:26:13.933047 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9622 00:26:13.936591 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9623 00:26:13.942995 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9624 00:26:13.946474 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9625 00:26:13.949772 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9626 00:26:13.955976 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9627 00:26:13.959407 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9628 00:26:13.962602 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9629 00:26:13.969142 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9630 00:26:13.972762 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9631 00:26:13.979463 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9632 00:26:13.982474 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9633 00:26:13.985900 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9634 00:26:13.992202 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9635 00:26:13.995737 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9636 00:26:14.002490 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9637 00:26:14.005670 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9638 00:26:14.009073 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9639 00:26:14.015424 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9640 00:26:14.018813 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9641 00:26:14.025602 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9642 00:26:14.029139 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9643 00:26:14.032074 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9644 00:26:14.038664 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9645 00:26:14.041878 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9646 00:26:14.048488 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9647 00:26:14.052018 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9648 00:26:14.055335 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9649 00:26:14.061902 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9650 00:26:14.065389 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9651 00:26:14.071648 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9652 00:26:14.075138 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9653 00:26:14.078151 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9654 00:26:14.084973 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9655 00:26:14.088324 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9656 00:26:14.094893 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9657 00:26:14.097853 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9658 00:26:14.101426 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9659 00:26:14.107941 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9660 00:26:14.111229 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9661 00:26:14.117854 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9662 00:26:14.121308 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9663 00:26:14.127664 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9664 00:26:14.130931 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9665 00:26:14.134388 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9666 00:26:14.140681 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9667 00:26:14.143979 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9668 00:26:14.150722 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9669 00:26:14.154139 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9670 00:26:14.160488 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9671 00:26:14.164052 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9672 00:26:14.167498 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9673 00:26:14.173792 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9674 00:26:14.177287 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9675 00:26:14.184047 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9676 00:26:14.187205 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9677 00:26:14.190759 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9678 00:26:14.197102 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9679 00:26:14.200791 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9680 00:26:14.207235 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9681 00:26:14.210755 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9682 00:26:14.217241 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9683 00:26:14.220599 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9684 00:26:14.223768 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9685 00:26:14.229997 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9686 00:26:14.233447 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9687 00:26:14.240198 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9688 00:26:14.243755 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9689 00:26:14.246747 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9690 00:26:14.253497 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9691 00:26:14.257014 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9692 00:26:14.263377 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9693 00:26:14.266927 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9694 00:26:14.273543 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9695 00:26:14.276895 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9696 00:26:14.280127 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9697 00:26:14.286962 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9698 00:26:14.289922 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9699 00:26:14.296776 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9700 00:26:14.299977 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9701 00:26:14.303485 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9702 00:26:14.309797 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9703 00:26:14.313365 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9704 00:26:14.316393 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9705 00:26:14.319825 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9706 00:26:14.326275 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9707 00:26:14.329666 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9708 00:26:14.333059 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9709 00:26:14.339632 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9710 00:26:14.342912 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9711 00:26:14.346198 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9712 00:26:14.352703 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9713 00:26:14.355938 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9714 00:26:14.362820 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9715 00:26:14.366284 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9716 00:26:14.369344 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9717 00:26:14.375927 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9718 00:26:14.379481 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9719 00:26:14.382922 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9720 00:26:14.389481 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9721 00:26:14.392675 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9722 00:26:14.399413 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9723 00:26:14.402353 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9724 00:26:14.405901 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9725 00:26:14.412670 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9726 00:26:14.415774 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9727 00:26:14.419446 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9728 00:26:14.425730 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9729 00:26:14.429301 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9730 00:26:14.435872 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9731 00:26:14.438860 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9732 00:26:14.442250 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9733 00:26:14.448893 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9734 00:26:14.452272 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9735 00:26:14.455505 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9736 00:26:14.462275 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9737 00:26:14.465567 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9738 00:26:14.472112 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9739 00:26:14.475076 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9740 00:26:14.478681 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9741 00:26:14.485130 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9742 00:26:14.488577 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9743 00:26:14.491459 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9744 00:26:14.494900 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9745 00:26:14.498340 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9746 00:26:14.504819 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9747 00:26:14.508332 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9748 00:26:14.511882 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9749 00:26:14.514818 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9750 00:26:14.521340 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9751 00:26:14.525064 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9752 00:26:14.528227 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9753 00:26:14.534868 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9754 00:26:14.537975 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9755 00:26:14.541621 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9756 00:26:14.548197 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9757 00:26:14.551194 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9758 00:26:14.558022 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9759 00:26:14.561255 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9760 00:26:14.564828 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9761 00:26:14.571278 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9762 00:26:14.574734 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9763 00:26:14.581183 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9764 00:26:14.584562 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9765 00:26:14.587562 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9766 00:26:14.594494 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9767 00:26:14.597753 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9768 00:26:14.604253 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9769 00:26:14.607569 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9770 00:26:14.610673 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9771 00:26:14.617724 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9772 00:26:14.620598 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9773 00:26:14.627563 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9774 00:26:14.630445 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9775 00:26:14.637227 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9776 00:26:14.640795 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9777 00:26:14.643865 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9778 00:26:14.650703 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9779 00:26:14.653723 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9780 00:26:14.660821 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9781 00:26:14.663685 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9782 00:26:14.667084 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9783 00:26:14.673764 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9784 00:26:14.676857 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9785 00:26:14.683585 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9786 00:26:14.686671 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9787 00:26:14.690415 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9788 00:26:14.696826 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9789 00:26:14.700267 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9790 00:26:14.706742 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9791 00:26:14.709772 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9792 00:26:14.716733 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9793 00:26:14.719880 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9794 00:26:14.723062 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9795 00:26:14.729607 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9796 00:26:14.733204 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9797 00:26:14.739802 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9798 00:26:14.743329 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9799 00:26:14.749621 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9800 00:26:14.752711 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9801 00:26:14.756097 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9802 00:26:14.762730 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9803 00:26:14.766192 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9804 00:26:14.772547 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9805 00:26:14.776121 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9806 00:26:14.779649 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9807 00:26:14.786105 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9808 00:26:14.789345 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9809 00:26:14.795771 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9810 00:26:14.799034 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9811 00:26:14.802731 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9812 00:26:14.809360 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9813 00:26:14.812704 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9814 00:26:14.819191 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9815 00:26:14.822700 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9816 00:26:14.829247 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9817 00:26:14.832727 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9818 00:26:14.835629 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9819 00:26:14.842096 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9820 00:26:14.845557 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9821 00:26:14.852015 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9822 00:26:14.855397 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9823 00:26:14.858896 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9824 00:26:14.865328 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9825 00:26:14.868796 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9826 00:26:14.875210 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9827 00:26:14.878779 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9828 00:26:14.885290 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9829 00:26:14.888562 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9830 00:26:14.891606 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9831 00:26:14.898211 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9832 00:26:14.901679 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9833 00:26:14.908136 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9834 00:26:14.911728 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9835 00:26:14.918521 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9836 00:26:14.921538 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9837 00:26:14.928082 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9838 00:26:14.931501 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9839 00:26:14.934815 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9840 00:26:14.941413 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9841 00:26:14.944929 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9842 00:26:14.951482 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9843 00:26:14.954573 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9844 00:26:14.961612 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9845 00:26:14.964464 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9846 00:26:14.971353 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9847 00:26:14.974621 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9848 00:26:14.978052 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9849 00:26:14.984569 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9850 00:26:14.988075 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9851 00:26:14.994357 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9852 00:26:14.997553 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9853 00:26:15.004313 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9854 00:26:15.007863 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9855 00:26:15.010811 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9856 00:26:15.017405 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9857 00:26:15.020944 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9858 00:26:15.027361 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9859 00:26:15.030873 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9860 00:26:15.037835 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9861 00:26:15.040988 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9862 00:26:15.044077 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9863 00:26:15.050695 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9864 00:26:15.054088 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9865 00:26:15.060445 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9866 00:26:15.063977 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9867 00:26:15.070513 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9868 00:26:15.073983 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9869 00:26:15.080288 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9870 00:26:15.083912 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9871 00:26:15.087259 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9872 00:26:15.093729 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9873 00:26:15.097168 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9874 00:26:15.103554 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9875 00:26:15.107296 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9876 00:26:15.110231 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9877 00:26:15.116630 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9878 00:26:15.120302 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9879 00:26:15.126754 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9880 00:26:15.130300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9881 00:26:15.136994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9882 00:26:15.139932 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9883 00:26:15.146398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9884 00:26:15.149764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9885 00:26:15.156350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9886 00:26:15.159956 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9887 00:26:15.166493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9888 00:26:15.169818 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9889 00:26:15.176458 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9890 00:26:15.179383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9891 00:26:15.186265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9892 00:26:15.189360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9893 00:26:15.196194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9894 00:26:15.199783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9895 00:26:15.206142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9896 00:26:15.209347 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9897 00:26:15.215907 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9898 00:26:15.219422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9899 00:26:15.225837 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9900 00:26:15.229280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9901 00:26:15.235636 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9902 00:26:15.239196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9903 00:26:15.245602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9904 00:26:15.249090 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9905 00:26:15.255653 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9906 00:26:15.259069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9907 00:26:15.265718 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9908 00:26:15.265795 INFO: [APUAPC] vio 0
9909 00:26:15.272388 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9910 00:26:15.275465 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9911 00:26:15.279086 INFO: [APUAPC] D0_APC_0: 0x400510
9912 00:26:15.282608 INFO: [APUAPC] D0_APC_1: 0x0
9913 00:26:15.285554 INFO: [APUAPC] D0_APC_2: 0x1540
9914 00:26:15.289159 INFO: [APUAPC] D0_APC_3: 0x0
9915 00:26:15.292172 INFO: [APUAPC] D1_APC_0: 0xffffffff
9916 00:26:15.295565 INFO: [APUAPC] D1_APC_1: 0xffffffff
9917 00:26:15.298783 INFO: [APUAPC] D1_APC_2: 0x3fffff
9918 00:26:15.301831 INFO: [APUAPC] D1_APC_3: 0x0
9919 00:26:15.305584 INFO: [APUAPC] D2_APC_0: 0xffffffff
9920 00:26:15.308518 INFO: [APUAPC] D2_APC_1: 0xffffffff
9921 00:26:15.311865 INFO: [APUAPC] D2_APC_2: 0x3fffff
9922 00:26:15.315138 INFO: [APUAPC] D2_APC_3: 0x0
9923 00:26:15.318463 INFO: [APUAPC] D3_APC_0: 0xffffffff
9924 00:26:15.321691 INFO: [APUAPC] D3_APC_1: 0xffffffff
9925 00:26:15.325242 INFO: [APUAPC] D3_APC_2: 0x3fffff
9926 00:26:15.328251 INFO: [APUAPC] D3_APC_3: 0x0
9927 00:26:15.331700 INFO: [APUAPC] D4_APC_0: 0xffffffff
9928 00:26:15.335207 INFO: [APUAPC] D4_APC_1: 0xffffffff
9929 00:26:15.338184 INFO: [APUAPC] D4_APC_2: 0x3fffff
9930 00:26:15.341800 INFO: [APUAPC] D4_APC_3: 0x0
9931 00:26:15.345316 INFO: [APUAPC] D5_APC_0: 0xffffffff
9932 00:26:15.348165 INFO: [APUAPC] D5_APC_1: 0xffffffff
9933 00:26:15.351818 INFO: [APUAPC] D5_APC_2: 0x3fffff
9934 00:26:15.351894 INFO: [APUAPC] D5_APC_3: 0x0
9935 00:26:15.358070 INFO: [APUAPC] D6_APC_0: 0xffffffff
9936 00:26:15.361871 INFO: [APUAPC] D6_APC_1: 0xffffffff
9937 00:26:15.364595 INFO: [APUAPC] D6_APC_2: 0x3fffff
9938 00:26:15.364723 INFO: [APUAPC] D6_APC_3: 0x0
9939 00:26:15.368174 INFO: [APUAPC] D7_APC_0: 0xffffffff
9940 00:26:15.371457 INFO: [APUAPC] D7_APC_1: 0xffffffff
9941 00:26:15.374990 INFO: [APUAPC] D7_APC_2: 0x3fffff
9942 00:26:15.377900 INFO: [APUAPC] D7_APC_3: 0x0
9943 00:26:15.381689 INFO: [APUAPC] D8_APC_0: 0xffffffff
9944 00:26:15.384783 INFO: [APUAPC] D8_APC_1: 0xffffffff
9945 00:26:15.388327 INFO: [APUAPC] D8_APC_2: 0x3fffff
9946 00:26:15.391638 INFO: [APUAPC] D8_APC_3: 0x0
9947 00:26:15.394576 INFO: [APUAPC] D9_APC_0: 0xffffffff
9948 00:26:15.398044 INFO: [APUAPC] D9_APC_1: 0xffffffff
9949 00:26:15.401442 INFO: [APUAPC] D9_APC_2: 0x3fffff
9950 00:26:15.404865 INFO: [APUAPC] D9_APC_3: 0x0
9951 00:26:15.408286 INFO: [APUAPC] D10_APC_0: 0xffffffff
9952 00:26:15.411161 INFO: [APUAPC] D10_APC_1: 0xffffffff
9953 00:26:15.414382 INFO: [APUAPC] D10_APC_2: 0x3fffff
9954 00:26:15.417645 INFO: [APUAPC] D10_APC_3: 0x0
9955 00:26:15.420987 INFO: [APUAPC] D11_APC_0: 0xffffffff
9956 00:26:15.424307 INFO: [APUAPC] D11_APC_1: 0xffffffff
9957 00:26:15.427826 INFO: [APUAPC] D11_APC_2: 0x3fffff
9958 00:26:15.430998 INFO: [APUAPC] D11_APC_3: 0x0
9959 00:26:15.434606 INFO: [APUAPC] D12_APC_0: 0xffffffff
9960 00:26:15.437510 INFO: [APUAPC] D12_APC_1: 0xffffffff
9961 00:26:15.440965 INFO: [APUAPC] D12_APC_2: 0x3fffff
9962 00:26:15.444033 INFO: [APUAPC] D12_APC_3: 0x0
9963 00:26:15.447573 INFO: [APUAPC] D13_APC_0: 0xffffffff
9964 00:26:15.450665 INFO: [APUAPC] D13_APC_1: 0xffffffff
9965 00:26:15.454131 INFO: [APUAPC] D13_APC_2: 0x3fffff
9966 00:26:15.457668 INFO: [APUAPC] D13_APC_3: 0x0
9967 00:26:15.460552 INFO: [APUAPC] D14_APC_0: 0xffffffff
9968 00:26:15.467391 INFO: [APUAPC] D14_APC_1: 0xffffffff
9969 00:26:15.470564 INFO: [APUAPC] D14_APC_2: 0x3fffff
9970 00:26:15.470663 INFO: [APUAPC] D14_APC_3: 0x0
9971 00:26:15.473970 INFO: [APUAPC] D15_APC_0: 0xffffffff
9972 00:26:15.480863 INFO: [APUAPC] D15_APC_1: 0xffffffff
9973 00:26:15.483715 INFO: [APUAPC] D15_APC_2: 0x3fffff
9974 00:26:15.483791 INFO: [APUAPC] D15_APC_3: 0x0
9975 00:26:15.487168 INFO: [APUAPC] APC_CON: 0x4
9976 00:26:15.490582 INFO: [NOCDAPC] D0_APC_0: 0x0
9977 00:26:15.493623 INFO: [NOCDAPC] D0_APC_1: 0x0
9978 00:26:15.497188 INFO: [NOCDAPC] D1_APC_0: 0x0
9979 00:26:15.500520 INFO: [NOCDAPC] D1_APC_1: 0xfff
9980 00:26:15.503983 INFO: [NOCDAPC] D2_APC_0: 0x0
9981 00:26:15.506926 INFO: [NOCDAPC] D2_APC_1: 0xfff
9982 00:26:15.510334 INFO: [NOCDAPC] D3_APC_0: 0x0
9983 00:26:15.513689 INFO: [NOCDAPC] D3_APC_1: 0xfff
9984 00:26:15.513764 INFO: [NOCDAPC] D4_APC_0: 0x0
9985 00:26:15.516944 INFO: [NOCDAPC] D4_APC_1: 0xfff
9986 00:26:15.520130 INFO: [NOCDAPC] D5_APC_0: 0x0
9987 00:26:15.523868 INFO: [NOCDAPC] D5_APC_1: 0xfff
9988 00:26:15.527061 INFO: [NOCDAPC] D6_APC_0: 0x0
9989 00:26:15.530286 INFO: [NOCDAPC] D6_APC_1: 0xfff
9990 00:26:15.533361 INFO: [NOCDAPC] D7_APC_0: 0x0
9991 00:26:15.537185 INFO: [NOCDAPC] D7_APC_1: 0xfff
9992 00:26:15.540464 INFO: [NOCDAPC] D8_APC_0: 0x0
9993 00:26:15.543624 INFO: [NOCDAPC] D8_APC_1: 0xfff
9994 00:26:15.546571 INFO: [NOCDAPC] D9_APC_0: 0x0
9995 00:26:15.546650 INFO: [NOCDAPC] D9_APC_1: 0xfff
9996 00:26:15.550223 INFO: [NOCDAPC] D10_APC_0: 0x0
9997 00:26:15.553776 INFO: [NOCDAPC] D10_APC_1: 0xfff
9998 00:26:15.556568 INFO: [NOCDAPC] D11_APC_0: 0x0
9999 00:26:15.560120 INFO: [NOCDAPC] D11_APC_1: 0xfff
10000 00:26:15.563693 INFO: [NOCDAPC] D12_APC_0: 0x0
10001 00:26:15.566743 INFO: [NOCDAPC] D12_APC_1: 0xfff
10002 00:26:15.569698 INFO: [NOCDAPC] D13_APC_0: 0x0
10003 00:26:15.573098 INFO: [NOCDAPC] D13_APC_1: 0xfff
10004 00:26:15.576346 INFO: [NOCDAPC] D14_APC_0: 0x0
10005 00:26:15.579929 INFO: [NOCDAPC] D14_APC_1: 0xfff
10006 00:26:15.583230 INFO: [NOCDAPC] D15_APC_0: 0x0
10007 00:26:15.586697 INFO: [NOCDAPC] D15_APC_1: 0xfff
10008 00:26:15.589597 INFO: [NOCDAPC] APC_CON: 0x4
10009 00:26:15.593235 INFO: [APUAPC] set_apusys_apc done
10010 00:26:15.596262 INFO: [DEVAPC] devapc_init done
10011 00:26:15.599626 INFO: GICv3 without legacy support detected.
10012 00:26:15.602750 INFO: ARM GICv3 driver initialized in EL3
10013 00:26:15.606236 INFO: Maximum SPI INTID supported: 639
10014 00:26:15.609410 INFO: BL31: Initializing runtime services
10015 00:26:15.615888 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10016 00:26:15.619561 INFO: SPM: enable CPC mode
10017 00:26:15.622923 INFO: mcdi ready for mcusys-off-idle and system suspend
10018 00:26:15.629274 INFO: BL31: Preparing for EL3 exit to normal world
10019 00:26:15.632499 INFO: Entry point address = 0x80000000
10020 00:26:15.636021 INFO: SPSR = 0x8
10021 00:26:15.640327
10022 00:26:15.640426
10023 00:26:15.640512
10024 00:26:15.643904 Starting depthcharge on Spherion...
10025 00:26:15.643980
10026 00:26:15.644038 Wipe memory regions:
10027 00:26:15.644092
10028 00:26:15.644746 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10029 00:26:15.644869 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10030 00:26:15.644945 Setting prompt string to ['asurada:']
10031 00:26:15.645018 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10032 00:26:15.646995 [0x00000040000000, 0x00000054600000)
10033 00:26:15.769368
10034 00:26:15.769483 [0x00000054660000, 0x00000080000000)
10035 00:26:16.029649
10036 00:26:16.029795 [0x000000821a7280, 0x000000ffe64000)
10037 00:26:16.774619
10038 00:26:16.774782 [0x00000100000000, 0x00000240000000)
10039 00:26:18.665149
10040 00:26:18.668482 Initializing XHCI USB controller at 0x11200000.
10041 00:26:19.706609
10042 00:26:19.709853 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10043 00:26:19.709975
10044 00:26:19.710092
10045 00:26:19.710413 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10047 00:26:19.810708 asurada: tftpboot 192.168.201.1 14479209/tftp-deploy-tqaqu76_/kernel/image.itb 14479209/tftp-deploy-tqaqu76_/kernel/cmdline
10048 00:26:19.810972 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10049 00:26:19.811081 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10050 00:26:19.815516 tftpboot 192.168.201.1 14479209/tftp-deploy-tqaqu76_/kernel/image.ittp-deploy-tqaqu76_/kernel/cmdline
10051 00:26:19.815597
10052 00:26:19.815657 Waiting for link
10053 00:26:19.973552
10054 00:26:19.973676 R8152: Initializing
10055 00:26:19.973739
10056 00:26:19.976934 Version 6 (ocp_data = 5c30)
10057 00:26:19.977002
10058 00:26:19.980517 R8152: Done initializing
10059 00:26:19.980607
10060 00:26:19.980685 Adding net device
10061 00:26:21.885744
10062 00:26:21.885888 done.
10063 00:26:21.885952
10064 00:26:21.886040 MAC: 00:24:32:30:78:ff
10065 00:26:21.886124
10066 00:26:21.889083 Sending DHCP discover... done.
10067 00:26:21.889151
10068 00:26:21.892685 Waiting for reply... done.
10069 00:26:21.892779
10070 00:26:21.895678 Sending DHCP request... done.
10071 00:26:21.895787
10072 00:26:21.895846 Waiting for reply... done.
10073 00:26:21.895902
10074 00:26:21.898854 My ip is 192.168.201.21
10075 00:26:21.898930
10076 00:26:21.902383 The DHCP server ip is 192.168.201.1
10077 00:26:21.902477
10078 00:26:21.905735 TFTP server IP predefined by user: 192.168.201.1
10079 00:26:21.905815
10080 00:26:21.912328 Bootfile predefined by user: 14479209/tftp-deploy-tqaqu76_/kernel/image.itb
10081 00:26:21.912407
10082 00:26:21.915817 Sending tftp read request... done.
10083 00:26:21.915896
10084 00:26:21.918941 Waiting for the transfer...
10085 00:26:21.921935
10086 00:26:22.458643 00000000 ################################################################
10087 00:26:22.458774
10088 00:26:22.983402 00080000 ################################################################
10089 00:26:22.983561
10090 00:26:23.525702 00100000 ################################################################
10091 00:26:23.525836
10092 00:26:24.055428 00180000 ################################################################
10093 00:26:24.055557
10094 00:26:24.597857 00200000 ################################################################
10095 00:26:24.598037
10096 00:26:25.136011 00280000 ################################################################
10097 00:26:25.136174
10098 00:26:25.670638 00300000 ################################################################
10099 00:26:25.670800
10100 00:26:26.203550 00380000 ################################################################
10101 00:26:26.203734
10102 00:26:26.759762 00400000 ################################################################
10103 00:26:26.759904
10104 00:26:27.309374 00480000 ################################################################
10105 00:26:27.309526
10106 00:26:27.853190 00500000 ################################################################
10107 00:26:27.853332
10108 00:26:28.372355 00580000 ################################################################
10109 00:26:28.372502
10110 00:26:28.904729 00600000 ################################################################
10111 00:26:28.904901
10112 00:26:29.428016 00680000 ################################################################
10113 00:26:29.428208
10114 00:26:29.950796 00700000 ################################################################
10115 00:26:29.950969
10116 00:26:30.492146 00780000 ################################################################
10117 00:26:30.492344
10118 00:26:31.027533 00800000 ################################################################
10119 00:26:31.027735
10120 00:26:31.569245 00880000 ################################################################
10121 00:26:31.569435
10122 00:26:32.112484 00900000 ################################################################
10123 00:26:32.112656
10124 00:26:32.646831 00980000 ################################################################
10125 00:26:32.647018
10126 00:26:33.165518 00a00000 ################################################################
10127 00:26:33.165667
10128 00:26:33.687223 00a80000 ################################################################
10129 00:26:33.687402
10130 00:26:34.216985 00b00000 ################################################################
10131 00:26:34.217153
10132 00:26:34.740677 00b80000 ################################################################
10133 00:26:34.740861
10134 00:26:35.275749 00c00000 ################################################################
10135 00:26:35.275925
10136 00:26:35.810280 00c80000 ################################################################
10137 00:26:35.810469
10138 00:26:36.344262 00d00000 ################################################################
10139 00:26:36.344406
10140 00:26:36.868636 00d80000 ################################################################
10141 00:26:36.868776
10142 00:26:37.392555 00e00000 ################################################################
10143 00:26:37.392719
10144 00:26:37.933702 00e80000 ################################################################
10145 00:26:37.933834
10146 00:26:38.459816 00f00000 ################################################################
10147 00:26:38.460005
10148 00:26:38.994157 00f80000 ################################################################
10149 00:26:38.994284
10150 00:26:39.534099 01000000 ################################################################
10151 00:26:39.534235
10152 00:26:40.058297 01080000 ################################################################
10153 00:26:40.058433
10154 00:26:40.595259 01100000 ################################################################
10155 00:26:40.595442
10156 00:26:41.126084 01180000 ################################################################
10157 00:26:41.126217
10158 00:26:41.659099 01200000 ################################################################
10159 00:26:41.659229
10160 00:26:42.194780 01280000 ################################################################
10161 00:26:42.194963
10162 00:26:42.720103 01300000 ################################################################
10163 00:26:42.720243
10164 00:26:43.240873 01380000 ################################################################
10165 00:26:43.241079
10166 00:26:43.777097 01400000 ################################################################
10167 00:26:43.777240
10168 00:26:44.312100 01480000 ################################################################
10169 00:26:44.312217
10170 00:26:44.837215 01500000 ################################################################
10171 00:26:44.837373
10172 00:26:45.372997 01580000 ################################################################
10173 00:26:45.373114
10174 00:26:45.920023 01600000 ################################################################
10175 00:26:45.920145
10176 00:26:46.464101 01680000 ################################################################
10177 00:26:46.464249
10178 00:26:46.998886 01700000 ################################################################
10179 00:26:46.999019
10180 00:26:47.526498 01780000 ################################################################
10181 00:26:47.526639
10182 00:26:48.070964 01800000 ################################################################
10183 00:26:48.071164
10184 00:26:48.607134 01880000 ################################################################
10185 00:26:48.607263
10186 00:26:49.124562 01900000 ################################################################
10187 00:26:49.124730
10188 00:26:49.663086 01980000 ################################################################
10189 00:26:49.663213
10190 00:26:50.197598 01a00000 ################################################################
10191 00:26:50.197727
10192 00:26:50.729574 01a80000 ################################################################
10193 00:26:50.729702
10194 00:26:51.282189 01b00000 ################################################################
10195 00:26:51.282398
10196 00:26:51.807666 01b80000 ################################################################
10197 00:26:51.807793
10198 00:26:52.335086 01c00000 ################################################################
10199 00:26:52.335257
10200 00:26:52.873144 01c80000 ################################################################
10201 00:26:52.873264
10202 00:26:53.400152 01d00000 ################################################################
10203 00:26:53.400264
10204 00:26:53.928282 01d80000 ################################################################
10205 00:26:53.928401
10206 00:26:54.457284 01e00000 ################################################################
10207 00:26:54.457403
10208 00:26:54.992258 01e80000 ################################################################
10209 00:26:54.992375
10210 00:26:55.530790 01f00000 ################################################################
10211 00:26:55.530934
10212 00:26:56.047975 01f80000 ################################################################
10213 00:26:56.048150
10214 00:26:56.582095 02000000 ################################################################
10215 00:26:56.582265
10216 00:26:57.107498 02080000 ################################################################
10217 00:26:57.107627
10218 00:26:57.651083 02100000 ################################################################
10219 00:26:57.651272
10220 00:26:58.206894 02180000 ################################################################
10221 00:26:58.207078
10222 00:26:58.754515 02200000 ################################################################
10223 00:26:58.754634
10224 00:26:59.303100 02280000 ################################################################
10225 00:26:59.303261
10226 00:26:59.855321 02300000 ################################################################
10227 00:26:59.855436
10228 00:27:00.396377 02380000 ################################################################
10229 00:27:00.396491
10230 00:27:00.944470 02400000 ################################################################
10231 00:27:00.944604
10232 00:27:01.485006 02480000 ################################################################
10233 00:27:01.485130
10234 00:27:02.026557 02500000 ################################################################
10235 00:27:02.026679
10236 00:27:02.590436 02580000 ################################################################
10237 00:27:02.590559
10238 00:27:03.123090 02600000 ################################################################
10239 00:27:03.123218
10240 00:27:03.680195 02680000 ################################################################
10241 00:27:03.680326
10242 00:27:04.230150 02700000 ################################################################
10243 00:27:04.230317
10244 00:27:04.773977 02780000 ################################################################
10245 00:27:04.774092
10246 00:27:05.314809 02800000 ################################################################
10247 00:27:05.314922
10248 00:27:05.843354 02880000 ################################################################
10249 00:27:05.843498
10250 00:27:06.379197 02900000 ################################################################
10251 00:27:06.379374
10252 00:27:06.916552 02980000 ################################################################
10253 00:27:06.916698
10254 00:27:07.439772 02a00000 ################################################################
10255 00:27:07.439926
10256 00:27:07.964173 02a80000 ################################################################
10257 00:27:07.964305
10258 00:27:08.504704 02b00000 ################################################################
10259 00:27:08.504873
10260 00:27:09.023165 02b80000 ################################################################
10261 00:27:09.023293
10262 00:27:09.559650 02c00000 ################################################################
10263 00:27:09.559810
10264 00:27:10.095620 02c80000 ################################################################
10265 00:27:10.095752
10266 00:27:10.632860 02d00000 ################################################################
10267 00:27:10.632995
10268 00:27:11.164438 02d80000 ################################################################
10269 00:27:11.164587
10270 00:27:11.688539 02e00000 ################################################################
10271 00:27:11.688696
10272 00:27:12.230980 02e80000 ################################################################
10273 00:27:12.231097
10274 00:27:12.757959 02f00000 ################################################################
10275 00:27:12.758117
10276 00:27:13.297446 02f80000 ################################################################
10277 00:27:13.297567
10278 00:27:13.831206 03000000 ################################################################
10279 00:27:13.831329
10280 00:27:14.375277 03080000 ################################################################
10281 00:27:14.375402
10282 00:27:14.902958 03100000 ################################################################
10283 00:27:14.903083
10284 00:27:15.435890 03180000 ################################################################
10285 00:27:15.436012
10286 00:27:15.965335 03200000 ################################################################
10287 00:27:15.965507
10288 00:27:16.501712 03280000 ################################################################
10289 00:27:16.501860
10290 00:27:17.047660 03300000 ################################################################
10291 00:27:17.047771
10292 00:27:17.464739 03380000 ################################################# done.
10293 00:27:17.464899
10294 00:27:17.468031 The bootfile was 54400178 bytes long.
10295 00:27:17.468157
10296 00:27:17.471362 Sending tftp read request... done.
10297 00:27:17.471439
10298 00:27:17.471498 Waiting for the transfer...
10299 00:27:17.471553
10300 00:27:17.474568 00000000 # done.
10301 00:27:17.474646
10302 00:27:17.481260 Command line loaded dynamically from TFTP file: 14479209/tftp-deploy-tqaqu76_/kernel/cmdline
10303 00:27:17.481339
10304 00:27:17.494463 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10305 00:27:17.494546
10306 00:27:17.497837 Loading FIT.
10307 00:27:17.497914
10308 00:27:17.501151 Image ramdisk-1 has 41225997 bytes.
10309 00:27:17.501228
10310 00:27:17.501288 Image fdt-1 has 47258 bytes.
10311 00:27:17.504430
10312 00:27:17.504506 Image kernel-1 has 13124896 bytes.
10313 00:27:17.504565
10314 00:27:17.514444 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10315 00:27:17.514527
10316 00:27:17.531031 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10317 00:27:17.533723
10318 00:27:17.537169 Choosing best match conf-1 for compat google,spherion-rev2.
10319 00:27:17.541655
10320 00:27:17.546188 Connected to device vid:did:rid of 1ae0:0028:00
10321 00:27:17.554697
10322 00:27:17.557504 tpm_get_response: command 0x17b, return code 0x0
10323 00:27:17.557584
10324 00:27:17.561050 ec_init: CrosEC protocol v3 supported (256, 248)
10325 00:27:17.565812
10326 00:27:17.569330 tpm_cleanup: add release locality here.
10327 00:27:17.569412
10328 00:27:17.569500 Shutting down all USB controllers.
10329 00:27:17.572861
10330 00:27:17.572939 Removing current net device
10331 00:27:17.573001
10332 00:27:17.579535 Exiting depthcharge with code 4 at timestamp: 91239055
10333 00:27:17.579639
10334 00:27:17.582845 LZMA decompressing kernel-1 to 0x821a6718
10335 00:27:17.582952
10336 00:27:17.585950 LZMA decompressing kernel-1 to 0x40000000
10337 00:27:19.202037
10338 00:27:19.202154 jumping to kernel
10339 00:27:19.202669 end: 2.2.4 bootloader-commands (duration 00:01:04) [common]
10340 00:27:19.202764 start: 2.2.5 auto-login-action (timeout 00:03:23) [common]
10341 00:27:19.202835 Setting prompt string to ['Linux version [0-9]']
10342 00:27:19.202899 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10343 00:27:19.202963 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10344 00:27:19.284695
10345 00:27:19.287752 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10346 00:27:19.291450 start: 2.2.5.1 login-action (timeout 00:03:23) [common]
10347 00:27:19.291553 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10348 00:27:19.291624 Setting prompt string to []
10349 00:27:19.291698 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10350 00:27:19.291769 Using line separator: #'\n'#
10351 00:27:19.291824 No login prompt set.
10352 00:27:19.291883 Parsing kernel messages
10353 00:27:19.291936 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10354 00:27:19.292038 [login-action] Waiting for messages, (timeout 00:03:23)
10355 00:27:19.292102 Waiting using forced prompt support (timeout 00:01:42)
10356 00:27:19.311061 [ 0.000000] Linux version 6.1.94-cip23 (KernelCI@build-j239242-arm64-gcc-10-defconfig-arm64-chromebook-c5lwc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024
10357 00:27:19.314606 [ 0.000000] random: crng init done
10358 00:27:19.321230 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10359 00:27:19.324209 [ 0.000000] efi: UEFI not found.
10360 00:27:19.330698 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10361 00:27:19.337677 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10362 00:27:19.347643 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10363 00:27:19.357426 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10364 00:27:19.363997 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10365 00:27:19.370622 [ 0.000000] printk: bootconsole [mtk8250] enabled
10366 00:27:19.377215 [ 0.000000] NUMA: No NUMA configuration found
10367 00:27:19.383568 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10368 00:27:19.387069 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10369 00:27:19.390341 [ 0.000000] Zone ranges:
10370 00:27:19.397200 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10371 00:27:19.400254 [ 0.000000] DMA32 empty
10372 00:27:19.406685 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10373 00:27:19.410282 [ 0.000000] Movable zone start for each node
10374 00:27:19.413258 [ 0.000000] Early memory node ranges
10375 00:27:19.419720 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10376 00:27:19.426299 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10377 00:27:19.433334 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10378 00:27:19.439938 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10379 00:27:19.446037 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10380 00:27:19.452948 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10381 00:27:19.509127 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10382 00:27:19.515638 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10383 00:27:19.522733 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10384 00:27:19.525857 [ 0.000000] psci: probing for conduit method from DT.
10385 00:27:19.532362 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10386 00:27:19.535860 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10387 00:27:19.542438 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10388 00:27:19.545923 [ 0.000000] psci: SMC Calling Convention v1.2
10389 00:27:19.552245 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10390 00:27:19.555705 [ 0.000000] Detected VIPT I-cache on CPU0
10391 00:27:19.562176 [ 0.000000] CPU features: detected: GIC system register CPU interface
10392 00:27:19.568992 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10393 00:27:19.575524 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10394 00:27:19.582247 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10395 00:27:19.588730 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10396 00:27:19.598855 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10397 00:27:19.601871 [ 0.000000] alternatives: applying boot alternatives
10398 00:27:19.608592 [ 0.000000] Fallback order for Node 0: 0
10399 00:27:19.615436 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10400 00:27:19.618501 [ 0.000000] Policy zone: Normal
10401 00:27:19.631542 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10402 00:27:19.641682 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10403 00:27:19.653583 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10404 00:27:19.663924 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10405 00:27:19.669984 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10406 00:27:19.673551 <6>[ 0.000000] software IO TLB: area num 8.
10407 00:27:19.729793 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10408 00:27:19.879339 <6>[ 0.000000] Memory: 7923804K/8385536K available (18112K kernel code, 4120K rwdata, 22648K rodata, 8512K init, 616K bss, 428964K reserved, 32768K cma-reserved)
10409 00:27:19.885605 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10410 00:27:19.892205 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10411 00:27:19.895580 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10412 00:27:19.902560 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10413 00:27:19.909114 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10414 00:27:19.912079 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10415 00:27:19.922053 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10416 00:27:19.928707 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10417 00:27:19.935140 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10418 00:27:19.941849 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10419 00:27:19.945284 <6>[ 0.000000] GICv3: 608 SPIs implemented
10420 00:27:19.948825 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10421 00:27:19.955451 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10422 00:27:19.958450 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10423 00:27:19.965175 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10424 00:27:19.978682 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10425 00:27:19.988500 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10426 00:27:19.998403 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10427 00:27:20.005939 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10428 00:27:20.019048 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10429 00:27:20.025667 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10430 00:27:20.032055 <6>[ 0.009231] Console: colour dummy device 80x25
10431 00:27:20.042412 <6>[ 0.013948] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10432 00:27:20.045647 <6>[ 0.024390] pid_max: default: 32768 minimum: 301
10433 00:27:20.052230 <6>[ 0.029261] LSM: Security Framework initializing
10434 00:27:20.058662 <6>[ 0.034198] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10435 00:27:20.068683 <6>[ 0.042012] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10436 00:27:20.075265 <6>[ 0.051477] cblist_init_generic: Setting adjustable number of callback queues.
10437 00:27:20.081737 <6>[ 0.058920] cblist_init_generic: Setting shift to 3 and lim to 1.
10438 00:27:20.092223 <6>[ 0.065259] cblist_init_generic: Setting adjustable number of callback queues.
10439 00:27:20.095630 <6>[ 0.072686] cblist_init_generic: Setting shift to 3 and lim to 1.
10440 00:27:20.102207 <6>[ 0.079088] rcu: Hierarchical SRCU implementation.
10441 00:27:20.108529 <6>[ 0.084134] rcu: Max phase no-delay instances is 1000.
10442 00:27:20.115028 <6>[ 0.091158] EFI services will not be available.
10443 00:27:20.118604 <6>[ 0.096145] smp: Bringing up secondary CPUs ...
10444 00:27:20.126320 <6>[ 0.101196] Detected VIPT I-cache on CPU1
10445 00:27:20.133212 <6>[ 0.101268] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10446 00:27:20.139876 <6>[ 0.101299] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10447 00:27:20.142647 <6>[ 0.101628] Detected VIPT I-cache on CPU2
10448 00:27:20.152677 <6>[ 0.101675] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10449 00:27:20.159091 <6>[ 0.101690] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10450 00:27:20.162378 <6>[ 0.101948] Detected VIPT I-cache on CPU3
10451 00:27:20.169469 <6>[ 0.101993] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10452 00:27:20.175945 <6>[ 0.102007] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10453 00:27:20.182280 <6>[ 0.102310] CPU features: detected: Spectre-v4
10454 00:27:20.185867 <6>[ 0.102316] CPU features: detected: Spectre-BHB
10455 00:27:20.189059 <6>[ 0.102321] Detected PIPT I-cache on CPU4
10456 00:27:20.195497 <6>[ 0.102380] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10457 00:27:20.205492 <6>[ 0.102396] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10458 00:27:20.208590 <6>[ 0.102689] Detected PIPT I-cache on CPU5
10459 00:27:20.215619 <6>[ 0.102751] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10460 00:27:20.222121 <6>[ 0.102768] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10461 00:27:20.225061 <6>[ 0.103049] Detected PIPT I-cache on CPU6
10462 00:27:20.235066 <6>[ 0.103114] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10463 00:27:20.242139 <6>[ 0.103130] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10464 00:27:20.245220 <6>[ 0.103431] Detected PIPT I-cache on CPU7
10465 00:27:20.251680 <6>[ 0.103497] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10466 00:27:20.258180 <6>[ 0.103513] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10467 00:27:20.261653 <6>[ 0.103560] smp: Brought up 1 node, 8 CPUs
10468 00:27:20.268291 <6>[ 0.244956] SMP: Total of 8 processors activated.
10469 00:27:20.271805 <6>[ 0.249907] CPU features: detected: 32-bit EL0 Support
10470 00:27:20.281537 <6>[ 0.255271] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10471 00:27:20.288049 <6>[ 0.264072] CPU features: detected: Common not Private translations
10472 00:27:20.294756 <6>[ 0.270588] CPU features: detected: CRC32 instructions
10473 00:27:20.301782 <6>[ 0.275940] CPU features: detected: RCpc load-acquire (LDAPR)
10474 00:27:20.304743 <6>[ 0.281900] CPU features: detected: LSE atomic instructions
10475 00:27:20.311583 <6>[ 0.287717] CPU features: detected: Privileged Access Never
10476 00:27:20.317990 <6>[ 0.293497] CPU features: detected: RAS Extension Support
10477 00:27:20.324473 <6>[ 0.299141] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10478 00:27:20.328053 <6>[ 0.306362] CPU: All CPU(s) started at EL2
10479 00:27:20.334224 <6>[ 0.310679] alternatives: applying system-wide alternatives
10480 00:27:20.344156 <6>[ 0.321525] devtmpfs: initialized
10481 00:27:20.356629 <6>[ 0.330345] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10482 00:27:20.366435 <6>[ 0.340303] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10483 00:27:20.373011 <6>[ 0.348318] pinctrl core: initialized pinctrl subsystem
10484 00:27:20.376510 <6>[ 0.354991] DMI not present or invalid.
10485 00:27:20.382901 <6>[ 0.359402] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10486 00:27:20.392795 <6>[ 0.366183] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10487 00:27:20.399319 <6>[ 0.373770] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10488 00:27:20.409503 <6>[ 0.381994] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10489 00:27:20.412928 <6>[ 0.390239] audit: initializing netlink subsys (disabled)
10490 00:27:20.422921 <5>[ 0.395930] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10491 00:27:20.429400 <6>[ 0.396645] thermal_sys: Registered thermal governor 'step_wise'
10492 00:27:20.435842 <6>[ 0.403895] thermal_sys: Registered thermal governor 'power_allocator'
10493 00:27:20.439136 <6>[ 0.410150] cpuidle: using governor menu
10494 00:27:20.445436 <6>[ 0.421108] NET: Registered PF_QIPCRTR protocol family
10495 00:27:20.452024 <6>[ 0.426585] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10496 00:27:20.459052 <6>[ 0.433690] ASID allocator initialised with 32768 entries
10497 00:27:20.462009 <6>[ 0.440255] Serial: AMBA PL011 UART driver
10498 00:27:20.472040 <4>[ 0.449078] Trying to register duplicate clock ID: 134
10499 00:27:20.529903 <6>[ 0.510282] KASLR enabled
10500 00:27:20.544435 <6>[ 0.517913] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10501 00:27:20.550583 <6>[ 0.524926] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10502 00:27:20.557534 <6>[ 0.531414] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10503 00:27:20.563851 <6>[ 0.538423] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10504 00:27:20.570453 <6>[ 0.544910] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10505 00:27:20.577065 <6>[ 0.551914] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10506 00:27:20.583799 <6>[ 0.558401] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10507 00:27:20.590479 <6>[ 0.565408] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10508 00:27:20.593591 <6>[ 0.572873] ACPI: Interpreter disabled.
10509 00:27:20.602101 <6>[ 0.579317] iommu: Default domain type: Translated
10510 00:27:20.608537 <6>[ 0.584432] iommu: DMA domain TLB invalidation policy: strict mode
10511 00:27:20.612409 <5>[ 0.591094] SCSI subsystem initialized
10512 00:27:20.618636 <6>[ 0.595342] usbcore: registered new interface driver usbfs
10513 00:27:20.625266 <6>[ 0.601073] usbcore: registered new interface driver hub
10514 00:27:20.628575 <6>[ 0.606623] usbcore: registered new device driver usb
10515 00:27:20.635671 <6>[ 0.612734] pps_core: LinuxPPS API ver. 1 registered
10516 00:27:20.645490 <6>[ 0.617930] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10517 00:27:20.648878 <6>[ 0.627273] PTP clock support registered
10518 00:27:20.651836 <6>[ 0.631514] EDAC MC: Ver: 3.0.0
10519 00:27:20.659450 <6>[ 0.636692] FPGA manager framework
10520 00:27:20.666134 <6>[ 0.640369] Advanced Linux Sound Architecture Driver Initialized.
10521 00:27:20.669755 <6>[ 0.647142] vgaarb: loaded
10522 00:27:20.675854 <6>[ 0.650281] clocksource: Switched to clocksource arch_sys_counter
10523 00:27:20.679497 <5>[ 0.656719] VFS: Disk quotas dquot_6.6.0
10524 00:27:20.686221 <6>[ 0.660909] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10525 00:27:20.689232 <6>[ 0.668100] pnp: PnP ACPI: disabled
10526 00:27:20.697514 <6>[ 0.674756] NET: Registered PF_INET protocol family
10527 00:27:20.707623 <6>[ 0.680342] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10528 00:27:20.719004 <6>[ 0.692664] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10529 00:27:20.728634 <6>[ 0.701477] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10530 00:27:20.735072 <6>[ 0.709448] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10531 00:27:20.744999 <6>[ 0.718148] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10532 00:27:20.751877 <6>[ 0.727907] TCP: Hash tables configured (established 65536 bind 65536)
10533 00:27:20.758673 <6>[ 0.734711] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10534 00:27:20.768404 <6>[ 0.741909] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10535 00:27:20.774928 <6>[ 0.749612] NET: Registered PF_UNIX/PF_LOCAL protocol family
10536 00:27:20.781433 <6>[ 0.755757] RPC: Registered named UNIX socket transport module.
10537 00:27:20.784469 <6>[ 0.761911] RPC: Registered udp transport module.
10538 00:27:20.791013 <6>[ 0.766844] RPC: Registered tcp transport module.
10539 00:27:20.797661 <6>[ 0.771776] RPC: Registered tcp NFSv4.1 backchannel transport module.
10540 00:27:20.801323 <6>[ 0.778441] PCI: CLS 0 bytes, default 64
10541 00:27:20.804281 <6>[ 0.782773] Unpacking initramfs...
10542 00:27:20.828343 <6>[ 0.802412] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10543 00:27:20.838536 <6>[ 0.811065] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10544 00:27:20.841823 <6>[ 0.819906] kvm [1]: IPA Size Limit: 40 bits
10545 00:27:20.848307 <6>[ 0.824434] kvm [1]: GICv3: no GICV resource entry
10546 00:27:20.851759 <6>[ 0.829455] kvm [1]: disabling GICv2 emulation
10547 00:27:20.858253 <6>[ 0.834141] kvm [1]: GIC system register CPU interface enabled
10548 00:27:20.861332 <6>[ 0.840308] kvm [1]: vgic interrupt IRQ18
10549 00:27:20.868543 <6>[ 0.844667] kvm [1]: VHE mode initialized successfully
10550 00:27:20.874913 <5>[ 0.851133] Initialise system trusted keyrings
10551 00:27:20.881220 <6>[ 0.855968] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10552 00:27:20.889119 <6>[ 0.865978] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10553 00:27:20.895076 <5>[ 0.872360] NFS: Registering the id_resolver key type
10554 00:27:20.898656 <5>[ 0.877660] Key type id_resolver registered
10555 00:27:20.905233 <5>[ 0.882076] Key type id_legacy registered
10556 00:27:20.911684 <6>[ 0.886357] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10557 00:27:20.918206 <6>[ 0.893277] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10558 00:27:20.925076 <6>[ 0.900967] 9p: Installing v9fs 9p2000 file system support
10559 00:27:20.962038 <5>[ 0.939034] Key type asymmetric registered
10560 00:27:20.965064 <5>[ 0.943363] Asymmetric key parser 'x509' registered
10561 00:27:20.975253 <6>[ 0.948496] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10562 00:27:20.978179 <6>[ 0.956108] io scheduler mq-deadline registered
10563 00:27:20.981890 <6>[ 0.960867] io scheduler kyber registered
10564 00:27:21.000330 <6>[ 0.977723] EINJ: ACPI disabled.
10565 00:27:21.032635 <4>[ 1.003278] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10566 00:27:21.042790 <4>[ 1.013895] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10567 00:27:21.057433 <6>[ 1.034704] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10568 00:27:21.065379 <6>[ 1.042699] printk: console [ttyS0] disabled
10569 00:27:21.093554 <6>[ 1.067324] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10570 00:27:21.100251 <6>[ 1.076807] printk: console [ttyS0] enabled
10571 00:27:21.103713 <6>[ 1.076807] printk: console [ttyS0] enabled
10572 00:27:21.110346 <6>[ 1.085706] printk: bootconsole [mtk8250] disabled
10573 00:27:21.113358 <6>[ 1.085706] printk: bootconsole [mtk8250] disabled
10574 00:27:21.120044 <6>[ 1.096765] SuperH (H)SCI(F) driver initialized
10575 00:27:21.123104 <6>[ 1.102033] msm_serial: driver initialized
10576 00:27:21.137178 <6>[ 1.110907] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10577 00:27:21.147388 <6>[ 1.119449] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10578 00:27:21.154100 <6>[ 1.127991] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10579 00:27:21.163535 <6>[ 1.136618] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10580 00:27:21.170272 <6>[ 1.145326] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10581 00:27:21.180340 <6>[ 1.154049] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10582 00:27:21.189890 <6>[ 1.162590] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10583 00:27:21.196545 <6>[ 1.171382] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10584 00:27:21.206428 <6>[ 1.179924] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10585 00:27:21.218320 <6>[ 1.195264] loop: module loaded
10586 00:27:21.224431 <6>[ 1.201212] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10587 00:27:21.247102 <4>[ 1.224301] mtk-pmic-keys: Failed to locate of_node [id: -1]
10588 00:27:21.253702 <6>[ 1.231053] megasas: 07.719.03.00-rc1
10589 00:27:21.263731 <6>[ 1.240669] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10590 00:27:21.276308 <6>[ 1.253658] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10591 00:27:21.293336 <6>[ 1.270285] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10592 00:27:21.349729 <6>[ 1.320217] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10593 00:27:22.529486 <6>[ 2.507045] Freeing initrd memory: 40252K
10594 00:27:22.541255 <6>[ 2.518893] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10595 00:27:22.552929 <6>[ 2.529998] tun: Universal TUN/TAP device driver, 1.6
10596 00:27:22.555859 <6>[ 2.536073] thunder_xcv, ver 1.0
10597 00:27:22.559386 <6>[ 2.539578] thunder_bgx, ver 1.0
10598 00:27:22.562386 <6>[ 2.543070] nicpf, ver 1.0
10599 00:27:22.573000 <6>[ 2.547095] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10600 00:27:22.576612 <6>[ 2.554571] hns3: Copyright (c) 2017 Huawei Corporation.
10601 00:27:22.583073 <6>[ 2.560160] hclge is initializing
10602 00:27:22.586529 <6>[ 2.563741] e1000: Intel(R) PRO/1000 Network Driver
10603 00:27:22.593116 <6>[ 2.568869] e1000: Copyright (c) 1999-2006 Intel Corporation.
10604 00:27:22.596505 <6>[ 2.574881] e1000e: Intel(R) PRO/1000 Network Driver
10605 00:27:22.603049 <6>[ 2.580097] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10606 00:27:22.609350 <6>[ 2.586290] igb: Intel(R) Gigabit Ethernet Network Driver
10607 00:27:22.616025 <6>[ 2.591941] igb: Copyright (c) 2007-2014 Intel Corporation.
10608 00:27:22.623132 <6>[ 2.597777] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10609 00:27:22.629592 <6>[ 2.604295] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10610 00:27:22.632440 <6>[ 2.610753] sky2: driver version 1.30
10611 00:27:22.639311 <6>[ 2.615677] usbcore: registered new device driver r8152-cfgselector
10612 00:27:22.645700 <6>[ 2.622211] usbcore: registered new interface driver r8152
10613 00:27:22.652140 <6>[ 2.628035] VFIO - User Level meta-driver version: 0.3
10614 00:27:22.658907 <6>[ 2.636280] usbcore: registered new interface driver usb-storage
10615 00:27:22.665482 <6>[ 2.642727] usbcore: registered new device driver onboard-usb-hub
10616 00:27:22.674699 <6>[ 2.651908] mt6397-rtc mt6359-rtc: registered as rtc0
10617 00:27:22.684636 <6>[ 2.657393] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-21T00:27:22 UTC (1718929642)
10618 00:27:22.687570 <6>[ 2.666976] i2c_dev: i2c /dev entries driver
10619 00:27:22.701634 <4>[ 2.678910] cpu cpu0: supply cpu not found, using dummy regulator
10620 00:27:22.708469 <4>[ 2.685332] cpu cpu1: supply cpu not found, using dummy regulator
10621 00:27:22.714786 <4>[ 2.691736] cpu cpu2: supply cpu not found, using dummy regulator
10622 00:27:22.721248 <4>[ 2.698148] cpu cpu3: supply cpu not found, using dummy regulator
10623 00:27:22.727705 <4>[ 2.704551] cpu cpu4: supply cpu not found, using dummy regulator
10624 00:27:22.734158 <4>[ 2.710948] cpu cpu5: supply cpu not found, using dummy regulator
10625 00:27:22.741089 <4>[ 2.717344] cpu cpu6: supply cpu not found, using dummy regulator
10626 00:27:22.747815 <4>[ 2.723738] cpu cpu7: supply cpu not found, using dummy regulator
10627 00:27:22.767211 <6>[ 2.744391] cpu cpu0: EM: created perf domain
10628 00:27:22.770199 <6>[ 2.749318] cpu cpu4: EM: created perf domain
10629 00:27:22.777391 <6>[ 2.754948] sdhci: Secure Digital Host Controller Interface driver
10630 00:27:22.784049 <6>[ 2.761380] sdhci: Copyright(c) Pierre Ossman
10631 00:27:22.790685 <6>[ 2.766325] Synopsys Designware Multimedia Card Interface Driver
10632 00:27:22.797589 <6>[ 2.772959] sdhci-pltfm: SDHCI platform and OF driver helper
10633 00:27:22.800999 <6>[ 2.773011] mmc0: CQHCI version 5.10
10634 00:27:22.807237 <6>[ 2.782919] ledtrig-cpu: registered to indicate activity on CPUs
10635 00:27:22.814051 <6>[ 2.789851] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10636 00:27:22.820462 <6>[ 2.796900] usbcore: registered new interface driver usbhid
10637 00:27:22.824042 <6>[ 2.802721] usbhid: USB HID core driver
10638 00:27:22.830581 <6>[ 2.806929] spi_master spi0: will run message pump with realtime priority
10639 00:27:22.880226 <6>[ 2.851090] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10640 00:27:22.898672 <6>[ 2.866197] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10641 00:27:22.902303 <6>[ 2.873437] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15414
10642 00:27:22.909662 <6>[ 2.886941] cros-ec-spi spi0.0: Chrome EC device registered
10643 00:27:22.916567 <6>[ 2.892968] mmc0: Command Queue Engine enabled
10644 00:27:22.923122 <6>[ 2.897724] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10645 00:27:22.926061 <6>[ 2.905458] mmcblk0: mmc0:0001 DA4128 116 GiB
10646 00:27:22.937356 <6>[ 2.914563] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10647 00:27:22.944102 <6>[ 2.921718] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10648 00:27:22.954053 <6>[ 2.926312] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10649 00:27:22.957630 <6>[ 2.927627] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10650 00:27:22.964084 <6>[ 2.937616] NET: Registered PF_PACKET protocol family
10651 00:27:22.970620 <6>[ 2.942199] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10652 00:27:22.974136 <6>[ 2.946824] 9pnet: Installing 9P2000 support
10653 00:27:22.980559 <5>[ 2.957847] Key type dns_resolver registered
10654 00:27:22.984262 <6>[ 2.962907] registered taskstats version 1
10655 00:27:22.990701 <5>[ 2.967291] Loading compiled-in X.509 certificates
10656 00:27:23.021197 <4>[ 2.992206] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10657 00:27:23.031204 <4>[ 3.003143] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10658 00:27:23.047582 <6>[ 3.024696] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10659 00:27:23.054583 <6>[ 3.031642] xhci-mtk 11200000.usb: xHCI Host Controller
10660 00:27:23.060917 <6>[ 3.037168] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10661 00:27:23.070932 <6>[ 3.045033] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10662 00:27:23.077406 <6>[ 3.054468] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10663 00:27:23.084479 <6>[ 3.060644] xhci-mtk 11200000.usb: xHCI Host Controller
10664 00:27:23.090894 <6>[ 3.066136] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10665 00:27:23.097643 <6>[ 3.073805] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10666 00:27:23.104382 <6>[ 3.081620] hub 1-0:1.0: USB hub found
10667 00:27:23.107732 <6>[ 3.085648] hub 1-0:1.0: 1 port detected
10668 00:27:23.117489 <6>[ 3.089957] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10669 00:27:23.120913 <6>[ 3.098684] hub 2-0:1.0: USB hub found
10670 00:27:23.124142 <6>[ 3.102708] hub 2-0:1.0: 1 port detected
10671 00:27:23.132007 <6>[ 3.109674] mtk-msdc 11f70000.mmc: Got CD GPIO
10672 00:27:23.145623 <6>[ 3.119783] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10673 00:27:23.155543 <6>[ 3.128175] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10674 00:27:23.162217 <6>[ 3.136516] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10675 00:27:23.172005 <6>[ 3.144858] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10676 00:27:23.179054 <6>[ 3.153197] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10677 00:27:23.188392 <6>[ 3.161537] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10678 00:27:23.195426 <6>[ 3.169875] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10679 00:27:23.205241 <6>[ 3.178213] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10680 00:27:23.211687 <6>[ 3.186552] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10681 00:27:23.221541 <6>[ 3.194890] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10682 00:27:23.228187 <6>[ 3.203228] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10683 00:27:23.238094 <6>[ 3.211575] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10684 00:27:23.244823 <6>[ 3.219915] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10685 00:27:23.254935 <6>[ 3.228252] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10686 00:27:23.261323 <6>[ 3.236590] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10687 00:27:23.267723 <6>[ 3.245302] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10688 00:27:23.274804 <6>[ 3.252446] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10689 00:27:23.281997 <6>[ 3.259253] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10690 00:27:23.292060 <6>[ 3.266027] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10691 00:27:23.298495 <6>[ 3.272964] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10692 00:27:23.305282 <6>[ 3.279846] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10693 00:27:23.315401 <6>[ 3.288981] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10694 00:27:23.324967 <6>[ 3.298101] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10695 00:27:23.334630 <6>[ 3.307395] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10696 00:27:23.344794 <6>[ 3.316862] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10697 00:27:23.354608 <6>[ 3.326329] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10698 00:27:23.361073 <6>[ 3.335449] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10699 00:27:23.371293 <6>[ 3.344915] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10700 00:27:23.381041 <6>[ 3.354037] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10701 00:27:23.391134 <6>[ 3.363335] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10702 00:27:23.400623 <6>[ 3.373495] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10703 00:27:23.411105 <6>[ 3.385080] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10704 00:27:23.536163 <6>[ 3.510574] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10705 00:27:23.691151 <6>[ 3.668304] hub 1-1:1.0: USB hub found
10706 00:27:23.694329 <6>[ 3.672837] hub 1-1:1.0: 4 ports detected
10707 00:27:23.704891 <6>[ 3.682493] hub 1-1:1.0: USB hub found
10708 00:27:23.708400 <6>[ 3.686827] hub 1-1:1.0: 4 ports detected
10709 00:27:23.816720 <6>[ 3.790907] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10710 00:27:23.843379 <6>[ 3.820507] hub 2-1:1.0: USB hub found
10711 00:27:23.846464 <6>[ 3.825005] hub 2-1:1.0: 3 ports detected
10712 00:27:23.858086 <6>[ 3.835348] hub 2-1:1.0: USB hub found
10713 00:27:23.861051 <6>[ 3.839775] hub 2-1:1.0: 3 ports detected
10714 00:27:24.028551 <6>[ 4.002565] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10715 00:27:24.160883 <6>[ 4.138244] hub 1-1.4:1.0: USB hub found
10716 00:27:24.164317 <6>[ 4.142848] hub 1-1.4:1.0: 2 ports detected
10717 00:27:24.176851 <6>[ 4.154119] hub 1-1.4:1.0: USB hub found
10718 00:27:24.179823 <6>[ 4.158692] hub 1-1.4:1.0: 2 ports detected
10719 00:27:24.240684 <6>[ 4.214808] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10720 00:27:24.349201 <6>[ 4.323234] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10721 00:27:24.385220 <4>[ 4.359637] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10722 00:27:24.395097 <4>[ 4.368744] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10723 00:27:24.430549 <6>[ 4.408061] r8152 2-1.3:1.0 eth0: v1.12.13
10724 00:27:24.480097 <6>[ 4.454393] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10725 00:27:24.671927 <6>[ 4.646406] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10726 00:27:26.082050 <6>[ 6.059568] r8152 2-1.3:1.0 eth0: carrier on
10727 00:27:28.316539 <5>[ 6.086377] Sending DHCP requests .., OK
10728 00:27:28.323115 <6>[ 8.298735] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10729 00:27:28.326745 <6>[ 8.307019] IP-Config: Complete:
10730 00:27:28.339596 <6>[ 8.310516] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10731 00:27:28.346686 <6>[ 8.321224] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10732 00:27:28.353139 <6>[ 8.329842] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10733 00:27:28.359715 <6>[ 8.329852] nameserver0=192.168.201.1
10734 00:27:28.362659 <6>[ 8.342030] clk: Disabling unused clocks
10735 00:27:28.366236 <6>[ 8.347567] ALSA device list:
10736 00:27:28.372874 <6>[ 8.350827] No soundcards found.
10737 00:27:28.380175 <6>[ 8.358154] Freeing unused kernel memory: 8512K
10738 00:27:28.383635 <6>[ 8.363138] Run /init as init process
10739 00:27:28.413827 <6>[ 8.391779] NET: Registered PF_INET6 protocol family
10740 00:27:28.420642 <6>[ 8.398458] Segment Routing with IPv6
10741 00:27:28.423461 <6>[ 8.402431] In-situ OAM (IOAM) with IPv6
10742 00:27:28.463667 <30>[ 8.415144] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10743 00:27:28.470288 <30>[ 8.448177] systemd[1]: Detected architecture arm64.
10744 00:27:28.470363
10745 00:27:28.476719 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10746 00:27:28.476788
10747 00:27:28.488530 <30>[ 8.466569] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10748 00:27:28.606038 <30>[ 8.580806] systemd[1]: Queued start job for default target graphical.target.
10749 00:27:28.645231 <30>[ 8.620172] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10750 00:27:28.652276 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10751 00:27:28.672689 <30>[ 8.647458] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10752 00:27:28.682705 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10753 00:27:28.701640 <30>[ 8.676124] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10754 00:27:28.711347 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10755 00:27:28.729672 <30>[ 8.703985] systemd[1]: Created slice user.slice - User and Session Slice.
10756 00:27:28.736178 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10757 00:27:28.759584 <30>[ 8.730827] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10758 00:27:28.766332 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10759 00:27:28.786947 <30>[ 8.758536] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10760 00:27:28.793698 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10761 00:27:28.822416 <30>[ 8.787161] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10762 00:27:28.832658 <30>[ 8.807125] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10763 00:27:28.839092 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10764 00:27:28.855746 <30>[ 8.830593] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10765 00:27:28.862351 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10766 00:27:28.880086 <30>[ 8.854653] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10767 00:27:28.889841 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10768 00:27:28.904624 <30>[ 8.882690] systemd[1]: Reached target paths.target - Path Units.
10769 00:27:28.914507 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10770 00:27:28.932240 <30>[ 8.906939] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10771 00:27:28.938605 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10772 00:27:28.955374 <30>[ 8.930564] systemd[1]: Reached target slices.target - Slice Units.
10773 00:27:28.962376 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10774 00:27:28.976904 <30>[ 8.955099] systemd[1]: Reached target swap.target - Swaps.
10775 00:27:28.983294 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10776 00:27:29.004381 <30>[ 8.979078] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10777 00:27:29.014540 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10778 00:27:29.032306 <30>[ 9.007043] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10779 00:27:29.042315 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10780 00:27:29.061853 <30>[ 9.036504] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10781 00:27:29.071284 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10782 00:27:29.088234 <30>[ 9.063205] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10783 00:27:29.098254 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10784 00:27:29.116879 <30>[ 9.091158] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10785 00:27:29.123336 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10786 00:27:29.140573 <30>[ 9.115244] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10787 00:27:29.150121 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10788 00:27:29.169430 <30>[ 9.144003] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10789 00:27:29.179023 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10790 00:27:29.197032 <30>[ 9.171693] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10791 00:27:29.207066 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10792 00:27:29.248347 <30>[ 9.222781] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10793 00:27:29.254952 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10794 00:27:29.273646 <30>[ 9.248512] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10795 00:27:29.280456 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10796 00:27:29.302396 <30>[ 9.277184] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10797 00:27:29.309308 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10798 00:27:29.334975 <30>[ 9.303065] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10799 00:27:29.372368 <30>[ 9.347338] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10800 00:27:29.382119 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10801 00:27:29.404994 <30>[ 9.379937] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10802 00:27:29.411548 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10803 00:27:29.437115 <30>[ 9.411807] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10804 00:27:29.447108 Startin<6>[ 9.421199] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10805 00:27:29.453686 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10806 00:27:29.477397 <30>[ 9.452034] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10807 00:27:29.483738 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10808 00:27:29.508685 <30>[ 9.483618] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10809 00:27:29.518592 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10810 00:27:29.541463 <30>[ 9.516175] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10811 00:27:29.548032 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10812 00:27:29.612636 <30>[ 9.587239] systemd[1]: Starting systemd-journald.service - Journal Service...
10813 00:27:29.619087 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10814 00:27:29.639821 <30>[ 9.614312] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10815 00:27:29.646444 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10816 00:27:29.699829 <30>[ 9.671294] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10817 00:27:29.706342 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10818 00:27:29.729082 <30>[ 9.703764] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10819 00:27:29.738706 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10820 00:27:29.758735 <30>[ 9.733639] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10821 00:27:29.765686 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10822 00:27:29.787779 <30>[ 9.762302] systemd[1]: Started systemd-journald.service - Journal Service.
10823 00:27:29.794178 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10824 00:27:29.814204 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10825 00:27:29.832607 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10826 00:27:29.852523 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10827 00:27:29.869078 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10828 00:27:29.889209 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10829 00:27:29.913628 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10830 00:27:29.938401 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10831 00:27:29.962576 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10832 00:27:29.990387 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10833 00:27:30.013722 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10834 00:27:30.037265 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10835 00:27:30.062291 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10836 00:27:30.080368 See 'systemctl status systemd-remount-fs.service' for details.
10837 00:27:30.105339 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10838 00:27:30.130722 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10839 00:27:30.192516 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10840 00:27:30.221310 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10841 00:27:30.232389 <46>[ 10.207024] systemd-journald[195]: Received client request to flush runtime journal.
10842 00:27:30.249944 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10843 00:27:30.277979 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10844 00:27:30.305152 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10845 00:27:30.338274 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10846 00:27:30.361106 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10847 00:27:30.385007 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10848 00:27:30.405003 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10849 00:27:30.425265 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10850 00:27:30.480847 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10851 00:27:30.502569 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10852 00:27:30.519995 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10853 00:27:30.539668 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10854 00:27:30.596946 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10855 00:27:30.622308 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10856 00:27:30.646618 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10857 00:27:30.688601 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10858 00:27:30.716800 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10859 00:27:30.736343 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10860 00:27:30.791894 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10861 00:27:30.815707 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10862 00:27:30.860479 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10863 00:27:30.962554 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10864 00:27:30.981123 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10865 00:27:31.001303 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10866 00:27:31.021790 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10867 00:27:31.040603 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10868 00:27:31.059727 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10869 00:27:31.066247 <3>[ 11.041583] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10870 00:27:31.076990 <3>[ 11.052030] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10871 00:27:31.083339 <3>[ 11.060448] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10872 00:27:31.093638 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10873 00:27:31.103757 <6>[ 11.078847] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10874 00:27:31.110221 <6>[ 11.078941] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10875 00:27:31.120160 <6>[ 11.086855] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10876 00:27:31.127143 <6>[ 11.089163] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10877 00:27:31.133664 <3>[ 11.100169] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10878 00:27:31.143383 <6>[ 11.103281] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10879 00:27:31.153649 <3>[ 11.110455] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10880 00:27:31.160051 <6>[ 11.111428] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10881 00:27:31.166517 <6>[ 11.111436] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10882 00:27:31.176573 <4>[ 11.111665] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10883 00:27:31.186253 <6>[ 11.112350] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10884 00:27:31.192827 <6>[ 11.112354] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10885 00:27:31.199461 <6>[ 11.174534] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10886 00:27:31.209714 <3>[ 11.176107] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10887 00:27:31.216294 <6>[ 11.184035] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10888 00:27:31.226098 <3>[ 11.192123] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10889 00:27:31.229391 <6>[ 11.195269] remoteproc remoteproc0: scp is available
10890 00:27:31.235970 <6>[ 11.195403] remoteproc remoteproc0: powering up scp
10891 00:27:31.242527 <6>[ 11.195413] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10892 00:27:31.249227 <6>[ 11.195440] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10893 00:27:31.256137 <6>[ 11.199916] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10894 00:27:31.266198 <3>[ 11.208005] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10895 00:27:31.272678 <6>[ 11.213219] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10896 00:27:31.278999 <6>[ 11.227284] mc: Linux media interface: v0.10
10897 00:27:31.286036 <6>[ 11.245766] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10898 00:27:31.292777 <6>[ 11.269029] pci_bus 0000:00: root bus resource [bus 00-ff]
10899 00:27:31.299062 <6>[ 11.274785] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10900 00:27:31.305912 <3>[ 11.275792] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10901 00:27:31.315533 <6>[ 11.281924] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10902 00:27:31.325503 <4>[ 11.293992] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10903 00:27:31.328626 <6>[ 11.300070] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10904 00:27:31.338648 <6>[ 11.309003] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10905 00:27:31.345307 <4>[ 11.309055] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10906 00:27:31.351949 <6>[ 11.313534] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10907 00:27:31.358533 <6>[ 11.313624] pci 0000:00:00.0: supports D1 D2
10908 00:27:31.365481 <6>[ 11.323519] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10909 00:27:31.372083 <6>[ 11.323526] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10910 00:27:31.378594 <6>[ 11.328503] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10911 00:27:31.388496 <6>[ 11.329758] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10912 00:27:31.395062 <6>[ 11.339903] remoteproc remoteproc0: remote processor scp is now up
10913 00:27:31.401895 <6>[ 11.371732] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10914 00:27:31.408289 <3>[ 11.371826] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10915 00:27:31.418253 <3>[ 11.371852] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10916 00:27:31.424600 <3>[ 11.371864] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10917 00:27:31.432118 <4>[ 11.388703] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10918 00:27:31.438607 <4>[ 11.388703] Fallback method does not support PEC.
10919 00:27:31.445416 <6>[ 11.392025] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10920 00:27:31.455622 <3>[ 11.418994] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 00:27:31.462155 <6>[ 11.421811] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10922 00:27:31.472126 <3>[ 11.437326] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10923 00:27:31.478628 <6>[ 11.438052] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10924 00:27:31.485150 <3>[ 11.446053] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10925 00:27:31.491646 <6>[ 11.453714] pci 0000:01:00.0: supports D1 D2
10926 00:27:31.498124 <3>[ 11.461107] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10927 00:27:31.505050 <6>[ 11.469150] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10928 00:27:31.515022 <6>[ 11.470998] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10929 00:27:31.521677 <3>[ 11.473729] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10930 00:27:31.528068 <6>[ 11.482821] videodev: Linux video capture interface: v2.00
10931 00:27:31.538415 <3>[ 11.488726] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10932 00:27:31.544922 Startin<3>[ 11.521309] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10933 00:27:31.558446 g [0;1;39msystemd-networkd.…ice[0m - Network<3>[ 11.532767] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 00:27:31.568277 Configuration..<6>[ 11.536555] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10935 00:27:31.568358 .
10936 00:27:31.575055 <6>[ 11.551197] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10937 00:27:31.585218 <6>[ 11.559778] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10938 00:27:31.591698 <6>[ 11.567952] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10939 00:27:31.601660 <6>[ 11.567973] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10940 00:27:31.608019 <6>[ 11.583979] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10941 00:27:31.615078 <6>[ 11.591985] pci 0000:00:00.0: PCI bridge to [bus 01]
10942 00:27:31.621491 <6>[ 11.597203] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10943 00:27:31.631366 [[0;32m OK [<5>[ 11.599161] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10944 00:27:31.637876 <6>[ 11.605485] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10945 00:27:31.644246 0m] Reached targ<6>[ 11.621857] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10946 00:27:31.654345 et [0;1;39mbasi<6>[ 11.622617] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10947 00:27:31.661166 c.target[0m - B<6>[ 11.629046] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10948 00:27:31.664260 asic System.
10949 00:27:31.670881 <5>[ 11.629362] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10950 00:27:31.677711 <5>[ 11.629594] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10951 00:27:31.688414 <4>[ 11.629657] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10952 00:27:31.692526 <6>[ 11.629662] cfg80211: failed to load regulatory.db
10953 00:27:31.702049 <6>[ 11.639868] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10954 00:27:31.712599 <6>[ 11.672204] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10955 00:27:31.722524 Startin<6>[ 11.696265] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10956 00:27:31.735923 g [0;1;39mdbus.service[0m - D-<3>[ 11.708644] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10957 00:27:31.736022 Bus System Message Bus...
10958 00:27:31.749093 <3>[ 11.723676] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 00:27:31.758807 <3>[ 11.733269] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10960 00:27:31.799871 <6>[ 11.777989] Bluetooth: Core ver 2.22
10961 00:27:31.802780 <6>[ 11.782040] NET: Registered PF_BLUETOOTH protocol family
10962 00:27:31.810016 <6>[ 11.787638] Bluetooth: HCI device and connection manager initialized
10963 00:27:31.816434 <6>[ 11.794267] Bluetooth: HCI socket layer initialized
10964 00:27:31.822799 <6>[ 11.799411] Bluetooth: L2CAP socket layer initialized
10965 00:27:31.826372 <6>[ 11.804734] Bluetooth: SCO socket layer initialized
10966 00:27:31.839891 <6>[ 11.818482] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10967 00:27:31.859757 <6>[ 11.837895] usbcore: registered new interface driver btusb
10968 00:27:31.870119 <4>[ 11.838627] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10969 00:27:31.876870 <6>[ 11.840790] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10970 00:27:31.886873 <6>[ 11.847731] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10971 00:27:31.897851 <6>[ 11.849521] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10972 00:27:31.904358 <6>[ 11.849949] usbcore: registered new interface driver uvcvideo
10973 00:27:31.914457 <3>[ 11.851224] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 00:27:31.918140 <3>[ 11.854358] Bluetooth: hci0: Failed to load firmware file (-2)
10975 00:27:31.924866 <6>[ 11.861432] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10976 00:27:31.931433 <3>[ 11.868733] Bluetooth: hci0: Failed to set up firmware (-2)
10977 00:27:31.941515 <4>[ 11.868753] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10978 00:27:31.951456 <3>[ 11.879781] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 00:27:31.954532 <6>[ 11.894665] mt7921e 0000:01:00.0: ASIC revision: 79610010
10980 00:27:31.964356 <3>[ 11.900634] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10981 00:27:31.971106 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10982 00:27:31.998677 [[0;32m OK [0m] Started [0;<3>[ 11.972458] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 00:27:32.002134 1;39mdbus.service[0m - D-Bus System Message Bus.
10984 00:27:32.022990 <6>[ 11.998127] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10985 00:27:32.026512 <6>[ 11.998127]
10986 00:27:32.041636 <3>[ 12.016432] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10987 00:27:32.051741 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10988 00:27:32.092748 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10989 00:27:32.114662 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10990 00:27:32.132599 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10991 00:27:32.150034 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10992 00:27:32.173011 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10993 00:27:32.224514 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10994 00:27:32.249124 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10995 00:27:32.275053 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10996 00:27:32.300560 [[0;32m OK [0m] Finished [0<6>[ 12.274743] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10997 00:27:32.307182 ;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10998 00:27:32.373485 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10999 00:27:32.423633 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11000 00:27:32.443872 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11001 00:27:32.462793 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11002 00:27:32.482575 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11003 00:27:32.538641 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11004 00:27:32.563553 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11005 00:27:32.588891 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11006 00:27:32.631461 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11007 00:27:32.672931
11008 00:27:32.676051 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11009 00:27:32.676146
11010 00:27:32.679593 debian-bookworm-arm64 login: root (automatic login)
11011 00:27:32.679683
11012 00:27:32.703042 Linux debian-bookworm-arm64 6.1.94-cip23 #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024 aarch64
11013 00:27:32.703124
11014 00:27:32.709323 The programs included with the Debian GNU/Linux system are free software;
11015 00:27:32.715781 the exact distribution terms for each program are described in the
11016 00:27:32.718977 individual files in /usr/share/doc/*/copyright.
11017 00:27:32.719054
11018 00:27:32.726074 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11019 00:27:32.728940 permitted by applicable law.
11020 00:27:32.729313 Matched prompt #10: / #
11022 00:27:32.729497 Setting prompt string to ['/ #']
11023 00:27:32.729587 end: 2.2.5.1 login-action (duration 00:00:13) [common]
11025 00:27:32.729760 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11026 00:27:32.729842 start: 2.2.6 expect-shell-connection (timeout 00:03:10) [common]
11027 00:27:32.729908 Setting prompt string to ['/ #']
11028 00:27:32.729963 Forcing a shell prompt, looking for ['/ #']
11030 00:27:32.780162 / #
11031 00:27:32.780310 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11032 00:27:32.780398 Waiting using forced prompt support (timeout 00:02:30)
11033 00:27:32.785376
11034 00:27:32.785661 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11035 00:27:32.785781 start: 2.2.7 export-device-env (timeout 00:03:10) [common]
11036 00:27:32.785892 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11037 00:27:32.785994 end: 2.2 depthcharge-retry (duration 00:01:50) [common]
11038 00:27:32.786097 end: 2 depthcharge-action (duration 00:01:50) [common]
11039 00:27:32.786269 start: 3 lava-test-retry (timeout 00:07:47) [common]
11040 00:27:32.786393 start: 3.1 lava-test-shell (timeout 00:07:47) [common]
11041 00:27:32.786487 Using namespace: common
11043 00:27:32.886805 / # #
11044 00:27:32.887017 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11045 00:27:32.891781 #
11046 00:27:32.892082 Using /lava-14479209
11048 00:27:32.992429 / # export SHELL=/bin/sh
11049 00:27:32.997741 export SHELL=/bin/sh
11051 00:27:33.098285 / # . /lava-14479209/environment
11052 00:27:33.103210 . /lava-14479209/environment
11054 00:27:33.203672 / # /lava-14479209/bin/lava-test-runner /lava-14479209/0
11055 00:27:33.203881 Test shell timeout: 10s (minimum of the action and connection timeout)
11056 00:27:33.204310 /lava-14479209/bin/lava-test-runner /lava-14479209/0<6>[ 13.146542] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11057 00:27:33.208760
11058 00:27:33.252783 + export TESTRUN_ID=0_v4l2-compliance-uvc
11059 00:27:33.252862 + cd /lava-14479209/0/tests/0_v4l2-compliance-uvc
11060 00:27:33.252922 + cat uuid
11061 00:27:33.252978 + UUID=14479209_1.5.2.3.1
11062 00:27:33.253030 + set +x
11063 00:27:33.257217 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 14479209_1.5.2.3.1>
11064 00:27:33.257520 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 14479209_1.5.2.3.1
11065 00:27:33.257627 Starting test lava.0_v4l2-compliance-uvc (14479209_1.5.2.3.1)
11066 00:27:33.257758 Skipping test definition patterns.
11067 00:27:33.260289 + /usr/bin/v4l2-parser.sh -d uvcvideo
11068 00:27:33.266980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11069 00:27:33.267058 device: /dev/video1
11070 00:27:33.267285 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11072 00:27:39.710679 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11073 00:27:39.721777 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11074 00:27:39.729630
11075 00:27:39.748747 Compliance test for uvcvideo device /dev/video1:
11076 00:27:39.757222
11077 00:27:39.771824 Driver Info:
11078 00:27:39.782106 Driver name : uvcvideo
11079 00:27:39.796738 Card type : HD User Facing: HD User Facing
11080 00:27:39.807486 Bus info : usb-11200000.usb-1.4.1
11081 00:27:39.817040 Driver version : 6.1.94
11082 00:27:39.827646 Capabilities : 0x84a00001
11083 00:27:39.839718 Metadata Capture
11084 00:27:39.850530 Streaming
11085 00:27:39.864032 Extended Pix Format
11086 00:27:39.873917 Device Capabilities
11087 00:27:39.884773 Device Caps : 0x04200001
11088 00:27:39.899985 Streaming
11089 00:27:39.913359 Extended Pix Format
11090 00:27:39.924013 Media Driver Info:
11091 00:27:39.938319 Driver name : uvcvideo
11092 00:27:39.950983 Model : HD User Facing: HD User Facing
11093 00:27:39.958543 Serial : 200901010001
11094 00:27:39.972109 Bus info : usb-11200000.usb-1.4.1
11095 00:27:39.979721 Media version : 6.1.94
11096 00:27:39.998442 Hardware revision: 0x00009758 (38744)
11097 00:27:40.007726 Driver version : 6.1.94
11098 00:27:40.020566 Interface Info:
11099 00:27:40.036325 <LAVA_SIGNAL_TESTSET START Interface-Info>
11100 00:27:40.036446 ID : 0x03000002
11101 00:27:40.036734 Received signal: <TESTSET> START Interface-Info
11102 00:27:40.036860 Starting test_set Interface-Info
11103 00:27:40.047374 Type : V4L Video
11104 00:27:40.061611 Entity Info:
11105 00:27:40.068223 <LAVA_SIGNAL_TESTSET STOP>
11106 00:27:40.068512 Received signal: <TESTSET> STOP
11107 00:27:40.068630 Closing test_set Interface-Info
11108 00:27:40.077893 <LAVA_SIGNAL_TESTSET START Entity-Info>
11109 00:27:40.078009 ID : 0x00000001 (1)
11110 00:27:40.078284 Received signal: <TESTSET> START Entity-Info
11111 00:27:40.078410 Starting test_set Entity-Info
11112 00:27:40.090761 Name : HD User Facing: HD User Facing
11113 00:27:40.100580 Function : V4L2 I/O
11114 00:27:40.111605 Flags : default
11115 00:27:40.122381 Pad 0x01000007 : 0: Sink
11116 00:27:40.143569 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11117 00:27:40.143689
11118 00:27:40.155272 Required ioctls:
11119 00:27:40.162234 <LAVA_SIGNAL_TESTSET STOP>
11120 00:27:40.162526 Received signal: <TESTSET> STOP
11121 00:27:40.162640 Closing test_set Entity-Info
11122 00:27:40.172213 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11123 00:27:40.172499 Received signal: <TESTSET> START Required-ioctls
11124 00:27:40.172606 Starting test_set Required-ioctls
11125 00:27:40.175902 test MC information (see 'Media Driver Info' above): OK
11126 00:27:40.200907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11127 00:27:40.201163 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11129 00:27:40.203909 test VIDIOC_QUERYCAP: OK
11130 00:27:40.224131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11131 00:27:40.224416 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11133 00:27:40.227768 test invalid ioctls: OK
11134 00:27:40.248872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11135 00:27:40.248988
11136 00:27:40.249272 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11138 00:27:40.258118 Allow for multiple opens:
11139 00:27:40.266395 <LAVA_SIGNAL_TESTSET STOP>
11140 00:27:40.266678 Received signal: <TESTSET> STOP
11141 00:27:40.266796 Closing test_set Required-ioctls
11142 00:27:40.276016 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11143 00:27:40.276294 Received signal: <TESTSET> START Allow-for-multiple-opens
11144 00:27:40.276398 Starting test_set Allow-for-multiple-opens
11145 00:27:40.279089 test second /dev/video1 open: OK
11146 00:27:40.300515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video1-open RESULT=pass>
11147 00:27:40.300805 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video1-open RESULT=pass
11149 00:27:40.303553 test VIDIOC_QUERYCAP: OK
11150 00:27:40.324803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11151 00:27:40.325088 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11153 00:27:40.328223 test VIDIOC_G/S_PRIORITY: OK
11154 00:27:40.351668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11155 00:27:40.351967 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11157 00:27:40.355345 test for unlimited opens: OK
11158 00:27:40.377480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11159 00:27:40.377594
11160 00:27:40.377865 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11162 00:27:40.386484 Debug ioctls:
11163 00:27:40.393504 <LAVA_SIGNAL_TESTSET STOP>
11164 00:27:40.393802 Received signal: <TESTSET> STOP
11165 00:27:40.393904 Closing test_set Allow-for-multiple-opens
11166 00:27:40.402766 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11167 00:27:40.403015 Received signal: <TESTSET> START Debug-ioctls
11168 00:27:40.403078 Starting test_set Debug-ioctls
11169 00:27:40.406125 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11170 00:27:40.427386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11171 00:27:40.427645 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11173 00:27:40.433930 test VIDIOC_LOG_STATUS: OK (Not Supported)
11174 00:27:40.454715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11175 00:27:40.454794
11176 00:27:40.455019 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11178 00:27:40.465380 Input ioctls:
11179 00:27:40.474605 <LAVA_SIGNAL_TESTSET STOP>
11180 00:27:40.474847 Received signal: <TESTSET> STOP
11181 00:27:40.474909 Closing test_set Debug-ioctls
11182 00:27:40.485220 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11183 00:27:40.485464 Received signal: <TESTSET> START Input-ioctls
11184 00:27:40.485526 Starting test_set Input-ioctls
11185 00:27:40.488882 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11186 00:27:40.512917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11187 00:27:40.513184 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11189 00:27:40.516156 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11190 00:27:40.535544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11191 00:27:40.535831 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11193 00:27:40.541509 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11194 00:27:40.563487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11195 00:27:40.563732 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11197 00:27:40.569722 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11198 00:27:40.587811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11199 00:27:40.588056 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11201 00:27:40.591220 test VIDIOC_G/S/ENUMINPUT: OK
11202 00:27:40.613290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11203 00:27:40.613589 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11205 00:27:40.616800 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11206 00:27:40.637247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11207 00:27:40.637530 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11209 00:27:40.640949 Inputs: 1 Audio Inputs: 0 Tuners: 0
11210 00:27:40.653545
11211 00:27:40.669441 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11212 00:27:40.695940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11213 00:27:40.696188 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11215 00:27:40.702724 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11216 00:27:40.720219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11217 00:27:40.720513 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11219 00:27:40.726725 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11220 00:27:40.745516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11221 00:27:40.745801 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11223 00:27:40.752110 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11224 00:27:40.774100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11225 00:27:40.774369 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11227 00:27:40.780701 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11228 00:27:40.797497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11229 00:27:40.797576
11230 00:27:40.797801 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11232 00:27:40.818025 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11233 00:27:40.841647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11234 00:27:40.841895 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11236 00:27:40.848551 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11237 00:27:40.872872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11238 00:27:40.873150 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11240 00:27:40.876271 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11241 00:27:40.893696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11242 00:27:40.893943 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11244 00:27:40.900082 test VIDIOC_G/S_EDID: OK (Not Supported)
11245 00:27:40.921782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11246 00:27:40.921881
11247 00:27:40.922127 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11249 00:27:40.932170 Control ioctls (Input 0):
11250 00:27:40.938767 <LAVA_SIGNAL_TESTSET STOP>
11251 00:27:40.939032 Received signal: <TESTSET> STOP
11252 00:27:40.939123 Closing test_set Input-ioctls
11253 00:27:40.948542 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11254 00:27:40.948813 Received signal: <TESTSET> START Control-ioctls-Input-0
11255 00:27:40.948882 Starting test_set Control-ioctls-Input-0
11256 00:27:40.951549 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11257 00:27:40.977377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11258 00:27:40.977456 test VIDIOC_QUERYCTRL: OK
11259 00:27:40.977681 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11261 00:27:40.998943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11262 00:27:40.999185 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11264 00:27:41.002321 test VIDIOC_G/S_CTRL: OK
11265 00:27:41.024535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11266 00:27:41.024856 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11268 00:27:41.028207 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11269 00:27:41.049167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11270 00:27:41.049493 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11272 00:27:41.055628 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11273 00:27:41.082015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11274 00:27:41.082288 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11276 00:27:41.085113 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11277 00:27:41.104247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11278 00:27:41.104525 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11280 00:27:41.107750 Standard Controls: 16 Private Controls: 0
11281 00:27:41.115921
11282 00:27:41.126261 Format ioctls (Input 0):
11283 00:27:41.135683 <LAVA_SIGNAL_TESTSET STOP>
11284 00:27:41.135955 Received signal: <TESTSET> STOP
11285 00:27:41.136021 Closing test_set Control-ioctls-Input-0
11286 00:27:41.145862 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11287 00:27:41.146109 Received signal: <TESTSET> START Format-ioctls-Input-0
11288 00:27:41.146172 Starting test_set Format-ioctls-Input-0
11289 00:27:41.149380 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11290 00:27:41.173853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11291 00:27:41.174142 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11293 00:27:41.177358 test VIDIOC_G/S_PARM: OK
11294 00:27:41.195492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11295 00:27:41.195794 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11297 00:27:41.198599 test VIDIOC_G_FBUF: OK (Not Supported)
11298 00:27:41.224184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11299 00:27:41.224503 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11301 00:27:41.227743 test VIDIOC_G_FMT: OK
11302 00:27:41.250623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11303 00:27:41.250887 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11305 00:27:41.253590 test VIDIOC_TRY_FMT: OK
11306 00:27:41.275659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11307 00:27:41.275949 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11309 00:27:41.282231 warn: v4l2-test-formats.cpp(1046): Could not set fmt2
11310 00:27:41.287010 test VIDIOC_S_FMT: OK
11311 00:27:41.312564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11312 00:27:41.312867 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11314 00:27:41.315865 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11315 00:27:41.336024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11316 00:27:41.336328 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11318 00:27:41.338878 test Cropping: OK (Not Supported)
11319 00:27:41.361356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11320 00:27:41.361600 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11322 00:27:41.364303 test Composing: OK (Not Supported)
11323 00:27:41.386657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11324 00:27:41.386942 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11326 00:27:41.389505 test Scaling: OK (Not Supported)
11327 00:27:41.410852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11328 00:27:41.410928
11329 00:27:41.411152 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11331 00:27:41.422300 Codec ioctls (Input 0):
11332 00:27:41.430719 <LAVA_SIGNAL_TESTSET STOP>
11333 00:27:41.430956 Received signal: <TESTSET> STOP
11334 00:27:41.431037 Closing test_set Format-ioctls-Input-0
11335 00:27:41.440961 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11336 00:27:41.441253 Received signal: <TESTSET> START Codec-ioctls-Input-0
11337 00:27:41.441356 Starting test_set Codec-ioctls-Input-0
11338 00:27:41.444245 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11339 00:27:41.465833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11340 00:27:41.466121 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11342 00:27:41.472407 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11343 00:27:41.496026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11344 00:27:41.496312 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11346 00:27:41.502801 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11347 00:27:41.518670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11348 00:27:41.518745
11349 00:27:41.518971 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11351 00:27:41.530506 Buffer ioctls (Input 0):
11352 00:27:41.537932 <LAVA_SIGNAL_TESTSET STOP>
11353 00:27:41.538166 Received signal: <TESTSET> STOP
11354 00:27:41.538226 Closing test_set Codec-ioctls-Input-0
11355 00:27:41.548175 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11356 00:27:41.548491 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11357 00:27:41.548618 Starting test_set Buffer-ioctls-Input-0
11358 00:27:41.551047 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11359 00:27:41.576775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11360 00:27:41.577026 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11362 00:27:41.579596 test CREATE_BUFS maximum buffers: OK
11363 00:27:41.597515 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11365 00:27:41.600198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11366 00:27:41.600273 test VIDIOC_EXPBUF: OK
11367 00:27:41.621597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11368 00:27:41.621845 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11370 00:27:41.624557 test Requests: OK (Not Supported)
11371 00:27:41.645550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11372 00:27:41.645644
11373 00:27:41.645882 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11375 00:27:41.656752 Test input 0:
11376 00:27:41.665534
11377 00:27:41.684690 Streaming ioctls:
11378 00:27:41.694745 <LAVA_SIGNAL_TESTSET STOP>
11379 00:27:41.694988 Received signal: <TESTSET> STOP
11380 00:27:41.695054 Closing test_set Buffer-ioctls-Input-0
11381 00:27:41.704127 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11382 00:27:41.704376 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11383 00:27:41.704465 Starting test_set Streaming-ioctls_Test-input-0
11384 00:27:41.707599 test read/write: OK (Not Supported)
11385 00:27:41.728638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11386 00:27:41.728902 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11388 00:27:41.731984 test blocking wait: OK
11389 00:27:41.756833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11390 00:27:41.757076 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11392 00:27:41.763183 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11393 00:27:41.769956 test MMAP (no poll): FAIL
11394 00:27:41.795017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11395 00:27:41.795262 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11397 00:27:41.801474 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11398 00:27:41.805654 test MMAP (select): FAIL
11399 00:27:41.835791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11400 00:27:41.836034 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11402 00:27:41.842536 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11403 00:27:41.847772 test MMAP (epoll): FAIL
11404 00:27:41.872276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11405 00:27:41.872351
11406 00:27:41.872575 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11408 00:27:41.884565
11409 00:27:42.073815
11410 00:27:42.085342 test USERPTR (no poll): OK
11411 00:27:42.114544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11412 00:27:42.114705
11413 00:27:42.114979 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11415 00:27:42.127680
11416 00:27:42.306480
11417 00:27:42.315723 test USERPTR (select): OK
11418 00:27:42.343633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11419 00:27:42.343914 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11421 00:27:42.350543 test DMABUF: Cannot test, specify --expbuf-device
11422 00:27:42.354058
11423 00:27:42.371877 Total for uvcvideo device /dev/video1: 54, Succeeded: 51, Failed: 3, Warnings: 3
11424 00:27:42.375414 <LAVA_TEST_RUNNER EXIT>
11425 00:27:42.375661 ok: lava_test_shell seems to have completed
11426 00:27:42.375752 Marking unfinished test run as failed
11428 00:27:42.376807 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls-Input-0
Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video1-open:
result: pass
set: Allow-for-multiple-opens
11429 00:27:42.376941 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11430 00:27:42.377022 end: 3 lava-test-retry (duration 00:00:10) [common]
11431 00:27:42.377103 start: 4 finalize (timeout 00:07:38) [common]
11432 00:27:42.377198 start: 4.1 power-off (timeout 00:00:30) [common]
11433 00:27:42.377331 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
11434 00:27:42.577354 >> Command sent successfully.
11435 00:27:42.581630 Returned 0 in 0 seconds
11436 00:27:42.681945 end: 4.1 power-off (duration 00:00:00) [common]
11438 00:27:42.682229 start: 4.2 read-feedback (timeout 00:07:38) [common]
11439 00:27:42.682464 Listened to connection for namespace 'common' for up to 1s
11440 00:27:43.683425 Finalising connection for namespace 'common'
11441 00:27:43.683576 Disconnecting from shell: Finalise
11442 00:27:43.683649 / #
11443 00:27:43.783907 end: 4.2 read-feedback (duration 00:00:01) [common]
11444 00:27:43.784053 end: 4 finalize (duration 00:00:01) [common]
11445 00:27:43.784158 Cleaning after the job
11446 00:27:43.784262 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479209/tftp-deploy-tqaqu76_/ramdisk
11447 00:27:43.788444 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479209/tftp-deploy-tqaqu76_/kernel
11448 00:27:43.800485 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479209/tftp-deploy-tqaqu76_/dtb
11449 00:27:43.800670 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479209/tftp-deploy-tqaqu76_/modules
11450 00:27:43.805768 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14479209
11451 00:27:43.863019 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14479209
11452 00:27:43.863176 Job finished correctly