[Enter `^Ec?' for help] coreboot-v1.9308_26_0.0.22-6034-gd586c7b122 Wed Jul 15 17:51:44 UTC 2020 bootblock starting... Family_Model: 00670f00 PMxC0 STATUS: 0x80800 DoReset BIT11 DW I2C bus 1 at 0xfedc3000 (400 KHz) VBOOT: Loading verstage. CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset aab00 size d5e4 coreboot-v1.9308_26_0.0.22-6034-gd586c7b122 Wed Jul 15 17:51:44 UTC 2020 verstage starting... Probing TPM I2C: done! DID_VID 0x00281ae0 TPM ready after 0 ms cr50 TPM 2.0 (i2c 1:0x50 id 0x28) TPM: setup succeeded src/security/tpm/tss/tcg-2.0/tss.c:177 index 0x1007 return code 0 Chrome EC: UHEPI supported Phase 1 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area GBB found @ d80000 (458752 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0 Phase 2 Phase 3 FMAP: area GBB found @ d80000 (458752 bytes) VB2:vb2_report_dev_firmware() This is developer signed firmware FMAP: area VBLOCK_B found @ 23f000 (65536 bytes) FMAP: area VBLOCK_B found @ 23f000 (65536 bytes) VB2:vb2_verify_keyblock() Checking key block signature... FMAP: area VBLOCK_B found @ 23f000 (65536 bytes) FMAP: area VBLOCK_B found @ 23f000 (65536 bytes) VB2:vb2_verify_fw_preamble() Verifying preamble. Phase 4 FMAP: area FW_MAIN_B found @ 24f000 (2154432 bytes) VB2:vb2api_init_hash() HW crypto for hash_alg 2 not supported, using SW VB2:vb2_rsa_verify_digest() Digest check failed! VB2:vb2_fail() Need recovery, reason: 0x1b / 0x7 Saving nvdata Reboot requested (10020007) board_reset() called! coreboot-v1.9308_26_0.0.22-6034-gd586c7b122 Wed Jul 15 17:51:44 UTC 2020 bootblock starting... Family_Model: 00670f00 PMxC0 STATUS: 0x80800 DoReset BIT11 DW I2C bus 1 at 0xfedc3000 (400 KHz) VBOOT: Loading verstage. CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset aab00 size d5e4 coreboot-v1.9308_26_0.0.22-6034-gd586c7b122 Wed Jul 15 17:51:44 UTC 2020 verstage starting... Probing TPM I2C: done! DID_VID 0x00281ae0 TPM ready after 0 ms cr50 TPM 2.0 (i2c 1:0x50 id 0x28) TPM: setup succeeded src/security/tpm/tss/tcg-2.0/tss.c:177 index 0x1007 return code 0 Chrome EC: UHEPI supported Phase 1 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area GBB found @ d80000 (458752 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x0 Recovery requested (1009000e) Saving nvdata tlcl_extend: response is 0 tlcl_extend: response is 0 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size d544 coreboot-v1.9308_26_0.0.22-6034-gd586c7b122 Wed Jul 15 17:51:44 UTC 2020 romstage starting... CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'smu_fw' CBFS: Found @ offset 7bdc0 size 12262 PSP: Load blob type 19 from @ffe6bdf8... OK POST: 0x37 agesawrapper_amdinitreset() entry CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'AGESA_PRE_MEM' CBFS: Found @ offset df80 size 53bcc agesawrapper_amdinitreset() returned AGESA_SUCCESS POST: 0x38 agesawrapper_amdinitearly() entry Warning - AGESA callout: platform_PcieSlotResetControl not supported Warning - AGESA callout: platform_PcieSlotResetControl not supported agesawrapper_amdinitearly() returned AGESA_SUCCESS POST: 0x40 agesawrapper_amdinitpost() entry DRAM clear on reset: Keep variant_mainboard_read_spd SPD index 6 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'spd.bin' CBFS: Found @ offset 79d80 size 2000 AGESA set: umamode UMA_SPECIFIED : syslimit 0x12effffff, bottomio 0x00d00000 : uma size 16MB, uma start 0xcf000000 agesawrapper_amdinitpost() returned AGESA_SUCCESS POST: 0x41 Boot Count incremented to 29599 POST: 0x42 PSP: Notify that DRAM is available... OK POST: 0x43 CBMEM: IMD: root @ cdfff000 254 entries. IMD: root @ cdffec00 62 entries. External stage cache: IMD: root @ cefff000 254 entries. IMD: root @ ceffec00 62 entries. creating vboot_handoff structure Chrome EC: UHEPI supported Chrome EC: clear events_b mask to 0x0000000021004000 POST: 0x44 MTRR Range: Start=cd000000 End=ce000000 (Size 1000000) MTRR Range: Start=ff000000 End=0 (Size 1000000) MTRR Range: Start=ce800000 End=cf000000 (Size 800000) POST: 0x45 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/postcar' CBFS: Found @ offset a2c40 size 41f4 Decompressing stage fallback/postcar @ 0xcdfa1fc0 (33488 bytes) Loading module at cdfa2000 with entry cdfa2000. filesize: 0x3fd0 memsize: 0x8290 Processing 114 relocs. Offset value of 0xcbfa2000 coreboot-v1.9308_26_0.0.22-6034-gd586c7b122 Wed Jul 15 17:51:44 UTC 2020 postcar starting... CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 61bc0 size 18160 Decompressing stage fallback/ramstage @ 0xcde9efc0 (1055256 bytes) Loading module at cde9f000 with entry cde9f000. filesize: 0x378e0 memsize: 0x1019d8 Processing 3496 relocs. Offset value of 0xcdd9f000 coreboot-v1.9308_26_0.0.22-6034-gd586c7b122 Wed Jul 15 17:51:44 UTC 2020 ramstage starting... POST: 0x39 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RO_VPD found @ c00000 (16384 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ 465000 (8192 bytes) FMAP: area RW_VPD found @ 465000 (8192 bytes) POST: 0x80 Normal boot. POST: 0x46 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'smu_fw2' CBFS: Found @ offset 8e080 size 4cf2 PSP: Load blob type 1a from @ffe7e0b8... OK POST: 0x47 agesawrapper_amdinitenv() entry CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'AGESA_POST_MEM' CBFS: Found @ offset b8180 size 135b2 Decompressing stage AGESA_POST_MEM @ 0xcde6cfc0 (198492 bytes) Loading module at cde6d000 with entry cde6d000. filesize: 0x2f340 memsize: 0x2f480 Processing 1271 relocs. Offset value of 0xce06d000 AGESA: Saving stage to cache Fch OEM config in INIT ENV Done agesawrapper_amdinitenv() returned AGESA_SUCCESS POST: 0x70 BS: BS_PRE_DEVICE times (us): entry 124178 run 1060 exit 0 POST: 0x71 Board ID: 6 mainboard: EC init Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: UHEPI supported FMAP: area RW_ELOG found @ 45d000 (16384 bytes) Manufacturer: ef SF: Detected W25Q128FW with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x45d000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(17) added with size 13 at 2024-06-21 00:18:38 UTC POST: Unexpected post code in previous boot: 0x90 ELOG: Event(A3) added with size 11 at 2024-06-21 00:18:38 UTC ELOG: Event(91) added with size 10 at 2024-06-21 00:18:38 UTC Chrome EC: clear events_b mask to 0x0000000000000004 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006 Chrome EC: Set S3 LAZY WAKE mask to 0x0000000010001006 Chrome EC: Set WAKE mask to 0x0000000000000000 DW I2C bus 0 at 0xfedc2000 (400 KHz) DW I2C bus 2 at 0xfedc4000 (400 KHz) DW I2C bus 3 at 0xfedc5000 (400 KHz) ELOG: Event(9F) added with size 14 at 2024-06-21 00:18:38 UTC PM1_STS: PWRBTN BMSTATUS setup_bsp_ramtop, TOP MEM: msr.lo = 0xd0000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x2f000000, msr.hi = 0x00000001 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 106816 exit 0 POST: 0x72 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 00:50: enabled 1 I2C: 00:15: enabled 1 I2C: 00:2c: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 PCI: 00:00.0: enabled 1 PNP: 0c09.0: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 10: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 MMIO: fedc2000: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 MMIO: fedc3000: enabled 1 I2C: 00:50: enabled 1 MMIO: fedc4000: enabled 1 I2C: 00:15: enabled 1 I2C: 00:2c: enabled 1 MMIO: fedc5000: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 Mainboard Grunt Enable. Root Device scanning... root_dev_scan_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled MMIO: fedc2000 enabled MMIO: fedc3000 enabled MMIO: fedc4000 enabled MMIO: fedc5000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 sb_enable PCI: 00:00.0 [1022/1576] enabled sb_enable sb_enable PCI: 00:01.0 [1002/98e4] enabled sb_enable PCI: 00:01.1 [1002/15b3] enabled sb_enable PCI: 00:02.0 [1022/157b] enabled sb_enable PCI: Static device PCI: 00:02.1 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.2 subordinate bus PCI Express PCI: 00:02.2 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.3 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.4 subordinate bus PCI Express PCI: 00:02.4 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.5 not found, disabling it. PCI: 00:03.0 [1022/157b] enabled sb_enable PCI: 00:08.0 [1022/1578] enabled sb_enable PCI: 00:09.0 [1022/157d] enabled sb_enable PCI: Static device PCI: 00:09.2 not found, disabling it. sb_enable PCI: 00:10.0 [1022/0000] bus ops PCI: 00:10.0 [1022/7914] enabled sb_enable sb_enable PCI: 00:12.0 [1022/0000] bus ops PCI: 00:12.0 [1022/7908] enabled sb_enable PCI: 00:14.0 [1022/790b] bus ops PCI: 00:14.0 [1022/790b] enabled sb_enable PCI: 00:14.3 [1022/0000] bus ops PCI: 00:14.3 [1022/790e] enabled sb_enable PCI: 00:14.7 [1022/7906] enabled sb_enable PCI: 00:18.0 [1022/15b0] ops PCI: 00:18.0 [1022/15b0] enabled sb_enable PCI: 00:18.1 [1022/15b1] enabled sb_enable PCI: 00:18.2 [1022/15b2] enabled sb_enable PCI: 00:18.3 [1022/15b3] enabled sb_enable PCI: 00:18.4 [1022/15b4] enabled sb_enable PCI: 00:18.5 [1022/15b5] enabled POST: 0x25 PCI: 00:02.2 scanning... do_pci_scan_bridge for PCI: 00:02.2 PCI: pci_scan_bus for bus 01 POST: 0x24 PCI: 01:00.0 [168c/003e] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 scan_bus: scanning of bus PCI: 00:02.2 took 40750 usecs PCI: 00:02.4 scanning... do_pci_scan_bridge for PCI: 00:02.4 PCI: pci_scan_bus for bus 02 POST: 0x24 PCI: 02:00.0 [1217/0000] ops PCI: 02:00.0 [1217/8620] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 scan_bus: scanning of bus PCI: 00:02.4 took 40327 usecs PCI: 00:10.0 scanning... scan_usb_bus for PCI: 00:10.0 scan_usb_bus for PCI: 00:10.0 done scan_bus: scanning of bus PCI: 00:10.0 took 8113 usecs PCI: 00:12.0 scanning... scan_usb_bus for PCI: 00:12.0 scan_usb_bus for PCI: 00:12.0 done scan_bus: scanning of bus PCI: 00:12.0 took 8114 usecs PCI: 00:14.0 scanning... scan_generic_bus for PCI: 00:14.0 scan_generic_bus for PCI: 00:14.0 done scan_bus: scanning of bus PCI: 00:14.0 took 8803 usecs PCI: 00:14.3 scanning... scan_lpc_bus for PCI: 00:14.3 PNP: 0c09.0 enabled scan_lpc_bus for PCI: 00:14.3 done scan_bus: scanning of bus PCI: 00:14.3 took 9952 usecs POST: 0x55 scan_bus: scanning of bus DOMAIN: 0000 took 315053 usecs MMIO: fedc2000 scanning... scan_generic_bus for MMIO: fedc2000 bus: MMIO: fedc2000[0]->GENERIC: 0.0 enabled bus: MMIO: fedc2000[0]->I2C: 01:1a enabled bus: MMIO: fedc2000[0]->GENERIC: 0.1 enabled scan_generic_bus for MMIO: fedc2000 done scan_bus: scanning of bus MMIO: fedc2000 took 21198 usecs MMIO: fedc3000 scanning... scan_generic_bus for MMIO: fedc3000 bus: MMIO: fedc3000[0]->I2C: 02:50 enabled scan_generic_bus for MMIO: fedc3000 done scan_bus: scanning of bus MMIO: fedc3000 took 13152 usecs MMIO: fedc4000 scanning... scan_generic_bus for MMIO: fedc4000 bus: MMIO: fedc4000[0]->I2C: 03:15 enabled bus: MMIO: fedc4000[0]->I2C: 03:2c enabled scan_generic_bus for MMIO: fedc4000 done scan_bus: scanning of bus MMIO: fedc4000 took 16992 usecs MMIO: fedc5000 scanning... scan_generic_bus for MMIO: fedc5000 bus: MMIO: fedc5000[0]->I2C: 04:39 enabled bus: MMIO: fedc5000[0]->I2C: 04:10 enabled scan_generic_bus for MMIO: fedc5000 done scan_bus: scanning of bus MMIO: fedc5000 took 16987 usecs root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 429992 usecs done BS: BS_DEV_ENUMERATE times (us): entry 0 run 639132 exit 0 POST: 0x73 found VGA at PCI: 00:01.0 Setting up VGA for PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 done PCI: 00:02.4 read_resources bus 2 link: 0 PCI: 00:02.4 read_resources bus 2 link: 0 done PCI: 00:14.3 read_resources bus 0 link: 0 PCI: 00:14.3 read_resources bus 0 link: 0 done Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000. DOMAIN: 0000 read_resources bus 0 link: 0 done MMIO: fedc2000 read_resources bus 1 link: 0 MMIO: fedc2000 read_resources bus 1 link: 0 done MMIO: fedc3000 read_resources bus 2 link: 0 MMIO: fedc3000 read_resources bus 2 link: 0 done MMIO: fedc4000 read_resources bus 3 link: 0 MMIO: fedc4000 read_resources bus 3 link: 0 done MMIO: fedc5000 read_resources bus 4 link: 0 MMIO: fedc5000 read_resources bus 4 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffffffffffff flags 1201 index 10 PCI: 00:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffffffffffff flags 1201 index 18 PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 20 PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 24 PCI: 00:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 02:00.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 1201 index 10 PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 18 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 20 PCI: 00:08.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:10.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:12.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:14.7 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 I2C: 03:2c MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:01.0 20 * [0x0 - 0xff] io DOMAIN: 0000 io: base: 100 size: 100 align: 8 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0x1fffff] mem PCI: 00:02.2 mem: base: 200000 size: 200000 align: 21 gran: 20 limit: ffffffff done PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.0 10 * [0x0 - 0xfff] mem PCI: 02:00.0 14 * [0x1000 - 0x17ff] mem PCI: 00:02.4 mem: base: 1800 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.0 10 * [0x0 - 0x3ffffff] prefmem PCI: 00:01.0 18 * [0x4000000 - 0x47fffff] prefmem PCI: 00:02.2 20 * [0x4800000 - 0x49fffff] mem PCI: 00:02.4 20 * [0x4a00000 - 0x4afffff] mem PCI: 00:08.0 18 * [0x4b00000 - 0x4bfffff] mem PCI: 00:08.0 20 * [0x4c00000 - 0x4cfffff] mem PCI: 00:01.0 24 * [0x4d00000 - 0x4d3ffff] mem PCI: 00:01.0 30 * [0x4d40000 - 0x4d5ffff] mem PCI: 00:08.0 10 * [0x4d60000 - 0x4d7ffff] prefmem PCI: 00:01.1 10 * [0x4d80000 - 0x4d83fff] mem PCI: 00:08.0 24 * [0x4d84000 - 0x4d85fff] mem PCI: 00:10.0 10 * [0x4d86000 - 0x4d87fff] mem PCI: 00:08.0 1c * [0x4d88000 - 0x4d88fff] mem PCI: 00:12.0 10 * [0x4d89000 - 0x4d890ff] mem PCI: 00:14.7 10 * [0x4d8a000 - 0x4d8a0ff] mem DOMAIN: 0000 mem: base: 4d8a100 size: 4d8a100 align: 26 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed) constrain_resources: PCI: 00:14.3 10000100 base ff000000 limit ffffffff mem (fixed) constrain_resources: PCI: 00:14.3 02 base fec10000 limit fec103ff mem (fixed) constrain_resources: PCI: 00:14.3 03 base fec00000 limit fec00fff mem (fixed) constrain_resources: PCI: 00:18.0 c0010058 base f8000000 limit fbffffff mem (fixed) avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 base f0000000 limit f7ffffff Setting resources... DOMAIN: 0000 io: base:1000 size:100 align:8 gran:0 limit:ffff PCI: 00:01.0 20 * [0x1000 - 0x10ff] io DOMAIN: 0000 io: next_base: 1100 size: 100 align: 8 gran: 0 done PCI: 00:02.2 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.2 io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:02.4 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.4 io: next_base: ffff size: 0 align: 12 gran: 12 done DOMAIN: 0000 mem: base:f0000000 size:4d8a100 align:26 gran:0 limit:f7ffffff PCI: 00:01.0 10 * [0xf0000000 - 0xf3ffffff] prefmem PCI: 00:01.0 18 * [0xf4000000 - 0xf47fffff] prefmem PCI: 00:02.2 20 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.4 20 * [0xf4a00000 - 0xf4afffff] mem PCI: 00:08.0 18 * [0xf4b00000 - 0xf4bfffff] mem PCI: 00:08.0 20 * [0xf4c00000 - 0xf4cfffff] mem PCI: 00:01.0 24 * [0xf4d00000 - 0xf4d3ffff] mem PCI: 00:01.0 30 * [0xf4d40000 - 0xf4d5ffff] mem PCI: 00:08.0 10 * [0xf4d60000 - 0xf4d7ffff] prefmem PCI: 00:01.1 10 * [0xf4d80000 - 0xf4d83fff] mem PCI: 00:08.0 24 * [0xf4d84000 - 0xf4d85fff] mem PCI: 00:10.0 10 * [0xf4d86000 - 0xf4d87fff] mem PCI: 00:08.0 1c * [0xf4d88000 - 0xf4d88fff] mem PCI: 00:12.0 10 * [0xf4d89000 - 0xf4d890ff] mem PCI: 00:14.7 10 * [0xf4d8a000 - 0xf4d8a0ff] mem DOMAIN: 0000 mem: next_base: f4d8a100 size: 4d8a100 align: 26 gran: 0 done PCI: 00:02.2 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.2 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.2 mem: base:f4800000 size:200000 align:21 gran:20 limit:f49fffff PCI: 01:00.0 10 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.2 mem: next_base: f4a00000 size: 200000 align: 21 gran: 20 done PCI: 00:02.4 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.4 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.4 mem: base:f4a00000 size:100000 align:20 gran:20 limit:f4afffff PCI: 02:00.0 10 * [0xf4a00000 - 0xf4a00fff] mem PCI: 02:00.0 14 * [0xf4a01000 - 0xf4a017ff] mem PCI: 00:02.4 mem: next_base: f4a01800 size: 100000 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.0 10 <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x1a prefmem64 PCI: 00:01.0 18 <- [0x00f4000000 - 0x00f47fffff] size 0x00800000 gran 0x17 prefmem64 PCI: 00:01.0 20 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:01.0 24 <- [0x00f4d00000 - 0x00f4d3ffff] size 0x00040000 gran 0x12 mem PCI: 00:01.0 30 <- [0x00f4d40000 - 0x00f4d5ffff] size 0x00020000 gran 0x11 romem PCI: 00:01.1 10 <- [0x00f4d80000 - 0x00f4d83fff] size 0x00004000 gran 0x0e mem64 PCI: 00:02.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:02.2 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:02.2 20 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x14 bus 01 mem PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x15 mem64 PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 00:02.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:02.4 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:02.4 20 <- [0x00f4a00000 - 0x00f4afffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 02:00.0 10 <- [0x00f4a00000 - 0x00f4a00fff] size 0x00001000 gran 0x0c mem PCI: 02:00.0 14 <- [0x00f4a01000 - 0x00f4a017ff] size 0x00000800 gran 0x0b mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 00:08.0 10 <- [0x00f4d60000 - 0x00f4d7ffff] size 0x00020000 gran 0x11 prefmem64 PCI: 00:08.0 18 <- [0x00f4b00000 - 0x00f4bfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 1c <- [0x00f4d88000 - 0x00f4d88fff] size 0x00001000 gran 0x0c mem PCI: 00:08.0 20 <- [0x00f4c00000 - 0x00f4cfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 24 <- [0x00f4d84000 - 0x00f4d85fff] size 0x00002000 gran 0x0d mem PCI: 00:10.0 10 <- [0x00f4d86000 - 0x00f4d87fff] size 0x00002000 gran 0x0d mem64 PCI: 00:12.0 10 <- [0x00f4d89000 - 0x00f4d890ff] size 0x00000100 gran 0x08 mem PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.7 10 <- [0x00f4d8a000 - 0x00f4d8a0ff] size 0x00000100 gran 0x08 mem64 DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1000 size 100 align 8 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base f0000000 size 4d8a100 align 26 gran 0 limit f7ffffff flags 40040200 index 10000100 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11 DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12 DOMAIN: 0000 resource base 100000 size cdf00000 align 0 gran 0 limit 0 flags e0004200 index 13 DOMAIN: 0000 resource base ce000000 size 2000000 align 0 gran 0 limit 0 flags f0004200 index 14 DOMAIN: 0000 resource base 100000000 size 2f000000 align 0 gran 0 limit 0 flags e0004200 index 15 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base f0000000 size 4000000 align 26 gran 26 limit f3ffffff flags 60001201 index 10 PCI: 00:01.0 resource base f4000000 size 800000 align 23 gran 23 limit f47fffff flags 60001201 index 18 PCI: 00:01.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 20 PCI: 00:01.0 resource base f4d00000 size 40000 align 18 gran 18 limit f4d3ffff flags 60000200 index 24 PCI: 00:01.0 resource base f4d40000 size 20000 align 17 gran 17 limit f4d5ffff flags 60002200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base f4d80000 size 4000 align 14 gran 14 limit f4d83fff flags 60000201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.2 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.2 resource base f4800000 size 200000 align 21 gran 20 limit f49fffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base f4800000 size 200000 align 21 gran 21 limit f49fffff flags 60000201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.4 resource base f4a00000 size 100000 align 20 gran 20 limit f4afffff flags 60080202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base f4a00000 size 1000 align 12 gran 12 limit f4a00fff flags 60000200 index 10 PCI: 02:00.0 resource base f4a01000 size 800 align 12 gran 11 limit f4a017ff flags 60000200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base f4d60000 size 20000 align 17 gran 17 limit f4d7ffff flags 60001201 index 10 PCI: 00:08.0 resource base f4b00000 size 100000 align 20 gran 20 limit f4bfffff flags 60000200 index 18 PCI: 00:08.0 resource base f4d88000 size 1000 align 12 gran 12 limit f4d88fff flags 60000200 index 1c PCI: 00:08.0 resource base f4c00000 size 100000 align 20 gran 20 limit f4cfffff flags 60000200 index 20 PCI: 00:08.0 resource base f4d84000 size 2000 align 13 gran 13 limit f4d85fff flags 60000200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:10.0 resource base f4d86000 size 2000 align 13 gran 13 limit f4d87fff flags 60000201 index 10 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:12.0 resource base f4d89000 size 100 align 12 gran 8 limit f4d890ff flags 60000200 index 10 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:14.7 resource base f4d8a000 size 100 align 12 gran 8 limit f4d8a0ff flags 60000201 index 10 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 I2C: 03:2c MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 1566471 exit 0 PCI_INTR tables: Writing registers C00/C01 for PCI IRQ routing: PCI_INTR_INDEX name PIC mode APIC mode 0x00 INTA# 0x03 0x10 0x01 INTB# 0x04 0x11 0x02 INTC# 0x05 0x12 0x03 INTD# 0x07 0x13 0x04 INTE# 0x0B 0x14 0x05 INTF# 0x1F 0x1F 0x06 INTG# 0x1F 0x16 0x07 INTH# 0x1F 0x17 0x08 Misc 0xFA 0x00 0x09 Misc0 0xF1 0x00 0x0A Misc1 0x00 0x00 0x0B Misc2 0x00 0x00 0x0C Ser IRQ INTA 0x1F 0x1F 0x0D Ser IRQ INTB 0x1F 0x1F 0x0E Ser IRQ INTC 0x1F 0x1F 0x0F Ser IRQ INTD 0x1F 0x1F 0x10 SCI 0x09 0x09 0x11 SMBUS 0x1F 0x1F 0x12 ASF 0x1F 0x1F 0x13 HDA 0x03 0x10 0x14 FC 0x1F 0x1F 0x16 PerMon 0x1F 0x1F 0x17 SD 0x03 0x10 0x1A SDIOt 0x00 0x1F 0x30 EHCI 0x05 0x12 0x34 XHCI 0x04 0x12 0x41 SATA 0x07 0x13 0x62 GPIO 0x07 0x07 0x70 I2C0 0x03 0x03 0x71 I2C1 0x0F 0x0F 0x72 I2C2 0x06 0x06 0x73 I2C3 0x0E 0x0E 0x74 UART0 0x0A 0x0A 0x75 UART1 0x0B 0x0B PCI_CFG IRQ: Write PCI config space IRQ assignments PCI IRQ: Found device 0:01.00 using PIN A PCI Devfn (0x8) not found in pirq_data table PCI IRQ: Found device 0:01.01 using PIN B Found this device in pirq_data table entry 5 Orig INT_PIN : 2 (PIN B) PCI_INTR idx : 0x13 (HDA) INT_LINE : 0x3 (IRQ 3) PCI IRQ: Found device 0:02.02 using PIN A Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI IRQ: Found device 0:02.04 using PIN A Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 0:08.00 using PIN A PCI Devfn (0x40) not found in pirq_data table PCI IRQ: Found device 0:10.00 using PIN A Found this device in pirq_data table entry 10 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x34 (XHCI) INT_LINE : 0x4 (IRQ 4) PCI IRQ: Found device 0:12.00 using PIN A Found this device in pirq_data table entry 9 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x30 (EHCI) INT_LINE : 0x5 (IRQ 5) PCI IRQ: Found device 0:14.07 using PIN A Found this device in pirq_data table entry 6 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x17 (SD) INT_LINE : 0x3 (IRQ 3) PCI IRQ: Found device 2:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.04h Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 1:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.02h Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI_CFG IRQ: Finished writing PCI config space IRQ assignments POST: 0x74 Enabling resources... agesawrapper_amdinitmid() entry agesawrapper_amdinitmid() returned AGESA_SUCCESS PCI: 00:00.0 subsystem <- 1022/1576 PCI: 00:00.0 cmd <- 04 PCI: 00:01.0 subsystem <- 1002/98e4 PCI: 00:01.0 cmd <- 07 PCI: 00:01.1 subsystem <- 1002/15b3 PCI: 00:01.1 cmd <- 02 PCI: 00:02.0 subsystem <- 1022/157b PCI: 00:02.0 cmd <- 00 PCI: 00:02.2 bridge ctrl <- 0003 PCI: 00:02.2 cmd <- 06 PCI: 00:02.4 bridge ctrl <- 0003 PCI: 00:02.4 cmd <- 06 PCI: 00:03.0 cmd <- 00 PCI: 00:08.0 subsystem <- 1022/1578 PCI: 00:08.0 cmd <- 06 PCI: 00:09.0 subsystem <- 1022/157d PCI: 00:09.0 cmd <- 00 PCI: 00:10.0 subsystem <- 1022/7914 PCI: 00:10.0 cmd <- 02 PCI: 00:12.0 subsystem <- 1022/7908 PCI: 00:12.0 cmd <- 02 PCI: 00:14.0 subsystem <- 1022/790b PCI: 00:14.0 cmd <- 403 PCI: 00:14.3 subsystem <- 1022/790e PCI: 00:14.3 cmd <- 0f Southbridge LPC decode:PNP: 0c09.0, base=0x00000800, end=0x000009fe Covered by wideIO 0 PCI: 00:14.7 subsystem <- 1022/7906 PCI: 00:14.7 cmd <- 06 PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1022/15b1 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1022/15b2 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 subsystem <- 1022/15b3 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1022/15b4 PCI: 00:18.4 cmd <- 00 PCI: 00:18.5 subsystem <- 1022/15b5 PCI: 00:18.5 cmd <- 00 PCI: 01:00.0 cmd <- 02 PCI: 02:00.0 subsystem <- 1217/8620 PCI: 02:00.0 cmd <- 06 done. BS: BS_DEV_ENABLE times (us): entry 279588 run 130750 exit 0 POST: 0x75 Initializing devices... Root Device init ... Root Device init finished in 1983 usecs POST: 0x75 CPU_CLUSTER: 0 init ... MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000f0000000 size 0x20000000 type 0 0x00000000f0000000 - 0x00000000f4800000 size 0x04800000 type 1 0x00000000f4800000 - 0x0000000100000000 size 0x0b800000 type 0 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e call enable_fixed_mtrr() CPU physical address size: 48 bits MTRR: default type WB/UC MTRR counts: 8/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000f0000000 mask 0x0000fffffc000000 type 1 MTRR: 4 base 0x00000000f4000000 mask 0x0000ffffff800000 type 1 MTRR: 5 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Will perform SMM setup. CPU: AMD A4-9120C RADEON R4, 5 COMPUTE CORES 2C+3G . Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 1 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 1 apic_id 11. done. Waiting for 2nd SIPI to complete...done. Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call cdeb9967(00000000) Installing SMM handler to 0xce800000 Loading module at ce810000 with entry ce81142b. filesize: 0x6d18 memsize: 0xad98 Processing 473 relocs. Offset value of 0xce810000 Loading module at ce808000 with entry ce808000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0xce808000 SMM Module: placing jmp sequence at ce807e00 rel16 0x01fd SMM Module: stub loaded at ce808000. Will call ce81142b(00000000) New SMBASE 0xce800000 Relocation complete. New SMBASE 0xce7ffe00 Relocation complete. Initializing CPU #0 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x10 done. CPU #0 initialized Initializing CPU #1 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x11 done. CPU #1 initialized bsp_do_flight_plan done after 91 msecs. MTRR: TEMPORARY Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000ff000000 size 0x2f000000 type 0 0x00000000ff000000 - 0x0000000100000000 size 0x01000000 type 5 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: default type WB/UC MTRR counts: 7/5. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000ff000000 mask 0x0000ffffff000000 type 5 MTRR: 4 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 CPU_CLUSTER: 0 init finished in 346100 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:00.0 init ... PCI: 00:00.0 init finished in 2003 usecs POST: 0x75 POST: 0x75 PCI: 00:01.0 init ... CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'pci1002,98e4.rom' CBFS: Found @ offset 92dc0 size fe00 Mapping PCI device 100298e4 to 100298e0 In CBFS, ROM address for PCI: 00:01.0 = ffe82e08 PCI expansion ROM, signature 0xaa55, INIT size 0xfe00, data ptr 0x01c4 PCI ROM image, vendor ID 1002, device ID 98e0, PCI ROM image, Class Code 030000, Code Type 00 Copying VGA ROM Image from ffe82e08 to 0xc0000, 0xfe00 bytes Real mode stub @00000600: 867 bytes Calling Option ROM... ... Option ROM returned. VBE: Getting information about VESA mode 41d4 VBE: resolution: 1366x768@32 VBE: framebuffer: f0000000 VBE: Setting VESA mode 41d4 VGA Option ROM was run PCI: 00:01.0 init finished in 112175 usecs POST: 0x75 PCI: 00:01.1 init ... PCI: 00:01.1 init finished in 2003 usecs POST: 0x75 PCI: 00:02.0 init ... PCI: 00:02.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:03.0 init ... PCI: 00:03.0 init finished in 2003 usecs POST: 0x75 PCI: 00:08.0 init ... PCI: 00:08.0 init finished in 2002 usecs POST: 0x75 PCI: 00:09.0 init ... PCI: 00:09.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 PCI: 00:10.0 init ... PCI: 00:10.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 PCI: 00:12.0 init ... PCI: 00:12.0 init finished in 2002 usecs POST: 0x75 PCI: 00:14.0 init ... IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x04 IOAPIC: Dumping registers reg 0x0000: 0x04000000 reg 0x0001: 0x00178021 reg 0x0002: 0x04000000 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 PCI: 00:14.0 init finished in 133953 usecs POST: 0x75 PCI: 00:14.3 init ... RTC Init PCI: 00:14.3 init finished in 2962 usecs POST: 0x75 PCI: 00:14.7 init ... PCI: 00:14.7 init finished in 2002 usecs POST: 0x75 PCI: 00:18.0 init ... IOAPIC: Initializing IOAPIC at 0xfec20000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x05 IOAPIC: Dumping registers reg 0x0000: 0x05000000 reg 0x0001: 0x001f8021 reg 0x0002: 0x00000000 IOAPIC: 32 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 IOAPIC: reg 0x00000018 value 0x00000000 0x00010000 IOAPIC: reg 0x00000019 value 0x00000000 0x00010000 IOAPIC: reg 0x0000001a value 0x00000000 0x00010000 IOAPIC: reg 0x0000001b value 0x00000000 0x00010000 IOAPIC: reg 0x0000001c value 0x00000000 0x00010000 IOAPIC: reg 0x0000001d value 0x00000000 0x00010000 IOAPIC: reg 0x0000001e value 0x00000000 0x00010000 IOAPIC: reg 0x0000001f value 0x00000000 0x00010000 PCI: 00:18.0 init finished in 170064 usecs POST: 0x75 PCI: 00:18.1 init ... PCI: 00:18.1 init finished in 2002 usecs POST: 0x75 PCI: 00:18.2 init ... PCI: 00:18.2 init finished in 2002 usecs POST: 0x75 PCI: 00:18.3 init ... PCI: 00:18.3 init finished in 2002 usecs POST: 0x75 PCI: 00:18.4 init ... PCI: 00:18.4 init finished in 2002 usecs POST: 0x75 PCI: 00:18.5 init ... PCI: 00:18.5 init finished in 2002 usecs POST: 0x75 PCI: 01:00.0 init ... PCI: 01:00.0 init finished in 2002 usecs POST: 0x75 PCI: 02:00.0 init ... BayHub BH720: Power-saving enabled (link_ctrl=0x110103) PCI: 02:00.0 init finished in 7128 usecs POST: 0x75 PNP: 0c09.0 init ... Google Chrome EC: Hello got back 11223344 status (0) Google Chrome EC: version: ro: aleena_v2.1.108-9ca28c388 rw: aleena_v2.1.333-a6ea0bc7f running image: 1 Google Chrome EC uptime: 749225.412 seconds Google Chrome AP resets since EC boot: 570 Google Chrome most recent AP reset causes: 738273.643: 32774 shutdown: by console command 739181.480: 32774 shutdown: by console command 740027.266: 32774 shutdown: by console command 746126.897: 32774 shutdown: by console command Google Chrome EC reset flags at last EC boot: reset-pin PNP: 0c09.0 init finished in 51269 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 0 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 0 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 0 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 0 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 01:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 02:50: enabled 1 I2C: 03:15: enabled 1 I2C: 03:2c: enabled 1 I2C: 04:39: enabled 1 I2C: 04:10: enabled 1 PCI: 02:00.0: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 01:00.0: enabled 1 APIC: 11: enabled 1 BS: BS_DEV_INIT times (us): entry 0 run 1096289 exit 150 ELOG: Event(A1) added with size 10 at 2024-06-21 00:18:42 UTC elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b ELOG: Event(A0) added with size 9 at 2024-06-21 00:18:42 UTC elog_add_boot_reason: Logged dev mode boot POST: 0x76 Finalize devices... Devices finalized FMAP: area RW_NVRAM found @ 467000 (20480 bytes) agesawrapper_amdinitlate() entry DmiTable:cdfbd4a3, AcpiPstatein: cdfbc2b9, AcpiSrat:00000000,AcpiSlit:00000000, Mce:cdfbd327, Cmc:cdfbd3e9,Alib:cdfbe586, AcpiIvrs:00000000 in agesawrapper_amdinitlate agesawrapper_amdinitlate() returned AGESA_SUCCESS agesawrapper_amdinitrtb() entry agesawrapper_amdinitrtb() returned AGESA_SUCCESS BS: BS_POST_DEVICE times (us): entry 22110 run 4547 exit 37729 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) MRC: Checking cached data update for 'RW_MRC_CACHE'. MRC: cache data 'RW_MRC_CACHE' needs update. ELOG: Event(AA) added with size 11 at 2024-06-21 00:18:42 UTC POST: 0x77 BS: BS_OS_RESUME_CHECK times (us): entry 29692 run 1061 exit 0 POST: 0x79 POST: 0x9c CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/dsdt.aml' CBFS: Found @ offset a6e80 size 3c21 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/slic' CBFS: 'fallback/slic' not found. ACPI: Writing ACPI tables at cde2e000. ACPI: * FACS ACPI: * DSDT Ramoops buffer: 0x100000@0xcdd2e000. ACPI: * FADT pm_base: 0x0400 ACPI: added table 1/32, length now 40 ACPI: * SSDT ACPI \_PR report 2 core(s) dw_i2c: bad counts. hcnt = -1 lcnt = 9 dw_i2c: bad counts. hcnt = -1 lcnt = 16 dw_i2c: bad counts. hcnt = -2 lcnt = 19 dw_i2c: bad counts. hcnt = -3 lcnt = 21 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'pci1002,98e4.rom' CBFS: Found @ offset 92dc0 size fe00 Mapping PCI device 100298e4 to 100298e0 In CBFS, ROM address for PCI: 00:01.0 = ffe82e08 PCI expansion ROM, signature 0xaa55, INIT size 0xfe00, data ptr 0x01c4 PCI ROM image, vendor ID 1002, device ID 98e0, PCI ROM image, Class Code 030000, Code Type 00 \_SB.I2CA.ADAU: Analog Digital DMIC \_SB.I2CA.DLG7: Dialog Semiconductor DA7219 Audio Codec address 01ah irq 0 \_SB.I2CA.MAXM: Maxim Integrated 98357A Amplifier \_SB.I2CB.TPMI: I2C TPM at I2C: 02:50 \_SB.I2CC.D015: ELAN Touchpad at I2C: 03:15 \_SB.I2CC.H02C: Synaptics Touchpad at I2C: 03:2c \_SB.I2CD.D039: Raydium Touchscreen at I2C: 04:39 \_SB.I2CD.D010: ELAN Touchscreen at I2C: 04:10 ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * TCPA TCPA log created at cdd0e000 ACPI: added table 4/32, length now 52 ACPI: * MADT ACPI: added table 5/32, length now 56 current = cde33050 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'pci1002,98e4.rom' CBFS: Found @ offset 92dc0 size fe00 Mapping PCI device 100298e4 to 100298e0 In CBFS, ROM address for PCI: 00:01.0 = ffe82e08 PCI expansion ROM, signature 0xaa55, INIT size 0xfe00, data ptr 0x01c4 PCI ROM image, vendor ID 1002, device ID 98e0, PCI ROM image, Class Code 030000, Code Type 00 ACPI: * VFCT at cde33050 Copying initialized VBIOS image from 000c0000 ACPI: added table 6/32, length now 60 ACPI: * HPET ACPI: added table 7/32, length now 64 ACPI: added table 8/32, length now 68 ACPI: * IVRS at cde430d0 AGESA IVRS table NULL. Skipping. ACPI: * SRAT at cde430d0 AGESA SRAT table NULL. Skipping. ACPI: * SLIT at cde430d0 AGESA SLIT table NULL. Skipping. ACPI: * AGESA ALIB SSDT at cde430d0 ACPI: added table 9/32, length now 72 ACPI: * SSDT at cde47c30 ACPI: added table 10/32, length now 76 ACPI: * SSDT for PState at cde4806c ACPI: done. ACPI tables: 106608 bytes. smbios_write_tables: cdd0d000 Create SMBIOS type 17 SMBIOS tables: 543 bytes. Writing table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 11f9 Writing coreboot table at 0xcde52000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-00000000cdd0cfff: RAM 4. 00000000cdd0d000-00000000cde9efff: CONFIGURATION TABLES 5. 00000000cde9f000-00000000cdfa0fff: RAMSTAGE 6. 00000000cdfa1000-00000000cdffffff: CONFIGURATION TABLES 7. 00000000ce000000-00000000cfffffff: RESERVED 8. 00000000f8000000-00000000fbffffff: RESERVED 9. 0000000100000000-000000012effffff: RAM Passing 5 GPIOs to payload: NAME | PORT | POLARITY | VALUE write protect | undefined | high | low recovery | undefined | high | low lid | undefined | high | high power | undefined | high | low EC in RW | 0x0000000f | high | low Board ID: 6 SKU ID: 82 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) Wrote coreboot table at: cde52000, 0x550 bytes, checksum e05d coreboot table: 1384 bytes. IMD ROOT 0. cdfff000 00001000 IMD SMALL 1. cdffe000 00001000 CONSOLE 2. cdfde000 00020000 TIME STAMP 3. cdfdd000 00000910 VBOOT 4. cdfdc000 00000c0c ACPISCRATCH 5. cdfac000 00030000 ROMSTG STCK 6. cdfab000 00000400 AFTER CAR 7. cdfa1000 0000a000 RAMSTAGE 8. cde9e000 00103000 REFCODE 9. cde6c000 00032000 ACPI GNVS 10. cde6b000 00001000 SMM BACKUP 11. cde5b000 00010000 MRC DATA 12. cde5a000 00000e75 COREBOOT 13. cde52000 00008000 ACPI 14. cde2e000 00024000 RAMOOPS 15. cdd2e000 00100000 VGA ROM #0 16. cdd1e000 0000fe00 TCPA TCGLOG17. cdd0e000 00010000 SMBIOS 18. cdd0d000 00000800 IMD small region: IMD ROOT 0. cdffec00 00000400 VBOOT SEL 1. cdffebe0 00000008 EC HOSTEVENT 2. cdffebc0 00000008 ROMSTAGE 3. cdffeba0 00000004 VPD 4. cdffeb60 00000027 POWER STATE 5. cdffeb40 00000010 MEM INFO 6. cdffe9e0 00000149 COREBOOTFWD 7. cdffe9a0 00000028 BS: BS_WRITE_TABLES times (us): entry 2 run 442706 exit 1 POST: 0x7a CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/payload' CBFS: Found @ offset 1c2380 size 39f90 Loading segment from ROM address 0xfffb23b8 code (compression=0) New segment dstaddr 0x30104020 memsize 0x254890 srcaddr 0xfffb23f0 filesize 0x39f58 Loading segment from ROM address 0xfffb23d4 Entry Point 0x30104020 Loading Segment: addr: 0x0000000030104020 memsz: 0x0000000000254890 filesz: 0x0000000000039f58 lb: [0x00000000cde9f000, 0x00000000cdfa09d8) Post relocation: addr: 0x0000000030104020 memsz: 0x0000000000254890 filesz: 0x0000000000039f58 it's not compressed! [ 0x30104020, 3013df78, 0x303588b0) <- fffb23f0 Clearing Segment: addr: 0x000000003013df78 memsz: 0x000000000021a938 dest 30104020, end 303588b0, bouncebuffer ffffffff Loaded segments Lock SMM configuration POST: 0xfe BS: BS_PAYLOAD_LOAD times (us): entry 200 run 92806 exit 3312 PSP: Notify that POST is finishing... OK POST: 0x7b mp_park_aps done after 0 msecs. Jumping to boot code at 30104020(cde52000) POST: 0xf8 CPU0: stack: cdeda000 - cdedb000, lowest used address cdeda558, stack used: 2728 bytes Starting depthcharge on grunt... WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime! WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime! The GBB signature is at 0x30004020 and is: 24 47 42 42 [firmware-grunt-11031.B-collabora] Aug 12 2022 14:54:28 grunt: tftpboot 192.168.201.1 14479077/tftp-deploy-50hm_9yk/kernel/bzImage 14479077/tftp-deploy-50hm_9yk/kernel/cmdline 14479077/tftp-deploy-50hm_9yk/ramdisk/ramdisk.cpio.gz tftpboot 192.168.201.1 14479077/tftp-deploy-50hm_9yk/kernel/bzImage 19yk/kernel/cmdline 14479077/tftp-deploy-50hm_9yk/ramdisk/ramdisk.cpio.gz Waiting for link R8152: Initializing Version 6 (ocp_data = 5c30) R8152: Done initializing Adding net device done. MAC: 00:24:32:50:19:6c Sending DHCP discover... done. Waiting for reply... done. Sending DHCP request... done. Waiting for reply... done. My ip is 192.168.201.16 The DHCP server ip is 192.168.201.1 TFTP server IP predefined by user: 192.168.201.1 Bootfile predefined by user: 14479077/tftp-deploy-50hm_9yk/kernel/bzImage Sending tftp read request... done. Waiting for the transfer... 00000000 ################################################################ 00080000 ################################################################ 00100000 ################################################################ 00180000 ################################################################ 00200000 ################################################################ 00280000 ################################################################ 00300000 ################################################################ 00380000 ################################################################ 00400000 ################################################################ 00480000 ################################################################ 00500000 ################################################################ 00580000 ################################################################ 00600000 ################################################################ 00680000 ################################################################ 00700000 ################################################################ 00780000 ################################################################ 00800000 ################################################################ 00880000 ################################################################ 00900000 ################################################################ 00980000 ################################################################ 00a00000 ################################################################ 00a80000 ################################################################ 00b00000 #######################################R8152: Bulk read error 0xfffffffc Receive failed. R8152: Bulk read error 0xfffffffc Receive failed. R8152: Bulk read error 0xfffffffc R8152: Bul�