[Enter `^Ec?' for help] { coreboot-9211c87 Fri Feb 9 21:48:12 UTC 2018 bootblock starting... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception PLL at 00000000ff750000: fbdiv=169, refdiv=3, postdiv1=2, postdiv2=1, vco=1352000 khz, output=676000 khz PLL at 00000000ff760080: fbdiv=99, refdiv=1, postdiv1=4, postdiv2=1, vco=2376000 khz, output=594000 khz PLL at 00000000ff760060: fbdiv=100, refdiv=1, postdiv1=3, postdiv2=1, vco=2400000 khz, output=800000 khz Backing address range [0000000000000000:0000008000000000) with new page table @00000000ff8e6000 Mapping address range [0000000000000000:0000000100000000) as cacheable | read-write | secure | device Mapping address range [00000000ff8c0000:00000000ff8f0000) as cacheable | read-write | secure | normal Backing address range [00000000c0000000:0000000100000000) with new page table @00000000ff8e7000 Backing address range [00000000ff800000:00000000ffa00000) with new page table @00000000ff8e8000 ADC reading 582, ID 8 PLL at 00000000ff760000: fbdiv=63, refdiv=1, postdiv1=1, postdiv2=1, vco=1512000 khz, output=1512000 khz I2C bus 0: 398584Hz (divh = 44, divl = 60) SF: Detected GD25LQ64C/GD25LB64C with sector size 0x1000, total 0x800000 VBOOT: Loading verstage. CBFS @ 20000 size 2e0000 CBFS: 'Master Header Locator' located CBFS at [20000:300000) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset 19e00 size 852b coreboot-9211c87 Fri Feb 9 21:48:12 UTC 2018 verstage starting... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception SF: Detected GD25LQ64C/GD25LB64C with sector size 0x1000, total 0x800000 FMAP: Found "FMAP" version 1.0 at 300000. FMAP: base = 0 size = 800000 #areas = 22 FMAP: area RW_NVRAM found @ 5f0000 (65536 bytes) tpm_vendor_probe: ValidSts bit set(1) in TPM_ACCESS register after 1 ms I2C TPM 0:20 (chip type slb9645tt device-id 0x1A) TPM: Startup TPM: command 0x99 returned 0x0 TPM: Asserting physical presence TPM: command 0x4000000a returned 0x0 TPM: command 0x65 returned 0x0 TPM: flags disable=0, deactivated=0, nvlocked=1 setup_tpm():445: TPM: SetupTPM() succeeded TPM: tlcl_read(0x1007, 10) TPM: command 0xcf returned 0x0 out: cmd=0x87: 03 bf 87 00 00 00 04 00 08 20 8c ff in-header: 03 b1 00 00 04 00 00 00 in-data: 00 20 20 08 Phase 1 FMAP: area GBB found @ 301000 (913152 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0 Phase 2 Phase 3 FMAP: area GBB found @ 301000 (913152 bytes) VB2:vb2_report_dev_firmware() This is developer signed firmware FMAP: area VBLOCK_A found @ 400000 (8192 bytes) FMAP: area VBLOCK_A found @ 400000 (8192 bytes) VB2:vb2_verify_keyblock() Checking key block signature... FMAP: area VBLOCK_A found @ 400000 (8192 bytes) FMAP: area VBLOCK_A found @ 400000 (8192 bytes) VB2:vb2_verify_fw_preamble() Verifying preamble. Phase 4 FMAP: area FW_MAIN_A found @ 402000 (941824 bytes) VB2:vb2api_init_hash() HW crypto for hash_alg 2 not supported, using SW TPM: command 0x14 returned 0x0 TPM: command 0x14 returned 0x0 TPM: Set global lock TPM: tlcl_write(0x0, 0) TPM: command 0xcd returned 0x0 Slot A is selected CBFS: 'VBOOT' located CBFS at [402000:449900) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 0 size 6b60 coreboot-9211c87 Fri Feb 9 21:48:12 UTC 2018 romstage starting... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception ADC reading 583, ID 8 Starting DWC3 and TCPHY reset for USB OTG0 Starting DWC3 and TCPHY reset for USB OTG1 ADC reading 63, ID 0 SF: Detected GD25LQ64C/GD25LB64C with sector size 0x1000, total 0x800000 CBFS: 'VBOOT' located CBFS at [402000:449900) CBFS: Locating 'sdram-lpddr3-hynix-4GB-928' CBFS: Found @ offset 19d80 size 374 Starting SDRAM initialization... PLL at 00000000ff760040: fbdiv=116, refdiv=1, postdiv1=3, postdiv2=1, vco=2784000 khz, output=928000 khz Finish SDRAM initialization... Mapping address range [0000000000000000:00000000f8000000) as cacheable | read-write | non-secure | normal Mapping address range [0000000010000000:0000000010200000) as non-cacheable | read-write | non-secure | normal Backing address range [0000000000000000:0000000040000000) with new page table @00000000ff8e9000 CBMEM: IMD: root @ 00000000f7fff000 254 entries. IMD: root @ 00000000f7ffec00 62 entries. creating vboot_handoff structure Copying FW preamble CBFS: 'VBOOT' located CBFS at [402000:449900) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 6bc0 size a121 coreboot-9211c87 Fri Feb 9 21:48:12 UTC 2018 ramstage starting... SF: Detected GD25LQ64C/GD25LB64C with sector size 0x1000, total 0x800000 FMAP: Found "FMAP" version 1.0 at 300000. FMAP: base = 0 size = 800000 #areas = 22 FMAP: area RO_VPD found @ 3e0000 (131072 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ 4e8000 (32768 bytes) WARNING: RW_VPD is uninitialized or empty. ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception BS: BS_PRE_DEVICE times (us): entry 1 run 0 exit 1 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3 exit 0 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 Root Device scanning... root_dev_scan_bus for Root Device CPU_CLUSTER: 0 enabled root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 10790 usecs done BS: BS_DEV_ENUMERATE times (us): entry 1 run 32901 exit 1 Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 resource base 0 size f8000000 align 0 gran 0 limit 0 flags e0004200 index 0 Setting resources... Root Device assign_resources, bus 0 link: 0 CPU_CLUSTER: 0 missing set_resources Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 resource base 0 size f8000000 align 0 gran 0 limit 0 flags e0004200 index 0 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 1 run 69861 exit 1 Enabling resources... done. BS: BS_DEV_ENABLE times (us): entry 0 run 2622 exit 1 Initializing devices... Root Device init ... ADC reading 582, ID 8 DWC3 and TCPHY setup for USB OTG0 finished out: cmd=0x101: 03 f4 01 01 00 00 04 00 00 03 00 00 in-header: 03 f5 00 00 04 00 00 00 in-data: 01 00 01 02 out: cmd=0x101: 03 f6 01 01 00 00 04 00 00 01 00 00 in-header: 03 f5 00 00 04 00 00 00 in-data: 01 00 01 02 DWC3 and TCPHY setup for USB OTG1 finished out: cmd=0x101: 03 f3 01 01 00 00 04 00 01 03 00 00 in-header: 03 ef 00 00 04 00 00 00 in-data: 01 00 00 09 out: cmd=0x101: 03 f5 01 01 00 00 04 00 01 01 00 00 in-header: 03 ef 00 00 04 00 00 00 in-data: 01 00 00 09 Root Device init finished in 82392 usecs CPU_CLUSTER: 0 init ... Attempting to set up EDP display. Extracted contents: header: 00 ff ff ff ff ff ff 00 serial number: 4d 10 71 14 00 00 00 00 24 1a version: 01 04 basic params: a5 1a 11 78 06 chroma info: de 50 a3 54 4c 99 26 0f 50 54 established: 00 00 00 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 descriptor 1: bb 62 60 a0 90 40 2e 60 30 20 3a 00 03 ad 10 00 00 18 descriptor 2: 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 descriptor 3: 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 descriptor 4: 00 00 00 fc 00 4c 51 31 32 33 50 31 4a 58 33 31 0a 20 extensions: 00 checksum: c3 Manufacturer: SHP Model 1471 Serial Number 0 Made week 36 of 2016 EDID version: 1.4 Digital display 8 bits per primary color channel DisplayPort interface Maximum image size: 26 cm x 17 cm Gamma: 220% Check DPMS levels Supported color formats: RGB 4:4:4 Default (sRGB) color space is primary color space First detailed timing is preferred timing Established timings supported: Standard timings supported: Detailed timings Hex of detail: bb6260a090402e6030203a0003ad10000018 Detailed mode (IN HEX): Clock 252750 KHz, 103 mm x ad mm 0960 0990 09b0 0a00 hborder 0 0640 0643 064d 066e vborder 0 -hsync -vsync Did detailed timing Hex of detail: 000000100000000000000000000000000000 Dummy block Hex of detail: 000000100000000000000000000000000000 Dummy block Hex of detail: 000000fc004c5131323350314a5833310a20 Monitor name: LQ123P1JX31 Checksum Checksum: 0xc3 (valid) PLL at 00000000ff7600c0: fbdiv=337, refdiv=8, postdiv1=4, postdiv2=1, vco=1011000 khz, output=252750 khz clock recovery at voltage 0 pre-emphasis 0 requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 0 voltage 0.4V pre_emph 6dB requested signal parameters: lane 1 voltage 0.4V pre_emph 6dB requested signal parameters: lane 2 voltage 0.4V pre_emph 6dB requested signal parameters: lane 3 voltage 0.4V pre_emph 6dB using signal parameters: voltage 0.4V pre_emph 6dB requested signal parameters: lane 0 voltage 0.4V pre_emph 0dB requested signal parameters: lane 1 voltage 0.4V pre_emph 0dB requested signal parameters: lane 2 voltage 0.4V pre_emph 0dB requested signal parameters: lane 3 voltage 0.4V pre_emph 0dB using signal parameters: voltage 0.4V pre_emph 0dB channel eq at voltage 0 pre-emphasis 0 PLL at 00000000ff760020: fbdiv=75, refdiv=1, postdiv1=3, postdiv2=1, vco=1800000 khz, output=600000 khz CPU_CLUSTER: 0 init finished in 266238 usecs Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 BS: BS_DEV_INIT times (us): entry 1 run 367338 exit 1 FMAP: area RW_ELOG found @ 5d8000 (4096 bytes) ELOG: NV offset 0x5d8000 size 0x1000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 out: cmd=0x44: 03 b9 44 00 00 00 00 00 in-header: 03 41 00 00 04 00 00 00 in-data: ac 0d 99 66 ELOG: Event(17) added with size 13 out: cmd=0x87: 03 6b 87 00 00 00 04 00 07 00 00 00 in-header: 03 b1 00 00 04 00 00 00 in-data: 00 20 20 08 FMAP: area RW_NVRAM found @ 5f0000 (65536 bytes) out: cmd=0x44: 03 b9 44 00 00 00 00 00 in-header: 03 41 00 00 04 00 00 00 in-data: ac 0d 99 66 ELOG: Event(A0) added with size 9 elog_add_boot_reason: Logged dev mode boot Finalize devices... Devices finalized BS: BS_POST_DEVICE times (us): entry 58151 run 3490 exit 0 BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1 exit 1 Writing coreboot table at 0xf7eda000 0. 0000000000000000-00000000000fffff: RESERVED 1. 0000000000100000-00000000f7ed9fff: RAM 2. 00000000f7eda000-00000000f7ffffff: CONFIGURATION TABLES out: cmd=0x87: 03 74 87 00 00 00 04 00 be 34 0c 00 in-header: 03 b1 00 00 04 00 00 00 in-data: 00 20 20 08 Passing 6 GPIOs to payload: NAME | PORT | POLARITY | VALUE write protect | 0x00120001 | high | high recovery | undefined | high | high backlight | 0x00110001 | high | undefined EC in RW | 0x00080003 | high | undefined EC interrupt | 0x00010000 | low | undefined reset | 0x000b0000 | high | undefined ADC reading 62, ID 0 CBFS: 'VBOOT' located CBFS at [402000:449900) Wrote coreboot table at: 00000000f7eda000, 0x300 bytes, checksum fcd2 coreboot table: 792 bytes. IMD ROOT 0. 00000000f7fff000 00001000 IMD SMALL 1. 00000000f7ffe000 00001000 CONSOLE 2. 00000000f7fde000 00020000 TIME STAMP 3. 00000000f7fdd000 00000400 VBOOT 4. 00000000f7fdc000 00000c0c RAMOOPS 5. 00000000f7edc000 00100000 COREBOOT 6. 00000000f7eda000 00002000 IMD small region: IMD ROOT 0. 00000000f7ffec00 00000400 VBOOT SEL 1. 00000000f7ffebe0 00000008 BS: BS_WRITE_TABLES times (us): entry 1 run 113382 exit 0 CBFS: 'VBOOT' located CBFS at [402000:449900) CBFS: Locating 'fallback/payload' CBFS: Found @ offset 2ca40 size 1ae72 Loading segment from ROM address 0x0000000000100000 code (compression=1) New segment dstaddr 0x40104800 memsize 0x1194d80 srcaddr 0x100038 filesize 0x1ae3a Loading segment from ROM address 0x000000000010001c Entry Point 0x0000000040104800 Loading Segment: addr: 0x0000000040104800 memsz: 0x0000000001194d80 filesz: 0x000000000001ae3a lb: [0x0000000000300000, 0x000000000031fc48) Post relocation: addr: 0x0000000040104800 memsz: 0x0000000001194d80 filesz: 0x000000000001ae3a using LZMA [ 0x40104800, 40144ca8, 0x41299580) <- 00100038 Clearing Segment: addr: 0x0000000040144ca8 memsz: 0x00000000011548d8 dest 0000000040104800, end 0000000041299580, bouncebuffer ffffffffffffffff Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 1 run 126930 exit 0 Jumping to boot code at 0000000040104800(00000000f7eda000) CPU0: stack: 00000000ff8ec000 - 00000000ff8f0000, lowest used address 00000000ff8eefb0, stack used: 4176 bytes CBFS: 'VBOOT' located CBFS at [402000:449900) CBFS: Locating 'fallback/bl31' CBFS: Found @ offset 11180 size 8bce Loading segment from ROM address 0x0000000000100000 code (compression=1) New segment dstaddr 0x0 memsize 0x4f000 srcaddr 0x100070 filesize 0x804b Loading segment from ROM address 0x000000000010001c data (compression=1) New segment dstaddr 0xff8c0000 memsize 0x1000 srcaddr 0x1080bb filesize 0x152 Loading segment from ROM address 0x0000000000100038 code (compression=1) New segment dstaddr 0xff8c1000 memsize 0x4000 srcaddr 0x10820d filesize 0x9c1 Loading segment from ROM address 0x0000000000100054 Entry Point 0x0000000000001000 Loading Segment: addr: 0x0000000000000000 memsz: 0x000000000004f000 filesz: 0x000000000000804b lb: [0x0000000000300000, 0x000000000031fc48) Post relocation: addr: 0x0000000000000000 memsz: 0x000000000004f000 filesz: 0x000000000000804b using LZMA [ 0x00000000, 00035098, 0x0004f000) <- 00100070 Clearing Segment: addr: 0x0000000000035098 memsz: 0x0000000000019f68 dest 0000000000000000, end 000000000004f000, bouncebuffer ffffffffffffffff Loading Segment: addr: 0x00000000ff8c0000 memsz: 0x0000000000001000 filesz: 0x0000000000000152 lb: [0x0000000000300000, 0x000000000031fc48) Post relocation: addr: 0x00000000ff8c0000 memsz: 0x0000000000001000 filesz: 0x0000000000000152 using LZMA [ 0xff8c0000, ff8c1000, 0xff8c1000) <- 001080bb dest 00000000ff8c0000, end 00000000ff8c1000, bouncebuffer ffffffffffffffff Loading Segment: addr: 0x00000000ff8c1000 memsz: 0x0000000000004000 filesz: 0x00000000000009c1 lb: [0x0000000000300000, 0x000000000031fc48) Post relocation: addr: 0x00000000ff8c1000 memsz: 0x0000000000004000 filesz: 0x00000000000009c1 using LZMA [ 0xff8c1000, ff8c5000, 0xff8c5000) <- 0010820d dest 00000000ff8c1000, end 00000000ff8c5000, bouncebuffer ffffffffffffffff Loaded segments NOTICE: BL31: v1.2(debug):0f202a3 NOTICE: BL31: Built : Fri Feb 9 21:48:12 UTC 2018 INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3 INFO: plat_rockchip_pmu_init(1336): pd status 3e INFO: BL31: Initializing runtime services INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x40104800 INFO: SPSR = 0x8 Starting depthcharge on kevin... [firmware-gru-8785.B-collabora] Feb 1 2021 12:35:55 kevin: tftpboot 192.168.201.1 14879067/tftp-deploy-n6nz0dfb/kernel/image.itb 14879067/tftp-deploy-n6nz0dfb/kernel/cmdline Waiting for link Initializing XHCI USB controller at 0xfe900000. Initializing XHCI USB controller at 0xfe800000.