Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 13:14:29.807387 lava-dispatcher, installed at version: 2024.05
2 13:14:29.807605 start: 0 validate
3 13:14:29.807774 Start time: 2024-07-18 13:14:29.807752+00:00 (UTC)
4 13:14:29.807947 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:14:29.808132 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 13:14:30.070186 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:14:30.070920 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 13:14:30.334359 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:14:30.335184 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:14:30.600063 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:14:30.600676 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
12 13:14:31.119254 validate duration: 1.31
14 13:14:31.120380 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:14:31.120859 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:14:31.121288 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:14:31.121958 Not decompressing ramdisk as can be used compressed.
18 13:14:31.122392 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 13:14:31.122690 saving as /var/lib/lava/dispatcher/tmp/14879028/tftp-deploy-kxj7s8bm/ramdisk/rootfs.cpio.gz
20 13:14:31.123006 total size: 47897469 (45 MB)
21 13:14:31.127391 progress 0 % (0 MB)
22 13:14:31.164724 progress 5 % (2 MB)
23 13:14:31.180353 progress 10 % (4 MB)
24 13:14:31.192378 progress 15 % (6 MB)
25 13:14:31.203909 progress 20 % (9 MB)
26 13:14:31.215736 progress 25 % (11 MB)
27 13:14:31.227276 progress 30 % (13 MB)
28 13:14:31.238843 progress 35 % (16 MB)
29 13:14:31.250456 progress 40 % (18 MB)
30 13:14:31.262026 progress 45 % (20 MB)
31 13:14:31.273439 progress 50 % (22 MB)
32 13:14:31.284816 progress 55 % (25 MB)
33 13:14:31.296545 progress 60 % (27 MB)
34 13:14:31.307989 progress 65 % (29 MB)
35 13:14:31.319506 progress 70 % (32 MB)
36 13:14:31.331063 progress 75 % (34 MB)
37 13:14:31.342574 progress 80 % (36 MB)
38 13:14:31.354148 progress 85 % (38 MB)
39 13:14:31.365572 progress 90 % (41 MB)
40 13:14:31.377064 progress 95 % (43 MB)
41 13:14:31.388289 progress 100 % (45 MB)
42 13:14:31.388490 45 MB downloaded in 0.27 s (172.05 MB/s)
43 13:14:31.388644 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:14:31.388863 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:14:31.388942 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:14:31.389017 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:14:31.389196 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
49 13:14:31.389259 saving as /var/lib/lava/dispatcher/tmp/14879028/tftp-deploy-kxj7s8bm/kernel/Image
50 13:14:31.389312 total size: 54813184 (52 MB)
51 13:14:31.389366 No compression specified
52 13:14:31.390391 progress 0 % (0 MB)
53 13:14:31.403373 progress 5 % (2 MB)
54 13:14:31.416534 progress 10 % (5 MB)
55 13:14:31.429468 progress 15 % (7 MB)
56 13:14:31.442590 progress 20 % (10 MB)
57 13:14:31.455941 progress 25 % (13 MB)
58 13:14:31.468854 progress 30 % (15 MB)
59 13:14:31.481930 progress 35 % (18 MB)
60 13:14:31.495181 progress 40 % (20 MB)
61 13:14:31.508208 progress 45 % (23 MB)
62 13:14:31.521326 progress 50 % (26 MB)
63 13:14:31.534564 progress 55 % (28 MB)
64 13:14:31.547564 progress 60 % (31 MB)
65 13:14:31.560860 progress 65 % (34 MB)
66 13:14:31.574029 progress 70 % (36 MB)
67 13:14:31.587098 progress 75 % (39 MB)
68 13:14:31.600303 progress 80 % (41 MB)
69 13:14:31.613308 progress 85 % (44 MB)
70 13:14:31.626365 progress 90 % (47 MB)
71 13:14:31.639540 progress 95 % (49 MB)
72 13:14:31.652324 progress 100 % (52 MB)
73 13:14:31.652531 52 MB downloaded in 0.26 s (198.60 MB/s)
74 13:14:31.652677 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:14:31.652888 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:14:31.652969 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:14:31.653045 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:14:31.653214 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:14:31.653281 saving as /var/lib/lava/dispatcher/tmp/14879028/tftp-deploy-kxj7s8bm/dtb/mt8192-asurada-spherion-r0.dtb
81 13:14:31.653334 total size: 47258 (0 MB)
82 13:14:31.653387 No compression specified
83 13:14:31.654373 progress 69 % (0 MB)
84 13:14:31.654624 progress 100 % (0 MB)
85 13:14:31.654766 0 MB downloaded in 0.00 s (31.53 MB/s)
86 13:14:31.654877 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:14:31.655076 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:14:31.655151 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:14:31.655231 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:14:31.655338 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
92 13:14:31.655400 saving as /var/lib/lava/dispatcher/tmp/14879028/tftp-deploy-kxj7s8bm/modules/modules.tar
93 13:14:31.655452 total size: 8611320 (8 MB)
94 13:14:31.655505 Using unxz to decompress xz
95 13:14:31.656798 progress 0 % (0 MB)
96 13:14:31.676823 progress 5 % (0 MB)
97 13:14:31.700499 progress 10 % (0 MB)
98 13:14:31.724317 progress 15 % (1 MB)
99 13:14:31.749610 progress 20 % (1 MB)
100 13:14:31.773987 progress 25 % (2 MB)
101 13:14:31.797962 progress 30 % (2 MB)
102 13:14:31.821068 progress 35 % (2 MB)
103 13:14:31.846832 progress 40 % (3 MB)
104 13:14:31.870926 progress 45 % (3 MB)
105 13:14:31.894193 progress 50 % (4 MB)
106 13:14:31.917862 progress 55 % (4 MB)
107 13:14:31.940958 progress 60 % (4 MB)
108 13:14:31.963396 progress 65 % (5 MB)
109 13:14:31.987879 progress 70 % (5 MB)
110 13:14:32.013856 progress 75 % (6 MB)
111 13:14:32.040056 progress 80 % (6 MB)
112 13:14:32.062864 progress 85 % (7 MB)
113 13:14:32.085250 progress 90 % (7 MB)
114 13:14:32.107621 progress 95 % (7 MB)
115 13:14:32.129716 progress 100 % (8 MB)
116 13:14:32.135029 8 MB downloaded in 0.48 s (17.12 MB/s)
117 13:14:32.135173 end: 1.4.1 http-download (duration 00:00:00) [common]
119 13:14:32.135382 end: 1.4 download-retry (duration 00:00:00) [common]
120 13:14:32.135462 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:14:32.135540 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:14:32.135611 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:14:32.135681 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:14:32.135849 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo
125 13:14:32.135966 makedir: /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin
126 13:14:32.136056 makedir: /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/tests
127 13:14:32.136144 makedir: /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/results
128 13:14:32.136230 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-add-keys
129 13:14:32.136356 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-add-sources
130 13:14:32.136472 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-background-process-start
131 13:14:32.136591 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-background-process-stop
132 13:14:32.136715 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-common-functions
133 13:14:32.136829 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-echo-ipv4
134 13:14:32.136947 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-install-packages
135 13:14:32.137063 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-installed-packages
136 13:14:32.137183 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-os-build
137 13:14:32.137294 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-probe-channel
138 13:14:32.137405 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-probe-ip
139 13:14:32.137515 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-target-ip
140 13:14:32.137623 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-target-mac
141 13:14:32.137731 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-target-storage
142 13:14:32.137844 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-test-case
143 13:14:32.137955 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-test-event
144 13:14:32.138066 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-test-feedback
145 13:14:32.138176 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-test-raise
146 13:14:32.138285 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-test-reference
147 13:14:32.138395 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-test-runner
148 13:14:32.138506 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-test-set
149 13:14:32.138616 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-test-shell
150 13:14:32.138727 Updating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-install-packages (oe)
151 13:14:32.138864 Updating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/bin/lava-installed-packages (oe)
152 13:14:32.138980 Creating /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/environment
153 13:14:32.139074 LAVA metadata
154 13:14:32.139138 - LAVA_JOB_ID=14879028
155 13:14:32.139194 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:14:32.139280 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:14:32.139337 skipped lava-vland-overlay
158 13:14:32.139402 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:14:32.139471 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:14:32.139523 skipped lava-multinode-overlay
161 13:14:32.139586 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:14:32.139654 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:14:32.139717 Loading test definitions
164 13:14:32.139792 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:14:32.139849 Using /lava-14879028 at stage 0
166 13:14:32.140136 uuid=14879028_1.5.2.3.1 testdef=None
167 13:14:32.140216 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:14:32.140292 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:14:32.140718 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:14:32.140912 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:14:32.141494 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:14:32.141701 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:14:32.142252 runner path: /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/0/tests/0_igt-gpu-panfrost test_uuid 14879028_1.5.2.3.1
176 13:14:32.142425 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:14:32.142615 Creating lava-test-runner.conf files
179 13:14:32.142671 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14879028/lava-overlay-77f81feo/lava-14879028/0 for stage 0
180 13:14:32.142750 - 0_igt-gpu-panfrost
181 13:14:32.142838 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:14:32.142913 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:14:32.148922 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:14:32.149015 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:14:32.149093 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:14:32.149214 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:14:32.149289 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:14:33.672499 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 13:14:33.672628 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 13:14:33.672701 extracting modules file /var/lib/lava/dispatcher/tmp/14879028/tftp-deploy-kxj7s8bm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14879028/extract-overlay-ramdisk-l0jofb20/ramdisk
191 13:14:33.938415 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:14:33.938555 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 13:14:33.938658 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14879028/compress-overlay-5_rvf9xb/overlay-1.5.2.4.tar.gz to ramdisk
194 13:14:33.938746 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14879028/compress-overlay-5_rvf9xb/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14879028/extract-overlay-ramdisk-l0jofb20/ramdisk
195 13:14:33.946167 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:14:33.946260 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 13:14:33.946343 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:14:33.946420 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 13:14:33.946483 Building ramdisk /var/lib/lava/dispatcher/tmp/14879028/extract-overlay-ramdisk-l0jofb20/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14879028/extract-overlay-ramdisk-l0jofb20/ramdisk
200 13:14:34.927764 >> 465549 blocks
201 13:14:41.400057 rename /var/lib/lava/dispatcher/tmp/14879028/extract-overlay-ramdisk-l0jofb20/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14879028/tftp-deploy-kxj7s8bm/ramdisk/ramdisk.cpio.gz
202 13:14:41.400210 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 13:14:41.400298 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 13:14:41.400375 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 13:14:41.400452 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14879028/tftp-deploy-kxj7s8bm/kernel/Image']
206 13:14:54.792238 Returned 0 in 13 seconds
207 13:14:54.792407 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14879028/tftp-deploy-kxj7s8bm/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14879028/tftp-deploy-kxj7s8bm/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14879028/tftp-deploy-kxj7s8bm/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14879028/tftp-deploy-kxj7s8bm/kernel/image.itb
208 13:14:55.707159 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:14:55.707291 output: Created: Thu Jul 18 14:14:55 2024
210 13:14:55.707351 output: Image 0 (kernel-1)
211 13:14:55.707405 output: Description:
212 13:14:55.707455 output: Created: Thu Jul 18 14:14:55 2024
213 13:14:55.707505 output: Type: Kernel Image
214 13:14:55.707553 output: Compression: lzma compressed
215 13:14:55.707604 output: Data Size: 13114469 Bytes = 12807.10 KiB = 12.51 MiB
216 13:14:55.707652 output: Architecture: AArch64
217 13:14:55.707699 output: OS: Linux
218 13:14:55.707747 output: Load Address: 0x00000000
219 13:14:55.707794 output: Entry Point: 0x00000000
220 13:14:55.707865 output: Hash algo: crc32
221 13:14:55.707914 output: Hash value: a47b020b
222 13:14:55.707962 output: Image 1 (fdt-1)
223 13:14:55.708008 output: Description: mt8192-asurada-spherion-r0
224 13:14:55.708055 output: Created: Thu Jul 18 14:14:55 2024
225 13:14:55.708116 output: Type: Flat Device Tree
226 13:14:55.708162 output: Compression: uncompressed
227 13:14:55.708209 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 13:14:55.708257 output: Architecture: AArch64
229 13:14:55.708303 output: Hash algo: crc32
230 13:14:55.708349 output: Hash value: 0f8e4d2e
231 13:14:55.708395 output: Image 2 (ramdisk-1)
232 13:14:55.708441 output: Description: unavailable
233 13:14:55.708487 output: Created: Thu Jul 18 14:14:55 2024
234 13:14:55.708533 output: Type: RAMDisk Image
235 13:14:55.708579 output: Compression: uncompressed
236 13:14:55.708625 output: Data Size: 61002098 Bytes = 59572.36 KiB = 58.18 MiB
237 13:14:55.708671 output: Architecture: AArch64
238 13:14:55.708717 output: OS: Linux
239 13:14:55.708762 output: Load Address: unavailable
240 13:14:55.708808 output: Entry Point: unavailable
241 13:14:55.708869 output: Hash algo: crc32
242 13:14:55.708928 output: Hash value: 77608053
243 13:14:55.708973 output: Default Configuration: 'conf-1'
244 13:14:55.709020 output: Configuration 0 (conf-1)
245 13:14:55.709066 output: Description: mt8192-asurada-spherion-r0
246 13:14:55.709112 output: Kernel: kernel-1
247 13:14:55.709187 output: Init Ramdisk: ramdisk-1
248 13:14:55.709248 output: FDT: fdt-1
249 13:14:55.709294 output: Loadables: kernel-1
250 13:14:55.709340 output:
251 13:14:55.709438 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 13:14:55.709510 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 13:14:55.709581 end: 1.5 prepare-tftp-overlay (duration 00:00:24) [common]
254 13:14:55.709653 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
255 13:14:55.709708 No LXC device requested
256 13:14:55.709776 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:14:55.709844 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
258 13:14:55.709910 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:14:55.709964 Checking files for TFTP limit of 4294967296 bytes.
260 13:14:55.710323 end: 1 tftp-deploy (duration 00:00:25) [common]
261 13:14:55.710410 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:14:55.710487 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:14:55.710574 substitutions:
264 13:14:55.710633 - {DTB}: 14879028/tftp-deploy-kxj7s8bm/dtb/mt8192-asurada-spherion-r0.dtb
265 13:14:55.710688 - {INITRD}: 14879028/tftp-deploy-kxj7s8bm/ramdisk/ramdisk.cpio.gz
266 13:14:55.710739 - {KERNEL}: 14879028/tftp-deploy-kxj7s8bm/kernel/Image
267 13:14:55.710788 - {LAVA_MAC}: None
268 13:14:55.710838 - {PRESEED_CONFIG}: None
269 13:14:55.710887 - {PRESEED_LOCAL}: None
270 13:14:55.710935 - {RAMDISK}: 14879028/tftp-deploy-kxj7s8bm/ramdisk/ramdisk.cpio.gz
271 13:14:55.710987 - {ROOT_PART}: None
272 13:14:55.711036 - {ROOT}: None
273 13:14:55.711084 - {SERVER_IP}: 192.168.201.1
274 13:14:55.711131 - {TEE}: None
275 13:14:55.711179 Parsed boot commands:
276 13:14:55.711225 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:14:55.711368 Parsed boot commands: tftpboot 192.168.201.1 14879028/tftp-deploy-kxj7s8bm/kernel/image.itb 14879028/tftp-deploy-kxj7s8bm/kernel/cmdline
278 13:14:55.711446 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:14:55.711519 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:14:55.711589 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:14:55.711659 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:14:55.711712 Not connected, no need to disconnect.
283 13:14:55.711776 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:14:55.711843 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:14:55.711896 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 13:14:55.714717 Setting prompt string to ['lava-test: # ']
287 13:14:55.715011 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:14:55.715102 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:14:55.715246 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:14:55.715372 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:14:55.715586 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
292 13:15:04.876147 >> Command sent successfully.
293 13:15:04.890157 Returned 0 in 9 seconds
294 13:15:04.890749 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 13:15:04.891762 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 13:15:04.892212 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 13:15:04.892547 Setting prompt string to 'Starting depthcharge on Spherion...'
299 13:15:04.892829 Changing prompt to 'Starting depthcharge on Spherion...'
300 13:15:04.893112 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 13:15:04.894967 [Enter `^Ec?' for help]
302 13:15:06.495818
303 13:15:06.496286
304 13:15:06.496587 F0: 102B 0000
305 13:15:06.496874
306 13:15:06.497181 F3: 1001 0000 [0200]
307 13:15:06.499074
308 13:15:06.499520 F3: 1001 0000
309 13:15:06.499821
310 13:15:06.500094 F7: 102D 0000
311 13:15:06.500357
312 13:15:06.502763 F1: 0000 0000
313 13:15:06.503140
314 13:15:06.503427 V0: 0000 0000 [0001]
315 13:15:06.503731
316 13:15:06.504104 00: 0007 8000
317 13:15:06.504535
318 13:15:06.506853 01: 0000 0000
319 13:15:06.507242
320 13:15:06.507530 BP: 0C00 0209 [0000]
321 13:15:06.507801
322 13:15:06.510985 G0: 1182 0000
323 13:15:06.511364
324 13:15:06.511652 EC: 0000 0021 [4000]
325 13:15:06.511925
326 13:15:06.514682 S7: 0000 0000 [0000]
327 13:15:06.515082
328 13:15:06.515375 CC: 0000 0000 [0001]
329 13:15:06.515671
330 13:15:06.518085 T0: 0000 0040 [010F]
331 13:15:06.518466
332 13:15:06.518758 Jump to BL
333 13:15:06.519059
334 13:15:06.543353
335 13:15:06.543765
336 13:15:06.549363 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 13:15:06.553405 ARM64: Exception handlers installed.
338 13:15:06.556221 ARM64: Testing exception
339 13:15:06.559565 ARM64: Done test exception
340 13:15:06.566314 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 13:15:06.576762 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 13:15:06.582620 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 13:15:06.592986 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 13:15:06.599587 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 13:15:06.610055 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 13:15:06.620354 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 13:15:06.626642 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 13:15:06.645088 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 13:15:06.648960 WDT: Last reset was cold boot
350 13:15:06.652293 SPI1(PAD0) initialized at 2873684 Hz
351 13:15:06.654971 SPI5(PAD0) initialized at 992727 Hz
352 13:15:06.658771 VBOOT: Loading verstage.
353 13:15:06.665565 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 13:15:06.668322 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 13:15:06.672120 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 13:15:06.675079 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 13:15:06.682953 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 13:15:06.689133 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 13:15:06.699920 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 13:15:06.700013
361 13:15:06.700075
362 13:15:06.710495 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 13:15:06.713522 ARM64: Exception handlers installed.
364 13:15:06.716929 ARM64: Testing exception
365 13:15:06.717011 ARM64: Done test exception
366 13:15:06.723778 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 13:15:06.727252 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 13:15:06.741447 Probing TPM: . done!
369 13:15:06.741574 TPM ready after 0 ms
370 13:15:06.748006 Connected to device vid:did:rid of 1ae0:0028:00
371 13:15:06.754332 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 13:15:06.794128 Initialized TPM device CR50 revision 0
373 13:15:06.805613 tlcl_send_startup: Startup return code is 0
374 13:15:06.805717 TPM: setup succeeded
375 13:15:06.816934 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 13:15:06.826430 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 13:15:06.836115 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 13:15:06.845038 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 13:15:06.848508 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 13:15:06.851705 in-header: 03 07 00 00 08 00 00 00
381 13:15:06.855282 in-data: aa e4 47 04 13 02 00 00
382 13:15:06.858648 Chrome EC: UHEPI supported
383 13:15:06.865769 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 13:15:06.869180 in-header: 03 a9 00 00 08 00 00 00
385 13:15:06.872568 in-data: 84 60 60 08 00 00 00 00
386 13:15:06.872956 Phase 1
387 13:15:06.875412 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 13:15:06.882174 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 13:15:06.888813 VB2:vb2_check_recovery() Recovery was requested manually
390 13:15:06.892061 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 13:15:06.895295 Recovery requested (1009000e)
392 13:15:06.905069 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 13:15:06.909178 tlcl_extend: response is 0
394 13:15:06.918674 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 13:15:06.922716 tlcl_extend: response is 0
396 13:15:06.928968 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 13:15:06.949987 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 13:15:06.956572 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 13:15:06.956960
400 13:15:06.957299
401 13:15:06.966439 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 13:15:06.969888 ARM64: Exception handlers installed.
403 13:15:06.973192 ARM64: Testing exception
404 13:15:06.973612 ARM64: Done test exception
405 13:15:06.995710 pmic_efuse_setting: Set efuses in 11 msecs
406 13:15:06.998873 pmwrap_interface_init: Select PMIF_VLD_RDY
407 13:15:07.005694 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 13:15:07.009714 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 13:15:07.012771 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 13:15:07.020141 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 13:15:07.023297 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 13:15:07.029688 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 13:15:07.033047 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 13:15:07.036562 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 13:15:07.043089 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 13:15:07.046726 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 13:15:07.053525 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 13:15:07.057058 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 13:15:07.060493 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 13:15:07.067047 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 13:15:07.073564 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 13:15:07.080307 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 13:15:07.083714 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 13:15:07.090466 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 13:15:07.097283 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 13:15:07.100298 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 13:15:07.107035 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 13:15:07.114329 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 13:15:07.117444 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 13:15:07.124201 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 13:15:07.127578 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 13:15:07.134253 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 13:15:07.140727 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 13:15:07.143951 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 13:15:07.150901 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 13:15:07.154079 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 13:15:07.157991 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 13:15:07.164562 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 13:15:07.167721 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 13:15:07.174457 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 13:15:07.177461 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 13:15:07.184565 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 13:15:07.190886 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 13:15:07.194839 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 13:15:07.197891 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 13:15:07.201097 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 13:15:07.208852 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 13:15:07.211596 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 13:15:07.215102 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 13:15:07.221683 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 13:15:07.225262 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 13:15:07.228522 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 13:15:07.231614 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 13:15:07.238582 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 13:15:07.242004 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 13:15:07.245042 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 13:15:07.248483 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 13:15:07.258372 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 13:15:07.265161 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 13:15:07.272172 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 13:15:07.279041 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 13:15:07.288866 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 13:15:07.292024 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 13:15:07.295600 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:15:07.301961 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 13:15:07.309012 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 13:15:07.312486 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 13:15:07.319612 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 13:15:07.323222 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 13:15:07.332487 [RTC]rtc_get_frequency_meter,154: input=15, output=791
471 13:15:07.342230 [RTC]rtc_get_frequency_meter,154: input=23, output=979
472 13:15:07.351317 [RTC]rtc_get_frequency_meter,154: input=19, output=884
473 13:15:07.361163 [RTC]rtc_get_frequency_meter,154: input=17, output=838
474 13:15:07.370516 [RTC]rtc_get_frequency_meter,154: input=16, output=815
475 13:15:07.380030 [RTC]rtc_get_frequency_meter,154: input=15, output=789
476 13:15:07.389363 [RTC]rtc_get_frequency_meter,154: input=16, output=814
477 13:15:07.392933 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 13:15:07.400214 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 13:15:07.403153 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 13:15:07.406771 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 13:15:07.413519 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 13:15:07.416822 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 13:15:07.419942 ADC[4]: Raw value=900959 ID=7
484 13:15:07.420334 ADC[3]: Raw value=213336 ID=1
485 13:15:07.423460 RAM Code: 0x71
486 13:15:07.426772 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 13:15:07.433784 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 13:15:07.440201 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 13:15:07.447130 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 13:15:07.450460 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 13:15:07.453758 in-header: 03 07 00 00 08 00 00 00
492 13:15:07.457493 in-data: aa e4 47 04 13 02 00 00
493 13:15:07.460457 Chrome EC: UHEPI supported
494 13:15:07.467450 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 13:15:07.470709 in-header: 03 a9 00 00 08 00 00 00
496 13:15:07.473989 in-data: 84 60 60 08 00 00 00 00
497 13:15:07.477683 MRC: failed to locate region type 0.
498 13:15:07.484652 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 13:15:07.485060 DRAM-K: Running full calibration
500 13:15:07.490940 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 13:15:07.494489 header.status = 0x0
502 13:15:07.498058 header.version = 0x6 (expected: 0x6)
503 13:15:07.500905 header.size = 0xd00 (expected: 0xd00)
504 13:15:07.501328 header.flags = 0x0
505 13:15:07.507584 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 13:15:07.526262 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 13:15:07.532899 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 13:15:07.536295 dram_init: ddr_geometry: 2
509 13:15:07.536695 [EMI] MDL number = 2
510 13:15:07.539540 [EMI] Get MDL freq = 0
511 13:15:07.543181 dram_init: ddr_type: 0
512 13:15:07.543572 is_discrete_lpddr4: 1
513 13:15:07.546555 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 13:15:07.546944
515 13:15:07.547245
516 13:15:07.549946 [Bian_co] ETT version 0.0.0.1
517 13:15:07.556532 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 13:15:07.556924
519 13:15:07.559764 dramc_set_vcore_voltage set vcore to 650000
520 13:15:07.560157 Read voltage for 800, 4
521 13:15:07.563181 Vio18 = 0
522 13:15:07.563574 Vcore = 650000
523 13:15:07.563873 Vdram = 0
524 13:15:07.566513 Vddq = 0
525 13:15:07.566901 Vmddr = 0
526 13:15:07.569945 dram_init: config_dvfs: 1
527 13:15:07.573110 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 13:15:07.580681 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 13:15:07.583188 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 13:15:07.586393 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 13:15:07.590062 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 13:15:07.593286 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 13:15:07.596836 MEM_TYPE=3, freq_sel=18
534 13:15:07.599958 sv_algorithm_assistance_LP4_1600
535 13:15:07.603794 ============ PULL DRAM RESETB DOWN ============
536 13:15:07.606475 ========== PULL DRAM RESETB DOWN end =========
537 13:15:07.613448 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 13:15:07.616641 ===================================
539 13:15:07.617036 LPDDR4 DRAM CONFIGURATION
540 13:15:07.620469 ===================================
541 13:15:07.623138 EX_ROW_EN[0] = 0x0
542 13:15:07.626688 EX_ROW_EN[1] = 0x0
543 13:15:07.627080 LP4Y_EN = 0x0
544 13:15:07.630047 WORK_FSP = 0x0
545 13:15:07.630563 WL = 0x2
546 13:15:07.633346 RL = 0x2
547 13:15:07.633787 BL = 0x2
548 13:15:07.636772 RPST = 0x0
549 13:15:07.637208 RD_PRE = 0x0
550 13:15:07.639969 WR_PRE = 0x1
551 13:15:07.640409 WR_PST = 0x0
552 13:15:07.644188 DBI_WR = 0x0
553 13:15:07.644732 DBI_RD = 0x0
554 13:15:07.647752 OTF = 0x1
555 13:15:07.648256 ===================================
556 13:15:07.651424 ===================================
557 13:15:07.654150 ANA top config
558 13:15:07.658396 ===================================
559 13:15:07.658790 DLL_ASYNC_EN = 0
560 13:15:07.661668 ALL_SLAVE_EN = 1
561 13:15:07.665637 NEW_RANK_MODE = 1
562 13:15:07.669325 DLL_IDLE_MODE = 1
563 13:15:07.669721 LP45_APHY_COMB_EN = 1
564 13:15:07.673253 TX_ODT_DIS = 1
565 13:15:07.676774 NEW_8X_MODE = 1
566 13:15:07.680057 ===================================
567 13:15:07.680647 ===================================
568 13:15:07.683367 data_rate = 1600
569 13:15:07.687225 CKR = 1
570 13:15:07.690231 DQ_P2S_RATIO = 8
571 13:15:07.693887 ===================================
572 13:15:07.697081 CA_P2S_RATIO = 8
573 13:15:07.700795 DQ_CA_OPEN = 0
574 13:15:07.701229 DQ_SEMI_OPEN = 0
575 13:15:07.703756 CA_SEMI_OPEN = 0
576 13:15:07.707193 CA_FULL_RATE = 0
577 13:15:07.710609 DQ_CKDIV4_EN = 1
578 13:15:07.713815 CA_CKDIV4_EN = 1
579 13:15:07.717210 CA_PREDIV_EN = 0
580 13:15:07.717596 PH8_DLY = 0
581 13:15:07.720670 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 13:15:07.724312 DQ_AAMCK_DIV = 4
583 13:15:07.727598 CA_AAMCK_DIV = 4
584 13:15:07.730697 CA_ADMCK_DIV = 4
585 13:15:07.731216 DQ_TRACK_CA_EN = 0
586 13:15:07.734701 CA_PICK = 800
587 13:15:07.737773 CA_MCKIO = 800
588 13:15:07.740585 MCKIO_SEMI = 0
589 13:15:07.744022 PLL_FREQ = 3068
590 13:15:07.747497 DQ_UI_PI_RATIO = 32
591 13:15:07.751110 CA_UI_PI_RATIO = 0
592 13:15:07.754329 ===================================
593 13:15:07.754718 ===================================
594 13:15:07.757715 memory_type:LPDDR4
595 13:15:07.761272 GP_NUM : 10
596 13:15:07.761667 SRAM_EN : 1
597 13:15:07.764359 MD32_EN : 0
598 13:15:07.767682 ===================================
599 13:15:07.771334 [ANA_INIT] >>>>>>>>>>>>>>
600 13:15:07.774510 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 13:15:07.777521 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 13:15:07.780784 ===================================
603 13:15:07.781190 data_rate = 1600,PCW = 0X7600
604 13:15:07.784598 ===================================
605 13:15:07.787977 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 13:15:07.794683 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 13:15:07.802230 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 13:15:07.804424 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 13:15:07.807848 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 13:15:07.811543 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 13:15:07.814761 [ANA_INIT] flow start
612 13:15:07.815146 [ANA_INIT] PLL >>>>>>>>
613 13:15:07.818354 [ANA_INIT] PLL <<<<<<<<
614 13:15:07.821417 [ANA_INIT] MIDPI >>>>>>>>
615 13:15:07.824819 [ANA_INIT] MIDPI <<<<<<<<
616 13:15:07.825243 [ANA_INIT] DLL >>>>>>>>
617 13:15:07.828260 [ANA_INIT] flow end
618 13:15:07.831293 ============ LP4 DIFF to SE enter ============
619 13:15:07.834745 ============ LP4 DIFF to SE exit ============
620 13:15:07.837951 [ANA_INIT] <<<<<<<<<<<<<
621 13:15:07.841523 [Flow] Enable top DCM control >>>>>
622 13:15:07.844895 [Flow] Enable top DCM control <<<<<
623 13:15:07.848050 Enable DLL master slave shuffle
624 13:15:07.851669 ==============================================================
625 13:15:07.854895 Gating Mode config
626 13:15:07.861663 ==============================================================
627 13:15:07.862058 Config description:
628 13:15:07.871731 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 13:15:07.878282 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 13:15:07.882405 SELPH_MODE 0: By rank 1: By Phase
631 13:15:07.888443 ==============================================================
632 13:15:07.891834 GAT_TRACK_EN = 1
633 13:15:07.895319 RX_GATING_MODE = 2
634 13:15:07.898277 RX_GATING_TRACK_MODE = 2
635 13:15:07.902136 SELPH_MODE = 1
636 13:15:07.905436 PICG_EARLY_EN = 1
637 13:15:07.905822 VALID_LAT_VALUE = 1
638 13:15:07.912117 ==============================================================
639 13:15:07.915518 Enter into Gating configuration >>>>
640 13:15:07.918754 Exit from Gating configuration <<<<
641 13:15:07.922220 Enter into DVFS_PRE_config >>>>>
642 13:15:07.932318 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 13:15:07.935527 Exit from DVFS_PRE_config <<<<<
644 13:15:07.938651 Enter into PICG configuration >>>>
645 13:15:07.942501 Exit from PICG configuration <<<<
646 13:15:07.945588 [RX_INPUT] configuration >>>>>
647 13:15:07.948867 [RX_INPUT] configuration <<<<<
648 13:15:07.952750 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 13:15:07.958900 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 13:15:07.965970 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 13:15:07.972642 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 13:15:07.976095 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 13:15:07.982429 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 13:15:07.985886 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 13:15:07.992813 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 13:15:07.995912 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 13:15:07.999142 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 13:15:08.002931 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 13:15:08.009761 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 13:15:08.012901 ===================================
661 13:15:08.013343 LPDDR4 DRAM CONFIGURATION
662 13:15:08.016356 ===================================
663 13:15:08.019980 EX_ROW_EN[0] = 0x0
664 13:15:08.020367 EX_ROW_EN[1] = 0x0
665 13:15:08.023352 LP4Y_EN = 0x0
666 13:15:08.023738 WORK_FSP = 0x0
667 13:15:08.026429 WL = 0x2
668 13:15:08.029978 RL = 0x2
669 13:15:08.030364 BL = 0x2
670 13:15:08.033321 RPST = 0x0
671 13:15:08.033727 RD_PRE = 0x0
672 13:15:08.036392 WR_PRE = 0x1
673 13:15:08.036788 WR_PST = 0x0
674 13:15:08.039931 DBI_WR = 0x0
675 13:15:08.040317 DBI_RD = 0x0
676 13:15:08.043651 OTF = 0x1
677 13:15:08.046437 ===================================
678 13:15:08.050537 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 13:15:08.052925 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 13:15:08.056545 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 13:15:08.059786 ===================================
682 13:15:08.063228 LPDDR4 DRAM CONFIGURATION
683 13:15:08.066503 ===================================
684 13:15:08.069676 EX_ROW_EN[0] = 0x10
685 13:15:08.070198 EX_ROW_EN[1] = 0x0
686 13:15:08.073292 LP4Y_EN = 0x0
687 13:15:08.073782 WORK_FSP = 0x0
688 13:15:08.076513 WL = 0x2
689 13:15:08.076988 RL = 0x2
690 13:15:08.079879 BL = 0x2
691 13:15:08.080349 RPST = 0x0
692 13:15:08.083115 RD_PRE = 0x0
693 13:15:08.083499 WR_PRE = 0x1
694 13:15:08.086585 WR_PST = 0x0
695 13:15:08.086972 DBI_WR = 0x0
696 13:15:08.090110 DBI_RD = 0x0
697 13:15:08.090652 OTF = 0x1
698 13:15:08.093628 ===================================
699 13:15:08.100269 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 13:15:08.105168 nWR fixed to 40
701 13:15:08.108108 [ModeRegInit_LP4] CH0 RK0
702 13:15:08.108493 [ModeRegInit_LP4] CH0 RK1
703 13:15:08.111261 [ModeRegInit_LP4] CH1 RK0
704 13:15:08.114685 [ModeRegInit_LP4] CH1 RK1
705 13:15:08.115072 match AC timing 13
706 13:15:08.121394 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 13:15:08.124799 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 13:15:08.127920 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 13:15:08.135029 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 13:15:08.138454 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 13:15:08.138844 [EMI DOE] emi_dcm 0
712 13:15:08.145296 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 13:15:08.145685 ==
714 13:15:08.148448 Dram Type= 6, Freq= 0, CH_0, rank 0
715 13:15:08.152034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 13:15:08.152424 ==
717 13:15:08.158348 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 13:15:08.161607 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 13:15:08.172265 [CA 0] Center 37 (7~68) winsize 62
720 13:15:08.176006 [CA 1] Center 37 (6~68) winsize 63
721 13:15:08.179141 [CA 2] Center 35 (5~66) winsize 62
722 13:15:08.182133 [CA 3] Center 34 (4~65) winsize 62
723 13:15:08.185650 [CA 4] Center 34 (3~65) winsize 63
724 13:15:08.188732 [CA 5] Center 33 (3~64) winsize 62
725 13:15:08.189147
726 13:15:08.192221 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 13:15:08.192625
728 13:15:08.195868 [CATrainingPosCal] consider 1 rank data
729 13:15:08.199514 u2DelayCellTimex100 = 270/100 ps
730 13:15:08.202348 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 13:15:08.206185 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 13:15:08.209749 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 13:15:08.213147 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 13:15:08.216490 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
735 13:15:08.223520 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 13:15:08.223914
737 13:15:08.226923 CA PerBit enable=1, Macro0, CA PI delay=33
738 13:15:08.227312
739 13:15:08.230798 [CBTSetCACLKResult] CA Dly = 33
740 13:15:08.231189 CS Dly: 5 (0~36)
741 13:15:08.231493 ==
742 13:15:08.233935 Dram Type= 6, Freq= 0, CH_0, rank 1
743 13:15:08.237377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 13:15:08.237795 ==
745 13:15:08.243724 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 13:15:08.250363 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 13:15:08.258385 [CA 0] Center 37 (6~68) winsize 63
748 13:15:08.261745 [CA 1] Center 37 (7~68) winsize 62
749 13:15:08.264942 [CA 2] Center 35 (5~66) winsize 62
750 13:15:08.268917 [CA 3] Center 35 (4~66) winsize 63
751 13:15:08.271750 [CA 4] Center 34 (3~65) winsize 63
752 13:15:08.275445 [CA 5] Center 33 (3~64) winsize 62
753 13:15:08.275841
754 13:15:08.278427 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 13:15:08.278820
756 13:15:08.281590 [CATrainingPosCal] consider 2 rank data
757 13:15:08.284836 u2DelayCellTimex100 = 270/100 ps
758 13:15:08.288913 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 13:15:08.292033 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 13:15:08.298288 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 13:15:08.301883 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 13:15:08.305300 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
763 13:15:08.308619 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 13:15:08.309014
765 13:15:08.311816 CA PerBit enable=1, Macro0, CA PI delay=33
766 13:15:08.312211
767 13:15:08.315084 [CBTSetCACLKResult] CA Dly = 33
768 13:15:08.315476 CS Dly: 5 (0~37)
769 13:15:08.315780
770 13:15:08.318981 ----->DramcWriteLeveling(PI) begin...
771 13:15:08.319381 ==
772 13:15:08.322088 Dram Type= 6, Freq= 0, CH_0, rank 0
773 13:15:08.328678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 13:15:08.329077 ==
775 13:15:08.332033 Write leveling (Byte 0): 30 => 30
776 13:15:08.335222 Write leveling (Byte 1): 29 => 29
777 13:15:08.335660 DramcWriteLeveling(PI) end<-----
778 13:15:08.335967
779 13:15:08.339011 ==
780 13:15:08.342642 Dram Type= 6, Freq= 0, CH_0, rank 0
781 13:15:08.345287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 13:15:08.345686 ==
783 13:15:08.349178 [Gating] SW mode calibration
784 13:15:08.355481 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 13:15:08.358557 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 13:15:08.365899 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 13:15:08.368752 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 13:15:08.372593 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 13:15:08.379196 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:15:08.382015 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:15:08.385756 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:15:08.389043 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:15:08.395515 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:15:08.399228 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:15:08.402973 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:15:08.409045 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:15:08.412724 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:15:08.415866 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:15:08.422859 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:15:08.426254 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:15:08.429643 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:15:08.436059 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:15:08.439415 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 13:15:08.442805 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
805 13:15:08.446352 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:15:08.452704 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:15:08.456439 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:15:08.459793 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:15:08.466469 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:15:08.469653 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 13:15:08.473204 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 13:15:08.479971 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 13:15:08.483008 0 9 12 | B1->B0 | 2525 3232 | 1 1 | (1 1) (1 1)
814 13:15:08.486328 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 13:15:08.493729 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 13:15:08.496535 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 13:15:08.500214 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 13:15:08.502905 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 13:15:08.510114 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 13:15:08.513268 0 10 8 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
821 13:15:08.516769 0 10 12 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
822 13:15:08.523572 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 13:15:08.526601 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 13:15:08.530390 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 13:15:08.536714 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 13:15:08.539896 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 13:15:08.543367 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 13:15:08.549807 0 11 8 | B1->B0 | 2727 3232 | 0 1 | (0 0) (1 1)
829 13:15:08.553439 0 11 12 | B1->B0 | 3a3a 4242 | 0 0 | (0 0) (0 0)
830 13:15:08.556894 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 13:15:08.563203 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 13:15:08.566688 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 13:15:08.570035 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 13:15:08.576779 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 13:15:08.579843 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 13:15:08.583406 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 13:15:08.586538 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 13:15:08.593700 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:15:08.596959 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:15:08.600363 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:15:08.606868 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:15:08.610467 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:15:08.613790 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:15:08.620548 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:15:08.623640 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:15:08.627251 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:15:08.633717 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:15:08.637523 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:15:08.640896 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:15:08.644651 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:15:08.650882 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 13:15:08.653819 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 13:15:08.657880 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
854 13:15:08.661099 Total UI for P1: 0, mck2ui 16
855 13:15:08.664266 best dqsien dly found for B0: ( 0, 14, 8)
856 13:15:08.671526 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 13:15:08.672036 Total UI for P1: 0, mck2ui 16
858 13:15:08.677863 best dqsien dly found for B1: ( 0, 14, 10)
859 13:15:08.680666 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
860 13:15:08.684628 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 13:15:08.685101
862 13:15:08.687572 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 13:15:08.690903 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 13:15:08.694350 [Gating] SW calibration Done
865 13:15:08.694747 ==
866 13:15:08.697807 Dram Type= 6, Freq= 0, CH_0, rank 0
867 13:15:08.701076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 13:15:08.701510 ==
869 13:15:08.704325 RX Vref Scan: 0
870 13:15:08.704714
871 13:15:08.705020 RX Vref 0 -> 0, step: 1
872 13:15:08.705358
873 13:15:08.707589 RX Delay -130 -> 252, step: 16
874 13:15:08.711425 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 13:15:08.717456 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
876 13:15:08.721164 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 13:15:08.724898 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 13:15:08.727832 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
879 13:15:08.731434 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
880 13:15:08.734814 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
881 13:15:08.741236 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
882 13:15:08.744536 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
883 13:15:08.748176 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
884 13:15:08.751248 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
885 13:15:08.754658 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
886 13:15:08.762042 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
887 13:15:08.764528 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
888 13:15:08.768478 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
889 13:15:08.771850 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
890 13:15:08.772294 ==
891 13:15:08.774963 Dram Type= 6, Freq= 0, CH_0, rank 0
892 13:15:08.778173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 13:15:08.781522 ==
894 13:15:08.782045 DQS Delay:
895 13:15:08.782511 DQS0 = 0, DQS1 = 0
896 13:15:08.785219 DQM Delay:
897 13:15:08.785715 DQM0 = 84, DQM1 = 75
898 13:15:08.788552 DQ Delay:
899 13:15:08.788963 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
900 13:15:08.791481 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
901 13:15:08.794859 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
902 13:15:08.798290 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
903 13:15:08.798831
904 13:15:08.801467
905 13:15:08.801956 ==
906 13:15:08.805080 Dram Type= 6, Freq= 0, CH_0, rank 0
907 13:15:08.808557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 13:15:08.809210 ==
909 13:15:08.809759
910 13:15:08.810127
911 13:15:08.811584 TX Vref Scan disable
912 13:15:08.811969 == TX Byte 0 ==
913 13:15:08.818891 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
914 13:15:08.822119 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
915 13:15:08.822508 == TX Byte 1 ==
916 13:15:08.828060 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
917 13:15:08.831823 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
918 13:15:08.832210 ==
919 13:15:08.835298 Dram Type= 6, Freq= 0, CH_0, rank 0
920 13:15:08.838585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 13:15:08.838974 ==
922 13:15:08.852264 TX Vref=22, minBit 5, minWin=27, winSum=441
923 13:15:08.855318 TX Vref=24, minBit 5, minWin=27, winSum=445
924 13:15:08.859322 TX Vref=26, minBit 5, minWin=27, winSum=448
925 13:15:08.862188 TX Vref=28, minBit 12, minWin=27, winSum=449
926 13:15:08.865287 TX Vref=30, minBit 12, minWin=27, winSum=456
927 13:15:08.868671 TX Vref=32, minBit 12, minWin=27, winSum=454
928 13:15:08.875742 [TxChooseVref] Worse bit 12, Min win 27, Win sum 456, Final Vref 30
929 13:15:08.876259
930 13:15:08.879185 Final TX Range 1 Vref 30
931 13:15:08.879717
932 13:15:08.880050 ==
933 13:15:08.882423 Dram Type= 6, Freq= 0, CH_0, rank 0
934 13:15:08.886030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 13:15:08.886549 ==
936 13:15:08.886885
937 13:15:08.889177
938 13:15:08.889606 TX Vref Scan disable
939 13:15:08.892431 == TX Byte 0 ==
940 13:15:08.896045 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
941 13:15:08.899470 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
942 13:15:08.902341 == TX Byte 1 ==
943 13:15:08.906117 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
944 13:15:08.909474 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
945 13:15:08.909996
946 13:15:08.912691 [DATLAT]
947 13:15:08.913243 Freq=800, CH0 RK0
948 13:15:08.913588
949 13:15:08.915849 DATLAT Default: 0xa
950 13:15:08.916356 0, 0xFFFF, sum = 0
951 13:15:08.918964 1, 0xFFFF, sum = 0
952 13:15:08.919544 2, 0xFFFF, sum = 0
953 13:15:08.923037 3, 0xFFFF, sum = 0
954 13:15:08.923560 4, 0xFFFF, sum = 0
955 13:15:08.926243 5, 0xFFFF, sum = 0
956 13:15:08.926779 6, 0xFFFF, sum = 0
957 13:15:08.929068 7, 0xFFFF, sum = 0
958 13:15:08.929537 8, 0xFFFF, sum = 0
959 13:15:08.932528 9, 0x0, sum = 1
960 13:15:08.932989 10, 0x0, sum = 2
961 13:15:08.936002 11, 0x0, sum = 3
962 13:15:08.936439 12, 0x0, sum = 4
963 13:15:08.939859 best_step = 10
964 13:15:08.940373
965 13:15:08.940725 ==
966 13:15:08.942572 Dram Type= 6, Freq= 0, CH_0, rank 0
967 13:15:08.945829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 13:15:08.946265 ==
969 13:15:08.949576 RX Vref Scan: 1
970 13:15:08.950021
971 13:15:08.950420 Set Vref Range= 32 -> 127
972 13:15:08.950856
973 13:15:08.952570 RX Vref 32 -> 127, step: 1
974 13:15:08.953001
975 13:15:08.956589 RX Delay -95 -> 252, step: 8
976 13:15:08.957022
977 13:15:08.960328 Set Vref, RX VrefLevel [Byte0]: 32
978 13:15:08.962854 [Byte1]: 32
979 13:15:08.963377
980 13:15:08.966277 Set Vref, RX VrefLevel [Byte0]: 33
981 13:15:08.969455 [Byte1]: 33
982 13:15:08.969848
983 13:15:08.973277 Set Vref, RX VrefLevel [Byte0]: 34
984 13:15:08.976156 [Byte1]: 34
985 13:15:08.980151
986 13:15:08.980539 Set Vref, RX VrefLevel [Byte0]: 35
987 13:15:08.983102 [Byte1]: 35
988 13:15:08.987946
989 13:15:08.988449 Set Vref, RX VrefLevel [Byte0]: 36
990 13:15:08.990858 [Byte1]: 36
991 13:15:08.995225
992 13:15:08.995661 Set Vref, RX VrefLevel [Byte0]: 37
993 13:15:08.998919 [Byte1]: 37
994 13:15:09.002925
995 13:15:09.003431 Set Vref, RX VrefLevel [Byte0]: 38
996 13:15:09.006310 [Byte1]: 38
997 13:15:09.010628
998 13:15:09.011147 Set Vref, RX VrefLevel [Byte0]: 39
999 13:15:09.014479 [Byte1]: 39
1000 13:15:09.018166
1001 13:15:09.018676 Set Vref, RX VrefLevel [Byte0]: 40
1002 13:15:09.021444 [Byte1]: 40
1003 13:15:09.025740
1004 13:15:09.026250 Set Vref, RX VrefLevel [Byte0]: 41
1005 13:15:09.029337 [Byte1]: 41
1006 13:15:09.033363
1007 13:15:09.033796 Set Vref, RX VrefLevel [Byte0]: 42
1008 13:15:09.036282 [Byte1]: 42
1009 13:15:09.040632
1010 13:15:09.041065 Set Vref, RX VrefLevel [Byte0]: 43
1011 13:15:09.044596 [Byte1]: 43
1012 13:15:09.048274
1013 13:15:09.048808 Set Vref, RX VrefLevel [Byte0]: 44
1014 13:15:09.051823 [Byte1]: 44
1015 13:15:09.056310
1016 13:15:09.056822 Set Vref, RX VrefLevel [Byte0]: 45
1017 13:15:09.059667 [Byte1]: 45
1018 13:15:09.063594
1019 13:15:09.064022 Set Vref, RX VrefLevel [Byte0]: 46
1020 13:15:09.067015 [Byte1]: 46
1021 13:15:09.071195
1022 13:15:09.071709 Set Vref, RX VrefLevel [Byte0]: 47
1023 13:15:09.074796 [Byte1]: 47
1024 13:15:09.079472
1025 13:15:09.079984 Set Vref, RX VrefLevel [Byte0]: 48
1026 13:15:09.082363 [Byte1]: 48
1027 13:15:09.086823
1028 13:15:09.087336 Set Vref, RX VrefLevel [Byte0]: 49
1029 13:15:09.089874 [Byte1]: 49
1030 13:15:09.094396
1031 13:15:09.094916 Set Vref, RX VrefLevel [Byte0]: 50
1032 13:15:09.097836 [Byte1]: 50
1033 13:15:09.102094
1034 13:15:09.102622 Set Vref, RX VrefLevel [Byte0]: 51
1035 13:15:09.105241 [Byte1]: 51
1036 13:15:09.109287
1037 13:15:09.109825 Set Vref, RX VrefLevel [Byte0]: 52
1038 13:15:09.112947 [Byte1]: 52
1039 13:15:09.116962
1040 13:15:09.117523 Set Vref, RX VrefLevel [Byte0]: 53
1041 13:15:09.120457 [Byte1]: 53
1042 13:15:09.124399
1043 13:15:09.124909 Set Vref, RX VrefLevel [Byte0]: 54
1044 13:15:09.127535 [Byte1]: 54
1045 13:15:09.131987
1046 13:15:09.132415 Set Vref, RX VrefLevel [Byte0]: 55
1047 13:15:09.135582 [Byte1]: 55
1048 13:15:09.139337
1049 13:15:09.139763 Set Vref, RX VrefLevel [Byte0]: 56
1050 13:15:09.142764 [Byte1]: 56
1051 13:15:09.147311
1052 13:15:09.147700 Set Vref, RX VrefLevel [Byte0]: 57
1053 13:15:09.150501 [Byte1]: 57
1054 13:15:09.155102
1055 13:15:09.155565 Set Vref, RX VrefLevel [Byte0]: 58
1056 13:15:09.158011 [Byte1]: 58
1057 13:15:09.163007
1058 13:15:09.163397 Set Vref, RX VrefLevel [Byte0]: 59
1059 13:15:09.166040 [Byte1]: 59
1060 13:15:09.170019
1061 13:15:09.170506 Set Vref, RX VrefLevel [Byte0]: 60
1062 13:15:09.173304 [Byte1]: 60
1063 13:15:09.178126
1064 13:15:09.178661 Set Vref, RX VrefLevel [Byte0]: 61
1065 13:15:09.180837 [Byte1]: 61
1066 13:15:09.185003
1067 13:15:09.185448 Set Vref, RX VrefLevel [Byte0]: 62
1068 13:15:09.188624 [Byte1]: 62
1069 13:15:09.193273
1070 13:15:09.193774 Set Vref, RX VrefLevel [Byte0]: 63
1071 13:15:09.196505 [Byte1]: 63
1072 13:15:09.200349
1073 13:15:09.200860 Set Vref, RX VrefLevel [Byte0]: 64
1074 13:15:09.203730 [Byte1]: 64
1075 13:15:09.208164
1076 13:15:09.208676 Set Vref, RX VrefLevel [Byte0]: 65
1077 13:15:09.211271 [Byte1]: 65
1078 13:15:09.215880
1079 13:15:09.216391 Set Vref, RX VrefLevel [Byte0]: 66
1080 13:15:09.219112 [Byte1]: 66
1081 13:15:09.223345
1082 13:15:09.223853 Set Vref, RX VrefLevel [Byte0]: 67
1083 13:15:09.227015 [Byte1]: 67
1084 13:15:09.231034
1085 13:15:09.231548 Set Vref, RX VrefLevel [Byte0]: 68
1086 13:15:09.234174 [Byte1]: 68
1087 13:15:09.239135
1088 13:15:09.239662 Set Vref, RX VrefLevel [Byte0]: 69
1089 13:15:09.241710 [Byte1]: 69
1090 13:15:09.246299
1091 13:15:09.246807 Set Vref, RX VrefLevel [Byte0]: 70
1092 13:15:09.249701 [Byte1]: 70
1093 13:15:09.253598
1094 13:15:09.254107 Set Vref, RX VrefLevel [Byte0]: 71
1095 13:15:09.256976 [Byte1]: 71
1096 13:15:09.261478
1097 13:15:09.262008 Set Vref, RX VrefLevel [Byte0]: 72
1098 13:15:09.264304 [Byte1]: 72
1099 13:15:09.269267
1100 13:15:09.269780 Final RX Vref Byte 0 = 62 to rank0
1101 13:15:09.272343 Final RX Vref Byte 1 = 55 to rank0
1102 13:15:09.275448 Final RX Vref Byte 0 = 62 to rank1
1103 13:15:09.278833 Final RX Vref Byte 1 = 55 to rank1==
1104 13:15:09.282604 Dram Type= 6, Freq= 0, CH_0, rank 0
1105 13:15:09.288896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1106 13:15:09.289624 ==
1107 13:15:09.290124 DQS Delay:
1108 13:15:09.290454 DQS0 = 0, DQS1 = 0
1109 13:15:09.292436 DQM Delay:
1110 13:15:09.292946 DQM0 = 87, DQM1 = 78
1111 13:15:09.295492 DQ Delay:
1112 13:15:09.298702 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1113 13:15:09.299212 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1114 13:15:09.302068 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1115 13:15:09.305589 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1116 13:15:09.309266
1117 13:15:09.309774
1118 13:15:09.316090 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
1119 13:15:09.318457 CH0 RK0: MR19=606, MR18=2B12
1120 13:15:09.325915 CH0_RK0: MR19=0x606, MR18=0x2B12, DQSOSC=398, MR23=63, INC=93, DEC=62
1121 13:15:09.326431
1122 13:15:09.328870 ----->DramcWriteLeveling(PI) begin...
1123 13:15:09.329427 ==
1124 13:15:09.332545 Dram Type= 6, Freq= 0, CH_0, rank 1
1125 13:15:09.335913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1126 13:15:09.336429 ==
1127 13:15:09.338741 Write leveling (Byte 0): 30 => 30
1128 13:15:09.341989 Write leveling (Byte 1): 26 => 26
1129 13:15:09.345697 DramcWriteLeveling(PI) end<-----
1130 13:15:09.346215
1131 13:15:09.346552 ==
1132 13:15:09.349161 Dram Type= 6, Freq= 0, CH_0, rank 1
1133 13:15:09.353042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1134 13:15:09.353666 ==
1135 13:15:09.355912 [Gating] SW mode calibration
1136 13:15:09.362838 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1137 13:15:09.369229 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1138 13:15:09.372596 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1139 13:15:09.376060 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1140 13:15:09.379150 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1141 13:15:09.385969 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1142 13:15:09.390050 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1143 13:15:09.393156 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1144 13:15:09.399245 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1145 13:15:09.402646 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 13:15:09.406048 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 13:15:09.413839 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 13:15:09.416296 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 13:15:09.419734 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 13:15:09.426371 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 13:15:09.429806 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 13:15:09.473789 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 13:15:09.474450 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 13:15:09.475233 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 13:15:09.475660 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1156 13:15:09.475979 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1157 13:15:09.476284 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 13:15:09.476576 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 13:15:09.476901 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 13:15:09.477419 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 13:15:09.477724 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 13:15:09.518416 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:15:09.519066 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 13:15:09.519501 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
1165 13:15:09.520198 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1166 13:15:09.520644 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1167 13:15:09.521075 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1168 13:15:09.521533 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1169 13:15:09.521842 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1170 13:15:09.522130 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 13:15:09.522414 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
1172 13:15:09.562054 0 10 8 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
1173 13:15:09.562576 0 10 12 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
1174 13:15:09.562933 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 13:15:09.563249 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 13:15:09.563892 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 13:15:09.564220 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 13:15:09.564512 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 13:15:09.564805 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1180 13:15:09.565093 0 11 8 | B1->B0 | 2626 3d3d | 0 0 | (1 1) (1 1)
1181 13:15:09.565421 0 11 12 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
1182 13:15:09.567984 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1183 13:15:09.571546 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 13:15:09.575312 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 13:15:09.577980 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 13:15:09.581179 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 13:15:09.588234 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1188 13:15:09.591413 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1189 13:15:09.594901 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1190 13:15:09.601238 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 13:15:09.604507 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 13:15:09.607634 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 13:15:09.614309 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 13:15:09.617786 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 13:15:09.621330 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 13:15:09.628454 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 13:15:09.631744 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 13:15:09.635010 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 13:15:09.641543 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 13:15:09.644845 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 13:15:09.648215 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 13:15:09.651466 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 13:15:09.658657 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1204 13:15:09.661926 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1205 13:15:09.665193 Total UI for P1: 0, mck2ui 16
1206 13:15:09.668455 best dqsien dly found for B0: ( 0, 14, 4)
1207 13:15:09.671956 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 13:15:09.675374 Total UI for P1: 0, mck2ui 16
1209 13:15:09.678403 best dqsien dly found for B1: ( 0, 14, 8)
1210 13:15:09.681779 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1211 13:15:09.684967 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1212 13:15:09.685429
1213 13:15:09.691805 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1214 13:15:09.694938 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1215 13:15:09.695372 [Gating] SW calibration Done
1216 13:15:09.698498 ==
1217 13:15:09.699010 Dram Type= 6, Freq= 0, CH_0, rank 1
1218 13:15:09.705011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1219 13:15:09.705564 ==
1220 13:15:09.705910 RX Vref Scan: 0
1221 13:15:09.706222
1222 13:15:09.708827 RX Vref 0 -> 0, step: 1
1223 13:15:09.709383
1224 13:15:09.711990 RX Delay -130 -> 252, step: 16
1225 13:15:09.715147 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1226 13:15:09.718748 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1227 13:15:09.721883 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1228 13:15:09.728722 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1229 13:15:09.731705 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1230 13:15:09.735607 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1231 13:15:09.738941 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1232 13:15:09.742146 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1233 13:15:09.745481 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1234 13:15:09.752193 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1235 13:15:09.755271 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1236 13:15:09.759233 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1237 13:15:09.762456 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1238 13:15:09.765210 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1239 13:15:09.772773 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1240 13:15:09.775297 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1241 13:15:09.775691 ==
1242 13:15:09.778716 Dram Type= 6, Freq= 0, CH_0, rank 1
1243 13:15:09.781879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1244 13:15:09.781964 ==
1245 13:15:09.785545 DQS Delay:
1246 13:15:09.785623 DQS0 = 0, DQS1 = 0
1247 13:15:09.785681 DQM Delay:
1248 13:15:09.788657 DQM0 = 84, DQM1 = 77
1249 13:15:09.788733 DQ Delay:
1250 13:15:09.791982 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1251 13:15:09.795357 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
1252 13:15:09.798984 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1253 13:15:09.802515 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1254 13:15:09.802594
1255 13:15:09.802653
1256 13:15:09.802707 ==
1257 13:15:09.805617 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 13:15:09.808673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1259 13:15:09.812015 ==
1260 13:15:09.812095
1261 13:15:09.812154
1262 13:15:09.812209 TX Vref Scan disable
1263 13:15:09.815225 == TX Byte 0 ==
1264 13:15:09.818925 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1265 13:15:09.821983 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1266 13:15:09.825722 == TX Byte 1 ==
1267 13:15:09.828927 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1268 13:15:09.832032 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1269 13:15:09.835516 ==
1270 13:15:09.835596 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 13:15:09.842153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 13:15:09.842238 ==
1273 13:15:09.854983 TX Vref=22, minBit 9, minWin=26, winSum=437
1274 13:15:09.858125 TX Vref=24, minBit 9, minWin=26, winSum=445
1275 13:15:09.861993 TX Vref=26, minBit 3, minWin=27, winSum=448
1276 13:15:09.865073 TX Vref=28, minBit 9, minWin=26, winSum=447
1277 13:15:09.868302 TX Vref=30, minBit 9, minWin=27, winSum=449
1278 13:15:09.872530 TX Vref=32, minBit 8, minWin=27, winSum=445
1279 13:15:09.878206 [TxChooseVref] Worse bit 9, Min win 27, Win sum 449, Final Vref 30
1280 13:15:09.878304
1281 13:15:09.882252 Final TX Range 1 Vref 30
1282 13:15:09.882342
1283 13:15:09.882401 ==
1284 13:15:09.885346 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 13:15:09.888502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 13:15:09.888580 ==
1287 13:15:09.888639
1288 13:15:09.888692
1289 13:15:09.892056 TX Vref Scan disable
1290 13:15:09.895773 == TX Byte 0 ==
1291 13:15:09.898531 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1292 13:15:09.902094 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1293 13:15:09.905015 == TX Byte 1 ==
1294 13:15:09.908783 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1295 13:15:09.911841 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1296 13:15:09.911921
1297 13:15:09.915259 [DATLAT]
1298 13:15:09.915336 Freq=800, CH0 RK1
1299 13:15:09.915394
1300 13:15:09.918920 DATLAT Default: 0xa
1301 13:15:09.919001 0, 0xFFFF, sum = 0
1302 13:15:09.922548 1, 0xFFFF, sum = 0
1303 13:15:09.922627 2, 0xFFFF, sum = 0
1304 13:15:09.925728 3, 0xFFFF, sum = 0
1305 13:15:09.925805 4, 0xFFFF, sum = 0
1306 13:15:09.929006 5, 0xFFFF, sum = 0
1307 13:15:09.929107 6, 0xFFFF, sum = 0
1308 13:15:09.932451 7, 0xFFFF, sum = 0
1309 13:15:09.932534 8, 0xFFFF, sum = 0
1310 13:15:09.935693 9, 0x0, sum = 1
1311 13:15:09.935778 10, 0x0, sum = 2
1312 13:15:09.939251 11, 0x0, sum = 3
1313 13:15:09.939331 12, 0x0, sum = 4
1314 13:15:09.942025 best_step = 10
1315 13:15:09.942101
1316 13:15:09.942159 ==
1317 13:15:09.945442 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 13:15:09.948938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1319 13:15:09.949037 ==
1320 13:15:09.949127 RX Vref Scan: 0
1321 13:15:09.952122
1322 13:15:09.952198 RX Vref 0 -> 0, step: 1
1323 13:15:09.952255
1324 13:15:09.955688 RX Delay -95 -> 252, step: 8
1325 13:15:09.959210 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1326 13:15:09.965905 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1327 13:15:09.969491 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1328 13:15:09.972406 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1329 13:15:09.975711 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1330 13:15:09.979243 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1331 13:15:09.986053 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1332 13:15:09.989375 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1333 13:15:09.992761 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1334 13:15:09.996045 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1335 13:15:09.999364 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1336 13:15:10.003239 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1337 13:15:10.009715 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1338 13:15:10.012616 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1339 13:15:10.016582 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1340 13:15:10.019592 iDelay=209, Bit 15, Center 84 (-23 ~ 192) 216
1341 13:15:10.019816 ==
1342 13:15:10.023299 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 13:15:10.029598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 13:15:10.029897 ==
1345 13:15:10.030080 DQS Delay:
1346 13:15:10.033214 DQS0 = 0, DQS1 = 0
1347 13:15:10.033584 DQM Delay:
1348 13:15:10.033803 DQM0 = 87, DQM1 = 77
1349 13:15:10.036236 DQ Delay:
1350 13:15:10.040165 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1351 13:15:10.043519 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1352 13:15:10.046497 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1353 13:15:10.050016 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1354 13:15:10.050400
1355 13:15:10.050697
1356 13:15:10.056839 [DQSOSCAuto] RK1, (LSB)MR18= 0x3721, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 395 ps
1357 13:15:10.060203 CH0 RK1: MR19=606, MR18=3721
1358 13:15:10.066541 CH0_RK1: MR19=0x606, MR18=0x3721, DQSOSC=395, MR23=63, INC=94, DEC=63
1359 13:15:10.070072 [RxdqsGatingPostProcess] freq 800
1360 13:15:10.073207 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1361 13:15:10.077088 Pre-setting of DQS Precalculation
1362 13:15:10.083453 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1363 13:15:10.083918 ==
1364 13:15:10.086656 Dram Type= 6, Freq= 0, CH_1, rank 0
1365 13:15:10.090119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1366 13:15:10.090600 ==
1367 13:15:10.096533 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1368 13:15:10.099920 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1369 13:15:10.110282 [CA 0] Center 36 (6~66) winsize 61
1370 13:15:10.113822 [CA 1] Center 36 (6~66) winsize 61
1371 13:15:10.116957 [CA 2] Center 34 (4~65) winsize 62
1372 13:15:10.120500 [CA 3] Center 34 (3~65) winsize 63
1373 13:15:10.123819 [CA 4] Center 34 (4~65) winsize 62
1374 13:15:10.127349 [CA 5] Center 33 (3~64) winsize 62
1375 13:15:10.127816
1376 13:15:10.130495 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1377 13:15:10.130956
1378 13:15:10.133762 [CATrainingPosCal] consider 1 rank data
1379 13:15:10.137256 u2DelayCellTimex100 = 270/100 ps
1380 13:15:10.140547 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1381 13:15:10.143946 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1382 13:15:10.147234 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1383 13:15:10.153672 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1384 13:15:10.157204 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1385 13:15:10.160737 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1386 13:15:10.161296
1387 13:15:10.164059 CA PerBit enable=1, Macro0, CA PI delay=33
1388 13:15:10.164487
1389 13:15:10.167573 [CBTSetCACLKResult] CA Dly = 33
1390 13:15:10.168078 CS Dly: 4 (0~35)
1391 13:15:10.168410 ==
1392 13:15:10.170540 Dram Type= 6, Freq= 0, CH_1, rank 1
1393 13:15:10.177607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 13:15:10.178126 ==
1395 13:15:10.181050 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1396 13:15:10.187625 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1397 13:15:10.196490 [CA 0] Center 36 (6~66) winsize 61
1398 13:15:10.199514 [CA 1] Center 36 (6~66) winsize 61
1399 13:15:10.202725 [CA 2] Center 34 (4~64) winsize 61
1400 13:15:10.205973 [CA 3] Center 33 (3~64) winsize 62
1401 13:15:10.209697 [CA 4] Center 34 (3~65) winsize 63
1402 13:15:10.212902 [CA 5] Center 33 (3~64) winsize 62
1403 13:15:10.213348
1404 13:15:10.216319 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1405 13:15:10.216779
1406 13:15:10.219765 [CATrainingPosCal] consider 2 rank data
1407 13:15:10.223015 u2DelayCellTimex100 = 270/100 ps
1408 13:15:10.226517 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1409 13:15:10.229861 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1410 13:15:10.233564 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1411 13:15:10.239623 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1412 13:15:10.243058 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1413 13:15:10.246378 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1414 13:15:10.246763
1415 13:15:10.249615 CA PerBit enable=1, Macro0, CA PI delay=33
1416 13:15:10.250180
1417 13:15:10.253187 [CBTSetCACLKResult] CA Dly = 33
1418 13:15:10.253832 CS Dly: 5 (0~38)
1419 13:15:10.254147
1420 13:15:10.256721 ----->DramcWriteLeveling(PI) begin...
1421 13:15:10.257247 ==
1422 13:15:10.260147 Dram Type= 6, Freq= 0, CH_1, rank 0
1423 13:15:10.266541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1424 13:15:10.267005 ==
1425 13:15:10.270383 Write leveling (Byte 0): 27 => 27
1426 13:15:10.273839 Write leveling (Byte 1): 28 => 28
1427 13:15:10.274298 DramcWriteLeveling(PI) end<-----
1428 13:15:10.274596
1429 13:15:10.277139 ==
1430 13:15:10.277602 Dram Type= 6, Freq= 0, CH_1, rank 0
1431 13:15:10.283341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1432 13:15:10.283805 ==
1433 13:15:10.287609 [Gating] SW mode calibration
1434 13:15:10.294413 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1435 13:15:10.297517 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1436 13:15:10.304026 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1437 13:15:10.307467 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1438 13:15:10.310296 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1439 13:15:10.313536 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 13:15:10.320639 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 13:15:10.323299 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 13:15:10.327227 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 13:15:10.334156 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 13:15:10.337081 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 13:15:10.340353 0 7 4 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1446 13:15:10.347014 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 13:15:10.350367 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 13:15:10.353314 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 13:15:10.360879 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 13:15:10.363663 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 13:15:10.367466 0 7 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1452 13:15:10.374082 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 13:15:10.377501 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1454 13:15:10.380634 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 13:15:10.383700 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:15:10.390684 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 13:15:10.394076 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 13:15:10.397306 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 13:15:10.404326 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 13:15:10.407520 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 13:15:10.411105 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 13:15:10.417477 0 9 8 | B1->B0 | 2626 2a2a | 1 1 | (1 1) (1 1)
1463 13:15:10.421021 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1464 13:15:10.423987 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1465 13:15:10.431267 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1466 13:15:10.434252 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1467 13:15:10.437423 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 13:15:10.444065 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 13:15:10.447372 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
1470 13:15:10.451063 0 10 8 | B1->B0 | 2e2e 2b2b | 0 0 | (1 1) (0 0)
1471 13:15:10.454529 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 13:15:10.461338 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 13:15:10.464266 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 13:15:10.468286 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 13:15:10.474770 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 13:15:10.477767 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 13:15:10.481027 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1478 13:15:10.488774 0 11 8 | B1->B0 | 3535 3232 | 0 1 | (1 1) (0 0)
1479 13:15:10.491837 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1480 13:15:10.494384 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1481 13:15:10.501714 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1482 13:15:10.504651 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1483 13:15:10.507656 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 13:15:10.511249 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 13:15:10.518098 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 13:15:10.521800 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1487 13:15:10.524484 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1488 13:15:10.531679 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1489 13:15:10.534799 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1490 13:15:10.538237 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1491 13:15:10.544695 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 13:15:10.547971 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 13:15:10.551555 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 13:15:10.558669 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 13:15:10.561809 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 13:15:10.564925 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 13:15:10.571771 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 13:15:10.574964 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 13:15:10.578118 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 13:15:10.584875 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 13:15:10.588571 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1502 13:15:10.592191 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 13:15:10.595708 Total UI for P1: 0, mck2ui 16
1504 13:15:10.598593 best dqsien dly found for B0: ( 0, 14, 4)
1505 13:15:10.602062 Total UI for P1: 0, mck2ui 16
1506 13:15:10.605761 best dqsien dly found for B1: ( 0, 14, 6)
1507 13:15:10.608652 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1508 13:15:10.612075 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1509 13:15:10.612581
1510 13:15:10.615161 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1511 13:15:10.618730 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1512 13:15:10.622484 [Gating] SW calibration Done
1513 13:15:10.622994 ==
1514 13:15:10.625486 Dram Type= 6, Freq= 0, CH_1, rank 0
1515 13:15:10.628833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1516 13:15:10.629398 ==
1517 13:15:10.631803 RX Vref Scan: 0
1518 13:15:10.632231
1519 13:15:10.635294 RX Vref 0 -> 0, step: 1
1520 13:15:10.635841
1521 13:15:10.636196 RX Delay -130 -> 252, step: 16
1522 13:15:10.641983 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1523 13:15:10.644984 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1524 13:15:10.648876 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1525 13:15:10.651822 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1526 13:15:10.654992 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1527 13:15:10.662044 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1528 13:15:10.665225 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1529 13:15:10.668816 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1530 13:15:10.671996 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1531 13:15:10.675402 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1532 13:15:10.678662 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1533 13:15:10.685680 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1534 13:15:10.689041 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1535 13:15:10.692038 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1536 13:15:10.696017 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1537 13:15:10.698768 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1538 13:15:10.702951 ==
1539 13:15:10.705805 Dram Type= 6, Freq= 0, CH_1, rank 0
1540 13:15:10.708868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1541 13:15:10.708946 ==
1542 13:15:10.709005 DQS Delay:
1543 13:15:10.712199 DQS0 = 0, DQS1 = 0
1544 13:15:10.712277 DQM Delay:
1545 13:15:10.715788 DQM0 = 83, DQM1 = 76
1546 13:15:10.715864 DQ Delay:
1547 13:15:10.718952 DQ0 =93, DQ1 =69, DQ2 =69, DQ3 =85
1548 13:15:10.722406 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1549 13:15:10.725912 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1550 13:15:10.729396 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1551 13:15:10.729472
1552 13:15:10.729530
1553 13:15:10.729583 ==
1554 13:15:10.732299 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 13:15:10.735850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 13:15:10.735935 ==
1557 13:15:10.735995
1558 13:15:10.736049
1559 13:15:10.739344 TX Vref Scan disable
1560 13:15:10.739422 == TX Byte 0 ==
1561 13:15:10.746167 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1562 13:15:10.749223 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1563 13:15:10.749315 == TX Byte 1 ==
1564 13:15:10.756440 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1565 13:15:10.759664 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1566 13:15:10.759747 ==
1567 13:15:10.762947 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 13:15:10.766490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 13:15:10.766571 ==
1570 13:15:10.780197 TX Vref=22, minBit 0, minWin=27, winSum=435
1571 13:15:10.783189 TX Vref=24, minBit 3, minWin=27, winSum=442
1572 13:15:10.786798 TX Vref=26, minBit 0, minWin=27, winSum=445
1573 13:15:10.789910 TX Vref=28, minBit 11, minWin=27, winSum=451
1574 13:15:10.793511 TX Vref=30, minBit 0, minWin=28, winSum=452
1575 13:15:10.796450 TX Vref=32, minBit 2, minWin=28, winSum=456
1576 13:15:10.803223 [TxChooseVref] Worse bit 2, Min win 28, Win sum 456, Final Vref 32
1577 13:15:10.803322
1578 13:15:10.806762 Final TX Range 1 Vref 32
1579 13:15:10.806852
1580 13:15:10.806910 ==
1581 13:15:10.810184 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 13:15:10.813516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 13:15:10.813629 ==
1584 13:15:10.813692
1585 13:15:10.817017
1586 13:15:10.817218 TX Vref Scan disable
1587 13:15:10.820495 == TX Byte 0 ==
1588 13:15:10.823366 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1589 13:15:10.827003 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1590 13:15:10.830962 == TX Byte 1 ==
1591 13:15:10.833600 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1592 13:15:10.837531 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1593 13:15:10.837666
1594 13:15:10.840416 [DATLAT]
1595 13:15:10.840523 Freq=800, CH1 RK0
1596 13:15:10.840586
1597 13:15:10.843572 DATLAT Default: 0xa
1598 13:15:10.843696 0, 0xFFFF, sum = 0
1599 13:15:10.847348 1, 0xFFFF, sum = 0
1600 13:15:10.847492 2, 0xFFFF, sum = 0
1601 13:15:10.850474 3, 0xFFFF, sum = 0
1602 13:15:10.850638 4, 0xFFFF, sum = 0
1603 13:15:10.853460 5, 0xFFFF, sum = 0
1604 13:15:10.853570 6, 0xFFFF, sum = 0
1605 13:15:10.857001 7, 0xFFFF, sum = 0
1606 13:15:10.857138 8, 0xFFFF, sum = 0
1607 13:15:10.860538 9, 0x0, sum = 1
1608 13:15:10.860928 10, 0x0, sum = 2
1609 13:15:10.864226 11, 0x0, sum = 3
1610 13:15:10.864710 12, 0x0, sum = 4
1611 13:15:10.867470 best_step = 10
1612 13:15:10.867858
1613 13:15:10.868157 ==
1614 13:15:10.871455 Dram Type= 6, Freq= 0, CH_1, rank 0
1615 13:15:10.874012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1616 13:15:10.874657 ==
1617 13:15:10.877466 RX Vref Scan: 1
1618 13:15:10.877853
1619 13:15:10.878154 Set Vref Range= 32 -> 127
1620 13:15:10.878487
1621 13:15:10.880678 RX Vref 32 -> 127, step: 1
1622 13:15:10.881067
1623 13:15:10.884096 RX Delay -111 -> 252, step: 8
1624 13:15:10.884485
1625 13:15:10.887575 Set Vref, RX VrefLevel [Byte0]: 32
1626 13:15:10.890867 [Byte1]: 32
1627 13:15:10.891258
1628 13:15:10.894576 Set Vref, RX VrefLevel [Byte0]: 33
1629 13:15:10.897506 [Byte1]: 33
1630 13:15:10.900701
1631 13:15:10.901089 Set Vref, RX VrefLevel [Byte0]: 34
1632 13:15:10.905166 [Byte1]: 34
1633 13:15:10.908918
1634 13:15:10.909432 Set Vref, RX VrefLevel [Byte0]: 35
1635 13:15:10.912148 [Byte1]: 35
1636 13:15:10.916665
1637 13:15:10.917187 Set Vref, RX VrefLevel [Byte0]: 36
1638 13:15:10.919799 [Byte1]: 36
1639 13:15:10.924058
1640 13:15:10.924583 Set Vref, RX VrefLevel [Byte0]: 37
1641 13:15:10.927232 [Byte1]: 37
1642 13:15:10.931409
1643 13:15:10.931844 Set Vref, RX VrefLevel [Byte0]: 38
1644 13:15:10.935858 [Byte1]: 38
1645 13:15:10.938786
1646 13:15:10.939174 Set Vref, RX VrefLevel [Byte0]: 39
1647 13:15:10.942364 [Byte1]: 39
1648 13:15:10.946689
1649 13:15:10.947077 Set Vref, RX VrefLevel [Byte0]: 40
1650 13:15:10.950406 [Byte1]: 40
1651 13:15:10.954217
1652 13:15:10.954603 Set Vref, RX VrefLevel [Byte0]: 41
1653 13:15:10.958058 [Byte1]: 41
1654 13:15:10.961942
1655 13:15:10.962398 Set Vref, RX VrefLevel [Byte0]: 42
1656 13:15:10.965599 [Byte1]: 42
1657 13:15:10.969743
1658 13:15:10.970129 Set Vref, RX VrefLevel [Byte0]: 43
1659 13:15:10.972928 [Byte1]: 43
1660 13:15:10.977363
1661 13:15:10.977755 Set Vref, RX VrefLevel [Byte0]: 44
1662 13:15:10.980771 [Byte1]: 44
1663 13:15:10.985554
1664 13:15:10.985952 Set Vref, RX VrefLevel [Byte0]: 45
1665 13:15:10.988311 [Byte1]: 45
1666 13:15:10.992588
1667 13:15:10.992980 Set Vref, RX VrefLevel [Byte0]: 46
1668 13:15:10.996135 [Byte1]: 46
1669 13:15:11.000166
1670 13:15:11.000552 Set Vref, RX VrefLevel [Byte0]: 47
1671 13:15:11.003647 [Byte1]: 47
1672 13:15:11.007845
1673 13:15:11.008234 Set Vref, RX VrefLevel [Byte0]: 48
1674 13:15:11.011069 [Byte1]: 48
1675 13:15:11.015593
1676 13:15:11.015980 Set Vref, RX VrefLevel [Byte0]: 49
1677 13:15:11.018850 [Byte1]: 49
1678 13:15:11.023084
1679 13:15:11.023359 Set Vref, RX VrefLevel [Byte0]: 50
1680 13:15:11.026540 [Byte1]: 50
1681 13:15:11.030812
1682 13:15:11.031086 Set Vref, RX VrefLevel [Byte0]: 51
1683 13:15:11.034102 [Byte1]: 51
1684 13:15:11.038459
1685 13:15:11.038734 Set Vref, RX VrefLevel [Byte0]: 52
1686 13:15:11.041453 [Byte1]: 52
1687 13:15:11.045811
1688 13:15:11.046085 Set Vref, RX VrefLevel [Byte0]: 53
1689 13:15:11.049322 [Byte1]: 53
1690 13:15:11.053527
1691 13:15:11.053817 Set Vref, RX VrefLevel [Byte0]: 54
1692 13:15:11.057007 [Byte1]: 54
1693 13:15:11.061666
1694 13:15:11.062055 Set Vref, RX VrefLevel [Byte0]: 55
1695 13:15:11.064785 [Byte1]: 55
1696 13:15:11.069443
1697 13:15:11.069836 Set Vref, RX VrefLevel [Byte0]: 56
1698 13:15:11.072376 [Byte1]: 56
1699 13:15:11.076650
1700 13:15:11.077158 Set Vref, RX VrefLevel [Byte0]: 57
1701 13:15:11.080015 [Byte1]: 57
1702 13:15:11.084345
1703 13:15:11.084735 Set Vref, RX VrefLevel [Byte0]: 58
1704 13:15:11.087874 [Byte1]: 58
1705 13:15:11.092031
1706 13:15:11.092420 Set Vref, RX VrefLevel [Byte0]: 59
1707 13:15:11.095291 [Byte1]: 59
1708 13:15:11.099730
1709 13:15:11.100117 Set Vref, RX VrefLevel [Byte0]: 60
1710 13:15:11.103274 [Byte1]: 60
1711 13:15:11.107074
1712 13:15:11.107466 Set Vref, RX VrefLevel [Byte0]: 61
1713 13:15:11.110519 [Byte1]: 61
1714 13:15:11.114850
1715 13:15:11.115238 Set Vref, RX VrefLevel [Byte0]: 62
1716 13:15:11.118221 [Byte1]: 62
1717 13:15:11.122504
1718 13:15:11.122892 Set Vref, RX VrefLevel [Byte0]: 63
1719 13:15:11.125556 [Byte1]: 63
1720 13:15:11.129994
1721 13:15:11.130430 Set Vref, RX VrefLevel [Byte0]: 64
1722 13:15:11.133841 [Byte1]: 64
1723 13:15:11.137732
1724 13:15:11.138200 Set Vref, RX VrefLevel [Byte0]: 65
1725 13:15:11.141349 [Byte1]: 65
1726 13:15:11.145729
1727 13:15:11.146119 Set Vref, RX VrefLevel [Byte0]: 66
1728 13:15:11.149353 [Byte1]: 66
1729 13:15:11.153774
1730 13:15:11.154235 Set Vref, RX VrefLevel [Byte0]: 67
1731 13:15:11.156541 [Byte1]: 67
1732 13:15:11.161168
1733 13:15:11.161636 Set Vref, RX VrefLevel [Byte0]: 68
1734 13:15:11.164494 [Byte1]: 68
1735 13:15:11.168770
1736 13:15:11.169188 Set Vref, RX VrefLevel [Byte0]: 69
1737 13:15:11.171912 [Byte1]: 69
1738 13:15:11.176587
1739 13:15:11.177113 Set Vref, RX VrefLevel [Byte0]: 70
1740 13:15:11.179835 [Byte1]: 70
1741 13:15:11.183886
1742 13:15:11.184278 Set Vref, RX VrefLevel [Byte0]: 71
1743 13:15:11.187235 [Byte1]: 71
1744 13:15:11.191573
1745 13:15:11.192040 Set Vref, RX VrefLevel [Byte0]: 72
1746 13:15:11.194698 [Byte1]: 72
1747 13:15:11.198854
1748 13:15:11.199380 Set Vref, RX VrefLevel [Byte0]: 73
1749 13:15:11.202350 [Byte1]: 73
1750 13:15:11.206961
1751 13:15:11.207432 Set Vref, RX VrefLevel [Byte0]: 74
1752 13:15:11.210567 [Byte1]: 74
1753 13:15:11.214533
1754 13:15:11.215003 Set Vref, RX VrefLevel [Byte0]: 75
1755 13:15:11.217657 [Byte1]: 75
1756 13:15:11.222537
1757 13:15:11.223006 Set Vref, RX VrefLevel [Byte0]: 76
1758 13:15:11.225185 [Byte1]: 76
1759 13:15:11.230069
1760 13:15:11.230534 Set Vref, RX VrefLevel [Byte0]: 77
1761 13:15:11.233293 [Byte1]: 77
1762 13:15:11.236922
1763 13:15:11.237363 Set Vref, RX VrefLevel [Byte0]: 78
1764 13:15:11.240831 [Byte1]: 78
1765 13:15:11.245100
1766 13:15:11.245599 Set Vref, RX VrefLevel [Byte0]: 79
1767 13:15:11.248633 [Byte1]: 79
1768 13:15:11.252665
1769 13:15:11.253201 Final RX Vref Byte 0 = 61 to rank0
1770 13:15:11.256469 Final RX Vref Byte 1 = 59 to rank0
1771 13:15:11.259560 Final RX Vref Byte 0 = 61 to rank1
1772 13:15:11.262774 Final RX Vref Byte 1 = 59 to rank1==
1773 13:15:11.266436 Dram Type= 6, Freq= 0, CH_1, rank 0
1774 13:15:11.273167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1775 13:15:11.273689 ==
1776 13:15:11.274023 DQS Delay:
1777 13:15:11.274328 DQS0 = 0, DQS1 = 0
1778 13:15:11.275841 DQM Delay:
1779 13:15:11.276270 DQM0 = 84, DQM1 = 73
1780 13:15:11.279586 DQ Delay:
1781 13:15:11.282601 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =84
1782 13:15:11.283033 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1783 13:15:11.286331 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1784 13:15:11.289550 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =76
1785 13:15:11.290063
1786 13:15:11.293520
1787 13:15:11.299531 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c00, (MSB)MR19= 0x606, tDQSOscB0 = 410 ps tDQSOscB1 = 398 ps
1788 13:15:11.302641 CH1 RK0: MR19=606, MR18=2C00
1789 13:15:11.309647 CH1_RK0: MR19=0x606, MR18=0x2C00, DQSOSC=398, MR23=63, INC=93, DEC=62
1790 13:15:11.310115
1791 13:15:11.312976 ----->DramcWriteLeveling(PI) begin...
1792 13:15:11.313408 ==
1793 13:15:11.316579 Dram Type= 6, Freq= 0, CH_1, rank 1
1794 13:15:11.319781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1795 13:15:11.320263 ==
1796 13:15:11.322986 Write leveling (Byte 0): 29 => 29
1797 13:15:11.326097 Write leveling (Byte 1): 30 => 30
1798 13:15:11.329861 DramcWriteLeveling(PI) end<-----
1799 13:15:11.330248
1800 13:15:11.330546 ==
1801 13:15:11.333828 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 13:15:11.336862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 13:15:11.337395 ==
1804 13:15:11.339779 [Gating] SW mode calibration
1805 13:15:11.346535 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1806 13:15:11.353371 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1807 13:15:11.356813 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1808 13:15:11.359980 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1809 13:15:11.363401 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1810 13:15:11.369991 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 13:15:11.373886 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 13:15:11.377036 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 13:15:11.383797 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 13:15:11.386808 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 13:15:11.390447 0 7 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1816 13:15:11.396573 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 13:15:11.399865 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 13:15:11.403327 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1819 13:15:11.410512 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 13:15:11.413142 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1821 13:15:11.416454 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 13:15:11.420340 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 13:15:11.426642 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1824 13:15:11.429886 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1825 13:15:11.433693 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 13:15:11.440028 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 13:15:11.443239 0 8 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1828 13:15:11.446852 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 13:15:11.453351 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 13:15:11.456757 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 13:15:11.460214 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 13:15:11.466991 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1833 13:15:11.470736 0 9 8 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
1834 13:15:11.473412 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 13:15:11.477160 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 13:15:11.483531 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 13:15:11.487012 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 13:15:11.490363 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 13:15:11.497432 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 13:15:11.500492 0 10 4 | B1->B0 | 3030 2b2b | 0 0 | (0 1) (1 1)
1841 13:15:11.503790 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
1842 13:15:11.510310 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 13:15:11.513641 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 13:15:11.517035 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 13:15:11.524062 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 13:15:11.527478 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 13:15:11.530785 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 13:15:11.534203 0 11 4 | B1->B0 | 2c2c 3939 | 1 0 | (0 0) (0 0)
1849 13:15:11.540568 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1850 13:15:11.544304 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 13:15:11.547720 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 13:15:11.554143 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 13:15:11.557707 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 13:15:11.561192 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 13:15:11.567626 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 13:15:11.570810 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1857 13:15:11.574586 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 13:15:11.581242 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 13:15:11.584381 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 13:15:11.588186 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 13:15:11.591270 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 13:15:11.598054 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 13:15:11.601452 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 13:15:11.604759 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 13:15:11.611432 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 13:15:11.614801 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 13:15:11.618460 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 13:15:11.625003 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 13:15:11.628292 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 13:15:11.631985 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 13:15:11.638918 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 13:15:11.641631 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1873 13:15:11.645143 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1874 13:15:11.648548 Total UI for P1: 0, mck2ui 16
1875 13:15:11.651890 best dqsien dly found for B0: ( 0, 14, 4)
1876 13:15:11.655218 Total UI for P1: 0, mck2ui 16
1877 13:15:11.658453 best dqsien dly found for B1: ( 0, 14, 6)
1878 13:15:11.662111 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1879 13:15:11.665290 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1880 13:15:11.665367
1881 13:15:11.668944 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1882 13:15:11.671823 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1883 13:15:11.675231 [Gating] SW calibration Done
1884 13:15:11.675348 ==
1885 13:15:11.678525 Dram Type= 6, Freq= 0, CH_1, rank 1
1886 13:15:11.681955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1887 13:15:11.685436 ==
1888 13:15:11.685543 RX Vref Scan: 0
1889 13:15:11.685604
1890 13:15:11.688712 RX Vref 0 -> 0, step: 1
1891 13:15:11.688788
1892 13:15:11.691873 RX Delay -130 -> 252, step: 16
1893 13:15:11.695011 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1894 13:15:11.698448 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1895 13:15:11.701598 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1896 13:15:11.705062 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1897 13:15:11.712310 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1898 13:15:11.715168 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1899 13:15:11.718556 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1900 13:15:11.722178 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1901 13:15:11.725435 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1902 13:15:11.728375 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1903 13:15:11.735476 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1904 13:15:11.738785 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1905 13:15:11.742320 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1906 13:15:11.745685 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1907 13:15:11.748529 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1908 13:15:11.755217 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1909 13:15:11.755297 ==
1910 13:15:11.759035 Dram Type= 6, Freq= 0, CH_1, rank 1
1911 13:15:11.761973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1912 13:15:11.762051 ==
1913 13:15:11.762110 DQS Delay:
1914 13:15:11.765611 DQS0 = 0, DQS1 = 0
1915 13:15:11.765688 DQM Delay:
1916 13:15:11.768674 DQM0 = 82, DQM1 = 78
1917 13:15:11.768750 DQ Delay:
1918 13:15:11.772381 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1919 13:15:11.775253 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1920 13:15:11.778497 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1921 13:15:11.782163 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1922 13:15:11.782239
1923 13:15:11.782297
1924 13:15:11.782351 ==
1925 13:15:11.785862 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 13:15:11.788797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 13:15:11.788880 ==
1928 13:15:11.792719
1929 13:15:11.792856
1930 13:15:11.792920 TX Vref Scan disable
1931 13:15:11.795238 == TX Byte 0 ==
1932 13:15:11.798751 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1933 13:15:11.802355 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1934 13:15:11.805429 == TX Byte 1 ==
1935 13:15:11.808826 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1936 13:15:11.812878 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1937 13:15:11.813018 ==
1938 13:15:11.815901 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 13:15:11.821894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 13:15:11.822007 ==
1941 13:15:11.833978 TX Vref=22, minBit 8, minWin=27, winSum=445
1942 13:15:11.837927 TX Vref=24, minBit 3, minWin=27, winSum=443
1943 13:15:11.840844 TX Vref=26, minBit 12, minWin=27, winSum=450
1944 13:15:11.844382 TX Vref=28, minBit 0, minWin=28, winSum=452
1945 13:15:11.847115 TX Vref=30, minBit 0, minWin=28, winSum=455
1946 13:15:11.850539 TX Vref=32, minBit 0, minWin=28, winSum=453
1947 13:15:11.857482 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
1948 13:15:11.857607
1949 13:15:11.860505 Final TX Range 1 Vref 30
1950 13:15:11.860595
1951 13:15:11.860669 ==
1952 13:15:11.863882 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 13:15:11.867620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 13:15:11.867736 ==
1955 13:15:11.867812
1956 13:15:11.867898
1957 13:15:11.871116 TX Vref Scan disable
1958 13:15:11.874146 == TX Byte 0 ==
1959 13:15:11.877415 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1960 13:15:11.880779 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1961 13:15:11.884061 == TX Byte 1 ==
1962 13:15:11.887521 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1963 13:15:11.890857 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1964 13:15:11.890957
1965 13:15:11.894333 [DATLAT]
1966 13:15:11.894422 Freq=800, CH1 RK1
1967 13:15:11.894482
1968 13:15:11.897808 DATLAT Default: 0xa
1969 13:15:11.897918 0, 0xFFFF, sum = 0
1970 13:15:11.900979 1, 0xFFFF, sum = 0
1971 13:15:11.901089 2, 0xFFFF, sum = 0
1972 13:15:11.904081 3, 0xFFFF, sum = 0
1973 13:15:11.904186 4, 0xFFFF, sum = 0
1974 13:15:11.907836 5, 0xFFFF, sum = 0
1975 13:15:11.907923 6, 0xFFFF, sum = 0
1976 13:15:11.910830 7, 0xFFFF, sum = 0
1977 13:15:11.910919 8, 0xFFFF, sum = 0
1978 13:15:11.914674 9, 0x0, sum = 1
1979 13:15:11.914788 10, 0x0, sum = 2
1980 13:15:11.917682 11, 0x0, sum = 3
1981 13:15:11.917769 12, 0x0, sum = 4
1982 13:15:11.921030 best_step = 10
1983 13:15:11.921145
1984 13:15:11.921209 ==
1985 13:15:11.924350 Dram Type= 6, Freq= 0, CH_1, rank 1
1986 13:15:11.927997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1987 13:15:11.928098 ==
1988 13:15:11.928158 RX Vref Scan: 0
1989 13:15:11.931083
1990 13:15:11.931163 RX Vref 0 -> 0, step: 1
1991 13:15:11.931224
1992 13:15:11.934810 RX Delay -95 -> 252, step: 8
1993 13:15:11.937925 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1994 13:15:11.944250 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1995 13:15:11.947745 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
1996 13:15:11.951021 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
1997 13:15:11.954784 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1998 13:15:11.958050 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
1999 13:15:11.964820 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2000 13:15:11.968083 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2001 13:15:11.971661 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
2002 13:15:11.974975 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2003 13:15:11.977996 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2004 13:15:11.981608 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2005 13:15:11.988650 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
2006 13:15:11.992230 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2007 13:15:11.995091 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2008 13:15:11.998159 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2009 13:15:11.998253 ==
2010 13:15:12.001710 Dram Type= 6, Freq= 0, CH_1, rank 1
2011 13:15:12.008185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2012 13:15:12.008315 ==
2013 13:15:12.008381 DQS Delay:
2014 13:15:12.008437 DQS0 = 0, DQS1 = 0
2015 13:15:12.012104 DQM Delay:
2016 13:15:12.012191 DQM0 = 80, DQM1 = 76
2017 13:15:12.015372 DQ Delay:
2018 13:15:12.018835 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2019 13:15:12.018935 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2020 13:15:12.021838 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
2021 13:15:12.025158 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
2022 13:15:12.029040
2023 13:15:12.029159
2024 13:15:12.035138 [DQSOSCAuto] RK1, (LSB)MR18= 0x2833, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
2025 13:15:12.038800 CH1 RK1: MR19=606, MR18=2833
2026 13:15:12.045668 CH1_RK1: MR19=0x606, MR18=0x2833, DQSOSC=396, MR23=63, INC=94, DEC=62
2027 13:15:12.045772 [RxdqsGatingPostProcess] freq 800
2028 13:15:12.052442 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2029 13:15:12.055419 Pre-setting of DQS Precalculation
2030 13:15:12.059033 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2031 13:15:12.069048 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2032 13:15:12.075512 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2033 13:15:12.075627
2034 13:15:12.075711
2035 13:15:12.078861 [Calibration Summary] 1600 Mbps
2036 13:15:12.078949 CH 0, Rank 0
2037 13:15:12.082118 SW Impedance : PASS
2038 13:15:12.082201 DUTY Scan : NO K
2039 13:15:12.085859 ZQ Calibration : PASS
2040 13:15:12.088974 Jitter Meter : NO K
2041 13:15:12.089082 CBT Training : PASS
2042 13:15:12.093052 Write leveling : PASS
2043 13:15:12.095903 RX DQS gating : PASS
2044 13:15:12.095992 RX DQ/DQS(RDDQC) : PASS
2045 13:15:12.099310 TX DQ/DQS : PASS
2046 13:15:12.099398 RX DATLAT : PASS
2047 13:15:12.102468 RX DQ/DQS(Engine): PASS
2048 13:15:12.105789 TX OE : NO K
2049 13:15:12.105915 All Pass.
2050 13:15:12.106000
2051 13:15:12.106082 CH 0, Rank 1
2052 13:15:12.109102 SW Impedance : PASS
2053 13:15:12.113210 DUTY Scan : NO K
2054 13:15:12.113289 ZQ Calibration : PASS
2055 13:15:12.115971 Jitter Meter : NO K
2056 13:15:12.119238 CBT Training : PASS
2057 13:15:12.119339 Write leveling : PASS
2058 13:15:12.123033 RX DQS gating : PASS
2059 13:15:12.125860 RX DQ/DQS(RDDQC) : PASS
2060 13:15:12.125939 TX DQ/DQS : PASS
2061 13:15:12.129210 RX DATLAT : PASS
2062 13:15:12.132515 RX DQ/DQS(Engine): PASS
2063 13:15:12.132620 TX OE : NO K
2064 13:15:12.132705 All Pass.
2065 13:15:12.136028
2066 13:15:12.136127 CH 1, Rank 0
2067 13:15:12.139696 SW Impedance : PASS
2068 13:15:12.139842 DUTY Scan : NO K
2069 13:15:12.142805 ZQ Calibration : PASS
2070 13:15:12.142894 Jitter Meter : NO K
2071 13:15:12.145831 CBT Training : PASS
2072 13:15:12.149240 Write leveling : PASS
2073 13:15:12.149328 RX DQS gating : PASS
2074 13:15:12.152748 RX DQ/DQS(RDDQC) : PASS
2075 13:15:12.155982 TX DQ/DQS : PASS
2076 13:15:12.156088 RX DATLAT : PASS
2077 13:15:12.159445 RX DQ/DQS(Engine): PASS
2078 13:15:12.162973 TX OE : NO K
2079 13:15:12.163065 All Pass.
2080 13:15:12.163125
2081 13:15:12.163180 CH 1, Rank 1
2082 13:15:12.166314 SW Impedance : PASS
2083 13:15:12.169408 DUTY Scan : NO K
2084 13:15:12.169493 ZQ Calibration : PASS
2085 13:15:12.173020 Jitter Meter : NO K
2086 13:15:12.173109 CBT Training : PASS
2087 13:15:12.176391 Write leveling : PASS
2088 13:15:12.180090 RX DQS gating : PASS
2089 13:15:12.180182 RX DQ/DQS(RDDQC) : PASS
2090 13:15:12.183154 TX DQ/DQS : PASS
2091 13:15:12.186666 RX DATLAT : PASS
2092 13:15:12.186760 RX DQ/DQS(Engine): PASS
2093 13:15:12.189693 TX OE : NO K
2094 13:15:12.189782 All Pass.
2095 13:15:12.189841
2096 13:15:12.193542 DramC Write-DBI off
2097 13:15:12.196317 PER_BANK_REFRESH: Hybrid Mode
2098 13:15:12.196405 TX_TRACKING: ON
2099 13:15:12.199599 [GetDramInforAfterCalByMRR] Vendor 6.
2100 13:15:12.203245 [GetDramInforAfterCalByMRR] Revision 606.
2101 13:15:12.206744 [GetDramInforAfterCalByMRR] Revision 2 0.
2102 13:15:12.209733 MR0 0x3b3b
2103 13:15:12.209828 MR8 0x5151
2104 13:15:12.213315 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2105 13:15:12.213405
2106 13:15:12.213465 MR0 0x3b3b
2107 13:15:12.216644 MR8 0x5151
2108 13:15:12.220214 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2109 13:15:12.220313
2110 13:15:12.230134 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2111 13:15:12.233294 [FAST_K] Save calibration result to emmc
2112 13:15:12.236428 [FAST_K] Save calibration result to emmc
2113 13:15:12.236542 dram_init: config_dvfs: 1
2114 13:15:12.243831 dramc_set_vcore_voltage set vcore to 662500
2115 13:15:12.243960 Read voltage for 1200, 2
2116 13:15:12.244082 Vio18 = 0
2117 13:15:12.247414 Vcore = 662500
2118 13:15:12.247500 Vdram = 0
2119 13:15:12.247598 Vddq = 0
2120 13:15:12.249925 Vmddr = 0
2121 13:15:12.253565 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2122 13:15:12.259906 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2123 13:15:12.260027 MEM_TYPE=3, freq_sel=15
2124 13:15:12.263192 sv_algorithm_assistance_LP4_1600
2125 13:15:12.269900 ============ PULL DRAM RESETB DOWN ============
2126 13:15:12.273736 ========== PULL DRAM RESETB DOWN end =========
2127 13:15:12.277392 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2128 13:15:12.280070 ===================================
2129 13:15:12.283836 LPDDR4 DRAM CONFIGURATION
2130 13:15:12.287134 ===================================
2131 13:15:12.287274 EX_ROW_EN[0] = 0x0
2132 13:15:12.290555 EX_ROW_EN[1] = 0x0
2133 13:15:12.293872 LP4Y_EN = 0x0
2134 13:15:12.293966 WORK_FSP = 0x0
2135 13:15:12.296909 WL = 0x4
2136 13:15:12.297037 RL = 0x4
2137 13:15:12.300414 BL = 0x2
2138 13:15:12.300506 RPST = 0x0
2139 13:15:12.303608 RD_PRE = 0x0
2140 13:15:12.303712 WR_PRE = 0x1
2141 13:15:12.307098 WR_PST = 0x0
2142 13:15:12.307191 DBI_WR = 0x0
2143 13:15:12.310733 DBI_RD = 0x0
2144 13:15:12.310856 OTF = 0x1
2145 13:15:12.313899 ===================================
2146 13:15:12.317036 ===================================
2147 13:15:12.320310 ANA top config
2148 13:15:12.324006 ===================================
2149 13:15:12.324102 DLL_ASYNC_EN = 0
2150 13:15:12.327237 ALL_SLAVE_EN = 0
2151 13:15:12.330514 NEW_RANK_MODE = 1
2152 13:15:12.334331 DLL_IDLE_MODE = 1
2153 13:15:12.334430 LP45_APHY_COMB_EN = 1
2154 13:15:12.337384 TX_ODT_DIS = 1
2155 13:15:12.340436 NEW_8X_MODE = 1
2156 13:15:12.344218 ===================================
2157 13:15:12.347361 ===================================
2158 13:15:12.350892 data_rate = 2400
2159 13:15:12.354465 CKR = 1
2160 13:15:12.354561 DQ_P2S_RATIO = 8
2161 13:15:12.357696 ===================================
2162 13:15:12.360749 CA_P2S_RATIO = 8
2163 13:15:12.364110 DQ_CA_OPEN = 0
2164 13:15:12.367727 DQ_SEMI_OPEN = 0
2165 13:15:12.370977 CA_SEMI_OPEN = 0
2166 13:15:12.371067 CA_FULL_RATE = 0
2167 13:15:12.374218 DQ_CKDIV4_EN = 0
2168 13:15:12.377747 CA_CKDIV4_EN = 0
2169 13:15:12.381722 CA_PREDIV_EN = 0
2170 13:15:12.384513 PH8_DLY = 17
2171 13:15:12.387559 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2172 13:15:12.387663 DQ_AAMCK_DIV = 4
2173 13:15:12.390893 CA_AAMCK_DIV = 4
2174 13:15:12.394683 CA_ADMCK_DIV = 4
2175 13:15:12.397955 DQ_TRACK_CA_EN = 0
2176 13:15:12.401114 CA_PICK = 1200
2177 13:15:12.404827 CA_MCKIO = 1200
2178 13:15:12.408575 MCKIO_SEMI = 0
2179 13:15:12.408668 PLL_FREQ = 2366
2180 13:15:12.411041 DQ_UI_PI_RATIO = 32
2181 13:15:12.414519 CA_UI_PI_RATIO = 0
2182 13:15:12.418095 ===================================
2183 13:15:12.421274 ===================================
2184 13:15:12.424638 memory_type:LPDDR4
2185 13:15:12.424722 GP_NUM : 10
2186 13:15:12.428221 SRAM_EN : 1
2187 13:15:12.431393 MD32_EN : 0
2188 13:15:12.434579 ===================================
2189 13:15:12.434662 [ANA_INIT] >>>>>>>>>>>>>>
2190 13:15:12.438170 <<<<<< [CONFIGURE PHASE]: ANA_TX
2191 13:15:12.441698 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2192 13:15:12.445011 ===================================
2193 13:15:12.448302 data_rate = 2400,PCW = 0X5b00
2194 13:15:12.451301 ===================================
2195 13:15:12.454814 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2196 13:15:12.461379 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2197 13:15:12.464907 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2198 13:15:12.471671 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2199 13:15:12.475780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2200 13:15:12.478129 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2201 13:15:12.478213 [ANA_INIT] flow start
2202 13:15:12.481653 [ANA_INIT] PLL >>>>>>>>
2203 13:15:12.485456 [ANA_INIT] PLL <<<<<<<<
2204 13:15:12.485548 [ANA_INIT] MIDPI >>>>>>>>
2205 13:15:12.488725 [ANA_INIT] MIDPI <<<<<<<<
2206 13:15:12.492034 [ANA_INIT] DLL >>>>>>>>
2207 13:15:12.492122 [ANA_INIT] DLL <<<<<<<<
2208 13:15:12.494985 [ANA_INIT] flow end
2209 13:15:12.498810 ============ LP4 DIFF to SE enter ============
2210 13:15:12.501603 ============ LP4 DIFF to SE exit ============
2211 13:15:12.505300 [ANA_INIT] <<<<<<<<<<<<<
2212 13:15:12.509062 [Flow] Enable top DCM control >>>>>
2213 13:15:12.511970 [Flow] Enable top DCM control <<<<<
2214 13:15:12.515239 Enable DLL master slave shuffle
2215 13:15:12.522441 ==============================================================
2216 13:15:12.522548 Gating Mode config
2217 13:15:12.528379 ==============================================================
2218 13:15:12.528506 Config description:
2219 13:15:12.538542 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2220 13:15:12.545376 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2221 13:15:12.551822 SELPH_MODE 0: By rank 1: By Phase
2222 13:15:12.555246 ==============================================================
2223 13:15:12.558694 GAT_TRACK_EN = 1
2224 13:15:12.561932 RX_GATING_MODE = 2
2225 13:15:12.565712 RX_GATING_TRACK_MODE = 2
2226 13:15:12.568963 SELPH_MODE = 1
2227 13:15:12.572095 PICG_EARLY_EN = 1
2228 13:15:12.575841 VALID_LAT_VALUE = 1
2229 13:15:12.579039 ==============================================================
2230 13:15:12.582034 Enter into Gating configuration >>>>
2231 13:15:12.585370 Exit from Gating configuration <<<<
2232 13:15:12.588883 Enter into DVFS_PRE_config >>>>>
2233 13:15:12.602305 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2234 13:15:12.602435 Exit from DVFS_PRE_config <<<<<
2235 13:15:12.605973 Enter into PICG configuration >>>>
2236 13:15:12.608868 Exit from PICG configuration <<<<
2237 13:15:12.612208 [RX_INPUT] configuration >>>>>
2238 13:15:12.615986 [RX_INPUT] configuration <<<<<
2239 13:15:12.622614 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2240 13:15:12.625725 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2241 13:15:12.632439 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2242 13:15:12.639239 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2243 13:15:12.646061 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2244 13:15:12.652519 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2245 13:15:12.656762 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2246 13:15:12.659510 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2247 13:15:12.662656 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2248 13:15:12.666146 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2249 13:15:12.673008 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2250 13:15:12.676737 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2251 13:15:12.680090 ===================================
2252 13:15:12.683338 LPDDR4 DRAM CONFIGURATION
2253 13:15:12.686793 ===================================
2254 13:15:12.686893 EX_ROW_EN[0] = 0x0
2255 13:15:12.690086 EX_ROW_EN[1] = 0x0
2256 13:15:12.690185 LP4Y_EN = 0x0
2257 13:15:12.693016 WORK_FSP = 0x0
2258 13:15:12.693150 WL = 0x4
2259 13:15:12.696395 RL = 0x4
2260 13:15:12.696514 BL = 0x2
2261 13:15:12.699766 RPST = 0x0
2262 13:15:12.699870 RD_PRE = 0x0
2263 13:15:12.702842 WR_PRE = 0x1
2264 13:15:12.702945 WR_PST = 0x0
2265 13:15:12.706449 DBI_WR = 0x0
2266 13:15:12.706568 DBI_RD = 0x0
2267 13:15:12.709751 OTF = 0x1
2268 13:15:12.713321 ===================================
2269 13:15:12.716910 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2270 13:15:12.720230 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2271 13:15:12.726570 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2272 13:15:12.730092 ===================================
2273 13:15:12.730211 LPDDR4 DRAM CONFIGURATION
2274 13:15:12.733226 ===================================
2275 13:15:12.736944 EX_ROW_EN[0] = 0x10
2276 13:15:12.737050 EX_ROW_EN[1] = 0x0
2277 13:15:12.739976 LP4Y_EN = 0x0
2278 13:15:12.740074 WORK_FSP = 0x0
2279 13:15:12.743200 WL = 0x4
2280 13:15:12.746703 RL = 0x4
2281 13:15:12.746804 BL = 0x2
2282 13:15:12.750187 RPST = 0x0
2283 13:15:12.750338 RD_PRE = 0x0
2284 13:15:12.753870 WR_PRE = 0x1
2285 13:15:12.753987 WR_PST = 0x0
2286 13:15:12.757547 DBI_WR = 0x0
2287 13:15:12.757655 DBI_RD = 0x0
2288 13:15:12.760199 OTF = 0x1
2289 13:15:12.763584 ===================================
2290 13:15:12.767288 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2291 13:15:12.770702 ==
2292 13:15:12.770815 Dram Type= 6, Freq= 0, CH_0, rank 0
2293 13:15:12.776971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2294 13:15:12.777101 ==
2295 13:15:12.780605 [Duty_Offset_Calibration]
2296 13:15:12.780706 B0:2 B1:-1 CA:1
2297 13:15:12.780784
2298 13:15:12.783976 [DutyScan_Calibration_Flow] k_type=0
2299 13:15:12.792169
2300 13:15:12.792313 ==CLK 0==
2301 13:15:12.796038 Final CLK duty delay cell = -4
2302 13:15:12.799027 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2303 13:15:12.802111 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2304 13:15:12.805517 [-4] AVG Duty = 4937%(X100)
2305 13:15:12.805633
2306 13:15:12.809017 CH0 CLK Duty spec in!! Max-Min= 125%
2307 13:15:12.812294 [DutyScan_Calibration_Flow] ====Done====
2308 13:15:12.812398
2309 13:15:12.815698 [DutyScan_Calibration_Flow] k_type=1
2310 13:15:12.831543
2311 13:15:12.831694 ==DQS 0 ==
2312 13:15:12.834747 Final DQS duty delay cell = 0
2313 13:15:12.838091 [0] MAX Duty = 5125%(X100), DQS PI = 46
2314 13:15:12.841280 [0] MIN Duty = 5000%(X100), DQS PI = 12
2315 13:15:12.841389 [0] AVG Duty = 5062%(X100)
2316 13:15:12.844960
2317 13:15:12.845058 ==DQS 1 ==
2318 13:15:12.848319 Final DQS duty delay cell = -4
2319 13:15:12.851684 [-4] MAX Duty = 5124%(X100), DQS PI = 18
2320 13:15:12.854809 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2321 13:15:12.858247 [-4] AVG Duty = 5062%(X100)
2322 13:15:12.858361
2323 13:15:12.861242 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2324 13:15:12.861347
2325 13:15:12.864644 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2326 13:15:12.868094 [DutyScan_Calibration_Flow] ====Done====
2327 13:15:12.868209
2328 13:15:12.871626 [DutyScan_Calibration_Flow] k_type=3
2329 13:15:12.888084
2330 13:15:12.888237 ==DQM 0 ==
2331 13:15:12.891589 Final DQM duty delay cell = 0
2332 13:15:12.894633 [0] MAX Duty = 5000%(X100), DQS PI = 54
2333 13:15:12.898416 [0] MIN Duty = 4875%(X100), DQS PI = 4
2334 13:15:12.898533 [0] AVG Duty = 4937%(X100)
2335 13:15:12.901410
2336 13:15:12.901521 ==DQM 1 ==
2337 13:15:12.905354 Final DQM duty delay cell = 0
2338 13:15:12.907923 [0] MAX Duty = 5124%(X100), DQS PI = 32
2339 13:15:12.911447 [0] MIN Duty = 4969%(X100), DQS PI = 56
2340 13:15:12.911554 [0] AVG Duty = 5046%(X100)
2341 13:15:12.911637
2342 13:15:12.918168 CH0 DQM 0 Duty spec in!! Max-Min= 125%
2343 13:15:12.918291
2344 13:15:12.921894 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2345 13:15:12.925309 [DutyScan_Calibration_Flow] ====Done====
2346 13:15:12.925413
2347 13:15:12.928530 [DutyScan_Calibration_Flow] k_type=2
2348 13:15:12.944396
2349 13:15:12.944525 ==DQ 0 ==
2350 13:15:12.947293 Final DQ duty delay cell = -4
2351 13:15:12.951075 [-4] MAX Duty = 5031%(X100), DQS PI = 0
2352 13:15:12.953882 [-4] MIN Duty = 4844%(X100), DQS PI = 12
2353 13:15:12.954002 [-4] AVG Duty = 4937%(X100)
2354 13:15:12.957423
2355 13:15:12.957530 ==DQ 1 ==
2356 13:15:12.960555 Final DQ duty delay cell = 0
2357 13:15:12.964427 [0] MAX Duty = 5031%(X100), DQS PI = 18
2358 13:15:12.967223 [0] MIN Duty = 4907%(X100), DQS PI = 46
2359 13:15:12.967329 [0] AVG Duty = 4969%(X100)
2360 13:15:12.967441
2361 13:15:12.971148 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2362 13:15:12.974093
2363 13:15:12.977019 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2364 13:15:12.980764 [DutyScan_Calibration_Flow] ====Done====
2365 13:15:12.980875 ==
2366 13:15:12.984148 Dram Type= 6, Freq= 0, CH_1, rank 0
2367 13:15:12.987256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2368 13:15:12.987371 ==
2369 13:15:12.990695 [Duty_Offset_Calibration]
2370 13:15:12.990808 B0:1 B1:1 CA:2
2371 13:15:12.990892
2372 13:15:12.994079 [DutyScan_Calibration_Flow] k_type=0
2373 13:15:13.004205
2374 13:15:13.004355 ==CLK 0==
2375 13:15:13.007496 Final CLK duty delay cell = 0
2376 13:15:13.010687 [0] MAX Duty = 5156%(X100), DQS PI = 24
2377 13:15:13.014279 [0] MIN Duty = 4969%(X100), DQS PI = 40
2378 13:15:13.014390 [0] AVG Duty = 5062%(X100)
2379 13:15:13.017603
2380 13:15:13.017712 CH1 CLK Duty spec in!! Max-Min= 187%
2381 13:15:13.024069 [DutyScan_Calibration_Flow] ====Done====
2382 13:15:13.024199
2383 13:15:13.027193 [DutyScan_Calibration_Flow] k_type=1
2384 13:15:13.043581
2385 13:15:13.043742 ==DQS 0 ==
2386 13:15:13.046857 Final DQS duty delay cell = 0
2387 13:15:13.050180 [0] MAX Duty = 5031%(X100), DQS PI = 18
2388 13:15:13.053453 [0] MIN Duty = 4813%(X100), DQS PI = 50
2389 13:15:13.053571 [0] AVG Duty = 4922%(X100)
2390 13:15:13.053651
2391 13:15:13.056821 ==DQS 1 ==
2392 13:15:13.060257 Final DQS duty delay cell = 0
2393 13:15:13.063730 [0] MAX Duty = 5062%(X100), DQS PI = 36
2394 13:15:13.067215 [0] MIN Duty = 4906%(X100), DQS PI = 16
2395 13:15:13.067329 [0] AVG Duty = 4984%(X100)
2396 13:15:13.067407
2397 13:15:13.070462 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2398 13:15:13.073917
2399 13:15:13.076842 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2400 13:15:13.080477 [DutyScan_Calibration_Flow] ====Done====
2401 13:15:13.080594
2402 13:15:13.083530 [DutyScan_Calibration_Flow] k_type=3
2403 13:15:13.100027
2404 13:15:13.100194 ==DQM 0 ==
2405 13:15:13.103704 Final DQM duty delay cell = 0
2406 13:15:13.106808 [0] MAX Duty = 5093%(X100), DQS PI = 18
2407 13:15:13.110024 [0] MIN Duty = 4907%(X100), DQS PI = 48
2408 13:15:13.110148 [0] AVG Duty = 5000%(X100)
2409 13:15:13.113277
2410 13:15:13.113378 ==DQM 1 ==
2411 13:15:13.116729 Final DQM duty delay cell = 0
2412 13:15:13.120195 [0] MAX Duty = 5125%(X100), DQS PI = 0
2413 13:15:13.123376 [0] MIN Duty = 4938%(X100), DQS PI = 22
2414 13:15:13.123482 [0] AVG Duty = 5031%(X100)
2415 13:15:13.123575
2416 13:15:13.127040 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2417 13:15:13.130262
2418 13:15:13.133647 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2419 13:15:13.136782 [DutyScan_Calibration_Flow] ====Done====
2420 13:15:13.136877
2421 13:15:13.140191 [DutyScan_Calibration_Flow] k_type=2
2422 13:15:13.156607
2423 13:15:13.156763 ==DQ 0 ==
2424 13:15:13.159797 Final DQ duty delay cell = 0
2425 13:15:13.163115 [0] MAX Duty = 5124%(X100), DQS PI = 18
2426 13:15:13.166901 [0] MIN Duty = 4907%(X100), DQS PI = 50
2427 13:15:13.167009 [0] AVG Duty = 5015%(X100)
2428 13:15:13.167098
2429 13:15:13.169710 ==DQ 1 ==
2430 13:15:13.173325 Final DQ duty delay cell = 0
2431 13:15:13.176540 [0] MAX Duty = 5093%(X100), DQS PI = 10
2432 13:15:13.180139 [0] MIN Duty = 5031%(X100), DQS PI = 2
2433 13:15:13.180238 [0] AVG Duty = 5062%(X100)
2434 13:15:13.180327
2435 13:15:13.183388 CH1 DQ 0 Duty spec in!! Max-Min= 217%
2436 13:15:13.183487
2437 13:15:13.186807 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2438 13:15:13.193358 [DutyScan_Calibration_Flow] ====Done====
2439 13:15:13.196688 nWR fixed to 30
2440 13:15:13.196813 [ModeRegInit_LP4] CH0 RK0
2441 13:15:13.200273 [ModeRegInit_LP4] CH0 RK1
2442 13:15:13.203492 [ModeRegInit_LP4] CH1 RK0
2443 13:15:13.203597 [ModeRegInit_LP4] CH1 RK1
2444 13:15:13.207013 match AC timing 7
2445 13:15:13.210444 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2446 13:15:13.213681 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2447 13:15:13.219849 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2448 13:15:13.223491 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2449 13:15:13.230003 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2450 13:15:13.230143 ==
2451 13:15:13.233302 Dram Type= 6, Freq= 0, CH_0, rank 0
2452 13:15:13.237065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2453 13:15:13.237209 ==
2454 13:15:13.243489 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2455 13:15:13.246827 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2456 13:15:13.256512 [CA 0] Center 40 (10~71) winsize 62
2457 13:15:13.259506 [CA 1] Center 39 (9~70) winsize 62
2458 13:15:13.263054 [CA 2] Center 36 (6~67) winsize 62
2459 13:15:13.266335 [CA 3] Center 36 (6~66) winsize 61
2460 13:15:13.269893 [CA 4] Center 34 (4~65) winsize 62
2461 13:15:13.273189 [CA 5] Center 34 (4~64) winsize 61
2462 13:15:13.273296
2463 13:15:13.276690 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2464 13:15:13.276860
2465 13:15:13.279956 [CATrainingPosCal] consider 1 rank data
2466 13:15:13.283719 u2DelayCellTimex100 = 270/100 ps
2467 13:15:13.286968 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2468 13:15:13.289895 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2469 13:15:13.296957 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2470 13:15:13.299816 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2471 13:15:13.303379 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2472 13:15:13.306966 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2473 13:15:13.307075
2474 13:15:13.310361 CA PerBit enable=1, Macro0, CA PI delay=34
2475 13:15:13.310458
2476 13:15:13.314073 [CBTSetCACLKResult] CA Dly = 34
2477 13:15:13.314197 CS Dly: 7 (0~38)
2478 13:15:13.314281 ==
2479 13:15:13.316542 Dram Type= 6, Freq= 0, CH_0, rank 1
2480 13:15:13.323893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2481 13:15:13.324064 ==
2482 13:15:13.326974 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2483 13:15:13.333618 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2484 13:15:13.342150 [CA 0] Center 39 (9~70) winsize 62
2485 13:15:13.345686 [CA 1] Center 39 (9~70) winsize 62
2486 13:15:13.349014 [CA 2] Center 36 (6~67) winsize 62
2487 13:15:13.352261 [CA 3] Center 36 (5~67) winsize 63
2488 13:15:13.355836 [CA 4] Center 34 (4~65) winsize 62
2489 13:15:13.359018 [CA 5] Center 34 (4~64) winsize 61
2490 13:15:13.359135
2491 13:15:13.362416 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2492 13:15:13.362538
2493 13:15:13.365607 [CATrainingPosCal] consider 2 rank data
2494 13:15:13.368971 u2DelayCellTimex100 = 270/100 ps
2495 13:15:13.372596 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2496 13:15:13.376160 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2497 13:15:13.379462 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2498 13:15:13.385979 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2499 13:15:13.389374 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2500 13:15:13.393093 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2501 13:15:13.393234
2502 13:15:13.396497 CA PerBit enable=1, Macro0, CA PI delay=34
2503 13:15:13.396633
2504 13:15:13.399321 [CBTSetCACLKResult] CA Dly = 34
2505 13:15:13.399423 CS Dly: 8 (0~41)
2506 13:15:13.399505
2507 13:15:13.403187 ----->DramcWriteLeveling(PI) begin...
2508 13:15:13.403287 ==
2509 13:15:13.406474 Dram Type= 6, Freq= 0, CH_0, rank 0
2510 13:15:13.413310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2511 13:15:13.413422 ==
2512 13:15:13.416417 Write leveling (Byte 0): 32 => 32
2513 13:15:13.416518 Write leveling (Byte 1): 28 => 28
2514 13:15:13.419385 DramcWriteLeveling(PI) end<-----
2515 13:15:13.419485
2516 13:15:13.419570 ==
2517 13:15:13.423422 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 13:15:13.429732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 13:15:13.429872 ==
2520 13:15:13.433017 [Gating] SW mode calibration
2521 13:15:13.439770 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2522 13:15:13.443346 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2523 13:15:13.449820 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 13:15:13.452954 0 15 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
2525 13:15:13.456240 0 15 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2526 13:15:13.459811 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 13:15:13.466352 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 13:15:13.469765 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 13:15:13.473207 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 13:15:13.480242 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 13:15:13.483516 1 0 0 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 1)
2532 13:15:13.486489 1 0 4 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
2533 13:15:13.493507 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 13:15:13.497148 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 13:15:13.500294 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 13:15:13.507169 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 13:15:13.510343 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 13:15:13.513822 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 13:15:13.517076 1 1 0 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
2540 13:15:13.524016 1 1 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2541 13:15:13.527409 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 13:15:13.530901 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 13:15:13.537472 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 13:15:13.540342 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 13:15:13.543530 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 13:15:13.550386 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 13:15:13.553530 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2548 13:15:13.557041 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2549 13:15:13.563820 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 13:15:13.567092 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 13:15:13.570357 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 13:15:13.577515 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 13:15:13.580444 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 13:15:13.583905 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 13:15:13.590710 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 13:15:13.593981 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 13:15:13.597062 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 13:15:13.600577 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 13:15:13.607343 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 13:15:13.610491 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 13:15:13.614012 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 13:15:13.620708 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 13:15:13.624215 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2564 13:15:13.627310 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2565 13:15:13.630705 Total UI for P1: 0, mck2ui 16
2566 13:15:13.634415 best dqsien dly found for B0: ( 1, 4, 0)
2567 13:15:13.637419 Total UI for P1: 0, mck2ui 16
2568 13:15:13.641100 best dqsien dly found for B1: ( 1, 4, 0)
2569 13:15:13.644503 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2570 13:15:13.647497 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2571 13:15:13.647587
2572 13:15:13.651010 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2573 13:15:13.654177 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2574 13:15:13.657580 [Gating] SW calibration Done
2575 13:15:13.657671 ==
2576 13:15:13.661102 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 13:15:13.667794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 13:15:13.667899 ==
2579 13:15:13.667963 RX Vref Scan: 0
2580 13:15:13.668018
2581 13:15:13.671205 RX Vref 0 -> 0, step: 1
2582 13:15:13.671287
2583 13:15:13.674380 RX Delay -40 -> 252, step: 8
2584 13:15:13.677782 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2585 13:15:13.680956 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2586 13:15:13.684608 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2587 13:15:13.687775 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2588 13:15:13.694917 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2589 13:15:13.697970 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2590 13:15:13.701435 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2591 13:15:13.704396 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2592 13:15:13.708203 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2593 13:15:13.711683 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2594 13:15:13.718245 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2595 13:15:13.721968 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2596 13:15:13.725040 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2597 13:15:13.728069 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2598 13:15:13.731386 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2599 13:15:13.738724 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2600 13:15:13.738883 ==
2601 13:15:13.741505 Dram Type= 6, Freq= 0, CH_0, rank 0
2602 13:15:13.744933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2603 13:15:13.745022 ==
2604 13:15:13.745080 DQS Delay:
2605 13:15:13.748620 DQS0 = 0, DQS1 = 0
2606 13:15:13.748723 DQM Delay:
2607 13:15:13.751583 DQM0 = 115, DQM1 = 107
2608 13:15:13.751667 DQ Delay:
2609 13:15:13.755689 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2610 13:15:13.758205 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2611 13:15:13.761721 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2612 13:15:13.764892 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =115
2613 13:15:13.764993
2614 13:15:13.765052
2615 13:15:13.765105 ==
2616 13:15:13.768636 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 13:15:13.775029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 13:15:13.775184 ==
2619 13:15:13.775274
2620 13:15:13.775330
2621 13:15:13.775382 TX Vref Scan disable
2622 13:15:13.778862 == TX Byte 0 ==
2623 13:15:13.782146 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2624 13:15:13.785637 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2625 13:15:13.788919 == TX Byte 1 ==
2626 13:15:13.792475 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2627 13:15:13.795428 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2628 13:15:13.799107 ==
2629 13:15:13.802116 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 13:15:13.805255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 13:15:13.805364 ==
2632 13:15:13.817320 TX Vref=22, minBit 1, minWin=24, winSum=417
2633 13:15:13.820399 TX Vref=24, minBit 1, minWin=25, winSum=425
2634 13:15:13.823991 TX Vref=26, minBit 0, minWin=26, winSum=429
2635 13:15:13.826915 TX Vref=28, minBit 1, minWin=26, winSum=435
2636 13:15:13.830466 TX Vref=30, minBit 1, minWin=26, winSum=435
2637 13:15:13.833805 TX Vref=32, minBit 0, minWin=26, winSum=436
2638 13:15:13.840266 [TxChooseVref] Worse bit 0, Min win 26, Win sum 436, Final Vref 32
2639 13:15:13.840399
2640 13:15:13.843602 Final TX Range 1 Vref 32
2641 13:15:13.843722
2642 13:15:13.843784 ==
2643 13:15:13.847129 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 13:15:13.850661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 13:15:13.850785 ==
2646 13:15:13.850847
2647 13:15:13.850902
2648 13:15:13.854279 TX Vref Scan disable
2649 13:15:13.857543 == TX Byte 0 ==
2650 13:15:13.860596 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2651 13:15:13.863692 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2652 13:15:13.867280 == TX Byte 1 ==
2653 13:15:13.870494 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2654 13:15:13.873995 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2655 13:15:13.874115
2656 13:15:13.877031 [DATLAT]
2657 13:15:13.877128 Freq=1200, CH0 RK0
2658 13:15:13.877204
2659 13:15:13.880459 DATLAT Default: 0xd
2660 13:15:13.880546 0, 0xFFFF, sum = 0
2661 13:15:13.883884 1, 0xFFFF, sum = 0
2662 13:15:13.883973 2, 0xFFFF, sum = 0
2663 13:15:13.887535 3, 0xFFFF, sum = 0
2664 13:15:13.887617 4, 0xFFFF, sum = 0
2665 13:15:13.890580 5, 0xFFFF, sum = 0
2666 13:15:13.890660 6, 0xFFFF, sum = 0
2667 13:15:13.894178 7, 0xFFFF, sum = 0
2668 13:15:13.894261 8, 0xFFFF, sum = 0
2669 13:15:13.897270 9, 0xFFFF, sum = 0
2670 13:15:13.897353 10, 0xFFFF, sum = 0
2671 13:15:13.900409 11, 0xFFFF, sum = 0
2672 13:15:13.900486 12, 0x0, sum = 1
2673 13:15:13.903961 13, 0x0, sum = 2
2674 13:15:13.904047 14, 0x0, sum = 3
2675 13:15:13.907462 15, 0x0, sum = 4
2676 13:15:13.907546 best_step = 13
2677 13:15:13.907606
2678 13:15:13.907659 ==
2679 13:15:13.911072 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 13:15:13.917819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 13:15:13.917932 ==
2682 13:15:13.917993 RX Vref Scan: 1
2683 13:15:13.918047
2684 13:15:13.921008 Set Vref Range= 32 -> 127
2685 13:15:13.921085
2686 13:15:13.924085 RX Vref 32 -> 127, step: 1
2687 13:15:13.924165
2688 13:15:13.924223 RX Delay -21 -> 252, step: 4
2689 13:15:13.924277
2690 13:15:13.927666 Set Vref, RX VrefLevel [Byte0]: 32
2691 13:15:13.931152 [Byte1]: 32
2692 13:15:13.935359
2693 13:15:13.935455 Set Vref, RX VrefLevel [Byte0]: 33
2694 13:15:13.938809 [Byte1]: 33
2695 13:15:13.943342
2696 13:15:13.943439 Set Vref, RX VrefLevel [Byte0]: 34
2697 13:15:13.946355 [Byte1]: 34
2698 13:15:13.951108
2699 13:15:13.951204 Set Vref, RX VrefLevel [Byte0]: 35
2700 13:15:13.954163 [Byte1]: 35
2701 13:15:13.958968
2702 13:15:13.959101 Set Vref, RX VrefLevel [Byte0]: 36
2703 13:15:13.962299 [Byte1]: 36
2704 13:15:13.967123
2705 13:15:13.967251 Set Vref, RX VrefLevel [Byte0]: 37
2706 13:15:13.970600 [Byte1]: 37
2707 13:15:13.974995
2708 13:15:13.975114 Set Vref, RX VrefLevel [Byte0]: 38
2709 13:15:13.978117 [Byte1]: 38
2710 13:15:13.982901
2711 13:15:13.983012 Set Vref, RX VrefLevel [Byte0]: 39
2712 13:15:13.985973 [Byte1]: 39
2713 13:15:13.990781
2714 13:15:13.990948 Set Vref, RX VrefLevel [Byte0]: 40
2715 13:15:13.993900 [Byte1]: 40
2716 13:15:13.998298
2717 13:15:13.998404 Set Vref, RX VrefLevel [Byte0]: 41
2718 13:15:14.002359 [Byte1]: 41
2719 13:15:14.006871
2720 13:15:14.006997 Set Vref, RX VrefLevel [Byte0]: 42
2721 13:15:14.009944 [Byte1]: 42
2722 13:15:14.014459
2723 13:15:14.014586 Set Vref, RX VrefLevel [Byte0]: 43
2724 13:15:14.017901 [Byte1]: 43
2725 13:15:14.022280
2726 13:15:14.022371 Set Vref, RX VrefLevel [Byte0]: 44
2727 13:15:14.025450 [Byte1]: 44
2728 13:15:14.030289
2729 13:15:14.030414 Set Vref, RX VrefLevel [Byte0]: 45
2730 13:15:14.033373 [Byte1]: 45
2731 13:15:14.038135
2732 13:15:14.038229 Set Vref, RX VrefLevel [Byte0]: 46
2733 13:15:14.041647 [Byte1]: 46
2734 13:15:14.046145
2735 13:15:14.046244 Set Vref, RX VrefLevel [Byte0]: 47
2736 13:15:14.049291 [Byte1]: 47
2737 13:15:14.054145
2738 13:15:14.054234 Set Vref, RX VrefLevel [Byte0]: 48
2739 13:15:14.057585 [Byte1]: 48
2740 13:15:14.061930
2741 13:15:14.062053 Set Vref, RX VrefLevel [Byte0]: 49
2742 13:15:14.065450 [Byte1]: 49
2743 13:15:14.070079
2744 13:15:14.070174 Set Vref, RX VrefLevel [Byte0]: 50
2745 13:15:14.073451 [Byte1]: 50
2746 13:15:14.078665
2747 13:15:14.078775 Set Vref, RX VrefLevel [Byte0]: 51
2748 13:15:14.081423 [Byte1]: 51
2749 13:15:14.085845
2750 13:15:14.085931 Set Vref, RX VrefLevel [Byte0]: 52
2751 13:15:14.089075 [Byte1]: 52
2752 13:15:14.093669
2753 13:15:14.093763 Set Vref, RX VrefLevel [Byte0]: 53
2754 13:15:14.097279 [Byte1]: 53
2755 13:15:14.101501
2756 13:15:14.101629 Set Vref, RX VrefLevel [Byte0]: 54
2757 13:15:14.105031 [Byte1]: 54
2758 13:15:14.109852
2759 13:15:14.109951 Set Vref, RX VrefLevel [Byte0]: 55
2760 13:15:14.112817 [Byte1]: 55
2761 13:15:14.117338
2762 13:15:14.117421 Set Vref, RX VrefLevel [Byte0]: 56
2763 13:15:14.120603 [Byte1]: 56
2764 13:15:14.125523
2765 13:15:14.125612 Set Vref, RX VrefLevel [Byte0]: 57
2766 13:15:14.128723 [Byte1]: 57
2767 13:15:14.133527
2768 13:15:14.133614 Set Vref, RX VrefLevel [Byte0]: 58
2769 13:15:14.136700 [Byte1]: 58
2770 13:15:14.141287
2771 13:15:14.141371 Set Vref, RX VrefLevel [Byte0]: 59
2772 13:15:14.144557 [Byte1]: 59
2773 13:15:14.148956
2774 13:15:14.149081 Set Vref, RX VrefLevel [Byte0]: 60
2775 13:15:14.152366 [Byte1]: 60
2776 13:15:14.157360
2777 13:15:14.157475 Set Vref, RX VrefLevel [Byte0]: 61
2778 13:15:14.160124 [Byte1]: 61
2779 13:15:14.164823
2780 13:15:14.164923 Set Vref, RX VrefLevel [Byte0]: 62
2781 13:15:14.168228 [Byte1]: 62
2782 13:15:14.172787
2783 13:15:14.172873 Set Vref, RX VrefLevel [Byte0]: 63
2784 13:15:14.176406 [Byte1]: 63
2785 13:15:14.180923
2786 13:15:14.181015 Set Vref, RX VrefLevel [Byte0]: 64
2787 13:15:14.183959 [Byte1]: 64
2788 13:15:14.189042
2789 13:15:14.189178 Set Vref, RX VrefLevel [Byte0]: 65
2790 13:15:14.192224 [Byte1]: 65
2791 13:15:14.196941
2792 13:15:14.197077 Set Vref, RX VrefLevel [Byte0]: 66
2793 13:15:14.199953 [Byte1]: 66
2794 13:15:14.204962
2795 13:15:14.205119 Set Vref, RX VrefLevel [Byte0]: 67
2796 13:15:14.207918 [Byte1]: 67
2797 13:15:14.212737
2798 13:15:14.212829 Set Vref, RX VrefLevel [Byte0]: 68
2799 13:15:14.215709 [Byte1]: 68
2800 13:15:14.220515
2801 13:15:14.220609 Final RX Vref Byte 0 = 54 to rank0
2802 13:15:14.223675 Final RX Vref Byte 1 = 51 to rank0
2803 13:15:14.227571 Final RX Vref Byte 0 = 54 to rank1
2804 13:15:14.230955 Final RX Vref Byte 1 = 51 to rank1==
2805 13:15:14.233704 Dram Type= 6, Freq= 0, CH_0, rank 0
2806 13:15:14.237175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2807 13:15:14.240915 ==
2808 13:15:14.241004 DQS Delay:
2809 13:15:14.241064 DQS0 = 0, DQS1 = 0
2810 13:15:14.244343 DQM Delay:
2811 13:15:14.244423 DQM0 = 114, DQM1 = 105
2812 13:15:14.247582 DQ Delay:
2813 13:15:14.251030 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =112
2814 13:15:14.254120 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2815 13:15:14.257305 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2816 13:15:14.260518 DQ12 =114, DQ13 =110, DQ14 =120, DQ15 =114
2817 13:15:14.260631
2818 13:15:14.260691
2819 13:15:14.267313 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
2820 13:15:14.270830 CH0 RK0: MR19=403, MR18=2F2
2821 13:15:14.277373 CH0_RK0: MR19=0x403, MR18=0x2F2, DQSOSC=409, MR23=63, INC=39, DEC=26
2822 13:15:14.277550
2823 13:15:14.281292 ----->DramcWriteLeveling(PI) begin...
2824 13:15:14.281471 ==
2825 13:15:14.284235 Dram Type= 6, Freq= 0, CH_0, rank 1
2826 13:15:14.287716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 13:15:14.287835 ==
2828 13:15:14.290693 Write leveling (Byte 0): 32 => 32
2829 13:15:14.294260 Write leveling (Byte 1): 30 => 30
2830 13:15:14.297522 DramcWriteLeveling(PI) end<-----
2831 13:15:14.297639
2832 13:15:14.297734 ==
2833 13:15:14.301014 Dram Type= 6, Freq= 0, CH_0, rank 1
2834 13:15:14.304719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2835 13:15:14.304857 ==
2836 13:15:14.308523 [Gating] SW mode calibration
2837 13:15:14.314466 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2838 13:15:14.320912 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2839 13:15:14.324450 0 15 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2840 13:15:14.327629 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2841 13:15:14.334543 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 13:15:14.338203 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 13:15:14.341261 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 13:15:14.348035 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 13:15:14.351170 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2846 13:15:14.355180 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2847 13:15:14.360996 1 0 0 | B1->B0 | 2e2e 2525 | 0 0 | (0 0) (0 0)
2848 13:15:14.364476 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 13:15:14.367839 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 13:15:14.374319 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 13:15:14.377970 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 13:15:14.381036 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 13:15:14.388081 1 0 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2854 13:15:14.391603 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2855 13:15:14.394355 1 1 0 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
2856 13:15:14.398194 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 13:15:14.404757 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 13:15:14.407851 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 13:15:14.411456 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 13:15:14.418129 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 13:15:14.421597 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 13:15:14.424918 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2863 13:15:14.431763 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2864 13:15:14.434886 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2865 13:15:14.438539 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 13:15:14.445297 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 13:15:14.448293 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 13:15:14.451955 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 13:15:14.458557 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 13:15:14.461552 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 13:15:14.465170 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 13:15:14.468618 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 13:15:14.474950 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 13:15:14.478690 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 13:15:14.481779 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 13:15:14.488409 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 13:15:14.491772 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 13:15:14.495324 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2879 13:15:14.502106 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2880 13:15:14.502206 Total UI for P1: 0, mck2ui 16
2881 13:15:14.508402 best dqsien dly found for B0: ( 1, 3, 28)
2882 13:15:14.511693 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 13:15:14.515699 Total UI for P1: 0, mck2ui 16
2884 13:15:14.518856 best dqsien dly found for B1: ( 1, 4, 0)
2885 13:15:14.522481 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2886 13:15:14.525444 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2887 13:15:14.525527
2888 13:15:14.528611 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2889 13:15:14.532175 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2890 13:15:14.535511 [Gating] SW calibration Done
2891 13:15:14.535591 ==
2892 13:15:14.538736 Dram Type= 6, Freq= 0, CH_0, rank 1
2893 13:15:14.541943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2894 13:15:14.542022 ==
2895 13:15:14.545563 RX Vref Scan: 0
2896 13:15:14.545642
2897 13:15:14.548867 RX Vref 0 -> 0, step: 1
2898 13:15:14.548945
2899 13:15:14.549004 RX Delay -40 -> 252, step: 8
2900 13:15:14.555127 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2901 13:15:14.559017 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2902 13:15:14.562951 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2903 13:15:14.565863 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2904 13:15:14.568806 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2905 13:15:14.575304 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2906 13:15:14.578960 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2907 13:15:14.581915 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2908 13:15:14.585532 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2909 13:15:14.588746 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2910 13:15:14.591941 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2911 13:15:14.598940 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2912 13:15:14.602179 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2913 13:15:14.605356 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2914 13:15:14.608445 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2915 13:15:14.612427 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2916 13:15:14.615720 ==
2917 13:15:14.618801 Dram Type= 6, Freq= 0, CH_0, rank 1
2918 13:15:14.622496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2919 13:15:14.622589 ==
2920 13:15:14.622649 DQS Delay:
2921 13:15:14.625404 DQS0 = 0, DQS1 = 0
2922 13:15:14.625487 DQM Delay:
2923 13:15:14.628816 DQM0 = 115, DQM1 = 105
2924 13:15:14.628921 DQ Delay:
2925 13:15:14.632223 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2926 13:15:14.635970 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2927 13:15:14.639148 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2928 13:15:14.642398 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2929 13:15:14.642489
2930 13:15:14.642547
2931 13:15:14.642600 ==
2932 13:15:14.645656 Dram Type= 6, Freq= 0, CH_0, rank 1
2933 13:15:14.649402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2934 13:15:14.652667 ==
2935 13:15:14.652775
2936 13:15:14.652835
2937 13:15:14.652920 TX Vref Scan disable
2938 13:15:14.655454 == TX Byte 0 ==
2939 13:15:14.659028 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2940 13:15:14.662059 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2941 13:15:14.665596 == TX Byte 1 ==
2942 13:15:14.668560 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2943 13:15:14.672594 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2944 13:15:14.675737 ==
2945 13:15:14.675850 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 13:15:14.682062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 13:15:14.682200 ==
2948 13:15:14.693336 TX Vref=22, minBit 4, minWin=25, winSum=422
2949 13:15:14.696963 TX Vref=24, minBit 0, minWin=26, winSum=426
2950 13:15:14.700084 TX Vref=26, minBit 3, minWin=26, winSum=434
2951 13:15:14.703348 TX Vref=28, minBit 3, minWin=26, winSum=436
2952 13:15:14.707420 TX Vref=30, minBit 3, minWin=26, winSum=436
2953 13:15:14.709914 TX Vref=32, minBit 3, minWin=26, winSum=434
2954 13:15:14.716491 [TxChooseVref] Worse bit 3, Min win 26, Win sum 436, Final Vref 28
2955 13:15:14.716600
2956 13:15:14.719957 Final TX Range 1 Vref 28
2957 13:15:14.720045
2958 13:15:14.720122 ==
2959 13:15:14.723262 Dram Type= 6, Freq= 0, CH_0, rank 1
2960 13:15:14.726936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2961 13:15:14.727028 ==
2962 13:15:14.727094
2963 13:15:14.727149
2964 13:15:14.730128 TX Vref Scan disable
2965 13:15:14.733472 == TX Byte 0 ==
2966 13:15:14.736581 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2967 13:15:14.739926 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2968 13:15:14.743397 == TX Byte 1 ==
2969 13:15:14.746824 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2970 13:15:14.750105 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2971 13:15:14.750182
2972 13:15:14.753690 [DATLAT]
2973 13:15:14.753767 Freq=1200, CH0 RK1
2974 13:15:14.753825
2975 13:15:14.756799 DATLAT Default: 0xd
2976 13:15:14.756875 0, 0xFFFF, sum = 0
2977 13:15:14.760276 1, 0xFFFF, sum = 0
2978 13:15:14.760354 2, 0xFFFF, sum = 0
2979 13:15:14.763373 3, 0xFFFF, sum = 0
2980 13:15:14.763451 4, 0xFFFF, sum = 0
2981 13:15:14.766536 5, 0xFFFF, sum = 0
2982 13:15:14.766614 6, 0xFFFF, sum = 0
2983 13:15:14.770318 7, 0xFFFF, sum = 0
2984 13:15:14.770394 8, 0xFFFF, sum = 0
2985 13:15:14.773515 9, 0xFFFF, sum = 0
2986 13:15:14.776631 10, 0xFFFF, sum = 0
2987 13:15:14.776708 11, 0xFFFF, sum = 0
2988 13:15:14.780180 12, 0x0, sum = 1
2989 13:15:14.780257 13, 0x0, sum = 2
2990 13:15:14.780317 14, 0x0, sum = 3
2991 13:15:14.783685 15, 0x0, sum = 4
2992 13:15:14.783762 best_step = 13
2993 13:15:14.783821
2994 13:15:14.783875 ==
2995 13:15:14.786896 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 13:15:14.793421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 13:15:14.793502 ==
2998 13:15:14.793561 RX Vref Scan: 0
2999 13:15:14.793615
3000 13:15:14.796706 RX Vref 0 -> 0, step: 1
3001 13:15:14.796917
3002 13:15:14.800379 RX Delay -21 -> 252, step: 4
3003 13:15:14.803710 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3004 13:15:14.806707 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3005 13:15:14.813786 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3006 13:15:14.817019 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3007 13:15:14.819808 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3008 13:15:14.823468 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3009 13:15:14.826881 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3010 13:15:14.833507 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3011 13:15:14.836715 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3012 13:15:14.840209 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3013 13:15:14.843985 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3014 13:15:14.846600 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3015 13:15:14.853254 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3016 13:15:14.856900 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3017 13:15:14.859923 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3018 13:15:14.863235 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3019 13:15:14.863315 ==
3020 13:15:14.867034 Dram Type= 6, Freq= 0, CH_0, rank 1
3021 13:15:14.873194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3022 13:15:14.873293 ==
3023 13:15:14.873378 DQS Delay:
3024 13:15:14.873458 DQS0 = 0, DQS1 = 0
3025 13:15:14.876621 DQM Delay:
3026 13:15:14.876697 DQM0 = 113, DQM1 = 104
3027 13:15:14.880363 DQ Delay:
3028 13:15:14.883069 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3029 13:15:14.886583 DQ4 =112, DQ5 =104, DQ6 =120, DQ7 =122
3030 13:15:14.890220 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3031 13:15:14.893515 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =112
3032 13:15:14.893613
3033 13:15:14.893697
3034 13:15:14.900122 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3035 13:15:14.902949 CH0 RK1: MR19=403, MR18=2F3
3036 13:15:14.909917 CH0_RK1: MR19=0x403, MR18=0x2F3, DQSOSC=409, MR23=63, INC=39, DEC=26
3037 13:15:14.913104 [RxdqsGatingPostProcess] freq 1200
3038 13:15:14.919935 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3039 13:15:14.920012 best DQS0 dly(2T, 0.5T) = (0, 12)
3040 13:15:14.923062 best DQS1 dly(2T, 0.5T) = (0, 12)
3041 13:15:14.926484 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3042 13:15:14.930170 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3043 13:15:14.933332 best DQS0 dly(2T, 0.5T) = (0, 11)
3044 13:15:14.937288 best DQS1 dly(2T, 0.5T) = (0, 12)
3045 13:15:14.940160 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3046 13:15:14.944291 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3047 13:15:14.946919 Pre-setting of DQS Precalculation
3048 13:15:14.950353 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3049 13:15:14.950432 ==
3050 13:15:14.953851 Dram Type= 6, Freq= 0, CH_1, rank 0
3051 13:15:14.960344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3052 13:15:14.960421 ==
3053 13:15:14.963599 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3054 13:15:14.970140 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3055 13:15:14.979042 [CA 0] Center 38 (9~68) winsize 60
3056 13:15:14.982704 [CA 1] Center 38 (8~68) winsize 61
3057 13:15:14.985840 [CA 2] Center 35 (5~65) winsize 61
3058 13:15:14.989074 [CA 3] Center 34 (3~65) winsize 63
3059 13:15:14.992162 [CA 4] Center 34 (4~65) winsize 62
3060 13:15:14.995772 [CA 5] Center 34 (4~64) winsize 61
3061 13:15:14.995848
3062 13:15:14.998756 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3063 13:15:14.998832
3064 13:15:15.001967 [CATrainingPosCal] consider 1 rank data
3065 13:15:15.005541 u2DelayCellTimex100 = 270/100 ps
3066 13:15:15.008851 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3067 13:15:15.011941 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3068 13:15:15.018733 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3069 13:15:15.022570 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
3070 13:15:15.025655 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3071 13:15:15.029009 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3072 13:15:15.029113
3073 13:15:15.032370 CA PerBit enable=1, Macro0, CA PI delay=34
3074 13:15:15.032445
3075 13:15:15.035348 [CBTSetCACLKResult] CA Dly = 34
3076 13:15:15.035424 CS Dly: 6 (0~37)
3077 13:15:15.035483 ==
3078 13:15:15.038639 Dram Type= 6, Freq= 0, CH_1, rank 1
3079 13:15:15.045564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3080 13:15:15.045642 ==
3081 13:15:15.048925 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3082 13:15:15.056355 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3083 13:15:15.064443 [CA 0] Center 37 (7~68) winsize 62
3084 13:15:15.067638 [CA 1] Center 38 (9~68) winsize 60
3085 13:15:15.071138 [CA 2] Center 34 (4~65) winsize 62
3086 13:15:15.074433 [CA 3] Center 34 (3~65) winsize 63
3087 13:15:15.077763 [CA 4] Center 34 (4~65) winsize 62
3088 13:15:15.081068 [CA 5] Center 33 (3~63) winsize 61
3089 13:15:15.081179
3090 13:15:15.084416 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3091 13:15:15.084492
3092 13:15:15.087608 [CATrainingPosCal] consider 2 rank data
3093 13:15:15.091070 u2DelayCellTimex100 = 270/100 ps
3094 13:15:15.094818 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3095 13:15:15.097558 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3096 13:15:15.104102 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3097 13:15:15.107970 CA3 delay=34 (3~65),Diff = 1 PI (4 cell)
3098 13:15:15.111142 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3099 13:15:15.114437 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3100 13:15:15.114513
3101 13:15:15.118062 CA PerBit enable=1, Macro0, CA PI delay=33
3102 13:15:15.118138
3103 13:15:15.121257 [CBTSetCACLKResult] CA Dly = 33
3104 13:15:15.121333 CS Dly: 7 (0~40)
3105 13:15:15.121392
3106 13:15:15.124679 ----->DramcWriteLeveling(PI) begin...
3107 13:15:15.127866 ==
3108 13:15:15.127941 Dram Type= 6, Freq= 0, CH_1, rank 0
3109 13:15:15.134377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3110 13:15:15.134454 ==
3111 13:15:15.137690 Write leveling (Byte 0): 27 => 27
3112 13:15:15.141231 Write leveling (Byte 1): 31 => 31
3113 13:15:15.141322 DramcWriteLeveling(PI) end<-----
3114 13:15:15.144643
3115 13:15:15.144718 ==
3116 13:15:15.147906 Dram Type= 6, Freq= 0, CH_1, rank 0
3117 13:15:15.151255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 13:15:15.151332 ==
3119 13:15:15.154760 [Gating] SW mode calibration
3120 13:15:15.161135 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3121 13:15:15.164776 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3122 13:15:15.171070 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3123 13:15:15.174752 0 15 4 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
3124 13:15:15.177847 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 13:15:15.184450 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 13:15:15.188069 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 13:15:15.191905 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 13:15:15.198201 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 13:15:15.201075 0 15 28 | B1->B0 | 3232 3434 | 1 0 | (1 1) (0 0)
3130 13:15:15.204818 1 0 0 | B1->B0 | 2525 2929 | 0 0 | (1 0) (1 0)
3131 13:15:15.211721 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 13:15:15.214361 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 13:15:15.217914 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 13:15:15.224320 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 13:15:15.227872 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 13:15:15.231605 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 13:15:15.234736 1 0 28 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (0 0)
3138 13:15:15.241346 1 1 0 | B1->B0 | 4141 3838 | 0 0 | (0 0) (0 0)
3139 13:15:15.244520 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 13:15:15.248205 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 13:15:15.254998 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 13:15:15.257920 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 13:15:15.261871 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 13:15:15.268240 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 13:15:15.271402 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3146 13:15:15.274516 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3147 13:15:15.281158 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 13:15:15.284384 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 13:15:15.288482 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 13:15:15.294817 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 13:15:15.297899 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 13:15:15.301029 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 13:15:15.308145 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 13:15:15.311675 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 13:15:15.314891 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 13:15:15.321546 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 13:15:15.324485 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 13:15:15.327661 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 13:15:15.330937 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 13:15:15.338034 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 13:15:15.341801 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3162 13:15:15.344956 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3163 13:15:15.348030 Total UI for P1: 0, mck2ui 16
3164 13:15:15.351492 best dqsien dly found for B1: ( 1, 3, 30)
3165 13:15:15.358525 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 13:15:15.358602 Total UI for P1: 0, mck2ui 16
3167 13:15:15.364887 best dqsien dly found for B0: ( 1, 3, 30)
3168 13:15:15.367930 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3169 13:15:15.371347 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3170 13:15:15.371423
3171 13:15:15.375195 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3172 13:15:15.378161 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3173 13:15:15.381952 [Gating] SW calibration Done
3174 13:15:15.382028 ==
3175 13:15:15.384695 Dram Type= 6, Freq= 0, CH_1, rank 0
3176 13:15:15.388322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3177 13:15:15.388399 ==
3178 13:15:15.391471 RX Vref Scan: 0
3179 13:15:15.391554
3180 13:15:15.391613 RX Vref 0 -> 0, step: 1
3181 13:15:15.391667
3182 13:15:15.394624 RX Delay -40 -> 252, step: 8
3183 13:15:15.398198 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3184 13:15:15.404804 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3185 13:15:15.408237 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3186 13:15:15.411753 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3187 13:15:15.414815 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3188 13:15:15.418013 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3189 13:15:15.425286 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3190 13:15:15.428425 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3191 13:15:15.431391 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3192 13:15:15.434986 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3193 13:15:15.438333 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3194 13:15:15.441322 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3195 13:15:15.448036 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3196 13:15:15.451340 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3197 13:15:15.454955 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3198 13:15:15.458170 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3199 13:15:15.458245 ==
3200 13:15:15.461502 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 13:15:15.468151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 13:15:15.468229 ==
3203 13:15:15.468288 DQS Delay:
3204 13:15:15.471154 DQS0 = 0, DQS1 = 0
3205 13:15:15.471231 DQM Delay:
3206 13:15:15.474632 DQM0 = 115, DQM1 = 108
3207 13:15:15.474707 DQ Delay:
3208 13:15:15.477871 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3209 13:15:15.481446 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3210 13:15:15.484688 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3211 13:15:15.487924 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3212 13:15:15.488003
3213 13:15:15.488062
3214 13:15:15.488116 ==
3215 13:15:15.491584 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 13:15:15.494623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 13:15:15.498016 ==
3218 13:15:15.498093
3219 13:15:15.498151
3220 13:15:15.498205 TX Vref Scan disable
3221 13:15:15.501510 == TX Byte 0 ==
3222 13:15:15.504986 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3223 13:15:15.508136 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3224 13:15:15.511202 == TX Byte 1 ==
3225 13:15:15.514551 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3226 13:15:15.518109 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3227 13:15:15.518186 ==
3228 13:15:15.521774 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 13:15:15.527879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 13:15:15.527986 ==
3231 13:15:15.539269 TX Vref=22, minBit 13, minWin=24, winSum=409
3232 13:15:15.542662 TX Vref=24, minBit 2, minWin=25, winSum=414
3233 13:15:15.545920 TX Vref=26, minBit 1, minWin=26, winSum=421
3234 13:15:15.548906 TX Vref=28, minBit 1, minWin=26, winSum=425
3235 13:15:15.552123 TX Vref=30, minBit 13, minWin=25, winSum=425
3236 13:15:15.559953 TX Vref=32, minBit 1, minWin=26, winSum=427
3237 13:15:15.562490 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 32
3238 13:15:15.562568
3239 13:15:15.565927 Final TX Range 1 Vref 32
3240 13:15:15.566003
3241 13:15:15.566061 ==
3242 13:15:15.569080 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 13:15:15.572470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 13:15:15.572546 ==
3245 13:15:15.572606
3246 13:15:15.575615
3247 13:15:15.575698 TX Vref Scan disable
3248 13:15:15.579314 == TX Byte 0 ==
3249 13:15:15.582443 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3250 13:15:15.585647 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3251 13:15:15.588967 == TX Byte 1 ==
3252 13:15:15.592257 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3253 13:15:15.595584 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3254 13:15:15.595661
3255 13:15:15.599293 [DATLAT]
3256 13:15:15.599369 Freq=1200, CH1 RK0
3257 13:15:15.599428
3258 13:15:15.602787 DATLAT Default: 0xd
3259 13:15:15.602863 0, 0xFFFF, sum = 0
3260 13:15:15.605465 1, 0xFFFF, sum = 0
3261 13:15:15.605543 2, 0xFFFF, sum = 0
3262 13:15:15.609101 3, 0xFFFF, sum = 0
3263 13:15:15.609222 4, 0xFFFF, sum = 0
3264 13:15:15.612158 5, 0xFFFF, sum = 0
3265 13:15:15.616103 6, 0xFFFF, sum = 0
3266 13:15:15.616181 7, 0xFFFF, sum = 0
3267 13:15:15.618739 8, 0xFFFF, sum = 0
3268 13:15:15.618817 9, 0xFFFF, sum = 0
3269 13:15:15.622425 10, 0xFFFF, sum = 0
3270 13:15:15.622502 11, 0xFFFF, sum = 0
3271 13:15:15.625859 12, 0x0, sum = 1
3272 13:15:15.625936 13, 0x0, sum = 2
3273 13:15:15.629251 14, 0x0, sum = 3
3274 13:15:15.629329 15, 0x0, sum = 4
3275 13:15:15.629389 best_step = 13
3276 13:15:15.629443
3277 13:15:15.632019 ==
3278 13:15:15.635394 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 13:15:15.639003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 13:15:15.639081 ==
3281 13:15:15.639139 RX Vref Scan: 1
3282 13:15:15.639194
3283 13:15:15.642313 Set Vref Range= 32 -> 127
3284 13:15:15.642388
3285 13:15:15.645670 RX Vref 32 -> 127, step: 1
3286 13:15:15.645747
3287 13:15:15.649111 RX Delay -21 -> 252, step: 4
3288 13:15:15.649228
3289 13:15:15.652102 Set Vref, RX VrefLevel [Byte0]: 32
3290 13:15:15.656046 [Byte1]: 32
3291 13:15:15.656123
3292 13:15:15.659305 Set Vref, RX VrefLevel [Byte0]: 33
3293 13:15:15.662027 [Byte1]: 33
3294 13:15:15.662103
3295 13:15:15.665406 Set Vref, RX VrefLevel [Byte0]: 34
3296 13:15:15.669087 [Byte1]: 34
3297 13:15:15.673494
3298 13:15:15.673570 Set Vref, RX VrefLevel [Byte0]: 35
3299 13:15:15.676486 [Byte1]: 35
3300 13:15:15.680944
3301 13:15:15.681022 Set Vref, RX VrefLevel [Byte0]: 36
3302 13:15:15.684538 [Byte1]: 36
3303 13:15:15.688989
3304 13:15:15.689069 Set Vref, RX VrefLevel [Byte0]: 37
3305 13:15:15.692758 [Byte1]: 37
3306 13:15:15.697218
3307 13:15:15.697293 Set Vref, RX VrefLevel [Byte0]: 38
3308 13:15:15.700499 [Byte1]: 38
3309 13:15:15.705147
3310 13:15:15.705236 Set Vref, RX VrefLevel [Byte0]: 39
3311 13:15:15.708203 [Byte1]: 39
3312 13:15:15.712864
3313 13:15:15.712940 Set Vref, RX VrefLevel [Byte0]: 40
3314 13:15:15.716251 [Byte1]: 40
3315 13:15:15.721100
3316 13:15:15.721213 Set Vref, RX VrefLevel [Byte0]: 41
3317 13:15:15.724142 [Byte1]: 41
3318 13:15:15.729067
3319 13:15:15.729181 Set Vref, RX VrefLevel [Byte0]: 42
3320 13:15:15.731770 [Byte1]: 42
3321 13:15:15.736780
3322 13:15:15.736856 Set Vref, RX VrefLevel [Byte0]: 43
3323 13:15:15.739852 [Byte1]: 43
3324 13:15:15.745031
3325 13:15:15.745154 Set Vref, RX VrefLevel [Byte0]: 44
3326 13:15:15.747786 [Byte1]: 44
3327 13:15:15.752517
3328 13:15:15.752607 Set Vref, RX VrefLevel [Byte0]: 45
3329 13:15:15.755770 [Byte1]: 45
3330 13:15:15.760519
3331 13:15:15.760594 Set Vref, RX VrefLevel [Byte0]: 46
3332 13:15:15.763691 [Byte1]: 46
3333 13:15:15.768174
3334 13:15:15.768248 Set Vref, RX VrefLevel [Byte0]: 47
3335 13:15:15.771735 [Byte1]: 47
3336 13:15:15.776060
3337 13:15:15.776135 Set Vref, RX VrefLevel [Byte0]: 48
3338 13:15:15.779702 [Byte1]: 48
3339 13:15:15.783954
3340 13:15:15.784047 Set Vref, RX VrefLevel [Byte0]: 49
3341 13:15:15.787651 [Byte1]: 49
3342 13:15:15.791919
3343 13:15:15.792020 Set Vref, RX VrefLevel [Byte0]: 50
3344 13:15:15.795323 [Byte1]: 50
3345 13:15:15.799880
3346 13:15:15.799955 Set Vref, RX VrefLevel [Byte0]: 51
3347 13:15:15.803351 [Byte1]: 51
3348 13:15:15.807727
3349 13:15:15.807802 Set Vref, RX VrefLevel [Byte0]: 52
3350 13:15:15.811350 [Byte1]: 52
3351 13:15:15.815879
3352 13:15:15.815954 Set Vref, RX VrefLevel [Byte0]: 53
3353 13:15:15.819410 [Byte1]: 53
3354 13:15:15.823822
3355 13:15:15.823898 Set Vref, RX VrefLevel [Byte0]: 54
3356 13:15:15.827052 [Byte1]: 54
3357 13:15:15.831867
3358 13:15:15.831951 Set Vref, RX VrefLevel [Byte0]: 55
3359 13:15:15.835332 [Byte1]: 55
3360 13:15:15.839469
3361 13:15:15.839544 Set Vref, RX VrefLevel [Byte0]: 56
3362 13:15:15.843010 [Byte1]: 56
3363 13:15:15.847226
3364 13:15:15.847302 Set Vref, RX VrefLevel [Byte0]: 57
3365 13:15:15.851042 [Byte1]: 57
3366 13:15:15.855182
3367 13:15:15.855260 Set Vref, RX VrefLevel [Byte0]: 58
3368 13:15:15.859016 [Byte1]: 58
3369 13:15:15.863254
3370 13:15:15.863329 Set Vref, RX VrefLevel [Byte0]: 59
3371 13:15:15.866541 [Byte1]: 59
3372 13:15:15.871503
3373 13:15:15.871579 Set Vref, RX VrefLevel [Byte0]: 60
3374 13:15:15.874765 [Byte1]: 60
3375 13:15:15.879026
3376 13:15:15.879101 Set Vref, RX VrefLevel [Byte0]: 61
3377 13:15:15.882583 [Byte1]: 61
3378 13:15:15.887038
3379 13:15:15.887113 Set Vref, RX VrefLevel [Byte0]: 62
3380 13:15:15.890532 [Byte1]: 62
3381 13:15:15.894966
3382 13:15:15.895042 Set Vref, RX VrefLevel [Byte0]: 63
3383 13:15:15.898370 [Byte1]: 63
3384 13:15:15.902956
3385 13:15:15.903031 Set Vref, RX VrefLevel [Byte0]: 64
3386 13:15:15.906185 [Byte1]: 64
3387 13:15:15.910933
3388 13:15:15.911008 Set Vref, RX VrefLevel [Byte0]: 65
3389 13:15:15.914249 [Byte1]: 65
3390 13:15:15.918819
3391 13:15:15.918919 Set Vref, RX VrefLevel [Byte0]: 66
3392 13:15:15.922344 [Byte1]: 66
3393 13:15:15.926690
3394 13:15:15.926764 Set Vref, RX VrefLevel [Byte0]: 67
3395 13:15:15.930210 [Byte1]: 67
3396 13:15:15.934806
3397 13:15:15.934881 Set Vref, RX VrefLevel [Byte0]: 68
3398 13:15:15.937987 [Byte1]: 68
3399 13:15:15.942276
3400 13:15:15.942352 Set Vref, RX VrefLevel [Byte0]: 69
3401 13:15:15.945841 [Byte1]: 69
3402 13:15:15.950275
3403 13:15:15.950349 Set Vref, RX VrefLevel [Byte0]: 70
3404 13:15:15.953514 [Byte1]: 70
3405 13:15:15.958184
3406 13:15:15.958258 Final RX Vref Byte 0 = 56 to rank0
3407 13:15:15.961434 Final RX Vref Byte 1 = 50 to rank0
3408 13:15:15.964980 Final RX Vref Byte 0 = 56 to rank1
3409 13:15:15.968101 Final RX Vref Byte 1 = 50 to rank1==
3410 13:15:15.971450 Dram Type= 6, Freq= 0, CH_1, rank 0
3411 13:15:15.978141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3412 13:15:15.978219 ==
3413 13:15:15.978306 DQS Delay:
3414 13:15:15.978387 DQS0 = 0, DQS1 = 0
3415 13:15:15.981746 DQM Delay:
3416 13:15:15.981822 DQM0 = 115, DQM1 = 108
3417 13:15:15.984888 DQ Delay:
3418 13:15:15.988561 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =112
3419 13:15:15.992028 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =112
3420 13:15:15.995097 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =104
3421 13:15:15.998241 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =114
3422 13:15:15.998317
3423 13:15:15.998376
3424 13:15:16.004978 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e7, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
3425 13:15:16.008852 CH1 RK0: MR19=403, MR18=3E7
3426 13:15:16.015608 CH1_RK0: MR19=0x403, MR18=0x3E7, DQSOSC=408, MR23=63, INC=39, DEC=26
3427 13:15:16.015713
3428 13:15:16.018443 ----->DramcWriteLeveling(PI) begin...
3429 13:15:16.018519 ==
3430 13:15:16.022222 Dram Type= 6, Freq= 0, CH_1, rank 1
3431 13:15:16.025253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3432 13:15:16.025353 ==
3433 13:15:16.029086 Write leveling (Byte 0): 26 => 26
3434 13:15:16.032114 Write leveling (Byte 1): 31 => 31
3435 13:15:16.035304 DramcWriteLeveling(PI) end<-----
3436 13:15:16.035396
3437 13:15:16.035484 ==
3438 13:15:16.038831 Dram Type= 6, Freq= 0, CH_1, rank 1
3439 13:15:16.041817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3440 13:15:16.045485 ==
3441 13:15:16.045598 [Gating] SW mode calibration
3442 13:15:16.052381 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3443 13:15:16.058582 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3444 13:15:16.062342 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3445 13:15:16.068944 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 13:15:16.071859 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 13:15:16.075251 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3448 13:15:16.081840 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 13:15:16.085794 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3450 13:15:16.088921 0 15 24 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 1)
3451 13:15:16.095041 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
3452 13:15:16.098716 1 0 0 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
3453 13:15:16.102098 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 13:15:16.108222 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 13:15:16.111525 1 0 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3456 13:15:16.115113 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 13:15:16.118345 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3458 13:15:16.124999 1 0 24 | B1->B0 | 2525 3d3d | 0 0 | (0 0) (1 1)
3459 13:15:16.128576 1 0 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
3460 13:15:16.131828 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 13:15:16.138483 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 13:15:16.141423 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 13:15:16.145430 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 13:15:16.151839 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 13:15:16.155211 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 13:15:16.158572 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3467 13:15:16.164802 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3468 13:15:16.168474 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 13:15:16.172208 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 13:15:16.178455 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 13:15:16.182104 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 13:15:16.185380 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 13:15:16.191999 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 13:15:16.195030 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 13:15:16.198518 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 13:15:16.205392 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 13:15:16.208688 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 13:15:16.211883 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 13:15:16.215279 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 13:15:16.221798 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 13:15:16.225246 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3482 13:15:16.228343 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3483 13:15:16.235726 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3484 13:15:16.238657 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 13:15:16.241978 Total UI for P1: 0, mck2ui 16
3486 13:15:16.245048 best dqsien dly found for B0: ( 1, 3, 24)
3487 13:15:16.248656 Total UI for P1: 0, mck2ui 16
3488 13:15:16.252083 best dqsien dly found for B1: ( 1, 3, 28)
3489 13:15:16.255628 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3490 13:15:16.259199 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3491 13:15:16.259308
3492 13:15:16.262295 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3493 13:15:16.265562 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3494 13:15:16.268792 [Gating] SW calibration Done
3495 13:15:16.268977 ==
3496 13:15:16.271970 Dram Type= 6, Freq= 0, CH_1, rank 1
3497 13:15:16.275769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3498 13:15:16.275862 ==
3499 13:15:16.278947 RX Vref Scan: 0
3500 13:15:16.279021
3501 13:15:16.282207 RX Vref 0 -> 0, step: 1
3502 13:15:16.282282
3503 13:15:16.282340 RX Delay -40 -> 252, step: 8
3504 13:15:16.288974 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3505 13:15:16.292645 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3506 13:15:16.295463 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3507 13:15:16.298996 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3508 13:15:16.302080 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3509 13:15:16.308760 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3510 13:15:16.312488 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3511 13:15:16.315823 iDelay=200, Bit 7, Center 111 (48 ~ 175) 128
3512 13:15:16.318876 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3513 13:15:16.322631 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3514 13:15:16.325555 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3515 13:15:16.332401 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3516 13:15:16.335674 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3517 13:15:16.339344 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3518 13:15:16.342328 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3519 13:15:16.348620 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3520 13:15:16.348696 ==
3521 13:15:16.352668 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 13:15:16.355804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 13:15:16.355880 ==
3524 13:15:16.355939 DQS Delay:
3525 13:15:16.358659 DQS0 = 0, DQS1 = 0
3526 13:15:16.358734 DQM Delay:
3527 13:15:16.362441 DQM0 = 114, DQM1 = 109
3528 13:15:16.362517 DQ Delay:
3529 13:15:16.365557 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3530 13:15:16.368737 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =111
3531 13:15:16.372013 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3532 13:15:16.375950 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
3533 13:15:16.376026
3534 13:15:16.376084
3535 13:15:16.376136 ==
3536 13:15:16.379199 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 13:15:16.386058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 13:15:16.386134 ==
3539 13:15:16.386192
3540 13:15:16.386246
3541 13:15:16.386296 TX Vref Scan disable
3542 13:15:16.388868 == TX Byte 0 ==
3543 13:15:16.392251 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3544 13:15:16.395849 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3545 13:15:16.399069 == TX Byte 1 ==
3546 13:15:16.402645 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3547 13:15:16.405589 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3548 13:15:16.409076 ==
3549 13:15:16.412132 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 13:15:16.415611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 13:15:16.415704 ==
3552 13:15:16.427062 TX Vref=22, minBit 1, minWin=25, winSum=416
3553 13:15:16.430541 TX Vref=24, minBit 0, minWin=25, winSum=417
3554 13:15:16.433747 TX Vref=26, minBit 0, minWin=26, winSum=423
3555 13:15:16.436778 TX Vref=28, minBit 15, minWin=25, winSum=430
3556 13:15:16.441096 TX Vref=30, minBit 4, minWin=26, winSum=430
3557 13:15:16.447052 TX Vref=32, minBit 13, minWin=25, winSum=428
3558 13:15:16.450342 [TxChooseVref] Worse bit 4, Min win 26, Win sum 430, Final Vref 30
3559 13:15:16.450486
3560 13:15:16.453627 Final TX Range 1 Vref 30
3561 13:15:16.453776
3562 13:15:16.453864 ==
3563 13:15:16.457015 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 13:15:16.460534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 13:15:16.460611 ==
3566 13:15:16.463859
3567 13:15:16.463934
3568 13:15:16.463992 TX Vref Scan disable
3569 13:15:16.466994 == TX Byte 0 ==
3570 13:15:16.471115 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3571 13:15:16.474032 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3572 13:15:16.477101 == TX Byte 1 ==
3573 13:15:16.480536 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3574 13:15:16.483809 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3575 13:15:16.487103
3576 13:15:16.487178 [DATLAT]
3577 13:15:16.487237 Freq=1200, CH1 RK1
3578 13:15:16.487291
3579 13:15:16.490304 DATLAT Default: 0xd
3580 13:15:16.490380 0, 0xFFFF, sum = 0
3581 13:15:16.493898 1, 0xFFFF, sum = 0
3582 13:15:16.493975 2, 0xFFFF, sum = 0
3583 13:15:16.496781 3, 0xFFFF, sum = 0
3584 13:15:16.496857 4, 0xFFFF, sum = 0
3585 13:15:16.500906 5, 0xFFFF, sum = 0
3586 13:15:16.500983 6, 0xFFFF, sum = 0
3587 13:15:16.504034 7, 0xFFFF, sum = 0
3588 13:15:16.507192 8, 0xFFFF, sum = 0
3589 13:15:16.507268 9, 0xFFFF, sum = 0
3590 13:15:16.510505 10, 0xFFFF, sum = 0
3591 13:15:16.510581 11, 0xFFFF, sum = 0
3592 13:15:16.514189 12, 0x0, sum = 1
3593 13:15:16.514266 13, 0x0, sum = 2
3594 13:15:16.517030 14, 0x0, sum = 3
3595 13:15:16.517105 15, 0x0, sum = 4
3596 13:15:16.517205 best_step = 13
3597 13:15:16.517258
3598 13:15:16.520466 ==
3599 13:15:16.520540 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 13:15:16.527042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 13:15:16.527119 ==
3602 13:15:16.527177 RX Vref Scan: 0
3603 13:15:16.527230
3604 13:15:16.530755 RX Vref 0 -> 0, step: 1
3605 13:15:16.530830
3606 13:15:16.534220 RX Delay -21 -> 252, step: 4
3607 13:15:16.537246 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3608 13:15:16.540882 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3609 13:15:16.547823 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3610 13:15:16.550924 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3611 13:15:16.553993 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3612 13:15:16.557461 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3613 13:15:16.560813 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3614 13:15:16.567463 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3615 13:15:16.570978 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3616 13:15:16.574303 iDelay=191, Bit 9, Center 96 (31 ~ 162) 132
3617 13:15:16.577548 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3618 13:15:16.581159 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3619 13:15:16.587323 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3620 13:15:16.590913 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3621 13:15:16.594043 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3622 13:15:16.597012 iDelay=191, Bit 15, Center 118 (55 ~ 182) 128
3623 13:15:16.597088 ==
3624 13:15:16.600412 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 13:15:16.607059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 13:15:16.607135 ==
3627 13:15:16.607194 DQS Delay:
3628 13:15:16.607248 DQS0 = 0, DQS1 = 0
3629 13:15:16.610663 DQM Delay:
3630 13:15:16.610738 DQM0 = 113, DQM1 = 108
3631 13:15:16.613949 DQ Delay:
3632 13:15:16.617083 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3633 13:15:16.620678 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3634 13:15:16.623799 DQ8 =96, DQ9 =96, DQ10 =110, DQ11 =100
3635 13:15:16.627596 DQ12 =114, DQ13 =118, DQ14 =118, DQ15 =118
3636 13:15:16.627671
3637 13:15:16.627729
3638 13:15:16.633698 [DQSOSCAuto] RK1, (LSB)MR18= 0xfc03, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 411 ps
3639 13:15:16.637314 CH1 RK1: MR19=304, MR18=FC03
3640 13:15:16.644101 CH1_RK1: MR19=0x304, MR18=0xFC03, DQSOSC=408, MR23=63, INC=39, DEC=26
3641 13:15:16.647102 [RxdqsGatingPostProcess] freq 1200
3642 13:15:16.653765 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3643 13:15:16.657233 best DQS0 dly(2T, 0.5T) = (0, 11)
3644 13:15:16.657309 best DQS1 dly(2T, 0.5T) = (0, 11)
3645 13:15:16.661450 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3646 13:15:16.664103 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3647 13:15:16.667005 best DQS0 dly(2T, 0.5T) = (0, 11)
3648 13:15:16.670366 best DQS1 dly(2T, 0.5T) = (0, 11)
3649 13:15:16.674076 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3650 13:15:16.677545 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3651 13:15:16.680530 Pre-setting of DQS Precalculation
3652 13:15:16.687599 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3653 13:15:16.694223 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3654 13:15:16.700825 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3655 13:15:16.700904
3656 13:15:16.700994
3657 13:15:16.704393 [Calibration Summary] 2400 Mbps
3658 13:15:16.704468 CH 0, Rank 0
3659 13:15:16.707584 SW Impedance : PASS
3660 13:15:16.710847 DUTY Scan : NO K
3661 13:15:16.710925 ZQ Calibration : PASS
3662 13:15:16.714254 Jitter Meter : NO K
3663 13:15:16.714333 CBT Training : PASS
3664 13:15:16.717085 Write leveling : PASS
3665 13:15:16.720533 RX DQS gating : PASS
3666 13:15:16.720610 RX DQ/DQS(RDDQC) : PASS
3667 13:15:16.725037 TX DQ/DQS : PASS
3668 13:15:16.727276 RX DATLAT : PASS
3669 13:15:16.727353 RX DQ/DQS(Engine): PASS
3670 13:15:16.731170 TX OE : NO K
3671 13:15:16.731248 All Pass.
3672 13:15:16.731325
3673 13:15:16.734352 CH 0, Rank 1
3674 13:15:16.734429 SW Impedance : PASS
3675 13:15:16.737818 DUTY Scan : NO K
3676 13:15:16.740717 ZQ Calibration : PASS
3677 13:15:16.740795 Jitter Meter : NO K
3678 13:15:16.744185 CBT Training : PASS
3679 13:15:16.747698 Write leveling : PASS
3680 13:15:16.747778 RX DQS gating : PASS
3681 13:15:16.751077 RX DQ/DQS(RDDQC) : PASS
3682 13:15:16.751152 TX DQ/DQS : PASS
3683 13:15:16.754410 RX DATLAT : PASS
3684 13:15:16.757528 RX DQ/DQS(Engine): PASS
3685 13:15:16.757613 TX OE : NO K
3686 13:15:16.761086 All Pass.
3687 13:15:16.761206
3688 13:15:16.761265 CH 1, Rank 0
3689 13:15:16.764192 SW Impedance : PASS
3690 13:15:16.764266 DUTY Scan : NO K
3691 13:15:16.768147 ZQ Calibration : PASS
3692 13:15:16.770858 Jitter Meter : NO K
3693 13:15:16.770936 CBT Training : PASS
3694 13:15:16.774399 Write leveling : PASS
3695 13:15:16.777611 RX DQS gating : PASS
3696 13:15:16.777747 RX DQ/DQS(RDDQC) : PASS
3697 13:15:16.781044 TX DQ/DQS : PASS
3698 13:15:16.784535 RX DATLAT : PASS
3699 13:15:16.784612 RX DQ/DQS(Engine): PASS
3700 13:15:16.787372 TX OE : NO K
3701 13:15:16.787450 All Pass.
3702 13:15:16.787526
3703 13:15:16.791070 CH 1, Rank 1
3704 13:15:16.791148 SW Impedance : PASS
3705 13:15:16.794314 DUTY Scan : NO K
3706 13:15:16.797463 ZQ Calibration : PASS
3707 13:15:16.797540 Jitter Meter : NO K
3708 13:15:16.801088 CBT Training : PASS
3709 13:15:16.801174 Write leveling : PASS
3710 13:15:16.804474 RX DQS gating : PASS
3711 13:15:16.807891 RX DQ/DQS(RDDQC) : PASS
3712 13:15:16.807968 TX DQ/DQS : PASS
3713 13:15:16.810930 RX DATLAT : PASS
3714 13:15:16.814339 RX DQ/DQS(Engine): PASS
3715 13:15:16.814417 TX OE : NO K
3716 13:15:16.817452 All Pass.
3717 13:15:16.817529
3718 13:15:16.817604 DramC Write-DBI off
3719 13:15:16.821006 PER_BANK_REFRESH: Hybrid Mode
3720 13:15:16.821083 TX_TRACKING: ON
3721 13:15:16.831118 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3722 13:15:16.834723 [FAST_K] Save calibration result to emmc
3723 13:15:16.837649 dramc_set_vcore_voltage set vcore to 650000
3724 13:15:16.841046 Read voltage for 600, 5
3725 13:15:16.841147 Vio18 = 0
3726 13:15:16.844284 Vcore = 650000
3727 13:15:16.844361 Vdram = 0
3728 13:15:16.844437 Vddq = 0
3729 13:15:16.847541 Vmddr = 0
3730 13:15:16.851109 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3731 13:15:16.858014 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3732 13:15:16.858092 MEM_TYPE=3, freq_sel=19
3733 13:15:16.861103 sv_algorithm_assistance_LP4_1600
3734 13:15:16.864287 ============ PULL DRAM RESETB DOWN ============
3735 13:15:16.871238 ========== PULL DRAM RESETB DOWN end =========
3736 13:15:16.874332 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3737 13:15:16.877469 ===================================
3738 13:15:16.881041 LPDDR4 DRAM CONFIGURATION
3739 13:15:16.884344 ===================================
3740 13:15:16.884422 EX_ROW_EN[0] = 0x0
3741 13:15:16.887477 EX_ROW_EN[1] = 0x0
3742 13:15:16.887555 LP4Y_EN = 0x0
3743 13:15:16.891147 WORK_FSP = 0x0
3744 13:15:16.891225 WL = 0x2
3745 13:15:16.894566 RL = 0x2
3746 13:15:16.894643 BL = 0x2
3747 13:15:16.897586 RPST = 0x0
3748 13:15:16.901146 RD_PRE = 0x0
3749 13:15:16.901238 WR_PRE = 0x1
3750 13:15:16.904595 WR_PST = 0x0
3751 13:15:16.904672 DBI_WR = 0x0
3752 13:15:16.907675 DBI_RD = 0x0
3753 13:15:16.907753 OTF = 0x1
3754 13:15:16.910871 ===================================
3755 13:15:16.914628 ===================================
3756 13:15:16.914705 ANA top config
3757 13:15:16.917698 ===================================
3758 13:15:16.921176 DLL_ASYNC_EN = 0
3759 13:15:16.924563 ALL_SLAVE_EN = 1
3760 13:15:16.928056 NEW_RANK_MODE = 1
3761 13:15:16.931344 DLL_IDLE_MODE = 1
3762 13:15:16.931422 LP45_APHY_COMB_EN = 1
3763 13:15:16.934434 TX_ODT_DIS = 1
3764 13:15:16.937749 NEW_8X_MODE = 1
3765 13:15:16.941153 ===================================
3766 13:15:16.944482 ===================================
3767 13:15:16.947749 data_rate = 1200
3768 13:15:16.951188 CKR = 1
3769 13:15:16.951266 DQ_P2S_RATIO = 8
3770 13:15:16.954631 ===================================
3771 13:15:16.958140 CA_P2S_RATIO = 8
3772 13:15:16.961554 DQ_CA_OPEN = 0
3773 13:15:16.964778 DQ_SEMI_OPEN = 0
3774 13:15:16.968006 CA_SEMI_OPEN = 0
3775 13:15:16.968084 CA_FULL_RATE = 0
3776 13:15:16.971262 DQ_CKDIV4_EN = 1
3777 13:15:16.974657 CA_CKDIV4_EN = 1
3778 13:15:16.977677 CA_PREDIV_EN = 0
3779 13:15:16.981104 PH8_DLY = 0
3780 13:15:16.984289 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3781 13:15:16.984367 DQ_AAMCK_DIV = 4
3782 13:15:16.988010 CA_AAMCK_DIV = 4
3783 13:15:16.991289 CA_ADMCK_DIV = 4
3784 13:15:16.994921 DQ_TRACK_CA_EN = 0
3785 13:15:16.997620 CA_PICK = 600
3786 13:15:17.001361 CA_MCKIO = 600
3787 13:15:17.004271 MCKIO_SEMI = 0
3788 13:15:17.004348 PLL_FREQ = 2288
3789 13:15:17.007940 DQ_UI_PI_RATIO = 32
3790 13:15:17.011159 CA_UI_PI_RATIO = 0
3791 13:15:17.014630 ===================================
3792 13:15:17.018099 ===================================
3793 13:15:17.021424 memory_type:LPDDR4
3794 13:15:17.021501 GP_NUM : 10
3795 13:15:17.024402 SRAM_EN : 1
3796 13:15:17.028142 MD32_EN : 0
3797 13:15:17.031243 ===================================
3798 13:15:17.031320 [ANA_INIT] >>>>>>>>>>>>>>
3799 13:15:17.034541 <<<<<< [CONFIGURE PHASE]: ANA_TX
3800 13:15:17.038029 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3801 13:15:17.041091 ===================================
3802 13:15:17.044747 data_rate = 1200,PCW = 0X5800
3803 13:15:17.047709 ===================================
3804 13:15:17.051317 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3805 13:15:17.057858 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3806 13:15:17.061465 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3807 13:15:17.068050 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3808 13:15:17.071096 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3809 13:15:17.074775 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3810 13:15:17.074852 [ANA_INIT] flow start
3811 13:15:17.078014 [ANA_INIT] PLL >>>>>>>>
3812 13:15:17.081284 [ANA_INIT] PLL <<<<<<<<
3813 13:15:17.081362 [ANA_INIT] MIDPI >>>>>>>>
3814 13:15:17.084899 [ANA_INIT] MIDPI <<<<<<<<
3815 13:15:17.088225 [ANA_INIT] DLL >>>>>>>>
3816 13:15:17.088302 [ANA_INIT] flow end
3817 13:15:17.094625 ============ LP4 DIFF to SE enter ============
3818 13:15:17.098191 ============ LP4 DIFF to SE exit ============
3819 13:15:17.101386 [ANA_INIT] <<<<<<<<<<<<<
3820 13:15:17.104509 [Flow] Enable top DCM control >>>>>
3821 13:15:17.107808 [Flow] Enable top DCM control <<<<<
3822 13:15:17.107885 Enable DLL master slave shuffle
3823 13:15:17.115084 ==============================================================
3824 13:15:17.118181 Gating Mode config
3825 13:15:17.121332 ==============================================================
3826 13:15:17.124719 Config description:
3827 13:15:17.134665 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3828 13:15:17.141268 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3829 13:15:17.144596 SELPH_MODE 0: By rank 1: By Phase
3830 13:15:17.151549 ==============================================================
3831 13:15:17.154695 GAT_TRACK_EN = 1
3832 13:15:17.158233 RX_GATING_MODE = 2
3833 13:15:17.161033 RX_GATING_TRACK_MODE = 2
3834 13:15:17.161172 SELPH_MODE = 1
3835 13:15:17.164690 PICG_EARLY_EN = 1
3836 13:15:17.167906 VALID_LAT_VALUE = 1
3837 13:15:17.175066 ==============================================================
3838 13:15:17.178165 Enter into Gating configuration >>>>
3839 13:15:17.181389 Exit from Gating configuration <<<<
3840 13:15:17.184433 Enter into DVFS_PRE_config >>>>>
3841 13:15:17.194717 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3842 13:15:17.197779 Exit from DVFS_PRE_config <<<<<
3843 13:15:17.201074 Enter into PICG configuration >>>>
3844 13:15:17.204310 Exit from PICG configuration <<<<
3845 13:15:17.207972 [RX_INPUT] configuration >>>>>
3846 13:15:17.211628 [RX_INPUT] configuration <<<<<
3847 13:15:17.214723 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3848 13:15:17.221543 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3849 13:15:17.227970 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3850 13:15:17.234596 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3851 13:15:17.238391 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3852 13:15:17.244335 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3853 13:15:17.247942 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3854 13:15:17.254120 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3855 13:15:17.257785 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3856 13:15:17.260937 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3857 13:15:17.264470 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3858 13:15:17.271155 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3859 13:15:17.274262 ===================================
3860 13:15:17.274337 LPDDR4 DRAM CONFIGURATION
3861 13:15:17.278176 ===================================
3862 13:15:17.280765 EX_ROW_EN[0] = 0x0
3863 13:15:17.283905 EX_ROW_EN[1] = 0x0
3864 13:15:17.283979 LP4Y_EN = 0x0
3865 13:15:17.287424 WORK_FSP = 0x0
3866 13:15:17.287499 WL = 0x2
3867 13:15:17.290734 RL = 0x2
3868 13:15:17.290809 BL = 0x2
3869 13:15:17.294278 RPST = 0x0
3870 13:15:17.294352 RD_PRE = 0x0
3871 13:15:17.297302 WR_PRE = 0x1
3872 13:15:17.297376 WR_PST = 0x0
3873 13:15:17.301413 DBI_WR = 0x0
3874 13:15:17.301488 DBI_RD = 0x0
3875 13:15:17.303984 OTF = 0x1
3876 13:15:17.307357 ===================================
3877 13:15:17.310689 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3878 13:15:17.313901 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3879 13:15:17.321019 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3880 13:15:17.324267 ===================================
3881 13:15:17.324352 LPDDR4 DRAM CONFIGURATION
3882 13:15:17.327202 ===================================
3883 13:15:17.330879 EX_ROW_EN[0] = 0x10
3884 13:15:17.333961 EX_ROW_EN[1] = 0x0
3885 13:15:17.334036 LP4Y_EN = 0x0
3886 13:15:17.337586 WORK_FSP = 0x0
3887 13:15:17.337661 WL = 0x2
3888 13:15:17.340676 RL = 0x2
3889 13:15:17.340750 BL = 0x2
3890 13:15:17.343755 RPST = 0x0
3891 13:15:17.343829 RD_PRE = 0x0
3892 13:15:17.346828 WR_PRE = 0x1
3893 13:15:17.346903 WR_PST = 0x0
3894 13:15:17.350214 DBI_WR = 0x0
3895 13:15:17.350288 DBI_RD = 0x0
3896 13:15:17.353883 OTF = 0x1
3897 13:15:17.357055 ===================================
3898 13:15:17.363774 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3899 13:15:17.367359 nWR fixed to 30
3900 13:15:17.371028 [ModeRegInit_LP4] CH0 RK0
3901 13:15:17.371122 [ModeRegInit_LP4] CH0 RK1
3902 13:15:17.373807 [ModeRegInit_LP4] CH1 RK0
3903 13:15:17.377123 [ModeRegInit_LP4] CH1 RK1
3904 13:15:17.377199 match AC timing 17
3905 13:15:17.383659 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3906 13:15:17.387272 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3907 13:15:17.390636 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3908 13:15:17.397111 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3909 13:15:17.400962 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3910 13:15:17.401038 ==
3911 13:15:17.404052 Dram Type= 6, Freq= 0, CH_0, rank 0
3912 13:15:17.407420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3913 13:15:17.407496 ==
3914 13:15:17.413855 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3915 13:15:17.420180 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3916 13:15:17.424066 [CA 0] Center 36 (6~67) winsize 62
3917 13:15:17.427264 [CA 1] Center 36 (6~66) winsize 61
3918 13:15:17.430602 [CA 2] Center 34 (4~65) winsize 62
3919 13:15:17.433671 [CA 3] Center 34 (4~65) winsize 62
3920 13:15:17.437223 [CA 4] Center 34 (4~64) winsize 61
3921 13:15:17.440730 [CA 5] Center 33 (3~64) winsize 62
3922 13:15:17.440807
3923 13:15:17.444131 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3924 13:15:17.444208
3925 13:15:17.447441 [CATrainingPosCal] consider 1 rank data
3926 13:15:17.450788 u2DelayCellTimex100 = 270/100 ps
3927 13:15:17.454422 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3928 13:15:17.456914 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3929 13:15:17.460293 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3930 13:15:17.463703 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3931 13:15:17.467295 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3932 13:15:17.470553 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3933 13:15:17.470631
3934 13:15:17.474082 CA PerBit enable=1, Macro0, CA PI delay=33
3935 13:15:17.477063
3936 13:15:17.477162 [CBTSetCACLKResult] CA Dly = 33
3937 13:15:17.480320 CS Dly: 5 (0~36)
3938 13:15:17.480397 ==
3939 13:15:17.483650 Dram Type= 6, Freq= 0, CH_0, rank 1
3940 13:15:17.486901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3941 13:15:17.486980 ==
3942 13:15:17.493909 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3943 13:15:17.500601 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3944 13:15:17.503693 [CA 0] Center 35 (5~66) winsize 62
3945 13:15:17.506897 [CA 1] Center 35 (5~66) winsize 62
3946 13:15:17.510537 [CA 2] Center 34 (4~65) winsize 62
3947 13:15:17.513900 [CA 3] Center 34 (4~65) winsize 62
3948 13:15:17.517068 [CA 4] Center 34 (3~65) winsize 63
3949 13:15:17.520620 [CA 5] Center 34 (3~65) winsize 63
3950 13:15:17.520698
3951 13:15:17.523622 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3952 13:15:17.523700
3953 13:15:17.527041 [CATrainingPosCal] consider 2 rank data
3954 13:15:17.530196 u2DelayCellTimex100 = 270/100 ps
3955 13:15:17.533769 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3956 13:15:17.537071 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3957 13:15:17.540297 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3958 13:15:17.543691 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3959 13:15:17.546953 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3960 13:15:17.550585 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3961 13:15:17.550663
3962 13:15:17.557554 CA PerBit enable=1, Macro0, CA PI delay=33
3963 13:15:17.557631
3964 13:15:17.557707 [CBTSetCACLKResult] CA Dly = 33
3965 13:15:17.560544 CS Dly: 5 (0~36)
3966 13:15:17.560622
3967 13:15:17.564022 ----->DramcWriteLeveling(PI) begin...
3968 13:15:17.564101 ==
3969 13:15:17.567423 Dram Type= 6, Freq= 0, CH_0, rank 0
3970 13:15:17.570295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 13:15:17.570374 ==
3972 13:15:17.573810 Write leveling (Byte 0): 32 => 32
3973 13:15:17.577212 Write leveling (Byte 1): 30 => 30
3974 13:15:17.580241 DramcWriteLeveling(PI) end<-----
3975 13:15:17.580318
3976 13:15:17.580395 ==
3977 13:15:17.583724 Dram Type= 6, Freq= 0, CH_0, rank 0
3978 13:15:17.587130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3979 13:15:17.587209 ==
3980 13:15:17.590982 [Gating] SW mode calibration
3981 13:15:17.597076 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3982 13:15:17.603886 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3983 13:15:17.606921 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 13:15:17.613636 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3985 13:15:17.617094 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3986 13:15:17.620770 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3987 13:15:17.627498 0 9 16 | B1->B0 | 3131 2f2f | 0 0 | (0 1) (1 1)
3988 13:15:17.631553 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 13:15:17.633974 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 13:15:17.636948 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 13:15:17.643894 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 13:15:17.647679 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 13:15:17.650758 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 13:15:17.657528 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 13:15:17.660689 0 10 16 | B1->B0 | 2f2f 4545 | 0 0 | (1 1) (0 0)
3996 13:15:17.663902 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 13:15:17.670362 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 13:15:17.674105 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 13:15:17.677397 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 13:15:17.684033 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 13:15:17.687436 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 13:15:17.690300 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 13:15:17.697434 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 13:15:17.700453 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 13:15:17.704269 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 13:15:17.707363 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 13:15:17.714106 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 13:15:17.717684 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 13:15:17.720805 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 13:15:17.727406 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 13:15:17.730819 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 13:15:17.734105 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 13:15:17.740929 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 13:15:17.744063 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 13:15:17.747278 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 13:15:17.753898 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 13:15:17.757443 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 13:15:17.760606 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 13:15:17.767512 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4020 13:15:17.767590 Total UI for P1: 0, mck2ui 16
4021 13:15:17.774219 best dqsien dly found for B0: ( 0, 13, 14)
4022 13:15:17.777569 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 13:15:17.781015 Total UI for P1: 0, mck2ui 16
4024 13:15:17.783934 best dqsien dly found for B1: ( 0, 13, 16)
4025 13:15:17.787163 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4026 13:15:17.790740 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4027 13:15:17.790816
4028 13:15:17.793708 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4029 13:15:17.797347 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4030 13:15:17.800560 [Gating] SW calibration Done
4031 13:15:17.800635 ==
4032 13:15:17.803701 Dram Type= 6, Freq= 0, CH_0, rank 0
4033 13:15:17.807176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4034 13:15:17.810358 ==
4035 13:15:17.810434 RX Vref Scan: 0
4036 13:15:17.810493
4037 13:15:17.813815 RX Vref 0 -> 0, step: 1
4038 13:15:17.813891
4039 13:15:17.816719 RX Delay -230 -> 252, step: 16
4040 13:15:17.820187 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4041 13:15:17.823568 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4042 13:15:17.827055 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4043 13:15:17.833592 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4044 13:15:17.837266 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4045 13:15:17.840425 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4046 13:15:17.843726 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4047 13:15:17.847247 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4048 13:15:17.853726 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4049 13:15:17.857080 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4050 13:15:17.860838 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4051 13:15:17.863987 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4052 13:15:17.870948 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4053 13:15:17.873657 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4054 13:15:17.877355 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4055 13:15:17.880025 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4056 13:15:17.880101 ==
4057 13:15:17.883975 Dram Type= 6, Freq= 0, CH_0, rank 0
4058 13:15:17.890503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4059 13:15:17.890583 ==
4060 13:15:17.890642 DQS Delay:
4061 13:15:17.890696 DQS0 = 0, DQS1 = 0
4062 13:15:17.893429 DQM Delay:
4063 13:15:17.893505 DQM0 = 41, DQM1 = 32
4064 13:15:17.896855 DQ Delay:
4065 13:15:17.900276 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4066 13:15:17.904023 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4067 13:15:17.906972 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4068 13:15:17.910159 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4069 13:15:17.910234
4070 13:15:17.910293
4071 13:15:17.910346 ==
4072 13:15:17.913790 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 13:15:17.916793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 13:15:17.916892 ==
4075 13:15:17.916976
4076 13:15:17.917055
4077 13:15:17.920410 TX Vref Scan disable
4078 13:15:17.920485 == TX Byte 0 ==
4079 13:15:17.926651 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4080 13:15:17.930012 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4081 13:15:17.930088 == TX Byte 1 ==
4082 13:15:17.937546 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4083 13:15:17.940087 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4084 13:15:17.940164 ==
4085 13:15:17.943406 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 13:15:17.946920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 13:15:17.946996 ==
4088 13:15:17.947054
4089 13:15:17.947107
4090 13:15:17.950032 TX Vref Scan disable
4091 13:15:17.953374 == TX Byte 0 ==
4092 13:15:17.956809 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4093 13:15:17.963575 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4094 13:15:17.963652 == TX Byte 1 ==
4095 13:15:17.967019 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4096 13:15:17.970153 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4097 13:15:17.973630
4098 13:15:17.973705 [DATLAT]
4099 13:15:17.973763 Freq=600, CH0 RK0
4100 13:15:17.973817
4101 13:15:17.976799 DATLAT Default: 0x9
4102 13:15:17.976874 0, 0xFFFF, sum = 0
4103 13:15:17.981048 1, 0xFFFF, sum = 0
4104 13:15:17.981163 2, 0xFFFF, sum = 0
4105 13:15:17.983550 3, 0xFFFF, sum = 0
4106 13:15:17.983626 4, 0xFFFF, sum = 0
4107 13:15:17.986791 5, 0xFFFF, sum = 0
4108 13:15:17.990813 6, 0xFFFF, sum = 0
4109 13:15:17.990890 7, 0xFFFF, sum = 0
4110 13:15:17.990950 8, 0x0, sum = 1
4111 13:15:17.993540 9, 0x0, sum = 2
4112 13:15:17.993618 10, 0x0, sum = 3
4113 13:15:17.996638 11, 0x0, sum = 4
4114 13:15:17.996714 best_step = 9
4115 13:15:17.996773
4116 13:15:17.996827 ==
4117 13:15:18.000175 Dram Type= 6, Freq= 0, CH_0, rank 0
4118 13:15:18.006910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4119 13:15:18.006988 ==
4120 13:15:18.007047 RX Vref Scan: 1
4121 13:15:18.007100
4122 13:15:18.010058 RX Vref 0 -> 0, step: 1
4123 13:15:18.010134
4124 13:15:18.013409 RX Delay -195 -> 252, step: 8
4125 13:15:18.013508
4126 13:15:18.016906 Set Vref, RX VrefLevel [Byte0]: 54
4127 13:15:18.019879 [Byte1]: 51
4128 13:15:18.019955
4129 13:15:18.023675 Final RX Vref Byte 0 = 54 to rank0
4130 13:15:18.026715 Final RX Vref Byte 1 = 51 to rank0
4131 13:15:18.030251 Final RX Vref Byte 0 = 54 to rank1
4132 13:15:18.033509 Final RX Vref Byte 1 = 51 to rank1==
4133 13:15:18.036965 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 13:15:18.040014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 13:15:18.040091 ==
4136 13:15:18.043409 DQS Delay:
4137 13:15:18.043484 DQS0 = 0, DQS1 = 0
4138 13:15:18.043547 DQM Delay:
4139 13:15:18.046843 DQM0 = 42, DQM1 = 33
4140 13:15:18.046918 DQ Delay:
4141 13:15:18.050486 DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40
4142 13:15:18.053983 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4143 13:15:18.056898 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4144 13:15:18.060604 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4145 13:15:18.060681
4146 13:15:18.060739
4147 13:15:18.070467 [DQSOSCAuto] RK0, (LSB)MR18= 0x4220, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
4148 13:15:18.070546 CH0 RK0: MR19=808, MR18=4220
4149 13:15:18.076972 CH0_RK0: MR19=0x808, MR18=0x4220, DQSOSC=397, MR23=63, INC=166, DEC=110
4150 13:15:18.077072
4151 13:15:18.080578 ----->DramcWriteLeveling(PI) begin...
4152 13:15:18.080679 ==
4153 13:15:18.084034 Dram Type= 6, Freq= 0, CH_0, rank 1
4154 13:15:18.090569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 13:15:18.090669 ==
4156 13:15:18.093920 Write leveling (Byte 0): 32 => 32
4157 13:15:18.096881 Write leveling (Byte 1): 29 => 29
4158 13:15:18.096957 DramcWriteLeveling(PI) end<-----
4159 13:15:18.097016
4160 13:15:18.100328 ==
4161 13:15:18.103767 Dram Type= 6, Freq= 0, CH_0, rank 1
4162 13:15:18.107252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4163 13:15:18.107328 ==
4164 13:15:18.110392 [Gating] SW mode calibration
4165 13:15:18.117078 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4166 13:15:18.120481 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4167 13:15:18.127102 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4168 13:15:18.130466 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4169 13:15:18.133689 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4170 13:15:18.140125 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (0 1)
4171 13:15:18.144041 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
4172 13:15:18.146964 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 13:15:18.153885 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 13:15:18.157065 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 13:15:18.160602 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 13:15:18.163774 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 13:15:18.170354 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 13:15:18.174317 0 10 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
4179 13:15:18.177729 0 10 16 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
4180 13:15:18.184152 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 13:15:18.187235 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 13:15:18.190591 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 13:15:18.196951 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 13:15:18.200655 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 13:15:18.204043 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 13:15:18.211081 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4187 13:15:18.213691 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4188 13:15:18.217351 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 13:15:18.223917 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 13:15:18.227114 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 13:15:18.230996 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 13:15:18.236955 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 13:15:18.240758 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 13:15:18.243864 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 13:15:18.250618 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 13:15:18.253955 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 13:15:18.257277 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 13:15:18.260558 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 13:15:18.267105 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 13:15:18.270856 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 13:15:18.273946 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 13:15:18.280577 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4203 13:15:18.283820 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4204 13:15:18.287371 Total UI for P1: 0, mck2ui 16
4205 13:15:18.290895 best dqsien dly found for B0: ( 0, 13, 12)
4206 13:15:18.294325 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 13:15:18.297472 Total UI for P1: 0, mck2ui 16
4208 13:15:18.300888 best dqsien dly found for B1: ( 0, 13, 16)
4209 13:15:18.304538 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4210 13:15:18.307661 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4211 13:15:18.307738
4212 13:15:18.310656 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4213 13:15:18.317903 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4214 13:15:18.317980 [Gating] SW calibration Done
4215 13:15:18.321017 ==
4216 13:15:18.321093 Dram Type= 6, Freq= 0, CH_0, rank 1
4217 13:15:18.327603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4218 13:15:18.327681 ==
4219 13:15:18.327740 RX Vref Scan: 0
4220 13:15:18.327794
4221 13:15:18.331191 RX Vref 0 -> 0, step: 1
4222 13:15:18.331267
4223 13:15:18.334365 RX Delay -230 -> 252, step: 16
4224 13:15:18.337314 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4225 13:15:18.341091 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4226 13:15:18.347405 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4227 13:15:18.350734 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4228 13:15:18.354367 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4229 13:15:18.357469 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4230 13:15:18.361112 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4231 13:15:18.367591 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4232 13:15:18.371155 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4233 13:15:18.374167 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4234 13:15:18.377470 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4235 13:15:18.380990 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4236 13:15:18.387832 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4237 13:15:18.391412 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4238 13:15:18.394552 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4239 13:15:18.397541 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4240 13:15:18.400891 ==
4241 13:15:18.400968 Dram Type= 6, Freq= 0, CH_0, rank 1
4242 13:15:18.407752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4243 13:15:18.407829 ==
4244 13:15:18.407888 DQS Delay:
4245 13:15:18.410974 DQS0 = 0, DQS1 = 0
4246 13:15:18.411051 DQM Delay:
4247 13:15:18.414713 DQM0 = 39, DQM1 = 31
4248 13:15:18.414789 DQ Delay:
4249 13:15:18.418348 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4250 13:15:18.421278 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4251 13:15:18.424649 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4252 13:15:18.427962 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4253 13:15:18.428037
4254 13:15:18.428095
4255 13:15:18.428147 ==
4256 13:15:18.431215 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 13:15:18.434781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 13:15:18.434857 ==
4259 13:15:18.434915
4260 13:15:18.434968
4261 13:15:18.437702 TX Vref Scan disable
4262 13:15:18.441461 == TX Byte 0 ==
4263 13:15:18.444684 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4264 13:15:18.448188 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4265 13:15:18.448279 == TX Byte 1 ==
4266 13:15:18.454691 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4267 13:15:18.458233 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4268 13:15:18.458308 ==
4269 13:15:18.461107 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 13:15:18.464500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 13:15:18.464584 ==
4272 13:15:18.464649
4273 13:15:18.468359
4274 13:15:18.468434 TX Vref Scan disable
4275 13:15:18.471682 == TX Byte 0 ==
4276 13:15:18.474818 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4277 13:15:18.478025 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4278 13:15:18.481899 == TX Byte 1 ==
4279 13:15:18.484779 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4280 13:15:18.488326 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4281 13:15:18.491321
4282 13:15:18.491396 [DATLAT]
4283 13:15:18.491454 Freq=600, CH0 RK1
4284 13:15:18.491508
4285 13:15:18.495310 DATLAT Default: 0x9
4286 13:15:18.495386 0, 0xFFFF, sum = 0
4287 13:15:18.498781 1, 0xFFFF, sum = 0
4288 13:15:18.498858 2, 0xFFFF, sum = 0
4289 13:15:18.501392 3, 0xFFFF, sum = 0
4290 13:15:18.501476 4, 0xFFFF, sum = 0
4291 13:15:18.505036 5, 0xFFFF, sum = 0
4292 13:15:18.505112 6, 0xFFFF, sum = 0
4293 13:15:18.507953 7, 0xFFFF, sum = 0
4294 13:15:18.508030 8, 0x0, sum = 1
4295 13:15:18.511534 9, 0x0, sum = 2
4296 13:15:18.511613 10, 0x0, sum = 3
4297 13:15:18.514902 11, 0x0, sum = 4
4298 13:15:18.514993 best_step = 9
4299 13:15:18.515074
4300 13:15:18.515160 ==
4301 13:15:18.517986 Dram Type= 6, Freq= 0, CH_0, rank 1
4302 13:15:18.524545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4303 13:15:18.524621 ==
4304 13:15:18.524679 RX Vref Scan: 0
4305 13:15:18.524733
4306 13:15:18.528420 RX Vref 0 -> 0, step: 1
4307 13:15:18.528495
4308 13:15:18.531345 RX Delay -195 -> 252, step: 8
4309 13:15:18.534861 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4310 13:15:18.541160 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4311 13:15:18.544775 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4312 13:15:18.548405 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4313 13:15:18.551320 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4314 13:15:18.554803 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4315 13:15:18.561061 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4316 13:15:18.565072 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4317 13:15:18.568269 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4318 13:15:18.571583 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4319 13:15:18.578007 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4320 13:15:18.581488 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4321 13:15:18.584796 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4322 13:15:18.588301 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4323 13:15:18.591385 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4324 13:15:18.598343 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4325 13:15:18.598420 ==
4326 13:15:18.601604 Dram Type= 6, Freq= 0, CH_0, rank 1
4327 13:15:18.605016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4328 13:15:18.605092 ==
4329 13:15:18.605190 DQS Delay:
4330 13:15:18.607935 DQS0 = 0, DQS1 = 0
4331 13:15:18.608010 DQM Delay:
4332 13:15:18.611507 DQM0 = 40, DQM1 = 33
4333 13:15:18.611582 DQ Delay:
4334 13:15:18.614872 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4335 13:15:18.618145 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4336 13:15:18.621236 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =20
4337 13:15:18.624434 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4338 13:15:18.624509
4339 13:15:18.624566
4340 13:15:18.634862 [DQSOSCAuto] RK1, (LSB)MR18= 0x5032, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4341 13:15:18.634940 CH0 RK1: MR19=808, MR18=5032
4342 13:15:18.641683 CH0_RK1: MR19=0x808, MR18=0x5032, DQSOSC=394, MR23=63, INC=168, DEC=112
4343 13:15:18.644658 [RxdqsGatingPostProcess] freq 600
4344 13:15:18.651198 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4345 13:15:18.654490 Pre-setting of DQS Precalculation
4346 13:15:18.657781 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4347 13:15:18.657856 ==
4348 13:15:18.661248 Dram Type= 6, Freq= 0, CH_1, rank 0
4349 13:15:18.664321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 13:15:18.667885 ==
4351 13:15:18.671027 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4352 13:15:18.677527 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4353 13:15:18.681071 [CA 0] Center 35 (5~66) winsize 62
4354 13:15:18.684135 [CA 1] Center 35 (5~66) winsize 62
4355 13:15:18.687612 [CA 2] Center 34 (4~65) winsize 62
4356 13:15:18.691139 [CA 3] Center 33 (3~64) winsize 62
4357 13:15:18.694565 [CA 4] Center 34 (3~65) winsize 63
4358 13:15:18.697688 [CA 5] Center 33 (2~64) winsize 63
4359 13:15:18.697763
4360 13:15:18.701105 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4361 13:15:18.701238
4362 13:15:18.704641 [CATrainingPosCal] consider 1 rank data
4363 13:15:18.707516 u2DelayCellTimex100 = 270/100 ps
4364 13:15:18.710818 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4365 13:15:18.714638 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4366 13:15:18.718285 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4367 13:15:18.721402 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4368 13:15:18.727663 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4369 13:15:18.731279 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4370 13:15:18.731355
4371 13:15:18.734403 CA PerBit enable=1, Macro0, CA PI delay=33
4372 13:15:18.734478
4373 13:15:18.738194 [CBTSetCACLKResult] CA Dly = 33
4374 13:15:18.738270 CS Dly: 4 (0~35)
4375 13:15:18.738328 ==
4376 13:15:18.741449 Dram Type= 6, Freq= 0, CH_1, rank 1
4377 13:15:18.744346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 13:15:18.747469 ==
4379 13:15:18.751532 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4380 13:15:18.757589 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4381 13:15:18.761393 [CA 0] Center 35 (5~66) winsize 62
4382 13:15:18.764214 [CA 1] Center 35 (5~66) winsize 62
4383 13:15:18.768016 [CA 2] Center 34 (4~65) winsize 62
4384 13:15:18.771245 [CA 3] Center 33 (3~64) winsize 62
4385 13:15:18.774290 [CA 4] Center 34 (4~65) winsize 62
4386 13:15:18.777506 [CA 5] Center 33 (3~64) winsize 62
4387 13:15:18.777585
4388 13:15:18.781041 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4389 13:15:18.781126
4390 13:15:18.785042 [CATrainingPosCal] consider 2 rank data
4391 13:15:18.788035 u2DelayCellTimex100 = 270/100 ps
4392 13:15:18.791096 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4393 13:15:18.794570 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4394 13:15:18.797736 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4395 13:15:18.800907 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4396 13:15:18.807881 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4397 13:15:18.810983 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4398 13:15:18.811061
4399 13:15:18.814202 CA PerBit enable=1, Macro0, CA PI delay=33
4400 13:15:18.814279
4401 13:15:18.817948 [CBTSetCACLKResult] CA Dly = 33
4402 13:15:18.818025 CS Dly: 5 (0~37)
4403 13:15:18.818084
4404 13:15:18.820840 ----->DramcWriteLeveling(PI) begin...
4405 13:15:18.820918 ==
4406 13:15:18.824327 Dram Type= 6, Freq= 0, CH_1, rank 0
4407 13:15:18.831063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 13:15:18.831188 ==
4409 13:15:18.834601 Write leveling (Byte 0): 30 => 30
4410 13:15:18.834746 Write leveling (Byte 1): 30 => 30
4411 13:15:18.837685 DramcWriteLeveling(PI) end<-----
4412 13:15:18.837761
4413 13:15:18.840759 ==
4414 13:15:18.840835 Dram Type= 6, Freq= 0, CH_1, rank 0
4415 13:15:18.848101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 13:15:18.848179 ==
4417 13:15:18.850921 [Gating] SW mode calibration
4418 13:15:18.857563 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4419 13:15:18.861292 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4420 13:15:18.867640 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4421 13:15:18.871446 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4422 13:15:18.874709 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4423 13:15:18.881152 0 9 12 | B1->B0 | 3333 3232 | 1 1 | (1 0) (1 0)
4424 13:15:18.884510 0 9 16 | B1->B0 | 2e2e 2929 | 0 0 | (1 1) (1 0)
4425 13:15:18.888050 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 13:15:18.891594 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 13:15:18.898035 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 13:15:18.901090 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 13:15:18.904390 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4430 13:15:18.910965 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 13:15:18.914430 0 10 12 | B1->B0 | 2727 2727 | 0 0 | (0 0) (0 0)
4432 13:15:18.917777 0 10 16 | B1->B0 | 3c3c 4040 | 0 0 | (0 0) (0 0)
4433 13:15:18.924371 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 13:15:18.927966 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 13:15:18.931054 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 13:15:18.937638 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 13:15:18.941312 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 13:15:18.945144 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 13:15:18.950907 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4440 13:15:18.954675 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4441 13:15:18.958307 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 13:15:18.964263 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 13:15:18.967875 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 13:15:18.972060 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 13:15:18.974964 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 13:15:18.981032 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 13:15:18.984966 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 13:15:18.987868 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 13:15:18.994638 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 13:15:18.998308 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 13:15:19.001566 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 13:15:19.007922 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 13:15:19.011618 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 13:15:19.014766 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 13:15:19.021820 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4456 13:15:19.025295 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 13:15:19.028542 Total UI for P1: 0, mck2ui 16
4458 13:15:19.031344 best dqsien dly found for B0: ( 0, 13, 12)
4459 13:15:19.034996 Total UI for P1: 0, mck2ui 16
4460 13:15:19.038169 best dqsien dly found for B1: ( 0, 13, 14)
4461 13:15:19.041797 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4462 13:15:19.044864 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4463 13:15:19.044940
4464 13:15:19.048379 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4465 13:15:19.051737 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4466 13:15:19.054906 [Gating] SW calibration Done
4467 13:15:19.054982 ==
4468 13:15:19.058808 Dram Type= 6, Freq= 0, CH_1, rank 0
4469 13:15:19.062795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4470 13:15:19.062877 ==
4471 13:15:19.065113 RX Vref Scan: 0
4472 13:15:19.065227
4473 13:15:19.068432 RX Vref 0 -> 0, step: 1
4474 13:15:19.068508
4475 13:15:19.068566 RX Delay -230 -> 252, step: 16
4476 13:15:19.075175 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4477 13:15:19.078553 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4478 13:15:19.081526 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4479 13:15:19.085087 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4480 13:15:19.091982 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4481 13:15:19.095141 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4482 13:15:19.098541 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4483 13:15:19.101911 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4484 13:15:19.105039 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4485 13:15:19.111917 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4486 13:15:19.114834 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4487 13:15:19.118194 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4488 13:15:19.121590 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4489 13:15:19.128039 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4490 13:15:19.131388 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4491 13:15:19.134858 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4492 13:15:19.134935 ==
4493 13:15:19.138172 Dram Type= 6, Freq= 0, CH_1, rank 0
4494 13:15:19.141719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4495 13:15:19.144950 ==
4496 13:15:19.145026 DQS Delay:
4497 13:15:19.145085 DQS0 = 0, DQS1 = 0
4498 13:15:19.148270 DQM Delay:
4499 13:15:19.148346 DQM0 = 43, DQM1 = 36
4500 13:15:19.151492 DQ Delay:
4501 13:15:19.151568 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4502 13:15:19.155136 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4503 13:15:19.158376 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4504 13:15:19.161575 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4505 13:15:19.161651
4506 13:15:19.164925
4507 13:15:19.165000 ==
4508 13:15:19.168180 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 13:15:19.171597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 13:15:19.171675 ==
4511 13:15:19.171735
4512 13:15:19.171788
4513 13:15:19.175306 TX Vref Scan disable
4514 13:15:19.175382 == TX Byte 0 ==
4515 13:15:19.181304 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4516 13:15:19.184885 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4517 13:15:19.184984 == TX Byte 1 ==
4518 13:15:19.191736 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4519 13:15:19.194833 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4520 13:15:19.194910 ==
4521 13:15:19.198163 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 13:15:19.201746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 13:15:19.201823 ==
4524 13:15:19.201881
4525 13:15:19.201934
4526 13:15:19.205003 TX Vref Scan disable
4527 13:15:19.208455 == TX Byte 0 ==
4528 13:15:19.211984 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4529 13:15:19.214796 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4530 13:15:19.217934 == TX Byte 1 ==
4531 13:15:19.221505 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4532 13:15:19.224617 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4533 13:15:19.224689
4534 13:15:19.228064 [DATLAT]
4535 13:15:19.228140 Freq=600, CH1 RK0
4536 13:15:19.228198
4537 13:15:19.232323 DATLAT Default: 0x9
4538 13:15:19.232399 0, 0xFFFF, sum = 0
4539 13:15:19.234578 1, 0xFFFF, sum = 0
4540 13:15:19.234656 2, 0xFFFF, sum = 0
4541 13:15:19.238381 3, 0xFFFF, sum = 0
4542 13:15:19.238458 4, 0xFFFF, sum = 0
4543 13:15:19.241440 5, 0xFFFF, sum = 0
4544 13:15:19.241518 6, 0xFFFF, sum = 0
4545 13:15:19.245074 7, 0xFFFF, sum = 0
4546 13:15:19.245193 8, 0x0, sum = 1
4547 13:15:19.248027 9, 0x0, sum = 2
4548 13:15:19.248105 10, 0x0, sum = 3
4549 13:15:19.251360 11, 0x0, sum = 4
4550 13:15:19.251437 best_step = 9
4551 13:15:19.251496
4552 13:15:19.251550 ==
4553 13:15:19.254612 Dram Type= 6, Freq= 0, CH_1, rank 0
4554 13:15:19.258777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4555 13:15:19.258854 ==
4556 13:15:19.261447 RX Vref Scan: 1
4557 13:15:19.261512
4558 13:15:19.265008 RX Vref 0 -> 0, step: 1
4559 13:15:19.265085
4560 13:15:19.265181 RX Delay -179 -> 252, step: 8
4561 13:15:19.268379
4562 13:15:19.268455 Set Vref, RX VrefLevel [Byte0]: 56
4563 13:15:19.271535 [Byte1]: 50
4564 13:15:19.276270
4565 13:15:19.276345 Final RX Vref Byte 0 = 56 to rank0
4566 13:15:19.279886 Final RX Vref Byte 1 = 50 to rank0
4567 13:15:19.282849 Final RX Vref Byte 0 = 56 to rank1
4568 13:15:19.285975 Final RX Vref Byte 1 = 50 to rank1==
4569 13:15:19.289557 Dram Type= 6, Freq= 0, CH_1, rank 0
4570 13:15:19.296046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 13:15:19.296123 ==
4572 13:15:19.296183 DQS Delay:
4573 13:15:19.296238 DQS0 = 0, DQS1 = 0
4574 13:15:19.299616 DQM Delay:
4575 13:15:19.299692 DQM0 = 40, DQM1 = 32
4576 13:15:19.303112 DQ Delay:
4577 13:15:19.306409 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4578 13:15:19.306485 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4579 13:15:19.310155 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4580 13:15:19.312949 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4581 13:15:19.316198
4582 13:15:19.316273
4583 13:15:19.323003 [DQSOSCAuto] RK0, (LSB)MR18= 0x4509, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 396 ps
4584 13:15:19.326291 CH1 RK0: MR19=808, MR18=4509
4585 13:15:19.333413 CH1_RK0: MR19=0x808, MR18=0x4509, DQSOSC=396, MR23=63, INC=167, DEC=111
4586 13:15:19.333501
4587 13:15:19.336286 ----->DramcWriteLeveling(PI) begin...
4588 13:15:19.336362 ==
4589 13:15:19.340082 Dram Type= 6, Freq= 0, CH_1, rank 1
4590 13:15:19.343059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 13:15:19.343159 ==
4592 13:15:19.346143 Write leveling (Byte 0): 33 => 33
4593 13:15:19.349720 Write leveling (Byte 1): 30 => 30
4594 13:15:19.352888 DramcWriteLeveling(PI) end<-----
4595 13:15:19.352964
4596 13:15:19.353022 ==
4597 13:15:19.356109 Dram Type= 6, Freq= 0, CH_1, rank 1
4598 13:15:19.359705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 13:15:19.359782 ==
4600 13:15:19.363011 [Gating] SW mode calibration
4601 13:15:19.369386 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4602 13:15:19.376385 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4603 13:15:19.379430 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4604 13:15:19.382942 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4605 13:15:19.389417 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4606 13:15:19.392696 0 9 12 | B1->B0 | 2f2f 2727 | 0 1 | (0 0) (1 0)
4607 13:15:19.396494 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4608 13:15:19.403329 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 13:15:19.406477 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 13:15:19.410048 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 13:15:19.416253 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 13:15:19.419694 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 13:15:19.423156 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4614 13:15:19.429849 0 10 12 | B1->B0 | 3131 4040 | 0 0 | (0 0) (0 0)
4615 13:15:19.433108 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4616 13:15:19.436367 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 13:15:19.442914 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 13:15:19.446192 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 13:15:19.449459 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 13:15:19.456121 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 13:15:19.459622 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4622 13:15:19.463483 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4623 13:15:19.466031 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 13:15:19.472869 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 13:15:19.475864 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 13:15:19.479561 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 13:15:19.485954 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 13:15:19.489693 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 13:15:19.492844 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 13:15:19.499916 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 13:15:19.502826 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 13:15:19.506394 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 13:15:19.513016 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 13:15:19.516252 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 13:15:19.519479 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 13:15:19.526066 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 13:15:19.529480 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4638 13:15:19.533064 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4639 13:15:19.536688 Total UI for P1: 0, mck2ui 16
4640 13:15:19.539803 best dqsien dly found for B0: ( 0, 13, 8)
4641 13:15:19.542672 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 13:15:19.546268 Total UI for P1: 0, mck2ui 16
4643 13:15:19.549443 best dqsien dly found for B1: ( 0, 13, 12)
4644 13:15:19.552754 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4645 13:15:19.559218 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4646 13:15:19.559294
4647 13:15:19.562810 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4648 13:15:19.565928 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4649 13:15:19.569433 [Gating] SW calibration Done
4650 13:15:19.569509 ==
4651 13:15:19.572539 Dram Type= 6, Freq= 0, CH_1, rank 1
4652 13:15:19.576595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4653 13:15:19.576672 ==
4654 13:15:19.576731 RX Vref Scan: 0
4655 13:15:19.579450
4656 13:15:19.579525 RX Vref 0 -> 0, step: 1
4657 13:15:19.579584
4658 13:15:19.582505 RX Delay -230 -> 252, step: 16
4659 13:15:19.586401 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4660 13:15:19.592989 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4661 13:15:19.596144 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4662 13:15:19.599278 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4663 13:15:19.602493 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4664 13:15:19.606606 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4665 13:15:19.613378 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4666 13:15:19.615930 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4667 13:15:19.619488 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4668 13:15:19.623202 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4669 13:15:19.629481 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4670 13:15:19.632904 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4671 13:15:19.636047 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4672 13:15:19.639255 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4673 13:15:19.642882 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4674 13:15:19.649996 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4675 13:15:19.650071 ==
4676 13:15:19.652623 Dram Type= 6, Freq= 0, CH_1, rank 1
4677 13:15:19.655985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4678 13:15:19.656061 ==
4679 13:15:19.656120 DQS Delay:
4680 13:15:19.659234 DQS0 = 0, DQS1 = 0
4681 13:15:19.659309 DQM Delay:
4682 13:15:19.662845 DQM0 = 39, DQM1 = 36
4683 13:15:19.662921 DQ Delay:
4684 13:15:19.665982 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4685 13:15:19.669384 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4686 13:15:19.672760 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4687 13:15:19.675873 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4688 13:15:19.675960
4689 13:15:19.676019
4690 13:15:19.676072 ==
4691 13:15:19.679615 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 13:15:19.682728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 13:15:19.682816 ==
4694 13:15:19.686047
4695 13:15:19.686125
4696 13:15:19.686184 TX Vref Scan disable
4697 13:15:19.690088 == TX Byte 0 ==
4698 13:15:19.692805 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4699 13:15:19.696457 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4700 13:15:19.699321 == TX Byte 1 ==
4701 13:15:19.702898 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4702 13:15:19.706100 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4703 13:15:19.706180 ==
4704 13:15:19.709592 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 13:15:19.716486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 13:15:19.716575 ==
4707 13:15:19.716638
4708 13:15:19.716693
4709 13:15:19.716745 TX Vref Scan disable
4710 13:15:19.720833 == TX Byte 0 ==
4711 13:15:19.724659 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4712 13:15:19.727769 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4713 13:15:19.731094 == TX Byte 1 ==
4714 13:15:19.734536 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4715 13:15:19.737756 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4716 13:15:19.740757
4717 13:15:19.740852 [DATLAT]
4718 13:15:19.740912 Freq=600, CH1 RK1
4719 13:15:19.740968
4720 13:15:19.744295 DATLAT Default: 0x9
4721 13:15:19.744377 0, 0xFFFF, sum = 0
4722 13:15:19.747367 1, 0xFFFF, sum = 0
4723 13:15:19.747459 2, 0xFFFF, sum = 0
4724 13:15:19.751283 3, 0xFFFF, sum = 0
4725 13:15:19.751374 4, 0xFFFF, sum = 0
4726 13:15:19.754804 5, 0xFFFF, sum = 0
4727 13:15:19.754892 6, 0xFFFF, sum = 0
4728 13:15:19.757437 7, 0xFFFF, sum = 0
4729 13:15:19.757520 8, 0x0, sum = 1
4730 13:15:19.761033 9, 0x0, sum = 2
4731 13:15:19.761145 10, 0x0, sum = 3
4732 13:15:19.764433 11, 0x0, sum = 4
4733 13:15:19.764518 best_step = 9
4734 13:15:19.764579
4735 13:15:19.764633 ==
4736 13:15:19.767513 Dram Type= 6, Freq= 0, CH_1, rank 1
4737 13:15:19.774634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4738 13:15:19.774740 ==
4739 13:15:19.774799 RX Vref Scan: 0
4740 13:15:19.774854
4741 13:15:19.778078 RX Vref 0 -> 0, step: 1
4742 13:15:19.778156
4743 13:15:19.781017 RX Delay -179 -> 252, step: 8
4744 13:15:19.784477 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4745 13:15:19.787923 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4746 13:15:19.794558 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4747 13:15:19.797973 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4748 13:15:19.800828 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4749 13:15:19.804410 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4750 13:15:19.810898 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4751 13:15:19.814626 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4752 13:15:19.817865 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4753 13:15:19.820863 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4754 13:15:19.824360 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4755 13:15:19.831229 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4756 13:15:19.834638 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4757 13:15:19.837642 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4758 13:15:19.841015 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4759 13:15:19.847794 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4760 13:15:19.847906 ==
4761 13:15:19.851097 Dram Type= 6, Freq= 0, CH_1, rank 1
4762 13:15:19.854434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4763 13:15:19.854532 ==
4764 13:15:19.854593 DQS Delay:
4765 13:15:19.857658 DQS0 = 0, DQS1 = 0
4766 13:15:19.857739 DQM Delay:
4767 13:15:19.861260 DQM0 = 38, DQM1 = 33
4768 13:15:19.861348 DQ Delay:
4769 13:15:19.864257 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4770 13:15:19.867594 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4771 13:15:19.871447 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4772 13:15:19.874269 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4773 13:15:19.874363
4774 13:15:19.874423
4775 13:15:19.880859 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a48, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
4776 13:15:19.884510 CH1 RK1: MR19=808, MR18=3A48
4777 13:15:19.891488 CH1_RK1: MR19=0x808, MR18=0x3A48, DQSOSC=396, MR23=63, INC=167, DEC=111
4778 13:15:19.894755 [RxdqsGatingPostProcess] freq 600
4779 13:15:19.901107 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4780 13:15:19.904801 Pre-setting of DQS Precalculation
4781 13:15:19.907791 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4782 13:15:19.914525 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4783 13:15:19.921049 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4784 13:15:19.921199
4785 13:15:19.921297
4786 13:15:19.924373 [Calibration Summary] 1200 Mbps
4787 13:15:19.928129 CH 0, Rank 0
4788 13:15:19.928213 SW Impedance : PASS
4789 13:15:19.931342 DUTY Scan : NO K
4790 13:15:19.934808 ZQ Calibration : PASS
4791 13:15:19.934888 Jitter Meter : NO K
4792 13:15:19.937868 CBT Training : PASS
4793 13:15:19.937949 Write leveling : PASS
4794 13:15:19.941068 RX DQS gating : PASS
4795 13:15:19.944680 RX DQ/DQS(RDDQC) : PASS
4796 13:15:19.944758 TX DQ/DQS : PASS
4797 13:15:19.948317 RX DATLAT : PASS
4798 13:15:19.951316 RX DQ/DQS(Engine): PASS
4799 13:15:19.951396 TX OE : NO K
4800 13:15:19.954960 All Pass.
4801 13:15:19.955037
4802 13:15:19.955097 CH 0, Rank 1
4803 13:15:19.958185 SW Impedance : PASS
4804 13:15:19.958262 DUTY Scan : NO K
4805 13:15:19.961417 ZQ Calibration : PASS
4806 13:15:19.964591 Jitter Meter : NO K
4807 13:15:19.964668 CBT Training : PASS
4808 13:15:19.967948 Write leveling : PASS
4809 13:15:19.971540 RX DQS gating : PASS
4810 13:15:19.971617 RX DQ/DQS(RDDQC) : PASS
4811 13:15:19.974384 TX DQ/DQS : PASS
4812 13:15:19.974462 RX DATLAT : PASS
4813 13:15:19.978058 RX DQ/DQS(Engine): PASS
4814 13:15:19.981372 TX OE : NO K
4815 13:15:19.981449 All Pass.
4816 13:15:19.981508
4817 13:15:19.981563 CH 1, Rank 0
4818 13:15:19.984885 SW Impedance : PASS
4819 13:15:19.988056 DUTY Scan : NO K
4820 13:15:19.988138 ZQ Calibration : PASS
4821 13:15:19.991307 Jitter Meter : NO K
4822 13:15:19.994545 CBT Training : PASS
4823 13:15:19.994622 Write leveling : PASS
4824 13:15:19.998077 RX DQS gating : PASS
4825 13:15:20.001042 RX DQ/DQS(RDDQC) : PASS
4826 13:15:20.001180 TX DQ/DQS : PASS
4827 13:15:20.004719 RX DATLAT : PASS
4828 13:15:20.007860 RX DQ/DQS(Engine): PASS
4829 13:15:20.007938 TX OE : NO K
4830 13:15:20.011495 All Pass.
4831 13:15:20.011572
4832 13:15:20.011631 CH 1, Rank 1
4833 13:15:20.014697 SW Impedance : PASS
4834 13:15:20.014774 DUTY Scan : NO K
4835 13:15:20.017711 ZQ Calibration : PASS
4836 13:15:20.020909 Jitter Meter : NO K
4837 13:15:20.020985 CBT Training : PASS
4838 13:15:20.024708 Write leveling : PASS
4839 13:15:20.024785 RX DQS gating : PASS
4840 13:15:20.027839 RX DQ/DQS(RDDQC) : PASS
4841 13:15:20.031313 TX DQ/DQS : PASS
4842 13:15:20.031389 RX DATLAT : PASS
4843 13:15:20.034237 RX DQ/DQS(Engine): PASS
4844 13:15:20.037929 TX OE : NO K
4845 13:15:20.038006 All Pass.
4846 13:15:20.038102
4847 13:15:20.040994 DramC Write-DBI off
4848 13:15:20.041070 PER_BANK_REFRESH: Hybrid Mode
4849 13:15:20.044677 TX_TRACKING: ON
4850 13:15:20.051414 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4851 13:15:20.057752 [FAST_K] Save calibration result to emmc
4852 13:15:20.061878 dramc_set_vcore_voltage set vcore to 662500
4853 13:15:20.061958 Read voltage for 933, 3
4854 13:15:20.064553 Vio18 = 0
4855 13:15:20.064629 Vcore = 662500
4856 13:15:20.064687 Vdram = 0
4857 13:15:20.068282 Vddq = 0
4858 13:15:20.068358 Vmddr = 0
4859 13:15:20.071156 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4860 13:15:20.078013 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4861 13:15:20.081508 MEM_TYPE=3, freq_sel=17
4862 13:15:20.084814 sv_algorithm_assistance_LP4_1600
4863 13:15:20.087980 ============ PULL DRAM RESETB DOWN ============
4864 13:15:20.090976 ========== PULL DRAM RESETB DOWN end =========
4865 13:15:20.094705 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4866 13:15:20.098509 ===================================
4867 13:15:20.101365 LPDDR4 DRAM CONFIGURATION
4868 13:15:20.105093 ===================================
4869 13:15:20.107926 EX_ROW_EN[0] = 0x0
4870 13:15:20.108002 EX_ROW_EN[1] = 0x0
4871 13:15:20.111618 LP4Y_EN = 0x0
4872 13:15:20.111695 WORK_FSP = 0x0
4873 13:15:20.114533 WL = 0x3
4874 13:15:20.114609 RL = 0x3
4875 13:15:20.117995 BL = 0x2
4876 13:15:20.118102 RPST = 0x0
4877 13:15:20.121303 RD_PRE = 0x0
4878 13:15:20.121379 WR_PRE = 0x1
4879 13:15:20.124548 WR_PST = 0x0
4880 13:15:20.124625 DBI_WR = 0x0
4881 13:15:20.128172 DBI_RD = 0x0
4882 13:15:20.128250 OTF = 0x1
4883 13:15:20.131301 ===================================
4884 13:15:20.134588 ===================================
4885 13:15:20.137759 ANA top config
4886 13:15:20.141003 ===================================
4887 13:15:20.144428 DLL_ASYNC_EN = 0
4888 13:15:20.144505 ALL_SLAVE_EN = 1
4889 13:15:20.148036 NEW_RANK_MODE = 1
4890 13:15:20.151290 DLL_IDLE_MODE = 1
4891 13:15:20.154955 LP45_APHY_COMB_EN = 1
4892 13:15:20.155032 TX_ODT_DIS = 1
4893 13:15:20.158374 NEW_8X_MODE = 1
4894 13:15:20.161598 ===================================
4895 13:15:20.165008 ===================================
4896 13:15:20.168036 data_rate = 1866
4897 13:15:20.171184 CKR = 1
4898 13:15:20.174582 DQ_P2S_RATIO = 8
4899 13:15:20.178059 ===================================
4900 13:15:20.181721 CA_P2S_RATIO = 8
4901 13:15:20.181800 DQ_CA_OPEN = 0
4902 13:15:20.184904 DQ_SEMI_OPEN = 0
4903 13:15:20.187837 CA_SEMI_OPEN = 0
4904 13:15:20.191069 CA_FULL_RATE = 0
4905 13:15:20.194851 DQ_CKDIV4_EN = 1
4906 13:15:20.198293 CA_CKDIV4_EN = 1
4907 13:15:20.198374 CA_PREDIV_EN = 0
4908 13:15:20.201289 PH8_DLY = 0
4909 13:15:20.204918 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4910 13:15:20.208212 DQ_AAMCK_DIV = 4
4911 13:15:20.211294 CA_AAMCK_DIV = 4
4912 13:15:20.211379 CA_ADMCK_DIV = 4
4913 13:15:20.214797 DQ_TRACK_CA_EN = 0
4914 13:15:20.217947 CA_PICK = 933
4915 13:15:20.221384 CA_MCKIO = 933
4916 13:15:20.225319 MCKIO_SEMI = 0
4917 13:15:20.228236 PLL_FREQ = 3732
4918 13:15:20.231201 DQ_UI_PI_RATIO = 32
4919 13:15:20.231284 CA_UI_PI_RATIO = 0
4920 13:15:20.234863 ===================================
4921 13:15:20.238022 ===================================
4922 13:15:20.241446 memory_type:LPDDR4
4923 13:15:20.244662 GP_NUM : 10
4924 13:15:20.244743 SRAM_EN : 1
4925 13:15:20.247900 MD32_EN : 0
4926 13:15:20.251491 ===================================
4927 13:15:20.255357 [ANA_INIT] >>>>>>>>>>>>>>
4928 13:15:20.258255 <<<<<< [CONFIGURE PHASE]: ANA_TX
4929 13:15:20.261883 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4930 13:15:20.264867 ===================================
4931 13:15:20.264956 data_rate = 1866,PCW = 0X8f00
4932 13:15:20.268489 ===================================
4933 13:15:20.271476 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4934 13:15:20.278151 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4935 13:15:20.284911 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4936 13:15:20.288636 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4937 13:15:20.291730 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4938 13:15:20.294993 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4939 13:15:20.298528 [ANA_INIT] flow start
4940 13:15:20.298628 [ANA_INIT] PLL >>>>>>>>
4941 13:15:20.301354 [ANA_INIT] PLL <<<<<<<<
4942 13:15:20.304826 [ANA_INIT] MIDPI >>>>>>>>
4943 13:15:20.308141 [ANA_INIT] MIDPI <<<<<<<<
4944 13:15:20.308234 [ANA_INIT] DLL >>>>>>>>
4945 13:15:20.311824 [ANA_INIT] flow end
4946 13:15:20.315007 ============ LP4 DIFF to SE enter ============
4947 13:15:20.318270 ============ LP4 DIFF to SE exit ============
4948 13:15:20.321606 [ANA_INIT] <<<<<<<<<<<<<
4949 13:15:20.325073 [Flow] Enable top DCM control >>>>>
4950 13:15:20.328408 [Flow] Enable top DCM control <<<<<
4951 13:15:20.331911 Enable DLL master slave shuffle
4952 13:15:20.334698 ==============================================================
4953 13:15:20.338117 Gating Mode config
4954 13:15:20.345019 ==============================================================
4955 13:15:20.345132 Config description:
4956 13:15:20.355136 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4957 13:15:20.361227 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4958 13:15:20.368078 SELPH_MODE 0: By rank 1: By Phase
4959 13:15:20.371488 ==============================================================
4960 13:15:20.374583 GAT_TRACK_EN = 1
4961 13:15:20.378222 RX_GATING_MODE = 2
4962 13:15:20.381312 RX_GATING_TRACK_MODE = 2
4963 13:15:20.384658 SELPH_MODE = 1
4964 13:15:20.388011 PICG_EARLY_EN = 1
4965 13:15:20.392004 VALID_LAT_VALUE = 1
4966 13:15:20.394932 ==============================================================
4967 13:15:20.398278 Enter into Gating configuration >>>>
4968 13:15:20.401955 Exit from Gating configuration <<<<
4969 13:15:20.405307 Enter into DVFS_PRE_config >>>>>
4970 13:15:20.418143 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4971 13:15:20.418262 Exit from DVFS_PRE_config <<<<<
4972 13:15:20.421695 Enter into PICG configuration >>>>
4973 13:15:20.425330 Exit from PICG configuration <<<<
4974 13:15:20.428376 [RX_INPUT] configuration >>>>>
4975 13:15:20.432316 [RX_INPUT] configuration <<<<<
4976 13:15:20.438471 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4977 13:15:20.441653 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4978 13:15:20.448573 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4979 13:15:20.455559 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4980 13:15:20.461814 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4981 13:15:20.468476 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4982 13:15:20.471494 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4983 13:15:20.475129 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4984 13:15:20.478603 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4985 13:15:20.485529 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4986 13:15:20.488055 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4987 13:15:20.491390 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4988 13:15:20.494973 ===================================
4989 13:15:20.498077 LPDDR4 DRAM CONFIGURATION
4990 13:15:20.501675 ===================================
4991 13:15:20.501751 EX_ROW_EN[0] = 0x0
4992 13:15:20.505237 EX_ROW_EN[1] = 0x0
4993 13:15:20.505315 LP4Y_EN = 0x0
4994 13:15:20.508189 WORK_FSP = 0x0
4995 13:15:20.508267 WL = 0x3
4996 13:15:20.511719 RL = 0x3
4997 13:15:20.511796 BL = 0x2
4998 13:15:20.515113 RPST = 0x0
4999 13:15:20.518442 RD_PRE = 0x0
5000 13:15:20.518525 WR_PRE = 0x1
5001 13:15:20.521698 WR_PST = 0x0
5002 13:15:20.521778 DBI_WR = 0x0
5003 13:15:20.524954 DBI_RD = 0x0
5004 13:15:20.525055 OTF = 0x1
5005 13:15:20.529050 ===================================
5006 13:15:20.531906 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5007 13:15:20.535662 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5008 13:15:20.542064 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5009 13:15:20.545709 ===================================
5010 13:15:20.548598 LPDDR4 DRAM CONFIGURATION
5011 13:15:20.551762 ===================================
5012 13:15:20.551852 EX_ROW_EN[0] = 0x10
5013 13:15:20.555140 EX_ROW_EN[1] = 0x0
5014 13:15:20.555220 LP4Y_EN = 0x0
5015 13:15:20.558451 WORK_FSP = 0x0
5016 13:15:20.558530 WL = 0x3
5017 13:15:20.561902 RL = 0x3
5018 13:15:20.561980 BL = 0x2
5019 13:15:20.564986 RPST = 0x0
5020 13:15:20.565085 RD_PRE = 0x0
5021 13:15:20.568222 WR_PRE = 0x1
5022 13:15:20.568301 WR_PST = 0x0
5023 13:15:20.571632 DBI_WR = 0x0
5024 13:15:20.571711 DBI_RD = 0x0
5025 13:15:20.575473 OTF = 0x1
5026 13:15:20.578470 ===================================
5027 13:15:20.585073 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5028 13:15:20.588267 nWR fixed to 30
5029 13:15:20.591736 [ModeRegInit_LP4] CH0 RK0
5030 13:15:20.591826 [ModeRegInit_LP4] CH0 RK1
5031 13:15:20.594880 [ModeRegInit_LP4] CH1 RK0
5032 13:15:20.598167 [ModeRegInit_LP4] CH1 RK1
5033 13:15:20.598257 match AC timing 9
5034 13:15:20.605000 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5035 13:15:20.608284 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5036 13:15:20.611572 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5037 13:15:20.618322 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5038 13:15:20.621455 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5039 13:15:20.621564 ==
5040 13:15:20.624928 Dram Type= 6, Freq= 0, CH_0, rank 0
5041 13:15:20.628262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5042 13:15:20.628351 ==
5043 13:15:20.634927 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5044 13:15:20.641128 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5045 13:15:20.644965 [CA 0] Center 38 (8~69) winsize 62
5046 13:15:20.648026 [CA 1] Center 38 (7~69) winsize 63
5047 13:15:20.651287 [CA 2] Center 35 (5~66) winsize 62
5048 13:15:20.654715 [CA 3] Center 35 (5~66) winsize 62
5049 13:15:20.658179 [CA 4] Center 34 (4~64) winsize 61
5050 13:15:20.661361 [CA 5] Center 34 (4~64) winsize 61
5051 13:15:20.661437
5052 13:15:20.665470 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5053 13:15:20.665546
5054 13:15:20.668036 [CATrainingPosCal] consider 1 rank data
5055 13:15:20.671087 u2DelayCellTimex100 = 270/100 ps
5056 13:15:20.674923 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5057 13:15:20.677830 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5058 13:15:20.681889 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5059 13:15:20.685332 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5060 13:15:20.688169 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5061 13:15:20.691245 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5062 13:15:20.694509
5063 13:15:20.697768 CA PerBit enable=1, Macro0, CA PI delay=34
5064 13:15:20.697853
5065 13:15:20.701296 [CBTSetCACLKResult] CA Dly = 34
5066 13:15:20.701381 CS Dly: 6 (0~37)
5067 13:15:20.701442 ==
5068 13:15:20.704675 Dram Type= 6, Freq= 0, CH_0, rank 1
5069 13:15:20.708042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5070 13:15:20.708120 ==
5071 13:15:20.714529 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5072 13:15:20.721064 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5073 13:15:20.724753 [CA 0] Center 38 (7~69) winsize 63
5074 13:15:20.727863 [CA 1] Center 38 (7~69) winsize 63
5075 13:15:20.730946 [CA 2] Center 35 (5~66) winsize 62
5076 13:15:20.734090 [CA 3] Center 35 (4~66) winsize 63
5077 13:15:20.737776 [CA 4] Center 34 (4~65) winsize 62
5078 13:15:20.741145 [CA 5] Center 33 (3~64) winsize 62
5079 13:15:20.741236
5080 13:15:20.744594 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5081 13:15:20.744671
5082 13:15:20.747441 [CATrainingPosCal] consider 2 rank data
5083 13:15:20.750813 u2DelayCellTimex100 = 270/100 ps
5084 13:15:20.754876 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5085 13:15:20.758053 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5086 13:15:20.761036 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5087 13:15:20.764267 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5088 13:15:20.767791 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5089 13:15:20.774279 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5090 13:15:20.774358
5091 13:15:20.777705 CA PerBit enable=1, Macro0, CA PI delay=34
5092 13:15:20.777783
5093 13:15:20.780958 [CBTSetCACLKResult] CA Dly = 34
5094 13:15:20.781035 CS Dly: 7 (0~39)
5095 13:15:20.781131
5096 13:15:20.784296 ----->DramcWriteLeveling(PI) begin...
5097 13:15:20.784373 ==
5098 13:15:20.787539 Dram Type= 6, Freq= 0, CH_0, rank 0
5099 13:15:20.794148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5100 13:15:20.794230 ==
5101 13:15:20.797686 Write leveling (Byte 0): 30 => 30
5102 13:15:20.797762 Write leveling (Byte 1): 29 => 29
5103 13:15:20.800900 DramcWriteLeveling(PI) end<-----
5104 13:15:20.800975
5105 13:15:20.801034 ==
5106 13:15:20.804324 Dram Type= 6, Freq= 0, CH_0, rank 0
5107 13:15:20.810575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 13:15:20.810652 ==
5109 13:15:20.813936 [Gating] SW mode calibration
5110 13:15:20.820636 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5111 13:15:20.824191 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5112 13:15:20.830987 0 14 0 | B1->B0 | 2323 2f2f | 1 0 | (0 0) (0 0)
5113 13:15:20.834401 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5114 13:15:20.837293 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 13:15:20.840620 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 13:15:20.847584 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 13:15:20.850570 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 13:15:20.854461 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 13:15:20.860850 0 14 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5120 13:15:20.864201 0 15 0 | B1->B0 | 3131 2525 | 0 0 | (0 1) (1 0)
5121 13:15:20.867481 0 15 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5122 13:15:20.874169 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 13:15:20.877758 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 13:15:20.880838 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 13:15:20.887872 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 13:15:20.890885 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 13:15:20.894120 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
5128 13:15:20.901525 1 0 0 | B1->B0 | 3535 3c3c | 0 0 | (0 0) (0 0)
5129 13:15:20.904566 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 13:15:20.908049 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 13:15:20.914127 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 13:15:20.917691 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 13:15:20.921086 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 13:15:20.924409 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 13:15:20.931132 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 13:15:20.934358 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 13:15:20.937849 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5138 13:15:20.944314 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 13:15:20.947515 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 13:15:20.950845 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 13:15:20.958051 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 13:15:20.960828 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 13:15:20.964429 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 13:15:20.971159 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 13:15:20.974721 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 13:15:20.977639 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 13:15:20.984828 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 13:15:20.987924 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 13:15:20.990954 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 13:15:20.998084 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 13:15:21.001033 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5152 13:15:21.004630 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5153 13:15:21.008225 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 13:15:21.011042 Total UI for P1: 0, mck2ui 16
5155 13:15:21.014454 best dqsien dly found for B0: ( 1, 2, 30)
5156 13:15:21.017797 Total UI for P1: 0, mck2ui 16
5157 13:15:21.021435 best dqsien dly found for B1: ( 1, 2, 30)
5158 13:15:21.024626 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5159 13:15:21.027525 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5160 13:15:21.031081
5161 13:15:21.034200 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5162 13:15:21.037869 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5163 13:15:21.041104 [Gating] SW calibration Done
5164 13:15:21.041207 ==
5165 13:15:21.044434 Dram Type= 6, Freq= 0, CH_0, rank 0
5166 13:15:21.047745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5167 13:15:21.047829 ==
5168 13:15:21.047907 RX Vref Scan: 0
5169 13:15:21.047980
5170 13:15:21.050997 RX Vref 0 -> 0, step: 1
5171 13:15:21.051075
5172 13:15:21.055055 RX Delay -80 -> 252, step: 8
5173 13:15:21.057932 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5174 13:15:21.061564 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5175 13:15:21.064272 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5176 13:15:21.071271 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5177 13:15:21.074617 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5178 13:15:21.078388 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5179 13:15:21.081093 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5180 13:15:21.084353 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5181 13:15:21.087823 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5182 13:15:21.094291 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5183 13:15:21.098258 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5184 13:15:21.101544 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5185 13:15:21.104497 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5186 13:15:21.107991 iDelay=208, Bit 13, Center 87 (-8 ~ 183) 192
5187 13:15:21.114754 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5188 13:15:21.117990 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5189 13:15:21.118069 ==
5190 13:15:21.121392 Dram Type= 6, Freq= 0, CH_0, rank 0
5191 13:15:21.124816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5192 13:15:21.124895 ==
5193 13:15:21.124955 DQS Delay:
5194 13:15:21.128231 DQS0 = 0, DQS1 = 0
5195 13:15:21.128309 DQM Delay:
5196 13:15:21.131276 DQM0 = 97, DQM1 = 86
5197 13:15:21.131362 DQ Delay:
5198 13:15:21.134873 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5199 13:15:21.137883 DQ4 =99, DQ5 =87, DQ6 =111, DQ7 =103
5200 13:15:21.141730 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5201 13:15:21.144644 DQ12 =91, DQ13 =87, DQ14 =95, DQ15 =95
5202 13:15:21.144776
5203 13:15:21.144846
5204 13:15:21.144902 ==
5205 13:15:21.147851 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 13:15:21.151494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 13:15:21.151575 ==
5208 13:15:21.151690
5209 13:15:21.154439
5210 13:15:21.154539 TX Vref Scan disable
5211 13:15:21.158163 == TX Byte 0 ==
5212 13:15:21.161604 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5213 13:15:21.164797 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5214 13:15:21.168250 == TX Byte 1 ==
5215 13:15:21.171487 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5216 13:15:21.174646 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5217 13:15:21.174741 ==
5218 13:15:21.178030 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 13:15:21.184632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 13:15:21.184743 ==
5221 13:15:21.184826
5222 13:15:21.184915
5223 13:15:21.185003 TX Vref Scan disable
5224 13:15:21.189004 == TX Byte 0 ==
5225 13:15:21.192263 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5226 13:15:21.198822 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5227 13:15:21.198926 == TX Byte 1 ==
5228 13:15:21.202413 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5229 13:15:21.205448 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5230 13:15:21.209052
5231 13:15:21.209178 [DATLAT]
5232 13:15:21.209257 Freq=933, CH0 RK0
5233 13:15:21.209332
5234 13:15:21.212293 DATLAT Default: 0xd
5235 13:15:21.212373 0, 0xFFFF, sum = 0
5236 13:15:21.215239 1, 0xFFFF, sum = 0
5237 13:15:21.215339 2, 0xFFFF, sum = 0
5238 13:15:21.218827 3, 0xFFFF, sum = 0
5239 13:15:21.218925 4, 0xFFFF, sum = 0
5240 13:15:21.222204 5, 0xFFFF, sum = 0
5241 13:15:21.222291 6, 0xFFFF, sum = 0
5242 13:15:21.225659 7, 0xFFFF, sum = 0
5243 13:15:21.229253 8, 0xFFFF, sum = 0
5244 13:15:21.229347 9, 0xFFFF, sum = 0
5245 13:15:21.229429 10, 0x0, sum = 1
5246 13:15:21.232332 11, 0x0, sum = 2
5247 13:15:21.232413 12, 0x0, sum = 3
5248 13:15:21.235680 13, 0x0, sum = 4
5249 13:15:21.235761 best_step = 11
5250 13:15:21.235838
5251 13:15:21.235910 ==
5252 13:15:21.238766 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 13:15:21.245667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 13:15:21.245762 ==
5255 13:15:21.245841 RX Vref Scan: 1
5256 13:15:21.245920
5257 13:15:21.248970 RX Vref 0 -> 0, step: 1
5258 13:15:21.249048
5259 13:15:21.252355 RX Delay -61 -> 252, step: 4
5260 13:15:21.252434
5261 13:15:21.255443 Set Vref, RX VrefLevel [Byte0]: 54
5262 13:15:21.259136 [Byte1]: 51
5263 13:15:21.259216
5264 13:15:21.262445 Final RX Vref Byte 0 = 54 to rank0
5265 13:15:21.265954 Final RX Vref Byte 1 = 51 to rank0
5266 13:15:21.268745 Final RX Vref Byte 0 = 54 to rank1
5267 13:15:21.272130 Final RX Vref Byte 1 = 51 to rank1==
5268 13:15:21.276141 Dram Type= 6, Freq= 0, CH_0, rank 0
5269 13:15:21.278881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 13:15:21.278958 ==
5271 13:15:21.282470 DQS Delay:
5272 13:15:21.282545 DQS0 = 0, DQS1 = 0
5273 13:15:21.282604 DQM Delay:
5274 13:15:21.285775 DQM0 = 97, DQM1 = 87
5275 13:15:21.285851 DQ Delay:
5276 13:15:21.289130 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5277 13:15:21.292940 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =102
5278 13:15:21.295917 DQ8 =78, DQ9 =76, DQ10 =86, DQ11 =80
5279 13:15:21.299314 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =96
5280 13:15:21.299390
5281 13:15:21.299448
5282 13:15:21.309463 [DQSOSCAuto] RK0, (LSB)MR18= 0x14ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5283 13:15:21.312366 CH0 RK0: MR19=504, MR18=14FF
5284 13:15:21.315965 CH0_RK0: MR19=0x504, MR18=0x14FF, DQSOSC=415, MR23=63, INC=62, DEC=41
5285 13:15:21.316041
5286 13:15:21.319301 ----->DramcWriteLeveling(PI) begin...
5287 13:15:21.319378 ==
5288 13:15:21.322451 Dram Type= 6, Freq= 0, CH_0, rank 1
5289 13:15:21.329172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 13:15:21.329249 ==
5291 13:15:21.332583 Write leveling (Byte 0): 32 => 32
5292 13:15:21.335980 Write leveling (Byte 1): 30 => 30
5293 13:15:21.336057 DramcWriteLeveling(PI) end<-----
5294 13:15:21.336115
5295 13:15:21.339454 ==
5296 13:15:21.342604 Dram Type= 6, Freq= 0, CH_0, rank 1
5297 13:15:21.346421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 13:15:21.346501 ==
5299 13:15:21.349184 [Gating] SW mode calibration
5300 13:15:21.356253 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5301 13:15:21.359125 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5302 13:15:21.366063 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5303 13:15:21.369208 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5304 13:15:21.372747 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 13:15:21.379465 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 13:15:21.382640 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 13:15:21.386152 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 13:15:21.393216 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 13:15:21.396561 0 14 28 | B1->B0 | 3333 3030 | 0 1 | (0 1) (0 0)
5310 13:15:21.400041 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 1) (1 0)
5311 13:15:21.402985 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 13:15:21.409760 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 13:15:21.412808 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 13:15:21.416335 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 13:15:21.422876 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 13:15:21.426290 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 13:15:21.429900 0 15 28 | B1->B0 | 2c2c 3a3a | 0 0 | (0 0) (1 1)
5318 13:15:21.436294 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
5319 13:15:21.439425 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 13:15:21.443375 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 13:15:21.449798 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 13:15:21.453037 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 13:15:21.456332 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 13:15:21.463047 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5325 13:15:21.466457 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5326 13:15:21.469824 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5327 13:15:21.476405 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 13:15:21.479863 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 13:15:21.482909 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 13:15:21.489840 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 13:15:21.492990 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 13:15:21.496426 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 13:15:21.499899 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 13:15:21.506554 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 13:15:21.509833 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 13:15:21.512779 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 13:15:21.520296 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 13:15:21.523254 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 13:15:21.527013 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 13:15:21.533421 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5341 13:15:21.536802 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5342 13:15:21.540451 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5343 13:15:21.543497 Total UI for P1: 0, mck2ui 16
5344 13:15:21.546350 best dqsien dly found for B0: ( 1, 2, 26)
5345 13:15:21.553070 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 13:15:21.553195 Total UI for P1: 0, mck2ui 16
5347 13:15:21.556605 best dqsien dly found for B1: ( 1, 2, 30)
5348 13:15:21.563509 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5349 13:15:21.566598 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5350 13:15:21.566674
5351 13:15:21.569768 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5352 13:15:21.572927 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5353 13:15:21.576488 [Gating] SW calibration Done
5354 13:15:21.576563 ==
5355 13:15:21.579648 Dram Type= 6, Freq= 0, CH_0, rank 1
5356 13:15:21.582906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 13:15:21.582984 ==
5358 13:15:21.586322 RX Vref Scan: 0
5359 13:15:21.586397
5360 13:15:21.586456 RX Vref 0 -> 0, step: 1
5361 13:15:21.586510
5362 13:15:21.590046 RX Delay -80 -> 252, step: 8
5363 13:15:21.593290 iDelay=200, Bit 0, Center 99 (0 ~ 199) 200
5364 13:15:21.596619 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5365 13:15:21.603323 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5366 13:15:21.606235 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5367 13:15:21.609725 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5368 13:15:21.613151 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5369 13:15:21.616704 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5370 13:15:21.619923 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5371 13:15:21.623320 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5372 13:15:21.630063 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5373 13:15:21.633044 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5374 13:15:21.636721 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5375 13:15:21.639774 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5376 13:15:21.642936 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5377 13:15:21.649867 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5378 13:15:21.653033 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5379 13:15:21.653129 ==
5380 13:15:21.656571 Dram Type= 6, Freq= 0, CH_0, rank 1
5381 13:15:21.660123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5382 13:15:21.660211 ==
5383 13:15:21.660270 DQS Delay:
5384 13:15:21.663168 DQS0 = 0, DQS1 = 0
5385 13:15:21.663248 DQM Delay:
5386 13:15:21.667031 DQM0 = 97, DQM1 = 88
5387 13:15:21.667111 DQ Delay:
5388 13:15:21.670029 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5389 13:15:21.673051 DQ4 =95, DQ5 =87, DQ6 =103, DQ7 =103
5390 13:15:21.676634 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =79
5391 13:15:21.679942 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5392 13:15:21.680018
5393 13:15:21.680103
5394 13:15:21.680187 ==
5395 13:15:21.683164 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 13:15:21.686500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 13:15:21.689861 ==
5398 13:15:21.689937
5399 13:15:21.689996
5400 13:15:21.690050 TX Vref Scan disable
5401 13:15:21.693430 == TX Byte 0 ==
5402 13:15:21.696632 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5403 13:15:21.700382 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5404 13:15:21.703253 == TX Byte 1 ==
5405 13:15:21.707060 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5406 13:15:21.710235 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5407 13:15:21.710311 ==
5408 13:15:21.713478 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 13:15:21.720182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 13:15:21.720260 ==
5411 13:15:21.720319
5412 13:15:21.720373
5413 13:15:21.720424 TX Vref Scan disable
5414 13:15:21.724382 == TX Byte 0 ==
5415 13:15:21.727815 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5416 13:15:21.730911 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5417 13:15:21.734123 == TX Byte 1 ==
5418 13:15:21.737687 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5419 13:15:21.740886 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5420 13:15:21.744083
5421 13:15:21.744159 [DATLAT]
5422 13:15:21.744218 Freq=933, CH0 RK1
5423 13:15:21.744273
5424 13:15:21.747791 DATLAT Default: 0xb
5425 13:15:21.747867 0, 0xFFFF, sum = 0
5426 13:15:21.750835 1, 0xFFFF, sum = 0
5427 13:15:21.750914 2, 0xFFFF, sum = 0
5428 13:15:21.754197 3, 0xFFFF, sum = 0
5429 13:15:21.754274 4, 0xFFFF, sum = 0
5430 13:15:21.757762 5, 0xFFFF, sum = 0
5431 13:15:21.760775 6, 0xFFFF, sum = 0
5432 13:15:21.760856 7, 0xFFFF, sum = 0
5433 13:15:21.764726 8, 0xFFFF, sum = 0
5434 13:15:21.764805 9, 0xFFFF, sum = 0
5435 13:15:21.767810 10, 0x0, sum = 1
5436 13:15:21.767890 11, 0x0, sum = 2
5437 13:15:21.767968 12, 0x0, sum = 3
5438 13:15:21.771011 13, 0x0, sum = 4
5439 13:15:21.771090 best_step = 11
5440 13:15:21.771168
5441 13:15:21.771240 ==
5442 13:15:21.774026 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 13:15:21.780999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 13:15:21.781079 ==
5445 13:15:21.781209 RX Vref Scan: 0
5446 13:15:21.781283
5447 13:15:21.784100 RX Vref 0 -> 0, step: 1
5448 13:15:21.784178
5449 13:15:21.787797 RX Delay -61 -> 252, step: 4
5450 13:15:21.790573 iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192
5451 13:15:21.797510 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5452 13:15:21.801245 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5453 13:15:21.804702 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5454 13:15:21.807865 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5455 13:15:21.810989 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5456 13:15:21.814089 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5457 13:15:21.821123 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5458 13:15:21.824733 iDelay=199, Bit 8, Center 78 (-9 ~ 166) 176
5459 13:15:21.827876 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5460 13:15:21.831165 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5461 13:15:21.834268 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5462 13:15:21.837825 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5463 13:15:21.844182 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5464 13:15:21.847248 iDelay=199, Bit 14, Center 94 (7 ~ 182) 176
5465 13:15:21.850820 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5466 13:15:21.850897 ==
5467 13:15:21.854163 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 13:15:21.857432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 13:15:21.857510 ==
5470 13:15:21.860508 DQS Delay:
5471 13:15:21.860583 DQS0 = 0, DQS1 = 0
5472 13:15:21.863741 DQM Delay:
5473 13:15:21.863817 DQM0 = 95, DQM1 = 86
5474 13:15:21.863875 DQ Delay:
5475 13:15:21.867377 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5476 13:15:21.870802 DQ4 =94, DQ5 =86, DQ6 =104, DQ7 =102
5477 13:15:21.874310 DQ8 =78, DQ9 =78, DQ10 =88, DQ11 =78
5478 13:15:21.877462 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =94
5479 13:15:21.877539
5480 13:15:21.877597
5481 13:15:21.887255 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b08, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5482 13:15:21.890753 CH0 RK1: MR19=505, MR18=1B08
5483 13:15:21.893760 CH0_RK1: MR19=0x505, MR18=0x1B08, DQSOSC=413, MR23=63, INC=63, DEC=42
5484 13:15:21.897207 [RxdqsGatingPostProcess] freq 933
5485 13:15:21.903988 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5486 13:15:21.907679 best DQS0 dly(2T, 0.5T) = (0, 10)
5487 13:15:21.911189 best DQS1 dly(2T, 0.5T) = (0, 10)
5488 13:15:21.914593 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5489 13:15:21.917469 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5490 13:15:21.920702 best DQS0 dly(2T, 0.5T) = (0, 10)
5491 13:15:21.923991 best DQS1 dly(2T, 0.5T) = (0, 10)
5492 13:15:21.927328 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5493 13:15:21.930938 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5494 13:15:21.931015 Pre-setting of DQS Precalculation
5495 13:15:21.937531 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5496 13:15:21.937612 ==
5497 13:15:21.941462 Dram Type= 6, Freq= 0, CH_1, rank 0
5498 13:15:21.944383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5499 13:15:21.944459 ==
5500 13:15:21.950860 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5501 13:15:21.957566 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5502 13:15:21.960739 [CA 0] Center 36 (6~67) winsize 62
5503 13:15:21.964227 [CA 1] Center 36 (6~67) winsize 62
5504 13:15:21.967797 [CA 2] Center 34 (4~64) winsize 61
5505 13:15:21.971245 [CA 3] Center 33 (3~64) winsize 62
5506 13:15:21.974602 [CA 4] Center 34 (4~64) winsize 61
5507 13:15:21.977628 [CA 5] Center 33 (3~64) winsize 62
5508 13:15:21.977705
5509 13:15:21.981464 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5510 13:15:21.981541
5511 13:15:21.984317 [CATrainingPosCal] consider 1 rank data
5512 13:15:21.987565 u2DelayCellTimex100 = 270/100 ps
5513 13:15:21.991159 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5514 13:15:21.994197 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5515 13:15:21.998080 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5516 13:15:22.001716 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5517 13:15:22.004284 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5518 13:15:22.007704 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5519 13:15:22.007781
5520 13:15:22.010739 CA PerBit enable=1, Macro0, CA PI delay=33
5521 13:15:22.014325
5522 13:15:22.014404 [CBTSetCACLKResult] CA Dly = 33
5523 13:15:22.017578 CS Dly: 4 (0~35)
5524 13:15:22.017654 ==
5525 13:15:22.021051 Dram Type= 6, Freq= 0, CH_1, rank 1
5526 13:15:22.024570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5527 13:15:22.024646 ==
5528 13:15:22.031185 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5529 13:15:22.037399 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5530 13:15:22.040804 [CA 0] Center 36 (6~67) winsize 62
5531 13:15:22.044148 [CA 1] Center 37 (7~67) winsize 61
5532 13:15:22.047529 [CA 2] Center 33 (3~64) winsize 62
5533 13:15:22.051146 [CA 3] Center 33 (2~64) winsize 63
5534 13:15:22.054478 [CA 4] Center 34 (4~64) winsize 61
5535 13:15:22.057775 [CA 5] Center 32 (2~63) winsize 62
5536 13:15:22.057851
5537 13:15:22.060826 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5538 13:15:22.060902
5539 13:15:22.064316 [CATrainingPosCal] consider 2 rank data
5540 13:15:22.067980 u2DelayCellTimex100 = 270/100 ps
5541 13:15:22.070852 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5542 13:15:22.074590 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5543 13:15:22.077749 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5544 13:15:22.081111 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5545 13:15:22.084505 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5546 13:15:22.087446 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5547 13:15:22.087522
5548 13:15:22.090819 CA PerBit enable=1, Macro0, CA PI delay=33
5549 13:15:22.090895
5550 13:15:22.094574 [CBTSetCACLKResult] CA Dly = 33
5551 13:15:22.097936 CS Dly: 5 (0~38)
5552 13:15:22.098012
5553 13:15:22.101010 ----->DramcWriteLeveling(PI) begin...
5554 13:15:22.101110 ==
5555 13:15:22.104075 Dram Type= 6, Freq= 0, CH_1, rank 0
5556 13:15:22.107487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 13:15:22.107564 ==
5558 13:15:22.111170 Write leveling (Byte 0): 26 => 26
5559 13:15:22.114293 Write leveling (Byte 1): 28 => 28
5560 13:15:22.117456 DramcWriteLeveling(PI) end<-----
5561 13:15:22.117532
5562 13:15:22.117591 ==
5563 13:15:22.121353 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 13:15:22.124204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 13:15:22.124281 ==
5566 13:15:22.127795 [Gating] SW mode calibration
5567 13:15:22.134409 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5568 13:15:22.141107 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5569 13:15:22.144519 0 14 0 | B1->B0 | 2f2f 3232 | 0 1 | (0 0) (0 0)
5570 13:15:22.148060 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 13:15:22.154750 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 13:15:22.157946 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 13:15:22.161337 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 13:15:22.168143 0 14 20 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
5575 13:15:22.170914 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 13:15:22.174746 0 14 28 | B1->B0 | 3030 3030 | 0 1 | (0 1) (1 0)
5577 13:15:22.180779 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5578 13:15:22.184490 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 13:15:22.187842 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 13:15:22.194436 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 13:15:22.197611 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 13:15:22.201050 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 13:15:22.208018 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 13:15:22.211335 0 15 28 | B1->B0 | 2929 2c2c | 0 1 | (0 0) (1 1)
5585 13:15:22.214331 1 0 0 | B1->B0 | 4444 4141 | 0 1 | (0 0) (0 0)
5586 13:15:22.220987 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 13:15:22.224109 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 13:15:22.227669 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 13:15:22.234168 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 13:15:22.237995 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 13:15:22.241238 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5592 13:15:22.244477 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5593 13:15:22.250939 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5594 13:15:22.254523 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 13:15:22.258054 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 13:15:22.264422 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 13:15:22.267618 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 13:15:22.271146 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 13:15:22.277667 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 13:15:22.281068 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 13:15:22.284343 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 13:15:22.291143 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 13:15:22.294806 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 13:15:22.298191 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 13:15:22.304426 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 13:15:22.307653 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 13:15:22.311234 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5608 13:15:22.318081 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5609 13:15:22.321419 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 13:15:22.324606 Total UI for P1: 0, mck2ui 16
5611 13:15:22.327814 best dqsien dly found for B0: ( 1, 2, 26)
5612 13:15:22.331107 Total UI for P1: 0, mck2ui 16
5613 13:15:22.334621 best dqsien dly found for B1: ( 1, 2, 28)
5614 13:15:22.338354 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5615 13:15:22.341067 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5616 13:15:22.341179
5617 13:15:22.344604 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5618 13:15:22.348246 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5619 13:15:22.351479 [Gating] SW calibration Done
5620 13:15:22.351559 ==
5621 13:15:22.354365 Dram Type= 6, Freq= 0, CH_1, rank 0
5622 13:15:22.358041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5623 13:15:22.358118 ==
5624 13:15:22.361282 RX Vref Scan: 0
5625 13:15:22.361372
5626 13:15:22.361432 RX Vref 0 -> 0, step: 1
5627 13:15:22.364292
5628 13:15:22.364367 RX Delay -80 -> 252, step: 8
5629 13:15:22.371239 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5630 13:15:22.374356 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5631 13:15:22.377679 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5632 13:15:22.381479 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5633 13:15:22.384715 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5634 13:15:22.387972 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5635 13:15:22.391003 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5636 13:15:22.398115 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5637 13:15:22.400974 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5638 13:15:22.404961 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5639 13:15:22.407982 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5640 13:15:22.411451 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5641 13:15:22.417936 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5642 13:15:22.421114 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5643 13:15:22.424857 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5644 13:15:22.428005 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5645 13:15:22.428081 ==
5646 13:15:22.431408 Dram Type= 6, Freq= 0, CH_1, rank 0
5647 13:15:22.434544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5648 13:15:22.434622 ==
5649 13:15:22.437800 DQS Delay:
5650 13:15:22.437875 DQS0 = 0, DQS1 = 0
5651 13:15:22.441344 DQM Delay:
5652 13:15:22.441419 DQM0 = 95, DQM1 = 89
5653 13:15:22.441477 DQ Delay:
5654 13:15:22.444741 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5655 13:15:22.448188 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5656 13:15:22.451172 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5657 13:15:22.455030 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5658 13:15:22.455106
5659 13:15:22.455165
5660 13:15:22.457932 ==
5661 13:15:22.461822 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 13:15:22.464832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 13:15:22.464908 ==
5664 13:15:22.464967
5665 13:15:22.465021
5666 13:15:22.467774 TX Vref Scan disable
5667 13:15:22.467849 == TX Byte 0 ==
5668 13:15:22.471372 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5669 13:15:22.478145 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5670 13:15:22.478222 == TX Byte 1 ==
5671 13:15:22.481572 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5672 13:15:22.488044 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5673 13:15:22.488121 ==
5674 13:15:22.491344 Dram Type= 6, Freq= 0, CH_1, rank 0
5675 13:15:22.494564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5676 13:15:22.494644 ==
5677 13:15:22.494704
5678 13:15:22.494757
5679 13:15:22.498070 TX Vref Scan disable
5680 13:15:22.501459 == TX Byte 0 ==
5681 13:15:22.504931 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5682 13:15:22.508341 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5683 13:15:22.511761 == TX Byte 1 ==
5684 13:15:22.514854 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5685 13:15:22.518529 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5686 13:15:22.518606
5687 13:15:22.518664 [DATLAT]
5688 13:15:22.521344 Freq=933, CH1 RK0
5689 13:15:22.521420
5690 13:15:22.521477 DATLAT Default: 0xd
5691 13:15:22.525072 0, 0xFFFF, sum = 0
5692 13:15:22.528365 1, 0xFFFF, sum = 0
5693 13:15:22.528442 2, 0xFFFF, sum = 0
5694 13:15:22.531739 3, 0xFFFF, sum = 0
5695 13:15:22.531816 4, 0xFFFF, sum = 0
5696 13:15:22.535415 5, 0xFFFF, sum = 0
5697 13:15:22.535491 6, 0xFFFF, sum = 0
5698 13:15:22.538316 7, 0xFFFF, sum = 0
5699 13:15:22.538393 8, 0xFFFF, sum = 0
5700 13:15:22.541240 9, 0xFFFF, sum = 0
5701 13:15:22.541317 10, 0x0, sum = 1
5702 13:15:22.545002 11, 0x0, sum = 2
5703 13:15:22.545080 12, 0x0, sum = 3
5704 13:15:22.545148 13, 0x0, sum = 4
5705 13:15:22.548086 best_step = 11
5706 13:15:22.548160
5707 13:15:22.548218 ==
5708 13:15:22.551747 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 13:15:22.554770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 13:15:22.554847 ==
5711 13:15:22.558422 RX Vref Scan: 1
5712 13:15:22.558497
5713 13:15:22.558556 RX Vref 0 -> 0, step: 1
5714 13:15:22.561668
5715 13:15:22.561745 RX Delay -61 -> 252, step: 4
5716 13:15:22.561804
5717 13:15:22.564845 Set Vref, RX VrefLevel [Byte0]: 56
5718 13:15:22.568547 [Byte1]: 50
5719 13:15:22.572726
5720 13:15:22.572802 Final RX Vref Byte 0 = 56 to rank0
5721 13:15:22.575886 Final RX Vref Byte 1 = 50 to rank0
5722 13:15:22.579765 Final RX Vref Byte 0 = 56 to rank1
5723 13:15:22.582578 Final RX Vref Byte 1 = 50 to rank1==
5724 13:15:22.586108 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 13:15:22.592821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 13:15:22.592907 ==
5727 13:15:22.592967 DQS Delay:
5728 13:15:22.593021 DQS0 = 0, DQS1 = 0
5729 13:15:22.595947 DQM Delay:
5730 13:15:22.596024 DQM0 = 98, DQM1 = 90
5731 13:15:22.599437 DQ Delay:
5732 13:15:22.602935 DQ0 =100, DQ1 =92, DQ2 =88, DQ3 =98
5733 13:15:22.605955 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5734 13:15:22.609642 DQ8 =78, DQ9 =76, DQ10 =90, DQ11 =86
5735 13:15:22.612855 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =96
5736 13:15:22.612952
5737 13:15:22.613036
5738 13:15:22.619797 [DQSOSCAuto] RK0, (LSB)MR18= 0x1cf8, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 412 ps
5739 13:15:22.622957 CH1 RK0: MR19=504, MR18=1CF8
5740 13:15:22.629215 CH1_RK0: MR19=0x504, MR18=0x1CF8, DQSOSC=412, MR23=63, INC=63, DEC=42
5741 13:15:22.629291
5742 13:15:22.633067 ----->DramcWriteLeveling(PI) begin...
5743 13:15:22.633154 ==
5744 13:15:22.636006 Dram Type= 6, Freq= 0, CH_1, rank 1
5745 13:15:22.639212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 13:15:22.639291 ==
5747 13:15:22.642896 Write leveling (Byte 0): 28 => 28
5748 13:15:22.646106 Write leveling (Byte 1): 30 => 30
5749 13:15:22.649301 DramcWriteLeveling(PI) end<-----
5750 13:15:22.649377
5751 13:15:22.649435 ==
5752 13:15:22.652633 Dram Type= 6, Freq= 0, CH_1, rank 1
5753 13:15:22.656218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5754 13:15:22.656324 ==
5755 13:15:22.659564 [Gating] SW mode calibration
5756 13:15:22.666258 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5757 13:15:22.673036 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5758 13:15:22.676171 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 13:15:22.679571 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 13:15:22.686133 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 13:15:22.690477 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5762 13:15:22.693412 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 13:15:22.699910 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 13:15:22.703205 0 14 24 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (1 0)
5765 13:15:22.706529 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
5766 13:15:22.710024 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 13:15:22.716911 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 13:15:22.720034 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 13:15:22.723276 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 13:15:22.729992 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 13:15:22.733501 0 15 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5772 13:15:22.736529 0 15 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5773 13:15:22.743136 0 15 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5774 13:15:22.746331 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 13:15:22.750145 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 13:15:22.756657 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 13:15:22.759778 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 13:15:22.763450 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 13:15:22.769878 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 13:15:22.773524 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5781 13:15:22.776665 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 13:15:22.783428 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 13:15:22.787017 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 13:15:22.790364 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 13:15:22.793533 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 13:15:22.800408 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 13:15:22.804012 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 13:15:22.807155 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 13:15:22.813658 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 13:15:22.816961 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 13:15:22.820283 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 13:15:22.826996 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 13:15:22.829957 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 13:15:22.833928 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 13:15:22.840057 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 13:15:22.843547 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5797 13:15:22.847005 Total UI for P1: 0, mck2ui 16
5798 13:15:22.850359 best dqsien dly found for B0: ( 1, 2, 22)
5799 13:15:22.853367 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 13:15:22.856765 Total UI for P1: 0, mck2ui 16
5801 13:15:22.860002 best dqsien dly found for B1: ( 1, 2, 24)
5802 13:15:22.863923 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5803 13:15:22.867018 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5804 13:15:22.867082
5805 13:15:22.870213 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5806 13:15:22.876655 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5807 13:15:22.876733 [Gating] SW calibration Done
5808 13:15:22.880445 ==
5809 13:15:22.880529 Dram Type= 6, Freq= 0, CH_1, rank 1
5810 13:15:22.886608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 13:15:22.886684 ==
5812 13:15:22.886743 RX Vref Scan: 0
5813 13:15:22.886797
5814 13:15:22.890202 RX Vref 0 -> 0, step: 1
5815 13:15:22.890300
5816 13:15:22.893454 RX Delay -80 -> 252, step: 8
5817 13:15:22.896954 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5818 13:15:22.900523 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5819 13:15:22.903867 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5820 13:15:22.906728 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5821 13:15:22.913557 iDelay=200, Bit 4, Center 91 (-8 ~ 191) 200
5822 13:15:22.916878 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5823 13:15:22.919942 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5824 13:15:22.923423 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5825 13:15:22.926767 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5826 13:15:22.929954 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5827 13:15:22.936896 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5828 13:15:22.940206 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5829 13:15:22.943711 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5830 13:15:22.946680 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5831 13:15:22.949915 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5832 13:15:22.956891 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5833 13:15:22.956958 ==
5834 13:15:22.959839 Dram Type= 6, Freq= 0, CH_1, rank 1
5835 13:15:22.963304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5836 13:15:22.963368 ==
5837 13:15:22.963420 DQS Delay:
5838 13:15:22.966701 DQS0 = 0, DQS1 = 0
5839 13:15:22.966761 DQM Delay:
5840 13:15:22.970030 DQM0 = 93, DQM1 = 88
5841 13:15:22.970091 DQ Delay:
5842 13:15:22.973606 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5843 13:15:22.976766 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =87
5844 13:15:22.980044 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5845 13:15:22.983127 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5846 13:15:22.983195
5847 13:15:22.983250
5848 13:15:22.983302 ==
5849 13:15:22.986665 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 13:15:22.990183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 13:15:22.990260 ==
5852 13:15:22.990315
5853 13:15:22.990366
5854 13:15:22.993864 TX Vref Scan disable
5855 13:15:22.996479 == TX Byte 0 ==
5856 13:15:23.000289 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5857 13:15:23.003029 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5858 13:15:23.006657 == TX Byte 1 ==
5859 13:15:23.009985 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5860 13:15:23.013294 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5861 13:15:23.013371 ==
5862 13:15:23.016890 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 13:15:23.023272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 13:15:23.023349 ==
5865 13:15:23.023408
5866 13:15:23.023461
5867 13:15:23.023511 TX Vref Scan disable
5868 13:15:23.027004 == TX Byte 0 ==
5869 13:15:23.030173 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5870 13:15:23.033900 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5871 13:15:23.037309 == TX Byte 1 ==
5872 13:15:23.040601 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5873 13:15:23.043687 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5874 13:15:23.047016
5875 13:15:23.047092 [DATLAT]
5876 13:15:23.047150 Freq=933, CH1 RK1
5877 13:15:23.047205
5878 13:15:23.050353 DATLAT Default: 0xb
5879 13:15:23.050429 0, 0xFFFF, sum = 0
5880 13:15:23.053525 1, 0xFFFF, sum = 0
5881 13:15:23.053602 2, 0xFFFF, sum = 0
5882 13:15:23.057770 3, 0xFFFF, sum = 0
5883 13:15:23.057847 4, 0xFFFF, sum = 0
5884 13:15:23.060582 5, 0xFFFF, sum = 0
5885 13:15:23.063479 6, 0xFFFF, sum = 0
5886 13:15:23.063556 7, 0xFFFF, sum = 0
5887 13:15:23.066857 8, 0xFFFF, sum = 0
5888 13:15:23.066933 9, 0xFFFF, sum = 0
5889 13:15:23.070109 10, 0x0, sum = 1
5890 13:15:23.070186 11, 0x0, sum = 2
5891 13:15:23.070245 12, 0x0, sum = 3
5892 13:15:23.074115 13, 0x0, sum = 4
5893 13:15:23.074192 best_step = 11
5894 13:15:23.074250
5895 13:15:23.074303 ==
5896 13:15:23.077006 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 13:15:23.083865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 13:15:23.083945 ==
5899 13:15:23.084004 RX Vref Scan: 0
5900 13:15:23.084058
5901 13:15:23.086992 RX Vref 0 -> 0, step: 1
5902 13:15:23.087069
5903 13:15:23.090538 RX Delay -61 -> 252, step: 4
5904 13:15:23.093657 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5905 13:15:23.100223 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5906 13:15:23.103712 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5907 13:15:23.107047 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5908 13:15:23.110416 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5909 13:15:23.114346 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5910 13:15:23.116972 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5911 13:15:23.120559 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5912 13:15:23.127139 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5913 13:15:23.130220 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5914 13:15:23.133632 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5915 13:15:23.137404 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5916 13:15:23.140339 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5917 13:15:23.147067 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5918 13:15:23.150443 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5919 13:15:23.154169 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5920 13:15:23.154246 ==
5921 13:15:23.157619 Dram Type= 6, Freq= 0, CH_1, rank 1
5922 13:15:23.160383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5923 13:15:23.160459 ==
5924 13:15:23.163895 DQS Delay:
5925 13:15:23.163970 DQS0 = 0, DQS1 = 0
5926 13:15:23.164029 DQM Delay:
5927 13:15:23.167263 DQM0 = 95, DQM1 = 91
5928 13:15:23.167339 DQ Delay:
5929 13:15:23.170282 DQ0 =98, DQ1 =88, DQ2 =84, DQ3 =92
5930 13:15:23.173873 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =92
5931 13:15:23.177024 DQ8 =78, DQ9 =80, DQ10 =90, DQ11 =84
5932 13:15:23.180471 DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =98
5933 13:15:23.180547
5934 13:15:23.180606
5935 13:15:23.190417 [DQSOSCAuto] RK1, (LSB)MR18= 0x121b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
5936 13:15:23.193672 CH1 RK1: MR19=505, MR18=121B
5937 13:15:23.196811 CH1_RK1: MR19=0x505, MR18=0x121B, DQSOSC=413, MR23=63, INC=63, DEC=42
5938 13:15:23.200371 [RxdqsGatingPostProcess] freq 933
5939 13:15:23.207467 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5940 13:15:23.210356 best DQS0 dly(2T, 0.5T) = (0, 10)
5941 13:15:23.214328 best DQS1 dly(2T, 0.5T) = (0, 10)
5942 13:15:23.217249 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5943 13:15:23.220362 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5944 13:15:23.223713 best DQS0 dly(2T, 0.5T) = (0, 10)
5945 13:15:23.227133 best DQS1 dly(2T, 0.5T) = (0, 10)
5946 13:15:23.231091 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5947 13:15:23.231167 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5948 13:15:23.234098 Pre-setting of DQS Precalculation
5949 13:15:23.240938 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5950 13:15:23.247636 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5951 13:15:23.254063 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5952 13:15:23.254141
5953 13:15:23.254199
5954 13:15:23.256945 [Calibration Summary] 1866 Mbps
5955 13:15:23.260428 CH 0, Rank 0
5956 13:15:23.260503 SW Impedance : PASS
5957 13:15:23.263878 DUTY Scan : NO K
5958 13:15:23.267336 ZQ Calibration : PASS
5959 13:15:23.267412 Jitter Meter : NO K
5960 13:15:23.270463 CBT Training : PASS
5961 13:15:23.270564 Write leveling : PASS
5962 13:15:23.274049 RX DQS gating : PASS
5963 13:15:23.277041 RX DQ/DQS(RDDQC) : PASS
5964 13:15:23.277168 TX DQ/DQS : PASS
5965 13:15:23.280376 RX DATLAT : PASS
5966 13:15:23.283788 RX DQ/DQS(Engine): PASS
5967 13:15:23.283865 TX OE : NO K
5968 13:15:23.287146 All Pass.
5969 13:15:23.287221
5970 13:15:23.287279 CH 0, Rank 1
5971 13:15:23.290338 SW Impedance : PASS
5972 13:15:23.290414 DUTY Scan : NO K
5973 13:15:23.293729 ZQ Calibration : PASS
5974 13:15:23.297143 Jitter Meter : NO K
5975 13:15:23.297261 CBT Training : PASS
5976 13:15:23.300161 Write leveling : PASS
5977 13:15:23.303849 RX DQS gating : PASS
5978 13:15:23.303916 RX DQ/DQS(RDDQC) : PASS
5979 13:15:23.306793 TX DQ/DQS : PASS
5980 13:15:23.310702 RX DATLAT : PASS
5981 13:15:23.310768 RX DQ/DQS(Engine): PASS
5982 13:15:23.314328 TX OE : NO K
5983 13:15:23.314401 All Pass.
5984 13:15:23.314454
5985 13:15:23.317269 CH 1, Rank 0
5986 13:15:23.317331 SW Impedance : PASS
5987 13:15:23.320590 DUTY Scan : NO K
5988 13:15:23.320680 ZQ Calibration : PASS
5989 13:15:23.323967 Jitter Meter : NO K
5990 13:15:23.327429 CBT Training : PASS
5991 13:15:23.327495 Write leveling : PASS
5992 13:15:23.330833 RX DQS gating : PASS
5993 13:15:23.333683 RX DQ/DQS(RDDQC) : PASS
5994 13:15:23.333749 TX DQ/DQS : PASS
5995 13:15:23.337065 RX DATLAT : PASS
5996 13:15:23.340966 RX DQ/DQS(Engine): PASS
5997 13:15:23.341074 TX OE : NO K
5998 13:15:23.343897 All Pass.
5999 13:15:23.343974
6000 13:15:23.344032 CH 1, Rank 1
6001 13:15:23.347356 SW Impedance : PASS
6002 13:15:23.347433 DUTY Scan : NO K
6003 13:15:23.350396 ZQ Calibration : PASS
6004 13:15:23.353501 Jitter Meter : NO K
6005 13:15:23.353583 CBT Training : PASS
6006 13:15:23.357048 Write leveling : PASS
6007 13:15:23.357169 RX DQS gating : PASS
6008 13:15:23.360284 RX DQ/DQS(RDDQC) : PASS
6009 13:15:23.363901 TX DQ/DQS : PASS
6010 13:15:23.363978 RX DATLAT : PASS
6011 13:15:23.367359 RX DQ/DQS(Engine): PASS
6012 13:15:23.370601 TX OE : NO K
6013 13:15:23.370688 All Pass.
6014 13:15:23.370749
6015 13:15:23.373877 DramC Write-DBI off
6016 13:15:23.373953 PER_BANK_REFRESH: Hybrid Mode
6017 13:15:23.376917 TX_TRACKING: ON
6018 13:15:23.383984 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6019 13:15:23.390379 [FAST_K] Save calibration result to emmc
6020 13:15:23.393933 dramc_set_vcore_voltage set vcore to 650000
6021 13:15:23.394009 Read voltage for 400, 6
6022 13:15:23.397449 Vio18 = 0
6023 13:15:23.397531 Vcore = 650000
6024 13:15:23.397587 Vdram = 0
6025 13:15:23.400232 Vddq = 0
6026 13:15:23.400293 Vmddr = 0
6027 13:15:23.403983 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6028 13:15:23.410839 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6029 13:15:23.413873 MEM_TYPE=3, freq_sel=20
6030 13:15:23.417359 sv_algorithm_assistance_LP4_800
6031 13:15:23.420411 ============ PULL DRAM RESETB DOWN ============
6032 13:15:23.423667 ========== PULL DRAM RESETB DOWN end =========
6033 13:15:23.427191 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6034 13:15:23.430603 ===================================
6035 13:15:23.434203 LPDDR4 DRAM CONFIGURATION
6036 13:15:23.436924 ===================================
6037 13:15:23.440443 EX_ROW_EN[0] = 0x0
6038 13:15:23.440510 EX_ROW_EN[1] = 0x0
6039 13:15:23.444219 LP4Y_EN = 0x0
6040 13:15:23.444285 WORK_FSP = 0x0
6041 13:15:23.447132 WL = 0x2
6042 13:15:23.447195 RL = 0x2
6043 13:15:23.450737 BL = 0x2
6044 13:15:23.450802 RPST = 0x0
6045 13:15:23.454506 RD_PRE = 0x0
6046 13:15:23.454569 WR_PRE = 0x1
6047 13:15:23.457897 WR_PST = 0x0
6048 13:15:23.457976 DBI_WR = 0x0
6049 13:15:23.461005 DBI_RD = 0x0
6050 13:15:23.461104 OTF = 0x1
6051 13:15:23.464361 ===================================
6052 13:15:23.467522 ===================================
6053 13:15:23.470578 ANA top config
6054 13:15:23.474434 ===================================
6055 13:15:23.477221 DLL_ASYNC_EN = 0
6056 13:15:23.477302 ALL_SLAVE_EN = 1
6057 13:15:23.480825 NEW_RANK_MODE = 1
6058 13:15:23.483962 DLL_IDLE_MODE = 1
6059 13:15:23.487483 LP45_APHY_COMB_EN = 1
6060 13:15:23.487561 TX_ODT_DIS = 1
6061 13:15:23.490771 NEW_8X_MODE = 1
6062 13:15:23.493902 ===================================
6063 13:15:23.497583 ===================================
6064 13:15:23.500833 data_rate = 800
6065 13:15:23.503898 CKR = 1
6066 13:15:23.507901 DQ_P2S_RATIO = 4
6067 13:15:23.510598 ===================================
6068 13:15:23.513922 CA_P2S_RATIO = 4
6069 13:15:23.513989 DQ_CA_OPEN = 0
6070 13:15:23.517492 DQ_SEMI_OPEN = 1
6071 13:15:23.521408 CA_SEMI_OPEN = 1
6072 13:15:23.523899 CA_FULL_RATE = 0
6073 13:15:23.527267 DQ_CKDIV4_EN = 0
6074 13:15:23.530612 CA_CKDIV4_EN = 1
6075 13:15:23.530681 CA_PREDIV_EN = 0
6076 13:15:23.534334 PH8_DLY = 0
6077 13:15:23.537498 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6078 13:15:23.540936 DQ_AAMCK_DIV = 0
6079 13:15:23.544018 CA_AAMCK_DIV = 0
6080 13:15:23.544085 CA_ADMCK_DIV = 4
6081 13:15:23.547789 DQ_TRACK_CA_EN = 0
6082 13:15:23.550613 CA_PICK = 800
6083 13:15:23.554716 CA_MCKIO = 400
6084 13:15:23.557567 MCKIO_SEMI = 400
6085 13:15:23.560870 PLL_FREQ = 3016
6086 13:15:23.564427 DQ_UI_PI_RATIO = 32
6087 13:15:23.568071 CA_UI_PI_RATIO = 32
6088 13:15:23.568143 ===================================
6089 13:15:23.571136 ===================================
6090 13:15:23.574345 memory_type:LPDDR4
6091 13:15:23.577787 GP_NUM : 10
6092 13:15:23.577863 SRAM_EN : 1
6093 13:15:23.580854 MD32_EN : 0
6094 13:15:23.584601 ===================================
6095 13:15:23.587370 [ANA_INIT] >>>>>>>>>>>>>>
6096 13:15:23.591194 <<<<<< [CONFIGURE PHASE]: ANA_TX
6097 13:15:23.594303 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6098 13:15:23.597917 ===================================
6099 13:15:23.598027 data_rate = 800,PCW = 0X7400
6100 13:15:23.600985 ===================================
6101 13:15:23.604169 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6102 13:15:23.610913 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6103 13:15:23.624286 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6104 13:15:23.627662 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6105 13:15:23.630890 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6106 13:15:23.634028 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6107 13:15:23.637747 [ANA_INIT] flow start
6108 13:15:23.637817 [ANA_INIT] PLL >>>>>>>>
6109 13:15:23.640812 [ANA_INIT] PLL <<<<<<<<
6110 13:15:23.644244 [ANA_INIT] MIDPI >>>>>>>>
6111 13:15:23.644313 [ANA_INIT] MIDPI <<<<<<<<
6112 13:15:23.647939 [ANA_INIT] DLL >>>>>>>>
6113 13:15:23.651299 [ANA_INIT] flow end
6114 13:15:23.654338 ============ LP4 DIFF to SE enter ============
6115 13:15:23.657916 ============ LP4 DIFF to SE exit ============
6116 13:15:23.660954 [ANA_INIT] <<<<<<<<<<<<<
6117 13:15:23.664181 [Flow] Enable top DCM control >>>>>
6118 13:15:23.668101 [Flow] Enable top DCM control <<<<<
6119 13:15:23.671276 Enable DLL master slave shuffle
6120 13:15:23.674797 ==============================================================
6121 13:15:23.677557 Gating Mode config
6122 13:15:23.681054 ==============================================================
6123 13:15:23.684772 Config description:
6124 13:15:23.694919 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6125 13:15:23.701286 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6126 13:15:23.704298 SELPH_MODE 0: By rank 1: By Phase
6127 13:15:23.711371 ==============================================================
6128 13:15:23.714592 GAT_TRACK_EN = 0
6129 13:15:23.718341 RX_GATING_MODE = 2
6130 13:15:23.721252 RX_GATING_TRACK_MODE = 2
6131 13:15:23.725077 SELPH_MODE = 1
6132 13:15:23.725239 PICG_EARLY_EN = 1
6133 13:15:23.727756 VALID_LAT_VALUE = 1
6134 13:15:23.734722 ==============================================================
6135 13:15:23.737865 Enter into Gating configuration >>>>
6136 13:15:23.741497 Exit from Gating configuration <<<<
6137 13:15:23.744730 Enter into DVFS_PRE_config >>>>>
6138 13:15:23.754800 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6139 13:15:23.758445 Exit from DVFS_PRE_config <<<<<
6140 13:15:23.761494 Enter into PICG configuration >>>>
6141 13:15:23.764451 Exit from PICG configuration <<<<
6142 13:15:23.768241 [RX_INPUT] configuration >>>>>
6143 13:15:23.771571 [RX_INPUT] configuration <<<<<
6144 13:15:23.774779 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6145 13:15:23.781430 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6146 13:15:23.787990 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6147 13:15:23.794838 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6148 13:15:23.798113 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6149 13:15:23.805044 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6150 13:15:23.808070 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6151 13:15:23.814434 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6152 13:15:23.818049 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6153 13:15:23.821439 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6154 13:15:23.825234 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6155 13:15:23.831236 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6156 13:15:23.834671 ===================================
6157 13:15:23.834751 LPDDR4 DRAM CONFIGURATION
6158 13:15:23.838261 ===================================
6159 13:15:23.841494 EX_ROW_EN[0] = 0x0
6160 13:15:23.844743 EX_ROW_EN[1] = 0x0
6161 13:15:23.844830 LP4Y_EN = 0x0
6162 13:15:23.848255 WORK_FSP = 0x0
6163 13:15:23.848331 WL = 0x2
6164 13:15:23.851392 RL = 0x2
6165 13:15:23.851468 BL = 0x2
6166 13:15:23.855282 RPST = 0x0
6167 13:15:23.855358 RD_PRE = 0x0
6168 13:15:23.858081 WR_PRE = 0x1
6169 13:15:23.858158 WR_PST = 0x0
6170 13:15:23.861280 DBI_WR = 0x0
6171 13:15:23.861355 DBI_RD = 0x0
6172 13:15:23.864862 OTF = 0x1
6173 13:15:23.868173 ===================================
6174 13:15:23.871576 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6175 13:15:23.875029 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6176 13:15:23.881229 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6177 13:15:23.884925 ===================================
6178 13:15:23.885002 LPDDR4 DRAM CONFIGURATION
6179 13:15:23.888160 ===================================
6180 13:15:23.891544 EX_ROW_EN[0] = 0x10
6181 13:15:23.891620 EX_ROW_EN[1] = 0x0
6182 13:15:23.895658 LP4Y_EN = 0x0
6183 13:15:23.895734 WORK_FSP = 0x0
6184 13:15:23.898141 WL = 0x2
6185 13:15:23.901416 RL = 0x2
6186 13:15:23.901493 BL = 0x2
6187 13:15:23.905048 RPST = 0x0
6188 13:15:23.905165 RD_PRE = 0x0
6189 13:15:23.908250 WR_PRE = 0x1
6190 13:15:23.908320 WR_PST = 0x0
6191 13:15:23.911748 DBI_WR = 0x0
6192 13:15:23.911814 DBI_RD = 0x0
6193 13:15:23.914555 OTF = 0x1
6194 13:15:23.918237 ===================================
6195 13:15:23.921418 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6196 13:15:23.926878 nWR fixed to 30
6197 13:15:23.930553 [ModeRegInit_LP4] CH0 RK0
6198 13:15:23.930619 [ModeRegInit_LP4] CH0 RK1
6199 13:15:23.933611 [ModeRegInit_LP4] CH1 RK0
6200 13:15:23.936713 [ModeRegInit_LP4] CH1 RK1
6201 13:15:23.936777 match AC timing 19
6202 13:15:23.943658 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6203 13:15:23.947003 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6204 13:15:23.950261 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6205 13:15:23.956690 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6206 13:15:23.960072 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6207 13:15:23.960149 ==
6208 13:15:23.963959 Dram Type= 6, Freq= 0, CH_0, rank 0
6209 13:15:23.966992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6210 13:15:23.967068 ==
6211 13:15:23.973574 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6212 13:15:23.980343 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6213 13:15:23.983920 [CA 0] Center 36 (8~64) winsize 57
6214 13:15:23.986989 [CA 1] Center 36 (8~64) winsize 57
6215 13:15:23.990047 [CA 2] Center 36 (8~64) winsize 57
6216 13:15:23.990119 [CA 3] Center 36 (8~64) winsize 57
6217 13:15:23.993622 [CA 4] Center 36 (8~64) winsize 57
6218 13:15:23.996584 [CA 5] Center 36 (8~64) winsize 57
6219 13:15:23.996652
6220 13:15:24.000399 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6221 13:15:24.003531
6222 13:15:24.007578 [CATrainingPosCal] consider 1 rank data
6223 13:15:24.007647 u2DelayCellTimex100 = 270/100 ps
6224 13:15:24.013766 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 13:15:24.017024 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 13:15:24.020199 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 13:15:24.023653 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 13:15:24.027227 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 13:15:24.030549 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 13:15:24.030652
6231 13:15:24.033555 CA PerBit enable=1, Macro0, CA PI delay=36
6232 13:15:24.033641
6233 13:15:24.037249 [CBTSetCACLKResult] CA Dly = 36
6234 13:15:24.037338 CS Dly: 1 (0~32)
6235 13:15:24.040468 ==
6236 13:15:24.043711 Dram Type= 6, Freq= 0, CH_0, rank 1
6237 13:15:24.047269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6238 13:15:24.047372 ==
6239 13:15:24.050562 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6240 13:15:24.057285 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6241 13:15:24.060399 [CA 0] Center 36 (8~64) winsize 57
6242 13:15:24.063770 [CA 1] Center 36 (8~64) winsize 57
6243 13:15:24.067177 [CA 2] Center 36 (8~64) winsize 57
6244 13:15:24.070667 [CA 3] Center 36 (8~64) winsize 57
6245 13:15:24.073858 [CA 4] Center 36 (8~64) winsize 57
6246 13:15:24.077142 [CA 5] Center 36 (8~64) winsize 57
6247 13:15:24.077254
6248 13:15:24.080482 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6249 13:15:24.080572
6250 13:15:24.083570 [CATrainingPosCal] consider 2 rank data
6251 13:15:24.087724 u2DelayCellTimex100 = 270/100 ps
6252 13:15:24.090268 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 13:15:24.093818 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 13:15:24.097331 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 13:15:24.100456 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 13:15:24.103821 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 13:15:24.110669 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 13:15:24.110797
6259 13:15:24.114744 CA PerBit enable=1, Macro0, CA PI delay=36
6260 13:15:24.114840
6261 13:15:24.117092 [CBTSetCACLKResult] CA Dly = 36
6262 13:15:24.117202 CS Dly: 1 (0~32)
6263 13:15:24.117261
6264 13:15:24.120440 ----->DramcWriteLeveling(PI) begin...
6265 13:15:24.120531 ==
6266 13:15:24.123951 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 13:15:24.127077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 13:15:24.130616 ==
6269 13:15:24.130717 Write leveling (Byte 0): 40 => 8
6270 13:15:24.134011 Write leveling (Byte 1): 32 => 0
6271 13:15:24.137330 DramcWriteLeveling(PI) end<-----
6272 13:15:24.137426
6273 13:15:24.137486 ==
6274 13:15:24.140387 Dram Type= 6, Freq= 0, CH_0, rank 0
6275 13:15:24.147228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 13:15:24.147345 ==
6277 13:15:24.147409 [Gating] SW mode calibration
6278 13:15:24.156915 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6279 13:15:24.160664 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6280 13:15:24.163667 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6281 13:15:24.170641 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6282 13:15:24.173703 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6283 13:15:24.177548 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6284 13:15:24.184102 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 13:15:24.187437 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6286 13:15:24.190800 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6287 13:15:24.197111 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6288 13:15:24.200786 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 13:15:24.203889 Total UI for P1: 0, mck2ui 16
6290 13:15:24.207319 best dqsien dly found for B0: ( 0, 14, 24)
6291 13:15:24.210623 Total UI for P1: 0, mck2ui 16
6292 13:15:24.213949 best dqsien dly found for B1: ( 0, 14, 24)
6293 13:15:24.217372 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6294 13:15:24.221100 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6295 13:15:24.221226
6296 13:15:24.224289 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6297 13:15:24.228158 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6298 13:15:24.230942 [Gating] SW calibration Done
6299 13:15:24.231026 ==
6300 13:15:24.233808 Dram Type= 6, Freq= 0, CH_0, rank 0
6301 13:15:24.237416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 13:15:24.237510 ==
6303 13:15:24.240604 RX Vref Scan: 0
6304 13:15:24.240689
6305 13:15:24.243752 RX Vref 0 -> 0, step: 1
6306 13:15:24.243842
6307 13:15:24.247053 RX Delay -410 -> 252, step: 16
6308 13:15:24.250583 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6309 13:15:24.253933 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6310 13:15:24.257009 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6311 13:15:24.263810 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6312 13:15:24.267236 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6313 13:15:24.270467 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6314 13:15:24.273465 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6315 13:15:24.280608 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6316 13:15:24.283901 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6317 13:15:24.287188 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6318 13:15:24.290416 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6319 13:15:24.297323 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6320 13:15:24.300201 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6321 13:15:24.303790 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6322 13:15:24.307010 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6323 13:15:24.313360 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6324 13:15:24.313439 ==
6325 13:15:24.316753 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 13:15:24.320222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 13:15:24.320297 ==
6328 13:15:24.320354 DQS Delay:
6329 13:15:24.323484 DQS0 = 43, DQS1 = 51
6330 13:15:24.323557 DQM Delay:
6331 13:15:24.327313 DQM0 = 14, DQM1 = 10
6332 13:15:24.327387 DQ Delay:
6333 13:15:24.329950 DQ0 =16, DQ1 =8, DQ2 =8, DQ3 =8
6334 13:15:24.333984 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6335 13:15:24.336509 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6336 13:15:24.340095 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6337 13:15:24.340159
6338 13:15:24.340212
6339 13:15:24.340261 ==
6340 13:15:24.343665 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 13:15:24.346491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 13:15:24.346569 ==
6343 13:15:24.346622
6344 13:15:24.346674
6345 13:15:24.349875 TX Vref Scan disable
6346 13:15:24.353307 == TX Byte 0 ==
6347 13:15:24.356590 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 13:15:24.360279 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 13:15:24.363368 == TX Byte 1 ==
6350 13:15:24.366600 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6351 13:15:24.369931 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6352 13:15:24.369998 ==
6353 13:15:24.373425 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 13:15:24.376627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 13:15:24.376704 ==
6356 13:15:24.380062
6357 13:15:24.380135
6358 13:15:24.380190 TX Vref Scan disable
6359 13:15:24.383499 == TX Byte 0 ==
6360 13:15:24.386650 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6361 13:15:24.389909 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6362 13:15:24.393148 == TX Byte 1 ==
6363 13:15:24.396772 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6364 13:15:24.399800 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6365 13:15:24.399895
6366 13:15:24.403052 [DATLAT]
6367 13:15:24.403118 Freq=400, CH0 RK0
6368 13:15:24.403173
6369 13:15:24.406998 DATLAT Default: 0xf
6370 13:15:24.407071 0, 0xFFFF, sum = 0
6371 13:15:24.410016 1, 0xFFFF, sum = 0
6372 13:15:24.410086 2, 0xFFFF, sum = 0
6373 13:15:24.413069 3, 0xFFFF, sum = 0
6374 13:15:24.413190 4, 0xFFFF, sum = 0
6375 13:15:24.416856 5, 0xFFFF, sum = 0
6376 13:15:24.416948 6, 0xFFFF, sum = 0
6377 13:15:24.419812 7, 0xFFFF, sum = 0
6378 13:15:24.419901 8, 0xFFFF, sum = 0
6379 13:15:24.423332 9, 0xFFFF, sum = 0
6380 13:15:24.423398 10, 0xFFFF, sum = 0
6381 13:15:24.426583 11, 0xFFFF, sum = 0
6382 13:15:24.426657 12, 0xFFFF, sum = 0
6383 13:15:24.429833 13, 0x0, sum = 1
6384 13:15:24.429929 14, 0x0, sum = 2
6385 13:15:24.433281 15, 0x0, sum = 3
6386 13:15:24.433349 16, 0x0, sum = 4
6387 13:15:24.436560 best_step = 14
6388 13:15:24.436626
6389 13:15:24.436679 ==
6390 13:15:24.440177 Dram Type= 6, Freq= 0, CH_0, rank 0
6391 13:15:24.443965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6392 13:15:24.444063 ==
6393 13:15:24.446678 RX Vref Scan: 1
6394 13:15:24.446741
6395 13:15:24.446794 RX Vref 0 -> 0, step: 1
6396 13:15:24.446844
6397 13:15:24.450026 RX Delay -343 -> 252, step: 8
6398 13:15:24.450096
6399 13:15:24.453624 Set Vref, RX VrefLevel [Byte0]: 54
6400 13:15:24.456534 [Byte1]: 51
6401 13:15:24.460884
6402 13:15:24.460979 Final RX Vref Byte 0 = 54 to rank0
6403 13:15:24.464280 Final RX Vref Byte 1 = 51 to rank0
6404 13:15:24.467499 Final RX Vref Byte 0 = 54 to rank1
6405 13:15:24.470958 Final RX Vref Byte 1 = 51 to rank1==
6406 13:15:24.474375 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 13:15:24.480901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 13:15:24.481007 ==
6409 13:15:24.481091 DQS Delay:
6410 13:15:24.484792 DQS0 = 44, DQS1 = 60
6411 13:15:24.484863 DQM Delay:
6412 13:15:24.484917 DQM0 = 11, DQM1 = 14
6413 13:15:24.487308 DQ Delay:
6414 13:15:24.490780 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6415 13:15:24.490846 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6416 13:15:24.494037 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6417 13:15:24.497660 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6418 13:15:24.497727
6419 13:15:24.501040
6420 13:15:24.507495 [DQSOSCAuto] RK0, (LSB)MR18= 0x8958, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6421 13:15:24.510751 CH0 RK0: MR19=C0C, MR18=8958
6422 13:15:24.517962 CH0_RK0: MR19=0xC0C, MR18=0x8958, DQSOSC=392, MR23=63, INC=384, DEC=256
6423 13:15:24.518044 ==
6424 13:15:24.521036 Dram Type= 6, Freq= 0, CH_0, rank 1
6425 13:15:24.524507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 13:15:24.524587 ==
6427 13:15:24.527587 [Gating] SW mode calibration
6428 13:15:24.534131 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6429 13:15:24.537600 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6430 13:15:24.544426 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6431 13:15:24.547447 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6432 13:15:24.550867 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6433 13:15:24.557598 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6434 13:15:24.561164 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 13:15:24.564661 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6436 13:15:24.571185 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6437 13:15:24.574389 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 13:15:24.577432 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 13:15:24.581306 Total UI for P1: 0, mck2ui 16
6440 13:15:24.584131 best dqsien dly found for B0: ( 0, 14, 24)
6441 13:15:24.587338 Total UI for P1: 0, mck2ui 16
6442 13:15:24.591070 best dqsien dly found for B1: ( 0, 14, 24)
6443 13:15:24.594267 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6444 13:15:24.597794 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6445 13:15:24.597870
6446 13:15:24.604440 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6447 13:15:24.607418 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6448 13:15:24.607495 [Gating] SW calibration Done
6449 13:15:24.611078 ==
6450 13:15:24.614558 Dram Type= 6, Freq= 0, CH_0, rank 1
6451 13:15:24.617776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 13:15:24.617853 ==
6453 13:15:24.617912 RX Vref Scan: 0
6454 13:15:24.617966
6455 13:15:24.620915 RX Vref 0 -> 0, step: 1
6456 13:15:24.620990
6457 13:15:24.624225 RX Delay -410 -> 252, step: 16
6458 13:15:24.628163 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6459 13:15:24.631238 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6460 13:15:24.637973 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6461 13:15:24.641260 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6462 13:15:24.644446 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6463 13:15:24.648460 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6464 13:15:24.654732 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6465 13:15:24.657865 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6466 13:15:24.661075 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6467 13:15:24.664629 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6468 13:15:24.671446 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6469 13:15:24.674902 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6470 13:15:24.677885 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6471 13:15:24.681233 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6472 13:15:24.687848 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6473 13:15:24.690987 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6474 13:15:24.691064 ==
6475 13:15:24.694722 Dram Type= 6, Freq= 0, CH_0, rank 1
6476 13:15:24.697661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 13:15:24.697739 ==
6478 13:15:24.701113 DQS Delay:
6479 13:15:24.701227 DQS0 = 43, DQS1 = 51
6480 13:15:24.701289 DQM Delay:
6481 13:15:24.704426 DQM0 = 11, DQM1 = 10
6482 13:15:24.704502 DQ Delay:
6483 13:15:24.708074 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6484 13:15:24.711084 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6485 13:15:24.714589 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6486 13:15:24.718071 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6487 13:15:24.718147
6488 13:15:24.718206
6489 13:15:24.718260 ==
6490 13:15:24.721263 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 13:15:24.724739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 13:15:24.728375 ==
6493 13:15:24.728495
6494 13:15:24.728557
6495 13:15:24.728610 TX Vref Scan disable
6496 13:15:24.731062 == TX Byte 0 ==
6497 13:15:24.734876 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6498 13:15:24.737733 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6499 13:15:24.741364 == TX Byte 1 ==
6500 13:15:24.744338 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6501 13:15:24.747813 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6502 13:15:24.747890 ==
6503 13:15:24.751362 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 13:15:24.754618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 13:15:24.754695 ==
6506 13:15:24.757716
6507 13:15:24.757792
6508 13:15:24.757850 TX Vref Scan disable
6509 13:15:24.761636 == TX Byte 0 ==
6510 13:15:24.765029 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6511 13:15:24.767993 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6512 13:15:24.770983 == TX Byte 1 ==
6513 13:15:24.774596 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6514 13:15:24.777894 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6515 13:15:24.777971
6516 13:15:24.778030 [DATLAT]
6517 13:15:24.781274 Freq=400, CH0 RK1
6518 13:15:24.781352
6519 13:15:24.781411 DATLAT Default: 0xe
6520 13:15:24.784834 0, 0xFFFF, sum = 0
6521 13:15:24.787806 1, 0xFFFF, sum = 0
6522 13:15:24.787885 2, 0xFFFF, sum = 0
6523 13:15:24.791365 3, 0xFFFF, sum = 0
6524 13:15:24.791442 4, 0xFFFF, sum = 0
6525 13:15:24.794371 5, 0xFFFF, sum = 0
6526 13:15:24.794448 6, 0xFFFF, sum = 0
6527 13:15:24.797937 7, 0xFFFF, sum = 0
6528 13:15:24.798015 8, 0xFFFF, sum = 0
6529 13:15:24.801077 9, 0xFFFF, sum = 0
6530 13:15:24.801177 10, 0xFFFF, sum = 0
6531 13:15:24.804821 11, 0xFFFF, sum = 0
6532 13:15:24.804898 12, 0xFFFF, sum = 0
6533 13:15:24.808049 13, 0x0, sum = 1
6534 13:15:24.808126 14, 0x0, sum = 2
6535 13:15:24.811028 15, 0x0, sum = 3
6536 13:15:24.811106 16, 0x0, sum = 4
6537 13:15:24.815002 best_step = 14
6538 13:15:24.815079
6539 13:15:24.815138 ==
6540 13:15:24.818032 Dram Type= 6, Freq= 0, CH_0, rank 1
6541 13:15:24.821341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6542 13:15:24.821427 ==
6543 13:15:24.821487 RX Vref Scan: 0
6544 13:15:24.824466
6545 13:15:24.824542 RX Vref 0 -> 0, step: 1
6546 13:15:24.824601
6547 13:15:24.827737 RX Delay -343 -> 252, step: 8
6548 13:15:24.835481 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6549 13:15:24.838836 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6550 13:15:24.842014 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6551 13:15:24.845270 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6552 13:15:24.852091 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6553 13:15:24.855433 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6554 13:15:24.859078 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6555 13:15:24.862465 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6556 13:15:24.869203 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6557 13:15:24.872242 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6558 13:15:24.875306 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6559 13:15:24.878853 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6560 13:15:24.885512 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6561 13:15:24.889328 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6562 13:15:24.892342 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6563 13:15:24.895780 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6564 13:15:24.895859 ==
6565 13:15:24.898780 Dram Type= 6, Freq= 0, CH_0, rank 1
6566 13:15:24.905747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6567 13:15:24.905829 ==
6568 13:15:24.905890 DQS Delay:
6569 13:15:24.909403 DQS0 = 48, DQS1 = 60
6570 13:15:24.909481 DQM Delay:
6571 13:15:24.912721 DQM0 = 13, DQM1 = 12
6572 13:15:24.912798 DQ Delay:
6573 13:15:24.915831 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6574 13:15:24.918901 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6575 13:15:24.922663 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6576 13:15:24.925593 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6577 13:15:24.925675
6578 13:15:24.925733
6579 13:15:24.932226 [DQSOSCAuto] RK1, (LSB)MR18= 0x976a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6580 13:15:24.936067 CH0 RK1: MR19=C0C, MR18=976A
6581 13:15:24.942165 CH0_RK1: MR19=0xC0C, MR18=0x976A, DQSOSC=390, MR23=63, INC=388, DEC=258
6582 13:15:24.945521 [RxdqsGatingPostProcess] freq 400
6583 13:15:24.948587 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6584 13:15:24.952102 best DQS0 dly(2T, 0.5T) = (0, 10)
6585 13:15:24.955554 best DQS1 dly(2T, 0.5T) = (0, 10)
6586 13:15:24.959199 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6587 13:15:24.962290 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6588 13:15:24.965135 best DQS0 dly(2T, 0.5T) = (0, 10)
6589 13:15:24.968535 best DQS1 dly(2T, 0.5T) = (0, 10)
6590 13:15:24.972042 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6591 13:15:24.975735 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6592 13:15:24.978776 Pre-setting of DQS Precalculation
6593 13:15:24.982079 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6594 13:15:24.982162 ==
6595 13:15:24.985501 Dram Type= 6, Freq= 0, CH_1, rank 0
6596 13:15:24.991894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 13:15:24.991979 ==
6598 13:15:24.995857 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6599 13:15:25.002167 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6600 13:15:25.005516 [CA 0] Center 36 (8~64) winsize 57
6601 13:15:25.008999 [CA 1] Center 36 (8~64) winsize 57
6602 13:15:25.011976 [CA 2] Center 36 (8~64) winsize 57
6603 13:15:25.015542 [CA 3] Center 36 (8~64) winsize 57
6604 13:15:25.018949 [CA 4] Center 36 (8~64) winsize 57
6605 13:15:25.022022 [CA 5] Center 36 (8~64) winsize 57
6606 13:15:25.022101
6607 13:15:25.025842 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6608 13:15:25.025920
6609 13:15:25.028661 [CATrainingPosCal] consider 1 rank data
6610 13:15:25.032492 u2DelayCellTimex100 = 270/100 ps
6611 13:15:25.035324 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 13:15:25.039018 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 13:15:25.042814 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 13:15:25.045396 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 13:15:25.048823 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 13:15:25.052341 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 13:15:25.052423
6618 13:15:25.058773 CA PerBit enable=1, Macro0, CA PI delay=36
6619 13:15:25.058856
6620 13:15:25.058915 [CBTSetCACLKResult] CA Dly = 36
6621 13:15:25.062265 CS Dly: 1 (0~32)
6622 13:15:25.062345 ==
6623 13:15:25.065709 Dram Type= 6, Freq= 0, CH_1, rank 1
6624 13:15:25.069095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 13:15:25.069216 ==
6626 13:15:25.075371 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6627 13:15:25.082226 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6628 13:15:25.085303 [CA 0] Center 36 (8~64) winsize 57
6629 13:15:25.088857 [CA 1] Center 36 (8~64) winsize 57
6630 13:15:25.092400 [CA 2] Center 36 (8~64) winsize 57
6631 13:15:25.092487 [CA 3] Center 36 (8~64) winsize 57
6632 13:15:25.095716 [CA 4] Center 36 (8~64) winsize 57
6633 13:15:25.099077 [CA 5] Center 36 (8~64) winsize 57
6634 13:15:25.099156
6635 13:15:25.102459 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6636 13:15:25.102539
6637 13:15:25.108945 [CATrainingPosCal] consider 2 rank data
6638 13:15:25.109052 u2DelayCellTimex100 = 270/100 ps
6639 13:15:25.115991 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 13:15:25.118915 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 13:15:25.122296 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 13:15:25.125877 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 13:15:25.129081 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 13:15:25.132221 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 13:15:25.132299
6646 13:15:25.135421 CA PerBit enable=1, Macro0, CA PI delay=36
6647 13:15:25.135499
6648 13:15:25.138718 [CBTSetCACLKResult] CA Dly = 36
6649 13:15:25.142512 CS Dly: 1 (0~32)
6650 13:15:25.142593
6651 13:15:25.145936 ----->DramcWriteLeveling(PI) begin...
6652 13:15:25.146017 ==
6653 13:15:25.148738 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 13:15:25.152318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 13:15:25.152398 ==
6656 13:15:25.155531 Write leveling (Byte 0): 40 => 8
6657 13:15:25.159216 Write leveling (Byte 1): 40 => 8
6658 13:15:25.162475 DramcWriteLeveling(PI) end<-----
6659 13:15:25.162563
6660 13:15:25.162622 ==
6661 13:15:25.165892 Dram Type= 6, Freq= 0, CH_1, rank 0
6662 13:15:25.169361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 13:15:25.169440 ==
6664 13:15:25.172610 [Gating] SW mode calibration
6665 13:15:25.179326 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6666 13:15:25.182358 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6667 13:15:25.189428 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6668 13:15:25.192386 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6669 13:15:25.195684 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6670 13:15:25.202613 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6671 13:15:25.205582 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 13:15:25.209176 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6673 13:15:25.216397 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6674 13:15:25.219793 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6675 13:15:25.222405 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6676 13:15:25.226163 Total UI for P1: 0, mck2ui 16
6677 13:15:25.229569 best dqsien dly found for B0: ( 0, 14, 24)
6678 13:15:25.232563 Total UI for P1: 0, mck2ui 16
6679 13:15:25.235994 best dqsien dly found for B1: ( 0, 14, 24)
6680 13:15:25.239219 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6681 13:15:25.242343 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6682 13:15:25.242427
6683 13:15:25.249214 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6684 13:15:25.252436 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6685 13:15:25.252518 [Gating] SW calibration Done
6686 13:15:25.255734 ==
6687 13:15:25.259461 Dram Type= 6, Freq= 0, CH_1, rank 0
6688 13:15:25.263237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 13:15:25.263317 ==
6690 13:15:25.263376 RX Vref Scan: 0
6691 13:15:25.263430
6692 13:15:25.266025 RX Vref 0 -> 0, step: 1
6693 13:15:25.266102
6694 13:15:25.269187 RX Delay -410 -> 252, step: 16
6695 13:15:25.272323 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6696 13:15:25.275722 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6697 13:15:25.282747 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6698 13:15:25.285892 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6699 13:15:25.289054 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6700 13:15:25.292465 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6701 13:15:25.299550 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6702 13:15:25.302389 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6703 13:15:25.306198 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6704 13:15:25.309351 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6705 13:15:25.316149 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6706 13:15:25.319486 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6707 13:15:25.322746 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6708 13:15:25.325908 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6709 13:15:25.332859 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6710 13:15:25.336244 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6711 13:15:25.336328 ==
6712 13:15:25.339505 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 13:15:25.342912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 13:15:25.342990 ==
6715 13:15:25.346315 DQS Delay:
6716 13:15:25.346394 DQS0 = 51, DQS1 = 59
6717 13:15:25.346453 DQM Delay:
6718 13:15:25.349537 DQM0 = 19, DQM1 = 16
6719 13:15:25.349615 DQ Delay:
6720 13:15:25.352754 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6721 13:15:25.356291 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6722 13:15:25.359767 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6723 13:15:25.363502 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6724 13:15:25.363603
6725 13:15:25.363692
6726 13:15:25.363791 ==
6727 13:15:25.366045 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 13:15:25.373074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 13:15:25.373173 ==
6730 13:15:25.373234
6731 13:15:25.373289
6732 13:15:25.373341 TX Vref Scan disable
6733 13:15:25.376643 == TX Byte 0 ==
6734 13:15:25.379821 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 13:15:25.383050 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 13:15:25.386613 == TX Byte 1 ==
6737 13:15:25.390026 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 13:15:25.393016 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 13:15:25.393099 ==
6740 13:15:25.396646 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 13:15:25.400347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 13:15:25.403324 ==
6743 13:15:25.403404
6744 13:15:25.403463
6745 13:15:25.403517 TX Vref Scan disable
6746 13:15:25.406485 == TX Byte 0 ==
6747 13:15:25.410145 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6748 13:15:25.413235 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6749 13:15:25.416705 == TX Byte 1 ==
6750 13:15:25.420165 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6751 13:15:25.423039 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6752 13:15:25.423120
6753 13:15:25.423179 [DATLAT]
6754 13:15:25.426904 Freq=400, CH1 RK0
6755 13:15:25.426986
6756 13:15:25.429769 DATLAT Default: 0xf
6757 13:15:25.429847 0, 0xFFFF, sum = 0
6758 13:15:25.433259 1, 0xFFFF, sum = 0
6759 13:15:25.433337 2, 0xFFFF, sum = 0
6760 13:15:25.436742 3, 0xFFFF, sum = 0
6761 13:15:25.436821 4, 0xFFFF, sum = 0
6762 13:15:25.439731 5, 0xFFFF, sum = 0
6763 13:15:25.439809 6, 0xFFFF, sum = 0
6764 13:15:25.443966 7, 0xFFFF, sum = 0
6765 13:15:25.444046 8, 0xFFFF, sum = 0
6766 13:15:25.446658 9, 0xFFFF, sum = 0
6767 13:15:25.446736 10, 0xFFFF, sum = 0
6768 13:15:25.449989 11, 0xFFFF, sum = 0
6769 13:15:25.450069 12, 0xFFFF, sum = 0
6770 13:15:25.453278 13, 0x0, sum = 1
6771 13:15:25.453357 14, 0x0, sum = 2
6772 13:15:25.456221 15, 0x0, sum = 3
6773 13:15:25.456299 16, 0x0, sum = 4
6774 13:15:25.459758 best_step = 14
6775 13:15:25.459862
6776 13:15:25.459946 ==
6777 13:15:25.463224 Dram Type= 6, Freq= 0, CH_1, rank 0
6778 13:15:25.466320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6779 13:15:25.466400 ==
6780 13:15:25.469694 RX Vref Scan: 1
6781 13:15:25.469772
6782 13:15:25.469831 RX Vref 0 -> 0, step: 1
6783 13:15:25.469886
6784 13:15:25.473072 RX Delay -359 -> 252, step: 8
6785 13:15:25.473210
6786 13:15:25.476580 Set Vref, RX VrefLevel [Byte0]: 56
6787 13:15:25.479785 [Byte1]: 50
6788 13:15:25.484150
6789 13:15:25.484237 Final RX Vref Byte 0 = 56 to rank0
6790 13:15:25.487581 Final RX Vref Byte 1 = 50 to rank0
6791 13:15:25.490951 Final RX Vref Byte 0 = 56 to rank1
6792 13:15:25.494426 Final RX Vref Byte 1 = 50 to rank1==
6793 13:15:25.497595 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 13:15:25.504567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 13:15:25.504653 ==
6796 13:15:25.504712 DQS Delay:
6797 13:15:25.504767 DQS0 = 48, DQS1 = 60
6798 13:15:25.507605 DQM Delay:
6799 13:15:25.507694 DQM0 = 12, DQM1 = 12
6800 13:15:25.511171 DQ Delay:
6801 13:15:25.514973 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6802 13:15:25.515059 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6803 13:15:25.517562 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6804 13:15:25.521082 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =16
6805 13:15:25.521197
6806 13:15:25.521255
6807 13:15:25.531163 [DQSOSCAuto] RK0, (LSB)MR18= 0x8e34, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6808 13:15:25.534581 CH1 RK0: MR19=C0C, MR18=8E34
6809 13:15:25.541226 CH1_RK0: MR19=0xC0C, MR18=0x8E34, DQSOSC=392, MR23=63, INC=384, DEC=256
6810 13:15:25.541328 ==
6811 13:15:25.544652 Dram Type= 6, Freq= 0, CH_1, rank 1
6812 13:15:25.547598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 13:15:25.547706 ==
6814 13:15:25.551268 [Gating] SW mode calibration
6815 13:15:25.557499 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6816 13:15:25.561089 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6817 13:15:25.568059 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6818 13:15:25.571155 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6819 13:15:25.574669 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6820 13:15:25.580789 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6821 13:15:25.584437 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 13:15:25.587708 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6823 13:15:25.594764 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6824 13:15:25.597409 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6825 13:15:25.600834 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6826 13:15:25.604306 Total UI for P1: 0, mck2ui 16
6827 13:15:25.607500 best dqsien dly found for B0: ( 0, 14, 24)
6828 13:15:25.611060 Total UI for P1: 0, mck2ui 16
6829 13:15:25.614346 best dqsien dly found for B1: ( 0, 14, 24)
6830 13:15:25.617818 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6831 13:15:25.621067 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6832 13:15:25.621195
6833 13:15:25.627647 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6834 13:15:25.630961 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6835 13:15:25.634334 [Gating] SW calibration Done
6836 13:15:25.634417 ==
6837 13:15:25.637778 Dram Type= 6, Freq= 0, CH_1, rank 1
6838 13:15:25.640608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 13:15:25.640688 ==
6840 13:15:25.640747 RX Vref Scan: 0
6841 13:15:25.640803
6842 13:15:25.644229 RX Vref 0 -> 0, step: 1
6843 13:15:25.644308
6844 13:15:25.647158 RX Delay -410 -> 252, step: 16
6845 13:15:25.650620 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6846 13:15:25.657238 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6847 13:15:25.660435 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6848 13:15:25.664176 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6849 13:15:25.667212 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6850 13:15:25.670935 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6851 13:15:25.677324 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6852 13:15:25.680851 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6853 13:15:25.683828 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6854 13:15:25.687159 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6855 13:15:25.694249 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6856 13:15:25.697333 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6857 13:15:25.700626 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6858 13:15:25.707137 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6859 13:15:25.710825 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6860 13:15:25.713835 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6861 13:15:25.713907 ==
6862 13:15:25.717343 Dram Type= 6, Freq= 0, CH_1, rank 1
6863 13:15:25.720627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 13:15:25.720706 ==
6865 13:15:25.723991 DQS Delay:
6866 13:15:25.724067 DQS0 = 43, DQS1 = 59
6867 13:15:25.727591 DQM Delay:
6868 13:15:25.727664 DQM0 = 10, DQM1 = 17
6869 13:15:25.730868 DQ Delay:
6870 13:15:25.730936 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6871 13:15:25.734001 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6872 13:15:25.737435 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6873 13:15:25.740782 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6874 13:15:25.740853
6875 13:15:25.740906
6876 13:15:25.740964 ==
6877 13:15:25.744190 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 13:15:25.750633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 13:15:25.750718 ==
6880 13:15:25.750774
6881 13:15:25.750832
6882 13:15:25.750911 TX Vref Scan disable
6883 13:15:25.754170 == TX Byte 0 ==
6884 13:15:25.757474 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6885 13:15:25.761324 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6886 13:15:25.764016 == TX Byte 1 ==
6887 13:15:25.767928 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6888 13:15:25.771007 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6889 13:15:25.771103 ==
6890 13:15:25.774114 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 13:15:25.780967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 13:15:25.781089 ==
6893 13:15:25.781219
6894 13:15:25.781303
6895 13:15:25.781382 TX Vref Scan disable
6896 13:15:25.784115 == TX Byte 0 ==
6897 13:15:25.787613 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6898 13:15:25.790998 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6899 13:15:25.794380 == TX Byte 1 ==
6900 13:15:25.797747 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6901 13:15:25.801035 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6902 13:15:25.801124
6903 13:15:25.801200 [DATLAT]
6904 13:15:25.804362 Freq=400, CH1 RK1
6905 13:15:25.804426
6906 13:15:25.808014 DATLAT Default: 0xe
6907 13:15:25.808083 0, 0xFFFF, sum = 0
6908 13:15:25.810964 1, 0xFFFF, sum = 0
6909 13:15:25.811055 2, 0xFFFF, sum = 0
6910 13:15:25.814649 3, 0xFFFF, sum = 0
6911 13:15:25.814740 4, 0xFFFF, sum = 0
6912 13:15:25.817933 5, 0xFFFF, sum = 0
6913 13:15:25.818001 6, 0xFFFF, sum = 0
6914 13:15:25.821418 7, 0xFFFF, sum = 0
6915 13:15:25.821510 8, 0xFFFF, sum = 0
6916 13:15:25.824635 9, 0xFFFF, sum = 0
6917 13:15:25.824707 10, 0xFFFF, sum = 0
6918 13:15:25.828040 11, 0xFFFF, sum = 0
6919 13:15:25.828134 12, 0xFFFF, sum = 0
6920 13:15:25.831167 13, 0x0, sum = 1
6921 13:15:25.831260 14, 0x0, sum = 2
6922 13:15:25.834656 15, 0x0, sum = 3
6923 13:15:25.834736 16, 0x0, sum = 4
6924 13:15:25.837800 best_step = 14
6925 13:15:25.837880
6926 13:15:25.837941 ==
6927 13:15:25.840990 Dram Type= 6, Freq= 0, CH_1, rank 1
6928 13:15:25.844298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6929 13:15:25.844370 ==
6930 13:15:25.844428 RX Vref Scan: 0
6931 13:15:25.844481
6932 13:15:25.848238 RX Vref 0 -> 0, step: 1
6933 13:15:25.848327
6934 13:15:25.851069 RX Delay -359 -> 252, step: 8
6935 13:15:25.858388 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6936 13:15:25.861892 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6937 13:15:25.865214 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6938 13:15:25.868286 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6939 13:15:25.875000 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6940 13:15:25.878429 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6941 13:15:25.882166 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6942 13:15:25.885825 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6943 13:15:25.891919 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6944 13:15:25.895217 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6945 13:15:25.898569 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6946 13:15:25.902157 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6947 13:15:25.908699 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6948 13:15:25.911936 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6949 13:15:25.915531 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6950 13:15:25.918349 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6951 13:15:25.922191 ==
6952 13:15:25.925239 Dram Type= 6, Freq= 0, CH_1, rank 1
6953 13:15:25.928861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6954 13:15:25.928980 ==
6955 13:15:25.929070 DQS Delay:
6956 13:15:25.931938 DQS0 = 52, DQS1 = 60
6957 13:15:25.932031 DQM Delay:
6958 13:15:25.935056 DQM0 = 12, DQM1 = 13
6959 13:15:25.935135 DQ Delay:
6960 13:15:25.938871 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6961 13:15:25.941743 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6962 13:15:25.945080 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6963 13:15:25.948720 DQ12 =16, DQ13 =20, DQ14 =20, DQ15 =24
6964 13:15:25.948802
6965 13:15:25.948863
6966 13:15:25.955101 [DQSOSCAuto] RK1, (LSB)MR18= 0x7c90, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 394 ps
6967 13:15:25.958669 CH1 RK1: MR19=C0C, MR18=7C90
6968 13:15:25.965585 CH1_RK1: MR19=0xC0C, MR18=0x7C90, DQSOSC=391, MR23=63, INC=386, DEC=257
6969 13:15:25.968743 [RxdqsGatingPostProcess] freq 400
6970 13:15:25.972059 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6971 13:15:25.975250 best DQS0 dly(2T, 0.5T) = (0, 10)
6972 13:15:25.978890 best DQS1 dly(2T, 0.5T) = (0, 10)
6973 13:15:25.982071 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6974 13:15:25.985193 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6975 13:15:25.988859 best DQS0 dly(2T, 0.5T) = (0, 10)
6976 13:15:25.991924 best DQS1 dly(2T, 0.5T) = (0, 10)
6977 13:15:25.995215 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6978 13:15:25.999219 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6979 13:15:26.001853 Pre-setting of DQS Precalculation
6980 13:15:26.005337 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6981 13:15:26.015263 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6982 13:15:26.022102 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6983 13:15:26.022229
6984 13:15:26.022319
6985 13:15:26.025537 [Calibration Summary] 800 Mbps
6986 13:15:26.025636 CH 0, Rank 0
6987 13:15:26.028937 SW Impedance : PASS
6988 13:15:26.029030 DUTY Scan : NO K
6989 13:15:26.032063 ZQ Calibration : PASS
6990 13:15:26.035900 Jitter Meter : NO K
6991 13:15:26.035993 CBT Training : PASS
6992 13:15:26.038857 Write leveling : PASS
6993 13:15:26.038948 RX DQS gating : PASS
6994 13:15:26.041979 RX DQ/DQS(RDDQC) : PASS
6995 13:15:26.045517 TX DQ/DQS : PASS
6996 13:15:26.045612 RX DATLAT : PASS
6997 13:15:26.048562 RX DQ/DQS(Engine): PASS
6998 13:15:26.052278 TX OE : NO K
6999 13:15:26.052366 All Pass.
7000 13:15:26.052433
7001 13:15:26.052490 CH 0, Rank 1
7002 13:15:26.056143 SW Impedance : PASS
7003 13:15:26.059203 DUTY Scan : NO K
7004 13:15:26.059307 ZQ Calibration : PASS
7005 13:15:26.062251 Jitter Meter : NO K
7006 13:15:26.066065 CBT Training : PASS
7007 13:15:26.066156 Write leveling : NO K
7008 13:15:26.068920 RX DQS gating : PASS
7009 13:15:26.068987 RX DQ/DQS(RDDQC) : PASS
7010 13:15:26.072168 TX DQ/DQS : PASS
7011 13:15:26.075744 RX DATLAT : PASS
7012 13:15:26.075841 RX DQ/DQS(Engine): PASS
7013 13:15:26.079069 TX OE : NO K
7014 13:15:26.079168 All Pass.
7015 13:15:26.079254
7016 13:15:26.082267 CH 1, Rank 0
7017 13:15:26.082363 SW Impedance : PASS
7018 13:15:26.085564 DUTY Scan : NO K
7019 13:15:26.089576 ZQ Calibration : PASS
7020 13:15:26.089674 Jitter Meter : NO K
7021 13:15:26.092410 CBT Training : PASS
7022 13:15:26.095655 Write leveling : PASS
7023 13:15:26.095726 RX DQS gating : PASS
7024 13:15:26.098932 RX DQ/DQS(RDDQC) : PASS
7025 13:15:26.102516 TX DQ/DQS : PASS
7026 13:15:26.102597 RX DATLAT : PASS
7027 13:15:26.106081 RX DQ/DQS(Engine): PASS
7028 13:15:26.109295 TX OE : NO K
7029 13:15:26.109368 All Pass.
7030 13:15:26.109426
7031 13:15:26.109480 CH 1, Rank 1
7032 13:15:26.112422 SW Impedance : PASS
7033 13:15:26.112511 DUTY Scan : NO K
7034 13:15:26.115492 ZQ Calibration : PASS
7035 13:15:26.119454 Jitter Meter : NO K
7036 13:15:26.119536 CBT Training : PASS
7037 13:15:26.122367 Write leveling : NO K
7038 13:15:26.125568 RX DQS gating : PASS
7039 13:15:26.125676 RX DQ/DQS(RDDQC) : PASS
7040 13:15:26.128994 TX DQ/DQS : PASS
7041 13:15:26.132355 RX DATLAT : PASS
7042 13:15:26.132451 RX DQ/DQS(Engine): PASS
7043 13:15:26.135532 TX OE : NO K
7044 13:15:26.135635 All Pass.
7045 13:15:26.135720
7046 13:15:26.139273 DramC Write-DBI off
7047 13:15:26.142530 PER_BANK_REFRESH: Hybrid Mode
7048 13:15:26.142639 TX_TRACKING: ON
7049 13:15:26.152839 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7050 13:15:26.155680 [FAST_K] Save calibration result to emmc
7051 13:15:26.159464 dramc_set_vcore_voltage set vcore to 725000
7052 13:15:26.162582 Read voltage for 1600, 0
7053 13:15:26.162655 Vio18 = 0
7054 13:15:26.162712 Vcore = 725000
7055 13:15:26.165639 Vdram = 0
7056 13:15:26.165727 Vddq = 0
7057 13:15:26.165807 Vmddr = 0
7058 13:15:26.172935 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7059 13:15:26.175847 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7060 13:15:26.179021 MEM_TYPE=3, freq_sel=13
7061 13:15:26.182527 sv_algorithm_assistance_LP4_3733
7062 13:15:26.185474 ============ PULL DRAM RESETB DOWN ============
7063 13:15:26.189088 ========== PULL DRAM RESETB DOWN end =========
7064 13:15:26.196052 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7065 13:15:26.199472 ===================================
7066 13:15:26.199543 LPDDR4 DRAM CONFIGURATION
7067 13:15:26.202261 ===================================
7068 13:15:26.205896 EX_ROW_EN[0] = 0x0
7069 13:15:26.208990 EX_ROW_EN[1] = 0x0
7070 13:15:26.209111 LP4Y_EN = 0x0
7071 13:15:26.212445 WORK_FSP = 0x1
7072 13:15:26.212542 WL = 0x5
7073 13:15:26.216140 RL = 0x5
7074 13:15:26.216236 BL = 0x2
7075 13:15:26.219259 RPST = 0x0
7076 13:15:26.219350 RD_PRE = 0x0
7077 13:15:26.222625 WR_PRE = 0x1
7078 13:15:26.222716 WR_PST = 0x1
7079 13:15:26.226287 DBI_WR = 0x0
7080 13:15:26.226369 DBI_RD = 0x0
7081 13:15:26.229210 OTF = 0x1
7082 13:15:26.232632 ===================================
7083 13:15:26.235979 ===================================
7084 13:15:26.236083 ANA top config
7085 13:15:26.239053 ===================================
7086 13:15:26.242349 DLL_ASYNC_EN = 0
7087 13:15:26.246338 ALL_SLAVE_EN = 0
7088 13:15:26.246429 NEW_RANK_MODE = 1
7089 13:15:26.249189 DLL_IDLE_MODE = 1
7090 13:15:26.253030 LP45_APHY_COMB_EN = 1
7091 13:15:26.255943 TX_ODT_DIS = 0
7092 13:15:26.259428 NEW_8X_MODE = 1
7093 13:15:26.262368 ===================================
7094 13:15:26.265652 ===================================
7095 13:15:26.265746 data_rate = 3200
7096 13:15:26.269333 CKR = 1
7097 13:15:26.272844 DQ_P2S_RATIO = 8
7098 13:15:26.275984 ===================================
7099 13:15:26.279432 CA_P2S_RATIO = 8
7100 13:15:26.282825 DQ_CA_OPEN = 0
7101 13:15:26.286135 DQ_SEMI_OPEN = 0
7102 13:15:26.286212 CA_SEMI_OPEN = 0
7103 13:15:26.289346 CA_FULL_RATE = 0
7104 13:15:26.292736 DQ_CKDIV4_EN = 0
7105 13:15:26.295767 CA_CKDIV4_EN = 0
7106 13:15:26.299372 CA_PREDIV_EN = 0
7107 13:15:26.299471 PH8_DLY = 12
7108 13:15:26.302893 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7109 13:15:26.306117 DQ_AAMCK_DIV = 4
7110 13:15:26.309706 CA_AAMCK_DIV = 4
7111 13:15:26.312787 CA_ADMCK_DIV = 4
7112 13:15:26.316487 DQ_TRACK_CA_EN = 0
7113 13:15:26.319173 CA_PICK = 1600
7114 13:15:26.319255 CA_MCKIO = 1600
7115 13:15:26.322447 MCKIO_SEMI = 0
7116 13:15:26.326042 PLL_FREQ = 3068
7117 13:15:26.329361 DQ_UI_PI_RATIO = 32
7118 13:15:26.332602 CA_UI_PI_RATIO = 0
7119 13:15:26.336014 ===================================
7120 13:15:26.339767 ===================================
7121 13:15:26.342836 memory_type:LPDDR4
7122 13:15:26.342923 GP_NUM : 10
7123 13:15:26.346347 SRAM_EN : 1
7124 13:15:26.346429 MD32_EN : 0
7125 13:15:26.349479 ===================================
7126 13:15:26.353090 [ANA_INIT] >>>>>>>>>>>>>>
7127 13:15:26.356518 <<<<<< [CONFIGURE PHASE]: ANA_TX
7128 13:15:26.359851 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7129 13:15:26.362962 ===================================
7130 13:15:26.366149 data_rate = 3200,PCW = 0X7600
7131 13:15:26.369403 ===================================
7132 13:15:26.372633 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7133 13:15:26.375839 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7134 13:15:26.382430 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7135 13:15:26.386031 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7136 13:15:26.389587 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7137 13:15:26.392680 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7138 13:15:26.395830 [ANA_INIT] flow start
7139 13:15:26.399432 [ANA_INIT] PLL >>>>>>>>
7140 13:15:26.399522 [ANA_INIT] PLL <<<<<<<<
7141 13:15:26.402865 [ANA_INIT] MIDPI >>>>>>>>
7142 13:15:26.406070 [ANA_INIT] MIDPI <<<<<<<<
7143 13:15:26.409500 [ANA_INIT] DLL >>>>>>>>
7144 13:15:26.409571 [ANA_INIT] DLL <<<<<<<<
7145 13:15:26.412832 [ANA_INIT] flow end
7146 13:15:26.416279 ============ LP4 DIFF to SE enter ============
7147 13:15:26.419305 ============ LP4 DIFF to SE exit ============
7148 13:15:26.422548 [ANA_INIT] <<<<<<<<<<<<<
7149 13:15:26.426108 [Flow] Enable top DCM control >>>>>
7150 13:15:26.429244 [Flow] Enable top DCM control <<<<<
7151 13:15:26.433220 Enable DLL master slave shuffle
7152 13:15:26.439572 ==============================================================
7153 13:15:26.439666 Gating Mode config
7154 13:15:26.446080 ==============================================================
7155 13:15:26.446163 Config description:
7156 13:15:26.456326 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7157 13:15:26.462925 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7158 13:15:26.469549 SELPH_MODE 0: By rank 1: By Phase
7159 13:15:26.473780 ==============================================================
7160 13:15:26.476095 GAT_TRACK_EN = 1
7161 13:15:26.480339 RX_GATING_MODE = 2
7162 13:15:26.483311 RX_GATING_TRACK_MODE = 2
7163 13:15:26.486876 SELPH_MODE = 1
7164 13:15:26.489699 PICG_EARLY_EN = 1
7165 13:15:26.493345 VALID_LAT_VALUE = 1
7166 13:15:26.496602 ==============================================================
7167 13:15:26.500000 Enter into Gating configuration >>>>
7168 13:15:26.503361 Exit from Gating configuration <<<<
7169 13:15:26.506420 Enter into DVFS_PRE_config >>>>>
7170 13:15:26.516866 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7171 13:15:26.519931 Exit from DVFS_PRE_config <<<<<
7172 13:15:26.523245 Enter into PICG configuration >>>>
7173 13:15:26.526556 Exit from PICG configuration <<<<
7174 13:15:26.529467 [RX_INPUT] configuration >>>>>
7175 13:15:26.532982 [RX_INPUT] configuration <<<<<
7176 13:15:26.540008 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7177 13:15:26.543138 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7178 13:15:26.550106 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7179 13:15:26.556286 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7180 13:15:26.563027 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7181 13:15:26.570157 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7182 13:15:26.573211 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7183 13:15:26.576376 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7184 13:15:26.579770 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7185 13:15:26.583654 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7186 13:15:26.589626 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7187 13:15:26.593281 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7188 13:15:26.596498 ===================================
7189 13:15:26.600274 LPDDR4 DRAM CONFIGURATION
7190 13:15:26.602910 ===================================
7191 13:15:26.602981 EX_ROW_EN[0] = 0x0
7192 13:15:26.606503 EX_ROW_EN[1] = 0x0
7193 13:15:26.606575 LP4Y_EN = 0x0
7194 13:15:26.609799 WORK_FSP = 0x1
7195 13:15:26.609863 WL = 0x5
7196 13:15:26.613673 RL = 0x5
7197 13:15:26.613738 BL = 0x2
7198 13:15:26.616346 RPST = 0x0
7199 13:15:26.616433 RD_PRE = 0x0
7200 13:15:26.619780 WR_PRE = 0x1
7201 13:15:26.623144 WR_PST = 0x1
7202 13:15:26.623210 DBI_WR = 0x0
7203 13:15:26.626333 DBI_RD = 0x0
7204 13:15:26.626421 OTF = 0x1
7205 13:15:26.629988 ===================================
7206 13:15:26.633030 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7207 13:15:26.636684 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7208 13:15:26.642987 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7209 13:15:26.646580 ===================================
7210 13:15:26.649813 LPDDR4 DRAM CONFIGURATION
7211 13:15:26.652941 ===================================
7212 13:15:26.653023 EX_ROW_EN[0] = 0x10
7213 13:15:26.656474 EX_ROW_EN[1] = 0x0
7214 13:15:26.656565 LP4Y_EN = 0x0
7215 13:15:26.659849 WORK_FSP = 0x1
7216 13:15:26.659931 WL = 0x5
7217 13:15:26.663628 RL = 0x5
7218 13:15:26.663711 BL = 0x2
7219 13:15:26.666730 RPST = 0x0
7220 13:15:26.666810 RD_PRE = 0x0
7221 13:15:26.669854 WR_PRE = 0x1
7222 13:15:26.669933 WR_PST = 0x1
7223 13:15:26.673153 DBI_WR = 0x0
7224 13:15:26.673275 DBI_RD = 0x0
7225 13:15:26.677231 OTF = 0x1
7226 13:15:26.680175 ===================================
7227 13:15:26.686723 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7228 13:15:26.686839 ==
7229 13:15:26.689775 Dram Type= 6, Freq= 0, CH_0, rank 0
7230 13:15:26.693721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7231 13:15:26.693807 ==
7232 13:15:26.696843 [Duty_Offset_Calibration]
7233 13:15:26.696945 B0:2 B1:-1 CA:1
7234 13:15:26.697029
7235 13:15:26.700043 [DutyScan_Calibration_Flow] k_type=0
7236 13:15:26.710103
7237 13:15:26.710216 ==CLK 0==
7238 13:15:26.713300 Final CLK duty delay cell = -4
7239 13:15:26.716739 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7240 13:15:26.720176 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7241 13:15:26.723178 [-4] AVG Duty = 4922%(X100)
7242 13:15:26.723264
7243 13:15:26.726763 CH0 CLK Duty spec in!! Max-Min= 156%
7244 13:15:26.729996 [DutyScan_Calibration_Flow] ====Done====
7245 13:15:26.730081
7246 13:15:26.733426 [DutyScan_Calibration_Flow] k_type=1
7247 13:15:26.749420
7248 13:15:26.749549 ==DQS 0 ==
7249 13:15:26.752756 Final DQS duty delay cell = 0
7250 13:15:26.756864 [0] MAX Duty = 5125%(X100), DQS PI = 22
7251 13:15:26.759439 [0] MIN Duty = 5000%(X100), DQS PI = 14
7252 13:15:26.759520 [0] AVG Duty = 5062%(X100)
7253 13:15:26.763098
7254 13:15:26.763180 ==DQS 1 ==
7255 13:15:26.766264 Final DQS duty delay cell = -4
7256 13:15:26.769374 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7257 13:15:26.772924 [-4] MIN Duty = 5031%(X100), DQS PI = 6
7258 13:15:26.776232 [-4] AVG Duty = 5062%(X100)
7259 13:15:26.776313
7260 13:15:26.779712 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7261 13:15:26.779798
7262 13:15:26.782975 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7263 13:15:26.786245 [DutyScan_Calibration_Flow] ====Done====
7264 13:15:26.786332
7265 13:15:26.789735 [DutyScan_Calibration_Flow] k_type=3
7266 13:15:26.806635
7267 13:15:26.806763 ==DQM 0 ==
7268 13:15:26.810161 Final DQM duty delay cell = 0
7269 13:15:26.813477 [0] MAX Duty = 5000%(X100), DQS PI = 18
7270 13:15:26.816895 [0] MIN Duty = 4875%(X100), DQS PI = 4
7271 13:15:26.816976 [0] AVG Duty = 4937%(X100)
7272 13:15:26.820579
7273 13:15:26.820656 ==DQM 1 ==
7274 13:15:26.823493 Final DQM duty delay cell = 0
7275 13:15:26.826970 [0] MAX Duty = 5187%(X100), DQS PI = 58
7276 13:15:26.830537 [0] MIN Duty = 4969%(X100), DQS PI = 18
7277 13:15:26.830622 [0] AVG Duty = 5078%(X100)
7278 13:15:26.833534
7279 13:15:26.836799 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7280 13:15:26.836879
7281 13:15:26.839916 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7282 13:15:26.843902 [DutyScan_Calibration_Flow] ====Done====
7283 13:15:26.843985
7284 13:15:26.846588 [DutyScan_Calibration_Flow] k_type=2
7285 13:15:26.864100
7286 13:15:26.864229 ==DQ 0 ==
7287 13:15:26.867097 Final DQ duty delay cell = 0
7288 13:15:26.870781 [0] MAX Duty = 5187%(X100), DQS PI = 56
7289 13:15:26.873851 [0] MIN Duty = 5031%(X100), DQS PI = 10
7290 13:15:26.873934 [0] AVG Duty = 5109%(X100)
7291 13:15:26.877573
7292 13:15:26.877654 ==DQ 1 ==
7293 13:15:26.881729 Final DQ duty delay cell = 0
7294 13:15:26.883912 [0] MAX Duty = 5000%(X100), DQS PI = 14
7295 13:15:26.887805 [0] MIN Duty = 4907%(X100), DQS PI = 18
7296 13:15:26.887891 [0] AVG Duty = 4953%(X100)
7297 13:15:26.887956
7298 13:15:26.890407 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7299 13:15:26.894157
7300 13:15:26.897695 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7301 13:15:26.900740 [DutyScan_Calibration_Flow] ====Done====
7302 13:15:26.900828 ==
7303 13:15:26.903700 Dram Type= 6, Freq= 0, CH_1, rank 0
7304 13:15:26.907223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7305 13:15:26.907336 ==
7306 13:15:26.910463 [Duty_Offset_Calibration]
7307 13:15:26.910562 B0:1 B1:1 CA:2
7308 13:15:26.910646
7309 13:15:26.913897 [DutyScan_Calibration_Flow] k_type=0
7310 13:15:26.924319
7311 13:15:26.924425 ==CLK 0==
7312 13:15:26.927466 Final CLK duty delay cell = 0
7313 13:15:26.931015 [0] MAX Duty = 5187%(X100), DQS PI = 24
7314 13:15:26.933928 [0] MIN Duty = 4938%(X100), DQS PI = 50
7315 13:15:26.934012 [0] AVG Duty = 5062%(X100)
7316 13:15:26.937739
7317 13:15:26.937848 CH1 CLK Duty spec in!! Max-Min= 249%
7318 13:15:26.944275 [DutyScan_Calibration_Flow] ====Done====
7319 13:15:26.944368
7320 13:15:26.947666 [DutyScan_Calibration_Flow] k_type=1
7321 13:15:26.963575
7322 13:15:26.963720 ==DQS 0 ==
7323 13:15:26.967424 Final DQS duty delay cell = 0
7324 13:15:26.970438 [0] MAX Duty = 5031%(X100), DQS PI = 20
7325 13:15:26.973904 [0] MIN Duty = 4813%(X100), DQS PI = 52
7326 13:15:26.977125 [0] AVG Duty = 4922%(X100)
7327 13:15:26.977206
7328 13:15:26.977266 ==DQS 1 ==
7329 13:15:26.980696 Final DQS duty delay cell = 0
7330 13:15:26.984103 [0] MAX Duty = 5031%(X100), DQS PI = 34
7331 13:15:26.987252 [0] MIN Duty = 4938%(X100), DQS PI = 14
7332 13:15:26.990456 [0] AVG Duty = 4984%(X100)
7333 13:15:26.990531
7334 13:15:26.993789 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7335 13:15:26.993859
7336 13:15:26.997283 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7337 13:15:27.000482 [DutyScan_Calibration_Flow] ====Done====
7338 13:15:27.000550
7339 13:15:27.003658 [DutyScan_Calibration_Flow] k_type=3
7340 13:15:27.020701
7341 13:15:27.020829 ==DQM 0 ==
7342 13:15:27.023722 Final DQM duty delay cell = 0
7343 13:15:27.027509 [0] MAX Duty = 5124%(X100), DQS PI = 18
7344 13:15:27.030822 [0] MIN Duty = 4844%(X100), DQS PI = 50
7345 13:15:27.033896 [0] AVG Duty = 4984%(X100)
7346 13:15:27.033976
7347 13:15:27.034037 ==DQM 1 ==
7348 13:15:27.037467 Final DQM duty delay cell = 0
7349 13:15:27.040948 [0] MAX Duty = 5156%(X100), DQS PI = 12
7350 13:15:27.043865 [0] MIN Duty = 4907%(X100), DQS PI = 20
7351 13:15:27.043986 [0] AVG Duty = 5031%(X100)
7352 13:15:27.047599
7353 13:15:27.050623 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7354 13:15:27.050722
7355 13:15:27.054160 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7356 13:15:27.057348 [DutyScan_Calibration_Flow] ====Done====
7357 13:15:27.057447
7358 13:15:27.060943 [DutyScan_Calibration_Flow] k_type=2
7359 13:15:27.077461
7360 13:15:27.077578 ==DQ 0 ==
7361 13:15:27.080740 Final DQ duty delay cell = 0
7362 13:15:27.084304 [0] MAX Duty = 5125%(X100), DQS PI = 20
7363 13:15:27.087319 [0] MIN Duty = 4875%(X100), DQS PI = 52
7364 13:15:27.087400 [0] AVG Duty = 5000%(X100)
7365 13:15:27.090898
7366 13:15:27.090966 ==DQ 1 ==
7367 13:15:27.094034 Final DQ duty delay cell = 0
7368 13:15:27.097282 [0] MAX Duty = 5093%(X100), DQS PI = 6
7369 13:15:27.101237 [0] MIN Duty = 5031%(X100), DQS PI = 0
7370 13:15:27.101334 [0] AVG Duty = 5062%(X100)
7371 13:15:27.101421
7372 13:15:27.104628 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7373 13:15:27.104721
7374 13:15:27.107232 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7375 13:15:27.114331 [DutyScan_Calibration_Flow] ====Done====
7376 13:15:27.118416 nWR fixed to 30
7377 13:15:27.118494 [ModeRegInit_LP4] CH0 RK0
7378 13:15:27.120764 [ModeRegInit_LP4] CH0 RK1
7379 13:15:27.124113 [ModeRegInit_LP4] CH1 RK0
7380 13:15:27.124182 [ModeRegInit_LP4] CH1 RK1
7381 13:15:27.127549 match AC timing 5
7382 13:15:27.130630 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7383 13:15:27.133893 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7384 13:15:27.141088 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7385 13:15:27.144364 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7386 13:15:27.150924 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7387 13:15:27.151009 [MiockJmeterHQA]
7388 13:15:27.151067
7389 13:15:27.154128 [DramcMiockJmeter] u1RxGatingPI = 0
7390 13:15:27.157758 0 : 4258, 4029
7391 13:15:27.157823 4 : 4252, 4027
7392 13:15:27.157877 8 : 4253, 4026
7393 13:15:27.160958 12 : 4255, 4029
7394 13:15:27.161022 16 : 4363, 4137
7395 13:15:27.164281 20 : 4252, 4027
7396 13:15:27.164350 24 : 4250, 4027
7397 13:15:27.167384 28 : 4252, 4027
7398 13:15:27.167472 32 : 4255, 4029
7399 13:15:27.167528 36 : 4252, 4027
7400 13:15:27.170812 40 : 4252, 4026
7401 13:15:27.170884 44 : 4366, 4140
7402 13:15:27.174271 48 : 4253, 4027
7403 13:15:27.174335 52 : 4255, 4029
7404 13:15:27.177674 56 : 4253, 4027
7405 13:15:27.177743 60 : 4361, 4137
7406 13:15:27.180687 64 : 4250, 4027
7407 13:15:27.180760 68 : 4361, 4137
7408 13:15:27.180816 72 : 4250, 4027
7409 13:15:27.184374 76 : 4250, 4027
7410 13:15:27.184456 80 : 4250, 4027
7411 13:15:27.187634 84 : 4252, 4029
7412 13:15:27.187715 88 : 4360, 4138
7413 13:15:27.190929 92 : 4250, 4027
7414 13:15:27.191010 96 : 4361, 3472
7415 13:15:27.191071 100 : 4250, 0
7416 13:15:27.194219 104 : 4250, 0
7417 13:15:27.194298 108 : 4250, 0
7418 13:15:27.197437 112 : 4250, 0
7419 13:15:27.197518 116 : 4250, 0
7420 13:15:27.197578 120 : 4252, 0
7421 13:15:27.200817 124 : 4361, 0
7422 13:15:27.200904 128 : 4250, 0
7423 13:15:27.203899 132 : 4250, 0
7424 13:15:27.204004 136 : 4360, 0
7425 13:15:27.204090 140 : 4361, 0
7426 13:15:27.207825 144 : 4363, 0
7427 13:15:27.207906 148 : 4250, 0
7428 13:15:27.207967 152 : 4360, 0
7429 13:15:27.210847 156 : 4361, 0
7430 13:15:27.210914 160 : 4250, 0
7431 13:15:27.214214 164 : 4250, 0
7432 13:15:27.214277 168 : 4250, 0
7433 13:15:27.214330 172 : 4250, 0
7434 13:15:27.217418 176 : 4249, 0
7435 13:15:27.217483 180 : 4250, 0
7436 13:15:27.221051 184 : 4253, 0
7437 13:15:27.221190 188 : 4360, 0
7438 13:15:27.221245 192 : 4361, 0
7439 13:15:27.224380 196 : 4363, 0
7440 13:15:27.224443 200 : 4250, 0
7441 13:15:27.224494 204 : 4250, 0
7442 13:15:27.227307 208 : 4250, 0
7443 13:15:27.227370 212 : 4252, 33
7444 13:15:27.230744 216 : 4360, 3747
7445 13:15:27.230815 220 : 4360, 4138
7446 13:15:27.234305 224 : 4247, 4024
7447 13:15:27.234368 228 : 4363, 4139
7448 13:15:27.237871 232 : 4360, 4138
7449 13:15:27.237938 236 : 4250, 4027
7450 13:15:27.240915 240 : 4250, 4027
7451 13:15:27.241006 244 : 4252, 4029
7452 13:15:27.241086 248 : 4250, 4027
7453 13:15:27.244210 252 : 4250, 4027
7454 13:15:27.244273 256 : 4249, 4027
7455 13:15:27.247329 260 : 4250, 4027
7456 13:15:27.247420 264 : 4250, 4027
7457 13:15:27.251029 268 : 4360, 4138
7458 13:15:27.251095 272 : 4360, 4138
7459 13:15:27.254549 276 : 4250, 4027
7460 13:15:27.254611 280 : 4363, 4140
7461 13:15:27.257846 284 : 4360, 4138
7462 13:15:27.257907 288 : 4250, 4027
7463 13:15:27.260744 292 : 4249, 4027
7464 13:15:27.260806 296 : 4252, 4029
7465 13:15:27.264595 300 : 4250, 4027
7466 13:15:27.264661 304 : 4250, 4027
7467 13:15:27.264712 308 : 4250, 4027
7468 13:15:27.267528 312 : 4252, 4029
7469 13:15:27.267615 316 : 4250, 4027
7470 13:15:27.270646 320 : 4360, 4138
7471 13:15:27.270722 324 : 4361, 4138
7472 13:15:27.274174 328 : 4250, 4026
7473 13:15:27.274236 332 : 4360, 3403
7474 13:15:27.277547 336 : 4361, 66
7475 13:15:27.277636
7476 13:15:27.277713 MIOCK jitter meter ch=0
7477 13:15:27.277790
7478 13:15:27.280984 1T = (336-100) = 236 dly cells
7479 13:15:27.287850 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7480 13:15:27.287950 ==
7481 13:15:27.291006 Dram Type= 6, Freq= 0, CH_0, rank 0
7482 13:15:27.294507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7483 13:15:27.294593 ==
7484 13:15:27.300909 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7485 13:15:27.305054 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7486 13:15:27.307737 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7487 13:15:27.314190 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7488 13:15:27.323751 [CA 0] Center 44 (14~75) winsize 62
7489 13:15:27.327586 [CA 1] Center 44 (14~75) winsize 62
7490 13:15:27.330480 [CA 2] Center 40 (11~69) winsize 59
7491 13:15:27.333909 [CA 3] Center 39 (10~69) winsize 60
7492 13:15:27.337389 [CA 4] Center 38 (8~68) winsize 61
7493 13:15:27.341093 [CA 5] Center 37 (7~67) winsize 61
7494 13:15:27.341206
7495 13:15:27.344195 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7496 13:15:27.344261
7497 13:15:27.347623 [CATrainingPosCal] consider 1 rank data
7498 13:15:27.350728 u2DelayCellTimex100 = 275/100 ps
7499 13:15:27.354064 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7500 13:15:27.360528 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7501 13:15:27.364269 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7502 13:15:27.367219 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7503 13:15:27.370646 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7504 13:15:27.373897 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7505 13:15:27.373967
7506 13:15:27.377564 CA PerBit enable=1, Macro0, CA PI delay=37
7507 13:15:27.377654
7508 13:15:27.381182 [CBTSetCACLKResult] CA Dly = 37
7509 13:15:27.384597 CS Dly: 11 (0~42)
7510 13:15:27.387527 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7511 13:15:27.391117 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7512 13:15:27.391188 ==
7513 13:15:27.394269 Dram Type= 6, Freq= 0, CH_0, rank 1
7514 13:15:27.397851 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7515 13:15:27.397917 ==
7516 13:15:27.404438 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7517 13:15:27.407349 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7518 13:15:27.414312 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7519 13:15:27.417450 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7520 13:15:27.427739 [CA 0] Center 43 (13~74) winsize 62
7521 13:15:27.431327 [CA 1] Center 43 (13~74) winsize 62
7522 13:15:27.434751 [CA 2] Center 39 (10~69) winsize 60
7523 13:15:27.437803 [CA 3] Center 38 (9~68) winsize 60
7524 13:15:27.441373 [CA 4] Center 37 (7~67) winsize 61
7525 13:15:27.444862 [CA 5] Center 36 (6~67) winsize 62
7526 13:15:27.444943
7527 13:15:27.447728 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7528 13:15:27.447806
7529 13:15:27.451791 [CATrainingPosCal] consider 2 rank data
7530 13:15:27.454975 u2DelayCellTimex100 = 275/100 ps
7531 13:15:27.457940 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7532 13:15:27.464799 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7533 13:15:27.467785 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7534 13:15:27.471538 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7535 13:15:27.475095 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7536 13:15:27.477737 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7537 13:15:27.477819
7538 13:15:27.481370 CA PerBit enable=1, Macro0, CA PI delay=37
7539 13:15:27.481449
7540 13:15:27.484979 [CBTSetCACLKResult] CA Dly = 37
7541 13:15:27.488388 CS Dly: 12 (0~44)
7542 13:15:27.491330 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7543 13:15:27.495047 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7544 13:15:27.495128
7545 13:15:27.498178 ----->DramcWriteLeveling(PI) begin...
7546 13:15:27.498256 ==
7547 13:15:27.501522 Dram Type= 6, Freq= 0, CH_0, rank 0
7548 13:15:27.504710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7549 13:15:27.507785 ==
7550 13:15:27.507864 Write leveling (Byte 0): 34 => 34
7551 13:15:27.511329 Write leveling (Byte 1): 26 => 26
7552 13:15:27.514285 DramcWriteLeveling(PI) end<-----
7553 13:15:27.514379
7554 13:15:27.514438 ==
7555 13:15:27.517500 Dram Type= 6, Freq= 0, CH_0, rank 0
7556 13:15:27.524372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7557 13:15:27.524464 ==
7558 13:15:27.528270 [Gating] SW mode calibration
7559 13:15:27.534666 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7560 13:15:27.538099 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7561 13:15:27.544489 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7562 13:15:27.547854 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7563 13:15:27.551201 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7564 13:15:27.554277 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 13:15:27.561145 1 4 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 13:15:27.564505 1 4 20 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
7567 13:15:27.568042 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7568 13:15:27.574292 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7569 13:15:27.577449 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7570 13:15:27.581130 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7571 13:15:27.587778 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7572 13:15:27.590796 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7573 13:15:27.594270 1 5 16 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
7574 13:15:27.601127 1 5 20 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
7575 13:15:27.604264 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
7576 13:15:27.607994 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 13:15:27.614378 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 13:15:27.617561 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 13:15:27.621211 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 13:15:27.627664 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 13:15:27.631008 1 6 16 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
7582 13:15:27.634449 1 6 20 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7583 13:15:27.640897 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7584 13:15:27.644472 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 13:15:27.647846 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 13:15:27.654852 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 13:15:27.657801 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 13:15:27.661349 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 13:15:27.665078 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7590 13:15:27.671326 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7591 13:15:27.674345 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7592 13:15:27.677953 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 13:15:27.684390 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 13:15:27.687918 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 13:15:27.691026 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 13:15:27.697548 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 13:15:27.701062 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 13:15:27.704772 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 13:15:27.711165 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 13:15:27.714119 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 13:15:27.717717 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 13:15:27.724425 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 13:15:27.727785 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 13:15:27.730866 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 13:15:27.737788 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7606 13:15:27.740741 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7607 13:15:27.744192 Total UI for P1: 0, mck2ui 16
7608 13:15:27.747883 best dqsien dly found for B0: ( 1, 9, 16)
7609 13:15:27.750910 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 13:15:27.754116 Total UI for P1: 0, mck2ui 16
7611 13:15:27.757432 best dqsien dly found for B1: ( 1, 9, 18)
7612 13:15:27.760682 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7613 13:15:27.764756 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7614 13:15:27.764846
7615 13:15:27.767297 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7616 13:15:27.774289 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7617 13:15:27.774408 [Gating] SW calibration Done
7618 13:15:27.774494 ==
7619 13:15:27.777727 Dram Type= 6, Freq= 0, CH_0, rank 0
7620 13:15:27.784632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7621 13:15:27.784740 ==
7622 13:15:27.784801 RX Vref Scan: 0
7623 13:15:27.784855
7624 13:15:27.787894 RX Vref 0 -> 0, step: 1
7625 13:15:27.787972
7626 13:15:27.790947 RX Delay 0 -> 252, step: 8
7627 13:15:27.794599 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7628 13:15:27.797741 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7629 13:15:27.801370 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7630 13:15:27.804418 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7631 13:15:27.810892 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7632 13:15:27.814400 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7633 13:15:27.818793 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7634 13:15:27.821068 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7635 13:15:27.824311 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7636 13:15:27.830736 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7637 13:15:27.834123 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7638 13:15:27.837665 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7639 13:15:27.840761 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7640 13:15:27.844446 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7641 13:15:27.850951 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7642 13:15:27.854525 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
7643 13:15:27.854653 ==
7644 13:15:27.857345 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 13:15:27.860636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 13:15:27.860707 ==
7647 13:15:27.864333 DQS Delay:
7648 13:15:27.864414 DQS0 = 0, DQS1 = 0
7649 13:15:27.864472 DQM Delay:
7650 13:15:27.868624 DQM0 = 132, DQM1 = 124
7651 13:15:27.868728 DQ Delay:
7652 13:15:27.871170 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7653 13:15:27.874197 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7654 13:15:27.877546 DQ8 =111, DQ9 =115, DQ10 =119, DQ11 =119
7655 13:15:27.884507 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7656 13:15:27.884610
7657 13:15:27.884670
7658 13:15:27.884722 ==
7659 13:15:27.887475 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 13:15:27.890926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 13:15:27.891008 ==
7662 13:15:27.891067
7663 13:15:27.891120
7664 13:15:27.894172 TX Vref Scan disable
7665 13:15:27.894247 == TX Byte 0 ==
7666 13:15:27.901033 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7667 13:15:27.904344 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7668 13:15:27.904424 == TX Byte 1 ==
7669 13:15:27.911125 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7670 13:15:27.915014 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7671 13:15:27.915097 ==
7672 13:15:27.917873 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 13:15:27.920832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 13:15:27.920909 ==
7675 13:15:27.937101
7676 13:15:27.940584 TX Vref early break, caculate TX vref
7677 13:15:27.943746 TX Vref=16, minBit 8, minWin=20, winSum=357
7678 13:15:27.947700 TX Vref=18, minBit 1, minWin=22, winSum=368
7679 13:15:27.950618 TX Vref=20, minBit 4, minWin=22, winSum=377
7680 13:15:27.953929 TX Vref=22, minBit 8, minWin=23, winSum=393
7681 13:15:27.957251 TX Vref=24, minBit 1, minWin=24, winSum=401
7682 13:15:27.963699 TX Vref=26, minBit 4, minWin=25, winSum=415
7683 13:15:27.967323 TX Vref=28, minBit 4, minWin=25, winSum=423
7684 13:15:27.970750 TX Vref=30, minBit 4, minWin=24, winSum=411
7685 13:15:27.973892 TX Vref=32, minBit 9, minWin=24, winSum=411
7686 13:15:27.977558 TX Vref=34, minBit 8, minWin=24, winSum=404
7687 13:15:27.980503 TX Vref=36, minBit 9, minWin=22, winSum=390
7688 13:15:27.987539 [TxChooseVref] Worse bit 4, Min win 25, Win sum 423, Final Vref 28
7689 13:15:27.987640
7690 13:15:27.991022 Final TX Range 0 Vref 28
7691 13:15:27.991107
7692 13:15:27.991164 ==
7693 13:15:27.994072 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 13:15:27.997083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 13:15:27.997187 ==
7696 13:15:27.997246
7697 13:15:27.997298
7698 13:15:28.000259 TX Vref Scan disable
7699 13:15:28.007173 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7700 13:15:28.007268 == TX Byte 0 ==
7701 13:15:28.010217 u2DelayCellOfst[0]=17 cells (5 PI)
7702 13:15:28.013617 u2DelayCellOfst[1]=21 cells (6 PI)
7703 13:15:28.016957 u2DelayCellOfst[2]=10 cells (3 PI)
7704 13:15:28.020731 u2DelayCellOfst[3]=14 cells (4 PI)
7705 13:15:28.024339 u2DelayCellOfst[4]=10 cells (3 PI)
7706 13:15:28.027254 u2DelayCellOfst[5]=0 cells (0 PI)
7707 13:15:28.030335 u2DelayCellOfst[6]=21 cells (6 PI)
7708 13:15:28.034038 u2DelayCellOfst[7]=17 cells (5 PI)
7709 13:15:28.037232 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7710 13:15:28.040667 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7711 13:15:28.044290 == TX Byte 1 ==
7712 13:15:28.044372 u2DelayCellOfst[8]=0 cells (0 PI)
7713 13:15:28.047003 u2DelayCellOfst[9]=0 cells (0 PI)
7714 13:15:28.050657 u2DelayCellOfst[10]=7 cells (2 PI)
7715 13:15:28.054324 u2DelayCellOfst[11]=0 cells (0 PI)
7716 13:15:28.057038 u2DelayCellOfst[12]=10 cells (3 PI)
7717 13:15:28.060977 u2DelayCellOfst[13]=10 cells (3 PI)
7718 13:15:28.063938 u2DelayCellOfst[14]=14 cells (4 PI)
7719 13:15:28.067582 u2DelayCellOfst[15]=10 cells (3 PI)
7720 13:15:28.070507 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7721 13:15:28.077647 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7722 13:15:28.077744 DramC Write-DBI on
7723 13:15:28.077804 ==
7724 13:15:28.080839 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 13:15:28.083927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 13:15:28.087719 ==
7727 13:15:28.087801
7728 13:15:28.087858
7729 13:15:28.087911 TX Vref Scan disable
7730 13:15:28.090661 == TX Byte 0 ==
7731 13:15:28.094174 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7732 13:15:28.097284 == TX Byte 1 ==
7733 13:15:28.100616 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7734 13:15:28.100721 DramC Write-DBI off
7735 13:15:28.104278
7736 13:15:28.104355 [DATLAT]
7737 13:15:28.104413 Freq=1600, CH0 RK0
7738 13:15:28.104467
7739 13:15:28.107538 DATLAT Default: 0xf
7740 13:15:28.107614 0, 0xFFFF, sum = 0
7741 13:15:28.110684 1, 0xFFFF, sum = 0
7742 13:15:28.110762 2, 0xFFFF, sum = 0
7743 13:15:28.113600 3, 0xFFFF, sum = 0
7744 13:15:28.117618 4, 0xFFFF, sum = 0
7745 13:15:28.117700 5, 0xFFFF, sum = 0
7746 13:15:28.121549 6, 0xFFFF, sum = 0
7747 13:15:28.121629 7, 0xFFFF, sum = 0
7748 13:15:28.123744 8, 0xFFFF, sum = 0
7749 13:15:28.123820 9, 0xFFFF, sum = 0
7750 13:15:28.127880 10, 0xFFFF, sum = 0
7751 13:15:28.127960 11, 0xFFFF, sum = 0
7752 13:15:28.130450 12, 0xFFFF, sum = 0
7753 13:15:28.130527 13, 0xFFFF, sum = 0
7754 13:15:28.133975 14, 0x0, sum = 1
7755 13:15:28.134053 15, 0x0, sum = 2
7756 13:15:28.137121 16, 0x0, sum = 3
7757 13:15:28.137199 17, 0x0, sum = 4
7758 13:15:28.140440 best_step = 15
7759 13:15:28.140515
7760 13:15:28.140572 ==
7761 13:15:28.143890 Dram Type= 6, Freq= 0, CH_0, rank 0
7762 13:15:28.147294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7763 13:15:28.147372 ==
7764 13:15:28.147430 RX Vref Scan: 1
7765 13:15:28.147485
7766 13:15:28.151072 Set Vref Range= 24 -> 127
7767 13:15:28.151149
7768 13:15:28.154123 RX Vref 24 -> 127, step: 1
7769 13:15:28.154199
7770 13:15:28.158033 RX Delay 11 -> 252, step: 4
7771 13:15:28.158111
7772 13:15:28.160880 Set Vref, RX VrefLevel [Byte0]: 24
7773 13:15:28.163933 [Byte1]: 24
7774 13:15:28.164011
7775 13:15:28.167285 Set Vref, RX VrefLevel [Byte0]: 25
7776 13:15:28.170837 [Byte1]: 25
7777 13:15:28.170915
7778 13:15:28.174324 Set Vref, RX VrefLevel [Byte0]: 26
7779 13:15:28.177414 [Byte1]: 26
7780 13:15:28.181266
7781 13:15:28.181348 Set Vref, RX VrefLevel [Byte0]: 27
7782 13:15:28.184293 [Byte1]: 27
7783 13:15:28.188787
7784 13:15:28.188869 Set Vref, RX VrefLevel [Byte0]: 28
7785 13:15:28.192016 [Byte1]: 28
7786 13:15:28.195988
7787 13:15:28.196068 Set Vref, RX VrefLevel [Byte0]: 29
7788 13:15:28.199890 [Byte1]: 29
7789 13:15:28.204069
7790 13:15:28.204147 Set Vref, RX VrefLevel [Byte0]: 30
7791 13:15:28.207182 [Byte1]: 30
7792 13:15:28.211292
7793 13:15:28.211373 Set Vref, RX VrefLevel [Byte0]: 31
7794 13:15:28.215072 [Byte1]: 31
7795 13:15:28.219099
7796 13:15:28.219177 Set Vref, RX VrefLevel [Byte0]: 32
7797 13:15:28.222183 [Byte1]: 32
7798 13:15:28.226922
7799 13:15:28.227013 Set Vref, RX VrefLevel [Byte0]: 33
7800 13:15:28.230472 [Byte1]: 33
7801 13:15:28.234437
7802 13:15:28.234519 Set Vref, RX VrefLevel [Byte0]: 34
7803 13:15:28.237516 [Byte1]: 34
7804 13:15:28.242248
7805 13:15:28.242328 Set Vref, RX VrefLevel [Byte0]: 35
7806 13:15:28.245770 [Byte1]: 35
7807 13:15:28.249880
7808 13:15:28.249960 Set Vref, RX VrefLevel [Byte0]: 36
7809 13:15:28.253079 [Byte1]: 36
7810 13:15:28.257288
7811 13:15:28.257369 Set Vref, RX VrefLevel [Byte0]: 37
7812 13:15:28.260613 [Byte1]: 37
7813 13:15:28.264527
7814 13:15:28.264607 Set Vref, RX VrefLevel [Byte0]: 38
7815 13:15:28.268265 [Byte1]: 38
7816 13:15:28.272550
7817 13:15:28.272633 Set Vref, RX VrefLevel [Byte0]: 39
7818 13:15:28.275602 [Byte1]: 39
7819 13:15:28.280432
7820 13:15:28.280540 Set Vref, RX VrefLevel [Byte0]: 40
7821 13:15:28.283776 [Byte1]: 40
7822 13:15:28.287479
7823 13:15:28.287562 Set Vref, RX VrefLevel [Byte0]: 41
7824 13:15:28.291096 [Byte1]: 41
7825 13:15:28.295182
7826 13:15:28.295263 Set Vref, RX VrefLevel [Byte0]: 42
7827 13:15:28.298777 [Byte1]: 42
7828 13:15:28.302620
7829 13:15:28.302699 Set Vref, RX VrefLevel [Byte0]: 43
7830 13:15:28.309942 [Byte1]: 43
7831 13:15:28.310032
7832 13:15:28.312387 Set Vref, RX VrefLevel [Byte0]: 44
7833 13:15:28.315923 [Byte1]: 44
7834 13:15:28.316000
7835 13:15:28.319504 Set Vref, RX VrefLevel [Byte0]: 45
7836 13:15:28.322577 [Byte1]: 45
7837 13:15:28.322663
7838 13:15:28.325804 Set Vref, RX VrefLevel [Byte0]: 46
7839 13:15:28.329422 [Byte1]: 46
7840 13:15:28.333198
7841 13:15:28.333279 Set Vref, RX VrefLevel [Byte0]: 47
7842 13:15:28.336923 [Byte1]: 47
7843 13:15:28.340685
7844 13:15:28.340770 Set Vref, RX VrefLevel [Byte0]: 48
7845 13:15:28.344123 [Byte1]: 48
7846 13:15:28.348497
7847 13:15:28.348576 Set Vref, RX VrefLevel [Byte0]: 49
7848 13:15:28.351980 [Byte1]: 49
7849 13:15:28.356065
7850 13:15:28.356176 Set Vref, RX VrefLevel [Byte0]: 50
7851 13:15:28.359272 [Byte1]: 50
7852 13:15:28.363614
7853 13:15:28.363718 Set Vref, RX VrefLevel [Byte0]: 51
7854 13:15:28.367089 [Byte1]: 51
7855 13:15:28.371389
7856 13:15:28.371470 Set Vref, RX VrefLevel [Byte0]: 52
7857 13:15:28.374477 [Byte1]: 52
7858 13:15:28.379018
7859 13:15:28.379101 Set Vref, RX VrefLevel [Byte0]: 53
7860 13:15:28.382159 [Byte1]: 53
7861 13:15:28.387385
7862 13:15:28.387476 Set Vref, RX VrefLevel [Byte0]: 54
7863 13:15:28.390214 [Byte1]: 54
7864 13:15:28.394203
7865 13:15:28.394281 Set Vref, RX VrefLevel [Byte0]: 55
7866 13:15:28.397559 [Byte1]: 55
7867 13:15:28.401682
7868 13:15:28.401761 Set Vref, RX VrefLevel [Byte0]: 56
7869 13:15:28.404993 [Byte1]: 56
7870 13:15:28.409070
7871 13:15:28.409176 Set Vref, RX VrefLevel [Byte0]: 57
7872 13:15:28.412739 [Byte1]: 57
7873 13:15:28.416856
7874 13:15:28.416934 Set Vref, RX VrefLevel [Byte0]: 58
7875 13:15:28.420399 [Byte1]: 58
7876 13:15:28.424520
7877 13:15:28.424604 Set Vref, RX VrefLevel [Byte0]: 59
7878 13:15:28.427953 [Byte1]: 59
7879 13:15:28.432625
7880 13:15:28.432709 Set Vref, RX VrefLevel [Byte0]: 60
7881 13:15:28.435998 [Byte1]: 60
7882 13:15:28.440176
7883 13:15:28.440257 Set Vref, RX VrefLevel [Byte0]: 61
7884 13:15:28.443051 [Byte1]: 61
7885 13:15:28.447593
7886 13:15:28.447676 Set Vref, RX VrefLevel [Byte0]: 62
7887 13:15:28.450783 [Byte1]: 62
7888 13:15:28.455304
7889 13:15:28.455384 Set Vref, RX VrefLevel [Byte0]: 63
7890 13:15:28.458441 [Byte1]: 63
7891 13:15:28.462434
7892 13:15:28.462512 Set Vref, RX VrefLevel [Byte0]: 64
7893 13:15:28.466092 [Byte1]: 64
7894 13:15:28.470057
7895 13:15:28.470136 Set Vref, RX VrefLevel [Byte0]: 65
7896 13:15:28.473851 [Byte1]: 65
7897 13:15:28.477942
7898 13:15:28.478022 Set Vref, RX VrefLevel [Byte0]: 66
7899 13:15:28.481200 [Byte1]: 66
7900 13:15:28.485745
7901 13:15:28.485828 Set Vref, RX VrefLevel [Byte0]: 67
7902 13:15:28.488578 [Byte1]: 67
7903 13:15:28.493243
7904 13:15:28.493326 Set Vref, RX VrefLevel [Byte0]: 68
7905 13:15:28.496499 [Byte1]: 68
7906 13:15:28.500798
7907 13:15:28.500878 Set Vref, RX VrefLevel [Byte0]: 69
7908 13:15:28.503829 [Byte1]: 69
7909 13:15:28.508171
7910 13:15:28.508252 Set Vref, RX VrefLevel [Byte0]: 70
7911 13:15:28.511824 [Byte1]: 70
7912 13:15:28.515923
7913 13:15:28.516004 Set Vref, RX VrefLevel [Byte0]: 71
7914 13:15:28.519110 [Byte1]: 71
7915 13:15:28.523688
7916 13:15:28.523771 Set Vref, RX VrefLevel [Byte0]: 72
7917 13:15:28.526860 [Byte1]: 72
7918 13:15:28.531286
7919 13:15:28.531392 Set Vref, RX VrefLevel [Byte0]: 73
7920 13:15:28.534201 [Byte1]: 73
7921 13:15:28.539018
7922 13:15:28.539098 Set Vref, RX VrefLevel [Byte0]: 74
7923 13:15:28.542515 [Byte1]: 74
7924 13:15:28.546153
7925 13:15:28.546233 Set Vref, RX VrefLevel [Byte0]: 75
7926 13:15:28.549482 [Byte1]: 75
7927 13:15:28.553923
7928 13:15:28.554005 Final RX Vref Byte 0 = 60 to rank0
7929 13:15:28.557058 Final RX Vref Byte 1 = 62 to rank0
7930 13:15:28.560624 Final RX Vref Byte 0 = 60 to rank1
7931 13:15:28.564339 Final RX Vref Byte 1 = 62 to rank1==
7932 13:15:28.567316 Dram Type= 6, Freq= 0, CH_0, rank 0
7933 13:15:28.573834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7934 13:15:28.573927 ==
7935 13:15:28.573988 DQS Delay:
7936 13:15:28.574043 DQS0 = 0, DQS1 = 0
7937 13:15:28.577220 DQM Delay:
7938 13:15:28.577296 DQM0 = 129, DQM1 = 121
7939 13:15:28.580496 DQ Delay:
7940 13:15:28.583970 DQ0 =128, DQ1 =132, DQ2 =126, DQ3 =124
7941 13:15:28.587350 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =138
7942 13:15:28.590739 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7943 13:15:28.593761 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130
7944 13:15:28.593841
7945 13:15:28.593899
7946 13:15:28.593951
7947 13:15:28.597040 [DramC_TX_OE_Calibration] TA2
7948 13:15:28.600817 Original DQ_B0 (3 6) =30, OEN = 27
7949 13:15:28.604107 Original DQ_B1 (3 6) =30, OEN = 27
7950 13:15:28.607469 24, 0x0, End_B0=24 End_B1=24
7951 13:15:28.607553 25, 0x0, End_B0=25 End_B1=25
7952 13:15:28.610538 26, 0x0, End_B0=26 End_B1=26
7953 13:15:28.614172 27, 0x0, End_B0=27 End_B1=27
7954 13:15:28.617454 28, 0x0, End_B0=28 End_B1=28
7955 13:15:28.617535 29, 0x0, End_B0=29 End_B1=29
7956 13:15:28.620769 30, 0x0, End_B0=30 End_B1=30
7957 13:15:28.624017 31, 0x4141, End_B0=30 End_B1=30
7958 13:15:28.627134 Byte0 end_step=30 best_step=27
7959 13:15:28.630935 Byte1 end_step=30 best_step=27
7960 13:15:28.634263 Byte0 TX OE(2T, 0.5T) = (3, 3)
7961 13:15:28.634346 Byte1 TX OE(2T, 0.5T) = (3, 3)
7962 13:15:28.634404
7963 13:15:29.420064
7964 13:15:29.420182 [DQSOSCAuto] RK0, (LSB)MR18= 0x1307, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
7965 13:15:29.420244 CH0 RK0: MR19=303, MR18=1307
7966 13:15:29.420299 CH0_RK0: MR19=0x303, MR18=0x1307, DQSOSC=400, MR23=63, INC=23, DEC=15
7967 13:15:29.420352
7968 13:15:29.420402 ----->DramcWriteLeveling(PI) begin...
7969 13:15:29.420454 ==
7970 13:15:29.420504 Dram Type= 6, Freq= 0, CH_0, rank 1
7971 13:15:29.420553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7972 13:15:29.420604 ==
7973 13:15:29.420652 Write leveling (Byte 0): 33 => 33
7974 13:15:29.420701 Write leveling (Byte 1): 28 => 28
7975 13:15:29.420750 DramcWriteLeveling(PI) end<-----
7976 13:15:29.420798
7977 13:15:29.420846 ==
7978 13:15:29.420894 Dram Type= 6, Freq= 0, CH_0, rank 1
7979 13:15:29.420943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7980 13:15:29.420995 ==
7981 13:15:29.421045 [Gating] SW mode calibration
7982 13:15:29.421093 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7983 13:15:29.421172 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7984 13:15:29.421223 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7985 13:15:29.421273 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7986 13:15:29.421322 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7987 13:15:29.421385 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7988 13:15:29.421434 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7989 13:15:29.421483 1 4 20 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
7990 13:15:29.421531 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7991 13:15:29.421579 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7992 13:15:29.421627 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7993 13:15:29.421688 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7994 13:15:29.421802 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7995 13:15:29.421883 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7996 13:15:29.421961 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7997 13:15:29.422036 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
7998 13:15:29.422103 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7999 13:15:29.422153 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8000 13:15:29.422202 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 13:15:29.422251 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 13:15:29.422299 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8003 13:15:29.422347 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8004 13:15:29.422396 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8005 13:15:29.422445 1 6 20 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
8006 13:15:29.422493 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 13:15:29.422541 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8008 13:15:29.422589 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 13:15:29.422637 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8010 13:15:29.422685 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 13:15:29.422734 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8012 13:15:29.422801 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8013 13:15:29.422850 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8014 13:15:29.422913 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 13:15:29.422961 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 13:15:29.423009 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 13:15:29.423058 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 13:15:29.423106 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 13:15:29.423154 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 13:15:29.423203 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 13:15:29.423251 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 13:15:29.423299 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 13:15:29.423365 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 13:15:29.423414 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 13:15:29.423477 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 13:15:29.423528 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8027 13:15:29.423576 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8028 13:15:29.423623 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8029 13:15:29.423671 Total UI for P1: 0, mck2ui 16
8030 13:15:29.423720 best dqsien dly found for B0: ( 1, 9, 10)
8031 13:15:29.423768 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8032 13:15:29.423817 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 13:15:29.423865 Total UI for P1: 0, mck2ui 16
8034 13:15:29.423913 best dqsien dly found for B1: ( 1, 9, 18)
8035 13:15:29.423961 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8036 13:15:29.424010 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8037 13:15:29.424057
8038 13:15:29.424108 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8039 13:15:29.424156 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8040 13:15:29.424204 [Gating] SW calibration Done
8041 13:15:29.424252 ==
8042 13:15:29.424299 Dram Type= 6, Freq= 0, CH_0, rank 1
8043 13:15:29.424347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8044 13:15:29.424395 ==
8045 13:15:29.424443 RX Vref Scan: 0
8046 13:15:29.424490
8047 13:15:29.424537 RX Vref 0 -> 0, step: 1
8048 13:15:29.424585
8049 13:15:29.424632 RX Delay 0 -> 252, step: 8
8050 13:15:29.424679 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8051 13:15:29.424727 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8052 13:15:29.424775 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8053 13:15:29.424824 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8054 13:15:29.424872 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8055 13:15:29.424919 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8056 13:15:29.424968 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8057 13:15:29.425016 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8058 13:15:29.425064 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8059 13:15:29.425112 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8060 13:15:29.425400 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8061 13:15:29.425454 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8062 13:15:29.425504 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8063 13:15:29.425553 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8064 13:15:29.425601 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8065 13:15:29.425650 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8066 13:15:29.425698 ==
8067 13:15:29.425746 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 13:15:29.425795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 13:15:29.425843 ==
8070 13:15:29.425891 DQS Delay:
8071 13:15:29.425939 DQS0 = 0, DQS1 = 0
8072 13:15:29.425987 DQM Delay:
8073 13:15:29.426035 DQM0 = 131, DQM1 = 126
8074 13:15:29.426083 DQ Delay:
8075 13:15:29.426131 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =131
8076 13:15:29.426179 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8077 13:15:29.426228 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8078 13:15:29.426294 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8079 13:15:29.426358
8080 13:15:29.426406
8081 13:15:29.426454 ==
8082 13:15:29.426502 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 13:15:29.426550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 13:15:29.426598 ==
8085 13:15:29.426646
8086 13:15:29.426693
8087 13:15:29.426740 TX Vref Scan disable
8088 13:15:29.426789 == TX Byte 0 ==
8089 13:15:29.426838 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8090 13:15:29.426886 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8091 13:15:29.426935 == TX Byte 1 ==
8092 13:15:29.426983 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8093 13:15:29.427032 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8094 13:15:29.427079 ==
8095 13:15:29.427127 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 13:15:29.427176 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 13:15:29.427224 ==
8098 13:15:29.427272
8099 13:15:29.427319 TX Vref early break, caculate TX vref
8100 13:15:29.427367 TX Vref=16, minBit 12, minWin=22, winSum=375
8101 13:15:29.427416 TX Vref=18, minBit 3, minWin=23, winSum=387
8102 13:15:29.427465 TX Vref=20, minBit 0, minWin=24, winSum=400
8103 13:15:29.427512 TX Vref=22, minBit 3, minWin=24, winSum=408
8104 13:15:29.427560 TX Vref=24, minBit 0, minWin=25, winSum=416
8105 13:15:29.427608 TX Vref=26, minBit 3, minWin=25, winSum=425
8106 13:15:29.427656 TX Vref=28, minBit 0, minWin=26, winSum=429
8107 13:15:29.427704 TX Vref=30, minBit 0, minWin=26, winSum=427
8108 13:15:29.427752 TX Vref=32, minBit 0, minWin=24, winSum=414
8109 13:15:29.427801 TX Vref=34, minBit 4, minWin=24, winSum=406
8110 13:15:29.427849 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
8111 13:15:29.427898
8112 13:15:29.427946 Final TX Range 0 Vref 28
8113 13:15:29.427994
8114 13:15:29.428041 ==
8115 13:15:29.428090 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 13:15:29.428138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 13:15:29.428187 ==
8118 13:15:29.428234
8119 13:15:29.428281
8120 13:15:29.428328 TX Vref Scan disable
8121 13:15:29.428375 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8122 13:15:29.428423 == TX Byte 0 ==
8123 13:15:29.428471 u2DelayCellOfst[0]=10 cells (3 PI)
8124 13:15:29.428519 u2DelayCellOfst[1]=17 cells (5 PI)
8125 13:15:29.428567 u2DelayCellOfst[2]=7 cells (2 PI)
8126 13:15:29.428615 u2DelayCellOfst[3]=10 cells (3 PI)
8127 13:15:29.428662 u2DelayCellOfst[4]=7 cells (2 PI)
8128 13:15:29.428710 u2DelayCellOfst[5]=0 cells (0 PI)
8129 13:15:29.428758 u2DelayCellOfst[6]=17 cells (5 PI)
8130 13:15:29.428806 u2DelayCellOfst[7]=17 cells (5 PI)
8131 13:15:29.428854 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8132 13:15:29.428902 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8133 13:15:29.428950 == TX Byte 1 ==
8134 13:15:29.428998 u2DelayCellOfst[8]=0 cells (0 PI)
8135 13:15:29.429046 u2DelayCellOfst[9]=0 cells (0 PI)
8136 13:15:29.429094 u2DelayCellOfst[10]=7 cells (2 PI)
8137 13:15:29.429188 u2DelayCellOfst[11]=0 cells (0 PI)
8138 13:15:29.429285 u2DelayCellOfst[12]=14 cells (4 PI)
8139 13:15:29.429395 u2DelayCellOfst[13]=10 cells (3 PI)
8140 13:15:29.429506 u2DelayCellOfst[14]=14 cells (4 PI)
8141 13:15:29.429615 u2DelayCellOfst[15]=10 cells (3 PI)
8142 13:15:29.429706 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8143 13:15:29.429773 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8144 13:15:29.429839 DramC Write-DBI on
8145 13:15:29.429920 ==
8146 13:15:29.429969 Dram Type= 6, Freq= 0, CH_0, rank 1
8147 13:15:29.430018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8148 13:15:29.430068 ==
8149 13:15:29.430117
8150 13:15:29.430166
8151 13:15:29.430215 TX Vref Scan disable
8152 13:15:29.430265 == TX Byte 0 ==
8153 13:15:29.430314 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8154 13:15:29.430364 == TX Byte 1 ==
8155 13:15:29.430413 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8156 13:15:29.430462 DramC Write-DBI off
8157 13:15:29.430512
8158 13:15:29.430561 [DATLAT]
8159 13:15:29.430611 Freq=1600, CH0 RK1
8160 13:15:29.430659
8161 13:15:29.430708 DATLAT Default: 0xf
8162 13:15:29.430757 0, 0xFFFF, sum = 0
8163 13:15:29.430807 1, 0xFFFF, sum = 0
8164 13:15:29.430857 2, 0xFFFF, sum = 0
8165 13:15:29.430907 3, 0xFFFF, sum = 0
8166 13:15:29.430957 4, 0xFFFF, sum = 0
8167 13:15:29.431007 5, 0xFFFF, sum = 0
8168 13:15:29.431056 6, 0xFFFF, sum = 0
8169 13:15:29.431106 7, 0xFFFF, sum = 0
8170 13:15:29.431155 8, 0xFFFF, sum = 0
8171 13:15:29.431204 9, 0xFFFF, sum = 0
8172 13:15:29.431254 10, 0xFFFF, sum = 0
8173 13:15:29.431304 11, 0xFFFF, sum = 0
8174 13:15:29.431353 12, 0xFFFF, sum = 0
8175 13:15:29.431402 13, 0xFFFF, sum = 0
8176 13:15:29.431452 14, 0x0, sum = 1
8177 13:15:29.431502 15, 0x0, sum = 2
8178 13:15:29.431552 16, 0x0, sum = 3
8179 13:15:29.431603 17, 0x0, sum = 4
8180 13:15:29.431653 best_step = 15
8181 13:15:29.431701
8182 13:15:29.431750 ==
8183 13:15:29.431799 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 13:15:29.431848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 13:15:29.431898 ==
8186 13:15:29.431947 RX Vref Scan: 0
8187 13:15:29.431998
8188 13:15:29.432048 RX Vref 0 -> 0, step: 1
8189 13:15:29.432097
8190 13:15:29.432146 RX Delay 11 -> 252, step: 4
8191 13:15:29.432196 iDelay=195, Bit 0, Center 126 (71 ~ 182) 112
8192 13:15:29.432246 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
8193 13:15:29.432295 iDelay=195, Bit 2, Center 124 (67 ~ 182) 116
8194 13:15:29.432344 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8195 13:15:29.432393 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8196 13:15:29.432443 iDelay=195, Bit 5, Center 114 (59 ~ 170) 112
8197 13:15:29.432492 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8198 13:15:29.432541 iDelay=195, Bit 7, Center 134 (79 ~ 190) 112
8199 13:15:29.432591 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
8200 13:15:29.432640 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8201 13:15:29.432689 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8202 13:15:29.432738 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
8203 13:15:29.432977 iDelay=195, Bit 12, Center 126 (75 ~ 178) 104
8204 13:15:29.433033 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8205 13:15:29.433083 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8206 13:15:29.433144 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8207 13:15:29.433195 ==
8208 13:15:29.433246 Dram Type= 6, Freq= 0, CH_0, rank 1
8209 13:15:29.433296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8210 13:15:29.433346 ==
8211 13:15:29.433396 DQS Delay:
8212 13:15:29.433445 DQS0 = 0, DQS1 = 0
8213 13:15:29.433495 DQM Delay:
8214 13:15:29.433544 DQM0 = 127, DQM1 = 122
8215 13:15:29.433593 DQ Delay:
8216 13:15:29.433641 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8217 13:15:29.433691 DQ4 =126, DQ5 =114, DQ6 =138, DQ7 =134
8218 13:15:29.433740 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8219 13:15:29.433822 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8220 13:15:29.433870
8221 13:15:29.433949
8222 13:15:29.434027
8223 13:15:29.434076 [DramC_TX_OE_Calibration] TA2
8224 13:15:29.434157 Original DQ_B0 (3 6) =30, OEN = 27
8225 13:15:29.434207 Original DQ_B1 (3 6) =30, OEN = 27
8226 13:15:29.434256 24, 0x0, End_B0=24 End_B1=24
8227 13:15:29.434307 25, 0x0, End_B0=25 End_B1=25
8228 13:15:29.434357 26, 0x0, End_B0=26 End_B1=26
8229 13:15:29.434407 27, 0x0, End_B0=27 End_B1=27
8230 13:15:29.434458 28, 0x0, End_B0=28 End_B1=28
8231 13:15:29.434508 29, 0x0, End_B0=29 End_B1=29
8232 13:15:29.434558 30, 0x0, End_B0=30 End_B1=30
8233 13:15:29.434609 31, 0x4141, End_B0=30 End_B1=30
8234 13:15:29.434659 Byte0 end_step=30 best_step=27
8235 13:15:29.436201 Byte1 end_step=30 best_step=27
8236 13:15:29.439377 Byte0 TX OE(2T, 0.5T) = (3, 3)
8237 13:15:29.439472 Byte1 TX OE(2T, 0.5T) = (3, 3)
8238 13:15:29.439547
8239 13:15:29.442538
8240 13:15:29.449310 [DQSOSCAuto] RK1, (LSB)MR18= 0x170c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8241 13:15:29.452517 CH0 RK1: MR19=303, MR18=170C
8242 13:15:29.459719 CH0_RK1: MR19=0x303, MR18=0x170C, DQSOSC=398, MR23=63, INC=23, DEC=15
8243 13:15:29.459821 [RxdqsGatingPostProcess] freq 1600
8244 13:15:29.465833 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8245 13:15:29.469198 best DQS0 dly(2T, 0.5T) = (1, 1)
8246 13:15:29.472875 best DQS1 dly(2T, 0.5T) = (1, 1)
8247 13:15:29.476190 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8248 13:15:29.480212 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8249 13:15:29.483171 best DQS0 dly(2T, 0.5T) = (1, 1)
8250 13:15:29.486230 best DQS1 dly(2T, 0.5T) = (1, 1)
8251 13:15:29.489278 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8252 13:15:29.493244 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8253 13:15:29.493331 Pre-setting of DQS Precalculation
8254 13:15:29.499503 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8255 13:15:29.499596 ==
8256 13:15:29.502875 Dram Type= 6, Freq= 0, CH_1, rank 0
8257 13:15:29.505723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8258 13:15:29.505802 ==
8259 13:15:29.512770 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8260 13:15:29.516091 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8261 13:15:29.519224 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8262 13:15:29.525891 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8263 13:15:29.535613 [CA 0] Center 42 (14~71) winsize 58
8264 13:15:29.538893 [CA 1] Center 42 (13~71) winsize 59
8265 13:15:29.541985 [CA 2] Center 37 (8~66) winsize 59
8266 13:15:29.545506 [CA 3] Center 36 (7~65) winsize 59
8267 13:15:29.548800 [CA 4] Center 37 (8~66) winsize 59
8268 13:15:29.552190 [CA 5] Center 36 (7~66) winsize 60
8269 13:15:29.552273
8270 13:15:29.555199 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8271 13:15:29.555276
8272 13:15:29.558790 [CATrainingPosCal] consider 1 rank data
8273 13:15:29.562030 u2DelayCellTimex100 = 275/100 ps
8274 13:15:29.565491 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8275 13:15:29.571915 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8276 13:15:29.575836 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8277 13:15:29.578938 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8278 13:15:29.582015 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8279 13:15:29.585542 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8280 13:15:29.585627
8281 13:15:29.588715 CA PerBit enable=1, Macro0, CA PI delay=36
8282 13:15:29.588794
8283 13:15:29.592623 [CBTSetCACLKResult] CA Dly = 36
8284 13:15:29.592767 CS Dly: 8 (0~39)
8285 13:15:29.599016 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8286 13:15:29.602284 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8287 13:15:29.602368 ==
8288 13:15:29.605535 Dram Type= 6, Freq= 0, CH_1, rank 1
8289 13:15:29.609903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8290 13:15:29.609987 ==
8291 13:15:29.615437 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8292 13:15:29.618657 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8293 13:15:29.625490 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8294 13:15:29.629077 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8295 13:15:29.638530 [CA 0] Center 43 (14~73) winsize 60
8296 13:15:29.641883 [CA 1] Center 43 (14~72) winsize 59
8297 13:15:29.645466 [CA 2] Center 38 (9~67) winsize 59
8298 13:15:29.648373 [CA 3] Center 37 (8~66) winsize 59
8299 13:15:29.651679 [CA 4] Center 38 (9~68) winsize 60
8300 13:15:29.655763 [CA 5] Center 37 (8~66) winsize 59
8301 13:15:29.655844
8302 13:15:29.658750 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8303 13:15:29.658827
8304 13:15:29.661993 [CATrainingPosCal] consider 2 rank data
8305 13:15:29.665370 u2DelayCellTimex100 = 275/100 ps
8306 13:15:29.669008 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8307 13:15:29.675452 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8308 13:15:29.678455 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8309 13:15:29.682171 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8310 13:15:29.685275 CA4 delay=37 (9~66),Diff = 1 PI (3 cell)
8311 13:15:29.689383 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8312 13:15:29.689484
8313 13:15:29.691947 CA PerBit enable=1, Macro0, CA PI delay=36
8314 13:15:29.692023
8315 13:15:29.695580 [CBTSetCACLKResult] CA Dly = 36
8316 13:15:29.695663 CS Dly: 10 (0~44)
8317 13:15:29.702187 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8318 13:15:29.705340 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8319 13:15:29.705422
8320 13:15:29.708636 ----->DramcWriteLeveling(PI) begin...
8321 13:15:29.708737 ==
8322 13:15:29.712085 Dram Type= 6, Freq= 0, CH_1, rank 0
8323 13:15:29.715414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8324 13:15:29.715500 ==
8325 13:15:29.719001 Write leveling (Byte 0): 24 => 24
8326 13:15:29.722256 Write leveling (Byte 1): 28 => 28
8327 13:15:29.725764 DramcWriteLeveling(PI) end<-----
8328 13:15:29.725854
8329 13:15:29.725912 ==
8330 13:15:29.728683 Dram Type= 6, Freq= 0, CH_1, rank 0
8331 13:15:29.732147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 13:15:29.735776 ==
8333 13:15:29.735858 [Gating] SW mode calibration
8334 13:15:29.742616 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8335 13:15:29.748741 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8336 13:15:29.752361 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 13:15:29.758886 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 13:15:29.762001 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 13:15:29.765466 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 13:15:29.772018 1 4 16 | B1->B0 | 2929 2424 | 1 0 | (1 1) (0 0)
8341 13:15:29.775737 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8342 13:15:29.778909 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8343 13:15:29.785313 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8344 13:15:29.789210 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 13:15:29.791947 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 13:15:29.798530 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 13:15:29.802172 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8348 13:15:29.805351 1 5 16 | B1->B0 | 2f2f 3232 | 0 0 | (0 1) (0 1)
8349 13:15:29.811900 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 13:15:29.815211 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 13:15:29.818860 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 13:15:29.822084 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 13:15:29.828507 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 13:15:29.832137 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 13:15:29.835244 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 13:15:29.842398 1 6 16 | B1->B0 | 4141 3535 | 1 1 | (0 0) (0 0)
8357 13:15:29.846038 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8358 13:15:29.848739 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8359 13:15:29.855343 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 13:15:29.859424 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 13:15:29.861964 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 13:15:29.869263 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 13:15:29.872576 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8364 13:15:29.875511 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8365 13:15:29.882287 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 13:15:29.886129 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 13:15:29.888970 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 13:15:29.895617 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 13:15:29.899114 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 13:15:29.902695 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 13:15:29.905797 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 13:15:29.912452 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 13:15:29.915933 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 13:15:29.918878 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 13:15:29.925952 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 13:15:29.928861 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 13:15:29.932842 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 13:15:29.939215 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 13:15:29.942479 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8380 13:15:29.945766 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8381 13:15:29.952546 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 13:15:29.952646 Total UI for P1: 0, mck2ui 16
8383 13:15:29.959133 best dqsien dly found for B0: ( 1, 9, 14)
8384 13:15:29.959224 Total UI for P1: 0, mck2ui 16
8385 13:15:29.962776 best dqsien dly found for B1: ( 1, 9, 16)
8386 13:15:29.969138 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8387 13:15:29.972523 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8388 13:15:29.972607
8389 13:15:29.976004 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8390 13:15:29.979850 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8391 13:15:29.982528 [Gating] SW calibration Done
8392 13:15:29.982658 ==
8393 13:15:29.985715 Dram Type= 6, Freq= 0, CH_1, rank 0
8394 13:15:29.988985 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8395 13:15:29.989090 ==
8396 13:15:29.992203 RX Vref Scan: 0
8397 13:15:29.992306
8398 13:15:29.992391 RX Vref 0 -> 0, step: 1
8399 13:15:29.992470
8400 13:15:29.995746 RX Delay 0 -> 252, step: 8
8401 13:15:29.998937 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8402 13:15:30.002203 iDelay=208, Bit 1, Center 127 (72 ~ 183) 112
8403 13:15:30.009230 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8404 13:15:30.012673 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8405 13:15:30.015901 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8406 13:15:30.019356 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8407 13:15:30.022889 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8408 13:15:30.029316 iDelay=208, Bit 7, Center 131 (80 ~ 183) 104
8409 13:15:30.032471 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8410 13:15:30.035645 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8411 13:15:30.039841 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8412 13:15:30.042999 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8413 13:15:30.048832 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8414 13:15:30.052885 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8415 13:15:30.056044 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8416 13:15:30.059243 iDelay=208, Bit 15, Center 131 (80 ~ 183) 104
8417 13:15:30.059407 ==
8418 13:15:30.062431 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 13:15:30.068968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 13:15:30.069092 ==
8421 13:15:30.069187 DQS Delay:
8422 13:15:30.069241 DQS0 = 0, DQS1 = 0
8423 13:15:30.072545 DQM Delay:
8424 13:15:30.072622 DQM0 = 135, DQM1 = 126
8425 13:15:30.075732 DQ Delay:
8426 13:15:30.080551 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8427 13:15:30.082269 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =131
8428 13:15:30.085965 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8429 13:15:30.089655 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8430 13:15:30.089757
8431 13:15:30.089843
8432 13:15:30.089923 ==
8433 13:15:30.092820 Dram Type= 6, Freq= 0, CH_1, rank 0
8434 13:15:30.096152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8435 13:15:30.096255 ==
8436 13:15:30.096339
8437 13:15:30.099583
8438 13:15:30.099661 TX Vref Scan disable
8439 13:15:30.102765 == TX Byte 0 ==
8440 13:15:30.106137 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8441 13:15:30.109346 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8442 13:15:30.112768 == TX Byte 1 ==
8443 13:15:30.116390 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8444 13:15:30.119376 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8445 13:15:30.119527 ==
8446 13:15:30.122592 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 13:15:30.129079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 13:15:30.129204 ==
8449 13:15:30.140829
8450 13:15:30.144102 TX Vref early break, caculate TX vref
8451 13:15:30.147682 TX Vref=16, minBit 8, minWin=20, winSum=362
8452 13:15:30.151124 TX Vref=18, minBit 8, minWin=21, winSum=377
8453 13:15:30.155039 TX Vref=20, minBit 8, minWin=22, winSum=389
8454 13:15:30.157589 TX Vref=22, minBit 8, minWin=22, winSum=393
8455 13:15:30.161278 TX Vref=24, minBit 8, minWin=23, winSum=403
8456 13:15:30.167620 TX Vref=26, minBit 5, minWin=25, winSum=417
8457 13:15:30.170997 TX Vref=28, minBit 0, minWin=26, winSum=420
8458 13:15:30.174102 TX Vref=30, minBit 8, minWin=24, winSum=416
8459 13:15:30.177347 TX Vref=32, minBit 0, minWin=25, winSum=413
8460 13:15:30.180927 TX Vref=34, minBit 0, minWin=24, winSum=396
8461 13:15:30.187640 [TxChooseVref] Worse bit 0, Min win 26, Win sum 420, Final Vref 28
8462 13:15:30.187742
8463 13:15:30.191003 Final TX Range 0 Vref 28
8464 13:15:30.191083
8465 13:15:30.191144 ==
8466 13:15:30.194104 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 13:15:30.197677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 13:15:30.197758 ==
8469 13:15:30.197815
8470 13:15:30.197868
8471 13:15:30.200801 TX Vref Scan disable
8472 13:15:30.207474 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8473 13:15:30.207569 == TX Byte 0 ==
8474 13:15:30.210682 u2DelayCellOfst[0]=14 cells (4 PI)
8475 13:15:30.213947 u2DelayCellOfst[1]=10 cells (3 PI)
8476 13:15:30.218039 u2DelayCellOfst[2]=0 cells (0 PI)
8477 13:15:30.221069 u2DelayCellOfst[3]=7 cells (2 PI)
8478 13:15:30.224062 u2DelayCellOfst[4]=7 cells (2 PI)
8479 13:15:30.227677 u2DelayCellOfst[5]=17 cells (5 PI)
8480 13:15:30.227759 u2DelayCellOfst[6]=17 cells (5 PI)
8481 13:15:30.230868 u2DelayCellOfst[7]=7 cells (2 PI)
8482 13:15:30.237723 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8483 13:15:30.240919 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8484 13:15:30.241002 == TX Byte 1 ==
8485 13:15:30.244306 u2DelayCellOfst[8]=0 cells (0 PI)
8486 13:15:30.247514 u2DelayCellOfst[9]=0 cells (0 PI)
8487 13:15:30.250977 u2DelayCellOfst[10]=7 cells (2 PI)
8488 13:15:30.254326 u2DelayCellOfst[11]=3 cells (1 PI)
8489 13:15:30.257376 u2DelayCellOfst[12]=10 cells (3 PI)
8490 13:15:30.260930 u2DelayCellOfst[13]=10 cells (3 PI)
8491 13:15:30.264152 u2DelayCellOfst[14]=14 cells (4 PI)
8492 13:15:30.267644 u2DelayCellOfst[15]=14 cells (4 PI)
8493 13:15:30.271128 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8494 13:15:30.274193 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8495 13:15:30.277760 DramC Write-DBI on
8496 13:15:30.277851 ==
8497 13:15:30.281474 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 13:15:30.284444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8499 13:15:30.284526 ==
8500 13:15:30.284585
8501 13:15:30.284638
8502 13:15:30.288146 TX Vref Scan disable
8503 13:15:30.290914 == TX Byte 0 ==
8504 13:15:30.294726 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8505 13:15:30.294821 == TX Byte 1 ==
8506 13:15:30.300850 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8507 13:15:30.300952 DramC Write-DBI off
8508 13:15:30.301037
8509 13:15:30.304256 [DATLAT]
8510 13:15:30.304335 Freq=1600, CH1 RK0
8511 13:15:30.304394
8512 13:15:30.307912 DATLAT Default: 0xf
8513 13:15:30.307990 0, 0xFFFF, sum = 0
8514 13:15:30.311121 1, 0xFFFF, sum = 0
8515 13:15:30.311198 2, 0xFFFF, sum = 0
8516 13:15:30.314259 3, 0xFFFF, sum = 0
8517 13:15:30.314343 4, 0xFFFF, sum = 0
8518 13:15:30.317541 5, 0xFFFF, sum = 0
8519 13:15:30.317620 6, 0xFFFF, sum = 0
8520 13:15:30.320801 7, 0xFFFF, sum = 0
8521 13:15:30.320880 8, 0xFFFF, sum = 0
8522 13:15:30.324486 9, 0xFFFF, sum = 0
8523 13:15:30.324565 10, 0xFFFF, sum = 0
8524 13:15:30.327717 11, 0xFFFF, sum = 0
8525 13:15:30.327814 12, 0xFFFF, sum = 0
8526 13:15:30.331266 13, 0xFFFF, sum = 0
8527 13:15:30.331343 14, 0x0, sum = 1
8528 13:15:30.334240 15, 0x0, sum = 2
8529 13:15:30.334319 16, 0x0, sum = 3
8530 13:15:30.337713 17, 0x0, sum = 4
8531 13:15:30.337815 best_step = 15
8532 13:15:30.337891
8533 13:15:30.337977 ==
8534 13:15:30.341822 Dram Type= 6, Freq= 0, CH_1, rank 0
8535 13:15:30.347730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8536 13:15:30.347864 ==
8537 13:15:30.347930 RX Vref Scan: 1
8538 13:15:30.348015
8539 13:15:30.351460 Set Vref Range= 24 -> 127
8540 13:15:30.351574
8541 13:15:30.354704 RX Vref 24 -> 127, step: 1
8542 13:15:30.354795
8543 13:15:30.354854 RX Delay 11 -> 252, step: 4
8544 13:15:30.354909
8545 13:15:30.357917 Set Vref, RX VrefLevel [Byte0]: 24
8546 13:15:30.361166 [Byte1]: 24
8547 13:15:30.365044
8548 13:15:30.365185 Set Vref, RX VrefLevel [Byte0]: 25
8549 13:15:30.368541 [Byte1]: 25
8550 13:15:30.372853
8551 13:15:30.373015 Set Vref, RX VrefLevel [Byte0]: 26
8552 13:15:30.375920 [Byte1]: 26
8553 13:15:30.380633
8554 13:15:30.380742 Set Vref, RX VrefLevel [Byte0]: 27
8555 13:15:30.383905 [Byte1]: 27
8556 13:15:30.388075
8557 13:15:30.388199 Set Vref, RX VrefLevel [Byte0]: 28
8558 13:15:30.394699 [Byte1]: 28
8559 13:15:30.394814
8560 13:15:30.397872 Set Vref, RX VrefLevel [Byte0]: 29
8561 13:15:30.401112 [Byte1]: 29
8562 13:15:30.401248
8563 13:15:30.404923 Set Vref, RX VrefLevel [Byte0]: 30
8564 13:15:30.407904 [Byte1]: 30
8565 13:15:30.408026
8566 13:15:30.411467 Set Vref, RX VrefLevel [Byte0]: 31
8567 13:15:30.414811 [Byte1]: 31
8568 13:15:30.418774
8569 13:15:30.418868 Set Vref, RX VrefLevel [Byte0]: 32
8570 13:15:30.422180 [Byte1]: 32
8571 13:15:30.426303
8572 13:15:30.426394 Set Vref, RX VrefLevel [Byte0]: 33
8573 13:15:30.429507 [Byte1]: 33
8574 13:15:30.433795
8575 13:15:30.433908 Set Vref, RX VrefLevel [Byte0]: 34
8576 13:15:30.436986 [Byte1]: 34
8577 13:15:30.441512
8578 13:15:30.441616 Set Vref, RX VrefLevel [Byte0]: 35
8579 13:15:30.444561 [Byte1]: 35
8580 13:15:30.449083
8581 13:15:30.449233 Set Vref, RX VrefLevel [Byte0]: 36
8582 13:15:30.452041 [Byte1]: 36
8583 13:15:30.456408
8584 13:15:30.456525 Set Vref, RX VrefLevel [Byte0]: 37
8585 13:15:30.459805 [Byte1]: 37
8586 13:15:30.464157
8587 13:15:30.464266 Set Vref, RX VrefLevel [Byte0]: 38
8588 13:15:30.467403 [Byte1]: 38
8589 13:15:30.471877
8590 13:15:30.471990 Set Vref, RX VrefLevel [Byte0]: 39
8591 13:15:30.475289 [Byte1]: 39
8592 13:15:30.479309
8593 13:15:30.479418 Set Vref, RX VrefLevel [Byte0]: 40
8594 13:15:30.482867 [Byte1]: 40
8595 13:15:30.487026
8596 13:15:30.487124 Set Vref, RX VrefLevel [Byte0]: 41
8597 13:15:30.490189 [Byte1]: 41
8598 13:15:30.494810
8599 13:15:30.494926 Set Vref, RX VrefLevel [Byte0]: 42
8600 13:15:30.497852 [Byte1]: 42
8601 13:15:30.502101
8602 13:15:30.502199 Set Vref, RX VrefLevel [Byte0]: 43
8603 13:15:30.505814 [Byte1]: 43
8604 13:15:30.510073
8605 13:15:30.510169 Set Vref, RX VrefLevel [Byte0]: 44
8606 13:15:30.513040 [Byte1]: 44
8607 13:15:30.517737
8608 13:15:30.517845 Set Vref, RX VrefLevel [Byte0]: 45
8609 13:15:30.520644 [Byte1]: 45
8610 13:15:30.525039
8611 13:15:30.525183 Set Vref, RX VrefLevel [Byte0]: 46
8612 13:15:30.528492 [Byte1]: 46
8613 13:15:30.532715
8614 13:15:30.532802 Set Vref, RX VrefLevel [Byte0]: 47
8615 13:15:30.536384 [Byte1]: 47
8616 13:15:30.540730
8617 13:15:30.540817 Set Vref, RX VrefLevel [Byte0]: 48
8618 13:15:30.543486 [Byte1]: 48
8619 13:15:30.548314
8620 13:15:30.548400 Set Vref, RX VrefLevel [Byte0]: 49
8621 13:15:30.551107 [Byte1]: 49
8622 13:15:30.555703
8623 13:15:30.555790 Set Vref, RX VrefLevel [Byte0]: 50
8624 13:15:30.558932 [Byte1]: 50
8625 13:15:30.563273
8626 13:15:30.563356 Set Vref, RX VrefLevel [Byte0]: 51
8627 13:15:30.566508 [Byte1]: 51
8628 13:15:30.571662
8629 13:15:30.571769 Set Vref, RX VrefLevel [Byte0]: 52
8630 13:15:30.574264 [Byte1]: 52
8631 13:15:30.578148
8632 13:15:30.578231 Set Vref, RX VrefLevel [Byte0]: 53
8633 13:15:30.581727 [Byte1]: 53
8634 13:15:30.585956
8635 13:15:30.586043 Set Vref, RX VrefLevel [Byte0]: 54
8636 13:15:30.589096 [Byte1]: 54
8637 13:15:30.593665
8638 13:15:30.593754 Set Vref, RX VrefLevel [Byte0]: 55
8639 13:15:30.596723 [Byte1]: 55
8640 13:15:30.600947
8641 13:15:30.601031 Set Vref, RX VrefLevel [Byte0]: 56
8642 13:15:30.604452 [Byte1]: 56
8643 13:15:30.608704
8644 13:15:30.608789 Set Vref, RX VrefLevel [Byte0]: 57
8645 13:15:30.612276 [Byte1]: 57
8646 13:15:30.616490
8647 13:15:30.616573 Set Vref, RX VrefLevel [Byte0]: 58
8648 13:15:30.619942 [Byte1]: 58
8649 13:15:30.624065
8650 13:15:30.624149 Set Vref, RX VrefLevel [Byte0]: 59
8651 13:15:30.627394 [Byte1]: 59
8652 13:15:30.631545
8653 13:15:30.631628 Set Vref, RX VrefLevel [Byte0]: 60
8654 13:15:30.634840 [Byte1]: 60
8655 13:15:30.639254
8656 13:15:30.639340 Set Vref, RX VrefLevel [Byte0]: 61
8657 13:15:30.642330 [Byte1]: 61
8658 13:15:30.646911
8659 13:15:30.646996 Set Vref, RX VrefLevel [Byte0]: 62
8660 13:15:30.649851 [Byte1]: 62
8661 13:15:30.654664
8662 13:15:30.654747 Set Vref, RX VrefLevel [Byte0]: 63
8663 13:15:30.658231 [Byte1]: 63
8664 13:15:30.661868
8665 13:15:30.661951 Set Vref, RX VrefLevel [Byte0]: 64
8666 13:15:30.665437 [Byte1]: 64
8667 13:15:30.669811
8668 13:15:30.669895 Set Vref, RX VrefLevel [Byte0]: 65
8669 13:15:30.673129 [Byte1]: 65
8670 13:15:30.677326
8671 13:15:30.677411 Set Vref, RX VrefLevel [Byte0]: 66
8672 13:15:30.681070 [Byte1]: 66
8673 13:15:30.684890
8674 13:15:30.684976 Set Vref, RX VrefLevel [Byte0]: 67
8675 13:15:30.688592 [Byte1]: 67
8676 13:15:30.692869
8677 13:15:30.692958 Set Vref, RX VrefLevel [Byte0]: 68
8678 13:15:30.695948 [Byte1]: 68
8679 13:15:30.700163
8680 13:15:30.700286 Set Vref, RX VrefLevel [Byte0]: 69
8681 13:15:30.703772 [Byte1]: 69
8682 13:15:30.708463
8683 13:15:30.708565 Set Vref, RX VrefLevel [Byte0]: 70
8684 13:15:30.710922 [Byte1]: 70
8685 13:15:30.715218
8686 13:15:30.715306 Set Vref, RX VrefLevel [Byte0]: 71
8687 13:15:30.718817 [Byte1]: 71
8688 13:15:30.723265
8689 13:15:30.723349 Set Vref, RX VrefLevel [Byte0]: 72
8690 13:15:30.726108 [Byte1]: 72
8691 13:15:30.730782
8692 13:15:30.730868 Set Vref, RX VrefLevel [Byte0]: 73
8693 13:15:30.734250 [Byte1]: 73
8694 13:15:30.738288
8695 13:15:30.738376 Final RX Vref Byte 0 = 63 to rank0
8696 13:15:30.741320 Final RX Vref Byte 1 = 55 to rank0
8697 13:15:30.744976 Final RX Vref Byte 0 = 63 to rank1
8698 13:15:30.748563 Final RX Vref Byte 1 = 55 to rank1==
8699 13:15:30.751757 Dram Type= 6, Freq= 0, CH_1, rank 0
8700 13:15:30.758248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8701 13:15:30.758346 ==
8702 13:15:30.758427 DQS Delay:
8703 13:15:30.761317 DQS0 = 0, DQS1 = 0
8704 13:15:30.761400 DQM Delay:
8705 13:15:30.761477 DQM0 = 131, DQM1 = 124
8706 13:15:30.764965 DQ Delay:
8707 13:15:30.768245 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8708 13:15:30.771453 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8709 13:15:30.774458 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =118
8710 13:15:30.778271 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8711 13:15:30.778356
8712 13:15:30.778415
8713 13:15:30.778468
8714 13:15:30.781462 [DramC_TX_OE_Calibration] TA2
8715 13:15:30.784780 Original DQ_B0 (3 6) =30, OEN = 27
8716 13:15:30.787856 Original DQ_B1 (3 6) =30, OEN = 27
8717 13:15:30.790865 24, 0x0, End_B0=24 End_B1=24
8718 13:15:30.790952 25, 0x0, End_B0=25 End_B1=25
8719 13:15:30.794825 26, 0x0, End_B0=26 End_B1=26
8720 13:15:30.797961 27, 0x0, End_B0=27 End_B1=27
8721 13:15:30.800942 28, 0x0, End_B0=28 End_B1=28
8722 13:15:30.804812 29, 0x0, End_B0=29 End_B1=29
8723 13:15:30.804897 30, 0x0, End_B0=30 End_B1=30
8724 13:15:30.808337 31, 0x4141, End_B0=30 End_B1=30
8725 13:15:30.811187 Byte0 end_step=30 best_step=27
8726 13:15:30.814226 Byte1 end_step=30 best_step=27
8727 13:15:30.817518 Byte0 TX OE(2T, 0.5T) = (3, 3)
8728 13:15:30.821291 Byte1 TX OE(2T, 0.5T) = (3, 3)
8729 13:15:30.821374
8730 13:15:30.821432
8731 13:15:30.827493 [DQSOSCAuto] RK0, (LSB)MR18= 0x14fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 399 ps
8732 13:15:30.830922 CH1 RK0: MR19=302, MR18=14FE
8733 13:15:30.837832 CH1_RK0: MR19=0x302, MR18=0x14FE, DQSOSC=399, MR23=63, INC=23, DEC=15
8734 13:15:30.837935
8735 13:15:30.840993 ----->DramcWriteLeveling(PI) begin...
8736 13:15:30.841099 ==
8737 13:15:30.844369 Dram Type= 6, Freq= 0, CH_1, rank 1
8738 13:15:30.847805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8739 13:15:30.847889 ==
8740 13:15:30.851080 Write leveling (Byte 0): 26 => 26
8741 13:15:30.854098 Write leveling (Byte 1): 27 => 27
8742 13:15:30.857431 DramcWriteLeveling(PI) end<-----
8743 13:15:30.857516
8744 13:15:30.857591 ==
8745 13:15:30.861102 Dram Type= 6, Freq= 0, CH_1, rank 1
8746 13:15:30.864420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8747 13:15:30.864503 ==
8748 13:15:30.867551 [Gating] SW mode calibration
8749 13:15:30.874116 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8750 13:15:30.881010 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8751 13:15:30.883915 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 13:15:30.890934 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 13:15:30.894159 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 13:15:30.897199 1 4 12 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
8755 13:15:30.900893 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8756 13:15:30.907289 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 13:15:30.911124 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 13:15:30.914351 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 13:15:30.920738 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 13:15:30.923962 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 13:15:30.927279 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
8762 13:15:30.934026 1 5 12 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
8763 13:15:30.937550 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 13:15:30.940474 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 13:15:30.947679 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 13:15:30.950796 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 13:15:30.954029 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 13:15:30.960401 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 13:15:30.963741 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8770 13:15:30.967157 1 6 12 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
8771 13:15:30.974044 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8772 13:15:30.977169 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 13:15:30.980349 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 13:15:30.987532 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 13:15:30.990967 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 13:15:30.994196 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 13:15:30.997957 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8778 13:15:31.003883 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8779 13:15:31.007527 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8780 13:15:31.010608 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 13:15:31.017261 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 13:15:31.021347 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 13:15:31.024353 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 13:15:31.030858 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 13:15:31.034304 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 13:15:31.037760 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 13:15:31.044000 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 13:15:31.047332 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 13:15:31.050865 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 13:15:31.057587 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 13:15:31.060663 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 13:15:31.064255 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8793 13:15:31.070607 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8794 13:15:31.073932 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8795 13:15:31.077477 Total UI for P1: 0, mck2ui 16
8796 13:15:31.080773 best dqsien dly found for B0: ( 1, 9, 6)
8797 13:15:31.084520 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8798 13:15:31.087369 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 13:15:31.090681 Total UI for P1: 0, mck2ui 16
8800 13:15:31.094139 best dqsien dly found for B1: ( 1, 9, 14)
8801 13:15:31.097303 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8802 13:15:31.103867 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8803 13:15:31.103983
8804 13:15:31.107161 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8805 13:15:31.110766 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8806 13:15:31.113898 [Gating] SW calibration Done
8807 13:15:31.113996 ==
8808 13:15:31.117352 Dram Type= 6, Freq= 0, CH_1, rank 1
8809 13:15:31.120821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8810 13:15:31.120916 ==
8811 13:15:31.120998 RX Vref Scan: 0
8812 13:15:31.123970
8813 13:15:31.124060 RX Vref 0 -> 0, step: 1
8814 13:15:31.124139
8815 13:15:31.127287 RX Delay 0 -> 252, step: 8
8816 13:15:31.130870 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8817 13:15:31.134422 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8818 13:15:31.140745 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8819 13:15:31.144367 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8820 13:15:31.147192 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8821 13:15:31.150526 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8822 13:15:31.154292 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8823 13:15:31.157619 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8824 13:15:31.163889 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8825 13:15:31.167361 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8826 13:15:31.170786 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8827 13:15:31.174148 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8828 13:15:31.181015 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8829 13:15:31.184082 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8830 13:15:31.188148 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8831 13:15:31.191172 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8832 13:15:31.191259 ==
8833 13:15:31.194323 Dram Type= 6, Freq= 0, CH_1, rank 1
8834 13:15:31.197548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8835 13:15:31.200754 ==
8836 13:15:31.200834 DQS Delay:
8837 13:15:31.200893 DQS0 = 0, DQS1 = 0
8838 13:15:31.204303 DQM Delay:
8839 13:15:31.204384 DQM0 = 132, DQM1 = 127
8840 13:15:31.207684 DQ Delay:
8841 13:15:31.210804 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =135
8842 13:15:31.214299 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =127
8843 13:15:31.217660 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8844 13:15:31.220928 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8845 13:15:31.221012
8846 13:15:31.221070
8847 13:15:31.221129 ==
8848 13:15:31.224096 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 13:15:31.227498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 13:15:31.227599 ==
8851 13:15:31.227687
8852 13:15:31.227768
8853 13:15:31.230923 TX Vref Scan disable
8854 13:15:31.234604 == TX Byte 0 ==
8855 13:15:31.237730 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8856 13:15:31.241252 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8857 13:15:31.244346 == TX Byte 1 ==
8858 13:15:31.247599 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8859 13:15:31.251214 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8860 13:15:31.251326 ==
8861 13:15:31.254598 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 13:15:31.258070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 13:15:31.260786 ==
8864 13:15:31.272702
8865 13:15:31.276307 TX Vref early break, caculate TX vref
8866 13:15:31.279404 TX Vref=16, minBit 11, minWin=22, winSum=380
8867 13:15:31.282741 TX Vref=18, minBit 8, minWin=23, winSum=388
8868 13:15:31.286422 TX Vref=20, minBit 0, minWin=24, winSum=394
8869 13:15:31.289608 TX Vref=22, minBit 8, minWin=24, winSum=400
8870 13:15:31.292694 TX Vref=24, minBit 5, minWin=25, winSum=415
8871 13:15:31.299499 TX Vref=26, minBit 0, minWin=26, winSum=421
8872 13:15:31.303045 TX Vref=28, minBit 0, minWin=26, winSum=425
8873 13:15:31.306239 TX Vref=30, minBit 0, minWin=26, winSum=421
8874 13:15:31.309636 TX Vref=32, minBit 0, minWin=25, winSum=414
8875 13:15:31.312795 TX Vref=34, minBit 0, minWin=25, winSum=409
8876 13:15:31.316521 TX Vref=36, minBit 0, minWin=24, winSum=398
8877 13:15:31.322884 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
8878 13:15:31.322978
8879 13:15:31.326311 Final TX Range 0 Vref 28
8880 13:15:31.326392
8881 13:15:31.326481 ==
8882 13:15:31.329492 Dram Type= 6, Freq= 0, CH_1, rank 1
8883 13:15:31.332963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8884 13:15:31.333045 ==
8885 13:15:31.333160
8886 13:15:31.333248
8887 13:15:31.336563 TX Vref Scan disable
8888 13:15:31.342875 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8889 13:15:31.342968 == TX Byte 0 ==
8890 13:15:31.346348 u2DelayCellOfst[0]=17 cells (5 PI)
8891 13:15:31.349803 u2DelayCellOfst[1]=10 cells (3 PI)
8892 13:15:31.352935 u2DelayCellOfst[2]=0 cells (0 PI)
8893 13:15:31.356431 u2DelayCellOfst[3]=7 cells (2 PI)
8894 13:15:31.359928 u2DelayCellOfst[4]=7 cells (2 PI)
8895 13:15:31.363347 u2DelayCellOfst[5]=17 cells (5 PI)
8896 13:15:31.366506 u2DelayCellOfst[6]=17 cells (5 PI)
8897 13:15:31.366591 u2DelayCellOfst[7]=7 cells (2 PI)
8898 13:15:31.373368 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8899 13:15:31.376675 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8900 13:15:31.376761 == TX Byte 1 ==
8901 13:15:31.380070 u2DelayCellOfst[8]=0 cells (0 PI)
8902 13:15:31.383353 u2DelayCellOfst[9]=7 cells (2 PI)
8903 13:15:31.387047 u2DelayCellOfst[10]=14 cells (4 PI)
8904 13:15:31.390170 u2DelayCellOfst[11]=7 cells (2 PI)
8905 13:15:31.393484 u2DelayCellOfst[12]=17 cells (5 PI)
8906 13:15:31.396618 u2DelayCellOfst[13]=17 cells (5 PI)
8907 13:15:31.400209 u2DelayCellOfst[14]=21 cells (6 PI)
8908 13:15:31.403048 u2DelayCellOfst[15]=21 cells (6 PI)
8909 13:15:31.406579 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8910 13:15:31.412966 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8911 13:15:31.413084 DramC Write-DBI on
8912 13:15:31.413172 ==
8913 13:15:31.416652 Dram Type= 6, Freq= 0, CH_1, rank 1
8914 13:15:31.419952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8915 13:15:31.420033 ==
8916 13:15:31.420109
8917 13:15:31.420181
8918 13:15:31.423199 TX Vref Scan disable
8919 13:15:31.426517 == TX Byte 0 ==
8920 13:15:31.430148 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8921 13:15:31.433157 == TX Byte 1 ==
8922 13:15:31.436456 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8923 13:15:31.436540 DramC Write-DBI off
8924 13:15:31.436617
8925 13:15:31.439941 [DATLAT]
8926 13:15:31.440022 Freq=1600, CH1 RK1
8927 13:15:31.440099
8928 13:15:31.443373 DATLAT Default: 0xf
8929 13:15:31.443453 0, 0xFFFF, sum = 0
8930 13:15:31.446698 1, 0xFFFF, sum = 0
8931 13:15:31.446779 2, 0xFFFF, sum = 0
8932 13:15:31.449714 3, 0xFFFF, sum = 0
8933 13:15:31.449796 4, 0xFFFF, sum = 0
8934 13:15:31.453806 5, 0xFFFF, sum = 0
8935 13:15:31.453896 6, 0xFFFF, sum = 0
8936 13:15:31.456382 7, 0xFFFF, sum = 0
8937 13:15:31.456460 8, 0xFFFF, sum = 0
8938 13:15:31.459602 9, 0xFFFF, sum = 0
8939 13:15:31.463080 10, 0xFFFF, sum = 0
8940 13:15:31.463161 11, 0xFFFF, sum = 0
8941 13:15:31.466516 12, 0xFFFF, sum = 0
8942 13:15:31.466596 13, 0xFFFF, sum = 0
8943 13:15:31.469889 14, 0x0, sum = 1
8944 13:15:31.469969 15, 0x0, sum = 2
8945 13:15:31.473192 16, 0x0, sum = 3
8946 13:15:31.473273 17, 0x0, sum = 4
8947 13:15:31.473333 best_step = 15
8948 13:15:31.473387
8949 13:15:31.476448 ==
8950 13:15:31.480305 Dram Type= 6, Freq= 0, CH_1, rank 1
8951 13:15:31.482917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8952 13:15:31.483027 ==
8953 13:15:31.483092 RX Vref Scan: 0
8954 13:15:31.483147
8955 13:15:31.486535 RX Vref 0 -> 0, step: 1
8956 13:15:31.486616
8957 13:15:31.490334 RX Delay 11 -> 252, step: 4
8958 13:15:31.492831 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8959 13:15:31.496321 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8960 13:15:31.503017 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
8961 13:15:31.506566 iDelay=191, Bit 3, Center 128 (79 ~ 178) 100
8962 13:15:31.510167 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8963 13:15:31.513047 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
8964 13:15:31.516193 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8965 13:15:31.523093 iDelay=191, Bit 7, Center 124 (75 ~ 174) 100
8966 13:15:31.526326 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8967 13:15:31.529916 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8968 13:15:31.533262 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8969 13:15:31.536140 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8970 13:15:31.542891 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8971 13:15:31.546264 iDelay=191, Bit 13, Center 136 (83 ~ 190) 108
8972 13:15:31.549836 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8973 13:15:31.553211 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8974 13:15:31.553293 ==
8975 13:15:31.556434 Dram Type= 6, Freq= 0, CH_1, rank 1
8976 13:15:31.562922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8977 13:15:31.563015 ==
8978 13:15:31.563095 DQS Delay:
8979 13:15:31.563167 DQS0 = 0, DQS1 = 0
8980 13:15:31.566665 DQM Delay:
8981 13:15:31.566744 DQM0 = 129, DQM1 = 125
8982 13:15:31.569962 DQ Delay:
8983 13:15:31.573326 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =128
8984 13:15:31.576462 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =124
8985 13:15:31.579823 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =116
8986 13:15:31.583256 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134
8987 13:15:31.583340
8988 13:15:31.583430
8989 13:15:31.583522
8990 13:15:31.586447 [DramC_TX_OE_Calibration] TA2
8991 13:15:31.589728 Original DQ_B0 (3 6) =30, OEN = 27
8992 13:15:31.593311 Original DQ_B1 (3 6) =30, OEN = 27
8993 13:15:31.596811 24, 0x0, End_B0=24 End_B1=24
8994 13:15:31.596891 25, 0x0, End_B0=25 End_B1=25
8995 13:15:31.599944 26, 0x0, End_B0=26 End_B1=26
8996 13:15:31.603097 27, 0x0, End_B0=27 End_B1=27
8997 13:15:31.606857 28, 0x0, End_B0=28 End_B1=28
8998 13:15:31.606937 29, 0x0, End_B0=29 End_B1=29
8999 13:15:31.609761 30, 0x0, End_B0=30 End_B1=30
9000 13:15:31.613386 31, 0x4141, End_B0=30 End_B1=30
9001 13:15:31.616443 Byte0 end_step=30 best_step=27
9002 13:15:31.619862 Byte1 end_step=30 best_step=27
9003 13:15:31.623332 Byte0 TX OE(2T, 0.5T) = (3, 3)
9004 13:15:31.623429 Byte1 TX OE(2T, 0.5T) = (3, 3)
9005 13:15:31.623517
9006 13:15:31.626442
9007 13:15:31.633113 [DQSOSCAuto] RK1, (LSB)MR18= 0x1015, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 401 ps
9008 13:15:31.636379 CH1 RK1: MR19=303, MR18=1015
9009 13:15:31.643395 CH1_RK1: MR19=0x303, MR18=0x1015, DQSOSC=399, MR23=63, INC=23, DEC=15
9010 13:15:31.643474 [RxdqsGatingPostProcess] freq 1600
9011 13:15:31.650205 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9012 13:15:31.653282 best DQS0 dly(2T, 0.5T) = (1, 1)
9013 13:15:31.656421 best DQS1 dly(2T, 0.5T) = (1, 1)
9014 13:15:31.659963 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9015 13:15:31.663303 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9016 13:15:31.666498 best DQS0 dly(2T, 0.5T) = (1, 1)
9017 13:15:31.670095 best DQS1 dly(2T, 0.5T) = (1, 1)
9018 13:15:31.673203 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9019 13:15:31.673280 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9020 13:15:31.676816 Pre-setting of DQS Precalculation
9021 13:15:31.683118 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9022 13:15:31.689871 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9023 13:15:31.696413 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9024 13:15:31.696493
9025 13:15:31.696570
9026 13:15:31.700724 [Calibration Summary] 3200 Mbps
9027 13:15:31.703052 CH 0, Rank 0
9028 13:15:31.703158 SW Impedance : PASS
9029 13:15:31.706367 DUTY Scan : NO K
9030 13:15:31.706445 ZQ Calibration : PASS
9031 13:15:31.710064 Jitter Meter : NO K
9032 13:15:31.713251 CBT Training : PASS
9033 13:15:31.713329 Write leveling : PASS
9034 13:15:31.716417 RX DQS gating : PASS
9035 13:15:31.719906 RX DQ/DQS(RDDQC) : PASS
9036 13:15:31.719983 TX DQ/DQS : PASS
9037 13:15:31.723448 RX DATLAT : PASS
9038 13:15:31.726346 RX DQ/DQS(Engine): PASS
9039 13:15:31.726425 TX OE : PASS
9040 13:15:31.730881 All Pass.
9041 13:15:31.730959
9042 13:15:31.731035 CH 0, Rank 1
9043 13:15:31.733022 SW Impedance : PASS
9044 13:15:31.733100 DUTY Scan : NO K
9045 13:15:31.736787 ZQ Calibration : PASS
9046 13:15:31.740129 Jitter Meter : NO K
9047 13:15:31.740208 CBT Training : PASS
9048 13:15:31.743313 Write leveling : PASS
9049 13:15:31.746582 RX DQS gating : PASS
9050 13:15:31.746660 RX DQ/DQS(RDDQC) : PASS
9051 13:15:31.749675 TX DQ/DQS : PASS
9052 13:15:31.749752 RX DATLAT : PASS
9053 13:15:31.752947 RX DQ/DQS(Engine): PASS
9054 13:15:31.756514 TX OE : PASS
9055 13:15:31.756592 All Pass.
9056 13:15:31.756668
9057 13:15:31.756741 CH 1, Rank 0
9058 13:15:31.759814 SW Impedance : PASS
9059 13:15:31.763472 DUTY Scan : NO K
9060 13:15:31.763574 ZQ Calibration : PASS
9061 13:15:31.767928 Jitter Meter : NO K
9062 13:15:31.769831 CBT Training : PASS
9063 13:15:31.769906 Write leveling : PASS
9064 13:15:31.773346 RX DQS gating : PASS
9065 13:15:31.776612 RX DQ/DQS(RDDQC) : PASS
9066 13:15:31.776760 TX DQ/DQS : PASS
9067 13:15:31.780150 RX DATLAT : PASS
9068 13:15:31.782886 RX DQ/DQS(Engine): PASS
9069 13:15:31.782978 TX OE : PASS
9070 13:15:31.783064 All Pass.
9071 13:15:31.786442
9072 13:15:31.786518 CH 1, Rank 1
9073 13:15:31.789791 SW Impedance : PASS
9074 13:15:31.789866 DUTY Scan : NO K
9075 13:15:31.793133 ZQ Calibration : PASS
9076 13:15:31.793222 Jitter Meter : NO K
9077 13:15:31.796744 CBT Training : PASS
9078 13:15:31.799979 Write leveling : PASS
9079 13:15:31.800079 RX DQS gating : PASS
9080 13:15:31.803200 RX DQ/DQS(RDDQC) : PASS
9081 13:15:31.807202 TX DQ/DQS : PASS
9082 13:15:31.807296 RX DATLAT : PASS
9083 13:15:31.809779 RX DQ/DQS(Engine): PASS
9084 13:15:31.813023 TX OE : PASS
9085 13:15:31.813139 All Pass.
9086 13:15:31.813237
9087 13:15:31.816430 DramC Write-DBI on
9088 13:15:31.816517 PER_BANK_REFRESH: Hybrid Mode
9089 13:15:31.819859 TX_TRACKING: ON
9090 13:15:31.826411 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9091 13:15:31.836614 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9092 13:15:31.843145 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9093 13:15:31.846273 [FAST_K] Save calibration result to emmc
9094 13:15:31.849778 sync common calibartion params.
9095 13:15:31.853336 sync cbt_mode0:1, 1:1
9096 13:15:31.853410 dram_init: ddr_geometry: 2
9097 13:15:31.856834 dram_init: ddr_geometry: 2
9098 13:15:31.859804 dram_init: ddr_geometry: 2
9099 13:15:31.859879 0:dram_rank_size:100000000
9100 13:15:31.863480 1:dram_rank_size:100000000
9101 13:15:31.869796 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9102 13:15:31.869872 DFS_SHUFFLE_HW_MODE: ON
9103 13:15:31.876801 dramc_set_vcore_voltage set vcore to 725000
9104 13:15:31.876878 Read voltage for 1600, 0
9105 13:15:31.880310 Vio18 = 0
9106 13:15:31.880386 Vcore = 725000
9107 13:15:31.880443 Vdram = 0
9108 13:15:31.880497 Vddq = 0
9109 13:15:31.883471 Vmddr = 0
9110 13:15:31.883549 switch to 3200 Mbps bootup
9111 13:15:31.886978 [DramcRunTimeConfig]
9112 13:15:31.887067 PHYPLL
9113 13:15:31.890163 DPM_CONTROL_AFTERK: ON
9114 13:15:31.890239 PER_BANK_REFRESH: ON
9115 13:15:31.893327 REFRESH_OVERHEAD_REDUCTION: ON
9116 13:15:31.896882 CMD_PICG_NEW_MODE: OFF
9117 13:15:31.896958 XRTWTW_NEW_MODE: ON
9118 13:15:31.900125 XRTRTR_NEW_MODE: ON
9119 13:15:31.900200 TX_TRACKING: ON
9120 13:15:31.903712 RDSEL_TRACKING: OFF
9121 13:15:31.907497 DQS Precalculation for DVFS: ON
9122 13:15:31.907574 RX_TRACKING: OFF
9123 13:15:31.910310 HW_GATING DBG: ON
9124 13:15:31.910385 ZQCS_ENABLE_LP4: ON
9125 13:15:31.913378 RX_PICG_NEW_MODE: ON
9126 13:15:31.913453 TX_PICG_NEW_MODE: ON
9127 13:15:31.916888 ENABLE_RX_DCM_DPHY: ON
9128 13:15:31.919918 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9129 13:15:31.923467 DUMMY_READ_FOR_TRACKING: OFF
9130 13:15:31.927062 !!! SPM_CONTROL_AFTERK: OFF
9131 13:15:31.927145 !!! SPM could not control APHY
9132 13:15:31.930337 IMPEDANCE_TRACKING: ON
9133 13:15:31.930412 TEMP_SENSOR: ON
9134 13:15:31.933423 HW_SAVE_FOR_SR: OFF
9135 13:15:31.936726 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9136 13:15:31.940102 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9137 13:15:31.943497 Read ODT Tracking: ON
9138 13:15:31.943595 Refresh Rate DeBounce: ON
9139 13:15:31.946770 DFS_NO_QUEUE_FLUSH: ON
9140 13:15:31.950219 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9141 13:15:31.953364 ENABLE_DFS_RUNTIME_MRW: OFF
9142 13:15:31.953438 DDR_RESERVE_NEW_MODE: ON
9143 13:15:31.957160 MR_CBT_SWITCH_FREQ: ON
9144 13:15:31.960650 =========================
9145 13:15:31.977789 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9146 13:15:31.980509 dram_init: ddr_geometry: 2
9147 13:15:31.999411 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9148 13:15:32.002456 dram_init: dram init end (result: 0)
9149 13:15:32.008917 DRAM-K: Full calibration passed in 24511 msecs
9150 13:15:32.012375 MRC: failed to locate region type 0.
9151 13:15:32.012470 DRAM rank0 size:0x100000000,
9152 13:15:32.015903 DRAM rank1 size=0x100000000
9153 13:15:32.026017 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9154 13:15:32.032459 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9155 13:15:32.039333 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9156 13:15:32.045986 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9157 13:15:32.049294 DRAM rank0 size:0x100000000,
9158 13:15:32.052473 DRAM rank1 size=0x100000000
9159 13:15:32.052563 CBMEM:
9160 13:15:32.056032 IMD: root @ 0xfffff000 254 entries.
9161 13:15:32.059692 IMD: root @ 0xffffec00 62 entries.
9162 13:15:32.062603 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9163 13:15:32.066035 WARNING: RO_VPD is uninitialized or empty.
9164 13:15:32.072301 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9165 13:15:32.079524 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9166 13:15:32.091768 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9167 13:15:32.103629 BS: romstage times (exec / console): total (unknown) / 24022 ms
9168 13:15:32.103730
9169 13:15:32.103815
9170 13:15:32.113282 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9171 13:15:32.116513 ARM64: Exception handlers installed.
9172 13:15:32.120007 ARM64: Testing exception
9173 13:15:32.123182 ARM64: Done test exception
9174 13:15:32.123271 Enumerating buses...
9175 13:15:32.126582 Show all devs... Before device enumeration.
9176 13:15:32.129910 Root Device: enabled 1
9177 13:15:32.133068 CPU_CLUSTER: 0: enabled 1
9178 13:15:32.133170 CPU: 00: enabled 1
9179 13:15:32.136773 Compare with tree...
9180 13:15:32.136878 Root Device: enabled 1
9181 13:15:32.140056 CPU_CLUSTER: 0: enabled 1
9182 13:15:32.143332 CPU: 00: enabled 1
9183 13:15:32.143423 Root Device scanning...
9184 13:15:32.146799 scan_static_bus for Root Device
9185 13:15:32.150159 CPU_CLUSTER: 0 enabled
9186 13:15:32.153428 scan_static_bus for Root Device done
9187 13:15:32.156961 scan_bus: bus Root Device finished in 8 msecs
9188 13:15:32.157068 done
9189 13:15:32.164155 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9190 13:15:32.166409 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9191 13:15:32.173763 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9192 13:15:32.176856 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9193 13:15:32.180428 Allocating resources...
9194 13:15:32.180519 Reading resources...
9195 13:15:32.186598 Root Device read_resources bus 0 link: 0
9196 13:15:32.186690 DRAM rank0 size:0x100000000,
9197 13:15:32.190175 DRAM rank1 size=0x100000000
9198 13:15:32.193513 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9199 13:15:32.196602 CPU: 00 missing read_resources
9200 13:15:32.199882 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9201 13:15:32.207040 Root Device read_resources bus 0 link: 0 done
9202 13:15:32.207121 Done reading resources.
9203 13:15:32.213783 Show resources in subtree (Root Device)...After reading.
9204 13:15:32.216835 Root Device child on link 0 CPU_CLUSTER: 0
9205 13:15:32.220547 CPU_CLUSTER: 0 child on link 0 CPU: 00
9206 13:15:32.230228 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9207 13:15:32.230331 CPU: 00
9208 13:15:32.233595 Root Device assign_resources, bus 0 link: 0
9209 13:15:32.237340 CPU_CLUSTER: 0 missing set_resources
9210 13:15:32.240104 Root Device assign_resources, bus 0 link: 0 done
9211 13:15:32.243524 Done setting resources.
9212 13:15:32.250315 Show resources in subtree (Root Device)...After assigning values.
9213 13:15:32.253774 Root Device child on link 0 CPU_CLUSTER: 0
9214 13:15:32.256928 CPU_CLUSTER: 0 child on link 0 CPU: 00
9215 13:15:32.264134 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9216 13:15:32.267231 CPU: 00
9217 13:15:32.267326 Done allocating resources.
9218 13:15:32.273881 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9219 13:15:32.277562 Enabling resources...
9220 13:15:32.277660 done.
9221 13:15:32.280693 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9222 13:15:32.283961 Initializing devices...
9223 13:15:32.284059 Root Device init
9224 13:15:32.287538 init hardware done!
9225 13:15:32.291043 0x00000018: ctrlr->caps
9226 13:15:32.291121 52.000 MHz: ctrlr->f_max
9227 13:15:32.293849 0.400 MHz: ctrlr->f_min
9228 13:15:32.298431 0x40ff8080: ctrlr->voltages
9229 13:15:32.298528 sclk: 390625
9230 13:15:32.298611 Bus Width = 1
9231 13:15:32.300511 sclk: 390625
9232 13:15:32.300599 Bus Width = 1
9233 13:15:32.303861 Early init status = 3
9234 13:15:32.307527 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9235 13:15:32.311778 in-header: 03 fc 00 00 01 00 00 00
9236 13:15:32.315011 in-data: 00
9237 13:15:32.318113 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9238 13:15:32.324665 in-header: 03 fd 00 00 00 00 00 00
9239 13:15:32.327507 in-data:
9240 13:15:32.331042 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9241 13:15:32.335068 in-header: 03 fc 00 00 01 00 00 00
9242 13:15:32.338291 in-data: 00
9243 13:15:32.341364 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9244 13:15:32.347141 in-header: 03 fd 00 00 00 00 00 00
9245 13:15:32.350604 in-data:
9246 13:15:32.353776 [SSUSB] Setting up USB HOST controller...
9247 13:15:32.357311 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9248 13:15:32.360442 [SSUSB] phy power-on done.
9249 13:15:32.363779 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9250 13:15:32.370383 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9251 13:15:32.374143 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9252 13:15:32.380543 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9253 13:15:32.387646 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9254 13:15:32.393858 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9255 13:15:32.400776 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9256 13:15:32.407281 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9257 13:15:32.410437 SPM: binary array size = 0x9dc
9258 13:15:32.413686 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9259 13:15:32.420435 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9260 13:15:32.427040 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9261 13:15:32.430161 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9262 13:15:32.436802 configure_display: Starting display init
9263 13:15:32.470504 anx7625_power_on_init: Init interface.
9264 13:15:32.474050 anx7625_disable_pd_protocol: Disabled PD feature.
9265 13:15:32.477451 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9266 13:15:32.504925 anx7625_start_dp_work: Secure OCM version=00
9267 13:15:32.508211 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9268 13:15:32.523143 sp_tx_get_edid_block: EDID Block = 1
9269 13:15:32.625684 Extracted contents:
9270 13:15:32.628682 header: 00 ff ff ff ff ff ff 00
9271 13:15:32.632465 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9272 13:15:32.635427 version: 01 04
9273 13:15:32.638905 basic params: 95 1f 11 78 0a
9274 13:15:32.643217 chroma info: 76 90 94 55 54 90 27 21 50 54
9275 13:15:32.645799 established: 00 00 00
9276 13:15:32.652540 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9277 13:15:32.655166 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9278 13:15:32.662259 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9279 13:15:32.669089 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9280 13:15:32.675466 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9281 13:15:32.678742 extensions: 00
9282 13:15:32.678845 checksum: fb
9283 13:15:32.678929
9284 13:15:32.682271 Manufacturer: IVO Model 57d Serial Number 0
9285 13:15:32.685483 Made week 0 of 2020
9286 13:15:32.685581 EDID version: 1.4
9287 13:15:32.688656 Digital display
9288 13:15:32.692138 6 bits per primary color channel
9289 13:15:32.692240 DisplayPort interface
9290 13:15:32.695427 Maximum image size: 31 cm x 17 cm
9291 13:15:32.699038 Gamma: 220%
9292 13:15:32.699136 Check DPMS levels
9293 13:15:32.701900 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9294 13:15:32.706023 First detailed timing is preferred timing
9295 13:15:32.708887 Established timings supported:
9296 13:15:32.711930 Standard timings supported:
9297 13:15:32.712035 Detailed timings
9298 13:15:32.718573 Hex of detail: 383680a07038204018303c0035ae10000019
9299 13:15:32.722156 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9300 13:15:32.728672 0780 0798 07c8 0820 hborder 0
9301 13:15:32.732050 0438 043b 0447 0458 vborder 0
9302 13:15:32.732158 -hsync -vsync
9303 13:15:32.735462 Did detailed timing
9304 13:15:32.738549 Hex of detail: 000000000000000000000000000000000000
9305 13:15:32.742023 Manufacturer-specified data, tag 0
9306 13:15:32.748749 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9307 13:15:32.748853 ASCII string: InfoVision
9308 13:15:32.755615 Hex of detail: 000000fe00523134304e574635205248200a
9309 13:15:32.755718 ASCII string: R140NWF5 RH
9310 13:15:32.758686 Checksum
9311 13:15:32.758783 Checksum: 0xfb (valid)
9312 13:15:32.765537 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9313 13:15:32.768647 DSI data_rate: 832800000 bps
9314 13:15:32.772155 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9315 13:15:32.775136 anx7625_parse_edid: pixelclock(138800).
9316 13:15:32.781823 hactive(1920), hsync(48), hfp(24), hbp(88)
9317 13:15:32.785766 vactive(1080), vsync(12), vfp(3), vbp(17)
9318 13:15:32.788568 anx7625_dsi_config: config dsi.
9319 13:15:32.795136 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9320 13:15:32.807346 anx7625_dsi_config: success to config DSI
9321 13:15:32.811272 anx7625_dp_start: MIPI phy setup OK.
9322 13:15:32.814547 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9323 13:15:32.817913 mtk_ddp_mode_set invalid vrefresh 60
9324 13:15:32.821431 main_disp_path_setup
9325 13:15:32.821530 ovl_layer_smi_id_en
9326 13:15:32.823909 ovl_layer_smi_id_en
9327 13:15:32.823984 ccorr_config
9328 13:15:32.824043 aal_config
9329 13:15:32.827275 gamma_config
9330 13:15:32.827351 postmask_config
9331 13:15:32.831695 dither_config
9332 13:15:32.834392 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9333 13:15:32.840623 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9334 13:15:32.844068 Root Device init finished in 555 msecs
9335 13:15:32.847319 CPU_CLUSTER: 0 init
9336 13:15:32.854086 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9337 13:15:32.857489 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9338 13:15:32.860771 APU_MBOX 0x190000b0 = 0x10001
9339 13:15:32.863963 APU_MBOX 0x190001b0 = 0x10001
9340 13:15:32.867337 APU_MBOX 0x190005b0 = 0x10001
9341 13:15:32.870717 APU_MBOX 0x190006b0 = 0x10001
9342 13:15:32.873937 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9343 13:15:32.886769 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9344 13:15:32.898839 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9345 13:15:32.905533 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9346 13:15:32.917396 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9347 13:15:32.926410 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9348 13:15:32.929747 CPU_CLUSTER: 0 init finished in 81 msecs
9349 13:15:32.933078 Devices initialized
9350 13:15:32.936609 Show all devs... After init.
9351 13:15:32.936706 Root Device: enabled 1
9352 13:15:32.939660 CPU_CLUSTER: 0: enabled 1
9353 13:15:32.942869 CPU: 00: enabled 1
9354 13:15:32.946190 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9355 13:15:32.949563 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9356 13:15:32.953003 ELOG: NV offset 0x57f000 size 0x1000
9357 13:15:32.959675 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9358 13:15:32.966439 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9359 13:15:32.969522 ELOG: Event(17) added with size 13 at 2024-07-18 13:15:32 UTC
9360 13:15:32.973044 out: cmd=0x121: 03 db 21 01 00 00 00 00
9361 13:15:32.977359 in-header: 03 d8 00 00 2c 00 00 00
9362 13:15:32.989840 in-data: 65 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9363 13:15:32.996700 ELOG: Event(A1) added with size 10 at 2024-07-18 13:15:32 UTC
9364 13:15:33.003205 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9365 13:15:33.010516 ELOG: Event(A0) added with size 9 at 2024-07-18 13:15:32 UTC
9366 13:15:33.013105 elog_add_boot_reason: Logged dev mode boot
9367 13:15:33.016900 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9368 13:15:33.019760 Finalize devices...
9369 13:15:33.019861 Devices finalized
9370 13:15:33.026832 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9371 13:15:33.030322 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9372 13:15:33.033310 in-header: 03 07 00 00 08 00 00 00
9373 13:15:33.036663 in-data: aa e4 47 04 13 02 00 00
9374 13:15:33.040392 Chrome EC: UHEPI supported
9375 13:15:33.046620 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9376 13:15:33.049830 in-header: 03 a9 00 00 08 00 00 00
9377 13:15:33.053549 in-data: 84 60 60 08 00 00 00 00
9378 13:15:33.056924 ELOG: Event(91) added with size 10 at 2024-07-18 13:15:32 UTC
9379 13:15:33.064084 Chrome EC: clear events_b mask to 0x0000000020004000
9380 13:15:33.070246 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9381 13:15:33.073322 in-header: 03 fd 00 00 00 00 00 00
9382 13:15:33.073426 in-data:
9383 13:15:33.080102 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9384 13:15:33.083203 Writing coreboot table at 0xffe64000
9385 13:15:33.087041 0. 000000000010a000-0000000000113fff: RAMSTAGE
9386 13:15:33.089921 1. 0000000040000000-00000000400fffff: RAM
9387 13:15:33.093759 2. 0000000040100000-000000004032afff: RAMSTAGE
9388 13:15:33.096812 3. 000000004032b000-00000000545fffff: RAM
9389 13:15:33.103323 4. 0000000054600000-000000005465ffff: BL31
9390 13:15:33.106744 5. 0000000054660000-00000000ffe63fff: RAM
9391 13:15:33.110124 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9392 13:15:33.116705 7. 0000000100000000-000000023fffffff: RAM
9393 13:15:33.116805 Passing 5 GPIOs to payload:
9394 13:15:33.123306 NAME | PORT | POLARITY | VALUE
9395 13:15:33.126826 EC in RW | 0x000000aa | low | undefined
9396 13:15:33.130269 EC interrupt | 0x00000005 | low | undefined
9397 13:15:33.136848 TPM interrupt | 0x000000ab | high | undefined
9398 13:15:33.140266 SD card detect | 0x00000011 | high | undefined
9399 13:15:33.146583 speaker enable | 0x00000093 | high | undefined
9400 13:15:33.150032 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9401 13:15:33.153533 in-header: 03 f9 00 00 02 00 00 00
9402 13:15:33.153634 in-data: 02 00
9403 13:15:33.156677 ADC[4]: Raw value=900221 ID=7
9404 13:15:33.160224 ADC[3]: Raw value=212967 ID=1
9405 13:15:33.160330 RAM Code: 0x71
9406 13:15:33.163611 ADC[6]: Raw value=74557 ID=0
9407 13:15:33.166567 ADC[5]: Raw value=211860 ID=1
9408 13:15:33.166665 SKU Code: 0x1
9409 13:15:33.173225 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d4d9
9410 13:15:33.176994 coreboot table: 964 bytes.
9411 13:15:33.180147 IMD ROOT 0. 0xfffff000 0x00001000
9412 13:15:33.183484 IMD SMALL 1. 0xffffe000 0x00001000
9413 13:15:33.187401 RO MCACHE 2. 0xffffc000 0x00001104
9414 13:15:33.190013 CONSOLE 3. 0xfff7c000 0x00080000
9415 13:15:33.193259 FMAP 4. 0xfff7b000 0x00000452
9416 13:15:33.196578 TIME STAMP 5. 0xfff7a000 0x00000910
9417 13:15:33.199800 VBOOT WORK 6. 0xfff66000 0x00014000
9418 13:15:33.203019 RAMOOPS 7. 0xffe66000 0x00100000
9419 13:15:33.206643 COREBOOT 8. 0xffe64000 0x00002000
9420 13:15:33.206720 IMD small region:
9421 13:15:33.209561 IMD ROOT 0. 0xffffec00 0x00000400
9422 13:15:33.213438 VPD 1. 0xffffeb80 0x0000006c
9423 13:15:33.216693 MMC STATUS 2. 0xffffeb60 0x00000004
9424 13:15:33.223209 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9425 13:15:33.229738 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9426 13:15:33.269073 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9427 13:15:33.272175 Checking segment from ROM address 0x40100000
9428 13:15:33.275435 Checking segment from ROM address 0x4010001c
9429 13:15:33.281910 Loading segment from ROM address 0x40100000
9430 13:15:33.281998 code (compression=0)
9431 13:15:33.292122 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9432 13:15:33.298661 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9433 13:15:33.298757 it's not compressed!
9434 13:15:33.305431 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9435 13:15:33.308677 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9436 13:15:33.329323 Loading segment from ROM address 0x4010001c
9437 13:15:33.329440 Entry Point 0x80000000
9438 13:15:33.332477 Loaded segments
9439 13:15:33.336512 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9440 13:15:33.342585 Jumping to boot code at 0x80000000(0xffe64000)
9441 13:15:33.349318 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9442 13:15:33.355590 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9443 13:15:33.363413 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9444 13:15:33.367089 Checking segment from ROM address 0x40100000
9445 13:15:33.370244 Checking segment from ROM address 0x4010001c
9446 13:15:33.376737 Loading segment from ROM address 0x40100000
9447 13:15:33.376849 code (compression=1)
9448 13:15:33.383437 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9449 13:15:33.393617 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9450 13:15:33.393733 using LZMA
9451 13:15:33.401808 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9452 13:15:33.408700 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9453 13:15:33.411737 Loading segment from ROM address 0x4010001c
9454 13:15:33.411823 Entry Point 0x54601000
9455 13:15:33.415104 Loaded segments
9456 13:15:33.418166 NOTICE: MT8192 bl31_setup
9457 13:15:33.425270 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9458 13:15:33.428613 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9459 13:15:33.431967 WARNING: region 0:
9460 13:15:33.435219 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9461 13:15:33.435303 WARNING: region 1:
9462 13:15:33.441785 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9463 13:15:33.445433 WARNING: region 2:
9464 13:15:33.448652 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9465 13:15:33.451854 WARNING: region 3:
9466 13:15:33.455704 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9467 13:15:33.458766 WARNING: region 4:
9468 13:15:33.465652 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9469 13:15:33.465749 WARNING: region 5:
9470 13:15:33.468840 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 13:15:33.471784 WARNING: region 6:
9472 13:15:33.475310 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 13:15:33.478553 WARNING: region 7:
9474 13:15:33.481866 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9475 13:15:33.488920 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9476 13:15:33.492133 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9477 13:15:33.495491 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9478 13:15:33.502024 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9479 13:15:33.505279 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9480 13:15:33.508906 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9481 13:15:33.515587 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9482 13:15:33.518881 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9483 13:15:33.525121 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9484 13:15:33.528568 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9485 13:15:33.532060 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9486 13:15:33.538536 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9487 13:15:33.542127 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9488 13:15:33.545240 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9489 13:15:33.551903 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9490 13:15:33.555791 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9491 13:15:33.561940 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9492 13:15:33.565277 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9493 13:15:33.569403 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9494 13:15:33.575868 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9495 13:15:33.578784 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9496 13:15:33.581899 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9497 13:15:33.589302 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9498 13:15:33.592343 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9499 13:15:33.599097 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9500 13:15:33.602508 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9501 13:15:33.606154 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9502 13:15:33.612489 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9503 13:15:33.615469 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9504 13:15:33.618811 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9505 13:15:33.625652 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9506 13:15:33.629287 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9507 13:15:33.632130 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9508 13:15:33.639843 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9509 13:15:33.642230 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9510 13:15:33.645550 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9511 13:15:33.648744 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9512 13:15:33.655643 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9513 13:15:33.659005 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9514 13:15:33.662189 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9515 13:15:33.666234 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9516 13:15:33.672516 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9517 13:15:33.675513 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9518 13:15:33.679157 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9519 13:15:33.682244 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9520 13:15:33.688992 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9521 13:15:33.691902 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9522 13:15:33.695316 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9523 13:15:33.702551 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9524 13:15:33.705504 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9525 13:15:33.712082 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9526 13:15:33.715413 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9527 13:15:33.718634 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9528 13:15:33.725476 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9529 13:15:33.728344 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9530 13:15:33.735483 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9531 13:15:33.738828 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9532 13:15:33.745497 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9533 13:15:33.748541 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9534 13:15:33.751710 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9535 13:15:33.758639 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9536 13:15:33.761846 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9537 13:15:33.768502 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9538 13:15:33.771748 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9539 13:15:33.778684 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9540 13:15:33.781819 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9541 13:15:33.788445 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9542 13:15:33.792088 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9543 13:15:33.795208 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9544 13:15:33.802084 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9545 13:15:33.805384 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9546 13:15:33.811650 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9547 13:15:33.815162 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9548 13:15:33.818821 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9549 13:15:33.825036 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9550 13:15:33.828680 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9551 13:15:33.834928 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9552 13:15:33.838708 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9553 13:15:33.845108 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9554 13:15:33.848204 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9555 13:15:33.854818 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9556 13:15:33.858299 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9557 13:15:33.862069 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9558 13:15:33.868117 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9559 13:15:33.871370 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9560 13:15:33.878263 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9561 13:15:33.881653 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9562 13:15:33.888366 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9563 13:15:33.891714 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9564 13:15:33.895238 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9565 13:15:33.901172 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9566 13:15:33.904387 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9567 13:15:33.911515 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9568 13:15:33.914967 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9569 13:15:33.921324 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9570 13:15:33.924811 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9571 13:15:33.928120 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9572 13:15:33.934913 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9573 13:15:33.937922 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9574 13:15:33.941826 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9575 13:15:33.944785 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9576 13:15:33.952172 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9577 13:15:33.954813 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9578 13:15:33.961270 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9579 13:15:33.965067 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9580 13:15:33.968352 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9581 13:15:33.974736 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9582 13:15:33.977939 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9583 13:15:33.984695 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9584 13:15:33.988335 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9585 13:15:33.991291 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9586 13:15:33.998125 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9587 13:15:34.001701 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9588 13:15:34.007863 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9589 13:15:34.011381 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9590 13:15:34.014389 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9591 13:15:34.021727 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9592 13:15:34.024892 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9593 13:15:34.027944 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9594 13:15:34.034525 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9595 13:15:34.038154 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9596 13:15:34.040886 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9597 13:15:34.044450 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9598 13:15:34.051763 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9599 13:15:34.054516 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9600 13:15:34.057761 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9601 13:15:34.064553 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9602 13:15:34.067607 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9603 13:15:34.074822 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9604 13:15:34.077976 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9605 13:15:34.081475 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9606 13:15:34.087508 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9607 13:15:34.091168 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9608 13:15:34.094845 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9609 13:15:34.101302 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9610 13:15:34.104478 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9611 13:15:34.111205 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9612 13:15:34.114299 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9613 13:15:34.117535 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9614 13:15:34.124387 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9615 13:15:34.127443 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9616 13:15:34.134212 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9617 13:15:34.137580 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9618 13:15:34.140711 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9619 13:15:34.148122 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9620 13:15:34.151331 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9621 13:15:34.154531 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9622 13:15:34.160935 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9623 13:15:34.164583 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9624 13:15:34.170965 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9625 13:15:34.174717 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9626 13:15:34.178084 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9627 13:15:34.184183 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9628 13:15:34.187701 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9629 13:15:34.194365 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9630 13:15:34.198015 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9631 13:15:34.201227 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9632 13:15:34.207744 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9633 13:15:34.211142 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9634 13:15:34.214160 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9635 13:15:34.220967 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9636 13:15:34.224099 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9637 13:15:34.230814 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9638 13:15:34.234771 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9639 13:15:34.237348 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9640 13:15:34.244127 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9641 13:15:34.247323 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9642 13:15:34.254217 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9643 13:15:34.257913 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9644 13:15:34.261058 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9645 13:15:34.267640 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9646 13:15:34.271315 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9647 13:15:34.274554 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9648 13:15:34.280821 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9649 13:15:34.284284 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9650 13:15:34.291034 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9651 13:15:34.294877 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9652 13:15:34.297694 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9653 13:15:34.304425 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9654 13:15:34.307935 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9655 13:15:34.314420 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9656 13:15:34.317404 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9657 13:15:34.321033 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9658 13:15:34.327889 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9659 13:15:34.331003 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9660 13:15:34.337712 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9661 13:15:34.341055 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9662 13:15:34.343940 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9663 13:15:34.350931 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9664 13:15:34.354459 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9665 13:15:34.360715 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9666 13:15:34.364347 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9667 13:15:34.367458 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9668 13:15:34.374213 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9669 13:15:34.377814 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9670 13:15:34.384722 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9671 13:15:34.387339 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9672 13:15:34.390759 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9673 13:15:34.397324 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9674 13:15:34.400680 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9675 13:15:34.407072 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9676 13:15:34.410723 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9677 13:15:34.417358 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9678 13:15:34.420392 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9679 13:15:34.424420 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9680 13:15:34.430480 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9681 13:15:34.433782 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9682 13:15:34.440634 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9683 13:15:34.443946 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9684 13:15:34.447331 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9685 13:15:34.453877 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9686 13:15:34.457162 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9687 13:15:34.463499 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9688 13:15:34.466956 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9689 13:15:34.470740 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9690 13:15:34.477133 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9691 13:15:34.480615 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9692 13:15:34.486981 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9693 13:15:34.490853 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9694 13:15:34.497038 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9695 13:15:34.500695 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9696 13:15:34.504213 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9697 13:15:34.510373 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9698 13:15:34.513872 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9699 13:15:34.520347 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9700 13:15:34.523920 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9701 13:15:34.527313 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9702 13:15:34.533688 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9703 13:15:34.537069 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9704 13:15:34.540615 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9705 13:15:34.547453 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9706 13:15:34.550711 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9707 13:15:34.553664 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9708 13:15:34.557099 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9709 13:15:34.563955 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9710 13:15:34.567303 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9711 13:15:34.573737 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9712 13:15:34.576941 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9713 13:15:34.580481 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9714 13:15:34.586845 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9715 13:15:34.590337 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9716 13:15:34.593822 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9717 13:15:34.600308 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9718 13:15:34.603574 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9719 13:15:34.607182 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9720 13:15:34.613473 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9721 13:15:34.617285 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9722 13:15:34.623447 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9723 13:15:34.627058 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9724 13:15:34.630153 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9725 13:15:34.637014 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9726 13:15:34.640297 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9727 13:15:34.643639 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9728 13:15:34.650015 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9729 13:15:34.653669 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9730 13:15:34.656826 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9731 13:15:34.663465 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9732 13:15:34.666845 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9733 13:15:34.670331 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9734 13:15:34.676972 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9735 13:15:34.680092 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9736 13:15:34.687169 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9737 13:15:34.690282 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9738 13:15:34.693299 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9739 13:15:34.700243 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9740 13:15:34.703907 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9741 13:15:34.706948 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9742 13:15:34.713618 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9743 13:15:34.716719 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9744 13:15:34.720293 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9745 13:15:34.723328 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9746 13:15:34.730165 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9747 13:15:34.733916 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9748 13:15:34.736944 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9749 13:15:34.740539 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9750 13:15:34.746670 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9751 13:15:34.749951 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9752 13:15:34.753713 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9753 13:15:34.756618 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9754 13:15:34.763322 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9755 13:15:34.766759 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9756 13:15:34.770078 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9757 13:15:34.776855 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9758 13:15:34.780076 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9759 13:15:34.783211 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9760 13:15:34.790416 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9761 13:15:34.793704 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9762 13:15:34.800083 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9763 13:15:34.803490 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9764 13:15:34.806729 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9765 13:15:34.813588 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9766 13:15:34.817298 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9767 13:15:34.823932 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9768 13:15:34.827022 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9769 13:15:34.830702 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9770 13:15:34.837189 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9771 13:15:34.841051 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9772 13:15:34.843850 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9773 13:15:34.850714 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9774 13:15:34.853901 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9775 13:15:34.860735 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9776 13:15:34.864088 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9777 13:15:34.870403 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9778 13:15:34.874120 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9779 13:15:34.877273 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9780 13:15:34.883527 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9781 13:15:34.887145 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9782 13:15:34.894246 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9783 13:15:34.897384 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9784 13:15:34.900290 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9785 13:15:34.907158 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9786 13:15:34.910696 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9787 13:15:34.916922 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9788 13:15:34.920479 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9789 13:15:34.923526 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9790 13:15:34.930506 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9791 13:15:34.933841 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9792 13:15:34.940254 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9793 13:15:34.943692 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9794 13:15:34.947214 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9795 13:15:34.953818 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9796 13:15:34.956895 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9797 13:15:34.963519 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9798 13:15:34.967037 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9799 13:15:34.970246 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9800 13:15:34.976994 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9801 13:15:34.980361 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9802 13:15:34.986810 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9803 13:15:34.990625 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9804 13:15:34.993457 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9805 13:15:35.000858 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9806 13:15:35.003546 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9807 13:15:35.010651 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9808 13:15:35.013734 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9809 13:15:35.016787 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9810 13:15:35.023650 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9811 13:15:35.027052 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9812 13:15:35.033931 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9813 13:15:35.037876 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9814 13:15:35.040348 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9815 13:15:35.047343 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9816 13:15:35.050408 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9817 13:15:35.056838 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9818 13:15:35.060157 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9819 13:15:35.067043 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9820 13:15:35.070229 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9821 13:15:35.074105 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9822 13:15:35.080161 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9823 13:15:35.083957 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9824 13:15:35.087004 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9825 13:15:35.093528 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9826 13:15:35.097328 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9827 13:15:35.103598 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9828 13:15:35.106997 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9829 13:15:35.111115 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9830 13:15:35.117205 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9831 13:15:35.120674 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9832 13:15:35.127756 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9833 13:15:35.130568 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9834 13:15:35.137655 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9835 13:15:35.140577 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9836 13:15:35.143836 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9837 13:15:35.150328 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9838 13:15:35.154037 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9839 13:15:35.160433 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9840 13:15:35.163851 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9841 13:15:35.170589 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9842 13:15:35.173964 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9843 13:15:35.180350 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9844 13:15:35.183948 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9845 13:15:35.187572 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9846 13:15:35.193729 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9847 13:15:35.197363 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9848 13:15:35.203978 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9849 13:15:35.207140 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9850 13:15:35.210634 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9851 13:15:35.217305 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9852 13:15:35.220658 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9853 13:15:35.226910 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9854 13:15:35.230502 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9855 13:15:35.237447 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9856 13:15:35.240463 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9857 13:15:35.244077 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9858 13:15:35.250314 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9859 13:15:35.254178 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9860 13:15:35.260505 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9861 13:15:35.263656 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9862 13:15:35.270315 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9863 13:15:35.273860 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9864 13:15:35.277453 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9865 13:15:35.283668 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9866 13:15:35.287234 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9867 13:15:35.294144 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9868 13:15:35.297284 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9869 13:15:35.303559 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9870 13:15:35.307487 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9871 13:15:35.310321 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9872 13:15:35.317100 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9873 13:15:35.320563 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9874 13:15:35.326999 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9875 13:15:35.330429 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9876 13:15:35.337242 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9877 13:15:35.340205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9878 13:15:35.343769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9879 13:15:35.351129 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9880 13:15:35.354037 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9881 13:15:35.360557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9882 13:15:35.363781 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9883 13:15:35.370552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9884 13:15:35.374335 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9885 13:15:35.380765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9886 13:15:35.383778 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9887 13:15:35.390795 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9888 13:15:35.393724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9889 13:15:35.400703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9890 13:15:35.403900 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9891 13:15:35.407117 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9892 13:15:35.413993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9893 13:15:35.416881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9894 13:15:35.423702 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9895 13:15:35.427047 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9896 13:15:35.433531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9897 13:15:35.437381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9898 13:15:35.443632 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9899 13:15:35.447261 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9900 13:15:35.453520 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9901 13:15:35.457016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9902 13:15:35.463784 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9903 13:15:35.467401 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9904 13:15:35.473657 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9905 13:15:35.477302 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9906 13:15:35.484488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9907 13:15:35.486612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9908 13:15:35.493522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9909 13:15:35.496805 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9910 13:15:35.500052 INFO: [APUAPC] vio 0
9911 13:15:35.503544 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9912 13:15:35.510136 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9913 13:15:35.513778 INFO: [APUAPC] D0_APC_0: 0x400510
9914 13:15:35.513850 INFO: [APUAPC] D0_APC_1: 0x0
9915 13:15:35.517058 INFO: [APUAPC] D0_APC_2: 0x1540
9916 13:15:35.519998 INFO: [APUAPC] D0_APC_3: 0x0
9917 13:15:35.523688 INFO: [APUAPC] D1_APC_0: 0xffffffff
9918 13:15:35.526706 INFO: [APUAPC] D1_APC_1: 0xffffffff
9919 13:15:35.530131 INFO: [APUAPC] D1_APC_2: 0x3fffff
9920 13:15:35.533619 INFO: [APUAPC] D1_APC_3: 0x0
9921 13:15:35.536714 INFO: [APUAPC] D2_APC_0: 0xffffffff
9922 13:15:35.539906 INFO: [APUAPC] D2_APC_1: 0xffffffff
9923 13:15:35.543360 INFO: [APUAPC] D2_APC_2: 0x3fffff
9924 13:15:35.546981 INFO: [APUAPC] D2_APC_3: 0x0
9925 13:15:35.550877 INFO: [APUAPC] D3_APC_0: 0xffffffff
9926 13:15:35.553373 INFO: [APUAPC] D3_APC_1: 0xffffffff
9927 13:15:35.556717 INFO: [APUAPC] D3_APC_2: 0x3fffff
9928 13:15:35.560248 INFO: [APUAPC] D3_APC_3: 0x0
9929 13:15:35.563194 INFO: [APUAPC] D4_APC_0: 0xffffffff
9930 13:15:35.566853 INFO: [APUAPC] D4_APC_1: 0xffffffff
9931 13:15:35.569884 INFO: [APUAPC] D4_APC_2: 0x3fffff
9932 13:15:35.573832 INFO: [APUAPC] D4_APC_3: 0x0
9933 13:15:35.576585 INFO: [APUAPC] D5_APC_0: 0xffffffff
9934 13:15:35.580358 INFO: [APUAPC] D5_APC_1: 0xffffffff
9935 13:15:35.583275 INFO: [APUAPC] D5_APC_2: 0x3fffff
9936 13:15:35.586759 INFO: [APUAPC] D5_APC_3: 0x0
9937 13:15:35.590511 INFO: [APUAPC] D6_APC_0: 0xffffffff
9938 13:15:35.593586 INFO: [APUAPC] D6_APC_1: 0xffffffff
9939 13:15:35.596780 INFO: [APUAPC] D6_APC_2: 0x3fffff
9940 13:15:35.600207 INFO: [APUAPC] D6_APC_3: 0x0
9941 13:15:35.603215 INFO: [APUAPC] D7_APC_0: 0xffffffff
9942 13:15:35.606815 INFO: [APUAPC] D7_APC_1: 0xffffffff
9943 13:15:35.610074 INFO: [APUAPC] D7_APC_2: 0x3fffff
9944 13:15:35.613678 INFO: [APUAPC] D7_APC_3: 0x0
9945 13:15:35.616710 INFO: [APUAPC] D8_APC_0: 0xffffffff
9946 13:15:35.620165 INFO: [APUAPC] D8_APC_1: 0xffffffff
9947 13:15:35.623386 INFO: [APUAPC] D8_APC_2: 0x3fffff
9948 13:15:35.627062 INFO: [APUAPC] D8_APC_3: 0x0
9949 13:15:35.630468 INFO: [APUAPC] D9_APC_0: 0xffffffff
9950 13:15:35.633671 INFO: [APUAPC] D9_APC_1: 0xffffffff
9951 13:15:35.636603 INFO: [APUAPC] D9_APC_2: 0x3fffff
9952 13:15:35.636681 INFO: [APUAPC] D9_APC_3: 0x0
9953 13:15:35.640409 INFO: [APUAPC] D10_APC_0: 0xffffffff
9954 13:15:35.646948 INFO: [APUAPC] D10_APC_1: 0xffffffff
9955 13:15:35.649973 INFO: [APUAPC] D10_APC_2: 0x3fffff
9956 13:15:35.650074 INFO: [APUAPC] D10_APC_3: 0x0
9957 13:15:35.656678 INFO: [APUAPC] D11_APC_0: 0xffffffff
9958 13:15:35.660172 INFO: [APUAPC] D11_APC_1: 0xffffffff
9959 13:15:35.663322 INFO: [APUAPC] D11_APC_2: 0x3fffff
9960 13:15:35.663399 INFO: [APUAPC] D11_APC_3: 0x0
9961 13:15:35.670086 INFO: [APUAPC] D12_APC_0: 0xffffffff
9962 13:15:35.673258 INFO: [APUAPC] D12_APC_1: 0xffffffff
9963 13:15:35.676662 INFO: [APUAPC] D12_APC_2: 0x3fffff
9964 13:15:35.676740 INFO: [APUAPC] D12_APC_3: 0x0
9965 13:15:35.683140 INFO: [APUAPC] D13_APC_0: 0xffffffff
9966 13:15:35.686973 INFO: [APUAPC] D13_APC_1: 0xffffffff
9967 13:15:35.689932 INFO: [APUAPC] D13_APC_2: 0x3fffff
9968 13:15:35.690010 INFO: [APUAPC] D13_APC_3: 0x0
9969 13:15:35.697023 INFO: [APUAPC] D14_APC_0: 0xffffffff
9970 13:15:35.700135 INFO: [APUAPC] D14_APC_1: 0xffffffff
9971 13:15:35.703048 INFO: [APUAPC] D14_APC_2: 0x3fffff
9972 13:15:35.703127 INFO: [APUAPC] D14_APC_3: 0x0
9973 13:15:35.710026 INFO: [APUAPC] D15_APC_0: 0xffffffff
9974 13:15:35.712982 INFO: [APUAPC] D15_APC_1: 0xffffffff
9975 13:15:35.716546 INFO: [APUAPC] D15_APC_2: 0x3fffff
9976 13:15:35.719724 INFO: [APUAPC] D15_APC_3: 0x0
9977 13:15:35.719801 INFO: [APUAPC] APC_CON: 0x4
9978 13:15:35.723224 INFO: [NOCDAPC] D0_APC_0: 0x0
9979 13:15:35.726792 INFO: [NOCDAPC] D0_APC_1: 0x0
9980 13:15:35.730190 INFO: [NOCDAPC] D1_APC_0: 0x0
9981 13:15:35.733424 INFO: [NOCDAPC] D1_APC_1: 0xfff
9982 13:15:35.736243 INFO: [NOCDAPC] D2_APC_0: 0x0
9983 13:15:35.740274 INFO: [NOCDAPC] D2_APC_1: 0xfff
9984 13:15:35.743674 INFO: [NOCDAPC] D3_APC_0: 0x0
9985 13:15:35.746509 INFO: [NOCDAPC] D3_APC_1: 0xfff
9986 13:15:35.746581 INFO: [NOCDAPC] D4_APC_0: 0x0
9987 13:15:35.749876 INFO: [NOCDAPC] D4_APC_1: 0xfff
9988 13:15:35.753060 INFO: [NOCDAPC] D5_APC_0: 0x0
9989 13:15:35.756592 INFO: [NOCDAPC] D5_APC_1: 0xfff
9990 13:15:35.759836 INFO: [NOCDAPC] D6_APC_0: 0x0
9991 13:15:35.763222 INFO: [NOCDAPC] D6_APC_1: 0xfff
9992 13:15:35.766190 INFO: [NOCDAPC] D7_APC_0: 0x0
9993 13:15:35.769760 INFO: [NOCDAPC] D7_APC_1: 0xfff
9994 13:15:35.773914 INFO: [NOCDAPC] D8_APC_0: 0x0
9995 13:15:35.776671 INFO: [NOCDAPC] D8_APC_1: 0xfff
9996 13:15:35.779824 INFO: [NOCDAPC] D9_APC_0: 0x0
9997 13:15:35.779907 INFO: [NOCDAPC] D9_APC_1: 0xfff
9998 13:15:35.783011 INFO: [NOCDAPC] D10_APC_0: 0x0
9999 13:15:35.786487 INFO: [NOCDAPC] D10_APC_1: 0xfff
10000 13:15:35.789444 INFO: [NOCDAPC] D11_APC_0: 0x0
10001 13:15:35.793817 INFO: [NOCDAPC] D11_APC_1: 0xfff
10002 13:15:35.796581 INFO: [NOCDAPC] D12_APC_0: 0x0
10003 13:15:35.799663 INFO: [NOCDAPC] D12_APC_1: 0xfff
10004 13:15:35.803203 INFO: [NOCDAPC] D13_APC_0: 0x0
10005 13:15:35.806241 INFO: [NOCDAPC] D13_APC_1: 0xfff
10006 13:15:35.809926 INFO: [NOCDAPC] D14_APC_0: 0x0
10007 13:15:35.813151 INFO: [NOCDAPC] D14_APC_1: 0xfff
10008 13:15:35.816653 INFO: [NOCDAPC] D15_APC_0: 0x0
10009 13:15:35.819674 INFO: [NOCDAPC] D15_APC_1: 0xfff
10010 13:15:35.819755 INFO: [NOCDAPC] APC_CON: 0x4
10011 13:15:35.823322 INFO: [APUAPC] set_apusys_apc done
10012 13:15:35.826339 INFO: [DEVAPC] devapc_init done
10013 13:15:35.833163 INFO: GICv3 without legacy support detected.
10014 13:15:35.836242 INFO: ARM GICv3 driver initialized in EL3
10015 13:15:35.839614 INFO: Maximum SPI INTID supported: 639
10016 13:15:35.842793 INFO: BL31: Initializing runtime services
10017 13:15:35.849692 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10018 13:15:35.852870 INFO: SPM: enable CPC mode
10019 13:15:35.856008 INFO: mcdi ready for mcusys-off-idle and system suspend
10020 13:15:35.863208 INFO: BL31: Preparing for EL3 exit to normal world
10021 13:15:35.866470 INFO: Entry point address = 0x80000000
10022 13:15:35.866542 INFO: SPSR = 0x8
10023 13:15:35.873381
10024 13:15:35.873448
10025 13:15:35.873505
10026 13:15:35.876664 Starting depthcharge on Spherion...
10027 13:15:35.876727
10028 13:15:35.876779 Wipe memory regions:
10029 13:15:35.876830
10030 13:15:35.877489 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10031 13:15:35.877587 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10032 13:15:35.877662 Setting prompt string to ['asurada:']
10033 13:15:35.877727 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10034 13:15:35.880156 [0x00000040000000, 0x00000054600000)
10035 13:15:36.002920
10036 13:15:36.003050 [0x00000054660000, 0x00000080000000)
10037 13:15:36.262586
10038 13:15:36.262715 [0x000000821a7280, 0x000000ffe64000)
10039 13:15:37.007643
10040 13:15:37.007968 [0x00000100000000, 0x00000240000000)
10041 13:15:38.897709
10042 13:15:38.900657 Initializing XHCI USB controller at 0x11200000.
10043 13:15:39.938566
10044 13:15:39.941866 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10045 13:15:39.942385
10046 13:15:39.942726
10047 13:15:39.943454 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10048 13:15:39.943970 Sending line: 'tftpboot 192.168.201.1 14879028/tftp-deploy-kxj7s8bm/kernel/image.itb 14879028/tftp-deploy-kxj7s8bm/kernel/cmdline '
10050 13:15:40.045426 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10051 13:15:40.045844 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10052 13:15:40.050245 asurada: tftpboot 192.168.201.1 14879028/tftp-deploy-kxj7s8bm/kernel/image.ittp-deploy-kxj7s8bm/kernel/cmdline
10053 13:15:40.050686
10054 13:15:40.051075 Waiting for link
10055 13:15:40.207987
10056 13:15:40.208425 R8152: Initializing
10057 13:15:40.208819
10058 13:15:40.211469 Version 6 (ocp_data = 5c30)
10059 13:15:40.211865
10060 13:15:40.214942 R8152: Done initializing
10061 13:15:40.215492
10062 13:15:40.215838 Adding net device
10063 13:15:42.085986
10064 13:15:42.086455 done.
10065 13:15:42.086759
10066 13:15:42.087053 MAC: 00:24:32:30:78:52
10067 13:15:42.087429
10068 13:15:42.089222 Sending DHCP discover... done.
10069 13:15:42.089623
10070 13:15:42.092530 Waiting for reply... done.
10071 13:15:42.093017
10072 13:15:42.095568 Sending DHCP request... done.
10073 13:15:42.095736
10074 13:15:42.098900 Waiting for reply... done.
10075 13:15:42.099068
10076 13:15:42.099197 My ip is 192.168.201.14
10077 13:15:42.099316
10078 13:15:42.102686 The DHCP server ip is 192.168.201.1
10079 13:15:42.102856
10080 13:15:42.105782 TFTP server IP predefined by user: 192.168.201.1
10081 13:15:42.105953
10082 13:15:42.112619 Bootfile predefined by user: 14879028/tftp-deploy-kxj7s8bm/kernel/image.itb
10083 13:15:42.112787
10084 13:15:42.115929 Sending tftp read request... done.
10085 13:15:42.116167
10086 13:15:42.124252 Waiting for the transfer...
10087 13:15:42.124681
10088 13:15:42.686659 00000000 ################################################################
10089 13:15:42.686788
10090 13:15:43.203533 00080000 ################################################################
10091 13:15:43.203735
10092 13:15:43.725022 00100000 ################################################################
10093 13:15:43.725240
10094 13:15:44.257640 00180000 ################################################################
10095 13:15:44.257769
10096 13:15:44.786673 00200000 ################################################################
10097 13:15:44.786813
10098 13:15:45.338106 00280000 ################################################################
10099 13:15:45.338309
10100 13:15:45.873485 00300000 ################################################################
10101 13:15:45.873638
10102 13:15:46.442393 00380000 ################################################################
10103 13:15:46.442521
10104 13:15:47.017945 00400000 ################################################################
10105 13:15:47.018072
10106 13:15:47.570827 00480000 ################################################################
10107 13:15:47.570942
10108 13:15:48.150221 00500000 ################################################################
10109 13:15:48.150338
10110 13:15:48.732390 00580000 ################################################################
10111 13:15:48.732509
10112 13:15:49.289694 00600000 ################################################################
10113 13:15:49.289812
10114 13:15:49.823097 00680000 ################################################################
10115 13:15:49.823221
10116 13:15:50.353542 00700000 ################################################################
10117 13:15:50.353668
10118 13:15:50.892045 00780000 ################################################################
10119 13:15:50.892187
10120 13:15:51.438086 00800000 ################################################################
10121 13:15:51.438217
10122 13:15:51.979908 00880000 ################################################################
10123 13:15:51.980049
10124 13:15:52.533613 00900000 ################################################################
10125 13:15:52.533782
10126 13:15:53.062747 00980000 ################################################################
10127 13:15:53.062890
10128 13:15:53.591915 00a00000 ################################################################
10129 13:15:53.592090
10130 13:15:54.116510 00a80000 ################################################################
10131 13:15:54.116642
10132 13:15:54.644441 00b00000 ################################################################
10133 13:15:54.644591
10134 13:15:55.175094 00b80000 ################################################################
10135 13:15:55.175224
10136 13:15:55.709503 00c00000 ################################################################
10137 13:15:55.709670
10138 13:15:56.238886 00c80000 ################################################################
10139 13:15:56.239058
10140 13:15:56.763623 00d00000 ################################################################
10141 13:15:56.763765
10142 13:15:57.289295 00d80000 ################################################################
10143 13:15:57.289471
10144 13:15:57.817679 00e00000 ################################################################
10145 13:15:57.817815
10146 13:15:58.347739 00e80000 ################################################################
10147 13:15:58.347870
10148 13:15:58.870909 00f00000 ################################################################
10149 13:15:58.871071
10150 13:15:59.392126 00f80000 ################################################################
10151 13:15:59.392281
10152 13:15:59.912577 01000000 ################################################################
10153 13:15:59.912758
10154 13:16:00.439918 01080000 ################################################################
10155 13:16:00.440091
10156 13:16:00.970243 01100000 ################################################################
10157 13:16:00.970395
10158 13:16:01.503683 01180000 ################################################################
10159 13:16:01.503806
10160 13:16:02.053001 01200000 ################################################################
10161 13:16:02.053185
10162 13:16:02.589190 01280000 ################################################################
10163 13:16:02.589338
10164 13:16:03.155240 01300000 ################################################################
10165 13:16:03.155377
10166 13:16:03.710012 01380000 ################################################################
10167 13:16:03.710139
10168 13:16:04.248346 01400000 ################################################################
10169 13:16:04.248474
10170 13:16:04.821108 01480000 ################################################################
10171 13:16:04.821258
10172 13:16:05.390388 01500000 ################################################################
10173 13:16:05.390543
10174 13:16:06.001984 01580000 ################################################################
10175 13:16:06.002100
10176 13:16:06.595011 01600000 ################################################################
10177 13:16:06.595157
10178 13:16:07.171223 01680000 ################################################################
10179 13:16:07.171379
10180 13:16:07.708187 01700000 ################################################################
10181 13:16:07.708326
10182 13:16:08.251633 01780000 ################################################################
10183 13:16:08.251766
10184 13:16:08.783555 01800000 ################################################################
10185 13:16:08.783703
10186 13:16:09.315081 01880000 ################################################################
10187 13:16:09.315309
10188 13:16:09.855065 01900000 ################################################################
10189 13:16:09.855192
10190 13:16:10.400522 01980000 ################################################################
10191 13:16:10.400671
10192 13:16:10.939344 01a00000 ################################################################
10193 13:16:10.939456
10194 13:16:11.473291 01a80000 ################################################################
10195 13:16:11.473437
10196 13:16:11.995741 01b00000 ################################################################
10197 13:16:11.995858
10198 13:16:12.519060 01b80000 ################################################################
10199 13:16:12.519204
10200 13:16:13.047116 01c00000 ################################################################
10201 13:16:13.047257
10202 13:16:13.571778 01c80000 ################################################################
10203 13:16:13.571891
10204 13:16:14.100436 01d00000 ################################################################
10205 13:16:14.100552
10206 13:16:14.646816 01d80000 ################################################################
10207 13:16:14.646951
10208 13:16:15.190997 01e00000 ################################################################
10209 13:16:15.191168
10210 13:16:15.751494 01e80000 ################################################################
10211 13:16:15.751665
10212 13:16:16.289518 01f00000 ################################################################
10213 13:16:16.289637
10214 13:16:16.828626 01f80000 ################################################################
10215 13:16:16.828744
10216 13:16:17.379224 02000000 ################################################################
10217 13:16:17.379371
10218 13:16:17.916798 02080000 ################################################################
10219 13:16:17.916925
10220 13:16:18.455282 02100000 ################################################################
10221 13:16:18.455596
10222 13:16:18.989982 02180000 ################################################################
10223 13:16:18.990145
10224 13:16:19.539968 02200000 ################################################################
10225 13:16:19.540117
10226 13:16:20.076846 02280000 ################################################################
10227 13:16:20.077022
10228 13:16:20.621079 02300000 ################################################################
10229 13:16:20.621242
10230 13:16:21.159158 02380000 ################################################################
10231 13:16:21.159307
10232 13:16:21.708647 02400000 ################################################################
10233 13:16:21.708786
10234 13:16:22.243140 02480000 ################################################################
10235 13:16:22.243297
10236 13:16:22.756721 02500000 ################################################################
10237 13:16:22.756887
10238 13:16:23.273393 02580000 ################################################################
10239 13:16:23.273529
10240 13:16:23.803073 02600000 ################################################################
10241 13:16:23.803200
10242 13:16:24.341449 02680000 ################################################################
10243 13:16:24.341588
10244 13:16:24.855416 02700000 ################################################################
10245 13:16:24.855557
10246 13:16:25.370059 02780000 ################################################################
10247 13:16:25.370176
10248 13:16:25.893431 02800000 ################################################################
10249 13:16:25.893548
10250 13:16:26.437930 02880000 ################################################################
10251 13:16:26.438045
10252 13:16:26.971480 02900000 ################################################################
10253 13:16:26.971593
10254 13:16:27.510331 02980000 ################################################################
10255 13:16:27.510444
10256 13:16:28.039691 02a00000 ################################################################
10257 13:16:28.039809
10258 13:16:28.547565 02a80000 ################################################################
10259 13:16:28.547820
10260 13:16:29.078798 02b00000 ################################################################
10261 13:16:29.078912
10262 13:16:29.590568 02b80000 ################################################################
10263 13:16:29.590705
10264 13:16:30.101142 02c00000 ################################################################
10265 13:16:30.101257
10266 13:16:30.628600 02c80000 ################################################################
10267 13:16:30.628712
10268 13:16:31.140607 02d00000 ################################################################
10269 13:16:31.140744
10270 13:16:31.660513 02d80000 ################################################################
10271 13:16:31.660726
10272 13:16:32.169656 02e00000 ################################################################
10273 13:16:32.169802
10274 13:16:32.680592 02e80000 ################################################################
10275 13:16:32.680705
10276 13:16:33.190714 02f00000 ################################################################
10277 13:16:33.190826
10278 13:16:33.720696 02f80000 ################################################################
10279 13:16:33.720841
10280 13:16:34.269845 03000000 ################################################################
10281 13:16:34.269962
10282 13:16:34.797384 03080000 ################################################################
10283 13:16:34.797498
10284 13:16:35.322926 03100000 ################################################################
10285 13:16:35.323065
10286 13:16:35.849566 03180000 ################################################################
10287 13:16:35.849686
10288 13:16:36.361874 03200000 ################################################################
10289 13:16:36.361990
10290 13:16:36.878097 03280000 ################################################################
10291 13:16:36.878206
10292 13:16:37.394875 03300000 ################################################################
10293 13:16:37.394982
10294 13:16:37.915483 03380000 ################################################################
10295 13:16:37.915619
10296 13:16:38.433224 03400000 ################################################################
10297 13:16:38.433334
10298 13:16:38.946496 03480000 ################################################################
10299 13:16:38.946629
10300 13:16:39.476160 03500000 ################################################################
10301 13:16:39.476311
10302 13:16:40.011092 03580000 ################################################################
10303 13:16:40.011243
10304 13:16:40.524722 03600000 ################################################################
10305 13:16:40.524896
10306 13:16:41.048423 03680000 ################################################################
10307 13:16:41.048569
10308 13:16:41.567219 03700000 ################################################################
10309 13:16:41.567330
10310 13:16:42.107092 03780000 ################################################################
10311 13:16:42.107232
10312 13:16:42.637346 03800000 ################################################################
10313 13:16:42.637493
10314 13:16:43.152397 03880000 ################################################################
10315 13:16:43.152546
10316 13:16:43.669580 03900000 ################################################################
10317 13:16:43.669707
10318 13:16:44.193522 03980000 ################################################################
10319 13:16:44.193638
10320 13:16:44.705574 03a00000 ################################################################
10321 13:16:44.705693
10322 13:16:45.218606 03a80000 ################################################################
10323 13:16:45.218719
10324 13:16:45.746972 03b00000 ################################################################
10325 13:16:45.747088
10326 13:16:46.296125 03b80000 ################################################################
10327 13:16:46.296262
10328 13:16:46.859219 03c00000 ################################################################
10329 13:16:46.859346
10330 13:16:47.403374 03c80000 ################################################################
10331 13:16:47.403502
10332 13:16:47.940838 03d00000 ################################################################
10333 13:16:47.940970
10334 13:16:48.478557 03d80000 ################################################################
10335 13:16:48.478674
10336 13:16:49.022080 03e00000 ################################################################
10337 13:16:49.022247
10338 13:16:49.580592 03e80000 ################################################################
10339 13:16:49.580727
10340 13:16:50.211678 03f00000 ################################################################
10341 13:16:50.211799
10342 13:16:50.825774 03f80000 ################################################################
10343 13:16:50.825931
10344 13:16:51.419597 04000000 ################################################################
10345 13:16:51.419716
10346 13:16:52.059155 04080000 ################################################################
10347 13:16:52.059294
10348 13:16:52.668567 04100000 ################################################################
10349 13:16:52.668695
10350 13:16:53.307402 04180000 ################################################################
10351 13:16:53.307531
10352 13:16:53.917767 04200000 ################################################################
10353 13:16:53.917910
10354 13:16:54.572251 04280000 ################################################################
10355 13:16:54.572367
10356 13:16:55.217682 04300000 ################################################################
10357 13:16:55.217832
10358 13:16:55.766284 04380000 ################################################################
10359 13:16:55.766423
10360 13:16:56.344798 04400000 ################################################################
10361 13:16:56.344948
10362 13:16:57.008563 04480000 ################################################################
10363 13:16:57.008711
10364 13:16:57.671399 04500000 ################################################################
10365 13:16:57.671536
10366 13:16:58.330082 04580000 ################################################################
10367 13:16:58.330199
10368 13:16:59.002525 04600000 ################################################################
10369 13:16:59.002642
10370 13:16:59.299103 04680000 ############################## done.
10371 13:16:59.299230
10372 13:16:59.302599 The bootfile was 74165854 bytes long.
10373 13:16:59.302688
10374 13:16:59.306338 Sending tftp read request... done.
10375 13:16:59.306416
10376 13:16:59.306481 Waiting for the transfer...
10377 13:16:59.306564
10378 13:16:59.309504 00000000 # done.
10379 13:16:59.309578
10380 13:16:59.315877 Command line loaded dynamically from TFTP file: 14879028/tftp-deploy-kxj7s8bm/kernel/cmdline
10381 13:16:59.315971
10382 13:16:59.329447 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10383 13:16:59.329550
10384 13:16:59.332371 Loading FIT.
10385 13:16:59.332468
10386 13:16:59.336000 Image ramdisk-1 has 61002098 bytes.
10387 13:16:59.336094
10388 13:16:59.336177 Image fdt-1 has 47258 bytes.
10389 13:16:59.339411
10390 13:16:59.339556 Image kernel-1 has 13114469 bytes.
10391 13:16:59.339684
10392 13:16:59.349248 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10393 13:16:59.349336
10394 13:16:59.365848 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10395 13:16:59.365937
10396 13:16:59.372486 Choosing best match conf-1 for compat google,spherion-rev2.
10397 13:16:59.376565
10398 13:16:59.381336 Connected to device vid:did:rid of 1ae0:0028:00
10399 13:16:59.389194
10400 13:16:59.392558 tpm_get_response: command 0x17b, return code 0x0
10401 13:16:59.392653
10402 13:16:59.396091 ec_init: CrosEC protocol v3 supported (256, 248)
10403 13:16:59.399717
10404 13:16:59.403387 tpm_cleanup: add release locality here.
10405 13:16:59.403458
10406 13:16:59.403515 Shutting down all USB controllers.
10407 13:16:59.406263
10408 13:16:59.406337 Removing current net device
10409 13:16:59.406395
10410 13:16:59.413341 Exiting depthcharge with code 4 at timestamp: 112867662
10411 13:16:59.413415
10412 13:16:59.416450 LZMA decompressing kernel-1 to 0x821a6718
10413 13:16:59.416541
10414 13:16:59.419943 LZMA decompressing kernel-1 to 0x40000000
10415 13:17:01.035152
10416 13:17:01.035279 jumping to kernel
10417 13:17:01.035818 end: 2.2.4 bootloader-commands (duration 00:01:25) [common]
10418 13:17:01.035946 start: 2.2.5 auto-login-action (timeout 00:02:55) [common]
10419 13:17:01.036043 Setting prompt string to ['Linux version [0-9]']
10420 13:17:01.036135 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10421 13:17:01.036208 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10422 13:17:01.115825
10423 13:17:01.119451 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10424 13:17:01.123273 start: 2.2.5.1 login-action (timeout 00:02:55) [common]
10425 13:17:01.123392 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10426 13:17:01.123485 Setting prompt string to []
10427 13:17:01.123588 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10428 13:17:01.123697 Using line separator: #'\n'#
10429 13:17:01.123779 No login prompt set.
10430 13:17:01.123876 Parsing kernel messages
10431 13:17:01.123955 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10432 13:17:01.124118 [login-action] Waiting for messages, (timeout 00:02:55)
10433 13:17:01.124202 Waiting using forced prompt support (timeout 00:01:27)
10434 13:17:01.142631 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j272990-arm64-gcc-12-defconfig-arm64-chromebook-fgzcq) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024
10435 13:17:01.145793 [ 0.000000] random: crng init done
10436 13:17:01.149263 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10437 13:17:01.152929 [ 0.000000] efi: UEFI not found.
10438 13:17:01.162904 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10439 13:17:01.169557 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10440 13:17:01.179224 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10441 13:17:01.189676 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10442 13:17:01.196261 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10443 13:17:01.199141 [ 0.000000] printk: bootconsole [mtk8250] enabled
10444 13:17:01.207116 [ 0.000000] NUMA: No NUMA configuration found
10445 13:17:01.213562 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10446 13:17:01.220103 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10447 13:17:01.220199 [ 0.000000] Zone ranges:
10448 13:17:01.226644 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10449 13:17:01.230087 [ 0.000000] DMA32 empty
10450 13:17:01.236591 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10451 13:17:01.240361 [ 0.000000] Movable zone start for each node
10452 13:17:01.243438 [ 0.000000] Early memory node ranges
10453 13:17:01.250195 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10454 13:17:01.257026 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10455 13:17:01.263734 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10456 13:17:01.270450 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10457 13:17:01.276876 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10458 13:17:01.283400 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10459 13:17:01.340224 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10460 13:17:01.347061 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10461 13:17:01.353477 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10462 13:17:01.356733 [ 0.000000] psci: probing for conduit method from DT.
10463 13:17:01.363484 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10464 13:17:01.366913 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10465 13:17:01.373699 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10466 13:17:01.377079 [ 0.000000] psci: SMC Calling Convention v1.2
10467 13:17:01.383583 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10468 13:17:01.387003 [ 0.000000] Detected VIPT I-cache on CPU0
10469 13:17:01.393821 [ 0.000000] CPU features: detected: GIC system register CPU interface
10470 13:17:01.400224 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10471 13:17:01.407387 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10472 13:17:01.413955 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10473 13:17:01.420451 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10474 13:17:01.427091 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10475 13:17:01.433876 [ 0.000000] alternatives: applying boot alternatives
10476 13:17:01.437359 [ 0.000000] Fallback order for Node 0: 0
10477 13:17:01.443953 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10478 13:17:01.446960 [ 0.000000] Policy zone: Normal
10479 13:17:01.463786 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10480 13:17:01.473761 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10481 13:17:01.485075 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10482 13:17:01.494959 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10483 13:17:01.501313 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10484 13:17:01.504823 <6>[ 0.000000] software IO TLB: area num 8.
10485 13:17:01.561769 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10486 13:17:01.711252 <6>[ 0.000000] Memory: 7904488K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 448280K reserved, 32768K cma-reserved)
10487 13:17:01.718279 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10488 13:17:01.724819 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10489 13:17:01.727861 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10490 13:17:01.734539 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10491 13:17:01.741098 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10492 13:17:01.744657 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10493 13:17:01.754540 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10494 13:17:01.761580 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10495 13:17:01.764574 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10496 13:17:01.772158 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10497 13:17:01.775735 <6>[ 0.000000] GICv3: 608 SPIs implemented
10498 13:17:01.782114 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10499 13:17:01.785493 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10500 13:17:01.788656 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10501 13:17:01.798732 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10502 13:17:01.808844 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10503 13:17:01.822198 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10504 13:17:01.829127 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10505 13:17:01.837585 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10506 13:17:01.850903 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10507 13:17:01.858018 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10508 13:17:01.864295 <6>[ 0.009174] Console: colour dummy device 80x25
10509 13:17:01.874307 <6>[ 0.013897] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10510 13:17:01.877908 <6>[ 0.024403] pid_max: default: 32768 minimum: 301
10511 13:17:01.884484 <6>[ 0.029275] LSM: Security Framework initializing
10512 13:17:01.890843 <6>[ 0.034213] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10513 13:17:01.901383 <6>[ 0.042025] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10514 13:17:01.907831 <6>[ 0.051444] cblist_init_generic: Setting adjustable number of callback queues.
10515 13:17:01.914783 <6>[ 0.058884] cblist_init_generic: Setting shift to 3 and lim to 1.
10516 13:17:01.921358 <6>[ 0.065261] cblist_init_generic: Setting adjustable number of callback queues.
10517 13:17:01.927860 <6>[ 0.072734] cblist_init_generic: Setting shift to 3 and lim to 1.
10518 13:17:01.934108 <6>[ 0.079175] rcu: Hierarchical SRCU implementation.
10519 13:17:01.941064 <6>[ 0.084221] rcu: Max phase no-delay instances is 1000.
10520 13:17:01.947654 <6>[ 0.091276] EFI services will not be available.
10521 13:17:01.950786 <6>[ 0.096233] smp: Bringing up secondary CPUs ...
10522 13:17:01.959004 <6>[ 0.101288] Detected VIPT I-cache on CPU1
10523 13:17:01.965587 <6>[ 0.101360] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10524 13:17:01.971920 <6>[ 0.101389] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10525 13:17:01.975551 <6>[ 0.101737] Detected VIPT I-cache on CPU2
10526 13:17:01.982285 <6>[ 0.101790] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10527 13:17:01.988719 <6>[ 0.101808] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10528 13:17:01.995339 <6>[ 0.102072] Detected VIPT I-cache on CPU3
10529 13:17:02.001918 <6>[ 0.102119] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10530 13:17:02.009233 <6>[ 0.102133] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10531 13:17:02.012068 <6>[ 0.102439] CPU features: detected: Spectre-v4
10532 13:17:02.018665 <6>[ 0.102445] CPU features: detected: Spectre-BHB
10533 13:17:02.021898 <6>[ 0.102451] Detected PIPT I-cache on CPU4
10534 13:17:02.028738 <6>[ 0.102510] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10535 13:17:02.035193 <6>[ 0.102527] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10536 13:17:02.038791 <6>[ 0.102824] Detected PIPT I-cache on CPU5
10537 13:17:02.048772 <6>[ 0.102887] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10538 13:17:02.055474 <6>[ 0.102902] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10539 13:17:02.058904 <6>[ 0.103187] Detected PIPT I-cache on CPU6
10540 13:17:02.064990 <6>[ 0.103252] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10541 13:17:02.072165 <6>[ 0.103267] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10542 13:17:02.075397 <6>[ 0.103566] Detected PIPT I-cache on CPU7
10543 13:17:02.085486 <6>[ 0.103631] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10544 13:17:02.091597 <6>[ 0.103647] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10545 13:17:02.095242 <6>[ 0.103694] smp: Brought up 1 node, 8 CPUs
10546 13:17:02.098763 <6>[ 0.244907] SMP: Total of 8 processors activated.
10547 13:17:02.104927 <6>[ 0.249858] CPU features: detected: 32-bit EL0 Support
10548 13:17:02.115439 <6>[ 0.255221] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10549 13:17:02.121545 <6>[ 0.264021] CPU features: detected: Common not Private translations
10550 13:17:02.125169 <6>[ 0.270538] CPU features: detected: CRC32 instructions
10551 13:17:02.131700 <6>[ 0.275889] CPU features: detected: RCpc load-acquire (LDAPR)
10552 13:17:02.138199 <6>[ 0.281849] CPU features: detected: LSE atomic instructions
10553 13:17:02.141731 <6>[ 0.287629] CPU features: detected: Privileged Access Never
10554 13:17:02.148184 <6>[ 0.293416] CPU features: detected: RAS Extension Support
10555 13:17:02.155427 <6>[ 0.299026] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10556 13:17:02.161696 <6>[ 0.306248] CPU: All CPU(s) started at EL2
10557 13:17:02.165174 <6>[ 0.310565] alternatives: applying system-wide alternatives
10558 13:17:02.176435 <6>[ 0.321443] devtmpfs: initialized
10559 13:17:02.188596 <6>[ 0.330232] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10560 13:17:02.198577 <6>[ 0.340193] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10561 13:17:02.204908 <6>[ 0.348458] pinctrl core: initialized pinctrl subsystem
10562 13:17:02.208334 <6>[ 0.355128] DMI not present or invalid.
10563 13:17:02.215155 <6>[ 0.359536] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10564 13:17:02.225236 <6>[ 0.366351] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10565 13:17:02.231824 <6>[ 0.373938] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10566 13:17:02.241775 <6>[ 0.382171] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10567 13:17:02.244752 <6>[ 0.390408] audit: initializing netlink subsys (disabled)
10568 13:17:02.254968 <5>[ 0.396100] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10569 13:17:02.261570 <6>[ 0.396800] thermal_sys: Registered thermal governor 'step_wise'
10570 13:17:02.268376 <6>[ 0.404065] thermal_sys: Registered thermal governor 'power_allocator'
10571 13:17:02.272030 <6>[ 0.410317] cpuidle: using governor menu
10572 13:17:02.274985 <6>[ 0.421279] NET: Registered PF_QIPCRTR protocol family
10573 13:17:02.285255 <6>[ 0.426763] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10574 13:17:02.288474 <6>[ 0.433864] ASID allocator initialised with 32768 entries
10575 13:17:02.295385 <6>[ 0.440428] Serial: AMBA PL011 UART driver
10576 13:17:02.304693 <4>[ 0.449751] Trying to register duplicate clock ID: 134
10577 13:17:02.362977 <6>[ 0.511069] KASLR enabled
10578 13:17:02.377104 <6>[ 0.518725] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10579 13:17:02.383692 <6>[ 0.525737] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10580 13:17:02.390156 <6>[ 0.532224] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10581 13:17:02.397379 <6>[ 0.539231] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10582 13:17:02.403834 <6>[ 0.545717] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10583 13:17:02.410181 <6>[ 0.552721] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10584 13:17:02.416918 <6>[ 0.559205] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10585 13:17:02.423280 <6>[ 0.566207] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10586 13:17:02.426632 <6>[ 0.573733] ACPI: Interpreter disabled.
10587 13:17:02.434907 <6>[ 0.580170] iommu: Default domain type: Translated
10588 13:17:02.442163 <6>[ 0.585284] iommu: DMA domain TLB invalidation policy: strict mode
10589 13:17:02.445228 <5>[ 0.591940] SCSI subsystem initialized
10590 13:17:02.451565 <6>[ 0.596102] usbcore: registered new interface driver usbfs
10591 13:17:02.458690 <6>[ 0.601835] usbcore: registered new interface driver hub
10592 13:17:02.461573 <6>[ 0.607388] usbcore: registered new device driver usb
10593 13:17:02.468547 <6>[ 0.613494] pps_core: LinuxPPS API ver. 1 registered
10594 13:17:02.478620 <6>[ 0.618685] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10595 13:17:02.481665 <6>[ 0.628027] PTP clock support registered
10596 13:17:02.485538 <6>[ 0.632269] EDAC MC: Ver: 3.0.0
10597 13:17:02.492114 <6>[ 0.637440] FPGA manager framework
10598 13:17:02.498685 <6>[ 0.641130] Advanced Linux Sound Architecture Driver Initialized.
10599 13:17:02.502376 <6>[ 0.647916] vgaarb: loaded
10600 13:17:02.508728 <6>[ 0.651071] clocksource: Switched to clocksource arch_sys_counter
10601 13:17:02.511938 <5>[ 0.657509] VFS: Disk quotas dquot_6.6.0
10602 13:17:02.519166 <6>[ 0.661694] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10603 13:17:02.521733 <6>[ 0.668887] pnp: PnP ACPI: disabled
10604 13:17:02.530443 <6>[ 0.675604] NET: Registered PF_INET protocol family
10605 13:17:02.540511 <6>[ 0.681200] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10606 13:17:02.551819 <6>[ 0.693468] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10607 13:17:02.561930 <6>[ 0.702278] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10608 13:17:02.568173 <6>[ 0.710247] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10609 13:17:02.575160 <6>[ 0.718946] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10610 13:17:02.586801 <6>[ 0.728698] TCP: Hash tables configured (established 65536 bind 65536)
10611 13:17:02.593350 <6>[ 0.735563] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10612 13:17:02.600385 <6>[ 0.742764] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10613 13:17:02.607142 <6>[ 0.750461] NET: Registered PF_UNIX/PF_LOCAL protocol family
10614 13:17:02.613672 <6>[ 0.756620] RPC: Registered named UNIX socket transport module.
10615 13:17:02.616822 <6>[ 0.762774] RPC: Registered udp transport module.
10616 13:17:02.623473 <6>[ 0.767704] RPC: Registered tcp transport module.
10617 13:17:02.630338 <6>[ 0.772637] RPC: Registered tcp NFSv4.1 backchannel transport module.
10618 13:17:02.633494 <6>[ 0.779302] PCI: CLS 0 bytes, default 64
10619 13:17:02.636799 <6>[ 0.783633] Unpacking initramfs...
10620 13:17:02.661684 <6>[ 0.803189] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10621 13:17:02.671670 <6>[ 0.811836] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10622 13:17:02.674921 <6>[ 0.820679] kvm [1]: IPA Size Limit: 40 bits
10623 13:17:02.681815 <6>[ 0.825210] kvm [1]: GICv3: no GICV resource entry
10624 13:17:02.685224 <6>[ 0.830230] kvm [1]: disabling GICv2 emulation
10625 13:17:02.691319 <6>[ 0.834911] kvm [1]: GIC system register CPU interface enabled
10626 13:17:02.694949 <6>[ 0.841069] kvm [1]: vgic interrupt IRQ18
10627 13:17:02.701547 <6>[ 0.845426] kvm [1]: VHE mode initialized successfully
10628 13:17:02.708051 <5>[ 0.851903] Initialise system trusted keyrings
10629 13:17:02.714604 <6>[ 0.856751] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10630 13:17:02.721599 <6>[ 0.866856] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10631 13:17:02.728410 <5>[ 0.873274] NFS: Registering the id_resolver key type
10632 13:17:02.732101 <5>[ 0.878578] Key type id_resolver registered
10633 13:17:02.738612 <5>[ 0.882995] Key type id_legacy registered
10634 13:17:02.745212 <6>[ 0.887276] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10635 13:17:02.751587 <6>[ 0.894200] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10636 13:17:02.758099 <6>[ 0.901903] 9p: Installing v9fs 9p2000 file system support
10637 13:17:02.794392 <5>[ 0.939242] Key type asymmetric registered
10638 13:17:02.797548 <5>[ 0.943584] Asymmetric key parser 'x509' registered
10639 13:17:02.807721 <6>[ 0.948732] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10640 13:17:02.810702 <6>[ 0.956343] io scheduler mq-deadline registered
10641 13:17:02.813722 <6>[ 0.961120] io scheduler kyber registered
10642 13:17:02.833042 <6>[ 0.978299] EINJ: ACPI disabled.
10643 13:17:02.865399 <4>[ 1.004129] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10644 13:17:02.875670 <4>[ 1.014766] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10645 13:17:02.890543 <6>[ 1.035913] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10646 13:17:02.898816 <6>[ 1.043952] printk: console [ttyS0] disabled
10647 13:17:02.927005 <6>[ 1.068583] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10648 13:17:02.933454 <6>[ 1.078055] printk: console [ttyS0] enabled
10649 13:17:02.936969 <6>[ 1.078055] printk: console [ttyS0] enabled
10650 13:17:02.943444 <6>[ 1.086948] printk: bootconsole [mtk8250] disabled
10651 13:17:02.947133 <6>[ 1.086948] printk: bootconsole [mtk8250] disabled
10652 13:17:02.953630 <6>[ 1.098241] SuperH (H)SCI(F) driver initialized
10653 13:17:02.956717 <6>[ 1.103514] msm_serial: driver initialized
10654 13:17:02.970827 <6>[ 1.112608] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10655 13:17:02.980899 <6>[ 1.121162] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10656 13:17:02.987623 <6>[ 1.129704] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10657 13:17:02.997692 <6>[ 1.138333] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10658 13:17:03.007281 <6>[ 1.147051] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10659 13:17:03.013900 <6>[ 1.155772] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10660 13:17:03.023910 <6>[ 1.164312] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10661 13:17:03.030345 <6>[ 1.173129] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10662 13:17:03.040723 <6>[ 1.181672] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10663 13:17:03.052279 <6>[ 1.197206] loop: module loaded
10664 13:17:03.058233 <6>[ 1.203224] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10665 13:17:03.081156 <4>[ 1.226562] mtk-pmic-keys: Failed to locate of_node [id: -1]
10666 13:17:03.088127 <6>[ 1.233555] megasas: 07.719.03.00-rc1
10667 13:17:03.098251 <6>[ 1.243376] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10668 13:17:03.105536 <6>[ 1.250465] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10669 13:17:03.122172 <6>[ 1.267269] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10670 13:17:03.179117 <6>[ 1.317603] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10671 13:17:05.365326 <6>[ 3.511021] Freeing initrd memory: 59568K
10672 13:17:05.377257 <6>[ 3.522676] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10673 13:17:05.388192 <6>[ 3.533513] tun: Universal TUN/TAP device driver, 1.6
10674 13:17:05.391129 <6>[ 3.539581] thunder_xcv, ver 1.0
10675 13:17:05.395076 <6>[ 3.543088] thunder_bgx, ver 1.0
10676 13:17:05.398300 <6>[ 3.546576] nicpf, ver 1.0
10677 13:17:05.408794 <6>[ 3.550577] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10678 13:17:05.411826 <6>[ 3.558053] hns3: Copyright (c) 2017 Huawei Corporation.
10679 13:17:05.418157 <6>[ 3.563643] hclge is initializing
10680 13:17:05.421612 <6>[ 3.567223] e1000: Intel(R) PRO/1000 Network Driver
10681 13:17:05.428233 <6>[ 3.572352] e1000: Copyright (c) 1999-2006 Intel Corporation.
10682 13:17:05.431680 <6>[ 3.578365] e1000e: Intel(R) PRO/1000 Network Driver
10683 13:17:05.438653 <6>[ 3.583580] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10684 13:17:05.445081 <6>[ 3.589767] igb: Intel(R) Gigabit Ethernet Network Driver
10685 13:17:05.451711 <6>[ 3.595417] igb: Copyright (c) 2007-2014 Intel Corporation.
10686 13:17:05.458357 <6>[ 3.601252] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10687 13:17:05.464936 <6>[ 3.607770] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10688 13:17:05.468585 <6>[ 3.614251] sky2: driver version 1.30
10689 13:17:05.475203 <6>[ 3.619189] usbcore: registered new device driver r8152-cfgselector
10690 13:17:05.481898 <6>[ 3.625724] usbcore: registered new interface driver r8152
10691 13:17:05.484762 <6>[ 3.631544] VFIO - User Level meta-driver version: 0.3
10692 13:17:05.494297 <6>[ 3.639794] usbcore: registered new interface driver usb-storage
10693 13:17:05.500977 <6>[ 3.646234] usbcore: registered new device driver onboard-usb-hub
10694 13:17:05.510263 <6>[ 3.655367] mt6397-rtc mt6359-rtc: registered as rtc0
10695 13:17:05.520117 <6>[ 3.660833] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-18T13:17:05 UTC (1721308625)
10696 13:17:05.522923 <6>[ 3.670396] i2c_dev: i2c /dev entries driver
10697 13:17:05.536856 <4>[ 3.682372] cpu cpu0: supply cpu not found, using dummy regulator
10698 13:17:05.543308 <4>[ 3.688810] cpu cpu1: supply cpu not found, using dummy regulator
10699 13:17:05.550207 <4>[ 3.695212] cpu cpu2: supply cpu not found, using dummy regulator
10700 13:17:05.556835 <4>[ 3.701610] cpu cpu3: supply cpu not found, using dummy regulator
10701 13:17:05.563314 <4>[ 3.708009] cpu cpu4: supply cpu not found, using dummy regulator
10702 13:17:05.570521 <4>[ 3.714403] cpu cpu5: supply cpu not found, using dummy regulator
10703 13:17:05.576813 <4>[ 3.720820] cpu cpu6: supply cpu not found, using dummy regulator
10704 13:17:05.583385 <4>[ 3.727213] cpu cpu7: supply cpu not found, using dummy regulator
10705 13:17:05.602400 <6>[ 3.747842] cpu cpu0: EM: created perf domain
10706 13:17:05.605829 <6>[ 3.752775] cpu cpu4: EM: created perf domain
10707 13:17:05.612815 <6>[ 3.758379] sdhci: Secure Digital Host Controller Interface driver
10708 13:17:05.619551 <6>[ 3.764812] sdhci: Copyright(c) Pierre Ossman
10709 13:17:05.626307 <6>[ 3.769763] Synopsys Designware Multimedia Card Interface Driver
10710 13:17:05.632872 <6>[ 3.776404] sdhci-pltfm: SDHCI platform and OF driver helper
10711 13:17:05.636529 <6>[ 3.776466] mmc0: CQHCI version 5.10
10712 13:17:05.643194 <6>[ 3.786456] ledtrig-cpu: registered to indicate activity on CPUs
10713 13:17:05.649478 <6>[ 3.793551] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10714 13:17:05.656088 <6>[ 3.800610] usbcore: registered new interface driver usbhid
10715 13:17:05.659467 <6>[ 3.806431] usbhid: USB HID core driver
10716 13:17:05.666237 <6>[ 3.810619] spi_master spi0: will run message pump with realtime priority
10717 13:17:05.710100 <6>[ 3.849284] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10718 13:17:05.729045 <6>[ 3.864169] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10719 13:17:05.732126 <3>[ 3.875776] mtk-msdc 11f60000.mmc: phase error: [map:0]
10720 13:17:05.738769 <3>[ 3.883042] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10721 13:17:05.745350 <3>[ 3.889019] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10722 13:17:05.751997 <3>[ 3.895413] mmc0: error -5 whilst initialising MMC card
10723 13:17:05.755616 <6>[ 3.901786] cros-ec-spi spi0.0: Chrome EC device registered
10724 13:17:05.777683 <6>[ 3.920125] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10725 13:17:05.785465 <6>[ 3.930833] NET: Registered PF_PACKET protocol family
10726 13:17:05.788596 <6>[ 3.936235] 9pnet: Installing 9P2000 support
10727 13:17:05.795412 <5>[ 3.940797] Key type dns_resolver registered
10728 13:17:05.798628 <6>[ 3.945807] registered taskstats version 1
10729 13:17:05.805618 <5>[ 3.950188] Loading compiled-in X.509 certificates
10730 13:17:05.836841 <4>[ 3.975350] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10731 13:17:05.846432 <4>[ 3.986176] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10732 13:17:05.863584 <6>[ 4.008884] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15814
10733 13:17:05.869927 <6>[ 4.009801] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10734 13:17:05.876712 <6>[ 4.021292] mmc0: Command Queue Engine enabled
10735 13:17:05.880206 <6>[ 4.021795] xhci-mtk 11200000.usb: xHCI Host Controller
10736 13:17:05.886480 <6>[ 4.026005] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10737 13:17:05.893073 <6>[ 4.026494] mmcblk0: mmc0:0001 DA4128 116 GiB
10738 13:17:05.900024 <6>[ 4.031585] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10739 13:17:05.906885 <6>[ 4.041869] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10740 13:17:05.916525 <6>[ 4.043002] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10741 13:17:05.919787 <6>[ 4.051285] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10742 13:17:05.927016 <6>[ 4.056396] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10743 13:17:05.933093 <6>[ 4.066303] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10744 13:17:05.936739 <6>[ 4.071033] xhci-mtk 11200000.usb: xHCI Host Controller
10745 13:17:05.943427 <6>[ 4.077475] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10746 13:17:05.950005 <6>[ 4.082180] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10747 13:17:05.959672 <6>[ 4.082187] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10748 13:17:05.963213 <6>[ 4.109519] hub 1-0:1.0: USB hub found
10749 13:17:05.966863 <6>[ 4.113535] hub 1-0:1.0: 1 port detected
10750 13:17:05.976547 <6>[ 4.117806] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10751 13:17:05.980058 <6>[ 4.126489] hub 2-0:1.0: USB hub found
10752 13:17:05.983067 <6>[ 4.130514] hub 2-0:1.0: 1 port detected
10753 13:17:05.992481 <6>[ 4.137978] mtk-msdc 11f70000.mmc: Got CD GPIO
10754 13:17:06.004943 <6>[ 4.147255] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10755 13:17:06.015196 <6>[ 4.155646] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10756 13:17:06.021591 <6>[ 4.163986] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10757 13:17:06.031810 <6>[ 4.172326] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10758 13:17:06.038117 <6>[ 4.180664] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10759 13:17:06.048060 <6>[ 4.189003] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10760 13:17:06.055110 <6>[ 4.197344] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10761 13:17:06.064704 <6>[ 4.205683] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10762 13:17:06.071290 <6>[ 4.214022] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10763 13:17:06.081332 <6>[ 4.222359] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10764 13:17:06.087849 <6>[ 4.230699] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10765 13:17:06.097928 <6>[ 4.239047] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10766 13:17:06.104531 <6>[ 4.247385] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10767 13:17:06.114778 <6>[ 4.255725] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10768 13:17:06.121332 <6>[ 4.264063] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10769 13:17:06.127945 <6>[ 4.272783] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10770 13:17:06.134546 <6>[ 4.279933] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10771 13:17:06.141561 <6>[ 4.286737] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10772 13:17:06.151156 <6>[ 4.293497] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10773 13:17:06.158065 <6>[ 4.300477] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10774 13:17:06.164569 <6>[ 4.307325] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10775 13:17:06.174577 <6>[ 4.316460] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10776 13:17:06.184743 <6>[ 4.325584] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10777 13:17:06.194408 <6>[ 4.334878] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10778 13:17:06.204301 <6>[ 4.344346] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10779 13:17:06.210777 <6>[ 4.353815] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10780 13:17:06.220936 <6>[ 4.362937] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10781 13:17:06.230913 <6>[ 4.372404] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10782 13:17:06.240681 <6>[ 4.381523] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10783 13:17:06.250568 <6>[ 4.390818] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10784 13:17:06.260779 <6>[ 4.400982] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10785 13:17:06.270309 <6>[ 4.412270] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10786 13:17:06.393362 <6>[ 4.535351] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10787 13:17:06.547768 <6>[ 4.693455] hub 1-1:1.0: USB hub found
10788 13:17:06.551627 <6>[ 4.697993] hub 1-1:1.0: 4 ports detected
10789 13:17:06.561387 <6>[ 4.706990] hub 1-1:1.0: USB hub found
10790 13:17:06.565079 <6>[ 4.711431] hub 1-1:1.0: 4 ports detected
10791 13:17:06.673985 <6>[ 4.815571] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10792 13:17:06.700658 <6>[ 4.845493] hub 2-1:1.0: USB hub found
10793 13:17:06.703490 <6>[ 4.849999] hub 2-1:1.0: 3 ports detected
10794 13:17:06.715303 <6>[ 4.860282] hub 2-1:1.0: USB hub found
10795 13:17:06.718573 <6>[ 4.864661] hub 2-1:1.0: 3 ports detected
10796 13:17:06.884854 <6>[ 5.027387] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10797 13:17:07.017793 <6>[ 5.163218] hub 1-1.4:1.0: USB hub found
10798 13:17:07.021218 <6>[ 5.167847] hub 1-1.4:1.0: 2 ports detected
10799 13:17:07.033515 <6>[ 5.178909] hub 1-1.4:1.0: USB hub found
10800 13:17:07.036426 <6>[ 5.183507] hub 1-1.4:1.0: 2 ports detected
10801 13:17:07.097257 <6>[ 5.239601] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10802 13:17:07.206095 <6>[ 5.348052] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10803 13:17:07.241850 <4>[ 5.384157] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10804 13:17:07.251574 <4>[ 5.393247] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10805 13:17:07.291056 <6>[ 5.436866] r8152 2-1.3:1.0 eth0: v1.12.13
10806 13:17:07.344738 <6>[ 5.487263] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10807 13:17:07.537041 <6>[ 5.679343] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10808 13:17:08.942036 <6>[ 7.087687] r8152 2-1.3:1.0 eth0: carrier on
10809 13:17:08.985287 <5>[ 7.115170] Sending DHCP requests ., OK
10810 13:17:08.991848 <6>[ 7.135410] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10811 13:17:08.995545 <6>[ 7.143707] IP-Config: Complete:
10812 13:17:09.008606 <6>[ 7.147210] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10813 13:17:09.015325 <6>[ 7.157937] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10814 13:17:09.022293 <6>[ 7.166558] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10815 13:17:09.028879 <6>[ 7.166567] nameserver0=192.168.201.1
10816 13:17:09.031750 <6>[ 7.178700] clk: Disabling unused clocks
10817 13:17:09.035263 <6>[ 7.184247] ALSA device list:
10818 13:17:09.041884 <6>[ 7.187531] No soundcards found.
10819 13:17:09.049657 <6>[ 7.195323] Freeing unused kernel memory: 8512K
10820 13:17:09.053129 <6>[ 7.200232] Run /init as init process
10821 13:17:09.083508 <6>[ 7.229190] NET: Registered PF_INET6 protocol family
10822 13:17:09.090598 <6>[ 7.236270] Segment Routing with IPv6
10823 13:17:09.094052 <6>[ 7.240229] In-situ OAM (IOAM) with IPv6
10824 13:17:09.134716 <30>[ 7.253968] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10825 13:17:09.141019 <30>[ 7.287028] systemd[1]: Detected architecture arm64.
10826 13:17:09.141126
10827 13:17:09.147847 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10828 13:17:09.147957
10829 13:17:09.161495 <30>[ 7.307487] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10830 13:17:09.306098 <30>[ 7.448632] systemd[1]: Queued start job for default target graphical.target.
10831 13:17:09.358154 <30>[ 7.500649] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10832 13:17:09.364963 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10833 13:17:09.385583 <30>[ 7.528274] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10834 13:17:09.395698 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10835 13:17:09.413936 <30>[ 7.556465] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10836 13:17:09.423731 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10837 13:17:09.442240 <30>[ 7.585003] systemd[1]: Created slice user.slice - User and Session Slice.
10838 13:17:09.448774 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10839 13:17:09.473252 <30>[ 7.612283] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10840 13:17:09.482844 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10841 13:17:09.500108 <30>[ 7.639604] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10842 13:17:09.506943 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10843 13:17:09.535289 <30>[ 7.667933] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10844 13:17:09.545039 <30>[ 7.687821] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10845 13:17:09.551586 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10846 13:17:09.569020 <30>[ 7.711758] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10847 13:17:09.579260 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10848 13:17:09.597244 <30>[ 7.739868] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10849 13:17:09.607301 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10850 13:17:09.622174 <30>[ 7.767889] systemd[1]: Reached target paths.target - Path Units.
10851 13:17:09.631815 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10852 13:17:09.649237 <30>[ 7.791757] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10853 13:17:09.655527 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10854 13:17:09.669572 <30>[ 7.815350] systemd[1]: Reached target slices.target - Slice Units.
10855 13:17:09.679695 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10856 13:17:09.694165 <30>[ 7.839875] systemd[1]: Reached target swap.target - Swaps.
10857 13:17:09.700830 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10858 13:17:09.721347 <30>[ 7.863869] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10859 13:17:09.731191 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10860 13:17:09.749230 <30>[ 7.891900] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10861 13:17:09.759033 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10862 13:17:09.778222 <30>[ 7.920747] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10863 13:17:09.788070 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10864 13:17:09.805298 <30>[ 7.948006] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10865 13:17:09.815258 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10866 13:17:09.833882 <30>[ 7.976694] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10867 13:17:09.840352 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10868 13:17:09.861670 <30>[ 8.004049] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10869 13:17:09.871469 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10870 13:17:09.889493 <30>[ 8.031865] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10871 13:17:09.898993 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10872 13:17:09.957155 <30>[ 8.099643] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10873 13:17:09.963599 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10874 13:17:09.982408 <30>[ 8.125256] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10875 13:17:09.989092 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10876 13:17:10.011516 <30>[ 8.154180] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10877 13:17:10.018212 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10878 13:17:10.043591 <30>[ 8.179890] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10879 13:17:10.073647 <30>[ 8.216032] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10880 13:17:10.083219 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10881 13:17:10.106015 <30>[ 8.248637] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10882 13:17:10.112379 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10883 13:17:10.138359 <30>[ 8.280614] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10884 13:17:10.148153 Startin<6>[ 8.289996] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10885 13:17:10.154894 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10886 13:17:10.217795 <30>[ 8.360224] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10887 13:17:10.224495 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10888 13:17:10.250347 <30>[ 8.392645] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10889 13:17:10.257050 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10890 13:17:10.282144 <30>[ 8.424649] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10891 13:17:10.288871 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10892 13:17:10.333220 <30>[ 8.475757] systemd[1]: Starting systemd-journald.service - Journal Service...
10893 13:17:10.339692 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10894 13:17:10.360524 <30>[ 8.502562] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10895 13:17:10.366874 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10896 13:17:10.392366 <30>[ 8.531394] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10897 13:17:10.398786 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10898 13:17:10.419951 <30>[ 8.562328] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10899 13:17:10.429638 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10900 13:17:10.478168 <30>[ 8.620467] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10901 13:17:10.484295 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10902 13:17:10.512843 <30>[ 8.655499] systemd[1]: Started systemd-journald.service - Journal Service.
10903 13:17:10.519220 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10904 13:17:10.543312 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10905 13:17:10.565592 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10906 13:17:10.585424 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10907 13:17:10.610718 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10908 13:17:10.636000 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10909 13:17:10.660027 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10910 13:17:10.680108 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10911 13:17:10.699883 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10912 13:17:10.720250 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10913 13:17:10.742562 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10914 13:17:10.766385 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10915 13:17:10.787103 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10916 13:17:10.794205 See 'systemctl status systemd-remount-fs.service' for details.
10917 13:17:10.803860 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10918 13:17:10.823584 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10919 13:17:10.868922 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10920 13:17:10.887624 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10921 13:17:10.902765 <46>[ 9.045219] systemd-journald[195]: Received client request to flush runtime journal.
10922 13:17:10.914482 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10923 13:17:10.941154 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10924 13:17:10.965148 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10925 13:17:10.990776 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10926 13:17:11.014061 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10927 13:17:11.037842 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10928 13:17:11.058191 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10929 13:17:11.078237 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10930 13:17:11.133806 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10931 13:17:11.159357 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10932 13:17:11.177011 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10933 13:17:11.196775 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10934 13:17:11.245020 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10935 13:17:11.265920 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10936 13:17:11.289066 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10937 13:17:11.333894 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10938 13:17:11.358553 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10939 13:17:11.381906 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10940 13:17:11.433467 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10941 13:17:11.458553 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10942 13:17:11.490545 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10943 13:17:11.591819 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10944 13:17:11.610687 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10945 13:17:11.629325 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10946 13:17:11.650048 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10947 13:17:11.673574 [[0;32m OK [<3>[ 9.817002] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10948 13:17:11.683269 0m] Reached targ<3>[ 9.826037] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10949 13:17:11.693292 et [0;1;39mtime<3>[ 9.835240] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10950 13:17:11.696327 rs.target[0m - Timer Units.
10951 13:17:11.702848 <3>[ 9.847338] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10952 13:17:11.713050 <6>[ 9.855476] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10953 13:17:11.720129 <6>[ 9.856532] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10954 13:17:11.726726 <6>[ 9.860414] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10955 13:17:11.736743 <6>[ 9.860420] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10956 13:17:11.746540 <4>[ 9.860574] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10957 13:17:11.753300 <6>[ 9.861210] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10958 13:17:11.760048 <6>[ 9.861214] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10959 13:17:11.769890 <3>[ 9.863588] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10960 13:17:11.776360 <3>[ 9.863594] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10961 13:17:11.786622 <3>[ 9.863607] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10962 13:17:11.793128 <3>[ 9.863612] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10963 13:17:11.800224 <6>[ 9.873711] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10964 13:17:11.809770 <6>[ 9.879748] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10965 13:17:11.816327 <6>[ 9.887795] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10966 13:17:11.826279 <3>[ 9.892605] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10967 13:17:11.833332 <6>[ 9.896600] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10968 13:17:11.843018 <6>[ 9.904504] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10969 13:17:11.853224 <6>[ 9.904513] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10970 13:17:11.859468 <3>[ 9.907152] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10971 13:17:11.866384 <6>[ 9.946953] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10972 13:17:11.876190 <3>[ 9.952900] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10973 13:17:11.880055 <6>[ 9.976156] remoteproc remoteproc0: scp is available
10974 13:17:11.889365 <3>[ 9.977299] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10975 13:17:11.893168 <6>[ 9.979360] mc: Linux media interface: v0.10
10976 13:17:11.899353 <6>[ 9.986076] remoteproc remoteproc0: powering up scp
10977 13:17:11.905796 <6>[ 9.995290] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10978 13:17:11.912411 <6>[ 10.002995] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10979 13:17:11.922536 <3>[ 10.006470] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10980 13:17:11.929485 <3>[ 10.006497] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10981 13:17:11.939629 <3>[ 10.006502] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10982 13:17:11.946271 <3>[ 10.006507] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10983 13:17:11.955877 <3>[ 10.006511] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10984 13:17:11.962262 <4>[ 10.006785] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10985 13:17:11.969215 <4>[ 10.010520] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10986 13:17:11.978849 <3>[ 10.021879] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10987 13:17:11.982754 <6>[ 10.026476] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10988 13:17:11.989798 <6>[ 10.038087] videodev: Linux video capture interface: v2.00
10989 13:17:11.996488 <6>[ 10.039323] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10990 13:17:12.003171 <6>[ 10.039331] pci_bus 0000:00: root bus resource [bus 00-ff]
10991 13:17:12.009536 <6>[ 10.039342] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10992 13:17:12.019856 <6>[ 10.039345] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10993 13:17:12.026384 <6>[ 10.039382] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10994 13:17:12.032772 <6>[ 10.039397] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10995 13:17:12.036370 <6>[ 10.039475] pci 0000:00:00.0: supports D1 D2
10996 13:17:12.042776 <6>[ 10.039477] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10997 13:17:12.052899 <4>[ 10.047598] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10998 13:17:12.056551 <4>[ 10.047598] Fallback method does not support PEC.
10999 13:17:12.066138 <6>[ 10.120388] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11000 13:17:12.076209 <3>[ 10.137363] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11001 13:17:12.086345 <6>[ 10.145496] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11002 13:17:12.092718 <6>[ 10.160999] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11003 13:17:12.099630 <6>[ 10.161063] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11004 13:17:12.106260 <6>[ 10.161073] remoteproc remoteproc0: remote processor scp is now up
11005 13:17:12.112875 <6>[ 10.170299] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11006 13:17:12.122490 <6>[ 10.184731] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11007 13:17:12.129528 <6>[ 10.188194] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11008 13:17:12.139245 <6>[ 10.195779] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11009 13:17:12.146030 <6>[ 10.208679] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11010 13:17:12.155855 <6>[ 10.259377] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11011 13:17:12.162662 <6>[ 10.264258] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11012 13:17:12.165652 <6>[ 10.269174] Bluetooth: Core ver 2.22
11013 13:17:12.172105 <6>[ 10.269247] NET: Registered PF_BLUETOOTH protocol family
11014 13:17:12.179312 <6>[ 10.269249] Bluetooth: HCI device and connection manager initialized
11015 13:17:12.182204 <6>[ 10.269265] Bluetooth: HCI socket layer initialized
11016 13:17:12.188784 <6>[ 10.269269] Bluetooth: L2CAP socket layer initialized
11017 13:17:12.192364 <6>[ 10.269279] Bluetooth: SCO socket layer initialized
11018 13:17:12.202146 <6>[ 10.276878] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11019 13:17:12.205558 <6>[ 10.281081] pci 0000:01:00.0: supports D1 D2
11020 13:17:12.212288 <6>[ 10.314395] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11021 13:17:12.219160 <6>[ 10.317093] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11022 13:17:12.225592 <6>[ 10.318046] usbcore: registered new interface driver btusb
11023 13:17:12.235556 <4>[ 10.318542] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11024 13:17:12.242226 <3>[ 10.318552] Bluetooth: hci0: Failed to load firmware file (-2)
11025 13:17:12.248888 <3>[ 10.318555] Bluetooth: hci0: Failed to set up firmware (-2)
11026 13:17:12.258996 <4>[ 10.318559] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11027 13:17:12.265498 <6>[ 10.323598] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11028 13:17:12.278413 <6>[ 10.324382] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11029 13:17:12.285042 <6>[ 10.324478] usbcore: registered new interface driver uvcvideo
11030 13:17:12.292284 <6>[ 10.327140] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11031 13:17:12.298775 <6>[ 10.327204] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11032 13:17:12.305415 <6>[ 10.327209] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11033 13:17:12.315363 <6>[ 10.327223] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11034 13:17:12.321836 <6>[ 10.327237] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11035 13:17:12.332018 <6>[ 10.327253] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11036 13:17:12.335487 <6>[ 10.327266] pci 0000:00:00.0: PCI bridge to [bus 01]
11037 13:17:12.345278 <6>[ 10.327271] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11038 13:17:12.352444 [[0;32m OK [<6>[ 10.495688] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11039 13:17:12.359700 0m] Listening on<6>[ 10.504445] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11040 13:17:12.369736 [0;1;39mdbus.s<3>[ 10.507633] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11041 13:17:12.376437 <3>[ 10.508474] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11042 13:17:12.386031 ocket[…- D-Bu<6>[ 10.511315] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11043 13:17:12.386109 s System Message Bus Socket.
11044 13:17:12.398783 <3>[ 10.541604] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11045 13:17:12.405386 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11046 13:17:12.415580 <5>[ 10.557298] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11047 13:17:12.415678
11048 13:17:12.434720 [[0;32m OK [0m] Reached target [0;1;39mbasi<5>[ 10.579642] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11049 13:17:12.437985 c.target[0m - Basic System.
11050 13:17:12.448069 <5>[ 10.588688] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11051 13:17:12.457545 <4>[ 10.598491] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11052 13:17:12.460847 <6>[ 10.607451] cfg80211: failed to load regulatory.db
11053 13:17:12.470771 <3>[ 10.612598] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11054 13:17:12.486761 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11055 13:17:12.515446 <3>[ 10.658646] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11056 13:17:12.527544 <6>[ 10.670171] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11057 13:17:12.533571 <6>[ 10.677720] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11058 13:17:12.540796 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11059 13:17:12.550937 <3>[ 10.693407] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11060 13:17:12.558357 <6>[ 10.704409] mt7921e 0000:01:00.0: ASIC revision: 79610010
11061 13:17:12.571491 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11062 13:17:12.581709 <3>[ 10.724484] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11063 13:17:12.591918 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11064 13:17:12.612401 <3>[ 10.754920] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11065 13:17:12.621884 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11066 13:17:12.643969 <3>[ 10.786674] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11067 13:17:12.661112 <6>[ 10.804242] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11068 13:17:12.664492 <6>[ 10.804242]
11069 13:17:12.671794 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11070 13:17:12.690575 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11071 13:17:12.708563 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11072 13:17:12.725440 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11073 13:17:12.787330 [[0;32m OK [<46>[ 10.917348] systemd-journald[195]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.0 (1536 of 2047 items, 524288 file size, 341 bytes per hash table item), suggesting rotation.
11074 13:17:12.803899 0m] Started [0;<46>[ 10.939766] systemd-journald[195]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11075 13:17:12.807337 1;39mgetty@tty1.service[0m - Getty on tty1.
11076 13:17:12.846488 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11077 13:17:12.865813 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11078 13:17:12.880987 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11079 13:17:12.900876 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11080 13:17:12.929894 <6>[ 11.073026] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11081 13:17:12.954030 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11082 13:17:12.978049 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11083 13:17:13.006932 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11084 13:17:13.066832 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11085 13:17:13.086981 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11086 13:17:13.111075 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11087 13:17:13.173773
11088 13:17:13.177067 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11089 13:17:13.177187
11090 13:17:13.180537 debian-bookworm-arm64 login: root (automatic login)
11091 13:17:13.180613
11092 13:17:13.197177 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024 aarch64
11093 13:17:13.197255
11094 13:17:13.204009 The programs included with the Debian GNU/Linux system are free software;
11095 13:17:13.210519 the exact distribution terms for each program are described in the
11096 13:17:13.213732 individual files in /usr/share/doc/*/copyright.
11097 13:17:13.213808
11098 13:17:13.220161 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11099 13:17:13.223671 permitted by applicable law.
11100 13:17:13.224037 Matched prompt #10: / #
11102 13:17:13.224224 Setting prompt string to ['/ #']
11103 13:17:13.224308 end: 2.2.5.1 login-action (duration 00:00:12) [common]
11105 13:17:13.224483 end: 2.2.5 auto-login-action (duration 00:00:12) [common]
11106 13:17:13.224563 start: 2.2.6 expect-shell-connection (timeout 00:02:42) [common]
11107 13:17:13.224622 Setting prompt string to ['/ #']
11108 13:17:13.224674 Forcing a shell prompt, looking for ['/ #']
11109 13:17:13.224728 Sending line: ''
11111 13:17:13.275058 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11112 13:17:13.275136 Waiting using forced prompt support (timeout 00:02:30)
11113 13:17:13.280443 / #
11114 13:17:13.280711 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11115 13:17:13.280799 start: 2.2.7 export-device-env (timeout 00:02:42) [common]
11116 13:17:13.280886 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11117 13:17:13.280965 end: 2.2 depthcharge-retry (duration 00:02:18) [common]
11118 13:17:13.281044 end: 2 depthcharge-action (duration 00:02:18) [common]
11119 13:17:13.281149 start: 3 lava-test-retry (timeout 00:07:18) [common]
11120 13:17:13.281277 start: 3.1 lava-test-shell (timeout 00:07:18) [common]
11121 13:17:13.281346 Using namespace: common
11122 13:17:13.281427 Sending line: '#'
11124 13:17:13.381840 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11125 13:17:13.386789 / # #
11126 13:17:13.387042 Using /lava-14879028
11127 13:17:13.387105 Sending line: 'export SHELL=/bin/sh'
11129 13:17:13.492485 / # export SHELL=/bin/sh
11130 13:17:13.492730 Sending line: '. /lava-14879028/environment'
11132 13:17:13.597975 / # . /lava-14879028/environment
11133 13:17:13.598236 Sending line: '/lava-14879028/bin/lava-test-runner /lava-14879028/0'
11135 13:17:13.698669 Test shell timeout: 10s (minimum of the action and connection timeout)
11136 13:17:13.703612 / # /lava-14879028/bin/lava-test-runner /lava-14879028/0
11137 13:17:13.729705 + export TESTRUN_ID=0_igt-gpu-panf<8>[ 11.875328] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 14879028_1.5.2.3.1>
11138 13:17:13.729963 Received signal: <STARTRUN> 0_igt-gpu-panfrost 14879028_1.5.2.3.1
11139 13:17:13.730033 Starting test lava.0_igt-gpu-panfrost (14879028_1.5.2.3.1)
11140 13:17:13.730106 Skipping test definition patterns.
11141 13:17:13.732762 rost
11142 13:17:13.736384 + cd /lava-14879028/0/tests/0_igt-gpu-panfrost
11143 13:17:13.736461 + cat uuid
11144 13:17:13.739698 + UUID=14879028_1.5.2.3.1
11145 13:17:13.739777 + set +x
11146 13:17:13.749727 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11147 13:17:13.756147 <8>[ 11.902053] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11148 13:17:13.756427 Received signal: <TESTSET> START panfrost_gem_new
11149 13:17:13.756523 Starting test_set panfrost_gem_new
11150 13:17:13.788276 <14>[ 11.934843] [IGT] panfrost_gem_new: executing
11151 13:17:13.798240 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 11.943485] [IGT] panfrost_gem_new: exiting, ret=77
11152 13:17:13.805148 <6>[ 11.947097] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11153 13:17:13.805235 .96-cip24 aarch64)
11154 13:17:13.808485 Using IGT_SRANDOM=1721308633 for randomisation
11155 13:17:13.818596 Test require<8>[ 11.960472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11156 13:17:13.818849 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11158 13:17:13.824795 ment not met in function drm_open_driver, file ../lib/drmtest.c:694:
11159 13:17:13.824896 Test requirement: !(fd<0)
11160 13:17:13.831998 No known gpu found for chipset flags 0x32 (panfrost)
11161 13:17:13.834736 Last errn<14>[ 11.982617] [IGT] panfrost_gem_new: executing
11162 13:17:13.838382 o: 2, No such file or directory
11163 13:17:13.844812 <14>[ 11.989722] [IGT] panfrost_gem_new: exiting, ret=77
11164 13:17:13.844888
11165 13:17:13.848215 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
11166 13:17:13.854852 IGT-Version: 1.28-<8>[ 11.999852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11167 13:17:13.855112 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11169 13:17:13.861865 ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11170 13:17:13.864834 Using IGT_SRANDOM=1721308633 for randomisation
11171 13:17:13.871601 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11172 13:17:13.878029 Test require<14>[ 12.024258] [IGT] panfrost_gem_new: executing
11173 13:17:13.878106 ment: !(fd<0)
11174 13:17:13.884727 No known gpu foun<14>[ 12.031879] [IGT] panfrost_gem_new: exiting, ret=77
11175 13:17:13.888228 d for chipset flags 0x32 (panfrost)
11176 13:17:13.891538 Last errno: 2, No such file or directory
11177 13:17:13.894821 [1mSubtest gem-new-0: SKIP (0.000s)[0m
11178 13:17:13.901765 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11179 13:17:13.908055 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11181 13:17:13.911279 Usi<8>[ 12.053857] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11182 13:17:13.918620 ng IGT_SRANDOM=1721308633 for ra<8>[ 12.062748] <LAVA_SIGNAL_TESTSET STOP>
11183 13:17:13.918719 ndomisation
11184 13:17:13.918974 Received signal: <TESTSET> STOP
11185 13:17:13.919066 Closing test_set panfrost_gem_new
11186 13:17:13.924945 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11187 13:17:13.928493 Test requirement: !(fd<0)
11188 13:17:13.931617 No known gpu found for chipset flags 0x32 (panfrost)
11189 13:17:13.938266 Last errno: 2, N<8>[ 12.084497] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11190 13:17:13.938542 Received signal: <TESTSET> START panfrost_get_param
11191 13:17:13.938634 Starting test_set panfrost_get_param
11192 13:17:13.941544 o such file or directory
11193 13:17:13.944763 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11194 13:17:13.958049 <14>[ 12.104197] [IGT] panfrost_get_param: executing
11195 13:17:13.964404 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 12.111312] [IGT] panfrost_get_param: exiting, ret=77
11196 13:17:13.968074 h64) (Linux: 6.1.96-cip24 aarch64)
11197 13:17:13.978194 Using IGT_SRANDOM=1721308633<8>[ 12.122209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11198 13:17:13.978477 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11200 13:17:13.981433 for randomisation
11201 13:17:13.987997 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11202 13:17:13.991105 Test requirement: !(fd<0)
11203 13:17:13.997703 No known gpu found for chipset <14>[ 12.143623] [IGT] panfrost_get_param: executing
11204 13:17:13.997807 flags 0x32 (panfrost)
11205 13:17:14.004671 Last errn<14>[ 12.150900] [IGT] panfrost_get_param: exiting, ret=77
11206 13:17:14.007619 o: 2, No such file or directory
11207 13:17:14.017839 [1mSubtest base-params: SKIP (<8>[ 12.161841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11208 13:17:14.017938 0.000s)[0m
11209 13:17:14.018196 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11211 13:17:14.024527 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11212 13:17:14.030890 Using IGT_SRANDOM=1721308633 for randomisation
11213 13:17:14.037999 Test requirement not met in fun<14>[ 12.183273] [IGT] panfrost_get_param: executing
11214 13:17:14.044560 ction drm_open_driver, file ../l<14>[ 12.191033] [IGT] panfrost_get_param: exiting, ret=77
11215 13:17:14.047488 ib/drmtest.c:694:
11216 13:17:14.047583 Test requirement: !(fd<0)
11217 13:17:14.057710 No known gpu found<8>[ 12.201451] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11218 13:17:14.057975 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11220 13:17:14.064176 for chipset flags 0x32 (panfros<8>[ 12.211242] <LAVA_SIGNAL_TESTSET STOP>
11221 13:17:14.064267 t)
11222 13:17:14.064516 Received signal: <TESTSET> STOP
11223 13:17:14.064603 Closing test_set panfrost_get_param
11224 13:17:14.067439 Last errno: 2, No such file or directory
11225 13:17:14.074215 [1mSubtest get-bad-param: SKIP (0.000s)[0m
11226 13:17:14.077621 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11227 13:17:14.087225 Using IGT_SRANDOM=1721308634 for<8>[ 12.232994] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11228 13:17:14.087325 randomisation
11229 13:17:14.087585 Received signal: <TESTSET> START panfrost_prime
11230 13:17:14.087675 Starting test_set panfrost_prime
11231 13:17:14.094273 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11232 13:17:14.097132 Test requirement: !(fd<0)
11233 13:17:14.103773 No known gpu found for chipset flag<14>[ 12.251434] [IGT] panfrost_prime: executing
11234 13:17:14.107312 s 0x32 (panfrost)
11235 13:17:14.114063 Last errno: 2<14>[ 12.259426] [IGT] panfrost_prime: exiting, ret=77
11236 13:17:14.117501 , No such file or directory
11237 13:17:14.127114 [1mSubtest get-bad-padding: SKIP (<8>[ 12.269519] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11238 13:17:14.127213 0.000s)[0m
11239 13:17:14.127474 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11241 13:17:14.133825 IGT-Version: 1.28-g<8>[ 12.279344] <LAVA_SIGNAL_TESTSET STOP>
11242 13:17:14.134102 Received signal: <TESTSET> STOP
11243 13:17:14.134194 Closing test_set panfrost_prime
11244 13:17:14.137099 a44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11245 13:17:14.140352 Using IGT_SRANDOM=1721308634 for randomisation
11246 13:17:14.147456 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11247 13:17:14.153560 Test requirem<8>[ 12.301094] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11248 13:17:14.153823 Received signal: <TESTSET> START panfrost_submit
11249 13:17:14.153911 Starting test_set panfrost_submit
11250 13:17:14.157098 ent: !(fd<0)
11251 13:17:14.160654 No known gpu found for chipset flags 0x32 (panfrost)
11252 13:17:14.163963 Last errno: 2, No such file or directory
11253 13:17:14.170704 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11254 13:17:14.173721 <14>[ 12.320940] [IGT] panfrost_submit: executing
11255 13:17:14.183932 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 12.327962] [IGT] panfrost_submit: exiting, ret=77
11256 13:17:14.187327 h64) (Linux: 6.1.96-cip24 aarch64)
11257 13:17:14.193922 Using IGT_SRANDOM=1721308634<8>[ 12.338241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11258 13:17:14.194194 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11260 13:17:14.196993 for randomisation
11261 13:17:14.203579 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11262 13:17:14.206859 Test requirement: !(fd<0)
11263 13:17:14.213821 No known gpu found for chipset <14>[ 12.359053] [IGT] panfrost_submit: executing
11264 13:17:14.213916 flags 0x32 (panfrost)
11265 13:17:14.220407 Last errn<14>[ 12.366927] [IGT] panfrost_submit: exiting, ret=77
11266 13:17:14.223444 o: 2, No such file or directory
11267 13:17:14.233535 [1mSubtest pan-submit: SKIP (0<8>[ 12.377554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11268 13:17:14.233782 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11270 13:17:14.236987 .000s)[0m
11271 13:17:14.239957 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11272 13:17:14.246838 Using IGT_SRANDOM=1721308634 for randomisation
11273 13:17:14.253603 Test requirement not met in func<14>[ 12.399906] [IGT] panfrost_submit: executing
11274 13:17:14.259766 tion drm_open_driver, file ../li<14>[ 12.406856] [IGT] panfrost_submit: exiting, ret=77
11275 13:17:14.263293 b/drmtest.c:694:
11276 13:17:14.266334 Test requirement: !(fd<0)
11277 13:17:14.276220 No known gpu found for chipset flags 0x32 (panfrost<8>[ 12.419656] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11278 13:17:14.276494 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11280 13:17:14.279781 )
11281 13:17:14.282852 Last errno: 2, No such file or directory
11282 13:17:14.286361 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
11283 13:17:14.292873 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11284 13:17:14.296138 Using IGT_SRANDOM=1721308634 for randomisation
11285 13:17:14.306991 Test requirement not met in function drm_open_driver, file ../lib/drmtes<14>[ 12.453111] [IGT] panfrost_submit: executing
11286 13:17:14.309889 t.c:694:
11287 13:17:14.309967 Test requirement: !(fd<0)
11288 13:17:14.319434 No known gpu found for chip<14>[ 12.463321] [IGT] panfrost_submit: exiting, ret=77
11289 13:17:14.319515 set flags 0x32 (panfrost)
11290 13:17:14.323075 Last errno: 2, No such file or directory
11291 13:17:14.333315 [1mSubtest<8>[ 12.475755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11292 13:17:14.333560 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11294 13:17:14.339663 pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11295 13:17:14.343267 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11296 13:17:14.352730 Using IGT_SRANDOM=1721308634 for randomis<14>[ 12.499354] [IGT] panfrost_submit: executing
11297 13:17:14.352807 ation
11298 13:17:14.359425 Test requirement not met <14>[ 12.506198] [IGT] panfrost_submit: exiting, ret=77
11299 13:17:14.366048 in function drm_open_driver, file ../lib/drmtest.c:694:
11300 13:17:14.376201 Test re<8>[ 12.517052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11301 13:17:14.376279 quirement: !(fd<0)
11302 13:17:14.376506 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11304 13:17:14.383038 No known gpu found for chipset flags 0x32 (panfrost)
11305 13:17:14.386190 Last errno: 2, No such file or directory
11306 13:17:14.392716 [1mSubtest pan-submit-error-bad-bo-handles:<14>[ 12.539766] [IGT] panfrost_submit: executing
11307 13:17:14.396397 SKIP (0.000s)[0m
11308 13:17:14.402773 IGT-Version:<14>[ 12.547178] [IGT] panfrost_submit: exiting, ret=77
11309 13:17:14.406181 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11310 13:17:14.416065 Using IG<8>[ 12.557847] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11311 13:17:14.416308 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11313 13:17:14.419528 T_SRANDOM=1721308634 for randomisation
11314 13:17:14.425901 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11315 13:17:14.429602 Test requirement: !(fd<0)
11316 13:17:14.432478 No known gp<14>[ 12.580936] [IGT] panfrost_submit: executing
11317 13:17:14.442586 u found for chipset flags 0x32 (<14>[ 12.588124] [IGT] panfrost_submit: exiting, ret=77
11318 13:17:14.442662 panfrost)
11319 13:17:14.446013 Last errno: 2, No such file or directory
11320 13:17:14.456045 [1mSubtest<8>[ 12.598038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11321 13:17:14.456311 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11323 13:17:14.459163 pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11324 13:17:14.465737 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11325 13:17:14.472206 Using IGT_SRANDOM=1721308634 for rand<14>[ 12.619552] [IGT] panfrost_submit: executing
11326 13:17:14.475720 omisation
11327 13:17:14.482431 Test requirement not <14>[ 12.626815] [IGT] panfrost_submit: exiting, ret=77
11328 13:17:14.485508 met in function drm_open_driver, file ../lib/drmtest.c:694:
11329 13:17:14.495361 Tes<8>[ 12.637187] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11330 13:17:14.495458 t requirement: !(fd<0)
11331 13:17:14.495729 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11333 13:17:14.502117 No known gpu found for chipset flags 0x32 (panfrost)
11334 13:17:14.505652 Last errno: 2, No such file or directory
11335 13:17:14.512052 [1mSubtest pan-submit-error-bad-out-syn<14>[ 12.659182] [IGT] panfrost_submit: executing
11336 13:17:14.515772 c: SKIP (0.000s)[0m
11337 13:17:14.522042 IGT-Versio<14>[ 12.666534] [IGT] panfrost_submit: exiting, ret=77
11338 13:17:14.525174 n: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11339 13:17:14.535274 Using <8>[ 12.677155] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11340 13:17:14.535541 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11342 13:17:14.541675 IGT_SRANDOM=1721308634 for rando<8>[ 12.687518] <LAVA_SIGNAL_TESTSET STOP>
11343 13:17:14.541760 misation
11344 13:17:14.541995 Received signal: <TESTSET> STOP
11345 13:17:14.542058 Closing test_set panfrost_submit
11346 13:17:14.548656 Test r<8>[ 12.693782] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 14879028_1.5.2.3.1>
11347 13:17:14.548898 Received signal: <ENDRUN> 0_igt-gpu-panfrost 14879028_1.5.2.3.1
11348 13:17:14.549026 Ending use of test pattern.
11349 13:17:14.549126 Ending test lava.0_igt-gpu-panfrost (14879028_1.5.2.3.1), duration 0.82
11351 13:17:14.554887 equirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11352 13:17:14.558480 Test requirement: !(fd<0)
11353 13:17:14.561522 No known gpu found for chipset flags 0x32 (panfrost)
11354 13:17:14.565071 Last errno: 2, No such file or directory
11355 13:17:14.571992 [1mSubtest pan-reset: SKIP (0.000s)[0m
11356 13:17:14.575244 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11357 13:17:14.581785 Using IGT_SRANDOM=1721308634 for randomisation
11358 13:17:14.588353 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11359 13:17:14.588454 Test requirement: !(fd<0)
11360 13:17:14.595059 No known gpu found for chipset flags 0x32 (panfrost)
11361 13:17:14.598427 Last errno: 2, No such file or directory
11362 13:17:14.601735 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11363 13:17:14.608379 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11364 13:17:14.611831 Using IGT_SRANDOM=1721308634 for randomisation
11365 13:17:14.621966 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11366 13:17:14.622054 Test requirement: !(fd<0)
11367 13:17:14.628455 No known gpu found for chipset flags 0x32 (panfrost)
11368 13:17:14.631784 Last errno: 2, No such file or directory
11369 13:17:14.634727 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11370 13:17:14.634820 + set +x
11371 13:17:14.638175 <LAVA_TEST_RUNNER EXIT>
11372 13:17:14.638431 ok: lava_test_shell seems to have completed
11373 13:17:14.639065 gem-new-4096:
set: panfrost_gem_new
result: skip
gem-new-0:
set: panfrost_gem_new
result: skip
gem-new-zeroed:
set: panfrost_gem_new
result: skip
base-params:
set: panfrost_get_param
result: skip
get-bad-param:
set: panfrost_get_param
result: skip
get-bad-padding:
set: panfrost_get_param
result: skip
gem-prime-import:
set: panfrost_prime
result: skip
pan-submit:
set: panfrost_submit
result: skip
pan-submit-error-no-jc:
set: panfrost_submit
result: skip
pan-submit-error-bad-in-syncs:
set: panfrost_submit
result: skip
pan-submit-error-bad-bo-handles:
set: panfrost_submit
result: skip
pan-submit-error-bad-requirements:
set: panfrost_submit
result: skip
pan-submit-error-bad-out-sync:
set: panfrost_submit
result: skip
pan-reset:
set: panfrost_submit
result: skip
pan-submit-and-close:
set: panfrost_submit
result: skip
pan-unhandled-pagefault:
set: panfrost_submit
result: skip
11374 13:17:14.639196 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11375 13:17:14.639318 end: 3 lava-test-retry (duration 00:00:01) [common]
11376 13:17:14.639436 start: 4 finalize (timeout 00:07:16) [common]
11377 13:17:14.639548 start: 4.1 power-off (timeout 00:00:30) [common]
11378 13:17:14.639807 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
11379 13:17:16.710402 >> Command sent successfully.
11380 13:17:16.713418 Returned 0 in 2 seconds
11381 13:17:16.713575 end: 4.1 power-off (duration 00:00:02) [common]
11383 13:17:16.713932 start: 4.2 read-feedback (timeout 00:07:14) [common]
11384 13:17:16.714124 Listened to connection for namespace 'common' for up to 1s
11385 13:17:17.715118 Finalising connection for namespace 'common'
11386 13:17:17.715248 Disconnecting from shell: Finalise
11387 13:17:17.715325 / #
11388 13:17:17.815545 end: 4.2 read-feedback (duration 00:00:01) [common]
11389 13:17:17.815678 end: 4 finalize (duration 00:00:03) [common]
11390 13:17:17.815784 Cleaning after the job
11391 13:17:17.815876 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879028/tftp-deploy-kxj7s8bm/ramdisk
11392 13:17:17.822377 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879028/tftp-deploy-kxj7s8bm/kernel
11393 13:17:17.837459 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879028/tftp-deploy-kxj7s8bm/dtb
11394 13:17:17.837639 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879028/tftp-deploy-kxj7s8bm/modules
11395 13:17:17.843121 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14879028
11396 13:17:17.957541 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14879028
11397 13:17:17.957708 Job finished correctly