Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 28
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 13:11:09.381287 lava-dispatcher, installed at version: 2024.05
2 13:11:09.381484 start: 0 validate
3 13:11:09.381612 Start time: 2024-07-18 13:11:09.381602+00:00 (UTC)
4 13:11:09.381743 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:11:09.381880 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 13:11:09.641364 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:11:09.641530 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 13:11:09.899175 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:11:09.899360 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:11:10.156685 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:11:10.156818 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
12 13:11:10.414959 validate duration: 1.03
14 13:11:10.415233 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:11:10.415329 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:11:10.415424 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:11:10.415584 Not decompressing ramdisk as can be used compressed.
18 13:11:10.415679 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 13:11:10.415740 saving as /var/lib/lava/dispatcher/tmp/14879019/tftp-deploy-b23ufq6g/ramdisk/rootfs.cpio.gz
20 13:11:10.415821 total size: 47897469 (45 MB)
21 13:11:10.417194 progress 0 % (0 MB)
22 13:11:10.430622 progress 5 % (2 MB)
23 13:11:10.443820 progress 10 % (4 MB)
24 13:11:10.457587 progress 15 % (6 MB)
25 13:11:10.470427 progress 20 % (9 MB)
26 13:11:10.483101 progress 25 % (11 MB)
27 13:11:10.495950 progress 30 % (13 MB)
28 13:11:10.508882 progress 35 % (16 MB)
29 13:11:10.521988 progress 40 % (18 MB)
30 13:11:10.535249 progress 45 % (20 MB)
31 13:11:10.548755 progress 50 % (22 MB)
32 13:11:10.561607 progress 55 % (25 MB)
33 13:11:10.574627 progress 60 % (27 MB)
34 13:11:10.587538 progress 65 % (29 MB)
35 13:11:10.599976 progress 70 % (32 MB)
36 13:11:10.611865 progress 75 % (34 MB)
37 13:11:10.624931 progress 80 % (36 MB)
38 13:11:10.638310 progress 85 % (38 MB)
39 13:11:10.651130 progress 90 % (41 MB)
40 13:11:10.663791 progress 95 % (43 MB)
41 13:11:10.676380 progress 100 % (45 MB)
42 13:11:10.676625 45 MB downloaded in 0.26 s (175.15 MB/s)
43 13:11:10.676835 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:11:10.677230 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:11:10.677326 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:11:10.677404 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:11:10.677547 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
49 13:11:10.677609 saving as /var/lib/lava/dispatcher/tmp/14879019/tftp-deploy-b23ufq6g/kernel/Image
50 13:11:10.677675 total size: 54813184 (52 MB)
51 13:11:10.677732 No compression specified
52 13:11:10.679139 progress 0 % (0 MB)
53 13:11:10.692662 progress 5 % (2 MB)
54 13:11:10.706756 progress 10 % (5 MB)
55 13:11:10.721284 progress 15 % (7 MB)
56 13:11:10.735244 progress 20 % (10 MB)
57 13:11:10.748892 progress 25 % (13 MB)
58 13:11:10.762475 progress 30 % (15 MB)
59 13:11:10.776177 progress 35 % (18 MB)
60 13:11:10.789916 progress 40 % (20 MB)
61 13:11:10.803427 progress 45 % (23 MB)
62 13:11:10.817036 progress 50 % (26 MB)
63 13:11:10.830665 progress 55 % (28 MB)
64 13:11:10.844326 progress 60 % (31 MB)
65 13:11:10.858045 progress 65 % (34 MB)
66 13:11:10.871565 progress 70 % (36 MB)
67 13:11:10.885273 progress 75 % (39 MB)
68 13:11:10.898892 progress 80 % (41 MB)
69 13:11:10.912369 progress 85 % (44 MB)
70 13:11:10.925912 progress 90 % (47 MB)
71 13:11:10.939427 progress 95 % (49 MB)
72 13:11:10.952803 progress 100 % (52 MB)
73 13:11:10.953018 52 MB downloaded in 0.28 s (189.85 MB/s)
74 13:11:10.953213 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:11:10.953423 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:11:10.953502 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:11:10.953577 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:11:10.953707 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:11:10.953781 saving as /var/lib/lava/dispatcher/tmp/14879019/tftp-deploy-b23ufq6g/dtb/mt8192-asurada-spherion-r0.dtb
81 13:11:10.953835 total size: 47258 (0 MB)
82 13:11:10.953887 No compression specified
83 13:11:10.954873 progress 69 % (0 MB)
84 13:11:10.955125 progress 100 % (0 MB)
85 13:11:10.955302 0 MB downloaded in 0.00 s (30.77 MB/s)
86 13:11:10.955413 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:11:10.955607 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:11:10.955681 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:11:10.955754 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:11:10.955858 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
92 13:11:10.955918 saving as /var/lib/lava/dispatcher/tmp/14879019/tftp-deploy-b23ufq6g/modules/modules.tar
93 13:11:10.955969 total size: 8611320 (8 MB)
94 13:11:10.956022 Using unxz to decompress xz
95 13:11:10.957360 progress 0 % (0 MB)
96 13:11:10.977664 progress 5 % (0 MB)
97 13:11:11.001847 progress 10 % (0 MB)
98 13:11:11.025189 progress 15 % (1 MB)
99 13:11:11.048965 progress 20 % (1 MB)
100 13:11:11.072723 progress 25 % (2 MB)
101 13:11:11.099292 progress 30 % (2 MB)
102 13:11:11.121539 progress 35 % (2 MB)
103 13:11:11.147302 progress 40 % (3 MB)
104 13:11:11.171431 progress 45 % (3 MB)
105 13:11:11.195332 progress 50 % (4 MB)
106 13:11:11.219734 progress 55 % (4 MB)
107 13:11:11.243374 progress 60 % (4 MB)
108 13:11:11.266484 progress 65 % (5 MB)
109 13:11:11.291539 progress 70 % (5 MB)
110 13:11:11.318179 progress 75 % (6 MB)
111 13:11:11.345105 progress 80 % (6 MB)
112 13:11:11.368333 progress 85 % (7 MB)
113 13:11:11.391122 progress 90 % (7 MB)
114 13:11:11.414493 progress 95 % (7 MB)
115 13:11:11.437044 progress 100 % (8 MB)
116 13:11:11.442585 8 MB downloaded in 0.49 s (16.88 MB/s)
117 13:11:11.442744 end: 1.4.1 http-download (duration 00:00:00) [common]
119 13:11:11.442949 end: 1.4 download-retry (duration 00:00:00) [common]
120 13:11:11.443027 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:11:11.443102 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:11:11.443176 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:11:11.443247 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:11:11.443411 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9
125 13:11:11.443530 makedir: /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin
126 13:11:11.443619 makedir: /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/tests
127 13:11:11.443706 makedir: /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/results
128 13:11:11.443792 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-add-keys
129 13:11:11.443920 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-add-sources
130 13:11:11.444039 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-background-process-start
131 13:11:11.444156 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-background-process-stop
132 13:11:11.444282 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-common-functions
133 13:11:11.444410 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-echo-ipv4
134 13:11:11.444526 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-install-packages
135 13:11:11.444658 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-installed-packages
136 13:11:11.444770 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-os-build
137 13:11:11.444897 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-probe-channel
138 13:11:11.445019 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-probe-ip
139 13:11:11.445166 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-target-ip
140 13:11:11.445280 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-target-mac
141 13:11:11.445408 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-target-storage
142 13:11:11.445533 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-test-case
143 13:11:11.445680 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-test-event
144 13:11:11.445800 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-test-feedback
145 13:11:11.445914 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-test-raise
146 13:11:11.446024 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-test-reference
147 13:11:11.446139 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-test-runner
148 13:11:11.446251 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-test-set
149 13:11:11.446364 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-test-shell
150 13:11:11.446514 Updating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-install-packages (oe)
151 13:11:11.523267 Updating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/bin/lava-installed-packages (oe)
152 13:11:11.524082 Creating /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/environment
153 13:11:11.524627 LAVA metadata
154 13:11:11.524972 - LAVA_JOB_ID=14879019
155 13:11:11.525331 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:11:11.525836 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:11:11.526146 skipped lava-vland-overlay
158 13:11:11.526494 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:11:11.526852 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:11:11.527147 skipped lava-multinode-overlay
161 13:11:11.527475 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:11:11.527825 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:11:11.528159 Loading test definitions
164 13:11:11.528541 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:11:11.528851 Using /lava-14879019 at stage 0
166 13:11:11.530418 uuid=14879019_1.5.2.3.1 testdef=None
167 13:11:11.530972 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:11:11.531367 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:11:11.533580 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:11:11.534583 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:11:11.537426 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:11:11.538489 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:11:11.637236 runner path: /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/0/tests/0_igt-kms-mediatek test_uuid 14879019_1.5.2.3.1
176 13:11:11.638076 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:11:11.639084 Creating lava-test-runner.conf files
179 13:11:11.639377 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14879019/lava-overlay-zupr4op9/lava-14879019/0 for stage 0
180 13:11:11.639790 - 0_igt-kms-mediatek
181 13:11:11.640345 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:11:11.640849 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:11:11.667734 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:11:11.668014 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:11:11.668241 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:11:11.668450 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:11:11.668653 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:11:13.380248 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 13:11:13.380392 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 13:11:13.380469 extracting modules file /var/lib/lava/dispatcher/tmp/14879019/tftp-deploy-b23ufq6g/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14879019/extract-overlay-ramdisk-pgic1li2/ramdisk
191 13:11:13.614625 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:11:13.614758 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 13:11:13.614834 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14879019/compress-overlay-5l7zo5wx/overlay-1.5.2.4.tar.gz to ramdisk
194 13:11:13.614894 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14879019/compress-overlay-5l7zo5wx/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14879019/extract-overlay-ramdisk-pgic1li2/ramdisk
195 13:11:13.621372 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:11:13.621472 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 13:11:13.621567 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:11:13.621646 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 13:11:13.621710 Building ramdisk /var/lib/lava/dispatcher/tmp/14879019/extract-overlay-ramdisk-pgic1li2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14879019/extract-overlay-ramdisk-pgic1li2/ramdisk
200 13:11:15.853970 >> 465549 blocks
201 13:11:22.356172 rename /var/lib/lava/dispatcher/tmp/14879019/extract-overlay-ramdisk-pgic1li2/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14879019/tftp-deploy-b23ufq6g/ramdisk/ramdisk.cpio.gz
202 13:11:22.356340 end: 1.5.7 compress-ramdisk (duration 00:00:09) [common]
203 13:11:22.356425 start: 1.5.8 prepare-kernel (timeout 00:09:48) [common]
204 13:11:22.356499 start: 1.5.8.1 prepare-fit (timeout 00:09:48) [common]
205 13:11:22.356574 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14879019/tftp-deploy-b23ufq6g/kernel/Image']
206 13:11:36.303965 Returned 0 in 13 seconds
207 13:11:36.304152 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14879019/tftp-deploy-b23ufq6g/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14879019/tftp-deploy-b23ufq6g/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14879019/tftp-deploy-b23ufq6g/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14879019/tftp-deploy-b23ufq6g/kernel/image.itb
208 13:11:38.224613 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:11:38.224735 output: Created: Thu Jul 18 14:11:37 2024
210 13:11:38.224799 output: Image 0 (kernel-1)
211 13:11:38.224852 output: Description:
212 13:11:38.224903 output: Created: Thu Jul 18 14:11:37 2024
213 13:11:38.224953 output: Type: Kernel Image
214 13:11:38.225001 output: Compression: lzma compressed
215 13:11:38.225052 output: Data Size: 13114469 Bytes = 12807.10 KiB = 12.51 MiB
216 13:11:38.225100 output: Architecture: AArch64
217 13:11:38.225152 output: OS: Linux
218 13:11:38.225242 output: Load Address: 0x00000000
219 13:11:38.225296 output: Entry Point: 0x00000000
220 13:11:38.225385 output: Hash algo: crc32
221 13:11:38.225442 output: Hash value: a47b020b
222 13:11:38.225490 output: Image 1 (fdt-1)
223 13:11:38.225554 output: Description: mt8192-asurada-spherion-r0
224 13:11:38.225608 output: Created: Thu Jul 18 14:11:37 2024
225 13:11:38.225657 output: Type: Flat Device Tree
226 13:11:38.225704 output: Compression: uncompressed
227 13:11:38.225750 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 13:11:38.225797 output: Architecture: AArch64
229 13:11:38.225844 output: Hash algo: crc32
230 13:11:38.225890 output: Hash value: 0f8e4d2e
231 13:11:38.225936 output: Image 2 (ramdisk-1)
232 13:11:38.225982 output: Description: unavailable
233 13:11:38.226029 output: Created: Thu Jul 18 14:11:37 2024
234 13:11:38.226076 output: Type: RAMDisk Image
235 13:11:38.226122 output: Compression: uncompressed
236 13:11:38.226168 output: Data Size: 60984890 Bytes = 59555.56 KiB = 58.16 MiB
237 13:11:38.226233 output: Architecture: AArch64
238 13:11:38.226281 output: OS: Linux
239 13:11:38.226327 output: Load Address: unavailable
240 13:11:38.226373 output: Entry Point: unavailable
241 13:11:38.226425 output: Hash algo: crc32
242 13:11:38.226481 output: Hash value: d4c404c1
243 13:11:38.226528 output: Default Configuration: 'conf-1'
244 13:11:38.226575 output: Configuration 0 (conf-1)
245 13:11:38.226639 output: Description: mt8192-asurada-spherion-r0
246 13:11:38.226690 output: Kernel: kernel-1
247 13:11:38.226736 output: Init Ramdisk: ramdisk-1
248 13:11:38.226783 output: FDT: fdt-1
249 13:11:38.226832 output: Loadables: kernel-1
250 13:11:38.226879 output:
251 13:11:38.226982 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 13:11:38.227056 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 13:11:38.227128 end: 1.5 prepare-tftp-overlay (duration 00:00:27) [common]
254 13:11:38.227199 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:32) [common]
255 13:11:38.227253 No LXC device requested
256 13:11:38.227320 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:11:38.227388 start: 1.7 deploy-device-env (timeout 00:09:32) [common]
258 13:11:38.227453 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:11:38.227506 Checking files for TFTP limit of 4294967296 bytes.
260 13:11:38.227854 end: 1 tftp-deploy (duration 00:00:28) [common]
261 13:11:38.227940 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:11:38.228016 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:11:38.228101 substitutions:
264 13:11:38.228159 - {DTB}: 14879019/tftp-deploy-b23ufq6g/dtb/mt8192-asurada-spherion-r0.dtb
265 13:11:38.228223 - {INITRD}: 14879019/tftp-deploy-b23ufq6g/ramdisk/ramdisk.cpio.gz
266 13:11:38.228278 - {KERNEL}: 14879019/tftp-deploy-b23ufq6g/kernel/Image
267 13:11:38.228327 - {LAVA_MAC}: None
268 13:11:38.228376 - {PRESEED_CONFIG}: None
269 13:11:38.228439 - {PRESEED_LOCAL}: None
270 13:11:38.228490 - {RAMDISK}: 14879019/tftp-deploy-b23ufq6g/ramdisk/ramdisk.cpio.gz
271 13:11:38.228547 - {ROOT_PART}: None
272 13:11:38.228598 - {ROOT}: None
273 13:11:38.228679 - {SERVER_IP}: 192.168.201.1
274 13:11:38.228754 - {TEE}: None
275 13:11:38.228835 Parsed boot commands:
276 13:11:38.228909 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:11:38.229079 Parsed boot commands: tftpboot 192.168.201.1 14879019/tftp-deploy-b23ufq6g/kernel/image.itb 14879019/tftp-deploy-b23ufq6g/kernel/cmdline
278 13:11:38.229224 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:11:38.229306 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:11:38.229377 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:11:38.229462 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:11:38.229515 Not connected, no need to disconnect.
283 13:11:38.229579 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:11:38.229649 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:11:38.229702 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 13:11:38.232797 Setting prompt string to ['lava-test: # ']
287 13:11:38.233119 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:11:38.233256 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:11:38.233345 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:11:38.233421 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:11:38.233591 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=reboot']
292 13:11:47.370314 >> Command sent successfully.
293 13:11:47.373487 Returned 0 in 9 seconds
294 13:11:47.373657 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 13:11:47.373868 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 13:11:47.373955 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 13:11:47.374026 Setting prompt string to 'Starting depthcharge on Spherion...'
299 13:11:47.374080 Changing prompt to 'Starting depthcharge on Spherion...'
300 13:11:47.374135 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 13:11:47.374463 [Enter `^Ec?' for help]
302 13:11:48.948585
303 13:11:48.948720
304 13:11:48.948779 F0: 102B 0000
305 13:11:48.948840
306 13:11:48.948892 F3: 1001 0000 [0200]
307 13:11:48.952475
308 13:11:48.952558 F3: 1001 0000
309 13:11:48.952617
310 13:11:48.952670 F7: 102D 0000
311 13:11:48.952725
312 13:11:48.956099 F1: 0000 0000
313 13:11:48.956178
314 13:11:48.956236 V0: 0000 0000 [0001]
315 13:11:48.956290
316 13:11:48.956341 00: 0007 8000
317 13:11:48.956393
318 13:11:48.959403 01: 0000 0000
319 13:11:48.959483
320 13:11:48.959540 BP: 0C00 0209 [0000]
321 13:11:48.959594
322 13:11:48.963414 G0: 1182 0000
323 13:11:48.963495
324 13:11:48.963575 EC: 0000 0021 [4000]
325 13:11:48.963631
326 13:11:48.967650 S7: 0000 0000 [0000]
327 13:11:48.967729
328 13:11:48.967787 CC: 0000 0000 [0001]
329 13:11:48.967842
330 13:11:48.970684 T0: 0000 0040 [010F]
331 13:11:48.970761
332 13:11:48.970819 Jump to BL
333 13:11:48.970872
334 13:11:48.995791
335 13:11:48.995919
336 13:11:49.003102 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 13:11:49.005855 ARM64: Exception handlers installed.
338 13:11:49.009364 ARM64: Testing exception
339 13:11:49.012649 ARM64: Done test exception
340 13:11:49.019690 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 13:11:49.029390 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 13:11:49.035924 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 13:11:49.046714 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 13:11:49.052851 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 13:11:49.155405 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 13:11:49.155944 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 13:11:49.156372 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 13:11:49.156795 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 13:11:49.157207 WDT: Last reset was cold boot
350 13:11:49.157611 SPI1(PAD0) initialized at 2873684 Hz
351 13:11:49.158031 SPI5(PAD0) initialized at 992727 Hz
352 13:11:49.158459 VBOOT: Loading verstage.
353 13:11:49.158890 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 13:11:49.159317 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 13:11:49.159741 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 13:11:49.160171 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 13:11:49.160596 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 13:11:49.160763 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 13:11:49.160860 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 13:11:49.160956
361 13:11:49.161054
362 13:11:49.164011 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 13:11:49.166849 ARM64: Exception handlers installed.
364 13:11:49.315105 ARM64: Testing exception
365 13:11:49.315665 ARM64: Done test exception
366 13:11:49.316456 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 13:11:49.316960 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 13:11:49.317461 Probing TPM: . done!
369 13:11:49.317917 TPM ready after 0 ms
370 13:11:49.318393 Connected to device vid:did:rid of 1ae0:0028:00
371 13:11:49.318839 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
372 13:11:49.319278 Initialized TPM device CR50 revision 0
373 13:11:49.319715 tlcl_send_startup: Startup return code is 0
374 13:11:49.320124 TPM: setup succeeded
375 13:11:49.320544 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 13:11:49.320958 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 13:11:49.321437 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 13:11:49.321862 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 13:11:49.322316 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 13:11:49.322594 in-header: 03 07 00 00 08 00 00 00
381 13:11:49.322826 in-data: aa e4 47 04 13 02 00 00
382 13:11:49.323106 Chrome EC: UHEPI supported
383 13:11:49.323396 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 13:11:49.323635 in-header: 03 a9 00 00 08 00 00 00
385 13:11:49.325486 in-data: 84 60 60 08 00 00 00 00
386 13:11:49.325834 Phase 1
387 13:11:49.332232 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 13:11:49.335506 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 13:11:49.341902 VB2:vb2_check_recovery() Recovery was requested manually
390 13:11:49.348693 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 13:11:49.348901 Recovery requested (1009000e)
392 13:11:49.357379 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 13:11:49.363051 tlcl_extend: response is 0
394 13:11:49.371155 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 13:11:49.376200 tlcl_extend: response is 0
396 13:11:49.382748 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 13:11:49.403315 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 13:11:49.410146 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 13:11:49.410252
400 13:11:49.410312
401 13:11:49.420136 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 13:11:49.423326 ARM64: Exception handlers installed.
403 13:11:49.426441 ARM64: Testing exception
404 13:11:49.426545 ARM64: Done test exception
405 13:11:49.449174 pmic_efuse_setting: Set efuses in 11 msecs
406 13:11:49.452667 pmwrap_interface_init: Select PMIF_VLD_RDY
407 13:11:49.456659 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 13:11:49.463359 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 13:11:49.466612 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 13:11:49.474026 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 13:11:49.477732 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 13:11:49.480641 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 13:11:49.487139 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 13:11:49.491116 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 13:11:49.497492 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 13:11:49.500451 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 13:11:49.507200 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 13:11:49.510799 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 13:11:49.513964 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 13:11:49.520719 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 13:11:49.527239 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 13:11:49.534338 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 13:11:49.537054 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 13:11:49.543862 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 13:11:49.550576 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 13:11:49.553860 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 13:11:49.560171 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 13:11:49.566602 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 13:11:49.573908 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 13:11:49.576477 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 13:11:49.583468 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 13:11:49.590003 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 13:11:49.593434 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 13:11:49.596274 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 13:11:49.602969 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 13:11:49.606542 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 13:11:49.613121 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 13:11:49.616622 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 13:11:49.623038 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 13:11:49.626170 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 13:11:49.632752 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 13:11:49.636064 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 13:11:49.642915 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 13:11:49.649862 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 13:11:49.653472 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 13:11:49.656539 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 13:11:49.659617 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 13:11:49.666271 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 13:11:49.669577 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 13:11:49.673090 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 13:11:49.679906 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 13:11:49.682836 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 13:11:49.686232 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 13:11:49.692924 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 13:11:49.696134 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 13:11:49.699254 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 13:11:49.702741 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 13:11:49.712854 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 13:11:49.719403 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 13:11:49.726761 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 13:11:49.732775 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 13:11:49.742537 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 13:11:49.745880 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 13:11:49.749483 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:11:49.756029 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 13:11:49.984857 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
467 13:11:49.985351 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 13:11:49.985730 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
469 13:11:49.986083 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 13:11:49.986353 [RTC]rtc_get_frequency_meter,154: input=15, output=853
471 13:11:49.986666 [RTC]rtc_get_frequency_meter,154: input=7, output=725
472 13:11:49.986930 [RTC]rtc_get_frequency_meter,154: input=11, output=789
473 13:11:49.987191 [RTC]rtc_get_frequency_meter,154: input=13, output=822
474 13:11:49.987468 [RTC]rtc_get_frequency_meter,154: input=12, output=806
475 13:11:49.987718 [RTC]rtc_get_frequency_meter,154: input=11, output=789
476 13:11:49.987956 [RTC]rtc_get_frequency_meter,154: input=12, output=805
477 13:11:49.988190 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
478 13:11:49.988426 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
479 13:11:49.988662 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 13:11:49.988896 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 13:11:49.989128 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 13:11:49.989443 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 13:11:49.989679 ADC[4]: Raw value=904802 ID=7
484 13:11:49.989752 ADC[3]: Raw value=213546 ID=1
485 13:11:49.989823 RAM Code: 0x71
486 13:11:49.989873 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 13:11:49.989924 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 13:11:49.989975 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 13:11:49.990025 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 13:11:49.990075 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 13:11:49.990131 in-header: 03 07 00 00 08 00 00 00
492 13:11:49.990183 in-data: aa e4 47 04 13 02 00 00
493 13:11:49.990232 Chrome EC: UHEPI supported
494 13:11:49.990281 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 13:11:49.990349 in-header: 03 a9 00 00 08 00 00 00
496 13:11:49.990418 in-data: 84 60 60 08 00 00 00 00
497 13:11:49.990535 MRC: failed to locate region type 0.
498 13:11:49.990650 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 13:11:49.990741 DRAM-K: Running full calibration
500 13:11:49.990830 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 13:11:49.990909 header.status = 0x0
502 13:11:49.990987 header.version = 0x6 (expected: 0x6)
503 13:11:49.991066 header.size = 0xd00 (expected: 0xd00)
504 13:11:49.991143 header.flags = 0x0
505 13:11:49.991222 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 13:11:49.991301 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 13:11:49.991414 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 13:11:49.991511 dram_init: ddr_geometry: 2
509 13:11:49.993512 [EMI] MDL number = 2
510 13:11:49.993582 [EMI] Get MDL freq = 0
511 13:11:49.996589 dram_init: ddr_type: 0
512 13:11:49.996672 is_discrete_lpddr4: 1
513 13:11:50.000206 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 13:11:50.000288
515 13:11:50.000351
516 13:11:50.003647 [Bian_co] ETT version 0.0.0.1
517 13:11:50.009799 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 13:11:50.009900
519 13:11:50.013021 dramc_set_vcore_voltage set vcore to 650000
520 13:11:50.016501 Read voltage for 800, 4
521 13:11:50.016583 Vio18 = 0
522 13:11:50.016643 Vcore = 650000
523 13:11:50.019756 Vdram = 0
524 13:11:50.019835 Vddq = 0
525 13:11:50.019894 Vmddr = 0
526 13:11:50.023144 dram_init: config_dvfs: 1
527 13:11:50.026274 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 13:11:50.032846 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 13:11:50.036430 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 13:11:50.039433 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 13:11:50.042813 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 13:11:50.046396 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 13:11:50.049738 MEM_TYPE=3, freq_sel=18
534 13:11:50.053051 sv_algorithm_assistance_LP4_1600
535 13:11:50.056098 ============ PULL DRAM RESETB DOWN ============
536 13:11:50.063081 ========== PULL DRAM RESETB DOWN end =========
537 13:11:50.066131 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 13:11:50.069250 ===================================
539 13:11:50.072952 LPDDR4 DRAM CONFIGURATION
540 13:11:50.075969 ===================================
541 13:11:50.076054 EX_ROW_EN[0] = 0x0
542 13:11:50.079666 EX_ROW_EN[1] = 0x0
543 13:11:50.079746 LP4Y_EN = 0x0
544 13:11:50.082881 WORK_FSP = 0x0
545 13:11:50.082960 WL = 0x2
546 13:11:50.086441 RL = 0x2
547 13:11:50.086521 BL = 0x2
548 13:11:50.089442 RPST = 0x0
549 13:11:50.089520 RD_PRE = 0x0
550 13:11:50.093033 WR_PRE = 0x1
551 13:11:50.093112 WR_PST = 0x0
552 13:11:50.095875 DBI_WR = 0x0
553 13:11:50.099207 DBI_RD = 0x0
554 13:11:50.099287 OTF = 0x1
555 13:11:50.102983 ===================================
556 13:11:50.106230 ===================================
557 13:11:50.106311 ANA top config
558 13:11:50.109797 ===================================
559 13:11:50.113364 DLL_ASYNC_EN = 0
560 13:11:50.117384 ALL_SLAVE_EN = 1
561 13:11:50.117473 NEW_RANK_MODE = 1
562 13:11:50.121238 DLL_IDLE_MODE = 1
563 13:11:50.124477 LP45_APHY_COMB_EN = 1
564 13:11:50.124568 TX_ODT_DIS = 1
565 13:11:50.128426 NEW_8X_MODE = 1
566 13:11:50.132510 ===================================
567 13:11:50.135852 ===================================
568 13:11:50.139618 data_rate = 1600
569 13:11:50.143194 CKR = 1
570 13:11:50.143280 DQ_P2S_RATIO = 8
571 13:11:50.146362 ===================================
572 13:11:50.149420 CA_P2S_RATIO = 8
573 13:11:50.152782 DQ_CA_OPEN = 0
574 13:11:50.156181 DQ_SEMI_OPEN = 0
575 13:11:50.159540 CA_SEMI_OPEN = 0
576 13:11:50.159631 CA_FULL_RATE = 0
577 13:11:50.162978 DQ_CKDIV4_EN = 1
578 13:11:50.166439 CA_CKDIV4_EN = 1
579 13:11:50.169698 CA_PREDIV_EN = 0
580 13:11:50.172918 PH8_DLY = 0
581 13:11:50.176493 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 13:11:50.176569 DQ_AAMCK_DIV = 4
583 13:11:50.179799 CA_AAMCK_DIV = 4
584 13:11:50.183027 CA_ADMCK_DIV = 4
585 13:11:50.186219 DQ_TRACK_CA_EN = 0
586 13:11:50.189590 CA_PICK = 800
587 13:11:50.192778 CA_MCKIO = 800
588 13:11:50.192859 MCKIO_SEMI = 0
589 13:11:50.195988 PLL_FREQ = 3068
590 13:11:50.199246 DQ_UI_PI_RATIO = 32
591 13:11:50.202425 CA_UI_PI_RATIO = 0
592 13:11:50.205855 ===================================
593 13:11:50.209370 ===================================
594 13:11:50.212387 memory_type:LPDDR4
595 13:11:50.212470 GP_NUM : 10
596 13:11:50.216031 SRAM_EN : 1
597 13:11:50.219068 MD32_EN : 0
598 13:11:50.222256 ===================================
599 13:11:50.222339 [ANA_INIT] >>>>>>>>>>>>>>
600 13:11:50.225972 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 13:11:50.229106 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 13:11:50.232570 ===================================
603 13:11:50.235434 data_rate = 1600,PCW = 0X7600
604 13:11:50.239276 ===================================
605 13:11:50.242479 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 13:11:50.249151 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 13:11:50.252448 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 13:11:50.259057 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 13:11:50.262171 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 13:11:50.265711 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 13:11:50.268750 [ANA_INIT] flow start
612 13:11:50.268831 [ANA_INIT] PLL >>>>>>>>
613 13:11:50.272268 [ANA_INIT] PLL <<<<<<<<
614 13:11:50.275624 [ANA_INIT] MIDPI >>>>>>>>
615 13:11:50.275707 [ANA_INIT] MIDPI <<<<<<<<
616 13:11:50.278819 [ANA_INIT] DLL >>>>>>>>
617 13:11:50.282025 [ANA_INIT] flow end
618 13:11:50.285207 ============ LP4 DIFF to SE enter ============
619 13:11:50.289022 ============ LP4 DIFF to SE exit ============
620 13:11:50.292042 [ANA_INIT] <<<<<<<<<<<<<
621 13:11:50.295550 [Flow] Enable top DCM control >>>>>
622 13:11:50.298854 [Flow] Enable top DCM control <<<<<
623 13:11:50.301903 Enable DLL master slave shuffle
624 13:11:50.305477 ==============================================================
625 13:11:50.308323 Gating Mode config
626 13:11:50.315247 ==============================================================
627 13:11:50.315370 Config description:
628 13:11:50.324916 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 13:11:50.331971 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 13:11:50.334872 SELPH_MODE 0: By rank 1: By Phase
631 13:11:50.341736 ==============================================================
632 13:11:50.344939 GAT_TRACK_EN = 1
633 13:11:50.349261 RX_GATING_MODE = 2
634 13:11:50.351622 RX_GATING_TRACK_MODE = 2
635 13:11:50.354974 SELPH_MODE = 1
636 13:11:50.358672 PICG_EARLY_EN = 1
637 13:11:50.361575 VALID_LAT_VALUE = 1
638 13:11:50.364721 ==============================================================
639 13:11:50.368868 Enter into Gating configuration >>>>
640 13:11:50.371821 Exit from Gating configuration <<<<
641 13:11:50.374707 Enter into DVFS_PRE_config >>>>>
642 13:11:50.387955 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 13:11:50.388075 Exit from DVFS_PRE_config <<<<<
644 13:11:50.391385 Enter into PICG configuration >>>>
645 13:11:50.394768 Exit from PICG configuration <<<<
646 13:11:50.398077 [RX_INPUT] configuration >>>>>
647 13:11:50.401325 [RX_INPUT] configuration <<<<<
648 13:11:50.408309 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 13:11:50.411621 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 13:11:50.417982 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 13:11:50.424515 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 13:11:50.431482 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 13:11:50.437859 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 13:11:50.441308 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 13:11:50.444345 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 13:11:50.447780 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 13:11:50.454358 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 13:11:50.458058 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 13:11:50.461225 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 13:11:50.464230 ===================================
661 13:11:50.467416 LPDDR4 DRAM CONFIGURATION
662 13:11:50.471074 ===================================
663 13:11:50.474148 EX_ROW_EN[0] = 0x0
664 13:11:50.474243 EX_ROW_EN[1] = 0x0
665 13:11:50.477445 LP4Y_EN = 0x0
666 13:11:50.477534 WORK_FSP = 0x0
667 13:11:50.480746 WL = 0x2
668 13:11:50.480861 RL = 0x2
669 13:11:50.484148 BL = 0x2
670 13:11:50.484254 RPST = 0x0
671 13:11:50.488009 RD_PRE = 0x0
672 13:11:50.488117 WR_PRE = 0x1
673 13:11:50.490928 WR_PST = 0x0
674 13:11:50.491026 DBI_WR = 0x0
675 13:11:50.494361 DBI_RD = 0x0
676 13:11:50.494469 OTF = 0x1
677 13:11:50.497558 ===================================
678 13:11:50.501301 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 13:11:50.507631 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 13:11:50.511308 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 13:11:50.514036 ===================================
682 13:11:50.517453 LPDDR4 DRAM CONFIGURATION
683 13:11:50.520565 ===================================
684 13:11:50.520681 EX_ROW_EN[0] = 0x10
685 13:11:50.524034 EX_ROW_EN[1] = 0x0
686 13:11:50.527212 LP4Y_EN = 0x0
687 13:11:50.527320 WORK_FSP = 0x0
688 13:11:50.530468 WL = 0x2
689 13:11:50.530578 RL = 0x2
690 13:11:50.533848 BL = 0x2
691 13:11:50.533960 RPST = 0x0
692 13:11:50.537611 RD_PRE = 0x0
693 13:11:50.537710 WR_PRE = 0x1
694 13:11:50.540682 WR_PST = 0x0
695 13:11:50.540780 DBI_WR = 0x0
696 13:11:50.544154 DBI_RD = 0x0
697 13:11:50.544248 OTF = 0x1
698 13:11:50.547307 ===================================
699 13:11:50.553641 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 13:11:50.558531 nWR fixed to 40
701 13:11:50.561569 [ModeRegInit_LP4] CH0 RK0
702 13:11:50.561671 [ModeRegInit_LP4] CH0 RK1
703 13:11:50.564848 [ModeRegInit_LP4] CH1 RK0
704 13:11:50.568152 [ModeRegInit_LP4] CH1 RK1
705 13:11:50.568248 match AC timing 13
706 13:11:50.574452 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 13:11:50.578132 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 13:11:50.581432 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 13:11:50.587840 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 13:11:50.591100 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 13:11:50.594318 [EMI DOE] emi_dcm 0
712 13:11:50.597487 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 13:11:50.597584 ==
714 13:11:50.601052 Dram Type= 6, Freq= 0, CH_0, rank 0
715 13:11:50.604167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 13:11:50.604262 ==
717 13:11:50.611037 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 13:11:50.617395 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 13:11:50.626426 [CA 0] Center 38 (7~69) winsize 63
720 13:11:50.645315 [CA 1] Center 37 (6~68) winsize 63
721 13:11:50.645503 [CA 2] Center 34 (4~65) winsize 62
722 13:11:50.645578 [CA 3] Center 34 (4~65) winsize 62
723 13:11:50.645648 [CA 4] Center 33 (3~64) winsize 62
724 13:11:50.645716 [CA 5] Center 33 (3~64) winsize 62
725 13:11:50.645806
726 13:11:50.646135 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 13:11:50.646255
728 13:11:50.649409 [CATrainingPosCal] consider 1 rank data
729 13:11:50.653449 u2DelayCellTimex100 = 270/100 ps
730 13:11:50.656643 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
731 13:11:50.660343 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 13:11:50.663314 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 13:11:50.666925 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 13:11:50.669984 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 13:11:50.673607 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 13:11:50.676958
737 13:11:50.680288 CA PerBit enable=1, Macro0, CA PI delay=33
738 13:11:50.680434
739 13:11:50.683891 [CBTSetCACLKResult] CA Dly = 33
740 13:11:50.684005 CS Dly: 5 (0~36)
741 13:11:50.684091 ==
742 13:11:50.686795 Dram Type= 6, Freq= 0, CH_0, rank 1
743 13:11:50.690851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 13:11:50.690929 ==
745 13:11:50.697358 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 13:11:50.703757 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 13:11:50.711853 [CA 0] Center 38 (7~69) winsize 63
748 13:11:50.715277 [CA 1] Center 37 (7~68) winsize 62
749 13:11:50.718641 [CA 2] Center 35 (4~66) winsize 63
750 13:11:50.721722 [CA 3] Center 35 (4~66) winsize 63
751 13:11:50.725307 [CA 4] Center 34 (4~65) winsize 62
752 13:11:50.728617 [CA 5] Center 33 (3~64) winsize 62
753 13:11:50.728692
754 13:11:50.731742 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 13:11:50.731817
756 13:11:50.735151 [CATrainingPosCal] consider 2 rank data
757 13:11:50.739001 u2DelayCellTimex100 = 270/100 ps
758 13:11:50.742082 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
759 13:11:50.748471 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 13:11:50.751834 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 13:11:50.755438 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 13:11:50.758595 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
763 13:11:50.761679 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 13:11:50.761755
765 13:11:50.765106 CA PerBit enable=1, Macro0, CA PI delay=33
766 13:11:50.765206
767 13:11:50.769087 [CBTSetCACLKResult] CA Dly = 33
768 13:11:50.769201 CS Dly: 6 (0~38)
769 13:11:50.769261
770 13:11:50.772247 ----->DramcWriteLeveling(PI) begin...
771 13:11:50.775607 ==
772 13:11:50.778718 Dram Type= 6, Freq= 0, CH_0, rank 0
773 13:11:50.782030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 13:11:50.782108 ==
775 13:11:50.785446 Write leveling (Byte 0): 31 => 31
776 13:11:50.788380 Write leveling (Byte 1): 26 => 26
777 13:11:50.791895 DramcWriteLeveling(PI) end<-----
778 13:11:50.792006
779 13:11:50.792098 ==
780 13:11:50.795180 Dram Type= 6, Freq= 0, CH_0, rank 0
781 13:11:50.798629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 13:11:50.798706 ==
783 13:11:50.801597 [Gating] SW mode calibration
784 13:11:50.808469 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 13:11:50.814892 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 13:11:50.818662 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 13:11:50.821626 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
788 13:11:50.824883 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
789 13:11:50.832009 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:11:50.835063 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:11:50.838376 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:11:50.845392 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:11:50.848310 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:11:50.851672 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:11:50.858330 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:11:50.861445 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:11:50.865079 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:11:50.871586 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:11:50.874978 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:11:50.878210 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:11:50.885063 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:11:50.888459 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:11:50.891528 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 13:11:50.898368 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 13:11:50.901960 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:11:50.905045 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:11:50.911885 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:11:50.915181 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:11:50.918594 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:11:50.921561 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 13:11:50.928496 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
812 13:11:50.931714 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
813 13:11:50.934778 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
814 13:11:50.941677 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 13:11:50.945024 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 13:11:50.948431 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 13:11:50.954902 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 13:11:50.958210 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 13:11:50.961430 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
820 13:11:50.968057 0 10 8 | B1->B0 | 3030 2424 | 1 1 | (1 1) (1 0)
821 13:11:50.971670 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
822 13:11:50.975167 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 13:11:50.981605 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 13:11:50.984839 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 13:11:50.988081 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 13:11:50.994953 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 13:11:50.998212 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
828 13:11:51.001461 0 11 8 | B1->B0 | 2b2b 4545 | 0 0 | (0 0) (0 0)
829 13:11:51.008073 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
830 13:11:51.011907 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 13:11:51.015089 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 13:11:51.021487 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 13:11:51.024895 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 13:11:51.028235 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 13:11:51.031660 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 13:11:51.038489 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 13:11:51.041554 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 13:11:51.044851 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:11:51.051670 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:11:51.054773 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:11:51.058059 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:11:51.219971 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:11:51.220463 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:11:51.220670 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:11:51.220843 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:11:51.221010 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:11:51.221191 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:11:51.221358 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:11:51.221524 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:11:51.221686 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:11:51.221848 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
852 13:11:51.222006 Total UI for P1: 0, mck2ui 16
853 13:11:51.222164 best dqsien dly found for B0: ( 0, 14, 2)
854 13:11:51.222322 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
855 13:11:51.222480 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 13:11:51.222639 Total UI for P1: 0, mck2ui 16
857 13:11:51.222801 best dqsien dly found for B1: ( 0, 14, 8)
858 13:11:51.222961 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
859 13:11:51.223120 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 13:11:51.223275
861 13:11:51.223439 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
862 13:11:51.223597 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 13:11:51.223754 [Gating] SW calibration Done
864 13:11:51.223912 ==
865 13:11:51.224071 Dram Type= 6, Freq= 0, CH_0, rank 0
866 13:11:51.224231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 13:11:51.224391 ==
868 13:11:51.224552 RX Vref Scan: 0
869 13:11:51.224692
870 13:11:51.224769 RX Vref 0 -> 0, step: 1
871 13:11:51.224846
872 13:11:51.224923 RX Delay -130 -> 252, step: 16
873 13:11:51.225000 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 13:11:51.225077 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 13:11:51.225175 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 13:11:51.225268 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 13:11:51.225374 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 13:11:51.225451 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 13:11:51.225527 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 13:11:51.225604 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 13:11:51.225681 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 13:11:51.225758 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
883 13:11:51.225833 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 13:11:51.225909 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 13:11:51.225985 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 13:11:51.226061 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 13:11:51.226137 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 13:11:51.226229 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 13:11:51.226308 ==
890 13:11:51.226383 Dram Type= 6, Freq= 0, CH_0, rank 0
891 13:11:51.227275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 13:11:51.231110 ==
893 13:11:51.231219 DQS Delay:
894 13:11:51.231304 DQS0 = 0, DQS1 = 0
895 13:11:51.234349 DQM Delay:
896 13:11:51.234464 DQM0 = 88, DQM1 = 77
897 13:11:51.237377 DQ Delay:
898 13:11:51.237460 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 13:11:51.240530 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
900 13:11:51.243761 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
901 13:11:51.247383 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 13:11:51.247459
903 13:11:51.250607
904 13:11:51.250683 ==
905 13:11:51.254435 Dram Type= 6, Freq= 0, CH_0, rank 0
906 13:11:51.257682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 13:11:51.257758 ==
908 13:11:51.257814
909 13:11:51.257866
910 13:11:51.260767 TX Vref Scan disable
911 13:11:51.260841 == TX Byte 0 ==
912 13:11:51.267087 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
913 13:11:51.270756 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
914 13:11:51.270832 == TX Byte 1 ==
915 13:11:51.277420 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
916 13:11:51.280520 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
917 13:11:51.280623 ==
918 13:11:51.283904 Dram Type= 6, Freq= 0, CH_0, rank 0
919 13:11:51.287189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 13:11:51.287288 ==
921 13:11:51.301313 TX Vref=22, minBit 1, minWin=26, winSum=438
922 13:11:51.304409 TX Vref=24, minBit 1, minWin=27, winSum=442
923 13:11:51.308116 TX Vref=26, minBit 0, minWin=27, winSum=444
924 13:11:51.311237 TX Vref=28, minBit 2, minWin=27, winSum=449
925 13:11:51.314651 TX Vref=30, minBit 2, minWin=27, winSum=454
926 13:11:51.317699 TX Vref=32, minBit 2, minWin=27, winSum=447
927 13:11:51.324349 [TxChooseVref] Worse bit 2, Min win 27, Win sum 454, Final Vref 30
928 13:11:51.324448
929 13:11:51.327573 Final TX Range 1 Vref 30
930 13:11:51.327669
931 13:11:51.327752 ==
932 13:11:51.331247 Dram Type= 6, Freq= 0, CH_0, rank 0
933 13:11:51.334276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 13:11:51.334373 ==
935 13:11:51.334454
936 13:11:51.337948
937 13:11:51.338042 TX Vref Scan disable
938 13:11:51.341063 == TX Byte 0 ==
939 13:11:51.344685 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
940 13:11:51.351045 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
941 13:11:51.351143 == TX Byte 1 ==
942 13:11:51.354507 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
943 13:11:51.361072 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
944 13:11:51.361211
945 13:11:51.361298 [DATLAT]
946 13:11:51.361418 Freq=800, CH0 RK0
947 13:11:51.361501
948 13:11:51.364381 DATLAT Default: 0xa
949 13:11:51.364475 0, 0xFFFF, sum = 0
950 13:11:51.367532 1, 0xFFFF, sum = 0
951 13:11:51.370957 2, 0xFFFF, sum = 0
952 13:11:51.371055 3, 0xFFFF, sum = 0
953 13:11:51.374615 4, 0xFFFF, sum = 0
954 13:11:51.374714 5, 0xFFFF, sum = 0
955 13:11:51.377344 6, 0xFFFF, sum = 0
956 13:11:51.377442 7, 0xFFFF, sum = 0
957 13:11:51.380867 8, 0xFFFF, sum = 0
958 13:11:51.380967 9, 0x0, sum = 1
959 13:11:51.384022 10, 0x0, sum = 2
960 13:11:51.384121 11, 0x0, sum = 3
961 13:11:51.384214 12, 0x0, sum = 4
962 13:11:51.387561 best_step = 10
963 13:11:51.387655
964 13:11:51.387735 ==
965 13:11:51.390770 Dram Type= 6, Freq= 0, CH_0, rank 0
966 13:11:51.394143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 13:11:51.394242 ==
968 13:11:51.397558 RX Vref Scan: 1
969 13:11:51.397656
970 13:11:51.400745 Set Vref Range= 32 -> 127
971 13:11:51.400840
972 13:11:51.400924 RX Vref 32 -> 127, step: 1
973 13:11:51.401006
974 13:11:51.403851 RX Delay -95 -> 252, step: 8
975 13:11:51.403947
976 13:11:51.407556 Set Vref, RX VrefLevel [Byte0]: 32
977 13:11:51.410657 [Byte1]: 32
978 13:11:51.410782
979 13:11:51.414380 Set Vref, RX VrefLevel [Byte0]: 33
980 13:11:51.417443 [Byte1]: 33
981 13:11:51.421412
982 13:11:51.421551 Set Vref, RX VrefLevel [Byte0]: 34
983 13:11:51.424628 [Byte1]: 34
984 13:11:51.428871
985 13:11:51.428975 Set Vref, RX VrefLevel [Byte0]: 35
986 13:11:51.432631 [Byte1]: 35
987 13:11:51.436934
988 13:11:51.437037 Set Vref, RX VrefLevel [Byte0]: 36
989 13:11:51.439803 [Byte1]: 36
990 13:11:51.444428
991 13:11:51.444531 Set Vref, RX VrefLevel [Byte0]: 37
992 13:11:51.447667 [Byte1]: 37
993 13:11:51.451860
994 13:11:51.451949 Set Vref, RX VrefLevel [Byte0]: 38
995 13:11:51.455124 [Byte1]: 38
996 13:11:51.459673
997 13:11:51.459761 Set Vref, RX VrefLevel [Byte0]: 39
998 13:11:51.462965 [Byte1]: 39
999 13:11:51.467073
1000 13:11:51.467157 Set Vref, RX VrefLevel [Byte0]: 40
1001 13:11:51.470530 [Byte1]: 40
1002 13:11:51.474779
1003 13:11:51.474862 Set Vref, RX VrefLevel [Byte0]: 41
1004 13:11:51.477819 [Byte1]: 41
1005 13:11:51.482256
1006 13:11:51.482368 Set Vref, RX VrefLevel [Byte0]: 42
1007 13:11:51.485658 [Byte1]: 42
1008 13:11:51.489709
1009 13:11:51.489808 Set Vref, RX VrefLevel [Byte0]: 43
1010 13:11:51.493248 [Byte1]: 43
1011 13:11:51.497449
1012 13:11:51.497548 Set Vref, RX VrefLevel [Byte0]: 44
1013 13:11:51.500417 [Byte1]: 44
1014 13:11:51.504983
1015 13:11:51.505079 Set Vref, RX VrefLevel [Byte0]: 45
1016 13:11:51.508594 [Byte1]: 45
1017 13:11:51.512671
1018 13:11:51.512774 Set Vref, RX VrefLevel [Byte0]: 46
1019 13:11:51.515819 [Byte1]: 46
1020 13:11:51.520221
1021 13:11:51.520321 Set Vref, RX VrefLevel [Byte0]: 47
1022 13:11:51.523944 [Byte1]: 47
1023 13:11:51.527793
1024 13:11:51.527898 Set Vref, RX VrefLevel [Byte0]: 48
1025 13:11:51.531224 [Byte1]: 48
1026 13:11:51.535376
1027 13:11:51.535490 Set Vref, RX VrefLevel [Byte0]: 49
1028 13:11:51.539141 [Byte1]: 49
1029 13:11:51.542986
1030 13:11:51.543084 Set Vref, RX VrefLevel [Byte0]: 50
1031 13:11:51.546344 [Byte1]: 50
1032 13:11:51.550372
1033 13:11:51.550473 Set Vref, RX VrefLevel [Byte0]: 51
1034 13:11:51.553895 [Byte1]: 51
1035 13:11:51.558479
1036 13:11:51.558581 Set Vref, RX VrefLevel [Byte0]: 52
1037 13:11:51.561700 [Byte1]: 52
1038 13:11:51.565677
1039 13:11:51.565776 Set Vref, RX VrefLevel [Byte0]: 53
1040 13:11:51.569188 [Byte1]: 53
1041 13:11:51.573323
1042 13:11:51.573421 Set Vref, RX VrefLevel [Byte0]: 54
1043 13:11:51.576470 [Byte1]: 54
1044 13:11:51.580763
1045 13:11:51.580858 Set Vref, RX VrefLevel [Byte0]: 55
1046 13:11:51.584254 [Byte1]: 55
1047 13:11:51.588564
1048 13:11:51.588662 Set Vref, RX VrefLevel [Byte0]: 56
1049 13:11:51.592324 [Byte1]: 56
1050 13:11:51.596189
1051 13:11:51.596289 Set Vref, RX VrefLevel [Byte0]: 57
1052 13:11:51.599559 [Byte1]: 57
1053 13:11:51.603802
1054 13:11:51.603900 Set Vref, RX VrefLevel [Byte0]: 58
1055 13:11:51.606990 [Byte1]: 58
1056 13:11:51.611639
1057 13:11:51.611736 Set Vref, RX VrefLevel [Byte0]: 59
1058 13:11:51.614736 [Byte1]: 59
1059 13:11:51.619380
1060 13:11:51.619476 Set Vref, RX VrefLevel [Byte0]: 60
1061 13:11:51.622129 [Byte1]: 60
1062 13:11:51.626706
1063 13:11:51.626808 Set Vref, RX VrefLevel [Byte0]: 61
1064 13:11:51.629915 [Byte1]: 61
1065 13:11:51.633977
1066 13:11:51.634073 Set Vref, RX VrefLevel [Byte0]: 62
1067 13:11:51.637201 [Byte1]: 62
1068 13:11:51.641564
1069 13:11:51.641660 Set Vref, RX VrefLevel [Byte0]: 63
1070 13:11:51.645436 [Byte1]: 63
1071 13:11:51.649656
1072 13:11:51.649753 Set Vref, RX VrefLevel [Byte0]: 64
1073 13:11:51.652393 [Byte1]: 64
1074 13:11:51.657015
1075 13:11:51.657117 Set Vref, RX VrefLevel [Byte0]: 65
1076 13:11:51.660239 [Byte1]: 65
1077 13:11:51.664688
1078 13:11:51.664781 Set Vref, RX VrefLevel [Byte0]: 66
1079 13:11:51.667761 [Byte1]: 66
1080 13:11:51.671869
1081 13:11:51.671946 Set Vref, RX VrefLevel [Byte0]: 67
1082 13:11:51.675243 [Byte1]: 67
1083 13:11:51.679811
1084 13:11:51.679909 Set Vref, RX VrefLevel [Byte0]: 68
1085 13:11:51.683469 [Byte1]: 68
1086 13:11:51.687729
1087 13:11:51.687805 Set Vref, RX VrefLevel [Byte0]: 69
1088 13:11:51.690495 [Byte1]: 69
1089 13:11:51.694987
1090 13:11:51.695090 Set Vref, RX VrefLevel [Byte0]: 70
1091 13:11:51.698364 [Byte1]: 70
1092 13:11:51.702634
1093 13:11:51.702736 Set Vref, RX VrefLevel [Byte0]: 71
1094 13:11:51.705747 [Byte1]: 71
1095 13:11:51.710177
1096 13:11:51.710279 Set Vref, RX VrefLevel [Byte0]: 72
1097 13:11:51.713579 [Byte1]: 72
1098 13:11:51.717472
1099 13:11:51.717566 Set Vref, RX VrefLevel [Byte0]: 73
1100 13:11:51.721040 [Byte1]: 73
1101 13:11:51.725225
1102 13:11:51.725332 Set Vref, RX VrefLevel [Byte0]: 74
1103 13:11:51.728509 [Byte1]: 74
1104 13:11:51.733223
1105 13:11:51.733299 Final RX Vref Byte 0 = 55 to rank0
1106 13:11:51.736045 Final RX Vref Byte 1 = 61 to rank0
1107 13:11:51.739733 Final RX Vref Byte 0 = 55 to rank1
1108 13:11:51.742977 Final RX Vref Byte 1 = 61 to rank1==
1109 13:11:51.746090 Dram Type= 6, Freq= 0, CH_0, rank 0
1110 13:11:51.753084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1111 13:11:51.753227 ==
1112 13:11:51.753287 DQS Delay:
1113 13:11:51.753342 DQS0 = 0, DQS1 = 0
1114 13:11:51.756306 DQM Delay:
1115 13:11:51.756382 DQM0 = 88, DQM1 = 76
1116 13:11:51.759941 DQ Delay:
1117 13:11:51.762852 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1118 13:11:51.762930 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1119 13:11:51.766223 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =76
1120 13:11:51.772512 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1121 13:11:51.772595
1122 13:11:51.772653
1123 13:11:51.779786 [DQSOSCAuto] RK0, (LSB)MR18= 0x342e, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
1124 13:11:51.782798 CH0 RK0: MR19=606, MR18=342E
1125 13:11:51.789003 CH0_RK0: MR19=0x606, MR18=0x342E, DQSOSC=396, MR23=63, INC=94, DEC=62
1126 13:11:51.789183
1127 13:11:51.792580 ----->DramcWriteLeveling(PI) begin...
1128 13:11:51.792693 ==
1129 13:11:51.796023 Dram Type= 6, Freq= 0, CH_0, rank 1
1130 13:11:51.799291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1131 13:11:51.799420 ==
1132 13:11:51.802653 Write leveling (Byte 0): 31 => 31
1133 13:11:51.805895 Write leveling (Byte 1): 27 => 27
1134 13:11:51.809539 DramcWriteLeveling(PI) end<-----
1135 13:11:51.809621
1136 13:11:51.809680 ==
1137 13:11:51.812500 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 13:11:51.815471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 13:11:51.815571 ==
1140 13:11:51.819246 [Gating] SW mode calibration
1141 13:11:51.825779 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1142 13:11:51.832293 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1143 13:11:51.835688 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1144 13:11:51.839078 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1145 13:11:51.845789 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1146 13:11:51.848904 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 13:11:51.852295 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 13:11:51.859039 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 13:11:51.862432 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 13:11:51.906519 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 13:11:51.906871 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 13:11:51.906947 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 13:11:51.907004 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 13:11:51.907416 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 13:11:51.907909 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 13:11:51.908560 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 13:11:51.908931 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 13:11:51.908999 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 13:11:51.909494 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1160 13:11:51.950314 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1161 13:11:51.950989 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1162 13:11:51.951366 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:11:51.951441 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 13:11:51.951901 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 13:11:51.952801 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 13:11:51.953056 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 13:11:51.953782 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 13:11:51.953857 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1169 13:11:51.954713 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
1170 13:11:51.967666 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 13:11:51.967978 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 13:11:51.968505 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 13:11:51.968598 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 13:11:51.971209 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 13:11:51.977711 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 13:11:51.981204 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
1177 13:11:51.984411 0 10 8 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (1 0)
1178 13:11:51.991188 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 13:11:51.994581 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 13:11:51.997770 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 13:11:52.004544 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 13:11:52.007563 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 13:11:52.011137 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 13:11:52.017784 0 11 4 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
1185 13:11:52.020864 0 11 8 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
1186 13:11:52.024002 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 13:11:52.030571 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 13:11:52.034250 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 13:11:52.037349 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 13:11:52.043804 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 13:11:52.047421 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 13:11:52.050856 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1193 13:11:52.056949 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 13:11:52.060479 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 13:11:52.064267 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 13:11:52.070591 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 13:11:52.073980 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 13:11:52.077570 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 13:11:52.083951 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 13:11:52.087281 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 13:11:52.090381 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 13:11:52.097078 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 13:11:52.100290 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 13:11:52.103902 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 13:11:52.107471 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 13:11:52.114162 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:11:52.116899 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1208 13:11:52.120306 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1209 13:11:52.126864 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1210 13:11:52.130472 Total UI for P1: 0, mck2ui 16
1211 13:11:52.133551 best dqsien dly found for B0: ( 0, 14, 2)
1212 13:11:52.136949 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 13:11:52.140384 Total UI for P1: 0, mck2ui 16
1214 13:11:52.143484 best dqsien dly found for B1: ( 0, 14, 8)
1215 13:11:52.146655 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1216 13:11:52.150091 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1217 13:11:52.150189
1218 13:11:52.153703 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1219 13:11:52.156902 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1220 13:11:52.159935 [Gating] SW calibration Done
1221 13:11:52.160037 ==
1222 13:11:52.163525 Dram Type= 6, Freq= 0, CH_0, rank 1
1223 13:11:52.169947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1224 13:11:52.170070 ==
1225 13:11:52.170155 RX Vref Scan: 0
1226 13:11:52.170234
1227 13:11:52.173362 RX Vref 0 -> 0, step: 1
1228 13:11:52.173458
1229 13:11:52.176717 RX Delay -130 -> 252, step: 16
1230 13:11:52.179771 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1231 13:11:52.183084 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1232 13:11:52.186700 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1233 13:11:52.190145 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1234 13:11:52.196680 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1235 13:11:52.200232 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1236 13:11:52.203283 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1237 13:11:52.206978 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1238 13:11:52.209630 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1239 13:11:52.216498 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1240 13:11:52.220396 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1241 13:11:52.223452 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1242 13:11:52.226447 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1243 13:11:52.230258 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1244 13:11:52.236450 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1245 13:11:52.240364 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1246 13:11:52.240447 ==
1247 13:11:52.243582 Dram Type= 6, Freq= 0, CH_0, rank 1
1248 13:11:52.246610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1249 13:11:52.246688 ==
1250 13:11:52.249824 DQS Delay:
1251 13:11:52.249901 DQS0 = 0, DQS1 = 0
1252 13:11:52.249961 DQM Delay:
1253 13:11:52.253595 DQM0 = 85, DQM1 = 75
1254 13:11:52.253674 DQ Delay:
1255 13:11:52.256596 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1256 13:11:52.260274 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
1257 13:11:52.263157 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
1258 13:11:52.266723 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1259 13:11:52.266801
1260 13:11:52.266860
1261 13:11:52.266916 ==
1262 13:11:52.270095 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 13:11:52.276205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 13:11:52.276289 ==
1265 13:11:52.276349
1266 13:11:52.276404
1267 13:11:52.276456 TX Vref Scan disable
1268 13:11:52.279915 == TX Byte 0 ==
1269 13:11:52.283286 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1270 13:11:52.290074 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1271 13:11:52.290157 == TX Byte 1 ==
1272 13:11:52.293303 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1273 13:11:52.296494 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1274 13:11:52.300302 ==
1275 13:11:52.303557 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 13:11:52.306383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 13:11:52.306463 ==
1278 13:11:52.319601 TX Vref=22, minBit 0, minWin=27, winSum=439
1279 13:11:52.322900 TX Vref=24, minBit 0, minWin=27, winSum=444
1280 13:11:52.326682 TX Vref=26, minBit 2, minWin=27, winSum=448
1281 13:11:52.329601 TX Vref=28, minBit 1, minWin=27, winSum=447
1282 13:11:52.333570 TX Vref=30, minBit 2, minWin=27, winSum=450
1283 13:11:52.336481 TX Vref=32, minBit 1, minWin=27, winSum=451
1284 13:11:52.342746 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 32
1285 13:11:52.342827
1286 13:11:52.346140 Final TX Range 1 Vref 32
1287 13:11:52.346218
1288 13:11:52.346277 ==
1289 13:11:52.349306 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 13:11:52.352848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 13:11:52.352925 ==
1292 13:11:52.352984
1293 13:11:52.356071
1294 13:11:52.356147 TX Vref Scan disable
1295 13:11:52.359308 == TX Byte 0 ==
1296 13:11:52.362519 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1297 13:11:52.366070 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1298 13:11:52.369366 == TX Byte 1 ==
1299 13:11:52.372622 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1300 13:11:52.379186 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1301 13:11:52.379272
1302 13:11:52.379330 [DATLAT]
1303 13:11:52.379384 Freq=800, CH0 RK1
1304 13:11:52.379508
1305 13:11:52.382428 DATLAT Default: 0xa
1306 13:11:52.382507 0, 0xFFFF, sum = 0
1307 13:11:52.385707 1, 0xFFFF, sum = 0
1308 13:11:52.385790 2, 0xFFFF, sum = 0
1309 13:11:52.389275 3, 0xFFFF, sum = 0
1310 13:11:52.392394 4, 0xFFFF, sum = 0
1311 13:11:52.392472 5, 0xFFFF, sum = 0
1312 13:11:52.395966 6, 0xFFFF, sum = 0
1313 13:11:52.396044 7, 0xFFFF, sum = 0
1314 13:11:52.399020 8, 0xFFFF, sum = 0
1315 13:11:52.399097 9, 0x0, sum = 1
1316 13:11:52.399157 10, 0x0, sum = 2
1317 13:11:52.402677 11, 0x0, sum = 3
1318 13:11:52.402755 12, 0x0, sum = 4
1319 13:11:52.405593 best_step = 10
1320 13:11:52.405669
1321 13:11:52.405727 ==
1322 13:11:52.409199 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 13:11:52.412468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 13:11:52.412545 ==
1325 13:11:52.415533 RX Vref Scan: 0
1326 13:11:52.415608
1327 13:11:52.415667 RX Vref 0 -> 0, step: 1
1328 13:11:52.418640
1329 13:11:52.418716 RX Delay -111 -> 252, step: 8
1330 13:11:52.425749 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1331 13:11:52.429205 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1332 13:11:52.432504 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1333 13:11:52.435947 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1334 13:11:52.439023 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1335 13:11:52.445989 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1336 13:11:52.449316 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1337 13:11:52.452237 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1338 13:11:52.455650 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1339 13:11:52.459154 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1340 13:11:52.466015 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1341 13:11:52.469039 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1342 13:11:52.472582 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1343 13:11:52.475808 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1344 13:11:52.482350 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1345 13:11:52.485603 iDelay=209, Bit 15, Center 80 (-31 ~ 192) 224
1346 13:11:52.485684 ==
1347 13:11:52.488895 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 13:11:52.492402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 13:11:52.492483 ==
1350 13:11:52.495619 DQS Delay:
1351 13:11:52.495697 DQS0 = 0, DQS1 = 0
1352 13:11:52.495755 DQM Delay:
1353 13:11:52.498918 DQM0 = 86, DQM1 = 76
1354 13:11:52.498993 DQ Delay:
1355 13:11:52.501967 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1356 13:11:52.505524 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1357 13:11:52.508607 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1358 13:11:52.512260 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =80
1359 13:11:52.512339
1360 13:11:52.512397
1361 13:11:52.522329 [DQSOSCAuto] RK1, (LSB)MR18= 0x322e, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1362 13:11:52.522417 CH0 RK1: MR19=606, MR18=322E
1363 13:11:52.528626 CH0_RK1: MR19=0x606, MR18=0x322E, DQSOSC=397, MR23=63, INC=93, DEC=62
1364 13:11:52.532207 [RxdqsGatingPostProcess] freq 800
1365 13:11:52.538650 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1366 13:11:52.542386 Pre-setting of DQS Precalculation
1367 13:11:52.545299 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1368 13:11:52.545379 ==
1369 13:11:52.548972 Dram Type= 6, Freq= 0, CH_1, rank 0
1370 13:11:52.555660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 13:11:52.555752 ==
1372 13:11:52.559087 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1373 13:11:52.565371 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1374 13:11:52.574433 [CA 0] Center 37 (6~68) winsize 63
1375 13:11:52.577736 [CA 1] Center 37 (6~68) winsize 63
1376 13:11:52.580751 [CA 2] Center 34 (4~65) winsize 62
1377 13:11:52.584194 [CA 3] Center 34 (4~65) winsize 62
1378 13:11:52.587463 [CA 4] Center 34 (4~65) winsize 62
1379 13:11:52.591232 [CA 5] Center 33 (3~64) winsize 62
1380 13:11:52.591316
1381 13:11:52.594241 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1382 13:11:52.594318
1383 13:11:52.597818 [CATrainingPosCal] consider 1 rank data
1384 13:11:52.600708 u2DelayCellTimex100 = 270/100 ps
1385 13:11:52.603986 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1386 13:11:52.610791 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1387 13:11:52.614213 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1388 13:11:52.617862 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1389 13:11:52.620826 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1390 13:11:52.624338 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1391 13:11:52.624417
1392 13:11:52.627438 CA PerBit enable=1, Macro0, CA PI delay=33
1393 13:11:52.627550
1394 13:11:52.631380 [CBTSetCACLKResult] CA Dly = 33
1395 13:11:52.631457 CS Dly: 4 (0~35)
1396 13:11:52.634336 ==
1397 13:11:52.637237 Dram Type= 6, Freq= 0, CH_1, rank 1
1398 13:11:52.640654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1399 13:11:52.640738 ==
1400 13:11:52.643924 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1401 13:11:52.650509 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1402 13:11:52.660439 [CA 0] Center 36 (6~67) winsize 62
1403 13:11:52.664108 [CA 1] Center 36 (6~67) winsize 62
1404 13:11:52.667077 [CA 2] Center 34 (4~65) winsize 62
1405 13:11:52.670417 [CA 3] Center 33 (3~64) winsize 62
1406 13:11:52.674138 [CA 4] Center 34 (3~65) winsize 63
1407 13:11:52.677273 [CA 5] Center 34 (3~65) winsize 63
1408 13:11:52.677353
1409 13:11:52.680467 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1410 13:11:52.680545
1411 13:11:52.683521 [CATrainingPosCal] consider 2 rank data
1412 13:11:52.687253 u2DelayCellTimex100 = 270/100 ps
1413 13:11:52.690539 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1414 13:11:52.696944 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1415 13:11:52.700316 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1416 13:11:52.703808 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1417 13:11:52.706923 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1418 13:11:52.710366 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1419 13:11:52.710477
1420 13:11:52.713774 CA PerBit enable=1, Macro0, CA PI delay=33
1421 13:11:52.713870
1422 13:11:52.716737 [CBTSetCACLKResult] CA Dly = 33
1423 13:11:52.720385 CS Dly: 5 (0~37)
1424 13:11:52.720481
1425 13:11:52.723275 ----->DramcWriteLeveling(PI) begin...
1426 13:11:52.723374 ==
1427 13:11:52.726733 Dram Type= 6, Freq= 0, CH_1, rank 0
1428 13:11:52.729648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1429 13:11:52.729746 ==
1430 13:11:52.733281 Write leveling (Byte 0): 28 => 28
1431 13:11:52.736522 Write leveling (Byte 1): 28 => 28
1432 13:11:52.739772 DramcWriteLeveling(PI) end<-----
1433 13:11:52.739869
1434 13:11:52.739952 ==
1435 13:11:52.743004 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 13:11:52.746490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 13:11:52.746572 ==
1438 13:11:52.749667 [Gating] SW mode calibration
1439 13:11:52.756371 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1440 13:11:52.763282 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1441 13:11:52.766125 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1442 13:11:52.769764 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1443 13:11:52.776045 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1444 13:11:52.779548 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 13:11:52.782466 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 13:11:52.789434 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 13:11:52.792491 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 13:11:52.795811 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 13:11:52.803188 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 13:11:52.805970 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 13:11:52.809422 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 13:11:52.815714 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 13:11:52.819016 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 13:11:52.822387 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 13:11:52.829185 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:11:52.832211 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 13:11:52.835949 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1458 13:11:52.842427 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1459 13:11:52.845586 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 13:11:52.849200 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 13:11:52.855561 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 13:11:52.859178 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 13:11:52.862648 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 13:11:52.868678 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 13:11:52.872092 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 13:11:52.875515 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1467 13:11:52.881862 0 9 8 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
1468 13:11:52.885332 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 13:11:52.888866 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 13:11:52.892285 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 13:11:52.898822 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 13:11:52.902420 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 13:11:52.905113 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1474 13:11:52.912353 0 10 4 | B1->B0 | 3131 2f2f | 1 1 | (1 0) (1 0)
1475 13:11:52.915209 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1476 13:11:52.918456 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 13:11:52.925116 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 13:11:52.928466 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 13:11:52.932104 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 13:11:52.938685 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 13:11:52.941584 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 13:11:52.945089 0 11 4 | B1->B0 | 2727 3030 | 0 0 | (0 0) (0 0)
1483 13:11:52.951670 0 11 8 | B1->B0 | 3d3d 4141 | 1 0 | (0 0) (0 0)
1484 13:11:52.954976 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 13:11:52.958392 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 13:11:52.964739 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 13:11:52.968488 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 13:11:52.971680 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 13:11:52.978170 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 13:11:52.981649 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1491 13:11:52.984548 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1492 13:11:52.991734 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 13:11:52.994896 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 13:11:52.997846 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 13:11:53.004813 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 13:11:53.007767 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 13:11:53.011517 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 13:11:53.017846 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 13:11:53.021041 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 13:11:53.024331 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 13:11:53.031206 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 13:11:53.034303 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 13:11:53.037672 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 13:11:53.044572 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 13:11:53.047597 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1506 13:11:53.051161 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 13:11:53.054682 Total UI for P1: 0, mck2ui 16
1508 13:11:53.057808 best dqsien dly found for B0: ( 0, 14, 0)
1509 13:11:53.061067 Total UI for P1: 0, mck2ui 16
1510 13:11:53.064552 best dqsien dly found for B1: ( 0, 14, 2)
1511 13:11:53.067187 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1512 13:11:53.070564 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1513 13:11:53.070651
1514 13:11:53.077432 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1515 13:11:53.080589 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1516 13:11:53.080668 [Gating] SW calibration Done
1517 13:11:53.084262 ==
1518 13:11:53.086889 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 13:11:53.090640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1520 13:11:53.090717 ==
1521 13:11:53.090777 RX Vref Scan: 0
1522 13:11:53.090832
1523 13:11:53.094178 RX Vref 0 -> 0, step: 1
1524 13:11:53.094253
1525 13:11:53.097320 RX Delay -130 -> 252, step: 16
1526 13:11:53.100201 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1527 13:11:53.103778 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1528 13:11:53.110386 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1529 13:11:53.113704 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1530 13:11:53.117036 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1531 13:11:53.120522 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1532 13:11:53.123656 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1533 13:11:53.130538 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1534 13:11:53.133744 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1535 13:11:53.137049 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1536 13:11:53.140814 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1537 13:11:53.143497 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1538 13:11:53.150084 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1539 13:11:53.153779 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1540 13:11:53.157281 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1541 13:11:53.159995 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1542 13:11:53.160071 ==
1543 13:11:53.163507 Dram Type= 6, Freq= 0, CH_1, rank 0
1544 13:11:53.170113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1545 13:11:53.170206 ==
1546 13:11:53.170267 DQS Delay:
1547 13:11:53.173450 DQS0 = 0, DQS1 = 0
1548 13:11:53.173526 DQM Delay:
1549 13:11:53.173584 DQM0 = 88, DQM1 = 84
1550 13:11:53.176766 DQ Delay:
1551 13:11:53.180140 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1552 13:11:53.183358 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1553 13:11:53.186631 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1554 13:11:53.190207 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1555 13:11:53.190283
1556 13:11:53.190341
1557 13:11:53.190394 ==
1558 13:11:53.193532 Dram Type= 6, Freq= 0, CH_1, rank 0
1559 13:11:53.196771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1560 13:11:53.196847 ==
1561 13:11:53.196906
1562 13:11:53.196959
1563 13:11:53.200022 TX Vref Scan disable
1564 13:11:53.200098 == TX Byte 0 ==
1565 13:11:53.206496 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1566 13:11:53.210109 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1567 13:11:53.212899 == TX Byte 1 ==
1568 13:11:53.216738 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1569 13:11:53.219713 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1570 13:11:53.219789 ==
1571 13:11:53.223106 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 13:11:53.226220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 13:11:53.226298 ==
1574 13:11:53.240557 TX Vref=22, minBit 4, minWin=26, winSum=441
1575 13:11:53.243863 TX Vref=24, minBit 5, minWin=27, winSum=449
1576 13:11:53.247598 TX Vref=26, minBit 0, minWin=28, winSum=452
1577 13:11:53.250240 TX Vref=28, minBit 1, minWin=27, winSum=455
1578 13:11:53.253768 TX Vref=30, minBit 1, minWin=27, winSum=454
1579 13:11:53.260635 TX Vref=32, minBit 1, minWin=27, winSum=452
1580 13:11:53.264155 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 26
1581 13:11:53.264233
1582 13:11:53.267559 Final TX Range 1 Vref 26
1583 13:11:53.267635
1584 13:11:53.267693 ==
1585 13:11:53.270435 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 13:11:53.273892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 13:11:53.273967 ==
1588 13:11:53.277070
1589 13:11:53.277193
1590 13:11:53.277266 TX Vref Scan disable
1591 13:11:53.280095 == TX Byte 0 ==
1592 13:11:53.284082 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1593 13:11:53.286994 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1594 13:11:53.290992 == TX Byte 1 ==
1595 13:11:53.293598 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1596 13:11:53.297264 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1597 13:11:53.300585
1598 13:11:53.300659 [DATLAT]
1599 13:11:53.300717 Freq=800, CH1 RK0
1600 13:11:53.300772
1601 13:11:53.303523 DATLAT Default: 0xa
1602 13:11:53.303598 0, 0xFFFF, sum = 0
1603 13:11:53.307196 1, 0xFFFF, sum = 0
1604 13:11:53.307298 2, 0xFFFF, sum = 0
1605 13:11:53.310803 3, 0xFFFF, sum = 0
1606 13:11:53.310879 4, 0xFFFF, sum = 0
1607 13:11:53.313586 5, 0xFFFF, sum = 0
1608 13:11:53.316834 6, 0xFFFF, sum = 0
1609 13:11:53.316911 7, 0xFFFF, sum = 0
1610 13:11:53.320488 8, 0xFFFF, sum = 0
1611 13:11:53.320565 9, 0x0, sum = 1
1612 13:11:53.320624 10, 0x0, sum = 2
1613 13:11:53.323648 11, 0x0, sum = 3
1614 13:11:53.323724 12, 0x0, sum = 4
1615 13:11:53.327200 best_step = 10
1616 13:11:53.327300
1617 13:11:53.327383 ==
1618 13:11:53.330189 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 13:11:53.333537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 13:11:53.333613 ==
1621 13:11:53.336751 RX Vref Scan: 1
1622 13:11:53.336849
1623 13:11:53.336935 Set Vref Range= 32 -> 127
1624 13:11:53.340468
1625 13:11:53.340544 RX Vref 32 -> 127, step: 1
1626 13:11:53.340603
1627 13:11:53.343565 RX Delay -95 -> 252, step: 8
1628 13:11:53.343640
1629 13:11:53.347022 Set Vref, RX VrefLevel [Byte0]: 32
1630 13:11:53.350132 [Byte1]: 32
1631 13:11:53.350231
1632 13:11:53.353363 Set Vref, RX VrefLevel [Byte0]: 33
1633 13:11:53.356634 [Byte1]: 33
1634 13:11:53.360794
1635 13:11:53.360875 Set Vref, RX VrefLevel [Byte0]: 34
1636 13:11:53.363843 [Byte1]: 34
1637 13:11:53.368469
1638 13:11:53.368544 Set Vref, RX VrefLevel [Byte0]: 35
1639 13:11:53.371711 [Byte1]: 35
1640 13:11:53.375943
1641 13:11:53.376017 Set Vref, RX VrefLevel [Byte0]: 36
1642 13:11:53.379538 [Byte1]: 36
1643 13:11:53.383638
1644 13:11:53.383713 Set Vref, RX VrefLevel [Byte0]: 37
1645 13:11:53.386916 [Byte1]: 37
1646 13:11:53.391077
1647 13:11:53.391153 Set Vref, RX VrefLevel [Byte0]: 38
1648 13:11:53.394106 [Byte1]: 38
1649 13:11:53.398894
1650 13:11:53.398969 Set Vref, RX VrefLevel [Byte0]: 39
1651 13:11:53.401944 [Byte1]: 39
1652 13:11:53.406244
1653 13:11:53.406321 Set Vref, RX VrefLevel [Byte0]: 40
1654 13:11:53.409544 [Byte1]: 40
1655 13:11:53.413868
1656 13:11:53.413944 Set Vref, RX VrefLevel [Byte0]: 41
1657 13:11:53.417365 [Byte1]: 41
1658 13:11:53.421623
1659 13:11:53.421699 Set Vref, RX VrefLevel [Byte0]: 42
1660 13:11:53.424529 [Byte1]: 42
1661 13:11:53.428932
1662 13:11:53.429032 Set Vref, RX VrefLevel [Byte0]: 43
1663 13:11:53.432437 [Byte1]: 43
1664 13:11:53.436603
1665 13:11:53.436689 Set Vref, RX VrefLevel [Byte0]: 44
1666 13:11:53.440008 [Byte1]: 44
1667 13:11:53.444191
1668 13:11:53.444299 Set Vref, RX VrefLevel [Byte0]: 45
1669 13:11:53.447664 [Byte1]: 45
1670 13:11:53.452023
1671 13:11:53.452119 Set Vref, RX VrefLevel [Byte0]: 46
1672 13:11:53.455210 [Byte1]: 46
1673 13:11:53.459650
1674 13:11:53.459727 Set Vref, RX VrefLevel [Byte0]: 47
1675 13:11:53.462525 [Byte1]: 47
1676 13:11:53.467219
1677 13:11:53.467297 Set Vref, RX VrefLevel [Byte0]: 48
1678 13:11:53.470690 [Byte1]: 48
1679 13:11:53.474832
1680 13:11:53.474908 Set Vref, RX VrefLevel [Byte0]: 49
1681 13:11:53.477653 [Byte1]: 49
1682 13:11:53.482438
1683 13:11:53.482517 Set Vref, RX VrefLevel [Byte0]: 50
1684 13:11:53.485839 [Byte1]: 50
1685 13:11:53.489711
1686 13:11:53.489787 Set Vref, RX VrefLevel [Byte0]: 51
1687 13:11:53.492874 [Byte1]: 51
1688 13:11:53.497972
1689 13:11:53.498048 Set Vref, RX VrefLevel [Byte0]: 52
1690 13:11:53.500840 [Byte1]: 52
1691 13:11:53.505002
1692 13:11:53.505077 Set Vref, RX VrefLevel [Byte0]: 53
1693 13:11:53.508056 [Byte1]: 53
1694 13:11:53.512584
1695 13:11:53.512660 Set Vref, RX VrefLevel [Byte0]: 54
1696 13:11:53.515956 [Byte1]: 54
1697 13:11:53.520218
1698 13:11:53.520294 Set Vref, RX VrefLevel [Byte0]: 55
1699 13:11:53.523412 [Byte1]: 55
1700 13:11:53.527671
1701 13:11:53.527749 Set Vref, RX VrefLevel [Byte0]: 56
1702 13:11:53.531282 [Byte1]: 56
1703 13:11:53.535293
1704 13:11:53.535393 Set Vref, RX VrefLevel [Byte0]: 57
1705 13:11:53.538991 [Byte1]: 57
1706 13:11:53.542829
1707 13:11:53.542907 Set Vref, RX VrefLevel [Byte0]: 58
1708 13:11:53.546347 [Byte1]: 58
1709 13:11:53.550534
1710 13:11:53.550633 Set Vref, RX VrefLevel [Byte0]: 59
1711 13:11:53.553695 [Byte1]: 59
1712 13:11:53.558406
1713 13:11:53.558483 Set Vref, RX VrefLevel [Byte0]: 60
1714 13:11:53.561534 [Byte1]: 60
1715 13:11:53.565606
1716 13:11:53.565694 Set Vref, RX VrefLevel [Byte0]: 61
1717 13:11:53.569037 [Byte1]: 61
1718 13:11:53.573420
1719 13:11:53.573519 Set Vref, RX VrefLevel [Byte0]: 62
1720 13:11:53.576920 [Byte1]: 62
1721 13:11:53.580731
1722 13:11:53.580801 Set Vref, RX VrefLevel [Byte0]: 63
1723 13:11:53.584301 [Byte1]: 63
1724 13:11:53.588960
1725 13:11:53.589036 Set Vref, RX VrefLevel [Byte0]: 64
1726 13:11:53.592197 [Byte1]: 64
1727 13:11:53.596183
1728 13:11:53.596258 Set Vref, RX VrefLevel [Byte0]: 65
1729 13:11:53.599816 [Byte1]: 65
1730 13:11:53.603840
1731 13:11:53.603915 Set Vref, RX VrefLevel [Byte0]: 66
1732 13:11:53.606904 [Byte1]: 66
1733 13:11:53.611641
1734 13:11:53.611716 Set Vref, RX VrefLevel [Byte0]: 67
1735 13:11:53.614489 [Byte1]: 67
1736 13:11:53.619112
1737 13:11:53.619196 Set Vref, RX VrefLevel [Byte0]: 68
1738 13:11:53.622602 [Byte1]: 68
1739 13:11:53.626549
1740 13:11:53.626626 Set Vref, RX VrefLevel [Byte0]: 69
1741 13:11:53.629944 [Byte1]: 69
1742 13:11:53.634124
1743 13:11:53.634200 Set Vref, RX VrefLevel [Byte0]: 70
1744 13:11:53.637610 [Byte1]: 70
1745 13:11:53.641637
1746 13:11:53.641713 Set Vref, RX VrefLevel [Byte0]: 71
1747 13:11:53.645102 [Byte1]: 71
1748 13:11:53.649529
1749 13:11:53.649605 Set Vref, RX VrefLevel [Byte0]: 72
1750 13:11:53.652466 [Byte1]: 72
1751 13:11:53.657315
1752 13:11:53.657396 Set Vref, RX VrefLevel [Byte0]: 73
1753 13:11:53.660377 [Byte1]: 73
1754 13:11:53.665074
1755 13:11:53.665205 Final RX Vref Byte 0 = 59 to rank0
1756 13:11:53.668151 Final RX Vref Byte 1 = 52 to rank0
1757 13:11:53.671470 Final RX Vref Byte 0 = 59 to rank1
1758 13:11:53.674642 Final RX Vref Byte 1 = 52 to rank1==
1759 13:11:53.677969 Dram Type= 6, Freq= 0, CH_1, rank 0
1760 13:11:53.684554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1761 13:11:53.684641 ==
1762 13:11:53.684701 DQS Delay:
1763 13:11:53.684754 DQS0 = 0, DQS1 = 0
1764 13:11:53.687724 DQM Delay:
1765 13:11:53.687799 DQM0 = 85, DQM1 = 79
1766 13:11:53.691094 DQ Delay:
1767 13:11:53.694746 DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =84
1768 13:11:53.694823 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =80
1769 13:11:53.698003 DQ8 =64, DQ9 =68, DQ10 =80, DQ11 =76
1770 13:11:53.704499 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1771 13:11:53.704576
1772 13:11:53.704633
1773 13:11:53.711332 [DQSOSCAuto] RK0, (LSB)MR18= 0x2235, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
1774 13:11:53.714311 CH1 RK0: MR19=606, MR18=2235
1775 13:11:53.721591 CH1_RK0: MR19=0x606, MR18=0x2235, DQSOSC=396, MR23=63, INC=94, DEC=62
1776 13:11:53.721671
1777 13:11:53.724515 ----->DramcWriteLeveling(PI) begin...
1778 13:11:53.724591 ==
1779 13:11:53.727726 Dram Type= 6, Freq= 0, CH_1, rank 1
1780 13:11:53.731344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1781 13:11:53.731421 ==
1782 13:11:53.734327 Write leveling (Byte 0): 25 => 25
1783 13:11:53.737668 Write leveling (Byte 1): 27 => 27
1784 13:11:53.741575 DramcWriteLeveling(PI) end<-----
1785 13:11:53.741652
1786 13:11:53.741710 ==
1787 13:11:53.744296 Dram Type= 6, Freq= 0, CH_1, rank 1
1788 13:11:53.747438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1789 13:11:53.747513 ==
1790 13:11:53.751108 [Gating] SW mode calibration
1791 13:11:53.757442 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1792 13:11:53.763966 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1793 13:11:53.767696 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1794 13:11:53.770706 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1795 13:11:53.777214 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1796 13:11:53.780902 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1797 13:11:53.783728 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1798 13:11:53.790470 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 13:11:53.793815 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 13:11:53.797299 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 13:11:53.803939 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 13:11:53.807401 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 13:11:53.810553 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 13:11:53.816992 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 13:11:53.820390 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 13:11:53.823927 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 13:11:53.830490 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 13:11:53.833646 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 13:11:53.836801 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 13:11:53.843811 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1811 13:11:53.846812 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1812 13:11:53.850585 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 13:11:53.857389 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 13:11:53.860093 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 13:11:53.863655 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 13:11:53.869882 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 13:11:53.873172 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 13:11:53.876865 0 9 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
1819 13:11:53.883391 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1820 13:11:53.886796 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1821 13:11:53.889809 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1822 13:11:53.897073 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1823 13:11:53.900246 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 13:11:53.903325 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 13:11:53.910358 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1826 13:11:53.913279 0 10 4 | B1->B0 | 3333 2b2b | 0 1 | (0 0) (1 0)
1827 13:11:53.916758 0 10 8 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
1828 13:11:53.923281 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 13:11:53.926681 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 13:11:53.930165 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 13:11:53.933651 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 13:11:53.939661 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 13:11:53.943151 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 13:11:53.946691 0 11 4 | B1->B0 | 2727 3a3a | 0 0 | (0 0) (0 0)
1835 13:11:53.953351 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1836 13:11:53.956486 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1837 13:11:53.960119 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1838 13:11:53.966822 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1839 13:11:53.969539 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 13:11:53.973370 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 13:11:53.979786 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1842 13:11:53.982953 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1843 13:11:53.986387 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1844 13:11:53.993080 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1845 13:11:53.996262 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1846 13:11:53.999987 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 13:11:54.006448 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 13:11:54.009644 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 13:11:54.012785 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 13:11:54.019572 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 13:11:54.022623 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 13:11:54.026112 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 13:11:54.032464 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 13:11:54.036373 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 13:11:54.039538 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 13:11:54.046314 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 13:11:54.049075 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1858 13:11:54.052449 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 13:11:54.055663 Total UI for P1: 0, mck2ui 16
1860 13:11:54.059197 best dqsien dly found for B0: ( 0, 14, 0)
1861 13:11:54.062647 Total UI for P1: 0, mck2ui 16
1862 13:11:54.065880 best dqsien dly found for B1: ( 0, 14, 2)
1863 13:11:54.069084 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1864 13:11:54.072311 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1865 13:11:54.072409
1866 13:11:54.075801 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1867 13:11:54.082572 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1868 13:11:54.082699 [Gating] SW calibration Done
1869 13:11:54.082797 ==
1870 13:11:54.085557 Dram Type= 6, Freq= 0, CH_1, rank 1
1871 13:11:54.092356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1872 13:11:54.092442 ==
1873 13:11:54.092502 RX Vref Scan: 0
1874 13:11:54.092558
1875 13:11:54.095553 RX Vref 0 -> 0, step: 1
1876 13:11:54.095629
1877 13:11:54.099178 RX Delay -130 -> 252, step: 16
1878 13:11:54.102302 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1879 13:11:54.105729 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1880 13:11:54.108735 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1881 13:11:54.115454 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1882 13:11:54.119066 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1883 13:11:54.122124 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1884 13:11:54.125343 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1885 13:11:54.129003 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1886 13:11:54.135144 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1887 13:11:54.138929 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1888 13:11:54.141844 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1889 13:11:54.145663 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1890 13:11:54.151979 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1891 13:11:54.155455 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1892 13:11:54.158558 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1893 13:11:54.162409 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1894 13:11:54.162519 ==
1895 13:11:54.165075 Dram Type= 6, Freq= 0, CH_1, rank 1
1896 13:11:54.168500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1897 13:11:54.172044 ==
1898 13:11:54.172122 DQS Delay:
1899 13:11:54.172181 DQS0 = 0, DQS1 = 0
1900 13:11:54.175612 DQM Delay:
1901 13:11:54.175688 DQM0 = 83, DQM1 = 79
1902 13:11:54.178860 DQ Delay:
1903 13:11:54.178939 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1904 13:11:54.182117 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1905 13:11:54.185405 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1906 13:11:54.188585 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1907 13:11:54.191599
1908 13:11:54.191693
1909 13:11:54.191767 ==
1910 13:11:54.195271 Dram Type= 6, Freq= 0, CH_1, rank 1
1911 13:11:54.198805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1912 13:11:54.198893 ==
1913 13:11:54.198989
1914 13:11:54.199085
1915 13:11:54.202095 TX Vref Scan disable
1916 13:11:54.202189 == TX Byte 0 ==
1917 13:11:54.205450 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1918 13:11:54.211935 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1919 13:11:54.212017 == TX Byte 1 ==
1920 13:11:54.218580 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1921 13:11:54.221876 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1922 13:11:54.221957 ==
1923 13:11:54.225494 Dram Type= 6, Freq= 0, CH_1, rank 1
1924 13:11:54.228591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1925 13:11:54.228669 ==
1926 13:11:54.242386 TX Vref=22, minBit 0, minWin=27, winSum=445
1927 13:11:54.245984 TX Vref=24, minBit 1, minWin=27, winSum=447
1928 13:11:54.248758 TX Vref=26, minBit 0, minWin=27, winSum=451
1929 13:11:54.252366 TX Vref=28, minBit 6, minWin=27, winSum=455
1930 13:11:54.255352 TX Vref=30, minBit 0, minWin=28, winSum=456
1931 13:11:54.262297 TX Vref=32, minBit 0, minWin=28, winSum=455
1932 13:11:54.265480 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
1933 13:11:54.265559
1934 13:11:54.268540 Final TX Range 1 Vref 30
1935 13:11:54.268616
1936 13:11:54.268675 ==
1937 13:11:54.271956 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 13:11:54.275424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 13:11:54.275502 ==
1940 13:11:54.275561
1941 13:11:54.278744
1942 13:11:54.278821 TX Vref Scan disable
1943 13:11:54.281652 == TX Byte 0 ==
1944 13:11:54.285191 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1945 13:11:54.291957 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1946 13:11:54.292038 == TX Byte 1 ==
1947 13:11:54.295118 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1948 13:11:54.301895 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1949 13:11:54.301974
1950 13:11:54.302033 [DATLAT]
1951 13:11:54.302088 Freq=800, CH1 RK1
1952 13:11:54.302140
1953 13:11:54.305668 DATLAT Default: 0xa
1954 13:11:54.305745 0, 0xFFFF, sum = 0
1955 13:11:54.308762 1, 0xFFFF, sum = 0
1956 13:11:54.308841 2, 0xFFFF, sum = 0
1957 13:11:54.311944 3, 0xFFFF, sum = 0
1958 13:11:54.315424 4, 0xFFFF, sum = 0
1959 13:11:54.315501 5, 0xFFFF, sum = 0
1960 13:11:54.318269 6, 0xFFFF, sum = 0
1961 13:11:54.318347 7, 0xFFFF, sum = 0
1962 13:11:54.321795 8, 0xFFFF, sum = 0
1963 13:11:54.321873 9, 0x0, sum = 1
1964 13:11:54.325014 10, 0x0, sum = 2
1965 13:11:54.325092 11, 0x0, sum = 3
1966 13:11:54.325212 12, 0x0, sum = 4
1967 13:11:54.328649 best_step = 10
1968 13:11:54.328726
1969 13:11:54.328785 ==
1970 13:11:54.331751 Dram Type= 6, Freq= 0, CH_1, rank 1
1971 13:11:54.335057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1972 13:11:54.335134 ==
1973 13:11:54.338135 RX Vref Scan: 0
1974 13:11:54.338212
1975 13:11:54.338270 RX Vref 0 -> 0, step: 1
1976 13:11:54.341407
1977 13:11:54.341483 RX Delay -95 -> 252, step: 8
1978 13:11:54.348471 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1979 13:11:54.352010 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1980 13:11:54.355196 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1981 13:11:54.358712 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1982 13:11:54.361854 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1983 13:11:54.368474 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1984 13:11:54.371713 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1985 13:11:54.375059 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1986 13:11:54.378589 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1987 13:11:54.382239 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1988 13:11:54.388464 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1989 13:11:54.391541 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1990 13:11:54.395038 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1991 13:11:54.398408 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1992 13:11:54.404622 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1993 13:11:54.408287 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1994 13:11:54.408416 ==
1995 13:11:54.411427 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 13:11:54.414797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 13:11:54.414875 ==
1998 13:11:54.417991 DQS Delay:
1999 13:11:54.418067 DQS0 = 0, DQS1 = 0
2000 13:11:54.418125 DQM Delay:
2001 13:11:54.421854 DQM0 = 86, DQM1 = 81
2002 13:11:54.421932 DQ Delay:
2003 13:11:54.424742 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
2004 13:11:54.428555 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2005 13:11:54.431445 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
2006 13:11:54.434744 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =88
2007 13:11:54.434820
2008 13:11:54.434878
2009 13:11:54.444874 [DQSOSCAuto] RK1, (LSB)MR18= 0x2541, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
2010 13:11:54.444954 CH1 RK1: MR19=606, MR18=2541
2011 13:11:54.451431 CH1_RK1: MR19=0x606, MR18=0x2541, DQSOSC=393, MR23=63, INC=95, DEC=63
2012 13:11:54.454557 [RxdqsGatingPostProcess] freq 800
2013 13:11:54.461111 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2014 13:11:54.464418 Pre-setting of DQS Precalculation
2015 13:11:54.467752 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2016 13:11:54.474848 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2017 13:11:54.484593 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2018 13:11:54.484687
2019 13:11:54.484748
2020 13:11:54.487990 [Calibration Summary] 1600 Mbps
2021 13:11:54.488068 CH 0, Rank 0
2022 13:11:54.491265 SW Impedance : PASS
2023 13:11:54.491344 DUTY Scan : NO K
2024 13:11:54.494435 ZQ Calibration : PASS
2025 13:11:54.494514 Jitter Meter : NO K
2026 13:11:54.498163 CBT Training : PASS
2027 13:11:54.501131 Write leveling : PASS
2028 13:11:54.501247 RX DQS gating : PASS
2029 13:11:54.504327 RX DQ/DQS(RDDQC) : PASS
2030 13:11:54.507558 TX DQ/DQS : PASS
2031 13:11:54.507636 RX DATLAT : PASS
2032 13:11:54.510862 RX DQ/DQS(Engine): PASS
2033 13:11:54.514809 TX OE : NO K
2034 13:11:54.514886 All Pass.
2035 13:11:54.514944
2036 13:11:54.514998 CH 0, Rank 1
2037 13:11:54.517819 SW Impedance : PASS
2038 13:11:54.520922 DUTY Scan : NO K
2039 13:11:54.520999 ZQ Calibration : PASS
2040 13:11:54.524405 Jitter Meter : NO K
2041 13:11:54.527747 CBT Training : PASS
2042 13:11:54.527824 Write leveling : PASS
2043 13:11:54.530994 RX DQS gating : PASS
2044 13:11:54.534541 RX DQ/DQS(RDDQC) : PASS
2045 13:11:54.534619 TX DQ/DQS : PASS
2046 13:11:54.537605 RX DATLAT : PASS
2047 13:11:54.537682 RX DQ/DQS(Engine): PASS
2048 13:11:54.541347 TX OE : NO K
2049 13:11:54.541425 All Pass.
2050 13:11:54.541484
2051 13:11:54.544503 CH 1, Rank 0
2052 13:11:54.544579 SW Impedance : PASS
2053 13:11:54.547544 DUTY Scan : NO K
2054 13:11:54.551178 ZQ Calibration : PASS
2055 13:11:54.551255 Jitter Meter : NO K
2056 13:11:54.554412 CBT Training : PASS
2057 13:11:54.557900 Write leveling : PASS
2058 13:11:54.557979 RX DQS gating : PASS
2059 13:11:54.560805 RX DQ/DQS(RDDQC) : PASS
2060 13:11:54.564755 TX DQ/DQS : PASS
2061 13:11:54.564856 RX DATLAT : PASS
2062 13:11:54.567367 RX DQ/DQS(Engine): PASS
2063 13:11:54.570942 TX OE : NO K
2064 13:11:54.571019 All Pass.
2065 13:11:54.571076
2066 13:11:54.571129 CH 1, Rank 1
2067 13:11:54.574561 SW Impedance : PASS
2068 13:11:54.577957 DUTY Scan : NO K
2069 13:11:54.578034 ZQ Calibration : PASS
2070 13:11:54.580788 Jitter Meter : NO K
2071 13:11:54.584398 CBT Training : PASS
2072 13:11:54.584474 Write leveling : PASS
2073 13:11:54.587586 RX DQS gating : PASS
2074 13:11:54.587663 RX DQ/DQS(RDDQC) : PASS
2075 13:11:54.590749 TX DQ/DQS : PASS
2076 13:11:54.594626 RX DATLAT : PASS
2077 13:11:54.594701 RX DQ/DQS(Engine): PASS
2078 13:11:54.597793 TX OE : NO K
2079 13:11:54.597869 All Pass.
2080 13:11:54.597927
2081 13:11:54.600773 DramC Write-DBI off
2082 13:11:54.604163 PER_BANK_REFRESH: Hybrid Mode
2083 13:11:54.604239 TX_TRACKING: ON
2084 13:11:54.607548 [GetDramInforAfterCalByMRR] Vendor 6.
2085 13:11:54.610844 [GetDramInforAfterCalByMRR] Revision 606.
2086 13:11:54.617208 [GetDramInforAfterCalByMRR] Revision 2 0.
2087 13:11:54.617288 MR0 0x3b3b
2088 13:11:54.617347 MR8 0x5151
2089 13:11:54.621098 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2090 13:11:54.621212
2091 13:11:54.623890 MR0 0x3b3b
2092 13:11:54.623965 MR8 0x5151
2093 13:11:54.627438 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2094 13:11:54.627514
2095 13:11:54.637125 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2096 13:11:54.640813 [FAST_K] Save calibration result to emmc
2097 13:11:54.643845 [FAST_K] Save calibration result to emmc
2098 13:11:54.647147 dram_init: config_dvfs: 1
2099 13:11:54.650597 dramc_set_vcore_voltage set vcore to 662500
2100 13:11:54.650677 Read voltage for 1200, 2
2101 13:11:54.653707 Vio18 = 0
2102 13:11:54.653811 Vcore = 662500
2103 13:11:54.653897 Vdram = 0
2104 13:11:54.656985 Vddq = 0
2105 13:11:54.657062 Vmddr = 0
2106 13:11:54.664069 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2107 13:11:54.667181 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2108 13:11:54.670350 MEM_TYPE=3, freq_sel=15
2109 13:11:54.673549 sv_algorithm_assistance_LP4_1600
2110 13:11:54.677398 ============ PULL DRAM RESETB DOWN ============
2111 13:11:54.680461 ========== PULL DRAM RESETB DOWN end =========
2112 13:11:54.686996 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2113 13:11:54.690563 ===================================
2114 13:11:54.690641 LPDDR4 DRAM CONFIGURATION
2115 13:11:54.693818 ===================================
2116 13:11:54.697080 EX_ROW_EN[0] = 0x0
2117 13:11:54.697221 EX_ROW_EN[1] = 0x0
2118 13:11:54.700578 LP4Y_EN = 0x0
2119 13:11:54.703800 WORK_FSP = 0x0
2120 13:11:54.703883 WL = 0x4
2121 13:11:54.707484 RL = 0x4
2122 13:11:54.707561 BL = 0x2
2123 13:11:54.710519 RPST = 0x0
2124 13:11:54.710598 RD_PRE = 0x0
2125 13:11:54.713887 WR_PRE = 0x1
2126 13:11:54.713966 WR_PST = 0x0
2127 13:11:54.717081 DBI_WR = 0x0
2128 13:11:54.717201 DBI_RD = 0x0
2129 13:11:54.720189 OTF = 0x1
2130 13:11:54.723787 ===================================
2131 13:11:54.726676 ===================================
2132 13:11:54.726777 ANA top config
2133 13:11:54.730263 ===================================
2134 13:11:54.733547 DLL_ASYNC_EN = 0
2135 13:11:54.736791 ALL_SLAVE_EN = 0
2136 13:11:54.736916 NEW_RANK_MODE = 1
2137 13:11:54.740102 DLL_IDLE_MODE = 1
2138 13:11:54.743463 LP45_APHY_COMB_EN = 1
2139 13:11:54.746791 TX_ODT_DIS = 1
2140 13:11:54.750077 NEW_8X_MODE = 1
2141 13:11:54.753913 ===================================
2142 13:11:54.756748 ===================================
2143 13:11:54.756826 data_rate = 2400
2144 13:11:54.760278 CKR = 1
2145 13:11:54.763997 DQ_P2S_RATIO = 8
2146 13:11:54.766658 ===================================
2147 13:11:54.770589 CA_P2S_RATIO = 8
2148 13:11:54.773474 DQ_CA_OPEN = 0
2149 13:11:54.776670 DQ_SEMI_OPEN = 0
2150 13:11:54.776748 CA_SEMI_OPEN = 0
2151 13:11:54.780270 CA_FULL_RATE = 0
2152 13:11:54.783445 DQ_CKDIV4_EN = 0
2153 13:11:54.786493 CA_CKDIV4_EN = 0
2154 13:11:54.790122 CA_PREDIV_EN = 0
2155 13:11:54.793274 PH8_DLY = 17
2156 13:11:54.793352 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2157 13:11:54.796994 DQ_AAMCK_DIV = 4
2158 13:11:54.800184 CA_AAMCK_DIV = 4
2159 13:11:54.803051 CA_ADMCK_DIV = 4
2160 13:11:54.807008 DQ_TRACK_CA_EN = 0
2161 13:11:54.809764 CA_PICK = 1200
2162 13:11:54.813324 CA_MCKIO = 1200
2163 13:11:54.813400 MCKIO_SEMI = 0
2164 13:11:54.816616 PLL_FREQ = 2366
2165 13:11:54.819931 DQ_UI_PI_RATIO = 32
2166 13:11:54.823284 CA_UI_PI_RATIO = 0
2167 13:11:54.826183 ===================================
2168 13:11:54.829948 ===================================
2169 13:11:54.832874 memory_type:LPDDR4
2170 13:11:54.832975 GP_NUM : 10
2171 13:11:54.836345 SRAM_EN : 1
2172 13:11:54.839416 MD32_EN : 0
2173 13:11:54.843104 ===================================
2174 13:11:54.843183 [ANA_INIT] >>>>>>>>>>>>>>
2175 13:11:54.846378 <<<<<< [CONFIGURE PHASE]: ANA_TX
2176 13:11:54.849686 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2177 13:11:54.852894 ===================================
2178 13:11:54.856159 data_rate = 2400,PCW = 0X5b00
2179 13:11:54.859893 ===================================
2180 13:11:54.862970 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2181 13:11:54.869392 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2182 13:11:54.872629 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2183 13:11:54.879445 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2184 13:11:54.882676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2185 13:11:54.886598 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2186 13:11:54.886678 [ANA_INIT] flow start
2187 13:11:54.889663 [ANA_INIT] PLL >>>>>>>>
2188 13:11:54.892725 [ANA_INIT] PLL <<<<<<<<
2189 13:11:54.892801 [ANA_INIT] MIDPI >>>>>>>>
2190 13:11:54.896283 [ANA_INIT] MIDPI <<<<<<<<
2191 13:11:54.899226 [ANA_INIT] DLL >>>>>>>>
2192 13:11:54.902683 [ANA_INIT] DLL <<<<<<<<
2193 13:11:54.902761 [ANA_INIT] flow end
2194 13:11:54.906102 ============ LP4 DIFF to SE enter ============
2195 13:11:54.912586 ============ LP4 DIFF to SE exit ============
2196 13:11:54.912665 [ANA_INIT] <<<<<<<<<<<<<
2197 13:11:54.916619 [Flow] Enable top DCM control >>>>>
2198 13:11:54.919265 [Flow] Enable top DCM control <<<<<
2199 13:11:54.922866 Enable DLL master slave shuffle
2200 13:11:54.929552 ==============================================================
2201 13:11:54.929631 Gating Mode config
2202 13:11:54.936040 ==============================================================
2203 13:11:54.939703 Config description:
2204 13:11:54.946014 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2205 13:11:54.952770 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2206 13:11:54.959231 SELPH_MODE 0: By rank 1: By Phase
2207 13:11:54.965621 ==============================================================
2208 13:11:54.969264 GAT_TRACK_EN = 1
2209 13:11:54.969342 RX_GATING_MODE = 2
2210 13:11:54.972567 RX_GATING_TRACK_MODE = 2
2211 13:11:54.976152 SELPH_MODE = 1
2212 13:11:54.979133 PICG_EARLY_EN = 1
2213 13:11:54.982378 VALID_LAT_VALUE = 1
2214 13:11:54.989112 ==============================================================
2215 13:11:54.992687 Enter into Gating configuration >>>>
2216 13:11:54.996019 Exit from Gating configuration <<<<
2217 13:11:54.999125 Enter into DVFS_PRE_config >>>>>
2218 13:11:55.008855 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2219 13:11:55.012129 Exit from DVFS_PRE_config <<<<<
2220 13:11:55.015427 Enter into PICG configuration >>>>
2221 13:11:55.018728 Exit from PICG configuration <<<<
2222 13:11:55.022055 [RX_INPUT] configuration >>>>>
2223 13:11:55.025552 [RX_INPUT] configuration <<<<<
2224 13:11:55.029043 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2225 13:11:55.035396 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2226 13:11:55.042012 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2227 13:11:55.045603 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2228 13:11:55.051718 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2229 13:11:55.059031 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2230 13:11:55.061590 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2231 13:11:55.068523 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2232 13:11:55.071602 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2233 13:11:55.074669 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2234 13:11:55.078463 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2235 13:11:55.085324 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2236 13:11:55.088428 ===================================
2237 13:11:55.088506 LPDDR4 DRAM CONFIGURATION
2238 13:11:55.091737 ===================================
2239 13:11:55.095204 EX_ROW_EN[0] = 0x0
2240 13:11:55.098529 EX_ROW_EN[1] = 0x0
2241 13:11:55.098607 LP4Y_EN = 0x0
2242 13:11:55.101645 WORK_FSP = 0x0
2243 13:11:55.101722 WL = 0x4
2244 13:11:55.105304 RL = 0x4
2245 13:11:55.105380 BL = 0x2
2246 13:11:55.108092 RPST = 0x0
2247 13:11:55.108168 RD_PRE = 0x0
2248 13:11:55.111477 WR_PRE = 0x1
2249 13:11:55.111587 WR_PST = 0x0
2250 13:11:55.114932 DBI_WR = 0x0
2251 13:11:55.115008 DBI_RD = 0x0
2252 13:11:55.118430 OTF = 0x1
2253 13:11:55.121416 ===================================
2254 13:11:55.125071 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2255 13:11:55.128218 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2256 13:11:55.134784 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2257 13:11:55.138102 ===================================
2258 13:11:55.138184 LPDDR4 DRAM CONFIGURATION
2259 13:11:55.141887 ===================================
2260 13:11:55.144989 EX_ROW_EN[0] = 0x10
2261 13:11:55.148017 EX_ROW_EN[1] = 0x0
2262 13:11:55.148094 LP4Y_EN = 0x0
2263 13:11:55.151483 WORK_FSP = 0x0
2264 13:11:55.151559 WL = 0x4
2265 13:11:55.154916 RL = 0x4
2266 13:11:55.154993 BL = 0x2
2267 13:11:55.157903 RPST = 0x0
2268 13:11:55.157986 RD_PRE = 0x0
2269 13:11:55.161200 WR_PRE = 0x1
2270 13:11:55.161277 WR_PST = 0x0
2271 13:11:55.164792 DBI_WR = 0x0
2272 13:11:55.164868 DBI_RD = 0x0
2273 13:11:55.167942 OTF = 0x1
2274 13:11:55.171300 ===================================
2275 13:11:55.178158 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2276 13:11:55.178234 ==
2277 13:11:55.181903 Dram Type= 6, Freq= 0, CH_0, rank 0
2278 13:11:55.184782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2279 13:11:55.184875 ==
2280 13:11:55.188084 [Duty_Offset_Calibration]
2281 13:11:55.188161 B0:2 B1:0 CA:4
2282 13:11:55.188219
2283 13:11:55.191681 [DutyScan_Calibration_Flow] k_type=0
2284 13:11:55.200638
2285 13:11:55.200717 ==CLK 0==
2286 13:11:55.204086 Final CLK duty delay cell = -4
2287 13:11:55.207382 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2288 13:11:55.210521 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2289 13:11:55.213893 [-4] AVG Duty = 4937%(X100)
2290 13:11:55.213972
2291 13:11:55.217253 CH0 CLK Duty spec in!! Max-Min= 187%
2292 13:11:55.220555 [DutyScan_Calibration_Flow] ====Done====
2293 13:11:55.220631
2294 13:11:55.223304 [DutyScan_Calibration_Flow] k_type=1
2295 13:11:55.239889
2296 13:11:55.239999 ==DQS 0 ==
2297 13:11:55.243491 Final DQS duty delay cell = 0
2298 13:11:55.246726 [0] MAX Duty = 5156%(X100), DQS PI = 18
2299 13:11:55.250311 [0] MIN Duty = 5093%(X100), DQS PI = 0
2300 13:11:55.253462 [0] AVG Duty = 5124%(X100)
2301 13:11:55.253538
2302 13:11:55.253597 ==DQS 1 ==
2303 13:11:55.256769 Final DQS duty delay cell = 0
2304 13:11:55.259979 [0] MAX Duty = 5125%(X100), DQS PI = 52
2305 13:11:55.263610 [0] MIN Duty = 5000%(X100), DQS PI = 0
2306 13:11:55.263686 [0] AVG Duty = 5062%(X100)
2307 13:11:55.266692
2308 13:11:55.270752 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2309 13:11:55.270828
2310 13:11:55.273119 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2311 13:11:55.276551 [DutyScan_Calibration_Flow] ====Done====
2312 13:11:55.276626
2313 13:11:55.279914 [DutyScan_Calibration_Flow] k_type=3
2314 13:11:55.296548
2315 13:11:55.296649 ==DQM 0 ==
2316 13:11:55.299734 Final DQM duty delay cell = 0
2317 13:11:55.303104 [0] MAX Duty = 5125%(X100), DQS PI = 20
2318 13:11:55.306105 [0] MIN Duty = 4844%(X100), DQS PI = 50
2319 13:11:55.309820 [0] AVG Duty = 4984%(X100)
2320 13:11:55.309895
2321 13:11:55.309953 ==DQM 1 ==
2322 13:11:55.312742 Final DQM duty delay cell = 0
2323 13:11:55.316539 [0] MAX Duty = 4969%(X100), DQS PI = 2
2324 13:11:55.319495 [0] MIN Duty = 4875%(X100), DQS PI = 18
2325 13:11:55.322824 [0] AVG Duty = 4922%(X100)
2326 13:11:55.322899
2327 13:11:55.326399 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2328 13:11:55.326475
2329 13:11:55.329606 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2330 13:11:55.332957 [DutyScan_Calibration_Flow] ====Done====
2331 13:11:55.333055
2332 13:11:55.336264 [DutyScan_Calibration_Flow] k_type=2
2333 13:11:55.352800
2334 13:11:55.352882 ==DQ 0 ==
2335 13:11:55.356419 Final DQ duty delay cell = 0
2336 13:11:55.359578 [0] MAX Duty = 5125%(X100), DQS PI = 18
2337 13:11:55.362602 [0] MIN Duty = 4938%(X100), DQS PI = 58
2338 13:11:55.362678 [0] AVG Duty = 5031%(X100)
2339 13:11:55.366232
2340 13:11:55.366308 ==DQ 1 ==
2341 13:11:55.369612 Final DQ duty delay cell = 0
2342 13:11:55.372976 [0] MAX Duty = 5156%(X100), DQS PI = 4
2343 13:11:55.376177 [0] MIN Duty = 4938%(X100), DQS PI = 14
2344 13:11:55.376254 [0] AVG Duty = 5047%(X100)
2345 13:11:55.376313
2346 13:11:55.379351 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2347 13:11:55.379428
2348 13:11:55.386333 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2349 13:11:55.389272 [DutyScan_Calibration_Flow] ====Done====
2350 13:11:55.389347 ==
2351 13:11:55.392682 Dram Type= 6, Freq= 0, CH_1, rank 0
2352 13:11:55.396550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2353 13:11:55.396627 ==
2354 13:11:55.399308 [Duty_Offset_Calibration]
2355 13:11:55.399383 B0:0 B1:-1 CA:3
2356 13:11:55.399442
2357 13:11:55.402510 [DutyScan_Calibration_Flow] k_type=0
2358 13:11:55.412532
2359 13:11:55.412609 ==CLK 0==
2360 13:11:55.415951 Final CLK duty delay cell = 0
2361 13:11:55.419567 [0] MAX Duty = 5156%(X100), DQS PI = 0
2362 13:11:55.422807 [0] MIN Duty = 5000%(X100), DQS PI = 36
2363 13:11:55.422917 [0] AVG Duty = 5078%(X100)
2364 13:11:55.425984
2365 13:11:55.426059 CH1 CLK Duty spec in!! Max-Min= 156%
2366 13:11:55.432973 [DutyScan_Calibration_Flow] ====Done====
2367 13:11:55.433074
2368 13:11:55.435882 [DutyScan_Calibration_Flow] k_type=1
2369 13:11:55.452118
2370 13:11:55.452199 ==DQS 0 ==
2371 13:11:55.455094 Final DQS duty delay cell = 0
2372 13:11:55.458771 [0] MAX Duty = 5187%(X100), DQS PI = 18
2373 13:11:55.462022 [0] MIN Duty = 4907%(X100), DQS PI = 38
2374 13:11:55.462108 [0] AVG Duty = 5047%(X100)
2375 13:11:55.465333
2376 13:11:55.465410 ==DQS 1 ==
2377 13:11:55.468581 Final DQS duty delay cell = 0
2378 13:11:55.472134 [0] MAX Duty = 5156%(X100), DQS PI = 8
2379 13:11:55.475146 [0] MIN Duty = 5000%(X100), DQS PI = 26
2380 13:11:55.478385 [0] AVG Duty = 5078%(X100)
2381 13:11:55.478460
2382 13:11:55.481700 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2383 13:11:55.481775
2384 13:11:55.485121 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2385 13:11:55.488449 [DutyScan_Calibration_Flow] ====Done====
2386 13:11:55.488525
2387 13:11:55.491661 [DutyScan_Calibration_Flow] k_type=3
2388 13:11:55.508437
2389 13:11:55.508518 ==DQM 0 ==
2390 13:11:55.512010 Final DQM duty delay cell = 0
2391 13:11:55.515446 [0] MAX Duty = 5031%(X100), DQS PI = 28
2392 13:11:55.518455 [0] MIN Duty = 4782%(X100), DQS PI = 38
2393 13:11:55.521782 [0] AVG Duty = 4906%(X100)
2394 13:11:55.521858
2395 13:11:55.521917 ==DQM 1 ==
2396 13:11:55.525384 Final DQM duty delay cell = 0
2397 13:11:55.528254 [0] MAX Duty = 5000%(X100), DQS PI = 34
2398 13:11:55.531698 [0] MIN Duty = 4813%(X100), DQS PI = 0
2399 13:11:55.534759 [0] AVG Duty = 4906%(X100)
2400 13:11:55.534838
2401 13:11:55.538716 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2402 13:11:55.538793
2403 13:11:55.541657 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2404 13:11:55.545226 [DutyScan_Calibration_Flow] ====Done====
2405 13:11:55.545305
2406 13:11:55.548424 [DutyScan_Calibration_Flow] k_type=2
2407 13:11:55.564300
2408 13:11:55.564396 ==DQ 0 ==
2409 13:11:55.567435 Final DQ duty delay cell = -4
2410 13:11:55.570497 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2411 13:11:55.574112 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2412 13:11:55.577598 [-4] AVG Duty = 4922%(X100)
2413 13:11:55.577681
2414 13:11:55.577741 ==DQ 1 ==
2415 13:11:55.581161 Final DQ duty delay cell = 0
2416 13:11:55.584323 [0] MAX Duty = 5031%(X100), DQS PI = 26
2417 13:11:55.587529 [0] MIN Duty = 4844%(X100), DQS PI = 62
2418 13:11:55.590503 [0] AVG Duty = 4937%(X100)
2419 13:11:55.590585
2420 13:11:55.593841 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2421 13:11:55.593919
2422 13:11:55.597546 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2423 13:11:55.600285 [DutyScan_Calibration_Flow] ====Done====
2424 13:11:55.604025 nWR fixed to 30
2425 13:11:55.607371 [ModeRegInit_LP4] CH0 RK0
2426 13:11:55.607499 [ModeRegInit_LP4] CH0 RK1
2427 13:11:55.610548 [ModeRegInit_LP4] CH1 RK0
2428 13:11:55.613787 [ModeRegInit_LP4] CH1 RK1
2429 13:11:55.613953 match AC timing 7
2430 13:11:55.620596 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2431 13:11:55.623729 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2432 13:11:55.627273 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2433 13:11:55.634035 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2434 13:11:55.637248 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2435 13:11:55.637324 ==
2436 13:11:55.640593 Dram Type= 6, Freq= 0, CH_0, rank 0
2437 13:11:55.644021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2438 13:11:55.644107 ==
2439 13:11:55.650470 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2440 13:11:55.657177 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2441 13:11:55.664316 [CA 0] Center 39 (9~70) winsize 62
2442 13:11:55.667761 [CA 1] Center 39 (8~70) winsize 63
2443 13:11:55.671794 [CA 2] Center 35 (5~66) winsize 62
2444 13:11:55.674585 [CA 3] Center 35 (5~66) winsize 62
2445 13:11:55.678158 [CA 4] Center 33 (3~64) winsize 62
2446 13:11:55.681402 [CA 5] Center 33 (3~64) winsize 62
2447 13:11:55.681577
2448 13:11:55.684620 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2449 13:11:55.684865
2450 13:11:55.688030 [CATrainingPosCal] consider 1 rank data
2451 13:11:55.691206 u2DelayCellTimex100 = 270/100 ps
2452 13:11:55.694300 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2453 13:11:55.702245 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2454 13:11:55.705232 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2455 13:11:55.707850 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2456 13:11:55.712146 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2457 13:11:55.714505 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2458 13:11:55.714840
2459 13:11:55.717867 CA PerBit enable=1, Macro0, CA PI delay=33
2460 13:11:55.718197
2461 13:11:55.721237 [CBTSetCACLKResult] CA Dly = 33
2462 13:11:55.721569 CS Dly: 7 (0~38)
2463 13:11:55.724240 ==
2464 13:11:55.724579 Dram Type= 6, Freq= 0, CH_0, rank 1
2465 13:11:55.731154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2466 13:11:55.731489 ==
2467 13:11:55.734852 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2468 13:11:55.741806 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2469 13:11:55.750525 [CA 0] Center 39 (9~70) winsize 62
2470 13:11:55.753756 [CA 1] Center 39 (9~70) winsize 62
2471 13:11:55.756932 [CA 2] Center 35 (5~66) winsize 62
2472 13:11:55.760621 [CA 3] Center 35 (5~66) winsize 62
2473 13:11:55.763806 [CA 4] Center 34 (4~65) winsize 62
2474 13:11:55.767203 [CA 5] Center 33 (3~64) winsize 62
2475 13:11:55.767534
2476 13:11:55.770513 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2477 13:11:55.770815
2478 13:11:55.773870 [CATrainingPosCal] consider 2 rank data
2479 13:11:55.777264 u2DelayCellTimex100 = 270/100 ps
2480 13:11:55.780831 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2481 13:11:55.783864 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2482 13:11:55.790409 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2483 13:11:55.793855 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2484 13:11:55.796755 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2485 13:11:55.800241 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2486 13:11:55.800572
2487 13:11:55.803648 CA PerBit enable=1, Macro0, CA PI delay=33
2488 13:11:55.803978
2489 13:11:55.807457 [CBTSetCACLKResult] CA Dly = 33
2490 13:11:55.807787 CS Dly: 8 (0~41)
2491 13:11:55.808042
2492 13:11:55.813519 ----->DramcWriteLeveling(PI) begin...
2493 13:11:55.813855 ==
2494 13:11:55.816803 Dram Type= 6, Freq= 0, CH_0, rank 0
2495 13:11:55.820067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2496 13:11:55.820595 ==
2497 13:11:55.823404 Write leveling (Byte 0): 31 => 31
2498 13:11:55.827154 Write leveling (Byte 1): 26 => 26
2499 13:11:55.829837 DramcWriteLeveling(PI) end<-----
2500 13:11:55.830426
2501 13:11:55.830996 ==
2502 13:11:55.833319 Dram Type= 6, Freq= 0, CH_0, rank 0
2503 13:11:55.836995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2504 13:11:55.837617 ==
2505 13:11:55.840218 [Gating] SW mode calibration
2506 13:11:55.846973 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2507 13:11:55.853309 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2508 13:11:55.856343 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2509 13:11:55.859791 0 15 4 | B1->B0 | 2a29 3434 | 1 1 | (0 0) (1 1)
2510 13:11:55.866239 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2511 13:11:55.870158 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2512 13:11:55.873016 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2513 13:11:55.879856 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2514 13:11:55.883315 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2515 13:11:55.886180 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
2516 13:11:55.890087 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2517 13:11:55.896676 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2518 13:11:55.900245 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2519 13:11:55.903327 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2520 13:11:55.910079 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2521 13:11:55.912964 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2522 13:11:55.916559 1 0 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2523 13:11:55.923072 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2524 13:11:55.926561 1 1 0 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
2525 13:11:55.929986 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2526 13:11:55.936183 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2527 13:11:55.939666 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2528 13:11:55.943106 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2529 13:11:55.949722 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2530 13:11:55.953030 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 13:11:55.956649 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2532 13:11:55.963298 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2533 13:11:55.966088 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2534 13:11:55.969433 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2535 13:11:55.976354 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2536 13:11:55.979439 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2537 13:11:55.982873 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 13:11:55.989644 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 13:11:55.992688 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 13:11:55.995985 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 13:11:56.002963 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 13:11:56.006000 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 13:11:56.009344 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 13:11:56.016320 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 13:11:56.019389 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 13:11:56.022684 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2547 13:11:56.029265 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2548 13:11:56.032543 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2549 13:11:56.035916 Total UI for P1: 0, mck2ui 16
2550 13:11:56.039333 best dqsien dly found for B0: ( 1, 3, 26)
2551 13:11:56.042424 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 13:11:56.046108 Total UI for P1: 0, mck2ui 16
2553 13:11:56.049191 best dqsien dly found for B1: ( 1, 4, 0)
2554 13:11:56.052390 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2555 13:11:56.055777 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2556 13:11:56.055983
2557 13:11:56.058976 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2558 13:11:56.062340 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2559 13:11:56.065959 [Gating] SW calibration Done
2560 13:11:56.066103 ==
2561 13:11:56.069315 Dram Type= 6, Freq= 0, CH_0, rank 0
2562 13:11:56.075507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2563 13:11:56.075626 ==
2564 13:11:56.075704 RX Vref Scan: 0
2565 13:11:56.075776
2566 13:11:56.078481 RX Vref 0 -> 0, step: 1
2567 13:11:56.078580
2568 13:11:56.081975 RX Delay -40 -> 252, step: 8
2569 13:11:56.085657 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2570 13:11:56.088600 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2571 13:11:56.091887 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2572 13:11:56.098663 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2573 13:11:56.101841 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2574 13:11:56.105106 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2575 13:11:56.108715 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2576 13:11:56.111703 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2577 13:11:56.115354 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2578 13:11:56.121486 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2579 13:11:56.125153 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2580 13:11:56.128660 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2581 13:11:56.131818 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2582 13:11:56.139945 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2583 13:11:56.141679 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2584 13:11:56.144936 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2585 13:11:56.145032 ==
2586 13:11:56.148510 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 13:11:56.151399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 13:11:56.151475 ==
2589 13:11:56.154984 DQS Delay:
2590 13:11:56.155059 DQS0 = 0, DQS1 = 0
2591 13:11:56.158035 DQM Delay:
2592 13:11:56.158141 DQM0 = 118, DQM1 = 107
2593 13:11:56.158234 DQ Delay:
2594 13:11:56.161520 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =115
2595 13:11:56.168317 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2596 13:11:56.171705 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2597 13:11:56.175154 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2598 13:11:56.175234
2599 13:11:56.175294
2600 13:11:56.175349 ==
2601 13:11:56.178145 Dram Type= 6, Freq= 0, CH_0, rank 0
2602 13:11:56.181308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2603 13:11:56.181388 ==
2604 13:11:56.181447
2605 13:11:56.181502
2606 13:11:56.184582 TX Vref Scan disable
2607 13:11:56.188164 == TX Byte 0 ==
2608 13:11:56.191268 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2609 13:11:56.194764 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2610 13:11:56.197968 == TX Byte 1 ==
2611 13:11:56.201333 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2612 13:11:56.204734 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2613 13:11:56.204817 ==
2614 13:11:56.208007 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 13:11:56.211856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 13:11:56.211935 ==
2617 13:11:56.224948 TX Vref=22, minBit 5, minWin=25, winSum=412
2618 13:11:56.227886 TX Vref=24, minBit 3, minWin=25, winSum=416
2619 13:11:56.231428 TX Vref=26, minBit 1, minWin=25, winSum=422
2620 13:11:56.234532 TX Vref=28, minBit 0, minWin=26, winSum=428
2621 13:11:56.237945 TX Vref=30, minBit 5, minWin=26, winSum=428
2622 13:11:56.244837 TX Vref=32, minBit 0, minWin=26, winSum=424
2623 13:11:56.248270 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
2624 13:11:56.248367
2625 13:11:56.251257 Final TX Range 1 Vref 28
2626 13:11:56.251423
2627 13:11:56.251537 ==
2628 13:11:56.325682 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 13:11:56.326006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 13:11:56.326080 ==
2631 13:11:56.326177
2632 13:11:56.326237
2633 13:11:56.326293 TX Vref Scan disable
2634 13:11:56.326347 == TX Byte 0 ==
2635 13:11:56.326400 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2636 13:11:56.326454 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2637 13:11:56.326507 == TX Byte 1 ==
2638 13:11:56.326590 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2639 13:11:56.326676 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2640 13:11:56.326757
2641 13:11:56.326838 [DATLAT]
2642 13:11:56.326918 Freq=1200, CH0 RK0
2643 13:11:56.327010
2644 13:11:56.327094 DATLAT Default: 0xd
2645 13:11:56.327177 0, 0xFFFF, sum = 0
2646 13:11:56.327267 1, 0xFFFF, sum = 0
2647 13:11:56.327349 2, 0xFFFF, sum = 0
2648 13:11:56.327432 3, 0xFFFF, sum = 0
2649 13:11:56.327515 4, 0xFFFF, sum = 0
2650 13:11:56.327597 5, 0xFFFF, sum = 0
2651 13:11:56.327688 6, 0xFFFF, sum = 0
2652 13:11:56.327771 7, 0xFFFF, sum = 0
2653 13:11:56.327853 8, 0xFFFF, sum = 0
2654 13:11:56.327935 9, 0xFFFF, sum = 0
2655 13:11:56.328018 10, 0xFFFF, sum = 0
2656 13:11:56.328106 11, 0xFFFF, sum = 0
2657 13:11:56.328195 12, 0x0, sum = 1
2658 13:11:56.328282 13, 0x0, sum = 2
2659 13:11:56.328366 14, 0x0, sum = 3
2660 13:11:56.328453 15, 0x0, sum = 4
2661 13:11:56.328538 best_step = 13
2662 13:11:56.328633
2663 13:11:56.328715 ==
2664 13:11:56.328795 Dram Type= 6, Freq= 0, CH_0, rank 0
2665 13:11:56.328876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2666 13:11:56.328962 ==
2667 13:11:56.329048 RX Vref Scan: 1
2668 13:11:56.329132
2669 13:11:56.329225 Set Vref Range= 32 -> 127
2670 13:11:56.329280
2671 13:11:56.330670 RX Vref 32 -> 127, step: 1
2672 13:11:56.330783
2673 13:11:56.333969 RX Delay -21 -> 252, step: 4
2674 13:11:56.334121
2675 13:11:56.337528 Set Vref, RX VrefLevel [Byte0]: 32
2676 13:11:56.341174 [Byte1]: 32
2677 13:11:56.341361
2678 13:11:56.344071 Set Vref, RX VrefLevel [Byte0]: 33
2679 13:11:56.347159 [Byte1]: 33
2680 13:11:56.350935
2681 13:11:56.351069 Set Vref, RX VrefLevel [Byte0]: 34
2682 13:11:56.354426 [Byte1]: 34
2683 13:11:56.359005
2684 13:11:56.359099 Set Vref, RX VrefLevel [Byte0]: 35
2685 13:11:56.362656 [Byte1]: 35
2686 13:11:56.366924
2687 13:11:56.367004 Set Vref, RX VrefLevel [Byte0]: 36
2688 13:11:56.370382 [Byte1]: 36
2689 13:11:56.374632
2690 13:11:56.374718 Set Vref, RX VrefLevel [Byte0]: 37
2691 13:11:56.377888 [Byte1]: 37
2692 13:11:56.382557
2693 13:11:56.382798 Set Vref, RX VrefLevel [Byte0]: 38
2694 13:11:56.386003 [Byte1]: 38
2695 13:11:56.390762
2696 13:11:56.390896 Set Vref, RX VrefLevel [Byte0]: 39
2697 13:11:56.394120 [Byte1]: 39
2698 13:11:56.398824
2699 13:11:56.398960 Set Vref, RX VrefLevel [Byte0]: 40
2700 13:11:56.402137 [Byte1]: 40
2701 13:11:56.406857
2702 13:11:56.406976 Set Vref, RX VrefLevel [Byte0]: 41
2703 13:11:56.410066 [Byte1]: 41
2704 13:11:56.414779
2705 13:11:56.414949 Set Vref, RX VrefLevel [Byte0]: 42
2706 13:11:56.417605 [Byte1]: 42
2707 13:11:56.422294
2708 13:11:56.422462 Set Vref, RX VrefLevel [Byte0]: 43
2709 13:11:56.425691 [Byte1]: 43
2710 13:11:56.430145
2711 13:11:56.430335 Set Vref, RX VrefLevel [Byte0]: 44
2712 13:11:56.433594 [Byte1]: 44
2713 13:11:56.438468
2714 13:11:56.438607 Set Vref, RX VrefLevel [Byte0]: 45
2715 13:11:56.441713 [Byte1]: 45
2716 13:11:56.446224
2717 13:11:56.446333 Set Vref, RX VrefLevel [Byte0]: 46
2718 13:11:56.449546 [Byte1]: 46
2719 13:11:56.454030
2720 13:11:56.454121 Set Vref, RX VrefLevel [Byte0]: 47
2721 13:11:56.457159 [Byte1]: 47
2722 13:11:56.462282
2723 13:11:56.462384 Set Vref, RX VrefLevel [Byte0]: 48
2724 13:11:56.465379 [Byte1]: 48
2725 13:11:56.469954
2726 13:11:56.470102 Set Vref, RX VrefLevel [Byte0]: 49
2727 13:11:56.473084 [Byte1]: 49
2728 13:11:56.477889
2729 13:11:56.478030 Set Vref, RX VrefLevel [Byte0]: 50
2730 13:11:56.481060 [Byte1]: 50
2731 13:11:56.485773
2732 13:11:56.485911 Set Vref, RX VrefLevel [Byte0]: 51
2733 13:11:56.489257 [Byte1]: 51
2734 13:11:56.493555
2735 13:11:56.493645 Set Vref, RX VrefLevel [Byte0]: 52
2736 13:11:56.496996 [Byte1]: 52
2737 13:11:56.501760
2738 13:11:56.501842 Set Vref, RX VrefLevel [Byte0]: 53
2739 13:11:56.504809 [Byte1]: 53
2740 13:11:56.509430
2741 13:11:56.509531 Set Vref, RX VrefLevel [Byte0]: 54
2742 13:11:56.512692 [Byte1]: 54
2743 13:11:56.517983
2744 13:11:56.518065 Set Vref, RX VrefLevel [Byte0]: 55
2745 13:11:56.520856 [Byte1]: 55
2746 13:11:56.525178
2747 13:11:56.525320 Set Vref, RX VrefLevel [Byte0]: 56
2748 13:11:56.528557 [Byte1]: 56
2749 13:11:56.533174
2750 13:11:56.533267 Set Vref, RX VrefLevel [Byte0]: 57
2751 13:11:56.536543 [Byte1]: 57
2752 13:11:56.541159
2753 13:11:56.541240 Set Vref, RX VrefLevel [Byte0]: 58
2754 13:11:56.544600 [Byte1]: 58
2755 13:11:56.549158
2756 13:11:56.549240 Set Vref, RX VrefLevel [Byte0]: 59
2757 13:11:56.552324 [Byte1]: 59
2758 13:11:56.557540
2759 13:11:56.557635 Set Vref, RX VrefLevel [Byte0]: 60
2760 13:11:56.560587 [Byte1]: 60
2761 13:11:56.564816
2762 13:11:56.564919 Set Vref, RX VrefLevel [Byte0]: 61
2763 13:11:56.568171 [Byte1]: 61
2764 13:11:56.573344
2765 13:11:56.573471 Set Vref, RX VrefLevel [Byte0]: 62
2766 13:11:56.576229 [Byte1]: 62
2767 13:11:56.580976
2768 13:11:56.581156 Set Vref, RX VrefLevel [Byte0]: 63
2769 13:11:56.584045 [Byte1]: 63
2770 13:11:56.588800
2771 13:11:56.588994 Set Vref, RX VrefLevel [Byte0]: 64
2772 13:11:56.592252 [Byte1]: 64
2773 13:11:56.596768
2774 13:11:56.597197 Set Vref, RX VrefLevel [Byte0]: 65
2775 13:11:56.600136 [Byte1]: 65
2776 13:11:56.604921
2777 13:11:56.605313 Set Vref, RX VrefLevel [Byte0]: 66
2778 13:11:56.608021 [Byte1]: 66
2779 13:11:56.613044
2780 13:11:56.613434 Set Vref, RX VrefLevel [Byte0]: 67
2781 13:11:56.615892 [Byte1]: 67
2782 13:11:56.620651
2783 13:11:56.620998 Set Vref, RX VrefLevel [Byte0]: 68
2784 13:11:56.624199 [Byte1]: 68
2785 13:11:56.628726
2786 13:11:56.629071 Set Vref, RX VrefLevel [Byte0]: 69
2787 13:11:56.631818 [Byte1]: 69
2788 13:11:56.636401
2789 13:11:56.636748 Set Vref, RX VrefLevel [Byte0]: 70
2790 13:11:56.640298 [Byte1]: 70
2791 13:11:56.644725
2792 13:11:56.645092 Final RX Vref Byte 0 = 54 to rank0
2793 13:11:56.647611 Final RX Vref Byte 1 = 59 to rank0
2794 13:11:56.651160 Final RX Vref Byte 0 = 54 to rank1
2795 13:11:56.654496 Final RX Vref Byte 1 = 59 to rank1==
2796 13:11:56.657899 Dram Type= 6, Freq= 0, CH_0, rank 0
2797 13:11:56.664508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2798 13:11:56.664868 ==
2799 13:11:56.665170 DQS Delay:
2800 13:11:56.665431 DQS0 = 0, DQS1 = 0
2801 13:11:56.668042 DQM Delay:
2802 13:11:56.668386 DQM0 = 117, DQM1 = 105
2803 13:11:56.671361 DQ Delay:
2804 13:11:56.674265 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2805 13:11:56.677824 DQ4 =120, DQ5 =110, DQ6 =124, DQ7 =122
2806 13:11:56.681027 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2807 13:11:56.684473 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2808 13:11:56.684822
2809 13:11:56.685091
2810 13:11:56.691228 [DQSOSCAuto] RK0, (LSB)MR18= 0x4ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2811 13:11:56.694122 CH0 RK0: MR19=403, MR18=4FF
2812 13:11:56.700989 CH0_RK0: MR19=0x403, MR18=0x4FF, DQSOSC=408, MR23=63, INC=39, DEC=26
2813 13:11:56.701503
2814 13:11:56.704201 ----->DramcWriteLeveling(PI) begin...
2815 13:11:56.704720 ==
2816 13:11:56.707744 Dram Type= 6, Freq= 0, CH_0, rank 1
2817 13:11:56.711317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2818 13:11:56.714408 ==
2819 13:11:56.714841 Write leveling (Byte 0): 32 => 32
2820 13:11:56.717334 Write leveling (Byte 1): 27 => 27
2821 13:11:56.720854 DramcWriteLeveling(PI) end<-----
2822 13:11:56.721402
2823 13:11:56.721701 ==
2824 13:11:56.723883 Dram Type= 6, Freq= 0, CH_0, rank 1
2825 13:11:56.730483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 13:11:56.730833 ==
2827 13:11:56.731107 [Gating] SW mode calibration
2828 13:11:56.740918 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2829 13:11:56.744554 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2830 13:11:56.750922 0 15 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2831 13:11:56.754341 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2832 13:11:56.757545 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2833 13:11:56.760779 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2834 13:11:56.767332 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 13:11:56.770638 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 13:11:56.774430 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
2837 13:11:56.780586 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2838 13:11:56.784019 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (0 1) (0 0)
2839 13:11:56.787583 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2840 13:11:56.794085 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2841 13:11:56.797027 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 13:11:56.800407 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 13:11:56.806875 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 13:11:56.810144 1 0 24 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
2845 13:11:56.813508 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2846 13:11:56.820156 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2847 13:11:56.823613 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2848 13:11:56.827003 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2849 13:11:56.833594 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 13:11:56.836871 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 13:11:56.840260 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 13:11:56.846920 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2853 13:11:56.850136 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2854 13:11:56.853404 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2855 13:11:56.860341 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2856 13:11:56.863683 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 13:11:56.867023 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 13:11:56.873544 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 13:11:56.876949 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 13:11:56.880153 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 13:11:56.886483 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 13:11:56.890352 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 13:11:56.893432 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 13:11:56.899917 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 13:11:56.903414 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 13:11:56.906692 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 13:11:56.913197 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 13:11:56.916453 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2869 13:11:56.919887 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2870 13:11:56.923743 Total UI for P1: 0, mck2ui 16
2871 13:11:56.926767 best dqsien dly found for B0: ( 1, 3, 24)
2872 13:11:56.930006 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2873 13:11:56.936484 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 13:11:56.940294 Total UI for P1: 0, mck2ui 16
2875 13:11:56.943309 best dqsien dly found for B1: ( 1, 3, 30)
2876 13:11:56.946284 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2877 13:11:56.949943 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2878 13:11:56.950300
2879 13:11:56.953085 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2880 13:11:56.956384 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2881 13:11:56.959873 [Gating] SW calibration Done
2882 13:11:56.960231 ==
2883 13:11:56.963155 Dram Type= 6, Freq= 0, CH_0, rank 1
2884 13:11:56.966782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2885 13:11:56.967140 ==
2886 13:11:56.969464 RX Vref Scan: 0
2887 13:11:56.969818
2888 13:11:56.972761 RX Vref 0 -> 0, step: 1
2889 13:11:56.973116
2890 13:11:56.973451 RX Delay -40 -> 252, step: 8
2891 13:11:56.979762 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2892 13:11:56.982926 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2893 13:11:56.986650 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2894 13:11:56.989778 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2895 13:11:56.992956 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2896 13:11:56.999353 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2897 13:11:57.002813 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2898 13:11:57.006506 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2899 13:11:57.009610 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2900 13:11:57.012871 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2901 13:11:57.019910 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2902 13:11:57.022881 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2903 13:11:57.025952 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2904 13:11:57.029705 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2905 13:11:57.032758 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2906 13:11:57.039383 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2907 13:11:57.039745 ==
2908 13:11:57.042787 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 13:11:57.045770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 13:11:57.046141 ==
2911 13:11:57.046419 DQS Delay:
2912 13:11:57.049278 DQS0 = 0, DQS1 = 0
2913 13:11:57.049635 DQM Delay:
2914 13:11:57.052651 DQM0 = 116, DQM1 = 109
2915 13:11:57.053008 DQ Delay:
2916 13:11:57.055966 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2917 13:11:57.059074 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2918 13:11:57.062875 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2919 13:11:57.065551 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =115
2920 13:11:57.065909
2921 13:11:57.068941
2922 13:11:57.069340 ==
2923 13:11:57.072473 Dram Type= 6, Freq= 0, CH_0, rank 1
2924 13:11:57.075777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2925 13:11:57.076138 ==
2926 13:11:57.076431
2927 13:11:57.076684
2928 13:11:57.079316 TX Vref Scan disable
2929 13:11:57.079670 == TX Byte 0 ==
2930 13:11:57.085634 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2931 13:11:57.088685 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2932 13:11:57.089042 == TX Byte 1 ==
2933 13:11:57.095397 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2934 13:11:57.098612 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2935 13:11:57.098972 ==
2936 13:11:57.102038 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 13:11:57.105401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 13:11:57.105760 ==
2939 13:11:57.118144 TX Vref=22, minBit 8, minWin=25, winSum=414
2940 13:11:57.121726 TX Vref=24, minBit 1, minWin=26, winSum=423
2941 13:11:57.125061 TX Vref=26, minBit 1, minWin=26, winSum=425
2942 13:11:57.127992 TX Vref=28, minBit 13, minWin=25, winSum=431
2943 13:11:57.131249 TX Vref=30, minBit 5, minWin=26, winSum=430
2944 13:11:57.137439 TX Vref=32, minBit 2, minWin=26, winSum=426
2945 13:11:57.141196 [TxChooseVref] Worse bit 5, Min win 26, Win sum 430, Final Vref 30
2946 13:11:57.141593
2947 13:11:57.144224 Final TX Range 1 Vref 30
2948 13:11:57.144613
2949 13:11:57.144916 ==
2950 13:11:57.147624 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 13:11:57.153876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 13:11:57.154268 ==
2953 13:11:57.154570
2954 13:11:57.154846
2955 13:11:57.155111 TX Vref Scan disable
2956 13:11:57.157773 == TX Byte 0 ==
2957 13:11:57.161032 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2958 13:11:57.167620 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2959 13:11:57.167979 == TX Byte 1 ==
2960 13:11:57.171051 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2961 13:11:57.177640 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2962 13:11:57.178031
2963 13:11:57.178334 [DATLAT]
2964 13:11:57.178614 Freq=1200, CH0 RK1
2965 13:11:57.178880
2966 13:11:57.180987 DATLAT Default: 0xd
2967 13:11:57.184005 0, 0xFFFF, sum = 0
2968 13:11:57.184401 1, 0xFFFF, sum = 0
2969 13:11:57.187577 2, 0xFFFF, sum = 0
2970 13:11:57.187973 3, 0xFFFF, sum = 0
2971 13:11:57.190974 4, 0xFFFF, sum = 0
2972 13:11:57.191371 5, 0xFFFF, sum = 0
2973 13:11:57.193943 6, 0xFFFF, sum = 0
2974 13:11:57.194307 7, 0xFFFF, sum = 0
2975 13:11:57.197229 8, 0xFFFF, sum = 0
2976 13:11:57.197762 9, 0xFFFF, sum = 0
2977 13:11:57.200705 10, 0xFFFF, sum = 0
2978 13:11:57.201099 11, 0xFFFF, sum = 0
2979 13:11:57.203638 12, 0x0, sum = 1
2980 13:11:57.204033 13, 0x0, sum = 2
2981 13:11:57.207192 14, 0x0, sum = 3
2982 13:11:57.207587 15, 0x0, sum = 4
2983 13:11:57.210570 best_step = 13
2984 13:11:57.211000
2985 13:11:57.211449 ==
2986 13:11:57.213610 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 13:11:57.217005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 13:11:57.217467 ==
2989 13:11:57.220530 RX Vref Scan: 0
2990 13:11:57.220932
2991 13:11:57.221293 RX Vref 0 -> 0, step: 1
2992 13:11:57.221586
2993 13:11:57.223733 RX Delay -21 -> 252, step: 4
2994 13:11:57.230017 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
2995 13:11:57.233543 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
2996 13:11:57.236668 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
2997 13:11:57.240284 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
2998 13:11:57.243454 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
2999 13:11:57.250011 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3000 13:11:57.253391 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3001 13:11:57.256925 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3002 13:11:57.259798 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3003 13:11:57.262980 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3004 13:11:57.269859 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3005 13:11:57.273383 iDelay=195, Bit 11, Center 100 (31 ~ 170) 140
3006 13:11:57.276778 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3007 13:11:57.279704 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3008 13:11:57.286250 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3009 13:11:57.289576 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3010 13:11:57.290095 ==
3011 13:11:57.292493 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 13:11:57.296117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 13:11:57.296476 ==
3014 13:11:57.299301 DQS Delay:
3015 13:11:57.299657 DQS0 = 0, DQS1 = 0
3016 13:11:57.299934 DQM Delay:
3017 13:11:57.302663 DQM0 = 116, DQM1 = 106
3018 13:11:57.303020 DQ Delay:
3019 13:11:57.305877 DQ0 =114, DQ1 =116, DQ2 =112, DQ3 =112
3020 13:11:57.309038 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3021 13:11:57.312293 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
3022 13:11:57.319135 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =112
3023 13:11:57.319611
3024 13:11:57.320041
3025 13:11:57.325627 [DQSOSCAuto] RK1, (LSB)MR18= 0xfffc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3026 13:11:57.328963 CH0 RK1: MR19=303, MR18=FFFC
3027 13:11:57.335698 CH0_RK1: MR19=0x303, MR18=0xFFFC, DQSOSC=410, MR23=63, INC=39, DEC=26
3028 13:11:57.339183 [RxdqsGatingPostProcess] freq 1200
3029 13:11:57.345252 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3030 13:11:57.345721 best DQS0 dly(2T, 0.5T) = (0, 11)
3031 13:11:57.348554 best DQS1 dly(2T, 0.5T) = (0, 12)
3032 13:11:57.352156 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3033 13:11:57.355434 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3034 13:11:57.358372 best DQS0 dly(2T, 0.5T) = (0, 11)
3035 13:11:57.362031 best DQS1 dly(2T, 0.5T) = (0, 11)
3036 13:11:57.365484 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3037 13:11:57.368719 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3038 13:11:57.371554 Pre-setting of DQS Precalculation
3039 13:11:57.378314 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3040 13:11:57.378674 ==
3041 13:11:57.381734 Dram Type= 6, Freq= 0, CH_1, rank 0
3042 13:11:57.384949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3043 13:11:57.385479 ==
3044 13:11:57.391656 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3045 13:11:57.394945 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3046 13:11:57.404204 [CA 0] Center 38 (8~68) winsize 61
3047 13:11:57.407767 [CA 1] Center 37 (7~68) winsize 62
3048 13:11:57.410825 [CA 2] Center 35 (5~65) winsize 61
3049 13:11:57.414256 [CA 3] Center 34 (4~64) winsize 61
3050 13:11:57.417723 [CA 4] Center 35 (5~65) winsize 61
3051 13:11:57.421062 [CA 5] Center 33 (4~63) winsize 60
3052 13:11:57.421458
3053 13:11:57.424240 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3054 13:11:57.424594
3055 13:11:57.427266 [CATrainingPosCal] consider 1 rank data
3056 13:11:57.430797 u2DelayCellTimex100 = 270/100 ps
3057 13:11:57.433997 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3058 13:11:57.440508 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3059 13:11:57.443641 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3060 13:11:57.447011 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3061 13:11:57.450489 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3062 13:11:57.454031 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3063 13:11:57.454387
3064 13:11:57.456840 CA PerBit enable=1, Macro0, CA PI delay=33
3065 13:11:57.457337
3066 13:11:57.460634 [CBTSetCACLKResult] CA Dly = 33
3067 13:11:57.463774 CS Dly: 4 (0~35)
3068 13:11:57.464224 ==
3069 13:11:57.466892 Dram Type= 6, Freq= 0, CH_1, rank 1
3070 13:11:57.470562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 13:11:57.470922 ==
3072 13:11:57.476777 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3073 13:11:57.480191 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3074 13:11:57.490084 [CA 0] Center 38 (8~68) winsize 61
3075 13:11:57.493173 [CA 1] Center 37 (7~68) winsize 62
3076 13:11:57.496458 [CA 2] Center 35 (5~65) winsize 61
3077 13:11:57.499967 [CA 3] Center 33 (3~64) winsize 62
3078 13:11:57.503353 [CA 4] Center 34 (4~64) winsize 61
3079 13:11:57.506205 [CA 5] Center 33 (3~63) winsize 61
3080 13:11:57.506558
3081 13:11:57.509708 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3082 13:11:57.510063
3083 13:11:57.513232 [CATrainingPosCal] consider 2 rank data
3084 13:11:57.516128 u2DelayCellTimex100 = 270/100 ps
3085 13:11:57.519812 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3086 13:11:57.526191 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3087 13:11:57.529724 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3088 13:11:57.533177 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3089 13:11:57.536505 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3090 13:11:57.539286 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3091 13:11:57.539639
3092 13:11:57.542747 CA PerBit enable=1, Macro0, CA PI delay=33
3093 13:11:57.543104
3094 13:11:57.546206 [CBTSetCACLKResult] CA Dly = 33
3095 13:11:57.549501 CS Dly: 6 (0~39)
3096 13:11:57.549925
3097 13:11:57.552941 ----->DramcWriteLeveling(PI) begin...
3098 13:11:57.553371 ==
3099 13:11:57.555912 Dram Type= 6, Freq= 0, CH_1, rank 0
3100 13:11:57.559824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 13:11:57.560212 ==
3102 13:11:57.563165 Write leveling (Byte 0): 23 => 23
3103 13:11:57.565752 Write leveling (Byte 1): 24 => 24
3104 13:11:57.569378 DramcWriteLeveling(PI) end<-----
3105 13:11:57.569904
3106 13:11:57.570371 ==
3107 13:11:57.572412 Dram Type= 6, Freq= 0, CH_1, rank 0
3108 13:11:57.575848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 13:11:57.576242 ==
3110 13:11:57.579053 [Gating] SW mode calibration
3111 13:11:57.585867 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3112 13:11:57.592599 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3113 13:11:57.595919 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3114 13:11:57.598878 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3115 13:11:57.605706 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 13:11:57.609017 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 13:11:57.611997 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 13:11:57.618946 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 13:11:57.621712 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3120 13:11:57.625677 0 15 28 | B1->B0 | 2d2d 2525 | 0 0 | (1 0) (1 0)
3121 13:11:57.631867 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3122 13:11:57.635109 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3123 13:11:57.638497 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 13:11:57.645294 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 13:11:57.648233 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 13:11:57.651534 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 13:11:57.658238 1 0 24 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)
3128 13:11:57.661386 1 0 28 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
3129 13:11:57.664948 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3130 13:11:57.671676 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 13:11:57.675311 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 13:11:57.677785 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 13:11:57.684489 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 13:11:57.687898 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 13:11:57.691391 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3136 13:11:57.697764 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3137 13:11:57.701555 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3138 13:11:57.704701 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 13:11:57.711259 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 13:11:57.714293 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 13:11:57.717654 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 13:11:57.724461 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 13:11:57.727674 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 13:11:57.731130 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 13:11:57.737797 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 13:11:57.740592 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 13:11:57.743848 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 13:11:57.750783 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 13:11:57.754105 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 13:11:57.757526 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 13:11:57.764144 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3152 13:11:57.767218 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 13:11:57.770580 Total UI for P1: 0, mck2ui 16
3154 13:11:57.773529 best dqsien dly found for B0: ( 1, 3, 24)
3155 13:11:57.777290 Total UI for P1: 0, mck2ui 16
3156 13:11:57.780147 best dqsien dly found for B1: ( 1, 3, 24)
3157 13:11:57.783477 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3158 13:11:57.786734 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3159 13:11:57.787281
3160 13:11:57.790478 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3161 13:11:57.793900 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3162 13:11:57.796745 [Gating] SW calibration Done
3163 13:11:57.797272 ==
3164 13:11:57.800501 Dram Type= 6, Freq= 0, CH_1, rank 0
3165 13:11:57.806679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3166 13:11:57.807074 ==
3167 13:11:57.807380 RX Vref Scan: 0
3168 13:11:57.807660
3169 13:11:57.810213 RX Vref 0 -> 0, step: 1
3170 13:11:57.810744
3171 13:11:57.813493 RX Delay -40 -> 252, step: 8
3172 13:11:57.816798 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3173 13:11:57.820036 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3174 13:11:57.823522 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3175 13:11:57.826319 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3176 13:11:57.833196 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3177 13:11:57.836385 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3178 13:11:57.839598 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3179 13:11:57.842982 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3180 13:11:57.846839 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3181 13:11:57.853032 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3182 13:11:57.856384 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3183 13:11:57.859217 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3184 13:11:57.862756 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3185 13:11:57.869586 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3186 13:11:57.873058 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3187 13:11:57.876019 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3188 13:11:57.876463 ==
3189 13:11:57.879211 Dram Type= 6, Freq= 0, CH_1, rank 0
3190 13:11:57.882511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3191 13:11:57.886171 ==
3192 13:11:57.886559 DQS Delay:
3193 13:11:57.886864 DQS0 = 0, DQS1 = 0
3194 13:11:57.888929 DQM Delay:
3195 13:11:57.889348 DQM0 = 118, DQM1 = 115
3196 13:11:57.892259 DQ Delay:
3197 13:11:57.895548 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3198 13:11:57.899075 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3199 13:11:57.902647 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =111
3200 13:11:57.905319 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =123
3201 13:11:57.905757
3202 13:11:57.906061
3203 13:11:57.906340 ==
3204 13:11:57.909021 Dram Type= 6, Freq= 0, CH_1, rank 0
3205 13:11:57.912007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3206 13:11:57.912412 ==
3207 13:11:57.915758
3208 13:11:57.916142
3209 13:11:57.916440 TX Vref Scan disable
3210 13:11:57.918671 == TX Byte 0 ==
3211 13:11:57.922096 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3212 13:11:57.925322 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3213 13:11:57.928327 == TX Byte 1 ==
3214 13:11:57.931541 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3215 13:11:57.935385 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3216 13:11:57.938365 ==
3217 13:11:57.938938 Dram Type= 6, Freq= 0, CH_1, rank 0
3218 13:11:57.944898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3219 13:11:57.945316 ==
3220 13:11:57.956029 TX Vref=22, minBit 9, minWin=24, winSum=408
3221 13:11:57.958890 TX Vref=24, minBit 9, minWin=24, winSum=411
3222 13:11:57.962104 TX Vref=26, minBit 9, minWin=24, winSum=412
3223 13:11:57.965443 TX Vref=28, minBit 9, minWin=25, winSum=426
3224 13:11:57.968834 TX Vref=30, minBit 3, minWin=26, winSum=427
3225 13:11:57.975525 TX Vref=32, minBit 9, minWin=25, winSum=425
3226 13:11:57.978917 [TxChooseVref] Worse bit 3, Min win 26, Win sum 427, Final Vref 30
3227 13:11:57.979322
3228 13:11:57.981882 Final TX Range 1 Vref 30
3229 13:11:57.982273
3230 13:11:57.982573 ==
3231 13:11:57.985031 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 13:11:57.988516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 13:11:57.991719 ==
3234 13:11:57.992106
3235 13:11:57.992404
3236 13:11:57.992721 TX Vref Scan disable
3237 13:11:57.995456 == TX Byte 0 ==
3238 13:11:57.998696 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3239 13:11:58.005435 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3240 13:11:58.005894 == TX Byte 1 ==
3241 13:11:58.008430 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3242 13:11:58.014997 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3243 13:11:58.015417
3244 13:11:58.015722 [DATLAT]
3245 13:11:58.016003 Freq=1200, CH1 RK0
3246 13:11:58.016275
3247 13:11:58.018645 DATLAT Default: 0xd
3248 13:11:58.021902 0, 0xFFFF, sum = 0
3249 13:11:58.022351 1, 0xFFFF, sum = 0
3250 13:11:58.025698 2, 0xFFFF, sum = 0
3251 13:11:58.026229 3, 0xFFFF, sum = 0
3252 13:11:58.028704 4, 0xFFFF, sum = 0
3253 13:11:58.029099 5, 0xFFFF, sum = 0
3254 13:11:58.031477 6, 0xFFFF, sum = 0
3255 13:11:58.031867 7, 0xFFFF, sum = 0
3256 13:11:58.034898 8, 0xFFFF, sum = 0
3257 13:11:58.035337 9, 0xFFFF, sum = 0
3258 13:11:58.038218 10, 0xFFFF, sum = 0
3259 13:11:58.038611 11, 0xFFFF, sum = 0
3260 13:11:58.041713 12, 0x0, sum = 1
3261 13:11:58.042110 13, 0x0, sum = 2
3262 13:11:58.044586 14, 0x0, sum = 3
3263 13:11:58.044978 15, 0x0, sum = 4
3264 13:11:58.048100 best_step = 13
3265 13:11:58.048487
3266 13:11:58.048785 ==
3267 13:11:58.051809 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 13:11:58.054608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 13:11:58.055036 ==
3270 13:11:58.058290 RX Vref Scan: 1
3271 13:11:58.058690
3272 13:11:58.059013 Set Vref Range= 32 -> 127
3273 13:11:58.059296
3274 13:11:58.061277 RX Vref 32 -> 127, step: 1
3275 13:11:58.061669
3276 13:11:58.064991 RX Delay -13 -> 252, step: 4
3277 13:11:58.065441
3278 13:11:58.067696 Set Vref, RX VrefLevel [Byte0]: 32
3279 13:11:58.071281 [Byte1]: 32
3280 13:11:58.071672
3281 13:11:58.074556 Set Vref, RX VrefLevel [Byte0]: 33
3282 13:11:58.077769 [Byte1]: 33
3283 13:11:58.081947
3284 13:11:58.082336 Set Vref, RX VrefLevel [Byte0]: 34
3285 13:11:58.084922 [Byte1]: 34
3286 13:11:58.089859
3287 13:11:58.090264 Set Vref, RX VrefLevel [Byte0]: 35
3288 13:11:58.092960 [Byte1]: 35
3289 13:11:58.097509
3290 13:11:58.097900 Set Vref, RX VrefLevel [Byte0]: 36
3291 13:11:58.100933 [Byte1]: 36
3292 13:11:58.105746
3293 13:11:58.106176 Set Vref, RX VrefLevel [Byte0]: 37
3294 13:11:58.109032 [Byte1]: 37
3295 13:11:58.113232
3296 13:11:58.113617 Set Vref, RX VrefLevel [Byte0]: 38
3297 13:11:58.116582 [Byte1]: 38
3298 13:11:58.121051
3299 13:11:58.121284 Set Vref, RX VrefLevel [Byte0]: 39
3300 13:11:58.124707 [Byte1]: 39
3301 13:11:58.128711
3302 13:11:58.128876 Set Vref, RX VrefLevel [Byte0]: 40
3303 13:11:58.132022 [Byte1]: 40
3304 13:11:58.136434
3305 13:11:58.136552 Set Vref, RX VrefLevel [Byte0]: 41
3306 13:11:58.140153 [Byte1]: 41
3307 13:11:58.144902
3308 13:11:58.145006 Set Vref, RX VrefLevel [Byte0]: 42
3309 13:11:58.148133 [Byte1]: 42
3310 13:11:58.152349
3311 13:11:58.152434 Set Vref, RX VrefLevel [Byte0]: 43
3312 13:11:58.156369 [Byte1]: 43
3313 13:11:58.160393
3314 13:11:58.160470 Set Vref, RX VrefLevel [Byte0]: 44
3315 13:11:58.163745 [Byte1]: 44
3316 13:11:58.168235
3317 13:11:58.168310 Set Vref, RX VrefLevel [Byte0]: 45
3318 13:11:58.171527 [Byte1]: 45
3319 13:11:58.176049
3320 13:11:58.176124 Set Vref, RX VrefLevel [Byte0]: 46
3321 13:11:58.179408 [Byte1]: 46
3322 13:11:58.183744
3323 13:11:58.183818 Set Vref, RX VrefLevel [Byte0]: 47
3324 13:11:58.187566 [Byte1]: 47
3325 13:11:58.191933
3326 13:11:58.192013 Set Vref, RX VrefLevel [Byte0]: 48
3327 13:11:58.195481 [Byte1]: 48
3328 13:11:58.199842
3329 13:11:58.199926 Set Vref, RX VrefLevel [Byte0]: 49
3330 13:11:58.202969 [Byte1]: 49
3331 13:11:58.207775
3332 13:11:58.207907 Set Vref, RX VrefLevel [Byte0]: 50
3333 13:11:58.210674 [Byte1]: 50
3334 13:11:58.215463
3335 13:11:58.215634 Set Vref, RX VrefLevel [Byte0]: 51
3336 13:11:58.219071 [Byte1]: 51
3337 13:11:58.223380
3338 13:11:58.223519 Set Vref, RX VrefLevel [Byte0]: 52
3339 13:11:58.226539 [Byte1]: 52
3340 13:11:58.231213
3341 13:11:58.231397 Set Vref, RX VrefLevel [Byte0]: 53
3342 13:11:58.234776 [Byte1]: 53
3343 13:11:58.239150
3344 13:11:58.239378 Set Vref, RX VrefLevel [Byte0]: 54
3345 13:11:58.242691 [Byte1]: 54
3346 13:11:58.247426
3347 13:11:58.247774 Set Vref, RX VrefLevel [Byte0]: 55
3348 13:11:58.250906 [Byte1]: 55
3349 13:11:58.255043
3350 13:11:58.255427 Set Vref, RX VrefLevel [Byte0]: 56
3351 13:11:58.258310 [Byte1]: 56
3352 13:11:58.262894
3353 13:11:58.263422 Set Vref, RX VrefLevel [Byte0]: 57
3354 13:11:58.266355 [Byte1]: 57
3355 13:11:58.271242
3356 13:11:58.271656 Set Vref, RX VrefLevel [Byte0]: 58
3357 13:11:58.274690 [Byte1]: 58
3358 13:11:58.279040
3359 13:11:58.279424 Set Vref, RX VrefLevel [Byte0]: 59
3360 13:11:58.282586 [Byte1]: 59
3361 13:11:58.286526
3362 13:11:58.286912 Set Vref, RX VrefLevel [Byte0]: 60
3363 13:11:58.290009 [Byte1]: 60
3364 13:11:58.294961
3365 13:11:58.295345 Set Vref, RX VrefLevel [Byte0]: 61
3366 13:11:58.298193 [Byte1]: 61
3367 13:11:58.302201
3368 13:11:58.302590 Set Vref, RX VrefLevel [Byte0]: 62
3369 13:11:58.305782 [Byte1]: 62
3370 13:11:58.310208
3371 13:11:58.310718 Set Vref, RX VrefLevel [Byte0]: 63
3372 13:11:58.313636 [Byte1]: 63
3373 13:11:58.318353
3374 13:11:58.318846 Set Vref, RX VrefLevel [Byte0]: 64
3375 13:11:58.321616 [Byte1]: 64
3376 13:11:58.325955
3377 13:11:58.326338 Set Vref, RX VrefLevel [Byte0]: 65
3378 13:11:58.329680 [Byte1]: 65
3379 13:11:58.333949
3380 13:11:58.334393 Final RX Vref Byte 0 = 52 to rank0
3381 13:11:58.337247 Final RX Vref Byte 1 = 53 to rank0
3382 13:11:58.340567 Final RX Vref Byte 0 = 52 to rank1
3383 13:11:58.343687 Final RX Vref Byte 1 = 53 to rank1==
3384 13:11:58.347320 Dram Type= 6, Freq= 0, CH_1, rank 0
3385 13:11:58.353519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3386 13:11:58.353913 ==
3387 13:11:58.354304 DQS Delay:
3388 13:11:58.356993 DQS0 = 0, DQS1 = 0
3389 13:11:58.357427 DQM Delay:
3390 13:11:58.357814 DQM0 = 117, DQM1 = 115
3391 13:11:58.360430 DQ Delay:
3392 13:11:58.363816 DQ0 =124, DQ1 =114, DQ2 =108, DQ3 =118
3393 13:11:58.366758 DQ4 =112, DQ5 =124, DQ6 =128, DQ7 =112
3394 13:11:58.370872 DQ8 =100, DQ9 =106, DQ10 =116, DQ11 =110
3395 13:11:58.373831 DQ12 =124, DQ13 =122, DQ14 =122, DQ15 =124
3396 13:11:58.374215
3397 13:11:58.374514
3398 13:11:58.383755 [DQSOSCAuto] RK0, (LSB)MR18= 0xf804, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 413 ps
3399 13:11:58.384152 CH1 RK0: MR19=304, MR18=F804
3400 13:11:58.390158 CH1_RK0: MR19=0x304, MR18=0xF804, DQSOSC=408, MR23=63, INC=39, DEC=26
3401 13:11:58.390547
3402 13:11:58.393682 ----->DramcWriteLeveling(PI) begin...
3403 13:11:58.394079 ==
3404 13:11:58.396881 Dram Type= 6, Freq= 0, CH_1, rank 1
3405 13:11:58.403286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3406 13:11:58.403679 ==
3407 13:11:58.406903 Write leveling (Byte 0): 25 => 25
3408 13:11:58.409754 Write leveling (Byte 1): 26 => 26
3409 13:11:58.410143 DramcWriteLeveling(PI) end<-----
3410 13:11:58.413261
3411 13:11:58.413650 ==
3412 13:11:58.416729 Dram Type= 6, Freq= 0, CH_1, rank 1
3413 13:11:58.420027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3414 13:11:58.420556 ==
3415 13:11:58.423031 [Gating] SW mode calibration
3416 13:11:58.429433 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3417 13:11:58.433371 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3418 13:11:58.439712 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3419 13:11:58.443142 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3420 13:11:58.449581 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3421 13:11:58.452695 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3422 13:11:58.456316 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3423 13:11:58.459427 0 15 20 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
3424 13:11:58.465974 0 15 24 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
3425 13:11:58.469031 0 15 28 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
3426 13:11:58.475764 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3427 13:11:58.478933 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3428 13:11:58.482221 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3429 13:11:58.488997 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3430 13:11:58.492149 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3431 13:11:58.495621 1 0 20 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
3432 13:11:58.502291 1 0 24 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
3433 13:11:58.505547 1 0 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3434 13:11:58.508882 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3435 13:11:58.515354 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3436 13:11:58.518797 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3437 13:11:58.521899 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3438 13:11:58.528310 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3439 13:11:58.531693 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3440 13:11:58.534811 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3441 13:11:58.541391 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3442 13:11:58.544754 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3443 13:11:58.548309 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3444 13:11:58.554547 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3445 13:11:58.557961 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3446 13:11:58.561453 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3447 13:11:58.567771 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3448 13:11:58.571148 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 13:11:58.574782 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 13:11:58.581253 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 13:11:58.584471 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 13:11:58.587784 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 13:11:58.594410 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 13:11:58.598061 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 13:11:58.600711 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3456 13:11:58.607297 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3457 13:11:58.610713 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3458 13:11:58.614028 Total UI for P1: 0, mck2ui 16
3459 13:11:58.617578 best dqsien dly found for B0: ( 1, 3, 22)
3460 13:11:58.620912 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 13:11:58.624208 Total UI for P1: 0, mck2ui 16
3462 13:11:58.627269 best dqsien dly found for B1: ( 1, 3, 26)
3463 13:11:58.630647 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3464 13:11:58.634122 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3465 13:11:58.634504
3466 13:11:58.637579 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3467 13:11:58.644027 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3468 13:11:58.644412 [Gating] SW calibration Done
3469 13:11:58.644743 ==
3470 13:11:58.647350 Dram Type= 6, Freq= 0, CH_1, rank 1
3471 13:11:58.654091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3472 13:11:58.654477 ==
3473 13:11:58.654807 RX Vref Scan: 0
3474 13:11:58.655088
3475 13:11:58.657099 RX Vref 0 -> 0, step: 1
3476 13:11:58.657526
3477 13:11:58.660289 RX Delay -40 -> 252, step: 8
3478 13:11:58.663985 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3479 13:11:58.666922 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
3480 13:11:58.670498 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3481 13:11:58.676957 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3482 13:11:58.680717 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3483 13:11:58.683293 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3484 13:11:58.686779 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3485 13:11:58.689871 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3486 13:11:58.697064 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3487 13:11:58.699990 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3488 13:11:58.703501 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3489 13:11:58.706906 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3490 13:11:58.710161 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3491 13:11:58.716750 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3492 13:11:58.720455 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3493 13:11:58.723630 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3494 13:11:58.724018 ==
3495 13:11:58.726533 Dram Type= 6, Freq= 0, CH_1, rank 1
3496 13:11:58.729854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3497 13:11:58.733496 ==
3498 13:11:58.733875 DQS Delay:
3499 13:11:58.734169 DQS0 = 0, DQS1 = 0
3500 13:11:58.736807 DQM Delay:
3501 13:11:58.737224 DQM0 = 116, DQM1 = 113
3502 13:11:58.739615 DQ Delay:
3503 13:11:58.743117 DQ0 =119, DQ1 =115, DQ2 =103, DQ3 =115
3504 13:11:58.746479 DQ4 =119, DQ5 =127, DQ6 =119, DQ7 =115
3505 13:11:58.749819 DQ8 =103, DQ9 =99, DQ10 =115, DQ11 =107
3506 13:11:58.753292 DQ12 =123, DQ13 =123, DQ14 =115, DQ15 =119
3507 13:11:58.753673
3508 13:11:58.753967
3509 13:11:58.754242 ==
3510 13:11:58.756108 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 13:11:58.759463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 13:11:58.759851 ==
3513 13:11:58.762842
3514 13:11:58.763236
3515 13:11:58.763542 TX Vref Scan disable
3516 13:11:58.765780 == TX Byte 0 ==
3517 13:11:58.769638 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3518 13:11:58.772685 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3519 13:11:58.775681 == TX Byte 1 ==
3520 13:11:58.779311 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3521 13:11:58.782707 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3522 13:11:58.783095 ==
3523 13:11:58.786111 Dram Type= 6, Freq= 0, CH_1, rank 1
3524 13:11:58.792230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3525 13:11:58.792614 ==
3526 13:11:58.803197 TX Vref=22, minBit 8, minWin=25, winSum=419
3527 13:11:58.806351 TX Vref=24, minBit 3, minWin=25, winSum=422
3528 13:11:58.809791 TX Vref=26, minBit 9, minWin=25, winSum=425
3529 13:11:58.813115 TX Vref=28, minBit 9, minWin=25, winSum=428
3530 13:11:58.816480 TX Vref=30, minBit 9, minWin=24, winSum=427
3531 13:11:58.822951 TX Vref=32, minBit 9, minWin=25, winSum=429
3532 13:11:58.826312 [TxChooseVref] Worse bit 9, Min win 25, Win sum 429, Final Vref 32
3533 13:11:58.826730
3534 13:11:58.829505 Final TX Range 1 Vref 32
3535 13:11:58.829894
3536 13:11:58.830190 ==
3537 13:11:58.833168 Dram Type= 6, Freq= 0, CH_1, rank 1
3538 13:11:58.835888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3539 13:11:58.839487 ==
3540 13:11:58.839880
3541 13:11:58.840176
3542 13:11:58.840447 TX Vref Scan disable
3543 13:11:58.842920 == TX Byte 0 ==
3544 13:11:58.846279 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3545 13:11:58.852768 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3546 13:11:58.853195 == TX Byte 1 ==
3547 13:11:58.855939 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3548 13:11:58.863059 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3549 13:11:58.863449
3550 13:11:58.863747 [DATLAT]
3551 13:11:58.864031 Freq=1200, CH1 RK1
3552 13:11:58.864302
3553 13:11:58.865811 DATLAT Default: 0xd
3554 13:11:58.869387 0, 0xFFFF, sum = 0
3555 13:11:58.869786 1, 0xFFFF, sum = 0
3556 13:11:58.872827 2, 0xFFFF, sum = 0
3557 13:11:58.873383 3, 0xFFFF, sum = 0
3558 13:11:58.876320 4, 0xFFFF, sum = 0
3559 13:11:58.876715 5, 0xFFFF, sum = 0
3560 13:11:58.879408 6, 0xFFFF, sum = 0
3561 13:11:58.879804 7, 0xFFFF, sum = 0
3562 13:11:58.882806 8, 0xFFFF, sum = 0
3563 13:11:58.883202 9, 0xFFFF, sum = 0
3564 13:11:58.886890 10, 0xFFFF, sum = 0
3565 13:11:58.887296 11, 0xFFFF, sum = 0
3566 13:11:58.889497 12, 0x0, sum = 1
3567 13:11:58.889897 13, 0x0, sum = 2
3568 13:11:58.892602 14, 0x0, sum = 3
3569 13:11:58.893001 15, 0x0, sum = 4
3570 13:11:58.893362 best_step = 13
3571 13:11:58.895990
3572 13:11:58.896404 ==
3573 13:11:58.899450 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 13:11:58.902629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 13:11:58.903022 ==
3576 13:11:58.903323 RX Vref Scan: 0
3577 13:11:58.903603
3578 13:11:58.906116 RX Vref 0 -> 0, step: 1
3579 13:11:58.906397
3580 13:11:58.908833 RX Delay -13 -> 252, step: 4
3581 13:11:58.915469 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3582 13:11:58.918662 iDelay=195, Bit 1, Center 112 (47 ~ 178) 132
3583 13:11:58.921893 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3584 13:11:58.925088 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3585 13:11:58.928559 iDelay=195, Bit 4, Center 116 (51 ~ 182) 132
3586 13:11:58.934938 iDelay=195, Bit 5, Center 126 (59 ~ 194) 136
3587 13:11:58.938539 iDelay=195, Bit 6, Center 124 (59 ~ 190) 132
3588 13:11:58.941611 iDelay=195, Bit 7, Center 114 (47 ~ 182) 136
3589 13:11:58.945082 iDelay=195, Bit 8, Center 102 (43 ~ 162) 120
3590 13:11:58.948501 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3591 13:11:58.954807 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3592 13:11:58.958187 iDelay=195, Bit 11, Center 108 (47 ~ 170) 124
3593 13:11:58.961627 iDelay=195, Bit 12, Center 122 (63 ~ 182) 120
3594 13:11:58.964929 iDelay=195, Bit 13, Center 120 (59 ~ 182) 124
3595 13:11:58.968163 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3596 13:11:58.974395 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3597 13:11:58.974471 ==
3598 13:11:58.977995 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 13:11:58.981317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 13:11:58.981405 ==
3601 13:11:58.981472 DQS Delay:
3602 13:11:58.984582 DQS0 = 0, DQS1 = 0
3603 13:11:58.984674 DQM Delay:
3604 13:11:58.987790 DQM0 = 116, DQM1 = 114
3605 13:11:58.987900 DQ Delay:
3606 13:11:58.991767 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =114
3607 13:11:58.994557 DQ4 =116, DQ5 =126, DQ6 =124, DQ7 =114
3608 13:11:58.997648 DQ8 =102, DQ9 =104, DQ10 =118, DQ11 =108
3609 13:11:59.004469 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =124
3610 13:11:59.004596
3611 13:11:59.004691
3612 13:11:59.011280 [DQSOSCAuto] RK1, (LSB)MR18= 0xfe10, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3613 13:11:59.014217 CH1 RK1: MR19=304, MR18=FE10
3614 13:11:59.020630 CH1_RK1: MR19=0x304, MR18=0xFE10, DQSOSC=403, MR23=63, INC=40, DEC=26
3615 13:11:59.024069 [RxdqsGatingPostProcess] freq 1200
3616 13:11:59.027670 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3617 13:11:59.030977 best DQS0 dly(2T, 0.5T) = (0, 11)
3618 13:11:59.034076 best DQS1 dly(2T, 0.5T) = (0, 11)
3619 13:11:59.037653 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3620 13:11:59.040915 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3621 13:11:59.043887 best DQS0 dly(2T, 0.5T) = (0, 11)
3622 13:11:59.047364 best DQS1 dly(2T, 0.5T) = (0, 11)
3623 13:11:59.050805 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3624 13:11:59.054042 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3625 13:11:59.057500 Pre-setting of DQS Precalculation
3626 13:11:59.060420 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3627 13:11:59.070424 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3628 13:11:59.077621 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3629 13:11:59.078017
3630 13:11:59.078321
3631 13:11:59.080297 [Calibration Summary] 2400 Mbps
3632 13:11:59.080691 CH 0, Rank 0
3633 13:11:59.083672 SW Impedance : PASS
3634 13:11:59.087091 DUTY Scan : NO K
3635 13:11:59.087483 ZQ Calibration : PASS
3636 13:11:59.090011 Jitter Meter : NO K
3637 13:11:59.090398 CBT Training : PASS
3638 13:11:59.093809 Write leveling : PASS
3639 13:11:59.097103 RX DQS gating : PASS
3640 13:11:59.097534 RX DQ/DQS(RDDQC) : PASS
3641 13:11:59.099847 TX DQ/DQS : PASS
3642 13:11:59.103116 RX DATLAT : PASS
3643 13:11:59.103505 RX DQ/DQS(Engine): PASS
3644 13:11:59.106887 TX OE : NO K
3645 13:11:59.107415 All Pass.
3646 13:11:59.107731
3647 13:11:59.110010 CH 0, Rank 1
3648 13:11:59.110398 SW Impedance : PASS
3649 13:11:59.113427 DUTY Scan : NO K
3650 13:11:59.116361 ZQ Calibration : PASS
3651 13:11:59.116788 Jitter Meter : NO K
3652 13:11:59.119733 CBT Training : PASS
3653 13:11:59.123193 Write leveling : PASS
3654 13:11:59.123642 RX DQS gating : PASS
3655 13:11:59.126509 RX DQ/DQS(RDDQC) : PASS
3656 13:11:59.129840 TX DQ/DQS : PASS
3657 13:11:59.130232 RX DATLAT : PASS
3658 13:11:59.133166 RX DQ/DQS(Engine): PASS
3659 13:11:59.136578 TX OE : NO K
3660 13:11:59.136970 All Pass.
3661 13:11:59.137328
3662 13:11:59.137617 CH 1, Rank 0
3663 13:11:59.139516 SW Impedance : PASS
3664 13:11:59.143093 DUTY Scan : NO K
3665 13:11:59.143688 ZQ Calibration : PASS
3666 13:11:59.146408 Jitter Meter : NO K
3667 13:11:59.149267 CBT Training : PASS
3668 13:11:59.149655 Write leveling : PASS
3669 13:11:59.153078 RX DQS gating : PASS
3670 13:11:59.156131 RX DQ/DQS(RDDQC) : PASS
3671 13:11:59.156523 TX DQ/DQS : PASS
3672 13:11:59.159543 RX DATLAT : PASS
3673 13:11:59.162471 RX DQ/DQS(Engine): PASS
3674 13:11:59.162860 TX OE : NO K
3675 13:11:59.163165 All Pass.
3676 13:11:59.166338
3677 13:11:59.166756 CH 1, Rank 1
3678 13:11:59.169199 SW Impedance : PASS
3679 13:11:59.169590 DUTY Scan : NO K
3680 13:11:59.172362 ZQ Calibration : PASS
3681 13:11:59.175611 Jitter Meter : NO K
3682 13:11:59.175999 CBT Training : PASS
3683 13:11:59.178784 Write leveling : PASS
3684 13:11:59.179172 RX DQS gating : PASS
3685 13:11:59.182257 RX DQ/DQS(RDDQC) : PASS
3686 13:11:59.185761 TX DQ/DQS : PASS
3687 13:11:59.186162 RX DATLAT : PASS
3688 13:11:59.188636 RX DQ/DQS(Engine): PASS
3689 13:11:59.192314 TX OE : NO K
3690 13:11:59.192699 All Pass.
3691 13:11:59.193077
3692 13:11:59.195783 DramC Write-DBI off
3693 13:11:59.196170 PER_BANK_REFRESH: Hybrid Mode
3694 13:11:59.199076 TX_TRACKING: ON
3695 13:11:59.208466 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3696 13:11:59.211700 [FAST_K] Save calibration result to emmc
3697 13:11:59.215314 dramc_set_vcore_voltage set vcore to 650000
3698 13:11:59.218436 Read voltage for 600, 5
3699 13:11:59.218940 Vio18 = 0
3700 13:11:59.219356 Vcore = 650000
3701 13:11:59.222066 Vdram = 0
3702 13:11:59.222455 Vddq = 0
3703 13:11:59.222756 Vmddr = 0
3704 13:11:59.228442 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3705 13:11:59.231864 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3706 13:11:59.235124 MEM_TYPE=3, freq_sel=19
3707 13:11:59.238329 sv_algorithm_assistance_LP4_1600
3708 13:11:59.241996 ============ PULL DRAM RESETB DOWN ============
3709 13:11:59.244795 ========== PULL DRAM RESETB DOWN end =========
3710 13:11:59.251478 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3711 13:11:59.254749 ===================================
3712 13:11:59.255142 LPDDR4 DRAM CONFIGURATION
3713 13:11:59.257958 ===================================
3714 13:11:59.261519 EX_ROW_EN[0] = 0x0
3715 13:11:59.265201 EX_ROW_EN[1] = 0x0
3716 13:11:59.265597 LP4Y_EN = 0x0
3717 13:11:59.268006 WORK_FSP = 0x0
3718 13:11:59.268443 WL = 0x2
3719 13:11:59.271281 RL = 0x2
3720 13:11:59.271670 BL = 0x2
3721 13:11:59.274836 RPST = 0x0
3722 13:11:59.275256 RD_PRE = 0x0
3723 13:11:59.277685 WR_PRE = 0x1
3724 13:11:59.278075 WR_PST = 0x0
3725 13:11:59.280815 DBI_WR = 0x0
3726 13:11:59.281243 DBI_RD = 0x0
3727 13:11:59.284470 OTF = 0x1
3728 13:11:59.287695 ===================================
3729 13:11:59.290749 ===================================
3730 13:11:59.291141 ANA top config
3731 13:11:59.294100 ===================================
3732 13:11:59.297848 DLL_ASYNC_EN = 0
3733 13:11:59.301057 ALL_SLAVE_EN = 1
3734 13:11:59.304090 NEW_RANK_MODE = 1
3735 13:11:59.304480 DLL_IDLE_MODE = 1
3736 13:11:59.307480 LP45_APHY_COMB_EN = 1
3737 13:11:59.310897 TX_ODT_DIS = 1
3738 13:11:59.314207 NEW_8X_MODE = 1
3739 13:11:59.317699 ===================================
3740 13:11:59.320694 ===================================
3741 13:11:59.324054 data_rate = 1200
3742 13:11:59.327062 CKR = 1
3743 13:11:59.327454 DQ_P2S_RATIO = 8
3744 13:11:59.330364 ===================================
3745 13:11:59.333983 CA_P2S_RATIO = 8
3746 13:11:59.336948 DQ_CA_OPEN = 0
3747 13:11:59.340410 DQ_SEMI_OPEN = 0
3748 13:11:59.343663 CA_SEMI_OPEN = 0
3749 13:11:59.347215 CA_FULL_RATE = 0
3750 13:11:59.347605 DQ_CKDIV4_EN = 1
3751 13:11:59.350596 CA_CKDIV4_EN = 1
3752 13:11:59.353695 CA_PREDIV_EN = 0
3753 13:11:59.356967 PH8_DLY = 0
3754 13:11:59.360519 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3755 13:11:59.363285 DQ_AAMCK_DIV = 4
3756 13:11:59.363673 CA_AAMCK_DIV = 4
3757 13:11:59.366860 CA_ADMCK_DIV = 4
3758 13:11:59.370091 DQ_TRACK_CA_EN = 0
3759 13:11:59.373300 CA_PICK = 600
3760 13:11:59.376529 CA_MCKIO = 600
3761 13:11:59.380008 MCKIO_SEMI = 0
3762 13:11:59.383348 PLL_FREQ = 2288
3763 13:11:59.386251 DQ_UI_PI_RATIO = 32
3764 13:11:59.386636 CA_UI_PI_RATIO = 0
3765 13:11:59.390307 ===================================
3766 13:11:59.393435 ===================================
3767 13:11:59.396208 memory_type:LPDDR4
3768 13:11:59.399524 GP_NUM : 10
3769 13:11:59.399920 SRAM_EN : 1
3770 13:11:59.402954 MD32_EN : 0
3771 13:11:59.406272 ===================================
3772 13:11:59.409559 [ANA_INIT] >>>>>>>>>>>>>>
3773 13:11:59.412936 <<<<<< [CONFIGURE PHASE]: ANA_TX
3774 13:11:59.416011 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3775 13:11:59.419756 ===================================
3776 13:11:59.420247 data_rate = 1200,PCW = 0X5800
3777 13:11:59.422505 ===================================
3778 13:11:59.425884 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3779 13:11:59.432871 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3780 13:11:59.439435 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3781 13:11:59.442378 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3782 13:11:59.446076 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3783 13:11:59.448882 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3784 13:11:59.452385 [ANA_INIT] flow start
3785 13:11:59.455649 [ANA_INIT] PLL >>>>>>>>
3786 13:11:59.456038 [ANA_INIT] PLL <<<<<<<<
3787 13:11:59.459096 [ANA_INIT] MIDPI >>>>>>>>
3788 13:11:59.462512 [ANA_INIT] MIDPI <<<<<<<<
3789 13:11:59.462905 [ANA_INIT] DLL >>>>>>>>
3790 13:11:59.465449 [ANA_INIT] flow end
3791 13:11:59.468827 ============ LP4 DIFF to SE enter ============
3792 13:11:59.472209 ============ LP4 DIFF to SE exit ============
3793 13:11:59.475728 [ANA_INIT] <<<<<<<<<<<<<
3794 13:11:59.478910 [Flow] Enable top DCM control >>>>>
3795 13:11:59.482099 [Flow] Enable top DCM control <<<<<
3796 13:11:59.485261 Enable DLL master slave shuffle
3797 13:11:59.491984 ==============================================================
3798 13:11:59.492377 Gating Mode config
3799 13:11:59.498571 ==============================================================
3800 13:11:59.502314 Config description:
3801 13:11:59.508547 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3802 13:11:59.514899 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3803 13:11:59.521499 SELPH_MODE 0: By rank 1: By Phase
3804 13:11:59.527864 ==============================================================
3805 13:11:59.531767 GAT_TRACK_EN = 1
3806 13:11:59.532161 RX_GATING_MODE = 2
3807 13:11:59.534989 RX_GATING_TRACK_MODE = 2
3808 13:11:59.537850 SELPH_MODE = 1
3809 13:11:59.541346 PICG_EARLY_EN = 1
3810 13:11:59.544541 VALID_LAT_VALUE = 1
3811 13:11:59.551570 ==============================================================
3812 13:11:59.554906 Enter into Gating configuration >>>>
3813 13:11:59.557692 Exit from Gating configuration <<<<
3814 13:11:59.561232 Enter into DVFS_PRE_config >>>>>
3815 13:11:59.570834 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3816 13:11:59.574411 Exit from DVFS_PRE_config <<<<<
3817 13:11:59.577593 Enter into PICG configuration >>>>
3818 13:11:59.580952 Exit from PICG configuration <<<<
3819 13:11:59.584413 [RX_INPUT] configuration >>>>>
3820 13:11:59.587611 [RX_INPUT] configuration <<<<<
3821 13:11:59.590541 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3822 13:11:59.597591 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3823 13:11:59.603985 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3824 13:11:59.610299 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3825 13:11:59.616996 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3826 13:11:59.620491 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3827 13:11:59.626891 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3828 13:11:59.630284 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3829 13:11:59.633490 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3830 13:11:59.636834 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3831 13:11:59.643468 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3832 13:11:59.646874 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3833 13:11:59.649667 ===================================
3834 13:11:59.653209 LPDDR4 DRAM CONFIGURATION
3835 13:11:59.657103 ===================================
3836 13:11:59.657533 EX_ROW_EN[0] = 0x0
3837 13:11:59.659801 EX_ROW_EN[1] = 0x0
3838 13:11:59.660305 LP4Y_EN = 0x0
3839 13:11:59.663263 WORK_FSP = 0x0
3840 13:11:59.663651 WL = 0x2
3841 13:11:59.666611 RL = 0x2
3842 13:11:59.666992 BL = 0x2
3843 13:11:59.669720 RPST = 0x0
3844 13:11:59.672943 RD_PRE = 0x0
3845 13:11:59.673423 WR_PRE = 0x1
3846 13:11:59.676169 WR_PST = 0x0
3847 13:11:59.676550 DBI_WR = 0x0
3848 13:11:59.679684 DBI_RD = 0x0
3849 13:11:59.680066 OTF = 0x1
3850 13:11:59.683196 ===================================
3851 13:11:59.686024 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3852 13:11:59.693022 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3853 13:11:59.696152 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3854 13:11:59.699605 ===================================
3855 13:11:59.702975 LPDDR4 DRAM CONFIGURATION
3856 13:11:59.705930 ===================================
3857 13:11:59.706315 EX_ROW_EN[0] = 0x10
3858 13:11:59.709370 EX_ROW_EN[1] = 0x0
3859 13:11:59.709769 LP4Y_EN = 0x0
3860 13:11:59.712931 WORK_FSP = 0x0
3861 13:11:59.713369 WL = 0x2
3862 13:11:59.715793 RL = 0x2
3863 13:11:59.719220 BL = 0x2
3864 13:11:59.719602 RPST = 0x0
3865 13:11:59.722586 RD_PRE = 0x0
3866 13:11:59.722966 WR_PRE = 0x1
3867 13:11:59.725985 WR_PST = 0x0
3868 13:11:59.726467 DBI_WR = 0x0
3869 13:11:59.729443 DBI_RD = 0x0
3870 13:11:59.729825 OTF = 0x1
3871 13:11:59.732350 ===================================
3872 13:11:59.739087 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3873 13:11:59.743298 nWR fixed to 30
3874 13:11:59.746383 [ModeRegInit_LP4] CH0 RK0
3875 13:11:59.746821 [ModeRegInit_LP4] CH0 RK1
3876 13:11:59.749417 [ModeRegInit_LP4] CH1 RK0
3877 13:11:59.753449 [ModeRegInit_LP4] CH1 RK1
3878 13:11:59.753830 match AC timing 17
3879 13:11:59.759636 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3880 13:11:59.762731 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3881 13:11:59.766497 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3882 13:11:59.772564 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3883 13:11:59.775818 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3884 13:11:59.776203 ==
3885 13:11:59.779248 Dram Type= 6, Freq= 0, CH_0, rank 0
3886 13:11:59.782690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3887 13:11:59.783078 ==
3888 13:11:59.789118 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3889 13:11:59.796079 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3890 13:11:59.799361 [CA 0] Center 36 (6~67) winsize 62
3891 13:11:59.802581 [CA 1] Center 36 (5~67) winsize 63
3892 13:11:59.805847 [CA 2] Center 34 (3~65) winsize 63
3893 13:11:59.809207 [CA 3] Center 34 (3~65) winsize 63
3894 13:11:59.812661 [CA 4] Center 33 (3~64) winsize 62
3895 13:11:59.816096 [CA 5] Center 33 (3~64) winsize 62
3896 13:11:59.816587
3897 13:11:59.818952 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3898 13:11:59.819333
3899 13:11:59.822223 [CATrainingPosCal] consider 1 rank data
3900 13:11:59.825783 u2DelayCellTimex100 = 270/100 ps
3901 13:11:59.829117 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3902 13:11:59.832025 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3903 13:11:59.835638 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
3904 13:11:59.838892 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3905 13:11:59.845454 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3906 13:11:59.848484 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3907 13:11:59.848865
3908 13:11:59.851774 CA PerBit enable=1, Macro0, CA PI delay=33
3909 13:11:59.852175
3910 13:11:59.855532 [CBTSetCACLKResult] CA Dly = 33
3911 13:11:59.855916 CS Dly: 5 (0~36)
3912 13:11:59.856261 ==
3913 13:11:59.858783 Dram Type= 6, Freq= 0, CH_0, rank 1
3914 13:11:59.865174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3915 13:11:59.865560 ==
3916 13:11:59.868568 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3917 13:11:59.875245 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3918 13:11:59.878383 [CA 0] Center 36 (6~67) winsize 62
3919 13:11:59.881502 [CA 1] Center 36 (6~67) winsize 62
3920 13:11:59.884794 [CA 2] Center 34 (4~65) winsize 62
3921 13:11:59.888045 [CA 3] Center 34 (3~65) winsize 63
3922 13:11:59.891380 [CA 4] Center 34 (3~65) winsize 63
3923 13:11:59.895027 [CA 5] Center 33 (3~64) winsize 62
3924 13:11:59.895413
3925 13:11:59.898044 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3926 13:11:59.898430
3927 13:11:59.901389 [CATrainingPosCal] consider 2 rank data
3928 13:11:59.904601 u2DelayCellTimex100 = 270/100 ps
3929 13:11:59.908069 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3930 13:11:59.914644 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3931 13:11:59.917813 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3932 13:11:59.921404 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3933 13:11:59.924526 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3934 13:11:59.927786 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3935 13:11:59.928178
3936 13:11:59.931238 CA PerBit enable=1, Macro0, CA PI delay=33
3937 13:11:59.931629
3938 13:11:59.934162 [CBTSetCACLKResult] CA Dly = 33
3939 13:11:59.937610 CS Dly: 5 (0~37)
3940 13:11:59.937999
3941 13:11:59.941204 ----->DramcWriteLeveling(PI) begin...
3942 13:11:59.941603 ==
3943 13:11:59.944687 Dram Type= 6, Freq= 0, CH_0, rank 0
3944 13:11:59.948096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3945 13:11:59.948487 ==
3946 13:11:59.950745 Write leveling (Byte 0): 31 => 31
3947 13:11:59.954082 Write leveling (Byte 1): 30 => 30
3948 13:11:59.957527 DramcWriteLeveling(PI) end<-----
3949 13:11:59.957914
3950 13:11:59.958211 ==
3951 13:11:59.960603 Dram Type= 6, Freq= 0, CH_0, rank 0
3952 13:11:59.963817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3953 13:11:59.964206 ==
3954 13:11:59.967286 [Gating] SW mode calibration
3955 13:11:59.973786 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3956 13:11:59.980497 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3957 13:11:59.983486 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3958 13:11:59.986791 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3959 13:11:59.993550 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3960 13:11:59.997041 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
3961 13:11:59.999924 0 9 16 | B1->B0 | 2e2e 2525 | 0 0 | (0 0) (0 0)
3962 13:12:00.006664 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3963 13:12:00.010520 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3964 13:12:00.013243 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3965 13:12:00.020010 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3966 13:12:00.023451 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3967 13:12:00.026558 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3968 13:12:00.032994 0 10 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
3969 13:12:00.036628 0 10 16 | B1->B0 | 3a3a 4141 | 0 0 | (1 1) (0 0)
3970 13:12:00.039796 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3971 13:12:00.046201 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3972 13:12:00.049857 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3973 13:12:00.052676 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3974 13:12:00.059601 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3975 13:12:00.062882 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3976 13:12:00.065947 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3977 13:12:00.072477 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3978 13:12:00.076041 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3979 13:12:00.079360 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3980 13:12:00.085672 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3981 13:12:00.089313 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3982 13:12:00.092486 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 13:12:00.098813 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 13:12:00.101823 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 13:12:00.108397 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 13:12:00.112061 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 13:12:00.115041 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 13:12:00.121824 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 13:12:00.124957 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 13:12:00.128410 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 13:12:00.135199 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 13:12:00.138423 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3993 13:12:00.141648 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 13:12:00.144566 Total UI for P1: 0, mck2ui 16
3995 13:12:00.147943 best dqsien dly found for B0: ( 0, 13, 12)
3996 13:12:00.151276 Total UI for P1: 0, mck2ui 16
3997 13:12:00.155205 best dqsien dly found for B1: ( 0, 13, 14)
3998 13:12:00.158023 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
3999 13:12:00.161295 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4000 13:12:00.161700
4001 13:12:00.167984 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4002 13:12:00.171261 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4003 13:12:00.171780 [Gating] SW calibration Done
4004 13:12:00.174675 ==
4005 13:12:00.177697 Dram Type= 6, Freq= 0, CH_0, rank 0
4006 13:12:00.180847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 13:12:00.181364 ==
4008 13:12:00.181826 RX Vref Scan: 0
4009 13:12:00.182276
4010 13:12:00.184380 RX Vref 0 -> 0, step: 1
4011 13:12:00.184709
4012 13:12:00.187495 RX Delay -230 -> 252, step: 16
4013 13:12:00.190804 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4014 13:12:00.194448 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4015 13:12:00.200890 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4016 13:12:00.204428 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4017 13:12:00.207208 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4018 13:12:00.210570 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4019 13:12:00.217353 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4020 13:12:00.220657 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4021 13:12:00.223883 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4022 13:12:00.226954 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4023 13:12:00.234079 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4024 13:12:00.237175 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4025 13:12:00.240249 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4026 13:12:00.243579 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4027 13:12:00.249980 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4028 13:12:00.253234 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4029 13:12:00.253682 ==
4030 13:12:00.256385 Dram Type= 6, Freq= 0, CH_0, rank 0
4031 13:12:00.259995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4032 13:12:00.260381 ==
4033 13:12:00.263488 DQS Delay:
4034 13:12:00.263871 DQS0 = 0, DQS1 = 0
4035 13:12:00.264168 DQM Delay:
4036 13:12:00.266837 DQM0 = 40, DQM1 = 33
4037 13:12:00.267224 DQ Delay:
4038 13:12:00.270096 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4039 13:12:00.272975 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4040 13:12:00.276510 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4041 13:12:00.279550 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =33
4042 13:12:00.279938
4043 13:12:00.280364
4044 13:12:00.280676 ==
4045 13:12:00.282926 Dram Type= 6, Freq= 0, CH_0, rank 0
4046 13:12:00.289611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4047 13:12:00.290010 ==
4048 13:12:00.290320
4049 13:12:00.290601
4050 13:12:00.292946 TX Vref Scan disable
4051 13:12:00.293387 == TX Byte 0 ==
4052 13:12:00.295990 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4053 13:12:00.302658 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4054 13:12:00.303071 == TX Byte 1 ==
4055 13:12:00.306235 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4056 13:12:00.312379 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4057 13:12:00.312769 ==
4058 13:12:00.315861 Dram Type= 6, Freq= 0, CH_0, rank 0
4059 13:12:00.319307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4060 13:12:00.319699 ==
4061 13:12:00.320000
4062 13:12:00.320276
4063 13:12:00.322415 TX Vref Scan disable
4064 13:12:00.325837 == TX Byte 0 ==
4065 13:12:00.329127 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4066 13:12:00.332101 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4067 13:12:00.335798 == TX Byte 1 ==
4068 13:12:00.339090 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4069 13:12:00.342142 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4070 13:12:00.342530
4071 13:12:00.345428 [DATLAT]
4072 13:12:00.345813 Freq=600, CH0 RK0
4073 13:12:00.346111
4074 13:12:00.348815 DATLAT Default: 0x9
4075 13:12:00.349348 0, 0xFFFF, sum = 0
4076 13:12:00.352159 1, 0xFFFF, sum = 0
4077 13:12:00.352552 2, 0xFFFF, sum = 0
4078 13:12:00.355291 3, 0xFFFF, sum = 0
4079 13:12:00.355685 4, 0xFFFF, sum = 0
4080 13:12:00.358649 5, 0xFFFF, sum = 0
4081 13:12:00.359043 6, 0xFFFF, sum = 0
4082 13:12:00.361992 7, 0xFFFF, sum = 0
4083 13:12:00.362390 8, 0x0, sum = 1
4084 13:12:00.366014 9, 0x0, sum = 2
4085 13:12:00.366409 10, 0x0, sum = 3
4086 13:12:00.368519 11, 0x0, sum = 4
4087 13:12:00.368914 best_step = 9
4088 13:12:00.369250
4089 13:12:00.369539 ==
4090 13:12:00.371945 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 13:12:00.378350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 13:12:00.378750 ==
4093 13:12:00.379268 RX Vref Scan: 1
4094 13:12:00.379582
4095 13:12:00.382166 RX Vref 0 -> 0, step: 1
4096 13:12:00.382555
4097 13:12:00.384750 RX Delay -195 -> 252, step: 8
4098 13:12:00.385158
4099 13:12:00.388404 Set Vref, RX VrefLevel [Byte0]: 54
4100 13:12:00.391718 [Byte1]: 59
4101 13:12:00.392131
4102 13:12:00.394652 Final RX Vref Byte 0 = 54 to rank0
4103 13:12:00.398215 Final RX Vref Byte 1 = 59 to rank0
4104 13:12:00.401729 Final RX Vref Byte 0 = 54 to rank1
4105 13:12:00.404524 Final RX Vref Byte 1 = 59 to rank1==
4106 13:12:00.408035 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 13:12:00.411233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 13:12:00.411635 ==
4109 13:12:00.414702 DQS Delay:
4110 13:12:00.415088 DQS0 = 0, DQS1 = 0
4111 13:12:00.417902 DQM Delay:
4112 13:12:00.418287 DQM0 = 41, DQM1 = 32
4113 13:12:00.418588 DQ Delay:
4114 13:12:00.421471 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4115 13:12:00.424650 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4116 13:12:00.427943 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4117 13:12:00.431241 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4118 13:12:00.431627
4119 13:12:00.431926
4120 13:12:00.440720 [DQSOSCAuto] RK0, (LSB)MR18= 0x5048, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
4121 13:12:00.444372 CH0 RK0: MR19=808, MR18=5048
4122 13:12:00.451167 CH0_RK0: MR19=0x808, MR18=0x5048, DQSOSC=394, MR23=63, INC=168, DEC=112
4123 13:12:00.451553
4124 13:12:00.454301 ----->DramcWriteLeveling(PI) begin...
4125 13:12:00.454698 ==
4126 13:12:00.457423 Dram Type= 6, Freq= 0, CH_0, rank 1
4127 13:12:00.460787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 13:12:00.461320 ==
4129 13:12:00.464177 Write leveling (Byte 0): 35 => 35
4130 13:12:00.467527 Write leveling (Byte 1): 30 => 30
4131 13:12:00.470793 DramcWriteLeveling(PI) end<-----
4132 13:12:00.471339
4133 13:12:00.471808 ==
4134 13:12:00.474142 Dram Type= 6, Freq= 0, CH_0, rank 1
4135 13:12:00.477521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 13:12:00.478009 ==
4137 13:12:00.480532 [Gating] SW mode calibration
4138 13:12:00.487352 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4139 13:12:00.493623 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4140 13:12:00.496974 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4141 13:12:00.500493 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4142 13:12:00.506957 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4143 13:12:00.510260 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4144 13:12:00.513674 0 9 16 | B1->B0 | 2f2f 2424 | 0 0 | (1 1) (0 0)
4145 13:12:00.520040 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4146 13:12:00.523329 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4147 13:12:00.526672 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4148 13:12:00.533006 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4149 13:12:00.536631 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4150 13:12:00.539597 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4151 13:12:00.546382 0 10 12 | B1->B0 | 2c2c 3535 | 0 0 | (0 0) (0 0)
4152 13:12:00.549700 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
4153 13:12:00.552952 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4154 13:12:00.559777 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4155 13:12:00.562851 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4156 13:12:00.569232 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4157 13:12:00.572629 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4158 13:12:00.576354 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4159 13:12:00.582518 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4160 13:12:00.585990 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4161 13:12:00.588942 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4162 13:12:00.595451 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4163 13:12:00.598734 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4164 13:12:00.602829 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4165 13:12:00.608992 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4166 13:12:00.612156 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4167 13:12:00.615508 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 13:12:00.622178 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 13:12:00.625194 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 13:12:00.628517 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 13:12:00.635349 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 13:12:00.638303 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 13:12:00.641886 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 13:12:00.648611 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4175 13:12:00.651597 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 13:12:00.655036 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4177 13:12:00.658200 Total UI for P1: 0, mck2ui 16
4178 13:12:00.661492 best dqsien dly found for B0: ( 0, 13, 14)
4179 13:12:00.668089 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 13:12:00.668477 Total UI for P1: 0, mck2ui 16
4181 13:12:00.675023 best dqsien dly found for B1: ( 0, 13, 16)
4182 13:12:00.678083 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4183 13:12:00.681509 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4184 13:12:00.681895
4185 13:12:00.684488 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4186 13:12:00.687899 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4187 13:12:00.691307 [Gating] SW calibration Done
4188 13:12:00.691694 ==
4189 13:12:00.694641 Dram Type= 6, Freq= 0, CH_0, rank 1
4190 13:12:00.697645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 13:12:00.698032 ==
4192 13:12:00.700944 RX Vref Scan: 0
4193 13:12:00.701388
4194 13:12:00.701691 RX Vref 0 -> 0, step: 1
4195 13:12:00.701969
4196 13:12:00.704450 RX Delay -230 -> 252, step: 16
4197 13:12:00.710934 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4198 13:12:00.714274 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4199 13:12:00.717798 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4200 13:12:00.720674 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4201 13:12:00.723940 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4202 13:12:00.730997 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4203 13:12:00.733812 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4204 13:12:00.737584 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4205 13:12:00.740375 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4206 13:12:00.747101 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4207 13:12:00.750460 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4208 13:12:00.753777 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4209 13:12:00.756956 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4210 13:12:00.763720 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4211 13:12:00.766908 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4212 13:12:00.770305 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4213 13:12:00.770788 ==
4214 13:12:00.774078 Dram Type= 6, Freq= 0, CH_0, rank 1
4215 13:12:00.776789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4216 13:12:00.780579 ==
4217 13:12:00.781088 DQS Delay:
4218 13:12:00.781498 DQS0 = 0, DQS1 = 0
4219 13:12:00.783708 DQM Delay:
4220 13:12:00.784120 DQM0 = 41, DQM1 = 34
4221 13:12:00.786994 DQ Delay:
4222 13:12:00.790044 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4223 13:12:00.790432 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4224 13:12:00.793415 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4225 13:12:00.797201 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4226 13:12:00.799778
4227 13:12:00.800161
4228 13:12:00.800459 ==
4229 13:12:00.803192 Dram Type= 6, Freq= 0, CH_0, rank 1
4230 13:12:00.806983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4231 13:12:00.807370 ==
4232 13:12:00.807671
4233 13:12:00.807944
4234 13:12:00.810261 TX Vref Scan disable
4235 13:12:00.810666 == TX Byte 0 ==
4236 13:12:00.816514 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4237 13:12:00.819931 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4238 13:12:00.820317 == TX Byte 1 ==
4239 13:12:00.826636 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4240 13:12:00.829572 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4241 13:12:00.829967 ==
4242 13:12:00.833101 Dram Type= 6, Freq= 0, CH_0, rank 1
4243 13:12:00.836255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4244 13:12:00.836656 ==
4245 13:12:00.839702
4246 13:12:00.840081
4247 13:12:00.840375 TX Vref Scan disable
4248 13:12:00.843218 == TX Byte 0 ==
4249 13:12:00.846527 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4250 13:12:00.853365 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4251 13:12:00.853765 == TX Byte 1 ==
4252 13:12:00.856717 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4253 13:12:00.863215 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4254 13:12:00.863601
4255 13:12:00.863897 [DATLAT]
4256 13:12:00.864174 Freq=600, CH0 RK1
4257 13:12:00.864444
4258 13:12:00.866635 DATLAT Default: 0x9
4259 13:12:00.867021 0, 0xFFFF, sum = 0
4260 13:12:00.869927 1, 0xFFFF, sum = 0
4261 13:12:00.873058 2, 0xFFFF, sum = 0
4262 13:12:00.873473 3, 0xFFFF, sum = 0
4263 13:12:00.876123 4, 0xFFFF, sum = 0
4264 13:12:00.876517 5, 0xFFFF, sum = 0
4265 13:12:00.879675 6, 0xFFFF, sum = 0
4266 13:12:00.880066 7, 0xFFFF, sum = 0
4267 13:12:00.882949 8, 0x0, sum = 1
4268 13:12:00.883340 9, 0x0, sum = 2
4269 13:12:00.886383 10, 0x0, sum = 3
4270 13:12:00.886791 11, 0x0, sum = 4
4271 13:12:00.887096 best_step = 9
4272 13:12:00.887380
4273 13:12:00.889427 ==
4274 13:12:00.889856 Dram Type= 6, Freq= 0, CH_0, rank 1
4275 13:12:00.896201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4276 13:12:00.896585 ==
4277 13:12:00.896986 RX Vref Scan: 0
4278 13:12:00.897516
4279 13:12:00.899223 RX Vref 0 -> 0, step: 1
4280 13:12:00.899612
4281 13:12:00.902621 RX Delay -179 -> 252, step: 8
4282 13:12:00.909118 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4283 13:12:00.912514 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4284 13:12:00.915993 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4285 13:12:00.918812 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4286 13:12:00.922538 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4287 13:12:00.929110 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4288 13:12:00.932555 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4289 13:12:00.935891 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4290 13:12:00.938599 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4291 13:12:00.945481 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4292 13:12:00.948708 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4293 13:12:00.951864 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4294 13:12:00.955405 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4295 13:12:00.961672 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4296 13:12:00.965342 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4297 13:12:00.968680 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4298 13:12:00.969063 ==
4299 13:12:00.971678 Dram Type= 6, Freq= 0, CH_0, rank 1
4300 13:12:00.974959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4301 13:12:00.975343 ==
4302 13:12:00.978695 DQS Delay:
4303 13:12:00.979099 DQS0 = 0, DQS1 = 0
4304 13:12:00.981804 DQM Delay:
4305 13:12:00.982310 DQM0 = 41, DQM1 = 32
4306 13:12:00.982745 DQ Delay:
4307 13:12:00.985859 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4308 13:12:00.988245 DQ4 =44, DQ5 =28, DQ6 =52, DQ7 =48
4309 13:12:00.991651 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =24
4310 13:12:00.995053 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4311 13:12:00.995438
4312 13:12:00.998402
4313 13:12:01.004955 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b47, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
4314 13:12:01.008045 CH0 RK1: MR19=808, MR18=4B47
4315 13:12:01.014739 CH0_RK1: MR19=0x808, MR18=0x4B47, DQSOSC=395, MR23=63, INC=168, DEC=112
4316 13:12:01.018145 [RxdqsGatingPostProcess] freq 600
4317 13:12:01.022036 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4318 13:12:01.024364 Pre-setting of DQS Precalculation
4319 13:12:01.031054 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4320 13:12:01.031435 ==
4321 13:12:01.034268 Dram Type= 6, Freq= 0, CH_1, rank 0
4322 13:12:01.037723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 13:12:01.038111 ==
4324 13:12:01.044661 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4325 13:12:01.047874 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4326 13:12:01.052134 [CA 0] Center 36 (6~66) winsize 61
4327 13:12:01.055546 [CA 1] Center 36 (6~66) winsize 61
4328 13:12:01.058567 [CA 2] Center 34 (4~65) winsize 62
4329 13:12:01.062197 [CA 3] Center 34 (4~65) winsize 62
4330 13:12:01.065421 [CA 4] Center 34 (4~65) winsize 62
4331 13:12:01.069214 [CA 5] Center 34 (4~65) winsize 62
4332 13:12:01.069720
4333 13:12:01.071892 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4334 13:12:01.072278
4335 13:12:01.075225 [CATrainingPosCal] consider 1 rank data
4336 13:12:01.078701 u2DelayCellTimex100 = 270/100 ps
4337 13:12:01.081864 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4338 13:12:01.088097 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4339 13:12:01.091653 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4340 13:12:01.095229 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4341 13:12:01.098049 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4342 13:12:01.101537 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4343 13:12:01.102018
4344 13:12:01.104969 CA PerBit enable=1, Macro0, CA PI delay=34
4345 13:12:01.105486
4346 13:12:01.108426 [CBTSetCACLKResult] CA Dly = 34
4347 13:12:01.111908 CS Dly: 5 (0~36)
4348 13:12:01.112293 ==
4349 13:12:01.114622 Dram Type= 6, Freq= 0, CH_1, rank 1
4350 13:12:01.117995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 13:12:01.118396 ==
4352 13:12:01.124774 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4353 13:12:01.127873 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4354 13:12:01.132177 [CA 0] Center 36 (6~66) winsize 61
4355 13:12:01.135356 [CA 1] Center 36 (6~66) winsize 61
4356 13:12:01.138883 [CA 2] Center 35 (5~65) winsize 61
4357 13:12:01.142533 [CA 3] Center 34 (4~65) winsize 62
4358 13:12:01.145312 [CA 4] Center 34 (4~65) winsize 62
4359 13:12:01.148814 [CA 5] Center 34 (4~64) winsize 61
4360 13:12:01.149370
4361 13:12:01.152134 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4362 13:12:01.152629
4363 13:12:01.155531 [CATrainingPosCal] consider 2 rank data
4364 13:12:01.158712 u2DelayCellTimex100 = 270/100 ps
4365 13:12:01.162175 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4366 13:12:01.168356 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4367 13:12:01.171505 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4368 13:12:01.175163 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4369 13:12:01.178535 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4370 13:12:01.181623 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4371 13:12:01.182137
4372 13:12:01.184870 CA PerBit enable=1, Macro0, CA PI delay=34
4373 13:12:01.185394
4374 13:12:01.188190 [CBTSetCACLKResult] CA Dly = 34
4375 13:12:01.191445 CS Dly: 5 (0~36)
4376 13:12:01.191945
4377 13:12:01.194780 ----->DramcWriteLeveling(PI) begin...
4378 13:12:01.195274 ==
4379 13:12:01.198080 Dram Type= 6, Freq= 0, CH_1, rank 0
4380 13:12:01.201737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4381 13:12:01.202232 ==
4382 13:12:01.204551 Write leveling (Byte 0): 29 => 29
4383 13:12:01.207923 Write leveling (Byte 1): 30 => 30
4384 13:12:01.211295 DramcWriteLeveling(PI) end<-----
4385 13:12:01.211799
4386 13:12:01.212245 ==
4387 13:12:01.214504 Dram Type= 6, Freq= 0, CH_1, rank 0
4388 13:12:01.218335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 13:12:01.218833 ==
4390 13:12:01.220989 [Gating] SW mode calibration
4391 13:12:01.228146 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4392 13:12:01.234488 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4393 13:12:01.237748 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4394 13:12:01.241008 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4395 13:12:01.247625 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4396 13:12:01.250866 0 9 12 | B1->B0 | 3232 3030 | 0 0 | (0 1) (1 1)
4397 13:12:01.254708 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4398 13:12:01.260518 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4399 13:12:01.263938 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4400 13:12:01.267264 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4401 13:12:01.273695 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4402 13:12:01.277192 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4403 13:12:01.280309 0 10 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
4404 13:12:01.286935 0 10 12 | B1->B0 | 3636 3737 | 0 0 | (0 0) (0 0)
4405 13:12:01.290311 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4406 13:12:01.293919 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4407 13:12:01.300262 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4408 13:12:01.303922 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4409 13:12:01.307014 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4410 13:12:01.313395 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4411 13:12:01.316492 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4412 13:12:01.319978 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4413 13:12:01.326676 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4414 13:12:01.329893 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4415 13:12:01.333425 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4416 13:12:01.339523 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 13:12:01.343015 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 13:12:01.346379 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 13:12:01.353273 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 13:12:01.356289 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 13:12:01.359285 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 13:12:01.366308 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 13:12:01.369197 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 13:12:01.372448 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 13:12:01.379293 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 13:12:01.382506 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 13:12:01.385819 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 13:12:01.392585 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4429 13:12:01.395795 Total UI for P1: 0, mck2ui 16
4430 13:12:01.399097 best dqsien dly found for B0: ( 0, 13, 10)
4431 13:12:01.402439 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 13:12:01.405683 Total UI for P1: 0, mck2ui 16
4433 13:12:01.408653 best dqsien dly found for B1: ( 0, 13, 12)
4434 13:12:01.411940 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4435 13:12:01.415989 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4436 13:12:01.416376
4437 13:12:01.418940 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4438 13:12:01.425628 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4439 13:12:01.426049 [Gating] SW calibration Done
4440 13:12:01.426445 ==
4441 13:12:01.428478 Dram Type= 6, Freq= 0, CH_1, rank 0
4442 13:12:01.435065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4443 13:12:01.435555 ==
4444 13:12:01.435951 RX Vref Scan: 0
4445 13:12:01.436322
4446 13:12:01.438663 RX Vref 0 -> 0, step: 1
4447 13:12:01.439062
4448 13:12:01.442066 RX Delay -230 -> 252, step: 16
4449 13:12:01.445172 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4450 13:12:01.448225 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4451 13:12:01.455202 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4452 13:12:01.458456 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4453 13:12:01.461883 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4454 13:12:01.465480 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4455 13:12:01.468227 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4456 13:12:01.474997 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4457 13:12:01.478065 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4458 13:12:01.481403 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4459 13:12:01.485115 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4460 13:12:01.491590 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4461 13:12:01.494872 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4462 13:12:01.497792 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4463 13:12:01.501290 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4464 13:12:01.507706 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4465 13:12:01.508109 ==
4466 13:12:01.511857 Dram Type= 6, Freq= 0, CH_1, rank 0
4467 13:12:01.514797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 13:12:01.515198 ==
4469 13:12:01.515502 DQS Delay:
4470 13:12:01.517636 DQS0 = 0, DQS1 = 0
4471 13:12:01.518027 DQM Delay:
4472 13:12:01.521017 DQM0 = 45, DQM1 = 38
4473 13:12:01.521450 DQ Delay:
4474 13:12:01.524327 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4475 13:12:01.527514 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4476 13:12:01.530762 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4477 13:12:01.534198 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4478 13:12:01.534588
4479 13:12:01.534944
4480 13:12:01.535386 ==
4481 13:12:01.537318 Dram Type= 6, Freq= 0, CH_1, rank 0
4482 13:12:01.544026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4483 13:12:01.544416 ==
4484 13:12:01.544721
4485 13:12:01.545000
4486 13:12:01.545317 TX Vref Scan disable
4487 13:12:01.547472 == TX Byte 0 ==
4488 13:12:01.550908 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4489 13:12:01.557486 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4490 13:12:01.558042 == TX Byte 1 ==
4491 13:12:01.560627 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4492 13:12:01.567443 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4493 13:12:01.567837 ==
4494 13:12:01.570248 Dram Type= 6, Freq= 0, CH_1, rank 0
4495 13:12:01.573716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 13:12:01.574226 ==
4497 13:12:01.574696
4498 13:12:01.575149
4499 13:12:01.576838 TX Vref Scan disable
4500 13:12:01.580159 == TX Byte 0 ==
4501 13:12:01.583135 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4502 13:12:01.586544 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4503 13:12:01.589977 == TX Byte 1 ==
4504 13:12:01.593221 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4505 13:12:01.597081 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4506 13:12:01.597625
4507 13:12:01.600032 [DATLAT]
4508 13:12:01.600527 Freq=600, CH1 RK0
4509 13:12:01.600990
4510 13:12:01.603066 DATLAT Default: 0x9
4511 13:12:01.603570 0, 0xFFFF, sum = 0
4512 13:12:01.606501 1, 0xFFFF, sum = 0
4513 13:12:01.606895 2, 0xFFFF, sum = 0
4514 13:12:01.609915 3, 0xFFFF, sum = 0
4515 13:12:01.610449 4, 0xFFFF, sum = 0
4516 13:12:01.613125 5, 0xFFFF, sum = 0
4517 13:12:01.613656 6, 0xFFFF, sum = 0
4518 13:12:01.616397 7, 0xFFFF, sum = 0
4519 13:12:01.616911 8, 0x0, sum = 1
4520 13:12:01.619641 9, 0x0, sum = 2
4521 13:12:01.620067 10, 0x0, sum = 3
4522 13:12:01.623133 11, 0x0, sum = 4
4523 13:12:01.623527 best_step = 9
4524 13:12:01.623875
4525 13:12:01.624169 ==
4526 13:12:01.626171 Dram Type= 6, Freq= 0, CH_1, rank 0
4527 13:12:01.629611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4528 13:12:01.633030 ==
4529 13:12:01.633457 RX Vref Scan: 1
4530 13:12:01.633851
4531 13:12:01.636349 RX Vref 0 -> 0, step: 1
4532 13:12:01.636811
4533 13:12:01.639334 RX Delay -179 -> 252, step: 8
4534 13:12:01.639735
4535 13:12:01.642599 Set Vref, RX VrefLevel [Byte0]: 52
4536 13:12:01.645996 [Byte1]: 53
4537 13:12:01.646398
4538 13:12:01.649529 Final RX Vref Byte 0 = 52 to rank0
4539 13:12:01.652798 Final RX Vref Byte 1 = 53 to rank0
4540 13:12:01.655817 Final RX Vref Byte 0 = 52 to rank1
4541 13:12:01.659251 Final RX Vref Byte 1 = 53 to rank1==
4542 13:12:01.662372 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 13:12:01.665739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 13:12:01.666239 ==
4545 13:12:01.669079 DQS Delay:
4546 13:12:01.669623 DQS0 = 0, DQS1 = 0
4547 13:12:01.670073 DQM Delay:
4548 13:12:01.672529 DQM0 = 43, DQM1 = 36
4549 13:12:01.673011 DQ Delay:
4550 13:12:01.675749 DQ0 =52, DQ1 =40, DQ2 =32, DQ3 =44
4551 13:12:01.678947 DQ4 =36, DQ5 =52, DQ6 =56, DQ7 =36
4552 13:12:01.682556 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =32
4553 13:12:01.685673 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4554 13:12:01.686064
4555 13:12:01.686363
4556 13:12:01.695366 [DQSOSCAuto] RK0, (LSB)MR18= 0x3952, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 399 ps
4557 13:12:01.698902 CH1 RK0: MR19=808, MR18=3952
4558 13:12:01.702397 CH1_RK0: MR19=0x808, MR18=0x3952, DQSOSC=394, MR23=63, INC=168, DEC=112
4559 13:12:01.702790
4560 13:12:01.708858 ----->DramcWriteLeveling(PI) begin...
4561 13:12:01.709285 ==
4562 13:12:01.711947 Dram Type= 6, Freq= 0, CH_1, rank 1
4563 13:12:01.715347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 13:12:01.715740 ==
4565 13:12:01.719052 Write leveling (Byte 0): 30 => 30
4566 13:12:01.721773 Write leveling (Byte 1): 30 => 30
4567 13:12:01.725015 DramcWriteLeveling(PI) end<-----
4568 13:12:01.725570
4569 13:12:01.725884 ==
4570 13:12:01.728363 Dram Type= 6, Freq= 0, CH_1, rank 1
4571 13:12:01.731918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 13:12:01.732307 ==
4573 13:12:01.735171 [Gating] SW mode calibration
4574 13:12:01.741419 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4575 13:12:01.748208 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4576 13:12:01.751317 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4577 13:12:01.754903 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4578 13:12:01.761438 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4579 13:12:01.764777 0 9 12 | B1->B0 | 3131 2f2f | 0 0 | (0 1) (1 1)
4580 13:12:01.768199 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4581 13:12:01.774419 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4582 13:12:01.777807 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4583 13:12:01.781477 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4584 13:12:01.787802 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4585 13:12:01.791154 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4586 13:12:01.793997 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4587 13:12:01.801133 0 10 12 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
4588 13:12:01.803961 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4589 13:12:01.807358 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4590 13:12:01.814234 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4591 13:12:01.817723 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4592 13:12:01.821377 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4593 13:12:01.827080 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4594 13:12:01.830261 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4595 13:12:01.833757 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4596 13:12:01.840183 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4597 13:12:01.843336 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4598 13:12:01.846725 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4599 13:12:01.853871 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4600 13:12:01.856775 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4601 13:12:01.859932 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4602 13:12:01.866565 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 13:12:01.869768 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 13:12:01.873219 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 13:12:01.880199 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 13:12:01.882991 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 13:12:01.886358 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 13:12:01.893410 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 13:12:01.896423 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 13:12:01.899947 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 13:12:01.906060 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 13:12:01.906451 Total UI for P1: 0, mck2ui 16
4613 13:12:01.912768 best dqsien dly found for B0: ( 0, 13, 10)
4614 13:12:01.913193 Total UI for P1: 0, mck2ui 16
4615 13:12:01.919402 best dqsien dly found for B1: ( 0, 13, 10)
4616 13:12:01.922933 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4617 13:12:01.926129 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4618 13:12:01.926517
4619 13:12:01.929672 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4620 13:12:01.932308 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4621 13:12:01.935790 [Gating] SW calibration Done
4622 13:12:01.936180 ==
4623 13:12:01.939336 Dram Type= 6, Freq= 0, CH_1, rank 1
4624 13:12:01.942351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4625 13:12:01.942743 ==
4626 13:12:01.945605 RX Vref Scan: 0
4627 13:12:01.945992
4628 13:12:01.948971 RX Vref 0 -> 0, step: 1
4629 13:12:01.949404
4630 13:12:01.949712 RX Delay -230 -> 252, step: 16
4631 13:12:01.955370 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4632 13:12:01.958476 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4633 13:12:01.962192 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4634 13:12:01.965628 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4635 13:12:01.972047 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4636 13:12:01.975105 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4637 13:12:01.978343 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4638 13:12:01.981785 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4639 13:12:01.988710 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4640 13:12:01.991670 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4641 13:12:01.994674 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4642 13:12:01.998270 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4643 13:12:02.004935 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4644 13:12:02.008070 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4645 13:12:02.011325 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4646 13:12:02.014946 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4647 13:12:02.015335 ==
4648 13:12:02.018083 Dram Type= 6, Freq= 0, CH_1, rank 1
4649 13:12:02.024592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 13:12:02.024985 ==
4651 13:12:02.025339 DQS Delay:
4652 13:12:02.027896 DQS0 = 0, DQS1 = 0
4653 13:12:02.028277 DQM Delay:
4654 13:12:02.028574 DQM0 = 44, DQM1 = 41
4655 13:12:02.031554 DQ Delay:
4656 13:12:02.034566 DQ0 =57, DQ1 =33, DQ2 =33, DQ3 =33
4657 13:12:02.037911 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4658 13:12:02.041188 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4659 13:12:02.044268 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4660 13:12:02.044652
4661 13:12:02.044951
4662 13:12:02.045281 ==
4663 13:12:02.047461 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 13:12:02.051125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 13:12:02.051513 ==
4666 13:12:02.051810
4667 13:12:02.052086
4668 13:12:02.054557 TX Vref Scan disable
4669 13:12:02.057772 == TX Byte 0 ==
4670 13:12:02.061278 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4671 13:12:02.064329 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4672 13:12:02.067524 == TX Byte 1 ==
4673 13:12:02.071109 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4674 13:12:02.074029 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4675 13:12:02.074413 ==
4676 13:12:02.077164 Dram Type= 6, Freq= 0, CH_1, rank 1
4677 13:12:02.083920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4678 13:12:02.084420 ==
4679 13:12:02.084729
4680 13:12:02.085007
4681 13:12:02.085349 TX Vref Scan disable
4682 13:12:02.087800 == TX Byte 0 ==
4683 13:12:02.091245 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4684 13:12:02.097899 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4685 13:12:02.098288 == TX Byte 1 ==
4686 13:12:02.101329 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4687 13:12:02.107667 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4688 13:12:02.108069
4689 13:12:02.108362 [DATLAT]
4690 13:12:02.108679 Freq=600, CH1 RK1
4691 13:12:02.108949
4692 13:12:02.111182 DATLAT Default: 0x9
4693 13:12:02.111573 0, 0xFFFF, sum = 0
4694 13:12:02.114481 1, 0xFFFF, sum = 0
4695 13:12:02.117856 2, 0xFFFF, sum = 0
4696 13:12:02.118249 3, 0xFFFF, sum = 0
4697 13:12:02.120907 4, 0xFFFF, sum = 0
4698 13:12:02.121396 5, 0xFFFF, sum = 0
4699 13:12:02.123955 6, 0xFFFF, sum = 0
4700 13:12:02.124348 7, 0xFFFF, sum = 0
4701 13:12:02.127600 8, 0x0, sum = 1
4702 13:12:02.127993 9, 0x0, sum = 2
4703 13:12:02.130978 10, 0x0, sum = 3
4704 13:12:02.131370 11, 0x0, sum = 4
4705 13:12:02.131680 best_step = 9
4706 13:12:02.131958
4707 13:12:02.134188 ==
4708 13:12:02.137563 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 13:12:02.140342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 13:12:02.140730 ==
4711 13:12:02.141031 RX Vref Scan: 0
4712 13:12:02.141395
4713 13:12:02.143675 RX Vref 0 -> 0, step: 1
4714 13:12:02.144063
4715 13:12:02.146994 RX Delay -179 -> 252, step: 8
4716 13:12:02.153611 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4717 13:12:02.156928 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4718 13:12:02.160023 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4719 13:12:02.163473 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4720 13:12:02.169926 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4721 13:12:02.173675 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4722 13:12:02.176403 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4723 13:12:02.179964 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4724 13:12:02.183345 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4725 13:12:02.189768 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4726 13:12:02.193421 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4727 13:12:02.196682 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4728 13:12:02.200076 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4729 13:12:02.206484 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4730 13:12:02.209630 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4731 13:12:02.212981 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4732 13:12:02.213415 ==
4733 13:12:02.215954 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 13:12:02.222862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 13:12:02.223252 ==
4736 13:12:02.223555 DQS Delay:
4737 13:12:02.226298 DQS0 = 0, DQS1 = 0
4738 13:12:02.226681 DQM Delay:
4739 13:12:02.226981 DQM0 = 39, DQM1 = 36
4740 13:12:02.229340 DQ Delay:
4741 13:12:02.232692 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4742 13:12:02.235771 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4743 13:12:02.238957 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4744 13:12:02.242845 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4745 13:12:02.243266
4746 13:12:02.243568
4747 13:12:02.248799 [DQSOSCAuto] RK1, (LSB)MR18= 0x385c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4748 13:12:02.252266 CH1 RK1: MR19=808, MR18=385C
4749 13:12:02.258818 CH1_RK1: MR19=0x808, MR18=0x385C, DQSOSC=392, MR23=63, INC=170, DEC=113
4750 13:12:02.262280 [RxdqsGatingPostProcess] freq 600
4751 13:12:02.266002 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4752 13:12:02.268870 Pre-setting of DQS Precalculation
4753 13:12:02.275854 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4754 13:12:02.282194 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4755 13:12:02.288519 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4756 13:12:02.288927
4757 13:12:02.289284
4758 13:12:02.291820 [Calibration Summary] 1200 Mbps
4759 13:12:02.292206 CH 0, Rank 0
4760 13:12:02.295127 SW Impedance : PASS
4761 13:12:02.298544 DUTY Scan : NO K
4762 13:12:02.298932 ZQ Calibration : PASS
4763 13:12:02.302040 Jitter Meter : NO K
4764 13:12:02.305177 CBT Training : PASS
4765 13:12:02.305635 Write leveling : PASS
4766 13:12:02.308581 RX DQS gating : PASS
4767 13:12:02.311503 RX DQ/DQS(RDDQC) : PASS
4768 13:12:02.311899 TX DQ/DQS : PASS
4769 13:12:02.315289 RX DATLAT : PASS
4770 13:12:02.318208 RX DQ/DQS(Engine): PASS
4771 13:12:02.318593 TX OE : NO K
4772 13:12:02.321665 All Pass.
4773 13:12:02.322049
4774 13:12:02.322347 CH 0, Rank 1
4775 13:12:02.324968 SW Impedance : PASS
4776 13:12:02.325437 DUTY Scan : NO K
4777 13:12:02.327911 ZQ Calibration : PASS
4778 13:12:02.331397 Jitter Meter : NO K
4779 13:12:02.331783 CBT Training : PASS
4780 13:12:02.334646 Write leveling : PASS
4781 13:12:02.337992 RX DQS gating : PASS
4782 13:12:02.338375 RX DQ/DQS(RDDQC) : PASS
4783 13:12:02.341475 TX DQ/DQS : PASS
4784 13:12:02.344504 RX DATLAT : PASS
4785 13:12:02.344888 RX DQ/DQS(Engine): PASS
4786 13:12:02.347786 TX OE : NO K
4787 13:12:02.348215 All Pass.
4788 13:12:02.348521
4789 13:12:02.351238 CH 1, Rank 0
4790 13:12:02.351623 SW Impedance : PASS
4791 13:12:02.354662 DUTY Scan : NO K
4792 13:12:02.358051 ZQ Calibration : PASS
4793 13:12:02.358468 Jitter Meter : NO K
4794 13:12:02.360978 CBT Training : PASS
4795 13:12:02.364040 Write leveling : PASS
4796 13:12:02.364427 RX DQS gating : PASS
4797 13:12:02.367328 RX DQ/DQS(RDDQC) : PASS
4798 13:12:02.371379 TX DQ/DQS : PASS
4799 13:12:02.371765 RX DATLAT : PASS
4800 13:12:02.374519 RX DQ/DQS(Engine): PASS
4801 13:12:02.374913 TX OE : NO K
4802 13:12:02.377487 All Pass.
4803 13:12:02.377877
4804 13:12:02.378179 CH 1, Rank 1
4805 13:12:02.380875 SW Impedance : PASS
4806 13:12:02.381382 DUTY Scan : NO K
4807 13:12:02.384249 ZQ Calibration : PASS
4808 13:12:02.387622 Jitter Meter : NO K
4809 13:12:02.388013 CBT Training : PASS
4810 13:12:02.391149 Write leveling : PASS
4811 13:12:02.393891 RX DQS gating : PASS
4812 13:12:02.394282 RX DQ/DQS(RDDQC) : PASS
4813 13:12:02.397825 TX DQ/DQS : PASS
4814 13:12:02.400862 RX DATLAT : PASS
4815 13:12:02.401384 RX DQ/DQS(Engine): PASS
4816 13:12:02.403952 TX OE : NO K
4817 13:12:02.404342 All Pass.
4818 13:12:02.404642
4819 13:12:02.407277 DramC Write-DBI off
4820 13:12:02.410627 PER_BANK_REFRESH: Hybrid Mode
4821 13:12:02.411016 TX_TRACKING: ON
4822 13:12:02.420704 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4823 13:12:02.423676 [FAST_K] Save calibration result to emmc
4824 13:12:02.427298 dramc_set_vcore_voltage set vcore to 662500
4825 13:12:02.430612 Read voltage for 933, 3
4826 13:12:02.431000 Vio18 = 0
4827 13:12:02.431305 Vcore = 662500
4828 13:12:02.433877 Vdram = 0
4829 13:12:02.434264 Vddq = 0
4830 13:12:02.434566 Vmddr = 0
4831 13:12:02.440345 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4832 13:12:02.443610 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4833 13:12:02.447231 MEM_TYPE=3, freq_sel=17
4834 13:12:02.449986 sv_algorithm_assistance_LP4_1600
4835 13:12:02.453333 ============ PULL DRAM RESETB DOWN ============
4836 13:12:02.460413 ========== PULL DRAM RESETB DOWN end =========
4837 13:12:02.463537 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4838 13:12:02.466667 ===================================
4839 13:12:02.469940 LPDDR4 DRAM CONFIGURATION
4840 13:12:02.473372 ===================================
4841 13:12:02.473762 EX_ROW_EN[0] = 0x0
4842 13:12:02.476391 EX_ROW_EN[1] = 0x0
4843 13:12:02.476776 LP4Y_EN = 0x0
4844 13:12:02.479556 WORK_FSP = 0x0
4845 13:12:02.479945 WL = 0x3
4846 13:12:02.483168 RL = 0x3
4847 13:12:02.483574 BL = 0x2
4848 13:12:02.486508 RPST = 0x0
4849 13:12:02.489850 RD_PRE = 0x0
4850 13:12:02.490235 WR_PRE = 0x1
4851 13:12:02.493063 WR_PST = 0x0
4852 13:12:02.493493 DBI_WR = 0x0
4853 13:12:02.496405 DBI_RD = 0x0
4854 13:12:02.496791 OTF = 0x1
4855 13:12:02.499412 ===================================
4856 13:12:02.502977 ===================================
4857 13:12:02.505936 ANA top config
4858 13:12:02.509261 ===================================
4859 13:12:02.509650 DLL_ASYNC_EN = 0
4860 13:12:02.512969 ALL_SLAVE_EN = 1
4861 13:12:02.516055 NEW_RANK_MODE = 1
4862 13:12:02.519109 DLL_IDLE_MODE = 1
4863 13:12:02.519497 LP45_APHY_COMB_EN = 1
4864 13:12:02.522424 TX_ODT_DIS = 1
4865 13:12:02.525628 NEW_8X_MODE = 1
4866 13:12:02.529191 ===================================
4867 13:12:02.532523 ===================================
4868 13:12:02.535927 data_rate = 1866
4869 13:12:02.538779 CKR = 1
4870 13:12:02.542163 DQ_P2S_RATIO = 8
4871 13:12:02.545503 ===================================
4872 13:12:02.545891 CA_P2S_RATIO = 8
4873 13:12:02.548861 DQ_CA_OPEN = 0
4874 13:12:02.552354 DQ_SEMI_OPEN = 0
4875 13:12:02.555196 CA_SEMI_OPEN = 0
4876 13:12:02.558659 CA_FULL_RATE = 0
4877 13:12:02.562103 DQ_CKDIV4_EN = 1
4878 13:12:02.562492 CA_CKDIV4_EN = 1
4879 13:12:02.565601 CA_PREDIV_EN = 0
4880 13:12:02.568896 PH8_DLY = 0
4881 13:12:02.572148 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4882 13:12:02.574908 DQ_AAMCK_DIV = 4
4883 13:12:02.578244 CA_AAMCK_DIV = 4
4884 13:12:02.581448 CA_ADMCK_DIV = 4
4885 13:12:02.581838 DQ_TRACK_CA_EN = 0
4886 13:12:02.585080 CA_PICK = 933
4887 13:12:02.588326 CA_MCKIO = 933
4888 13:12:02.591467 MCKIO_SEMI = 0
4889 13:12:02.594848 PLL_FREQ = 3732
4890 13:12:02.597828 DQ_UI_PI_RATIO = 32
4891 13:12:02.601656 CA_UI_PI_RATIO = 0
4892 13:12:02.604901 ===================================
4893 13:12:02.608240 ===================================
4894 13:12:02.608629 memory_type:LPDDR4
4895 13:12:02.611653 GP_NUM : 10
4896 13:12:02.614651 SRAM_EN : 1
4897 13:12:02.615040 MD32_EN : 0
4898 13:12:02.617960 ===================================
4899 13:12:02.621007 [ANA_INIT] >>>>>>>>>>>>>>
4900 13:12:02.624572 <<<<<< [CONFIGURE PHASE]: ANA_TX
4901 13:12:02.627736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4902 13:12:02.630875 ===================================
4903 13:12:02.634448 data_rate = 1866,PCW = 0X8f00
4904 13:12:02.638028 ===================================
4905 13:12:02.640741 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4906 13:12:02.644129 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4907 13:12:02.651111 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4908 13:12:02.654128 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4909 13:12:02.657608 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4910 13:12:02.660603 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4911 13:12:02.664183 [ANA_INIT] flow start
4912 13:12:02.667499 [ANA_INIT] PLL >>>>>>>>
4913 13:12:02.667889 [ANA_INIT] PLL <<<<<<<<
4914 13:12:02.670485 [ANA_INIT] MIDPI >>>>>>>>
4915 13:12:02.674304 [ANA_INIT] MIDPI <<<<<<<<
4916 13:12:02.677606 [ANA_INIT] DLL >>>>>>>>
4917 13:12:02.677998 [ANA_INIT] flow end
4918 13:12:02.680627 ============ LP4 DIFF to SE enter ============
4919 13:12:02.687359 ============ LP4 DIFF to SE exit ============
4920 13:12:02.687750 [ANA_INIT] <<<<<<<<<<<<<
4921 13:12:02.690285 [Flow] Enable top DCM control >>>>>
4922 13:12:02.693818 [Flow] Enable top DCM control <<<<<
4923 13:12:02.697335 Enable DLL master slave shuffle
4924 13:12:02.703496 ==============================================================
4925 13:12:02.703884 Gating Mode config
4926 13:12:02.710391 ==============================================================
4927 13:12:02.713649 Config description:
4928 13:12:02.723545 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4929 13:12:02.729842 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4930 13:12:02.733399 SELPH_MODE 0: By rank 1: By Phase
4931 13:12:02.740052 ==============================================================
4932 13:12:02.743473 GAT_TRACK_EN = 1
4933 13:12:02.746507 RX_GATING_MODE = 2
4934 13:12:02.749776 RX_GATING_TRACK_MODE = 2
4935 13:12:02.750163 SELPH_MODE = 1
4936 13:12:02.753030 PICG_EARLY_EN = 1
4937 13:12:02.756212 VALID_LAT_VALUE = 1
4938 13:12:02.763066 ==============================================================
4939 13:12:02.766626 Enter into Gating configuration >>>>
4940 13:12:02.769927 Exit from Gating configuration <<<<
4941 13:12:02.772868 Enter into DVFS_PRE_config >>>>>
4942 13:12:02.782786 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4943 13:12:02.785707 Exit from DVFS_PRE_config <<<<<
4944 13:12:02.789042 Enter into PICG configuration >>>>
4945 13:12:02.792498 Exit from PICG configuration <<<<
4946 13:12:02.796186 [RX_INPUT] configuration >>>>>
4947 13:12:02.799039 [RX_INPUT] configuration <<<<<
4948 13:12:02.805919 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4949 13:12:02.809220 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4950 13:12:02.815386 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4951 13:12:02.821891 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4952 13:12:02.828568 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4953 13:12:02.835355 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4954 13:12:02.838717 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4955 13:12:02.841905 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4956 13:12:02.845045 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4957 13:12:02.851779 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4958 13:12:02.854959 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4959 13:12:02.858032 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4960 13:12:02.861677 ===================================
4961 13:12:02.864931 LPDDR4 DRAM CONFIGURATION
4962 13:12:02.868081 ===================================
4963 13:12:02.871168 EX_ROW_EN[0] = 0x0
4964 13:12:02.871675 EX_ROW_EN[1] = 0x0
4965 13:12:02.874477 LP4Y_EN = 0x0
4966 13:12:02.874937 WORK_FSP = 0x0
4967 13:12:02.878008 WL = 0x3
4968 13:12:02.878393 RL = 0x3
4969 13:12:02.881504 BL = 0x2
4970 13:12:02.881891 RPST = 0x0
4971 13:12:02.884682 RD_PRE = 0x0
4972 13:12:02.885068 WR_PRE = 0x1
4973 13:12:02.888193 WR_PST = 0x0
4974 13:12:02.888582 DBI_WR = 0x0
4975 13:12:02.891071 DBI_RD = 0x0
4976 13:12:02.891463 OTF = 0x1
4977 13:12:02.894788 ===================================
4978 13:12:02.900910 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4979 13:12:02.904534 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4980 13:12:02.907747 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4981 13:12:02.911148 ===================================
4982 13:12:02.914089 LPDDR4 DRAM CONFIGURATION
4983 13:12:02.917644 ===================================
4984 13:12:02.920617 EX_ROW_EN[0] = 0x10
4985 13:12:02.921014 EX_ROW_EN[1] = 0x0
4986 13:12:02.924146 LP4Y_EN = 0x0
4987 13:12:02.924543 WORK_FSP = 0x0
4988 13:12:02.927512 WL = 0x3
4989 13:12:02.927910 RL = 0x3
4990 13:12:02.930536 BL = 0x2
4991 13:12:02.930935 RPST = 0x0
4992 13:12:02.933966 RD_PRE = 0x0
4993 13:12:02.934365 WR_PRE = 0x1
4994 13:12:02.937568 WR_PST = 0x0
4995 13:12:02.937955 DBI_WR = 0x0
4996 13:12:02.940858 DBI_RD = 0x0
4997 13:12:02.941279 OTF = 0x1
4998 13:12:02.943834 ===================================
4999 13:12:02.950159 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5000 13:12:02.955266 nWR fixed to 30
5001 13:12:02.958888 [ModeRegInit_LP4] CH0 RK0
5002 13:12:02.959317 [ModeRegInit_LP4] CH0 RK1
5003 13:12:02.962109 [ModeRegInit_LP4] CH1 RK0
5004 13:12:02.965450 [ModeRegInit_LP4] CH1 RK1
5005 13:12:02.965834 match AC timing 9
5006 13:12:02.971828 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5007 13:12:02.975211 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5008 13:12:02.978445 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5009 13:12:02.985052 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5010 13:12:02.988243 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5011 13:12:02.988629 ==
5012 13:12:02.991466 Dram Type= 6, Freq= 0, CH_0, rank 0
5013 13:12:02.994464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5014 13:12:02.997995 ==
5015 13:12:03.001333 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5016 13:12:03.008087 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5017 13:12:03.011511 [CA 0] Center 37 (7~68) winsize 62
5018 13:12:03.014434 [CA 1] Center 37 (7~68) winsize 62
5019 13:12:03.017891 [CA 2] Center 34 (4~64) winsize 61
5020 13:12:03.021233 [CA 3] Center 34 (4~65) winsize 62
5021 13:12:03.024574 [CA 4] Center 33 (2~64) winsize 63
5022 13:12:03.027573 [CA 5] Center 32 (2~63) winsize 62
5023 13:12:03.027997
5024 13:12:03.030983 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5025 13:12:03.031586
5026 13:12:03.034204 [CATrainingPosCal] consider 1 rank data
5027 13:12:03.037946 u2DelayCellTimex100 = 270/100 ps
5028 13:12:03.040905 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5029 13:12:03.044596 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5030 13:12:03.047772 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5031 13:12:03.054104 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5032 13:12:03.057226 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5033 13:12:03.060412 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5034 13:12:03.060798
5035 13:12:03.064023 CA PerBit enable=1, Macro0, CA PI delay=32
5036 13:12:03.064546
5037 13:12:03.067459 [CBTSetCACLKResult] CA Dly = 32
5038 13:12:03.067848 CS Dly: 6 (0~37)
5039 13:12:03.068282 ==
5040 13:12:03.070619 Dram Type= 6, Freq= 0, CH_0, rank 1
5041 13:12:03.077030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5042 13:12:03.077470 ==
5043 13:12:03.080592 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5044 13:12:03.087161 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5045 13:12:03.090707 [CA 0] Center 37 (7~68) winsize 62
5046 13:12:03.093661 [CA 1] Center 37 (7~68) winsize 62
5047 13:12:03.096851 [CA 2] Center 34 (4~65) winsize 62
5048 13:12:03.100393 [CA 3] Center 34 (4~65) winsize 62
5049 13:12:03.104008 [CA 4] Center 33 (3~64) winsize 62
5050 13:12:03.106909 [CA 5] Center 32 (2~63) winsize 62
5051 13:12:03.107305
5052 13:12:03.110370 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5053 13:12:03.110760
5054 13:12:03.113612 [CATrainingPosCal] consider 2 rank data
5055 13:12:03.117045 u2DelayCellTimex100 = 270/100 ps
5056 13:12:03.119906 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5057 13:12:03.126588 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5058 13:12:03.130066 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5059 13:12:03.133474 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5060 13:12:03.136558 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5061 13:12:03.139998 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5062 13:12:03.140448
5063 13:12:03.142711 CA PerBit enable=1, Macro0, CA PI delay=32
5064 13:12:03.143104
5065 13:12:03.146255 [CBTSetCACLKResult] CA Dly = 32
5066 13:12:03.149463 CS Dly: 7 (0~39)
5067 13:12:03.149969
5068 13:12:03.152723 ----->DramcWriteLeveling(PI) begin...
5069 13:12:03.153117 ==
5070 13:12:03.156209 Dram Type= 6, Freq= 0, CH_0, rank 0
5071 13:12:03.159261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5072 13:12:03.159657 ==
5073 13:12:03.162704 Write leveling (Byte 0): 31 => 31
5074 13:12:03.166101 Write leveling (Byte 1): 28 => 28
5075 13:12:03.169081 DramcWriteLeveling(PI) end<-----
5076 13:12:03.169539
5077 13:12:03.169997 ==
5078 13:12:03.172514 Dram Type= 6, Freq= 0, CH_0, rank 0
5079 13:12:03.175670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5080 13:12:03.176076 ==
5081 13:12:03.179083 [Gating] SW mode calibration
5082 13:12:03.185430 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5083 13:12:03.191930 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5084 13:12:03.195578 0 14 0 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
5085 13:12:03.201815 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5086 13:12:03.205228 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5087 13:12:03.208662 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5088 13:12:03.215048 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5089 13:12:03.218154 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5090 13:12:03.221344 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5091 13:12:03.228112 0 14 28 | B1->B0 | 3434 2828 | 1 1 | (0 0) (1 0)
5092 13:12:03.231412 0 15 0 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (0 0)
5093 13:12:03.234885 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5094 13:12:03.241856 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5095 13:12:03.244778 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5096 13:12:03.248170 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5097 13:12:03.254383 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5098 13:12:03.258062 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5099 13:12:03.261153 0 15 28 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (1 1)
5100 13:12:03.267778 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5101 13:12:03.270943 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5102 13:12:03.274658 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5103 13:12:03.281312 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5104 13:12:03.284319 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5105 13:12:03.287691 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5106 13:12:03.294448 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5107 13:12:03.297239 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5108 13:12:03.300612 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5109 13:12:03.307191 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5110 13:12:03.310723 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5111 13:12:03.313505 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5112 13:12:03.320245 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5113 13:12:03.323549 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 13:12:03.326769 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 13:12:03.333603 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 13:12:03.336820 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 13:12:03.339815 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 13:12:03.346486 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 13:12:03.350078 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 13:12:03.353286 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 13:12:03.359653 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 13:12:03.362885 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5123 13:12:03.366646 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5124 13:12:03.370084 Total UI for P1: 0, mck2ui 16
5125 13:12:03.373114 best dqsien dly found for B0: ( 1, 2, 24)
5126 13:12:03.379709 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5127 13:12:03.382870 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 13:12:03.386041 Total UI for P1: 0, mck2ui 16
5129 13:12:03.389601 best dqsien dly found for B1: ( 1, 2, 30)
5130 13:12:03.393116 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5131 13:12:03.395961 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5132 13:12:03.396044
5133 13:12:03.399392 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5134 13:12:03.402876 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5135 13:12:03.405658 [Gating] SW calibration Done
5136 13:12:03.405741 ==
5137 13:12:03.408983 Dram Type= 6, Freq= 0, CH_0, rank 0
5138 13:12:03.415687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5139 13:12:03.415763 ==
5140 13:12:03.415822 RX Vref Scan: 0
5141 13:12:03.415876
5142 13:12:03.419164 RX Vref 0 -> 0, step: 1
5143 13:12:03.419329
5144 13:12:03.422458 RX Delay -80 -> 252, step: 8
5145 13:12:03.425436 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5146 13:12:03.428984 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5147 13:12:03.432107 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5148 13:12:03.435523 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5149 13:12:03.441858 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5150 13:12:03.445387 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5151 13:12:03.448493 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5152 13:12:03.451912 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5153 13:12:03.455635 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5154 13:12:03.458411 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5155 13:12:03.465042 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5156 13:12:03.468344 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5157 13:12:03.472265 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5158 13:12:03.475148 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5159 13:12:03.478586 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5160 13:12:03.485279 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5161 13:12:03.485466 ==
5162 13:12:03.488325 Dram Type= 6, Freq= 0, CH_0, rank 0
5163 13:12:03.491644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5164 13:12:03.491920 ==
5165 13:12:03.492133 DQS Delay:
5166 13:12:03.495371 DQS0 = 0, DQS1 = 0
5167 13:12:03.495697 DQM Delay:
5168 13:12:03.498278 DQM0 = 99, DQM1 = 88
5169 13:12:03.498736 DQ Delay:
5170 13:12:03.502276 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5171 13:12:03.505506 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =111
5172 13:12:03.508335 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5173 13:12:03.511619 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5174 13:12:03.512006
5175 13:12:03.512306
5176 13:12:03.512579 ==
5177 13:12:03.514952 Dram Type= 6, Freq= 0, CH_0, rank 0
5178 13:12:03.518470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5179 13:12:03.518879 ==
5180 13:12:03.521883
5181 13:12:03.522277
5182 13:12:03.522579 TX Vref Scan disable
5183 13:12:03.525190 == TX Byte 0 ==
5184 13:12:03.528116 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5185 13:12:03.531641 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5186 13:12:03.534918 == TX Byte 1 ==
5187 13:12:03.538543 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5188 13:12:03.541438 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5189 13:12:03.544961 ==
5190 13:12:03.548264 Dram Type= 6, Freq= 0, CH_0, rank 0
5191 13:12:03.551176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5192 13:12:03.551563 ==
5193 13:12:03.551862
5194 13:12:03.552135
5195 13:12:03.554561 TX Vref Scan disable
5196 13:12:03.554944 == TX Byte 0 ==
5197 13:12:03.561167 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5198 13:12:03.564508 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5199 13:12:03.564891 == TX Byte 1 ==
5200 13:12:03.571221 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5201 13:12:03.574439 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5202 13:12:03.574828
5203 13:12:03.575128 [DATLAT]
5204 13:12:03.577733 Freq=933, CH0 RK0
5205 13:12:03.578141
5206 13:12:03.578443 DATLAT Default: 0xd
5207 13:12:03.580775 0, 0xFFFF, sum = 0
5208 13:12:03.581192 1, 0xFFFF, sum = 0
5209 13:12:03.584342 2, 0xFFFF, sum = 0
5210 13:12:03.584731 3, 0xFFFF, sum = 0
5211 13:12:03.587824 4, 0xFFFF, sum = 0
5212 13:12:03.591003 5, 0xFFFF, sum = 0
5213 13:12:03.591527 6, 0xFFFF, sum = 0
5214 13:12:03.594242 7, 0xFFFF, sum = 0
5215 13:12:03.594757 8, 0xFFFF, sum = 0
5216 13:12:03.597864 9, 0xFFFF, sum = 0
5217 13:12:03.598438 10, 0x0, sum = 1
5218 13:12:03.601249 11, 0x0, sum = 2
5219 13:12:03.601845 12, 0x0, sum = 3
5220 13:12:03.604035 13, 0x0, sum = 4
5221 13:12:03.604548 best_step = 11
5222 13:12:03.605011
5223 13:12:03.605525 ==
5224 13:12:03.607260 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 13:12:03.610551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 13:12:03.611038 ==
5227 13:12:03.613991 RX Vref Scan: 1
5228 13:12:03.614488
5229 13:12:03.617255 RX Vref 0 -> 0, step: 1
5230 13:12:03.617750
5231 13:12:03.618199 RX Delay -61 -> 252, step: 4
5232 13:12:03.618635
5233 13:12:03.620517 Set Vref, RX VrefLevel [Byte0]: 54
5234 13:12:03.623405 [Byte1]: 59
5235 13:12:03.628287
5236 13:12:03.628632 Final RX Vref Byte 0 = 54 to rank0
5237 13:12:03.631926 Final RX Vref Byte 1 = 59 to rank0
5238 13:12:03.635336 Final RX Vref Byte 0 = 54 to rank1
5239 13:12:03.638481 Final RX Vref Byte 1 = 59 to rank1==
5240 13:12:03.642062 Dram Type= 6, Freq= 0, CH_0, rank 0
5241 13:12:03.648102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5242 13:12:03.648503 ==
5243 13:12:03.648805 DQS Delay:
5244 13:12:03.651345 DQS0 = 0, DQS1 = 0
5245 13:12:03.651736 DQM Delay:
5246 13:12:03.652037 DQM0 = 98, DQM1 = 87
5247 13:12:03.654832 DQ Delay:
5248 13:12:03.658137 DQ0 =100, DQ1 =100, DQ2 =92, DQ3 =94
5249 13:12:03.661307 DQ4 =100, DQ5 =90, DQ6 =106, DQ7 =106
5250 13:12:03.664714 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =82
5251 13:12:03.667924 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =94
5252 13:12:03.668305
5253 13:12:03.668599
5254 13:12:03.675152 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 412 ps
5255 13:12:03.678238 CH0 RK0: MR19=505, MR18=1D18
5256 13:12:03.684306 CH0_RK0: MR19=0x505, MR18=0x1D18, DQSOSC=412, MR23=63, INC=63, DEC=42
5257 13:12:03.684691
5258 13:12:03.687794 ----->DramcWriteLeveling(PI) begin...
5259 13:12:03.688183 ==
5260 13:12:03.690981 Dram Type= 6, Freq= 0, CH_0, rank 1
5261 13:12:03.694883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 13:12:03.695268 ==
5263 13:12:03.697882 Write leveling (Byte 0): 31 => 31
5264 13:12:03.701024 Write leveling (Byte 1): 27 => 27
5265 13:12:03.704086 DramcWriteLeveling(PI) end<-----
5266 13:12:03.704509
5267 13:12:03.704812 ==
5268 13:12:03.707443 Dram Type= 6, Freq= 0, CH_0, rank 1
5269 13:12:03.713907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 13:12:03.714443 ==
5271 13:12:03.717379 [Gating] SW mode calibration
5272 13:12:03.723910 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5273 13:12:03.727140 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5274 13:12:03.733688 0 14 0 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
5275 13:12:03.737067 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5276 13:12:03.740296 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5277 13:12:03.747249 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5278 13:12:03.750041 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5279 13:12:03.753845 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5280 13:12:03.760522 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5281 13:12:03.763452 0 14 28 | B1->B0 | 3232 2b2b | 0 0 | (0 1) (0 0)
5282 13:12:03.766875 0 15 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5283 13:12:03.773798 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5284 13:12:03.776607 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5285 13:12:03.780101 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5286 13:12:03.786464 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5287 13:12:03.789449 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5288 13:12:03.792840 0 15 24 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
5289 13:12:03.799856 0 15 28 | B1->B0 | 2e2d 3f3f | 1 0 | (1 1) (0 0)
5290 13:12:03.803108 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5291 13:12:03.806160 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5292 13:12:03.813203 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5293 13:12:03.816120 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5294 13:12:03.819349 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5295 13:12:03.826233 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5296 13:12:03.829281 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5297 13:12:03.832536 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5298 13:12:03.839181 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5299 13:12:03.842669 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5300 13:12:03.845979 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5301 13:12:03.852106 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5302 13:12:03.855609 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5303 13:12:03.858654 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5304 13:12:03.865510 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5305 13:12:03.868862 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 13:12:03.872305 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 13:12:03.878824 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 13:12:03.882001 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 13:12:03.885488 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 13:12:03.891662 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 13:12:03.895065 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 13:12:03.898353 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 13:12:03.905219 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5314 13:12:03.908216 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 13:12:03.911696 Total UI for P1: 0, mck2ui 16
5316 13:12:03.915141 best dqsien dly found for B0: ( 1, 2, 28)
5317 13:12:03.918098 Total UI for P1: 0, mck2ui 16
5318 13:12:03.921725 best dqsien dly found for B1: ( 1, 2, 28)
5319 13:12:03.925209 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5320 13:12:03.928348 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5321 13:12:03.928705
5322 13:12:03.931498 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5323 13:12:03.934507 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5324 13:12:03.937974 [Gating] SW calibration Done
5325 13:12:03.938397 ==
5326 13:12:03.941239 Dram Type= 6, Freq= 0, CH_0, rank 1
5327 13:12:03.944642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5328 13:12:03.947998 ==
5329 13:12:03.948499 RX Vref Scan: 0
5330 13:12:03.948896
5331 13:12:03.951096 RX Vref 0 -> 0, step: 1
5332 13:12:03.951586
5333 13:12:03.954435 RX Delay -80 -> 252, step: 8
5334 13:12:03.957800 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5335 13:12:03.960966 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5336 13:12:03.964697 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5337 13:12:03.967479 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5338 13:12:03.971036 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5339 13:12:03.977852 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5340 13:12:03.981270 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5341 13:12:03.984395 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5342 13:12:03.987434 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5343 13:12:03.990841 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5344 13:12:03.994150 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5345 13:12:04.000419 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5346 13:12:04.003869 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5347 13:12:04.007337 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5348 13:12:04.010201 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5349 13:12:04.013380 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5350 13:12:04.016948 ==
5351 13:12:04.017446 Dram Type= 6, Freq= 0, CH_0, rank 1
5352 13:12:04.023561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5353 13:12:04.023949 ==
5354 13:12:04.024247 DQS Delay:
5355 13:12:04.027150 DQS0 = 0, DQS1 = 0
5356 13:12:04.027559 DQM Delay:
5357 13:12:04.029988 DQM0 = 97, DQM1 = 90
5358 13:12:04.030375 DQ Delay:
5359 13:12:04.033724 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5360 13:12:04.036499 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5361 13:12:04.040025 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5362 13:12:04.043094 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5363 13:12:04.043569
5364 13:12:04.043873
5365 13:12:04.044151 ==
5366 13:12:04.046421 Dram Type= 6, Freq= 0, CH_0, rank 1
5367 13:12:04.049696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5368 13:12:04.050086 ==
5369 13:12:04.050385
5370 13:12:04.053113
5371 13:12:04.053539 TX Vref Scan disable
5372 13:12:04.056350 == TX Byte 0 ==
5373 13:12:04.059869 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5374 13:12:04.063165 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5375 13:12:04.066345 == TX Byte 1 ==
5376 13:12:04.069879 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5377 13:12:04.072862 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5378 13:12:04.073481 ==
5379 13:12:04.076112 Dram Type= 6, Freq= 0, CH_0, rank 1
5380 13:12:04.083009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 13:12:04.083393 ==
5382 13:12:04.083822
5383 13:12:04.084251
5384 13:12:04.084731 TX Vref Scan disable
5385 13:12:04.087303 == TX Byte 0 ==
5386 13:12:04.090614 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5387 13:12:04.096974 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5388 13:12:04.097453 == TX Byte 1 ==
5389 13:12:04.100584 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5390 13:12:04.107108 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5391 13:12:04.107489
5392 13:12:04.107779 [DATLAT]
5393 13:12:04.108051 Freq=933, CH0 RK1
5394 13:12:04.108315
5395 13:12:04.110428 DATLAT Default: 0xb
5396 13:12:04.113492 0, 0xFFFF, sum = 0
5397 13:12:04.113883 1, 0xFFFF, sum = 0
5398 13:12:04.117296 2, 0xFFFF, sum = 0
5399 13:12:04.117750 3, 0xFFFF, sum = 0
5400 13:12:04.120135 4, 0xFFFF, sum = 0
5401 13:12:04.120528 5, 0xFFFF, sum = 0
5402 13:12:04.123640 6, 0xFFFF, sum = 0
5403 13:12:04.124032 7, 0xFFFF, sum = 0
5404 13:12:04.126978 8, 0xFFFF, sum = 0
5405 13:12:04.127422 9, 0xFFFF, sum = 0
5406 13:12:04.130273 10, 0x0, sum = 1
5407 13:12:04.130795 11, 0x0, sum = 2
5408 13:12:04.133409 12, 0x0, sum = 3
5409 13:12:04.133801 13, 0x0, sum = 4
5410 13:12:04.134103 best_step = 11
5411 13:12:04.136543
5412 13:12:04.136926 ==
5413 13:12:04.140117 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 13:12:04.143533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 13:12:04.144077 ==
5416 13:12:04.144565 RX Vref Scan: 0
5417 13:12:04.145028
5418 13:12:04.146871 RX Vref 0 -> 0, step: 1
5419 13:12:04.147344
5420 13:12:04.150015 RX Delay -53 -> 252, step: 4
5421 13:12:04.156546 iDelay=195, Bit 0, Center 94 (7 ~ 182) 176
5422 13:12:04.160231 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5423 13:12:04.163261 iDelay=195, Bit 2, Center 92 (3 ~ 182) 180
5424 13:12:04.166171 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5425 13:12:04.169890 iDelay=195, Bit 4, Center 100 (7 ~ 194) 188
5426 13:12:04.172871 iDelay=195, Bit 5, Center 88 (-1 ~ 178) 180
5427 13:12:04.179580 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5428 13:12:04.182811 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5429 13:12:04.186250 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5430 13:12:04.189650 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5431 13:12:04.192711 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5432 13:12:04.199056 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5433 13:12:04.202583 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5434 13:12:04.205885 iDelay=195, Bit 13, Center 94 (3 ~ 186) 184
5435 13:12:04.208925 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5436 13:12:04.212423 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5437 13:12:04.212828 ==
5438 13:12:04.215776 Dram Type= 6, Freq= 0, CH_0, rank 1
5439 13:12:04.222679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5440 13:12:04.223071 ==
5441 13:12:04.223376 DQS Delay:
5442 13:12:04.223651 DQS0 = 0, DQS1 = 0
5443 13:12:04.225611 DQM Delay:
5444 13:12:04.225994 DQM0 = 97, DQM1 = 88
5445 13:12:04.228817 DQ Delay:
5446 13:12:04.232383 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =94
5447 13:12:04.235404 DQ4 =100, DQ5 =88, DQ6 =106, DQ7 =104
5448 13:12:04.238841 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =84
5449 13:12:04.242102 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =94
5450 13:12:04.242487
5451 13:12:04.242798
5452 13:12:04.248476 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 413 ps
5453 13:12:04.251971 CH0 RK1: MR19=505, MR18=1A18
5454 13:12:04.258873 CH0_RK1: MR19=0x505, MR18=0x1A18, DQSOSC=413, MR23=63, INC=63, DEC=42
5455 13:12:04.262033 [RxdqsGatingPostProcess] freq 933
5456 13:12:04.265607 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5457 13:12:04.268576 best DQS0 dly(2T, 0.5T) = (0, 10)
5458 13:12:04.272015 best DQS1 dly(2T, 0.5T) = (0, 10)
5459 13:12:04.275041 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5460 13:12:04.278524 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5461 13:12:04.281893 best DQS0 dly(2T, 0.5T) = (0, 10)
5462 13:12:04.284972 best DQS1 dly(2T, 0.5T) = (0, 10)
5463 13:12:04.288501 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5464 13:12:04.291563 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5465 13:12:04.294817 Pre-setting of DQS Precalculation
5466 13:12:04.298257 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5467 13:12:04.301651 ==
5468 13:12:04.304889 Dram Type= 6, Freq= 0, CH_1, rank 0
5469 13:12:04.308145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5470 13:12:04.308531 ==
5471 13:12:04.314649 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5472 13:12:04.317970 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5473 13:12:04.321777 [CA 0] Center 36 (6~67) winsize 62
5474 13:12:04.324965 [CA 1] Center 36 (6~67) winsize 62
5475 13:12:04.328507 [CA 2] Center 34 (4~65) winsize 62
5476 13:12:04.331842 [CA 3] Center 34 (3~65) winsize 63
5477 13:12:04.335264 [CA 4] Center 34 (4~65) winsize 62
5478 13:12:04.338198 [CA 5] Center 33 (3~64) winsize 62
5479 13:12:04.338582
5480 13:12:04.341668 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5481 13:12:04.342056
5482 13:12:04.345126 [CATrainingPosCal] consider 1 rank data
5483 13:12:04.348253 u2DelayCellTimex100 = 270/100 ps
5484 13:12:04.351574 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5485 13:12:04.357794 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5486 13:12:04.361449 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5487 13:12:04.364471 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5488 13:12:04.367967 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5489 13:12:04.371223 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5490 13:12:04.371613
5491 13:12:04.374725 CA PerBit enable=1, Macro0, CA PI delay=33
5492 13:12:04.375116
5493 13:12:04.378100 [CBTSetCACLKResult] CA Dly = 33
5494 13:12:04.381130 CS Dly: 5 (0~36)
5495 13:12:04.381573 ==
5496 13:12:04.384619 Dram Type= 6, Freq= 0, CH_1, rank 1
5497 13:12:04.387945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5498 13:12:04.388344 ==
5499 13:12:04.394455 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5500 13:12:04.398029 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5501 13:12:04.401862 [CA 0] Center 36 (6~67) winsize 62
5502 13:12:04.405204 [CA 1] Center 37 (6~68) winsize 63
5503 13:12:04.408105 [CA 2] Center 34 (4~65) winsize 62
5504 13:12:04.411602 [CA 3] Center 33 (3~64) winsize 62
5505 13:12:04.414900 [CA 4] Center 34 (4~64) winsize 61
5506 13:12:04.418180 [CA 5] Center 33 (3~64) winsize 62
5507 13:12:04.418570
5508 13:12:04.421403 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5509 13:12:04.421797
5510 13:12:04.424674 [CATrainingPosCal] consider 2 rank data
5511 13:12:04.428441 u2DelayCellTimex100 = 270/100 ps
5512 13:12:04.431563 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5513 13:12:04.437751 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5514 13:12:04.441088 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5515 13:12:04.444485 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5516 13:12:04.447686 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5517 13:12:04.451083 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5518 13:12:04.451470
5519 13:12:04.454312 CA PerBit enable=1, Macro0, CA PI delay=33
5520 13:12:04.454703
5521 13:12:04.458044 [CBTSetCACLKResult] CA Dly = 33
5522 13:12:04.461407 CS Dly: 6 (0~39)
5523 13:12:04.461792
5524 13:12:04.464099 ----->DramcWriteLeveling(PI) begin...
5525 13:12:04.464496 ==
5526 13:12:04.467477 Dram Type= 6, Freq= 0, CH_1, rank 0
5527 13:12:04.470869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5528 13:12:04.471282 ==
5529 13:12:04.474210 Write leveling (Byte 0): 24 => 24
5530 13:12:04.477775 Write leveling (Byte 1): 25 => 25
5531 13:12:04.480906 DramcWriteLeveling(PI) end<-----
5532 13:12:04.481337
5533 13:12:04.481642 ==
5534 13:12:04.483933 Dram Type= 6, Freq= 0, CH_1, rank 0
5535 13:12:04.487652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5536 13:12:04.488078 ==
5537 13:12:04.490860 [Gating] SW mode calibration
5538 13:12:04.497492 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5539 13:12:04.503762 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5540 13:12:04.507067 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5541 13:12:04.510588 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5542 13:12:04.517340 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5543 13:12:04.520870 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5544 13:12:04.524041 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5545 13:12:04.530703 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5546 13:12:04.533906 0 14 24 | B1->B0 | 3434 3333 | 0 1 | (0 1) (1 1)
5547 13:12:04.537034 0 14 28 | B1->B0 | 2e2e 2929 | 1 1 | (1 0) (1 0)
5548 13:12:04.543788 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5549 13:12:04.546962 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5550 13:12:04.550276 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5551 13:12:04.556712 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5552 13:12:04.560178 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5553 13:12:04.563324 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5554 13:12:04.570190 0 15 24 | B1->B0 | 2626 2b2b | 0 0 | (0 0) (0 0)
5555 13:12:04.573476 0 15 28 | B1->B0 | 3333 3b3b | 1 1 | (0 0) (0 0)
5556 13:12:04.576709 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5557 13:12:04.583109 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5558 13:12:04.586865 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5559 13:12:04.589758 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5560 13:12:04.596664 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5561 13:12:04.599811 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5562 13:12:04.603193 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5563 13:12:04.610043 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5564 13:12:04.612880 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 13:12:04.616409 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 13:12:04.623033 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 13:12:04.626150 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 13:12:04.629691 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 13:12:04.636352 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 13:12:04.639769 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 13:12:04.642647 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 13:12:04.649472 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 13:12:04.652628 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 13:12:04.656032 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 13:12:04.662677 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 13:12:04.665749 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 13:12:04.668920 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 13:12:04.675861 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5579 13:12:04.678956 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5580 13:12:04.682465 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 13:12:04.685489 Total UI for P1: 0, mck2ui 16
5582 13:12:04.689209 best dqsien dly found for B0: ( 1, 2, 28)
5583 13:12:04.692309 Total UI for P1: 0, mck2ui 16
5584 13:12:04.695205 best dqsien dly found for B1: ( 1, 2, 26)
5585 13:12:04.698708 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5586 13:12:04.702219 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5587 13:12:04.702614
5588 13:12:04.708679 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5589 13:12:04.711967 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5590 13:12:04.715230 [Gating] SW calibration Done
5591 13:12:04.715617 ==
5592 13:12:04.718549 Dram Type= 6, Freq= 0, CH_1, rank 0
5593 13:12:04.721600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5594 13:12:04.721998 ==
5595 13:12:04.722303 RX Vref Scan: 0
5596 13:12:04.722586
5597 13:12:04.725316 RX Vref 0 -> 0, step: 1
5598 13:12:04.725704
5599 13:12:04.728077 RX Delay -80 -> 252, step: 8
5600 13:12:04.731611 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5601 13:12:04.734804 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5602 13:12:04.741881 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5603 13:12:04.745194 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5604 13:12:04.748409 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5605 13:12:04.751218 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5606 13:12:04.754747 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5607 13:12:04.758300 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5608 13:12:04.764463 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5609 13:12:04.768231 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5610 13:12:04.771150 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5611 13:12:04.774579 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5612 13:12:04.778213 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5613 13:12:04.784451 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5614 13:12:04.787958 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5615 13:12:04.790865 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5616 13:12:04.791376 ==
5617 13:12:04.794482 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 13:12:04.797780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 13:12:04.798180 ==
5620 13:12:04.800923 DQS Delay:
5621 13:12:04.801491 DQS0 = 0, DQS1 = 0
5622 13:12:04.804322 DQM Delay:
5623 13:12:04.804701 DQM0 = 98, DQM1 = 93
5624 13:12:04.804997 DQ Delay:
5625 13:12:04.807750 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =99
5626 13:12:04.811340 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5627 13:12:04.814155 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =87
5628 13:12:04.817271 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =103
5629 13:12:04.817770
5630 13:12:04.820812
5631 13:12:04.821336 ==
5632 13:12:04.824057 Dram Type= 6, Freq= 0, CH_1, rank 0
5633 13:12:04.827286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5634 13:12:04.827698 ==
5635 13:12:04.827997
5636 13:12:04.828270
5637 13:12:04.830498 TX Vref Scan disable
5638 13:12:04.830881 == TX Byte 0 ==
5639 13:12:04.837121 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5640 13:12:04.840522 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5641 13:12:04.840904 == TX Byte 1 ==
5642 13:12:04.847387 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5643 13:12:04.850286 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5644 13:12:04.850671 ==
5645 13:12:04.853573 Dram Type= 6, Freq= 0, CH_1, rank 0
5646 13:12:04.857022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5647 13:12:04.857453 ==
5648 13:12:04.857759
5649 13:12:04.858047
5650 13:12:04.860301 TX Vref Scan disable
5651 13:12:04.863773 == TX Byte 0 ==
5652 13:12:04.867251 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5653 13:12:04.870440 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5654 13:12:04.873393 == TX Byte 1 ==
5655 13:12:04.876844 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5656 13:12:04.880051 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5657 13:12:04.880433
5658 13:12:04.883323 [DATLAT]
5659 13:12:04.883732 Freq=933, CH1 RK0
5660 13:12:04.884037
5661 13:12:04.886592 DATLAT Default: 0xd
5662 13:12:04.886974 0, 0xFFFF, sum = 0
5663 13:12:04.890171 1, 0xFFFF, sum = 0
5664 13:12:04.890560 2, 0xFFFF, sum = 0
5665 13:12:04.893496 3, 0xFFFF, sum = 0
5666 13:12:04.893944 4, 0xFFFF, sum = 0
5667 13:12:04.896522 5, 0xFFFF, sum = 0
5668 13:12:04.896911 6, 0xFFFF, sum = 0
5669 13:12:04.899997 7, 0xFFFF, sum = 0
5670 13:12:04.902929 8, 0xFFFF, sum = 0
5671 13:12:04.903321 9, 0xFFFF, sum = 0
5672 13:12:04.906086 10, 0x0, sum = 1
5673 13:12:04.906490 11, 0x0, sum = 2
5674 13:12:04.906797 12, 0x0, sum = 3
5675 13:12:04.909619 13, 0x0, sum = 4
5676 13:12:04.910050 best_step = 11
5677 13:12:04.910350
5678 13:12:04.912723 ==
5679 13:12:04.916288 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 13:12:04.920037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 13:12:04.920429 ==
5682 13:12:04.920822 RX Vref Scan: 1
5683 13:12:04.921199
5684 13:12:04.922803 RX Vref 0 -> 0, step: 1
5685 13:12:04.923311
5686 13:12:04.926114 RX Delay -61 -> 252, step: 4
5687 13:12:04.926628
5688 13:12:04.929516 Set Vref, RX VrefLevel [Byte0]: 52
5689 13:12:04.932878 [Byte1]: 53
5690 13:12:04.933295
5691 13:12:04.935970 Final RX Vref Byte 0 = 52 to rank0
5692 13:12:04.939253 Final RX Vref Byte 1 = 53 to rank0
5693 13:12:04.942863 Final RX Vref Byte 0 = 52 to rank1
5694 13:12:04.946006 Final RX Vref Byte 1 = 53 to rank1==
5695 13:12:04.949753 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 13:12:04.952523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 13:12:04.955763 ==
5698 13:12:04.956145 DQS Delay:
5699 13:12:04.956440 DQS0 = 0, DQS1 = 0
5700 13:12:04.959365 DQM Delay:
5701 13:12:04.959747 DQM0 = 98, DQM1 = 96
5702 13:12:04.962192 DQ Delay:
5703 13:12:04.965556 DQ0 =106, DQ1 =92, DQ2 =88, DQ3 =98
5704 13:12:04.969131 DQ4 =94, DQ5 =108, DQ6 =110, DQ7 =92
5705 13:12:04.972445 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =88
5706 13:12:04.975729 DQ12 =106, DQ13 =106, DQ14 =100, DQ15 =106
5707 13:12:04.976110
5708 13:12:04.976403
5709 13:12:04.982158 [DQSOSCAuto] RK0, (LSB)MR18= 0x818, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5710 13:12:04.985485 CH1 RK0: MR19=505, MR18=818
5711 13:12:04.992200 CH1_RK0: MR19=0x505, MR18=0x818, DQSOSC=414, MR23=63, INC=63, DEC=42
5712 13:12:04.992585
5713 13:12:04.995141 ----->DramcWriteLeveling(PI) begin...
5714 13:12:04.995553 ==
5715 13:12:04.998811 Dram Type= 6, Freq= 0, CH_1, rank 1
5716 13:12:05.001834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 13:12:05.002219 ==
5718 13:12:05.005334 Write leveling (Byte 0): 27 => 27
5719 13:12:05.008696 Write leveling (Byte 1): 28 => 28
5720 13:12:05.011707 DramcWriteLeveling(PI) end<-----
5721 13:12:05.012093
5722 13:12:05.012387 ==
5723 13:12:05.015258 Dram Type= 6, Freq= 0, CH_1, rank 1
5724 13:12:05.018597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 13:12:05.021955 ==
5726 13:12:05.022368 [Gating] SW mode calibration
5727 13:12:05.028453 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5728 13:12:05.034785 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5729 13:12:05.037961 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5730 13:12:05.044971 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5731 13:12:05.048316 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5732 13:12:05.051564 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5733 13:12:05.058043 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5734 13:12:05.060951 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5735 13:12:05.064518 0 14 24 | B1->B0 | 3333 2e2e | 0 0 | (0 1) (0 1)
5736 13:12:05.070767 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5737 13:12:05.074186 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5738 13:12:05.077765 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5739 13:12:05.084238 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5740 13:12:05.087585 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5741 13:12:05.090692 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5742 13:12:05.097588 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5743 13:12:05.100762 0 15 24 | B1->B0 | 2525 3232 | 0 1 | (0 0) (0 0)
5744 13:12:05.103953 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5745 13:12:05.110664 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5746 13:12:05.113843 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5747 13:12:05.117246 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5748 13:12:05.124271 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5749 13:12:05.127125 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5750 13:12:05.130377 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5751 13:12:05.136932 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5752 13:12:05.140291 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5753 13:12:05.143601 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5754 13:12:05.150407 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5755 13:12:05.153526 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5756 13:12:05.156789 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5757 13:12:05.163354 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5758 13:12:05.166609 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5759 13:12:05.170158 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 13:12:05.176969 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 13:12:05.180325 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 13:12:05.183178 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 13:12:05.190299 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 13:12:05.193425 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 13:12:05.196606 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 13:12:05.203216 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 13:12:05.206369 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5768 13:12:05.209933 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 13:12:05.212982 Total UI for P1: 0, mck2ui 16
5770 13:12:05.216376 best dqsien dly found for B0: ( 1, 2, 24)
5771 13:12:05.219692 Total UI for P1: 0, mck2ui 16
5772 13:12:05.223027 best dqsien dly found for B1: ( 1, 2, 24)
5773 13:12:05.225943 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5774 13:12:05.229249 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5775 13:12:05.229633
5776 13:12:05.236264 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5777 13:12:05.239559 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5778 13:12:05.242761 [Gating] SW calibration Done
5779 13:12:05.243140 ==
5780 13:12:05.245749 Dram Type= 6, Freq= 0, CH_1, rank 1
5781 13:12:05.249530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 13:12:05.249914 ==
5783 13:12:05.250211 RX Vref Scan: 0
5784 13:12:05.250591
5785 13:12:05.252650 RX Vref 0 -> 0, step: 1
5786 13:12:05.253029
5787 13:12:05.255829 RX Delay -80 -> 252, step: 8
5788 13:12:05.259458 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5789 13:12:05.262432 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5790 13:12:05.268857 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5791 13:12:05.272411 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5792 13:12:05.275508 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5793 13:12:05.278758 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5794 13:12:05.282453 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5795 13:12:05.285464 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5796 13:12:05.292218 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5797 13:12:05.295455 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5798 13:12:05.298742 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5799 13:12:05.302159 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5800 13:12:05.305058 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5801 13:12:05.311541 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5802 13:12:05.314979 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5803 13:12:05.318254 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5804 13:12:05.318638 ==
5805 13:12:05.321765 Dram Type= 6, Freq= 0, CH_1, rank 1
5806 13:12:05.325178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5807 13:12:05.325657 ==
5808 13:12:05.328024 DQS Delay:
5809 13:12:05.328404 DQS0 = 0, DQS1 = 0
5810 13:12:05.331435 DQM Delay:
5811 13:12:05.331814 DQM0 = 96, DQM1 = 93
5812 13:12:05.332111 DQ Delay:
5813 13:12:05.334812 DQ0 =103, DQ1 =91, DQ2 =83, DQ3 =95
5814 13:12:05.338092 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5815 13:12:05.341540 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =87
5816 13:12:05.344881 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5817 13:12:05.348153
5818 13:12:05.348535
5819 13:12:05.348834 ==
5820 13:12:05.351442 Dram Type= 6, Freq= 0, CH_1, rank 1
5821 13:12:05.354696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5822 13:12:05.355094 ==
5823 13:12:05.355393
5824 13:12:05.355671
5825 13:12:05.358026 TX Vref Scan disable
5826 13:12:05.358409 == TX Byte 0 ==
5827 13:12:05.364704 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5828 13:12:05.368190 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5829 13:12:05.368572 == TX Byte 1 ==
5830 13:12:05.374475 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5831 13:12:05.377903 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5832 13:12:05.378286 ==
5833 13:12:05.380928 Dram Type= 6, Freq= 0, CH_1, rank 1
5834 13:12:05.384514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5835 13:12:05.384900 ==
5836 13:12:05.385231
5837 13:12:05.387473
5838 13:12:05.387853 TX Vref Scan disable
5839 13:12:05.390619 == TX Byte 0 ==
5840 13:12:05.394229 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5841 13:12:05.397028 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5842 13:12:05.400513 == TX Byte 1 ==
5843 13:12:05.404222 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5844 13:12:05.410399 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5845 13:12:05.410845
5846 13:12:05.411145 [DATLAT]
5847 13:12:05.411425 Freq=933, CH1 RK1
5848 13:12:05.411697
5849 13:12:05.413595 DATLAT Default: 0xb
5850 13:12:05.413988 0, 0xFFFF, sum = 0
5851 13:12:05.416860 1, 0xFFFF, sum = 0
5852 13:12:05.417355 2, 0xFFFF, sum = 0
5853 13:12:05.420721 3, 0xFFFF, sum = 0
5854 13:12:05.423546 4, 0xFFFF, sum = 0
5855 13:12:05.423940 5, 0xFFFF, sum = 0
5856 13:12:05.426915 6, 0xFFFF, sum = 0
5857 13:12:05.427303 7, 0xFFFF, sum = 0
5858 13:12:05.430584 8, 0xFFFF, sum = 0
5859 13:12:05.430975 9, 0xFFFF, sum = 0
5860 13:12:05.433588 10, 0x0, sum = 1
5861 13:12:05.433979 11, 0x0, sum = 2
5862 13:12:05.436891 12, 0x0, sum = 3
5863 13:12:05.437330 13, 0x0, sum = 4
5864 13:12:05.437639 best_step = 11
5865 13:12:05.437960
5866 13:12:05.440342 ==
5867 13:12:05.443502 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 13:12:05.446987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 13:12:05.447386 ==
5870 13:12:05.447685 RX Vref Scan: 0
5871 13:12:05.447958
5872 13:12:05.450356 RX Vref 0 -> 0, step: 1
5873 13:12:05.450740
5874 13:12:05.453745 RX Delay -61 -> 252, step: 4
5875 13:12:05.460164 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5876 13:12:05.463681 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5877 13:12:05.466400 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5878 13:12:05.469925 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5879 13:12:05.473259 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5880 13:12:05.476075 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5881 13:12:05.483139 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5882 13:12:05.486199 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5883 13:12:05.489404 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5884 13:12:05.492616 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5885 13:12:05.496109 iDelay=199, Bit 10, Center 94 (3 ~ 186) 184
5886 13:12:05.502501 iDelay=199, Bit 11, Center 88 (-1 ~ 178) 180
5887 13:12:05.506056 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5888 13:12:05.509222 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5889 13:12:05.512079 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5890 13:12:05.518919 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5891 13:12:05.519325 ==
5892 13:12:05.522110 Dram Type= 6, Freq= 0, CH_1, rank 1
5893 13:12:05.525329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5894 13:12:05.525721 ==
5895 13:12:05.526020 DQS Delay:
5896 13:12:05.529226 DQS0 = 0, DQS1 = 0
5897 13:12:05.529611 DQM Delay:
5898 13:12:05.532589 DQM0 = 96, DQM1 = 93
5899 13:12:05.533097 DQ Delay:
5900 13:12:05.535670 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =94
5901 13:12:05.539146 DQ4 =98, DQ5 =104, DQ6 =102, DQ7 =92
5902 13:12:05.542798 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =88
5903 13:12:05.545445 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =102
5904 13:12:05.545834
5905 13:12:05.546133
5906 13:12:05.555322 [DQSOSCAuto] RK1, (LSB)MR18= 0x142a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
5907 13:12:05.555779 CH1 RK1: MR19=505, MR18=142A
5908 13:12:05.562256 CH1_RK1: MR19=0x505, MR18=0x142A, DQSOSC=408, MR23=63, INC=65, DEC=43
5909 13:12:05.565241 [RxdqsGatingPostProcess] freq 933
5910 13:12:05.571527 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5911 13:12:05.575261 best DQS0 dly(2T, 0.5T) = (0, 10)
5912 13:12:05.578575 best DQS1 dly(2T, 0.5T) = (0, 10)
5913 13:12:05.582056 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5914 13:12:05.584982 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5915 13:12:05.588842 best DQS0 dly(2T, 0.5T) = (0, 10)
5916 13:12:05.589350 best DQS1 dly(2T, 0.5T) = (0, 10)
5917 13:12:05.592234 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5918 13:12:05.594848 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5919 13:12:05.598160 Pre-setting of DQS Precalculation
5920 13:12:05.605069 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5921 13:12:05.611317 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5922 13:12:05.618146 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5923 13:12:05.618531
5924 13:12:05.618824
5925 13:12:05.621894 [Calibration Summary] 1866 Mbps
5926 13:12:05.625027 CH 0, Rank 0
5927 13:12:05.625455 SW Impedance : PASS
5928 13:12:05.627895 DUTY Scan : NO K
5929 13:12:05.631319 ZQ Calibration : PASS
5930 13:12:05.631705 Jitter Meter : NO K
5931 13:12:05.634368 CBT Training : PASS
5932 13:12:05.637910 Write leveling : PASS
5933 13:12:05.638445 RX DQS gating : PASS
5934 13:12:05.641651 RX DQ/DQS(RDDQC) : PASS
5935 13:12:05.642118 TX DQ/DQS : PASS
5936 13:12:05.644279 RX DATLAT : PASS
5937 13:12:05.647743 RX DQ/DQS(Engine): PASS
5938 13:12:05.648218 TX OE : NO K
5939 13:12:05.651284 All Pass.
5940 13:12:05.651747
5941 13:12:05.652041 CH 0, Rank 1
5942 13:12:05.654768 SW Impedance : PASS
5943 13:12:05.655152 DUTY Scan : NO K
5944 13:12:05.657737 ZQ Calibration : PASS
5945 13:12:05.660961 Jitter Meter : NO K
5946 13:12:05.661448 CBT Training : PASS
5947 13:12:05.664222 Write leveling : PASS
5948 13:12:05.667216 RX DQS gating : PASS
5949 13:12:05.667604 RX DQ/DQS(RDDQC) : PASS
5950 13:12:05.670715 TX DQ/DQS : PASS
5951 13:12:05.674330 RX DATLAT : PASS
5952 13:12:05.674749 RX DQ/DQS(Engine): PASS
5953 13:12:05.677562 TX OE : NO K
5954 13:12:05.677952 All Pass.
5955 13:12:05.678247
5956 13:12:05.680761 CH 1, Rank 0
5957 13:12:05.681175 SW Impedance : PASS
5958 13:12:05.684061 DUTY Scan : NO K
5959 13:12:05.687084 ZQ Calibration : PASS
5960 13:12:05.687474 Jitter Meter : NO K
5961 13:12:05.690479 CBT Training : PASS
5962 13:12:05.693759 Write leveling : PASS
5963 13:12:05.694146 RX DQS gating : PASS
5964 13:12:05.697189 RX DQ/DQS(RDDQC) : PASS
5965 13:12:05.700339 TX DQ/DQS : PASS
5966 13:12:05.700808 RX DATLAT : PASS
5967 13:12:05.703882 RX DQ/DQS(Engine): PASS
5968 13:12:05.707151 TX OE : NO K
5969 13:12:05.707628 All Pass.
5970 13:12:05.707982
5971 13:12:05.708262 CH 1, Rank 1
5972 13:12:05.710103 SW Impedance : PASS
5973 13:12:05.713757 DUTY Scan : NO K
5974 13:12:05.714212 ZQ Calibration : PASS
5975 13:12:05.717029 Jitter Meter : NO K
5976 13:12:05.717467 CBT Training : PASS
5977 13:12:05.720197 Write leveling : PASS
5978 13:12:05.723771 RX DQS gating : PASS
5979 13:12:05.724238 RX DQ/DQS(RDDQC) : PASS
5980 13:12:05.726677 TX DQ/DQS : PASS
5981 13:12:05.730076 RX DATLAT : PASS
5982 13:12:05.730458 RX DQ/DQS(Engine): PASS
5983 13:12:05.733213 TX OE : NO K
5984 13:12:05.733768 All Pass.
5985 13:12:05.734249
5986 13:12:05.736856 DramC Write-DBI off
5987 13:12:05.739999 PER_BANK_REFRESH: Hybrid Mode
5988 13:12:05.740382 TX_TRACKING: ON
5989 13:12:05.749664 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5990 13:12:05.753191 [FAST_K] Save calibration result to emmc
5991 13:12:05.756351 dramc_set_vcore_voltage set vcore to 650000
5992 13:12:05.759298 Read voltage for 400, 6
5993 13:12:05.759712 Vio18 = 0
5994 13:12:05.762815 Vcore = 650000
5995 13:12:05.763200 Vdram = 0
5996 13:12:05.763498 Vddq = 0
5997 13:12:05.763771 Vmddr = 0
5998 13:12:05.769792 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5999 13:12:05.776012 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6000 13:12:05.776433 MEM_TYPE=3, freq_sel=20
6001 13:12:05.779428 sv_algorithm_assistance_LP4_800
6002 13:12:05.782708 ============ PULL DRAM RESETB DOWN ============
6003 13:12:05.789202 ========== PULL DRAM RESETB DOWN end =========
6004 13:12:05.792530 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6005 13:12:05.796224 ===================================
6006 13:12:05.799263 LPDDR4 DRAM CONFIGURATION
6007 13:12:05.802422 ===================================
6008 13:12:05.802812 EX_ROW_EN[0] = 0x0
6009 13:12:05.805932 EX_ROW_EN[1] = 0x0
6010 13:12:05.808900 LP4Y_EN = 0x0
6011 13:12:05.809378 WORK_FSP = 0x0
6012 13:12:05.812253 WL = 0x2
6013 13:12:05.812747 RL = 0x2
6014 13:12:05.815726 BL = 0x2
6015 13:12:05.816113 RPST = 0x0
6016 13:12:05.819064 RD_PRE = 0x0
6017 13:12:05.819448 WR_PRE = 0x1
6018 13:12:05.822150 WR_PST = 0x0
6019 13:12:05.822535 DBI_WR = 0x0
6020 13:12:05.825481 DBI_RD = 0x0
6021 13:12:05.825955 OTF = 0x1
6022 13:12:05.828784 ===================================
6023 13:12:05.832134 ===================================
6024 13:12:05.835213 ANA top config
6025 13:12:05.838663 ===================================
6026 13:12:05.839051 DLL_ASYNC_EN = 0
6027 13:12:05.841666 ALL_SLAVE_EN = 1
6028 13:12:05.844990 NEW_RANK_MODE = 1
6029 13:12:05.848453 DLL_IDLE_MODE = 1
6030 13:12:05.851549 LP45_APHY_COMB_EN = 1
6031 13:12:05.852051 TX_ODT_DIS = 1
6032 13:12:05.855504 NEW_8X_MODE = 1
6033 13:12:05.858226 ===================================
6034 13:12:05.861412 ===================================
6035 13:12:05.864986 data_rate = 800
6036 13:12:05.868394 CKR = 1
6037 13:12:05.871758 DQ_P2S_RATIO = 4
6038 13:12:05.875012 ===================================
6039 13:12:05.878216 CA_P2S_RATIO = 4
6040 13:12:05.878605 DQ_CA_OPEN = 0
6041 13:12:05.881087 DQ_SEMI_OPEN = 1
6042 13:12:05.884878 CA_SEMI_OPEN = 1
6043 13:12:05.887967 CA_FULL_RATE = 0
6044 13:12:05.891009 DQ_CKDIV4_EN = 0
6045 13:12:05.894273 CA_CKDIV4_EN = 1
6046 13:12:05.894665 CA_PREDIV_EN = 0
6047 13:12:05.897992 PH8_DLY = 0
6048 13:12:05.900971 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6049 13:12:05.904154 DQ_AAMCK_DIV = 0
6050 13:12:05.907423 CA_AAMCK_DIV = 0
6051 13:12:05.911199 CA_ADMCK_DIV = 4
6052 13:12:05.911669 DQ_TRACK_CA_EN = 0
6053 13:12:05.914347 CA_PICK = 800
6054 13:12:05.917816 CA_MCKIO = 400
6055 13:12:05.920971 MCKIO_SEMI = 400
6056 13:12:05.924391 PLL_FREQ = 3016
6057 13:12:05.927781 DQ_UI_PI_RATIO = 32
6058 13:12:05.930895 CA_UI_PI_RATIO = 32
6059 13:12:05.934183 ===================================
6060 13:12:05.937218 ===================================
6061 13:12:05.940660 memory_type:LPDDR4
6062 13:12:05.941119 GP_NUM : 10
6063 13:12:05.943984 SRAM_EN : 1
6064 13:12:05.944369 MD32_EN : 0
6065 13:12:05.947248 ===================================
6066 13:12:05.950716 [ANA_INIT] >>>>>>>>>>>>>>
6067 13:12:05.954083 <<<<<< [CONFIGURE PHASE]: ANA_TX
6068 13:12:05.957295 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6069 13:12:05.960518 ===================================
6070 13:12:05.963798 data_rate = 800,PCW = 0X7400
6071 13:12:05.967043 ===================================
6072 13:12:05.970931 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6073 13:12:05.974050 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6074 13:12:05.987158 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6075 13:12:05.990251 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6076 13:12:05.993611 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6077 13:12:05.996815 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6078 13:12:06.000322 [ANA_INIT] flow start
6079 13:12:06.003672 [ANA_INIT] PLL >>>>>>>>
6080 13:12:06.004060 [ANA_INIT] PLL <<<<<<<<
6081 13:12:06.006639 [ANA_INIT] MIDPI >>>>>>>>
6082 13:12:06.010122 [ANA_INIT] MIDPI <<<<<<<<
6083 13:12:06.010511 [ANA_INIT] DLL >>>>>>>>
6084 13:12:06.013622 [ANA_INIT] flow end
6085 13:12:06.017119 ============ LP4 DIFF to SE enter ============
6086 13:12:06.023583 ============ LP4 DIFF to SE exit ============
6087 13:12:06.024060 [ANA_INIT] <<<<<<<<<<<<<
6088 13:12:06.026609 [Flow] Enable top DCM control >>>>>
6089 13:12:06.030255 [Flow] Enable top DCM control <<<<<
6090 13:12:06.033317 Enable DLL master slave shuffle
6091 13:12:06.040154 ==============================================================
6092 13:12:06.040620 Gating Mode config
6093 13:12:06.046346 ==============================================================
6094 13:12:06.049623 Config description:
6095 13:12:06.059871 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6096 13:12:06.066397 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6097 13:12:06.069537 SELPH_MODE 0: By rank 1: By Phase
6098 13:12:06.076035 ==============================================================
6099 13:12:06.079646 GAT_TRACK_EN = 0
6100 13:12:06.080040 RX_GATING_MODE = 2
6101 13:12:06.082684 RX_GATING_TRACK_MODE = 2
6102 13:12:06.086325 SELPH_MODE = 1
6103 13:12:06.089464 PICG_EARLY_EN = 1
6104 13:12:06.092733 VALID_LAT_VALUE = 1
6105 13:12:06.099149 ==============================================================
6106 13:12:06.102429 Enter into Gating configuration >>>>
6107 13:12:06.105699 Exit from Gating configuration <<<<
6108 13:12:06.109008 Enter into DVFS_PRE_config >>>>>
6109 13:12:06.118700 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6110 13:12:06.122288 Exit from DVFS_PRE_config <<<<<
6111 13:12:06.125732 Enter into PICG configuration >>>>
6112 13:12:06.128578 Exit from PICG configuration <<<<
6113 13:12:06.132001 [RX_INPUT] configuration >>>>>
6114 13:12:06.135709 [RX_INPUT] configuration <<<<<
6115 13:12:06.138841 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6116 13:12:06.145128 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6117 13:12:06.152247 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6118 13:12:06.158435 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6119 13:12:06.165378 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6120 13:12:06.168801 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6121 13:12:06.175336 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6122 13:12:06.178219 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6123 13:12:06.181543 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6124 13:12:06.185007 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6125 13:12:06.191898 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6126 13:12:06.194777 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6127 13:12:06.197716 ===================================
6128 13:12:06.201582 LPDDR4 DRAM CONFIGURATION
6129 13:12:06.205000 ===================================
6130 13:12:06.205435 EX_ROW_EN[0] = 0x0
6131 13:12:06.207820 EX_ROW_EN[1] = 0x0
6132 13:12:06.208293 LP4Y_EN = 0x0
6133 13:12:06.211065 WORK_FSP = 0x0
6134 13:12:06.211456 WL = 0x2
6135 13:12:06.214288 RL = 0x2
6136 13:12:06.218172 BL = 0x2
6137 13:12:06.218560 RPST = 0x0
6138 13:12:06.221089 RD_PRE = 0x0
6139 13:12:06.221517 WR_PRE = 0x1
6140 13:12:06.224071 WR_PST = 0x0
6141 13:12:06.224525 DBI_WR = 0x0
6142 13:12:06.228199 DBI_RD = 0x0
6143 13:12:06.228584 OTF = 0x1
6144 13:12:06.230867 ===================================
6145 13:12:06.234362 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6146 13:12:06.241128 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6147 13:12:06.244167 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6148 13:12:06.247564 ===================================
6149 13:12:06.250677 LPDDR4 DRAM CONFIGURATION
6150 13:12:06.253710 ===================================
6151 13:12:06.254100 EX_ROW_EN[0] = 0x10
6152 13:12:06.257350 EX_ROW_EN[1] = 0x0
6153 13:12:06.257837 LP4Y_EN = 0x0
6154 13:12:06.260421 WORK_FSP = 0x0
6155 13:12:06.264028 WL = 0x2
6156 13:12:06.264418 RL = 0x2
6157 13:12:06.267317 BL = 0x2
6158 13:12:06.267782 RPST = 0x0
6159 13:12:06.270741 RD_PRE = 0x0
6160 13:12:06.271250 WR_PRE = 0x1
6161 13:12:06.274000 WR_PST = 0x0
6162 13:12:06.274391 DBI_WR = 0x0
6163 13:12:06.277348 DBI_RD = 0x0
6164 13:12:06.277737 OTF = 0x1
6165 13:12:06.280439 ===================================
6166 13:12:06.286956 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6167 13:12:06.291375 nWR fixed to 30
6168 13:12:06.294449 [ModeRegInit_LP4] CH0 RK0
6169 13:12:06.294843 [ModeRegInit_LP4] CH0 RK1
6170 13:12:06.297599 [ModeRegInit_LP4] CH1 RK0
6171 13:12:06.301092 [ModeRegInit_LP4] CH1 RK1
6172 13:12:06.301518 match AC timing 19
6173 13:12:06.307363 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6174 13:12:06.311093 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6175 13:12:06.314381 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6176 13:12:06.320576 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6177 13:12:06.324434 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6178 13:12:06.324976 ==
6179 13:12:06.327623 Dram Type= 6, Freq= 0, CH_0, rank 0
6180 13:12:06.330540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6181 13:12:06.330933 ==
6182 13:12:06.337225 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6183 13:12:06.344470 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6184 13:12:06.346976 [CA 0] Center 36 (8~64) winsize 57
6185 13:12:06.350224 [CA 1] Center 36 (8~64) winsize 57
6186 13:12:06.353651 [CA 2] Center 36 (8~64) winsize 57
6187 13:12:06.357133 [CA 3] Center 36 (8~64) winsize 57
6188 13:12:06.360529 [CA 4] Center 36 (8~64) winsize 57
6189 13:12:06.364098 [CA 5] Center 36 (8~64) winsize 57
6190 13:12:06.364572
6191 13:12:06.367379 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6192 13:12:06.367912
6193 13:12:06.370847 [CATrainingPosCal] consider 1 rank data
6194 13:12:06.373585 u2DelayCellTimex100 = 270/100 ps
6195 13:12:06.377083 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6196 13:12:06.380306 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6197 13:12:06.383420 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6198 13:12:06.386802 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6199 13:12:06.389750 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6200 13:12:06.393551 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6201 13:12:06.393941
6202 13:12:06.399733 CA PerBit enable=1, Macro0, CA PI delay=36
6203 13:12:06.400124
6204 13:12:06.400429 [CBTSetCACLKResult] CA Dly = 36
6205 13:12:06.403344 CS Dly: 1 (0~32)
6206 13:12:06.403752 ==
6207 13:12:06.406573 Dram Type= 6, Freq= 0, CH_0, rank 1
6208 13:12:06.410288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6209 13:12:06.410756 ==
6210 13:12:06.416714 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6211 13:12:06.423185 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6212 13:12:06.426148 [CA 0] Center 36 (8~64) winsize 57
6213 13:12:06.429759 [CA 1] Center 36 (8~64) winsize 57
6214 13:12:06.432741 [CA 2] Center 36 (8~64) winsize 57
6215 13:12:06.435891 [CA 3] Center 36 (8~64) winsize 57
6216 13:12:06.436372 [CA 4] Center 36 (8~64) winsize 57
6217 13:12:06.439203 [CA 5] Center 36 (8~64) winsize 57
6218 13:12:06.439590
6219 13:12:06.445831 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6220 13:12:06.446230
6221 13:12:06.449268 [CATrainingPosCal] consider 2 rank data
6222 13:12:06.452619 u2DelayCellTimex100 = 270/100 ps
6223 13:12:06.455985 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 13:12:06.459516 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 13:12:06.462254 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 13:12:06.465678 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 13:12:06.469074 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 13:12:06.472440 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 13:12:06.472901
6230 13:12:06.475775 CA PerBit enable=1, Macro0, CA PI delay=36
6231 13:12:06.476165
6232 13:12:06.479036 [CBTSetCACLKResult] CA Dly = 36
6233 13:12:06.482549 CS Dly: 1 (0~32)
6234 13:12:06.482938
6235 13:12:06.485467 ----->DramcWriteLeveling(PI) begin...
6236 13:12:06.485865 ==
6237 13:12:06.488546 Dram Type= 6, Freq= 0, CH_0, rank 0
6238 13:12:06.491843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6239 13:12:06.492238 ==
6240 13:12:06.495496 Write leveling (Byte 0): 40 => 8
6241 13:12:06.498895 Write leveling (Byte 1): 40 => 8
6242 13:12:06.501821 DramcWriteLeveling(PI) end<-----
6243 13:12:06.502335
6244 13:12:06.502649 ==
6245 13:12:06.505164 Dram Type= 6, Freq= 0, CH_0, rank 0
6246 13:12:06.508365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6247 13:12:06.508753 ==
6248 13:12:06.511822 [Gating] SW mode calibration
6249 13:12:06.518612 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6250 13:12:06.525054 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6251 13:12:06.528267 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6252 13:12:06.534784 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6253 13:12:06.538320 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6254 13:12:06.541472 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6255 13:12:06.547944 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6256 13:12:06.551486 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6257 13:12:06.554882 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6258 13:12:06.561630 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6259 13:12:06.565512 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6260 13:12:06.568623 Total UI for P1: 0, mck2ui 16
6261 13:12:06.571352 best dqsien dly found for B0: ( 0, 14, 24)
6262 13:12:06.574637 Total UI for P1: 0, mck2ui 16
6263 13:12:06.578033 best dqsien dly found for B1: ( 0, 14, 24)
6264 13:12:06.581178 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6265 13:12:06.584461 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6266 13:12:06.584852
6267 13:12:06.587907 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6268 13:12:06.591417 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6269 13:12:06.594730 [Gating] SW calibration Done
6270 13:12:06.595120 ==
6271 13:12:06.598041 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 13:12:06.604243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 13:12:06.604630 ==
6274 13:12:06.604927 RX Vref Scan: 0
6275 13:12:06.605258
6276 13:12:06.607947 RX Vref 0 -> 0, step: 1
6277 13:12:06.608473
6278 13:12:06.610600 RX Delay -410 -> 252, step: 16
6279 13:12:06.614337 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6280 13:12:06.617200 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6281 13:12:06.623977 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6282 13:12:06.627297 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6283 13:12:06.630895 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6284 13:12:06.634215 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6285 13:12:06.640721 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6286 13:12:06.644125 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6287 13:12:06.647225 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6288 13:12:06.650396 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6289 13:12:06.656928 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6290 13:12:06.660275 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6291 13:12:06.664136 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6292 13:12:06.667346 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6293 13:12:06.673500 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6294 13:12:06.677241 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6295 13:12:06.677842 ==
6296 13:12:06.680314 Dram Type= 6, Freq= 0, CH_0, rank 0
6297 13:12:06.683541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6298 13:12:06.683931 ==
6299 13:12:06.686522 DQS Delay:
6300 13:12:06.686908 DQS0 = 35, DQS1 = 59
6301 13:12:06.690029 DQM Delay:
6302 13:12:06.690416 DQM0 = 4, DQM1 = 18
6303 13:12:06.690714 DQ Delay:
6304 13:12:06.693170 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6305 13:12:06.696398 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6306 13:12:06.699889 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =16
6307 13:12:06.703562 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6308 13:12:06.704098
6309 13:12:06.704550
6310 13:12:06.704992 ==
6311 13:12:06.707119 Dram Type= 6, Freq= 0, CH_0, rank 0
6312 13:12:06.712879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6313 13:12:06.713315 ==
6314 13:12:06.713620
6315 13:12:06.713894
6316 13:12:06.714154 TX Vref Scan disable
6317 13:12:06.716425 == TX Byte 0 ==
6318 13:12:06.719827 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6319 13:12:06.723154 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6320 13:12:06.726607 == TX Byte 1 ==
6321 13:12:06.729460 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6322 13:12:06.732975 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6323 13:12:06.733217 ==
6324 13:12:06.735766 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 13:12:06.742404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 13:12:06.742546 ==
6327 13:12:06.742653
6328 13:12:06.742752
6329 13:12:06.742846 TX Vref Scan disable
6330 13:12:06.745954 == TX Byte 0 ==
6331 13:12:06.749304 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6332 13:12:06.752722 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6333 13:12:06.755717 == TX Byte 1 ==
6334 13:12:06.758979 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6335 13:12:06.762170 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6336 13:12:06.765416
6337 13:12:06.765553 [DATLAT]
6338 13:12:06.765660 Freq=400, CH0 RK0
6339 13:12:06.765760
6340 13:12:06.769414 DATLAT Default: 0xf
6341 13:12:06.769612 0, 0xFFFF, sum = 0
6342 13:12:06.771940 1, 0xFFFF, sum = 0
6343 13:12:06.772102 2, 0xFFFF, sum = 0
6344 13:12:06.775804 3, 0xFFFF, sum = 0
6345 13:12:06.776066 4, 0xFFFF, sum = 0
6346 13:12:06.779101 5, 0xFFFF, sum = 0
6347 13:12:06.779295 6, 0xFFFF, sum = 0
6348 13:12:06.782574 7, 0xFFFF, sum = 0
6349 13:12:06.785920 8, 0xFFFF, sum = 0
6350 13:12:06.786221 9, 0xFFFF, sum = 0
6351 13:12:06.788642 10, 0xFFFF, sum = 0
6352 13:12:06.788918 11, 0xFFFF, sum = 0
6353 13:12:06.792196 12, 0xFFFF, sum = 0
6354 13:12:06.792585 13, 0x0, sum = 1
6355 13:12:06.795767 14, 0x0, sum = 2
6356 13:12:06.796156 15, 0x0, sum = 3
6357 13:12:06.798894 16, 0x0, sum = 4
6358 13:12:06.799283 best_step = 14
6359 13:12:06.799582
6360 13:12:06.799859 ==
6361 13:12:06.802284 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 13:12:06.805580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 13:12:06.808648 ==
6364 13:12:06.809028 RX Vref Scan: 1
6365 13:12:06.809389
6366 13:12:06.812317 RX Vref 0 -> 0, step: 1
6367 13:12:06.812695
6368 13:12:06.815309 RX Delay -359 -> 252, step: 8
6369 13:12:06.815692
6370 13:12:06.818815 Set Vref, RX VrefLevel [Byte0]: 54
6371 13:12:06.821773 [Byte1]: 59
6372 13:12:06.822154
6373 13:12:06.825006 Final RX Vref Byte 0 = 54 to rank0
6374 13:12:06.828557 Final RX Vref Byte 1 = 59 to rank0
6375 13:12:06.831682 Final RX Vref Byte 0 = 54 to rank1
6376 13:12:06.835013 Final RX Vref Byte 1 = 59 to rank1==
6377 13:12:06.837999 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 13:12:06.841788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 13:12:06.844953 ==
6380 13:12:06.845377 DQS Delay:
6381 13:12:06.845676 DQS0 = 44, DQS1 = 60
6382 13:12:06.848326 DQM Delay:
6383 13:12:06.848748 DQM0 = 10, DQM1 = 16
6384 13:12:06.851585 DQ Delay:
6385 13:12:06.851969 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6386 13:12:06.854971 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6387 13:12:06.858468 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6388 13:12:06.861617 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6389 13:12:06.861995
6390 13:12:06.862376
6391 13:12:06.871396 [DQSOSCAuto] RK0, (LSB)MR18= 0x9b8f, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 390 ps
6392 13:12:06.874462 CH0 RK0: MR19=C0C, MR18=9B8F
6393 13:12:06.881220 CH0_RK0: MR19=0xC0C, MR18=0x9B8F, DQSOSC=390, MR23=63, INC=388, DEC=258
6394 13:12:06.881647 ==
6395 13:12:06.884464 Dram Type= 6, Freq= 0, CH_0, rank 1
6396 13:12:06.888169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 13:12:06.888575 ==
6398 13:12:06.890985 [Gating] SW mode calibration
6399 13:12:06.898006 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6400 13:12:06.904081 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6401 13:12:06.907804 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6402 13:12:06.910852 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6403 13:12:06.917396 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6404 13:12:06.920448 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6405 13:12:06.923986 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6406 13:12:06.930566 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6407 13:12:06.933659 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6408 13:12:06.937105 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6409 13:12:06.943781 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6410 13:12:06.944171 Total UI for P1: 0, mck2ui 16
6411 13:12:06.947286 best dqsien dly found for B0: ( 0, 14, 24)
6412 13:12:06.950209 Total UI for P1: 0, mck2ui 16
6413 13:12:06.953801 best dqsien dly found for B1: ( 0, 14, 24)
6414 13:12:06.960702 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6415 13:12:06.964036 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6416 13:12:06.964527
6417 13:12:06.967445 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6418 13:12:06.971093 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6419 13:12:06.973782 [Gating] SW calibration Done
6420 13:12:06.974235 ==
6421 13:12:06.977064 Dram Type= 6, Freq= 0, CH_0, rank 1
6422 13:12:06.980065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 13:12:06.980449 ==
6424 13:12:06.983838 RX Vref Scan: 0
6425 13:12:06.984318
6426 13:12:06.984624 RX Vref 0 -> 0, step: 1
6427 13:12:06.984899
6428 13:12:06.986987 RX Delay -410 -> 252, step: 16
6429 13:12:06.993261 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6430 13:12:06.996644 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6431 13:12:06.999958 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6432 13:12:07.003116 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6433 13:12:07.009920 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6434 13:12:07.013321 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6435 13:12:07.016580 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6436 13:12:07.019522 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6437 13:12:07.026567 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6438 13:12:07.029498 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6439 13:12:07.032882 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6440 13:12:07.036052 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6441 13:12:07.043029 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6442 13:12:07.045667 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6443 13:12:07.049477 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6444 13:12:07.056418 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6445 13:12:07.056843 ==
6446 13:12:07.059075 Dram Type= 6, Freq= 0, CH_0, rank 1
6447 13:12:07.062802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 13:12:07.063268 ==
6449 13:12:07.063670 DQS Delay:
6450 13:12:07.066009 DQS0 = 35, DQS1 = 59
6451 13:12:07.066391 DQM Delay:
6452 13:12:07.069433 DQM0 = 6, DQM1 = 16
6453 13:12:07.069813 DQ Delay:
6454 13:12:07.072501 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6455 13:12:07.075968 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6456 13:12:07.079222 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6457 13:12:07.082237 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6458 13:12:07.082623
6459 13:12:07.082918
6460 13:12:07.083191 ==
6461 13:12:07.085651 Dram Type= 6, Freq= 0, CH_0, rank 1
6462 13:12:07.088880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 13:12:07.089345 ==
6464 13:12:07.089649
6465 13:12:07.089921
6466 13:12:07.092577 TX Vref Scan disable
6467 13:12:07.093043 == TX Byte 0 ==
6468 13:12:07.098974 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6469 13:12:07.101872 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6470 13:12:07.102259 == TX Byte 1 ==
6471 13:12:07.108637 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6472 13:12:07.112255 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6473 13:12:07.112725 ==
6474 13:12:07.115160 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 13:12:07.118657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 13:12:07.119046 ==
6477 13:12:07.119347
6478 13:12:07.119623
6479 13:12:07.121620 TX Vref Scan disable
6480 13:12:07.125537 == TX Byte 0 ==
6481 13:12:07.128389 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6482 13:12:07.131603 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6483 13:12:07.135229 == TX Byte 1 ==
6484 13:12:07.138510 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6485 13:12:07.141637 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6486 13:12:07.142023
6487 13:12:07.142319 [DATLAT]
6488 13:12:07.144814 Freq=400, CH0 RK1
6489 13:12:07.145233
6490 13:12:07.145538 DATLAT Default: 0xe
6491 13:12:07.148088 0, 0xFFFF, sum = 0
6492 13:12:07.148630 1, 0xFFFF, sum = 0
6493 13:12:07.151716 2, 0xFFFF, sum = 0
6494 13:12:07.152207 3, 0xFFFF, sum = 0
6495 13:12:07.155209 4, 0xFFFF, sum = 0
6496 13:12:07.157942 5, 0xFFFF, sum = 0
6497 13:12:07.158341 6, 0xFFFF, sum = 0
6498 13:12:07.161895 7, 0xFFFF, sum = 0
6499 13:12:07.162288 8, 0xFFFF, sum = 0
6500 13:12:07.165023 9, 0xFFFF, sum = 0
6501 13:12:07.165459 10, 0xFFFF, sum = 0
6502 13:12:07.167706 11, 0xFFFF, sum = 0
6503 13:12:07.168131 12, 0xFFFF, sum = 0
6504 13:12:07.170973 13, 0x0, sum = 1
6505 13:12:07.171507 14, 0x0, sum = 2
6506 13:12:07.174290 15, 0x0, sum = 3
6507 13:12:07.174771 16, 0x0, sum = 4
6508 13:12:07.177762 best_step = 14
6509 13:12:07.178303
6510 13:12:07.178750 ==
6511 13:12:07.181091 Dram Type= 6, Freq= 0, CH_0, rank 1
6512 13:12:07.184643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 13:12:07.185230 ==
6514 13:12:07.187835 RX Vref Scan: 0
6515 13:12:07.188216
6516 13:12:07.188518 RX Vref 0 -> 0, step: 1
6517 13:12:07.188921
6518 13:12:07.191414 RX Delay -359 -> 252, step: 8
6519 13:12:07.198654 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6520 13:12:07.202117 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6521 13:12:07.205512 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6522 13:12:07.211973 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6523 13:12:07.215305 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6524 13:12:07.218543 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6525 13:12:07.221780 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6526 13:12:07.228479 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6527 13:12:07.231847 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6528 13:12:07.235085 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6529 13:12:07.238418 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6530 13:12:07.245121 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6531 13:12:07.248198 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6532 13:12:07.251470 iDelay=209, Bit 13, Center -36 (-279 ~ 208) 488
6533 13:12:07.254604 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6534 13:12:07.261246 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6535 13:12:07.261633 ==
6536 13:12:07.264925 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 13:12:07.267938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 13:12:07.268398 ==
6539 13:12:07.268703 DQS Delay:
6540 13:12:07.271322 DQS0 = 44, DQS1 = 60
6541 13:12:07.271765 DQM Delay:
6542 13:12:07.274426 DQM0 = 9, DQM1 = 16
6543 13:12:07.274859 DQ Delay:
6544 13:12:07.278109 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6545 13:12:07.281628 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6546 13:12:07.284150 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6547 13:12:07.287598 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6548 13:12:07.287984
6549 13:12:07.288375
6550 13:12:07.294144 [DQSOSCAuto] RK1, (LSB)MR18= 0x8e87, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
6551 13:12:07.297609 CH0 RK1: MR19=C0C, MR18=8E87
6552 13:12:07.304347 CH0_RK1: MR19=0xC0C, MR18=0x8E87, DQSOSC=392, MR23=63, INC=384, DEC=256
6553 13:12:07.307507 [RxdqsGatingPostProcess] freq 400
6554 13:12:07.314435 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6555 13:12:07.317589 best DQS0 dly(2T, 0.5T) = (0, 10)
6556 13:12:07.320479 best DQS1 dly(2T, 0.5T) = (0, 10)
6557 13:12:07.324043 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6558 13:12:07.326940 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6559 13:12:07.330496 best DQS0 dly(2T, 0.5T) = (0, 10)
6560 13:12:07.331024 best DQS1 dly(2T, 0.5T) = (0, 10)
6561 13:12:07.333626 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6562 13:12:07.336944 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6563 13:12:07.340437 Pre-setting of DQS Precalculation
6564 13:12:07.346832 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6565 13:12:07.347300 ==
6566 13:12:07.350336 Dram Type= 6, Freq= 0, CH_1, rank 0
6567 13:12:07.353694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6568 13:12:07.354080 ==
6569 13:12:07.360065 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6570 13:12:07.367371 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6571 13:12:07.370035 [CA 0] Center 36 (8~64) winsize 57
6572 13:12:07.373675 [CA 1] Center 36 (8~64) winsize 57
6573 13:12:07.376582 [CA 2] Center 36 (8~64) winsize 57
6574 13:12:07.377084 [CA 3] Center 36 (8~64) winsize 57
6575 13:12:07.379823 [CA 4] Center 36 (8~64) winsize 57
6576 13:12:07.383786 [CA 5] Center 36 (8~64) winsize 57
6577 13:12:07.384202
6578 13:12:07.389809 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6579 13:12:07.390198
6580 13:12:07.393494 [CATrainingPosCal] consider 1 rank data
6581 13:12:07.396679 u2DelayCellTimex100 = 270/100 ps
6582 13:12:07.400086 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6583 13:12:07.402944 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6584 13:12:07.406181 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6585 13:12:07.409269 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6586 13:12:07.412825 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6587 13:12:07.416025 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6588 13:12:07.416456
6589 13:12:07.419288 CA PerBit enable=1, Macro0, CA PI delay=36
6590 13:12:07.419717
6591 13:12:07.422597 [CBTSetCACLKResult] CA Dly = 36
6592 13:12:07.425874 CS Dly: 1 (0~32)
6593 13:12:07.426262 ==
6594 13:12:07.429181 Dram Type= 6, Freq= 0, CH_1, rank 1
6595 13:12:07.432446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6596 13:12:07.432836 ==
6597 13:12:07.439017 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6598 13:12:07.445537 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6599 13:12:07.448942 [CA 0] Center 36 (8~64) winsize 57
6600 13:12:07.452127 [CA 1] Center 36 (8~64) winsize 57
6601 13:12:07.455405 [CA 2] Center 36 (8~64) winsize 57
6602 13:12:07.455794 [CA 3] Center 36 (8~64) winsize 57
6603 13:12:07.458928 [CA 4] Center 36 (8~64) winsize 57
6604 13:12:07.461869 [CA 5] Center 36 (8~64) winsize 57
6605 13:12:07.462258
6606 13:12:07.468511 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6607 13:12:07.469002
6608 13:12:07.472369 [CATrainingPosCal] consider 2 rank data
6609 13:12:07.475140 u2DelayCellTimex100 = 270/100 ps
6610 13:12:07.478169 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 13:12:07.481533 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 13:12:07.485240 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 13:12:07.488235 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 13:12:07.492050 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 13:12:07.495071 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 13:12:07.495506
6617 13:12:07.498514 CA PerBit enable=1, Macro0, CA PI delay=36
6618 13:12:07.498905
6619 13:12:07.501343 [CBTSetCACLKResult] CA Dly = 36
6620 13:12:07.504597 CS Dly: 1 (0~32)
6621 13:12:07.505005
6622 13:12:07.507929 ----->DramcWriteLeveling(PI) begin...
6623 13:12:07.508319 ==
6624 13:12:07.511441 Dram Type= 6, Freq= 0, CH_1, rank 0
6625 13:12:07.515264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6626 13:12:07.515737 ==
6627 13:12:07.518361 Write leveling (Byte 0): 40 => 8
6628 13:12:07.521742 Write leveling (Byte 1): 40 => 8
6629 13:12:07.524879 DramcWriteLeveling(PI) end<-----
6630 13:12:07.525410
6631 13:12:07.525718 ==
6632 13:12:07.528026 Dram Type= 6, Freq= 0, CH_1, rank 0
6633 13:12:07.531543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6634 13:12:07.531937 ==
6635 13:12:07.534744 [Gating] SW mode calibration
6636 13:12:07.540839 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6637 13:12:07.547751 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6638 13:12:07.551203 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6639 13:12:07.557500 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6640 13:12:07.561331 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6641 13:12:07.564442 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6642 13:12:07.571051 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6643 13:12:07.573904 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6644 13:12:07.577682 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6645 13:12:07.584252 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6646 13:12:07.587206 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6647 13:12:07.590651 Total UI for P1: 0, mck2ui 16
6648 13:12:07.594009 best dqsien dly found for B0: ( 0, 14, 24)
6649 13:12:07.597246 Total UI for P1: 0, mck2ui 16
6650 13:12:07.600393 best dqsien dly found for B1: ( 0, 14, 24)
6651 13:12:07.603839 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6652 13:12:07.607241 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6653 13:12:07.607628
6654 13:12:07.610959 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6655 13:12:07.613839 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6656 13:12:07.617108 [Gating] SW calibration Done
6657 13:12:07.617575 ==
6658 13:12:07.620503 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 13:12:07.623978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 13:12:07.626912 ==
6661 13:12:07.627408 RX Vref Scan: 0
6662 13:12:07.627715
6663 13:12:07.630211 RX Vref 0 -> 0, step: 1
6664 13:12:07.630735
6665 13:12:07.633745 RX Delay -410 -> 252, step: 16
6666 13:12:07.636559 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6667 13:12:07.640108 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6668 13:12:07.643337 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6669 13:12:07.650234 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6670 13:12:07.653620 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6671 13:12:07.656687 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6672 13:12:07.660230 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6673 13:12:07.666336 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6674 13:12:07.669452 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6675 13:12:07.672907 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6676 13:12:07.679300 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6677 13:12:07.682739 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6678 13:12:07.685805 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6679 13:12:07.689314 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6680 13:12:07.695816 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6681 13:12:07.699088 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6682 13:12:07.699478 ==
6683 13:12:07.702814 Dram Type= 6, Freq= 0, CH_1, rank 0
6684 13:12:07.705471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6685 13:12:07.705862 ==
6686 13:12:07.708932 DQS Delay:
6687 13:12:07.709474 DQS0 = 43, DQS1 = 51
6688 13:12:07.712100 DQM Delay:
6689 13:12:07.712489 DQM0 = 13, DQM1 = 13
6690 13:12:07.712925 DQ Delay:
6691 13:12:07.715525 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6692 13:12:07.718644 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6693 13:12:07.722295 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6694 13:12:07.725599 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6695 13:12:07.725987
6696 13:12:07.726285
6697 13:12:07.726560 ==
6698 13:12:07.729026 Dram Type= 6, Freq= 0, CH_1, rank 0
6699 13:12:07.735813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6700 13:12:07.736258 ==
6701 13:12:07.736733
6702 13:12:07.737208
6703 13:12:07.737501 TX Vref Scan disable
6704 13:12:07.739148 == TX Byte 0 ==
6705 13:12:07.741835 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6706 13:12:07.745387 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6707 13:12:07.748798 == TX Byte 1 ==
6708 13:12:07.752272 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6709 13:12:07.755240 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6710 13:12:07.758316 ==
6711 13:12:07.758753 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 13:12:07.765729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 13:12:07.766186 ==
6714 13:12:07.766490
6715 13:12:07.766766
6716 13:12:07.768712 TX Vref Scan disable
6717 13:12:07.769225 == TX Byte 0 ==
6718 13:12:07.771965 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6719 13:12:07.778661 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6720 13:12:07.779216 == TX Byte 1 ==
6721 13:12:07.781786 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6722 13:12:07.788107 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6723 13:12:07.788495
6724 13:12:07.788794 [DATLAT]
6725 13:12:07.789118 Freq=400, CH1 RK0
6726 13:12:07.789463
6727 13:12:07.791459 DATLAT Default: 0xf
6728 13:12:07.791843 0, 0xFFFF, sum = 0
6729 13:12:07.795140 1, 0xFFFF, sum = 0
6730 13:12:07.798470 2, 0xFFFF, sum = 0
6731 13:12:07.798862 3, 0xFFFF, sum = 0
6732 13:12:07.801376 4, 0xFFFF, sum = 0
6733 13:12:07.801768 5, 0xFFFF, sum = 0
6734 13:12:07.804681 6, 0xFFFF, sum = 0
6735 13:12:07.805184 7, 0xFFFF, sum = 0
6736 13:12:07.808019 8, 0xFFFF, sum = 0
6737 13:12:07.808430 9, 0xFFFF, sum = 0
6738 13:12:07.811094 10, 0xFFFF, sum = 0
6739 13:12:07.811499 11, 0xFFFF, sum = 0
6740 13:12:07.814560 12, 0xFFFF, sum = 0
6741 13:12:07.814955 13, 0x0, sum = 1
6742 13:12:07.818105 14, 0x0, sum = 2
6743 13:12:07.818554 15, 0x0, sum = 3
6744 13:12:07.820797 16, 0x0, sum = 4
6745 13:12:07.821227 best_step = 14
6746 13:12:07.821535
6747 13:12:07.821814 ==
6748 13:12:07.824164 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 13:12:07.830979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 13:12:07.831367 ==
6751 13:12:07.831669 RX Vref Scan: 1
6752 13:12:07.832017
6753 13:12:07.834174 RX Vref 0 -> 0, step: 1
6754 13:12:07.834620
6755 13:12:07.837682 RX Delay -343 -> 252, step: 8
6756 13:12:07.838068
6757 13:12:07.840811 Set Vref, RX VrefLevel [Byte0]: 52
6758 13:12:07.843699 [Byte1]: 53
6759 13:12:07.844084
6760 13:12:07.847481 Final RX Vref Byte 0 = 52 to rank0
6761 13:12:07.850966 Final RX Vref Byte 1 = 53 to rank0
6762 13:12:07.854097 Final RX Vref Byte 0 = 52 to rank1
6763 13:12:07.857304 Final RX Vref Byte 1 = 53 to rank1==
6764 13:12:07.860715 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 13:12:07.863517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 13:12:07.867365 ==
6767 13:12:07.867891 DQS Delay:
6768 13:12:07.868245 DQS0 = 44, DQS1 = 52
6769 13:12:07.870552 DQM Delay:
6770 13:12:07.870935 DQM0 = 12, DQM1 = 10
6771 13:12:07.873721 DQ Delay:
6772 13:12:07.877532 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6773 13:12:07.877994 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6774 13:12:07.880442 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6775 13:12:07.883274 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6776 13:12:07.883662
6777 13:12:07.886849
6778 13:12:07.893581 [DQSOSCAuto] RK0, (LSB)MR18= 0x759b, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 395 ps
6779 13:12:07.896429 CH1 RK0: MR19=C0C, MR18=759B
6780 13:12:07.903983 CH1_RK0: MR19=0xC0C, MR18=0x759B, DQSOSC=390, MR23=63, INC=388, DEC=258
6781 13:12:07.904447 ==
6782 13:12:07.907037 Dram Type= 6, Freq= 0, CH_1, rank 1
6783 13:12:07.910136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 13:12:07.910546 ==
6785 13:12:07.913178 [Gating] SW mode calibration
6786 13:12:07.919780 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6787 13:12:07.925901 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6788 13:12:07.929707 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6789 13:12:07.932527 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6790 13:12:07.939586 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6791 13:12:07.942548 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6792 13:12:07.946145 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6793 13:12:07.952342 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6794 13:12:07.955992 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6795 13:12:07.958718 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6796 13:12:07.965413 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6797 13:12:07.968738 Total UI for P1: 0, mck2ui 16
6798 13:12:07.972021 best dqsien dly found for B0: ( 0, 14, 24)
6799 13:12:07.972475 Total UI for P1: 0, mck2ui 16
6800 13:12:07.978609 best dqsien dly found for B1: ( 0, 14, 24)
6801 13:12:07.982224 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6802 13:12:07.985440 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6803 13:12:07.985843
6804 13:12:07.989049 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6805 13:12:07.992344 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6806 13:12:07.995493 [Gating] SW calibration Done
6807 13:12:07.995874 ==
6808 13:12:07.998519 Dram Type= 6, Freq= 0, CH_1, rank 1
6809 13:12:08.001660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 13:12:08.002052 ==
6811 13:12:08.005232 RX Vref Scan: 0
6812 13:12:08.005625
6813 13:12:08.008465 RX Vref 0 -> 0, step: 1
6814 13:12:08.008850
6815 13:12:08.009184 RX Delay -410 -> 252, step: 16
6816 13:12:08.014837 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6817 13:12:08.018487 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6818 13:12:08.021506 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6819 13:12:08.028313 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6820 13:12:08.031599 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6821 13:12:08.034947 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6822 13:12:08.038242 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6823 13:12:08.044406 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6824 13:12:08.048520 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6825 13:12:08.051022 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6826 13:12:08.054427 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6827 13:12:08.061562 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6828 13:12:08.064441 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6829 13:12:08.067825 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6830 13:12:08.070936 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6831 13:12:08.078104 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6832 13:12:08.078624 ==
6833 13:12:08.080753 Dram Type= 6, Freq= 0, CH_1, rank 1
6834 13:12:08.084461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 13:12:08.084850 ==
6836 13:12:08.087704 DQS Delay:
6837 13:12:08.088178 DQS0 = 43, DQS1 = 51
6838 13:12:08.088481 DQM Delay:
6839 13:12:08.090757 DQM0 = 8, DQM1 = 14
6840 13:12:08.091144 DQ Delay:
6841 13:12:08.093778 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6842 13:12:08.097400 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6843 13:12:08.100744 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6844 13:12:08.104050 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6845 13:12:08.104538
6846 13:12:08.104847
6847 13:12:08.105124 ==
6848 13:12:08.107161 Dram Type= 6, Freq= 0, CH_1, rank 1
6849 13:12:08.110395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 13:12:08.113737 ==
6851 13:12:08.114255
6852 13:12:08.114566
6853 13:12:08.114844 TX Vref Scan disable
6854 13:12:08.116768 == TX Byte 0 ==
6855 13:12:08.120272 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6856 13:12:08.123531 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6857 13:12:08.126959 == TX Byte 1 ==
6858 13:12:08.130464 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6859 13:12:08.133535 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6860 13:12:08.133923 ==
6861 13:12:08.136717 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 13:12:08.143280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 13:12:08.143675 ==
6864 13:12:08.144022
6865 13:12:08.144454
6866 13:12:08.144747 TX Vref Scan disable
6867 13:12:08.146687 == TX Byte 0 ==
6868 13:12:08.150065 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6869 13:12:08.153325 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6870 13:12:08.156382 == TX Byte 1 ==
6871 13:12:08.160055 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6872 13:12:08.162967 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6873 13:12:08.163358
6874 13:12:08.166883 [DATLAT]
6875 13:12:08.167367 Freq=400, CH1 RK1
6876 13:12:08.167706
6877 13:12:08.169389 DATLAT Default: 0xe
6878 13:12:08.169778 0, 0xFFFF, sum = 0
6879 13:12:08.172833 1, 0xFFFF, sum = 0
6880 13:12:08.173257 2, 0xFFFF, sum = 0
6881 13:12:08.176483 3, 0xFFFF, sum = 0
6882 13:12:08.177003 4, 0xFFFF, sum = 0
6883 13:12:08.179249 5, 0xFFFF, sum = 0
6884 13:12:08.179644 6, 0xFFFF, sum = 0
6885 13:12:08.182827 7, 0xFFFF, sum = 0
6886 13:12:08.183292 8, 0xFFFF, sum = 0
6887 13:12:08.186172 9, 0xFFFF, sum = 0
6888 13:12:08.189179 10, 0xFFFF, sum = 0
6889 13:12:08.189589 11, 0xFFFF, sum = 0
6890 13:12:08.192966 12, 0xFFFF, sum = 0
6891 13:12:08.193495 13, 0x0, sum = 1
6892 13:12:08.196043 14, 0x0, sum = 2
6893 13:12:08.196444 15, 0x0, sum = 3
6894 13:12:08.196767 16, 0x0, sum = 4
6895 13:12:08.199437 best_step = 14
6896 13:12:08.199818
6897 13:12:08.200135 ==
6898 13:12:08.202745 Dram Type= 6, Freq= 0, CH_1, rank 1
6899 13:12:08.205728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 13:12:08.206155 ==
6901 13:12:08.209484 RX Vref Scan: 0
6902 13:12:08.209943
6903 13:12:08.212698 RX Vref 0 -> 0, step: 1
6904 13:12:08.213083
6905 13:12:08.213432 RX Delay -343 -> 252, step: 8
6906 13:12:08.221296 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6907 13:12:08.224090 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6908 13:12:08.227746 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6909 13:12:08.234080 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6910 13:12:08.237444 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6911 13:12:08.240807 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6912 13:12:08.244104 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6913 13:12:08.250867 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6914 13:12:08.253851 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6915 13:12:08.257164 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6916 13:12:08.260383 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6917 13:12:08.267192 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6918 13:12:08.270149 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6919 13:12:08.273477 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6920 13:12:08.280247 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6921 13:12:08.283414 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6922 13:12:08.283817 ==
6923 13:12:08.286840 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 13:12:08.289908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 13:12:08.290300 ==
6926 13:12:08.293463 DQS Delay:
6927 13:12:08.293846 DQS0 = 48, DQS1 = 52
6928 13:12:08.294144 DQM Delay:
6929 13:12:08.296591 DQM0 = 12, DQM1 = 10
6930 13:12:08.297049 DQ Delay:
6931 13:12:08.299934 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6932 13:12:08.303359 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =12
6933 13:12:08.306431 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6934 13:12:08.309575 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6935 13:12:08.310060
6936 13:12:08.310535
6937 13:12:08.319675 [DQSOSCAuto] RK1, (LSB)MR18= 0x7fb7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
6938 13:12:08.320153 CH1 RK1: MR19=C0C, MR18=7FB7
6939 13:12:08.326598 CH1_RK1: MR19=0xC0C, MR18=0x7FB7, DQSOSC=387, MR23=63, INC=394, DEC=262
6940 13:12:08.329305 [RxdqsGatingPostProcess] freq 400
6941 13:12:08.336293 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6942 13:12:08.339125 best DQS0 dly(2T, 0.5T) = (0, 10)
6943 13:12:08.342645 best DQS1 dly(2T, 0.5T) = (0, 10)
6944 13:12:08.345721 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6945 13:12:08.348969 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6946 13:12:08.352640 best DQS0 dly(2T, 0.5T) = (0, 10)
6947 13:12:08.356266 best DQS1 dly(2T, 0.5T) = (0, 10)
6948 13:12:08.359316 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6949 13:12:08.362557 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6950 13:12:08.365933 Pre-setting of DQS Precalculation
6951 13:12:08.369335 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6952 13:12:08.375953 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6953 13:12:08.382336 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6954 13:12:08.382789
6955 13:12:08.383091
6956 13:12:08.385446 [Calibration Summary] 800 Mbps
6957 13:12:08.389180 CH 0, Rank 0
6958 13:12:08.389565 SW Impedance : PASS
6959 13:12:08.392012 DUTY Scan : NO K
6960 13:12:08.395804 ZQ Calibration : PASS
6961 13:12:08.396278 Jitter Meter : NO K
6962 13:12:08.399064 CBT Training : PASS
6963 13:12:08.401922 Write leveling : PASS
6964 13:12:08.402309 RX DQS gating : PASS
6965 13:12:08.405418 RX DQ/DQS(RDDQC) : PASS
6966 13:12:08.408919 TX DQ/DQS : PASS
6967 13:12:08.409342 RX DATLAT : PASS
6968 13:12:08.412157 RX DQ/DQS(Engine): PASS
6969 13:12:08.415455 TX OE : NO K
6970 13:12:08.415871 All Pass.
6971 13:12:08.416178
6972 13:12:08.416455 CH 0, Rank 1
6973 13:12:08.418503 SW Impedance : PASS
6974 13:12:08.422005 DUTY Scan : NO K
6975 13:12:08.422391 ZQ Calibration : PASS
6976 13:12:08.425019 Jitter Meter : NO K
6977 13:12:08.428520 CBT Training : PASS
6978 13:12:08.428977 Write leveling : NO K
6979 13:12:08.431763 RX DQS gating : PASS
6980 13:12:08.432151 RX DQ/DQS(RDDQC) : PASS
6981 13:12:08.435307 TX DQ/DQS : PASS
6982 13:12:08.438584 RX DATLAT : PASS
6983 13:12:08.438975 RX DQ/DQS(Engine): PASS
6984 13:12:08.441987 TX OE : NO K
6985 13:12:08.442401 All Pass.
6986 13:12:08.442711
6987 13:12:08.444787 CH 1, Rank 0
6988 13:12:08.445207 SW Impedance : PASS
6989 13:12:08.448661 DUTY Scan : NO K
6990 13:12:08.451716 ZQ Calibration : PASS
6991 13:12:08.452284 Jitter Meter : NO K
6992 13:12:08.454939 CBT Training : PASS
6993 13:12:08.457988 Write leveling : PASS
6994 13:12:08.458547 RX DQS gating : PASS
6995 13:12:08.461755 RX DQ/DQS(RDDQC) : PASS
6996 13:12:08.464925 TX DQ/DQS : PASS
6997 13:12:08.465372 RX DATLAT : PASS
6998 13:12:08.468232 RX DQ/DQS(Engine): PASS
6999 13:12:08.471574 TX OE : NO K
7000 13:12:08.471964 All Pass.
7001 13:12:08.472262
7002 13:12:08.472538 CH 1, Rank 1
7003 13:12:08.474395 SW Impedance : PASS
7004 13:12:08.477638 DUTY Scan : NO K
7005 13:12:08.477914 ZQ Calibration : PASS
7006 13:12:08.480963 Jitter Meter : NO K
7007 13:12:08.484523 CBT Training : PASS
7008 13:12:08.484690 Write leveling : NO K
7009 13:12:08.487587 RX DQS gating : PASS
7010 13:12:08.490772 RX DQ/DQS(RDDQC) : PASS
7011 13:12:08.490946 TX DQ/DQS : PASS
7012 13:12:08.494257 RX DATLAT : PASS
7013 13:12:08.494385 RX DQ/DQS(Engine): PASS
7014 13:12:08.497108 TX OE : NO K
7015 13:12:08.497250 All Pass.
7016 13:12:08.497345
7017 13:12:08.500987 DramC Write-DBI off
7018 13:12:08.504144 PER_BANK_REFRESH: Hybrid Mode
7019 13:12:08.504239 TX_TRACKING: ON
7020 13:12:08.514106 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7021 13:12:08.517016 [FAST_K] Save calibration result to emmc
7022 13:12:08.520468 dramc_set_vcore_voltage set vcore to 725000
7023 13:12:08.523865 Read voltage for 1600, 0
7024 13:12:08.523947 Vio18 = 0
7025 13:12:08.527132 Vcore = 725000
7026 13:12:08.527207 Vdram = 0
7027 13:12:08.527264 Vddq = 0
7028 13:12:08.527348 Vmddr = 0
7029 13:12:08.533486 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7030 13:12:08.540639 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7031 13:12:08.540746 MEM_TYPE=3, freq_sel=13
7032 13:12:08.543455 sv_algorithm_assistance_LP4_3733
7033 13:12:08.547104 ============ PULL DRAM RESETB DOWN ============
7034 13:12:08.553508 ========== PULL DRAM RESETB DOWN end =========
7035 13:12:08.557028 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7036 13:12:08.560383 ===================================
7037 13:12:08.563350 LPDDR4 DRAM CONFIGURATION
7038 13:12:08.566559 ===================================
7039 13:12:08.566635 EX_ROW_EN[0] = 0x0
7040 13:12:08.569742 EX_ROW_EN[1] = 0x0
7041 13:12:08.573172 LP4Y_EN = 0x0
7042 13:12:08.573263 WORK_FSP = 0x1
7043 13:12:08.576548 WL = 0x5
7044 13:12:08.576625 RL = 0x5
7045 13:12:08.579849 BL = 0x2
7046 13:12:08.579927 RPST = 0x0
7047 13:12:08.583109 RD_PRE = 0x0
7048 13:12:08.583185 WR_PRE = 0x1
7049 13:12:08.586357 WR_PST = 0x1
7050 13:12:08.586459 DBI_WR = 0x0
7051 13:12:08.589684 DBI_RD = 0x0
7052 13:12:08.589762 OTF = 0x1
7053 13:12:08.593017 ===================================
7054 13:12:08.596453 ===================================
7055 13:12:08.599613 ANA top config
7056 13:12:08.603108 ===================================
7057 13:12:08.603210 DLL_ASYNC_EN = 0
7058 13:12:08.606456 ALL_SLAVE_EN = 0
7059 13:12:08.609742 NEW_RANK_MODE = 1
7060 13:12:08.613113 DLL_IDLE_MODE = 1
7061 13:12:08.615923 LP45_APHY_COMB_EN = 1
7062 13:12:08.616011 TX_ODT_DIS = 0
7063 13:12:08.619354 NEW_8X_MODE = 1
7064 13:12:08.622847 ===================================
7065 13:12:08.626700 ===================================
7066 13:12:08.629451 data_rate = 3200
7067 13:12:08.632816 CKR = 1
7068 13:12:08.636255 DQ_P2S_RATIO = 8
7069 13:12:08.639282 ===================================
7070 13:12:08.642808 CA_P2S_RATIO = 8
7071 13:12:08.642928 DQ_CA_OPEN = 0
7072 13:12:08.645948 DQ_SEMI_OPEN = 0
7073 13:12:08.649150 CA_SEMI_OPEN = 0
7074 13:12:08.652537 CA_FULL_RATE = 0
7075 13:12:08.655510 DQ_CKDIV4_EN = 0
7076 13:12:08.658824 CA_CKDIV4_EN = 0
7077 13:12:08.658970 CA_PREDIV_EN = 0
7078 13:12:08.662895 PH8_DLY = 12
7079 13:12:08.665983 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7080 13:12:08.669062 DQ_AAMCK_DIV = 4
7081 13:12:08.672016 CA_AAMCK_DIV = 4
7082 13:12:08.675452 CA_ADMCK_DIV = 4
7083 13:12:08.675584 DQ_TRACK_CA_EN = 0
7084 13:12:08.678892 CA_PICK = 1600
7085 13:12:08.682184 CA_MCKIO = 1600
7086 13:12:08.685620 MCKIO_SEMI = 0
7087 13:12:08.688556 PLL_FREQ = 3068
7088 13:12:08.692423 DQ_UI_PI_RATIO = 32
7089 13:12:08.695374 CA_UI_PI_RATIO = 0
7090 13:12:08.698924 ===================================
7091 13:12:08.701739 ===================================
7092 13:12:08.701832 memory_type:LPDDR4
7093 13:12:08.705044 GP_NUM : 10
7094 13:12:08.708525 SRAM_EN : 1
7095 13:12:08.708618 MD32_EN : 0
7096 13:12:08.711836 ===================================
7097 13:12:08.715236 [ANA_INIT] >>>>>>>>>>>>>>
7098 13:12:08.718129 <<<<<< [CONFIGURE PHASE]: ANA_TX
7099 13:12:08.721494 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7100 13:12:08.724820 ===================================
7101 13:12:08.728105 data_rate = 3200,PCW = 0X7600
7102 13:12:08.731723 ===================================
7103 13:12:08.734930 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7104 13:12:08.741288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7105 13:12:08.744723 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7106 13:12:08.750968 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7107 13:12:08.754552 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7108 13:12:08.757758 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7109 13:12:08.757901 [ANA_INIT] flow start
7110 13:12:08.760890 [ANA_INIT] PLL >>>>>>>>
7111 13:12:08.764442 [ANA_INIT] PLL <<<<<<<<
7112 13:12:08.764593 [ANA_INIT] MIDPI >>>>>>>>
7113 13:12:08.767415 [ANA_INIT] MIDPI <<<<<<<<
7114 13:12:08.770661 [ANA_INIT] DLL >>>>>>>>
7115 13:12:08.774286 [ANA_INIT] DLL <<<<<<<<
7116 13:12:08.774432 [ANA_INIT] flow end
7117 13:12:08.777612 ============ LP4 DIFF to SE enter ============
7118 13:12:08.784477 ============ LP4 DIFF to SE exit ============
7119 13:12:08.784635 [ANA_INIT] <<<<<<<<<<<<<
7120 13:12:08.787563 [Flow] Enable top DCM control >>>>>
7121 13:12:08.790896 [Flow] Enable top DCM control <<<<<
7122 13:12:08.793872 Enable DLL master slave shuffle
7123 13:12:08.800528 ==============================================================
7124 13:12:08.800671 Gating Mode config
7125 13:12:08.807547 ==============================================================
7126 13:12:08.810389 Config description:
7127 13:12:08.820532 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7128 13:12:08.827204 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7129 13:12:08.830232 SELPH_MODE 0: By rank 1: By Phase
7130 13:12:08.836882 ==============================================================
7131 13:12:08.840183 GAT_TRACK_EN = 1
7132 13:12:08.840318 RX_GATING_MODE = 2
7133 13:12:08.843598 RX_GATING_TRACK_MODE = 2
7134 13:12:08.847069 SELPH_MODE = 1
7135 13:12:08.850466 PICG_EARLY_EN = 1
7136 13:12:08.853593 VALID_LAT_VALUE = 1
7137 13:12:08.860168 ==============================================================
7138 13:12:08.863425 Enter into Gating configuration >>>>
7139 13:12:08.866715 Exit from Gating configuration <<<<
7140 13:12:08.869974 Enter into DVFS_PRE_config >>>>>
7141 13:12:08.879888 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7142 13:12:08.883317 Exit from DVFS_PRE_config <<<<<
7143 13:12:08.886175 Enter into PICG configuration >>>>
7144 13:12:08.890028 Exit from PICG configuration <<<<
7145 13:12:08.892864 [RX_INPUT] configuration >>>>>
7146 13:12:08.896289 [RX_INPUT] configuration <<<<<
7147 13:12:08.899491 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7148 13:12:08.906421 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7149 13:12:08.913032 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7150 13:12:08.919817 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7151 13:12:08.922677 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7152 13:12:08.929646 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7153 13:12:08.933116 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7154 13:12:08.939704 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7155 13:12:08.942834 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7156 13:12:08.945859 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7157 13:12:08.949174 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7158 13:12:08.955814 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7159 13:12:08.959432 ===================================
7160 13:12:08.963040 LPDDR4 DRAM CONFIGURATION
7161 13:12:08.965846 ===================================
7162 13:12:08.965942 EX_ROW_EN[0] = 0x0
7163 13:12:08.969287 EX_ROW_EN[1] = 0x0
7164 13:12:08.969379 LP4Y_EN = 0x0
7165 13:12:08.972442 WORK_FSP = 0x1
7166 13:12:08.972554 WL = 0x5
7167 13:12:08.975602 RL = 0x5
7168 13:12:08.975726 BL = 0x2
7169 13:12:08.978824 RPST = 0x0
7170 13:12:08.978962 RD_PRE = 0x0
7171 13:12:08.982408 WR_PRE = 0x1
7172 13:12:08.985761 WR_PST = 0x1
7173 13:12:08.985896 DBI_WR = 0x0
7174 13:12:08.988620 DBI_RD = 0x0
7175 13:12:08.988752 OTF = 0x1
7176 13:12:08.991930 ===================================
7177 13:12:08.995111 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7178 13:12:09.001640 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7179 13:12:09.005056 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7180 13:12:09.008495 ===================================
7181 13:12:09.011705 LPDDR4 DRAM CONFIGURATION
7182 13:12:09.015007 ===================================
7183 13:12:09.015138 EX_ROW_EN[0] = 0x10
7184 13:12:09.018270 EX_ROW_EN[1] = 0x0
7185 13:12:09.018403 LP4Y_EN = 0x0
7186 13:12:09.021512 WORK_FSP = 0x1
7187 13:12:09.021661 WL = 0x5
7188 13:12:09.024881 RL = 0x5
7189 13:12:09.024998 BL = 0x2
7190 13:12:09.028429 RPST = 0x0
7191 13:12:09.031648 RD_PRE = 0x0
7192 13:12:09.031766 WR_PRE = 0x1
7193 13:12:09.035093 WR_PST = 0x1
7194 13:12:09.035208 DBI_WR = 0x0
7195 13:12:09.038511 DBI_RD = 0x0
7196 13:12:09.038630 OTF = 0x1
7197 13:12:09.041312 ===================================
7198 13:12:09.048054 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7199 13:12:09.048203 ==
7200 13:12:09.051504 Dram Type= 6, Freq= 0, CH_0, rank 0
7201 13:12:09.054906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7202 13:12:09.055036 ==
7203 13:12:09.058043 [Duty_Offset_Calibration]
7204 13:12:09.061314 B0:2 B1:0 CA:4
7205 13:12:09.061437
7206 13:12:09.064764 [DutyScan_Calibration_Flow] k_type=0
7207 13:12:09.072366
7208 13:12:09.072515 ==CLK 0==
7209 13:12:09.075117 Final CLK duty delay cell = -4
7210 13:12:09.078427 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7211 13:12:09.081676 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7212 13:12:09.085351 [-4] AVG Duty = 4937%(X100)
7213 13:12:09.085479
7214 13:12:09.088418 CH0 CLK Duty spec in!! Max-Min= 187%
7215 13:12:09.091887 [DutyScan_Calibration_Flow] ====Done====
7216 13:12:09.092027
7217 13:12:09.095329 [DutyScan_Calibration_Flow] k_type=1
7218 13:12:09.112308
7219 13:12:09.112543 ==DQS 0 ==
7220 13:12:09.115648 Final DQS duty delay cell = 0
7221 13:12:09.118739 [0] MAX Duty = 5218%(X100), DQS PI = 38
7222 13:12:09.122395 [0] MIN Duty = 5093%(X100), DQS PI = 6
7223 13:12:09.125404 [0] AVG Duty = 5155%(X100)
7224 13:12:09.125521
7225 13:12:09.125613 ==DQS 1 ==
7226 13:12:09.128904 Final DQS duty delay cell = 0
7227 13:12:09.132025 [0] MAX Duty = 5156%(X100), DQS PI = 0
7228 13:12:09.135380 [0] MIN Duty = 4969%(X100), DQS PI = 10
7229 13:12:09.138709 [0] AVG Duty = 5062%(X100)
7230 13:12:09.138886
7231 13:12:09.142181 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7232 13:12:09.142297
7233 13:12:09.145578 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7234 13:12:09.148656 [DutyScan_Calibration_Flow] ====Done====
7235 13:12:09.148780
7236 13:12:09.151637 [DutyScan_Calibration_Flow] k_type=3
7237 13:12:09.169330
7238 13:12:09.169482 ==DQM 0 ==
7239 13:12:09.172881 Final DQM duty delay cell = 0
7240 13:12:09.175902 [0] MAX Duty = 5124%(X100), DQS PI = 22
7241 13:12:09.179800 [0] MIN Duty = 4844%(X100), DQS PI = 56
7242 13:12:09.182372 [0] AVG Duty = 4984%(X100)
7243 13:12:09.182576
7244 13:12:09.182669 ==DQM 1 ==
7245 13:12:09.185913 Final DQM duty delay cell = 0
7246 13:12:09.189433 [0] MAX Duty = 4969%(X100), DQS PI = 0
7247 13:12:09.192238 [0] MIN Duty = 4813%(X100), DQS PI = 34
7248 13:12:09.196159 [0] AVG Duty = 4891%(X100)
7249 13:12:09.196285
7250 13:12:09.199112 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7251 13:12:09.199225
7252 13:12:09.202730 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7253 13:12:09.206037 [DutyScan_Calibration_Flow] ====Done====
7254 13:12:09.206157
7255 13:12:09.208582 [DutyScan_Calibration_Flow] k_type=2
7256 13:12:09.226819
7257 13:12:09.226969 ==DQ 0 ==
7258 13:12:09.229830 Final DQ duty delay cell = 0
7259 13:12:09.233246 [0] MAX Duty = 5156%(X100), DQS PI = 26
7260 13:12:09.236485 [0] MIN Duty = 4938%(X100), DQS PI = 12
7261 13:12:09.236617 [0] AVG Duty = 5047%(X100)
7262 13:12:09.239918
7263 13:12:09.240044 ==DQ 1 ==
7264 13:12:09.242926 Final DQ duty delay cell = 0
7265 13:12:09.246359 [0] MAX Duty = 5187%(X100), DQS PI = 2
7266 13:12:09.249886 [0] MIN Duty = 4907%(X100), DQS PI = 34
7267 13:12:09.250019 [0] AVG Duty = 5047%(X100)
7268 13:12:09.253005
7269 13:12:09.256274 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7270 13:12:09.256409
7271 13:12:09.259652 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7272 13:12:09.262508 [DutyScan_Calibration_Flow] ====Done====
7273 13:12:09.262631 ==
7274 13:12:09.266059 Dram Type= 6, Freq= 0, CH_1, rank 0
7275 13:12:09.269365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7276 13:12:09.269486 ==
7277 13:12:09.272948 [Duty_Offset_Calibration]
7278 13:12:09.273066 B0:0 B1:-1 CA:3
7279 13:12:09.273170
7280 13:12:09.276156 [DutyScan_Calibration_Flow] k_type=0
7281 13:12:09.286822
7282 13:12:09.286983 ==CLK 0==
7283 13:12:09.290002 Final CLK duty delay cell = 0
7284 13:12:09.293248 [0] MAX Duty = 5187%(X100), DQS PI = 26
7285 13:12:09.296477 [0] MIN Duty = 5031%(X100), DQS PI = 36
7286 13:12:09.299957 [0] AVG Duty = 5109%(X100)
7287 13:12:09.300092
7288 13:12:09.303615 CH1 CLK Duty spec in!! Max-Min= 156%
7289 13:12:09.306471 [DutyScan_Calibration_Flow] ====Done====
7290 13:12:09.306599
7291 13:12:09.310021 [DutyScan_Calibration_Flow] k_type=1
7292 13:12:09.325599
7293 13:12:09.325747 ==DQS 0 ==
7294 13:12:09.328915 Final DQS duty delay cell = 0
7295 13:12:09.332287 [0] MAX Duty = 5218%(X100), DQS PI = 28
7296 13:12:09.335901 [0] MIN Duty = 4907%(X100), DQS PI = 60
7297 13:12:09.338696 [0] AVG Duty = 5062%(X100)
7298 13:12:09.338819
7299 13:12:09.338914 ==DQS 1 ==
7300 13:12:09.342279 Final DQS duty delay cell = -4
7301 13:12:09.345519 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7302 13:12:09.348627 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7303 13:12:09.352099 [-4] AVG Duty = 4906%(X100)
7304 13:12:09.352230
7305 13:12:09.355622 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7306 13:12:09.355748
7307 13:12:09.358483 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7308 13:12:09.362054 [DutyScan_Calibration_Flow] ====Done====
7309 13:12:09.362195
7310 13:12:09.365262 [DutyScan_Calibration_Flow] k_type=3
7311 13:12:09.383172
7312 13:12:09.383333 ==DQM 0 ==
7313 13:12:09.385989 Final DQM duty delay cell = 0
7314 13:12:09.389385 [0] MAX Duty = 5031%(X100), DQS PI = 30
7315 13:12:09.392894 [0] MIN Duty = 4782%(X100), DQS PI = 40
7316 13:12:09.396269 [0] AVG Duty = 4906%(X100)
7317 13:12:09.396423
7318 13:12:09.396521 ==DQM 1 ==
7319 13:12:09.399175 Final DQM duty delay cell = 0
7320 13:12:09.402615 [0] MAX Duty = 4969%(X100), DQS PI = 30
7321 13:12:09.406374 [0] MIN Duty = 4813%(X100), DQS PI = 60
7322 13:12:09.409295 [0] AVG Duty = 4891%(X100)
7323 13:12:09.409428
7324 13:12:09.412584 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7325 13:12:09.412702
7326 13:12:09.415736 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7327 13:12:09.419424 [DutyScan_Calibration_Flow] ====Done====
7328 13:12:09.419566
7329 13:12:09.422527 [DutyScan_Calibration_Flow] k_type=2
7330 13:12:09.439235
7331 13:12:09.439396 ==DQ 0 ==
7332 13:12:09.442512 Final DQ duty delay cell = -4
7333 13:12:09.445923 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7334 13:12:09.449037 [-4] MIN Duty = 4813%(X100), DQS PI = 20
7335 13:12:09.452224 [-4] AVG Duty = 4891%(X100)
7336 13:12:09.452358
7337 13:12:09.452448 ==DQ 1 ==
7338 13:12:09.455668 Final DQ duty delay cell = 0
7339 13:12:09.459607 [0] MAX Duty = 5062%(X100), DQS PI = 32
7340 13:12:09.462531 [0] MIN Duty = 4875%(X100), DQS PI = 0
7341 13:12:09.465994 [0] AVG Duty = 4968%(X100)
7342 13:12:09.466125
7343 13:12:09.468929 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7344 13:12:09.469235
7345 13:12:09.472170 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7346 13:12:09.475295 [DutyScan_Calibration_Flow] ====Done====
7347 13:12:09.478734 nWR fixed to 30
7348 13:12:09.482075 [ModeRegInit_LP4] CH0 RK0
7349 13:12:09.482241 [ModeRegInit_LP4] CH0 RK1
7350 13:12:09.485448 [ModeRegInit_LP4] CH1 RK0
7351 13:12:09.488717 [ModeRegInit_LP4] CH1 RK1
7352 13:12:09.488845 match AC timing 5
7353 13:12:09.495463 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7354 13:12:09.498345 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7355 13:12:09.501890 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7356 13:12:09.508149 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7357 13:12:09.511693 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7358 13:12:09.514670 [MiockJmeterHQA]
7359 13:12:09.514897
7360 13:12:09.518690 [DramcMiockJmeter] u1RxGatingPI = 0
7361 13:12:09.518822 0 : 4253, 4026
7362 13:12:09.518924 4 : 4363, 4138
7363 13:12:09.521472 8 : 4254, 4029
7364 13:12:09.521601 12 : 4252, 4027
7365 13:12:09.524544 16 : 4253, 4027
7366 13:12:09.524677 20 : 4252, 4027
7367 13:12:09.528035 24 : 4252, 4027
7368 13:12:09.528155 28 : 4253, 4027
7369 13:12:09.528246 32 : 4252, 4027
7370 13:12:09.531088 36 : 4365, 4140
7371 13:12:09.531213 40 : 4252, 4027
7372 13:12:09.535027 44 : 4255, 4029
7373 13:12:09.535157 48 : 4252, 4027
7374 13:12:09.537906 52 : 4363, 4137
7375 13:12:09.538025 56 : 4253, 4027
7376 13:12:09.541084 60 : 4361, 4138
7377 13:12:09.541211 64 : 4250, 4027
7378 13:12:09.541309 68 : 4250, 4027
7379 13:12:09.544465 72 : 4250, 4026
7380 13:12:09.544587 76 : 4252, 4029
7381 13:12:09.547968 80 : 4250, 4027
7382 13:12:09.548102 84 : 4250, 4027
7383 13:12:09.551365 88 : 4363, 4140
7384 13:12:09.551490 92 : 4250, 4026
7385 13:12:09.554573 96 : 4252, 2611
7386 13:12:09.554689 100 : 4250, 0
7387 13:12:09.554786 104 : 4252, 0
7388 13:12:09.557593 108 : 4253, 0
7389 13:12:09.557718 112 : 4250, 0
7390 13:12:09.561218 116 : 4253, 0
7391 13:12:09.561345 120 : 4250, 0
7392 13:12:09.561440 124 : 4361, 0
7393 13:12:09.564395 128 : 4361, 0
7394 13:12:09.564515 132 : 4250, 0
7395 13:12:09.564609 136 : 4360, 0
7396 13:12:09.567384 140 : 4360, 0
7397 13:12:09.567503 144 : 4250, 0
7398 13:12:09.570609 148 : 4250, 0
7399 13:12:09.570736 152 : 4249, 0
7400 13:12:09.570842 156 : 4253, 0
7401 13:12:09.573901 160 : 4361, 0
7402 13:12:09.574029 164 : 4250, 0
7403 13:12:09.577641 168 : 4250, 0
7404 13:12:09.577772 172 : 4250, 0
7405 13:12:09.577876 176 : 4360, 0
7406 13:12:09.580827 180 : 4250, 0
7407 13:12:09.580944 184 : 4250, 0
7408 13:12:09.583844 188 : 4250, 0
7409 13:12:09.583992 192 : 4250, 0
7410 13:12:09.584097 196 : 4250, 0
7411 13:12:09.587242 200 : 4250, 0
7412 13:12:09.587382 204 : 4250, 0
7413 13:12:09.590383 208 : 4252, 0
7414 13:12:09.590528 212 : 4361, 0
7415 13:12:09.590627 216 : 4250, 0
7416 13:12:09.593962 220 : 4250, 971
7417 13:12:09.594100 224 : 4361, 4136
7418 13:12:09.597402 228 : 4361, 4138
7419 13:12:09.597530 232 : 4247, 4024
7420 13:12:09.600288 236 : 4363, 4140
7421 13:12:09.600412 240 : 4361, 4138
7422 13:12:09.603713 244 : 4250, 4027
7423 13:12:09.603845 248 : 4250, 4027
7424 13:12:09.606726 252 : 4252, 4030
7425 13:12:09.606849 256 : 4250, 4027
7426 13:12:09.610806 260 : 4250, 4026
7427 13:12:09.610940 264 : 4250, 4027
7428 13:12:09.611035 268 : 4252, 4029
7429 13:12:09.613918 272 : 4250, 4027
7430 13:12:09.614038 276 : 4360, 4138
7431 13:12:09.617254 280 : 4361, 4138
7432 13:12:09.617414 284 : 4250, 4027
7433 13:12:09.620016 288 : 4360, 4138
7434 13:12:09.620139 292 : 4361, 4138
7435 13:12:09.623635 296 : 4250, 4026
7436 13:12:09.623852 300 : 4250, 4027
7437 13:12:09.626615 304 : 4252, 4030
7438 13:12:09.626769 308 : 4250, 4027
7439 13:12:09.630011 312 : 4250, 4026
7440 13:12:09.630309 316 : 4250, 4027
7441 13:12:09.633383 320 : 4252, 4029
7442 13:12:09.633505 324 : 4250, 4027
7443 13:12:09.636958 328 : 4361, 4137
7444 13:12:09.637174 332 : 4361, 3911
7445 13:12:09.637419 336 : 4250, 1240
7446 13:12:09.640202
7447 13:12:09.640507 MIOCK jitter meter ch=0
7448 13:12:09.640800
7449 13:12:09.642947 1T = (336-100) = 236 dly cells
7450 13:12:09.649512 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7451 13:12:09.649665 ==
7452 13:12:09.653051 Dram Type= 6, Freq= 0, CH_0, rank 0
7453 13:12:09.656395 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7454 13:12:09.656529 ==
7455 13:12:09.662885 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7456 13:12:09.665981 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7457 13:12:09.669758 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7458 13:12:09.675995 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7459 13:12:09.685510 [CA 0] Center 43 (14~73) winsize 60
7460 13:12:09.689418 [CA 1] Center 43 (13~73) winsize 61
7461 13:12:09.692784 [CA 2] Center 38 (9~67) winsize 59
7462 13:12:09.695725 [CA 3] Center 37 (8~67) winsize 60
7463 13:12:09.698645 [CA 4] Center 36 (6~66) winsize 61
7464 13:12:09.702575 [CA 5] Center 35 (5~66) winsize 62
7465 13:12:09.702722
7466 13:12:09.705958 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7467 13:12:09.706093
7468 13:12:09.709344 [CATrainingPosCal] consider 1 rank data
7469 13:12:09.712109 u2DelayCellTimex100 = 275/100 ps
7470 13:12:09.718899 CA0 delay=43 (14~73),Diff = 8 PI (28 cell)
7471 13:12:09.722228 CA1 delay=43 (13~73),Diff = 8 PI (28 cell)
7472 13:12:09.725893 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7473 13:12:09.728753 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7474 13:12:09.731933 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7475 13:12:09.735558 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7476 13:12:09.735774
7477 13:12:09.738568 CA PerBit enable=1, Macro0, CA PI delay=35
7478 13:12:09.738716
7479 13:12:09.742068 [CBTSetCACLKResult] CA Dly = 35
7480 13:12:09.745425 CS Dly: 10 (0~41)
7481 13:12:09.749055 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7482 13:12:09.751930 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7483 13:12:09.752162 ==
7484 13:12:09.754948 Dram Type= 6, Freq= 0, CH_0, rank 1
7485 13:12:09.761364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7486 13:12:09.761623 ==
7487 13:12:09.764906 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7488 13:12:09.771485 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7489 13:12:09.774578 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7490 13:12:09.781408 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7491 13:12:09.789314 [CA 0] Center 44 (14~75) winsize 62
7492 13:12:09.792903 [CA 1] Center 44 (14~74) winsize 61
7493 13:12:09.796020 [CA 2] Center 39 (10~69) winsize 60
7494 13:12:09.799524 [CA 3] Center 39 (10~68) winsize 59
7495 13:12:09.802181 [CA 4] Center 37 (7~67) winsize 61
7496 13:12:09.805964 [CA 5] Center 36 (6~66) winsize 61
7497 13:12:09.806229
7498 13:12:09.809092 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7499 13:12:09.809307
7500 13:12:09.815494 [CATrainingPosCal] consider 2 rank data
7501 13:12:09.815761 u2DelayCellTimex100 = 275/100 ps
7502 13:12:09.822000 CA0 delay=43 (14~73),Diff = 7 PI (24 cell)
7503 13:12:09.825314 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7504 13:12:09.828758 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7505 13:12:09.832134 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7506 13:12:09.835033 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7507 13:12:09.838477 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7508 13:12:09.838690
7509 13:12:09.841937 CA PerBit enable=1, Macro0, CA PI delay=36
7510 13:12:09.845344
7511 13:12:09.845470 [CBTSetCACLKResult] CA Dly = 36
7512 13:12:09.848308 CS Dly: 11 (0~44)
7513 13:12:09.851614 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7514 13:12:09.855159 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7515 13:12:09.855281
7516 13:12:09.861453 ----->DramcWriteLeveling(PI) begin...
7517 13:12:09.861599 ==
7518 13:12:09.864686 Dram Type= 6, Freq= 0, CH_0, rank 0
7519 13:12:09.868293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7520 13:12:09.868429 ==
7521 13:12:09.871844 Write leveling (Byte 0): 35 => 35
7522 13:12:09.874563 Write leveling (Byte 1): 25 => 25
7523 13:12:09.878140 DramcWriteLeveling(PI) end<-----
7524 13:12:09.878262
7525 13:12:09.878350 ==
7526 13:12:09.881441 Dram Type= 6, Freq= 0, CH_0, rank 0
7527 13:12:09.884627 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7528 13:12:09.884755 ==
7529 13:12:09.887677 [Gating] SW mode calibration
7530 13:12:09.894388 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7531 13:12:09.901030 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7532 13:12:09.904197 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7533 13:12:09.907497 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7534 13:12:09.913923 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7535 13:12:09.917684 1 4 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
7536 13:12:09.920596 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7537 13:12:09.927407 1 4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
7538 13:12:09.930941 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7539 13:12:09.933705 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7540 13:12:09.940607 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7541 13:12:09.943949 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7542 13:12:09.947405 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
7543 13:12:09.953675 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
7544 13:12:09.957058 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7545 13:12:09.960296 1 5 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
7546 13:12:09.967205 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7547 13:12:09.970083 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7548 13:12:09.973720 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7549 13:12:09.979979 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7550 13:12:09.983624 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
7551 13:12:09.986765 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7552 13:12:09.993243 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7553 13:12:09.996594 1 6 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7554 13:12:10.000077 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7555 13:12:10.006528 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7556 13:12:10.010031 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7557 13:12:10.013360 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7558 13:12:10.019787 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7559 13:12:10.022941 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7560 13:12:10.026347 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7561 13:12:10.032874 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7562 13:12:10.036298 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7563 13:12:10.039534 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7564 13:12:10.045839 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7565 13:12:10.049308 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7566 13:12:10.052904 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7567 13:12:10.059032 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 13:12:10.062617 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 13:12:10.065869 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 13:12:10.072164 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 13:12:10.075933 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 13:12:10.079327 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 13:12:10.085622 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 13:12:10.088702 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7575 13:12:10.092617 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7576 13:12:10.095793 Total UI for P1: 0, mck2ui 16
7577 13:12:10.098943 best dqsien dly found for B0: ( 1, 9, 8)
7578 13:12:10.105646 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7579 13:12:10.108978 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7580 13:12:10.112277 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7581 13:12:10.118651 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 13:12:10.118780 Total UI for P1: 0, mck2ui 16
7583 13:12:10.125378 best dqsien dly found for B1: ( 1, 9, 22)
7584 13:12:10.128125 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7585 13:12:10.131591 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7586 13:12:10.131710
7587 13:12:10.134927 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7588 13:12:10.138237 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7589 13:12:10.141391 [Gating] SW calibration Done
7590 13:12:10.141510 ==
7591 13:12:10.145065 Dram Type= 6, Freq= 0, CH_0, rank 0
7592 13:12:10.148249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7593 13:12:10.148371 ==
7594 13:12:10.151764 RX Vref Scan: 0
7595 13:12:10.151884
7596 13:12:10.151974 RX Vref 0 -> 0, step: 1
7597 13:12:10.152060
7598 13:12:10.155167 RX Delay 0 -> 252, step: 8
7599 13:12:10.158464 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7600 13:12:10.164936 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7601 13:12:10.167906 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7602 13:12:10.171249 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7603 13:12:10.174605 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7604 13:12:10.178119 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7605 13:12:10.184364 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7606 13:12:10.187888 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7607 13:12:10.191372 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7608 13:12:10.194511 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7609 13:12:10.197625 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7610 13:12:10.204261 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7611 13:12:10.207776 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7612 13:12:10.211008 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7613 13:12:10.214570 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7614 13:12:10.220449 iDelay=192, Bit 15, Center 131 (80 ~ 183) 104
7615 13:12:10.220575 ==
7616 13:12:10.224009 Dram Type= 6, Freq= 0, CH_0, rank 0
7617 13:12:10.227306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7618 13:12:10.227418 ==
7619 13:12:10.227512 DQS Delay:
7620 13:12:10.230719 DQS0 = 0, DQS1 = 0
7621 13:12:10.230825 DQM Delay:
7622 13:12:10.233620 DQM0 = 131, DQM1 = 127
7623 13:12:10.233729 DQ Delay:
7624 13:12:10.237410 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7625 13:12:10.240393 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7626 13:12:10.243690 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
7627 13:12:10.246989 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =131
7628 13:12:10.250431
7629 13:12:10.250542
7630 13:12:10.250630 ==
7631 13:12:10.253433 Dram Type= 6, Freq= 0, CH_0, rank 0
7632 13:12:10.257165 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7633 13:12:10.257276 ==
7634 13:12:10.257364
7635 13:12:10.257450
7636 13:12:10.259916 TX Vref Scan disable
7637 13:12:10.260020 == TX Byte 0 ==
7638 13:12:10.266724 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7639 13:12:10.270122 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7640 13:12:10.270236 == TX Byte 1 ==
7641 13:12:10.277016 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7642 13:12:10.279915 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7643 13:12:10.280035 ==
7644 13:12:10.283315 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 13:12:10.286708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 13:12:10.286820 ==
7647 13:12:10.301474
7648 13:12:10.304843 TX Vref early break, caculate TX vref
7649 13:12:10.308039 TX Vref=16, minBit 1, minWin=22, winSum=367
7650 13:12:10.311618 TX Vref=18, minBit 1, minWin=23, winSum=377
7651 13:12:10.314983 TX Vref=20, minBit 7, minWin=23, winSum=392
7652 13:12:10.317846 TX Vref=22, minBit 1, minWin=24, winSum=399
7653 13:12:10.321216 TX Vref=24, minBit 1, minWin=25, winSum=410
7654 13:12:10.328109 TX Vref=26, minBit 1, minWin=25, winSum=416
7655 13:12:10.331027 TX Vref=28, minBit 1, minWin=25, winSum=415
7656 13:12:10.334404 TX Vref=30, minBit 4, minWin=24, winSum=411
7657 13:12:10.337946 TX Vref=32, minBit 1, minWin=24, winSum=406
7658 13:12:10.341308 TX Vref=34, minBit 7, minWin=23, winSum=392
7659 13:12:10.347576 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 26
7660 13:12:10.347722
7661 13:12:10.351243 Final TX Range 0 Vref 26
7662 13:12:10.351360
7663 13:12:10.351452 ==
7664 13:12:10.354263 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 13:12:10.357777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 13:12:10.357902 ==
7667 13:12:10.357997
7668 13:12:10.358509
7669 13:12:10.360854 TX Vref Scan disable
7670 13:12:10.367475 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7671 13:12:10.367625 == TX Byte 0 ==
7672 13:12:10.370409 u2DelayCellOfst[0]=14 cells (4 PI)
7673 13:12:10.373955 u2DelayCellOfst[1]=17 cells (5 PI)
7674 13:12:10.377045 u2DelayCellOfst[2]=10 cells (3 PI)
7675 13:12:10.380640 u2DelayCellOfst[3]=14 cells (4 PI)
7676 13:12:10.384208 u2DelayCellOfst[4]=10 cells (3 PI)
7677 13:12:10.386917 u2DelayCellOfst[5]=0 cells (0 PI)
7678 13:12:10.390826 u2DelayCellOfst[6]=17 cells (5 PI)
7679 13:12:10.393855 u2DelayCellOfst[7]=17 cells (5 PI)
7680 13:12:10.397188 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7681 13:12:10.400252 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7682 13:12:10.403369 == TX Byte 1 ==
7683 13:12:10.406739 u2DelayCellOfst[8]=0 cells (0 PI)
7684 13:12:10.410518 u2DelayCellOfst[9]=0 cells (0 PI)
7685 13:12:10.413662 u2DelayCellOfst[10]=3 cells (1 PI)
7686 13:12:10.413782 u2DelayCellOfst[11]=0 cells (0 PI)
7687 13:12:10.416961 u2DelayCellOfst[12]=7 cells (2 PI)
7688 13:12:10.420524 u2DelayCellOfst[13]=7 cells (2 PI)
7689 13:12:10.423572 u2DelayCellOfst[14]=14 cells (4 PI)
7690 13:12:10.427019 u2DelayCellOfst[15]=7 cells (2 PI)
7691 13:12:10.430035 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7692 13:12:10.437070 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7693 13:12:10.437212 DramC Write-DBI on
7694 13:12:10.437301 ==
7695 13:12:10.440292 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 13:12:10.446811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 13:12:10.446948 ==
7698 13:12:10.447125
7699 13:12:10.447221
7700 13:12:10.447305 TX Vref Scan disable
7701 13:12:10.450748 == TX Byte 0 ==
7702 13:12:10.454129 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7703 13:12:10.457000 == TX Byte 1 ==
7704 13:12:10.460321 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7705 13:12:10.463724 DramC Write-DBI off
7706 13:12:10.463846
7707 13:12:10.463936 [DATLAT]
7708 13:12:10.464021 Freq=1600, CH0 RK0
7709 13:12:10.464110
7710 13:12:10.467173 DATLAT Default: 0xf
7711 13:12:10.470610 0, 0xFFFF, sum = 0
7712 13:12:10.470739 1, 0xFFFF, sum = 0
7713 13:12:10.473960 2, 0xFFFF, sum = 0
7714 13:12:10.474078 3, 0xFFFF, sum = 0
7715 13:12:10.476972 4, 0xFFFF, sum = 0
7716 13:12:10.477155 5, 0xFFFF, sum = 0
7717 13:12:10.480179 6, 0xFFFF, sum = 0
7718 13:12:10.480304 7, 0xFFFF, sum = 0
7719 13:12:10.483619 8, 0xFFFF, sum = 0
7720 13:12:10.483736 9, 0xFFFF, sum = 0
7721 13:12:10.486890 10, 0xFFFF, sum = 0
7722 13:12:10.487007 11, 0xFFFF, sum = 0
7723 13:12:10.489965 12, 0xFFFF, sum = 0
7724 13:12:10.490083 13, 0xFFFF, sum = 0
7725 13:12:10.493331 14, 0x0, sum = 1
7726 13:12:10.493445 15, 0x0, sum = 2
7727 13:12:10.496688 16, 0x0, sum = 3
7728 13:12:10.496808 17, 0x0, sum = 4
7729 13:12:10.500760 best_step = 15
7730 13:12:10.500884
7731 13:12:10.500979 ==
7732 13:12:10.503312 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 13:12:10.506680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 13:12:10.506819 ==
7735 13:12:10.510561 RX Vref Scan: 1
7736 13:12:10.510684
7737 13:12:10.510781 Set Vref Range= 24 -> 127
7738 13:12:10.510871
7739 13:12:10.513467 RX Vref 24 -> 127, step: 1
7740 13:12:10.513575
7741 13:12:10.516937 RX Delay 19 -> 252, step: 4
7742 13:12:10.517057
7743 13:12:10.519759 Set Vref, RX VrefLevel [Byte0]: 24
7744 13:12:10.523072 [Byte1]: 24
7745 13:12:10.523193
7746 13:12:10.526764 Set Vref, RX VrefLevel [Byte0]: 25
7747 13:12:10.529863 [Byte1]: 25
7748 13:12:10.533288
7749 13:12:10.533420 Set Vref, RX VrefLevel [Byte0]: 26
7750 13:12:10.536579 [Byte1]: 26
7751 13:12:10.541214
7752 13:12:10.541332 Set Vref, RX VrefLevel [Byte0]: 27
7753 13:12:10.543944 [Byte1]: 27
7754 13:12:10.548638
7755 13:12:10.548751 Set Vref, RX VrefLevel [Byte0]: 28
7756 13:12:10.551658 [Byte1]: 28
7757 13:12:10.556265
7758 13:12:10.556384 Set Vref, RX VrefLevel [Byte0]: 29
7759 13:12:10.559591 [Byte1]: 29
7760 13:12:10.563437
7761 13:12:10.563569 Set Vref, RX VrefLevel [Byte0]: 30
7762 13:12:10.567267 [Byte1]: 30
7763 13:12:10.571147
7764 13:12:10.571265 Set Vref, RX VrefLevel [Byte0]: 31
7765 13:12:10.574307 [Byte1]: 31
7766 13:12:10.578616
7767 13:12:10.578727 Set Vref, RX VrefLevel [Byte0]: 32
7768 13:12:10.581908 [Byte1]: 32
7769 13:12:10.586294
7770 13:12:10.586414 Set Vref, RX VrefLevel [Byte0]: 33
7771 13:12:10.589420 [Byte1]: 33
7772 13:12:10.593932
7773 13:12:10.594055 Set Vref, RX VrefLevel [Byte0]: 34
7774 13:12:10.597259 [Byte1]: 34
7775 13:12:10.601490
7776 13:12:10.601606 Set Vref, RX VrefLevel [Byte0]: 35
7777 13:12:10.604788 [Byte1]: 35
7778 13:12:10.609383
7779 13:12:10.609495 Set Vref, RX VrefLevel [Byte0]: 36
7780 13:12:10.612321 [Byte1]: 36
7781 13:12:10.616696
7782 13:12:10.616810 Set Vref, RX VrefLevel [Byte0]: 37
7783 13:12:10.620026 [Byte1]: 37
7784 13:12:10.624240
7785 13:12:10.624354 Set Vref, RX VrefLevel [Byte0]: 38
7786 13:12:10.627830 [Byte1]: 38
7787 13:12:10.631596
7788 13:12:10.631710 Set Vref, RX VrefLevel [Byte0]: 39
7789 13:12:10.635169 [Byte1]: 39
7790 13:12:10.639511
7791 13:12:10.639631 Set Vref, RX VrefLevel [Byte0]: 40
7792 13:12:10.642458 [Byte1]: 40
7793 13:12:10.647319
7794 13:12:10.647516 Set Vref, RX VrefLevel [Byte0]: 41
7795 13:12:10.650341 [Byte1]: 41
7796 13:12:10.654390
7797 13:12:10.654503 Set Vref, RX VrefLevel [Byte0]: 42
7798 13:12:10.657732 [Byte1]: 42
7799 13:12:10.662446
7800 13:12:10.662557 Set Vref, RX VrefLevel [Byte0]: 43
7801 13:12:10.665421 [Byte1]: 43
7802 13:12:10.669386
7803 13:12:10.669494 Set Vref, RX VrefLevel [Byte0]: 44
7804 13:12:10.672976 [Byte1]: 44
7805 13:12:10.677402
7806 13:12:10.677513 Set Vref, RX VrefLevel [Byte0]: 45
7807 13:12:10.680346 [Byte1]: 45
7808 13:12:10.684942
7809 13:12:10.685149 Set Vref, RX VrefLevel [Byte0]: 46
7810 13:12:10.688150 [Byte1]: 46
7811 13:12:10.692719
7812 13:12:10.692835 Set Vref, RX VrefLevel [Byte0]: 47
7813 13:12:10.695998 [Byte1]: 47
7814 13:12:10.699947
7815 13:12:10.700055 Set Vref, RX VrefLevel [Byte0]: 48
7816 13:12:10.703241 [Byte1]: 48
7817 13:12:10.707352
7818 13:12:10.707470 Set Vref, RX VrefLevel [Byte0]: 49
7819 13:12:10.711322 [Byte1]: 49
7820 13:12:10.714983
7821 13:12:10.715095 Set Vref, RX VrefLevel [Byte0]: 50
7822 13:12:10.718571 [Byte1]: 50
7823 13:12:10.722537
7824 13:12:10.722648 Set Vref, RX VrefLevel [Byte0]: 51
7825 13:12:10.725941 [Byte1]: 51
7826 13:12:10.730260
7827 13:12:10.730369 Set Vref, RX VrefLevel [Byte0]: 52
7828 13:12:10.733435 [Byte1]: 52
7829 13:12:10.737618
7830 13:12:10.737765 Set Vref, RX VrefLevel [Byte0]: 53
7831 13:12:10.741539 [Byte1]: 53
7832 13:12:10.745331
7833 13:12:10.745442 Set Vref, RX VrefLevel [Byte0]: 54
7834 13:12:10.748468 [Byte1]: 54
7835 13:12:10.753057
7836 13:12:10.753174 Set Vref, RX VrefLevel [Byte0]: 55
7837 13:12:10.756412 [Byte1]: 55
7838 13:12:10.760390
7839 13:12:10.760505 Set Vref, RX VrefLevel [Byte0]: 56
7840 13:12:10.764087 [Byte1]: 56
7841 13:12:10.767994
7842 13:12:10.768104 Set Vref, RX VrefLevel [Byte0]: 57
7843 13:12:10.771501 [Byte1]: 57
7844 13:12:10.775449
7845 13:12:10.775558 Set Vref, RX VrefLevel [Byte0]: 58
7846 13:12:10.778724 [Byte1]: 58
7847 13:12:10.783305
7848 13:12:10.783415 Set Vref, RX VrefLevel [Byte0]: 59
7849 13:12:10.786637 [Byte1]: 59
7850 13:12:10.790883
7851 13:12:10.790996 Set Vref, RX VrefLevel [Byte0]: 60
7852 13:12:10.794344 [Byte1]: 60
7853 13:12:10.798721
7854 13:12:10.798835 Set Vref, RX VrefLevel [Byte0]: 61
7855 13:12:10.801628 [Byte1]: 61
7856 13:12:10.806026
7857 13:12:10.806142 Set Vref, RX VrefLevel [Byte0]: 62
7858 13:12:10.809254 [Byte1]: 62
7859 13:12:10.813556
7860 13:12:10.813668 Set Vref, RX VrefLevel [Byte0]: 63
7861 13:12:10.816829 [Byte1]: 63
7862 13:12:10.821107
7863 13:12:10.821252 Set Vref, RX VrefLevel [Byte0]: 64
7864 13:12:10.824738 [Byte1]: 64
7865 13:12:10.828775
7866 13:12:10.828892 Set Vref, RX VrefLevel [Byte0]: 65
7867 13:12:10.832130 [Byte1]: 65
7868 13:12:10.836278
7869 13:12:10.836391 Set Vref, RX VrefLevel [Byte0]: 66
7870 13:12:10.839754 [Byte1]: 66
7871 13:12:10.843652
7872 13:12:10.843765 Set Vref, RX VrefLevel [Byte0]: 67
7873 13:12:10.847203 [Byte1]: 67
7874 13:12:10.851729
7875 13:12:10.851844 Set Vref, RX VrefLevel [Byte0]: 68
7876 13:12:10.854653 [Byte1]: 68
7877 13:12:10.859438
7878 13:12:10.859554 Set Vref, RX VrefLevel [Byte0]: 69
7879 13:12:10.862159 [Byte1]: 69
7880 13:12:10.866811
7881 13:12:10.866938 Set Vref, RX VrefLevel [Byte0]: 70
7882 13:12:10.869686 [Byte1]: 70
7883 13:12:10.874383
7884 13:12:10.874499 Set Vref, RX VrefLevel [Byte0]: 71
7885 13:12:10.877243 [Byte1]: 71
7886 13:12:10.881837
7887 13:12:10.881949 Set Vref, RX VrefLevel [Byte0]: 72
7888 13:12:10.885300 [Byte1]: 72
7889 13:12:10.889261
7890 13:12:10.889368 Set Vref, RX VrefLevel [Byte0]: 73
7891 13:12:10.892363 [Byte1]: 73
7892 13:12:10.896867
7893 13:12:10.896976 Set Vref, RX VrefLevel [Byte0]: 74
7894 13:12:10.900403 [Byte1]: 74
7895 13:12:10.904714
7896 13:12:10.904828 Set Vref, RX VrefLevel [Byte0]: 75
7897 13:12:10.907494 [Byte1]: 75
7898 13:12:10.911905
7899 13:12:10.912016 Final RX Vref Byte 0 = 55 to rank0
7900 13:12:10.915354 Final RX Vref Byte 1 = 58 to rank0
7901 13:12:10.918338 Final RX Vref Byte 0 = 55 to rank1
7902 13:12:10.921569 Final RX Vref Byte 1 = 58 to rank1==
7903 13:12:10.925358 Dram Type= 6, Freq= 0, CH_0, rank 0
7904 13:12:10.932093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7905 13:12:10.932290 ==
7906 13:12:10.932390 DQS Delay:
7907 13:12:10.934990 DQS0 = 0, DQS1 = 0
7908 13:12:10.935100 DQM Delay:
7909 13:12:10.935189 DQM0 = 129, DQM1 = 124
7910 13:12:10.938545 DQ Delay:
7911 13:12:10.941961 DQ0 =130, DQ1 =130, DQ2 =128, DQ3 =124
7912 13:12:10.944818 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =134
7913 13:12:10.948143 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7914 13:12:10.951405 DQ12 =130, DQ13 =130, DQ14 =132, DQ15 =130
7915 13:12:10.951514
7916 13:12:10.951603
7917 13:12:10.951687
7918 13:12:10.954423 [DramC_TX_OE_Calibration] TA2
7919 13:12:10.957956 Original DQ_B0 (3 6) =30, OEN = 27
7920 13:12:10.961544 Original DQ_B1 (3 6) =30, OEN = 27
7921 13:12:10.964899 24, 0x0, End_B0=24 End_B1=24
7922 13:12:10.968447 25, 0x0, End_B0=25 End_B1=25
7923 13:12:10.968560 26, 0x0, End_B0=26 End_B1=26
7924 13:12:10.971060 27, 0x0, End_B0=27 End_B1=27
7925 13:12:10.974979 28, 0x0, End_B0=28 End_B1=28
7926 13:12:10.978148 29, 0x0, End_B0=29 End_B1=29
7927 13:12:10.978256 30, 0x0, End_B0=30 End_B1=30
7928 13:12:10.981183 31, 0x5151, End_B0=30 End_B1=30
7929 13:12:10.984372 Byte0 end_step=30 best_step=27
7930 13:12:10.988121 Byte1 end_step=30 best_step=27
7931 13:12:10.990787 Byte0 TX OE(2T, 0.5T) = (3, 3)
7932 13:12:10.994236 Byte1 TX OE(2T, 0.5T) = (3, 3)
7933 13:12:10.994348
7934 13:12:10.994437
7935 13:12:11.001117 [DQSOSCAuto] RK0, (LSB)MR18= 0x1916, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
7936 13:12:11.003920 CH0 RK0: MR19=303, MR18=1916
7937 13:12:11.010995 CH0_RK0: MR19=0x303, MR18=0x1916, DQSOSC=397, MR23=63, INC=23, DEC=15
7938 13:12:11.011384
7939 13:12:11.014318 ----->DramcWriteLeveling(PI) begin...
7940 13:12:11.014423 ==
7941 13:12:11.017248 Dram Type= 6, Freq= 0, CH_0, rank 1
7942 13:12:11.020532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7943 13:12:11.020643 ==
7944 13:12:11.023920 Write leveling (Byte 0): 37 => 37
7945 13:12:11.027483 Write leveling (Byte 1): 26 => 26
7946 13:12:11.030590 DramcWriteLeveling(PI) end<-----
7947 13:12:11.030703
7948 13:12:11.030795 ==
7949 13:12:11.033414 Dram Type= 6, Freq= 0, CH_0, rank 1
7950 13:12:11.040360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7951 13:12:11.040492 ==
7952 13:12:11.040589 [Gating] SW mode calibration
7953 13:12:11.050085 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7954 13:12:11.053321 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7955 13:12:11.060257 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7956 13:12:11.063365 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7957 13:12:11.066679 1 4 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
7958 13:12:11.073129 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7959 13:12:11.076579 1 4 16 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
7960 13:12:11.080256 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7961 13:12:11.086491 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7962 13:12:11.089733 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7963 13:12:11.092839 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7964 13:12:11.099693 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7965 13:12:11.102864 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
7966 13:12:11.106368 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
7967 13:12:11.112748 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7968 13:12:11.116173 1 5 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7969 13:12:11.119463 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7970 13:12:11.125828 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7971 13:12:11.129313 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7972 13:12:11.132628 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7973 13:12:11.139331 1 6 8 | B1->B0 | 2323 3e3e | 0 1 | (0 0) (0 0)
7974 13:12:11.142318 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7975 13:12:11.145769 1 6 16 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
7976 13:12:11.152685 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7977 13:12:11.155783 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7978 13:12:11.158759 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7979 13:12:11.165797 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7980 13:12:11.168676 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7981 13:12:11.171819 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7982 13:12:11.179050 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7983 13:12:11.181786 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7984 13:12:11.185081 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7985 13:12:11.191558 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 13:12:11.194809 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 13:12:11.198144 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 13:12:11.204800 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 13:12:11.208039 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 13:12:11.211435 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 13:12:11.218396 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 13:12:11.221741 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 13:12:11.224544 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 13:12:11.231364 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 13:12:11.234708 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7996 13:12:11.237549 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7997 13:12:11.244276 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7998 13:12:11.247634 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7999 13:12:11.250674 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8000 13:12:11.254071 Total UI for P1: 0, mck2ui 16
8001 13:12:11.257270 best dqsien dly found for B0: ( 1, 9, 6)
8002 13:12:11.264232 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8003 13:12:11.267849 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8004 13:12:11.270663 Total UI for P1: 0, mck2ui 16
8005 13:12:11.274499 best dqsien dly found for B1: ( 1, 9, 18)
8006 13:12:11.277211 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8007 13:12:11.281097 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8008 13:12:11.281242
8009 13:12:11.283768 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8010 13:12:11.287126 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8011 13:12:11.290539 [Gating] SW calibration Done
8012 13:12:11.290676 ==
8013 13:12:11.294028 Dram Type= 6, Freq= 0, CH_0, rank 1
8014 13:12:11.297065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8015 13:12:11.300345 ==
8016 13:12:11.300472 RX Vref Scan: 0
8017 13:12:11.300566
8018 13:12:11.303834 RX Vref 0 -> 0, step: 1
8019 13:12:11.303992
8020 13:12:11.307538 RX Delay 0 -> 252, step: 8
8021 13:12:11.310178 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
8022 13:12:11.313699 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
8023 13:12:11.317159 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
8024 13:12:11.320647 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
8025 13:12:11.326908 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
8026 13:12:11.330225 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
8027 13:12:11.333715 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
8028 13:12:11.336656 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
8029 13:12:11.339885 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
8030 13:12:11.346263 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
8031 13:12:11.350056 iDelay=192, Bit 10, Center 127 (72 ~ 183) 112
8032 13:12:11.353006 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
8033 13:12:11.356404 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
8034 13:12:11.359769 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
8035 13:12:11.366591 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
8036 13:12:11.369420 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
8037 13:12:11.369555 ==
8038 13:12:11.372895 Dram Type= 6, Freq= 0, CH_0, rank 1
8039 13:12:11.376282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8040 13:12:11.376418 ==
8041 13:12:11.379355 DQS Delay:
8042 13:12:11.379475 DQS0 = 0, DQS1 = 0
8043 13:12:11.382572 DQM Delay:
8044 13:12:11.382692 DQM0 = 130, DQM1 = 126
8045 13:12:11.382784 DQ Delay:
8046 13:12:11.386395 DQ0 =127, DQ1 =135, DQ2 =127, DQ3 =127
8047 13:12:11.392555 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
8048 13:12:11.395550 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
8049 13:12:11.399288 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8050 13:12:11.399425
8051 13:12:11.399519
8052 13:12:11.399623 ==
8053 13:12:11.402515 Dram Type= 6, Freq= 0, CH_0, rank 1
8054 13:12:11.405872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8055 13:12:11.406000 ==
8056 13:12:11.406092
8057 13:12:11.406177
8058 13:12:11.409233 TX Vref Scan disable
8059 13:12:11.412768 == TX Byte 0 ==
8060 13:12:11.416002 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8061 13:12:11.419153 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8062 13:12:11.422833 == TX Byte 1 ==
8063 13:12:11.425774 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8064 13:12:11.428613 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8065 13:12:11.428738 ==
8066 13:12:11.432148 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 13:12:11.438893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 13:12:11.439055 ==
8069 13:12:11.452777
8070 13:12:11.455684 TX Vref early break, caculate TX vref
8071 13:12:11.459323 TX Vref=16, minBit 9, minWin=22, winSum=381
8072 13:12:11.462647 TX Vref=18, minBit 8, minWin=23, winSum=388
8073 13:12:11.465923 TX Vref=20, minBit 8, minWin=24, winSum=395
8074 13:12:11.469201 TX Vref=22, minBit 1, minWin=25, winSum=407
8075 13:12:11.472600 TX Vref=24, minBit 4, minWin=25, winSum=415
8076 13:12:11.479060 TX Vref=26, minBit 1, minWin=25, winSum=418
8077 13:12:11.482311 TX Vref=28, minBit 0, minWin=26, winSum=419
8078 13:12:11.485516 TX Vref=30, minBit 4, minWin=25, winSum=418
8079 13:12:11.489344 TX Vref=32, minBit 8, minWin=24, winSum=405
8080 13:12:11.492807 TX Vref=34, minBit 1, minWin=24, winSum=400
8081 13:12:11.499070 TX Vref=36, minBit 0, minWin=24, winSum=389
8082 13:12:11.502276 [TxChooseVref] Worse bit 0, Min win 26, Win sum 419, Final Vref 28
8083 13:12:11.502409
8084 13:12:11.505643 Final TX Range 0 Vref 28
8085 13:12:11.505766
8086 13:12:11.505861 ==
8087 13:12:11.508824 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 13:12:11.511990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 13:12:11.512116 ==
8090 13:12:11.515304
8091 13:12:11.515428
8092 13:12:11.515525 TX Vref Scan disable
8093 13:12:11.521742 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8094 13:12:11.521890 == TX Byte 0 ==
8095 13:12:11.525177 u2DelayCellOfst[0]=14 cells (4 PI)
8096 13:12:11.528481 u2DelayCellOfst[1]=17 cells (5 PI)
8097 13:12:11.531716 u2DelayCellOfst[2]=10 cells (3 PI)
8098 13:12:11.535257 u2DelayCellOfst[3]=14 cells (4 PI)
8099 13:12:11.538651 u2DelayCellOfst[4]=10 cells (3 PI)
8100 13:12:11.541843 u2DelayCellOfst[5]=0 cells (0 PI)
8101 13:12:11.544776 u2DelayCellOfst[6]=17 cells (5 PI)
8102 13:12:11.548300 u2DelayCellOfst[7]=17 cells (5 PI)
8103 13:12:11.551639 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8104 13:12:11.558161 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8105 13:12:11.558371 == TX Byte 1 ==
8106 13:12:11.561686 u2DelayCellOfst[8]=0 cells (0 PI)
8107 13:12:11.564819 u2DelayCellOfst[9]=0 cells (0 PI)
8108 13:12:11.567708 u2DelayCellOfst[10]=3 cells (1 PI)
8109 13:12:11.571534 u2DelayCellOfst[11]=0 cells (0 PI)
8110 13:12:11.574476 u2DelayCellOfst[12]=7 cells (2 PI)
8111 13:12:11.578119 u2DelayCellOfst[13]=7 cells (2 PI)
8112 13:12:11.580997 u2DelayCellOfst[14]=14 cells (4 PI)
8113 13:12:11.584341 u2DelayCellOfst[15]=14 cells (4 PI)
8114 13:12:11.587807 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8115 13:12:11.591333 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8116 13:12:11.594081 DramC Write-DBI on
8117 13:12:11.594215 ==
8118 13:12:11.597521 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 13:12:11.600891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 13:12:11.601021 ==
8121 13:12:11.601111
8122 13:12:11.601205
8123 13:12:11.603955 TX Vref Scan disable
8124 13:12:11.607558 == TX Byte 0 ==
8125 13:12:11.611007 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8126 13:12:11.611151 == TX Byte 1 ==
8127 13:12:11.617493 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8128 13:12:11.617677 DramC Write-DBI off
8129 13:12:11.617777
8130 13:12:11.617888 [DATLAT]
8131 13:12:11.621185 Freq=1600, CH0 RK1
8132 13:12:11.621342
8133 13:12:11.623857 DATLAT Default: 0xf
8134 13:12:11.624091 0, 0xFFFF, sum = 0
8135 13:12:11.627071 1, 0xFFFF, sum = 0
8136 13:12:11.627211 2, 0xFFFF, sum = 0
8137 13:12:11.630352 3, 0xFFFF, sum = 0
8138 13:12:11.630505 4, 0xFFFF, sum = 0
8139 13:12:11.633698 5, 0xFFFF, sum = 0
8140 13:12:11.633846 6, 0xFFFF, sum = 0
8141 13:12:11.637284 7, 0xFFFF, sum = 0
8142 13:12:11.637448 8, 0xFFFF, sum = 0
8143 13:12:11.640998 9, 0xFFFF, sum = 0
8144 13:12:11.641178 10, 0xFFFF, sum = 0
8145 13:12:11.643468 11, 0xFFFF, sum = 0
8146 13:12:11.643622 12, 0xFFFF, sum = 0
8147 13:12:11.646930 13, 0xFFFF, sum = 0
8148 13:12:11.647057 14, 0x0, sum = 1
8149 13:12:11.649910 15, 0x0, sum = 2
8150 13:12:11.650032 16, 0x0, sum = 3
8151 13:12:11.653479 17, 0x0, sum = 4
8152 13:12:11.653600 best_step = 15
8153 13:12:11.653692
8154 13:12:11.653779 ==
8155 13:12:11.656916 Dram Type= 6, Freq= 0, CH_0, rank 1
8156 13:12:11.663381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8157 13:12:11.663579 ==
8158 13:12:11.663721 RX Vref Scan: 0
8159 13:12:11.663852
8160 13:12:11.666970 RX Vref 0 -> 0, step: 1
8161 13:12:11.667089
8162 13:12:11.670377 RX Delay 11 -> 252, step: 4
8163 13:12:11.673361 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8164 13:12:11.676563 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8165 13:12:11.683211 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8166 13:12:11.686482 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8167 13:12:11.689517 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8168 13:12:11.693268 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8169 13:12:11.696519 iDelay=191, Bit 6, Center 136 (87 ~ 186) 100
8170 13:12:11.703437 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8171 13:12:11.706547 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8172 13:12:11.709312 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8173 13:12:11.713249 iDelay=191, Bit 10, Center 124 (71 ~ 178) 108
8174 13:12:11.716338 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8175 13:12:11.723212 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8176 13:12:11.725827 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8177 13:12:11.729362 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8178 13:12:11.732454 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8179 13:12:11.735714 ==
8180 13:12:11.735874 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 13:12:11.742216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 13:12:11.742375 ==
8183 13:12:11.742469 DQS Delay:
8184 13:12:11.745573 DQS0 = 0, DQS1 = 0
8185 13:12:11.745711 DQM Delay:
8186 13:12:11.749004 DQM0 = 128, DQM1 = 123
8187 13:12:11.749120 DQ Delay:
8188 13:12:11.752460 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8189 13:12:11.755454 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
8190 13:12:11.759014 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
8191 13:12:11.762619 DQ12 =128, DQ13 =130, DQ14 =134, DQ15 =132
8192 13:12:11.762770
8193 13:12:11.762869
8194 13:12:11.762955
8195 13:12:11.765422 [DramC_TX_OE_Calibration] TA2
8196 13:12:11.768915 Original DQ_B0 (3 6) =30, OEN = 27
8197 13:12:11.771892 Original DQ_B1 (3 6) =30, OEN = 27
8198 13:12:11.775352 24, 0x0, End_B0=24 End_B1=24
8199 13:12:11.778544 25, 0x0, End_B0=25 End_B1=25
8200 13:12:11.778686 26, 0x0, End_B0=26 End_B1=26
8201 13:12:11.782108 27, 0x0, End_B0=27 End_B1=27
8202 13:12:11.785454 28, 0x0, End_B0=28 End_B1=28
8203 13:12:11.788462 29, 0x0, End_B0=29 End_B1=29
8204 13:12:11.791869 30, 0x0, End_B0=30 End_B1=30
8205 13:12:11.792015 31, 0x4141, End_B0=30 End_B1=30
8206 13:12:11.795420 Byte0 end_step=30 best_step=27
8207 13:12:11.798432 Byte1 end_step=30 best_step=27
8208 13:12:11.801624 Byte0 TX OE(2T, 0.5T) = (3, 3)
8209 13:12:11.805122 Byte1 TX OE(2T, 0.5T) = (3, 3)
8210 13:12:11.805323
8211 13:12:11.805417
8212 13:12:11.811670 [DQSOSCAuto] RK1, (LSB)MR18= 0x1512, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8213 13:12:11.814565 CH0 RK1: MR19=303, MR18=1512
8214 13:12:11.821342 CH0_RK1: MR19=0x303, MR18=0x1512, DQSOSC=399, MR23=63, INC=23, DEC=15
8215 13:12:11.825043 [RxdqsGatingPostProcess] freq 1600
8216 13:12:11.831138 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8217 13:12:11.834319 best DQS0 dly(2T, 0.5T) = (1, 1)
8218 13:12:11.837659 best DQS1 dly(2T, 0.5T) = (1, 1)
8219 13:12:11.837823 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8220 13:12:11.841409 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8221 13:12:11.844557 best DQS0 dly(2T, 0.5T) = (1, 1)
8222 13:12:11.847896 best DQS1 dly(2T, 0.5T) = (1, 1)
8223 13:12:11.850854 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8224 13:12:11.854250 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8225 13:12:11.857556 Pre-setting of DQS Precalculation
8226 13:12:11.864040 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8227 13:12:11.864207 ==
8228 13:12:11.867567 Dram Type= 6, Freq= 0, CH_1, rank 0
8229 13:12:11.870766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8230 13:12:11.870886 ==
8231 13:12:11.877344 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8232 13:12:11.880982 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8233 13:12:11.884145 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8234 13:12:11.890765 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8235 13:12:11.899118 [CA 0] Center 42 (12~72) winsize 61
8236 13:12:11.902634 [CA 1] Center 42 (13~72) winsize 60
8237 13:12:11.905695 [CA 2] Center 38 (9~68) winsize 60
8238 13:12:11.909377 [CA 3] Center 37 (8~66) winsize 59
8239 13:12:11.912285 [CA 4] Center 38 (8~68) winsize 61
8240 13:12:11.915789 [CA 5] Center 36 (7~66) winsize 60
8241 13:12:11.915922
8242 13:12:11.919167 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8243 13:12:11.919307
8244 13:12:11.925394 [CATrainingPosCal] consider 1 rank data
8245 13:12:11.925554 u2DelayCellTimex100 = 275/100 ps
8246 13:12:11.932314 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8247 13:12:11.935504 CA1 delay=42 (13~72),Diff = 6 PI (21 cell)
8248 13:12:11.938706 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
8249 13:12:11.941744 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8250 13:12:11.945459 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8251 13:12:11.949123 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8252 13:12:11.949272
8253 13:12:11.951833 CA PerBit enable=1, Macro0, CA PI delay=36
8254 13:12:11.951949
8255 13:12:11.954853 [CBTSetCACLKResult] CA Dly = 36
8256 13:12:11.958501 CS Dly: 8 (0~39)
8257 13:12:11.961753 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8258 13:12:11.965009 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8259 13:12:11.965176 ==
8260 13:12:11.968026 Dram Type= 6, Freq= 0, CH_1, rank 1
8261 13:12:11.974969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8262 13:12:11.975119 ==
8263 13:12:11.977936 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8264 13:12:11.984612 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8265 13:12:11.987714 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8266 13:12:11.994507 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8267 13:12:12.002312 [CA 0] Center 42 (12~72) winsize 61
8268 13:12:12.005713 [CA 1] Center 43 (13~73) winsize 61
8269 13:12:12.009379 [CA 2] Center 38 (9~68) winsize 60
8270 13:12:12.012548 [CA 3] Center 37 (8~67) winsize 60
8271 13:12:12.015522 [CA 4] Center 38 (8~68) winsize 61
8272 13:12:12.019031 [CA 5] Center 37 (7~67) winsize 61
8273 13:12:12.019195
8274 13:12:12.022105 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8275 13:12:12.022262
8276 13:12:12.025822 [CATrainingPosCal] consider 2 rank data
8277 13:12:12.028899 u2DelayCellTimex100 = 275/100 ps
8278 13:12:12.035331 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8279 13:12:12.038749 CA1 delay=42 (13~72),Diff = 6 PI (21 cell)
8280 13:12:12.042243 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
8281 13:12:12.045060 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8282 13:12:12.048633 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8283 13:12:12.051755 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8284 13:12:12.051888
8285 13:12:12.054960 CA PerBit enable=1, Macro0, CA PI delay=36
8286 13:12:12.055090
8287 13:12:12.058636 [CBTSetCACLKResult] CA Dly = 36
8288 13:12:12.062057 CS Dly: 10 (0~43)
8289 13:12:12.064914 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8290 13:12:12.068488 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8291 13:12:12.068662
8292 13:12:12.071672 ----->DramcWriteLeveling(PI) begin...
8293 13:12:12.071804 ==
8294 13:12:12.074707 Dram Type= 6, Freq= 0, CH_1, rank 0
8295 13:12:12.081303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8296 13:12:12.081460 ==
8297 13:12:12.084920 Write leveling (Byte 0): 23 => 23
8298 13:12:12.087937 Write leveling (Byte 1): 25 => 25
8299 13:12:12.088058 DramcWriteLeveling(PI) end<-----
8300 13:12:12.091591
8301 13:12:12.091708 ==
8302 13:12:12.094659 Dram Type= 6, Freq= 0, CH_1, rank 0
8303 13:12:12.098436 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 13:12:12.098585 ==
8305 13:12:12.101412 [Gating] SW mode calibration
8306 13:12:12.107983 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8307 13:12:12.111115 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8308 13:12:12.117721 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8309 13:12:12.120798 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8310 13:12:12.124387 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8311 13:12:12.131175 1 4 12 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
8312 13:12:12.134161 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8313 13:12:12.137836 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8314 13:12:12.143873 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 13:12:12.147433 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8316 13:12:12.153908 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 13:12:12.157038 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 13:12:12.160135 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
8319 13:12:12.166860 1 5 12 | B1->B0 | 3333 2424 | 1 0 | (1 0) (1 0)
8320 13:12:12.170435 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 13:12:12.173577 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 13:12:12.176679 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 13:12:12.183863 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 13:12:12.186621 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 13:12:12.190354 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 13:12:12.196490 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8327 13:12:12.199999 1 6 12 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
8328 13:12:12.203642 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8329 13:12:12.209839 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8330 13:12:12.213427 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 13:12:12.220184 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 13:12:12.223091 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 13:12:12.226698 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 13:12:12.229732 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8335 13:12:12.236588 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8336 13:12:12.239448 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8337 13:12:12.246150 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 13:12:12.249498 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 13:12:12.252597 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 13:12:12.259061 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 13:12:12.262694 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 13:12:12.265793 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 13:12:12.272374 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 13:12:12.275484 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 13:12:12.278817 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 13:12:12.285401 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 13:12:12.289078 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 13:12:12.292256 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 13:12:12.298826 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 13:12:12.301860 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8351 13:12:12.305369 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8352 13:12:12.312274 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 13:12:12.312423 Total UI for P1: 0, mck2ui 16
8354 13:12:12.318507 best dqsien dly found for B0: ( 1, 9, 10)
8355 13:12:12.318648 Total UI for P1: 0, mck2ui 16
8356 13:12:12.321902 best dqsien dly found for B1: ( 1, 9, 10)
8357 13:12:12.328560 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8358 13:12:12.331590 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8359 13:12:12.331705
8360 13:12:12.335242 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8361 13:12:12.338390 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8362 13:12:12.341308 [Gating] SW calibration Done
8363 13:12:12.341440 ==
8364 13:12:12.344890 Dram Type= 6, Freq= 0, CH_1, rank 0
8365 13:12:12.347893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 13:12:12.348011 ==
8367 13:12:12.351542 RX Vref Scan: 0
8368 13:12:12.351652
8369 13:12:12.351741 RX Vref 0 -> 0, step: 1
8370 13:12:12.351826
8371 13:12:12.354579 RX Delay 0 -> 252, step: 8
8372 13:12:12.358290 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8373 13:12:12.364345 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8374 13:12:12.367978 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8375 13:12:12.370973 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8376 13:12:12.374575 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8377 13:12:12.377631 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8378 13:12:12.384387 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8379 13:12:12.387632 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8380 13:12:12.390878 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8381 13:12:12.394331 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8382 13:12:12.397582 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8383 13:12:12.403965 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8384 13:12:12.407558 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8385 13:12:12.410633 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8386 13:12:12.414251 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8387 13:12:12.420347 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8388 13:12:12.420499 ==
8389 13:12:12.424109 Dram Type= 6, Freq= 0, CH_1, rank 0
8390 13:12:12.427140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8391 13:12:12.427272 ==
8392 13:12:12.427394 DQS Delay:
8393 13:12:12.430356 DQS0 = 0, DQS1 = 0
8394 13:12:12.430476 DQM Delay:
8395 13:12:12.433668 DQM0 = 135, DQM1 = 130
8396 13:12:12.433783 DQ Delay:
8397 13:12:12.437117 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8398 13:12:12.440343 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =127
8399 13:12:12.443380 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8400 13:12:12.450037 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8401 13:12:12.450172
8402 13:12:12.450263
8403 13:12:12.450354 ==
8404 13:12:12.453086 Dram Type= 6, Freq= 0, CH_1, rank 0
8405 13:12:12.456726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8406 13:12:12.456841 ==
8407 13:12:12.456929
8408 13:12:12.457014
8409 13:12:12.459738 TX Vref Scan disable
8410 13:12:12.459855 == TX Byte 0 ==
8411 13:12:12.466397 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8412 13:12:12.469955 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8413 13:12:12.470057 == TX Byte 1 ==
8414 13:12:12.476055 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8415 13:12:12.479830 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8416 13:12:12.479954 ==
8417 13:12:12.482903 Dram Type= 6, Freq= 0, CH_1, rank 0
8418 13:12:12.486014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8419 13:12:12.486129 ==
8420 13:12:12.500819
8421 13:12:12.504285 TX Vref early break, caculate TX vref
8422 13:12:12.507664 TX Vref=16, minBit 8, minWin=22, winSum=369
8423 13:12:12.510909 TX Vref=18, minBit 8, minWin=22, winSum=379
8424 13:12:12.514493 TX Vref=20, minBit 9, minWin=23, winSum=391
8425 13:12:12.517727 TX Vref=22, minBit 9, minWin=23, winSum=397
8426 13:12:12.520786 TX Vref=24, minBit 9, minWin=24, winSum=409
8427 13:12:12.527353 TX Vref=26, minBit 3, minWin=25, winSum=414
8428 13:12:12.530893 TX Vref=28, minBit 0, minWin=25, winSum=416
8429 13:12:12.534309 TX Vref=30, minBit 9, minWin=24, winSum=415
8430 13:12:12.537398 TX Vref=32, minBit 0, minWin=24, winSum=407
8431 13:12:12.540838 TX Vref=34, minBit 9, minWin=23, winSum=399
8432 13:12:12.547275 TX Vref=36, minBit 11, minWin=22, winSum=387
8433 13:12:12.550308 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 28
8434 13:12:12.550437
8435 13:12:12.553973 Final TX Range 0 Vref 28
8436 13:12:12.554101
8437 13:12:12.554198 ==
8438 13:12:12.557355 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 13:12:12.560267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 13:12:12.563809 ==
8441 13:12:12.563941
8442 13:12:12.564037
8443 13:12:12.564123 TX Vref Scan disable
8444 13:12:12.570483 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8445 13:12:12.570635 == TX Byte 0 ==
8446 13:12:12.573478 u2DelayCellOfst[0]=14 cells (4 PI)
8447 13:12:12.577083 u2DelayCellOfst[1]=10 cells (3 PI)
8448 13:12:12.580272 u2DelayCellOfst[2]=0 cells (0 PI)
8449 13:12:12.583877 u2DelayCellOfst[3]=7 cells (2 PI)
8450 13:12:12.586886 u2DelayCellOfst[4]=10 cells (3 PI)
8451 13:12:12.589953 u2DelayCellOfst[5]=17 cells (5 PI)
8452 13:12:12.593566 u2DelayCellOfst[6]=14 cells (4 PI)
8453 13:12:12.597166 u2DelayCellOfst[7]=7 cells (2 PI)
8454 13:12:12.600081 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8455 13:12:12.603766 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8456 13:12:12.606842 == TX Byte 1 ==
8457 13:12:12.609848 u2DelayCellOfst[8]=0 cells (0 PI)
8458 13:12:12.613482 u2DelayCellOfst[9]=3 cells (1 PI)
8459 13:12:12.616376 u2DelayCellOfst[10]=10 cells (3 PI)
8460 13:12:12.619805 u2DelayCellOfst[11]=3 cells (1 PI)
8461 13:12:12.622983 u2DelayCellOfst[12]=14 cells (4 PI)
8462 13:12:12.626451 u2DelayCellOfst[13]=14 cells (4 PI)
8463 13:12:12.626575 u2DelayCellOfst[14]=14 cells (4 PI)
8464 13:12:12.629781 u2DelayCellOfst[15]=17 cells (5 PI)
8465 13:12:12.636280 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8466 13:12:12.639861 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8467 13:12:12.643027 DramC Write-DBI on
8468 13:12:12.643127 ==
8469 13:12:12.646557 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 13:12:12.649514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 13:12:12.649637 ==
8472 13:12:12.649729
8473 13:12:12.649814
8474 13:12:12.653023 TX Vref Scan disable
8475 13:12:12.653146 == TX Byte 0 ==
8476 13:12:12.659822 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8477 13:12:12.659961 == TX Byte 1 ==
8478 13:12:12.662826 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8479 13:12:12.666090 DramC Write-DBI off
8480 13:12:12.666210
8481 13:12:12.666303 [DATLAT]
8482 13:12:12.669627 Freq=1600, CH1 RK0
8483 13:12:12.669746
8484 13:12:12.669840 DATLAT Default: 0xf
8485 13:12:12.672850 0, 0xFFFF, sum = 0
8486 13:12:12.672965 1, 0xFFFF, sum = 0
8487 13:12:12.675971 2, 0xFFFF, sum = 0
8488 13:12:12.676079 3, 0xFFFF, sum = 0
8489 13:12:12.679617 4, 0xFFFF, sum = 0
8490 13:12:12.682556 5, 0xFFFF, sum = 0
8491 13:12:12.682676 6, 0xFFFF, sum = 0
8492 13:12:12.686253 7, 0xFFFF, sum = 0
8493 13:12:12.686375 8, 0xFFFF, sum = 0
8494 13:12:12.689332 9, 0xFFFF, sum = 0
8495 13:12:12.689447 10, 0xFFFF, sum = 0
8496 13:12:12.692780 11, 0xFFFF, sum = 0
8497 13:12:12.693030 12, 0xFFFF, sum = 0
8498 13:12:12.695810 13, 0xFFFF, sum = 0
8499 13:12:12.695936 14, 0x0, sum = 1
8500 13:12:12.699319 15, 0x0, sum = 2
8501 13:12:12.699443 16, 0x0, sum = 3
8502 13:12:12.702254 17, 0x0, sum = 4
8503 13:12:12.702369 best_step = 15
8504 13:12:12.702452
8505 13:12:12.702508 ==
8506 13:12:12.705882 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 13:12:12.708993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 13:12:12.712675 ==
8509 13:12:12.712797 RX Vref Scan: 1
8510 13:12:12.712890
8511 13:12:12.715666 Set Vref Range= 24 -> 127
8512 13:12:12.715782
8513 13:12:12.719338 RX Vref 24 -> 127, step: 1
8514 13:12:12.719456
8515 13:12:12.719553 RX Delay 19 -> 252, step: 4
8516 13:12:12.719646
8517 13:12:12.722378 Set Vref, RX VrefLevel [Byte0]: 24
8518 13:12:12.726011 [Byte1]: 24
8519 13:12:12.729578
8520 13:12:12.729698 Set Vref, RX VrefLevel [Byte0]: 25
8521 13:12:12.732962 [Byte1]: 25
8522 13:12:12.737039
8523 13:12:12.737180 Set Vref, RX VrefLevel [Byte0]: 26
8524 13:12:12.740299 [Byte1]: 26
8525 13:12:12.744672
8526 13:12:12.744807 Set Vref, RX VrefLevel [Byte0]: 27
8527 13:12:12.747899 [Byte1]: 27
8528 13:12:12.751889
8529 13:12:12.752016 Set Vref, RX VrefLevel [Byte0]: 28
8530 13:12:12.755284 [Byte1]: 28
8531 13:12:12.759521
8532 13:12:12.759652 Set Vref, RX VrefLevel [Byte0]: 29
8533 13:12:12.762957 [Byte1]: 29
8534 13:12:12.767266
8535 13:12:12.767371 Set Vref, RX VrefLevel [Byte0]: 30
8536 13:12:12.770855 [Byte1]: 30
8537 13:12:12.774891
8538 13:12:12.775044 Set Vref, RX VrefLevel [Byte0]: 31
8539 13:12:12.778216 [Byte1]: 31
8540 13:12:12.782657
8541 13:12:12.782783 Set Vref, RX VrefLevel [Byte0]: 32
8542 13:12:12.785724 [Byte1]: 32
8543 13:12:12.790040
8544 13:12:12.790137 Set Vref, RX VrefLevel [Byte0]: 33
8545 13:12:12.793242 [Byte1]: 33
8546 13:12:12.797906
8547 13:12:12.798034 Set Vref, RX VrefLevel [Byte0]: 34
8548 13:12:12.800711 [Byte1]: 34
8549 13:12:12.805260
8550 13:12:12.805400 Set Vref, RX VrefLevel [Byte0]: 35
8551 13:12:12.808531 [Byte1]: 35
8552 13:12:12.812762
8553 13:12:12.812891 Set Vref, RX VrefLevel [Byte0]: 36
8554 13:12:12.815794 [Byte1]: 36
8555 13:12:12.820074
8556 13:12:12.820206 Set Vref, RX VrefLevel [Byte0]: 37
8557 13:12:12.823847 [Byte1]: 37
8558 13:12:12.828170
8559 13:12:12.828296 Set Vref, RX VrefLevel [Byte0]: 38
8560 13:12:12.831130 [Byte1]: 38
8561 13:12:12.835504
8562 13:12:12.835626 Set Vref, RX VrefLevel [Byte0]: 39
8563 13:12:12.838463 [Byte1]: 39
8564 13:12:12.843216
8565 13:12:12.843339 Set Vref, RX VrefLevel [Byte0]: 40
8566 13:12:12.846240 [Byte1]: 40
8567 13:12:12.850863
8568 13:12:12.850995 Set Vref, RX VrefLevel [Byte0]: 41
8569 13:12:12.854100 [Byte1]: 41
8570 13:12:12.858128
8571 13:12:12.858259 Set Vref, RX VrefLevel [Byte0]: 42
8572 13:12:12.861402 [Byte1]: 42
8573 13:12:12.865595
8574 13:12:12.865722 Set Vref, RX VrefLevel [Byte0]: 43
8575 13:12:12.868769 [Byte1]: 43
8576 13:12:12.873673
8577 13:12:12.873785 Set Vref, RX VrefLevel [Byte0]: 44
8578 13:12:12.876542 [Byte1]: 44
8579 13:12:12.880892
8580 13:12:12.881015 Set Vref, RX VrefLevel [Byte0]: 45
8581 13:12:12.884463 [Byte1]: 45
8582 13:12:12.888281
8583 13:12:12.888400 Set Vref, RX VrefLevel [Byte0]: 46
8584 13:12:12.891553 [Byte1]: 46
8585 13:12:12.895842
8586 13:12:12.895976 Set Vref, RX VrefLevel [Byte0]: 47
8587 13:12:12.899408 [Byte1]: 47
8588 13:12:12.903606
8589 13:12:12.903735 Set Vref, RX VrefLevel [Byte0]: 48
8590 13:12:12.906669 [Byte1]: 48
8591 13:12:12.911371
8592 13:12:12.911501 Set Vref, RX VrefLevel [Byte0]: 49
8593 13:12:12.914866 [Byte1]: 49
8594 13:12:12.919071
8595 13:12:12.919200 Set Vref, RX VrefLevel [Byte0]: 50
8596 13:12:12.922143 [Byte1]: 50
8597 13:12:12.926344
8598 13:12:12.926468 Set Vref, RX VrefLevel [Byte0]: 51
8599 13:12:12.929385 [Byte1]: 51
8600 13:12:12.934270
8601 13:12:12.934401 Set Vref, RX VrefLevel [Byte0]: 52
8602 13:12:12.937259 [Byte1]: 52
8603 13:12:12.941408
8604 13:12:12.941533 Set Vref, RX VrefLevel [Byte0]: 53
8605 13:12:12.945008 [Byte1]: 53
8606 13:12:12.949272
8607 13:12:12.949371 Set Vref, RX VrefLevel [Byte0]: 54
8608 13:12:12.952165 [Byte1]: 54
8609 13:12:12.956511
8610 13:12:12.956633 Set Vref, RX VrefLevel [Byte0]: 55
8611 13:12:12.960116 [Byte1]: 55
8612 13:12:12.964265
8613 13:12:12.964362 Set Vref, RX VrefLevel [Byte0]: 56
8614 13:12:12.967670 [Byte1]: 56
8615 13:12:12.971927
8616 13:12:12.972045 Set Vref, RX VrefLevel [Byte0]: 57
8617 13:12:12.975025 [Byte1]: 57
8618 13:12:12.979457
8619 13:12:12.979584 Set Vref, RX VrefLevel [Byte0]: 58
8620 13:12:12.982749 [Byte1]: 58
8621 13:12:12.987020
8622 13:12:12.987140 Set Vref, RX VrefLevel [Byte0]: 59
8623 13:12:12.990124 [Byte1]: 59
8624 13:12:12.994642
8625 13:12:12.994777 Set Vref, RX VrefLevel [Byte0]: 60
8626 13:12:12.998002 [Byte1]: 60
8627 13:12:13.002233
8628 13:12:13.002375 Set Vref, RX VrefLevel [Byte0]: 61
8629 13:12:13.005470 [Byte1]: 61
8630 13:12:13.009440
8631 13:12:13.009570 Set Vref, RX VrefLevel [Byte0]: 62
8632 13:12:13.012937 [Byte1]: 62
8633 13:12:13.017223
8634 13:12:13.017349 Set Vref, RX VrefLevel [Byte0]: 63
8635 13:12:13.020736 [Byte1]: 63
8636 13:12:13.024891
8637 13:12:13.025018 Set Vref, RX VrefLevel [Byte0]: 64
8638 13:12:13.027890 [Byte1]: 64
8639 13:12:13.032137
8640 13:12:13.032269 Set Vref, RX VrefLevel [Byte0]: 65
8641 13:12:13.035850 [Byte1]: 65
8642 13:12:13.039960
8643 13:12:13.040082 Set Vref, RX VrefLevel [Byte0]: 66
8644 13:12:13.043096 [Byte1]: 66
8645 13:12:13.047327
8646 13:12:13.047430 Set Vref, RX VrefLevel [Byte0]: 67
8647 13:12:13.050916 [Byte1]: 67
8648 13:12:13.055057
8649 13:12:13.055182 Set Vref, RX VrefLevel [Byte0]: 68
8650 13:12:13.058128 [Byte1]: 68
8651 13:12:13.062374
8652 13:12:13.062498 Set Vref, RX VrefLevel [Byte0]: 69
8653 13:12:13.066122 [Byte1]: 69
8654 13:12:13.070360
8655 13:12:13.070493 Set Vref, RX VrefLevel [Byte0]: 70
8656 13:12:13.073396 [Byte1]: 70
8657 13:12:13.078081
8658 13:12:13.078209 Final RX Vref Byte 0 = 62 to rank0
8659 13:12:13.081040 Final RX Vref Byte 1 = 59 to rank0
8660 13:12:13.084476 Final RX Vref Byte 0 = 62 to rank1
8661 13:12:13.087486 Final RX Vref Byte 1 = 59 to rank1==
8662 13:12:13.091011 Dram Type= 6, Freq= 0, CH_1, rank 0
8663 13:12:13.097384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8664 13:12:13.097526 ==
8665 13:12:13.097621 DQS Delay:
8666 13:12:13.100873 DQS0 = 0, DQS1 = 0
8667 13:12:13.101002 DQM Delay:
8668 13:12:13.101099 DQM0 = 132, DQM1 = 127
8669 13:12:13.103910 DQ Delay:
8670 13:12:13.107981 DQ0 =138, DQ1 =130, DQ2 =118, DQ3 =132
8671 13:12:13.110668 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =128
8672 13:12:13.114100 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =120
8673 13:12:13.117324 DQ12 =138, DQ13 =138, DQ14 =134, DQ15 =136
8674 13:12:13.117449
8675 13:12:13.117515
8676 13:12:13.117572
8677 13:12:13.120551 [DramC_TX_OE_Calibration] TA2
8678 13:12:13.124101 Original DQ_B0 (3 6) =30, OEN = 27
8679 13:12:13.127185 Original DQ_B1 (3 6) =30, OEN = 27
8680 13:12:13.130372 24, 0x0, End_B0=24 End_B1=24
8681 13:12:13.130498 25, 0x0, End_B0=25 End_B1=25
8682 13:12:13.133919 26, 0x0, End_B0=26 End_B1=26
8683 13:12:13.136924 27, 0x0, End_B0=27 End_B1=27
8684 13:12:13.140511 28, 0x0, End_B0=28 End_B1=28
8685 13:12:13.143547 29, 0x0, End_B0=29 End_B1=29
8686 13:12:13.143685 30, 0x0, End_B0=30 End_B1=30
8687 13:12:13.147142 31, 0x4545, End_B0=30 End_B1=30
8688 13:12:13.150074 Byte0 end_step=30 best_step=27
8689 13:12:13.153721 Byte1 end_step=30 best_step=27
8690 13:12:13.156618 Byte0 TX OE(2T, 0.5T) = (3, 3)
8691 13:12:13.160117 Byte1 TX OE(2T, 0.5T) = (3, 3)
8692 13:12:13.160248
8693 13:12:13.160341
8694 13:12:13.166874 [DQSOSCAuto] RK0, (LSB)MR18= 0xf17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 402 ps
8695 13:12:13.169946 CH1 RK0: MR19=303, MR18=F17
8696 13:12:13.176623 CH1_RK0: MR19=0x303, MR18=0xF17, DQSOSC=398, MR23=63, INC=23, DEC=15
8697 13:12:13.176774
8698 13:12:13.180187 ----->DramcWriteLeveling(PI) begin...
8699 13:12:13.180306 ==
8700 13:12:13.183741 Dram Type= 6, Freq= 0, CH_1, rank 1
8701 13:12:13.186780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8702 13:12:13.186907 ==
8703 13:12:13.190296 Write leveling (Byte 0): 22 => 22
8704 13:12:13.193259 Write leveling (Byte 1): 25 => 25
8705 13:12:13.196358 DramcWriteLeveling(PI) end<-----
8706 13:12:13.196484
8707 13:12:13.196573 ==
8708 13:12:13.199878 Dram Type= 6, Freq= 0, CH_1, rank 1
8709 13:12:13.202974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8710 13:12:13.203095 ==
8711 13:12:13.206362 [Gating] SW mode calibration
8712 13:12:13.213023 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8713 13:12:13.219572 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8714 13:12:13.222846 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8715 13:12:13.229526 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8716 13:12:13.232887 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8717 13:12:13.236024 1 4 12 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8718 13:12:13.242560 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8719 13:12:13.246067 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8720 13:12:13.249279 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8721 13:12:13.255887 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8722 13:12:13.258993 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8723 13:12:13.262605 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8724 13:12:13.268691 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8725 13:12:13.272372 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8726 13:12:13.275425 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8727 13:12:13.282055 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8728 13:12:13.285465 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8729 13:12:13.288552 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8730 13:12:13.295368 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8731 13:12:13.298942 1 6 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8732 13:12:13.301930 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8733 13:12:13.308388 1 6 12 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
8734 13:12:13.311735 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8735 13:12:13.315406 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8736 13:12:13.321500 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8737 13:12:13.325143 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8738 13:12:13.328494 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8739 13:12:13.335093 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8740 13:12:13.338238 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8741 13:12:13.341730 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8742 13:12:13.348262 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8743 13:12:13.351477 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8744 13:12:13.354499 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8745 13:12:13.361165 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8746 13:12:13.364285 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8747 13:12:13.367705 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8748 13:12:13.374107 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8749 13:12:13.377775 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8750 13:12:13.380889 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8751 13:12:13.387420 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8752 13:12:13.390873 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8753 13:12:13.394451 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8754 13:12:13.401057 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8755 13:12:13.403960 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8756 13:12:13.407687 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8757 13:12:13.410542 Total UI for P1: 0, mck2ui 16
8758 13:12:13.414049 best dqsien dly found for B0: ( 1, 9, 4)
8759 13:12:13.420617 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8760 13:12:13.420764 Total UI for P1: 0, mck2ui 16
8761 13:12:13.427247 best dqsien dly found for B1: ( 1, 9, 8)
8762 13:12:13.430786 best DQS0 dly(MCK, UI, PI) = (1, 9, 4)
8763 13:12:13.433748 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8764 13:12:13.433875
8765 13:12:13.437586 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 4)
8766 13:12:13.440383 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8767 13:12:13.443683 [Gating] SW calibration Done
8768 13:12:13.443810 ==
8769 13:12:13.446865 Dram Type= 6, Freq= 0, CH_1, rank 1
8770 13:12:13.450307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8771 13:12:13.450428 ==
8772 13:12:13.453819 RX Vref Scan: 0
8773 13:12:13.453939
8774 13:12:13.454030 RX Vref 0 -> 0, step: 1
8775 13:12:13.454116
8776 13:12:13.456803 RX Delay 0 -> 252, step: 8
8777 13:12:13.460369 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8778 13:12:13.466869 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8779 13:12:13.470266 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8780 13:12:13.472989 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8781 13:12:13.476545 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8782 13:12:13.479630 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8783 13:12:13.486521 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8784 13:12:13.489563 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8785 13:12:13.492995 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8786 13:12:13.496811 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8787 13:12:13.499645 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8788 13:12:13.506302 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8789 13:12:13.509676 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8790 13:12:13.512737 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8791 13:12:13.516416 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8792 13:12:13.522882 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8793 13:12:13.523024 ==
8794 13:12:13.526023 Dram Type= 6, Freq= 0, CH_1, rank 1
8795 13:12:13.529486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8796 13:12:13.529618 ==
8797 13:12:13.529715 DQS Delay:
8798 13:12:13.532467 DQS0 = 0, DQS1 = 0
8799 13:12:13.532580 DQM Delay:
8800 13:12:13.536083 DQM0 = 133, DQM1 = 130
8801 13:12:13.536209 DQ Delay:
8802 13:12:13.539089 DQ0 =139, DQ1 =131, DQ2 =119, DQ3 =131
8803 13:12:13.542238 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =131
8804 13:12:13.545920 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =123
8805 13:12:13.548900 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8806 13:12:13.552501
8807 13:12:13.552631
8808 13:12:13.552727 ==
8809 13:12:13.555500 Dram Type= 6, Freq= 0, CH_1, rank 1
8810 13:12:13.558728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8811 13:12:13.558847 ==
8812 13:12:13.558939
8813 13:12:13.559024
8814 13:12:13.561973 TX Vref Scan disable
8815 13:12:13.562082 == TX Byte 0 ==
8816 13:12:13.568900 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8817 13:12:13.572318 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8818 13:12:13.572453 == TX Byte 1 ==
8819 13:12:13.578998 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8820 13:12:13.581774 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8821 13:12:13.581897 ==
8822 13:12:13.585250 Dram Type= 6, Freq= 0, CH_1, rank 1
8823 13:12:13.599423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 13:12:13.599592 ==
8825 13:12:13.602491
8826 13:12:13.605881 TX Vref early break, caculate TX vref
8827 13:12:13.609240 TX Vref=16, minBit 9, minWin=21, winSum=378
8828 13:12:13.612063 TX Vref=18, minBit 9, minWin=22, winSum=382
8829 13:12:13.615727 TX Vref=20, minBit 9, minWin=23, winSum=394
8830 13:12:13.618608 TX Vref=22, minBit 9, minWin=24, winSum=404
8831 13:12:13.622125 TX Vref=24, minBit 9, minWin=24, winSum=411
8832 13:12:13.628582 TX Vref=26, minBit 1, minWin=25, winSum=417
8833 13:12:13.632254 TX Vref=28, minBit 9, minWin=24, winSum=425
8834 13:12:13.635253 TX Vref=30, minBit 9, minWin=24, winSum=414
8835 13:12:13.638996 TX Vref=32, minBit 9, minWin=24, winSum=408
8836 13:12:13.641798 TX Vref=34, minBit 0, minWin=24, winSum=401
8837 13:12:13.648591 [TxChooseVref] Worse bit 1, Min win 25, Win sum 417, Final Vref 26
8838 13:12:13.648746
8839 13:12:13.651758 Final TX Range 0 Vref 26
8840 13:12:13.651870
8841 13:12:13.651964 ==
8842 13:12:13.655274 Dram Type= 6, Freq= 0, CH_1, rank 1
8843 13:12:13.658313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8844 13:12:13.658431 ==
8845 13:12:13.658526
8846 13:12:13.658620
8847 13:12:13.661963 TX Vref Scan disable
8848 13:12:13.668571 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8849 13:12:13.668736 == TX Byte 0 ==
8850 13:12:13.671621 u2DelayCellOfst[0]=14 cells (4 PI)
8851 13:12:13.674937 u2DelayCellOfst[1]=10 cells (3 PI)
8852 13:12:13.677992 u2DelayCellOfst[2]=0 cells (0 PI)
8853 13:12:13.681298 u2DelayCellOfst[3]=3 cells (1 PI)
8854 13:12:13.684947 u2DelayCellOfst[4]=7 cells (2 PI)
8855 13:12:13.687895 u2DelayCellOfst[5]=14 cells (4 PI)
8856 13:12:13.691626 u2DelayCellOfst[6]=14 cells (4 PI)
8857 13:12:13.694700 u2DelayCellOfst[7]=7 cells (2 PI)
8858 13:12:13.697821 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8859 13:12:13.700964 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8860 13:12:13.704262 == TX Byte 1 ==
8861 13:12:13.707499 u2DelayCellOfst[8]=0 cells (0 PI)
8862 13:12:13.711227 u2DelayCellOfst[9]=3 cells (1 PI)
8863 13:12:13.714327 u2DelayCellOfst[10]=10 cells (3 PI)
8864 13:12:13.714454 u2DelayCellOfst[11]=3 cells (1 PI)
8865 13:12:13.717917 u2DelayCellOfst[12]=10 cells (3 PI)
8866 13:12:13.720961 u2DelayCellOfst[13]=14 cells (4 PI)
8867 13:12:13.724013 u2DelayCellOfst[14]=14 cells (4 PI)
8868 13:12:13.727430 u2DelayCellOfst[15]=17 cells (5 PI)
8869 13:12:13.733988 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8870 13:12:13.737499 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8871 13:12:13.737628 DramC Write-DBI on
8872 13:12:13.740577 ==
8873 13:12:13.740696 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 13:12:13.747343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 13:12:13.747475 ==
8876 13:12:13.747566
8877 13:12:13.747655
8878 13:12:13.750460 TX Vref Scan disable
8879 13:12:13.750570 == TX Byte 0 ==
8880 13:12:13.757111 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8881 13:12:13.757254 == TX Byte 1 ==
8882 13:12:13.760174 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8883 13:12:13.763859 DramC Write-DBI off
8884 13:12:13.763972
8885 13:12:13.764064 [DATLAT]
8886 13:12:13.766876 Freq=1600, CH1 RK1
8887 13:12:13.766984
8888 13:12:13.767077 DATLAT Default: 0xf
8889 13:12:13.770548 0, 0xFFFF, sum = 0
8890 13:12:13.770662 1, 0xFFFF, sum = 0
8891 13:12:13.773412 2, 0xFFFF, sum = 0
8892 13:12:13.773523 3, 0xFFFF, sum = 0
8893 13:12:13.777035 4, 0xFFFF, sum = 0
8894 13:12:13.777168 5, 0xFFFF, sum = 0
8895 13:12:13.780028 6, 0xFFFF, sum = 0
8896 13:12:13.783386 7, 0xFFFF, sum = 0
8897 13:12:13.783514 8, 0xFFFF, sum = 0
8898 13:12:13.787024 9, 0xFFFF, sum = 0
8899 13:12:13.787162 10, 0xFFFF, sum = 0
8900 13:12:13.789959 11, 0xFFFF, sum = 0
8901 13:12:13.790078 12, 0xFFFF, sum = 0
8902 13:12:13.793385 13, 0xFFFF, sum = 0
8903 13:12:13.793509 14, 0x0, sum = 1
8904 13:12:13.796573 15, 0x0, sum = 2
8905 13:12:13.796723 16, 0x0, sum = 3
8906 13:12:13.799740 17, 0x0, sum = 4
8907 13:12:13.799900 best_step = 15
8908 13:12:13.799999
8909 13:12:13.800092 ==
8910 13:12:13.802900 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 13:12:13.806444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 13:12:13.809860 ==
8913 13:12:13.810006 RX Vref Scan: 0
8914 13:12:13.810106
8915 13:12:13.813320 RX Vref 0 -> 0, step: 1
8916 13:12:13.813438
8917 13:12:13.813528 RX Delay 11 -> 252, step: 4
8918 13:12:13.820722 iDelay=195, Bit 0, Center 136 (83 ~ 190) 108
8919 13:12:13.823771 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8920 13:12:13.827587 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8921 13:12:13.830314 iDelay=195, Bit 3, Center 128 (79 ~ 178) 100
8922 13:12:13.833716 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8923 13:12:13.840258 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8924 13:12:13.843690 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8925 13:12:13.846887 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8926 13:12:13.850415 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8927 13:12:13.853489 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8928 13:12:13.860142 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8929 13:12:13.863267 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8930 13:12:13.866864 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8931 13:12:13.870412 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8932 13:12:13.877152 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8933 13:12:13.880209 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8934 13:12:13.880332 ==
8935 13:12:13.883753 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 13:12:13.886622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 13:12:13.886747 ==
8938 13:12:13.886841 DQS Delay:
8939 13:12:13.890084 DQS0 = 0, DQS1 = 0
8940 13:12:13.890193 DQM Delay:
8941 13:12:13.893555 DQM0 = 130, DQM1 = 128
8942 13:12:13.893673 DQ Delay:
8943 13:12:13.897232 DQ0 =136, DQ1 =130, DQ2 =118, DQ3 =128
8944 13:12:13.900288 DQ4 =128, DQ5 =142, DQ6 =136, DQ7 =126
8945 13:12:13.903752 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
8946 13:12:13.910036 DQ12 =138, DQ13 =134, DQ14 =132, DQ15 =138
8947 13:12:13.910177
8948 13:12:13.910269
8949 13:12:13.910353
8950 13:12:13.910437 [DramC_TX_OE_Calibration] TA2
8951 13:12:13.913386 Original DQ_B0 (3 6) =30, OEN = 27
8952 13:12:13.916733 Original DQ_B1 (3 6) =30, OEN = 27
8953 13:12:13.919747 24, 0x0, End_B0=24 End_B1=24
8954 13:12:13.923353 25, 0x0, End_B0=25 End_B1=25
8955 13:12:13.926428 26, 0x0, End_B0=26 End_B1=26
8956 13:12:13.929989 27, 0x0, End_B0=27 End_B1=27
8957 13:12:13.930145 28, 0x0, End_B0=28 End_B1=28
8958 13:12:13.932878 29, 0x0, End_B0=29 End_B1=29
8959 13:12:13.936275 30, 0x0, End_B0=30 End_B1=30
8960 13:12:13.939717 31, 0x4545, End_B0=30 End_B1=30
8961 13:12:13.943177 Byte0 end_step=30 best_step=27
8962 13:12:13.943302 Byte1 end_step=30 best_step=27
8963 13:12:13.946347 Byte0 TX OE(2T, 0.5T) = (3, 3)
8964 13:12:13.949547 Byte1 TX OE(2T, 0.5T) = (3, 3)
8965 13:12:13.949671
8966 13:12:13.949763
8967 13:12:13.959513 [DQSOSCAuto] RK1, (LSB)MR18= 0x111f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
8968 13:12:13.962529 CH1 RK1: MR19=303, MR18=111F
8969 13:12:13.966192 CH1_RK1: MR19=0x303, MR18=0x111F, DQSOSC=394, MR23=63, INC=23, DEC=15
8970 13:12:13.969242 [RxdqsGatingPostProcess] freq 1600
8971 13:12:13.975835 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8972 13:12:13.979474 best DQS0 dly(2T, 0.5T) = (1, 1)
8973 13:12:13.982464 best DQS1 dly(2T, 0.5T) = (1, 1)
8974 13:12:13.985994 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8975 13:12:13.989036 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8976 13:12:13.992420 best DQS0 dly(2T, 0.5T) = (1, 1)
8977 13:12:13.992544 best DQS1 dly(2T, 0.5T) = (1, 1)
8978 13:12:13.996017 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8979 13:12:13.998897 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8980 13:12:14.002549 Pre-setting of DQS Precalculation
8981 13:12:14.009234 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8982 13:12:14.015764 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8983 13:12:14.021945 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8984 13:12:14.022093
8985 13:12:14.022184
8986 13:12:14.025287 [Calibration Summary] 3200 Mbps
8987 13:12:14.028946 CH 0, Rank 0
8988 13:12:14.029072 SW Impedance : PASS
8989 13:12:14.031843 DUTY Scan : NO K
8990 13:12:14.035326 ZQ Calibration : PASS
8991 13:12:14.035448 Jitter Meter : NO K
8992 13:12:14.038773 CBT Training : PASS
8993 13:12:14.038890 Write leveling : PASS
8994 13:12:14.041632 RX DQS gating : PASS
8995 13:12:14.045171 RX DQ/DQS(RDDQC) : PASS
8996 13:12:14.045296 TX DQ/DQS : PASS
8997 13:12:14.048757 RX DATLAT : PASS
8998 13:12:14.051699 RX DQ/DQS(Engine): PASS
8999 13:12:14.051819 TX OE : PASS
9000 13:12:14.055174 All Pass.
9001 13:12:14.055290
9002 13:12:14.055386 CH 0, Rank 1
9003 13:12:14.058589 SW Impedance : PASS
9004 13:12:14.058700 DUTY Scan : NO K
9005 13:12:14.061920 ZQ Calibration : PASS
9006 13:12:14.065025 Jitter Meter : NO K
9007 13:12:14.065160 CBT Training : PASS
9008 13:12:14.068756 Write leveling : PASS
9009 13:12:14.071930 RX DQS gating : PASS
9010 13:12:14.072059 RX DQ/DQS(RDDQC) : PASS
9011 13:12:14.074878 TX DQ/DQS : PASS
9012 13:12:14.078488 RX DATLAT : PASS
9013 13:12:14.078608 RX DQ/DQS(Engine): PASS
9014 13:12:14.081550 TX OE : PASS
9015 13:12:14.081665 All Pass.
9016 13:12:14.081754
9017 13:12:14.085260 CH 1, Rank 0
9018 13:12:14.085374 SW Impedance : PASS
9019 13:12:14.088234 DUTY Scan : NO K
9020 13:12:14.091837 ZQ Calibration : PASS
9021 13:12:14.091966 Jitter Meter : NO K
9022 13:12:14.094662 CBT Training : PASS
9023 13:12:14.094783 Write leveling : PASS
9024 13:12:14.098279 RX DQS gating : PASS
9025 13:12:14.101846 RX DQ/DQS(RDDQC) : PASS
9026 13:12:14.101996 TX DQ/DQS : PASS
9027 13:12:14.104760 RX DATLAT : PASS
9028 13:12:14.108531 RX DQ/DQS(Engine): PASS
9029 13:12:14.108670 TX OE : PASS
9030 13:12:14.111478 All Pass.
9031 13:12:14.111593
9032 13:12:14.111683 CH 1, Rank 1
9033 13:12:14.114614 SW Impedance : PASS
9034 13:12:14.114738 DUTY Scan : NO K
9035 13:12:14.118152 ZQ Calibration : PASS
9036 13:12:14.121113 Jitter Meter : NO K
9037 13:12:14.121251 CBT Training : PASS
9038 13:12:14.124456 Write leveling : PASS
9039 13:12:14.127892 RX DQS gating : PASS
9040 13:12:14.128020 RX DQ/DQS(RDDQC) : PASS
9041 13:12:14.131262 TX DQ/DQS : PASS
9042 13:12:14.134646 RX DATLAT : PASS
9043 13:12:14.134777 RX DQ/DQS(Engine): PASS
9044 13:12:14.137861 TX OE : PASS
9045 13:12:14.137985 All Pass.
9046 13:12:14.138086
9047 13:12:14.140760 DramC Write-DBI on
9048 13:12:14.144312 PER_BANK_REFRESH: Hybrid Mode
9049 13:12:14.144440 TX_TRACKING: ON
9050 13:12:14.154033 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9051 13:12:14.160901 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9052 13:12:14.167092 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9053 13:12:14.174235 [FAST_K] Save calibration result to emmc
9054 13:12:14.174393 sync common calibartion params.
9055 13:12:14.177300 sync cbt_mode0:1, 1:1
9056 13:12:14.180765 dram_init: ddr_geometry: 2
9057 13:12:14.180883 dram_init: ddr_geometry: 2
9058 13:12:14.183850 dram_init: ddr_geometry: 2
9059 13:12:14.187482 0:dram_rank_size:100000000
9060 13:12:14.190309 1:dram_rank_size:100000000
9061 13:12:14.193906 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9062 13:12:14.196797 DFS_SHUFFLE_HW_MODE: ON
9063 13:12:14.200261 dramc_set_vcore_voltage set vcore to 725000
9064 13:12:14.203267 Read voltage for 1600, 0
9065 13:12:14.203388 Vio18 = 0
9066 13:12:14.206764 Vcore = 725000
9067 13:12:14.206878 Vdram = 0
9068 13:12:14.206974 Vddq = 0
9069 13:12:14.207062 Vmddr = 0
9070 13:12:14.209870 switch to 3200 Mbps bootup
9071 13:12:14.213438 [DramcRunTimeConfig]
9072 13:12:14.213557 PHYPLL
9073 13:12:14.216690 DPM_CONTROL_AFTERK: ON
9074 13:12:14.216805 PER_BANK_REFRESH: ON
9075 13:12:14.219824 REFRESH_OVERHEAD_REDUCTION: ON
9076 13:12:14.223485 CMD_PICG_NEW_MODE: OFF
9077 13:12:14.223612 XRTWTW_NEW_MODE: ON
9078 13:12:14.226397 XRTRTR_NEW_MODE: ON
9079 13:12:14.226516 TX_TRACKING: ON
9080 13:12:14.229926 RDSEL_TRACKING: OFF
9081 13:12:14.233327 DQS Precalculation for DVFS: ON
9082 13:12:14.233448 RX_TRACKING: OFF
9083 13:12:14.236319 HW_GATING DBG: ON
9084 13:12:14.236442 ZQCS_ENABLE_LP4: ON
9085 13:12:14.239860 RX_PICG_NEW_MODE: ON
9086 13:12:14.239977 TX_PICG_NEW_MODE: ON
9087 13:12:14.243331 ENABLE_RX_DCM_DPHY: ON
9088 13:12:14.246192 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9089 13:12:14.249847 DUMMY_READ_FOR_TRACKING: OFF
9090 13:12:14.249970 !!! SPM_CONTROL_AFTERK: OFF
9091 13:12:14.253253 !!! SPM could not control APHY
9092 13:12:14.256555 IMPEDANCE_TRACKING: ON
9093 13:12:14.256674 TEMP_SENSOR: ON
9094 13:12:14.259458 HW_SAVE_FOR_SR: OFF
9095 13:12:14.263088 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9096 13:12:14.266222 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9097 13:12:14.266338 Read ODT Tracking: ON
9098 13:12:14.269635 Refresh Rate DeBounce: ON
9099 13:12:14.272566 DFS_NO_QUEUE_FLUSH: ON
9100 13:12:14.276111 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9101 13:12:14.279704 ENABLE_DFS_RUNTIME_MRW: OFF
9102 13:12:14.279827 DDR_RESERVE_NEW_MODE: ON
9103 13:12:14.282678 MR_CBT_SWITCH_FREQ: ON
9104 13:12:14.285789 =========================
9105 13:12:14.303166 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9106 13:12:14.306616 dram_init: ddr_geometry: 2
9107 13:12:14.324671 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9108 13:12:14.327687 dram_init: dram init end (result: 0)
9109 13:12:14.334739 DRAM-K: Full calibration passed in 24383 msecs
9110 13:12:14.337669 MRC: failed to locate region type 0.
9111 13:12:14.337791 DRAM rank0 size:0x100000000,
9112 13:12:14.341004 DRAM rank1 size=0x100000000
9113 13:12:14.350735 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9114 13:12:14.357543 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9115 13:12:14.364264 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9116 13:12:14.374307 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9117 13:12:14.374463 DRAM rank0 size:0x100000000,
9118 13:12:14.377256 DRAM rank1 size=0x100000000
9119 13:12:14.377379 CBMEM:
9120 13:12:14.380835 IMD: root @ 0xfffff000 254 entries.
9121 13:12:14.384118 IMD: root @ 0xffffec00 62 entries.
9122 13:12:14.387234 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9123 13:12:14.393927 WARNING: RO_VPD is uninitialized or empty.
9124 13:12:14.396910 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9125 13:12:14.404773 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9126 13:12:14.417729 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9127 13:12:14.429052 BS: romstage times (exec / console): total (unknown) / 23915 ms
9128 13:12:14.429258
9129 13:12:14.429356
9130 13:12:14.438783 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9131 13:12:14.442327 ARM64: Exception handlers installed.
9132 13:12:14.445357 ARM64: Testing exception
9133 13:12:14.448483 ARM64: Done test exception
9134 13:12:14.448610 Enumerating buses...
9135 13:12:14.452100 Show all devs... Before device enumeration.
9136 13:12:14.455212 Root Device: enabled 1
9137 13:12:14.458845 CPU_CLUSTER: 0: enabled 1
9138 13:12:14.458972 CPU: 00: enabled 1
9139 13:12:14.461961 Compare with tree...
9140 13:12:14.462079 Root Device: enabled 1
9141 13:12:14.465104 CPU_CLUSTER: 0: enabled 1
9142 13:12:14.468368 CPU: 00: enabled 1
9143 13:12:14.468492 Root Device scanning...
9144 13:12:14.471572 scan_static_bus for Root Device
9145 13:12:14.474815 CPU_CLUSTER: 0 enabled
9146 13:12:14.478478 scan_static_bus for Root Device done
9147 13:12:14.481466 scan_bus: bus Root Device finished in 8 msecs
9148 13:12:14.481592 done
9149 13:12:14.488107 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9150 13:12:14.491548 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9151 13:12:14.498063 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9152 13:12:14.504712 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9153 13:12:14.504870 Allocating resources...
9154 13:12:14.507739 Reading resources...
9155 13:12:14.511227 Root Device read_resources bus 0 link: 0
9156 13:12:14.514800 DRAM rank0 size:0x100000000,
9157 13:12:14.514939 DRAM rank1 size=0x100000000
9158 13:12:14.521410 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9159 13:12:14.521554 CPU: 00 missing read_resources
9160 13:12:14.528040 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9161 13:12:14.531193 Root Device read_resources bus 0 link: 0 done
9162 13:12:14.534209 Done reading resources.
9163 13:12:14.537887 Show resources in subtree (Root Device)...After reading.
9164 13:12:14.540828 Root Device child on link 0 CPU_CLUSTER: 0
9165 13:12:14.544428 CPU_CLUSTER: 0 child on link 0 CPU: 00
9166 13:12:14.554225 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9167 13:12:14.554384 CPU: 00
9168 13:12:14.560746 Root Device assign_resources, bus 0 link: 0
9169 13:12:14.563923 CPU_CLUSTER: 0 missing set_resources
9170 13:12:14.567490 Root Device assign_resources, bus 0 link: 0 done
9171 13:12:14.567632 Done setting resources.
9172 13:12:14.574021 Show resources in subtree (Root Device)...After assigning values.
9173 13:12:14.577062 Root Device child on link 0 CPU_CLUSTER: 0
9174 13:12:14.583979 CPU_CLUSTER: 0 child on link 0 CPU: 00
9175 13:12:14.590258 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9176 13:12:14.590415 CPU: 00
9177 13:12:14.593553 Done allocating resources.
9178 13:12:14.600375 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9179 13:12:14.600529 Enabling resources...
9180 13:12:14.603637 done.
9181 13:12:14.606977 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9182 13:12:14.610109 Initializing devices...
9183 13:12:14.610229 Root Device init
9184 13:12:14.613133 init hardware done!
9185 13:12:14.613258 0x00000018: ctrlr->caps
9186 13:12:14.616681 52.000 MHz: ctrlr->f_max
9187 13:12:14.620314 0.400 MHz: ctrlr->f_min
9188 13:12:14.623241 0x40ff8080: ctrlr->voltages
9189 13:12:14.623363 sclk: 390625
9190 13:12:14.623458 Bus Width = 1
9191 13:12:14.626297 sclk: 390625
9192 13:12:14.626414 Bus Width = 1
9193 13:12:14.629933 Early init status = 3
9194 13:12:14.633424 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9195 13:12:14.636478 in-header: 03 fc 00 00 01 00 00 00
9196 13:12:14.639494 in-data: 00
9197 13:12:14.643102 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9198 13:12:14.647917 in-header: 03 fd 00 00 00 00 00 00
9199 13:12:14.650924 in-data:
9200 13:12:14.654603 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9201 13:12:14.658002 in-header: 03 fc 00 00 01 00 00 00
9202 13:12:14.661560 in-data: 00
9203 13:12:14.664593 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9204 13:12:14.670019 in-header: 03 fd 00 00 00 00 00 00
9205 13:12:14.673467 in-data:
9206 13:12:14.676530 [SSUSB] Setting up USB HOST controller...
9207 13:12:14.679571 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9208 13:12:14.683220 [SSUSB] phy power-on done.
9209 13:12:14.686725 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9210 13:12:14.693179 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9211 13:12:14.696196 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9212 13:12:14.702705 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9213 13:12:14.709542 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9214 13:12:14.716372 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9215 13:12:14.722584 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9216 13:12:14.728998 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9217 13:12:14.732640 SPM: binary array size = 0x9dc
9218 13:12:14.736206 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9219 13:12:14.742826 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9220 13:12:14.749561 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9221 13:12:14.756049 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9222 13:12:14.759014 configure_display: Starting display init
9223 13:12:14.793361 anx7625_power_on_init: Init interface.
9224 13:12:14.796366 anx7625_disable_pd_protocol: Disabled PD feature.
9225 13:12:14.799435 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9226 13:12:14.827644 anx7625_start_dp_work: Secure OCM version=00
9227 13:12:14.830880 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9228 13:12:14.845468 sp_tx_get_edid_block: EDID Block = 1
9229 13:12:14.948176 Extracted contents:
9230 13:12:14.951435 header: 00 ff ff ff ff ff ff 00
9231 13:12:14.954948 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9232 13:12:14.958033 version: 01 04
9233 13:12:14.961303 basic params: 95 1f 11 78 0a
9234 13:12:14.964651 chroma info: 76 90 94 55 54 90 27 21 50 54
9235 13:12:14.967752 established: 00 00 00
9236 13:12:14.974228 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9237 13:12:14.980772 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9238 13:12:14.984413 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9239 13:12:14.991043 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9240 13:12:14.997620 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9241 13:12:15.001091 extensions: 00
9242 13:12:15.001228 checksum: fb
9243 13:12:15.001327
9244 13:12:15.004063 Manufacturer: IVO Model 57d Serial Number 0
9245 13:12:15.007487 Made week 0 of 2020
9246 13:12:15.010507 EDID version: 1.4
9247 13:12:15.010633 Digital display
9248 13:12:15.014165 6 bits per primary color channel
9249 13:12:15.014285 DisplayPort interface
9250 13:12:15.017100 Maximum image size: 31 cm x 17 cm
9251 13:12:15.020743 Gamma: 220%
9252 13:12:15.020865 Check DPMS levels
9253 13:12:15.027264 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9254 13:12:15.030314 First detailed timing is preferred timing
9255 13:12:15.030449 Established timings supported:
9256 13:12:15.034036 Standard timings supported:
9257 13:12:15.036832 Detailed timings
9258 13:12:15.040231 Hex of detail: 383680a07038204018303c0035ae10000019
9259 13:12:15.046800 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9260 13:12:15.050301 0780 0798 07c8 0820 hborder 0
9261 13:12:15.053916 0438 043b 0447 0458 vborder 0
9262 13:12:15.057023 -hsync -vsync
9263 13:12:15.057171 Did detailed timing
9264 13:12:15.063378 Hex of detail: 000000000000000000000000000000000000
9265 13:12:15.066892 Manufacturer-specified data, tag 0
9266 13:12:15.069954 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9267 13:12:15.073343 ASCII string: InfoVision
9268 13:12:15.076838 Hex of detail: 000000fe00523134304e574635205248200a
9269 13:12:15.080086 ASCII string: R140NWF5 RH
9270 13:12:15.080221 Checksum
9271 13:12:15.083132 Checksum: 0xfb (valid)
9272 13:12:15.086237 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9273 13:12:15.089912 DSI data_rate: 832800000 bps
9274 13:12:15.096627 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9275 13:12:15.099534 anx7625_parse_edid: pixelclock(138800).
9276 13:12:15.103055 hactive(1920), hsync(48), hfp(24), hbp(88)
9277 13:12:15.106082 vactive(1080), vsync(12), vfp(3), vbp(17)
9278 13:12:15.109545 anx7625_dsi_config: config dsi.
9279 13:12:15.116032 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9280 13:12:15.130272 anx7625_dsi_config: success to config DSI
9281 13:12:15.133887 anx7625_dp_start: MIPI phy setup OK.
9282 13:12:15.136956 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9283 13:12:15.139939 mtk_ddp_mode_set invalid vrefresh 60
9284 13:12:15.143417 main_disp_path_setup
9285 13:12:15.143551 ovl_layer_smi_id_en
9286 13:12:15.146836 ovl_layer_smi_id_en
9287 13:12:15.146959 ccorr_config
9288 13:12:15.147057 aal_config
9289 13:12:15.149818 gamma_config
9290 13:12:15.149932 postmask_config
9291 13:12:15.153422 dither_config
9292 13:12:15.156413 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9293 13:12:15.163028 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9294 13:12:15.166709 Root Device init finished in 552 msecs
9295 13:12:15.170044 CPU_CLUSTER: 0 init
9296 13:12:15.176430 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9297 13:12:15.183139 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9298 13:12:15.183289 APU_MBOX 0x190000b0 = 0x10001
9299 13:12:15.186614 APU_MBOX 0x190001b0 = 0x10001
9300 13:12:15.189842 APU_MBOX 0x190005b0 = 0x10001
9301 13:12:15.193033 APU_MBOX 0x190006b0 = 0x10001
9302 13:12:15.199541 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9303 13:12:15.209241 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9304 13:12:15.221355 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9305 13:12:15.227941 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9306 13:12:15.239727 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9307 13:12:15.249149 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9308 13:12:15.252030 CPU_CLUSTER: 0 init finished in 81 msecs
9309 13:12:15.255669 Devices initialized
9310 13:12:15.258673 Show all devs... After init.
9311 13:12:15.258814 Root Device: enabled 1
9312 13:12:15.262074 CPU_CLUSTER: 0: enabled 1
9313 13:12:15.265385 CPU: 00: enabled 1
9314 13:12:15.268346 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9315 13:12:15.272007 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9316 13:12:15.275511 ELOG: NV offset 0x57f000 size 0x1000
9317 13:12:15.282147 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9318 13:12:15.288544 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9319 13:12:15.291698 ELOG: Event(17) added with size 13 at 2024-07-18 13:12:15 UTC
9320 13:12:15.298500 out: cmd=0x121: 03 db 21 01 00 00 00 00
9321 13:12:15.301720 in-header: 03 23 00 00 2c 00 00 00
9322 13:12:15.311667 in-data: 1a 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9323 13:12:15.318652 ELOG: Event(A1) added with size 10 at 2024-07-18 13:12:15 UTC
9324 13:12:15.325247 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9325 13:12:15.331394 ELOG: Event(A0) added with size 9 at 2024-07-18 13:12:15 UTC
9326 13:12:15.334793 elog_add_boot_reason: Logged dev mode boot
9327 13:12:15.341415 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9328 13:12:15.341570 Finalize devices...
9329 13:12:15.344529 Devices finalized
9330 13:12:15.348118 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9331 13:12:15.351138 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9332 13:12:15.354738 in-header: 03 07 00 00 08 00 00 00
9333 13:12:15.357957 in-data: aa e4 47 04 13 02 00 00
9334 13:12:15.360955 Chrome EC: UHEPI supported
9335 13:12:15.367666 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9336 13:12:15.370720 in-header: 03 a9 00 00 08 00 00 00
9337 13:12:15.374389 in-data: 84 60 60 08 00 00 00 00
9338 13:12:15.380872 ELOG: Event(91) added with size 10 at 2024-07-18 13:12:15 UTC
9339 13:12:15.387363 Chrome EC: clear events_b mask to 0x0000000020004000
9340 13:12:15.394420 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9341 13:12:15.397260 in-header: 03 fd 00 00 00 00 00 00
9342 13:12:15.397389 in-data:
9343 13:12:15.403806 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9344 13:12:15.407114 Writing coreboot table at 0xffe64000
9345 13:12:15.410641 0. 000000000010a000-0000000000113fff: RAMSTAGE
9346 13:12:15.414232 1. 0000000040000000-00000000400fffff: RAM
9347 13:12:15.417060 2. 0000000040100000-000000004032afff: RAMSTAGE
9348 13:12:15.420412 3. 000000004032b000-00000000545fffff: RAM
9349 13:12:15.427184 4. 0000000054600000-000000005465ffff: BL31
9350 13:12:15.430220 5. 0000000054660000-00000000ffe63fff: RAM
9351 13:12:15.433833 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9352 13:12:15.440369 7. 0000000100000000-000000023fffffff: RAM
9353 13:12:15.440521 Passing 5 GPIOs to payload:
9354 13:12:15.446905 NAME | PORT | POLARITY | VALUE
9355 13:12:15.449907 EC in RW | 0x000000aa | low | undefined
9356 13:12:15.456470 EC interrupt | 0x00000005 | low | undefined
9357 13:12:15.460002 TPM interrupt | 0x000000ab | high | undefined
9358 13:12:15.463227 SD card detect | 0x00000011 | high | undefined
9359 13:12:15.469818 speaker enable | 0x00000093 | high | undefined
9360 13:12:15.473441 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9361 13:12:15.476470 in-header: 03 f9 00 00 02 00 00 00
9362 13:12:15.476595 in-data: 02 00
9363 13:12:15.479491 ADC[4]: Raw value=903325 ID=7
9364 13:12:15.482964 ADC[3]: Raw value=213546 ID=1
9365 13:12:15.483084 RAM Code: 0x71
9366 13:12:15.486423 ADC[6]: Raw value=74630 ID=0
9367 13:12:15.489430 ADC[5]: Raw value=213546 ID=1
9368 13:12:15.489557 SKU Code: 0x1
9369 13:12:15.496342 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3298
9370 13:12:15.499292 coreboot table: 964 bytes.
9371 13:12:15.502801 IMD ROOT 0. 0xfffff000 0x00001000
9372 13:12:15.506227 IMD SMALL 1. 0xffffe000 0x00001000
9373 13:12:15.509743 RO MCACHE 2. 0xffffc000 0x00001104
9374 13:12:15.512657 CONSOLE 3. 0xfff7c000 0x00080000
9375 13:12:15.516067 FMAP 4. 0xfff7b000 0x00000452
9376 13:12:15.519721 TIME STAMP 5. 0xfff7a000 0x00000910
9377 13:12:15.522610 VBOOT WORK 6. 0xfff66000 0x00014000
9378 13:12:15.526123 RAMOOPS 7. 0xffe66000 0x00100000
9379 13:12:15.529549 COREBOOT 8. 0xffe64000 0x00002000
9380 13:12:15.529685 IMD small region:
9381 13:12:15.532985 IMD ROOT 0. 0xffffec00 0x00000400
9382 13:12:15.535848 VPD 1. 0xffffeb80 0x0000006c
9383 13:12:15.539526 MMC STATUS 2. 0xffffeb60 0x00000004
9384 13:12:15.545986 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9385 13:12:15.552839 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9386 13:12:15.591970 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9387 13:12:15.595705 Checking segment from ROM address 0x40100000
9388 13:12:15.598596 Checking segment from ROM address 0x4010001c
9389 13:12:15.605250 Loading segment from ROM address 0x40100000
9390 13:12:15.605396 code (compression=0)
9391 13:12:15.615485 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9392 13:12:15.622022 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9393 13:12:15.622170 it's not compressed!
9394 13:12:15.628317 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9395 13:12:15.634896 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9396 13:12:15.652518 Loading segment from ROM address 0x4010001c
9397 13:12:15.652696 Entry Point 0x80000000
9398 13:12:15.655514 Loaded segments
9399 13:12:15.659279 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9400 13:12:15.665923 Jumping to boot code at 0x80000000(0xffe64000)
9401 13:12:15.672542 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9402 13:12:15.678860 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9403 13:12:15.687263 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9404 13:12:15.690397 Checking segment from ROM address 0x40100000
9405 13:12:15.693236 Checking segment from ROM address 0x4010001c
9406 13:12:15.699796 Loading segment from ROM address 0x40100000
9407 13:12:15.699959 code (compression=1)
9408 13:12:15.709618 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9409 13:12:15.716377 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9410 13:12:15.716541 using LZMA
9411 13:12:15.725273 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9412 13:12:15.732078 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9413 13:12:15.735472 Loading segment from ROM address 0x4010001c
9414 13:12:15.735614 Entry Point 0x54601000
9415 13:12:15.738443 Loaded segments
9416 13:12:15.741554 NOTICE: MT8192 bl31_setup
9417 13:12:15.748713 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9418 13:12:15.752038 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9419 13:12:15.755620 WARNING: region 0:
9420 13:12:15.759328 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9421 13:12:15.759466 WARNING: region 1:
9422 13:12:15.765352 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9423 13:12:15.768961 WARNING: region 2:
9424 13:12:15.772515 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9425 13:12:15.775707 WARNING: region 3:
9426 13:12:15.779252 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9427 13:12:15.782206 WARNING: region 4:
9428 13:12:15.789070 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9429 13:12:15.789232 WARNING: region 5:
9430 13:12:15.792136 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9431 13:12:15.795128 WARNING: region 6:
9432 13:12:15.798727 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9433 13:12:15.802227 WARNING: region 7:
9434 13:12:15.805336 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9435 13:12:15.811903 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9436 13:12:15.815344 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9437 13:12:15.821520 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9438 13:12:15.824837 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9439 13:12:15.828490 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9440 13:12:15.834509 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9441 13:12:15.837840 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9442 13:12:15.841218 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9443 13:12:15.847802 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9444 13:12:15.850801 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9445 13:12:15.857614 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9446 13:12:15.861226 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9447 13:12:15.864241 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9448 13:12:15.870943 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9449 13:12:15.874583 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9450 13:12:15.877599 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9451 13:12:15.884323 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9452 13:12:15.887252 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9453 13:12:15.894154 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9454 13:12:15.897117 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9455 13:12:15.903671 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9456 13:12:15.907176 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9457 13:12:15.910327 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9458 13:12:15.916934 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9459 13:12:15.920566 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9460 13:12:15.926924 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9461 13:12:15.930309 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9462 13:12:15.933221 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9463 13:12:15.939839 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9464 13:12:15.943477 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9465 13:12:15.949825 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9466 13:12:15.953045 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9467 13:12:15.956593 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9468 13:12:15.963317 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9469 13:12:15.966560 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9470 13:12:15.969624 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9471 13:12:15.973300 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9472 13:12:15.979418 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9473 13:12:15.983114 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9474 13:12:15.986752 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9475 13:12:15.989842 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9476 13:12:15.996222 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9477 13:12:15.999483 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9478 13:12:16.002840 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9479 13:12:16.006513 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9480 13:12:16.012445 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9481 13:12:16.016072 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9482 13:12:16.019504 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9483 13:12:16.025554 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9484 13:12:16.029017 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9485 13:12:16.035456 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9486 13:12:16.038873 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9487 13:12:16.042415 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9488 13:12:16.049021 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9489 13:12:16.051945 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9490 13:12:16.059130 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9491 13:12:16.062286 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9492 13:12:16.068461 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9493 13:12:16.071884 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9494 13:12:16.078559 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9495 13:12:16.081564 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9496 13:12:16.085114 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9497 13:12:16.091877 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9498 13:12:16.094922 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9499 13:12:16.101572 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9500 13:12:16.105111 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9501 13:12:16.111365 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9502 13:12:16.114925 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9503 13:12:16.121693 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9504 13:12:16.124697 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9505 13:12:16.127831 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9506 13:12:16.134920 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9507 13:12:16.137883 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9508 13:12:16.144235 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9509 13:12:16.147680 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9510 13:12:16.154247 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9511 13:12:16.157871 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9512 13:12:16.164485 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9513 13:12:16.167352 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9514 13:12:16.174452 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9515 13:12:16.177463 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9516 13:12:16.180566 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9517 13:12:16.187212 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9518 13:12:16.190907 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9519 13:12:16.197357 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9520 13:12:16.200434 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9521 13:12:16.207107 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9522 13:12:16.210085 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9523 13:12:16.217054 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9524 13:12:16.219865 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9525 13:12:16.223332 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9526 13:12:16.229772 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9527 13:12:16.233330 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9528 13:12:16.239861 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9529 13:12:16.242915 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9530 13:12:16.249344 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9531 13:12:16.252777 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9532 13:12:16.256382 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9533 13:12:16.263054 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9534 13:12:16.266094 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9535 13:12:16.269560 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9536 13:12:16.275972 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9537 13:12:16.279116 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9538 13:12:16.282707 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9539 13:12:16.289430 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9540 13:12:16.292534 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9541 13:12:16.298831 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9542 13:12:16.302066 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9543 13:12:16.305825 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9544 13:12:16.312291 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9545 13:12:16.315858 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9546 13:12:16.322255 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9547 13:12:16.325536 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9548 13:12:16.332259 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9549 13:12:16.335255 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9550 13:12:16.338744 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9551 13:12:16.341620 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9552 13:12:16.348858 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9553 13:12:16.351855 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9554 13:12:16.355324 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9555 13:12:16.361878 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9556 13:12:16.364949 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9557 13:12:16.368548 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9558 13:12:16.371602 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9559 13:12:16.378016 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9560 13:12:16.381745 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9561 13:12:16.388245 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9562 13:12:16.391218 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9563 13:12:16.394835 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9564 13:12:16.401634 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9565 13:12:16.404720 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9566 13:12:16.411343 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9567 13:12:16.414500 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9568 13:12:16.421034 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9569 13:12:16.424394 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9570 13:12:16.427380 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9571 13:12:16.434319 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9572 13:12:16.437637 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9573 13:12:16.444306 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9574 13:12:16.447213 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9575 13:12:16.450895 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9576 13:12:16.457161 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9577 13:12:16.460687 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9578 13:12:16.467393 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9579 13:12:16.470335 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9580 13:12:16.473984 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9581 13:12:16.480395 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9582 13:12:16.483815 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9583 13:12:16.487402 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9584 13:12:16.494349 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9585 13:12:16.497337 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9586 13:12:16.503935 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9587 13:12:16.506938 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9588 13:12:16.510523 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9589 13:12:16.517033 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9590 13:12:16.519927 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9591 13:12:16.526925 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9592 13:12:16.530228 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9593 13:12:16.533655 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9594 13:12:16.539953 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9595 13:12:16.542972 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9596 13:12:16.549953 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9597 13:12:16.553047 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9598 13:12:16.556582 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9599 13:12:16.563415 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9600 13:12:16.566228 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9601 13:12:16.572804 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9602 13:12:16.576416 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9603 13:12:16.579413 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9604 13:12:16.586478 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9605 13:12:16.589495 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9606 13:12:16.596105 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9607 13:12:16.599250 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9608 13:12:16.603039 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9609 13:12:16.609175 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9610 13:12:16.612207 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9611 13:12:16.618873 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9612 13:12:16.622449 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9613 13:12:16.625485 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9614 13:12:16.632505 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9615 13:12:16.635331 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9616 13:12:16.642140 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9617 13:12:16.645576 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9618 13:12:16.648326 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9619 13:12:16.655025 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9620 13:12:16.658378 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9621 13:12:16.664948 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9622 13:12:16.668086 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9623 13:12:16.674700 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9624 13:12:16.677923 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9625 13:12:16.681640 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9626 13:12:16.688051 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9627 13:12:16.691541 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9628 13:12:16.697620 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9629 13:12:16.701348 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9630 13:12:16.708103 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9631 13:12:16.711116 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9632 13:12:16.714186 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9633 13:12:16.720849 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9634 13:12:16.724305 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9635 13:12:16.730995 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9636 13:12:16.734409 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9637 13:12:16.740891 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9638 13:12:16.744213 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9639 13:12:16.747071 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9640 13:12:16.754193 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9641 13:12:16.757099 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9642 13:12:16.763700 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9643 13:12:16.767333 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9644 13:12:16.773910 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9645 13:12:16.776848 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9646 13:12:16.780316 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9647 13:12:16.787060 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9648 13:12:16.789856 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9649 13:12:16.796370 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9650 13:12:16.800059 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9651 13:12:16.806759 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9652 13:12:16.809784 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9653 13:12:16.812782 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9654 13:12:16.819420 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9655 13:12:16.823073 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9656 13:12:16.829223 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9657 13:12:16.832985 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9658 13:12:16.839327 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9659 13:12:16.842695 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9660 13:12:16.846257 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9661 13:12:16.852485 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9662 13:12:16.856029 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9663 13:12:16.862543 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9664 13:12:16.865607 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9665 13:12:16.869125 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9666 13:12:16.872642 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9667 13:12:16.878552 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9668 13:12:16.882102 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9669 13:12:16.885226 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9670 13:12:16.891777 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9671 13:12:16.895048 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9672 13:12:16.901772 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9673 13:12:16.905149 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9674 13:12:16.908542 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9675 13:12:16.915219 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9676 13:12:16.918234 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9677 13:12:16.921332 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9678 13:12:16.928489 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9679 13:12:16.931638 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9680 13:12:16.934559 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9681 13:12:16.941339 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9682 13:12:16.944817 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9683 13:12:16.951305 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9684 13:12:16.954675 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9685 13:12:16.957538 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9686 13:12:16.964052 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9687 13:12:16.967653 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9688 13:12:16.970666 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9689 13:12:16.977664 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9690 13:12:16.980640 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9691 13:12:16.987721 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9692 13:12:16.990693 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9693 13:12:16.994303 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9694 13:12:17.000327 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9695 13:12:17.004037 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9696 13:12:17.010728 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9697 13:12:17.014071 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9698 13:12:17.017242 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9699 13:12:17.023607 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9700 13:12:17.026684 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9701 13:12:17.030252 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9702 13:12:17.036588 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9703 13:12:17.040174 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9704 13:12:17.043145 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9705 13:12:17.049950 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9706 13:12:17.053269 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9707 13:12:17.056493 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9708 13:12:17.060087 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9709 13:12:17.062912 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9710 13:12:17.070009 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9711 13:12:17.072848 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9712 13:12:17.076508 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9713 13:12:17.080000 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9714 13:12:17.086525 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9715 13:12:17.089518 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9716 13:12:17.092994 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9717 13:12:17.099711 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9718 13:12:17.102835 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9719 13:12:17.109473 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9720 13:12:17.112923 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9721 13:12:17.118973 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9722 13:12:17.122639 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9723 13:12:17.125657 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9724 13:12:17.132537 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9725 13:12:17.136017 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9726 13:12:17.142368 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9727 13:12:17.145843 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9728 13:12:17.148925 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9729 13:12:17.155485 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9730 13:12:17.159275 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9731 13:12:17.165321 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9732 13:12:17.168791 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9733 13:12:17.171863 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9734 13:12:17.178323 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9735 13:12:17.181858 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9736 13:12:17.188488 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9737 13:12:17.191944 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9738 13:12:17.198684 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9739 13:12:17.201718 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9740 13:12:17.204673 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9741 13:12:17.211343 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9742 13:12:17.215150 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9743 13:12:17.221427 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9744 13:12:17.224982 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9745 13:12:17.230999 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9746 13:12:17.234650 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9747 13:12:17.241238 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9748 13:12:17.244694 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9749 13:12:17.247718 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9750 13:12:17.254410 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9751 13:12:17.257679 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9752 13:12:17.264235 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9753 13:12:17.267421 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9754 13:12:17.270747 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9755 13:12:17.276973 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9756 13:12:17.280616 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9757 13:12:17.287207 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9758 13:12:17.290731 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9759 13:12:17.297240 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9760 13:12:17.300334 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9761 13:12:17.303404 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9762 13:12:17.310019 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9763 13:12:17.313638 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9764 13:12:17.320499 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9765 13:12:17.323211 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9766 13:12:17.326949 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9767 13:12:17.333456 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9768 13:12:17.336506 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9769 13:12:17.342976 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9770 13:12:17.346624 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9771 13:12:17.353208 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9772 13:12:17.356655 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9773 13:12:17.359627 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9774 13:12:17.366516 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9775 13:12:17.369343 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9776 13:12:17.375990 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9777 13:12:17.379078 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9778 13:12:17.382630 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9779 13:12:17.389512 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9780 13:12:17.392450 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9781 13:12:17.399047 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9782 13:12:17.402427 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9783 13:12:17.409228 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9784 13:12:17.412218 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9785 13:12:17.415940 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9786 13:12:17.422464 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9787 13:12:17.425287 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9788 13:12:17.432179 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9789 13:12:17.435363 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9790 13:12:17.438719 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9791 13:12:17.445206 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9792 13:12:17.448819 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9793 13:12:17.454795 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9794 13:12:17.458400 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9795 13:12:17.464910 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9796 13:12:17.468283 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9797 13:12:17.474784 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9798 13:12:17.478494 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9799 13:12:17.484897 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9800 13:12:17.488267 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9801 13:12:17.491275 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9802 13:12:17.498204 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9803 13:12:17.501264 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9804 13:12:17.508535 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9805 13:12:17.511014 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9806 13:12:17.517831 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9807 13:12:17.521426 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9808 13:12:17.527576 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9809 13:12:17.531119 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9810 13:12:17.534125 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9811 13:12:17.540676 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9812 13:12:17.544268 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9813 13:12:17.550570 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9814 13:12:17.554284 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9815 13:12:17.560857 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9816 13:12:17.563814 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9817 13:12:17.570426 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9818 13:12:17.573572 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9819 13:12:17.579907 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9820 13:12:17.583421 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9821 13:12:17.586595 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9822 13:12:17.593232 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9823 13:12:17.596755 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9824 13:12:17.603097 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9825 13:12:17.606488 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9826 13:12:17.613462 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9827 13:12:17.616503 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9828 13:12:17.619675 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9829 13:12:17.626194 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9830 13:12:17.629990 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9831 13:12:17.636323 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9832 13:12:17.639987 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9833 13:12:17.646043 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9834 13:12:17.649400 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9835 13:12:17.656418 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9836 13:12:17.659415 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9837 13:12:17.662987 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9838 13:12:17.669088 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9839 13:12:17.672850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9840 13:12:17.679256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9841 13:12:17.682672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9842 13:12:17.688992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9843 13:12:17.692620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9844 13:12:17.699379 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9845 13:12:17.702325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9846 13:12:17.708727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9847 13:12:17.712207 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9848 13:12:17.718597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9849 13:12:17.722042 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9850 13:12:17.728693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9851 13:12:17.731595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9852 13:12:17.738564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9853 13:12:17.741647 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9854 13:12:17.748108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9855 13:12:17.751767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9856 13:12:17.758467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9857 13:12:17.761304 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9858 13:12:17.767843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9859 13:12:17.771477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9860 13:12:17.778176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9861 13:12:17.781212 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9862 13:12:17.788016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9863 13:12:17.791356 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9864 13:12:17.797916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9865 13:12:17.800931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9866 13:12:17.807608 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9867 13:12:17.810796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9868 13:12:17.817245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9869 13:12:17.820579 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9870 13:12:17.824241 INFO: [APUAPC] vio 0
9871 13:12:17.827215 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9872 13:12:17.833912 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9873 13:12:17.837255 INFO: [APUAPC] D0_APC_0: 0x400510
9874 13:12:17.837383 INFO: [APUAPC] D0_APC_1: 0x0
9875 13:12:17.840600 INFO: [APUAPC] D0_APC_2: 0x1540
9876 13:12:17.843650 INFO: [APUAPC] D0_APC_3: 0x0
9877 13:12:17.847654 INFO: [APUAPC] D1_APC_0: 0xffffffff
9878 13:12:17.850480 INFO: [APUAPC] D1_APC_1: 0xffffffff
9879 13:12:17.853714 INFO: [APUAPC] D1_APC_2: 0x3fffff
9880 13:12:17.857233 INFO: [APUAPC] D1_APC_3: 0x0
9881 13:12:17.860222 INFO: [APUAPC] D2_APC_0: 0xffffffff
9882 13:12:17.863731 INFO: [APUAPC] D2_APC_1: 0xffffffff
9883 13:12:17.867100 INFO: [APUAPC] D2_APC_2: 0x3fffff
9884 13:12:17.870358 INFO: [APUAPC] D2_APC_3: 0x0
9885 13:12:17.873352 INFO: [APUAPC] D3_APC_0: 0xffffffff
9886 13:12:17.876827 INFO: [APUAPC] D3_APC_1: 0xffffffff
9887 13:12:17.880141 INFO: [APUAPC] D3_APC_2: 0x3fffff
9888 13:12:17.883459 INFO: [APUAPC] D3_APC_3: 0x0
9889 13:12:17.886440 INFO: [APUAPC] D4_APC_0: 0xffffffff
9890 13:12:17.890098 INFO: [APUAPC] D4_APC_1: 0xffffffff
9891 13:12:17.893057 INFO: [APUAPC] D4_APC_2: 0x3fffff
9892 13:12:17.896365 INFO: [APUAPC] D4_APC_3: 0x0
9893 13:12:17.899845 INFO: [APUAPC] D5_APC_0: 0xffffffff
9894 13:12:17.902950 INFO: [APUAPC] D5_APC_1: 0xffffffff
9895 13:12:17.906603 INFO: [APUAPC] D5_APC_2: 0x3fffff
9896 13:12:17.909767 INFO: [APUAPC] D5_APC_3: 0x0
9897 13:12:17.913262 INFO: [APUAPC] D6_APC_0: 0xffffffff
9898 13:12:17.916258 INFO: [APUAPC] D6_APC_1: 0xffffffff
9899 13:12:17.919280 INFO: [APUAPC] D6_APC_2: 0x3fffff
9900 13:12:17.922764 INFO: [APUAPC] D6_APC_3: 0x0
9901 13:12:17.926086 INFO: [APUAPC] D7_APC_0: 0xffffffff
9902 13:12:17.929222 INFO: [APUAPC] D7_APC_1: 0xffffffff
9903 13:12:17.932800 INFO: [APUAPC] D7_APC_2: 0x3fffff
9904 13:12:17.935905 INFO: [APUAPC] D7_APC_3: 0x0
9905 13:12:17.939545 INFO: [APUAPC] D8_APC_0: 0xffffffff
9906 13:12:17.942543 INFO: [APUAPC] D8_APC_1: 0xffffffff
9907 13:12:17.946066 INFO: [APUAPC] D8_APC_2: 0x3fffff
9908 13:12:17.949012 INFO: [APUAPC] D8_APC_3: 0x0
9909 13:12:17.952426 INFO: [APUAPC] D9_APC_0: 0xffffffff
9910 13:12:17.955720 INFO: [APUAPC] D9_APC_1: 0xffffffff
9911 13:12:17.959157 INFO: [APUAPC] D9_APC_2: 0x3fffff
9912 13:12:17.962307 INFO: [APUAPC] D9_APC_3: 0x0
9913 13:12:17.965961 INFO: [APUAPC] D10_APC_0: 0xffffffff
9914 13:12:17.968804 INFO: [APUAPC] D10_APC_1: 0xffffffff
9915 13:12:17.972273 INFO: [APUAPC] D10_APC_2: 0x3fffff
9916 13:12:17.975404 INFO: [APUAPC] D10_APC_3: 0x0
9917 13:12:17.978731 INFO: [APUAPC] D11_APC_0: 0xffffffff
9918 13:12:17.982448 INFO: [APUAPC] D11_APC_1: 0xffffffff
9919 13:12:17.985427 INFO: [APUAPC] D11_APC_2: 0x3fffff
9920 13:12:17.988911 INFO: [APUAPC] D11_APC_3: 0x0
9921 13:12:17.991976 INFO: [APUAPC] D12_APC_0: 0xffffffff
9922 13:12:17.995626 INFO: [APUAPC] D12_APC_1: 0xffffffff
9923 13:12:17.998649 INFO: [APUAPC] D12_APC_2: 0x3fffff
9924 13:12:18.002095 INFO: [APUAPC] D12_APC_3: 0x0
9925 13:12:18.005544 INFO: [APUAPC] D13_APC_0: 0xffffffff
9926 13:12:18.008549 INFO: [APUAPC] D13_APC_1: 0xffffffff
9927 13:12:18.011598 INFO: [APUAPC] D13_APC_2: 0x3fffff
9928 13:12:18.015244 INFO: [APUAPC] D13_APC_3: 0x0
9929 13:12:18.018392 INFO: [APUAPC] D14_APC_0: 0xffffffff
9930 13:12:18.021488 INFO: [APUAPC] D14_APC_1: 0xffffffff
9931 13:12:18.025191 INFO: [APUAPC] D14_APC_2: 0x3fffff
9932 13:12:18.028008 INFO: [APUAPC] D14_APC_3: 0x0
9933 13:12:18.031347 INFO: [APUAPC] D15_APC_0: 0xffffffff
9934 13:12:18.034935 INFO: [APUAPC] D15_APC_1: 0xffffffff
9935 13:12:18.038492 INFO: [APUAPC] D15_APC_2: 0x3fffff
9936 13:12:18.041538 INFO: [APUAPC] D15_APC_3: 0x0
9937 13:12:18.044526 INFO: [APUAPC] APC_CON: 0x4
9938 13:12:18.048188 INFO: [NOCDAPC] D0_APC_0: 0x0
9939 13:12:18.051204 INFO: [NOCDAPC] D0_APC_1: 0x0
9940 13:12:18.054780 INFO: [NOCDAPC] D1_APC_0: 0x0
9941 13:12:18.058303 INFO: [NOCDAPC] D1_APC_1: 0xfff
9942 13:12:18.058408 INFO: [NOCDAPC] D2_APC_0: 0x0
9943 13:12:18.061208 INFO: [NOCDAPC] D2_APC_1: 0xfff
9944 13:12:18.064646 INFO: [NOCDAPC] D3_APC_0: 0x0
9945 13:12:18.067703 INFO: [NOCDAPC] D3_APC_1: 0xfff
9946 13:12:18.071334 INFO: [NOCDAPC] D4_APC_0: 0x0
9947 13:12:18.074327 INFO: [NOCDAPC] D4_APC_1: 0xfff
9948 13:12:18.077890 INFO: [NOCDAPC] D5_APC_0: 0x0
9949 13:12:18.080778 INFO: [NOCDAPC] D5_APC_1: 0xfff
9950 13:12:18.084206 INFO: [NOCDAPC] D6_APC_0: 0x0
9951 13:12:18.087577 INFO: [NOCDAPC] D6_APC_1: 0xfff
9952 13:12:18.091232 INFO: [NOCDAPC] D7_APC_0: 0x0
9953 13:12:18.094305 INFO: [NOCDAPC] D7_APC_1: 0xfff
9954 13:12:18.094418 INFO: [NOCDAPC] D8_APC_0: 0x0
9955 13:12:18.097335 INFO: [NOCDAPC] D8_APC_1: 0xfff
9956 13:12:18.100546 INFO: [NOCDAPC] D9_APC_0: 0x0
9957 13:12:18.103977 INFO: [NOCDAPC] D9_APC_1: 0xfff
9958 13:12:18.107309 INFO: [NOCDAPC] D10_APC_0: 0x0
9959 13:12:18.110625 INFO: [NOCDAPC] D10_APC_1: 0xfff
9960 13:12:18.113775 INFO: [NOCDAPC] D11_APC_0: 0x0
9961 13:12:18.117287 INFO: [NOCDAPC] D11_APC_1: 0xfff
9962 13:12:18.120312 INFO: [NOCDAPC] D12_APC_0: 0x0
9963 13:12:18.123938 INFO: [NOCDAPC] D12_APC_1: 0xfff
9964 13:12:18.126901 INFO: [NOCDAPC] D13_APC_0: 0x0
9965 13:12:18.130447 INFO: [NOCDAPC] D13_APC_1: 0xfff
9966 13:12:18.133928 INFO: [NOCDAPC] D14_APC_0: 0x0
9967 13:12:18.137297 INFO: [NOCDAPC] D14_APC_1: 0xfff
9968 13:12:18.140184 INFO: [NOCDAPC] D15_APC_0: 0x0
9969 13:12:18.140298 INFO: [NOCDAPC] D15_APC_1: 0xfff
9970 13:12:18.143827 INFO: [NOCDAPC] APC_CON: 0x4
9971 13:12:18.146843 INFO: [APUAPC] set_apusys_apc done
9972 13:12:18.150335 INFO: [DEVAPC] devapc_init done
9973 13:12:18.156431 INFO: GICv3 without legacy support detected.
9974 13:12:18.160080 INFO: ARM GICv3 driver initialized in EL3
9975 13:12:18.163567 INFO: Maximum SPI INTID supported: 639
9976 13:12:18.166612 INFO: BL31: Initializing runtime services
9977 13:12:18.172897 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9978 13:12:18.176661 INFO: SPM: enable CPC mode
9979 13:12:18.179514 INFO: mcdi ready for mcusys-off-idle and system suspend
9980 13:12:18.186256 INFO: BL31: Preparing for EL3 exit to normal world
9981 13:12:18.189773 INFO: Entry point address = 0x80000000
9982 13:12:18.189897 INFO: SPSR = 0x8
9983 13:12:18.196960
9984 13:12:18.197088
9985 13:12:18.197201
9986 13:12:18.198039 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
9987 13:12:18.198185 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
9988 13:12:18.198304 Setting prompt string to ['asurada:']
9989 13:12:18.198414 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
9990 13:12:18.200403 Starting depthcharge on Spherion...
9991 13:12:18.200514
9992 13:12:18.200614 Wipe memory regions:
9993 13:12:18.200712
9994 13:12:18.203317 [0x00000040000000, 0x00000054600000)
9995 13:12:18.325884
9996 13:12:18.326059 [0x00000054660000, 0x00000080000000)
9997 13:12:18.586469
9998 13:12:18.586644 [0x000000821a7280, 0x000000ffe64000)
9999 13:12:19.331371
10000 13:12:19.331584 [0x00000100000000, 0x00000240000000)
10001 13:12:21.221422
10002 13:12:21.224924 Initializing XHCI USB controller at 0x11200000.
10003 13:12:22.262613
10004 13:12:22.265821 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10005 13:12:22.265944
10006 13:12:22.266030
10007 13:12:22.266325 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10008 13:12:22.266423 Sending line: 'tftpboot 192.168.201.1 14879019/tftp-deploy-b23ufq6g/kernel/image.itb 14879019/tftp-deploy-b23ufq6g/kernel/cmdline '
10010 13:12:22.366929 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10011 13:12:22.367035 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10012 13:12:22.371629 asurada: tftpboot 192.168.201.1 14879019/tftp-deploy-b23ufq6g/kernel/image.ittp-deploy-b23ufq6g/kernel/cmdline
10013 13:12:22.371734
10014 13:12:22.371828 Waiting for link
10015 13:12:22.529576
10016 13:12:22.529730 R8152: Initializing
10017 13:12:22.529822
10018 13:12:22.532585 Version 6 (ocp_data = 5c30)
10019 13:12:22.532762
10020 13:12:22.536299 R8152: Done initializing
10021 13:12:22.536456
10022 13:12:22.536580 Adding net device
10023 13:12:24.472424
10024 13:12:24.472576 done.
10025 13:12:24.472663
10026 13:12:24.472722 MAC: 00:24:32:30:7c:7b
10027 13:12:24.472792
10028 13:12:24.475849 Sending DHCP discover... done.
10029 13:12:24.475934
10030 13:12:24.478982 Waiting for reply... done.
10031 13:12:24.479110
10032 13:12:24.482101 Sending DHCP request... done.
10033 13:12:24.482229
10034 13:12:25.167287 Waiting for reply... done.
10035 13:12:25.167430
10036 13:12:25.167522 My ip is 192.168.201.14
10037 13:12:25.167609
10038 13:12:25.170354 The DHCP server ip is 192.168.201.1
10039 13:12:25.170462
10040 13:12:25.176730 TFTP server IP predefined by user: 192.168.201.1
10041 13:12:25.176866
10042 13:12:25.183648 Bootfile predefined by user: 14879019/tftp-deploy-b23ufq6g/kernel/image.itb
10043 13:12:25.183776
10044 13:12:25.186611 Sending tftp read request... done.
10045 13:12:25.186757
10046 13:12:25.190927 Waiting for the transfer...
10047 13:12:25.191031
10048 13:12:25.796930 00000000 ################################################################
10049 13:12:25.797089
10050 13:12:26.399575 00080000 ################################################################
10051 13:12:26.399742
10052 13:12:26.991272 00100000 ################################################################
10053 13:12:26.991435
10054 13:12:27.593565 00180000 ################################################################
10055 13:12:27.593720
10056 13:12:28.145214 00200000 ################################################################
10057 13:12:28.145345
10058 13:12:28.665030 00280000 ################################################################
10059 13:12:28.665179
10060 13:12:29.182959 00300000 ################################################################
10061 13:12:29.183113
10062 13:12:29.697381 00380000 ################################################################
10063 13:12:29.697534
10064 13:12:30.216677 00400000 ################################################################
10065 13:12:30.216823
10066 13:12:30.737742 00480000 ################################################################
10067 13:12:30.737858
10068 13:12:31.260612 00500000 ################################################################
10069 13:12:31.260782
10070 13:12:31.778221 00580000 ################################################################
10071 13:12:31.778381
10072 13:12:32.292849 00600000 ################################################################
10073 13:12:32.292996
10074 13:12:32.804629 00680000 ################################################################
10075 13:12:32.804777
10076 13:12:33.316199 00700000 ################################################################
10077 13:12:33.316348
10078 13:12:33.833814 00780000 ################################################################
10079 13:12:33.833958
10080 13:12:34.367281 00800000 ################################################################
10081 13:12:34.367438
10082 13:12:34.910182 00880000 ################################################################
10083 13:12:34.910328
10084 13:12:35.436399 00900000 ################################################################
10085 13:12:35.436551
10086 13:12:35.958100 00980000 ################################################################
10087 13:12:35.958270
10088 13:12:36.492963 00a00000 ################################################################
10089 13:12:36.493119
10090 13:12:37.038004 00a80000 ################################################################
10091 13:12:37.038184
10092 13:12:37.570167 00b00000 ################################################################
10093 13:12:37.570343
10094 13:12:38.099775 00b80000 ################################################################
10095 13:12:38.099946
10096 13:12:38.618397 00c00000 ################################################################
10097 13:12:38.618552
10098 13:12:39.138195 00c80000 ################################################################
10099 13:12:39.138370
10100 13:12:39.656664 00d00000 ################################################################
10101 13:12:39.656832
10102 13:12:40.176111 00d80000 ################################################################
10103 13:12:40.176265
10104 13:12:40.693682 00e00000 ################################################################
10105 13:12:40.693848
10106 13:12:41.211481 00e80000 ################################################################
10107 13:12:41.211652
10108 13:12:41.732062 00f00000 ################################################################
10109 13:12:41.732216
10110 13:12:42.247613 00f80000 ################################################################
10111 13:12:42.247758
10112 13:12:42.763099 01000000 ################################################################
10113 13:12:42.763266
10114 13:12:43.280771 01080000 ################################################################
10115 13:12:43.280930
10116 13:12:43.795866 01100000 ################################################################
10117 13:12:43.796029
10118 13:12:44.311480 01180000 ################################################################
10119 13:12:44.311637
10120 13:12:44.830190 01200000 ################################################################
10121 13:12:44.830402
10122 13:12:45.351428 01280000 ################################################################
10123 13:12:45.351586
10124 13:12:45.872060 01300000 ################################################################
10125 13:12:45.872220
10126 13:12:46.394546 01380000 ################################################################
10127 13:12:46.394706
10128 13:12:46.918180 01400000 ################################################################
10129 13:12:46.918341
10130 13:12:47.437870 01480000 ################################################################
10131 13:12:47.438026
10132 13:12:47.959909 01500000 ################################################################
10133 13:12:47.960054
10134 13:12:48.481957 01580000 ################################################################
10135 13:12:48.482134
10136 13:12:49.001277 01600000 ################################################################
10137 13:12:49.001426
10138 13:12:49.520580 01680000 ################################################################
10139 13:12:49.520728
10140 13:12:50.038405 01700000 ################################################################
10141 13:12:50.038561
10142 13:12:50.562227 01780000 ################################################################
10143 13:12:50.562341
10144 13:12:51.082085 01800000 ################################################################
10145 13:12:51.082201
10146 13:12:51.606295 01880000 ################################################################
10147 13:12:51.606409
10148 13:12:52.124405 01900000 ################################################################
10149 13:12:52.124540
10150 13:12:52.651465 01980000 ################################################################
10151 13:12:52.651607
10152 13:12:53.175292 01a00000 ################################################################
10153 13:12:53.175409
10154 13:12:53.696232 01a80000 ################################################################
10155 13:12:53.696342
10156 13:12:54.217262 01b00000 ################################################################
10157 13:12:54.217373
10158 13:12:54.741582 01b80000 ################################################################
10159 13:12:54.741695
10160 13:12:55.263495 01c00000 ################################################################
10161 13:12:55.263634
10162 13:12:55.783901 01c80000 ################################################################
10163 13:12:55.784044
10164 13:12:56.302774 01d00000 ################################################################
10165 13:12:56.302914
10166 13:12:56.823192 01d80000 ################################################################
10167 13:12:56.823308
10168 13:12:57.346329 01e00000 ################################################################
10169 13:12:57.346446
10170 13:12:57.864727 01e80000 ################################################################
10171 13:12:57.864863
10172 13:12:58.382505 01f00000 ################################################################
10173 13:12:58.382653
10174 13:12:58.896074 01f80000 ################################################################
10175 13:12:58.896190
10176 13:12:59.416010 02000000 ################################################################
10177 13:12:59.416133
10178 13:12:59.940059 02080000 ################################################################
10179 13:12:59.940195
10180 13:13:00.469211 02100000 ################################################################
10181 13:13:00.469356
10182 13:13:00.988015 02180000 ################################################################
10183 13:13:00.988161
10184 13:13:01.505426 02200000 ################################################################
10185 13:13:01.505575
10186 13:13:02.022091 02280000 ################################################################
10187 13:13:02.022215
10188 13:13:02.529114 02300000 ################################################################
10189 13:13:02.529268
10190 13:13:03.050957 02380000 ################################################################
10191 13:13:03.051105
10192 13:13:03.561088 02400000 ################################################################
10193 13:13:03.561238
10194 13:13:04.075380 02480000 ################################################################
10195 13:13:04.075523
10196 13:13:04.586359 02500000 ################################################################
10197 13:13:04.586477
10198 13:13:05.097870 02580000 ################################################################
10199 13:13:05.097991
10200 13:13:05.616964 02600000 ################################################################
10201 13:13:05.617092
10202 13:13:06.130246 02680000 ################################################################
10203 13:13:06.130386
10204 13:13:06.642622 02700000 ################################################################
10205 13:13:06.642763
10206 13:13:07.155459 02780000 ################################################################
10207 13:13:07.155575
10208 13:13:07.670035 02800000 ################################################################
10209 13:13:07.670148
10210 13:13:08.183153 02880000 ################################################################
10211 13:13:08.183309
10212 13:13:08.698040 02900000 ################################################################
10213 13:13:08.698188
10214 13:13:09.219161 02980000 ################################################################
10215 13:13:09.219280
10216 13:13:09.740391 02a00000 ################################################################
10217 13:13:09.740531
10218 13:13:10.254561 02a80000 ################################################################
10219 13:13:10.254703
10220 13:13:10.769966 02b00000 ################################################################
10221 13:13:10.770121
10222 13:13:11.283316 02b80000 ################################################################
10223 13:13:11.283457
10224 13:13:11.797175 02c00000 ################################################################
10225 13:13:11.797283
10226 13:13:12.313925 02c80000 ################################################################
10227 13:13:12.314070
10228 13:13:12.833028 02d00000 ################################################################
10229 13:13:12.833217
10230 13:13:13.352435 02d80000 ################################################################
10231 13:13:13.352579
10232 13:13:13.880178 02e00000 ################################################################
10233 13:13:13.880329
10234 13:13:14.402970 02e80000 ################################################################
10235 13:13:14.403091
10236 13:13:14.930636 02f00000 ################################################################
10237 13:13:14.930767
10238 13:13:15.482528 02f80000 ################################################################
10239 13:13:15.482665
10240 13:13:16.037965 03000000 ################################################################
10241 13:13:16.038080
10242 13:13:16.569929 03080000 ################################################################
10243 13:13:16.570069
10244 13:13:17.091114 03100000 ################################################################
10245 13:13:17.091228
10246 13:13:17.626532 03180000 ################################################################
10247 13:13:17.626674
10248 13:13:18.183925 03200000 ################################################################
10249 13:13:18.184066
10250 13:13:18.718508 03280000 ################################################################
10251 13:13:18.718619
10252 13:13:19.249344 03300000 ################################################################
10253 13:13:19.249465
10254 13:13:19.776895 03380000 ################################################################
10255 13:13:19.777023
10256 13:13:20.308252 03400000 ################################################################
10257 13:13:20.308373
10258 13:13:20.835431 03480000 ################################################################
10259 13:13:20.835571
10260 13:13:21.364700 03500000 ################################################################
10261 13:13:21.364836
10262 13:13:21.902322 03580000 ################################################################
10263 13:13:21.902466
10264 13:13:22.429411 03600000 ################################################################
10265 13:13:22.429535
10266 13:13:22.961322 03680000 ################################################################
10267 13:13:22.961439
10268 13:13:23.490962 03700000 ################################################################
10269 13:13:23.491078
10270 13:13:24.019521 03780000 ################################################################
10271 13:13:24.019681
10272 13:13:24.550084 03800000 ################################################################
10273 13:13:24.550221
10274 13:13:25.083784 03880000 ################################################################
10275 13:13:25.083899
10276 13:13:25.614141 03900000 ################################################################
10277 13:13:25.614272
10278 13:13:26.146497 03980000 ################################################################
10279 13:13:26.146630
10280 13:13:26.679398 03a00000 ################################################################
10281 13:13:26.679524
10282 13:13:27.208663 03a80000 ################################################################
10283 13:13:27.208826
10284 13:13:27.734186 03b00000 ################################################################
10285 13:13:27.734304
10286 13:13:28.261020 03b80000 ################################################################
10287 13:13:28.261173
10288 13:13:28.787697 03c00000 ################################################################
10289 13:13:28.787828
10290 13:13:29.318492 03c80000 ################################################################
10291 13:13:29.318607
10292 13:13:29.847937 03d00000 ################################################################
10293 13:13:29.848090
10294 13:13:30.378623 03d80000 ################################################################
10295 13:13:30.378743
10296 13:13:30.912012 03e00000 ################################################################
10297 13:13:30.912168
10298 13:13:31.443835 03e80000 ################################################################
10299 13:13:31.443971
10300 13:13:31.977187 03f00000 ################################################################
10301 13:13:31.977315
10302 13:13:32.509448 03f80000 ################################################################
10303 13:13:32.509610
10304 13:13:33.037630 04000000 ################################################################
10305 13:13:33.037783
10306 13:13:33.573803 04080000 ################################################################
10307 13:13:33.573923
10308 13:13:34.114042 04100000 ################################################################
10309 13:13:34.114187
10310 13:13:34.650051 04180000 ################################################################
10311 13:13:34.650166
10312 13:13:35.178121 04200000 ################################################################
10313 13:13:35.178259
10314 13:13:35.704874 04280000 ################################################################
10315 13:13:35.705017
10316 13:13:36.229304 04300000 ################################################################
10317 13:13:36.229447
10318 13:13:36.754670 04380000 ################################################################
10319 13:13:36.754784
10320 13:13:37.279271 04400000 ################################################################
10321 13:13:37.279413
10322 13:13:37.802696 04480000 ################################################################
10323 13:13:37.802836
10324 13:13:38.334039 04500000 ################################################################
10325 13:13:38.334157
10326 13:13:38.859870 04580000 ################################################################
10327 13:13:38.859988
10328 13:13:39.385850 04600000 ################################################################
10329 13:13:39.385994
10330 13:13:39.609124 04680000 ############################ done.
10331 13:13:39.612391
10332 13:13:39.612472 The bootfile was 74148646 bytes long.
10333 13:13:39.615773
10334 13:13:39.615892 Sending tftp read request... done.
10335 13:13:39.615981
10336 13:13:39.618878 Waiting for the transfer...
10337 13:13:39.618958
10338 13:13:39.622697 00000000 # done.
10339 13:13:39.622778
10340 13:13:39.628643 Command line loaded dynamically from TFTP file: 14879019/tftp-deploy-b23ufq6g/kernel/cmdline
10341 13:13:39.628764
10342 13:13:39.641791 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10343 13:13:39.641918
10344 13:13:39.645224 Loading FIT.
10345 13:13:39.645299
10346 13:13:39.648714 Image ramdisk-1 has 60984890 bytes.
10347 13:13:39.648823
10348 13:13:39.648914 Image fdt-1 has 47258 bytes.
10349 13:13:39.649003
10350 13:13:39.651667 Image kernel-1 has 13114469 bytes.
10351 13:13:39.651760
10352 13:13:39.662229 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10353 13:13:39.662328
10354 13:13:39.678375 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10355 13:13:39.678511
10356 13:13:39.684686 Choosing best match conf-1 for compat google,spherion-rev2.
10357 13:13:39.689356
10358 13:13:39.693934 Connected to device vid:did:rid of 1ae0:0028:00
10359 13:13:39.701634
10360 13:13:39.704941 tpm_get_response: command 0x17b, return code 0x0
10361 13:13:39.705081
10362 13:13:39.708140 ec_init: CrosEC protocol v3 supported (256, 248)
10363 13:13:39.712071
10364 13:13:39.716085 tpm_cleanup: add release locality here.
10365 13:13:39.716166
10366 13:13:39.716223 Shutting down all USB controllers.
10367 13:13:39.718767
10368 13:13:39.718890 Removing current net device
10369 13:13:39.718949
10370 13:13:39.725384 Exiting depthcharge with code 4 at timestamp: 110726343
10371 13:13:39.725489
10372 13:13:39.729313 LZMA decompressing kernel-1 to 0x821a6718
10373 13:13:39.729395
10374 13:13:39.732401 LZMA decompressing kernel-1 to 0x40000000
10375 13:13:41.347745
10376 13:13:41.347860 jumping to kernel
10377 13:13:41.348916 end: 2.2.4 bootloader-commands (duration 00:01:23) [common]
10378 13:13:41.349039 start: 2.2.5 auto-login-action (timeout 00:02:57) [common]
10379 13:13:41.349147 Setting prompt string to ['Linux version [0-9]']
10380 13:13:41.349215 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10381 13:13:41.349281 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10382 13:13:41.428274
10383 13:13:41.431357 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10384 13:13:41.434870 start: 2.2.5.1 login-action (timeout 00:02:57) [common]
10385 13:13:41.434967 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10386 13:13:41.435036 Setting prompt string to []
10387 13:13:41.435109 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10388 13:13:41.435178 Using line separator: #'\n'#
10389 13:13:41.435236 No login prompt set.
10390 13:13:41.435298 Parsing kernel messages
10391 13:13:41.435350 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10392 13:13:41.435451 [login-action] Waiting for messages, (timeout 00:02:57)
10393 13:13:41.435518 Waiting using forced prompt support (timeout 00:01:28)
10394 13:13:41.454879 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j272990-arm64-gcc-12-defconfig-arm64-chromebook-fgzcq) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024
10395 13:13:41.457939 [ 0.000000] random: crng init done
10396 13:13:41.461178 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10397 13:13:41.464744 [ 0.000000] efi: UEFI not found.
10398 13:13:41.474304 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10399 13:13:41.481109 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10400 13:13:41.490893 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10401 13:13:41.501285 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10402 13:13:41.507774 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10403 13:13:41.510857 [ 0.000000] printk: bootconsole [mtk8250] enabled
10404 13:13:41.519293 [ 0.000000] NUMA: No NUMA configuration found
10405 13:13:41.526227 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10406 13:13:41.532851 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10407 13:13:41.532935 [ 0.000000] Zone ranges:
10408 13:13:41.539431 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10409 13:13:41.542698 [ 0.000000] DMA32 empty
10410 13:13:41.549250 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10411 13:13:41.552634 [ 0.000000] Movable zone start for each node
10412 13:13:41.555893 [ 0.000000] Early memory node ranges
10413 13:13:41.562295 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10414 13:13:41.569521 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10415 13:13:41.575738 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10416 13:13:41.582442 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10417 13:13:41.588988 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10418 13:13:41.595837 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10419 13:13:41.652725 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10420 13:13:41.659330 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10421 13:13:41.666361 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10422 13:13:41.669483 [ 0.000000] psci: probing for conduit method from DT.
10423 13:13:41.676058 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10424 13:13:41.679150 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10425 13:13:41.686088 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10426 13:13:41.689157 [ 0.000000] psci: SMC Calling Convention v1.2
10427 13:13:41.696044 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10428 13:13:41.698964 [ 0.000000] Detected VIPT I-cache on CPU0
10429 13:13:41.706087 [ 0.000000] CPU features: detected: GIC system register CPU interface
10430 13:13:41.712718 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10431 13:13:41.719315 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10432 13:13:41.725783 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10433 13:13:41.732194 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10434 13:13:41.742408 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10435 13:13:41.745897 [ 0.000000] alternatives: applying boot alternatives
10436 13:13:41.752077 [ 0.000000] Fallback order for Node 0: 0
10437 13:13:41.759174 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10438 13:13:41.762600 [ 0.000000] Policy zone: Normal
10439 13:13:41.775462 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10440 13:13:41.785049 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10441 13:13:41.797249 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10442 13:13:41.807289 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10443 13:13:41.814280 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10444 13:13:41.817448 <6>[ 0.000000] software IO TLB: area num 8.
10445 13:13:41.874462 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10446 13:13:42.023542 <6>[ 0.000000] Memory: 7904500K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 448268K reserved, 32768K cma-reserved)
10447 13:13:42.030135 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10448 13:13:42.036326 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10449 13:13:42.040156 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10450 13:13:42.046518 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10451 13:13:42.053190 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10452 13:13:42.056422 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10453 13:13:42.066131 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10454 13:13:42.073224 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10455 13:13:42.079501 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10456 13:13:42.086351 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10457 13:13:42.089617 <6>[ 0.000000] GICv3: 608 SPIs implemented
10458 13:13:42.092908 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10459 13:13:42.099394 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10460 13:13:42.102611 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10461 13:13:42.109272 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10462 13:13:42.122509 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10463 13:13:42.136133 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10464 13:13:42.142357 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10465 13:13:42.149966 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10466 13:13:42.163132 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10467 13:13:42.170065 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10468 13:13:42.176863 <6>[ 0.009178] Console: colour dummy device 80x25
10469 13:13:42.186719 <6>[ 0.013899] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10470 13:13:42.190052 <6>[ 0.024341] pid_max: default: 32768 minimum: 301
10471 13:13:42.196330 <6>[ 0.029213] LSM: Security Framework initializing
10472 13:13:42.202928 <6>[ 0.034181] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10473 13:13:42.212772 <6>[ 0.041994] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10474 13:13:42.219560 <6>[ 0.051468] cblist_init_generic: Setting adjustable number of callback queues.
10475 13:13:42.226412 <6>[ 0.058910] cblist_init_generic: Setting shift to 3 and lim to 1.
10476 13:13:42.235975 <6>[ 0.065289] cblist_init_generic: Setting adjustable number of callback queues.
10477 13:13:42.242630 <6>[ 0.072716] cblist_init_generic: Setting shift to 3 and lim to 1.
10478 13:13:42.245882 <6>[ 0.079117] rcu: Hierarchical SRCU implementation.
10479 13:13:42.252824 <6>[ 0.084133] rcu: Max phase no-delay instances is 1000.
10480 13:13:42.259193 <6>[ 0.091153] EFI services will not be available.
10481 13:13:42.262599 <6>[ 0.096111] smp: Bringing up secondary CPUs ...
10482 13:13:42.270933 <6>[ 0.101162] Detected VIPT I-cache on CPU1
10483 13:13:42.277421 <6>[ 0.101234] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10484 13:13:42.283816 <6>[ 0.101265] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10485 13:13:42.287260 <6>[ 0.101607] Detected VIPT I-cache on CPU2
10486 13:13:42.293994 <6>[ 0.101659] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10487 13:13:42.303590 <6>[ 0.101676] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10488 13:13:42.306833 <6>[ 0.101938] Detected VIPT I-cache on CPU3
10489 13:13:42.313368 <6>[ 0.101987] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10490 13:13:42.319956 <6>[ 0.102002] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10491 13:13:42.323843 <6>[ 0.102305] CPU features: detected: Spectre-v4
10492 13:13:42.330123 <6>[ 0.102312] CPU features: detected: Spectre-BHB
10493 13:13:42.333331 <6>[ 0.102318] Detected PIPT I-cache on CPU4
10494 13:13:42.339797 <6>[ 0.102381] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10495 13:13:42.346860 <6>[ 0.102398] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10496 13:13:42.353109 <6>[ 0.102696] Detected PIPT I-cache on CPU5
10497 13:13:42.359644 <6>[ 0.102759] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10498 13:13:42.366222 <6>[ 0.102775] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10499 13:13:42.370108 <6>[ 0.103058] Detected PIPT I-cache on CPU6
10500 13:13:42.376623 <6>[ 0.103125] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10501 13:13:42.382964 <6>[ 0.103141] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10502 13:13:42.389954 <6>[ 0.103440] Detected PIPT I-cache on CPU7
10503 13:13:42.396172 <6>[ 0.103506] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10504 13:13:42.403154 <6>[ 0.103522] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10505 13:13:42.406226 <6>[ 0.103570] smp: Brought up 1 node, 8 CPUs
10506 13:13:42.412672 <6>[ 0.244928] SMP: Total of 8 processors activated.
10507 13:13:42.416000 <6>[ 0.249848] CPU features: detected: 32-bit EL0 Support
10508 13:13:42.426024 <6>[ 0.255211] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10509 13:13:42.432473 <6>[ 0.264067] CPU features: detected: Common not Private translations
10510 13:13:42.439359 <6>[ 0.270543] CPU features: detected: CRC32 instructions
10511 13:13:42.442702 <6>[ 0.275894] CPU features: detected: RCpc load-acquire (LDAPR)
10512 13:13:42.449114 <6>[ 0.281854] CPU features: detected: LSE atomic instructions
10513 13:13:42.456033 <6>[ 0.287636] CPU features: detected: Privileged Access Never
10514 13:13:42.462411 <6>[ 0.293451] CPU features: detected: RAS Extension Support
10515 13:13:42.469053 <6>[ 0.299094] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10516 13:13:42.472287 <6>[ 0.306360] CPU: All CPU(s) started at EL2
10517 13:13:42.478763 <6>[ 0.310676] alternatives: applying system-wide alternatives
10518 13:13:42.488258 <6>[ 0.321556] devtmpfs: initialized
10519 13:13:42.503921 <6>[ 0.330458] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10520 13:13:42.511004 <6>[ 0.340418] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10521 13:13:42.517408 <6>[ 0.348678] pinctrl core: initialized pinctrl subsystem
10522 13:13:42.520732 <6>[ 0.355353] DMI not present or invalid.
10523 13:13:42.527249 <6>[ 0.359764] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10524 13:13:42.536796 <6>[ 0.366597] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10525 13:13:42.543504 <6>[ 0.374180] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10526 13:13:42.553291 <6>[ 0.382407] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10527 13:13:42.557067 <6>[ 0.390646] audit: initializing netlink subsys (disabled)
10528 13:13:42.566427 <5>[ 0.396339] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10529 13:13:42.573553 <6>[ 0.397048] thermal_sys: Registered thermal governor 'step_wise'
10530 13:13:42.580108 <6>[ 0.404307] thermal_sys: Registered thermal governor 'power_allocator'
10531 13:13:42.583314 <6>[ 0.410561] cpuidle: using governor menu
10532 13:13:42.589781 <6>[ 0.421518] NET: Registered PF_QIPCRTR protocol family
10533 13:13:42.596358 <6>[ 0.427009] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10534 13:13:42.603369 <6>[ 0.434114] ASID allocator initialised with 32768 entries
10535 13:13:42.606575 <6>[ 0.440693] Serial: AMBA PL011 UART driver
10536 13:13:42.617323 <4>[ 0.450035] Trying to register duplicate clock ID: 134
10537 13:13:42.674748 <6>[ 0.511276] KASLR enabled
10538 13:13:42.689130 <6>[ 0.518916] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10539 13:13:42.696063 <6>[ 0.525932] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10540 13:13:42.702542 <6>[ 0.532419] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10541 13:13:42.708953 <6>[ 0.539423] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10542 13:13:42.715465 <6>[ 0.545908] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10543 13:13:42.722488 <6>[ 0.552915] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10544 13:13:42.728945 <6>[ 0.559402] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10545 13:13:42.735410 <6>[ 0.566403] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10546 13:13:42.738803 <6>[ 0.573865] ACPI: Interpreter disabled.
10547 13:13:42.747233 <6>[ 0.580289] iommu: Default domain type: Translated
10548 13:13:42.754282 <6>[ 0.585441] iommu: DMA domain TLB invalidation policy: strict mode
10549 13:13:42.757210 <5>[ 0.592091] SCSI subsystem initialized
10550 13:13:42.763662 <6>[ 0.596336] usbcore: registered new interface driver usbfs
10551 13:13:42.770776 <6>[ 0.602066] usbcore: registered new interface driver hub
10552 13:13:42.774012 <6>[ 0.607617] usbcore: registered new device driver usb
10553 13:13:42.780636 <6>[ 0.613745] pps_core: LinuxPPS API ver. 1 registered
10554 13:13:42.790554 <6>[ 0.618936] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10555 13:13:42.793671 <6>[ 0.628279] PTP clock support registered
10556 13:13:42.796946 <6>[ 0.632522] EDAC MC: Ver: 3.0.0
10557 13:13:42.804671 <6>[ 0.637723] FPGA manager framework
10558 13:13:42.811297 <6>[ 0.641401] Advanced Linux Sound Architecture Driver Initialized.
10559 13:13:42.814713 <6>[ 0.648197] vgaarb: loaded
10560 13:13:42.821197 <6>[ 0.651354] clocksource: Switched to clocksource arch_sys_counter
10561 13:13:42.824884 <5>[ 0.657797] VFS: Disk quotas dquot_6.6.0
10562 13:13:42.831116 <6>[ 0.661983] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10563 13:13:42.834201 <6>[ 0.669181] pnp: PnP ACPI: disabled
10564 13:13:42.843238 <6>[ 0.675921] NET: Registered PF_INET protocol family
10565 13:13:42.852993 <6>[ 0.681518] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10566 13:13:42.864395 <6>[ 0.693834] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10567 13:13:42.874028 <6>[ 0.702652] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10568 13:13:42.880562 <6>[ 0.710619] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10569 13:13:42.890043 <6>[ 0.719322] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10570 13:13:42.897132 <6>[ 0.729071] TCP: Hash tables configured (established 65536 bind 65536)
10571 13:13:42.903678 <6>[ 0.735946] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10572 13:13:42.913506 <6>[ 0.743144] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10573 13:13:42.920014 <6>[ 0.750844] NET: Registered PF_UNIX/PF_LOCAL protocol family
10574 13:13:42.926629 <6>[ 0.756998] RPC: Registered named UNIX socket transport module.
10575 13:13:42.929790 <6>[ 0.763152] RPC: Registered udp transport module.
10576 13:13:42.936297 <6>[ 0.768086] RPC: Registered tcp transport module.
10577 13:13:42.943097 <6>[ 0.773018] RPC: Registered tcp NFSv4.1 backchannel transport module.
10578 13:13:42.946308 <6>[ 0.779682] PCI: CLS 0 bytes, default 64
10579 13:13:42.949560 <6>[ 0.784018] Unpacking initramfs...
10580 13:13:42.973909 <6>[ 0.803510] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10581 13:13:42.983658 <6>[ 0.812174] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10582 13:13:42.987014 <6>[ 0.821021] kvm [1]: IPA Size Limit: 40 bits
10583 13:13:42.993576 <6>[ 0.825552] kvm [1]: GICv3: no GICV resource entry
10584 13:13:42.996915 <6>[ 0.830574] kvm [1]: disabling GICv2 emulation
10585 13:13:43.003711 <6>[ 0.835261] kvm [1]: GIC system register CPU interface enabled
10586 13:13:43.006590 <6>[ 0.841421] kvm [1]: vgic interrupt IRQ18
10587 13:13:43.013387 <6>[ 0.845783] kvm [1]: VHE mode initialized successfully
10588 13:13:43.019965 <5>[ 0.852035] Initialise system trusted keyrings
10589 13:13:43.026277 <6>[ 0.856842] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10590 13:13:43.033503 <6>[ 0.866850] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10591 13:13:43.040246 <5>[ 0.873222] NFS: Registering the id_resolver key type
10592 13:13:43.044003 <5>[ 0.878519] Key type id_resolver registered
10593 13:13:43.050114 <5>[ 0.882933] Key type id_legacy registered
10594 13:13:43.056999 <6>[ 0.887215] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10595 13:13:43.063584 <6>[ 0.894135] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10596 13:13:43.070010 <6>[ 0.901868] 9p: Installing v9fs 9p2000 file system support
10597 13:13:43.106440 <5>[ 0.939717] Key type asymmetric registered
10598 13:13:43.110302 <5>[ 0.944048] Asymmetric key parser 'x509' registered
10599 13:13:43.119700 <6>[ 0.949197] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10600 13:13:43.123231 <6>[ 0.956812] io scheduler mq-deadline registered
10601 13:13:43.126490 <6>[ 0.961595] io scheduler kyber registered
10602 13:13:43.145637 <6>[ 0.978639] EINJ: ACPI disabled.
10603 13:13:43.177903 <4>[ 1.004396] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10604 13:13:43.188018 <4>[ 1.015040] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10605 13:13:43.203242 <6>[ 1.036121] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10606 13:13:43.210809 <6>[ 1.044142] printk: console [ttyS0] disabled
10607 13:13:43.238980 <6>[ 1.068769] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10608 13:13:43.245314 <6>[ 1.078252] printk: console [ttyS0] enabled
10609 13:13:43.248632 <6>[ 1.078252] printk: console [ttyS0] enabled
10610 13:13:43.255630 <6>[ 1.087148] printk: bootconsole [mtk8250] disabled
10611 13:13:43.258617 <6>[ 1.087148] printk: bootconsole [mtk8250] disabled
10612 13:13:43.265415 <6>[ 1.098398] SuperH (H)SCI(F) driver initialized
10613 13:13:43.268468 <6>[ 1.103673] msm_serial: driver initialized
10614 13:13:43.282609 <6>[ 1.112648] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10615 13:13:43.293061 <6>[ 1.121194] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10616 13:13:43.299244 <6>[ 1.129737] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10617 13:13:43.309531 <6>[ 1.138364] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10618 13:13:43.319321 <6>[ 1.147071] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10619 13:13:43.326126 <6>[ 1.155791] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10620 13:13:43.335884 <6>[ 1.164335] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10621 13:13:43.342744 <6>[ 1.173139] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10622 13:13:43.352208 <6>[ 1.181680] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10623 13:13:43.363900 <6>[ 1.197265] loop: module loaded
10624 13:13:43.370688 <6>[ 1.203205] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10625 13:13:43.393836 <4>[ 1.226667] mtk-pmic-keys: Failed to locate of_node [id: -1]
10626 13:13:43.400949 <6>[ 1.233785] megasas: 07.719.03.00-rc1
10627 13:13:43.410564 <6>[ 1.243674] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10628 13:13:43.417662 <6>[ 1.250745] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10629 13:13:43.434440 <6>[ 1.267531] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10630 13:13:43.491252 <6>[ 1.317949] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10631 13:13:45.678221 <6>[ 3.511803] Freeing initrd memory: 59552K
10632 13:13:45.689874 <6>[ 3.523449] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10633 13:13:45.701056 <6>[ 3.534129] tun: Universal TUN/TAP device driver, 1.6
10634 13:13:45.703849 <6>[ 3.540198] thunder_xcv, ver 1.0
10635 13:13:45.707377 <6>[ 3.543701] thunder_bgx, ver 1.0
10636 13:13:45.710424 <6>[ 3.547193] nicpf, ver 1.0
10637 13:13:45.721348 <6>[ 3.551203] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10638 13:13:45.724432 <6>[ 3.558679] hns3: Copyright (c) 2017 Huawei Corporation.
10639 13:13:45.731145 <6>[ 3.564266] hclge is initializing
10640 13:13:45.734916 <6>[ 3.567846] e1000: Intel(R) PRO/1000 Network Driver
10641 13:13:45.741467 <6>[ 3.572975] e1000: Copyright (c) 1999-2006 Intel Corporation.
10642 13:13:45.744848 <6>[ 3.578991] e1000e: Intel(R) PRO/1000 Network Driver
10643 13:13:45.751082 <6>[ 3.584207] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10644 13:13:45.757662 <6>[ 3.590392] igb: Intel(R) Gigabit Ethernet Network Driver
10645 13:13:45.764196 <6>[ 3.596042] igb: Copyright (c) 2007-2014 Intel Corporation.
10646 13:13:45.770674 <6>[ 3.601878] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10647 13:13:45.777129 <6>[ 3.608395] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10648 13:13:45.780880 <6>[ 3.614859] sky2: driver version 1.30
10649 13:13:45.787642 <6>[ 3.619792] usbcore: registered new device driver r8152-cfgselector
10650 13:13:45.794325 <6>[ 3.626330] usbcore: registered new interface driver r8152
10651 13:13:45.800857 <6>[ 3.632143] VFIO - User Level meta-driver version: 0.3
10652 13:13:45.806921 <6>[ 3.640376] usbcore: registered new interface driver usb-storage
10653 13:13:45.813710 <6>[ 3.646821] usbcore: registered new device driver onboard-usb-hub
10654 13:13:45.823359 <6>[ 3.655978] mt6397-rtc mt6359-rtc: registered as rtc0
10655 13:13:45.832554 <6>[ 3.661442] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-18T13:13:45 UTC (1721308425)
10656 13:13:45.836076 <6>[ 3.671001] i2c_dev: i2c /dev entries driver
10657 13:13:45.849584 <4>[ 3.682978] cpu cpu0: supply cpu not found, using dummy regulator
10658 13:13:45.856327 <4>[ 3.689420] cpu cpu1: supply cpu not found, using dummy regulator
10659 13:13:45.863147 <4>[ 3.695825] cpu cpu2: supply cpu not found, using dummy regulator
10660 13:13:45.869827 <4>[ 3.702221] cpu cpu3: supply cpu not found, using dummy regulator
10661 13:13:45.876279 <4>[ 3.708616] cpu cpu4: supply cpu not found, using dummy regulator
10662 13:13:45.882848 <4>[ 3.715017] cpu cpu5: supply cpu not found, using dummy regulator
10663 13:13:45.889120 <4>[ 3.721433] cpu cpu6: supply cpu not found, using dummy regulator
10664 13:13:45.895636 <4>[ 3.727830] cpu cpu7: supply cpu not found, using dummy regulator
10665 13:13:45.915128 <6>[ 3.748443] cpu cpu0: EM: created perf domain
10666 13:13:45.918244 <6>[ 3.753365] cpu cpu4: EM: created perf domain
10667 13:13:45.925528 <6>[ 3.758933] sdhci: Secure Digital Host Controller Interface driver
10668 13:13:45.932024 <6>[ 3.765364] sdhci: Copyright(c) Pierre Ossman
10669 13:13:45.938738 <6>[ 3.770325] Synopsys Designware Multimedia Card Interface Driver
10670 13:13:45.945697 <6>[ 3.776964] sdhci-pltfm: SDHCI platform and OF driver helper
10671 13:13:45.948612 <6>[ 3.777013] mmc0: CQHCI version 5.10
10672 13:13:45.955411 <6>[ 3.786898] ledtrig-cpu: registered to indicate activity on CPUs
10673 13:13:45.961959 <6>[ 3.793795] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10674 13:13:45.968371 <6>[ 3.800857] usbcore: registered new interface driver usbhid
10675 13:13:45.971628 <6>[ 3.806680] usbhid: USB HID core driver
10676 13:13:45.978328 <6>[ 3.810878] spi_master spi0: will run message pump with realtime priority
10677 13:13:46.027952 <6>[ 3.854808] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10678 13:13:46.046960 <6>[ 3.870401] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10679 13:13:46.050279 <6>[ 3.881688] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16014
10680 13:13:46.058407 <6>[ 3.891184] cros-ec-spi spi0.0: Chrome EC device registered
10681 13:13:46.064786 <6>[ 3.897202] mmc0: Command Queue Engine enabled
10682 13:13:46.071024 <6>[ 3.901928] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10683 13:13:46.074339 <6>[ 3.909309] mmcblk0: mmc0:0001 DA4128 116 GiB
10684 13:13:46.084789 <6>[ 3.910457] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10685 13:13:46.091184 <6>[ 3.917835] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10686 13:13:46.097515 <6>[ 3.924646] NET: Registered PF_PACKET protocol family
10687 13:13:46.101354 <6>[ 3.930645] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10688 13:13:46.107916 <6>[ 3.934654] 9pnet: Installing 9P2000 support
10689 13:13:46.110931 <6>[ 3.940422] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10690 13:13:46.114181 <5>[ 3.944346] Key type dns_resolver registered
10691 13:13:46.120641 <6>[ 3.950154] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10692 13:13:46.127915 <6>[ 3.954602] registered taskstats version 1
10693 13:13:46.131037 <5>[ 3.964955] Loading compiled-in X.509 certificates
10694 13:13:46.159369 <4>[ 3.986218] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10695 13:13:46.169132 <4>[ 3.996891] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10696 13:13:46.183478 <6>[ 4.016780] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10697 13:13:46.190070 <6>[ 4.023589] xhci-mtk 11200000.usb: xHCI Host Controller
10698 13:13:46.196596 <6>[ 4.029088] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10699 13:13:46.206840 <6>[ 4.036948] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10700 13:13:46.213328 <6>[ 4.046377] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10701 13:13:46.220338 <6>[ 4.052561] xhci-mtk 11200000.usb: xHCI Host Controller
10702 13:13:46.227061 <6>[ 4.058056] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10703 13:13:46.233496 <6>[ 4.065716] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10704 13:13:46.240039 <6>[ 4.073551] hub 1-0:1.0: USB hub found
10705 13:13:46.243782 <6>[ 4.077581] hub 1-0:1.0: 1 port detected
10706 13:13:46.253172 <6>[ 4.081859] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10707 13:13:46.256728 <6>[ 4.090641] hub 2-0:1.0: USB hub found
10708 13:13:46.259744 <6>[ 4.094663] hub 2-0:1.0: 1 port detected
10709 13:13:46.268805 <6>[ 4.102387] mtk-msdc 11f70000.mmc: Got CD GPIO
10710 13:13:46.281945 <6>[ 4.111982] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10711 13:13:46.291753 <6>[ 4.120356] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10712 13:13:46.298685 <6>[ 4.128697] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10713 13:13:46.308109 <6>[ 4.137043] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10714 13:13:46.314784 <6>[ 4.145382] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10715 13:13:46.324859 <6>[ 4.153722] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10716 13:13:46.331364 <6>[ 4.162061] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10717 13:13:46.341103 <6>[ 4.170400] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10718 13:13:46.347659 <6>[ 4.178740] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10719 13:13:46.358115 <6>[ 4.187083] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10720 13:13:46.364255 <6>[ 4.195422] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10721 13:13:46.374460 <6>[ 4.203765] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10722 13:13:46.381316 <6>[ 4.212104] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10723 13:13:46.390908 <6>[ 4.220444] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10724 13:13:46.397480 <6>[ 4.228784] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10725 13:13:46.404215 <6>[ 4.237426] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10726 13:13:46.411344 <6>[ 4.244607] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10727 13:13:46.418121 <6>[ 4.251386] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10728 13:13:46.428263 <6>[ 4.258186] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10729 13:13:46.434654 <6>[ 4.265120] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10730 13:13:46.441426 <6>[ 4.272002] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10731 13:13:46.451214 <6>[ 4.281138] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10732 13:13:46.460788 <6>[ 4.290271] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10733 13:13:46.471023 <6>[ 4.299566] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10734 13:13:46.481001 <6>[ 4.309033] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10735 13:13:46.490675 <6>[ 4.318500] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10736 13:13:46.497163 <6>[ 4.327624] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10737 13:13:46.507605 <6>[ 4.337091] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10738 13:13:46.516910 <6>[ 4.346210] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10739 13:13:46.527109 <6>[ 4.355505] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10740 13:13:46.537084 <6>[ 4.365664] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10741 13:13:46.547362 <6>[ 4.377541] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10742 13:13:46.673341 <6>[ 4.503632] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10743 13:13:46.827960 <6>[ 4.661680] hub 1-1:1.0: USB hub found
10744 13:13:46.831249 <6>[ 4.666185] hub 1-1:1.0: 4 ports detected
10745 13:13:46.843073 <6>[ 4.676721] hub 1-1:1.0: USB hub found
10746 13:13:46.846648 <6>[ 4.681022] hub 1-1:1.0: 4 ports detected
10747 13:13:46.953598 <6>[ 4.783652] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10748 13:13:46.980158 <6>[ 4.813557] hub 2-1:1.0: USB hub found
10749 13:13:46.983537 <6>[ 4.818059] hub 2-1:1.0: 3 ports detected
10750 13:13:46.994908 <6>[ 4.828394] hub 2-1:1.0: USB hub found
10751 13:13:46.998269 <6>[ 4.832838] hub 2-1:1.0: 3 ports detected
10752 13:13:47.165564 <6>[ 4.995612] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10753 13:13:47.297991 <6>[ 5.131246] hub 1-1.4:1.0: USB hub found
10754 13:13:47.300953 <6>[ 5.135825] hub 1-1.4:1.0: 2 ports detected
10755 13:13:47.316044 <6>[ 5.149333] hub 1-1.4:1.0: USB hub found
10756 13:13:47.319117 <6>[ 5.153932] hub 1-1.4:1.0: 2 ports detected
10757 13:13:47.377842 <6>[ 5.207888] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10758 13:13:47.485965 <6>[ 5.316312] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10759 13:13:47.522513 <4>[ 5.352547] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10760 13:13:47.531977 <4>[ 5.361642] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10761 13:13:47.567357 <6>[ 5.401093] r8152 2-1.3:1.0 eth0: v1.12.13
10762 13:13:47.617313 <6>[ 5.447481] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10763 13:13:47.813274 <6>[ 5.643583] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10764 13:13:49.154431 <6>[ 6.987846] r8152 2-1.3:1.0 eth0: carrier on
10765 13:13:51.785437 <5>[ 7.011413] Sending DHCP requests .., OK
10766 13:13:51.792381 <6>[ 9.623802] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10767 13:13:51.795479 <6>[ 9.632114] IP-Config: Complete:
10768 13:13:51.808362 <6>[ 9.635607] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10769 13:13:51.815672 <6>[ 9.646314] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10770 13:13:51.821615 <6>[ 9.654929] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10771 13:13:51.828539 <6>[ 9.654938] nameserver0=192.168.201.1
10772 13:13:51.831661 <6>[ 9.667017] clk: Disabling unused clocks
10773 13:13:51.835180 <6>[ 9.672475] ALSA device list:
10774 13:13:51.841455 <6>[ 9.675765] No soundcards found.
10775 13:13:51.849522 <6>[ 9.683448] Freeing unused kernel memory: 8512K
10776 13:13:51.852515 <6>[ 9.688382] Run /init as init process
10777 13:13:51.883373 <6>[ 9.717124] NET: Registered PF_INET6 protocol family
10778 13:13:51.889674 <6>[ 9.723886] Segment Routing with IPv6
10779 13:13:51.892936 <6>[ 9.727837] In-situ OAM (IOAM) with IPv6
10780 13:13:51.933741 <30>[ 9.741249] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10781 13:13:51.940839 <30>[ 9.774288] systemd[1]: Detected architecture arm64.
10782 13:13:51.941119
10783 13:13:51.947169 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10784 13:13:51.947523
10785 13:13:51.966568 <30>[ 9.799752] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10786 13:13:52.089922 <30>[ 9.920731] systemd[1]: Queued start job for default target graphical.target.
10787 13:13:52.142557 <30>[ 9.973213] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10788 13:13:52.149419 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10789 13:13:52.170195 <30>[ 10.000249] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10790 13:13:52.179590 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10791 13:13:52.197870 <30>[ 10.028546] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10792 13:13:52.207561 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10793 13:13:52.225616 <30>[ 10.056508] systemd[1]: Created slice user.slice - User and Session Slice.
10794 13:13:52.232592 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10795 13:13:52.252701 <30>[ 10.079801] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10796 13:13:52.259055 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10797 13:13:52.280499 <30>[ 10.107872] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10798 13:13:52.286898 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10799 13:13:52.315572 <30>[ 10.136197] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10800 13:13:52.325403 <30>[ 10.156090] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10801 13:13:52.332055 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10802 13:13:52.349022 <30>[ 10.179707] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10803 13:13:52.355710 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10804 13:13:52.372901 <30>[ 10.203698] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10805 13:13:52.382831 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10806 13:13:52.397798 <30>[ 10.231716] systemd[1]: Reached target paths.target - Path Units.
10807 13:13:52.407732 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10808 13:13:52.424930 <30>[ 10.255737] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10809 13:13:52.431224 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10810 13:13:52.445352 <30>[ 10.279637] systemd[1]: Reached target slices.target - Slice Units.
10811 13:13:52.455529 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10812 13:13:52.470493 <30>[ 10.304159] systemd[1]: Reached target swap.target - Swaps.
10813 13:13:52.476774 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10814 13:13:52.497309 <30>[ 10.328132] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10815 13:13:52.507308 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10816 13:13:52.525670 <30>[ 10.356168] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10817 13:13:52.535396 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10818 13:13:52.555273 <30>[ 10.386002] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10819 13:13:52.564888 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10820 13:13:52.581876 <30>[ 10.412411] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10821 13:13:52.591829 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10822 13:13:52.613689 <30>[ 10.444365] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10823 13:13:52.620393 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10824 13:13:52.637720 <30>[ 10.468440] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10825 13:13:52.647465 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10826 13:13:52.666118 <30>[ 10.496848] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10827 13:13:52.676140 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10828 13:13:52.729120 <30>[ 10.559878] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10829 13:13:52.735374 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10830 13:13:52.754812 <30>[ 10.585542] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10831 13:13:52.761101 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10832 13:13:52.783273 <30>[ 10.614168] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10833 13:13:52.790278 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10834 13:13:52.816081 <30>[ 10.640154] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10835 13:13:52.853824 <30>[ 10.684448] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10836 13:13:52.863330 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10837 13:13:52.886136 <30>[ 10.716973] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10838 13:13:52.892527 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10839 13:13:52.953664 <30>[ 10.784408] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10840 13:13:52.963619 Startin<6>[ 10.793795] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10841 13:13:52.970052 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10842 13:13:52.994446 <30>[ 10.824965] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10843 13:13:53.000672 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10844 13:13:53.025834 <30>[ 10.856872] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10845 13:13:53.035911 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10846 13:13:53.058378 <30>[ 10.888876] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10847 13:13:53.064841 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10848 13:13:53.125832 <30>[ 10.956195] systemd[1]: Starting systemd-journald.service - Journal Service...
10849 13:13:53.131689 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10850 13:13:53.152175 <30>[ 10.983019] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10851 13:13:53.158914 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10852 13:13:53.184588 <30>[ 11.011826] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10853 13:13:53.190645 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10854 13:13:53.211946 <30>[ 11.042477] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10855 13:13:53.221768 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10856 13:13:53.240579 <30>[ 11.071041] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10857 13:13:53.250241 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10858 13:13:53.275439 <30>[ 11.106005] systemd[1]: Started systemd-journald.service - Journal Service.
10859 13:13:53.281929 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10860 13:13:53.305321 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10861 13:13:53.322315 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10862 13:13:53.341822 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10863 13:13:53.362515 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10864 13:13:53.383230 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10865 13:13:53.403198 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10866 13:13:53.423620 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10867 13:13:53.448105 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10868 13:13:53.473491 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10869 13:13:53.495285 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10870 13:13:53.514454 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10871 13:13:53.535459 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10872 13:13:53.549748 See 'systemctl status systemd-remount-fs.service' for details.
10873 13:13:53.560342 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10874 13:13:53.579531 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10875 13:13:53.625321 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10876 13:13:53.646330 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10877 13:13:53.657211 <46>[ 11.488040] systemd-journald[181]: Received client request to flush runtime journal.
10878 13:13:53.671311 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10879 13:13:53.694816 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10880 13:13:53.717502 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10881 13:13:53.747801 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10882 13:13:53.766594 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10883 13:13:53.786322 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10884 13:13:53.805865 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10885 13:13:53.825997 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10886 13:13:53.885494 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10887 13:13:53.908869 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10888 13:13:53.925568 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10889 13:13:53.944678 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10890 13:13:53.989868 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10891 13:13:54.015938 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10892 13:13:54.037027 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10893 13:13:54.060612 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10894 13:13:54.086406 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10895 13:13:54.109927 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10896 13:13:54.168467 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10897 13:13:54.187950 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10898 13:13:54.215111 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10899 13:13:54.313903 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10900 13:13:54.334061 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10901 13:13:54.352936 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10902 13:13:54.374895 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10903 13:13:54.391572 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10904 13:13:54.407164 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10905 13:13:54.418631 <6>[ 12.249384] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10906 13:13:54.431854 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m -<6>[ 12.263898] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10907 13:13:54.434849 Socket Units.
10908 13:13:54.441297 <6>[ 12.267639] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10909 13:13:54.441375
10910 13:13:54.448140 <6>[ 12.269120] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10911 13:13:54.454487 <6>[ 12.272282] remoteproc remoteproc0: scp is available
10912 13:13:54.464858 <6>[ 12.277841] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10913 13:13:54.471023 <6>[ 12.277855] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10914 13:13:54.481172 <6>[ 12.280995] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10915 13:13:54.484324 <6>[ 12.290761] remoteproc remoteproc0: powering up scp
10916 13:13:54.494084 <4>[ 12.293853] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10917 13:13:54.501345 <6>[ 12.302310] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10918 13:13:54.510740 <3>[ 12.304921] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10919 13:13:54.517297 <3>[ 12.304942] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10920 13:13:54.526881 <3>[ 12.304950] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10921 13:13:54.533964 <6>[ 12.311664] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10922 13:13:54.540138 <6>[ 12.316830] mc: Linux media interface: v0.10
10923 13:13:54.544020 <6>[ 12.319043] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10924 13:13:54.553893 <6>[ 12.319927] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10925 13:13:54.560078 <6>[ 12.323982] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10926 13:13:54.566565 <6>[ 12.324397] videodev: Linux video capture interface: v2.00
10927 13:13:54.574363 <3>[ 12.326301] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10928 13:13:54.584050 <3>[ 12.326316] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10929 13:13:54.590533 <3>[ 12.326320] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10930 13:13:54.600412 <3>[ 12.326325] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10931 13:13:54.607497 <3>[ 12.326328] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10932 13:13:54.613660 <3>[ 12.326352] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10933 13:13:54.623821 <3>[ 12.326384] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10934 13:13:54.630247 <3>[ 12.326387] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10935 13:13:54.640200 <3>[ 12.326389] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10936 13:13:54.646754 <3>[ 12.326411] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10937 13:13:54.656814 <3>[ 12.326415] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10938 13:13:54.663666 <3>[ 12.326417] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10939 13:13:54.670814 <3>[ 12.326421] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10940 13:13:54.680868 <3>[ 12.326423] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10941 13:13:54.687890 <3>[ 12.326436] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10942 13:13:54.694041 <4>[ 12.341848] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10943 13:13:54.704899 <6>[ 12.350776] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10944 13:13:54.711549 <4>[ 12.358232] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10945 13:13:54.717758 <6>[ 12.366503] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10946 13:13:54.727988 <4>[ 12.380108] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10947 13:13:54.730960 <4>[ 12.380108] Fallback method does not support PEC.
10948 13:13:54.741076 <6>[ 12.384600] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10949 13:13:54.747428 <6>[ 12.392341] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10950 13:13:54.757284 <6>[ 12.400235] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10951 13:13:54.760738 <6>[ 12.405888] pci_bus 0000:00: root bus resource [bus 00-ff]
10952 13:13:54.770757 <6>[ 12.405893] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10953 13:13:54.780343 <6>[ 12.405896] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10954 13:13:54.783512 <6>[ 12.405946] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10955 13:13:54.793873 <6>[ 12.405965] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10956 13:13:54.796889 <6>[ 12.406048] pci 0000:00:00.0: supports D1 D2
10957 13:13:54.803521 <6>[ 12.406051] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10958 13:13:54.813116 <6>[ 12.407040] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10959 13:13:54.819906 <3>[ 12.416458] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 13:13:54.826208 <6>[ 12.422346] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10961 13:13:54.836592 <6>[ 12.433865] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10962 13:13:54.843548 <6>[ 12.438420] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10963 13:13:54.853664 <6>[ 12.447174] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10964 13:13:54.859918 <6>[ 12.454585] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10965 13:13:54.869898 <6>[ 12.454600] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10966 13:13:54.873290 <6>[ 12.454711] pci 0000:01:00.0: supports D1 D2
10967 13:13:54.880226 <6>[ 12.462859] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10968 13:13:54.890036 <6>[ 12.462929] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10969 13:13:54.896346 <6>[ 12.462938] remoteproc remoteproc0: remote processor scp is now up
10970 13:13:54.904013 <6>[ 12.470822] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10971 13:13:54.910104 <6>[ 12.479151] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10972 13:13:54.916909 <6>[ 12.483645] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10973 13:13:54.927014 <6>[ 12.487334] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10974 13:13:54.934091 <6>[ 12.503520] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10975 13:13:54.943924 <6>[ 12.511547] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10976 13:13:54.950318 <6>[ 12.511562] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10977 13:13:54.960224 <6>[ 12.511577] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10978 13:13:54.967361 <3>[ 12.527915] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 13:13:54.977245 <3>[ 12.528483] power_supply sbs-5-000b: driver failed to report `health' property: -6
10980 13:13:54.983372 <6>[ 12.535055] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10981 13:13:54.986866 <6>[ 12.543635] Bluetooth: Core ver 2.22
10982 13:13:54.997060 <3>[ 12.549490] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 13:13:55.000281 <6>[ 12.550268] pci 0000:00:00.0: PCI bridge to [bus 01]
10984 13:13:55.010003 <6>[ 12.551573] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10985 13:13:55.020388 <6>[ 12.552850] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10986 13:13:55.026703 <6>[ 12.553070] usbcore: registered new interface driver uvcvideo
10987 13:13:55.033182 <6>[ 12.558249] NET: Registered PF_BLUETOOTH protocol family
10988 13:13:55.039873 <6>[ 12.561261] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10989 13:13:55.050058 <6>[ 12.571715] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10990 13:13:55.056288 <6>[ 12.579556] Bluetooth: HCI device and connection manager initialized
10991 13:13:55.063107 <6>[ 12.586578] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10992 13:13:55.066230 <6>[ 12.595528] Bluetooth: HCI socket layer initialized
10993 13:13:55.073272 <6>[ 12.596249] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10994 13:13:55.079853 <6>[ 12.601791] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10995 13:13:55.086299 <6>[ 12.608459] Bluetooth: L2CAP socket layer initialized
10996 13:13:55.089350 <6>[ 12.618792] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10997 13:13:55.096177 <6>[ 12.624690] Bluetooth: SCO socket layer initialized
10998 13:13:55.102506 <5>[ 12.653806] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10999 13:13:55.112604 <3>[ 12.680602] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11000 13:13:55.119142 <5>[ 12.702047] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11001 13:13:55.125919 <6>[ 12.720774] usbcore: registered new interface driver btusb
11002 13:13:55.135160 <4>[ 12.721393] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11003 13:13:55.142091 <3>[ 12.721404] Bluetooth: hci0: Failed to load firmware file (-2)
11004 13:13:55.148564 <3>[ 12.721409] Bluetooth: hci0: Failed to set up firmware (-2)
11005 13:13:55.158252 <4>[ 12.721413] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11006 13:13:55.164750 <5>[ 12.728735] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11007 13:13:55.174560 <3>[ 12.740318] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11008 13:13:55.185041 <4>[ 12.741800] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11009 13:13:55.191460 <3>[ 12.769635] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11010 13:13:55.198179 <6>[ 12.774318] cfg80211: failed to load regulatory.db
11011 13:13:55.204255 <6>[ 12.841939] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11012 13:13:55.211493 <6>[ 13.044738] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11013 13:13:55.217786 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11014 13:13:55.236531 <6>[ 13.070941] mt7921e 0000:01:00.0: ASIC revision: 79610010
11015 13:13:55.249913 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11016 13:13:55.275998 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11017 13:13:55.297968 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11018 13:13:55.319049 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11019 13:13:55.336406 <6>[ 13.167719] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11020 13:13:55.339644 <6>[ 13.167719]
11021 13:13:55.366460 [[0;32m OK [0m] Finished [0;1;39msystemd-us<3>[ 13.198150] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11022 13:13:55.373152 er-sess…ervice[0m - Permit User Sessions.
11023 13:13:55.401104 <3>[ 13.232295] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11024 13:13:55.433842 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Man<3>[ 13.263916] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11025 13:13:55.433957 agement.
11026 13:13:55.462264 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11027 13:13:55.481783 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11028 13:13:55.500711 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11029 13:13:55.564619 [[0;32m OK [<46>[ 13.382974] systemd-journald[181]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.1 (1538 of 2047 items, 524288 file size, 340 bytes per hash table item), suggesting rotation.
11030 13:13:55.581216 0m] Started [0;<46>[ 13.405364] systemd-journald[181]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11031 13:13:55.587434 1;39mgetty@tty1.service[0m - Getty on tty1.
11032 13:13:55.609443 <6>[ 13.440436] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11033 13:13:55.619152 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11034 13:13:55.636102 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11035 13:13:55.651350 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11036 13:13:55.670188 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11037 13:13:55.722184 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11038 13:13:55.745803 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11039 13:13:55.770956 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11040 13:13:55.850012 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11041 13:13:55.868764 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11042 13:13:55.896866 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11043 13:13:55.930186
11044 13:13:55.933364 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11045 13:13:55.933442
11046 13:13:55.936745 debian-bookworm-arm64 login: root (automatic login)
11047 13:13:55.936840
11048 13:13:55.952100 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024 aarch64
11049 13:13:55.952181
11050 13:13:55.959195 The programs included with the Debian GNU/Linux system are free software;
11051 13:13:55.965438 the exact distribution terms for each program are described in the
11052 13:13:55.969096 individual files in /usr/share/doc/*/copyright.
11053 13:13:55.969219
11054 13:13:55.975083 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11055 13:13:55.978610 permitted by applicable law.
11056 13:13:55.979218 Matched prompt #10: / #
11058 13:13:55.979521 Setting prompt string to ['/ #']
11059 13:13:55.979637 end: 2.2.5.1 login-action (duration 00:00:15) [common]
11061 13:13:55.979923 end: 2.2.5 auto-login-action (duration 00:00:15) [common]
11062 13:13:55.980031 start: 2.2.6 expect-shell-connection (timeout 00:02:42) [common]
11063 13:13:55.980118 Setting prompt string to ['/ #']
11064 13:13:55.980198 Forcing a shell prompt, looking for ['/ #']
11065 13:13:55.980254 Sending line: ''
11067 13:13:56.030572 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11068 13:13:56.030671 Waiting using forced prompt support (timeout 00:02:30)
11069 13:13:56.035672 / #
11070 13:13:56.035967 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11071 13:13:56.036079 start: 2.2.7 export-device-env (timeout 00:02:42) [common]
11072 13:13:56.036196 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11073 13:13:56.036335 end: 2.2 depthcharge-retry (duration 00:02:18) [common]
11074 13:13:56.036447 end: 2 depthcharge-action (duration 00:02:18) [common]
11075 13:13:56.036608 start: 3 lava-test-retry (timeout 00:07:14) [common]
11076 13:13:56.036731 start: 3.1 lava-test-shell (timeout 00:07:14) [common]
11077 13:13:56.036827 Using namespace: common
11078 13:13:56.036923 Sending line: '#'
11080 13:13:56.137448 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11081 13:13:56.142540 / # #
11082 13:13:56.142819 Using /lava-14879019
11083 13:13:56.142909 Sending line: 'export SHELL=/bin/sh'
11085 13:13:56.248508 / # export SHELL=/bin/sh
11086 13:13:56.248776 Sending line: '. /lava-14879019/environment'
11088 13:13:56.354014 / # . /lava-14879019/environment
11089 13:13:56.354300 Sending line: '/lava-14879019/bin/lava-test-runner /lava-14879019/0'
11091 13:13:56.454812 Test shell timeout: 10s (minimum of the action and connection timeout)
11092 13:13:56.459296 / # /lava-14879019/bin/lava-test-runner /lava-14879019/0
11093 13:13:56.479086 <6>[ 14.313653] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11094 13:13:56.485979 + export TESTRUN_ID=0_igt-kms-mediatek
11095 13:13:56.492678 + cd /la<8>[ 14.323840] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 14879019_1.5.2.3.1>
11096 13:13:56.492971 Received signal: <STARTRUN> 0_igt-kms-mediatek 14879019_1.5.2.3.1
11097 13:13:56.493038 Starting test lava.0_igt-kms-mediatek (14879019_1.5.2.3.1)
11098 13:13:56.493128 Skipping test definition patterns.
11099 13:13:56.495919 va-14879019/0/tests/0_igt-kms-mediatek
11100 13:13:56.495996 + cat uuid
11101 13:13:56.499361 + UUID=14879019_1.5.2.3.1
11102 13:13:56.499437 + set +x
11103 13:13:56.519185 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11104 13:13:56.528981 <8>[ 14.363209] <LAVA_SIGNAL_TESTSET START core_auth>
11105 13:13:56.529259 Received signal: <TESTSET> START core_auth
11106 13:13:56.529327 Starting test_set core_auth
11107 13:13:56.562841 <14>[ 14.397240] [IGT] core_auth: executing
11108 13:13:56.569250 IGT-Version: 1.2<14>[ 14.401880] [IGT] core_auth: starting subtest getclient-simple
11109 13:13:56.579152 8-ga44ebfe (aarc<14>[ 14.409422] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11110 13:13:56.582259 h64) (Linux: 6.1<14>[ 14.417672] [IGT] core_auth: exiting, ret=0
11111 13:13:56.586271 .96-cip24 aarch64)
11112 13:13:56.589143 Using IGT_SRANDOM=1721308436 for randomisation
11113 13:13:56.599008 Starting sub<8>[ 14.429386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11114 13:13:56.599085 test: getclient-simple
11115 13:13:56.599316 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11117 13:13:56.602620 Opened device: /dev/dri/card0
11118 13:13:56.608759 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11119 13:13:56.617414 <14>[ 14.451754] [IGT] core_auth: executing
11120 13:13:56.623504 IGT-Version: 1.2<14>[ 14.456217] [IGT] core_auth: starting subtest getclient-master-drop
11121 13:13:56.633678 8-ga44ebfe (aarc<14>[ 14.464290] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11122 13:13:56.640341 h64) (Linux: 6.1<14>[ 14.473041] [IGT] core_auth: exiting, ret=0
11123 13:13:56.640419 .96-cip24 aarch64)
11124 13:13:56.653405 Using IGT_SRANDOM=1721308436 for randomisati<8>[ 14.483164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11125 13:13:56.653483 on
11126 13:13:56.653720 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11128 13:13:56.657115 Starting subtest: getclient-master-drop
11129 13:13:56.660415 Opened device: /dev/dri/card0
11130 13:13:56.663604 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11131 13:13:56.684930 <14>[ 14.519440] [IGT] core_auth: executing
11132 13:13:56.691923 IGT-Version: 1.2<14>[ 14.524141] [IGT] core_auth: starting subtest basic-auth
11133 13:13:56.698143 8-ga44ebfe (aarc<14>[ 14.531104] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11134 13:13:56.704782 h64) (Linux: 6.1<14>[ 14.538794] [IGT] core_auth: exiting, ret=0
11135 13:13:56.707739 .96-cip24 aarch64)
11136 13:13:56.717645 Using IGT_SRANDOM=1721308436 for randomisati<8>[ 14.550096] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11137 13:13:56.717741 on
11138 13:13:56.718033 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11140 13:13:56.721460 Opened device: /dev/dri/card0
11141 13:13:56.724635 Starting subtest: basic-auth
11142 13:13:56.727589 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11143 13:13:56.747350 <14>[ 14.581672] [IGT] core_auth: executing
11144 13:13:56.753620 IGT-Version: 1.2<14>[ 14.586392] [IGT] core_auth: starting subtest many-magics
11145 13:13:56.757130 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11146 13:13:56.763416 Using IGT_SRANDOM=1721308436 for randomisation
11147 13:13:56.770177 Opened device: /dev/dri/card<14>[ 14.604138] [IGT] core_auth: finished subtest many-magics, SUCCESS
11148 13:13:56.770255 0
11149 13:13:56.777074 Starting subt<14>[ 14.610968] [IGT] core_auth: exiting, ret=0
11150 13:13:56.780039 est: many-magics
11151 13:13:56.783014 Reopening device failed after 1020 opens
11152 13:13:56.789658 [1mSubtest many-mag<8>[ 14.623647] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11153 13:13:56.789905 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11155 13:13:56.793335 ics: SUCCESS (0.011s)[0m
11156 13:13:56.796583 <8>[ 14.632240] <LAVA_SIGNAL_TESTSET STOP>
11157 13:13:56.796825 Received signal: <TESTSET> STOP
11158 13:13:56.796886 Closing test_set core_auth
11159 13:13:56.848265 <14>[ 14.683047] [IGT] core_getclient: executing
11160 13:13:56.854742 IGT-Version: 1.2<14>[ 14.688174] [IGT] core_getclient: exiting, ret=0
11161 13:13:56.858258 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11162 13:13:56.868442 Using IGT_SRANDOM=1721308436<8>[ 14.700088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11163 13:13:56.868696 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11165 13:13:56.871716 for randomisation
11166 13:13:56.874794 Opened device: /dev/dri/card0
11167 13:13:56.874888 SUCCESS (0.006s)
11168 13:13:56.913246 <14>[ 14.747800] [IGT] core_getstats: executing
11169 13:13:56.920101 IGT-Version: 1.2<14>[ 14.752927] [IGT] core_getstats: exiting, ret=0
11170 13:13:56.923454 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11171 13:13:56.933084 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11173 13:13:56.936160 Using IGT_SRANDOM=1721308436 for randomisati<8>[ 14.766284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11174 13:13:56.936252 on
11175 13:13:56.936335 Opened device: /dev/dri/card0
11176 13:13:56.939244 SUCCESS (0.006s)
11177 13:13:56.988119 <14>[ 14.822644] [IGT] core_getversion: executing
11178 13:13:56.994462 IGT-Version: 1.2<14>[ 14.827882] [IGT] core_getversion: exiting, ret=0
11179 13:13:56.998227 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11180 13:13:57.004609 Using IGT_SRANDOM=1721308436 for randomisation
11181 13:13:57.010905 Opened devic<8>[ 14.842374] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11182 13:13:57.011167 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11184 13:13:57.014643 e: /dev/dri/card0
11185 13:13:57.014710 SUCCESS (0.006s)
11186 13:13:57.061438 <14>[ 14.896113] [IGT] core_setmaster_vs_auth: executing
11187 13:13:57.068103 IGT-Version: 1.2<14>[ 14.902099] [IGT] core_setmaster_vs_auth: exiting, ret=0
11188 13:13:57.075042 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11189 13:13:57.081370 Using IGT_SR<8>[ 14.914085] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11190 13:13:57.081612 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11192 13:13:57.084570 ANDOM=1721308436 for randomisation
11193 13:13:57.088292 Opened device: /dev/dri/card0
11194 13:13:57.091205 SUCCESS (0.007s)
11195 13:13:57.106073 <8>[ 14.940871] <LAVA_SIGNAL_TESTSET START drm_read>
11196 13:13:57.106319 Received signal: <TESTSET> START drm_read
11197 13:13:57.106382 Starting test_set drm_read
11198 13:13:57.137639 <14>[ 14.972207] [IGT] drm_read: executing
11199 13:13:57.143985 IGT-Version: 1.2<14>[ 14.977065] [IGT] drm_read: exiting, ret=77
11200 13:13:57.147733 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11201 13:13:57.154031 Using IGT_SR<8>[ 14.987923] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11202 13:13:57.154278 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11204 13:13:57.157616 ANDOM=1721308436 for randomisation
11205 13:13:57.160740 Opened device: /dev/dri/card0
11206 13:13:57.166994 No KMS driver or no outputs, pipes: 16, outputs: 0
11207 13:13:57.170625 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11208 13:13:57.173820 <14>[ 15.009922] [IGT] drm_read: executing
11209 13:13:57.180729 IGT-Version: 1.2<14>[ 15.014368] [IGT] drm_read: exiting, ret=77
11210 13:13:57.183889 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11211 13:13:57.194026 Using IGT_SRANDOM=1721308436<8>[ 15.026352] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11212 13:13:57.194273 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11214 13:13:57.197312 for randomisation
11215 13:13:57.200182 Opened device: /dev/dri/card0
11216 13:13:57.203816 No KMS driver or no outputs, pipes: 16, outputs: 0
11217 13:13:57.207059 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11218 13:13:57.222593 <14>[ 15.056957] [IGT] drm_read: executing
11219 13:13:57.229289 IGT-Version: 1.2<14>[ 15.061828] [IGT] drm_read: exiting, ret=77
11220 13:13:57.232294 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11221 13:13:57.239261 Using IGT_SR<8>[ 15.072671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11222 13:13:57.239508 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11224 13:13:57.242193 ANDOM=1721308436 for randomisation
11225 13:13:57.245416 Opened device: /dev/dri/card0
11226 13:13:57.249263 No KMS driver or no outputs, pipes: 16, outputs: 0
11227 13:13:57.258655 [1mSubtest empty-block: SKIP (0.000s)[0<14>[ 15.093653] [IGT] drm_read: executing
11228 13:13:57.258747 m
11229 13:13:57.265796 IGT-Version: 1.2<14>[ 15.098295] [IGT] drm_read: exiting, ret=77
11230 13:13:57.268772 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11231 13:13:57.278649 Using IGT_SRANDOM=1721308437<8>[ 15.110294] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11232 13:13:57.278751 for randomisation
11233 13:13:57.278982 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11235 13:13:57.281889 Opened device: /dev/dri/card0
11236 13:13:57.288445 No KMS driver or no outputs, pipes: 16, outputs: 0
11237 13:13:57.291902 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11238 13:13:57.306443 <14>[ 15.141166] [IGT] drm_read: executing
11239 13:13:57.313092 IGT-Version: 1.2<14>[ 15.145975] [IGT] drm_read: exiting, ret=77
11240 13:13:57.316296 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11241 13:13:57.319891 Using IGT_SRANDOM=1721308437 for randomisation
11242 13:13:57.329514 Opened devic<8>[ 15.160640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11243 13:13:57.329603 e: /dev/dri/card0
11244 13:13:57.329833 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11246 13:13:57.336407 No KMS driver or no outputs, pipes: 16, outputs: 0
11247 13:13:57.339843 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11248 13:13:57.348470 <14>[ 15.183134] [IGT] drm_read: executing
11249 13:13:57.354824 IGT-Version: 1.2<14>[ 15.187753] [IGT] drm_read: exiting, ret=77
11250 13:13:57.358515 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11251 13:13:57.368082 Using IGT_SRANDOM=1721308437<8>[ 15.199437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11252 13:13:57.368343 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11254 13:13:57.371296 for randomisation
11255 13:13:57.371372 Opened device: /dev/dri/card0
11256 13:13:57.378263 No KMS driver or no outputs, pipes: 16, outputs: 0
11257 13:13:57.381359 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11258 13:13:57.384922 <14>[ 15.221400] [IGT] drm_read: executing
11259 13:13:57.391667 IGT-Version: 1.2<14>[ 15.226048] [IGT] drm_read: exiting, ret=77
11260 13:13:57.398146 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11261 13:13:57.408206 Using IGT_SRANDOM=1721308437<8>[ 15.238112] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11262 13:13:57.408300 for randomisation
11263 13:13:57.408561 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11265 13:13:57.414528 Opened devic<8>[ 15.248007] <LAVA_SIGNAL_TESTSET STOP>
11266 13:13:57.414609 e: /dev/dri/card0
11267 13:13:57.414835 Received signal: <TESTSET> STOP
11268 13:13:57.414895 Closing test_set drm_read
11269 13:13:57.421286 No KMS driver or no outputs, pipes: 16, outputs: 0
11270 13:13:57.424223 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11271 13:13:57.445334 <8>[ 15.279893] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11272 13:13:57.445604 Received signal: <TESTSET> START kms_addfb_basic
11273 13:13:57.445669 Starting test_set kms_addfb_basic
11274 13:13:57.473213 <14>[ 15.307569] [IGT] kms_addfb_basic: executing
11275 13:13:57.486404 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch6<14>[ 15.317125] [IGT] kms_addfb_basic: starting subtest unused-handle
11276 13:13:57.486495 4)
11277 13:13:57.492644 Using IGT_SR<14>[ 15.324619] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11278 13:13:57.495757 ANDOM=1721308437 for randomisation
11279 13:13:57.499630 Opened device: /dev/dri/card0
11280 13:13:57.502709 Starting subtest: unused-handle
11281 13:13:57.508984 [1mSubtest <14>[ 15.342148] [IGT] kms_addfb_basic: exiting, ret=0
11282 13:13:57.512361 unused-handle: SUCCESS (0.000s)[0m
11283 13:13:57.522314 Test requirement not met in function igt_re<8>[ 15.353848] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11284 13:13:57.522619 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11286 13:13:57.525658 quire_intel, file ../lib/drmtest.c:880:
11287 13:13:57.529316 Test requirement: is_intel_device(fd)
11288 13:13:57.535371 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11289 13:13:57.539001 Test requirement: is_intel_device(fd)
11290 13:13:57.546013 No KMS driver or no outputs, pipes: 16, outputs: 0
11291 13:13:57.548988 <14>[ 15.385512] [IGT] kms_addfb_basic: executing
11292 13:13:57.562384 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch6<14>[ 15.395149] [IGT] kms_addfb_basic: starting subtest unused-pitches
11293 13:13:57.562489 4)
11294 13:13:57.572096 Using IGT_SR<14>[ 15.402775] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11295 13:13:57.575383 ANDOM=1721308437 for randomisation
11296 13:13:57.579055 Opened device: /dev/dri/card0
11297 13:13:57.579175 Starting subtest: unused-pitches
11298 13:13:57.585809 [1mSubtest<14>[ 15.420258] [IGT] kms_addfb_basic: exiting, ret=0
11299 13:13:57.589042 unused-pitches: SUCCESS (0.000s)[0m
11300 13:13:57.602161 Test requirement not met in function igt_require_intel, f<8>[ 15.433229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11301 13:13:57.602425 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11303 13:13:57.605145 ile ../lib/drmtest.c:880:
11304 13:13:57.609061 Test requirement: is_intel_device(fd)
11305 13:13:57.615402 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11306 13:13:57.618477 Test requirement: is_intel_device(fd)
11307 13:13:57.622037 No KMS driver or no outputs, pipes: 16, outputs: 0
11308 13:13:57.630259 <14>[ 15.465090] [IGT] kms_addfb_basic: executing
11309 13:13:57.643659 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch6<14>[ 15.474689] [IGT] kms_addfb_basic: starting subtest unused-offsets
11310 13:13:57.643760 4)
11311 13:13:57.650401 Using IGT_SR<14>[ 15.482298] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11312 13:13:57.653353 ANDOM=1721308437 for randomisation
11313 13:13:57.657245 Opened device: /dev/dri/card0
11314 13:13:57.660228 Starting subtest: unused-offsets
11315 13:13:57.667320 [1mSubtest<14>[ 15.500060] [IGT] kms_addfb_basic: exiting, ret=0
11316 13:13:57.670386 unused-offsets: SUCCESS (0.000s)[0m
11317 13:13:57.679928 Test requirement not met in function igt_<8>[ 15.512499] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11318 13:13:57.680248 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11320 13:13:57.683352 require_intel, file ../lib/drmtest.c:880:
11321 13:13:57.687075 Test requirement: is_intel_device(fd)
11322 13:13:57.699634 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:<14>[ 15.533694] [IGT] kms_addfb_basic: executing
11323 13:13:57.699753 880:
11324 13:13:57.703297 Test requirement: is_intel_device(fd)
11325 13:13:57.709597 No KMS driver or no<14>[ 15.543098] [IGT] kms_addfb_basic: starting subtest unused-modifier
11326 13:13:57.719542 outputs, pipes:<14>[ 15.550984] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11327 13:13:57.722853 16, outputs: 0
11328 13:13:57.726190 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11329 13:13:57.733054 Using IGT_S<14>[ 15.567902] [IGT] kms_addfb_basic: exiting, ret=0
11330 13:13:57.736219 RANDOM=1721308437 for randomisation
11331 13:13:57.739468 Opened device: /dev/dri/card0
11332 13:13:57.746300 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11334 13:13:57.749548 Starting sub<8>[ 15.579727] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11335 13:13:57.749618 test: unused-modifier
11336 13:13:57.752412 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11337 13:13:57.762366 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11338 13:13:57.766076 Test requirement: is_intel_device(fd)
11339 13:13:57.775720 Test requirement not met in function igt_require_intel, file ../lib/drmtest<14>[ 15.610789] [IGT] kms_addfb_basic: executing
11340 13:13:57.775822 .c:880:
11341 13:13:57.778820 Test requirement: is_intel_device(fd)
11342 13:13:57.789303 No KMS driver or<14>[ 15.620746] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11343 13:13:57.798742 no outputs, pip<14>[ 15.628334] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11344 13:13:57.798849 es: 16, outputs: 0
11345 13:13:57.805427 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11346 13:13:57.811937 Using IGT_SRANDOM=172130<14>[ 15.646008] [IGT] kms_addfb_basic: exiting, ret=77
11347 13:13:57.814968 8437 for randomisation
11348 13:13:57.818194 Opened device: /dev/dri/card0
11349 13:13:57.827964 Starting subtest: clobber<8>[ 15.658839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11350 13:13:57.828070 red-modifier
11351 13:13:57.828327 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11353 13:13:57.834815 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:885:
11354 13:13:57.838309 Test requirement: is_i915_device(fd)
11355 13:13:57.844762 [1mSubtest clobberred-modifier: SKIP (0.000s)[0m
11356 13:13:57.851437 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11357 13:13:57.854677 T<14>[ 15.689642] [IGT] kms_addfb_basic: executing
11358 13:13:57.857683 est requirement: is_intel_device(fd)
11359 13:13:57.867798 Test requirement not met i<14>[ 15.699865] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11360 13:13:57.877761 n function igt_r<14>[ 15.708239] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11361 13:13:57.881063 equire_intel, file ../lib/drmtest.c:880:
11362 13:13:57.884116 Test requirement: is_intel_device(fd)
11363 13:13:57.894321 No KMS driver or no outputs, pi<14>[ 15.726674] [IGT] kms_addfb_basic: exiting, ret=77
11364 13:13:57.894406 pes: 16, outputs: 0
11365 13:13:57.907764 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 a<8>[ 15.739588] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11366 13:13:57.908016 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11368 13:13:57.910718 arch64)
11369 13:13:57.913860 Using IGT_SRANDOM=1721308437 for randomisation
11370 13:13:57.917497 Opened device: /dev/dri/card0
11371 13:13:57.920371 Starting subtest: invalid-smem-bo-on-discrete
11372 13:13:57.927207 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11373 13:13:57.930366 Test requirement: is_intel_device(fd)
11374 13:13:57.937414 [1mSubtest in<14>[ 15.771330] [IGT] kms_addfb_basic: executing
11375 13:13:57.940176 valid-smem-bo-on-discrete: SKIP (0.000s)[0m
11376 13:13:57.946750 Test requirement n<14>[ 15.781249] [IGT] kms_addfb_basic: starting subtest legacy-format
11377 13:13:57.953446 ot met in function igt_require_intel, file ../lib/drmtest.c:880:
11378 13:13:57.957006 Test requirement: is_intel_device(fd)
11379 13:13:57.966941 Test requirement not met in function ig<14>[ 15.799866] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11380 13:13:57.973619 t_require_intel, file ../lib/drmtest.c:880:
11381 13:13:57.976777 Test requirement: is_intel_device(fd)
11382 13:13:57.983008 No KMS driver or no outputs,<14>[ 15.816619] [IGT] kms_addfb_basic: exiting, ret=0
11383 13:13:57.986919 pipes: 16, outputs: 0
11384 13:13:57.996214 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip2<8>[ 15.829421] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11385 13:13:57.996485 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11387 13:13:58.000127 4 aarch64)
11388 13:13:58.003247 Using IGT_SRANDOM=1721308437 for randomisation
11389 13:13:58.006297 Opened device: /dev/dri/card0
11390 13:13:58.006374 Starting subtest: legacy-format
11391 13:13:58.012842 Successfully fuzzed 10000 {bpp, depth} variations
11392 13:13:58.016618 [1mSubtest legacy-format: SUCCESS (0.012s)[0m
11393 13:13:58.029925 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:88<14>[ 15.862142] [IGT] kms_addfb_basic: executing
11394 13:13:58.030008 0:
11395 13:13:58.032802 Test requirement: is_intel_device(fd)
11396 13:13:58.042942 Test requirement not met in function igt_require_inte<14>[ 15.875432] [IGT] kms_addfb_basic: starting subtest no-handle
11397 13:13:58.049692 l, file ../lib/d<14>[ 15.882484] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11398 13:13:58.052512 rmtest.c:880:
11399 13:13:58.055991 Test requirement: is_intel_device(fd)
11400 13:13:58.062566 No KMS driver or no output<14>[ 15.897334] [IGT] kms_addfb_basic: exiting, ret=0
11401 13:13:58.065871 s, pipes: 16, outputs: 0
11402 13:13:58.075475 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-ci<8>[ 15.908775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11403 13:13:58.075730 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11405 13:13:58.079056 p24 aarch64)
11406 13:13:58.082410 Using IGT_SRANDOM=1721308437 for randomisation
11407 13:13:58.085359 Opened device: /dev/dri/card0
11408 13:13:58.088853 Starting subtest: no-handle
11409 13:13:58.095601 [1mSubtest no-handle: SUCCESS (0.000s<14>[ 15.930147] [IGT] kms_addfb_basic: executing
11410 13:13:58.095680 )[0m
11411 13:13:58.108800 Test requirement not met in function igt_require_intel, file ../lib/drmte<14>[ 15.941581] [IGT] kms_addfb_basic: starting subtest basic
11412 13:13:58.108916 st.c:880:
11413 13:13:58.115052 Test <14>[ 15.948029] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11414 13:13:58.118850 requirement: is_intel_device(fd)
11415 13:13:58.128325 Test requirement not met in function igt_requi<14>[ 15.961614] [IGT] kms_addfb_basic: exiting, ret=0
11416 13:13:58.131977 re_intel, file ../lib/drmtest.c:880:
11417 13:13:58.135062 Test requirement: is_intel_device(fd)
11418 13:13:58.142029 No <8>[ 15.974734] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11419 13:13:58.142309 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11421 13:13:58.145287 KMS driver or no outputs, pipes: 16, outputs: 0
11422 13:13:58.151877 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11423 13:13:58.155217 Using IGT_SRANDOM=1721308437 for randomisation
11424 13:13:58.158352 Opened device: /dev/dri/card0
11425 13:13:58.161711 Starting subtest: basic
11426 13:13:58.164495 [1mSubtest basic: SUCCESS (0.000s)[0m
11427 13:13:58.168010 Test requi<14>[ 16.004724] [IGT] kms_addfb_basic: executing
11428 13:13:58.174830 rement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11429 13:13:58.184583 Test requirement: is_i<14>[ 16.016834] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11430 13:13:58.184667 ntel_device(fd)
11431 13:13:58.191099 <14>[ 16.024353] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11432 13:13:58.194413
11433 13:13:58.204612 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:8<14>[ 16.039182] [IGT] kms_addfb_basic: exiting, ret=0
11434 13:13:58.204695 80:
11435 13:13:58.207813 Test requirement: is_intel_device(fd)
11436 13:13:58.217996 No KMS driver or no outputs, pipes: <8>[ 16.051396] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11437 13:13:58.218248 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11439 13:13:58.220911 16, outputs: 0
11440 13:13:58.227288 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11441 13:13:58.230578 Using IGT_SRANDOM=1721308437 for randomisation
11442 13:13:58.234160 Opened device: /dev/dri/card0
11443 13:13:58.234242 Starting subtest: bad-pitch-0
11444 13:13:58.241100 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11445 13:13:58.247460 Test requirement not met in fun<14>[ 16.081608] [IGT] kms_addfb_basic: executing
11446 13:13:58.250676 ction igt_require_intel, file ../lib/drmtest.c:880:
11447 13:13:58.253882 Test requirement: is_intel_device(fd)
11448 13:13:58.260553 Test<14>[ 16.094198] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11449 13:13:58.270343 requirement not<14>[ 16.101629] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11450 13:13:58.277202 met in function igt_require_intel, file ../lib/drmtest.c:880:
11451 13:13:58.283815 Test requirement<14>[ 16.116558] [IGT] kms_addfb_basic: exiting, ret=0
11452 13:13:58.283914 : is_intel_device(fd)
11453 13:13:58.290381 No KMS driver or no outputs, pipes: 16, outputs: 0
11454 13:13:58.297088 IGT-V<8>[ 16.128797] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11455 13:13:58.297364 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11457 13:13:58.300494 ersion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11458 13:13:58.306841 Using IGT_SRANDOM=1721308438 for randomisation
11459 13:13:58.310020 Opened device: /dev/dri/card0
11460 13:13:58.310101 Starting subtest: bad-pitch-32
11461 13:13:58.316914 [1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11462 13:13:58.323377 Test requirement not met in function igt_require_i<14>[ 16.159023] [IGT] kms_addfb_basic: executing
11463 13:13:58.326354 ntel, file ../lib/drmtest.c:880:
11464 13:13:58.330202 Test requirement: is_intel_device(fd)
11465 13:13:58.339648 Test requirement not me<14>[ 16.171713] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11466 13:13:58.346158 t in function ig<14>[ 16.179189] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11467 13:13:58.353292 t_require_intel, file ../lib/drmtest.c:880:
11468 13:13:58.359745 Test requirement: is_intel_device(f<14>[ 16.194081] [IGT] kms_addfb_basic: exiting, ret=0
11469 13:13:58.359845 d)
11470 13:13:58.366358 No KMS driver or no outputs, pipes: 16, outputs: 0
11471 13:13:58.373061 IGT-Version: 1.28-ga44eb<8>[ 16.206440] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11472 13:13:58.373399 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11474 13:13:58.375935 fe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11475 13:13:58.382568 Using IGT_SRANDOM=1721308438 for randomisation
11476 13:13:58.385758 Opened device: /dev/dri/card0
11477 13:13:58.385869 Starting subtest: bad-pitch-63
11478 13:13:58.392544 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11479 13:13:58.402866 Test requirement not met in function igt_require_intel, file ../lib/d<14>[ 16.237009] [IGT] kms_addfb_basic: executing
11480 13:13:58.403014 rmtest.c:880:
11481 13:13:58.405598 Test requirement: is_intel_device(fd)
11482 13:13:58.415910 Test requirement not met in function igt_r<14>[ 16.249382] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11483 13:13:58.425508 equire_intel, fi<14>[ 16.256869] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11484 13:13:58.428804 le ../lib/drmtest.c:880:
11485 13:13:58.431918 Test requirement: is_intel_device(fd)
11486 13:13:58.438464 No KMS driver o<14>[ 16.271826] [IGT] kms_addfb_basic: exiting, ret=0
11487 13:13:58.442282 r no outputs, pipes: 16, outputs: 0
11488 13:13:58.451994 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux<8>[ 16.284223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11489 13:13:58.452267 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11491 13:13:58.455246 : 6.1.96-cip24 aarch64)
11492 13:13:58.458458 Using IGT_SRANDOM=1721308438 for randomisation
11493 13:13:58.461753 Opened device: /dev/dri/card0
11494 13:13:58.465425 Starting subtest: bad-pitch-128
11495 13:13:58.468369 [1mSubtest bad-pitch-128: SUCCESS (0.000s)[0m
11496 13:13:58.475066 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11497 13:13:58.478134 Te<14>[ 16.314435] [IGT] kms_addfb_basic: executing
11498 13:13:58.481844 st requirement: is_intel_device(fd)
11499 13:13:58.494821 Test requirement not met in function igt_require_intel, fil<14>[ 16.327104] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11500 13:13:58.504947 e ../lib/drmtest<14>[ 16.334654] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11501 13:13:58.505045 .c:880:
11502 13:13:58.507937 Test requirement: is_intel_device(fd)
11503 13:13:58.514689 No KMS driver or no outputs, pip<14>[ 16.349880] [IGT] kms_addfb_basic: exiting, ret=0
11504 13:13:58.518072 es: 16, outputs: 0
11505 13:13:58.527994 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aa<8>[ 16.361974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11506 13:13:58.528247 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11508 13:13:58.531177 rch64)
11509 13:13:58.534739 Using IGT_SRANDOM=1721308438 for randomisation
11510 13:13:58.537798 Opened device: /dev/dri/card0
11511 13:13:58.541482 Starting subtest: bad-pitch-256
11512 13:13:58.547765 [1mSubtest bad-pitch-256: SUCCESS (0.00<14>[ 16.382918] [IGT] kms_addfb_basic: executing
11513 13:13:58.547849 0s)[0m
11514 13:13:58.561048 Test requirement not met in function igt_require_intel, file ../lib/drm<14>[ 16.394394] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11515 13:13:58.564249 test.c:880:
11516 13:13:58.570541 Tes<14>[ 16.401466] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11517 13:13:58.574391 t requirement: is_intel_device(fd)
11518 13:13:58.583789 Test requirement not met in function igt_req<14>[ 16.415901] [IGT] kms_addfb_basic: exiting, ret=0
11519 13:13:58.587870 uire_intel, file ../lib/drmtest.c:880:
11520 13:13:58.590787 Test requirement: is_intel_device(fd)
11521 13:13:58.597094 N<8>[ 16.428653] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11522 13:13:58.597360 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11524 13:13:58.600303 o KMS driver or no outputs, pipes: 16, outputs: 0
11525 13:13:58.607173 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11526 13:13:58.610209 Using IGT_SRANDOM=1721308438 for randomisation
11527 13:13:58.616791 Opened de<14>[ 16.450850] [IGT] kms_addfb_basic: executing
11528 13:13:58.616891 vice: /dev/dri/card0
11529 13:13:58.619978 Starting subtest: bad-pitch-1024
11530 13:13:58.630327 [1mSubtest bad-pitch-10<14>[ 16.462749] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11531 13:13:58.639890 24: SUCCESS (0.0<14>[ 16.469842] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11532 13:13:58.640010 00s)[0m
11533 13:13:58.650118 Test requirement not met in function igt_require_intel, file ../lib/dr<14>[ 16.484209] [IGT] kms_addfb_basic: exiting, ret=0
11534 13:13:58.653029 mtest.c:880:
11535 13:13:58.656774 Test requirement: is_intel_device(fd)
11536 13:13:58.662978 Test requirement not met in<8>[ 16.496874] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11537 13:13:58.663231 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11539 13:13:58.669780 function igt_require_intel, file ../lib/drmtest.c:880:
11540 13:13:58.673282 Test requirement: is_intel_device(fd)
11541 13:13:58.676652 No KMS driver or no outputs, pipes: 16, outputs: 0
11542 13:13:58.682734 IGT-Version: 1.28-ga44ebfe (<14>[ 16.519434] [IGT] kms_addfb_basic: executing
11543 13:13:58.689728 aarch64) (Linux: 6.1.96-cip24 aarch64)
11544 13:13:58.699588 Using IGT_SRANDOM=1721308438 for randomi<14>[ 16.530861] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11545 13:13:58.699716 sation
11546 13:13:58.706421 Opened d<14>[ 16.538178] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11547 13:13:58.709806 evice: /dev/dri/card0
11548 13:13:58.713155 Starting subtest: bad-pitch-999
11549 13:13:58.719428 [1mSubtest bad-pitch-99<14>[ 16.552645] [IGT] kms_addfb_basic: exiting, ret=0
11550 13:13:58.723128 9: SUCCESS (0.000s)[0m
11551 13:13:58.732960 Test requirement not met in function igt_require_intel,<8>[ 16.565522] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11552 13:13:58.733220 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11554 13:13:58.736140 file ../lib/drmtest.c:880:
11555 13:13:58.739254 Test requirement: is_intel_device(fd)
11556 13:13:58.745734 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11557 13:13:58.748902 Test requirement: is_intel_device(fd)
11558 13:13:58.755889 No KMS driver or no outputs, pipes: 16, outputs: 0
11559 13:13:58.762504 IGT-Version: 1.28-ga44ebfe (a<14>[ 16.596197] [IGT] kms_addfb_basic: executing
11560 13:13:58.765810 arch64) (Linux: 6.1.96-cip24 aarch64)
11561 13:13:58.768781 Using IGT_SRANDOM=1721308438 for randomisation
11562 13:13:58.778933 Opened device: /dev/dri/c<14>[ 16.610926] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11563 13:13:58.779026 ard0
11564 13:13:58.788519 Starting s<14>[ 16.618283] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11565 13:13:58.788600 ubtest: bad-pitch-65536
11566 13:13:58.798652 [1mSubtest bad-pitch-65536: SUCCESS (0<14>[ 16.631903] [IGT] kms_addfb_basic: exiting, ret=0
11567 13:13:58.798733 .000s)[0m
11568 13:13:58.811534 Test requirement not met in function igt_require_intel, file ../lib/<8>[ 16.644792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11569 13:13:58.811795 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11571 13:13:58.815382 drmtest.c:880:
11572 13:13:58.818500 Test requirement: is_intel_device(fd)
11573 13:13:58.824933 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11574 13:13:58.828581 Test requirement: is_intel_device(fd)
11575 13:13:58.831769 No KMS driver or no outputs, pipes: 16, outputs: 0
11576 13:13:58.841113 IGT-Version: 1.28-ga44ebfe (aarch64) (Linu<14>[ 16.675886] [IGT] kms_addfb_basic: executing
11577 13:13:58.845024 x: 6.1.96-cip24 aarch64)
11578 13:13:58.848275 Using IGT_SRANDOM=1721308438 for randomisation
11579 13:13:58.851402 Opened device: /dev/dri/card0
11580 13:13:58.857844 Startin<14>[ 16.690489] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11581 13:13:58.867882 g subtest: inval<14>[ 16.697596] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11582 13:13:58.868002 id-get-prop-any
11583 13:13:58.877936 [1mSubtest invalid-get-prop-any: SUCCESS (0.00<14>[ 16.710864] [IGT] kms_addfb_basic: exiting, ret=0
11584 13:13:58.878017 0s)[0m
11585 13:13:58.891088 Test requirement not met in function igt_require_intel, file ../lib/drm<8>[ 16.723787] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11586 13:13:58.891346 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11588 13:13:58.894275 test.c:880:
11589 13:13:58.897527 Test requirement: is_intel_device(fd)
11590 13:13:58.904386 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11591 13:13:58.907552 Test requirement: is_intel_device(fd)
11592 13:13:58.911180 N<14>[ 16.746306] [IGT] kms_addfb_basic: executing
11593 13:13:58.917478 o KMS driver or no outputs, pipes: 16, outputs: 0
11594 13:13:58.927610 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aar<14>[ 16.759811] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11595 13:13:58.927692 ch64)
11596 13:13:58.937456 Using IGT<14>[ 16.768347] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11597 13:13:58.940701 _SRANDOM=1721308438 for randomisation
11598 13:13:58.947260 Opened de<14>[ 16.781402] [IGT] kms_addfb_basic: exiting, ret=0
11599 13:13:58.947344 vice: /dev/dri/card0
11600 13:13:58.950908 Starting subtest: invalid-get-prop
11601 13:13:58.960162 [1mSubtest invalid-ge<8>[ 16.793429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11602 13:13:58.960416 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11604 13:13:58.963766 t-prop: SUCCESS (0.000s)[0m
11605 13:13:58.970717 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11606 13:13:58.973360 Test requirement: is_intel_device(fd)
11607 13:13:58.980197 Test requirement not me<14>[ 16.815751] [IGT] kms_addfb_basic: executing
11608 13:13:58.987072 t in function igt_require_intel, file ../lib/drmtest.c:880:
11609 13:13:58.990128 Test requirement: is_intel_device(fd)
11610 13:13:58.996930 No KMS drive<14>[ 16.829800] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11611 13:13:59.006582 r or no outputs,<14>[ 16.837849] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11612 13:13:59.009785 pipes: 16, outputs: 0
11613 13:13:59.016649 IGT-Version: 1.28-ga44eb<14>[ 16.850831] [IGT] kms_addfb_basic: exiting, ret=0
11614 13:13:59.019847 fe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11615 13:13:59.029774 Using IGT_SRANDOM=1721308438 for ran<8>[ 16.862599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11616 13:13:59.029880 domisation
11617 13:13:59.030136 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11619 13:13:59.032878 Opened device: /dev/dri/card0
11620 13:13:59.036676 Starting subtest: invalid-set-prop-any
11621 13:13:59.042962 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
11622 13:13:59.049505 Test requirement not met in function <14>[ 16.884804] [IGT] kms_addfb_basic: executing
11623 13:13:59.053087 igt_require_intel, file ../lib/drmtest.c:880:
11624 13:13:59.056228 Test requirement: is_intel_device(fd)
11625 13:13:59.066203 Test requirement not met in function igt_r<14>[ 16.900642] [IGT] kms_addfb_basic: starting subtest master-rmfb
11626 13:13:59.075865 equire_intel, fi<14>[ 16.907836] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11627 13:13:59.079549 le ../lib/drmtest.c:880:
11628 13:13:59.082996 Test r<14>[ 16.918238] [IGT] kms_addfb_basic: exiting, ret=0
11629 13:13:59.086101 equirement: is_intel_device(fd)
11630 13:13:59.098904 No KMS driver or no outputs, pipes: 16, outputs<8>[ 16.930562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11631 13:13:59.098991 : 0
11632 13:13:59.099222 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11634 13:13:59.105806 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11635 13:13:59.109495 Using IGT_SRANDOM=1721308438 for randomisation
11636 13:13:59.112266 Opened device: /dev/dri/card0
11637 13:13:59.118997 Starting subtest: invali<14>[ 16.952054] [IGT] kms_addfb_basic: executing
11638 13:13:59.119078 d-set-prop
11639 13:13:59.122183 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11640 13:13:59.138887 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:88<14>[ 16.970087] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11641 13:13:59.138978 0:
11642 13:13:59.148630 Test require<14>[ 16.977907] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11643 13:13:59.155697 ment: is_intel_d<14>[ 16.987602] [IGT] kms_addfb_basic: exiting, ret=0
11644 13:13:59.155776 evice(fd)
11645 13:13:59.168588 Test requirement not met in function igt_require_intel, file ../lib/d<8>[ 17.000639] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11646 13:13:59.168844 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11648 13:13:59.171607 rmtest.c:880:
11649 13:13:59.175191 Test requirement: is_intel_device(fd)
11650 13:13:59.178252 No KMS driver or no outputs, pipes: 16, outputs: 0
11651 13:13:59.185185 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11652 13:13:59.188168 Using IGT_SRANDOM=1721308438 for randomisation
11653 13:13:59.191769 Opened device: /dev/dri/card0
11654 13:13:59.198548 Starting subtest: m<14>[ 17.032144] [IGT] kms_addfb_basic: executing
11655 13:13:59.198630 aster-rmfb
11656 13:13:59.201696 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11657 13:13:59.208414 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11658 13:13:59.218072 Test requirement:<14>[ 17.050769] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11659 13:13:59.221244 is_intel_device(fd)
11660 13:13:59.234518 Test requirement not met in function igt_require_intel, file ../lib/drmtes<14>[ 17.066284] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11661 13:13:59.234602 t.c:880:
11662 13:13:59.241300 Test r<14>[ 17.074369] [IGT] kms_addfb_basic: exiting, ret=98
11663 13:13:59.244244 equirement: is_intel_device(fd)
11664 13:13:59.247934 No KMS driver or no outputs, pipes: 16, outputs: 0
11665 13:13:59.257749 IGT-Version<8>[ 17.087562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11666 13:13:59.258019 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11668 13:13:59.260810 : 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11669 13:13:59.267601 Using IGT_SRANDOM=1721308438 for randomisation
11670 13:13:59.267680 Opened device: /dev/dri/card0
11671 13:13:59.277268 Starting subtest: addfb25-modifier-no-fl<14>[ 17.111364] [IGT] kms_addfb_basic: executing
11672 13:13:59.277356 ag
11673 13:13:59.280656 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11674 13:13:59.290860 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11675 13:13:59.297421 Test require<14>[ 17.129321] [IGT] kms_addfb_basic: exiting, ret=77
11676 13:13:59.297504 ment: is_intel_device(fd)
11677 13:13:59.310117 Test requirement not met in function igt_require_inte<8>[ 17.142322] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11678 13:13:59.310393 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11680 13:13:59.313833 l, file ../lib/drmtest.c:880:
11681 13:13:59.317064 Test requirement: is_intel_device(fd)
11682 13:13:59.323297 No KMS driver or no outputs, pipes: 16, outputs: 0
11683 13:13:59.327047 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11684 13:13:59.333203 Using IGT_SRANDOM=1721308439 for randomisation
11685 13:13:59.333304 Opened device: /dev/dri/card0
11686 13:13:59.340232 Sta<14>[ 17.174077] [IGT] kms_addfb_basic: executing
11687 13:13:59.343321 rting subtest: addfb25-bad-modifier
11688 13:13:59.353315 (kms_addfb_basic:433) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11689 13:13:59.360056 (kms_addfb_basic:433) <14>[ 17.193605] [IGT] kms_addfb_basic: exiting, ret=77
11690 13:13:59.376337 CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('<8>[ 17.206755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11691 13:13:59.376611 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11693 13:13:59.383092 d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11694 13:13:59.389780 (kms_addfb_basic:433) CRITICAL: error: 0 != -1
11695 13:13:59.389862 Stack trace:
11696 13:13:59.396223 #0 ../li<14>[ 17.228914] [IGT] kms_addfb_basic: executing
11697 13:13:59.399280 b/igt_core.c:1989 __igt_fail_assert()
11698 13:13:59.399361 #1 [<unknown>+0xdc024358]
11699 13:13:59.402844 #2 [<unknown>+0xdc025fbc]
11700 13:13:59.405900 #3 [<unknown>+0xdc02156c]
11701 13:13:59.409182 #4 [__libc_init_first+0x80]
11702 13:13:59.412585 #<14>[ 17.247501] [IGT] kms_addfb_basic: exiting, ret=77
11703 13:13:59.416085 5 [__libc_start_main+0x98]
11704 13:13:59.419405 #6 [<unknown>+0xdc0215b0]
11705 13:13:59.429169 Subtest addfb25-bad-mod<8>[ 17.260596] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11706 13:13:59.429422 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11708 13:13:59.432220 ifier failed.
11709 13:13:59.432297 **** DEBUG ****
11710 13:13:59.442312 (kms_addfb_basic:433) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11711 13:13:59.452380 (kms_addfb_basic:433) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11712 13:13:59.459004 (kms_addfb_basic:433) CRITIC<14>[ 17.292357] [IGT] kms_addfb_basic: executing
11713 13:13:59.478987 AL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1<14>[ 17.312135] [IGT] kms_addfb_basic: exiting, ret=77
11714 13:13:59.479092
11715 13:13:59.482380 (kms_addfb_basic:433) CRITICAL: error: 0 != -1
11716 13:13:59.495213 (kms_addfb_basic:433) igt_core-INFO: Stack tra<8>[ 17.325908] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11717 13:13:59.495325 ce:
11718 13:13:59.495558 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11720 13:13:59.501834 (kms_addfb_basic:433) igt_core-INFO: #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11721 13:13:59.508475 (kms_addfb_basic:433) igt_core-INFO: #1 [<unknown>+0xdc024358]
11722 13:13:59.511626 (km<14>[ 17.348547] [IGT] kms_addfb_basic: executing
11723 13:13:59.518112 s_addfb_basic:433) igt_core-INFO: #2 [<unknown>+0xdc025fbc]
11724 13:13:59.524849 (kms_addfb_basic:433) igt_core-INFO: #3 [<unknown>+0xdc02156c]
11725 13:13:59.531632 (kms_addfb_basi<14>[ 17.365764] [IGT] kms_addfb_basic: exiting, ret=77
11726 13:13:59.535169 c:433) igt_core-INFO: #4 [__libc_init_first+0x80]
11727 13:13:59.544996 (kms_addfb_basic:433) igt_c<8>[ 17.377541] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11728 13:13:59.545245 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11730 13:13:59.548009 ore-INFO: #5 [__libc_start_main+0x98]
11731 13:13:59.555175 (kms_addfb_basic:433) igt_core-INFO: #6 [<unknown>+0xdc0215b0]
11732 13:13:59.558083 **** END ****
11733 13:13:59.561276 [1mSubtest addfb25-bad-modifier: FAIL (0.008s)[0m
11734 13:13:59.568022 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11735 13:13:59.574783 Test requir<14>[ 17.409161] [IGT] kms_addfb_basic: executing
11736 13:13:59.577651 ement: is_intel_device(fd)
11737 13:13:59.584349 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11738 13:13:59.587643 Test requirement: is_intel_device(fd)
11739 13:13:59.594579 No KMS driver or no outpu<14>[ 17.428408] [IGT] kms_addfb_basic: exiting, ret=77
11740 13:13:59.597559 ts, pipes: 16, outputs: 0
11741 13:13:59.604137 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11742 13:13:59.611211 U<8>[ 17.441888] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11743 13:13:59.611464 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11745 13:13:59.614507 sing IGT_SRANDOM=1721308439 for randomisation
11746 13:13:59.617601 Opened device: /dev/dri/card0
11747 13:13:59.630608 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:<14>[ 17.464491] [IGT] kms_addfb_basic: executing
11748 13:13:59.630705
11749 13:13:59.634235 Test requirement: is_intel_device(fd)
11750 13:13:59.637231 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11751 13:13:59.647578 Test requirement not met in function igt_require_intel,<14>[ 17.482114] [IGT] kms_addfb_basic: exiting, ret=77
11752 13:13:59.650763 file ../lib/drmtest.c:880:
11753 13:13:59.653850 Test requirement: is_intel_device(fd)
11754 13:13:59.663887 No KMS drive<8>[ 17.495071] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11755 13:13:59.664144 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11757 13:13:59.667233 r or no outputs, pipes: 16, outputs: 0
11758 13:13:59.674180 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11759 13:13:59.677320 Using IGT_SRANDOM=1721308439 for randomisation
11760 13:13:59.680387 Opened device: /dev/dri/card0
11761 13:13:59.687067 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11762 13:13:59.690214 T<14>[ 17.526519] [IGT] kms_addfb_basic: executing
11763 13:13:59.693331 est requirement: is_intel_device(fd)
11764 13:13:59.700123 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11765 13:13:59.706705 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11766 13:13:59.713469 <14>[ 17.545495] [IGT] kms_addfb_basic: exiting, ret=77
11767 13:13:59.713551
11768 13:13:59.716732 Test requirement: is_intel_device(fd)
11769 13:13:59.726194 No KMS driver or no outputs, pipes: 16, <8>[ 17.558707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11770 13:13:59.726278 outputs: 0
11771 13:13:59.726508 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11773 13:13:59.732991 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11774 13:13:59.736124 Using IGT_SRANDOM=1721308439 for randomisation
11775 13:13:59.739896 Opened device: /dev/dri/card0
11776 13:13:59.745983 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11777 13:13:59.752830 Test requirement: is_intel_de<14>[ 17.588585] [IGT] kms_addfb_basic: executing
11778 13:13:59.756158 vice(fd)
11779 13:13:59.759184 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11780 13:13:59.766377 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11781 13:13:59.772960 Test requirement<14>[ 17.607874] [IGT] kms_addfb_basic: exiting, ret=77
11782 13:13:59.775947 : is_intel_device(fd)
11783 13:13:59.779108 No KMS driver or no outputs, pipes: 16, outputs: 0
11784 13:13:59.789352 IGT-Version: 1.28-ga4<8>[ 17.621229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11785 13:13:59.789604 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11787 13:13:59.792323 4ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11788 13:13:59.799298 Using IGT_SRANDOM=1721308439 for randomisation
11789 13:13:59.799400 Opened device: /dev/dri/card0
11790 13:13:59.809325 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11791 13:13:59.812230 Test requirement: is_intel_device(fd)
11792 13:13:59.818928 Test requirement not me<14>[ 17.652404] [IGT] kms_addfb_basic: executing
11793 13:13:59.822355 t in function igt_require_intel, file ../lib/drmtest.c:880:
11794 13:13:59.825467 Test requirement: is_intel_device(fd)
11795 13:13:59.831946 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11796 13:13:59.838613 No KMS driver or no out<14>[ 17.671628] [IGT] kms_addfb_basic: exiting, ret=77
11797 13:13:59.841860 puts, pipes: 16, outputs: 0
11798 13:13:59.844953 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11799 13:13:59.851627 <8>[ 17.684925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11800 13:13:59.851705
11801 13:13:59.851951 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11803 13:13:59.858430 Using IGT_SRANDOM=1721308439 for randomisation
11804 13:13:59.861359 Opened device: /dev/dri/card0
11805 13:13:59.871546 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:88<14>[ 17.706663] [IGT] kms_addfb_basic: executing
11806 13:13:59.871639 0:
11807 13:13:59.874795 Test requirement: is_intel_device(fd)
11808 13:13:59.880934 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11809 13:13:59.891116 Test requirement: is_intel_device<14>[ 17.724276] [IGT] kms_addfb_basic: exiting, ret=77
11810 13:13:59.891208 (fd)
11811 13:13:59.897887 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11812 13:13:59.904135 No KMS driver or<8>[ 17.736793] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11813 13:13:59.904378 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11815 13:13:59.907805 no outputs, pipes: 16, outputs: 0
11816 13:13:59.914220 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11817 13:13:59.917175 Using IGT_SRANDOM=1721308439 for randomisation
11818 13:13:59.920861 Opened device: /dev/dri/card0
11819 13:13:59.927031 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11820 13:13:59.933759 Test <14>[ 17.767767] [IGT] kms_addfb_basic: executing
11821 13:13:59.937259 requirement: is_intel_device(fd)
11822 13:13:59.943428 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11823 13:13:59.947347 Test requirement: is_intel_device(fd)
11824 13:13:59.953836 [1mSubtest tile-pi<14>[ 17.786874] [IGT] kms_addfb_basic: exiting, ret=77
11825 13:13:59.957261 tch-mismatch: SKIP (0.000s)[0m
11826 13:13:59.967160 No KMS driver or no outputs, pipes: 16, outputs<8>[ 17.800127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11827 13:13:59.967248 : 0
11828 13:13:59.967543 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11830 13:13:59.973448 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11831 13:13:59.976656 Using IGT_SRANDOM=1721308439 for randomisation
11832 13:13:59.980460 Opened device: /dev/dri/card0
11833 13:13:59.986764 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11834 13:13:59.996732 Test requirement: is_intel_device(fd<14>[ 17.829899] [IGT] kms_addfb_basic: executing
11835 13:13:59.996820 )
11836 13:14:00.003490 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11837 13:14:00.006230 Test requirement: is_intel_device(fd)
11838 13:14:00.016447 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0<14>[ 17.849188] [IGT] kms_addfb_basic: exiting, ret=77
11839 13:14:00.016532 m
11840 13:14:00.019589 No KMS driver or no outputs, pipes: 16, outputs: 0
11841 13:14:00.032550 IGT-Version: 1.28-ga44ebfe (aarch64) (Lin<8>[ 17.863005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11842 13:14:00.032818 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11844 13:14:00.036357 ux: 6.1.96-cip24 aarch64)
11845 13:14:00.039119 Using IGT_SRANDOM=1721308439 for randomisation
11846 13:14:00.042797 Opened device: /dev/dri/card0
11847 13:14:00.052277 Test requirement not met in function igt_require_intel, file ../lib/dr<14>[ 17.886186] [IGT] kms_addfb_basic: executing
11848 13:14:00.052352 mtest.c:880:
11849 13:14:00.055699 Test requirement: is_intel_device(fd)
11850 13:14:00.065449 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11851 13:14:00.072129 Test requirement: is_in<14>[ 17.904959] [IGT] kms_addfb_basic: exiting, ret=77
11852 13:14:00.072237 tel_device(fd)
11853 13:14:00.075762 No KMS driver or no outputs, pipes: 16, outputs: 0
11854 13:14:00.085851 [1mSubtest <8>[ 17.917629] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11855 13:14:00.086105 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11857 13:14:00.088771 size-max: SKIP (0.000s)[0m
11858 13:14:00.095520 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11859 13:14:00.098866 Using IGT_SRANDOM=1721308439 for randomisation
11860 13:14:00.101899 Opened device: /dev/dri/card0
11861 13:14:00.108850 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11862 13:14:00.115150 Test require<14>[ 17.948914] [IGT] kms_addfb_basic: executing
11863 13:14:00.115260 ment: is_intel_device(fd)
11864 13:14:00.125561 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11865 13:14:00.128478 Test requirement: is_intel_device(fd)
11866 13:14:00.135099 No KMS driver or no output<14>[ 17.968394] [IGT] kms_addfb_basic: exiting, ret=77
11867 13:14:00.138605 s, pipes: 16, outputs: 0
11868 13:14:00.141956 [1mSubtest too-wide: SKIP (0.000s)[0m
11869 13:14:00.148142 IGT-Version: <8>[ 17.980896] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11870 13:14:00.148417 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11872 13:14:00.154635 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11873 13:14:00.158469 Using IGT_SRANDOM=1721308439 for randomisation
11874 13:14:00.161628 Opened device: /dev/dri/card0
11875 13:14:00.167864 Test requirement not met in function igt_r<14>[ 18.003776] [IGT] kms_addfb_basic: executing
11876 13:14:00.174973 equire_intel, file ../lib/drmtest.c:880:
11877 13:14:00.178124 Test requirement: is_intel_device(fd)
11878 13:14:00.187976 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:8<14>[ 18.022269] [IGT] kms_addfb_basic: exiting, ret=77
11879 13:14:00.188060 80:
11880 13:14:00.191191 Test requirement: is_intel_device(fd)
11881 13:14:00.204831 No KMS driver or no outputs, pipes: <8>[ 18.034924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11882 13:14:00.204939 16, outputs: 0
11883 13:14:00.205184 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11885 13:14:00.208110 [1mSubtest too-high: SKIP (0.000s)[0m
11886 13:14:00.214228 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11887 13:14:00.217495 Using IGT_SRANDOM=1721308439 for randomisation
11888 13:14:00.221422 Opened device: /dev/dri/card0
11889 13:14:00.230915 Test requirement not met in function igt_require_intel, file ../lib/<14>[ 18.066867] [IGT] kms_addfb_basic: executing
11890 13:14:00.234539 drmtest.c:880:
11891 13:14:00.237509 Test requirement: is_intel_device(fd)
11892 13:14:00.244127 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11893 13:14:00.250984 Test requirement: is_<14>[ 18.086096] [IGT] kms_addfb_basic: exiting, ret=77
11894 13:14:00.254060 intel_device(fd)
11895 13:14:00.257370 No KMS driver or no outputs, pipes: 16, outputs: 0
11896 13:14:00.267125 [1mSubtest bo-too-small: <8>[ 18.099022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11897 13:14:00.267220 SKIP (0.000s)[0m
11898 13:14:00.267473 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11900 13:14:00.273887 IGT-Version: <8>[ 18.108705] <LAVA_SIGNAL_TESTSET STOP>
11901 13:14:00.274135 Received signal: <TESTSET> STOP
11902 13:14:00.274197 Closing test_set kms_addfb_basic
11903 13:14:00.277543 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11904 13:14:00.283531 Using IGT_SRANDOM=1721308439 for randomisation
11905 13:14:00.283615 Opened device: /dev/dri/card0
11906 13:14:00.293828 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11907 13:14:00.296824 Test requirement: is_intel_device(fd)
11908 13:14:00.306749 Test requirement not met in function igt_require_intel, file ..<8>[ 18.140116] <LAVA_SIGNAL_TESTSET START kms_atomic>
11909 13:14:00.306836 /lib/drmtest.c:880:
11910 13:14:00.307066 Received signal: <TESTSET> START kms_atomic
11911 13:14:00.307130 Starting test_set kms_atomic
11912 13:14:00.310111 Test requirement: is_intel_device(fd)
11913 13:14:00.316867 No KMS driver or no outputs, pipes: 16, outputs: 0
11914 13:14:00.320220 [1mSubtest small-bo: SKIP (0.000s)[0m
11915 13:14:00.327036 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11916 13:14:00.330297 Using IGT_SRANDOM=1721308439 for randomisation
11917 13:14:00.333521 Ope<14>[ 18.169111] [IGT] kms_atomic: executing
11918 13:14:00.340291 ned device: /dev<14>[ 18.175117] [IGT] kms_atomic: exiting, ret=77
11919 13:14:00.340375 /dri/card0
11920 13:14:00.353645 Test requirement not met in function igt_require_int<8>[ 18.185872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11921 13:14:00.353900 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11923 13:14:00.356893 el, file ../lib/drmtest.c:880:
11924 13:14:00.359948 Test requirement: is_intel_device(fd)
11925 13:14:00.366741 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11926 13:14:00.373340 Test requirement: is_<14>[ 18.208325] [IGT] kms_atomic: executing
11927 13:14:00.379987 intel_device(fd)<14>[ 18.213657] [IGT] kms_atomic: exiting, ret=77
11928 13:14:00.380075
11929 13:14:00.383028 No KMS driver or no outputs, pipes: 16, outputs: 0
11930 13:14:00.393235 [1mSubtest bo-too-small-d<8>[ 18.225934] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11931 13:14:00.393533 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11933 13:14:00.396063 ue-to-tiling: SKIP (0.000s)[0m
11934 13:14:00.403051 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11935 13:14:00.405956 Using IGT_SRANDOM=1721308439 for randomisation
11936 13:14:00.409563 Opened device: /dev/dri/card0
11937 13:14:00.416402 Test require<14>[ 18.250639] [IGT] kms_atomic: executing
11938 13:14:00.423005 ment not met in <14>[ 18.255546] [IGT] kms_atomic: exiting, ret=77
11939 13:14:00.426197 function igt_require_intel, file ../lib/drmtest.c:880:
11940 13:14:00.435738 Test requirement: is_int<8>[ 18.267740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11941 13:14:00.436006 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11943 13:14:00.439576 el_device(fd)
11944 13:14:00.445884 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11945 13:14:00.449463 Test requirement: is_intel_device(fd)
11946 13:14:00.452698 No KMS driver or no outputs, pipes: 16, outputs: 0
11947 13:14:00.459212 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.000s)[0m
11948 13:14:00.465950 IGT-Version: 1.28-ga44ebfe <14>[ 18.300413] [IGT] kms_atomic: executing
11949 13:14:00.472088 (aarch64) (Linux<14>[ 18.305967] [IGT] kms_atomic: exiting, ret=77
11950 13:14:00.472198 : 6.1.96-cip24 aarch64)
11951 13:14:00.478813 Using IGT_SRANDOM=1721308439 for randomisation
11952 13:14:00.485248 Opened <8>[ 18.316763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11953 13:14:00.485494 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11955 13:14:00.488971 device: /dev/dri/card0
11956 13:14:00.495199 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11957 13:14:00.498861 Test requirement: is_intel_device(fd)
11958 13:14:00.505241 Test requirement not met in f<14>[ 18.339876] [IGT] kms_atomic: executing
11959 13:14:00.512043 unction igt_requ<14>[ 18.345910] [IGT] kms_atomic: exiting, ret=77
11960 13:14:00.515277 ire_intel, file ../lib/drmtest.c:880:
11961 13:14:00.518620 Test requirement: is_intel_device(fd)
11962 13:14:00.524964 No KMS driver or n<8>[ 18.358937] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11963 13:14:00.525271 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11965 13:14:00.528332 o outputs, pipes: 16, outputs: 0
11966 13:14:00.535232 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11967 13:14:00.541950 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11968 13:14:00.545334 Using IGT_SRANDOM=1721308440 for randomisation
11969 13:14:00.548626 Opened device: /dev/dri/card0
11970 13:14:00.555137 Test requirement not met in functio<14>[ 18.389929] [IGT] kms_atomic: executing
11971 13:14:00.561365 n igt_require_in<14>[ 18.395329] [IGT] kms_atomic: exiting, ret=77
11972 13:14:00.564797 tel, file ../lib/drmtest.c:880:
11973 13:14:00.568451 Test requirement: is_intel_device(fd)
11974 13:14:00.574738 Test req<8>[ 18.406530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11975 13:14:00.574990 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11977 13:14:00.581141 uirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11978 13:14:00.584936 Test requirement: is_intel_device(fd)
11979 13:14:00.591330 No KMS driver or no outputs, pipes: 16, outputs: 0
11980 13:14:00.594660 [1mSubte<14>[ 18.429477] [IGT] kms_atomic: executing
11981 13:14:00.601388 st addfb25-y-til<14>[ 18.435123] [IGT] kms_atomic: exiting, ret=77
11982 13:14:00.605004 ed-small-legacy: SKIP (0.000s)[0m
11983 13:14:00.615117 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<8>[ 18.447453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11984 13:14:00.615359 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11986 13:14:00.618053 6.1.96-cip24 aarch64)
11987 13:14:00.621130 Using IGT_SRANDOM=1721308440 for randomisation
11988 13:14:00.624610 Opened device: /dev/dri/card0
11989 13:14:00.631046 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11990 13:14:00.634618 Test requirement: is_intel_device(fd)
11991 13:14:00.644277 Test requirement not met in function igt_requi<14>[ 18.478832] [IGT] kms_atomic: executing
11992 13:14:00.650540 re_intel, file .<14>[ 18.483994] [IGT] kms_atomic: exiting, ret=77
11993 13:14:00.650629 ./lib/drmtest.c:880:
11994 13:14:00.654525 Test requirement: is_intel_device(fd)
11995 13:14:00.667438 No KMS driver or no outputs, pipes:<8>[ 18.496665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11996 13:14:00.667517 16, outputs: 0
11997 13:14:00.667750 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11999 13:14:00.671106 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
12000 13:14:00.677508 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12001 13:14:00.683766 Using IGT_SRANDOM=1721308440 for randomisat<14>[ 18.520397] [IGT] kms_atomic: executing
12002 13:14:00.687535 ion
12003 13:14:00.690476 Opened devi<14>[ 18.525905] [IGT] kms_atomic: exiting, ret=77
12004 13:14:00.693738 ce: /dev/dri/card0
12005 13:14:00.696977 No KMS driver or no outputs, pipes: 16, outputs: 0
12006 13:14:00.706726 [1mSubt<8>[ 18.537937] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
12007 13:14:00.706972 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
12009 13:14:00.710423 est plane-overlay-legacy: SKIP (0.000s)[0m
12010 13:14:00.716487 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12011 13:14:00.720241 Using IGT_SRANDOM=1721308440 for randomisation
12012 13:14:00.723272 Opened device: /dev/dri/card0
12013 13:14:00.726401 No KMS driver or no outputs, pipes: 16, outputs: 0
12014 13:14:00.733267 [1mSubtest plane-primary-le<14>[ 18.569718] [IGT] kms_atomic: executing
12015 13:14:00.739480 gacy: SKIP (0.00<14>[ 18.574695] [IGT] kms_atomic: exiting, ret=77
12016 13:14:00.739587 0s)[0m
12017 13:14:00.746235 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12018 13:14:00.756406 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
12020 13:14:00.759368 Using IGT_SRANDOM=1721308440 for ra<8>[ 18.589666] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
12021 13:14:00.759444 ndomisation
12022 13:14:00.763029 Opened device: /dev/dri/card0
12023 13:14:00.766130 No KMS driver or no outputs, pipes: 16, outputs: 0
12024 13:14:00.772478 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
12025 13:14:00.776070 IGT-Version: <14>[ 18.612001] [IGT] kms_atomic: executing
12026 13:14:00.782666 1.28-ga44ebfe (a<14>[ 18.617900] [IGT] kms_atomic: exiting, ret=77
12027 13:14:00.785788 arch64) (Linux: 6.1.96-cip24 aarch64)
12028 13:14:00.799239 Using IGT_SRANDOM=1721308440 for randomis<8>[ 18.629879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
12029 13:14:00.799331 ation
12030 13:14:00.799562 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
12032 13:14:00.802458 Opened device: /dev/dri/card0
12033 13:14:00.805482 No KMS driver or no outputs, pipes: 16, outputs: 0
12034 13:14:00.812362 [1mSubtest plane-immutable-zpos: SKIP (0.000s)[0m
12035 13:14:00.815325 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12036 13:14:00.822225 Using IGT_SRANDOM=1721308440 for randomisation
12037 13:14:00.825421 Opened device<14>[ 18.661873] [IGT] kms_atomic: executing
12038 13:14:00.831803 : /dev/dri/card0<14>[ 18.666976] [IGT] kms_atomic: exiting, ret=77
12039 13:14:00.831887
12040 13:14:00.838612 No KMS driver or no outputs, pipes: 16, outputs: 0
12041 13:14:00.845516 [1mSubtes<8>[ 18.677643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-plane-damage RESULT=skip>
12042 13:14:00.845764 Received signal: <TESTCASE> TEST_CASE_ID=atomic-plane-damage RESULT=skip
12044 13:14:00.848623 t test-only: SKIP (0.000s)[0m
12045 13:14:00.852015 <8>[ 18.687446] <LAVA_SIGNAL_TESTSET STOP>
12046 13:14:00.852260 Received signal: <TESTSET> STOP
12047 13:14:00.852326 Closing test_set kms_atomic
12048 13:14:00.858235 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12049 13:14:00.861709 Using IGT_SRANDOM=1721308440 for randomisation
12050 13:14:00.864976 Opened device: /dev/dri/card0
12051 13:14:00.868522 No KMS driver or no outputs, pipes: 16, outputs: 0
12052 13:14:00.875129 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
12053 13:14:00.881808 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12054 13:14:00.884814 U<8>[ 18.718806] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12055 13:14:00.885062 Received signal: <TESTSET> START kms_flip_event_leak
12056 13:14:00.885156 Starting test_set kms_flip_event_leak
12057 13:14:00.891226 sing IGT_SRANDOM=1721308440 for randomisation
12058 13:14:00.891305 Opened device: /dev/dri/card0
12059 13:14:00.897883 No KMS driver or no outputs, pipes: 16, outputs: 0
12060 13:14:00.901710 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
12061 13:14:00.907769 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12062 13:14:00.914642 Using<14>[ 18.747698] [IGT] kms_flip_event_leak: executing
12063 13:14:00.921503 IGT_SRANDOM=172<14>[ 18.753874] [IGT] kms_flip_event_leak: exiting, ret=77
12064 13:14:00.921586 1308440 for randomisation
12065 13:14:00.924465 Opened device: /dev/dri/card0
12066 13:14:00.931450 No KMS<8>[ 18.765538] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12067 13:14:00.931696 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12069 13:14:00.937723 driver or no outputs, pipes: 16<8>[ 18.773604] <LAVA_SIGNAL_TESTSET STOP>
12070 13:14:00.937963 Received signal: <TESTSET> STOP
12071 13:14:00.938026 Closing test_set kms_flip_event_leak
12072 13:14:00.940792 , outputs: 0
12073 13:14:00.944579 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
12074 13:14:00.950863 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12075 13:14:00.954141 Using IGT_SRANDOM=1721308440 for randomisation
12076 13:14:00.957277 Opened device: /dev/dri/card0
12077 13:14:00.964126 No KMS driver or no outputs, pipes: 16, outputs: 0
12078 13:14:00.967243 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
12079 13:14:00.976900 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<8>[ 18.810057] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12080 13:14:00.976998 6.1.96-cip24 aarch64)
12081 13:14:00.977256 Received signal: <TESTSET> START kms_prop_blob
12082 13:14:00.977342 Starting test_set kms_prop_blob
12083 13:14:00.983479 Using IGT_SRANDOM=1721308440 for randomisation
12084 13:14:00.983573 Opened device: /dev/dri/card0
12085 13:14:00.990133 No KMS driver or no outputs, pipes: 16, outputs: 0
12086 13:14:00.993741 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
12087 13:14:01.003781 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux<14>[ 18.837529] [IGT] kms_prop_blob: executing
12088 13:14:01.010224 : 6.1.96-cip24 a<14>[ 18.843495] [IGT] kms_prop_blob: starting subtest basic
12089 13:14:01.010323 arch64)
12090 13:14:01.016612 Using I<14>[ 18.849834] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12091 13:14:01.023611 GT_SRANDOM=17213<14>[ 18.857625] [IGT] kms_prop_blob: exiting, ret=0
12092 13:14:01.026736 08440 for randomisation
12093 13:14:01.029772 Opened device: /dev/dri/card0
12094 13:14:01.036677 No KMS driver or no outp<8>[ 18.870584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12095 13:14:01.036927 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12097 13:14:01.039801 uts, pipes: 16, outputs: 0
12098 13:14:01.043598 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m
12099 13:14:01.049916 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12100 13:14:01.056116 Using IGT_<14>[ 18.891024] [IGT] kms_prop_blob: executing
12101 13:14:01.062936 SRANDOM=17213084<14>[ 18.896009] [IGT] kms_prop_blob: starting subtest blob-prop-core
12102 13:14:01.072870 40 for randomisa<14>[ 18.903445] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12103 13:14:01.072962 tion
12104 13:14:01.079551 Opened dev<14>[ 18.912039] [IGT] kms_prop_blob: exiting, ret=0
12105 13:14:01.079632 ice: /dev/dri/card0
12106 13:14:01.086194 No KMS driver or no outputs, pipes: 16, outputs: 0
12107 13:14:01.092838 [1mSub<8>[ 18.924426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12108 13:14:01.093098 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12110 13:14:01.096005 test atomic-plane-damage: SKIP (0.000s)[0m
12111 13:14:01.102790 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12112 13:14:01.109127 Using IGT_SRANDOM=1721308440 fo<14>[ 18.944856] [IGT] kms_prop_blob: executing
12113 13:14:01.109272 r randomisation
12114 13:14:01.115773 <14>[ 18.949814] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12115 13:14:01.119114
12116 13:14:01.125797 Opened device: <14>[ 18.957653] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12117 13:14:01.128987 /dev/dri/card0
12118 13:14:01.132470 <14>[ 18.966634] [IGT] kms_prop_blob: exiting, ret=0
12119 13:14:01.136030 No KMS driver or no outputs, pipes: 16, outputs: 0
12120 13:14:01.145579 [1mSubtest basic: SKIP (0.0<8>[ 18.978870] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12121 13:14:01.145826 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12123 13:14:01.149162 00s)[0m
12124 13:14:01.155519 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12125 13:14:01.158808 Using IGT_SRANDOM=1721308440 for randomisation
12126 13:14:01.161908 Opened device: /dev/dri/card0
12127 13:14:01.161984 Starting subtest: basic
12128 13:14:01.165970 [1mSubtest basic: SUCCESS (0.000s)[0m
12129 13:14:01.175275 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.<14>[ 19.010114] [IGT] kms_prop_blob: executing
12130 13:14:01.181558 96-cip24 aarch64<14>[ 19.015950] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12131 13:14:01.185127 )
12132 13:14:01.191874 Using IGT_SRA<14>[ 19.023662] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12133 13:14:01.198235 NDOM=1721308440 <14>[ 19.032461] [IGT] kms_prop_blob: exiting, ret=0
12134 13:14:01.201815 for randomisation
12135 13:14:01.201891 Opened device: /dev/dri/card0
12136 13:14:01.211249 Starting subtest: blob-prop-co<8>[ 19.045620] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12137 13:14:01.211495 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12139 13:14:01.214976 re
12140 13:14:01.218138 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
12141 13:14:01.224619 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12142 13:14:01.228026 Using IGT_SRANDOM=1721308440 for randomisation
12143 13:14:01.231291 Opened device: /dev/dri/card0
12144 13:14:01.234800 Starting subtest: blob-prop-validate
12145 13:14:01.241129 [1mSubtest blob-prop-validate: S<14>[ 19.076299] [IGT] kms_prop_blob: executing
12146 13:14:01.247749 UCCESS (0.000s)<14>[ 19.081860] [IGT] kms_prop_blob: starting subtest blob-multiple
12147 13:14:01.247828 [0m
12148 13:14:01.257785 IGT-Version<14>[ 19.089249] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12149 13:14:01.264243 : 1.28-ga44ebfe (aarch64) (Linux<14>[ 19.098953] [IGT] kms_prop_blob: exiting, ret=0
12150 13:14:01.267479 : 6.1.96-cip24 aarch64)
12151 13:14:01.271318 Using IGT_SRANDOM=1721308441 for randomisation
12152 13:14:01.274308 Opened device: /dev/dri/card0
12153 13:14:01.280826 Starting<8>[ 19.113999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12154 13:14:01.281097 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12156 13:14:01.284297 subtest: blob-prop-lifetime
12157 13:14:01.287383 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12158 13:14:01.294286 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12159 13:14:01.300518 Using IGT_SRANDOM=172130<14>[ 19.137061] [IGT] kms_prop_blob: executing
12160 13:14:01.310206 8441 for randomi<14>[ 19.142015] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12161 13:14:01.310279 sation
12162 13:14:01.320471 Opened d<14>[ 19.149984] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12163 13:14:01.323630 evice: /dev/dri/<14>[ 19.159073] [IGT] kms_prop_blob: exiting, ret=0
12164 13:14:01.327011 card0
12165 13:14:01.330530 Starting subtest: blob-multiple
12166 13:14:01.340140 [1mSubtest blob-multiple: SUCCESS (0.00<8>[ 19.171916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12167 13:14:01.340231 0s)[0m
12168 13:14:01.340460 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12170 13:14:01.346667 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12171 13:14:01.350229 Using IGT_SRANDOM=1721308441 for randomisation
12172 13:14:01.353606 Opened device: /dev/dri/card0
12173 13:14:01.356898 Star<14>[ 19.193274] [IGT] kms_prop_blob: executing
12174 13:14:01.366831 ting subtest: in<14>[ 19.198662] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12175 13:14:01.376831 valid-get-prop-a<14>[ 19.206371] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12176 13:14:01.376902 ny
12177 13:14:01.379915 [1mSubtest <14>[ 19.215121] [IGT] kms_prop_blob: exiting, ret=0
12178 13:14:01.386370 invalid-get-prop-any: SUCCESS (0.000s)[0m
12179 13:14:01.395938 IGT-Version: 1.28-ga44ebfe (aarch64)<8>[ 19.227236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12180 13:14:01.396191 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12182 13:14:01.399851 (Linux: 6.1.96-cip24 aarch64)
12183 13:14:01.402900 Using IGT_SRANDOM=1721308441 for randomisation
12184 13:14:01.406014 Opened device: /dev/dri/card0
12185 13:14:01.409652 Starting subtest: invalid-get-prop
12186 13:14:01.412482 [1mSubtest i<14>[ 19.249427] [IGT] kms_prop_blob: executing
12187 13:14:01.422598 nvalid-get-prop:<14>[ 19.254352] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12188 13:14:01.432482 SUCCESS (0.000s<14>[ 19.262412] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12189 13:14:01.432559 )[0m
12190 13:14:01.438866 IGT-Versi<14>[ 19.271500] [IGT] kms_prop_blob: exiting, ret=0
12191 13:14:01.442633 on: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12192 13:14:01.452037 Using<8>[ 19.282953] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12193 13:14:01.452298 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12195 13:14:01.455342 IGT_SRANDOM=1721308441 for randomisation
12196 13:14:01.458793 Opened device: /dev/dri/card0
12197 13:14:01.462398 Starting subtest: invalid-set-prop-any
12198 13:14:01.465265 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12199 13:14:01.468601 <14>[ 19.305020] [IGT] kms_prop_blob: executing
12200 13:14:01.478998 IGT-Version: 1.2<14>[ 19.310511] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12201 13:14:01.485450 8-ga44ebfe (aarc<14>[ 19.318291] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12202 13:14:01.491958 h64) (Linux: 6.1<14>[ 19.327041] [IGT] kms_prop_blob: exiting, ret=0
12203 13:14:01.494915 .96-cip24 aarch64)
12204 13:14:01.505201 Using IGT_SRANDOM=1721308441 for randomisati<8>[ 19.338514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12205 13:14:01.505273 on
12206 13:14:01.505498 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12208 13:14:01.511358 Opened device: /dev/dri/card<8>[ 19.347633] <LAVA_SIGNAL_TESTSET STOP>
12209 13:14:01.511433 0
12210 13:14:01.511655 Received signal: <TESTSET> STOP
12211 13:14:01.511713 Closing test_set kms_prop_blob
12212 13:14:01.515161 Starting subtest: invalid-set-prop
12213 13:14:01.521866 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
12214 13:14:01.535463 <8>[ 19.370746] <LAVA_SIGNAL_TESTSET START kms_setmode>
12215 13:14:01.535706 Received signal: <TESTSET> START kms_setmode
12216 13:14:01.535768 Starting test_set kms_setmode
12217 13:14:01.556617 <14>[ 19.391931] [IGT] kms_setmode: executing
12218 13:14:01.563594 IGT-Version: 1.2<14>[ 19.396741] [IGT] kms_setmode: starting subtest basic
12219 13:14:01.570044 8-ga44ebfe (aarc<14>[ 19.403398] [IGT] kms_setmode: finished subtest basic, SKIP
12220 13:14:01.576487 h64) (Linux: 6.1<14>[ 19.410759] [IGT] kms_setmode: exiting, ret=77
12221 13:14:01.580101 .96-cip24 aarch64)
12222 13:14:01.589952 Using IGT_SRANDOM=1721308441 for randomisati<8>[ 19.422399] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12223 13:14:01.590022 on
12224 13:14:01.590246 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12226 13:14:01.592975 Opened device: /dev/dri/card0
12227 13:14:01.593060 Starting subtest: basic
12228 13:14:01.596379 No dynamic tests executed.
12229 13:14:01.599941 [1mSubtest basic: SKIP (0.000s)[0m
12230 13:14:01.610194 <14>[ 19.445118] [IGT] kms_setmode: executing
12231 13:14:01.616471 IGT-Version: 1.2<14>[ 19.449824] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12232 13:14:01.626495 8-ga44ebfe (aarc<14>[ 19.458172] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12233 13:14:01.633209 h64) (Linux: 6.1<14>[ 19.466991] [IGT] kms_setmode: exiting, ret=77
12234 13:14:01.636362 .96-cip24 aarch64)
12235 13:14:01.640077 Using IGT_SRANDOM=1721308441 for randomisation
12236 13:14:01.646429 Opened devic<8>[ 19.478741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12237 13:14:01.646668 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12239 13:14:01.649407 e: /dev/dri/card0
12240 13:14:01.653180 Starting subtest: basic-clone-single-crtc
12241 13:14:01.656351 No dynamic tests executed.
12242 13:14:01.659864 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12243 13:14:01.669723 <14>[ 19.504897] [IGT] kms_setmode: executing
12244 13:14:01.676474 IGT-Version: 1.2<14>[ 19.509529] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12245 13:14:01.686170 8-ga44ebfe (aarc<14>[ 19.517870] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12246 13:14:01.692762 h64) (Linux: 6.1<14>[ 19.526962] [IGT] kms_setmode: exiting, ret=77
12247 13:14:01.696432 .96-cip24 aarch64)
12248 13:14:01.705886 Using IGT_SRANDOM=1721308441 for randomisati<8>[ 19.538424] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12249 13:14:01.705983 on
12250 13:14:01.706215 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12252 13:14:01.709515 Opened device: /dev/dri/card0
12253 13:14:01.712391 Starting subtest: invalid-clone-single-crtc
12254 13:14:01.715848 No dynamic tests executed.
12255 13:14:01.722741 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12256 13:14:01.725869 <14>[ 19.561107] [IGT] kms_setmode: executing
12257 13:14:01.735816 IGT-Version: 1.2<14>[ 19.565943] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12258 13:14:01.742392 8-ga44ebfe (aarc<14>[ 19.574543] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12259 13:14:01.749423 h64) (Linux: 6.1<14>[ 19.583892] [IGT] kms_setmode: exiting, ret=77
12260 13:14:01.752474 .96-cip24 aarch64)
12261 13:14:01.761981 Using IGT_SRANDOM=1721308441 for randomisati<8>[ 19.594942] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12262 13:14:01.762250 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12264 13:14:01.765759 on
12265 13:14:01.765824 Opened device: /dev/dri/card0
12266 13:14:01.771880 Starting subtest: invalid-clone-exclusive-crtc
12267 13:14:01.771976 No dynamic tests executed.
12268 13:14:01.781920 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0<14>[ 19.617218] [IGT] kms_setmode: executing
12269 13:14:01.782018 .000s)[0m
12270 13:14:01.788312 <14>[ 19.622577] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12271 13:14:01.798579 IGT-Version: 1.2<14>[ 19.630174] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12272 13:14:01.805061 8-ga44ebfe (aarc<14>[ 19.638727] [IGT] kms_setmode: exiting, ret=77
12273 13:14:01.808348 h64) (Linux: 6.1.96-cip24 aarch64)
12274 13:14:01.818343 Using IGT_SRANDOM=1721308441<8>[ 19.649945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12275 13:14:01.818441 for randomisation
12276 13:14:01.818696 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12278 13:14:01.821753 Opened device: /dev/dri/card0
12279 13:14:01.824652 Starting subtest: clone-exclusive-crtc
12280 13:14:01.828439 No dynamic tests executed.
12281 13:14:01.835202 [1mSubtest clone-exclusive-crtc: SKIP (0<14>[ 19.671509] [IGT] kms_setmode: executing
12282 13:14:01.838841 .000s)[0m
12283 13:14:01.845013 <14>[ 19.676836] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12284 13:14:01.854646 IGT-Version: 1.2<14>[ 19.685372] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12285 13:14:01.861028 8-ga44ebfe (aarc<14>[ 19.695300] [IGT] kms_setmode: exiting, ret=77
12286 13:14:01.864774 h64) (Linux: 6.1.96-cip24 aarch64)
12287 13:14:01.874242 Using IGT_SRANDOM=1721308441<8>[ 19.706779] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12288 13:14:01.874503 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12290 13:14:01.881348 for randomisati<8>[ 19.717016] <LAVA_SIGNAL_TESTSET STOP>
12291 13:14:01.881429 on
12292 13:14:01.881668 Received signal: <TESTSET> STOP
12293 13:14:01.881759 Closing test_set kms_setmode
12294 13:14:01.884726 Opened device: /dev/dri/card0
12295 13:14:01.887615 Starting subtest: invalid-clone-single-crtc-stealing
12296 13:14:01.890552 No dynamic tests executed.
12297 13:14:01.897693 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12298 13:14:01.912755 <8>[ 19.748056] <LAVA_SIGNAL_TESTSET START kms_vblank>
12299 13:14:01.913021 Received signal: <TESTSET> START kms_vblank
12300 13:14:01.913086 Starting test_set kms_vblank
12301 13:14:01.939969 <14>[ 19.775102] [IGT] kms_vblank: executing
12302 13:14:01.946636 IGT-Version: 1.2<14>[ 19.780153] [IGT] kms_vblank: exiting, ret=77
12303 13:14:01.949780 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12304 13:14:01.956549 Using IGT_SR<8>[ 19.791384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12305 13:14:01.956817 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12307 13:14:01.959743 ANDOM=1721308441 for randomisation
12308 13:14:01.963270 Opened device: /dev/dri/card0
12309 13:14:01.969413 No KMS driver or no outputs, pipes: 16, outputs: 0
12310 13:14:01.973117 [1mSubtest invalid: SKIP (0.000s)[0m
12311 13:14:01.976143 <14>[ 19.811640] [IGT] kms_vblank: executing
12312 13:14:01.982914 IGT-Version: 1.2<14>[ 19.816492] [IGT] kms_vblank: exiting, ret=77
12313 13:14:01.986184 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12314 13:14:01.992557 Using IGT_SR<8>[ 19.827717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12315 13:14:01.992793 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12317 13:14:01.996173 ANDOM=1721308441 for randomisation
12318 13:14:01.999348 Opened device: /dev/dri/card0
12319 13:14:02.005865 No KMS driver or no outputs, pipes: 16, outputs: 0
12320 13:14:02.008844 [1mSubtest crtc-id: SKIP (0.000s)[0m
12321 13:14:02.012528 <14>[ 19.848090] [IGT] kms_vblank: executing
12322 13:14:02.018918 IGT-Version: 1.2<14>[ 19.852840] [IGT] kms_vblank: exiting, ret=77
12323 13:14:02.022496 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12324 13:14:02.032158 Using IGT_SRANDOM=1721308441<8>[ 19.864958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=accuracy-idle RESULT=skip>
12325 13:14:02.032410 Received signal: <TESTCASE> TEST_CASE_ID=accuracy-idle RESULT=skip
12327 13:14:02.035904 for randomisation
12328 13:14:02.035979 Opened device: /dev/dri/card0
12329 13:14:02.042397 No KMS driver or no outputs, pipes: 16, outputs: 0
12330 13:14:02.046087 [1mSubtest accuracy-idle: SKIP (0.000s)[0m
12331 13:14:02.048972 <14>[ 19.886153] [IGT] kms_vblank: executing
12332 13:14:02.055326 IGT-Version: 1.2<14>[ 19.890921] [IGT] kms_vblank: exiting, ret=77
12333 13:14:02.062133 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12334 13:14:02.068852 Using IGT_SRANDOM=1721308441<8>[ 19.902942] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle RESULT=skip>
12335 13:14:02.069122 Received signal: <TESTCASE> TEST_CASE_ID=query-idle RESULT=skip
12337 13:14:02.072455 for randomisation
12338 13:14:02.075590 Opened device: /dev/dri/card0
12339 13:14:02.078523 No KMS driver or no outputs, pipes: 16, outputs: 0
12340 13:14:02.082365 [1mSubtest query-idle: SKIP (0.000s)[0m
12341 13:14:02.091174 <14>[ 19.926467] [IGT] kms_vblank: executing
12342 13:14:02.098002 IGT-Version: 1.2<14>[ 19.931132] [IGT] kms_vblank: exiting, ret=77
12343 13:14:02.101113 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12344 13:14:02.111224 Using IGT_SRANDOM=1721308441<8>[ 19.943295] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle-hang RESULT=skip>
12345 13:14:02.111340 for randomisation
12346 13:14:02.111563 Received signal: <TESTCASE> TEST_CASE_ID=query-idle-hang RESULT=skip
12348 13:14:02.114271 Opened device: /dev/dri/card0
12349 13:14:02.120934 No KMS driver or no outputs, pipes: 16, outputs: 0
12350 13:14:02.124167 [1mSubtest query-idle-hang: SKIP (0.000s)[0m
12351 13:14:02.130906 <14>[ 19.966262] [IGT] kms_vblank: executing
12352 13:14:02.137905 IGT-Version: 1.2<14>[ 19.970972] [IGT] kms_vblank: exiting, ret=77
12353 13:14:02.141033 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12354 13:14:02.151114 Using IGT_SRANDOM=1721308442<8>[ 19.983517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked RESULT=skip>
12355 13:14:02.151225 for randomisation
12356 13:14:02.151460 Received signal: <TESTCASE> TEST_CASE_ID=query-forked RESULT=skip
12358 13:14:02.154554 Opened device: /dev/dri/card0
12359 13:14:02.160541 No KMS driver or no outputs, pipes: 16, outputs: 0
12360 13:14:02.164360 [1mSubtest query-forked: SKIP (0.000s)[0m
12361 13:14:02.170371 <14>[ 20.005096] [IGT] kms_vblank: executing
12362 13:14:02.174166 IGT-Version: 1.2<14>[ 20.009715] [IGT] kms_vblank: exiting, ret=77
12363 13:14:02.180396 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12364 13:14:02.186804 Using IGT_SR<8>[ 20.020851] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-hang RESULT=skip>
12365 13:14:02.187071 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-hang RESULT=skip
12367 13:14:02.190562 ANDOM=1721308442 for randomisation
12368 13:14:02.193861 Opened device: /dev/dri/card0
12369 13:14:02.200371 No KMS driver or no outputs, pipes: 16, outputs: 0
12370 13:14:02.207112 [1mSubtest query-forked-hang: SKIP (0.00<14>[ 20.041605] [IGT] kms_vblank: executing
12371 13:14:02.207240 0s)[0m
12372 13:14:02.213609 <14>[ 20.047137] [IGT] kms_vblank: exiting, ret=77
12373 13:14:02.216939 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12374 13:14:02.226632 Using IGT_SR<8>[ 20.058399] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy RESULT=skip>
12375 13:14:02.226933 Received signal: <TESTCASE> TEST_CASE_ID=query-busy RESULT=skip
12377 13:14:02.229617 ANDOM=1721308442 for randomisation
12378 13:14:02.229687 Opened device: /dev/dri/card0
12379 13:14:02.236502 No KMS driver or no outputs, pipes: 16, outputs: 0
12380 13:14:02.243596 [1mSubtest query-busy: SKIP (0.000s)[0m<14>[ 20.079515] [IGT] kms_vblank: executing
12381 13:14:02.243707
12382 13:14:02.249998 IGT-Version: 1.2<14>[ 20.084485] [IGT] kms_vblank: exiting, ret=77
12383 13:14:02.253042 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12384 13:14:02.263165 Using IGT_SR<8>[ 20.095684] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy-hang RESULT=skip>
12385 13:14:02.263467 Received signal: <TESTCASE> TEST_CASE_ID=query-busy-hang RESULT=skip
12387 13:14:02.266381 ANDOM=1721308442 for randomisation
12388 13:14:02.269414 Opened device: /dev/dri/card0
12389 13:14:02.272753 No KMS driver or no outputs, pipes: 16, outputs: 0
12390 13:14:02.279923 [1mSubtest query-busy-hang: SKIP (0.000s<14>[ 20.116758] [IGT] kms_vblank: executing
12391 13:14:02.283000 )[0m
12392 13:14:02.286186 <14>[ 20.121725] [IGT] kms_vblank: exiting, ret=77
12393 13:14:02.299444 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch6<8>[ 20.131387] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy RESULT=skip>
12394 13:14:02.299568 4)
12395 13:14:02.299804 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy RESULT=skip
12397 13:14:02.302769 Using IGT_SRANDOM=1721308442 for randomisation
12398 13:14:02.305902 Opened device: /dev/dri/card0
12399 13:14:02.312846 No KMS driver or no outputs, pipes: 16, outputs: 0
12400 13:14:02.316188 [1mSubtest query-forked-busy: SKIP (0.000s)[0m
12401 13:14:02.328934 <14>[ 20.163959] [IGT] kms_vblank: executing
12402 13:14:02.335654 IGT-Version: 1.2<14>[ 20.168881] [IGT] kms_vblank: exiting, ret=77
12403 13:14:02.338825 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12404 13:14:02.349004 Using IGT_SRANDOM=1721308442<8>[ 20.181393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy-hang RESULT=skip>
12405 13:14:02.349257 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy-hang RESULT=skip
12407 13:14:02.352044 for randomisation
12408 13:14:02.352120 Opened device: /dev/dri/card0
12409 13:14:02.359031 No KMS driver or no outputs, pipes: 16, outputs: 0
12410 13:14:02.362069 [1mSubtest query-forked-busy-hang: SKIP (0.000s)[0m
12411 13:14:02.368879 <14>[ 20.203439] [IGT] kms_vblank: executing
12412 13:14:02.372236 IGT-Version: 1.2<14>[ 20.208062] [IGT] kms_vblank: exiting, ret=77
12413 13:14:02.378676 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12414 13:14:02.385145 Using IGT_SR<8>[ 20.219271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle RESULT=skip>
12415 13:14:02.385397 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle RESULT=skip
12417 13:14:02.388291 ANDOM=1721308442 for randomisation
12418 13:14:02.392225 Opened device: /dev/dri/card0
12419 13:14:02.395411 No KMS driver or no outputs, pipes: 16, outputs: 0
12420 13:14:02.398493 [1mSubtest wait-idle: SKIP (0.000s)[0m
12421 13:14:02.407663 <14>[ 20.242626] [IGT] kms_vblank: executing
12422 13:14:02.414160 IGT-Version: 1.2<14>[ 20.247253] [IGT] kms_vblank: exiting, ret=77
12423 13:14:02.417149 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12424 13:14:02.427193 Using IGT_SRANDOM=1721308442<8>[ 20.258735] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle-hang RESULT=skip>
12425 13:14:02.427279 for randomisation
12426 13:14:02.427508 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle-hang RESULT=skip
12428 13:14:02.430333 Opened device: /dev/dri/card0
12429 13:14:02.437497 No KMS driver or no outputs, pipes: 16, outputs: 0
12430 13:14:02.440717 [1mSubtest wait-idle-hang: SKIP (0.000s)[0m
12431 13:14:02.448940 <14>[ 20.284105] [IGT] kms_vblank: executing
12432 13:14:02.455314 IGT-Version: 1.2<14>[ 20.288850] [IGT] kms_vblank: exiting, ret=77
12433 13:14:02.458537 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12434 13:14:02.465597 Using IGT_SR<8>[ 20.300175] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked RESULT=skip>
12435 13:14:02.465842 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked RESULT=skip
12437 13:14:02.468795 ANDOM=1721308442 for randomisation
12438 13:14:02.471902 Opened device: /dev/dri/card0
12439 13:14:02.478719 No KMS driver or no outputs, pipes: 16, outputs: 0
12440 13:14:02.485022 [1mSubtest wait-forked: SKIP (0.000s)[0<14>[ 20.320535] [IGT] kms_vblank: executing
12441 13:14:02.485101 m
12442 13:14:02.491658 IGT-Version: 1.2<14>[ 20.325704] [IGT] kms_vblank: exiting, ret=77
12443 13:14:02.494782 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12444 13:14:02.504852 Using IGT_SRANDOM=1721308442<8>[ 20.338060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-hang RESULT=skip>
12445 13:14:02.505099 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-hang RESULT=skip
12447 13:14:02.507942 for randomisation
12448 13:14:02.511660 Opened device: /dev/dri/card0
12449 13:14:02.514649 No KMS driver or no outputs, pipes: 16, outputs: 0
12450 13:14:02.518227 [1mSubtest wait-forked-hang: SKIP (0.000s)[0m
12451 13:14:02.524772 <14>[ 20.359627] [IGT] kms_vblank: executing
12452 13:14:02.528485 IGT-Version: 1.2<14>[ 20.364351] [IGT] kms_vblank: exiting, ret=77
12453 13:14:02.534797 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12454 13:14:02.541733 Using IGT_SR<8>[ 20.375321] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy RESULT=skip>
12455 13:14:02.541980 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy RESULT=skip
12457 13:14:02.544783 ANDOM=1721308442 for randomisation
12458 13:14:02.548060 Opened device: /dev/dri/card0
12459 13:14:02.551581 No KMS driver or no outputs, pipes: 16, outputs: 0
12460 13:14:02.554518 [1mSubtest wait-busy: SKIP (0.000s)[0m
12461 13:14:02.561000 <14>[ 20.395738] [IGT] kms_vblank: executing
12462 13:14:02.561077
12463 13:14:02.567967 IGT-Version: 1.2<14>[ 20.400842] [IGT] kms_vblank: exiting, ret=77
12464 13:14:02.571338 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12465 13:14:02.577468 Using IGT_SR<8>[ 20.412153] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy-hang RESULT=skip>
12466 13:14:02.577730 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy-hang RESULT=skip
12468 13:14:02.581480 ANDOM=1721308442 for randomisation
12469 13:14:02.584336 Opened device: /dev/dri/card0
12470 13:14:02.591156 No KMS driver or no outputs, pipes: 16, outputs: 0
12471 13:14:02.594259 [1mSubtest wait-busy-hang: SKIP (0.000s)[0m
12472 13:14:02.600796 <14>[ 20.435910] [IGT] kms_vblank: executing
12473 13:14:02.607710 IGT-Version: 1.2<14>[ 20.440536] [IGT] kms_vblank: exiting, ret=77
12474 13:14:02.610923 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12475 13:14:02.620998 Using IGT_SRANDOM=1721308442<8>[ 20.451909] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy RESULT=skip>
12476 13:14:02.621076 for randomisation
12477 13:14:02.621304 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy RESULT=skip
12479 13:14:02.624056 Opened device: /dev/dri/card0
12480 13:14:02.630619 No KMS driver or no outputs, pipes: 16, outputs: 0
12481 13:14:02.633654 [1mSubtest wait-forked-busy: SKIP (0.000s)[0m
12482 13:14:02.641744 <14>[ 20.477247] [IGT] kms_vblank: executing
12483 13:14:02.648415 IGT-Version: 1.2<14>[ 20.481878] [IGT] kms_vblank: exiting, ret=77
12484 13:14:02.652223 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12485 13:14:02.661675 Using IGT_SR<8>[ 20.493193] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy-hang RESULT=skip>
12486 13:14:02.661926 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy-hang RESULT=skip
12488 13:14:02.665544 ANDOM=1721308442 for randomisation
12489 13:14:02.665619 Opened device: /dev/dri/card0
12490 13:14:02.671909 No KMS driver or no outputs, pipes: 16, outputs: 0
12491 13:14:02.678138 [1mSubtest wait-forked-busy-hang: SKIP (<14>[ 20.514604] [IGT] kms_vblank: executing
12492 13:14:02.678221 0.000s)[0m
12493 13:14:02.685120 <14>[ 20.519523] [IGT] kms_vblank: exiting, ret=77
12494 13:14:02.691732 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12495 13:14:02.697951 Using IGT_SR<8>[ 20.531301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle RESULT=skip>
12496 13:14:02.698205 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle RESULT=skip
12498 13:14:02.701597 ANDOM=1721308442 for randomisation
12499 13:14:02.704883 Opened device: /dev/dri/card0
12500 13:14:02.707901 No KMS driver or no outputs, pipes: 16, outputs: 0
12501 13:14:02.717985 [1mSubtest ts-continuation-idle: SKIP (0<14>[ 20.553133] [IGT] kms_vblank: executing
12502 13:14:02.718058 .000s)[0m
12503 13:14:02.724985 <14>[ 20.558146] [IGT] kms_vblank: exiting, ret=77
12504 13:14:02.737603 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch6<8>[ 20.568875] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip>
12505 13:14:02.737686 4)
12506 13:14:02.737924 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip
12508 13:14:02.741173 Using IGT_SRANDOM=1721308442 for randomisation
12509 13:14:02.744370 Opened device: /dev/dri/card0
12510 13:14:02.747489 No KMS driver or no outputs, pipes: 16, outputs: 0
12511 13:14:02.754447 [1mSubtest ts-continuation-idle-hang: SKIP (0.000s)[0m
12512 13:14:02.757812 <14>[ 20.593743] [IGT] kms_vblank: executing
12513 13:14:02.757916
12514 13:14:02.763998 IGT-Version: 1.2<14>[ 20.598680] [IGT] kms_vblank: exiting, ret=77
12515 13:14:02.767526 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12516 13:14:02.780698 Using IGT_SRANDOM=1721308442<8>[ 20.610096] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip>
12517 13:14:02.780785 for randomisation
12518 13:14:02.781015 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip
12520 13:14:02.783885 Opened device: /dev/dri/card0
12521 13:14:02.786973 No KMS driver or no outputs, pipes: 16, outputs: 0
12522 13:14:02.793789 [1mSubtest ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12523 13:14:02.796955 <14>[ 20.632733] [IGT] kms_vblank: executing
12524 13:14:02.803763 IGT-Version: 1.2<14>[ 20.638122] [IGT] kms_vblank: exiting, ret=77
12525 13:14:02.807019 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12526 13:14:02.820152 Using IGT_SRANDOM=1721308442<8>[ 20.649804] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip>
12527 13:14:02.820242 for randomisation
12528 13:14:02.820471 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip
12530 13:14:02.823843 Opened device: /dev/dri/card0
12531 13:14:02.826890 No KMS driver or no outputs, pipes: 16, outputs: 0
12532 13:14:02.837057 [1mSubtest ts-continuation-dpms-suspend: SKIP (0.000s)[<14>[ 20.673072] [IGT] kms_vblank: executing
12533 13:14:02.837166 0m
12534 13:14:02.843716 IGT-Version: 1.2<14>[ 20.677782] [IGT] kms_vblank: exiting, ret=77
12535 13:14:02.846624 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12536 13:14:02.856747 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-suspend RESULT=skip
12538 13:14:02.859640 Using IGT_SRANDOM=1721308442<8>[ 20.689384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-suspend RESULT=skip>
12539 13:14:02.859715 for randomisation
12540 13:14:02.863441 Opened device: /dev/dri/card0
12541 13:14:02.866480 No KMS driver or no outputs, pipes: 16, outputs: 0
12542 13:14:02.873120 [1mSubtest ts-continuation-suspend: SKIP (0.000s)[0m
12543 13:14:02.879919 <14>[ 20.715011] [IGT] kms_vblank: executing
12544 13:14:02.886219 IGT-Version: 1.2<14>[ 20.719765] [IGT] kms_vblank: exiting, ret=77
12545 13:14:02.889435 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12546 13:14:02.899293 Using IGT_SR<8>[ 20.730766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset RESULT=skip>
12547 13:14:02.899550 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset RESULT=skip
12549 13:14:02.903166 ANDOM=1721308442 for randomisation
12550 13:14:02.903242 Opened device: /dev/dri/card0
12551 13:14:02.909599 No KMS driver or no outputs, pipes: 16, outputs: 0
12552 13:14:02.912771 [1mSubtest ts-continuation-modeset: SKIP (0.000s)[0m
12553 13:14:02.919843 <14>[ 20.755231] [IGT] kms_vblank: executing
12554 13:14:02.926748 IGT-Version: 1.2<14>[ 20.760005] [IGT] kms_vblank: exiting, ret=77
12555 13:14:02.929909 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12556 13:14:02.939470 Using IGT_SR<8>[ 20.771260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip>
12557 13:14:02.939720 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip
12559 13:14:02.943077 ANDOM=1721308442 for randomisation
12560 13:14:02.946297 Opened device: /dev/dri/card0
12561 13:14:02.950170 No KMS driver or no outputs, pipes: 16, outputs: 0
12562 13:14:02.956394 [1mSubtest ts-continuation-modeset-hang:<14>[ 20.793161] [IGT] kms_vblank: executing
12563 13:14:02.962978 SKIP (0.000s)[<14>[ 20.798369] [IGT] kms_vblank: exiting, ret=77
12564 13:14:02.963061 0m
12565 13:14:02.976183 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aa<8>[ 20.809257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip>
12566 13:14:02.976513 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip
12568 13:14:02.979621 rch64)
12569 13:14:02.982541 Using IGT_SRANDOM=172130<8>[ 20.819240] <LAVA_SIGNAL_TESTSET STOP>
12570 13:14:02.982791 Received signal: <TESTSET> STOP
12571 13:14:02.982869 Closing test_set kms_vblank
12572 13:14:02.992749 8442 for randomi<8>[ 20.825403] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 14879019_1.5.2.3.1>
12573 13:14:02.992873 sation
12574 13:14:02.993131 Received signal: <ENDRUN> 0_igt-kms-mediatek 14879019_1.5.2.3.1
12575 13:14:02.993235 Ending use of test pattern.
12576 13:14:02.993289 Ending test lava.0_igt-kms-mediatek (14879019_1.5.2.3.1), duration 6.50
12578 13:14:02.996027 Opened device: /dev/dri/card0
12579 13:14:02.998996 No KMS driver or no outputs, pipes: 16, outputs: 0
12580 13:14:03.005665 [1mSubtest ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12581 13:14:03.005748 + set +x
12582 13:14:03.008911 <LAVA_TEST_RUNNER EXIT>
12583 13:14:03.009161 ok: lava_test_shell seems to have completed
12584 13:14:03.010563 getclient-simple:
set: core_auth
result: pass
getclient-master-drop:
set: core_auth
result: pass
basic-auth:
set: core_auth
result: pass
many-magics:
set: core_auth
result: pass
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
invalid-buffer:
set: drm_read
result: skip
fault-buffer:
set: drm_read
result: skip
empty-block:
set: drm_read
result: skip
empty-nonblock:
set: drm_read
result: skip
short-buffer-block:
set: drm_read
result: skip
short-buffer-nonblock:
set: drm_read
result: skip
short-buffer-wakeup:
set: drm_read
result: skip
unused-handle:
set: kms_addfb_basic
result: pass
unused-pitches:
set: kms_addfb_basic
result: pass
unused-offsets:
set: kms_addfb_basic
result: pass
unused-modifier:
set: kms_addfb_basic
result: pass
clobberred-modifier:
set: kms_addfb_basic
result: skip
invalid-smem-bo-on-discrete:
set: kms_addfb_basic
result: skip
legacy-format:
set: kms_addfb_basic
result: pass
no-handle:
set: kms_addfb_basic
result: pass
basic:
set: kms_setmode
result: skip
bad-pitch-0:
set: kms_addfb_basic
result: pass
bad-pitch-32:
set: kms_addfb_basic
result: pass
bad-pitch-63:
set: kms_addfb_basic
result: pass
bad-pitch-128:
set: kms_addfb_basic
result: pass
bad-pitch-256:
set: kms_addfb_basic
result: pass
bad-pitch-1024:
set: kms_addfb_basic
result: pass
bad-pitch-999:
set: kms_addfb_basic
result: pass
bad-pitch-65536:
set: kms_addfb_basic
result: pass
invalid-get-prop-any:
set: kms_prop_blob
result: pass
invalid-get-prop:
set: kms_prop_blob
result: pass
invalid-set-prop-any:
set: kms_prop_blob
result: pass
invalid-set-prop:
set: kms_prop_blob
result: pass
master-rmfb:
set: kms_addfb_basic
result: pass
addfb25-modifier-no-flag:
set: kms_addfb_basic
result: pass
addfb25-bad-modifier:
set: kms_addfb_basic
result: fail
addfb25-x-tiled-mismatch-legacy:
set: kms_addfb_basic
result: skip
addfb25-x-tiled-legacy:
set: kms_addfb_basic
result: skip
addfb25-framebuffer-vs-set-tiling:
set: kms_addfb_basic
result: skip
basic-x-tiled-legacy:
set: kms_addfb_basic
result: skip
framebuffer-vs-set-tiling:
set: kms_addfb_basic
result: skip
tile-pitch-mismatch:
set: kms_addfb_basic
result: skip
basic-y-tiled-legacy:
set: kms_addfb_basic
result: skip
size-max:
set: kms_addfb_basic
result: skip
too-wide:
set: kms_addfb_basic
result: skip
too-high:
set: kms_addfb_basic
result: skip
bo-too-small:
set: kms_addfb_basic
result: skip
small-bo:
set: kms_addfb_basic
result: skip
bo-too-small-due-to-tiling:
set: kms_addfb_basic
result: skip
addfb25-y-tiled-legacy:
set: kms_addfb_basic
result: skip
addfb25-yf-tiled-legacy:
set: kms_addfb_basic
result: skip
addfb25-y-tiled-small-legacy:
set: kms_addfb_basic
result: skip
addfb25-4-tiled:
set: kms_addfb_basic
result: skip
plane-overlay-legacy:
set: kms_atomic
result: skip
plane-primary-legacy:
set: kms_atomic
result: skip
plane-primary-overlay-mutable-zpos:
set: kms_atomic
result: skip
plane-immutable-zpos:
set: kms_atomic
result: skip
test-only:
set: kms_atomic
result: skip
plane-cursor-legacy:
set: kms_atomic
result: skip
plane-invalid-params:
set: kms_atomic
result: skip
plane-invalid-params-fence:
set: kms_atomic
result: skip
crtc-invalid-params:
set: kms_atomic
result: skip
crtc-invalid-params-fence:
set: kms_atomic
result: skip
atomic-invalid-params:
set: kms_atomic
result: skip
atomic-plane-damage:
set: kms_atomic
result: skip
blob-prop-core:
set: kms_prop_blob
result: pass
blob-prop-validate:
set: kms_prop_blob
result: pass
blob-prop-lifetime:
set: kms_prop_blob
result: pass
blob-multiple:
set: kms_prop_blob
result: pass
basic-clone-single-crtc:
set: kms_setmode
result: skip
invalid-clone-single-crtc:
set: kms_setmode
result: skip
invalid-clone-exclusive-crtc:
set: kms_setmode
result: skip
clone-exclusive-crtc:
set: kms_setmode
result: skip
invalid-clone-single-crtc-stealing:
set: kms_setmode
result: skip
invalid:
set: kms_vblank
result: skip
crtc-id:
set: kms_vblank
result: skip
accuracy-idle:
set: kms_vblank
result: skip
query-idle:
set: kms_vblank
result: skip
query-idle-hang:
set: kms_vblank
result: skip
query-forked:
set: kms_vblank
result: skip
query-forked-hang:
set: kms_vblank
result: skip
query-busy:
set: kms_vblank
result: skip
query-busy-hang:
set: kms_vblank
result: skip
query-forked-busy:
set: kms_vblank
result: skip
query-forked-busy-hang:
set: kms_vblank
result: skip
wait-idle:
set: kms_vblank
result: skip
wait-idle-hang:
set: kms_vblank
result: skip
wait-forked:
set: kms_vblank
result: skip
wait-forked-hang:
set: kms_vblank
result: skip
wait-busy:
set: kms_vblank
result: skip
wait-busy-hang:
set: kms_vblank
result: skip
wait-forked-busy:
set: kms_vblank
result: skip
wait-forked-busy-hang:
set: kms_vblank
result: skip
ts-continuation-idle:
set: kms_vblank
result: skip
ts-continuation-idle-hang:
set: kms_vblank
result: skip
ts-continuation-dpms-rpm:
set: kms_vblank
result: skip
ts-continuation-dpms-suspend:
set: kms_vblank
result: skip
ts-continuation-suspend:
set: kms_vblank
result: skip
ts-continuation-modeset:
set: kms_vblank
result: skip
ts-continuation-modeset-hang:
set: kms_vblank
result: skip
ts-continuation-modeset-rpm:
set: kms_vblank
result: skip
12585 13:14:03.010736 end: 3.1 lava-test-shell (duration 00:00:07) [common]
12586 13:14:03.228961 end: 3 lava-test-retry (duration 00:00:07) [common]
12587 13:14:03.229133 start: 4 finalize (timeout 00:07:07) [common]
12588 13:14:03.229265 start: 4.1 power-off (timeout 00:00:30) [common]
12589 13:14:03.229517 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
12590 13:14:05.310704 >> Command sent successfully.
12591 13:14:05.314614 Returned 0 in 2 seconds
12592 13:14:05.314751 end: 4.1 power-off (duration 00:00:02) [common]
12594 13:14:05.314941 start: 4.2 read-feedback (timeout 00:07:05) [common]
12595 13:14:05.315073 Listened to connection for namespace 'common' for up to 1s
12596 13:14:06.316094 Finalising connection for namespace 'common'
12597 13:14:06.316242 Disconnecting from shell: Finalise
12598 13:14:06.316307 / #
12599 13:14:06.416571 end: 4.2 read-feedback (duration 00:00:01) [common]
12600 13:14:06.416715 end: 4 finalize (duration 00:00:03) [common]
12601 13:14:06.416814 Cleaning after the job
12602 13:14:06.416902 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879019/tftp-deploy-b23ufq6g/ramdisk
12603 13:14:06.423353 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879019/tftp-deploy-b23ufq6g/kernel
12604 13:14:06.438807 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879019/tftp-deploy-b23ufq6g/dtb
12605 13:14:06.439005 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879019/tftp-deploy-b23ufq6g/modules
12606 13:14:06.444442 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14879019
12607 13:14:06.553943 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14879019
12608 13:14:06.554172 Job finished correctly