Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 33
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 13:07:28.818446 lava-dispatcher, installed at version: 2024.05
2 13:07:28.818633 start: 0 validate
3 13:07:28.818754 Start time: 2024-07-18 13:07:28.818744+00:00 (UTC)
4 13:07:28.818883 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:07:28.819014 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 13:07:29.081903 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:07:29.082618 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 13:07:43.844128 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:07:43.844311 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:07:44.101578 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:07:44.101764 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:07:44.612916 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:07:44.613115 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 13:07:48.117474 validate duration: 19.30
16 13:07:48.117730 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:07:48.117826 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:07:48.117906 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:07:48.118050 Not decompressing ramdisk as can be used compressed.
20 13:07:48.118133 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 13:07:48.118191 saving as /var/lib/lava/dispatcher/tmp/14879017/tftp-deploy-1qe5qw7y/ramdisk/initrd.cpio.gz
22 13:07:48.118246 total size: 5628169 (5 MB)
23 13:07:48.375830 progress 0 % (0 MB)
24 13:07:48.377518 progress 5 % (0 MB)
25 13:07:48.379066 progress 10 % (0 MB)
26 13:07:48.380480 progress 15 % (0 MB)
27 13:07:48.382126 progress 20 % (1 MB)
28 13:07:48.383511 progress 25 % (1 MB)
29 13:07:48.385031 progress 30 % (1 MB)
30 13:07:48.386565 progress 35 % (1 MB)
31 13:07:48.387919 progress 40 % (2 MB)
32 13:07:48.389454 progress 45 % (2 MB)
33 13:07:48.390788 progress 50 % (2 MB)
34 13:07:48.392271 progress 55 % (2 MB)
35 13:07:48.393803 progress 60 % (3 MB)
36 13:07:48.395131 progress 65 % (3 MB)
37 13:07:48.396616 progress 70 % (3 MB)
38 13:07:48.397985 progress 75 % (4 MB)
39 13:07:48.399482 progress 80 % (4 MB)
40 13:07:48.400812 progress 85 % (4 MB)
41 13:07:48.402346 progress 90 % (4 MB)
42 13:07:48.403835 progress 95 % (5 MB)
43 13:07:48.405284 progress 100 % (5 MB)
44 13:07:48.405497 5 MB downloaded in 0.29 s (18.69 MB/s)
45 13:07:48.405646 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:07:48.405863 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:07:48.405942 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:07:48.406016 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:07:48.406153 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 13:07:48.406214 saving as /var/lib/lava/dispatcher/tmp/14879017/tftp-deploy-1qe5qw7y/kernel/Image
52 13:07:48.406268 total size: 54813184 (52 MB)
53 13:07:48.406322 No compression specified
54 13:07:48.407340 progress 0 % (0 MB)
55 13:07:48.421276 progress 5 % (2 MB)
56 13:07:48.435372 progress 10 % (5 MB)
57 13:07:48.449089 progress 15 % (7 MB)
58 13:07:48.462811 progress 20 % (10 MB)
59 13:07:48.476740 progress 25 % (13 MB)
60 13:07:48.490675 progress 30 % (15 MB)
61 13:07:48.505381 progress 35 % (18 MB)
62 13:07:48.519417 progress 40 % (20 MB)
63 13:07:48.533059 progress 45 % (23 MB)
64 13:07:48.547169 progress 50 % (26 MB)
65 13:07:48.561318 progress 55 % (28 MB)
66 13:07:48.574887 progress 60 % (31 MB)
67 13:07:48.588930 progress 65 % (34 MB)
68 13:07:48.602521 progress 70 % (36 MB)
69 13:07:48.616318 progress 75 % (39 MB)
70 13:07:48.630188 progress 80 % (41 MB)
71 13:07:48.643642 progress 85 % (44 MB)
72 13:07:48.657357 progress 90 % (47 MB)
73 13:07:48.671429 progress 95 % (49 MB)
74 13:07:48.684975 progress 100 % (52 MB)
75 13:07:48.685269 52 MB downloaded in 0.28 s (187.36 MB/s)
76 13:07:48.685449 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:07:48.685705 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:07:48.685814 start: 1.3 download-retry (timeout 00:09:59) [common]
80 13:07:48.685920 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 13:07:48.686083 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:07:48.686147 saving as /var/lib/lava/dispatcher/tmp/14879017/tftp-deploy-1qe5qw7y/dtb/mt8192-asurada-spherion-r0.dtb
83 13:07:48.686229 total size: 47258 (0 MB)
84 13:07:48.686283 No compression specified
85 13:07:48.687437 progress 69 % (0 MB)
86 13:07:48.687700 progress 100 % (0 MB)
87 13:07:48.687866 0 MB downloaded in 0.00 s (27.32 MB/s)
88 13:07:48.687995 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:07:48.688268 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:07:48.688393 start: 1.4 download-retry (timeout 00:09:59) [common]
92 13:07:48.688507 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 13:07:48.688653 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 13:07:48.688715 saving as /var/lib/lava/dispatcher/tmp/14879017/tftp-deploy-1qe5qw7y/nfsrootfs/full.rootfs.tar
95 13:07:48.688769 total size: 120894716 (115 MB)
96 13:07:48.688825 Using unxz to decompress xz
97 13:07:48.690063 progress 0 % (0 MB)
98 13:07:49.037230 progress 5 % (5 MB)
99 13:07:49.386187 progress 10 % (11 MB)
100 13:07:49.733124 progress 15 % (17 MB)
101 13:07:50.065209 progress 20 % (23 MB)
102 13:07:50.374228 progress 25 % (28 MB)
103 13:07:50.730614 progress 30 % (34 MB)
104 13:07:51.071768 progress 35 % (40 MB)
105 13:07:51.253482 progress 40 % (46 MB)
106 13:07:51.443498 progress 45 % (51 MB)
107 13:07:51.761073 progress 50 % (57 MB)
108 13:07:52.148175 progress 55 % (63 MB)
109 13:07:52.513003 progress 60 % (69 MB)
110 13:07:52.876036 progress 65 % (74 MB)
111 13:07:53.232106 progress 70 % (80 MB)
112 13:07:53.592276 progress 75 % (86 MB)
113 13:07:53.930068 progress 80 % (92 MB)
114 13:07:54.270222 progress 85 % (98 MB)
115 13:07:54.627282 progress 90 % (103 MB)
116 13:07:54.965033 progress 95 % (109 MB)
117 13:07:55.347057 progress 100 % (115 MB)
118 13:07:55.352535 115 MB downloaded in 6.66 s (17.30 MB/s)
119 13:07:55.352715 end: 1.4.1 http-download (duration 00:00:07) [common]
121 13:07:55.352935 end: 1.4 download-retry (duration 00:00:07) [common]
122 13:07:55.353015 start: 1.5 download-retry (timeout 00:09:53) [common]
123 13:07:55.353091 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 13:07:55.353233 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 13:07:55.353297 saving as /var/lib/lava/dispatcher/tmp/14879017/tftp-deploy-1qe5qw7y/modules/modules.tar
126 13:07:55.353352 total size: 8611320 (8 MB)
127 13:07:55.353408 Using unxz to decompress xz
128 13:07:55.611985 progress 0 % (0 MB)
129 13:07:55.632420 progress 5 % (0 MB)
130 13:07:55.656769 progress 10 % (0 MB)
131 13:07:55.680197 progress 15 % (1 MB)
132 13:07:55.704578 progress 20 % (1 MB)
133 13:07:55.727445 progress 25 % (2 MB)
134 13:07:55.751066 progress 30 % (2 MB)
135 13:07:55.773381 progress 35 % (2 MB)
136 13:07:55.799893 progress 40 % (3 MB)
137 13:07:55.824398 progress 45 % (3 MB)
138 13:07:55.848640 progress 50 % (4 MB)
139 13:07:55.874170 progress 55 % (4 MB)
140 13:07:55.898790 progress 60 % (4 MB)
141 13:07:55.922147 progress 65 % (5 MB)
142 13:07:55.947605 progress 70 % (5 MB)
143 13:07:55.974708 progress 75 % (6 MB)
144 13:07:56.002396 progress 80 % (6 MB)
145 13:07:56.026500 progress 85 % (7 MB)
146 13:07:56.049940 progress 90 % (7 MB)
147 13:07:56.073027 progress 95 % (7 MB)
148 13:07:56.095743 progress 100 % (8 MB)
149 13:07:56.101348 8 MB downloaded in 0.75 s (10.98 MB/s)
150 13:07:56.101565 end: 1.5.1 http-download (duration 00:00:01) [common]
152 13:07:56.101904 end: 1.5 download-retry (duration 00:00:01) [common]
153 13:07:56.102023 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 13:07:56.102140 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 13:08:00.062460 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14879017/extract-nfsrootfs-jt9hskzb
156 13:08:00.062633 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 13:08:00.062761 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 13:08:00.062961 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa
159 13:08:00.063127 makedir: /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin
160 13:08:00.063258 makedir: /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/tests
161 13:08:00.063384 makedir: /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/results
162 13:08:00.063510 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-add-keys
163 13:08:00.063696 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-add-sources
164 13:08:00.063872 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-background-process-start
165 13:08:00.064026 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-background-process-stop
166 13:08:00.064156 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-common-functions
167 13:08:00.064278 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-echo-ipv4
168 13:08:00.064397 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-install-packages
169 13:08:00.064514 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-installed-packages
170 13:08:00.064627 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-os-build
171 13:08:00.064742 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-probe-channel
172 13:08:00.064857 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-probe-ip
173 13:08:00.064971 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-target-ip
174 13:08:00.065083 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-target-mac
175 13:08:00.065203 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-target-storage
176 13:08:00.065321 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-test-case
177 13:08:00.065439 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-test-event
178 13:08:00.065552 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-test-feedback
179 13:08:00.065665 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-test-raise
180 13:08:00.065781 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-test-reference
181 13:08:00.065896 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-test-runner
182 13:08:00.066007 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-test-set
183 13:08:00.066119 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-test-shell
184 13:08:00.066235 Updating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-add-keys (debian)
185 13:08:00.089084 Updating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-add-sources (debian)
186 13:08:00.089283 Updating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-install-packages (debian)
187 13:08:00.089425 Updating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-installed-packages (debian)
188 13:08:00.089560 Updating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/bin/lava-os-build (debian)
189 13:08:00.089676 Creating /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/environment
190 13:08:00.089771 LAVA metadata
191 13:08:00.089839 - LAVA_JOB_ID=14879017
192 13:08:00.089897 - LAVA_DISPATCHER_IP=192.168.201.1
193 13:08:00.090002 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 13:08:00.090060 skipped lava-vland-overlay
195 13:08:00.090128 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 13:08:00.090202 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 13:08:00.090256 skipped lava-multinode-overlay
198 13:08:00.090320 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 13:08:00.090391 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 13:08:00.090456 Loading test definitions
201 13:08:00.090531 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 13:08:00.090589 Using /lava-14879017 at stage 0
203 13:08:00.090868 uuid=14879017_1.6.2.3.1 testdef=None
204 13:08:00.090948 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 13:08:00.091024 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 13:08:00.091425 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 13:08:00.091623 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 13:08:00.140487 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 13:08:00.140860 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 13:08:00.179661 runner path: /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/0/tests/0_timesync-off test_uuid 14879017_1.6.2.3.1
213 13:08:00.179881 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 13:08:00.180145 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 13:08:00.180231 Using /lava-14879017 at stage 0
217 13:08:00.180354 Fetching tests from https://github.com/kernelci/test-definitions.git
218 13:08:00.180454 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/0/tests/1_kselftest-dt'
219 13:08:03.882447 Running '/usr/bin/git checkout kernelci.org
220 13:08:04.251730 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 13:08:04.252456 uuid=14879017_1.6.2.3.5 testdef=None
222 13:08:04.252612 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 13:08:04.253014 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 13:08:04.254395 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 13:08:04.254728 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 13:08:04.342793 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 13:08:04.343408 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 13:08:04.436426 runner path: /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/0/tests/1_kselftest-dt test_uuid 14879017_1.6.2.3.5
232 13:08:04.436584 BOARD='mt8192-asurada-spherion-r0'
233 13:08:04.436698 BRANCH='cip'
234 13:08:04.436807 SKIPFILE='/dev/null'
235 13:08:04.436914 SKIP_INSTALL='True'
236 13:08:04.437018 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz'
237 13:08:04.437128 TST_CASENAME=''
238 13:08:04.437275 TST_CMDFILES='dt'
239 13:08:04.437578 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 13:08:04.438006 Creating lava-test-runner.conf files
242 13:08:04.438116 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14879017/lava-overlay-81yzx1xa/lava-14879017/0 for stage 0
243 13:08:04.438262 - 0_timesync-off
244 13:08:04.438378 - 1_kselftest-dt
245 13:08:04.438533 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 13:08:04.438676 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 13:08:11.839007 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 13:08:11.839147 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 13:08:11.839233 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 13:08:11.839351 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 13:08:11.839430 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 13:08:11.998319 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 13:08:11.998460 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 13:08:11.998535 extracting modules file /var/lib/lava/dispatcher/tmp/14879017/tftp-deploy-1qe5qw7y/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14879017/extract-nfsrootfs-jt9hskzb
255 13:08:12.218427 extracting modules file /var/lib/lava/dispatcher/tmp/14879017/tftp-deploy-1qe5qw7y/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14879017/extract-overlay-ramdisk-rcms8e0v/ramdisk
256 13:08:12.447590 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 13:08:12.447730 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 13:08:12.447811 [common] Applying overlay to NFS
259 13:08:12.447870 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14879017/compress-overlay-37j9r66p/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14879017/extract-nfsrootfs-jt9hskzb
260 13:08:13.298528 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 13:08:13.298666 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 13:08:13.298757 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 13:08:13.298838 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 13:08:13.298910 Building ramdisk /var/lib/lava/dispatcher/tmp/14879017/extract-overlay-ramdisk-rcms8e0v/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14879017/extract-overlay-ramdisk-rcms8e0v/ramdisk
265 13:08:14.183360 >> 129966 blocks
266 13:08:16.444423 rename /var/lib/lava/dispatcher/tmp/14879017/extract-overlay-ramdisk-rcms8e0v/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14879017/tftp-deploy-1qe5qw7y/ramdisk/ramdisk.cpio.gz
267 13:08:16.444583 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 13:08:16.444668 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 13:08:16.444763 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 13:08:16.444850 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14879017/tftp-deploy-1qe5qw7y/kernel/Image']
271 13:08:31.574618 Returned 0 in 15 seconds
272 13:08:31.574840 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14879017/tftp-deploy-1qe5qw7y/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14879017/tftp-deploy-1qe5qw7y/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14879017/tftp-deploy-1qe5qw7y/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14879017/tftp-deploy-1qe5qw7y/kernel/image.itb
273 13:08:32.071398 output: FIT description: Kernel Image image with one or more FDT blobs
274 13:08:32.071529 output: Created: Thu Jul 18 14:08:31 2024
275 13:08:32.071592 output: Image 0 (kernel-1)
276 13:08:32.071647 output: Description:
277 13:08:32.071699 output: Created: Thu Jul 18 14:08:31 2024
278 13:08:32.071750 output: Type: Kernel Image
279 13:08:32.071800 output: Compression: lzma compressed
280 13:08:32.071853 output: Data Size: 13114469 Bytes = 12807.10 KiB = 12.51 MiB
281 13:08:32.071905 output: Architecture: AArch64
282 13:08:32.071953 output: OS: Linux
283 13:08:32.072001 output: Load Address: 0x00000000
284 13:08:32.072050 output: Entry Point: 0x00000000
285 13:08:32.072098 output: Hash algo: crc32
286 13:08:32.072148 output: Hash value: a47b020b
287 13:08:32.072195 output: Image 1 (fdt-1)
288 13:08:32.072243 output: Description: mt8192-asurada-spherion-r0
289 13:08:32.072291 output: Created: Thu Jul 18 14:08:31 2024
290 13:08:32.072339 output: Type: Flat Device Tree
291 13:08:32.072386 output: Compression: uncompressed
292 13:08:32.072434 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 13:08:32.072483 output: Architecture: AArch64
294 13:08:32.072531 output: Hash algo: crc32
295 13:08:32.072579 output: Hash value: 0f8e4d2e
296 13:08:32.072625 output: Image 2 (ramdisk-1)
297 13:08:32.072672 output: Description: unavailable
298 13:08:32.072719 output: Created: Thu Jul 18 14:08:31 2024
299 13:08:32.072767 output: Type: RAMDisk Image
300 13:08:32.072814 output: Compression: uncompressed
301 13:08:32.072862 output: Data Size: 18722811 Bytes = 18284.00 KiB = 17.86 MiB
302 13:08:32.072909 output: Architecture: AArch64
303 13:08:32.072955 output: OS: Linux
304 13:08:32.073002 output: Load Address: unavailable
305 13:08:32.073049 output: Entry Point: unavailable
306 13:08:32.073097 output: Hash algo: crc32
307 13:08:32.073173 output: Hash value: 94c04ab0
308 13:08:32.073237 output: Default Configuration: 'conf-1'
309 13:08:32.073284 output: Configuration 0 (conf-1)
310 13:08:32.073331 output: Description: mt8192-asurada-spherion-r0
311 13:08:32.073378 output: Kernel: kernel-1
312 13:08:32.073425 output: Init Ramdisk: ramdisk-1
313 13:08:32.073473 output: FDT: fdt-1
314 13:08:32.073521 output: Loadables: kernel-1
315 13:08:32.073568 output:
316 13:08:32.073664 end: 1.6.8.1 prepare-fit (duration 00:00:16) [common]
317 13:08:32.073738 end: 1.6.8 prepare-kernel (duration 00:00:16) [common]
318 13:08:32.073813 end: 1.6 prepare-tftp-overlay (duration 00:00:36) [common]
319 13:08:32.073888 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:16) [common]
320 13:08:32.073946 No LXC device requested
321 13:08:32.074012 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 13:08:32.074082 start: 1.8 deploy-device-env (timeout 00:09:16) [common]
323 13:08:32.074149 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 13:08:32.074203 Checking files for TFTP limit of 4294967296 bytes.
325 13:08:32.074561 end: 1 tftp-deploy (duration 00:00:44) [common]
326 13:08:32.074649 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 13:08:32.074727 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 13:08:32.074815 substitutions:
329 13:08:32.074873 - {DTB}: 14879017/tftp-deploy-1qe5qw7y/dtb/mt8192-asurada-spherion-r0.dtb
330 13:08:32.074928 - {INITRD}: 14879017/tftp-deploy-1qe5qw7y/ramdisk/ramdisk.cpio.gz
331 13:08:32.074980 - {KERNEL}: 14879017/tftp-deploy-1qe5qw7y/kernel/Image
332 13:08:32.075031 - {LAVA_MAC}: None
333 13:08:32.075081 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14879017/extract-nfsrootfs-jt9hskzb
334 13:08:32.075132 - {NFS_SERVER_IP}: 192.168.201.1
335 13:08:32.075181 - {PRESEED_CONFIG}: None
336 13:08:32.075238 - {PRESEED_LOCAL}: None
337 13:08:32.075287 - {RAMDISK}: 14879017/tftp-deploy-1qe5qw7y/ramdisk/ramdisk.cpio.gz
338 13:08:32.075336 - {ROOT_PART}: None
339 13:08:32.075384 - {ROOT}: None
340 13:08:32.075433 - {SERVER_IP}: 192.168.201.1
341 13:08:32.075481 - {TEE}: None
342 13:08:32.075529 Parsed boot commands:
343 13:08:32.075577 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 13:08:32.075713 Parsed boot commands: tftpboot 192.168.201.1 14879017/tftp-deploy-1qe5qw7y/kernel/image.itb 14879017/tftp-deploy-1qe5qw7y/kernel/cmdline
345 13:08:32.075792 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 13:08:32.075865 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 13:08:32.075939 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 13:08:32.076010 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 13:08:32.076066 Not connected, no need to disconnect.
350 13:08:32.076130 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 13:08:32.076217 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 13:08:32.076285 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 13:08:32.079106 Setting prompt string to ['lava-test: # ']
354 13:08:32.079408 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 13:08:32.079501 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 13:08:32.079592 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 13:08:32.079670 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 13:08:32.079879 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=reboot']
359 13:08:41.227454 >> Command sent successfully.
360 13:08:41.245216 Returned 0 in 9 seconds
361 13:08:41.245850 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 13:08:41.246961 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 13:08:41.247527 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 13:08:41.247908 Setting prompt string to 'Starting depthcharge on Spherion...'
366 13:08:41.248236 Changing prompt to 'Starting depthcharge on Spherion...'
367 13:08:41.248551 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 13:08:41.250103 [Enter `^Ec?' for help]
369 13:08:42.547074
370 13:08:42.547573
371 13:08:42.547874 F0: 102B 0000
372 13:08:42.548218
373 13:08:42.548558 F3: 1001 0000 [0200]
374 13:08:42.548988
375 13:08:42.550173 F3: 1001 0000
376 13:08:42.550581
377 13:08:42.550882 F7: 102D 0000
378 13:08:42.551166
379 13:08:42.551431 F1: 0000 0000
380 13:08:42.551693
381 13:08:42.553874 V0: 0000 0000 [0001]
382 13:08:42.554256
383 13:08:42.554553 00: 0007 8000
384 13:08:42.554838
385 13:08:42.557264 01: 0000 0000
386 13:08:42.557688
387 13:08:42.557990 BP: 0C00 0209 [0000]
388 13:08:42.558265
389 13:08:42.560846 G0: 1182 0000
390 13:08:42.561263
391 13:08:42.561569 EC: 0000 0021 [4000]
392 13:08:42.561899
393 13:08:42.565248 S7: 0000 0000 [0000]
394 13:08:42.565636
395 13:08:42.565936 CC: 0000 0000 [0001]
396 13:08:42.566214
397 13:08:42.568379 T0: 0000 0040 [010F]
398 13:08:42.568844
399 13:08:42.569182 Jump to BL
400 13:08:42.569476
401 13:08:42.593106
402 13:08:42.593197
403 13:08:42.600621 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 13:08:42.604120 ARM64: Exception handlers installed.
405 13:08:42.608246 ARM64: Testing exception
406 13:08:42.611698 ARM64: Done test exception
407 13:08:42.615232 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 13:08:42.627424 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 13:08:42.634978 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 13:08:42.645472 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 13:08:42.653048 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 13:08:42.660497 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 13:08:42.671705 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 13:08:42.678373 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 13:08:42.697439 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 13:08:42.700525 WDT: Last reset was cold boot
417 13:08:42.704622 SPI1(PAD0) initialized at 2873684 Hz
418 13:08:42.707846 SPI5(PAD0) initialized at 992727 Hz
419 13:08:42.708297 VBOOT: Loading verstage.
420 13:08:42.714686 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 13:08:42.717914 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 13:08:42.724798 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 13:08:42.727802 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 13:08:42.734200 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 13:08:42.740823 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 13:08:42.750751 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
427 13:08:42.751138
428 13:08:42.751434
429 13:08:42.760762 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 13:08:42.764150 ARM64: Exception handlers installed.
431 13:08:42.767596 ARM64: Testing exception
432 13:08:42.768028 ARM64: Done test exception
433 13:08:42.774145 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 13:08:42.777802 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 13:08:42.791880 Probing TPM: . done!
436 13:08:42.792300 TPM ready after 0 ms
437 13:08:42.799549 Connected to device vid:did:rid of 1ae0:0028:00
438 13:08:42.805916 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
439 13:08:42.853453 Initialized TPM device CR50 revision 0
440 13:08:42.865862 tlcl_send_startup: Startup return code is 0
441 13:08:42.866361 TPM: setup succeeded
442 13:08:42.876776 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 13:08:42.885856 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 13:08:42.895872 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 13:08:42.904569 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 13:08:42.908194 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 13:08:42.911586 in-header: 03 07 00 00 08 00 00 00
448 13:08:42.914734 in-data: aa e4 47 04 13 02 00 00
449 13:08:42.918454 Chrome EC: UHEPI supported
450 13:08:42.924539 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 13:08:42.928004 in-header: 03 a9 00 00 08 00 00 00
452 13:08:42.931825 in-data: 84 60 60 08 00 00 00 00
453 13:08:42.932285 Phase 1
454 13:08:42.937893 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 13:08:42.941246 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 13:08:42.947920 VB2:vb2_check_recovery() Recovery was requested manually
457 13:08:42.954680 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
458 13:08:42.955247 Recovery requested (1009000e)
459 13:08:42.963132 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 13:08:42.968685 tlcl_extend: response is 0
461 13:08:42.976842 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 13:08:42.981994 tlcl_extend: response is 0
463 13:08:42.988779 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 13:08:43.009067 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 13:08:43.015396 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 13:08:43.015504
467 13:08:43.015600
468 13:08:43.026013 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 13:08:43.029038 ARM64: Exception handlers installed.
470 13:08:43.032372 ARM64: Testing exception
471 13:08:43.032519 ARM64: Done test exception
472 13:08:43.054799 pmic_efuse_setting: Set efuses in 11 msecs
473 13:08:43.058627 pmwrap_interface_init: Select PMIF_VLD_RDY
474 13:08:43.064436 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 13:08:43.067952 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 13:08:43.074499 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 13:08:43.077984 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 13:08:43.084667 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 13:08:43.088076 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 13:08:43.094718 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 13:08:43.097671 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 13:08:43.101257 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 13:08:43.107944 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 13:08:43.111410 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 13:08:43.117652 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 13:08:43.121025 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 13:08:43.127715 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 13:08:43.134275 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 13:08:43.137970 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 13:08:43.144487 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 13:08:43.150987 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 13:08:43.154581 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 13:08:43.161078 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 13:08:43.167741 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 13:08:43.170980 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 13:08:43.177565 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 13:08:43.184031 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 13:08:43.187597 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 13:08:43.194058 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 13:08:43.201002 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 13:08:43.204115 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 13:08:43.207649 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 13:08:43.214109 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 13:08:43.217795 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 13:08:43.224066 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 13:08:43.227603 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 13:08:43.234295 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 13:08:43.237476 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 13:08:43.244638 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 13:08:43.248223 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 13:08:43.255076 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 13:08:43.258055 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 13:08:43.261678 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 13:08:43.268341 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 13:08:43.271605 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 13:08:43.274909 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 13:08:43.282047 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 13:08:43.285477 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 13:08:43.288385 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 13:08:43.291589 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 13:08:43.298386 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 13:08:43.301681 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 13:08:43.304989 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 13:08:43.308246 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 13:08:43.318709 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
526 13:08:43.325133 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 13:08:43.331608 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 13:08:43.337818 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 13:08:43.348000 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 13:08:43.351260 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 13:08:43.357918 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 13:08:43.361461 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 13:08:43.367995 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
534 13:08:43.374526 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 13:08:43.378342 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
536 13:08:43.381518 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 13:08:43.393027 [RTC]rtc_get_frequency_meter,154: input=15, output=854
538 13:08:43.401793 [RTC]rtc_get_frequency_meter,154: input=7, output=726
539 13:08:43.411019 [RTC]rtc_get_frequency_meter,154: input=11, output=790
540 13:08:43.420359 [RTC]rtc_get_frequency_meter,154: input=13, output=822
541 13:08:43.429903 [RTC]rtc_get_frequency_meter,154: input=12, output=806
542 13:08:43.439804 [RTC]rtc_get_frequency_meter,154: input=11, output=789
543 13:08:43.449063 [RTC]rtc_get_frequency_meter,154: input=12, output=806
544 13:08:43.452269 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
545 13:08:43.459732 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
546 13:08:43.463165 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 13:08:43.465992 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 13:08:43.472897 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 13:08:43.476655 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 13:08:43.479517 ADC[4]: Raw value=903325 ID=7
551 13:08:43.479923 ADC[3]: Raw value=213916 ID=1
552 13:08:43.483047 RAM Code: 0x71
553 13:08:43.486246 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 13:08:43.493107 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 13:08:43.499580 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 13:08:43.506357 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 13:08:43.509469 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 13:08:43.513104 in-header: 03 07 00 00 08 00 00 00
559 13:08:43.516382 in-data: aa e4 47 04 13 02 00 00
560 13:08:43.519445 Chrome EC: UHEPI supported
561 13:08:43.525899 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 13:08:43.529128 in-header: 03 a9 00 00 08 00 00 00
563 13:08:43.532813 in-data: 84 60 60 08 00 00 00 00
564 13:08:43.536009 MRC: failed to locate region type 0.
565 13:08:43.542759 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 13:08:43.546268 DRAM-K: Running full calibration
567 13:08:43.552713 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 13:08:43.553258 header.status = 0x0
569 13:08:43.555823 header.version = 0x6 (expected: 0x6)
570 13:08:43.559259 header.size = 0xd00 (expected: 0xd00)
571 13:08:43.562686 header.flags = 0x0
572 13:08:43.568853 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 13:08:43.586143 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
574 13:08:43.592672 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 13:08:43.596020 dram_init: ddr_geometry: 2
576 13:08:43.599473 [EMI] MDL number = 2
577 13:08:43.599864 [EMI] Get MDL freq = 0
578 13:08:43.602509 dram_init: ddr_type: 0
579 13:08:43.602932 is_discrete_lpddr4: 1
580 13:08:43.605922 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 13:08:43.606317
582 13:08:43.606722
583 13:08:43.609386 [Bian_co] ETT version 0.0.0.1
584 13:08:43.616125 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 13:08:43.616508
586 13:08:43.619001 dramc_set_vcore_voltage set vcore to 650000
587 13:08:43.619389 Read voltage for 800, 4
588 13:08:43.622527 Vio18 = 0
589 13:08:43.622916 Vcore = 650000
590 13:08:43.623232 Vdram = 0
591 13:08:43.625917 Vddq = 0
592 13:08:43.626324 Vmddr = 0
593 13:08:43.629437 dram_init: config_dvfs: 1
594 13:08:43.632441 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 13:08:43.639241 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 13:08:43.642367 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 13:08:43.645714 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 13:08:43.649170 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 13:08:43.652735 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 13:08:43.655958 MEM_TYPE=3, freq_sel=18
601 13:08:43.658937 sv_algorithm_assistance_LP4_1600
602 13:08:43.662667 ============ PULL DRAM RESETB DOWN ============
603 13:08:43.665586 ========== PULL DRAM RESETB DOWN end =========
604 13:08:43.672487 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 13:08:43.675629 ===================================
606 13:08:43.679116 LPDDR4 DRAM CONFIGURATION
607 13:08:43.683008 ===================================
608 13:08:43.683478 EX_ROW_EN[0] = 0x0
609 13:08:43.685681 EX_ROW_EN[1] = 0x0
610 13:08:43.686080 LP4Y_EN = 0x0
611 13:08:43.689570 WORK_FSP = 0x0
612 13:08:43.690076 WL = 0x2
613 13:08:43.692386 RL = 0x2
614 13:08:43.692769 BL = 0x2
615 13:08:43.695905 RPST = 0x0
616 13:08:43.696316 RD_PRE = 0x0
617 13:08:43.698778 WR_PRE = 0x1
618 13:08:43.699197 WR_PST = 0x0
619 13:08:43.702248 DBI_WR = 0x0
620 13:08:43.702684 DBI_RD = 0x0
621 13:08:43.705730 OTF = 0x1
622 13:08:43.709052 ===================================
623 13:08:43.712294 ===================================
624 13:08:43.712810 ANA top config
625 13:08:43.715758 ===================================
626 13:08:43.718694 DLL_ASYNC_EN = 0
627 13:08:43.722519 ALL_SLAVE_EN = 1
628 13:08:43.725575 NEW_RANK_MODE = 1
629 13:08:43.725996 DLL_IDLE_MODE = 1
630 13:08:43.729302 LP45_APHY_COMB_EN = 1
631 13:08:43.732064 TX_ODT_DIS = 1
632 13:08:43.735623 NEW_8X_MODE = 1
633 13:08:43.738643 ===================================
634 13:08:43.743001 ===================================
635 13:08:43.745582 data_rate = 1600
636 13:08:43.748787 CKR = 1
637 13:08:43.749209 DQ_P2S_RATIO = 8
638 13:08:43.752469 ===================================
639 13:08:43.755590 CA_P2S_RATIO = 8
640 13:08:43.758897 DQ_CA_OPEN = 0
641 13:08:43.761924 DQ_SEMI_OPEN = 0
642 13:08:43.765103 CA_SEMI_OPEN = 0
643 13:08:43.765530 CA_FULL_RATE = 0
644 13:08:43.768927 DQ_CKDIV4_EN = 1
645 13:08:43.772336 CA_CKDIV4_EN = 1
646 13:08:43.775363 CA_PREDIV_EN = 0
647 13:08:43.778590 PH8_DLY = 0
648 13:08:43.781903 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 13:08:43.782321 DQ_AAMCK_DIV = 4
650 13:08:43.785457 CA_AAMCK_DIV = 4
651 13:08:43.788903 CA_ADMCK_DIV = 4
652 13:08:43.791838 DQ_TRACK_CA_EN = 0
653 13:08:43.795456 CA_PICK = 800
654 13:08:43.799066 CA_MCKIO = 800
655 13:08:43.801927 MCKIO_SEMI = 0
656 13:08:43.802318 PLL_FREQ = 3068
657 13:08:43.805511 DQ_UI_PI_RATIO = 32
658 13:08:43.808967 CA_UI_PI_RATIO = 0
659 13:08:43.812294 ===================================
660 13:08:43.815588 ===================================
661 13:08:43.818999 memory_type:LPDDR4
662 13:08:43.819390 GP_NUM : 10
663 13:08:43.822154 SRAM_EN : 1
664 13:08:43.825400 MD32_EN : 0
665 13:08:43.828912 ===================================
666 13:08:43.829403 [ANA_INIT] >>>>>>>>>>>>>>
667 13:08:43.832354 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 13:08:43.835363 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 13:08:43.838759 ===================================
670 13:08:43.841848 data_rate = 1600,PCW = 0X7600
671 13:08:43.845467 ===================================
672 13:08:43.848750 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 13:08:43.855568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 13:08:43.858708 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 13:08:43.865343 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 13:08:43.868677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 13:08:43.872067 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 13:08:43.872484 [ANA_INIT] flow start
679 13:08:43.874848 [ANA_INIT] PLL >>>>>>>>
680 13:08:43.878415 [ANA_INIT] PLL <<<<<<<<
681 13:08:43.881858 [ANA_INIT] MIDPI >>>>>>>>
682 13:08:43.882274 [ANA_INIT] MIDPI <<<<<<<<
683 13:08:43.885089 [ANA_INIT] DLL >>>>>>>>
684 13:08:43.888646 [ANA_INIT] flow end
685 13:08:43.891518 ============ LP4 DIFF to SE enter ============
686 13:08:43.895117 ============ LP4 DIFF to SE exit ============
687 13:08:43.898105 [ANA_INIT] <<<<<<<<<<<<<
688 13:08:43.901839 [Flow] Enable top DCM control >>>>>
689 13:08:43.905250 [Flow] Enable top DCM control <<<<<
690 13:08:43.908160 Enable DLL master slave shuffle
691 13:08:43.911743 ==============================================================
692 13:08:43.915170 Gating Mode config
693 13:08:43.918237 ==============================================================
694 13:08:43.921640 Config description:
695 13:08:43.931487 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 13:08:43.938243 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 13:08:43.941433 SELPH_MODE 0: By rank 1: By Phase
698 13:08:43.948222 ==============================================================
699 13:08:43.951601 GAT_TRACK_EN = 1
700 13:08:43.954725 RX_GATING_MODE = 2
701 13:08:43.958142 RX_GATING_TRACK_MODE = 2
702 13:08:43.961656 SELPH_MODE = 1
703 13:08:43.964695 PICG_EARLY_EN = 1
704 13:08:43.965299 VALID_LAT_VALUE = 1
705 13:08:43.971433 ==============================================================
706 13:08:43.974696 Enter into Gating configuration >>>>
707 13:08:43.977863 Exit from Gating configuration <<<<
708 13:08:43.981307 Enter into DVFS_PRE_config >>>>>
709 13:08:43.991584 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 13:08:43.994949 Exit from DVFS_PRE_config <<<<<
711 13:08:43.998458 Enter into PICG configuration >>>>
712 13:08:44.001276 Exit from PICG configuration <<<<
713 13:08:44.004703 [RX_INPUT] configuration >>>>>
714 13:08:44.007840 [RX_INPUT] configuration <<<<<
715 13:08:44.011331 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 13:08:44.018433 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 13:08:44.024486 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 13:08:44.031772 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 13:08:44.037945 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 13:08:44.041987 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 13:08:44.045718 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 13:08:44.052361 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 13:08:44.056430 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 13:08:44.059585 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 13:08:44.063784 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 13:08:44.067288 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 13:08:44.070733 ===================================
728 13:08:44.075167 LPDDR4 DRAM CONFIGURATION
729 13:08:44.078159 ===================================
730 13:08:44.078551 EX_ROW_EN[0] = 0x0
731 13:08:44.081471 EX_ROW_EN[1] = 0x0
732 13:08:44.081857 LP4Y_EN = 0x0
733 13:08:44.085031 WORK_FSP = 0x0
734 13:08:44.085567 WL = 0x2
735 13:08:44.088216 RL = 0x2
736 13:08:44.088744 BL = 0x2
737 13:08:44.091736 RPST = 0x0
738 13:08:44.092211 RD_PRE = 0x0
739 13:08:44.095124 WR_PRE = 0x1
740 13:08:44.095650 WR_PST = 0x0
741 13:08:44.098735 DBI_WR = 0x0
742 13:08:44.099242 DBI_RD = 0x0
743 13:08:44.101393 OTF = 0x1
744 13:08:44.105236 ===================================
745 13:08:44.108323 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 13:08:44.111805 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 13:08:44.118334 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 13:08:44.121924 ===================================
749 13:08:44.122324 LPDDR4 DRAM CONFIGURATION
750 13:08:44.125221 ===================================
751 13:08:44.128227 EX_ROW_EN[0] = 0x10
752 13:08:44.131638 EX_ROW_EN[1] = 0x0
753 13:08:44.132221 LP4Y_EN = 0x0
754 13:08:44.135190 WORK_FSP = 0x0
755 13:08:44.135718 WL = 0x2
756 13:08:44.138027 RL = 0x2
757 13:08:44.138606 BL = 0x2
758 13:08:44.141315 RPST = 0x0
759 13:08:44.141892 RD_PRE = 0x0
760 13:08:44.144756 WR_PRE = 0x1
761 13:08:44.145359 WR_PST = 0x0
762 13:08:44.148761 DBI_WR = 0x0
763 13:08:44.149356 DBI_RD = 0x0
764 13:08:44.151631 OTF = 0x1
765 13:08:44.155091 ===================================
766 13:08:44.161452 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 13:08:44.164496 nWR fixed to 40
768 13:08:44.164984 [ModeRegInit_LP4] CH0 RK0
769 13:08:44.167879 [ModeRegInit_LP4] CH0 RK1
770 13:08:44.171595 [ModeRegInit_LP4] CH1 RK0
771 13:08:44.174145 [ModeRegInit_LP4] CH1 RK1
772 13:08:44.174609 match AC timing 13
773 13:08:44.181261 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 13:08:44.184777 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 13:08:44.187889 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 13:08:44.194101 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 13:08:44.197711 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 13:08:44.197799 [EMI DOE] emi_dcm 0
779 13:08:44.203985 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 13:08:44.204112 ==
781 13:08:44.207616 Dram Type= 6, Freq= 0, CH_0, rank 0
782 13:08:44.210445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 13:08:44.210556 ==
784 13:08:44.217304 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 13:08:44.220464 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 13:08:44.232126 [CA 0] Center 38 (7~69) winsize 63
787 13:08:44.235387 [CA 1] Center 37 (6~68) winsize 63
788 13:08:44.238418 [CA 2] Center 34 (4~65) winsize 62
789 13:08:44.241936 [CA 3] Center 35 (4~66) winsize 63
790 13:08:44.245482 [CA 4] Center 34 (3~65) winsize 63
791 13:08:44.248836 [CA 5] Center 33 (3~64) winsize 62
792 13:08:44.249429
793 13:08:44.252555 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 13:08:44.253020
795 13:08:44.255919 [CATrainingPosCal] consider 1 rank data
796 13:08:44.258803 u2DelayCellTimex100 = 270/100 ps
797 13:08:44.262306 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
798 13:08:44.265284 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 13:08:44.268854 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 13:08:44.275727 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 13:08:44.278576 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
802 13:08:44.282106 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 13:08:44.282342
804 13:08:44.285619 CA PerBit enable=1, Macro0, CA PI delay=33
805 13:08:44.285829
806 13:08:44.288579 [CBTSetCACLKResult] CA Dly = 33
807 13:08:44.288797 CS Dly: 6 (0~37)
808 13:08:44.288962 ==
809 13:08:44.291989 Dram Type= 6, Freq= 0, CH_0, rank 1
810 13:08:44.298656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 13:08:44.298932 ==
812 13:08:44.302130 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 13:08:44.308414 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 13:08:44.317915 [CA 0] Center 38 (7~69) winsize 63
815 13:08:44.321560 [CA 1] Center 37 (7~68) winsize 62
816 13:08:44.324953 [CA 2] Center 35 (4~66) winsize 63
817 13:08:44.327897 [CA 3] Center 34 (4~65) winsize 62
818 13:08:44.331565 [CA 4] Center 34 (3~65) winsize 63
819 13:08:44.334517 [CA 5] Center 33 (3~64) winsize 62
820 13:08:44.334844
821 13:08:44.337775 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 13:08:44.338130
823 13:08:44.341304 [CATrainingPosCal] consider 2 rank data
824 13:08:44.344849 u2DelayCellTimex100 = 270/100 ps
825 13:08:44.347738 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
826 13:08:44.351028 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 13:08:44.358041 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 13:08:44.361872 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 13:08:44.364516 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
830 13:08:44.367958 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 13:08:44.368392
832 13:08:44.371171 CA PerBit enable=1, Macro0, CA PI delay=33
833 13:08:44.371498
834 13:08:44.374721 [CBTSetCACLKResult] CA Dly = 33
835 13:08:44.375074 CS Dly: 6 (0~38)
836 13:08:44.375388
837 13:08:44.378347 ----->DramcWriteLeveling(PI) begin...
838 13:08:44.381544 ==
839 13:08:44.381893 Dram Type= 6, Freq= 0, CH_0, rank 0
840 13:08:44.388057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 13:08:44.388509 ==
842 13:08:44.391452 Write leveling (Byte 0): 34 => 34
843 13:08:44.394710 Write leveling (Byte 1): 29 => 29
844 13:08:44.398009 DramcWriteLeveling(PI) end<-----
845 13:08:44.398506
846 13:08:44.398900 ==
847 13:08:44.401671 Dram Type= 6, Freq= 0, CH_0, rank 0
848 13:08:44.404917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 13:08:44.405431 ==
850 13:08:44.408169 [Gating] SW mode calibration
851 13:08:44.414584 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 13:08:44.417956 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 13:08:44.424514 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 13:08:44.427828 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 13:08:44.431181 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 13:08:44.437642 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 13:08:44.441329 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 13:08:44.444263 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 13:08:44.450855 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 13:08:44.454256 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 13:08:44.457759 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 13:08:44.464313 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 13:08:44.467740 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 13:08:44.471313 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 13:08:44.478006 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 13:08:44.481336 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 13:08:44.484980 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 13:08:44.491212 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 13:08:44.494462 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 13:08:44.497576 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
871 13:08:44.504385 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
872 13:08:44.507378 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 13:08:44.510868 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 13:08:44.517606 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 13:08:44.520988 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 13:08:44.524179 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 13:08:44.531182 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 13:08:44.534427 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 13:08:44.537536 0 9 8 | B1->B0 | 2323 3232 | 1 1 | (1 1) (1 1)
880 13:08:44.541072 0 9 12 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
881 13:08:44.547314 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 13:08:44.550707 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 13:08:44.554156 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 13:08:44.560998 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 13:08:44.564160 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 13:08:44.567662 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
887 13:08:44.574114 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
888 13:08:44.577719 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
889 13:08:44.580435 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 13:08:44.587504 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 13:08:44.590565 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 13:08:44.594132 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 13:08:44.600788 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 13:08:44.604221 0 11 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
895 13:08:44.607203 0 11 8 | B1->B0 | 2d2d 4646 | 1 0 | (1 1) (0 0)
896 13:08:44.614134 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
897 13:08:44.617184 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 13:08:44.620838 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 13:08:44.624222 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 13:08:44.631809 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 13:08:44.634916 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 13:08:44.637775 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 13:08:44.644603 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 13:08:44.648478 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 13:08:44.651995 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 13:08:44.658371 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 13:08:44.661561 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 13:08:44.664466 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 13:08:44.671468 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 13:08:44.674733 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 13:08:44.677901 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 13:08:44.685005 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 13:08:44.687943 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 13:08:44.691440 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 13:08:44.694848 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 13:08:44.701314 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 13:08:44.704782 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 13:08:44.708301 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
919 13:08:44.710730 Total UI for P1: 0, mck2ui 16
920 13:08:44.714514 best dqsien dly found for B0: ( 0, 14, 2)
921 13:08:44.720935 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
922 13:08:44.724564 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 13:08:44.727694 Total UI for P1: 0, mck2ui 16
924 13:08:44.731010 best dqsien dly found for B1: ( 0, 14, 10)
925 13:08:44.734382 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
926 13:08:44.737828 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 13:08:44.737906
928 13:08:44.741054 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
929 13:08:44.744408 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 13:08:44.747727 [Gating] SW calibration Done
931 13:08:44.747804 ==
932 13:08:44.751057 Dram Type= 6, Freq= 0, CH_0, rank 0
933 13:08:44.754431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 13:08:44.757616 ==
935 13:08:44.757728 RX Vref Scan: 0
936 13:08:44.757784
937 13:08:44.761033 RX Vref 0 -> 0, step: 1
938 13:08:44.761143
939 13:08:44.764210 RX Delay -130 -> 252, step: 16
940 13:08:44.767745 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 13:08:44.770852 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 13:08:44.774499 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 13:08:44.777438 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 13:08:44.784002 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 13:08:44.787847 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 13:08:44.790657 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 13:08:44.794076 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
948 13:08:44.797420 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 13:08:44.803788 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
950 13:08:44.807586 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 13:08:44.810546 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 13:08:44.814106 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 13:08:44.820715 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 13:08:44.823623 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 13:08:44.827092 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 13:08:44.827192 ==
957 13:08:44.830489 Dram Type= 6, Freq= 0, CH_0, rank 0
958 13:08:44.834024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 13:08:44.834096 ==
960 13:08:44.837359 DQS Delay:
961 13:08:44.837441 DQS0 = 0, DQS1 = 0
962 13:08:44.840615 DQM Delay:
963 13:08:44.840711 DQM0 = 88, DQM1 = 75
964 13:08:44.840795 DQ Delay:
965 13:08:44.843605 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 13:08:44.847024 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
967 13:08:44.850258 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
968 13:08:44.853502 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
969 13:08:44.853598
970 13:08:44.853684
971 13:08:44.856999 ==
972 13:08:44.857094 Dram Type= 6, Freq= 0, CH_0, rank 0
973 13:08:44.863835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 13:08:44.863927 ==
975 13:08:44.863986
976 13:08:44.864040
977 13:08:44.867199 TX Vref Scan disable
978 13:08:44.867286 == TX Byte 0 ==
979 13:08:44.870539 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
980 13:08:44.876505 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
981 13:08:44.876609 == TX Byte 1 ==
982 13:08:44.879967 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
983 13:08:44.886923 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
984 13:08:44.887001 ==
985 13:08:44.890126 Dram Type= 6, Freq= 0, CH_0, rank 0
986 13:08:44.893361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 13:08:44.893439 ==
988 13:08:44.906999 TX Vref=22, minBit 1, minWin=27, winSum=446
989 13:08:44.910447 TX Vref=24, minBit 1, minWin=27, winSum=448
990 13:08:44.914121 TX Vref=26, minBit 1, minWin=27, winSum=448
991 13:08:44.916937 TX Vref=28, minBit 5, minWin=27, winSum=454
992 13:08:44.920594 TX Vref=30, minBit 5, minWin=27, winSum=457
993 13:08:44.927086 TX Vref=32, minBit 4, minWin=27, winSum=450
994 13:08:44.930631 [TxChooseVref] Worse bit 5, Min win 27, Win sum 457, Final Vref 30
995 13:08:44.930710
996 13:08:44.934148 Final TX Range 1 Vref 30
997 13:08:44.934248
998 13:08:44.934324 ==
999 13:08:44.936905 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 13:08:44.940830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 13:08:44.940975 ==
1002 13:08:44.943735
1003 13:08:44.943841
1004 13:08:44.943928 TX Vref Scan disable
1005 13:08:44.947271 == TX Byte 0 ==
1006 13:08:44.950635 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1007 13:08:44.956886 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1008 13:08:44.957007 == TX Byte 1 ==
1009 13:08:44.960637 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1010 13:08:44.966981 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1011 13:08:44.967077
1012 13:08:44.967166 [DATLAT]
1013 13:08:44.967254 Freq=800, CH0 RK0
1014 13:08:44.967340
1015 13:08:44.970299 DATLAT Default: 0xa
1016 13:08:44.970392 0, 0xFFFF, sum = 0
1017 13:08:44.973861 1, 0xFFFF, sum = 0
1018 13:08:44.973962 2, 0xFFFF, sum = 0
1019 13:08:44.977359 3, 0xFFFF, sum = 0
1020 13:08:44.980447 4, 0xFFFF, sum = 0
1021 13:08:44.980539 5, 0xFFFF, sum = 0
1022 13:08:44.983566 6, 0xFFFF, sum = 0
1023 13:08:44.983673 7, 0xFFFF, sum = 0
1024 13:08:44.986929 8, 0xFFFF, sum = 0
1025 13:08:44.987023 9, 0x0, sum = 1
1026 13:08:44.987110 10, 0x0, sum = 2
1027 13:08:44.990421 11, 0x0, sum = 3
1028 13:08:44.990515 12, 0x0, sum = 4
1029 13:08:44.993923 best_step = 10
1030 13:08:44.994014
1031 13:08:44.994112 ==
1032 13:08:44.997323 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 13:08:45.000504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 13:08:45.000599 ==
1035 13:08:45.003570 RX Vref Scan: 1
1036 13:08:45.003666
1037 13:08:45.003751 Set Vref Range= 32 -> 127
1038 13:08:45.007354
1039 13:08:45.007451 RX Vref 32 -> 127, step: 1
1040 13:08:45.007542
1041 13:08:45.010361 RX Delay -111 -> 252, step: 8
1042 13:08:45.010465
1043 13:08:45.013722 Set Vref, RX VrefLevel [Byte0]: 32
1044 13:08:45.017346 [Byte1]: 32
1045 13:08:45.017422
1046 13:08:45.020412 Set Vref, RX VrefLevel [Byte0]: 33
1047 13:08:45.023432 [Byte1]: 33
1048 13:08:45.027544
1049 13:08:45.027638 Set Vref, RX VrefLevel [Byte0]: 34
1050 13:08:45.031237 [Byte1]: 34
1051 13:08:45.035319
1052 13:08:45.035419 Set Vref, RX VrefLevel [Byte0]: 35
1053 13:08:45.038385 [Byte1]: 35
1054 13:08:45.042928
1055 13:08:45.043022 Set Vref, RX VrefLevel [Byte0]: 36
1056 13:08:45.046414 [Byte1]: 36
1057 13:08:45.050451
1058 13:08:45.050544 Set Vref, RX VrefLevel [Byte0]: 37
1059 13:08:45.053903 [Byte1]: 37
1060 13:08:45.058068
1061 13:08:45.058159 Set Vref, RX VrefLevel [Byte0]: 38
1062 13:08:45.061355 [Byte1]: 38
1063 13:08:45.066041
1064 13:08:45.066133 Set Vref, RX VrefLevel [Byte0]: 39
1065 13:08:45.069067 [Byte1]: 39
1066 13:08:45.073431
1067 13:08:45.073510 Set Vref, RX VrefLevel [Byte0]: 40
1068 13:08:45.076658 [Byte1]: 40
1069 13:08:45.081361
1070 13:08:45.081444 Set Vref, RX VrefLevel [Byte0]: 41
1071 13:08:45.084751 [Byte1]: 41
1072 13:08:45.088936
1073 13:08:45.089028 Set Vref, RX VrefLevel [Byte0]: 42
1074 13:08:45.092451 [Byte1]: 42
1075 13:08:45.096328
1076 13:08:45.096429 Set Vref, RX VrefLevel [Byte0]: 43
1077 13:08:45.100139 [Byte1]: 43
1078 13:08:45.103912
1079 13:08:45.104013 Set Vref, RX VrefLevel [Byte0]: 44
1080 13:08:45.107673 [Byte1]: 44
1081 13:08:45.111960
1082 13:08:45.112054 Set Vref, RX VrefLevel [Byte0]: 45
1083 13:08:45.115238 [Byte1]: 45
1084 13:08:45.119746
1085 13:08:45.119840 Set Vref, RX VrefLevel [Byte0]: 46
1086 13:08:45.122703 [Byte1]: 46
1087 13:08:45.127025
1088 13:08:45.127120 Set Vref, RX VrefLevel [Byte0]: 47
1089 13:08:45.130475 [Byte1]: 47
1090 13:08:45.134453
1091 13:08:45.134554 Set Vref, RX VrefLevel [Byte0]: 48
1092 13:08:45.138076 [Byte1]: 48
1093 13:08:45.142340
1094 13:08:45.142436 Set Vref, RX VrefLevel [Byte0]: 49
1095 13:08:45.145550 [Byte1]: 49
1096 13:08:45.149910
1097 13:08:45.150014 Set Vref, RX VrefLevel [Byte0]: 50
1098 13:08:45.153357 [Byte1]: 50
1099 13:08:45.157765
1100 13:08:45.157857 Set Vref, RX VrefLevel [Byte0]: 51
1101 13:08:45.161065 [Byte1]: 51
1102 13:08:45.165368
1103 13:08:45.165471 Set Vref, RX VrefLevel [Byte0]: 52
1104 13:08:45.168284 [Byte1]: 52
1105 13:08:45.172677
1106 13:08:45.172770 Set Vref, RX VrefLevel [Byte0]: 53
1107 13:08:45.176244 [Byte1]: 53
1108 13:08:45.180523
1109 13:08:45.180591 Set Vref, RX VrefLevel [Byte0]: 54
1110 13:08:45.183818 [Byte1]: 54
1111 13:08:45.187964
1112 13:08:45.188056 Set Vref, RX VrefLevel [Byte0]: 55
1113 13:08:45.192036 [Byte1]: 55
1114 13:08:45.195844
1115 13:08:45.195936 Set Vref, RX VrefLevel [Byte0]: 56
1116 13:08:45.198964 [Byte1]: 56
1117 13:08:45.203521
1118 13:08:45.203645 Set Vref, RX VrefLevel [Byte0]: 57
1119 13:08:45.207063 [Byte1]: 57
1120 13:08:45.210870
1121 13:08:45.210969 Set Vref, RX VrefLevel [Byte0]: 58
1122 13:08:45.214172 [Byte1]: 58
1123 13:08:45.218999
1124 13:08:45.219104 Set Vref, RX VrefLevel [Byte0]: 59
1125 13:08:45.222185 [Byte1]: 59
1126 13:08:45.226274
1127 13:08:45.226369 Set Vref, RX VrefLevel [Byte0]: 60
1128 13:08:45.229783 [Byte1]: 60
1129 13:08:45.234084
1130 13:08:45.234180 Set Vref, RX VrefLevel [Byte0]: 61
1131 13:08:45.237467 [Byte1]: 61
1132 13:08:45.241612
1133 13:08:45.241682 Set Vref, RX VrefLevel [Byte0]: 62
1134 13:08:45.245205 [Byte1]: 62
1135 13:08:45.249426
1136 13:08:45.249499 Set Vref, RX VrefLevel [Byte0]: 63
1137 13:08:45.252829 [Byte1]: 63
1138 13:08:45.256860
1139 13:08:45.256958 Set Vref, RX VrefLevel [Byte0]: 64
1140 13:08:45.260481 [Byte1]: 64
1141 13:08:45.264951
1142 13:08:45.265044 Set Vref, RX VrefLevel [Byte0]: 65
1143 13:08:45.268011 [Byte1]: 65
1144 13:08:45.272256
1145 13:08:45.272349 Set Vref, RX VrefLevel [Byte0]: 66
1146 13:08:45.275715 [Byte1]: 66
1147 13:08:45.280237
1148 13:08:45.280331 Set Vref, RX VrefLevel [Byte0]: 67
1149 13:08:45.283534 [Byte1]: 67
1150 13:08:45.287389
1151 13:08:45.287482 Set Vref, RX VrefLevel [Byte0]: 68
1152 13:08:45.293886 [Byte1]: 68
1153 13:08:45.293991
1154 13:08:45.297224 Set Vref, RX VrefLevel [Byte0]: 69
1155 13:08:45.300817 [Byte1]: 69
1156 13:08:45.300911
1157 13:08:45.303924 Set Vref, RX VrefLevel [Byte0]: 70
1158 13:08:45.307566 [Byte1]: 70
1159 13:08:45.310449
1160 13:08:45.310541 Set Vref, RX VrefLevel [Byte0]: 71
1161 13:08:45.313926 [Byte1]: 71
1162 13:08:45.317856
1163 13:08:45.317949 Set Vref, RX VrefLevel [Byte0]: 72
1164 13:08:45.321765 [Byte1]: 72
1165 13:08:45.326132
1166 13:08:45.326226 Set Vref, RX VrefLevel [Byte0]: 73
1167 13:08:45.329347 [Byte1]: 73
1168 13:08:45.333585
1169 13:08:45.333655 Set Vref, RX VrefLevel [Byte0]: 74
1170 13:08:45.336575 [Byte1]: 74
1171 13:08:45.340861
1172 13:08:45.340959 Final RX Vref Byte 0 = 54 to rank0
1173 13:08:45.344504 Final RX Vref Byte 1 = 62 to rank0
1174 13:08:45.347909 Final RX Vref Byte 0 = 54 to rank1
1175 13:08:45.351565 Final RX Vref Byte 1 = 62 to rank1==
1176 13:08:45.354313 Dram Type= 6, Freq= 0, CH_0, rank 0
1177 13:08:45.360972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1178 13:08:45.361072 ==
1179 13:08:45.361176 DQS Delay:
1180 13:08:45.361235 DQS0 = 0, DQS1 = 0
1181 13:08:45.364696 DQM Delay:
1182 13:08:45.364789 DQM0 = 88, DQM1 = 76
1183 13:08:45.367727 DQ Delay:
1184 13:08:45.371106 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =88
1185 13:08:45.371200 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1186 13:08:45.374217 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1187 13:08:45.378097 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1188 13:08:45.380988
1189 13:08:45.381084
1190 13:08:45.387894 [DQSOSCAuto] RK0, (LSB)MR18= 0x3933, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1191 13:08:45.391307 CH0 RK0: MR19=606, MR18=3933
1192 13:08:45.397899 CH0_RK0: MR19=0x606, MR18=0x3933, DQSOSC=395, MR23=63, INC=94, DEC=63
1193 13:08:45.398000
1194 13:08:45.401541 ----->DramcWriteLeveling(PI) begin...
1195 13:08:45.401638 ==
1196 13:08:45.404465 Dram Type= 6, Freq= 0, CH_0, rank 1
1197 13:08:45.407608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1198 13:08:45.407708 ==
1199 13:08:45.411381 Write leveling (Byte 0): 31 => 31
1200 13:08:45.414267 Write leveling (Byte 1): 26 => 26
1201 13:08:45.417586 DramcWriteLeveling(PI) end<-----
1202 13:08:45.417666
1203 13:08:45.417726 ==
1204 13:08:45.421392 Dram Type= 6, Freq= 0, CH_0, rank 1
1205 13:08:45.424639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1206 13:08:45.424718 ==
1207 13:08:45.427601 [Gating] SW mode calibration
1208 13:08:45.434570 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1209 13:08:45.441043 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1210 13:08:45.444390 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1211 13:08:45.447480 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1212 13:08:45.454749 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 13:08:45.457264 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 13:08:45.460789 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 13:08:45.504608 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 13:08:45.505333 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 13:08:45.505590 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 13:08:45.505840 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 13:08:45.505931 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 13:08:45.506612 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 13:08:45.506880 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 13:08:45.506967 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 13:08:45.507060 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 13:08:45.507177 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 13:08:45.549065 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 13:08:45.549654 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 13:08:45.550251 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1228 13:08:45.550783 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1229 13:08:45.550852 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 13:08:45.551123 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 13:08:45.551182 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 13:08:45.551262 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 13:08:45.551873 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 13:08:45.551950 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 13:08:45.565490 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
1236 13:08:45.565775 0 9 8 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
1237 13:08:45.568937 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
1238 13:08:45.572049 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 13:08:45.572117 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 13:08:45.575604 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 13:08:45.582322 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 13:08:45.585273 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 13:08:45.588455 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
1244 13:08:45.595213 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
1245 13:08:45.598218 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 13:08:45.601778 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 13:08:45.608190 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 13:08:45.611774 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 13:08:45.615302 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 13:08:45.621646 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 13:08:45.624945 0 11 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
1252 13:08:45.628312 0 11 8 | B1->B0 | 3131 4545 | 0 1 | (0 0) (0 0)
1253 13:08:45.634711 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 13:08:45.638143 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 13:08:45.641526 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 13:08:45.648535 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 13:08:45.651627 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 13:08:45.654840 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 13:08:45.658100 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1260 13:08:45.664698 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 13:08:45.668230 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 13:08:45.671259 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 13:08:45.678123 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 13:08:45.681592 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 13:08:45.684480 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 13:08:45.691435 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 13:08:45.694423 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 13:08:45.697715 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 13:08:45.704327 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 13:08:45.707778 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 13:08:45.711063 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 13:08:45.717607 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 13:08:45.720986 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 13:08:45.724536 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 13:08:45.731122 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1276 13:08:45.734533 Total UI for P1: 0, mck2ui 16
1277 13:08:45.737728 best dqsien dly found for B0: ( 0, 14, 2)
1278 13:08:45.740990 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1279 13:08:45.744000 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 13:08:45.747612 Total UI for P1: 0, mck2ui 16
1281 13:08:45.751150 best dqsien dly found for B1: ( 0, 14, 6)
1282 13:08:45.754489 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1283 13:08:45.757735 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1284 13:08:45.757846
1285 13:08:45.764367 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1286 13:08:45.767847 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1287 13:08:45.767922 [Gating] SW calibration Done
1288 13:08:45.770964 ==
1289 13:08:45.771039 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 13:08:45.777723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 13:08:45.777799 ==
1292 13:08:45.777859 RX Vref Scan: 0
1293 13:08:45.777912
1294 13:08:45.781190 RX Vref 0 -> 0, step: 1
1295 13:08:45.781270
1296 13:08:45.784719 RX Delay -130 -> 252, step: 16
1297 13:08:45.788011 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1298 13:08:45.791158 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1299 13:08:45.794475 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1300 13:08:45.800913 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1301 13:08:45.804384 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1302 13:08:45.807865 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1303 13:08:45.810652 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1304 13:08:45.814178 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1305 13:08:45.821009 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1306 13:08:45.823977 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1307 13:08:45.827509 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1308 13:08:45.830686 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1309 13:08:45.834128 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1310 13:08:45.840421 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1311 13:08:45.844307 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1312 13:08:45.847165 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1313 13:08:45.847251 ==
1314 13:08:45.850966 Dram Type= 6, Freq= 0, CH_0, rank 1
1315 13:08:45.853803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1316 13:08:45.857302 ==
1317 13:08:45.857366 DQS Delay:
1318 13:08:45.857421 DQS0 = 0, DQS1 = 0
1319 13:08:45.860692 DQM Delay:
1320 13:08:45.860755 DQM0 = 84, DQM1 = 75
1321 13:08:45.863997 DQ Delay:
1322 13:08:45.864058 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1323 13:08:45.867396 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1324 13:08:45.870718 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1325 13:08:45.873654 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1326 13:08:45.873717
1327 13:08:45.877411
1328 13:08:45.877475 ==
1329 13:08:45.880661 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 13:08:45.883509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 13:08:45.883569 ==
1332 13:08:45.883621
1333 13:08:45.883674
1334 13:08:45.887285 TX Vref Scan disable
1335 13:08:45.887343 == TX Byte 0 ==
1336 13:08:45.893580 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1337 13:08:45.897113 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1338 13:08:45.897228 == TX Byte 1 ==
1339 13:08:45.903520 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1340 13:08:45.906950 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1341 13:08:45.907013 ==
1342 13:08:45.910651 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 13:08:45.913895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 13:08:45.913960 ==
1345 13:08:45.927951 TX Vref=22, minBit 1, minWin=27, winSum=440
1346 13:08:45.931279 TX Vref=24, minBit 1, minWin=27, winSum=443
1347 13:08:45.934403 TX Vref=26, minBit 1, minWin=27, winSum=448
1348 13:08:45.937968 TX Vref=28, minBit 3, minWin=27, winSum=449
1349 13:08:45.941198 TX Vref=30, minBit 0, minWin=28, winSum=454
1350 13:08:45.944620 TX Vref=32, minBit 1, minWin=27, winSum=446
1351 13:08:45.951543 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
1352 13:08:45.951620
1353 13:08:45.954364 Final TX Range 1 Vref 30
1354 13:08:45.954431
1355 13:08:45.954485 ==
1356 13:08:45.957714 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 13:08:45.961452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 13:08:45.961553 ==
1359 13:08:45.961633
1360 13:08:45.964598
1361 13:08:45.964665 TX Vref Scan disable
1362 13:08:45.967902 == TX Byte 0 ==
1363 13:08:45.971290 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1364 13:08:45.977964 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1365 13:08:45.978038 == TX Byte 1 ==
1366 13:08:45.981462 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1367 13:08:45.987702 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1368 13:08:45.987768
1369 13:08:45.987824 [DATLAT]
1370 13:08:45.987878 Freq=800, CH0 RK1
1371 13:08:45.987929
1372 13:08:45.991244 DATLAT Default: 0xa
1373 13:08:45.991303 0, 0xFFFF, sum = 0
1374 13:08:45.994162 1, 0xFFFF, sum = 0
1375 13:08:45.994225 2, 0xFFFF, sum = 0
1376 13:08:45.997715 3, 0xFFFF, sum = 0
1377 13:08:46.001376 4, 0xFFFF, sum = 0
1378 13:08:46.001438 5, 0xFFFF, sum = 0
1379 13:08:46.004368 6, 0xFFFF, sum = 0
1380 13:08:46.004427 7, 0xFFFF, sum = 0
1381 13:08:46.007992 8, 0xFFFF, sum = 0
1382 13:08:46.008052 9, 0x0, sum = 1
1383 13:08:46.008103 10, 0x0, sum = 2
1384 13:08:46.010868 11, 0x0, sum = 3
1385 13:08:46.010927 12, 0x0, sum = 4
1386 13:08:46.014301 best_step = 10
1387 13:08:46.014359
1388 13:08:46.014410 ==
1389 13:08:46.017361 Dram Type= 6, Freq= 0, CH_0, rank 1
1390 13:08:46.021008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1391 13:08:46.021071 ==
1392 13:08:46.024274 RX Vref Scan: 0
1393 13:08:46.024334
1394 13:08:46.024385 RX Vref 0 -> 0, step: 1
1395 13:08:46.027477
1396 13:08:46.027534 RX Delay -95 -> 252, step: 8
1397 13:08:46.034495 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1398 13:08:46.037973 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1399 13:08:46.041055 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1400 13:08:46.044155 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1401 13:08:46.050719 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1402 13:08:46.054035 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1403 13:08:46.057541 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1404 13:08:46.060589 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1405 13:08:46.064088 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1406 13:08:46.067669 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1407 13:08:46.074051 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1408 13:08:46.077472 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1409 13:08:46.080954 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1410 13:08:46.084077 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1411 13:08:46.090421 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1412 13:08:46.094266 iDelay=209, Bit 15, Center 80 (-31 ~ 192) 224
1413 13:08:46.094341 ==
1414 13:08:46.097549 Dram Type= 6, Freq= 0, CH_0, rank 1
1415 13:08:46.100394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1416 13:08:46.100473 ==
1417 13:08:46.104035 DQS Delay:
1418 13:08:46.104109 DQS0 = 0, DQS1 = 0
1419 13:08:46.104167 DQM Delay:
1420 13:08:46.106999 DQM0 = 86, DQM1 = 75
1421 13:08:46.107073 DQ Delay:
1422 13:08:46.110761 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1423 13:08:46.113714 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1424 13:08:46.117242 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1425 13:08:46.120636 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =80
1426 13:08:46.120724
1427 13:08:46.120793
1428 13:08:46.130585 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d2a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1429 13:08:46.130688 CH0 RK1: MR19=606, MR18=2D2A
1430 13:08:46.137118 CH0_RK1: MR19=0x606, MR18=0x2D2A, DQSOSC=398, MR23=63, INC=93, DEC=62
1431 13:08:46.140254 [RxdqsGatingPostProcess] freq 800
1432 13:08:46.147052 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1433 13:08:46.150417 Pre-setting of DQS Precalculation
1434 13:08:46.153693 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1435 13:08:46.153878 ==
1436 13:08:46.157083 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 13:08:46.164331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 13:08:46.164605 ==
1439 13:08:46.167143 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1440 13:08:46.174074 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1441 13:08:46.183153 [CA 0] Center 36 (6~67) winsize 62
1442 13:08:46.186906 [CA 1] Center 37 (6~68) winsize 63
1443 13:08:46.190348 [CA 2] Center 34 (4~65) winsize 62
1444 13:08:46.193481 [CA 3] Center 34 (4~65) winsize 62
1445 13:08:46.196337 [CA 4] Center 34 (4~65) winsize 62
1446 13:08:46.199998 [CA 5] Center 34 (3~65) winsize 63
1447 13:08:46.200380
1448 13:08:46.203131 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1449 13:08:46.203513
1450 13:08:46.206539 [CATrainingPosCal] consider 1 rank data
1451 13:08:46.209749 u2DelayCellTimex100 = 270/100 ps
1452 13:08:46.213117 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1453 13:08:46.216301 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1454 13:08:46.222890 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1455 13:08:46.226565 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1456 13:08:46.229923 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1457 13:08:46.232992 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1458 13:08:46.233408
1459 13:08:46.236441 CA PerBit enable=1, Macro0, CA PI delay=34
1460 13:08:46.236864
1461 13:08:46.239680 [CBTSetCACLKResult] CA Dly = 34
1462 13:08:46.240113 CS Dly: 4 (0~35)
1463 13:08:46.243204 ==
1464 13:08:46.246384 Dram Type= 6, Freq= 0, CH_1, rank 1
1465 13:08:46.249700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1466 13:08:46.250102 ==
1467 13:08:46.252848 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1468 13:08:46.259391 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1469 13:08:46.269540 [CA 0] Center 36 (6~67) winsize 62
1470 13:08:46.272441 [CA 1] Center 36 (6~67) winsize 62
1471 13:08:46.276091 [CA 2] Center 34 (4~65) winsize 62
1472 13:08:46.278987 [CA 3] Center 34 (3~65) winsize 63
1473 13:08:46.282260 [CA 4] Center 34 (3~65) winsize 63
1474 13:08:46.285952 [CA 5] Center 34 (3~65) winsize 63
1475 13:08:46.286391
1476 13:08:46.288854 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1477 13:08:46.289367
1478 13:08:46.292207 [CATrainingPosCal] consider 2 rank data
1479 13:08:46.295855 u2DelayCellTimex100 = 270/100 ps
1480 13:08:46.298855 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1481 13:08:46.306087 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1482 13:08:46.308997 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1483 13:08:46.312600 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1484 13:08:46.315283 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1485 13:08:46.319101 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1486 13:08:46.319572
1487 13:08:46.322029 CA PerBit enable=1, Macro0, CA PI delay=34
1488 13:08:46.322425
1489 13:08:46.325655 [CBTSetCACLKResult] CA Dly = 34
1490 13:08:46.326052 CS Dly: 5 (0~37)
1491 13:08:46.329065
1492 13:08:46.331890 ----->DramcWriteLeveling(PI) begin...
1493 13:08:46.332292 ==
1494 13:08:46.335488 Dram Type= 6, Freq= 0, CH_1, rank 0
1495 13:08:46.339039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1496 13:08:46.339435 ==
1497 13:08:46.341619 Write leveling (Byte 0): 28 => 28
1498 13:08:46.345068 Write leveling (Byte 1): 30 => 30
1499 13:08:46.348135 DramcWriteLeveling(PI) end<-----
1500 13:08:46.348213
1501 13:08:46.348288 ==
1502 13:08:46.351726 Dram Type= 6, Freq= 0, CH_1, rank 0
1503 13:08:46.354776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1504 13:08:46.354856 ==
1505 13:08:46.358391 [Gating] SW mode calibration
1506 13:08:46.365267 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1507 13:08:46.371432 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1508 13:08:46.374953 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1509 13:08:46.378614 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1510 13:08:46.384915 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 13:08:46.388401 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 13:08:46.391617 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 13:08:46.398109 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 13:08:46.401727 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 13:08:46.404642 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 13:08:46.408110 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 13:08:46.414611 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 13:08:46.418006 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 13:08:46.421459 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 13:08:46.428144 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 13:08:46.431590 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 13:08:46.434547 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 13:08:46.441327 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 13:08:46.444647 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1525 13:08:46.448155 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1526 13:08:46.454555 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 13:08:46.458282 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 13:08:46.461751 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 13:08:46.467987 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 13:08:46.471393 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 13:08:46.474716 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 13:08:46.481484 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 13:08:46.484897 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1534 13:08:46.487847 0 9 8 | B1->B0 | 2f2f 3333 | 1 0 | (1 1) (0 0)
1535 13:08:46.494319 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 13:08:46.497633 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 13:08:46.501040 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 13:08:46.508091 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 13:08:46.511189 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 13:08:46.514652 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 13:08:46.521561 0 10 4 | B1->B0 | 3333 3131 | 0 0 | (1 0) (1 0)
1542 13:08:46.524835 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1543 13:08:46.527390 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 13:08:46.533909 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 13:08:46.537527 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 13:08:46.541075 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 13:08:46.547508 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 13:08:46.551254 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 13:08:46.554154 0 11 4 | B1->B0 | 2525 3232 | 0 1 | (0 0) (0 0)
1550 13:08:46.557809 0 11 8 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
1551 13:08:46.564114 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 13:08:46.567518 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 13:08:46.571189 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 13:08:46.577427 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 13:08:46.581041 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 13:08:46.584267 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 13:08:46.590745 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1558 13:08:46.594037 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1559 13:08:46.597509 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 13:08:46.604299 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 13:08:46.607953 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 13:08:46.610719 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 13:08:46.617885 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 13:08:46.621338 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 13:08:46.624377 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 13:08:46.630982 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 13:08:46.634067 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 13:08:46.637338 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 13:08:46.643926 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 13:08:46.647551 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 13:08:46.650544 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 13:08:46.657763 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 13:08:46.660498 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1574 13:08:46.663768 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 13:08:46.667634 Total UI for P1: 0, mck2ui 16
1576 13:08:46.670500 best dqsien dly found for B0: ( 0, 14, 4)
1577 13:08:46.674037 Total UI for P1: 0, mck2ui 16
1578 13:08:46.677556 best dqsien dly found for B1: ( 0, 14, 6)
1579 13:08:46.680390 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1580 13:08:46.683909 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1581 13:08:46.683986
1582 13:08:46.687496 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1583 13:08:46.690781 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1584 13:08:46.693931 [Gating] SW calibration Done
1585 13:08:46.694008 ==
1586 13:08:46.697433 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 13:08:46.704110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 13:08:46.704188 ==
1589 13:08:46.704264 RX Vref Scan: 0
1590 13:08:46.704335
1591 13:08:46.707247 RX Vref 0 -> 0, step: 1
1592 13:08:46.707314
1593 13:08:46.710325 RX Delay -130 -> 252, step: 16
1594 13:08:46.713942 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1595 13:08:46.717293 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1596 13:08:46.720603 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1597 13:08:46.727042 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1598 13:08:46.730086 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1599 13:08:46.733934 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1600 13:08:46.737359 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1601 13:08:46.740602 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1602 13:08:46.747297 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1603 13:08:46.750368 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1604 13:08:46.753586 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1605 13:08:46.757436 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1606 13:08:46.760273 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1607 13:08:46.767319 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1608 13:08:46.770183 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1609 13:08:46.774011 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1610 13:08:46.774088 ==
1611 13:08:46.776985 Dram Type= 6, Freq= 0, CH_1, rank 0
1612 13:08:46.780464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1613 13:08:46.780543 ==
1614 13:08:46.783502 DQS Delay:
1615 13:08:46.783572 DQS0 = 0, DQS1 = 0
1616 13:08:46.786877 DQM Delay:
1617 13:08:46.786944 DQM0 = 86, DQM1 = 79
1618 13:08:46.787015 DQ Delay:
1619 13:08:46.789998 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1620 13:08:46.793515 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1621 13:08:46.797021 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1622 13:08:46.800371 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1623 13:08:46.800447
1624 13:08:46.800523
1625 13:08:46.803500 ==
1626 13:08:46.803577 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 13:08:46.810216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 13:08:46.810294 ==
1629 13:08:46.810370
1630 13:08:46.810442
1631 13:08:46.813623 TX Vref Scan disable
1632 13:08:46.813700 == TX Byte 0 ==
1633 13:08:46.816721 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1634 13:08:46.823193 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1635 13:08:46.823289 == TX Byte 1 ==
1636 13:08:46.826456 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1637 13:08:46.833093 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1638 13:08:46.833237 ==
1639 13:08:46.836561 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 13:08:46.840136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 13:08:46.840214 ==
1642 13:08:46.853577 TX Vref=22, minBit 6, minWin=26, winSum=441
1643 13:08:46.856768 TX Vref=24, minBit 3, minWin=27, winSum=448
1644 13:08:46.859819 TX Vref=26, minBit 3, minWin=27, winSum=449
1645 13:08:46.863372 TX Vref=28, minBit 0, minWin=27, winSum=454
1646 13:08:46.866945 TX Vref=30, minBit 0, minWin=28, winSum=454
1647 13:08:46.870050 TX Vref=32, minBit 1, minWin=27, winSum=451
1648 13:08:46.876401 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
1649 13:08:46.876493
1650 13:08:46.879924 Final TX Range 1 Vref 30
1651 13:08:46.880010
1652 13:08:46.880090 ==
1653 13:08:46.883472 Dram Type= 6, Freq= 0, CH_1, rank 0
1654 13:08:46.886448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1655 13:08:46.886532 ==
1656 13:08:46.889898
1657 13:08:46.889980
1658 13:08:46.890058 TX Vref Scan disable
1659 13:08:46.893451 == TX Byte 0 ==
1660 13:08:46.896433 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1661 13:08:46.899988 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1662 13:08:46.903609 == TX Byte 1 ==
1663 13:08:46.906798 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1664 13:08:46.910070 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1665 13:08:46.913424
1666 13:08:46.913482 [DATLAT]
1667 13:08:46.913534 Freq=800, CH1 RK0
1668 13:08:46.913590
1669 13:08:46.916326 DATLAT Default: 0xa
1670 13:08:46.916409 0, 0xFFFF, sum = 0
1671 13:08:46.920144 1, 0xFFFF, sum = 0
1672 13:08:46.920231 2, 0xFFFF, sum = 0
1673 13:08:46.923157 3, 0xFFFF, sum = 0
1674 13:08:46.923244 4, 0xFFFF, sum = 0
1675 13:08:46.926516 5, 0xFFFF, sum = 0
1676 13:08:46.929712 6, 0xFFFF, sum = 0
1677 13:08:46.929771 7, 0xFFFF, sum = 0
1678 13:08:46.933079 8, 0xFFFF, sum = 0
1679 13:08:46.933183 9, 0x0, sum = 1
1680 13:08:46.933259 10, 0x0, sum = 2
1681 13:08:46.936474 11, 0x0, sum = 3
1682 13:08:46.936557 12, 0x0, sum = 4
1683 13:08:46.939481 best_step = 10
1684 13:08:46.939562
1685 13:08:46.939639 ==
1686 13:08:46.943192 Dram Type= 6, Freq= 0, CH_1, rank 0
1687 13:08:46.946360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1688 13:08:46.946453 ==
1689 13:08:46.949504 RX Vref Scan: 1
1690 13:08:46.949601
1691 13:08:46.949686 Set Vref Range= 32 -> 127
1692 13:08:46.952874
1693 13:08:46.952965 RX Vref 32 -> 127, step: 1
1694 13:08:46.953046
1695 13:08:46.956228 RX Delay -95 -> 252, step: 8
1696 13:08:46.956317
1697 13:08:46.959825 Set Vref, RX VrefLevel [Byte0]: 32
1698 13:08:46.962804 [Byte1]: 32
1699 13:08:46.962894
1700 13:08:46.966014 Set Vref, RX VrefLevel [Byte0]: 33
1701 13:08:46.969867 [Byte1]: 33
1702 13:08:46.973250
1703 13:08:46.973316 Set Vref, RX VrefLevel [Byte0]: 34
1704 13:08:46.976806 [Byte1]: 34
1705 13:08:46.981066
1706 13:08:46.981189 Set Vref, RX VrefLevel [Byte0]: 35
1707 13:08:46.984707 [Byte1]: 35
1708 13:08:46.988712
1709 13:08:46.988801 Set Vref, RX VrefLevel [Byte0]: 36
1710 13:08:46.991693 [Byte1]: 36
1711 13:08:46.996606
1712 13:08:46.996694 Set Vref, RX VrefLevel [Byte0]: 37
1713 13:08:46.999500 [Byte1]: 37
1714 13:08:47.003594
1715 13:08:47.003683 Set Vref, RX VrefLevel [Byte0]: 38
1716 13:08:47.007303 [Byte1]: 38
1717 13:08:47.011360
1718 13:08:47.011461 Set Vref, RX VrefLevel [Byte0]: 39
1719 13:08:47.014864 [Byte1]: 39
1720 13:08:47.019307
1721 13:08:47.019400 Set Vref, RX VrefLevel [Byte0]: 40
1722 13:08:47.022374 [Byte1]: 40
1723 13:08:47.026662
1724 13:08:47.026754 Set Vref, RX VrefLevel [Byte0]: 41
1725 13:08:47.030129 [Byte1]: 41
1726 13:08:47.034326
1727 13:08:47.034418 Set Vref, RX VrefLevel [Byte0]: 42
1728 13:08:47.037584 [Byte1]: 42
1729 13:08:47.041893
1730 13:08:47.041989 Set Vref, RX VrefLevel [Byte0]: 43
1731 13:08:47.045051 [Byte1]: 43
1732 13:08:47.049715
1733 13:08:47.049808 Set Vref, RX VrefLevel [Byte0]: 44
1734 13:08:47.053009 [Byte1]: 44
1735 13:08:47.057218
1736 13:08:47.057309 Set Vref, RX VrefLevel [Byte0]: 45
1737 13:08:47.060334 [Byte1]: 45
1738 13:08:47.064559
1739 13:08:47.064650 Set Vref, RX VrefLevel [Byte0]: 46
1740 13:08:47.068023 [Byte1]: 46
1741 13:08:47.072554
1742 13:08:47.072623 Set Vref, RX VrefLevel [Byte0]: 47
1743 13:08:47.075693 [Byte1]: 47
1744 13:08:47.080097
1745 13:08:47.080172 Set Vref, RX VrefLevel [Byte0]: 48
1746 13:08:47.083315 [Byte1]: 48
1747 13:08:47.087251
1748 13:08:47.087326 Set Vref, RX VrefLevel [Byte0]: 49
1749 13:08:47.090785 [Byte1]: 49
1750 13:08:47.094796
1751 13:08:47.094871 Set Vref, RX VrefLevel [Byte0]: 50
1752 13:08:47.098413 [Byte1]: 50
1753 13:08:47.102594
1754 13:08:47.102668 Set Vref, RX VrefLevel [Byte0]: 51
1755 13:08:47.106083 [Byte1]: 51
1756 13:08:47.110367
1757 13:08:47.110445 Set Vref, RX VrefLevel [Byte0]: 52
1758 13:08:47.113252 [Byte1]: 52
1759 13:08:47.117999
1760 13:08:47.118076 Set Vref, RX VrefLevel [Byte0]: 53
1761 13:08:47.121113 [Byte1]: 53
1762 13:08:47.125476
1763 13:08:47.125569 Set Vref, RX VrefLevel [Byte0]: 54
1764 13:08:47.128795 [Byte1]: 54
1765 13:08:47.132882
1766 13:08:47.132982 Set Vref, RX VrefLevel [Byte0]: 55
1767 13:08:47.136791 [Byte1]: 55
1768 13:08:47.140903
1769 13:08:47.140989 Set Vref, RX VrefLevel [Byte0]: 56
1770 13:08:47.143765 [Byte1]: 56
1771 13:08:47.148174
1772 13:08:47.148266 Set Vref, RX VrefLevel [Byte0]: 57
1773 13:08:47.151418 [Byte1]: 57
1774 13:08:47.155617
1775 13:08:47.155709 Set Vref, RX VrefLevel [Byte0]: 58
1776 13:08:47.158837 [Byte1]: 58
1777 13:08:47.163178
1778 13:08:47.163267 Set Vref, RX VrefLevel [Byte0]: 59
1779 13:08:47.166869 [Byte1]: 59
1780 13:08:47.171080
1781 13:08:47.171157 Set Vref, RX VrefLevel [Byte0]: 60
1782 13:08:47.174350 [Byte1]: 60
1783 13:08:47.178521
1784 13:08:47.178598 Set Vref, RX VrefLevel [Byte0]: 61
1785 13:08:47.182372 [Byte1]: 61
1786 13:08:47.186437
1787 13:08:47.186514 Set Vref, RX VrefLevel [Byte0]: 62
1788 13:08:47.189606 [Byte1]: 62
1789 13:08:47.194056
1790 13:08:47.194191 Set Vref, RX VrefLevel [Byte0]: 63
1791 13:08:47.196802 [Byte1]: 63
1792 13:08:47.201528
1793 13:08:47.201597 Set Vref, RX VrefLevel [Byte0]: 64
1794 13:08:47.204546 [Byte1]: 64
1795 13:08:47.209293
1796 13:08:47.209371 Set Vref, RX VrefLevel [Byte0]: 65
1797 13:08:47.212162 [Byte1]: 65
1798 13:08:47.216899
1799 13:08:47.216975 Set Vref, RX VrefLevel [Byte0]: 66
1800 13:08:47.219838 [Byte1]: 66
1801 13:08:47.224045
1802 13:08:47.224122 Set Vref, RX VrefLevel [Byte0]: 67
1803 13:08:47.227587 [Byte1]: 67
1804 13:08:47.231519
1805 13:08:47.231603 Set Vref, RX VrefLevel [Byte0]: 68
1806 13:08:47.234838 [Byte1]: 68
1807 13:08:47.239323
1808 13:08:47.239399 Set Vref, RX VrefLevel [Byte0]: 69
1809 13:08:47.242838 [Byte1]: 69
1810 13:08:47.247005
1811 13:08:47.247082 Set Vref, RX VrefLevel [Byte0]: 70
1812 13:08:47.250594 [Byte1]: 70
1813 13:08:47.254397
1814 13:08:47.254472 Set Vref, RX VrefLevel [Byte0]: 71
1815 13:08:47.257584 [Byte1]: 71
1816 13:08:47.261958
1817 13:08:47.262034 Set Vref, RX VrefLevel [Byte0]: 72
1818 13:08:47.265483 [Byte1]: 72
1819 13:08:47.269607
1820 13:08:47.269685 Final RX Vref Byte 0 = 57 to rank0
1821 13:08:47.272883 Final RX Vref Byte 1 = 53 to rank0
1822 13:08:47.276514 Final RX Vref Byte 0 = 57 to rank1
1823 13:08:47.279553 Final RX Vref Byte 1 = 53 to rank1==
1824 13:08:47.282670 Dram Type= 6, Freq= 0, CH_1, rank 0
1825 13:08:47.289787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1826 13:08:47.289865 ==
1827 13:08:47.289931 DQS Delay:
1828 13:08:47.292682 DQS0 = 0, DQS1 = 0
1829 13:08:47.292770 DQM Delay:
1830 13:08:47.292850 DQM0 = 84, DQM1 = 80
1831 13:08:47.296669 DQ Delay:
1832 13:08:47.299805 DQ0 =92, DQ1 =80, DQ2 =72, DQ3 =84
1833 13:08:47.303007 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =80
1834 13:08:47.305953 DQ8 =64, DQ9 =72, DQ10 =80, DQ11 =76
1835 13:08:47.309523 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1836 13:08:47.309584
1837 13:08:47.309665
1838 13:08:47.315834 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d30, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1839 13:08:47.319442 CH1 RK0: MR19=606, MR18=1D30
1840 13:08:47.326075 CH1_RK0: MR19=0x606, MR18=0x1D30, DQSOSC=397, MR23=63, INC=93, DEC=62
1841 13:08:47.326164
1842 13:08:47.329621 ----->DramcWriteLeveling(PI) begin...
1843 13:08:47.329683 ==
1844 13:08:47.332466 Dram Type= 6, Freq= 0, CH_1, rank 1
1845 13:08:47.336040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1846 13:08:47.336123 ==
1847 13:08:47.339029 Write leveling (Byte 0): 27 => 27
1848 13:08:47.342286 Write leveling (Byte 1): 28 => 28
1849 13:08:47.346563 DramcWriteLeveling(PI) end<-----
1850 13:08:47.346649
1851 13:08:47.346728 ==
1852 13:08:47.349272 Dram Type= 6, Freq= 0, CH_1, rank 1
1853 13:08:47.352757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 13:08:47.352849 ==
1855 13:08:47.355521 [Gating] SW mode calibration
1856 13:08:47.362291 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1857 13:08:47.368821 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1858 13:08:47.372260 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1859 13:08:47.378961 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1860 13:08:47.382175 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1861 13:08:47.385637 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 13:08:47.392010 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 13:08:47.395724 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 13:08:47.398591 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 13:08:47.405130 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 13:08:47.408473 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 13:08:47.412049 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 13:08:47.418991 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 13:08:47.422019 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 13:08:47.425614 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 13:08:47.431974 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 13:08:47.434943 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 13:08:47.438272 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 13:08:47.445041 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1875 13:08:47.448617 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1876 13:08:47.451411 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 13:08:47.454996 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 13:08:47.461880 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 13:08:47.465305 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 13:08:47.468269 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 13:08:47.475415 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 13:08:47.478353 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 13:08:47.481945 0 9 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1884 13:08:47.488518 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1885 13:08:47.492411 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1886 13:08:47.495164 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1887 13:08:47.501682 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 13:08:47.505002 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 13:08:47.508803 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 13:08:47.515506 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 13:08:47.518711 0 10 4 | B1->B0 | 3131 2b2b | 1 0 | (1 0) (1 1)
1892 13:08:47.521899 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1893 13:08:47.528244 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 13:08:47.531970 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 13:08:47.534872 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 13:08:47.541960 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 13:08:47.545121 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 13:08:47.548912 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1899 13:08:47.555184 0 11 4 | B1->B0 | 2f2f 4040 | 0 0 | (0 0) (0 0)
1900 13:08:47.558559 0 11 8 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
1901 13:08:47.562101 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1902 13:08:47.568616 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 13:08:47.572124 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 13:08:47.574696 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 13:08:47.581033 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 13:08:47.584688 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1907 13:08:47.588211 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1908 13:08:47.591054 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 13:08:47.597708 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 13:08:47.601062 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 13:08:47.607520 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 13:08:47.611328 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 13:08:47.614246 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 13:08:47.620680 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 13:08:47.624027 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 13:08:47.627162 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 13:08:47.630798 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 13:08:47.637401 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 13:08:47.640341 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 13:08:47.644044 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 13:08:47.650959 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 13:08:47.653864 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1923 13:08:47.657315 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1924 13:08:47.660275 Total UI for P1: 0, mck2ui 16
1925 13:08:47.663761 best dqsien dly found for B0: ( 0, 14, 0)
1926 13:08:47.670487 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1927 13:08:47.673725 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 13:08:47.677435 Total UI for P1: 0, mck2ui 16
1929 13:08:47.680959 best dqsien dly found for B1: ( 0, 14, 6)
1930 13:08:47.683847 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1931 13:08:47.687361 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1932 13:08:47.687436
1933 13:08:47.690876 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1934 13:08:47.693887 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1935 13:08:47.697429 [Gating] SW calibration Done
1936 13:08:47.697504 ==
1937 13:08:47.700860 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 13:08:47.703615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 13:08:47.707399 ==
1940 13:08:47.707474 RX Vref Scan: 0
1941 13:08:47.707534
1942 13:08:47.710536 RX Vref 0 -> 0, step: 1
1943 13:08:47.710611
1944 13:08:47.713310 RX Delay -130 -> 252, step: 16
1945 13:08:47.716958 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1946 13:08:47.720243 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1947 13:08:47.723720 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1948 13:08:47.726890 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1949 13:08:47.733713 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1950 13:08:47.736719 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1951 13:08:47.740263 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1952 13:08:47.743478 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1953 13:08:47.746898 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1954 13:08:47.753065 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1955 13:08:47.756530 iDelay=206, Bit 10, Center 93 (-18 ~ 205) 224
1956 13:08:47.760076 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1957 13:08:47.763108 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1958 13:08:47.769961 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1959 13:08:47.773705 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1960 13:08:47.776367 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1961 13:08:47.776434 ==
1962 13:08:47.779777 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 13:08:47.782964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 13:08:47.783041 ==
1965 13:08:47.786214 DQS Delay:
1966 13:08:47.786290 DQS0 = 0, DQS1 = 0
1967 13:08:47.789686 DQM Delay:
1968 13:08:47.789761 DQM0 = 86, DQM1 = 85
1969 13:08:47.789820 DQ Delay:
1970 13:08:47.793165 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1971 13:08:47.796694 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1972 13:08:47.799720 DQ8 =69, DQ9 =69, DQ10 =93, DQ11 =77
1973 13:08:47.803280 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1974 13:08:47.803355
1975 13:08:47.803414
1976 13:08:47.803468 ==
1977 13:08:47.806484 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 13:08:47.812756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 13:08:47.812832 ==
1980 13:08:47.812891
1981 13:08:47.812944
1982 13:08:47.812995 TX Vref Scan disable
1983 13:08:47.816977 == TX Byte 0 ==
1984 13:08:47.820219 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1985 13:08:47.826578 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1986 13:08:47.826654 == TX Byte 1 ==
1987 13:08:47.830088 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1988 13:08:47.836823 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1989 13:08:47.836902 ==
1990 13:08:47.840272 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 13:08:47.843080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 13:08:47.843155 ==
1993 13:08:47.856020 TX Vref=22, minBit 1, minWin=27, winSum=449
1994 13:08:47.859418 TX Vref=24, minBit 1, minWin=27, winSum=449
1995 13:08:47.862548 TX Vref=26, minBit 5, minWin=27, winSum=452
1996 13:08:47.866000 TX Vref=28, minBit 5, minWin=27, winSum=454
1997 13:08:47.869522 TX Vref=30, minBit 0, minWin=28, winSum=456
1998 13:08:47.872459 TX Vref=32, minBit 5, minWin=27, winSum=453
1999 13:08:47.878880 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
2000 13:08:47.878955
2001 13:08:47.882514 Final TX Range 1 Vref 30
2002 13:08:47.882589
2003 13:08:47.882648 ==
2004 13:08:47.885400 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 13:08:47.888954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 13:08:47.889029 ==
2007 13:08:47.892281
2008 13:08:47.892355
2009 13:08:47.892413 TX Vref Scan disable
2010 13:08:47.895707 == TX Byte 0 ==
2011 13:08:47.899350 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2012 13:08:47.905809 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2013 13:08:47.905885 == TX Byte 1 ==
2014 13:08:47.908709 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2015 13:08:47.915643 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2016 13:08:47.915718
2017 13:08:47.915777 [DATLAT]
2018 13:08:47.915832 Freq=800, CH1 RK1
2019 13:08:47.915884
2020 13:08:47.919123 DATLAT Default: 0xa
2021 13:08:47.919199 0, 0xFFFF, sum = 0
2022 13:08:47.922652 1, 0xFFFF, sum = 0
2023 13:08:47.922728 2, 0xFFFF, sum = 0
2024 13:08:47.925531 3, 0xFFFF, sum = 0
2025 13:08:47.928918 4, 0xFFFF, sum = 0
2026 13:08:47.928994 5, 0xFFFF, sum = 0
2027 13:08:47.932493 6, 0xFFFF, sum = 0
2028 13:08:47.932569 7, 0xFFFF, sum = 0
2029 13:08:47.935258 8, 0xFFFF, sum = 0
2030 13:08:47.935334 9, 0x0, sum = 1
2031 13:08:47.938790 10, 0x0, sum = 2
2032 13:08:47.938867 11, 0x0, sum = 3
2033 13:08:47.938927 12, 0x0, sum = 4
2034 13:08:47.942029 best_step = 10
2035 13:08:47.942104
2036 13:08:47.942162 ==
2037 13:08:47.945477 Dram Type= 6, Freq= 0, CH_1, rank 1
2038 13:08:47.948882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2039 13:08:47.948958 ==
2040 13:08:47.952293 RX Vref Scan: 0
2041 13:08:47.952368
2042 13:08:47.952426 RX Vref 0 -> 0, step: 1
2043 13:08:47.955429
2044 13:08:47.955504 RX Delay -95 -> 252, step: 8
2045 13:08:47.962323 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2046 13:08:47.965901 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
2047 13:08:47.968906 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2048 13:08:47.972498 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2049 13:08:47.975427 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2050 13:08:47.982205 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2051 13:08:47.985718 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2052 13:08:47.988669 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2053 13:08:47.992300 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2054 13:08:47.995185 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2055 13:08:48.002144 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
2056 13:08:48.005415 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2057 13:08:48.009079 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2058 13:08:48.011918 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2059 13:08:48.018586 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2060 13:08:48.021918 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2061 13:08:48.021993 ==
2062 13:08:48.025117 Dram Type= 6, Freq= 0, CH_1, rank 1
2063 13:08:48.028713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2064 13:08:48.028789 ==
2065 13:08:48.031839 DQS Delay:
2066 13:08:48.031913 DQS0 = 0, DQS1 = 0
2067 13:08:48.031972 DQM Delay:
2068 13:08:48.035497 DQM0 = 86, DQM1 = 82
2069 13:08:48.035571 DQ Delay:
2070 13:08:48.038484 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
2071 13:08:48.042059 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2072 13:08:48.045430 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =76
2073 13:08:48.048730 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =88
2074 13:08:48.048804
2075 13:08:48.048863
2076 13:08:48.058628 [DQSOSCAuto] RK1, (LSB)MR18= 0x233f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 401 ps
2077 13:08:48.058707 CH1 RK1: MR19=606, MR18=233F
2078 13:08:48.065099 CH1_RK1: MR19=0x606, MR18=0x233F, DQSOSC=393, MR23=63, INC=95, DEC=63
2079 13:08:48.068276 [RxdqsGatingPostProcess] freq 800
2080 13:08:48.075121 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2081 13:08:48.078544 Pre-setting of DQS Precalculation
2082 13:08:48.081512 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2083 13:08:48.088602 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2084 13:08:48.098319 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2085 13:08:48.098397
2086 13:08:48.098457
2087 13:08:48.101442 [Calibration Summary] 1600 Mbps
2088 13:08:48.101556 CH 0, Rank 0
2089 13:08:48.104779 SW Impedance : PASS
2090 13:08:48.104854 DUTY Scan : NO K
2091 13:08:48.107660 ZQ Calibration : PASS
2092 13:08:48.111354 Jitter Meter : NO K
2093 13:08:48.111431 CBT Training : PASS
2094 13:08:48.114708 Write leveling : PASS
2095 13:08:48.117770 RX DQS gating : PASS
2096 13:08:48.117846 RX DQ/DQS(RDDQC) : PASS
2097 13:08:48.121128 TX DQ/DQS : PASS
2098 13:08:48.124755 RX DATLAT : PASS
2099 13:08:48.124831 RX DQ/DQS(Engine): PASS
2100 13:08:48.127751 TX OE : NO K
2101 13:08:48.127826 All Pass.
2102 13:08:48.127884
2103 13:08:48.127938 CH 0, Rank 1
2104 13:08:48.131127 SW Impedance : PASS
2105 13:08:48.134356 DUTY Scan : NO K
2106 13:08:48.134431 ZQ Calibration : PASS
2107 13:08:48.137549 Jitter Meter : NO K
2108 13:08:48.141102 CBT Training : PASS
2109 13:08:48.141227 Write leveling : PASS
2110 13:08:48.144103 RX DQS gating : PASS
2111 13:08:48.147754 RX DQ/DQS(RDDQC) : PASS
2112 13:08:48.147829 TX DQ/DQS : PASS
2113 13:08:48.151298 RX DATLAT : PASS
2114 13:08:48.154141 RX DQ/DQS(Engine): PASS
2115 13:08:48.154217 TX OE : NO K
2116 13:08:48.157630 All Pass.
2117 13:08:48.157705
2118 13:08:48.157763 CH 1, Rank 0
2119 13:08:48.160960 SW Impedance : PASS
2120 13:08:48.161035 DUTY Scan : NO K
2121 13:08:48.164124 ZQ Calibration : PASS
2122 13:08:48.167519 Jitter Meter : NO K
2123 13:08:48.167594 CBT Training : PASS
2124 13:08:48.170973 Write leveling : PASS
2125 13:08:48.174201 RX DQS gating : PASS
2126 13:08:48.174277 RX DQ/DQS(RDDQC) : PASS
2127 13:08:48.177487 TX DQ/DQS : PASS
2128 13:08:48.180729 RX DATLAT : PASS
2129 13:08:48.180819 RX DQ/DQS(Engine): PASS
2130 13:08:48.184372 TX OE : NO K
2131 13:08:48.184451 All Pass.
2132 13:08:48.184509
2133 13:08:48.187267 CH 1, Rank 1
2134 13:08:48.187357 SW Impedance : PASS
2135 13:08:48.190687 DUTY Scan : NO K
2136 13:08:48.190762 ZQ Calibration : PASS
2137 13:08:48.194092 Jitter Meter : NO K
2138 13:08:48.197116 CBT Training : PASS
2139 13:08:48.197228 Write leveling : PASS
2140 13:08:48.200740 RX DQS gating : PASS
2141 13:08:48.203772 RX DQ/DQS(RDDQC) : PASS
2142 13:08:48.203847 TX DQ/DQS : PASS
2143 13:08:48.207323 RX DATLAT : PASS
2144 13:08:48.210598 RX DQ/DQS(Engine): PASS
2145 13:08:48.210673 TX OE : NO K
2146 13:08:48.214114 All Pass.
2147 13:08:48.214189
2148 13:08:48.214247 DramC Write-DBI off
2149 13:08:48.217541 PER_BANK_REFRESH: Hybrid Mode
2150 13:08:48.217616 TX_TRACKING: ON
2151 13:08:48.223645 [GetDramInforAfterCalByMRR] Vendor 6.
2152 13:08:48.227274 [GetDramInforAfterCalByMRR] Revision 606.
2153 13:08:48.230164 [GetDramInforAfterCalByMRR] Revision 2 0.
2154 13:08:48.230240 MR0 0x3b3b
2155 13:08:48.230298 MR8 0x5151
2156 13:08:48.236656 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2157 13:08:48.236732
2158 13:08:48.236791 MR0 0x3b3b
2159 13:08:48.236845 MR8 0x5151
2160 13:08:48.240158 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2161 13:08:48.240233
2162 13:08:48.250365 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2163 13:08:48.253805 [FAST_K] Save calibration result to emmc
2164 13:08:48.256803 [FAST_K] Save calibration result to emmc
2165 13:08:48.260327 dram_init: config_dvfs: 1
2166 13:08:48.263394 dramc_set_vcore_voltage set vcore to 662500
2167 13:08:48.266838 Read voltage for 1200, 2
2168 13:08:48.266913 Vio18 = 0
2169 13:08:48.266971 Vcore = 662500
2170 13:08:48.270221 Vdram = 0
2171 13:08:48.270297 Vddq = 0
2172 13:08:48.270356 Vmddr = 0
2173 13:08:48.276961 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2174 13:08:48.280128 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2175 13:08:48.283624 MEM_TYPE=3, freq_sel=15
2176 13:08:48.286880 sv_algorithm_assistance_LP4_1600
2177 13:08:48.290448 ============ PULL DRAM RESETB DOWN ============
2178 13:08:48.293795 ========== PULL DRAM RESETB DOWN end =========
2179 13:08:48.300320 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2180 13:08:48.303352 ===================================
2181 13:08:48.306851 LPDDR4 DRAM CONFIGURATION
2182 13:08:48.310320 ===================================
2183 13:08:48.310396 EX_ROW_EN[0] = 0x0
2184 13:08:48.313356 EX_ROW_EN[1] = 0x0
2185 13:08:48.313431 LP4Y_EN = 0x0
2186 13:08:48.316823 WORK_FSP = 0x0
2187 13:08:48.316898 WL = 0x4
2188 13:08:48.320288 RL = 0x4
2189 13:08:48.320362 BL = 0x2
2190 13:08:48.323124 RPST = 0x0
2191 13:08:48.323199 RD_PRE = 0x0
2192 13:08:48.326642 WR_PRE = 0x1
2193 13:08:48.326717 WR_PST = 0x0
2194 13:08:48.330052 DBI_WR = 0x0
2195 13:08:48.330127 DBI_RD = 0x0
2196 13:08:48.333133 OTF = 0x1
2197 13:08:48.336894 ===================================
2198 13:08:48.339915 ===================================
2199 13:08:48.339991 ANA top config
2200 13:08:48.343027 ===================================
2201 13:08:48.346311 DLL_ASYNC_EN = 0
2202 13:08:48.349948 ALL_SLAVE_EN = 0
2203 13:08:48.353380 NEW_RANK_MODE = 1
2204 13:08:48.353457 DLL_IDLE_MODE = 1
2205 13:08:48.356524 LP45_APHY_COMB_EN = 1
2206 13:08:48.359913 TX_ODT_DIS = 1
2207 13:08:48.363495 NEW_8X_MODE = 1
2208 13:08:48.366286 ===================================
2209 13:08:48.369840 ===================================
2210 13:08:48.373198 data_rate = 2400
2211 13:08:48.376495 CKR = 1
2212 13:08:48.376570 DQ_P2S_RATIO = 8
2213 13:08:48.379673 ===================================
2214 13:08:48.383453 CA_P2S_RATIO = 8
2215 13:08:48.386176 DQ_CA_OPEN = 0
2216 13:08:48.389800 DQ_SEMI_OPEN = 0
2217 13:08:48.393016 CA_SEMI_OPEN = 0
2218 13:08:48.396063 CA_FULL_RATE = 0
2219 13:08:48.396138 DQ_CKDIV4_EN = 0
2220 13:08:48.399565 CA_CKDIV4_EN = 0
2221 13:08:48.402875 CA_PREDIV_EN = 0
2222 13:08:48.406401 PH8_DLY = 17
2223 13:08:48.409374 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2224 13:08:48.412944 DQ_AAMCK_DIV = 4
2225 13:08:48.413019 CA_AAMCK_DIV = 4
2226 13:08:48.415924 CA_ADMCK_DIV = 4
2227 13:08:48.419407 DQ_TRACK_CA_EN = 0
2228 13:08:48.422988 CA_PICK = 1200
2229 13:08:48.426340 CA_MCKIO = 1200
2230 13:08:48.429339 MCKIO_SEMI = 0
2231 13:08:48.432808 PLL_FREQ = 2366
2232 13:08:48.432883 DQ_UI_PI_RATIO = 32
2233 13:08:48.436004 CA_UI_PI_RATIO = 0
2234 13:08:48.439388 ===================================
2235 13:08:48.442944 ===================================
2236 13:08:48.446535 memory_type:LPDDR4
2237 13:08:48.449324 GP_NUM : 10
2238 13:08:48.449400 SRAM_EN : 1
2239 13:08:48.452711 MD32_EN : 0
2240 13:08:48.456309 ===================================
2241 13:08:48.456383 [ANA_INIT] >>>>>>>>>>>>>>
2242 13:08:48.459134 <<<<<< [CONFIGURE PHASE]: ANA_TX
2243 13:08:48.462569 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2244 13:08:48.466198 ===================================
2245 13:08:48.469675 data_rate = 2400,PCW = 0X5b00
2246 13:08:48.472486 ===================================
2247 13:08:48.476028 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2248 13:08:48.482792 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2249 13:08:48.489126 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2250 13:08:48.492437 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2251 13:08:48.495806 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2252 13:08:48.499293 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2253 13:08:48.502735 [ANA_INIT] flow start
2254 13:08:48.502815 [ANA_INIT] PLL >>>>>>>>
2255 13:08:48.505719 [ANA_INIT] PLL <<<<<<<<
2256 13:08:48.509142 [ANA_INIT] MIDPI >>>>>>>>
2257 13:08:48.509228 [ANA_INIT] MIDPI <<<<<<<<
2258 13:08:48.512779 [ANA_INIT] DLL >>>>>>>>
2259 13:08:48.515904 [ANA_INIT] DLL <<<<<<<<
2260 13:08:48.516035 [ANA_INIT] flow end
2261 13:08:48.522320 ============ LP4 DIFF to SE enter ============
2262 13:08:48.525818 ============ LP4 DIFF to SE exit ============
2263 13:08:48.529346 [ANA_INIT] <<<<<<<<<<<<<
2264 13:08:48.529418 [Flow] Enable top DCM control >>>>>
2265 13:08:48.532272 [Flow] Enable top DCM control <<<<<
2266 13:08:48.535678 Enable DLL master slave shuffle
2267 13:08:48.542802 ==============================================================
2268 13:08:48.546183 Gating Mode config
2269 13:08:48.549387 ==============================================================
2270 13:08:48.552483 Config description:
2271 13:08:48.562178 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2272 13:08:48.569037 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2273 13:08:48.572296 SELPH_MODE 0: By rank 1: By Phase
2274 13:08:48.578744 ==============================================================
2275 13:08:48.582284 GAT_TRACK_EN = 1
2276 13:08:48.585339 RX_GATING_MODE = 2
2277 13:08:48.588697 RX_GATING_TRACK_MODE = 2
2278 13:08:48.592117 SELPH_MODE = 1
2279 13:08:48.592192 PICG_EARLY_EN = 1
2280 13:08:48.595184 VALID_LAT_VALUE = 1
2281 13:08:48.602167 ==============================================================
2282 13:08:48.605088 Enter into Gating configuration >>>>
2283 13:08:48.608604 Exit from Gating configuration <<<<
2284 13:08:48.612052 Enter into DVFS_PRE_config >>>>>
2285 13:08:48.621994 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2286 13:08:48.625150 Exit from DVFS_PRE_config <<<<<
2287 13:08:48.628669 Enter into PICG configuration >>>>
2288 13:08:48.631621 Exit from PICG configuration <<<<
2289 13:08:48.634943 [RX_INPUT] configuration >>>>>
2290 13:08:48.638480 [RX_INPUT] configuration <<<<<
2291 13:08:48.641953 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2292 13:08:48.648453 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2293 13:08:48.655480 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2294 13:08:48.661649 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2295 13:08:48.668143 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2296 13:08:48.671672 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2297 13:08:48.678666 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2298 13:08:48.681586 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2299 13:08:48.685153 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2300 13:08:48.688490 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2301 13:08:48.695049 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2302 13:08:48.698488 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2303 13:08:48.701422 ===================================
2304 13:08:48.705072 LPDDR4 DRAM CONFIGURATION
2305 13:08:48.708139 ===================================
2306 13:08:48.708214 EX_ROW_EN[0] = 0x0
2307 13:08:48.711725 EX_ROW_EN[1] = 0x0
2308 13:08:48.711800 LP4Y_EN = 0x0
2309 13:08:48.714792 WORK_FSP = 0x0
2310 13:08:48.714863 WL = 0x4
2311 13:08:48.718268 RL = 0x4
2312 13:08:48.718341 BL = 0x2
2313 13:08:48.721527 RPST = 0x0
2314 13:08:48.721600 RD_PRE = 0x0
2315 13:08:48.724795 WR_PRE = 0x1
2316 13:08:48.724871 WR_PST = 0x0
2317 13:08:48.728048 DBI_WR = 0x0
2318 13:08:48.728123 DBI_RD = 0x0
2319 13:08:48.731963 OTF = 0x1
2320 13:08:48.735456 ===================================
2321 13:08:48.738573 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2322 13:08:48.741814 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2323 13:08:48.748441 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2324 13:08:48.751313 ===================================
2325 13:08:48.754847 LPDDR4 DRAM CONFIGURATION
2326 13:08:48.758219 ===================================
2327 13:08:48.758322 EX_ROW_EN[0] = 0x10
2328 13:08:48.761096 EX_ROW_EN[1] = 0x0
2329 13:08:48.761233 LP4Y_EN = 0x0
2330 13:08:48.764734 WORK_FSP = 0x0
2331 13:08:48.764857 WL = 0x4
2332 13:08:48.767925 RL = 0x4
2333 13:08:48.768001 BL = 0x2
2334 13:08:48.771361 RPST = 0x0
2335 13:08:48.771437 RD_PRE = 0x0
2336 13:08:48.774383 WR_PRE = 0x1
2337 13:08:48.774458 WR_PST = 0x0
2338 13:08:48.777991 DBI_WR = 0x0
2339 13:08:48.778066 DBI_RD = 0x0
2340 13:08:48.781516 OTF = 0x1
2341 13:08:48.784378 ===================================
2342 13:08:48.791049 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2343 13:08:48.791126 ==
2344 13:08:48.794533 Dram Type= 6, Freq= 0, CH_0, rank 0
2345 13:08:48.797810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2346 13:08:48.797886 ==
2347 13:08:48.801283 [Duty_Offset_Calibration]
2348 13:08:48.801359 B0:2 B1:0 CA:4
2349 13:08:48.801417
2350 13:08:48.804981 [DutyScan_Calibration_Flow] k_type=0
2351 13:08:48.815654
2352 13:08:48.815733 ==CLK 0==
2353 13:08:48.818772 Final CLK duty delay cell = 0
2354 13:08:48.822259 [0] MAX Duty = 5156%(X100), DQS PI = 14
2355 13:08:48.825252 [0] MIN Duty = 5000%(X100), DQS PI = 8
2356 13:08:48.825346 [0] AVG Duty = 5078%(X100)
2357 13:08:48.828244
2358 13:08:48.831707 CH0 CLK Duty spec in!! Max-Min= 156%
2359 13:08:48.834828 [DutyScan_Calibration_Flow] ====Done====
2360 13:08:48.834945
2361 13:08:48.838538 [DutyScan_Calibration_Flow] k_type=1
2362 13:08:48.854249
2363 13:08:48.854439 ==DQS 0 ==
2364 13:08:48.857718 Final DQS duty delay cell = 0
2365 13:08:48.861096 [0] MAX Duty = 5156%(X100), DQS PI = 18
2366 13:08:48.865090 [0] MIN Duty = 5093%(X100), DQS PI = 0
2367 13:08:48.865501 [0] AVG Duty = 5124%(X100)
2368 13:08:48.868089
2369 13:08:48.868477 ==DQS 1 ==
2370 13:08:48.871332 Final DQS duty delay cell = 0
2371 13:08:48.874792 [0] MAX Duty = 5125%(X100), DQS PI = 52
2372 13:08:48.878038 [0] MIN Duty = 5000%(X100), DQS PI = 0
2373 13:08:48.878534 [0] AVG Duty = 5062%(X100)
2374 13:08:48.881194
2375 13:08:48.884752 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2376 13:08:48.885261
2377 13:08:48.887998 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2378 13:08:48.890997 [DutyScan_Calibration_Flow] ====Done====
2379 13:08:48.891474
2380 13:08:48.894385 [DutyScan_Calibration_Flow] k_type=3
2381 13:08:48.911250
2382 13:08:48.911594 ==DQM 0 ==
2383 13:08:48.914500 Final DQM duty delay cell = 0
2384 13:08:48.917864 [0] MAX Duty = 5094%(X100), DQS PI = 20
2385 13:08:48.920914 [0] MIN Duty = 4844%(X100), DQS PI = 44
2386 13:08:48.924224 [0] AVG Duty = 4969%(X100)
2387 13:08:48.924501
2388 13:08:48.924715 ==DQM 1 ==
2389 13:08:48.927847 Final DQM duty delay cell = 0
2390 13:08:48.930626 [0] MAX Duty = 4969%(X100), DQS PI = 2
2391 13:08:48.934369 [0] MIN Duty = 4875%(X100), DQS PI = 18
2392 13:08:48.934736 [0] AVG Duty = 4922%(X100)
2393 13:08:48.937364
2394 13:08:48.940749 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2395 13:08:48.941132
2396 13:08:48.944127 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2397 13:08:48.948073 [DutyScan_Calibration_Flow] ====Done====
2398 13:08:48.948456
2399 13:08:48.951011 [DutyScan_Calibration_Flow] k_type=2
2400 13:08:48.967489
2401 13:08:48.967954 ==DQ 0 ==
2402 13:08:48.970653 Final DQ duty delay cell = 0
2403 13:08:48.973986 [0] MAX Duty = 5125%(X100), DQS PI = 18
2404 13:08:48.977038 [0] MIN Duty = 4969%(X100), DQS PI = 58
2405 13:08:48.977113 [0] AVG Duty = 5047%(X100)
2406 13:08:48.980762
2407 13:08:48.980837 ==DQ 1 ==
2408 13:08:48.983580 Final DQ duty delay cell = 0
2409 13:08:48.987101 [0] MAX Duty = 5125%(X100), DQS PI = 4
2410 13:08:48.990640 [0] MIN Duty = 4938%(X100), DQS PI = 16
2411 13:08:48.990715 [0] AVG Duty = 5031%(X100)
2412 13:08:48.990774
2413 13:08:48.993601 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2414 13:08:48.997068
2415 13:08:49.000067 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2416 13:08:49.003525 [DutyScan_Calibration_Flow] ====Done====
2417 13:08:49.003600 ==
2418 13:08:49.006719 Dram Type= 6, Freq= 0, CH_1, rank 0
2419 13:08:49.010390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2420 13:08:49.010476 ==
2421 13:08:49.013437 [Duty_Offset_Calibration]
2422 13:08:49.013503 B0:0 B1:-1 CA:3
2423 13:08:49.013559
2424 13:08:49.016987 [DutyScan_Calibration_Flow] k_type=0
2425 13:08:49.026944
2426 13:08:49.027020 ==CLK 0==
2427 13:08:49.030700 Final CLK duty delay cell = 0
2428 13:08:49.033602 [0] MAX Duty = 5156%(X100), DQS PI = 0
2429 13:08:49.036844 [0] MIN Duty = 5000%(X100), DQS PI = 52
2430 13:08:49.036919 [0] AVG Duty = 5078%(X100)
2431 13:08:49.040365
2432 13:08:49.043838 CH1 CLK Duty spec in!! Max-Min= 156%
2433 13:08:49.046762 [DutyScan_Calibration_Flow] ====Done====
2434 13:08:49.046837
2435 13:08:49.050337 [DutyScan_Calibration_Flow] k_type=1
2436 13:08:49.066096
2437 13:08:49.066195 ==DQS 0 ==
2438 13:08:49.069452 Final DQS duty delay cell = 0
2439 13:08:49.073291 [0] MAX Duty = 5156%(X100), DQS PI = 18
2440 13:08:49.076422 [0] MIN Duty = 4907%(X100), DQS PI = 38
2441 13:08:49.079468 [0] AVG Duty = 5031%(X100)
2442 13:08:49.079545
2443 13:08:49.079604 ==DQS 1 ==
2444 13:08:49.083010 Final DQS duty delay cell = 0
2445 13:08:49.086303 [0] MAX Duty = 5156%(X100), DQS PI = 8
2446 13:08:49.089496 [0] MIN Duty = 5031%(X100), DQS PI = 22
2447 13:08:49.092720 [0] AVG Duty = 5093%(X100)
2448 13:08:49.092796
2449 13:08:49.096429 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2450 13:08:49.096505
2451 13:08:49.099365 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2452 13:08:49.102923 [DutyScan_Calibration_Flow] ====Done====
2453 13:08:49.103055
2454 13:08:49.106039 [DutyScan_Calibration_Flow] k_type=3
2455 13:08:49.122754
2456 13:08:49.122863 ==DQM 0 ==
2457 13:08:49.126422 Final DQM duty delay cell = 0
2458 13:08:49.129639 [0] MAX Duty = 5031%(X100), DQS PI = 28
2459 13:08:49.132949 [0] MIN Duty = 4813%(X100), DQS PI = 38
2460 13:08:49.136301 [0] AVG Duty = 4922%(X100)
2461 13:08:49.136689
2462 13:08:49.136991 ==DQM 1 ==
2463 13:08:49.140021 Final DQM duty delay cell = 0
2464 13:08:49.144421 [0] MAX Duty = 5000%(X100), DQS PI = 34
2465 13:08:49.146321 [0] MIN Duty = 4813%(X100), DQS PI = 0
2466 13:08:49.149733 [0] AVG Duty = 4906%(X100)
2467 13:08:49.150119
2468 13:08:49.153197 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2469 13:08:49.153626
2470 13:08:49.156200 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2471 13:08:49.159592 [DutyScan_Calibration_Flow] ====Done====
2472 13:08:49.159980
2473 13:08:49.162897 [DutyScan_Calibration_Flow] k_type=2
2474 13:08:49.179804
2475 13:08:49.180216 ==DQ 0 ==
2476 13:08:49.182868 Final DQ duty delay cell = -4
2477 13:08:49.186163 [-4] MAX Duty = 5000%(X100), DQS PI = 14
2478 13:08:49.189639 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2479 13:08:49.192932 [-4] AVG Duty = 4922%(X100)
2480 13:08:49.193379
2481 13:08:49.193689 ==DQ 1 ==
2482 13:08:49.196087 Final DQ duty delay cell = 4
2483 13:08:49.199551 [4] MAX Duty = 5156%(X100), DQS PI = 10
2484 13:08:49.203034 [4] MIN Duty = 5031%(X100), DQS PI = 62
2485 13:08:49.206310 [4] AVG Duty = 5093%(X100)
2486 13:08:49.206699
2487 13:08:49.209400 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2488 13:08:49.209793
2489 13:08:49.212977 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2490 13:08:49.215910 [DutyScan_Calibration_Flow] ====Done====
2491 13:08:49.219440 nWR fixed to 30
2492 13:08:49.222896 [ModeRegInit_LP4] CH0 RK0
2493 13:08:49.223292 [ModeRegInit_LP4] CH0 RK1
2494 13:08:49.226171 [ModeRegInit_LP4] CH1 RK0
2495 13:08:49.229424 [ModeRegInit_LP4] CH1 RK1
2496 13:08:49.229827 match AC timing 7
2497 13:08:49.236024 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2498 13:08:49.239144 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2499 13:08:49.242812 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2500 13:08:49.249476 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2501 13:08:49.252784 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2502 13:08:49.253211 ==
2503 13:08:49.255928 Dram Type= 6, Freq= 0, CH_0, rank 0
2504 13:08:49.259308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2505 13:08:49.259700 ==
2506 13:08:49.265665 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2507 13:08:49.272477 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2508 13:08:49.280240 [CA 0] Center 39 (9~70) winsize 62
2509 13:08:49.283608 [CA 1] Center 38 (8~69) winsize 62
2510 13:08:49.286778 [CA 2] Center 35 (5~66) winsize 62
2511 13:08:49.289767 [CA 3] Center 35 (5~66) winsize 62
2512 13:08:49.293621 [CA 4] Center 33 (3~64) winsize 62
2513 13:08:49.296906 [CA 5] Center 33 (3~63) winsize 61
2514 13:08:49.297326
2515 13:08:49.300441 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2516 13:08:49.300907
2517 13:08:49.303208 [CATrainingPosCal] consider 1 rank data
2518 13:08:49.306871 u2DelayCellTimex100 = 270/100 ps
2519 13:08:49.310208 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2520 13:08:49.316827 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2521 13:08:49.320039 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2522 13:08:49.323183 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2523 13:08:49.326514 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2524 13:08:49.329992 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2525 13:08:49.330385
2526 13:08:49.332877 CA PerBit enable=1, Macro0, CA PI delay=33
2527 13:08:49.333341
2528 13:08:49.336365 [CBTSetCACLKResult] CA Dly = 33
2529 13:08:49.336848 CS Dly: 7 (0~38)
2530 13:08:49.340024 ==
2531 13:08:49.340416 Dram Type= 6, Freq= 0, CH_0, rank 1
2532 13:08:49.346864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 13:08:49.347327 ==
2534 13:08:49.349529 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2535 13:08:49.356682 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2536 13:08:49.366168 [CA 0] Center 39 (9~70) winsize 62
2537 13:08:49.369735 [CA 1] Center 39 (9~70) winsize 62
2538 13:08:49.372475 [CA 2] Center 35 (5~66) winsize 62
2539 13:08:49.376082 [CA 3] Center 35 (5~66) winsize 62
2540 13:08:49.379475 [CA 4] Center 34 (4~65) winsize 62
2541 13:08:49.382942 [CA 5] Center 33 (3~64) winsize 62
2542 13:08:49.383449
2543 13:08:49.385805 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2544 13:08:49.386232
2545 13:08:49.389083 [CATrainingPosCal] consider 2 rank data
2546 13:08:49.392381 u2DelayCellTimex100 = 270/100 ps
2547 13:08:49.395715 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2548 13:08:49.402140 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2549 13:08:49.405618 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2550 13:08:49.408982 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2551 13:08:49.411995 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2552 13:08:49.415139 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2553 13:08:49.415566
2554 13:08:49.418566 CA PerBit enable=1, Macro0, CA PI delay=33
2555 13:08:49.418952
2556 13:08:49.421790 [CBTSetCACLKResult] CA Dly = 33
2557 13:08:49.425288 CS Dly: 8 (0~41)
2558 13:08:49.425673
2559 13:08:49.428351 ----->DramcWriteLeveling(PI) begin...
2560 13:08:49.428741 ==
2561 13:08:49.432147 Dram Type= 6, Freq= 0, CH_0, rank 0
2562 13:08:49.435694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2563 13:08:49.436081 ==
2564 13:08:49.438776 Write leveling (Byte 0): 30 => 30
2565 13:08:49.442258 Write leveling (Byte 1): 26 => 26
2566 13:08:49.445239 DramcWriteLeveling(PI) end<-----
2567 13:08:49.445624
2568 13:08:49.445919 ==
2569 13:08:49.448581 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 13:08:49.452353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 13:08:49.452825 ==
2572 13:08:49.454974 [Gating] SW mode calibration
2573 13:08:49.462023 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2574 13:08:49.468728 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2575 13:08:49.471975 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2576 13:08:49.475434 0 15 4 | B1->B0 | 3130 3434 | 1 1 | (0 0) (1 1)
2577 13:08:49.482276 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2578 13:08:49.485176 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2579 13:08:49.488733 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 13:08:49.495524 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 13:08:49.498105 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2582 13:08:49.501917 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2583 13:08:49.504998 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
2584 13:08:49.511403 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 13:08:49.514671 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2586 13:08:49.518052 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 13:08:49.524937 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 13:08:49.528428 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 13:08:49.531249 1 0 24 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
2590 13:08:49.538569 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2591 13:08:49.541778 1 1 0 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
2592 13:08:49.545120 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2593 13:08:49.552052 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 13:08:49.554979 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 13:08:49.557798 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 13:08:49.564938 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 13:08:49.567926 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2598 13:08:49.571437 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2599 13:08:49.578030 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2600 13:08:49.581522 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 13:08:49.584762 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 13:08:49.591255 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 13:08:49.594500 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 13:08:49.597905 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 13:08:49.604618 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 13:08:49.608286 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 13:08:49.611073 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 13:08:49.617849 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 13:08:49.621910 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 13:08:49.624696 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 13:08:49.631432 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 13:08:49.634401 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 13:08:49.637855 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2614 13:08:49.644690 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2615 13:08:49.647964 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2616 13:08:49.651759 Total UI for P1: 0, mck2ui 16
2617 13:08:49.654509 best dqsien dly found for B0: ( 1, 3, 26)
2618 13:08:49.657965 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 13:08:49.661280 Total UI for P1: 0, mck2ui 16
2620 13:08:49.664735 best dqsien dly found for B1: ( 1, 4, 0)
2621 13:08:49.667599 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2622 13:08:49.671306 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2623 13:08:49.671717
2624 13:08:49.674348 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2625 13:08:49.680830 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2626 13:08:49.681269 [Gating] SW calibration Done
2627 13:08:49.681619 ==
2628 13:08:49.684154 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 13:08:49.691122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 13:08:49.691515 ==
2631 13:08:49.691820 RX Vref Scan: 0
2632 13:08:49.692094
2633 13:08:49.694066 RX Vref 0 -> 0, step: 1
2634 13:08:49.694455
2635 13:08:49.697703 RX Delay -40 -> 252, step: 8
2636 13:08:49.701128 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2637 13:08:49.704548 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2638 13:08:49.708071 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2639 13:08:49.714498 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2640 13:08:49.717743 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2641 13:08:49.721074 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2642 13:08:49.724147 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2643 13:08:49.727270 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2644 13:08:49.730970 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2645 13:08:49.737679 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2646 13:08:49.740627 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2647 13:08:49.743671 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2648 13:08:49.747508 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
2649 13:08:49.753934 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2650 13:08:49.757403 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2651 13:08:49.760416 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2652 13:08:49.760890 ==
2653 13:08:49.764231 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 13:08:49.767086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 13:08:49.767519 ==
2656 13:08:49.770708 DQS Delay:
2657 13:08:49.771090 DQS0 = 0, DQS1 = 0
2658 13:08:49.771387 DQM Delay:
2659 13:08:49.774720 DQM0 = 119, DQM1 = 106
2660 13:08:49.775180 DQ Delay:
2661 13:08:49.777696 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2662 13:08:49.780898 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2663 13:08:49.783812 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2664 13:08:49.791068 DQ12 =115, DQ13 =111, DQ14 =115, DQ15 =111
2665 13:08:49.791516
2666 13:08:49.791819
2667 13:08:49.792094 ==
2668 13:08:49.794211 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 13:08:49.797041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 13:08:49.797467 ==
2671 13:08:49.797770
2672 13:08:49.798047
2673 13:08:49.800837 TX Vref Scan disable
2674 13:08:49.801343 == TX Byte 0 ==
2675 13:08:49.807335 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2676 13:08:49.810966 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2677 13:08:49.811431 == TX Byte 1 ==
2678 13:08:49.817379 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2679 13:08:49.820859 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2680 13:08:49.821359 ==
2681 13:08:49.823377 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 13:08:49.826798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 13:08:49.827197 ==
2684 13:08:49.840152 TX Vref=22, minBit 5, minWin=24, winSum=406
2685 13:08:49.843856 TX Vref=24, minBit 1, minWin=25, winSum=412
2686 13:08:49.846936 TX Vref=26, minBit 1, minWin=25, winSum=422
2687 13:08:49.850289 TX Vref=28, minBit 3, minWin=26, winSum=425
2688 13:08:49.853718 TX Vref=30, minBit 4, minWin=26, winSum=429
2689 13:08:49.860724 TX Vref=32, minBit 0, minWin=26, winSum=424
2690 13:08:49.863922 [TxChooseVref] Worse bit 4, Min win 26, Win sum 429, Final Vref 30
2691 13:08:49.864388
2692 13:08:49.866979 Final TX Range 1 Vref 30
2693 13:08:49.867439
2694 13:08:49.867761 ==
2695 13:08:49.870426 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 13:08:49.873591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 13:08:49.873977 ==
2698 13:08:49.876799
2699 13:08:49.877198
2700 13:08:49.877498 TX Vref Scan disable
2701 13:08:49.879869 == TX Byte 0 ==
2702 13:08:49.883443 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2703 13:08:49.890106 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2704 13:08:49.890569 == TX Byte 1 ==
2705 13:08:49.893291 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2706 13:08:49.900327 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2707 13:08:49.900804
2708 13:08:49.901109 [DATLAT]
2709 13:08:49.901442 Freq=1200, CH0 RK0
2710 13:08:49.901716
2711 13:08:49.902995 DATLAT Default: 0xd
2712 13:08:49.906561 0, 0xFFFF, sum = 0
2713 13:08:49.906958 1, 0xFFFF, sum = 0
2714 13:08:49.909937 2, 0xFFFF, sum = 0
2715 13:08:49.910334 3, 0xFFFF, sum = 0
2716 13:08:49.912672 4, 0xFFFF, sum = 0
2717 13:08:49.912748 5, 0xFFFF, sum = 0
2718 13:08:49.916162 6, 0xFFFF, sum = 0
2719 13:08:49.916240 7, 0xFFFF, sum = 0
2720 13:08:49.919714 8, 0xFFFF, sum = 0
2721 13:08:49.919796 9, 0xFFFF, sum = 0
2722 13:08:49.922647 10, 0xFFFF, sum = 0
2723 13:08:49.922729 11, 0xFFFF, sum = 0
2724 13:08:49.926188 12, 0x0, sum = 1
2725 13:08:49.926312 13, 0x0, sum = 2
2726 13:08:49.929696 14, 0x0, sum = 3
2727 13:08:49.929791 15, 0x0, sum = 4
2728 13:08:49.932729 best_step = 13
2729 13:08:49.932823
2730 13:08:49.932895 ==
2731 13:08:49.936052 Dram Type= 6, Freq= 0, CH_0, rank 0
2732 13:08:49.939603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2733 13:08:49.940193 ==
2734 13:08:49.940608 RX Vref Scan: 1
2735 13:08:49.943219
2736 13:08:49.943682 Set Vref Range= 32 -> 127
2737 13:08:49.943984
2738 13:08:49.946288 RX Vref 32 -> 127, step: 1
2739 13:08:49.946749
2740 13:08:49.949793 RX Delay -21 -> 252, step: 4
2741 13:08:49.950178
2742 13:08:49.953015 Set Vref, RX VrefLevel [Byte0]: 32
2743 13:08:49.956468 [Byte1]: 32
2744 13:08:49.956866
2745 13:08:49.959820 Set Vref, RX VrefLevel [Byte0]: 33
2746 13:08:49.962820 [Byte1]: 33
2747 13:08:49.967149
2748 13:08:49.967610 Set Vref, RX VrefLevel [Byte0]: 34
2749 13:08:49.969866 [Byte1]: 34
2750 13:08:49.974670
2751 13:08:49.975135 Set Vref, RX VrefLevel [Byte0]: 35
2752 13:08:49.977691 [Byte1]: 35
2753 13:08:49.982419
2754 13:08:49.982808 Set Vref, RX VrefLevel [Byte0]: 36
2755 13:08:49.985940 [Byte1]: 36
2756 13:08:49.990530
2757 13:08:49.991126 Set Vref, RX VrefLevel [Byte0]: 37
2758 13:08:49.993286 [Byte1]: 37
2759 13:08:49.998952
2760 13:08:49.999340 Set Vref, RX VrefLevel [Byte0]: 38
2761 13:08:50.001608 [Byte1]: 38
2762 13:08:50.006396
2763 13:08:50.006786 Set Vref, RX VrefLevel [Byte0]: 39
2764 13:08:50.009753 [Byte1]: 39
2765 13:08:50.014229
2766 13:08:50.014615 Set Vref, RX VrefLevel [Byte0]: 40
2767 13:08:50.017233 [Byte1]: 40
2768 13:08:50.022171
2769 13:08:50.022561 Set Vref, RX VrefLevel [Byte0]: 41
2770 13:08:50.025004 [Byte1]: 41
2771 13:08:50.029716
2772 13:08:50.030099 Set Vref, RX VrefLevel [Byte0]: 42
2773 13:08:50.033292 [Byte1]: 42
2774 13:08:50.038138
2775 13:08:50.038603 Set Vref, RX VrefLevel [Byte0]: 43
2776 13:08:50.041054 [Byte1]: 43
2777 13:08:50.046144
2778 13:08:50.046610 Set Vref, RX VrefLevel [Byte0]: 44
2779 13:08:50.049633 [Byte1]: 44
2780 13:08:50.053806
2781 13:08:50.054295 Set Vref, RX VrefLevel [Byte0]: 45
2782 13:08:50.056705 [Byte1]: 45
2783 13:08:50.061668
2784 13:08:50.062167 Set Vref, RX VrefLevel [Byte0]: 46
2785 13:08:50.064935 [Byte1]: 46
2786 13:08:50.069863
2787 13:08:50.070346 Set Vref, RX VrefLevel [Byte0]: 47
2788 13:08:50.073327 [Byte1]: 47
2789 13:08:50.077326
2790 13:08:50.077401 Set Vref, RX VrefLevel [Byte0]: 48
2791 13:08:50.080539 [Byte1]: 48
2792 13:08:50.084776
2793 13:08:50.084852 Set Vref, RX VrefLevel [Byte0]: 49
2794 13:08:50.088232 [Byte1]: 49
2795 13:08:50.093082
2796 13:08:50.093248 Set Vref, RX VrefLevel [Byte0]: 50
2797 13:08:50.096390 [Byte1]: 50
2798 13:08:50.101516
2799 13:08:50.101989 Set Vref, RX VrefLevel [Byte0]: 51
2800 13:08:50.104202 [Byte1]: 51
2801 13:08:50.109220
2802 13:08:50.109694 Set Vref, RX VrefLevel [Byte0]: 52
2803 13:08:50.112796 [Byte1]: 52
2804 13:08:50.117383
2805 13:08:50.117860 Set Vref, RX VrefLevel [Byte0]: 53
2806 13:08:50.120660 [Byte1]: 53
2807 13:08:50.125084
2808 13:08:50.125516 Set Vref, RX VrefLevel [Byte0]: 54
2809 13:08:50.128016 [Byte1]: 54
2810 13:08:50.132774
2811 13:08:50.133187 Set Vref, RX VrefLevel [Byte0]: 55
2812 13:08:50.136711 [Byte1]: 55
2813 13:08:50.141204
2814 13:08:50.141592 Set Vref, RX VrefLevel [Byte0]: 56
2815 13:08:50.144416 [Byte1]: 56
2816 13:08:50.148991
2817 13:08:50.149549 Set Vref, RX VrefLevel [Byte0]: 57
2818 13:08:50.152241 [Byte1]: 57
2819 13:08:50.156828
2820 13:08:50.157235 Set Vref, RX VrefLevel [Byte0]: 58
2821 13:08:50.159734 [Byte1]: 58
2822 13:08:50.164749
2823 13:08:50.165133 Set Vref, RX VrefLevel [Byte0]: 59
2824 13:08:50.168135 [Byte1]: 59
2825 13:08:50.172706
2826 13:08:50.173236 Set Vref, RX VrefLevel [Byte0]: 60
2827 13:08:50.176034 [Byte1]: 60
2828 13:08:50.180525
2829 13:08:50.180917 Set Vref, RX VrefLevel [Byte0]: 61
2830 13:08:50.183974 [Byte1]: 61
2831 13:08:50.188495
2832 13:08:50.188895 Set Vref, RX VrefLevel [Byte0]: 62
2833 13:08:50.192012 [Byte1]: 62
2834 13:08:50.196589
2835 13:08:50.197051 Set Vref, RX VrefLevel [Byte0]: 63
2836 13:08:50.199816 [Byte1]: 63
2837 13:08:50.204377
2838 13:08:50.204845 Set Vref, RX VrefLevel [Byte0]: 64
2839 13:08:50.208547 [Byte1]: 64
2840 13:08:50.212220
2841 13:08:50.212604 Set Vref, RX VrefLevel [Byte0]: 65
2842 13:08:50.215566 [Byte1]: 65
2843 13:08:50.220363
2844 13:08:50.220827 Set Vref, RX VrefLevel [Byte0]: 66
2845 13:08:50.223640 [Byte1]: 66
2846 13:08:50.228321
2847 13:08:50.228759 Set Vref, RX VrefLevel [Byte0]: 67
2848 13:08:50.231530 [Byte1]: 67
2849 13:08:50.236147
2850 13:08:50.237277 Set Vref, RX VrefLevel [Byte0]: 68
2851 13:08:50.239258 [Byte1]: 68
2852 13:08:50.244115
2853 13:08:50.244503 Set Vref, RX VrefLevel [Byte0]: 69
2854 13:08:50.247047 [Byte1]: 69
2855 13:08:50.251807
2856 13:08:50.252194 Final RX Vref Byte 0 = 55 to rank0
2857 13:08:50.255350 Final RX Vref Byte 1 = 50 to rank0
2858 13:08:50.258389 Final RX Vref Byte 0 = 55 to rank1
2859 13:08:50.262000 Final RX Vref Byte 1 = 50 to rank1==
2860 13:08:50.265197 Dram Type= 6, Freq= 0, CH_0, rank 0
2861 13:08:50.272265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2862 13:08:50.272761 ==
2863 13:08:50.273291 DQS Delay:
2864 13:08:50.273596 DQS0 = 0, DQS1 = 0
2865 13:08:50.274930 DQM Delay:
2866 13:08:50.275322 DQM0 = 119, DQM1 = 105
2867 13:08:50.278192 DQ Delay:
2868 13:08:50.281228 DQ0 =120, DQ1 =118, DQ2 =116, DQ3 =116
2869 13:08:50.285410 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =124
2870 13:08:50.288576 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =100
2871 13:08:50.291440 DQ12 =114, DQ13 =110, DQ14 =116, DQ15 =114
2872 13:08:50.291832
2873 13:08:50.292134
2874 13:08:50.298359 [DQSOSCAuto] RK0, (LSB)MR18= 0x501, (MSB)MR19= 0x404, tDQSOscB0 = 409 ps tDQSOscB1 = 408 ps
2875 13:08:50.301855 CH0 RK0: MR19=404, MR18=501
2876 13:08:50.307822 CH0_RK0: MR19=0x404, MR18=0x501, DQSOSC=408, MR23=63, INC=39, DEC=26
2877 13:08:50.308220
2878 13:08:50.311544 ----->DramcWriteLeveling(PI) begin...
2879 13:08:50.312021 ==
2880 13:08:50.315587 Dram Type= 6, Freq= 0, CH_0, rank 1
2881 13:08:50.318382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2882 13:08:50.321402 ==
2883 13:08:50.324850 Write leveling (Byte 0): 31 => 31
2884 13:08:50.325264 Write leveling (Byte 1): 27 => 27
2885 13:08:50.327643 DramcWriteLeveling(PI) end<-----
2886 13:08:50.328029
2887 13:08:50.328329 ==
2888 13:08:50.331289 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 13:08:50.337723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 13:08:50.338114 ==
2891 13:08:50.341554 [Gating] SW mode calibration
2892 13:08:50.348258 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2893 13:08:50.351195 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2894 13:08:50.358426 0 15 0 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
2895 13:08:50.361194 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2896 13:08:50.365043 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 13:08:50.371623 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 13:08:50.374483 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 13:08:50.378167 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2900 13:08:50.381509 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2901 13:08:50.388117 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
2902 13:08:50.391206 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2903 13:08:50.394308 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 13:08:50.401101 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 13:08:50.404604 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 13:08:50.407382 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 13:08:50.414311 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 13:08:50.417877 1 0 24 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
2909 13:08:50.420627 1 0 28 | B1->B0 | 2828 4444 | 1 1 | (1 1) (0 0)
2910 13:08:50.427529 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 13:08:50.430731 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 13:08:50.434034 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 13:08:50.440723 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 13:08:50.444250 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 13:08:50.447541 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 13:08:50.454439 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2917 13:08:50.457498 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2918 13:08:50.460667 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 13:08:50.467714 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 13:08:50.470939 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 13:08:50.474547 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 13:08:50.480996 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 13:08:50.484325 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 13:08:50.487177 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 13:08:50.494009 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 13:08:50.497484 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 13:08:50.501292 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 13:08:50.507463 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 13:08:50.511102 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 13:08:50.514476 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 13:08:50.517456 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2932 13:08:50.524398 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2933 13:08:50.527420 Total UI for P1: 0, mck2ui 16
2934 13:08:50.530859 best dqsien dly found for B0: ( 1, 3, 20)
2935 13:08:50.534137 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2936 13:08:50.537511 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 13:08:50.540624 Total UI for P1: 0, mck2ui 16
2938 13:08:50.543892 best dqsien dly found for B1: ( 1, 3, 30)
2939 13:08:50.547721 best DQS0 dly(MCK, UI, PI) = (1, 3, 20)
2940 13:08:50.550932 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2941 13:08:50.553874
2942 13:08:50.557208 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 20)
2943 13:08:50.560451 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2944 13:08:50.564080 [Gating] SW calibration Done
2945 13:08:50.564506 ==
2946 13:08:50.566857 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 13:08:50.570479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 13:08:50.570894 ==
2949 13:08:50.571213 RX Vref Scan: 0
2950 13:08:50.573632
2951 13:08:50.574207 RX Vref 0 -> 0, step: 1
2952 13:08:50.574563
2953 13:08:50.576875 RX Delay -40 -> 252, step: 8
2954 13:08:50.580408 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2955 13:08:50.583459 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2956 13:08:50.590529 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2957 13:08:50.593430 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2958 13:08:50.596706 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2959 13:08:50.600139 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2960 13:08:50.603887 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2961 13:08:50.610080 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2962 13:08:50.613920 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2963 13:08:50.617029 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2964 13:08:50.620594 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2965 13:08:50.623971 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2966 13:08:50.629777 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2967 13:08:50.633243 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2968 13:08:50.636876 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2969 13:08:50.640203 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2970 13:08:50.640596 ==
2971 13:08:50.643545 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 13:08:50.649909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 13:08:50.650301 ==
2974 13:08:50.650605 DQS Delay:
2975 13:08:50.653177 DQS0 = 0, DQS1 = 0
2976 13:08:50.653567 DQM Delay:
2977 13:08:50.653869 DQM0 = 118, DQM1 = 106
2978 13:08:50.656728 DQ Delay:
2979 13:08:50.659971 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2980 13:08:50.663592 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2981 13:08:50.666549 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2982 13:08:50.670067 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2983 13:08:50.670452
2984 13:08:50.670749
2985 13:08:50.671060 ==
2986 13:08:50.673499 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 13:08:50.676435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 13:08:50.676823 ==
2989 13:08:50.679763
2990 13:08:50.680172
2991 13:08:50.680480 TX Vref Scan disable
2992 13:08:50.683166 == TX Byte 0 ==
2993 13:08:50.686639 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2994 13:08:50.690089 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2995 13:08:50.693182 == TX Byte 1 ==
2996 13:08:50.696487 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2997 13:08:50.700126 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2998 13:08:50.700614 ==
2999 13:08:50.703600 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 13:08:50.709821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 13:08:50.710291 ==
3002 13:08:50.721004 TX Vref=22, minBit 4, minWin=25, winSum=415
3003 13:08:50.724550 TX Vref=24, minBit 4, minWin=25, winSum=416
3004 13:08:50.727732 TX Vref=26, minBit 1, minWin=25, winSum=421
3005 13:08:50.730525 TX Vref=28, minBit 3, minWin=25, winSum=423
3006 13:08:50.733988 TX Vref=30, minBit 0, minWin=26, winSum=422
3007 13:08:50.740635 TX Vref=32, minBit 12, minWin=25, winSum=420
3008 13:08:50.743697 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 30
3009 13:08:50.744093
3010 13:08:50.747159 Final TX Range 1 Vref 30
3011 13:08:50.747551
3012 13:08:50.747858 ==
3013 13:08:50.750398 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 13:08:50.753507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 13:08:50.757126 ==
3016 13:08:50.757660
3017 13:08:50.757993
3018 13:08:50.758270 TX Vref Scan disable
3019 13:08:50.760456 == TX Byte 0 ==
3020 13:08:50.763682 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3021 13:08:50.767507 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3022 13:08:50.770472 == TX Byte 1 ==
3023 13:08:50.773892 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3024 13:08:50.777600 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3025 13:08:50.780697
3026 13:08:50.781208 [DATLAT]
3027 13:08:50.781526 Freq=1200, CH0 RK1
3028 13:08:50.781810
3029 13:08:50.783924 DATLAT Default: 0xd
3030 13:08:50.784306 0, 0xFFFF, sum = 0
3031 13:08:50.786859 1, 0xFFFF, sum = 0
3032 13:08:50.787251 2, 0xFFFF, sum = 0
3033 13:08:50.790580 3, 0xFFFF, sum = 0
3034 13:08:50.793808 4, 0xFFFF, sum = 0
3035 13:08:50.794273 5, 0xFFFF, sum = 0
3036 13:08:50.797086 6, 0xFFFF, sum = 0
3037 13:08:50.797597 7, 0xFFFF, sum = 0
3038 13:08:50.800745 8, 0xFFFF, sum = 0
3039 13:08:50.801175 9, 0xFFFF, sum = 0
3040 13:08:50.803718 10, 0xFFFF, sum = 0
3041 13:08:50.804190 11, 0xFFFF, sum = 0
3042 13:08:50.807026 12, 0x0, sum = 1
3043 13:08:50.807416 13, 0x0, sum = 2
3044 13:08:50.810565 14, 0x0, sum = 3
3045 13:08:50.811040 15, 0x0, sum = 4
3046 13:08:50.813709 best_step = 13
3047 13:08:50.814230
3048 13:08:50.814602 ==
3049 13:08:50.817252 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 13:08:50.819991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 13:08:50.820473 ==
3052 13:08:50.820965 RX Vref Scan: 0
3053 13:08:50.821467
3054 13:08:50.823715 RX Vref 0 -> 0, step: 1
3055 13:08:50.824176
3056 13:08:50.826577 RX Delay -21 -> 252, step: 4
3057 13:08:50.830171 iDelay=195, Bit 0, Center 116 (55 ~ 178) 124
3058 13:08:50.836693 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
3059 13:08:50.840439 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
3060 13:08:50.843360 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3061 13:08:50.847180 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3062 13:08:50.850019 iDelay=195, Bit 5, Center 110 (47 ~ 174) 128
3063 13:08:50.856802 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3064 13:08:50.860029 iDelay=195, Bit 7, Center 124 (59 ~ 190) 132
3065 13:08:50.863146 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3066 13:08:50.866549 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3067 13:08:50.870239 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3068 13:08:50.877225 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3069 13:08:50.880122 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3070 13:08:50.883804 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3071 13:08:50.886995 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3072 13:08:50.889941 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3073 13:08:50.893925 ==
3074 13:08:50.894392 Dram Type= 6, Freq= 0, CH_0, rank 1
3075 13:08:50.900055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 13:08:50.900616 ==
3077 13:08:50.901122 DQS Delay:
3078 13:08:50.903688 DQS0 = 0, DQS1 = 0
3079 13:08:50.904185 DQM Delay:
3080 13:08:50.906755 DQM0 = 118, DQM1 = 107
3081 13:08:50.907185 DQ Delay:
3082 13:08:50.910163 DQ0 =116, DQ1 =118, DQ2 =114, DQ3 =114
3083 13:08:50.913509 DQ4 =120, DQ5 =110, DQ6 =128, DQ7 =124
3084 13:08:50.916716 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =98
3085 13:08:50.920060 DQ12 =112, DQ13 =112, DQ14 =120, DQ15 =116
3086 13:08:50.920445
3087 13:08:50.920741
3088 13:08:50.929975 [DQSOSCAuto] RK1, (LSB)MR18= 0x200, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3089 13:08:50.930366 CH0 RK1: MR19=404, MR18=200
3090 13:08:50.936563 CH0_RK1: MR19=0x404, MR18=0x200, DQSOSC=409, MR23=63, INC=39, DEC=26
3091 13:08:50.940033 [RxdqsGatingPostProcess] freq 1200
3092 13:08:50.946904 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3093 13:08:50.949695 best DQS0 dly(2T, 0.5T) = (0, 11)
3094 13:08:50.952926 best DQS1 dly(2T, 0.5T) = (0, 12)
3095 13:08:50.956488 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3096 13:08:50.959725 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3097 13:08:50.963087 best DQS0 dly(2T, 0.5T) = (0, 11)
3098 13:08:50.963518 best DQS1 dly(2T, 0.5T) = (0, 11)
3099 13:08:50.966724 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3100 13:08:50.969833 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3101 13:08:50.972991 Pre-setting of DQS Precalculation
3102 13:08:50.979422 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3103 13:08:50.979850 ==
3104 13:08:50.983050 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 13:08:50.986306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 13:08:50.986694 ==
3107 13:08:50.992648 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3108 13:08:50.999140 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3109 13:08:51.006024 [CA 0] Center 38 (8~68) winsize 61
3110 13:08:51.009655 [CA 1] Center 37 (7~68) winsize 62
3111 13:08:51.013453 [CA 2] Center 35 (5~65) winsize 61
3112 13:08:51.016115 [CA 3] Center 34 (4~64) winsize 61
3113 13:08:51.019580 [CA 4] Center 34 (4~65) winsize 62
3114 13:08:51.023016 [CA 5] Center 34 (4~64) winsize 61
3115 13:08:51.023173
3116 13:08:51.025787 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3117 13:08:51.025914
3118 13:08:51.029282 [CATrainingPosCal] consider 1 rank data
3119 13:08:51.032600 u2DelayCellTimex100 = 270/100 ps
3120 13:08:51.035833 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3121 13:08:51.042641 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3122 13:08:51.046154 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3123 13:08:51.049579 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3124 13:08:51.052836 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3125 13:08:51.056345 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3126 13:08:51.056645
3127 13:08:51.059785 CA PerBit enable=1, Macro0, CA PI delay=34
3128 13:08:51.060085
3129 13:08:51.062291 [CBTSetCACLKResult] CA Dly = 34
3130 13:08:51.065831 CS Dly: 5 (0~36)
3131 13:08:51.066189 ==
3132 13:08:51.068889 Dram Type= 6, Freq= 0, CH_1, rank 1
3133 13:08:51.072102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 13:08:51.072492 ==
3135 13:08:51.079099 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3136 13:08:51.082273 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3137 13:08:51.091940 [CA 0] Center 38 (8~68) winsize 61
3138 13:08:51.095253 [CA 1] Center 38 (7~69) winsize 63
3139 13:08:51.099019 [CA 2] Center 35 (5~65) winsize 61
3140 13:08:51.102293 [CA 3] Center 33 (3~64) winsize 62
3141 13:08:51.105461 [CA 4] Center 34 (4~64) winsize 61
3142 13:08:51.108468 [CA 5] Center 33 (3~63) winsize 61
3143 13:08:51.108876
3144 13:08:51.112334 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3145 13:08:51.112802
3146 13:08:51.115424 [CATrainingPosCal] consider 2 rank data
3147 13:08:51.118922 u2DelayCellTimex100 = 270/100 ps
3148 13:08:51.125202 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3149 13:08:51.128206 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3150 13:08:51.131693 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3151 13:08:51.134464 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3152 13:08:51.138019 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3153 13:08:51.141082 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3154 13:08:51.141506
3155 13:08:51.144777 CA PerBit enable=1, Macro0, CA PI delay=33
3156 13:08:51.145206
3157 13:08:51.147928 [CBTSetCACLKResult] CA Dly = 33
3158 13:08:51.150686 CS Dly: 6 (0~39)
3159 13:08:51.151074
3160 13:08:51.154274 ----->DramcWriteLeveling(PI) begin...
3161 13:08:51.154668 ==
3162 13:08:51.157862 Dram Type= 6, Freq= 0, CH_1, rank 0
3163 13:08:51.160827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 13:08:51.161271 ==
3165 13:08:51.164208 Write leveling (Byte 0): 25 => 25
3166 13:08:51.167135 Write leveling (Byte 1): 25 => 25
3167 13:08:51.171020 DramcWriteLeveling(PI) end<-----
3168 13:08:51.171407
3169 13:08:51.171703 ==
3170 13:08:51.174329 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 13:08:51.177327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 13:08:51.177718 ==
3173 13:08:51.180968 [Gating] SW mode calibration
3174 13:08:51.187206 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3175 13:08:51.194342 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3176 13:08:51.197338 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
3177 13:08:51.204095 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 13:08:51.207208 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 13:08:51.210858 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 13:08:51.217215 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 13:08:51.221023 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 13:08:51.223717 0 15 24 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (0 1)
3183 13:08:51.230123 0 15 28 | B1->B0 | 2929 2626 | 0 0 | (1 0) (1 0)
3184 13:08:51.233098 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 13:08:51.236803 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 13:08:51.242990 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 13:08:51.246330 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 13:08:51.250007 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 13:08:51.256500 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 13:08:51.259901 1 0 24 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
3191 13:08:51.262687 1 0 28 | B1->B0 | 4242 4545 | 0 0 | (0 0) (0 0)
3192 13:08:51.269497 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 13:08:51.272981 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 13:08:51.275718 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 13:08:51.282607 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 13:08:51.285558 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 13:08:51.289175 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 13:08:51.295960 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3199 13:08:51.299304 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3200 13:08:51.302536 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 13:08:51.308971 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 13:08:51.312286 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 13:08:51.315246 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 13:08:51.321456 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 13:08:51.325220 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 13:08:51.328503 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 13:08:51.335073 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 13:08:51.338773 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 13:08:51.341559 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 13:08:51.348041 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 13:08:51.352051 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 13:08:51.354812 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 13:08:51.361347 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 13:08:51.364811 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3215 13:08:51.367972 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 13:08:51.371425 Total UI for P1: 0, mck2ui 16
3217 13:08:51.374488 best dqsien dly found for B0: ( 1, 3, 24)
3218 13:08:51.378063 Total UI for P1: 0, mck2ui 16
3219 13:08:51.381628 best dqsien dly found for B1: ( 1, 3, 24)
3220 13:08:51.385006 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3221 13:08:51.388283 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3222 13:08:51.388602
3223 13:08:51.394425 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3224 13:08:51.397800 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3225 13:08:51.400926 [Gating] SW calibration Done
3226 13:08:51.401373 ==
3227 13:08:51.404394 Dram Type= 6, Freq= 0, CH_1, rank 0
3228 13:08:51.407781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3229 13:08:51.408168 ==
3230 13:08:51.408469 RX Vref Scan: 0
3231 13:08:51.408790
3232 13:08:51.411397 RX Vref 0 -> 0, step: 1
3233 13:08:51.411802
3234 13:08:51.414098 RX Delay -40 -> 252, step: 8
3235 13:08:51.417566 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3236 13:08:51.420557 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
3237 13:08:51.426705 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3238 13:08:51.430238 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3239 13:08:51.433335 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3240 13:08:51.436865 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3241 13:08:51.440116 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3242 13:08:51.446442 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3243 13:08:51.450097 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3244 13:08:51.452923 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3245 13:08:51.456496 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3246 13:08:51.463481 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3247 13:08:51.466264 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3248 13:08:51.469788 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3249 13:08:51.473250 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3250 13:08:51.476283 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3251 13:08:51.479857 ==
3252 13:08:51.482733 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 13:08:51.486214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 13:08:51.486290 ==
3255 13:08:51.486349 DQS Delay:
3256 13:08:51.489399 DQS0 = 0, DQS1 = 0
3257 13:08:51.489474 DQM Delay:
3258 13:08:51.492397 DQM0 = 117, DQM1 = 113
3259 13:08:51.492472 DQ Delay:
3260 13:08:51.495633 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3261 13:08:51.499344 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3262 13:08:51.502469 DQ8 =103, DQ9 =103, DQ10 =111, DQ11 =107
3263 13:08:51.505813 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3264 13:08:51.505888
3265 13:08:51.505946
3266 13:08:51.508740 ==
3267 13:08:51.512079 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 13:08:51.515507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 13:08:51.515582 ==
3270 13:08:51.515641
3271 13:08:51.515694
3272 13:08:51.519009 TX Vref Scan disable
3273 13:08:51.519083 == TX Byte 0 ==
3274 13:08:51.525738 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3275 13:08:51.528721 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3276 13:08:51.528796 == TX Byte 1 ==
3277 13:08:51.532365 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3278 13:08:51.538972 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3279 13:08:51.539048 ==
3280 13:08:51.542423 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 13:08:51.545670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 13:08:51.545745 ==
3283 13:08:51.557598 TX Vref=22, minBit 9, minWin=24, winSum=409
3284 13:08:51.560644 TX Vref=24, minBit 3, minWin=25, winSum=415
3285 13:08:51.564014 TX Vref=26, minBit 9, minWin=25, winSum=419
3286 13:08:51.566973 TX Vref=28, minBit 1, minWin=26, winSum=425
3287 13:08:51.570382 TX Vref=30, minBit 3, minWin=26, winSum=429
3288 13:08:51.576950 TX Vref=32, minBit 1, minWin=26, winSum=426
3289 13:08:51.580033 [TxChooseVref] Worse bit 3, Min win 26, Win sum 429, Final Vref 30
3290 13:08:51.580103
3291 13:08:51.583411 Final TX Range 1 Vref 30
3292 13:08:51.583501
3293 13:08:51.583583 ==
3294 13:08:51.586839 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 13:08:51.593361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 13:08:51.593438 ==
3297 13:08:51.593496
3298 13:08:51.593548
3299 13:08:51.593600 TX Vref Scan disable
3300 13:08:51.597012 == TX Byte 0 ==
3301 13:08:51.600268 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3302 13:08:51.607177 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3303 13:08:51.607255 == TX Byte 1 ==
3304 13:08:51.610566 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3305 13:08:51.616601 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3306 13:08:51.616696
3307 13:08:51.616780 [DATLAT]
3308 13:08:51.616871 Freq=1200, CH1 RK0
3309 13:08:51.616952
3310 13:08:51.619891 DATLAT Default: 0xd
3311 13:08:51.623208 0, 0xFFFF, sum = 0
3312 13:08:51.623305 1, 0xFFFF, sum = 0
3313 13:08:51.626749 2, 0xFFFF, sum = 0
3314 13:08:51.626819 3, 0xFFFF, sum = 0
3315 13:08:51.630088 4, 0xFFFF, sum = 0
3316 13:08:51.630183 5, 0xFFFF, sum = 0
3317 13:08:51.633416 6, 0xFFFF, sum = 0
3318 13:08:51.633519 7, 0xFFFF, sum = 0
3319 13:08:51.636497 8, 0xFFFF, sum = 0
3320 13:08:51.636573 9, 0xFFFF, sum = 0
3321 13:08:51.640040 10, 0xFFFF, sum = 0
3322 13:08:51.640117 11, 0xFFFF, sum = 0
3323 13:08:51.643044 12, 0x0, sum = 1
3324 13:08:51.643121 13, 0x0, sum = 2
3325 13:08:51.646547 14, 0x0, sum = 3
3326 13:08:51.646623 15, 0x0, sum = 4
3327 13:08:51.649473 best_step = 13
3328 13:08:51.649548
3329 13:08:51.649605 ==
3330 13:08:51.653013 Dram Type= 6, Freq= 0, CH_1, rank 0
3331 13:08:51.656265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3332 13:08:51.656340 ==
3333 13:08:51.659636 RX Vref Scan: 1
3334 13:08:51.659711
3335 13:08:51.659769 Set Vref Range= 32 -> 127
3336 13:08:51.659822
3337 13:08:51.662848 RX Vref 32 -> 127, step: 1
3338 13:08:51.662922
3339 13:08:51.666319 RX Delay -13 -> 252, step: 4
3340 13:08:51.666394
3341 13:08:51.669643 Set Vref, RX VrefLevel [Byte0]: 32
3342 13:08:51.672956 [Byte1]: 32
3343 13:08:51.673054
3344 13:08:51.676493 Set Vref, RX VrefLevel [Byte0]: 33
3345 13:08:51.679379 [Byte1]: 33
3346 13:08:51.683523
3347 13:08:51.683598 Set Vref, RX VrefLevel [Byte0]: 34
3348 13:08:51.686891 [Byte1]: 34
3349 13:08:51.691414
3350 13:08:51.691488 Set Vref, RX VrefLevel [Byte0]: 35
3351 13:08:51.694618 [Byte1]: 35
3352 13:08:51.699278
3353 13:08:51.699352 Set Vref, RX VrefLevel [Byte0]: 36
3354 13:08:51.702643 [Byte1]: 36
3355 13:08:51.706950
3356 13:08:51.707025 Set Vref, RX VrefLevel [Byte0]: 37
3357 13:08:51.710419 [Byte1]: 37
3358 13:08:51.715181
3359 13:08:51.715256 Set Vref, RX VrefLevel [Byte0]: 38
3360 13:08:51.717990 [Byte1]: 38
3361 13:08:51.723013
3362 13:08:51.723105 Set Vref, RX VrefLevel [Byte0]: 39
3363 13:08:51.726008 [Byte1]: 39
3364 13:08:51.730695
3365 13:08:51.730785 Set Vref, RX VrefLevel [Byte0]: 40
3366 13:08:51.733934 [Byte1]: 40
3367 13:08:51.738789
3368 13:08:51.738864 Set Vref, RX VrefLevel [Byte0]: 41
3369 13:08:51.741945 [Byte1]: 41
3370 13:08:51.746300
3371 13:08:51.746376 Set Vref, RX VrefLevel [Byte0]: 42
3372 13:08:51.749812 [Byte1]: 42
3373 13:08:51.754501
3374 13:08:51.754575 Set Vref, RX VrefLevel [Byte0]: 43
3375 13:08:51.757463 [Byte1]: 43
3376 13:08:51.762370
3377 13:08:51.762444 Set Vref, RX VrefLevel [Byte0]: 44
3378 13:08:51.765820 [Byte1]: 44
3379 13:08:51.769821
3380 13:08:51.769896 Set Vref, RX VrefLevel [Byte0]: 45
3381 13:08:51.773110 [Byte1]: 45
3382 13:08:51.777883
3383 13:08:51.777958 Set Vref, RX VrefLevel [Byte0]: 46
3384 13:08:51.781694 [Byte1]: 46
3385 13:08:51.786034
3386 13:08:51.786108 Set Vref, RX VrefLevel [Byte0]: 47
3387 13:08:51.789333 [Byte1]: 47
3388 13:08:51.793685
3389 13:08:51.793759 Set Vref, RX VrefLevel [Byte0]: 48
3390 13:08:51.797236 [Byte1]: 48
3391 13:08:51.801373
3392 13:08:51.801447 Set Vref, RX VrefLevel [Byte0]: 49
3393 13:08:51.804874 [Byte1]: 49
3394 13:08:51.809421
3395 13:08:51.809496 Set Vref, RX VrefLevel [Byte0]: 50
3396 13:08:51.812910 [Byte1]: 50
3397 13:08:51.817684
3398 13:08:51.817759 Set Vref, RX VrefLevel [Byte0]: 51
3399 13:08:51.820728 [Byte1]: 51
3400 13:08:51.825025
3401 13:08:51.825100 Set Vref, RX VrefLevel [Byte0]: 52
3402 13:08:51.828672 [Byte1]: 52
3403 13:08:51.832962
3404 13:08:51.833037 Set Vref, RX VrefLevel [Byte0]: 53
3405 13:08:51.836515 [Byte1]: 53
3406 13:08:51.841011
3407 13:08:51.841086 Set Vref, RX VrefLevel [Byte0]: 54
3408 13:08:51.844275 [Byte1]: 54
3409 13:08:51.848620
3410 13:08:51.848694 Set Vref, RX VrefLevel [Byte0]: 55
3411 13:08:51.852306 [Byte1]: 55
3412 13:08:51.856482
3413 13:08:51.856577 Set Vref, RX VrefLevel [Byte0]: 56
3414 13:08:51.860111 [Byte1]: 56
3415 13:08:51.864487
3416 13:08:51.864561 Set Vref, RX VrefLevel [Byte0]: 57
3417 13:08:51.868096 [Byte1]: 57
3418 13:08:51.872246
3419 13:08:51.872320 Set Vref, RX VrefLevel [Byte0]: 58
3420 13:08:51.875776 [Byte1]: 58
3421 13:08:51.880465
3422 13:08:51.880539 Set Vref, RX VrefLevel [Byte0]: 59
3423 13:08:51.883881 [Byte1]: 59
3424 13:08:51.888420
3425 13:08:51.888496 Set Vref, RX VrefLevel [Byte0]: 60
3426 13:08:51.891435 [Byte1]: 60
3427 13:08:51.895907
3428 13:08:51.895982 Set Vref, RX VrefLevel [Byte0]: 61
3429 13:08:51.899345 [Byte1]: 61
3430 13:08:51.904277
3431 13:08:51.904352 Set Vref, RX VrefLevel [Byte0]: 62
3432 13:08:51.907230 [Byte1]: 62
3433 13:08:51.912121
3434 13:08:51.912195 Set Vref, RX VrefLevel [Byte0]: 63
3435 13:08:51.914972 [Byte1]: 63
3436 13:08:51.919622
3437 13:08:51.919697 Set Vref, RX VrefLevel [Byte0]: 64
3438 13:08:51.923209 [Byte1]: 64
3439 13:08:51.928083
3440 13:08:51.928157 Set Vref, RX VrefLevel [Byte0]: 65
3441 13:08:51.930926 [Byte1]: 65
3442 13:08:51.935590
3443 13:08:51.935665 Final RX Vref Byte 0 = 54 to rank0
3444 13:08:51.938743 Final RX Vref Byte 1 = 54 to rank0
3445 13:08:51.942278 Final RX Vref Byte 0 = 54 to rank1
3446 13:08:51.945734 Final RX Vref Byte 1 = 54 to rank1==
3447 13:08:51.948471 Dram Type= 6, Freq= 0, CH_1, rank 0
3448 13:08:51.955859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3449 13:08:51.955934 ==
3450 13:08:51.955992 DQS Delay:
3451 13:08:51.958633 DQS0 = 0, DQS1 = 0
3452 13:08:51.958707 DQM Delay:
3453 13:08:51.958764 DQM0 = 117, DQM1 = 115
3454 13:08:51.961923 DQ Delay:
3455 13:08:51.965134 DQ0 =124, DQ1 =114, DQ2 =108, DQ3 =118
3456 13:08:51.968409 DQ4 =114, DQ5 =124, DQ6 =128, DQ7 =112
3457 13:08:51.971792 DQ8 =102, DQ9 =106, DQ10 =116, DQ11 =110
3458 13:08:51.975153 DQ12 =124, DQ13 =122, DQ14 =122, DQ15 =124
3459 13:08:51.975228
3460 13:08:51.975299
3461 13:08:51.984935 [DQSOSCAuto] RK0, (LSB)MR18= 0xfa07, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 412 ps
3462 13:08:51.985036 CH1 RK0: MR19=304, MR18=FA07
3463 13:08:51.991319 CH1_RK0: MR19=0x304, MR18=0xFA07, DQSOSC=407, MR23=63, INC=39, DEC=26
3464 13:08:51.991415
3465 13:08:51.994835 ----->DramcWriteLeveling(PI) begin...
3466 13:08:51.994907 ==
3467 13:08:51.998349 Dram Type= 6, Freq= 0, CH_1, rank 1
3468 13:08:52.004828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3469 13:08:52.004897 ==
3470 13:08:52.008172 Write leveling (Byte 0): 24 => 24
3471 13:08:52.011250 Write leveling (Byte 1): 28 => 28
3472 13:08:52.014492 DramcWriteLeveling(PI) end<-----
3473 13:08:52.014563
3474 13:08:52.014621 ==
3475 13:08:52.017669 Dram Type= 6, Freq= 0, CH_1, rank 1
3476 13:08:52.021484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3477 13:08:52.021558 ==
3478 13:08:52.024342 [Gating] SW mode calibration
3479 13:08:52.030794 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3480 13:08:52.037994 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3481 13:08:52.040850 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3482 13:08:52.044346 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3483 13:08:52.050846 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 13:08:52.053983 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 13:08:52.057417 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 13:08:52.064564 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
3487 13:08:52.067421 0 15 24 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
3488 13:08:52.070371 0 15 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
3489 13:08:52.077097 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 13:08:52.080309 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 13:08:52.083602 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 13:08:52.090769 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 13:08:52.093698 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 13:08:52.097263 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3495 13:08:52.103962 1 0 24 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
3496 13:08:52.107004 1 0 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3497 13:08:52.109970 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 13:08:52.116864 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 13:08:52.120225 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 13:08:52.123274 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 13:08:52.126715 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 13:08:52.133443 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3503 13:08:52.136439 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3504 13:08:52.139885 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3505 13:08:52.146794 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 13:08:52.150090 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 13:08:52.153126 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 13:08:52.160105 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 13:08:52.162970 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 13:08:52.166712 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 13:08:52.172963 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 13:08:52.176633 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 13:08:52.179507 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 13:08:52.186435 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 13:08:52.189554 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 13:08:52.192776 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 13:08:52.199333 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 13:08:52.202886 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3519 13:08:52.205959 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3520 13:08:52.209089 Total UI for P1: 0, mck2ui 16
3521 13:08:52.212447 best dqsien dly found for B0: ( 1, 3, 20)
3522 13:08:52.218814 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3523 13:08:52.222212 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 13:08:52.225755 Total UI for P1: 0, mck2ui 16
3525 13:08:52.229316 best dqsien dly found for B1: ( 1, 3, 26)
3526 13:08:52.232618 best DQS0 dly(MCK, UI, PI) = (1, 3, 20)
3527 13:08:52.235441 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3528 13:08:52.235506
3529 13:08:52.239178 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 20)
3530 13:08:52.245730 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3531 13:08:52.245802 [Gating] SW calibration Done
3532 13:08:52.245859 ==
3533 13:08:52.248632 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 13:08:52.255262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 13:08:52.255331 ==
3536 13:08:52.255390 RX Vref Scan: 0
3537 13:08:52.255445
3538 13:08:52.258783 RX Vref 0 -> 0, step: 1
3539 13:08:52.258842
3540 13:08:52.262299 RX Delay -40 -> 252, step: 8
3541 13:08:52.265266 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3542 13:08:52.268791 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3543 13:08:52.272258 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3544 13:08:52.278260 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3545 13:08:52.281954 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3546 13:08:52.284986 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3547 13:08:52.288342 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3548 13:08:52.291830 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3549 13:08:52.298124 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3550 13:08:52.301541 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3551 13:08:52.304969 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3552 13:08:52.307843 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3553 13:08:52.315079 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3554 13:08:52.318162 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3555 13:08:52.320976 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3556 13:08:52.324619 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3557 13:08:52.324710 ==
3558 13:08:52.327935 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 13:08:52.334648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 13:08:52.334726 ==
3561 13:08:52.334800 DQS Delay:
3562 13:08:52.334872 DQS0 = 0, DQS1 = 0
3563 13:08:52.338116 DQM Delay:
3564 13:08:52.338205 DQM0 = 116, DQM1 = 114
3565 13:08:52.341017 DQ Delay:
3566 13:08:52.344135 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3567 13:08:52.347401 DQ4 =119, DQ5 =127, DQ6 =119, DQ7 =111
3568 13:08:52.350637 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =107
3569 13:08:52.354438 DQ12 =123, DQ13 =123, DQ14 =115, DQ15 =123
3570 13:08:52.354506
3571 13:08:52.354575
3572 13:08:52.354646 ==
3573 13:08:52.357774 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 13:08:52.360834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 13:08:52.364061 ==
3576 13:08:52.364129
3577 13:08:52.364199
3578 13:08:52.364266 TX Vref Scan disable
3579 13:08:52.367492 == TX Byte 0 ==
3580 13:08:52.370523 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3581 13:08:52.374101 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3582 13:08:52.377102 == TX Byte 1 ==
3583 13:08:52.380539 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3584 13:08:52.384091 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3585 13:08:52.387554 ==
3586 13:08:52.390903 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 13:08:52.393762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 13:08:52.393829 ==
3589 13:08:52.405306 TX Vref=22, minBit 1, minWin=25, winSum=421
3590 13:08:52.408353 TX Vref=24, minBit 2, minWin=26, winSum=428
3591 13:08:52.411865 TX Vref=26, minBit 2, minWin=26, winSum=431
3592 13:08:52.415303 TX Vref=28, minBit 2, minWin=26, winSum=431
3593 13:08:52.418307 TX Vref=30, minBit 2, minWin=26, winSum=434
3594 13:08:52.425364 TX Vref=32, minBit 11, minWin=26, winSum=433
3595 13:08:52.428192 [TxChooseVref] Worse bit 2, Min win 26, Win sum 434, Final Vref 30
3596 13:08:52.428259
3597 13:08:52.431677 Final TX Range 1 Vref 30
3598 13:08:52.431770
3599 13:08:52.431841 ==
3600 13:08:52.435186 Dram Type= 6, Freq= 0, CH_1, rank 1
3601 13:08:52.438259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3602 13:08:52.441403 ==
3603 13:08:52.441470
3604 13:08:52.441542
3605 13:08:52.441614 TX Vref Scan disable
3606 13:08:52.444808 == TX Byte 0 ==
3607 13:08:52.448543 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3608 13:08:52.454989 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3609 13:08:52.455059 == TX Byte 1 ==
3610 13:08:52.458258 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3611 13:08:52.464653 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3612 13:08:52.464726
3613 13:08:52.464801 [DATLAT]
3614 13:08:52.464870 Freq=1200, CH1 RK1
3615 13:08:52.464955
3616 13:08:52.467839 DATLAT Default: 0xd
3617 13:08:52.471477 0, 0xFFFF, sum = 0
3618 13:08:52.471603 1, 0xFFFF, sum = 0
3619 13:08:52.474461 2, 0xFFFF, sum = 0
3620 13:08:52.474551 3, 0xFFFF, sum = 0
3621 13:08:52.478147 4, 0xFFFF, sum = 0
3622 13:08:52.478261 5, 0xFFFF, sum = 0
3623 13:08:52.481094 6, 0xFFFF, sum = 0
3624 13:08:52.481240 7, 0xFFFF, sum = 0
3625 13:08:52.484832 8, 0xFFFF, sum = 0
3626 13:08:52.484954 9, 0xFFFF, sum = 0
3627 13:08:52.488353 10, 0xFFFF, sum = 0
3628 13:08:52.488448 11, 0xFFFF, sum = 0
3629 13:08:52.491028 12, 0x0, sum = 1
3630 13:08:52.491107 13, 0x0, sum = 2
3631 13:08:52.494430 14, 0x0, sum = 3
3632 13:08:52.494507 15, 0x0, sum = 4
3633 13:08:52.498090 best_step = 13
3634 13:08:52.498200
3635 13:08:52.498293 ==
3636 13:08:52.501411 Dram Type= 6, Freq= 0, CH_1, rank 1
3637 13:08:52.504716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3638 13:08:52.504828 ==
3639 13:08:52.504956 RX Vref Scan: 0
3640 13:08:52.507828
3641 13:08:52.507921 RX Vref 0 -> 0, step: 1
3642 13:08:52.508030
3643 13:08:52.511157 RX Delay -13 -> 252, step: 4
3644 13:08:52.517466 iDelay=191, Bit 0, Center 118 (51 ~ 186) 136
3645 13:08:52.520944 iDelay=191, Bit 1, Center 116 (51 ~ 182) 132
3646 13:08:52.524604 iDelay=191, Bit 2, Center 108 (43 ~ 174) 132
3647 13:08:52.527529 iDelay=191, Bit 3, Center 114 (51 ~ 178) 128
3648 13:08:52.530925 iDelay=191, Bit 4, Center 116 (51 ~ 182) 132
3649 13:08:52.537326 iDelay=191, Bit 5, Center 126 (63 ~ 190) 128
3650 13:08:52.540709 iDelay=191, Bit 6, Center 124 (59 ~ 190) 132
3651 13:08:52.544384 iDelay=191, Bit 7, Center 116 (51 ~ 182) 132
3652 13:08:52.547204 iDelay=191, Bit 8, Center 102 (43 ~ 162) 120
3653 13:08:52.550472 iDelay=191, Bit 9, Center 104 (43 ~ 166) 124
3654 13:08:52.557332 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
3655 13:08:52.560247 iDelay=191, Bit 11, Center 110 (51 ~ 170) 120
3656 13:08:52.563705 iDelay=191, Bit 12, Center 124 (63 ~ 186) 124
3657 13:08:52.567058 iDelay=191, Bit 13, Center 122 (63 ~ 182) 120
3658 13:08:52.573360 iDelay=191, Bit 14, Center 122 (63 ~ 182) 120
3659 13:08:52.576758 iDelay=191, Bit 15, Center 124 (63 ~ 186) 124
3660 13:08:52.576833 ==
3661 13:08:52.580431 Dram Type= 6, Freq= 0, CH_1, rank 1
3662 13:08:52.583491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3663 13:08:52.583567 ==
3664 13:08:52.587037 DQS Delay:
3665 13:08:52.587112 DQS0 = 0, DQS1 = 0
3666 13:08:52.587170 DQM Delay:
3667 13:08:52.589863 DQM0 = 117, DQM1 = 115
3668 13:08:52.589939 DQ Delay:
3669 13:08:52.593351 DQ0 =118, DQ1 =116, DQ2 =108, DQ3 =114
3670 13:08:52.596966 DQ4 =116, DQ5 =126, DQ6 =124, DQ7 =116
3671 13:08:52.599811 DQ8 =102, DQ9 =104, DQ10 =118, DQ11 =110
3672 13:08:52.606614 DQ12 =124, DQ13 =122, DQ14 =122, DQ15 =124
3673 13:08:52.606690
3674 13:08:52.606747
3675 13:08:52.613117 [DQSOSCAuto] RK1, (LSB)MR18= 0x11, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3676 13:08:52.616826 CH1 RK1: MR19=404, MR18=11
3677 13:08:52.623119 CH1_RK1: MR19=0x404, MR18=0x11, DQSOSC=403, MR23=63, INC=40, DEC=26
3678 13:08:52.626387 [RxdqsGatingPostProcess] freq 1200
3679 13:08:52.629624 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3680 13:08:52.632946 best DQS0 dly(2T, 0.5T) = (0, 11)
3681 13:08:52.635885 best DQS1 dly(2T, 0.5T) = (0, 11)
3682 13:08:52.639507 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3683 13:08:52.642968 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3684 13:08:52.645884 best DQS0 dly(2T, 0.5T) = (0, 11)
3685 13:08:52.649529 best DQS1 dly(2T, 0.5T) = (0, 11)
3686 13:08:52.652576 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3687 13:08:52.655963 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3688 13:08:52.659159 Pre-setting of DQS Precalculation
3689 13:08:52.662371 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3690 13:08:52.672693 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3691 13:08:52.679365 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3692 13:08:52.679443
3693 13:08:52.679502
3694 13:08:52.682757 [Calibration Summary] 2400 Mbps
3695 13:08:52.682833 CH 0, Rank 0
3696 13:08:52.685918 SW Impedance : PASS
3697 13:08:52.685995 DUTY Scan : NO K
3698 13:08:52.688957 ZQ Calibration : PASS
3699 13:08:52.692613 Jitter Meter : NO K
3700 13:08:52.692689 CBT Training : PASS
3701 13:08:52.695882 Write leveling : PASS
3702 13:08:52.698838 RX DQS gating : PASS
3703 13:08:52.698914 RX DQ/DQS(RDDQC) : PASS
3704 13:08:52.702353 TX DQ/DQS : PASS
3705 13:08:52.705330 RX DATLAT : PASS
3706 13:08:52.705406 RX DQ/DQS(Engine): PASS
3707 13:08:52.708811 TX OE : NO K
3708 13:08:52.708892 All Pass.
3709 13:08:52.708952
3710 13:08:52.711856 CH 0, Rank 1
3711 13:08:52.711933 SW Impedance : PASS
3712 13:08:52.715472 DUTY Scan : NO K
3713 13:08:52.718656 ZQ Calibration : PASS
3714 13:08:52.718735 Jitter Meter : NO K
3715 13:08:52.721931 CBT Training : PASS
3716 13:08:52.725264 Write leveling : PASS
3717 13:08:52.725339 RX DQS gating : PASS
3718 13:08:52.728488 RX DQ/DQS(RDDQC) : PASS
3719 13:08:52.728564 TX DQ/DQS : PASS
3720 13:08:52.731837 RX DATLAT : PASS
3721 13:08:52.735194 RX DQ/DQS(Engine): PASS
3722 13:08:52.735271 TX OE : NO K
3723 13:08:52.738544 All Pass.
3724 13:08:52.738619
3725 13:08:52.738678 CH 1, Rank 0
3726 13:08:52.741964 SW Impedance : PASS
3727 13:08:52.742041 DUTY Scan : NO K
3728 13:08:52.744940 ZQ Calibration : PASS
3729 13:08:52.748487 Jitter Meter : NO K
3730 13:08:52.748563 CBT Training : PASS
3731 13:08:52.751664 Write leveling : PASS
3732 13:08:52.755052 RX DQS gating : PASS
3733 13:08:52.755128 RX DQ/DQS(RDDQC) : PASS
3734 13:08:52.758495 TX DQ/DQS : PASS
3735 13:08:52.761465 RX DATLAT : PASS
3736 13:08:52.761540 RX DQ/DQS(Engine): PASS
3737 13:08:52.764958 TX OE : NO K
3738 13:08:52.765034 All Pass.
3739 13:08:52.765094
3740 13:08:52.768420 CH 1, Rank 1
3741 13:08:52.768496 SW Impedance : PASS
3742 13:08:52.771505 DUTY Scan : NO K
3743 13:08:52.775084 ZQ Calibration : PASS
3744 13:08:52.775159 Jitter Meter : NO K
3745 13:08:52.778276 CBT Training : PASS
3746 13:08:52.781072 Write leveling : PASS
3747 13:08:52.781175 RX DQS gating : PASS
3748 13:08:52.784455 RX DQ/DQS(RDDQC) : PASS
3749 13:08:52.788171 TX DQ/DQS : PASS
3750 13:08:52.788247 RX DATLAT : PASS
3751 13:08:52.791051 RX DQ/DQS(Engine): PASS
3752 13:08:52.794454 TX OE : NO K
3753 13:08:52.794530 All Pass.
3754 13:08:52.794589
3755 13:08:52.794644 DramC Write-DBI off
3756 13:08:52.797863 PER_BANK_REFRESH: Hybrid Mode
3757 13:08:52.800878 TX_TRACKING: ON
3758 13:08:52.808028 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3759 13:08:52.811127 [FAST_K] Save calibration result to emmc
3760 13:08:52.817538 dramc_set_vcore_voltage set vcore to 650000
3761 13:08:52.817672 Read voltage for 600, 5
3762 13:08:52.821001 Vio18 = 0
3763 13:08:52.821093 Vcore = 650000
3764 13:08:52.821218 Vdram = 0
3765 13:08:52.824460 Vddq = 0
3766 13:08:52.824536 Vmddr = 0
3767 13:08:52.827700 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3768 13:08:52.834559 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3769 13:08:52.837418 MEM_TYPE=3, freq_sel=19
3770 13:08:52.840708 sv_algorithm_assistance_LP4_1600
3771 13:08:52.843982 ============ PULL DRAM RESETB DOWN ============
3772 13:08:52.847926 ========== PULL DRAM RESETB DOWN end =========
3773 13:08:52.850959 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3774 13:08:52.854570 ===================================
3775 13:08:52.857490 LPDDR4 DRAM CONFIGURATION
3776 13:08:52.860881 ===================================
3777 13:08:52.863849 EX_ROW_EN[0] = 0x0
3778 13:08:52.863915 EX_ROW_EN[1] = 0x0
3779 13:08:52.867221 LP4Y_EN = 0x0
3780 13:08:52.867291 WORK_FSP = 0x0
3781 13:08:52.870723 WL = 0x2
3782 13:08:52.870799 RL = 0x2
3783 13:08:52.874160 BL = 0x2
3784 13:08:52.874236 RPST = 0x0
3785 13:08:52.877174 RD_PRE = 0x0
3786 13:08:52.880368 WR_PRE = 0x1
3787 13:08:52.880443 WR_PST = 0x0
3788 13:08:52.883578 DBI_WR = 0x0
3789 13:08:52.883680 DBI_RD = 0x0
3790 13:08:52.887330 OTF = 0x1
3791 13:08:52.890490 ===================================
3792 13:08:52.893791 ===================================
3793 13:08:52.893866 ANA top config
3794 13:08:52.896804 ===================================
3795 13:08:52.900301 DLL_ASYNC_EN = 0
3796 13:08:52.904059 ALL_SLAVE_EN = 1
3797 13:08:52.904136 NEW_RANK_MODE = 1
3798 13:08:52.907065 DLL_IDLE_MODE = 1
3799 13:08:52.910498 LP45_APHY_COMB_EN = 1
3800 13:08:52.913443 TX_ODT_DIS = 1
3801 13:08:52.913519 NEW_8X_MODE = 1
3802 13:08:52.916954 ===================================
3803 13:08:52.920366 ===================================
3804 13:08:52.923747 data_rate = 1200
3805 13:08:52.926987 CKR = 1
3806 13:08:52.930136 DQ_P2S_RATIO = 8
3807 13:08:52.933579 ===================================
3808 13:08:52.936829 CA_P2S_RATIO = 8
3809 13:08:52.940009 DQ_CA_OPEN = 0
3810 13:08:52.943553 DQ_SEMI_OPEN = 0
3811 13:08:52.943629 CA_SEMI_OPEN = 0
3812 13:08:52.946750 CA_FULL_RATE = 0
3813 13:08:52.950086 DQ_CKDIV4_EN = 1
3814 13:08:52.953011 CA_CKDIV4_EN = 1
3815 13:08:52.956751 CA_PREDIV_EN = 0
3816 13:08:52.959702 PH8_DLY = 0
3817 13:08:52.959781 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3818 13:08:52.962763 DQ_AAMCK_DIV = 4
3819 13:08:52.966204 CA_AAMCK_DIV = 4
3820 13:08:52.969694 CA_ADMCK_DIV = 4
3821 13:08:52.973078 DQ_TRACK_CA_EN = 0
3822 13:08:52.976117 CA_PICK = 600
3823 13:08:52.979787 CA_MCKIO = 600
3824 13:08:52.979864 MCKIO_SEMI = 0
3825 13:08:52.982648 PLL_FREQ = 2288
3826 13:08:52.986136 DQ_UI_PI_RATIO = 32
3827 13:08:52.989510 CA_UI_PI_RATIO = 0
3828 13:08:52.992661 ===================================
3829 13:08:52.995626 ===================================
3830 13:08:52.998957 memory_type:LPDDR4
3831 13:08:52.999033 GP_NUM : 10
3832 13:08:53.002630 SRAM_EN : 1
3833 13:08:53.006210 MD32_EN : 0
3834 13:08:53.009067 ===================================
3835 13:08:53.009167 [ANA_INIT] >>>>>>>>>>>>>>
3836 13:08:53.012328 <<<<<< [CONFIGURE PHASE]: ANA_TX
3837 13:08:53.015920 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3838 13:08:53.018833 ===================================
3839 13:08:53.022406 data_rate = 1200,PCW = 0X5800
3840 13:08:53.025969 ===================================
3841 13:08:53.028860 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3842 13:08:53.035649 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3843 13:08:53.038789 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3844 13:08:53.045551 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3845 13:08:53.048538 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3846 13:08:53.051872 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3847 13:08:53.051954 [ANA_INIT] flow start
3848 13:08:53.055675 [ANA_INIT] PLL >>>>>>>>
3849 13:08:53.058579 [ANA_INIT] PLL <<<<<<<<
3850 13:08:53.061590 [ANA_INIT] MIDPI >>>>>>>>
3851 13:08:53.061666 [ANA_INIT] MIDPI <<<<<<<<
3852 13:08:53.065087 [ANA_INIT] DLL >>>>>>>>
3853 13:08:53.068575 [ANA_INIT] flow end
3854 13:08:53.072096 ============ LP4 DIFF to SE enter ============
3855 13:08:53.074904 ============ LP4 DIFF to SE exit ============
3856 13:08:53.078354 [ANA_INIT] <<<<<<<<<<<<<
3857 13:08:53.081624 [Flow] Enable top DCM control >>>>>
3858 13:08:53.084845 [Flow] Enable top DCM control <<<<<
3859 13:08:53.087933 Enable DLL master slave shuffle
3860 13:08:53.091500 ==============================================================
3861 13:08:53.095011 Gating Mode config
3862 13:08:53.101485 ==============================================================
3863 13:08:53.101563 Config description:
3864 13:08:53.111565 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3865 13:08:53.117871 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3866 13:08:53.124907 SELPH_MODE 0: By rank 1: By Phase
3867 13:08:53.127665 ==============================================================
3868 13:08:53.130894 GAT_TRACK_EN = 1
3869 13:08:53.134586 RX_GATING_MODE = 2
3870 13:08:53.137524 RX_GATING_TRACK_MODE = 2
3871 13:08:53.141059 SELPH_MODE = 1
3872 13:08:53.144418 PICG_EARLY_EN = 1
3873 13:08:53.147757 VALID_LAT_VALUE = 1
3874 13:08:53.150802 ==============================================================
3875 13:08:53.154246 Enter into Gating configuration >>>>
3876 13:08:53.157556 Exit from Gating configuration <<<<
3877 13:08:53.160527 Enter into DVFS_PRE_config >>>>>
3878 13:08:53.173772 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3879 13:08:53.177301 Exit from DVFS_PRE_config <<<<<
3880 13:08:53.180278 Enter into PICG configuration >>>>
3881 13:08:53.183632 Exit from PICG configuration <<<<
3882 13:08:53.183711 [RX_INPUT] configuration >>>>>
3883 13:08:53.187059 [RX_INPUT] configuration <<<<<
3884 13:08:53.193612 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3885 13:08:53.197014 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3886 13:08:53.203596 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3887 13:08:53.209946 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3888 13:08:53.216524 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3889 13:08:53.223301 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3890 13:08:53.226760 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3891 13:08:53.229975 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3892 13:08:53.236600 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3893 13:08:53.240189 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3894 13:08:53.243275 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3895 13:08:53.246344 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3896 13:08:53.249487 ===================================
3897 13:08:53.253383 LPDDR4 DRAM CONFIGURATION
3898 13:08:53.256193 ===================================
3899 13:08:53.259886 EX_ROW_EN[0] = 0x0
3900 13:08:53.259954 EX_ROW_EN[1] = 0x0
3901 13:08:53.263055 LP4Y_EN = 0x0
3902 13:08:53.263133 WORK_FSP = 0x0
3903 13:08:53.266164 WL = 0x2
3904 13:08:53.269422 RL = 0x2
3905 13:08:53.269501 BL = 0x2
3906 13:08:53.272955 RPST = 0x0
3907 13:08:53.273056 RD_PRE = 0x0
3908 13:08:53.276090 WR_PRE = 0x1
3909 13:08:53.276191 WR_PST = 0x0
3910 13:08:53.279589 DBI_WR = 0x0
3911 13:08:53.279689 DBI_RD = 0x0
3912 13:08:53.282977 OTF = 0x1
3913 13:08:53.286054 ===================================
3914 13:08:53.289121 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3915 13:08:53.292301 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3916 13:08:53.299067 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3917 13:08:53.302693 ===================================
3918 13:08:53.302772 LPDDR4 DRAM CONFIGURATION
3919 13:08:53.305494 ===================================
3920 13:08:53.309128 EX_ROW_EN[0] = 0x10
3921 13:08:53.309252 EX_ROW_EN[1] = 0x0
3922 13:08:53.312688 LP4Y_EN = 0x0
3923 13:08:53.312766 WORK_FSP = 0x0
3924 13:08:53.315563 WL = 0x2
3925 13:08:53.319189 RL = 0x2
3926 13:08:53.319267 BL = 0x2
3927 13:08:53.322591 RPST = 0x0
3928 13:08:53.322669 RD_PRE = 0x0
3929 13:08:53.325412 WR_PRE = 0x1
3930 13:08:53.325496 WR_PST = 0x0
3931 13:08:53.328754 DBI_WR = 0x0
3932 13:08:53.328832 DBI_RD = 0x0
3933 13:08:53.332372 OTF = 0x1
3934 13:08:53.335206 ===================================
3935 13:08:53.342138 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3936 13:08:53.344912 nWR fixed to 30
3937 13:08:53.345014 [ModeRegInit_LP4] CH0 RK0
3938 13:08:53.348323 [ModeRegInit_LP4] CH0 RK1
3939 13:08:53.351893 [ModeRegInit_LP4] CH1 RK0
3940 13:08:53.355120 [ModeRegInit_LP4] CH1 RK1
3941 13:08:53.355206 match AC timing 17
3942 13:08:53.362047 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3943 13:08:53.365242 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3944 13:08:53.368268 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3945 13:08:53.374795 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3946 13:08:53.378040 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3947 13:08:53.378108 ==
3948 13:08:53.381268 Dram Type= 6, Freq= 0, CH_0, rank 0
3949 13:08:53.384686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3950 13:08:53.384759 ==
3951 13:08:53.391114 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3952 13:08:53.397883 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3953 13:08:53.401153 [CA 0] Center 36 (6~67) winsize 62
3954 13:08:53.404312 [CA 1] Center 36 (6~67) winsize 62
3955 13:08:53.407481 [CA 2] Center 34 (3~65) winsize 63
3956 13:08:53.411027 [CA 3] Center 34 (3~65) winsize 63
3957 13:08:53.414620 [CA 4] Center 33 (3~64) winsize 62
3958 13:08:53.417552 [CA 5] Center 33 (3~64) winsize 62
3959 13:08:53.417628
3960 13:08:53.420931 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3961 13:08:53.421007
3962 13:08:53.424430 [CATrainingPosCal] consider 1 rank data
3963 13:08:53.427260 u2DelayCellTimex100 = 270/100 ps
3964 13:08:53.430678 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3965 13:08:53.434080 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3966 13:08:53.437120 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
3967 13:08:53.440669 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3968 13:08:53.443605 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3969 13:08:53.450679 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3970 13:08:53.450756
3971 13:08:53.453694 CA PerBit enable=1, Macro0, CA PI delay=33
3972 13:08:53.453769
3973 13:08:53.457123 [CBTSetCACLKResult] CA Dly = 33
3974 13:08:53.457220 CS Dly: 5 (0~36)
3975 13:08:53.457279 ==
3976 13:08:53.460503 Dram Type= 6, Freq= 0, CH_0, rank 1
3977 13:08:53.466775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 13:08:53.466871 ==
3979 13:08:53.470579 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3980 13:08:53.476673 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3981 13:08:53.480126 [CA 0] Center 36 (6~67) winsize 62
3982 13:08:53.483463 [CA 1] Center 36 (6~67) winsize 62
3983 13:08:53.486730 [CA 2] Center 34 (4~65) winsize 62
3984 13:08:53.490324 [CA 3] Center 34 (4~65) winsize 62
3985 13:08:53.493097 [CA 4] Center 34 (3~65) winsize 63
3986 13:08:53.496600 [CA 5] Center 33 (3~64) winsize 62
3987 13:08:53.496667
3988 13:08:53.499995 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3989 13:08:53.500084
3990 13:08:53.503314 [CATrainingPosCal] consider 2 rank data
3991 13:08:53.506761 u2DelayCellTimex100 = 270/100 ps
3992 13:08:53.509588 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3993 13:08:53.516562 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3994 13:08:53.519579 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3995 13:08:53.523073 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3996 13:08:53.526175 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3997 13:08:53.529570 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3998 13:08:53.529637
3999 13:08:53.532944 CA PerBit enable=1, Macro0, CA PI delay=33
4000 13:08:53.533034
4001 13:08:53.536547 [CBTSetCACLKResult] CA Dly = 33
4002 13:08:53.536617 CS Dly: 6 (0~38)
4003 13:08:53.539498
4004 13:08:53.542766 ----->DramcWriteLeveling(PI) begin...
4005 13:08:53.542873 ==
4006 13:08:53.546475 Dram Type= 6, Freq= 0, CH_0, rank 0
4007 13:08:53.549277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4008 13:08:53.549344 ==
4009 13:08:53.552764 Write leveling (Byte 0): 31 => 31
4010 13:08:53.555859 Write leveling (Byte 1): 28 => 28
4011 13:08:53.559226 DramcWriteLeveling(PI) end<-----
4012 13:08:53.559318
4013 13:08:53.559407 ==
4014 13:08:53.562805 Dram Type= 6, Freq= 0, CH_0, rank 0
4015 13:08:53.565798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 13:08:53.565888 ==
4017 13:08:53.569409 [Gating] SW mode calibration
4018 13:08:53.576065 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4019 13:08:53.582172 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4020 13:08:53.585837 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4021 13:08:53.588851 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4022 13:08:53.595386 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4023 13:08:53.598982 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
4024 13:08:53.601745 0 9 16 | B1->B0 | 2f2f 2424 | 1 0 | (1 1) (0 0)
4025 13:08:53.608667 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 13:08:53.611747 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4027 13:08:53.615314 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 13:08:53.621553 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 13:08:53.624772 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 13:08:53.628653 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 13:08:53.634761 0 10 12 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4032 13:08:53.638060 0 10 16 | B1->B0 | 3939 4444 | 0 0 | (0 0) (0 0)
4033 13:08:53.641970 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 13:08:53.648066 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 13:08:53.651651 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 13:08:53.654474 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 13:08:53.661074 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 13:08:53.664574 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 13:08:53.668093 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4040 13:08:53.674647 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 13:08:53.677750 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 13:08:53.681092 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 13:08:53.687562 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 13:08:53.690817 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 13:08:53.694160 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 13:08:53.700971 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 13:08:53.704277 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 13:08:53.707568 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 13:08:53.714054 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 13:08:53.717445 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 13:08:53.720465 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 13:08:53.727087 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 13:08:53.730259 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 13:08:53.734118 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 13:08:53.740658 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 13:08:53.744472 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4057 13:08:53.746955 Total UI for P1: 0, mck2ui 16
4058 13:08:53.750546 best dqsien dly found for B0: ( 0, 13, 14)
4059 13:08:53.753441 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 13:08:53.756907 Total UI for P1: 0, mck2ui 16
4061 13:08:53.760200 best dqsien dly found for B1: ( 0, 13, 16)
4062 13:08:53.763685 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4063 13:08:53.767006 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4064 13:08:53.770102
4065 13:08:53.773547 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4066 13:08:53.776628 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4067 13:08:53.780061 [Gating] SW calibration Done
4068 13:08:53.780139 ==
4069 13:08:53.783023 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 13:08:53.786514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 13:08:53.786593 ==
4072 13:08:53.790085 RX Vref Scan: 0
4073 13:08:53.790163
4074 13:08:53.790240 RX Vref 0 -> 0, step: 1
4075 13:08:53.790314
4076 13:08:53.792825 RX Delay -230 -> 252, step: 16
4077 13:08:53.796584 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4078 13:08:53.803129 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4079 13:08:53.806592 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4080 13:08:53.809902 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4081 13:08:53.812704 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4082 13:08:53.819797 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4083 13:08:53.822688 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4084 13:08:53.826035 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4085 13:08:53.829305 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4086 13:08:53.832801 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4087 13:08:53.839301 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4088 13:08:53.842452 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4089 13:08:53.845507 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4090 13:08:53.849043 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4091 13:08:53.855936 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4092 13:08:53.858768 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4093 13:08:53.858836 ==
4094 13:08:53.862509 Dram Type= 6, Freq= 0, CH_0, rank 0
4095 13:08:53.865406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4096 13:08:53.865490 ==
4097 13:08:53.868805 DQS Delay:
4098 13:08:53.868874 DQS0 = 0, DQS1 = 0
4099 13:08:53.872433 DQM Delay:
4100 13:08:53.872495 DQM0 = 50, DQM1 = 40
4101 13:08:53.872554 DQ Delay:
4102 13:08:53.875221 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4103 13:08:53.878883 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4104 13:08:53.882431 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4105 13:08:53.885324 DQ12 =49, DQ13 =41, DQ14 =49, DQ15 =49
4106 13:08:53.885389
4107 13:08:53.885445
4108 13:08:53.888815 ==
4109 13:08:53.891928 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 13:08:53.894848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 13:08:53.894913 ==
4112 13:08:53.894966
4113 13:08:53.895016
4114 13:08:53.898176 TX Vref Scan disable
4115 13:08:53.898235 == TX Byte 0 ==
4116 13:08:53.905074 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4117 13:08:53.908216 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4118 13:08:53.908279 == TX Byte 1 ==
4119 13:08:53.915361 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4120 13:08:53.918650 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4121 13:08:53.918715 ==
4122 13:08:53.921819 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 13:08:53.925050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 13:08:53.925164 ==
4125 13:08:53.925241
4126 13:08:53.925297
4127 13:08:53.928244 TX Vref Scan disable
4128 13:08:53.931129 == TX Byte 0 ==
4129 13:08:53.934495 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4130 13:08:53.938212 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4131 13:08:53.940998 == TX Byte 1 ==
4132 13:08:53.944688 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4133 13:08:53.951194 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4134 13:08:53.951264
4135 13:08:53.951320 [DATLAT]
4136 13:08:53.951373 Freq=600, CH0 RK0
4137 13:08:53.951428
4138 13:08:53.954311 DATLAT Default: 0x9
4139 13:08:53.954372 0, 0xFFFF, sum = 0
4140 13:08:53.958180 1, 0xFFFF, sum = 0
4141 13:08:53.958249 2, 0xFFFF, sum = 0
4142 13:08:53.961019 3, 0xFFFF, sum = 0
4143 13:08:53.964315 4, 0xFFFF, sum = 0
4144 13:08:53.964383 5, 0xFFFF, sum = 0
4145 13:08:53.967808 6, 0xFFFF, sum = 0
4146 13:08:53.967883 7, 0xFFFF, sum = 0
4147 13:08:53.971021 8, 0x0, sum = 1
4148 13:08:53.971090 9, 0x0, sum = 2
4149 13:08:53.971160 10, 0x0, sum = 3
4150 13:08:53.974427 11, 0x0, sum = 4
4151 13:08:53.974493 best_step = 9
4152 13:08:53.974566
4153 13:08:53.974691 ==
4154 13:08:53.977644 Dram Type= 6, Freq= 0, CH_0, rank 0
4155 13:08:53.984228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 13:08:53.984302 ==
4157 13:08:53.984392 RX Vref Scan: 1
4158 13:08:53.984479
4159 13:08:53.987727 RX Vref 0 -> 0, step: 1
4160 13:08:53.987794
4161 13:08:53.990722 RX Delay -179 -> 252, step: 8
4162 13:08:53.990788
4163 13:08:53.994299 Set Vref, RX VrefLevel [Byte0]: 55
4164 13:08:53.997069 [Byte1]: 50
4165 13:08:53.997179
4166 13:08:54.000534 Final RX Vref Byte 0 = 55 to rank0
4167 13:08:54.004149 Final RX Vref Byte 1 = 50 to rank0
4168 13:08:54.007601 Final RX Vref Byte 0 = 55 to rank1
4169 13:08:54.010436 Final RX Vref Byte 1 = 50 to rank1==
4170 13:08:54.014174 Dram Type= 6, Freq= 0, CH_0, rank 0
4171 13:08:54.017077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4172 13:08:54.017191 ==
4173 13:08:54.020300 DQS Delay:
4174 13:08:54.020369 DQS0 = 0, DQS1 = 0
4175 13:08:54.023921 DQM Delay:
4176 13:08:54.023986 DQM0 = 44, DQM1 = 36
4177 13:08:54.027447 DQ Delay:
4178 13:08:54.027513 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4179 13:08:54.030512 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =48
4180 13:08:54.033933 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =32
4181 13:08:54.037242 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4182 13:08:54.037313
4183 13:08:54.039941
4184 13:08:54.047022 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d45, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
4185 13:08:54.049986 CH0 RK0: MR19=808, MR18=4D45
4186 13:08:54.056966 CH0_RK0: MR19=0x808, MR18=0x4D45, DQSOSC=395, MR23=63, INC=168, DEC=112
4187 13:08:54.057035
4188 13:08:54.059816 ----->DramcWriteLeveling(PI) begin...
4189 13:08:54.059884 ==
4190 13:08:54.062829 Dram Type= 6, Freq= 0, CH_0, rank 1
4191 13:08:54.066622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 13:08:54.066694 ==
4193 13:08:54.069558 Write leveling (Byte 0): 31 => 31
4194 13:08:54.072875 Write leveling (Byte 1): 31 => 31
4195 13:08:54.076206 DramcWriteLeveling(PI) end<-----
4196 13:08:54.076274
4197 13:08:54.076345 ==
4198 13:08:54.079487 Dram Type= 6, Freq= 0, CH_0, rank 1
4199 13:08:54.082581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 13:08:54.082648 ==
4201 13:08:54.086295 [Gating] SW mode calibration
4202 13:08:54.092793 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4203 13:08:54.099269 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4204 13:08:54.102754 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4205 13:08:54.109318 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4206 13:08:54.112470 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4207 13:08:54.115527 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (0 0)
4208 13:08:54.122085 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4209 13:08:54.125558 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 13:08:54.128502 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 13:08:54.135562 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 13:08:54.138756 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 13:08:54.141755 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 13:08:54.148563 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4215 13:08:54.151940 0 10 12 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
4216 13:08:54.155095 0 10 16 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
4217 13:08:54.161887 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 13:08:54.164727 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 13:08:54.168280 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 13:08:54.174727 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 13:08:54.178451 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 13:08:54.181167 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 13:08:54.188228 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4224 13:08:54.191287 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4225 13:08:54.194613 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 13:08:54.201245 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 13:08:54.204311 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 13:08:54.207860 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 13:08:54.214069 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 13:08:54.217830 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 13:08:54.221027 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 13:08:54.227647 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 13:08:54.230912 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 13:08:54.234284 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 13:08:54.240744 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 13:08:54.244370 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 13:08:54.247084 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 13:08:54.253735 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 13:08:54.257131 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4240 13:08:54.260220 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 13:08:54.264327 Total UI for P1: 0, mck2ui 16
4242 13:08:54.267028 best dqsien dly found for B0: ( 0, 13, 12)
4243 13:08:54.270568 Total UI for P1: 0, mck2ui 16
4244 13:08:54.273530 best dqsien dly found for B1: ( 0, 13, 12)
4245 13:08:54.276958 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4246 13:08:54.280599 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4247 13:08:54.283550
4248 13:08:54.286905 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4249 13:08:54.290266 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4250 13:08:54.293649 [Gating] SW calibration Done
4251 13:08:54.293727 ==
4252 13:08:54.296579 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 13:08:54.300273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 13:08:54.300352 ==
4255 13:08:54.300430 RX Vref Scan: 0
4256 13:08:54.303631
4257 13:08:54.303708 RX Vref 0 -> 0, step: 1
4258 13:08:54.303786
4259 13:08:54.306822 RX Delay -230 -> 252, step: 16
4260 13:08:54.309898 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4261 13:08:54.316535 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4262 13:08:54.320186 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4263 13:08:54.322948 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4264 13:08:54.326560 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4265 13:08:54.333421 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4266 13:08:54.336638 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4267 13:08:54.339806 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4268 13:08:54.343112 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4269 13:08:54.346515 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4270 13:08:54.352893 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4271 13:08:54.356592 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4272 13:08:54.359147 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4273 13:08:54.362882 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4274 13:08:54.369666 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4275 13:08:54.372470 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4276 13:08:54.372549 ==
4277 13:08:54.375868 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 13:08:54.379329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 13:08:54.379408 ==
4280 13:08:54.382479 DQS Delay:
4281 13:08:54.382558 DQS0 = 0, DQS1 = 0
4282 13:08:54.385460 DQM Delay:
4283 13:08:54.385561 DQM0 = 45, DQM1 = 34
4284 13:08:54.385655 DQ Delay:
4285 13:08:54.389025 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4286 13:08:54.392587 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =57
4287 13:08:54.395486 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4288 13:08:54.398958 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4289 13:08:54.399036
4290 13:08:54.399113
4291 13:08:54.401998 ==
4292 13:08:54.405372 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 13:08:54.408881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 13:08:54.408961 ==
4295 13:08:54.409054
4296 13:08:54.409168
4297 13:08:54.411848 TX Vref Scan disable
4298 13:08:54.411926 == TX Byte 0 ==
4299 13:08:54.418646 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4300 13:08:54.421909 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4301 13:08:54.421988 == TX Byte 1 ==
4302 13:08:54.428671 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4303 13:08:54.431869 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4304 13:08:54.431948 ==
4305 13:08:54.435110 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 13:08:54.438391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 13:08:54.438471 ==
4308 13:08:54.438549
4309 13:08:54.438621
4310 13:08:54.441556 TX Vref Scan disable
4311 13:08:54.444838 == TX Byte 0 ==
4312 13:08:54.448181 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4313 13:08:54.451521 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4314 13:08:54.454887 == TX Byte 1 ==
4315 13:08:54.458041 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4316 13:08:54.461456 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4317 13:08:54.465067
4318 13:08:54.465173 [DATLAT]
4319 13:08:54.465251 Freq=600, CH0 RK1
4320 13:08:54.465325
4321 13:08:54.468112 DATLAT Default: 0x9
4322 13:08:54.468213 0, 0xFFFF, sum = 0
4323 13:08:54.471466 1, 0xFFFF, sum = 0
4324 13:08:54.471543 2, 0xFFFF, sum = 0
4325 13:08:54.474617 3, 0xFFFF, sum = 0
4326 13:08:54.477785 4, 0xFFFF, sum = 0
4327 13:08:54.477861 5, 0xFFFF, sum = 0
4328 13:08:54.481058 6, 0xFFFF, sum = 0
4329 13:08:54.481168 7, 0xFFFF, sum = 0
4330 13:08:54.484466 8, 0x0, sum = 1
4331 13:08:54.484543 9, 0x0, sum = 2
4332 13:08:54.484603 10, 0x0, sum = 3
4333 13:08:54.488015 11, 0x0, sum = 4
4334 13:08:54.488091 best_step = 9
4335 13:08:54.488151
4336 13:08:54.488205 ==
4337 13:08:54.491024 Dram Type= 6, Freq= 0, CH_0, rank 1
4338 13:08:54.497956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 13:08:54.498033 ==
4340 13:08:54.498092 RX Vref Scan: 0
4341 13:08:54.498147
4342 13:08:54.500801 RX Vref 0 -> 0, step: 1
4343 13:08:54.500876
4344 13:08:54.504297 RX Delay -195 -> 252, step: 8
4345 13:08:54.507866 iDelay=205, Bit 0, Center 44 (-99 ~ 188) 288
4346 13:08:54.514271 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4347 13:08:54.517034 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4348 13:08:54.520718 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4349 13:08:54.524082 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4350 13:08:54.530736 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4351 13:08:54.533854 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4352 13:08:54.536777 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4353 13:08:54.540178 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4354 13:08:54.543595 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4355 13:08:54.549953 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4356 13:08:54.553261 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4357 13:08:54.556731 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4358 13:08:54.563398 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4359 13:08:54.566319 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4360 13:08:54.569918 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4361 13:08:54.569994 ==
4362 13:08:54.573519 Dram Type= 6, Freq= 0, CH_0, rank 1
4363 13:08:54.576503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 13:08:54.576580 ==
4365 13:08:54.579927 DQS Delay:
4366 13:08:54.580003 DQS0 = 0, DQS1 = 0
4367 13:08:54.582924 DQM Delay:
4368 13:08:54.583014 DQM0 = 44, DQM1 = 37
4369 13:08:54.586296 DQ Delay:
4370 13:08:54.586373 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4371 13:08:54.589646 DQ4 =48, DQ5 =32, DQ6 =56, DQ7 =52
4372 13:08:54.592720 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4373 13:08:54.596316 DQ12 =40, DQ13 =44, DQ14 =48, DQ15 =44
4374 13:08:54.596391
4375 13:08:54.596449
4376 13:08:54.606235 [DQSOSCAuto] RK1, (LSB)MR18= 0x4641, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4377 13:08:54.609494 CH0 RK1: MR19=808, MR18=4641
4378 13:08:54.616217 CH0_RK1: MR19=0x808, MR18=0x4641, DQSOSC=396, MR23=63, INC=167, DEC=111
4379 13:08:54.619218 [RxdqsGatingPostProcess] freq 600
4380 13:08:54.622461 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4381 13:08:54.625517 Pre-setting of DQS Precalculation
4382 13:08:54.632105 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4383 13:08:54.632187 ==
4384 13:08:54.635682 Dram Type= 6, Freq= 0, CH_1, rank 0
4385 13:08:54.639168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4386 13:08:54.639248 ==
4387 13:08:54.645679 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4388 13:08:54.648737 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4389 13:08:54.653396 [CA 0] Center 36 (6~66) winsize 61
4390 13:08:54.656605 [CA 1] Center 35 (5~66) winsize 62
4391 13:08:54.659870 [CA 2] Center 34 (4~65) winsize 62
4392 13:08:54.663258 [CA 3] Center 34 (3~65) winsize 63
4393 13:08:54.666854 [CA 4] Center 34 (4~65) winsize 62
4394 13:08:54.669927 [CA 5] Center 33 (3~64) winsize 62
4395 13:08:54.670006
4396 13:08:54.672804 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4397 13:08:54.672867
4398 13:08:54.676292 [CATrainingPosCal] consider 1 rank data
4399 13:08:54.679367 u2DelayCellTimex100 = 270/100 ps
4400 13:08:54.682883 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4401 13:08:54.689409 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4402 13:08:54.692783 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4403 13:08:54.696478 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4404 13:08:54.699273 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4405 13:08:54.702578 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4406 13:08:54.702637
4407 13:08:54.705835 CA PerBit enable=1, Macro0, CA PI delay=33
4408 13:08:54.705896
4409 13:08:54.709151 [CBTSetCACLKResult] CA Dly = 33
4410 13:08:54.712502 CS Dly: 3 (0~34)
4411 13:08:54.712565 ==
4412 13:08:54.715922 Dram Type= 6, Freq= 0, CH_1, rank 1
4413 13:08:54.718884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 13:08:54.718980 ==
4415 13:08:54.725738 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4416 13:08:54.728736 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4417 13:08:54.733314 [CA 0] Center 36 (6~66) winsize 61
4418 13:08:54.736833 [CA 1] Center 35 (5~66) winsize 62
4419 13:08:54.739801 [CA 2] Center 34 (4~65) winsize 62
4420 13:08:54.743104 [CA 3] Center 33 (3~64) winsize 62
4421 13:08:54.746549 [CA 4] Center 34 (4~65) winsize 62
4422 13:08:54.749636 [CA 5] Center 33 (3~64) winsize 62
4423 13:08:54.749705
4424 13:08:54.753021 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4425 13:08:54.753112
4426 13:08:54.756304 [CATrainingPosCal] consider 2 rank data
4427 13:08:54.759536 u2DelayCellTimex100 = 270/100 ps
4428 13:08:54.762873 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4429 13:08:54.769574 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4430 13:08:54.772538 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4431 13:08:54.775961 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4432 13:08:54.779265 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4433 13:08:54.782633 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4434 13:08:54.782703
4435 13:08:54.785496 CA PerBit enable=1, Macro0, CA PI delay=33
4436 13:08:54.785566
4437 13:08:54.789075 [CBTSetCACLKResult] CA Dly = 33
4438 13:08:54.792660 CS Dly: 4 (0~36)
4439 13:08:54.792732
4440 13:08:54.795594 ----->DramcWriteLeveling(PI) begin...
4441 13:08:54.795662 ==
4442 13:08:54.799073 Dram Type= 6, Freq= 0, CH_1, rank 0
4443 13:08:54.802010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 13:08:54.802078 ==
4445 13:08:54.805721 Write leveling (Byte 0): 26 => 26
4446 13:08:54.808501 Write leveling (Byte 1): 28 => 28
4447 13:08:54.811995 DramcWriteLeveling(PI) end<-----
4448 13:08:54.812062
4449 13:08:54.812132 ==
4450 13:08:54.815339 Dram Type= 6, Freq= 0, CH_1, rank 0
4451 13:08:54.818987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 13:08:54.819052 ==
4453 13:08:54.821902 [Gating] SW mode calibration
4454 13:08:54.828649 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4455 13:08:54.835144 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4456 13:08:54.838450 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4457 13:08:54.845511 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4458 13:08:54.848341 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4459 13:08:54.851679 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 1) (0 1)
4460 13:08:54.855184 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 13:08:54.861605 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 13:08:54.865114 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 13:08:54.868291 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 13:08:54.874543 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 13:08:54.878168 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 13:08:54.881719 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 13:08:54.887944 0 10 12 | B1->B0 | 3030 3333 | 0 0 | (0 0) (0 0)
4468 13:08:54.891094 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 13:08:54.897761 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 13:08:54.901333 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 13:08:54.904225 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 13:08:54.911258 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 13:08:54.914548 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 13:08:54.917549 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 13:08:54.923881 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 13:08:54.927604 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4477 13:08:54.931091 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 13:08:54.937378 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 13:08:54.940516 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 13:08:54.943837 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 13:08:54.950314 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 13:08:54.953634 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 13:08:54.957412 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 13:08:54.963939 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 13:08:54.967031 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 13:08:54.970359 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 13:08:54.976884 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 13:08:54.979948 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 13:08:54.983280 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 13:08:54.990282 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 13:08:54.993437 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4492 13:08:54.996313 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 13:08:54.999910 Total UI for P1: 0, mck2ui 16
4494 13:08:55.003247 best dqsien dly found for B0: ( 0, 13, 12)
4495 13:08:55.006284 Total UI for P1: 0, mck2ui 16
4496 13:08:55.009837 best dqsien dly found for B1: ( 0, 13, 12)
4497 13:08:55.013415 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4498 13:08:55.016229 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4499 13:08:55.016295
4500 13:08:55.023261 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4501 13:08:55.026196 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4502 13:08:55.026266 [Gating] SW calibration Done
4503 13:08:55.029807 ==
4504 13:08:55.032905 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 13:08:55.036239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 13:08:55.036306 ==
4507 13:08:55.036378 RX Vref Scan: 0
4508 13:08:55.036448
4509 13:08:55.039263 RX Vref 0 -> 0, step: 1
4510 13:08:55.039332
4511 13:08:55.042704 RX Delay -230 -> 252, step: 16
4512 13:08:55.046157 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4513 13:08:55.049253 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4514 13:08:55.055882 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4515 13:08:55.059596 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4516 13:08:55.062570 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4517 13:08:55.065747 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4518 13:08:55.072527 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4519 13:08:55.075664 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4520 13:08:55.079253 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4521 13:08:55.082045 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4522 13:08:55.089036 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4523 13:08:55.092239 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4524 13:08:55.095352 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4525 13:08:55.098694 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4526 13:08:55.105495 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4527 13:08:55.108919 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4528 13:08:55.108988 ==
4529 13:08:55.111737 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 13:08:55.115390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 13:08:55.115453 ==
4532 13:08:55.118097 DQS Delay:
4533 13:08:55.118158 DQS0 = 0, DQS1 = 0
4534 13:08:55.118210 DQM Delay:
4535 13:08:55.121529 DQM0 = 43, DQM1 = 37
4536 13:08:55.121591 DQ Delay:
4537 13:08:55.124756 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4538 13:08:55.128398 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4539 13:08:55.131259 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4540 13:08:55.134896 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4541 13:08:55.134956
4542 13:08:55.135011
4543 13:08:55.135062 ==
4544 13:08:55.137768 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 13:08:55.144721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 13:08:55.144828 ==
4547 13:08:55.144916
4548 13:08:55.144997
4549 13:08:55.145080 TX Vref Scan disable
4550 13:08:55.148786 == TX Byte 0 ==
4551 13:08:55.151756 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4552 13:08:55.158793 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4553 13:08:55.158887 == TX Byte 1 ==
4554 13:08:55.161770 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4555 13:08:55.168361 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4556 13:08:55.168435 ==
4557 13:08:55.171880 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 13:08:55.175244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 13:08:55.175312 ==
4560 13:08:55.175380
4561 13:08:55.175467
4562 13:08:55.178052 TX Vref Scan disable
4563 13:08:55.181545 == TX Byte 0 ==
4564 13:08:55.184433 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4565 13:08:55.187918 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4566 13:08:55.191524 == TX Byte 1 ==
4567 13:08:55.194550 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4568 13:08:55.197957 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4569 13:08:55.198022
4570 13:08:55.198078 [DATLAT]
4571 13:08:55.201519 Freq=600, CH1 RK0
4572 13:08:55.201578
4573 13:08:55.204415 DATLAT Default: 0x9
4574 13:08:55.204474 0, 0xFFFF, sum = 0
4575 13:08:55.207866 1, 0xFFFF, sum = 0
4576 13:08:55.207925 2, 0xFFFF, sum = 0
4577 13:08:55.211538 3, 0xFFFF, sum = 0
4578 13:08:55.211600 4, 0xFFFF, sum = 0
4579 13:08:55.214316 5, 0xFFFF, sum = 0
4580 13:08:55.214378 6, 0xFFFF, sum = 0
4581 13:08:55.217622 7, 0xFFFF, sum = 0
4582 13:08:55.217682 8, 0x0, sum = 1
4583 13:08:55.220866 9, 0x0, sum = 2
4584 13:08:55.220922 10, 0x0, sum = 3
4585 13:08:55.224407 11, 0x0, sum = 4
4586 13:08:55.224477 best_step = 9
4587 13:08:55.224536
4588 13:08:55.224590 ==
4589 13:08:55.227767 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 13:08:55.230931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 13:08:55.234160 ==
4592 13:08:55.234230 RX Vref Scan: 1
4593 13:08:55.234290
4594 13:08:55.237096 RX Vref 0 -> 0, step: 1
4595 13:08:55.237239
4596 13:08:55.240766 RX Delay -179 -> 252, step: 8
4597 13:08:55.240863
4598 13:08:55.243739 Set Vref, RX VrefLevel [Byte0]: 54
4599 13:08:55.247349 [Byte1]: 54
4600 13:08:55.247416
4601 13:08:55.250708 Final RX Vref Byte 0 = 54 to rank0
4602 13:08:55.254037 Final RX Vref Byte 1 = 54 to rank0
4603 13:08:55.257071 Final RX Vref Byte 0 = 54 to rank1
4604 13:08:55.260517 Final RX Vref Byte 1 = 54 to rank1==
4605 13:08:55.263486 Dram Type= 6, Freq= 0, CH_1, rank 0
4606 13:08:55.267082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 13:08:55.267159 ==
4608 13:08:55.269804 DQS Delay:
4609 13:08:55.269883 DQS0 = 0, DQS1 = 0
4610 13:08:55.269944 DQM Delay:
4611 13:08:55.273291 DQM0 = 45, DQM1 = 37
4612 13:08:55.273377 DQ Delay:
4613 13:08:55.276850 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4614 13:08:55.280347 DQ4 =40, DQ5 =52, DQ6 =56, DQ7 =40
4615 13:08:55.283452 DQ8 =24, DQ9 =28, DQ10 =36, DQ11 =32
4616 13:08:55.286533 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4617 13:08:55.286623
4618 13:08:55.286704
4619 13:08:55.296672 [DQSOSCAuto] RK0, (LSB)MR18= 0x304a, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
4620 13:08:55.299868 CH1 RK0: MR19=808, MR18=304A
4621 13:08:55.302947 CH1_RK0: MR19=0x808, MR18=0x304A, DQSOSC=395, MR23=63, INC=168, DEC=112
4622 13:08:55.303044
4623 13:08:55.306404 ----->DramcWriteLeveling(PI) begin...
4624 13:08:55.310020 ==
4625 13:08:55.312999 Dram Type= 6, Freq= 0, CH_1, rank 1
4626 13:08:55.316543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 13:08:55.316620 ==
4628 13:08:55.319949 Write leveling (Byte 0): 28 => 28
4629 13:08:55.323004 Write leveling (Byte 1): 29 => 29
4630 13:08:55.326406 DramcWriteLeveling(PI) end<-----
4631 13:08:55.326482
4632 13:08:55.326540 ==
4633 13:08:55.329845 Dram Type= 6, Freq= 0, CH_1, rank 1
4634 13:08:55.332989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 13:08:55.333065 ==
4636 13:08:55.336153 [Gating] SW mode calibration
4637 13:08:55.343071 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4638 13:08:55.349822 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4639 13:08:55.352731 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4640 13:08:55.356080 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4641 13:08:55.363024 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4642 13:08:55.365972 0 9 12 | B1->B0 | 2f2f 2929 | 0 0 | (0 0) (1 1)
4643 13:08:55.369354 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4644 13:08:55.376415 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 13:08:55.379729 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 13:08:55.382422 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 13:08:55.388841 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 13:08:55.392664 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 13:08:55.395571 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4650 13:08:55.402075 0 10 12 | B1->B0 | 3333 4141 | 0 0 | (0 0) (0 0)
4651 13:08:55.405492 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 13:08:55.408680 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 13:08:55.415571 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 13:08:55.418435 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 13:08:55.422404 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 13:08:55.428615 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 13:08:55.432295 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4658 13:08:55.435235 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4659 13:08:55.441604 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 13:08:55.444925 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 13:08:55.448385 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 13:08:55.455355 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 13:08:55.458421 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 13:08:55.461572 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 13:08:55.468170 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 13:08:55.471851 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 13:08:55.474562 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 13:08:55.481050 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 13:08:55.484585 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 13:08:55.487988 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 13:08:55.494524 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 13:08:55.497997 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 13:08:55.500922 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4674 13:08:55.507616 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 13:08:55.507687 Total UI for P1: 0, mck2ui 16
4676 13:08:55.511092 best dqsien dly found for B0: ( 0, 13, 8)
4677 13:08:55.514501 Total UI for P1: 0, mck2ui 16
4678 13:08:55.517816 best dqsien dly found for B1: ( 0, 13, 10)
4679 13:08:55.524044 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4680 13:08:55.527598 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4681 13:08:55.527666
4682 13:08:55.531063 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4683 13:08:55.534036 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4684 13:08:55.537485 [Gating] SW calibration Done
4685 13:08:55.537562 ==
4686 13:08:55.541005 Dram Type= 6, Freq= 0, CH_1, rank 1
4687 13:08:55.544002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4688 13:08:55.544080 ==
4689 13:08:55.547451 RX Vref Scan: 0
4690 13:08:55.547527
4691 13:08:55.547587 RX Vref 0 -> 0, step: 1
4692 13:08:55.547643
4693 13:08:55.550515 RX Delay -230 -> 252, step: 16
4694 13:08:55.554082 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4695 13:08:55.560397 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4696 13:08:55.564159 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4697 13:08:55.567112 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4698 13:08:55.570629 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4699 13:08:55.577262 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4700 13:08:55.580244 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4701 13:08:55.583829 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4702 13:08:55.586931 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4703 13:08:55.593394 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4704 13:08:55.596719 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4705 13:08:55.600318 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4706 13:08:55.603202 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4707 13:08:55.609749 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4708 13:08:55.613318 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4709 13:08:55.616256 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4710 13:08:55.616326 ==
4711 13:08:55.619658 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 13:08:55.623184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 13:08:55.626070 ==
4714 13:08:55.626138 DQS Delay:
4715 13:08:55.626195 DQS0 = 0, DQS1 = 0
4716 13:08:55.629537 DQM Delay:
4717 13:08:55.629613 DQM0 = 40, DQM1 = 39
4718 13:08:55.632780 DQ Delay:
4719 13:08:55.635931 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4720 13:08:55.636026 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4721 13:08:55.639174 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4722 13:08:55.645923 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4723 13:08:55.646015
4724 13:08:55.646097
4725 13:08:55.646182 ==
4726 13:08:55.649465 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 13:08:55.652351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 13:08:55.652436 ==
4729 13:08:55.652516
4730 13:08:55.652593
4731 13:08:55.656036 TX Vref Scan disable
4732 13:08:55.656120 == TX Byte 0 ==
4733 13:08:55.662576 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4734 13:08:55.666015 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4735 13:08:55.666117 == TX Byte 1 ==
4736 13:08:55.672224 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4737 13:08:55.675809 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4738 13:08:55.675887 ==
4739 13:08:55.679165 Dram Type= 6, Freq= 0, CH_1, rank 1
4740 13:08:55.682357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4741 13:08:55.682435 ==
4742 13:08:55.685148
4743 13:08:55.685239
4744 13:08:55.685297 TX Vref Scan disable
4745 13:08:55.688789 == TX Byte 0 ==
4746 13:08:55.692313 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4747 13:08:55.698896 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4748 13:08:55.698973 == TX Byte 1 ==
4749 13:08:55.702069 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4750 13:08:55.708531 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4751 13:08:55.708653
4752 13:08:55.708728 [DATLAT]
4753 13:08:55.708784 Freq=600, CH1 RK1
4754 13:08:55.708838
4755 13:08:55.711877 DATLAT Default: 0x9
4756 13:08:55.715277 0, 0xFFFF, sum = 0
4757 13:08:55.715356 1, 0xFFFF, sum = 0
4758 13:08:55.718406 2, 0xFFFF, sum = 0
4759 13:08:55.718479 3, 0xFFFF, sum = 0
4760 13:08:55.721884 4, 0xFFFF, sum = 0
4761 13:08:55.721957 5, 0xFFFF, sum = 0
4762 13:08:55.724969 6, 0xFFFF, sum = 0
4763 13:08:55.725036 7, 0xFFFF, sum = 0
4764 13:08:55.728631 8, 0x0, sum = 1
4765 13:08:55.728699 9, 0x0, sum = 2
4766 13:08:55.731677 10, 0x0, sum = 3
4767 13:08:55.731742 11, 0x0, sum = 4
4768 13:08:55.731815 best_step = 9
4769 13:08:55.731882
4770 13:08:55.735241 ==
4771 13:08:55.738311 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 13:08:55.741415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 13:08:55.741486 ==
4774 13:08:55.741558 RX Vref Scan: 0
4775 13:08:55.741630
4776 13:08:55.744581 RX Vref 0 -> 0, step: 1
4777 13:08:55.744646
4778 13:08:55.747939 RX Delay -179 -> 252, step: 8
4779 13:08:55.754934 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4780 13:08:55.757808 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4781 13:08:55.761462 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4782 13:08:55.764439 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4783 13:08:55.771292 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4784 13:08:55.774424 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4785 13:08:55.777635 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4786 13:08:55.781057 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4787 13:08:55.784549 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4788 13:08:55.791153 iDelay=205, Bit 9, Center 28 (-123 ~ 180) 304
4789 13:08:55.794013 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4790 13:08:55.797491 iDelay=205, Bit 11, Center 32 (-123 ~ 188) 312
4791 13:08:55.801068 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4792 13:08:55.807399 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4793 13:08:55.810754 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4794 13:08:55.814533 iDelay=205, Bit 15, Center 48 (-107 ~ 204) 312
4795 13:08:55.814609 ==
4796 13:08:55.817590 Dram Type= 6, Freq= 0, CH_1, rank 1
4797 13:08:55.820843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4798 13:08:55.823906 ==
4799 13:08:55.823983 DQS Delay:
4800 13:08:55.824043 DQS0 = 0, DQS1 = 0
4801 13:08:55.827379 DQM Delay:
4802 13:08:55.827455 DQM0 = 40, DQM1 = 38
4803 13:08:55.830796 DQ Delay:
4804 13:08:55.830873 DQ0 =44, DQ1 =36, DQ2 =32, DQ3 =36
4805 13:08:55.833966 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =36
4806 13:08:55.837412 DQ8 =28, DQ9 =28, DQ10 =40, DQ11 =32
4807 13:08:55.840562 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =48
4808 13:08:55.844064
4809 13:08:55.844139
4810 13:08:55.850473 [DQSOSCAuto] RK1, (LSB)MR18= 0x4368, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
4811 13:08:55.854039 CH1 RK1: MR19=808, MR18=4368
4812 13:08:55.860078 CH1_RK1: MR19=0x808, MR18=0x4368, DQSOSC=390, MR23=63, INC=172, DEC=114
4813 13:08:55.863579 [RxdqsGatingPostProcess] freq 600
4814 13:08:55.866695 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4815 13:08:55.870216 Pre-setting of DQS Precalculation
4816 13:08:55.876860 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4817 13:08:55.883158 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4818 13:08:55.889925 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4819 13:08:55.890004
4820 13:08:55.890065
4821 13:08:55.892940 [Calibration Summary] 1200 Mbps
4822 13:08:55.893019 CH 0, Rank 0
4823 13:08:55.896514 SW Impedance : PASS
4824 13:08:55.899788 DUTY Scan : NO K
4825 13:08:55.899866 ZQ Calibration : PASS
4826 13:08:55.903038 Jitter Meter : NO K
4827 13:08:55.906523 CBT Training : PASS
4828 13:08:55.906602 Write leveling : PASS
4829 13:08:55.909770 RX DQS gating : PASS
4830 13:08:55.912601 RX DQ/DQS(RDDQC) : PASS
4831 13:08:55.912680 TX DQ/DQS : PASS
4832 13:08:55.915911 RX DATLAT : PASS
4833 13:08:55.919402 RX DQ/DQS(Engine): PASS
4834 13:08:55.919480 TX OE : NO K
4835 13:08:55.922943 All Pass.
4836 13:08:55.923021
4837 13:08:55.923081 CH 0, Rank 1
4838 13:08:55.925972 SW Impedance : PASS
4839 13:08:55.926050 DUTY Scan : NO K
4840 13:08:55.929364 ZQ Calibration : PASS
4841 13:08:55.932467 Jitter Meter : NO K
4842 13:08:55.932545 CBT Training : PASS
4843 13:08:55.935545 Write leveling : PASS
4844 13:08:55.939135 RX DQS gating : PASS
4845 13:08:55.939223 RX DQ/DQS(RDDQC) : PASS
4846 13:08:55.942530 TX DQ/DQS : PASS
4847 13:08:55.945679 RX DATLAT : PASS
4848 13:08:55.945757 RX DQ/DQS(Engine): PASS
4849 13:08:55.949368 TX OE : NO K
4850 13:08:55.949446 All Pass.
4851 13:08:55.949507
4852 13:08:55.952333 CH 1, Rank 0
4853 13:08:55.952412 SW Impedance : PASS
4854 13:08:55.955345 DUTY Scan : NO K
4855 13:08:55.958686 ZQ Calibration : PASS
4856 13:08:55.958765 Jitter Meter : NO K
4857 13:08:55.962251 CBT Training : PASS
4858 13:08:55.965143 Write leveling : PASS
4859 13:08:55.965240 RX DQS gating : PASS
4860 13:08:55.968436 RX DQ/DQS(RDDQC) : PASS
4861 13:08:55.968537 TX DQ/DQS : PASS
4862 13:08:55.971801 RX DATLAT : PASS
4863 13:08:55.975394 RX DQ/DQS(Engine): PASS
4864 13:08:55.975497 TX OE : NO K
4865 13:08:55.978364 All Pass.
4866 13:08:55.978453
4867 13:08:55.978512 CH 1, Rank 1
4868 13:08:55.982179 SW Impedance : PASS
4869 13:08:55.982255 DUTY Scan : NO K
4870 13:08:55.985073 ZQ Calibration : PASS
4871 13:08:55.988404 Jitter Meter : NO K
4872 13:08:55.988480 CBT Training : PASS
4873 13:08:55.991649 Write leveling : PASS
4874 13:08:55.995028 RX DQS gating : PASS
4875 13:08:55.995125 RX DQ/DQS(RDDQC) : PASS
4876 13:08:55.998700 TX DQ/DQS : PASS
4877 13:08:56.001628 RX DATLAT : PASS
4878 13:08:56.001730 RX DQ/DQS(Engine): PASS
4879 13:08:56.005056 TX OE : NO K
4880 13:08:56.005163 All Pass.
4881 13:08:56.005226
4882 13:08:56.008653 DramC Write-DBI off
4883 13:08:56.011804 PER_BANK_REFRESH: Hybrid Mode
4884 13:08:56.011928 TX_TRACKING: ON
4885 13:08:56.021727 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4886 13:08:56.025043 [FAST_K] Save calibration result to emmc
4887 13:08:56.028141 dramc_set_vcore_voltage set vcore to 662500
4888 13:08:56.031423 Read voltage for 933, 3
4889 13:08:56.031499 Vio18 = 0
4890 13:08:56.031590 Vcore = 662500
4891 13:08:56.034945 Vdram = 0
4892 13:08:56.035040 Vddq = 0
4893 13:08:56.035113 Vmddr = 0
4894 13:08:56.041084 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4895 13:08:56.044554 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4896 13:08:56.047813 MEM_TYPE=3, freq_sel=17
4897 13:08:56.051550 sv_algorithm_assistance_LP4_1600
4898 13:08:56.054504 ============ PULL DRAM RESETB DOWN ============
4899 13:08:56.057781 ========== PULL DRAM RESETB DOWN end =========
4900 13:08:56.064076 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4901 13:08:56.067778 ===================================
4902 13:08:56.070801 LPDDR4 DRAM CONFIGURATION
4903 13:08:56.074422 ===================================
4904 13:08:56.074500 EX_ROW_EN[0] = 0x0
4905 13:08:56.077172 EX_ROW_EN[1] = 0x0
4906 13:08:56.077250 LP4Y_EN = 0x0
4907 13:08:56.080580 WORK_FSP = 0x0
4908 13:08:56.080663 WL = 0x3
4909 13:08:56.084211 RL = 0x3
4910 13:08:56.084279 BL = 0x2
4911 13:08:56.087374 RPST = 0x0
4912 13:08:56.087443 RD_PRE = 0x0
4913 13:08:56.090771 WR_PRE = 0x1
4914 13:08:56.093745 WR_PST = 0x0
4915 13:08:56.093815 DBI_WR = 0x0
4916 13:08:56.096892 DBI_RD = 0x0
4917 13:08:56.096992 OTF = 0x1
4918 13:08:56.100358 ===================================
4919 13:08:56.104169 ===================================
4920 13:08:56.104249 ANA top config
4921 13:08:56.107093 ===================================
4922 13:08:56.110672 DLL_ASYNC_EN = 0
4923 13:08:56.113694 ALL_SLAVE_EN = 1
4924 13:08:56.116872 NEW_RANK_MODE = 1
4925 13:08:56.120153 DLL_IDLE_MODE = 1
4926 13:08:56.120232 LP45_APHY_COMB_EN = 1
4927 13:08:56.123637 TX_ODT_DIS = 1
4928 13:08:56.126861 NEW_8X_MODE = 1
4929 13:08:56.130554 ===================================
4930 13:08:56.133471 ===================================
4931 13:08:56.136884 data_rate = 1866
4932 13:08:56.139829 CKR = 1
4933 13:08:56.143154 DQ_P2S_RATIO = 8
4934 13:08:56.146871 ===================================
4935 13:08:56.146968 CA_P2S_RATIO = 8
4936 13:08:56.149818 DQ_CA_OPEN = 0
4937 13:08:56.153150 DQ_SEMI_OPEN = 0
4938 13:08:56.156583 CA_SEMI_OPEN = 0
4939 13:08:56.159688 CA_FULL_RATE = 0
4940 13:08:56.163197 DQ_CKDIV4_EN = 1
4941 13:08:56.163269 CA_CKDIV4_EN = 1
4942 13:08:56.166458 CA_PREDIV_EN = 0
4943 13:08:56.169836 PH8_DLY = 0
4944 13:08:56.172674 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4945 13:08:56.175945 DQ_AAMCK_DIV = 4
4946 13:08:56.179585 CA_AAMCK_DIV = 4
4947 13:08:56.179698 CA_ADMCK_DIV = 4
4948 13:08:56.182523 DQ_TRACK_CA_EN = 0
4949 13:08:56.186353 CA_PICK = 933
4950 13:08:56.189502 CA_MCKIO = 933
4951 13:08:56.192780 MCKIO_SEMI = 0
4952 13:08:56.195861 PLL_FREQ = 3732
4953 13:08:56.199453 DQ_UI_PI_RATIO = 32
4954 13:08:56.202412 CA_UI_PI_RATIO = 0
4955 13:08:56.205990 ===================================
4956 13:08:56.209454 ===================================
4957 13:08:56.209554 memory_type:LPDDR4
4958 13:08:56.212131 GP_NUM : 10
4959 13:08:56.215731 SRAM_EN : 1
4960 13:08:56.215830 MD32_EN : 0
4961 13:08:56.218810 ===================================
4962 13:08:56.222300 [ANA_INIT] >>>>>>>>>>>>>>
4963 13:08:56.225682 <<<<<< [CONFIGURE PHASE]: ANA_TX
4964 13:08:56.228754 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4965 13:08:56.232090 ===================================
4966 13:08:56.235402 data_rate = 1866,PCW = 0X8f00
4967 13:08:56.238719 ===================================
4968 13:08:56.241947 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4969 13:08:56.245311 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4970 13:08:56.252014 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4971 13:08:56.255423 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4972 13:08:56.258420 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4973 13:08:56.261898 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4974 13:08:56.265173 [ANA_INIT] flow start
4975 13:08:56.268384 [ANA_INIT] PLL >>>>>>>>
4976 13:08:56.268459 [ANA_INIT] PLL <<<<<<<<
4977 13:08:56.271986 [ANA_INIT] MIDPI >>>>>>>>
4978 13:08:56.275085 [ANA_INIT] MIDPI <<<<<<<<
4979 13:08:56.278484 [ANA_INIT] DLL >>>>>>>>
4980 13:08:56.278585 [ANA_INIT] flow end
4981 13:08:56.281437 ============ LP4 DIFF to SE enter ============
4982 13:08:56.288056 ============ LP4 DIFF to SE exit ============
4983 13:08:56.288160 [ANA_INIT] <<<<<<<<<<<<<
4984 13:08:56.291674 [Flow] Enable top DCM control >>>>>
4985 13:08:56.294752 [Flow] Enable top DCM control <<<<<
4986 13:08:56.297786 Enable DLL master slave shuffle
4987 13:08:56.304562 ==============================================================
4988 13:08:56.304676 Gating Mode config
4989 13:08:56.311291 ==============================================================
4990 13:08:56.314381 Config description:
4991 13:08:56.324592 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4992 13:08:56.331144 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4993 13:08:56.334376 SELPH_MODE 0: By rank 1: By Phase
4994 13:08:56.341344 ==============================================================
4995 13:08:56.344371 GAT_TRACK_EN = 1
4996 13:08:56.347465 RX_GATING_MODE = 2
4997 13:08:56.350872 RX_GATING_TRACK_MODE = 2
4998 13:08:56.350970 SELPH_MODE = 1
4999 13:08:56.354356 PICG_EARLY_EN = 1
5000 13:08:56.357319 VALID_LAT_VALUE = 1
5001 13:08:56.364312 ==============================================================
5002 13:08:56.367486 Enter into Gating configuration >>>>
5003 13:08:56.370700 Exit from Gating configuration <<<<
5004 13:08:56.373776 Enter into DVFS_PRE_config >>>>>
5005 13:08:56.383890 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5006 13:08:56.386743 Exit from DVFS_PRE_config <<<<<
5007 13:08:56.390408 Enter into PICG configuration >>>>
5008 13:08:56.393591 Exit from PICG configuration <<<<
5009 13:08:56.396656 [RX_INPUT] configuration >>>>>
5010 13:08:56.400185 [RX_INPUT] configuration <<<<<
5011 13:08:56.403178 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5012 13:08:56.410403 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5013 13:08:56.416481 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5014 13:08:56.423123 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5015 13:08:56.429883 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5016 13:08:56.436330 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5017 13:08:56.439582 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5018 13:08:56.443080 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5019 13:08:56.446716 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5020 13:08:56.452940 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5021 13:08:56.456043 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5022 13:08:56.459271 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5023 13:08:56.463204 ===================================
5024 13:08:56.466313 LPDDR4 DRAM CONFIGURATION
5025 13:08:56.469515 ===================================
5026 13:08:56.469585 EX_ROW_EN[0] = 0x0
5027 13:08:56.472836 EX_ROW_EN[1] = 0x0
5028 13:08:56.476162 LP4Y_EN = 0x0
5029 13:08:56.476257 WORK_FSP = 0x0
5030 13:08:56.479293 WL = 0x3
5031 13:08:56.479394 RL = 0x3
5032 13:08:56.482657 BL = 0x2
5033 13:08:56.482750 RPST = 0x0
5034 13:08:56.486138 RD_PRE = 0x0
5035 13:08:56.486233 WR_PRE = 0x1
5036 13:08:56.489085 WR_PST = 0x0
5037 13:08:56.489184 DBI_WR = 0x0
5038 13:08:56.492720 DBI_RD = 0x0
5039 13:08:56.492812 OTF = 0x1
5040 13:08:56.496123 ===================================
5041 13:08:56.499047 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5042 13:08:56.505749 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5043 13:08:56.508782 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5044 13:08:56.512340 ===================================
5045 13:08:56.515501 LPDDR4 DRAM CONFIGURATION
5046 13:08:56.519000 ===================================
5047 13:08:56.519096 EX_ROW_EN[0] = 0x10
5048 13:08:56.522399 EX_ROW_EN[1] = 0x0
5049 13:08:56.525742 LP4Y_EN = 0x0
5050 13:08:56.525838 WORK_FSP = 0x0
5051 13:08:56.528644 WL = 0x3
5052 13:08:56.528735 RL = 0x3
5053 13:08:56.531817 BL = 0x2
5054 13:08:56.531915 RPST = 0x0
5055 13:08:56.535157 RD_PRE = 0x0
5056 13:08:56.535247 WR_PRE = 0x1
5057 13:08:56.538570 WR_PST = 0x0
5058 13:08:56.538672 DBI_WR = 0x0
5059 13:08:56.542432 DBI_RD = 0x0
5060 13:08:56.542530 OTF = 0x1
5061 13:08:56.545525 ===================================
5062 13:08:56.551799 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5063 13:08:56.556360 nWR fixed to 30
5064 13:08:56.559319 [ModeRegInit_LP4] CH0 RK0
5065 13:08:56.559422 [ModeRegInit_LP4] CH0 RK1
5066 13:08:56.562527 [ModeRegInit_LP4] CH1 RK0
5067 13:08:56.566353 [ModeRegInit_LP4] CH1 RK1
5068 13:08:56.566449 match AC timing 9
5069 13:08:56.572477 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5070 13:08:56.575855 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5071 13:08:56.579586 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5072 13:08:56.585830 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5073 13:08:56.589063 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5074 13:08:56.589197 ==
5075 13:08:56.592709 Dram Type= 6, Freq= 0, CH_0, rank 0
5076 13:08:56.595555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5077 13:08:56.595647 ==
5078 13:08:56.602277 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5079 13:08:56.608825 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5080 13:08:56.612520 [CA 0] Center 38 (7~69) winsize 63
5081 13:08:56.615444 [CA 1] Center 37 (7~68) winsize 62
5082 13:08:56.619063 [CA 2] Center 35 (5~65) winsize 61
5083 13:08:56.622005 [CA 3] Center 34 (4~65) winsize 62
5084 13:08:56.625464 [CA 4] Center 33 (3~64) winsize 62
5085 13:08:56.628929 [CA 5] Center 33 (3~63) winsize 61
5086 13:08:56.629021
5087 13:08:56.632481 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5088 13:08:56.632548
5089 13:08:56.635309 [CATrainingPosCal] consider 1 rank data
5090 13:08:56.638670 u2DelayCellTimex100 = 270/100 ps
5091 13:08:56.641954 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5092 13:08:56.645887 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5093 13:08:56.648799 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5094 13:08:56.652383 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5095 13:08:56.659008 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5096 13:08:56.662097 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5097 13:08:56.662174
5098 13:08:56.665641 CA PerBit enable=1, Macro0, CA PI delay=33
5099 13:08:56.665717
5100 13:08:56.668735 [CBTSetCACLKResult] CA Dly = 33
5101 13:08:56.668810 CS Dly: 6 (0~37)
5102 13:08:56.668869 ==
5103 13:08:56.671889 Dram Type= 6, Freq= 0, CH_0, rank 1
5104 13:08:56.678929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 13:08:56.679007 ==
5106 13:08:56.681889 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5107 13:08:56.688474 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5108 13:08:56.691598 [CA 0] Center 38 (8~68) winsize 61
5109 13:08:56.695202 [CA 1] Center 37 (7~68) winsize 62
5110 13:08:56.698575 [CA 2] Center 35 (5~65) winsize 61
5111 13:08:56.701624 [CA 3] Center 34 (4~65) winsize 62
5112 13:08:56.705045 [CA 4] Center 33 (3~64) winsize 62
5113 13:08:56.708661 [CA 5] Center 32 (2~63) winsize 62
5114 13:08:56.708736
5115 13:08:56.711708 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5116 13:08:56.711783
5117 13:08:56.714684 [CATrainingPosCal] consider 2 rank data
5118 13:08:56.718100 u2DelayCellTimex100 = 270/100 ps
5119 13:08:56.721761 CA0 delay=38 (8~68),Diff = 5 PI (31 cell)
5120 13:08:56.724629 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5121 13:08:56.731236 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5122 13:08:56.734789 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5123 13:08:56.737789 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5124 13:08:56.741299 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5125 13:08:56.741390
5126 13:08:56.744845 CA PerBit enable=1, Macro0, CA PI delay=33
5127 13:08:56.744946
5128 13:08:56.747860 [CBTSetCACLKResult] CA Dly = 33
5129 13:08:56.747979 CS Dly: 7 (0~39)
5130 13:08:56.748066
5131 13:08:56.754450 ----->DramcWriteLeveling(PI) begin...
5132 13:08:56.754562 ==
5133 13:08:56.757997 Dram Type= 6, Freq= 0, CH_0, rank 0
5134 13:08:56.761063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5135 13:08:56.761178 ==
5136 13:08:56.764555 Write leveling (Byte 0): 31 => 31
5137 13:08:56.768048 Write leveling (Byte 1): 26 => 26
5138 13:08:56.771415 DramcWriteLeveling(PI) end<-----
5139 13:08:56.771511
5140 13:08:56.771615 ==
5141 13:08:56.774446 Dram Type= 6, Freq= 0, CH_0, rank 0
5142 13:08:56.777685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5143 13:08:56.777777 ==
5144 13:08:56.780892 [Gating] SW mode calibration
5145 13:08:56.787379 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5146 13:08:56.794406 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5147 13:08:56.797773 0 14 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5148 13:08:56.800943 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5149 13:08:56.807833 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 13:08:56.810923 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 13:08:56.814275 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 13:08:56.820420 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 13:08:56.823989 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 13:08:56.827527 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 1)
5155 13:08:56.833615 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)
5156 13:08:56.837205 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5157 13:08:56.840136 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 13:08:56.846887 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 13:08:56.850544 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 13:08:56.853568 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 13:08:56.860172 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 13:08:56.863660 0 15 28 | B1->B0 | 2323 3838 | 0 0 | (0 0) (1 1)
5163 13:08:56.866798 1 0 0 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
5164 13:08:56.873457 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 13:08:56.876885 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 13:08:56.879871 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 13:08:56.886841 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 13:08:56.889999 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 13:08:56.892888 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 13:08:56.899890 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5171 13:08:56.903369 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5172 13:08:56.906475 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 13:08:56.912645 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 13:08:56.916280 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 13:08:56.919417 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 13:08:56.926490 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 13:08:56.929652 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 13:08:56.932737 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 13:08:56.939328 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 13:08:56.942351 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 13:08:56.945975 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 13:08:56.952256 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 13:08:56.956033 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 13:08:56.958989 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 13:08:56.965438 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5186 13:08:56.969066 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5187 13:08:56.972420 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5188 13:08:56.976048 Total UI for P1: 0, mck2ui 16
5189 13:08:56.978944 best dqsien dly found for B0: ( 1, 2, 26)
5190 13:08:56.985251 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 13:08:56.985331 Total UI for P1: 0, mck2ui 16
5192 13:08:56.988852 best dqsien dly found for B1: ( 1, 3, 0)
5193 13:08:56.995459 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5194 13:08:56.998633 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5195 13:08:56.998712
5196 13:08:57.002470 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5197 13:08:57.005400 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5198 13:08:57.008929 [Gating] SW calibration Done
5199 13:08:57.009007 ==
5200 13:08:57.011990 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 13:08:57.015345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 13:08:57.015423 ==
5203 13:08:57.018433 RX Vref Scan: 0
5204 13:08:57.018511
5205 13:08:57.018571 RX Vref 0 -> 0, step: 1
5206 13:08:57.018626
5207 13:08:57.022023 RX Delay -80 -> 252, step: 8
5208 13:08:57.024839 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5209 13:08:57.031420 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5210 13:08:57.034966 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5211 13:08:57.038563 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5212 13:08:57.041346 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5213 13:08:57.044783 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5214 13:08:57.048074 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5215 13:08:57.054539 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5216 13:08:57.058128 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5217 13:08:57.061122 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5218 13:08:57.064685 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5219 13:08:57.067669 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5220 13:08:57.074679 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5221 13:08:57.078147 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5222 13:08:57.081235 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5223 13:08:57.084381 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5224 13:08:57.084483 ==
5225 13:08:57.087740 Dram Type= 6, Freq= 0, CH_0, rank 0
5226 13:08:57.091107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5227 13:08:57.094382 ==
5228 13:08:57.094452 DQS Delay:
5229 13:08:57.094510 DQS0 = 0, DQS1 = 0
5230 13:08:57.097797 DQM Delay:
5231 13:08:57.097881 DQM0 = 102, DQM1 = 88
5232 13:08:57.100970 DQ Delay:
5233 13:08:57.104229 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5234 13:08:57.107233 DQ4 =103, DQ5 =91, DQ6 =111, DQ7 =107
5235 13:08:57.110624 DQ8 =83, DQ9 =71, DQ10 =87, DQ11 =87
5236 13:08:57.114170 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5237 13:08:57.114248
5238 13:08:57.114308
5239 13:08:57.114362 ==
5240 13:08:57.117157 Dram Type= 6, Freq= 0, CH_0, rank 0
5241 13:08:57.120544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5242 13:08:57.120621 ==
5243 13:08:57.120681
5244 13:08:57.120735
5245 13:08:57.124230 TX Vref Scan disable
5246 13:08:57.124308 == TX Byte 0 ==
5247 13:08:57.130678 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5248 13:08:57.133593 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5249 13:08:57.137166 == TX Byte 1 ==
5250 13:08:57.140601 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5251 13:08:57.143630 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5252 13:08:57.143708 ==
5253 13:08:57.146769 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 13:08:57.150168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 13:08:57.153380 ==
5256 13:08:57.153448
5257 13:08:57.153508
5258 13:08:57.153563 TX Vref Scan disable
5259 13:08:57.157382 == TX Byte 0 ==
5260 13:08:57.160353 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5261 13:08:57.166893 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5262 13:08:57.166995 == TX Byte 1 ==
5263 13:08:57.170511 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5264 13:08:57.177234 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5265 13:08:57.177312
5266 13:08:57.177395 [DATLAT]
5267 13:08:57.177455 Freq=933, CH0 RK0
5268 13:08:57.177510
5269 13:08:57.180038 DATLAT Default: 0xd
5270 13:08:57.180127 0, 0xFFFF, sum = 0
5271 13:08:57.183431 1, 0xFFFF, sum = 0
5272 13:08:57.186909 2, 0xFFFF, sum = 0
5273 13:08:57.186987 3, 0xFFFF, sum = 0
5274 13:08:57.190470 4, 0xFFFF, sum = 0
5275 13:08:57.190552 5, 0xFFFF, sum = 0
5276 13:08:57.193352 6, 0xFFFF, sum = 0
5277 13:08:57.193431 7, 0xFFFF, sum = 0
5278 13:08:57.196856 8, 0xFFFF, sum = 0
5279 13:08:57.196961 9, 0xFFFF, sum = 0
5280 13:08:57.200308 10, 0x0, sum = 1
5281 13:08:57.200386 11, 0x0, sum = 2
5282 13:08:57.203734 12, 0x0, sum = 3
5283 13:08:57.203859 13, 0x0, sum = 4
5284 13:08:57.203968 best_step = 11
5285 13:08:57.206905
5286 13:08:57.206983 ==
5287 13:08:57.210448 Dram Type= 6, Freq= 0, CH_0, rank 0
5288 13:08:57.213528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 13:08:57.213606 ==
5290 13:08:57.213677 RX Vref Scan: 1
5291 13:08:57.213735
5292 13:08:57.216300 RX Vref 0 -> 0, step: 1
5293 13:08:57.216404
5294 13:08:57.219736 RX Delay -69 -> 252, step: 4
5295 13:08:57.219840
5296 13:08:57.222847 Set Vref, RX VrefLevel [Byte0]: 55
5297 13:08:57.226285 [Byte1]: 50
5298 13:08:57.229985
5299 13:08:57.230096 Final RX Vref Byte 0 = 55 to rank0
5300 13:08:57.232904 Final RX Vref Byte 1 = 50 to rank0
5301 13:08:57.236478 Final RX Vref Byte 0 = 55 to rank1
5302 13:08:57.239458 Final RX Vref Byte 1 = 50 to rank1==
5303 13:08:57.243014 Dram Type= 6, Freq= 0, CH_0, rank 0
5304 13:08:57.249407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 13:08:57.249490 ==
5306 13:08:57.249560 DQS Delay:
5307 13:08:57.253075 DQS0 = 0, DQS1 = 0
5308 13:08:57.253175 DQM Delay:
5309 13:08:57.253237 DQM0 = 103, DQM1 = 90
5310 13:08:57.255803 DQ Delay:
5311 13:08:57.259559 DQ0 =104, DQ1 =104, DQ2 =98, DQ3 =100
5312 13:08:57.262734 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =108
5313 13:08:57.266239 DQ8 =82, DQ9 =76, DQ10 =92, DQ11 =86
5314 13:08:57.269293 DQ12 =98, DQ13 =92, DQ14 =96, DQ15 =98
5315 13:08:57.269382
5316 13:08:57.269471
5317 13:08:57.275783 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f19, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
5318 13:08:57.279192 CH0 RK0: MR19=505, MR18=1F19
5319 13:08:57.285809 CH0_RK0: MR19=0x505, MR18=0x1F19, DQSOSC=412, MR23=63, INC=63, DEC=42
5320 13:08:57.285893
5321 13:08:57.288872 ----->DramcWriteLeveling(PI) begin...
5322 13:08:57.288949 ==
5323 13:08:57.292613 Dram Type= 6, Freq= 0, CH_0, rank 1
5324 13:08:57.296246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5325 13:08:57.299133 ==
5326 13:08:57.299225 Write leveling (Byte 0): 32 => 32
5327 13:08:57.302439 Write leveling (Byte 1): 26 => 26
5328 13:08:57.305233 DramcWriteLeveling(PI) end<-----
5329 13:08:57.305298
5330 13:08:57.305353 ==
5331 13:08:57.308521 Dram Type= 6, Freq= 0, CH_0, rank 1
5332 13:08:57.315549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5333 13:08:57.315656 ==
5334 13:08:57.315743 [Gating] SW mode calibration
5335 13:08:57.325181 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5336 13:08:57.328264 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5337 13:08:57.334741 0 14 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
5338 13:08:57.338428 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5339 13:08:57.341679 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5340 13:08:57.348140 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 13:08:57.351726 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 13:08:57.354488 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 13:08:57.361342 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5344 13:08:57.364866 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
5345 13:08:57.368241 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5346 13:08:57.374679 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 13:08:57.377635 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5348 13:08:57.381209 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5349 13:08:57.387554 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 13:08:57.390950 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 13:08:57.394524 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 13:08:57.401041 0 15 28 | B1->B0 | 2424 3d3d | 0 0 | (0 0) (0 0)
5353 13:08:57.403963 1 0 0 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
5354 13:08:57.407713 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 13:08:57.414239 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 13:08:57.417514 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 13:08:57.420467 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 13:08:57.427489 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 13:08:57.430684 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5360 13:08:57.433898 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5361 13:08:57.440400 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 13:08:57.443802 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 13:08:57.446833 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 13:08:57.453624 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 13:08:57.456871 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 13:08:57.460410 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 13:08:57.466849 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 13:08:57.470234 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 13:08:57.473323 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 13:08:57.480015 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 13:08:57.483729 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 13:08:57.486704 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 13:08:57.493700 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 13:08:57.496590 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 13:08:57.500026 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5376 13:08:57.506696 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5377 13:08:57.509904 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 13:08:57.512900 Total UI for P1: 0, mck2ui 16
5379 13:08:57.516409 best dqsien dly found for B0: ( 1, 2, 26)
5380 13:08:57.519531 Total UI for P1: 0, mck2ui 16
5381 13:08:57.522904 best dqsien dly found for B1: ( 1, 2, 30)
5382 13:08:57.526006 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5383 13:08:57.529094 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5384 13:08:57.529221
5385 13:08:57.532458 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5386 13:08:57.535982 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5387 13:08:57.539005 [Gating] SW calibration Done
5388 13:08:57.539095 ==
5389 13:08:57.542635 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 13:08:57.548866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 13:08:57.548969 ==
5392 13:08:57.549053 RX Vref Scan: 0
5393 13:08:57.549146
5394 13:08:57.552317 RX Vref 0 -> 0, step: 1
5395 13:08:57.552405
5396 13:08:57.555357 RX Delay -80 -> 252, step: 8
5397 13:08:57.558936 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5398 13:08:57.562364 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5399 13:08:57.565359 iDelay=200, Bit 2, Center 95 (8 ~ 183) 176
5400 13:08:57.568881 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5401 13:08:57.575351 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5402 13:08:57.578331 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5403 13:08:57.581815 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5404 13:08:57.585308 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5405 13:08:57.588199 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5406 13:08:57.591504 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5407 13:08:57.598388 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5408 13:08:57.601641 iDelay=200, Bit 11, Center 87 (0 ~ 175) 176
5409 13:08:57.604698 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5410 13:08:57.607938 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5411 13:08:57.611475 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5412 13:08:57.617995 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5413 13:08:57.618088 ==
5414 13:08:57.621283 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 13:08:57.624994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 13:08:57.625061 ==
5417 13:08:57.625128 DQS Delay:
5418 13:08:57.628348 DQS0 = 0, DQS1 = 0
5419 13:08:57.628443 DQM Delay:
5420 13:08:57.631566 DQM0 = 99, DQM1 = 88
5421 13:08:57.631662 DQ Delay:
5422 13:08:57.634388 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5423 13:08:57.637946 DQ4 =99, DQ5 =91, DQ6 =107, DQ7 =107
5424 13:08:57.641374 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =87
5425 13:08:57.644411 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5426 13:08:57.644486
5427 13:08:57.644573
5428 13:08:57.644627 ==
5429 13:08:57.647903 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 13:08:57.650930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 13:08:57.654720 ==
5432 13:08:57.654795
5433 13:08:57.654853
5434 13:08:57.654908 TX Vref Scan disable
5435 13:08:57.657717 == TX Byte 0 ==
5436 13:08:57.660962 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5437 13:08:57.664334 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5438 13:08:57.667397 == TX Byte 1 ==
5439 13:08:57.670527 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5440 13:08:57.674384 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5441 13:08:57.677444 ==
5442 13:08:57.680729 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 13:08:57.684164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 13:08:57.684262 ==
5445 13:08:57.684327
5446 13:08:57.684382
5447 13:08:57.687005 TX Vref Scan disable
5448 13:08:57.687103 == TX Byte 0 ==
5449 13:08:57.694378 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5450 13:08:57.697159 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5451 13:08:57.697249 == TX Byte 1 ==
5452 13:08:57.703929 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5453 13:08:57.706986 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5454 13:08:57.707088
5455 13:08:57.707175 [DATLAT]
5456 13:08:57.710410 Freq=933, CH0 RK1
5457 13:08:57.710500
5458 13:08:57.710585 DATLAT Default: 0xb
5459 13:08:57.713765 0, 0xFFFF, sum = 0
5460 13:08:57.713833 1, 0xFFFF, sum = 0
5461 13:08:57.717557 2, 0xFFFF, sum = 0
5462 13:08:57.720527 3, 0xFFFF, sum = 0
5463 13:08:57.720625 4, 0xFFFF, sum = 0
5464 13:08:57.723248 5, 0xFFFF, sum = 0
5465 13:08:57.723339 6, 0xFFFF, sum = 0
5466 13:08:57.726739 7, 0xFFFF, sum = 0
5467 13:08:57.726847 8, 0xFFFF, sum = 0
5468 13:08:57.730248 9, 0xFFFF, sum = 0
5469 13:08:57.730349 10, 0x0, sum = 1
5470 13:08:57.733259 11, 0x0, sum = 2
5471 13:08:57.733326 12, 0x0, sum = 3
5472 13:08:57.736592 13, 0x0, sum = 4
5473 13:08:57.736658 best_step = 11
5474 13:08:57.736712
5475 13:08:57.736763 ==
5476 13:08:57.739846 Dram Type= 6, Freq= 0, CH_0, rank 1
5477 13:08:57.743511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5478 13:08:57.743607 ==
5479 13:08:57.746407 RX Vref Scan: 0
5480 13:08:57.746497
5481 13:08:57.749789 RX Vref 0 -> 0, step: 1
5482 13:08:57.749872
5483 13:08:57.749957 RX Delay -61 -> 252, step: 4
5484 13:08:57.757707 iDelay=195, Bit 0, Center 100 (19 ~ 182) 164
5485 13:08:57.760964 iDelay=195, Bit 1, Center 102 (15 ~ 190) 176
5486 13:08:57.764662 iDelay=195, Bit 2, Center 96 (11 ~ 182) 172
5487 13:08:57.768089 iDelay=195, Bit 3, Center 98 (11 ~ 186) 176
5488 13:08:57.770870 iDelay=195, Bit 4, Center 102 (15 ~ 190) 176
5489 13:08:57.777501 iDelay=195, Bit 5, Center 92 (7 ~ 178) 172
5490 13:08:57.780975 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5491 13:08:57.783793 iDelay=195, Bit 7, Center 108 (23 ~ 194) 172
5492 13:08:57.787295 iDelay=195, Bit 8, Center 84 (-1 ~ 170) 172
5493 13:08:57.790444 iDelay=195, Bit 9, Center 78 (-9 ~ 166) 176
5494 13:08:57.797358 iDelay=195, Bit 10, Center 92 (7 ~ 178) 172
5495 13:08:57.800265 iDelay=195, Bit 11, Center 84 (-1 ~ 170) 172
5496 13:08:57.803835 iDelay=195, Bit 12, Center 96 (11 ~ 182) 172
5497 13:08:57.807353 iDelay=195, Bit 13, Center 96 (11 ~ 182) 172
5498 13:08:57.810216 iDelay=195, Bit 14, Center 102 (19 ~ 186) 168
5499 13:08:57.816894 iDelay=195, Bit 15, Center 96 (11 ~ 182) 172
5500 13:08:57.816988 ==
5501 13:08:57.820651 Dram Type= 6, Freq= 0, CH_0, rank 1
5502 13:08:57.823421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 13:08:57.823518 ==
5504 13:08:57.823610 DQS Delay:
5505 13:08:57.827409 DQS0 = 0, DQS1 = 0
5506 13:08:57.827503 DQM Delay:
5507 13:08:57.830154 DQM0 = 100, DQM1 = 91
5508 13:08:57.830256 DQ Delay:
5509 13:08:57.833635 DQ0 =100, DQ1 =102, DQ2 =96, DQ3 =98
5510 13:08:57.836929 DQ4 =102, DQ5 =92, DQ6 =108, DQ7 =108
5511 13:08:57.840307 DQ8 =84, DQ9 =78, DQ10 =92, DQ11 =84
5512 13:08:57.843534 DQ12 =96, DQ13 =96, DQ14 =102, DQ15 =96
5513 13:08:57.843610
5514 13:08:57.843668
5515 13:08:57.853433 [DQSOSCAuto] RK1, (LSB)MR18= 0x1916, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 413 ps
5516 13:08:57.853510 CH0 RK1: MR19=505, MR18=1916
5517 13:08:57.859996 CH0_RK1: MR19=0x505, MR18=0x1916, DQSOSC=413, MR23=63, INC=63, DEC=42
5518 13:08:57.863396 [RxdqsGatingPostProcess] freq 933
5519 13:08:57.870032 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5520 13:08:57.873282 best DQS0 dly(2T, 0.5T) = (0, 10)
5521 13:08:57.877059 best DQS1 dly(2T, 0.5T) = (0, 11)
5522 13:08:57.879929 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5523 13:08:57.883488 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5524 13:08:57.886492 best DQS0 dly(2T, 0.5T) = (0, 10)
5525 13:08:57.890003 best DQS1 dly(2T, 0.5T) = (0, 10)
5526 13:08:57.890081 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5527 13:08:57.892891 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5528 13:08:57.896518 Pre-setting of DQS Precalculation
5529 13:08:57.903049 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5530 13:08:57.903144 ==
5531 13:08:57.906058 Dram Type= 6, Freq= 0, CH_1, rank 0
5532 13:08:57.909488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 13:08:57.909566 ==
5534 13:08:57.915906 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5535 13:08:57.922954 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5536 13:08:57.926164 [CA 0] Center 36 (6~67) winsize 62
5537 13:08:57.929079 [CA 1] Center 36 (6~67) winsize 62
5538 13:08:57.932471 [CA 2] Center 34 (4~65) winsize 62
5539 13:08:57.935973 [CA 3] Center 34 (4~65) winsize 62
5540 13:08:57.939398 [CA 4] Center 34 (4~65) winsize 62
5541 13:08:57.942505 [CA 5] Center 33 (3~64) winsize 62
5542 13:08:57.942601
5543 13:08:57.945960 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5544 13:08:57.946050
5545 13:08:57.948764 [CATrainingPosCal] consider 1 rank data
5546 13:08:57.951973 u2DelayCellTimex100 = 270/100 ps
5547 13:08:57.955681 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5548 13:08:57.958705 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5549 13:08:57.962268 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5550 13:08:57.965704 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5551 13:08:57.968554 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5552 13:08:57.975489 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5553 13:08:57.975586
5554 13:08:57.978531 CA PerBit enable=1, Macro0, CA PI delay=33
5555 13:08:57.978625
5556 13:08:57.982282 [CBTSetCACLKResult] CA Dly = 33
5557 13:08:57.982376 CS Dly: 5 (0~36)
5558 13:08:57.982458 ==
5559 13:08:57.985230 Dram Type= 6, Freq= 0, CH_1, rank 1
5560 13:08:57.988762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 13:08:57.992232 ==
5562 13:08:57.995318 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5563 13:08:58.001596 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5564 13:08:58.005272 [CA 0] Center 36 (6~67) winsize 62
5565 13:08:58.008249 [CA 1] Center 36 (6~67) winsize 62
5566 13:08:58.011805 [CA 2] Center 34 (4~65) winsize 62
5567 13:08:58.014742 [CA 3] Center 34 (4~64) winsize 61
5568 13:08:58.018328 [CA 4] Center 34 (4~64) winsize 61
5569 13:08:58.021467 [CA 5] Center 33 (3~64) winsize 62
5570 13:08:58.021539
5571 13:08:58.025044 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5572 13:08:58.025142
5573 13:08:58.028014 [CATrainingPosCal] consider 2 rank data
5574 13:08:58.031368 u2DelayCellTimex100 = 270/100 ps
5575 13:08:58.034501 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5576 13:08:58.037793 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5577 13:08:58.044374 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5578 13:08:58.047926 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5579 13:08:58.050933 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5580 13:08:58.054479 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5581 13:08:58.054555
5582 13:08:58.057606 CA PerBit enable=1, Macro0, CA PI delay=33
5583 13:08:58.057682
5584 13:08:58.060899 [CBTSetCACLKResult] CA Dly = 33
5585 13:08:58.060998 CS Dly: 6 (0~38)
5586 13:08:58.061093
5587 13:08:58.064521 ----->DramcWriteLeveling(PI) begin...
5588 13:08:58.068043 ==
5589 13:08:58.070827 Dram Type= 6, Freq= 0, CH_1, rank 0
5590 13:08:58.074289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5591 13:08:58.074383 ==
5592 13:08:58.077778 Write leveling (Byte 0): 25 => 25
5593 13:08:58.081161 Write leveling (Byte 1): 25 => 25
5594 13:08:58.084627 DramcWriteLeveling(PI) end<-----
5595 13:08:58.084720
5596 13:08:58.084806 ==
5597 13:08:58.087425 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 13:08:58.090960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 13:08:58.091051 ==
5600 13:08:58.094006 [Gating] SW mode calibration
5601 13:08:58.100536 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5602 13:08:58.107575 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5603 13:08:58.110396 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 13:08:58.113964 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 13:08:58.120554 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 13:08:58.123608 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 13:08:58.127157 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 13:08:58.133793 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 13:08:58.136881 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 1)
5610 13:08:58.140491 0 14 28 | B1->B0 | 2e2e 2727 | 0 0 | (0 0) (1 0)
5611 13:08:58.146924 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 13:08:58.150150 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 13:08:58.153759 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 13:08:58.159929 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 13:08:58.163438 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 13:08:58.166685 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 13:08:58.173737 0 15 24 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
5618 13:08:58.176961 0 15 28 | B1->B0 | 3838 3b3b | 0 0 | (0 0) (0 0)
5619 13:08:58.180110 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 13:08:58.186090 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 13:08:58.189505 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 13:08:58.192951 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 13:08:58.199640 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 13:08:58.202824 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 13:08:58.205666 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 13:08:58.212283 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 13:08:58.215920 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 13:08:58.218862 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 13:08:58.225362 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 13:08:58.228866 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 13:08:58.232728 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 13:08:58.238901 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 13:08:58.241942 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 13:08:58.245044 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 13:08:58.251913 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 13:08:58.255228 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 13:08:58.258444 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 13:08:58.265203 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 13:08:58.268707 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 13:08:58.271728 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 13:08:58.278070 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5642 13:08:58.281676 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 13:08:58.284587 Total UI for P1: 0, mck2ui 16
5644 13:08:58.288176 best dqsien dly found for B0: ( 1, 2, 24)
5645 13:08:58.291177 Total UI for P1: 0, mck2ui 16
5646 13:08:58.294890 best dqsien dly found for B1: ( 1, 2, 24)
5647 13:08:58.297858 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5648 13:08:58.301387 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5649 13:08:58.301463
5650 13:08:58.304929 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5651 13:08:58.311625 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5652 13:08:58.311701 [Gating] SW calibration Done
5653 13:08:58.311761 ==
5654 13:08:58.314472 Dram Type= 6, Freq= 0, CH_1, rank 0
5655 13:08:58.320983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5656 13:08:58.321060 ==
5657 13:08:58.321119 RX Vref Scan: 0
5658 13:08:58.321219
5659 13:08:58.324448 RX Vref 0 -> 0, step: 1
5660 13:08:58.324523
5661 13:08:58.327530 RX Delay -80 -> 252, step: 8
5662 13:08:58.330929 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5663 13:08:58.334562 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5664 13:08:58.337456 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5665 13:08:58.341046 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5666 13:08:58.347235 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5667 13:08:58.350519 iDelay=208, Bit 5, Center 103 (8 ~ 199) 192
5668 13:08:58.354247 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5669 13:08:58.357330 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5670 13:08:58.360681 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5671 13:08:58.363910 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5672 13:08:58.370578 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5673 13:08:58.373730 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5674 13:08:58.377060 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5675 13:08:58.380838 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5676 13:08:58.383649 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5677 13:08:58.390372 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5678 13:08:58.390470 ==
5679 13:08:58.393226 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 13:08:58.396776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 13:08:58.396869 ==
5682 13:08:58.396955 DQS Delay:
5683 13:08:58.399929 DQS0 = 0, DQS1 = 0
5684 13:08:58.400018 DQM Delay:
5685 13:08:58.403385 DQM0 = 98, DQM1 = 94
5686 13:08:58.403452 DQ Delay:
5687 13:08:58.406547 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5688 13:08:58.409936 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =95
5689 13:08:58.413061 DQ8 =79, DQ9 =87, DQ10 =95, DQ11 =87
5690 13:08:58.416762 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5691 13:08:58.416854
5692 13:08:58.416942
5693 13:08:58.417022 ==
5694 13:08:58.419812 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 13:08:58.426230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 13:08:58.426307 ==
5697 13:08:58.426366
5698 13:08:58.426419
5699 13:08:58.426471 TX Vref Scan disable
5700 13:08:58.430546 == TX Byte 0 ==
5701 13:08:58.433041 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5702 13:08:58.439850 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5703 13:08:58.439925 == TX Byte 1 ==
5704 13:08:58.443356 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5705 13:08:58.449719 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5706 13:08:58.449828 ==
5707 13:08:58.453272 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 13:08:58.456334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 13:08:58.456402 ==
5710 13:08:58.456459
5711 13:08:58.456548
5712 13:08:58.459727 TX Vref Scan disable
5713 13:08:58.459853 == TX Byte 0 ==
5714 13:08:58.466181 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5715 13:08:58.469404 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5716 13:08:58.472705 == TX Byte 1 ==
5717 13:08:58.476358 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5718 13:08:58.479811 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5719 13:08:58.479908
5720 13:08:58.479994 [DATLAT]
5721 13:08:58.482852 Freq=933, CH1 RK0
5722 13:08:58.482943
5723 13:08:58.483035 DATLAT Default: 0xd
5724 13:08:58.486415 0, 0xFFFF, sum = 0
5725 13:08:58.489249 1, 0xFFFF, sum = 0
5726 13:08:58.489323 2, 0xFFFF, sum = 0
5727 13:08:58.492678 3, 0xFFFF, sum = 0
5728 13:08:58.492771 4, 0xFFFF, sum = 0
5729 13:08:58.495759 5, 0xFFFF, sum = 0
5730 13:08:58.495851 6, 0xFFFF, sum = 0
5731 13:08:58.499200 7, 0xFFFF, sum = 0
5732 13:08:58.499293 8, 0xFFFF, sum = 0
5733 13:08:58.502585 9, 0xFFFF, sum = 0
5734 13:08:58.502677 10, 0x0, sum = 1
5735 13:08:58.506039 11, 0x0, sum = 2
5736 13:08:58.506146 12, 0x0, sum = 3
5737 13:08:58.509017 13, 0x0, sum = 4
5738 13:08:58.509112 best_step = 11
5739 13:08:58.509198
5740 13:08:58.509274 ==
5741 13:08:58.512865 Dram Type= 6, Freq= 0, CH_1, rank 0
5742 13:08:58.515777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 13:08:58.515869 ==
5744 13:08:58.519053 RX Vref Scan: 1
5745 13:08:58.519146
5746 13:08:58.522418 RX Vref 0 -> 0, step: 1
5747 13:08:58.522508
5748 13:08:58.522592 RX Delay -61 -> 252, step: 4
5749 13:08:58.522683
5750 13:08:58.525856 Set Vref, RX VrefLevel [Byte0]: 54
5751 13:08:58.528783 [Byte1]: 54
5752 13:08:58.533888
5753 13:08:58.533956 Final RX Vref Byte 0 = 54 to rank0
5754 13:08:58.536764 Final RX Vref Byte 1 = 54 to rank0
5755 13:08:58.540455 Final RX Vref Byte 0 = 54 to rank1
5756 13:08:58.543878 Final RX Vref Byte 1 = 54 to rank1==
5757 13:08:58.546802 Dram Type= 6, Freq= 0, CH_1, rank 0
5758 13:08:58.553373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 13:08:58.553450 ==
5760 13:08:58.553508 DQS Delay:
5761 13:08:58.556877 DQS0 = 0, DQS1 = 0
5762 13:08:58.556952 DQM Delay:
5763 13:08:58.557011 DQM0 = 98, DQM1 = 95
5764 13:08:58.560060 DQ Delay:
5765 13:08:58.563735 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =98
5766 13:08:58.566652 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =92
5767 13:08:58.569521 DQ8 =82, DQ9 =84, DQ10 =92, DQ11 =86
5768 13:08:58.572917 DQ12 =106, DQ13 =104, DQ14 =102, DQ15 =104
5769 13:08:58.572993
5770 13:08:58.573051
5771 13:08:58.579796 [DQSOSCAuto] RK0, (LSB)MR18= 0xa1a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 418 ps
5772 13:08:58.582873 CH1 RK0: MR19=505, MR18=A1A
5773 13:08:58.589390 CH1_RK0: MR19=0x505, MR18=0xA1A, DQSOSC=413, MR23=63, INC=63, DEC=42
5774 13:08:58.589479
5775 13:08:58.592636 ----->DramcWriteLeveling(PI) begin...
5776 13:08:58.592724 ==
5777 13:08:58.596303 Dram Type= 6, Freq= 0, CH_1, rank 1
5778 13:08:58.599397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5779 13:08:58.602362 ==
5780 13:08:58.605896 Write leveling (Byte 0): 27 => 27
5781 13:08:58.605968 Write leveling (Byte 1): 27 => 27
5782 13:08:58.609344 DramcWriteLeveling(PI) end<-----
5783 13:08:58.609411
5784 13:08:58.609466 ==
5785 13:08:58.612677 Dram Type= 6, Freq= 0, CH_1, rank 1
5786 13:08:58.619194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5787 13:08:58.619265 ==
5788 13:08:58.622618 [Gating] SW mode calibration
5789 13:08:58.629001 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5790 13:08:58.632344 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5791 13:08:58.638761 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5792 13:08:58.641917 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5793 13:08:58.645400 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5794 13:08:58.652226 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5795 13:08:58.655312 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5796 13:08:58.658374 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5797 13:08:58.665341 0 14 24 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 1)
5798 13:08:58.668267 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
5799 13:08:58.672037 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5800 13:08:58.678385 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5801 13:08:58.681963 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 13:08:58.685000 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5803 13:08:58.691584 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 13:08:58.694969 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 13:08:58.698134 0 15 24 | B1->B0 | 2a2a 3838 | 0 0 | (0 0) (1 1)
5806 13:08:58.704523 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5807 13:08:58.707879 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 13:08:58.710994 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 13:08:58.717791 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 13:08:58.721550 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 13:08:58.724427 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 13:08:58.731052 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 13:08:58.734835 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5814 13:08:58.737916 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5815 13:08:58.744628 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 13:08:58.747627 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 13:08:58.751041 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 13:08:58.757754 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 13:08:58.760741 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 13:08:58.764142 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 13:08:58.770694 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 13:08:58.773573 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 13:08:58.777052 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 13:08:58.783625 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 13:08:58.787321 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 13:08:58.790234 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 13:08:58.797092 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 13:08:58.800158 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5829 13:08:58.803647 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5830 13:08:58.810226 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5831 13:08:58.810304 Total UI for P1: 0, mck2ui 16
5832 13:08:58.816626 best dqsien dly found for B0: ( 1, 2, 22)
5833 13:08:58.819860 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 13:08:58.823082 Total UI for P1: 0, mck2ui 16
5835 13:08:58.826607 best dqsien dly found for B1: ( 1, 2, 28)
5836 13:08:58.830124 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5837 13:08:58.833428 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5838 13:08:58.833503
5839 13:08:58.836892 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5840 13:08:58.839655 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5841 13:08:58.842877 [Gating] SW calibration Done
5842 13:08:58.842953 ==
5843 13:08:58.846453 Dram Type= 6, Freq= 0, CH_1, rank 1
5844 13:08:58.853294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 13:08:58.853370 ==
5846 13:08:58.853430 RX Vref Scan: 0
5847 13:08:58.853485
5848 13:08:58.856149 RX Vref 0 -> 0, step: 1
5849 13:08:58.856223
5850 13:08:58.859297 RX Delay -80 -> 252, step: 8
5851 13:08:58.862726 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5852 13:08:58.866239 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5853 13:08:58.869088 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5854 13:08:58.872636 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5855 13:08:58.879055 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5856 13:08:58.882960 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5857 13:08:58.885667 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5858 13:08:58.889282 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5859 13:08:58.892279 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5860 13:08:58.895737 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5861 13:08:58.902321 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5862 13:08:58.905791 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5863 13:08:58.908983 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5864 13:08:58.912174 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5865 13:08:58.915375 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5866 13:08:58.921758 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5867 13:08:58.921835 ==
5868 13:08:58.925433 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 13:08:58.929025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 13:08:58.929101 ==
5871 13:08:58.929194 DQS Delay:
5872 13:08:58.932034 DQS0 = 0, DQS1 = 0
5873 13:08:58.932109 DQM Delay:
5874 13:08:58.935494 DQM0 = 95, DQM1 = 93
5875 13:08:58.935570 DQ Delay:
5876 13:08:58.938565 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5877 13:08:58.941587 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =91
5878 13:08:58.944809 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =87
5879 13:08:58.948336 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =103
5880 13:08:58.948412
5881 13:08:58.948470
5882 13:08:58.948525 ==
5883 13:08:58.951483 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 13:08:58.958080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 13:08:58.958157 ==
5886 13:08:58.958219
5887 13:08:58.958273
5888 13:08:58.958324 TX Vref Scan disable
5889 13:08:58.961409 == TX Byte 0 ==
5890 13:08:58.965019 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5891 13:08:58.971339 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5892 13:08:58.971415 == TX Byte 1 ==
5893 13:08:58.974840 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5894 13:08:58.981276 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5895 13:08:58.981353 ==
5896 13:08:58.984748 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 13:08:58.987770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 13:08:58.987846 ==
5899 13:08:58.987904
5900 13:08:58.987957
5901 13:08:58.991317 TX Vref Scan disable
5902 13:08:58.991392 == TX Byte 0 ==
5903 13:08:58.997684 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5904 13:08:59.001338 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5905 13:08:59.004316 == TX Byte 1 ==
5906 13:08:59.007792 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5907 13:08:59.010747 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5908 13:08:59.010822
5909 13:08:59.010880 [DATLAT]
5910 13:08:59.014327 Freq=933, CH1 RK1
5911 13:08:59.014402
5912 13:08:59.017819 DATLAT Default: 0xb
5913 13:08:59.017895 0, 0xFFFF, sum = 0
5914 13:08:59.020722 1, 0xFFFF, sum = 0
5915 13:08:59.020799 2, 0xFFFF, sum = 0
5916 13:08:59.024053 3, 0xFFFF, sum = 0
5917 13:08:59.024129 4, 0xFFFF, sum = 0
5918 13:08:59.027424 5, 0xFFFF, sum = 0
5919 13:08:59.027501 6, 0xFFFF, sum = 0
5920 13:08:59.030820 7, 0xFFFF, sum = 0
5921 13:08:59.030896 8, 0xFFFF, sum = 0
5922 13:08:59.033899 9, 0xFFFF, sum = 0
5923 13:08:59.033976 10, 0x0, sum = 1
5924 13:08:59.037381 11, 0x0, sum = 2
5925 13:08:59.037457 12, 0x0, sum = 3
5926 13:08:59.040727 13, 0x0, sum = 4
5927 13:08:59.040803 best_step = 11
5928 13:08:59.040861
5929 13:08:59.040914 ==
5930 13:08:59.043672 Dram Type= 6, Freq= 0, CH_1, rank 1
5931 13:08:59.047418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5932 13:08:59.050933 ==
5933 13:08:59.051008 RX Vref Scan: 0
5934 13:08:59.051066
5935 13:08:59.054097 RX Vref 0 -> 0, step: 1
5936 13:08:59.054172
5937 13:08:59.056853 RX Delay -61 -> 252, step: 4
5938 13:08:59.060574 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5939 13:08:59.063590 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5940 13:08:59.070251 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5941 13:08:59.073784 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5942 13:08:59.076846 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5943 13:08:59.080542 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5944 13:08:59.083627 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5945 13:08:59.086718 iDelay=199, Bit 7, Center 94 (-1 ~ 190) 192
5946 13:08:59.093176 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5947 13:08:59.096729 iDelay=199, Bit 9, Center 86 (-1 ~ 174) 176
5948 13:08:59.099650 iDelay=199, Bit 10, Center 98 (11 ~ 186) 176
5949 13:08:59.103453 iDelay=199, Bit 11, Center 88 (-1 ~ 178) 180
5950 13:08:59.106318 iDelay=199, Bit 12, Center 102 (15 ~ 190) 176
5951 13:08:59.112900 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5952 13:08:59.116532 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5953 13:08:59.119881 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5954 13:08:59.119956 ==
5955 13:08:59.122782 Dram Type= 6, Freq= 0, CH_1, rank 1
5956 13:08:59.126174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5957 13:08:59.126250 ==
5958 13:08:59.129871 DQS Delay:
5959 13:08:59.129947 DQS0 = 0, DQS1 = 0
5960 13:08:59.133169 DQM Delay:
5961 13:08:59.133245 DQM0 = 97, DQM1 = 94
5962 13:08:59.133303 DQ Delay:
5963 13:08:59.135962 DQ0 =102, DQ1 =94, DQ2 =90, DQ3 =94
5964 13:08:59.139273 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =94
5965 13:08:59.142694 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =88
5966 13:08:59.149359 DQ12 =102, DQ13 =100, DQ14 =98, DQ15 =102
5967 13:08:59.149459
5968 13:08:59.149548
5969 13:08:59.156289 [DQSOSCAuto] RK1, (LSB)MR18= 0x162d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5970 13:08:59.159202 CH1 RK1: MR19=505, MR18=162D
5971 13:08:59.166015 CH1_RK1: MR19=0x505, MR18=0x162D, DQSOSC=407, MR23=63, INC=65, DEC=43
5972 13:08:59.169498 [RxdqsGatingPostProcess] freq 933
5973 13:08:59.172418 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5974 13:08:59.175926 best DQS0 dly(2T, 0.5T) = (0, 10)
5975 13:08:59.179252 best DQS1 dly(2T, 0.5T) = (0, 10)
5976 13:08:59.182226 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5977 13:08:59.185778 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5978 13:08:59.189201 best DQS0 dly(2T, 0.5T) = (0, 10)
5979 13:08:59.192142 best DQS1 dly(2T, 0.5T) = (0, 10)
5980 13:08:59.195342 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5981 13:08:59.198986 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5982 13:08:59.201901 Pre-setting of DQS Precalculation
5983 13:08:59.205427 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5984 13:08:59.215627 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5985 13:08:59.221971 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5986 13:08:59.222048
5987 13:08:59.222107
5988 13:08:59.225499 [Calibration Summary] 1866 Mbps
5989 13:08:59.225576 CH 0, Rank 0
5990 13:08:59.228353 SW Impedance : PASS
5991 13:08:59.228430 DUTY Scan : NO K
5992 13:08:59.232039 ZQ Calibration : PASS
5993 13:08:59.234939 Jitter Meter : NO K
5994 13:08:59.235042 CBT Training : PASS
5995 13:08:59.238382 Write leveling : PASS
5996 13:08:59.241596 RX DQS gating : PASS
5997 13:08:59.241672 RX DQ/DQS(RDDQC) : PASS
5998 13:08:59.245055 TX DQ/DQS : PASS
5999 13:08:59.248047 RX DATLAT : PASS
6000 13:08:59.248124 RX DQ/DQS(Engine): PASS
6001 13:08:59.251360 TX OE : NO K
6002 13:08:59.251438 All Pass.
6003 13:08:59.251497
6004 13:08:59.254768 CH 0, Rank 1
6005 13:08:59.254836 SW Impedance : PASS
6006 13:08:59.258466 DUTY Scan : NO K
6007 13:08:59.261537 ZQ Calibration : PASS
6008 13:08:59.261606 Jitter Meter : NO K
6009 13:08:59.264791 CBT Training : PASS
6010 13:08:59.268225 Write leveling : PASS
6011 13:08:59.268290 RX DQS gating : PASS
6012 13:08:59.271284 RX DQ/DQS(RDDQC) : PASS
6013 13:08:59.274491 TX DQ/DQS : PASS
6014 13:08:59.274568 RX DATLAT : PASS
6015 13:08:59.278032 RX DQ/DQS(Engine): PASS
6016 13:08:59.281393 TX OE : NO K
6017 13:08:59.281469 All Pass.
6018 13:08:59.281528
6019 13:08:59.281583 CH 1, Rank 0
6020 13:08:59.284599 SW Impedance : PASS
6021 13:08:59.288011 DUTY Scan : NO K
6022 13:08:59.288113 ZQ Calibration : PASS
6023 13:08:59.291403 Jitter Meter : NO K
6024 13:08:59.291497 CBT Training : PASS
6025 13:08:59.294483 Write leveling : PASS
6026 13:08:59.297742 RX DQS gating : PASS
6027 13:08:59.297840 RX DQ/DQS(RDDQC) : PASS
6028 13:08:59.300940 TX DQ/DQS : PASS
6029 13:08:59.304205 RX DATLAT : PASS
6030 13:08:59.304297 RX DQ/DQS(Engine): PASS
6031 13:08:59.307556 TX OE : NO K
6032 13:08:59.307650 All Pass.
6033 13:08:59.307732
6034 13:08:59.311183 CH 1, Rank 1
6035 13:08:59.311285 SW Impedance : PASS
6036 13:08:59.314085 DUTY Scan : NO K
6037 13:08:59.317713 ZQ Calibration : PASS
6038 13:08:59.317785 Jitter Meter : NO K
6039 13:08:59.320634 CBT Training : PASS
6040 13:08:59.324261 Write leveling : PASS
6041 13:08:59.324327 RX DQS gating : PASS
6042 13:08:59.327533 RX DQ/DQS(RDDQC) : PASS
6043 13:08:59.330440 TX DQ/DQS : PASS
6044 13:08:59.330542 RX DATLAT : PASS
6045 13:08:59.334062 RX DQ/DQS(Engine): PASS
6046 13:08:59.337115 TX OE : NO K
6047 13:08:59.337233 All Pass.
6048 13:08:59.337291
6049 13:08:59.340680 DramC Write-DBI off
6050 13:08:59.340769 PER_BANK_REFRESH: Hybrid Mode
6051 13:08:59.343594 TX_TRACKING: ON
6052 13:08:59.350183 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6053 13:08:59.356949 [FAST_K] Save calibration result to emmc
6054 13:08:59.359951 dramc_set_vcore_voltage set vcore to 650000
6055 13:08:59.360052 Read voltage for 400, 6
6056 13:08:59.363410 Vio18 = 0
6057 13:08:59.363499 Vcore = 650000
6058 13:08:59.363587 Vdram = 0
6059 13:08:59.366721 Vddq = 0
6060 13:08:59.366808 Vmddr = 0
6061 13:08:59.370329 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6062 13:08:59.376819 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6063 13:08:59.379774 MEM_TYPE=3, freq_sel=20
6064 13:08:59.383347 sv_algorithm_assistance_LP4_800
6065 13:08:59.386427 ============ PULL DRAM RESETB DOWN ============
6066 13:08:59.389986 ========== PULL DRAM RESETB DOWN end =========
6067 13:08:59.396035 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6068 13:08:59.399446 ===================================
6069 13:08:59.399541 LPDDR4 DRAM CONFIGURATION
6070 13:08:59.402856 ===================================
6071 13:08:59.406185 EX_ROW_EN[0] = 0x0
6072 13:08:59.409755 EX_ROW_EN[1] = 0x0
6073 13:08:59.409830 LP4Y_EN = 0x0
6074 13:08:59.413035 WORK_FSP = 0x0
6075 13:08:59.413112 WL = 0x2
6076 13:08:59.416214 RL = 0x2
6077 13:08:59.416326 BL = 0x2
6078 13:08:59.419607 RPST = 0x0
6079 13:08:59.419707 RD_PRE = 0x0
6080 13:08:59.422925 WR_PRE = 0x1
6081 13:08:59.423015 WR_PST = 0x0
6082 13:08:59.426023 DBI_WR = 0x0
6083 13:08:59.426099 DBI_RD = 0x0
6084 13:08:59.429610 OTF = 0x1
6085 13:08:59.432835 ===================================
6086 13:08:59.435937 ===================================
6087 13:08:59.436012 ANA top config
6088 13:08:59.439295 ===================================
6089 13:08:59.442789 DLL_ASYNC_EN = 0
6090 13:08:59.445839 ALL_SLAVE_EN = 1
6091 13:08:59.449304 NEW_RANK_MODE = 1
6092 13:08:59.449381 DLL_IDLE_MODE = 1
6093 13:08:59.452276 LP45_APHY_COMB_EN = 1
6094 13:08:59.455589 TX_ODT_DIS = 1
6095 13:08:59.458797 NEW_8X_MODE = 1
6096 13:08:59.462428 ===================================
6097 13:08:59.465520 ===================================
6098 13:08:59.468938 data_rate = 800
6099 13:08:59.469038 CKR = 1
6100 13:08:59.471921 DQ_P2S_RATIO = 4
6101 13:08:59.475458 ===================================
6102 13:08:59.478672 CA_P2S_RATIO = 4
6103 13:08:59.482084 DQ_CA_OPEN = 0
6104 13:08:59.485437 DQ_SEMI_OPEN = 1
6105 13:08:59.488844 CA_SEMI_OPEN = 1
6106 13:08:59.488961 CA_FULL_RATE = 0
6107 13:08:59.492110 DQ_CKDIV4_EN = 0
6108 13:08:59.495750 CA_CKDIV4_EN = 1
6109 13:08:59.498963 CA_PREDIV_EN = 0
6110 13:08:59.501924 PH8_DLY = 0
6111 13:08:59.505197 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6112 13:08:59.505269 DQ_AAMCK_DIV = 0
6113 13:08:59.508805 CA_AAMCK_DIV = 0
6114 13:08:59.512129 CA_ADMCK_DIV = 4
6115 13:08:59.515207 DQ_TRACK_CA_EN = 0
6116 13:08:59.518181 CA_PICK = 800
6117 13:08:59.521608 CA_MCKIO = 400
6118 13:08:59.525003 MCKIO_SEMI = 400
6119 13:08:59.528026 PLL_FREQ = 3016
6120 13:08:59.528126 DQ_UI_PI_RATIO = 32
6121 13:08:59.531757 CA_UI_PI_RATIO = 32
6122 13:08:59.534956 ===================================
6123 13:08:59.538360 ===================================
6124 13:08:59.541329 memory_type:LPDDR4
6125 13:08:59.544893 GP_NUM : 10
6126 13:08:59.544994 SRAM_EN : 1
6127 13:08:59.548522 MD32_EN : 0
6128 13:08:59.551293 ===================================
6129 13:08:59.555025 [ANA_INIT] >>>>>>>>>>>>>>
6130 13:08:59.555095 <<<<<< [CONFIGURE PHASE]: ANA_TX
6131 13:08:59.557998 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6132 13:08:59.561300 ===================================
6133 13:08:59.564546 data_rate = 800,PCW = 0X7400
6134 13:08:59.567816 ===================================
6135 13:08:59.571304 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6136 13:08:59.578078 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6137 13:08:59.587382 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6138 13:08:59.593858 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6139 13:08:59.597272 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6140 13:08:59.600825 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6141 13:08:59.603819 [ANA_INIT] flow start
6142 13:08:59.603895 [ANA_INIT] PLL >>>>>>>>
6143 13:08:59.607341 [ANA_INIT] PLL <<<<<<<<
6144 13:08:59.610986 [ANA_INIT] MIDPI >>>>>>>>
6145 13:08:59.611061 [ANA_INIT] MIDPI <<<<<<<<
6146 13:08:59.614058 [ANA_INIT] DLL >>>>>>>>
6147 13:08:59.617059 [ANA_INIT] flow end
6148 13:08:59.620705 ============ LP4 DIFF to SE enter ============
6149 13:08:59.623613 ============ LP4 DIFF to SE exit ============
6150 13:08:59.627037 [ANA_INIT] <<<<<<<<<<<<<
6151 13:08:59.630746 [Flow] Enable top DCM control >>>>>
6152 13:08:59.633522 [Flow] Enable top DCM control <<<<<
6153 13:08:59.637250 Enable DLL master slave shuffle
6154 13:08:59.640545 ==============================================================
6155 13:08:59.643490 Gating Mode config
6156 13:08:59.650533 ==============================================================
6157 13:08:59.650613 Config description:
6158 13:08:59.660083 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6159 13:08:59.666933 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6160 13:08:59.673743 SELPH_MODE 0: By rank 1: By Phase
6161 13:08:59.676795 ==============================================================
6162 13:08:59.680317 GAT_TRACK_EN = 0
6163 13:08:59.683214 RX_GATING_MODE = 2
6164 13:08:59.686878 RX_GATING_TRACK_MODE = 2
6165 13:08:59.689718 SELPH_MODE = 1
6166 13:08:59.693453 PICG_EARLY_EN = 1
6167 13:08:59.696279 VALID_LAT_VALUE = 1
6168 13:08:59.699895 ==============================================================
6169 13:08:59.702812 Enter into Gating configuration >>>>
6170 13:08:59.706608 Exit from Gating configuration <<<<
6171 13:08:59.709570 Enter into DVFS_PRE_config >>>>>
6172 13:08:59.723014 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6173 13:08:59.726164 Exit from DVFS_PRE_config <<<<<
6174 13:08:59.729284 Enter into PICG configuration >>>>
6175 13:08:59.732714 Exit from PICG configuration <<<<
6176 13:08:59.732814 [RX_INPUT] configuration >>>>>
6177 13:08:59.736185 [RX_INPUT] configuration <<<<<
6178 13:08:59.742338 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6179 13:08:59.745917 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6180 13:08:59.752431 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6181 13:08:59.758807 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6182 13:08:59.765874 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6183 13:08:59.772403 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6184 13:08:59.775393 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6185 13:08:59.778776 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6186 13:08:59.785620 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6187 13:08:59.788901 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6188 13:08:59.791839 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6189 13:08:59.798419 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6190 13:08:59.801964 ===================================
6191 13:08:59.802041 LPDDR4 DRAM CONFIGURATION
6192 13:08:59.804994 ===================================
6193 13:08:59.808523 EX_ROW_EN[0] = 0x0
6194 13:08:59.811565 EX_ROW_EN[1] = 0x0
6195 13:08:59.811674 LP4Y_EN = 0x0
6196 13:08:59.815124 WORK_FSP = 0x0
6197 13:08:59.815239 WL = 0x2
6198 13:08:59.818533 RL = 0x2
6199 13:08:59.818627 BL = 0x2
6200 13:08:59.821429 RPST = 0x0
6201 13:08:59.821496 RD_PRE = 0x0
6202 13:08:59.824971 WR_PRE = 0x1
6203 13:08:59.825059 WR_PST = 0x0
6204 13:08:59.828088 DBI_WR = 0x0
6205 13:08:59.828178 DBI_RD = 0x0
6206 13:08:59.831480 OTF = 0x1
6207 13:08:59.834420 ===================================
6208 13:08:59.837873 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6209 13:08:59.841350 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6210 13:08:59.847931 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6211 13:08:59.851043 ===================================
6212 13:08:59.851143 LPDDR4 DRAM CONFIGURATION
6213 13:08:59.854573 ===================================
6214 13:08:59.857592 EX_ROW_EN[0] = 0x10
6215 13:08:59.861148 EX_ROW_EN[1] = 0x0
6216 13:08:59.861240 LP4Y_EN = 0x0
6217 13:08:59.864518 WORK_FSP = 0x0
6218 13:08:59.864587 WL = 0x2
6219 13:08:59.867286 RL = 0x2
6220 13:08:59.867378 BL = 0x2
6221 13:08:59.871038 RPST = 0x0
6222 13:08:59.871133 RD_PRE = 0x0
6223 13:08:59.874088 WR_PRE = 0x1
6224 13:08:59.874184 WR_PST = 0x0
6225 13:08:59.877285 DBI_WR = 0x0
6226 13:08:59.877371 DBI_RD = 0x0
6227 13:08:59.880850 OTF = 0x1
6228 13:08:59.884305 ===================================
6229 13:08:59.890409 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6230 13:08:59.894123 nWR fixed to 30
6231 13:08:59.894194 [ModeRegInit_LP4] CH0 RK0
6232 13:08:59.897567 [ModeRegInit_LP4] CH0 RK1
6233 13:08:59.900531 [ModeRegInit_LP4] CH1 RK0
6234 13:08:59.903866 [ModeRegInit_LP4] CH1 RK1
6235 13:08:59.903941 match AC timing 19
6236 13:08:59.910285 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6237 13:08:59.914082 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6238 13:08:59.917542 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6239 13:08:59.923848 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6240 13:08:59.927412 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6241 13:08:59.927488 ==
6242 13:08:59.930399 Dram Type= 6, Freq= 0, CH_0, rank 0
6243 13:08:59.933762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6244 13:08:59.933837 ==
6245 13:08:59.940125 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6246 13:08:59.946644 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6247 13:08:59.950224 [CA 0] Center 36 (8~64) winsize 57
6248 13:08:59.953518 [CA 1] Center 36 (8~64) winsize 57
6249 13:08:59.953589 [CA 2] Center 36 (8~64) winsize 57
6250 13:08:59.956758 [CA 3] Center 36 (8~64) winsize 57
6251 13:08:59.960340 [CA 4] Center 36 (8~64) winsize 57
6252 13:08:59.963480 [CA 5] Center 36 (8~64) winsize 57
6253 13:08:59.963572
6254 13:08:59.970034 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6255 13:08:59.970110
6256 13:08:59.973466 [CATrainingPosCal] consider 1 rank data
6257 13:08:59.976407 u2DelayCellTimex100 = 270/100 ps
6258 13:08:59.979765 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 13:08:59.983308 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 13:08:59.986229 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 13:08:59.989717 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 13:08:59.992853 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 13:08:59.996308 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 13:08:59.996383
6265 13:08:59.999705 CA PerBit enable=1, Macro0, CA PI delay=36
6266 13:08:59.999804
6267 13:09:00.002956 [CBTSetCACLKResult] CA Dly = 36
6268 13:09:00.006320 CS Dly: 1 (0~32)
6269 13:09:00.006395 ==
6270 13:09:00.009619 Dram Type= 6, Freq= 0, CH_0, rank 1
6271 13:09:00.012605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6272 13:09:00.012681 ==
6273 13:09:00.019003 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6274 13:09:00.025602 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6275 13:09:00.029311 [CA 0] Center 36 (8~64) winsize 57
6276 13:09:00.032175 [CA 1] Center 36 (8~64) winsize 57
6277 13:09:00.032251 [CA 2] Center 36 (8~64) winsize 57
6278 13:09:00.036017 [CA 3] Center 36 (8~64) winsize 57
6279 13:09:00.039275 [CA 4] Center 36 (8~64) winsize 57
6280 13:09:00.042172 [CA 5] Center 36 (8~64) winsize 57
6281 13:09:00.042248
6282 13:09:00.045871 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6283 13:09:00.045947
6284 13:09:00.052249 [CATrainingPosCal] consider 2 rank data
6285 13:09:00.052329 u2DelayCellTimex100 = 270/100 ps
6286 13:09:00.059144 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 13:09:00.062199 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 13:09:00.065564 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 13:09:00.068565 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 13:09:00.072073 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 13:09:00.075219 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 13:09:00.075309
6293 13:09:00.078617 CA PerBit enable=1, Macro0, CA PI delay=36
6294 13:09:00.078693
6295 13:09:00.082525 [CBTSetCACLKResult] CA Dly = 36
6296 13:09:00.085375 CS Dly: 1 (0~32)
6297 13:09:00.085451
6298 13:09:00.088840 ----->DramcWriteLeveling(PI) begin...
6299 13:09:00.088917 ==
6300 13:09:00.091671 Dram Type= 6, Freq= 0, CH_0, rank 0
6301 13:09:00.095557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 13:09:00.095634 ==
6303 13:09:00.098543 Write leveling (Byte 0): 40 => 8
6304 13:09:00.101839 Write leveling (Byte 1): 40 => 8
6305 13:09:00.105346 DramcWriteLeveling(PI) end<-----
6306 13:09:00.105421
6307 13:09:00.105480 ==
6308 13:09:00.108467 Dram Type= 6, Freq= 0, CH_0, rank 0
6309 13:09:00.111424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 13:09:00.111527 ==
6311 13:09:00.114754 [Gating] SW mode calibration
6312 13:09:00.121254 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6313 13:09:00.128173 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6314 13:09:00.131039 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6315 13:09:00.134412 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6316 13:09:00.141464 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6317 13:09:00.144496 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6318 13:09:00.147883 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6319 13:09:00.154136 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6320 13:09:00.157974 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6321 13:09:00.160894 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6322 13:09:00.167821 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6323 13:09:00.170766 Total UI for P1: 0, mck2ui 16
6324 13:09:00.174258 best dqsien dly found for B0: ( 0, 14, 24)
6325 13:09:00.177529 Total UI for P1: 0, mck2ui 16
6326 13:09:00.180856 best dqsien dly found for B1: ( 0, 14, 24)
6327 13:09:00.184109 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6328 13:09:00.187385 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6329 13:09:00.187474
6330 13:09:00.190543 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6331 13:09:00.194079 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6332 13:09:00.197024 [Gating] SW calibration Done
6333 13:09:00.197100 ==
6334 13:09:00.200611 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 13:09:00.204224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 13:09:00.204300 ==
6337 13:09:00.207015 RX Vref Scan: 0
6338 13:09:00.207097
6339 13:09:00.210839 RX Vref 0 -> 0, step: 1
6340 13:09:00.210942
6341 13:09:00.211000 RX Delay -410 -> 252, step: 16
6342 13:09:00.217290 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6343 13:09:00.220536 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6344 13:09:00.223627 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6345 13:09:00.230561 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6346 13:09:00.233887 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6347 13:09:00.236727 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6348 13:09:00.240425 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6349 13:09:00.246792 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6350 13:09:00.250447 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6351 13:09:00.253264 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6352 13:09:00.256559 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6353 13:09:00.263473 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6354 13:09:00.266651 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6355 13:09:00.270103 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6356 13:09:00.273063 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6357 13:09:00.279557 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6358 13:09:00.279653 ==
6359 13:09:00.282988 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 13:09:00.286541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 13:09:00.286633 ==
6362 13:09:00.290089 DQS Delay:
6363 13:09:00.290180 DQS0 = 35, DQS1 = 59
6364 13:09:00.290262 DQM Delay:
6365 13:09:00.292841 DQM0 = 4, DQM1 = 18
6366 13:09:00.292948 DQ Delay:
6367 13:09:00.296445 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6368 13:09:00.299438 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6369 13:09:00.302955 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =16
6370 13:09:00.306313 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6371 13:09:00.306409
6372 13:09:00.306495
6373 13:09:00.306574 ==
6374 13:09:00.309240 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 13:09:00.312823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 13:09:00.316389 ==
6377 13:09:00.316458
6378 13:09:00.316513
6379 13:09:00.316595 TX Vref Scan disable
6380 13:09:00.319498 == TX Byte 0 ==
6381 13:09:00.322965 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6382 13:09:00.326325 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6383 13:09:00.329278 == TX Byte 1 ==
6384 13:09:00.332589 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6385 13:09:00.336290 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6386 13:09:00.336422 ==
6387 13:09:00.339156 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 13:09:00.345639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 13:09:00.345712 ==
6390 13:09:00.345770
6391 13:09:00.345823
6392 13:09:00.345875 TX Vref Scan disable
6393 13:09:00.348789 == TX Byte 0 ==
6394 13:09:00.352423 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6395 13:09:00.355892 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6396 13:09:00.358671 == TX Byte 1 ==
6397 13:09:00.362181 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6398 13:09:00.365722 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6399 13:09:00.365797
6400 13:09:00.369187 [DATLAT]
6401 13:09:00.369263 Freq=400, CH0 RK0
6402 13:09:00.369322
6403 13:09:00.372219 DATLAT Default: 0xf
6404 13:09:00.372293 0, 0xFFFF, sum = 0
6405 13:09:00.375562 1, 0xFFFF, sum = 0
6406 13:09:00.375638 2, 0xFFFF, sum = 0
6407 13:09:00.378995 3, 0xFFFF, sum = 0
6408 13:09:00.379072 4, 0xFFFF, sum = 0
6409 13:09:00.381889 5, 0xFFFF, sum = 0
6410 13:09:00.381965 6, 0xFFFF, sum = 0
6411 13:09:00.385059 7, 0xFFFF, sum = 0
6412 13:09:00.385187 8, 0xFFFF, sum = 0
6413 13:09:00.388617 9, 0xFFFF, sum = 0
6414 13:09:00.391674 10, 0xFFFF, sum = 0
6415 13:09:00.391776 11, 0xFFFF, sum = 0
6416 13:09:00.394805 12, 0xFFFF, sum = 0
6417 13:09:00.394899 13, 0x0, sum = 1
6418 13:09:00.398337 14, 0x0, sum = 2
6419 13:09:00.398429 15, 0x0, sum = 3
6420 13:09:00.401562 16, 0x0, sum = 4
6421 13:09:00.401664 best_step = 14
6422 13:09:00.401745
6423 13:09:00.401828 ==
6424 13:09:00.404996 Dram Type= 6, Freq= 0, CH_0, rank 0
6425 13:09:00.408304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 13:09:00.408391 ==
6427 13:09:00.411782 RX Vref Scan: 1
6428 13:09:00.411942
6429 13:09:00.414640 RX Vref 0 -> 0, step: 1
6430 13:09:00.414738
6431 13:09:00.414819 RX Delay -359 -> 252, step: 8
6432 13:09:00.414902
6433 13:09:00.418354 Set Vref, RX VrefLevel [Byte0]: 55
6434 13:09:00.421463 [Byte1]: 50
6435 13:09:00.427021
6436 13:09:00.427114 Final RX Vref Byte 0 = 55 to rank0
6437 13:09:00.430049 Final RX Vref Byte 1 = 50 to rank0
6438 13:09:00.433564 Final RX Vref Byte 0 = 55 to rank1
6439 13:09:00.437237 Final RX Vref Byte 1 = 50 to rank1==
6440 13:09:00.440158 Dram Type= 6, Freq= 0, CH_0, rank 0
6441 13:09:00.446659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 13:09:00.446763 ==
6443 13:09:00.446854 DQS Delay:
6444 13:09:00.449853 DQS0 = 44, DQS1 = 56
6445 13:09:00.449950 DQM Delay:
6446 13:09:00.450034 DQM0 = 10, DQM1 = 14
6447 13:09:00.453253 DQ Delay:
6448 13:09:00.456446 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6449 13:09:00.460158 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6450 13:09:00.460229 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6451 13:09:00.463364 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6452 13:09:00.466921
6453 13:09:00.467010
6454 13:09:00.473440 [DQSOSCAuto] RK0, (LSB)MR18= 0xa89c, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
6455 13:09:00.476528 CH0 RK0: MR19=C0C, MR18=A89C
6456 13:09:00.483163 CH0_RK0: MR19=0xC0C, MR18=0xA89C, DQSOSC=388, MR23=63, INC=392, DEC=261
6457 13:09:00.483317 ==
6458 13:09:00.486592 Dram Type= 6, Freq= 0, CH_0, rank 1
6459 13:09:00.489470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 13:09:00.489591 ==
6461 13:09:00.492977 [Gating] SW mode calibration
6462 13:09:00.499636 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6463 13:09:00.506327 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6464 13:09:00.509554 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6465 13:09:00.512956 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6466 13:09:00.519192 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6467 13:09:00.522150 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6468 13:09:00.525863 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6469 13:09:00.532635 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6470 13:09:00.535614 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6471 13:09:00.539180 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6472 13:09:00.545765 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6473 13:09:00.549130 Total UI for P1: 0, mck2ui 16
6474 13:09:00.552219 best dqsien dly found for B0: ( 0, 14, 24)
6475 13:09:00.552296 Total UI for P1: 0, mck2ui 16
6476 13:09:00.558865 best dqsien dly found for B1: ( 0, 14, 24)
6477 13:09:00.562209 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6478 13:09:00.565302 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6479 13:09:00.565379
6480 13:09:00.568573 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6481 13:09:00.571675 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6482 13:09:00.575234 [Gating] SW calibration Done
6483 13:09:00.575313 ==
6484 13:09:00.578631 Dram Type= 6, Freq= 0, CH_0, rank 1
6485 13:09:00.581831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 13:09:00.581903 ==
6487 13:09:00.585067 RX Vref Scan: 0
6488 13:09:00.585188
6489 13:09:00.588738 RX Vref 0 -> 0, step: 1
6490 13:09:00.588814
6491 13:09:00.588896 RX Delay -410 -> 252, step: 16
6492 13:09:00.595295 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6493 13:09:00.598423 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6494 13:09:00.601874 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6495 13:09:00.605011 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6496 13:09:00.611803 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6497 13:09:00.615066 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6498 13:09:00.618231 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6499 13:09:00.624861 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6500 13:09:00.628526 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6501 13:09:00.631781 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6502 13:09:00.634992 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6503 13:09:00.641425 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6504 13:09:00.644613 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6505 13:09:00.648167 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6506 13:09:00.651652 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6507 13:09:00.658191 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6508 13:09:00.658268 ==
6509 13:09:00.661013 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 13:09:00.664431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 13:09:00.664509 ==
6512 13:09:00.664569 DQS Delay:
6513 13:09:00.667797 DQS0 = 35, DQS1 = 59
6514 13:09:00.667874 DQM Delay:
6515 13:09:00.671398 DQM0 = 7, DQM1 = 17
6516 13:09:00.671474 DQ Delay:
6517 13:09:00.674415 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6518 13:09:00.677643 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6519 13:09:00.680844 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6520 13:09:00.684039 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6521 13:09:00.684115
6522 13:09:00.684174
6523 13:09:00.684228 ==
6524 13:09:00.687930 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 13:09:00.690758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 13:09:00.690837 ==
6527 13:09:00.690896
6528 13:09:00.690950
6529 13:09:00.694399 TX Vref Scan disable
6530 13:09:00.697621 == TX Byte 0 ==
6531 13:09:00.700489 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6532 13:09:00.703943 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6533 13:09:00.707417 == TX Byte 1 ==
6534 13:09:00.710465 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6535 13:09:00.713874 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6536 13:09:00.713950 ==
6537 13:09:00.717239 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 13:09:00.720529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 13:09:00.720606 ==
6540 13:09:00.723777
6541 13:09:00.723852
6542 13:09:00.723929 TX Vref Scan disable
6543 13:09:00.727339 == TX Byte 0 ==
6544 13:09:00.730122 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6545 13:09:00.733678 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6546 13:09:00.737260 == TX Byte 1 ==
6547 13:09:00.740844 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6548 13:09:00.743460 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6549 13:09:00.743553
6550 13:09:00.743644 [DATLAT]
6551 13:09:00.746916 Freq=400, CH0 RK1
6552 13:09:00.746992
6553 13:09:00.749960 DATLAT Default: 0xe
6554 13:09:00.750036 0, 0xFFFF, sum = 0
6555 13:09:00.753238 1, 0xFFFF, sum = 0
6556 13:09:00.753315 2, 0xFFFF, sum = 0
6557 13:09:00.756917 3, 0xFFFF, sum = 0
6558 13:09:00.756996 4, 0xFFFF, sum = 0
6559 13:09:00.760285 5, 0xFFFF, sum = 0
6560 13:09:00.760362 6, 0xFFFF, sum = 0
6561 13:09:00.763494 7, 0xFFFF, sum = 0
6562 13:09:00.763571 8, 0xFFFF, sum = 0
6563 13:09:00.766563 9, 0xFFFF, sum = 0
6564 13:09:00.766640 10, 0xFFFF, sum = 0
6565 13:09:00.769802 11, 0xFFFF, sum = 0
6566 13:09:00.769879 12, 0xFFFF, sum = 0
6567 13:09:00.772828 13, 0x0, sum = 1
6568 13:09:00.772904 14, 0x0, sum = 2
6569 13:09:00.776163 15, 0x0, sum = 3
6570 13:09:00.776240 16, 0x0, sum = 4
6571 13:09:00.779507 best_step = 14
6572 13:09:00.779610
6573 13:09:00.779695 ==
6574 13:09:00.783154 Dram Type= 6, Freq= 0, CH_0, rank 1
6575 13:09:00.786521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6576 13:09:00.786616 ==
6577 13:09:00.789845 RX Vref Scan: 0
6578 13:09:00.789921
6579 13:09:00.789980 RX Vref 0 -> 0, step: 1
6580 13:09:00.790035
6581 13:09:00.792701 RX Delay -359 -> 252, step: 8
6582 13:09:00.801248 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6583 13:09:00.804167 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6584 13:09:00.807950 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6585 13:09:00.814318 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6586 13:09:00.817894 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6587 13:09:00.820846 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6588 13:09:00.824400 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6589 13:09:00.830899 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6590 13:09:00.834152 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6591 13:09:00.837612 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6592 13:09:00.840572 iDelay=209, Bit 10, Center -40 (-279 ~ 200) 480
6593 13:09:00.847047 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6594 13:09:00.850745 iDelay=209, Bit 12, Center -44 (-287 ~ 200) 488
6595 13:09:00.854240 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6596 13:09:00.856841 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6597 13:09:00.863416 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6598 13:09:00.863493 ==
6599 13:09:00.866723 Dram Type= 6, Freq= 0, CH_0, rank 1
6600 13:09:00.870446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6601 13:09:00.870522 ==
6602 13:09:00.870581 DQS Delay:
6603 13:09:00.873879 DQS0 = 44, DQS1 = 60
6604 13:09:00.873954 DQM Delay:
6605 13:09:00.876793 DQM0 = 9, DQM1 = 14
6606 13:09:00.876868 DQ Delay:
6607 13:09:00.880294 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6608 13:09:00.883761 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6609 13:09:00.886754 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6610 13:09:00.890109 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6611 13:09:00.890184
6612 13:09:00.890242
6613 13:09:00.899804 [DQSOSCAuto] RK1, (LSB)MR18= 0x958f, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
6614 13:09:00.899881 CH0 RK1: MR19=C0C, MR18=958F
6615 13:09:00.906744 CH0_RK1: MR19=0xC0C, MR18=0x958F, DQSOSC=391, MR23=63, INC=386, DEC=257
6616 13:09:00.909625 [RxdqsGatingPostProcess] freq 400
6617 13:09:00.916165 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6618 13:09:00.919659 best DQS0 dly(2T, 0.5T) = (0, 10)
6619 13:09:00.923302 best DQS1 dly(2T, 0.5T) = (0, 10)
6620 13:09:00.926392 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6621 13:09:00.929874 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6622 13:09:00.932918 best DQS0 dly(2T, 0.5T) = (0, 10)
6623 13:09:00.936785 best DQS1 dly(2T, 0.5T) = (0, 10)
6624 13:09:00.936860 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6625 13:09:00.939873 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6626 13:09:00.942817 Pre-setting of DQS Precalculation
6627 13:09:00.949419 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6628 13:09:00.949496 ==
6629 13:09:00.953040 Dram Type= 6, Freq= 0, CH_1, rank 0
6630 13:09:00.956218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 13:09:00.956295 ==
6632 13:09:00.963002 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6633 13:09:00.969572 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6634 13:09:00.972663 [CA 0] Center 36 (8~64) winsize 57
6635 13:09:00.975656 [CA 1] Center 36 (8~64) winsize 57
6636 13:09:00.979060 [CA 2] Center 36 (8~64) winsize 57
6637 13:09:00.979135 [CA 3] Center 36 (8~64) winsize 57
6638 13:09:00.982422 [CA 4] Center 36 (8~64) winsize 57
6639 13:09:00.985854 [CA 5] Center 36 (8~64) winsize 57
6640 13:09:00.985930
6641 13:09:00.989302 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6642 13:09:00.992785
6643 13:09:00.995584 [CATrainingPosCal] consider 1 rank data
6644 13:09:00.995661 u2DelayCellTimex100 = 270/100 ps
6645 13:09:01.002552 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 13:09:01.005972 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 13:09:01.009056 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 13:09:01.012012 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 13:09:01.015664 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 13:09:01.018674 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 13:09:01.018756
6652 13:09:01.022322 CA PerBit enable=1, Macro0, CA PI delay=36
6653 13:09:01.022398
6654 13:09:01.025726 [CBTSetCACLKResult] CA Dly = 36
6655 13:09:01.028539 CS Dly: 1 (0~32)
6656 13:09:01.028615 ==
6657 13:09:01.032158 Dram Type= 6, Freq= 0, CH_1, rank 1
6658 13:09:01.035172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 13:09:01.035249 ==
6660 13:09:01.042038 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6661 13:09:01.048305 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6662 13:09:01.051307 [CA 0] Center 36 (8~64) winsize 57
6663 13:09:01.051384 [CA 1] Center 36 (8~64) winsize 57
6664 13:09:01.054964 [CA 2] Center 36 (8~64) winsize 57
6665 13:09:01.057965 [CA 3] Center 36 (8~64) winsize 57
6666 13:09:01.061655 [CA 4] Center 36 (8~64) winsize 57
6667 13:09:01.064500 [CA 5] Center 36 (8~64) winsize 57
6668 13:09:01.064576
6669 13:09:01.068196 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6670 13:09:01.068273
6671 13:09:01.074985 [CATrainingPosCal] consider 2 rank data
6672 13:09:01.075061 u2DelayCellTimex100 = 270/100 ps
6673 13:09:01.081524 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 13:09:01.084830 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 13:09:01.087681 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 13:09:01.091029 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 13:09:01.094565 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 13:09:01.097845 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 13:09:01.097922
6680 13:09:01.101530 CA PerBit enable=1, Macro0, CA PI delay=36
6681 13:09:01.101606
6682 13:09:01.104167 [CBTSetCACLKResult] CA Dly = 36
6683 13:09:01.107706 CS Dly: 1 (0~32)
6684 13:09:01.107782
6685 13:09:01.111261 ----->DramcWriteLeveling(PI) begin...
6686 13:09:01.111339 ==
6687 13:09:01.114581 Dram Type= 6, Freq= 0, CH_1, rank 0
6688 13:09:01.117451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 13:09:01.117528 ==
6690 13:09:01.121097 Write leveling (Byte 0): 40 => 8
6691 13:09:01.124499 Write leveling (Byte 1): 40 => 8
6692 13:09:01.127301 DramcWriteLeveling(PI) end<-----
6693 13:09:01.127377
6694 13:09:01.127435 ==
6695 13:09:01.130787 Dram Type= 6, Freq= 0, CH_1, rank 0
6696 13:09:01.134322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 13:09:01.134399 ==
6698 13:09:01.137154 [Gating] SW mode calibration
6699 13:09:01.144092 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6700 13:09:01.150521 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6701 13:09:01.153930 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6702 13:09:01.157317 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6703 13:09:01.163807 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6704 13:09:01.166884 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6705 13:09:01.170365 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6706 13:09:01.177281 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6707 13:09:01.180072 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6708 13:09:01.183703 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6709 13:09:01.190084 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6710 13:09:01.193468 Total UI for P1: 0, mck2ui 16
6711 13:09:01.196483 best dqsien dly found for B0: ( 0, 14, 24)
6712 13:09:01.199588 Total UI for P1: 0, mck2ui 16
6713 13:09:01.202971 best dqsien dly found for B1: ( 0, 14, 24)
6714 13:09:01.206235 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6715 13:09:01.209600 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6716 13:09:01.209676
6717 13:09:01.212713 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6718 13:09:01.216348 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6719 13:09:01.219542 [Gating] SW calibration Done
6720 13:09:01.219618 ==
6721 13:09:01.222872 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 13:09:01.226027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 13:09:01.229437 ==
6724 13:09:01.229514 RX Vref Scan: 0
6725 13:09:01.229573
6726 13:09:01.232923 RX Vref 0 -> 0, step: 1
6727 13:09:01.232999
6728 13:09:01.236566 RX Delay -410 -> 252, step: 16
6729 13:09:01.239575 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6730 13:09:01.242671 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6731 13:09:01.246390 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6732 13:09:01.252468 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6733 13:09:01.255874 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6734 13:09:01.259163 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6735 13:09:01.262717 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6736 13:09:01.269099 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6737 13:09:01.271988 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6738 13:09:01.275492 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6739 13:09:01.279009 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6740 13:09:01.285268 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6741 13:09:01.288887 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6742 13:09:01.291912 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6743 13:09:01.298396 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6744 13:09:01.302135 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6745 13:09:01.302211 ==
6746 13:09:01.305075 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 13:09:01.308329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 13:09:01.308406 ==
6749 13:09:01.311452 DQS Delay:
6750 13:09:01.311529 DQS0 = 43, DQS1 = 51
6751 13:09:01.315019 DQM Delay:
6752 13:09:01.315096 DQM0 = 13, DQM1 = 13
6753 13:09:01.315156 DQ Delay:
6754 13:09:01.318259 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6755 13:09:01.321711 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6756 13:09:01.325054 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6757 13:09:01.328150 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6758 13:09:01.328226
6759 13:09:01.328285
6760 13:09:01.328339 ==
6761 13:09:01.331703 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 13:09:01.338240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 13:09:01.338317 ==
6764 13:09:01.338377
6765 13:09:01.338432
6766 13:09:01.338484 TX Vref Scan disable
6767 13:09:01.341288 == TX Byte 0 ==
6768 13:09:01.344923 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6769 13:09:01.348239 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6770 13:09:01.351474 == TX Byte 1 ==
6771 13:09:01.354469 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6772 13:09:01.357748 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6773 13:09:01.357824 ==
6774 13:09:01.360828 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 13:09:01.367414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 13:09:01.367491 ==
6777 13:09:01.367551
6778 13:09:01.367606
6779 13:09:01.367659 TX Vref Scan disable
6780 13:09:01.370863 == TX Byte 0 ==
6781 13:09:01.374517 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6782 13:09:01.378148 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6783 13:09:01.381054 == TX Byte 1 ==
6784 13:09:01.384535 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6785 13:09:01.387455 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6786 13:09:01.387531
6787 13:09:01.391030 [DATLAT]
6788 13:09:01.391105 Freq=400, CH1 RK0
6789 13:09:01.391164
6790 13:09:01.394473 DATLAT Default: 0xf
6791 13:09:01.394549 0, 0xFFFF, sum = 0
6792 13:09:01.397308 1, 0xFFFF, sum = 0
6793 13:09:01.397385 2, 0xFFFF, sum = 0
6794 13:09:01.400833 3, 0xFFFF, sum = 0
6795 13:09:01.400910 4, 0xFFFF, sum = 0
6796 13:09:01.404349 5, 0xFFFF, sum = 0
6797 13:09:01.404425 6, 0xFFFF, sum = 0
6798 13:09:01.407341 7, 0xFFFF, sum = 0
6799 13:09:01.410748 8, 0xFFFF, sum = 0
6800 13:09:01.410829 9, 0xFFFF, sum = 0
6801 13:09:01.414358 10, 0xFFFF, sum = 0
6802 13:09:01.414434 11, 0xFFFF, sum = 0
6803 13:09:01.417487 12, 0xFFFF, sum = 0
6804 13:09:01.417563 13, 0x0, sum = 1
6805 13:09:01.420668 14, 0x0, sum = 2
6806 13:09:01.420745 15, 0x0, sum = 3
6807 13:09:01.423719 16, 0x0, sum = 4
6808 13:09:01.423795 best_step = 14
6809 13:09:01.423885
6810 13:09:01.423940 ==
6811 13:09:01.427194 Dram Type= 6, Freq= 0, CH_1, rank 0
6812 13:09:01.430354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 13:09:01.430430 ==
6814 13:09:01.433898 RX Vref Scan: 1
6815 13:09:01.433973
6816 13:09:01.437425 RX Vref 0 -> 0, step: 1
6817 13:09:01.437500
6818 13:09:01.440167 RX Delay -343 -> 252, step: 8
6819 13:09:01.440274
6820 13:09:01.440333 Set Vref, RX VrefLevel [Byte0]: 54
6821 13:09:01.443761 [Byte1]: 54
6822 13:09:01.449661
6823 13:09:01.449737 Final RX Vref Byte 0 = 54 to rank0
6824 13:09:01.452646 Final RX Vref Byte 1 = 54 to rank0
6825 13:09:01.456206 Final RX Vref Byte 0 = 54 to rank1
6826 13:09:01.459129 Final RX Vref Byte 1 = 54 to rank1==
6827 13:09:01.462689 Dram Type= 6, Freq= 0, CH_1, rank 0
6828 13:09:01.468827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 13:09:01.468903 ==
6830 13:09:01.468962 DQS Delay:
6831 13:09:01.472135 DQS0 = 44, DQS1 = 52
6832 13:09:01.472211 DQM Delay:
6833 13:09:01.472270 DQM0 = 12, DQM1 = 11
6834 13:09:01.475693 DQ Delay:
6835 13:09:01.478836 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6836 13:09:01.482407 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6837 13:09:01.482483 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6838 13:09:01.485778 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6839 13:09:01.488676
6840 13:09:01.488751
6841 13:09:01.495489 [DQSOSCAuto] RK0, (LSB)MR18= 0x7097, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 395 ps
6842 13:09:01.499057 CH1 RK0: MR19=C0C, MR18=7097
6843 13:09:01.505399 CH1_RK0: MR19=0xC0C, MR18=0x7097, DQSOSC=390, MR23=63, INC=388, DEC=258
6844 13:09:01.505476 ==
6845 13:09:01.509013 Dram Type= 6, Freq= 0, CH_1, rank 1
6846 13:09:01.511820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 13:09:01.511925 ==
6848 13:09:01.515457 [Gating] SW mode calibration
6849 13:09:01.521807 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6850 13:09:01.528858 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6851 13:09:01.531631 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6852 13:09:01.535313 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6853 13:09:01.541563 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6854 13:09:01.545024 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6855 13:09:01.548139 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6856 13:09:01.554715 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6857 13:09:01.558162 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6858 13:09:01.561100 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6859 13:09:01.568181 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6860 13:09:01.571468 Total UI for P1: 0, mck2ui 16
6861 13:09:01.574755 best dqsien dly found for B0: ( 0, 14, 24)
6862 13:09:01.577597 Total UI for P1: 0, mck2ui 16
6863 13:09:01.581409 best dqsien dly found for B1: ( 0, 14, 24)
6864 13:09:01.584497 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6865 13:09:01.588035 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6866 13:09:01.588110
6867 13:09:01.590843 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6868 13:09:01.594613 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6869 13:09:01.597501 [Gating] SW calibration Done
6870 13:09:01.597577 ==
6871 13:09:01.601052 Dram Type= 6, Freq= 0, CH_1, rank 1
6872 13:09:01.604642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 13:09:01.604718 ==
6874 13:09:01.607549 RX Vref Scan: 0
6875 13:09:01.607626
6876 13:09:01.610931 RX Vref 0 -> 0, step: 1
6877 13:09:01.611006
6878 13:09:01.611065 RX Delay -410 -> 252, step: 16
6879 13:09:01.617490 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6880 13:09:01.621097 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6881 13:09:01.624130 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6882 13:09:01.627211 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6883 13:09:01.634347 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6884 13:09:01.637290 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6885 13:09:01.640630 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6886 13:09:01.647390 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6887 13:09:01.650751 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6888 13:09:01.654161 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6889 13:09:01.657430 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6890 13:09:01.664237 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6891 13:09:01.667036 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6892 13:09:01.670198 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6893 13:09:01.673458 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6894 13:09:01.680603 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6895 13:09:01.680681 ==
6896 13:09:01.683988 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 13:09:01.686898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 13:09:01.686975 ==
6899 13:09:01.687036 DQS Delay:
6900 13:09:01.690338 DQS0 = 43, DQS1 = 51
6901 13:09:01.690414 DQM Delay:
6902 13:09:01.693771 DQM0 = 12, DQM1 = 14
6903 13:09:01.693848 DQ Delay:
6904 13:09:01.696634 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6905 13:09:01.699984 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6906 13:09:01.703401 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6907 13:09:01.706421 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =16
6908 13:09:01.706497
6909 13:09:01.706556
6910 13:09:01.706610 ==
6911 13:09:01.709997 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 13:09:01.713006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 13:09:01.713083 ==
6914 13:09:01.713162
6915 13:09:01.716693
6916 13:09:01.716769 TX Vref Scan disable
6917 13:09:01.720005 == TX Byte 0 ==
6918 13:09:01.722989 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6919 13:09:01.726579 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6920 13:09:01.729544 == TX Byte 1 ==
6921 13:09:01.732932 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6922 13:09:01.736295 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6923 13:09:01.736372 ==
6924 13:09:01.739703 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 13:09:01.742733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 13:09:01.746526 ==
6927 13:09:01.746602
6928 13:09:01.746683
6929 13:09:01.746740 TX Vref Scan disable
6930 13:09:01.749578 == TX Byte 0 ==
6931 13:09:01.752704 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6932 13:09:01.756547 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6933 13:09:01.759523 == TX Byte 1 ==
6934 13:09:01.763009 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6935 13:09:01.766186 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6936 13:09:01.766261
6937 13:09:01.769106 [DATLAT]
6938 13:09:01.769220 Freq=400, CH1 RK1
6939 13:09:01.769279
6940 13:09:01.772432 DATLAT Default: 0xe
6941 13:09:01.772507 0, 0xFFFF, sum = 0
6942 13:09:01.775787 1, 0xFFFF, sum = 0
6943 13:09:01.775864 2, 0xFFFF, sum = 0
6944 13:09:01.779079 3, 0xFFFF, sum = 0
6945 13:09:01.779160 4, 0xFFFF, sum = 0
6946 13:09:01.782744 5, 0xFFFF, sum = 0
6947 13:09:01.782822 6, 0xFFFF, sum = 0
6948 13:09:01.785902 7, 0xFFFF, sum = 0
6949 13:09:01.785980 8, 0xFFFF, sum = 0
6950 13:09:01.788891 9, 0xFFFF, sum = 0
6951 13:09:01.788969 10, 0xFFFF, sum = 0
6952 13:09:01.792670 11, 0xFFFF, sum = 0
6953 13:09:01.792747 12, 0xFFFF, sum = 0
6954 13:09:01.795718 13, 0x0, sum = 1
6955 13:09:01.795795 14, 0x0, sum = 2
6956 13:09:01.798950 15, 0x0, sum = 3
6957 13:09:01.799028 16, 0x0, sum = 4
6958 13:09:01.802587 best_step = 14
6959 13:09:01.802663
6960 13:09:01.802722 ==
6961 13:09:01.805375 Dram Type= 6, Freq= 0, CH_1, rank 1
6962 13:09:01.808915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6963 13:09:01.808991 ==
6964 13:09:01.811809 RX Vref Scan: 0
6965 13:09:01.811885
6966 13:09:01.811944 RX Vref 0 -> 0, step: 1
6967 13:09:01.811999
6968 13:09:01.815348 RX Delay -343 -> 252, step: 8
6969 13:09:01.823586 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6970 13:09:01.827228 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6971 13:09:01.830120 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6972 13:09:01.836460 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6973 13:09:01.840214 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6974 13:09:01.843527 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6975 13:09:01.846539 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6976 13:09:01.853287 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6977 13:09:01.856731 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6978 13:09:01.860003 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6979 13:09:01.863321 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6980 13:09:01.869784 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6981 13:09:01.873016 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6982 13:09:01.876931 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6983 13:09:01.880120 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6984 13:09:01.886170 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6985 13:09:01.886251 ==
6986 13:09:01.889687 Dram Type= 6, Freq= 0, CH_1, rank 1
6987 13:09:01.892637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6988 13:09:01.892715 ==
6989 13:09:01.892775 DQS Delay:
6990 13:09:01.896089 DQS0 = 48, DQS1 = 52
6991 13:09:01.896165 DQM Delay:
6992 13:09:01.899556 DQM0 = 11, DQM1 = 10
6993 13:09:01.899633 DQ Delay:
6994 13:09:01.902489 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
6995 13:09:01.906323 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6996 13:09:01.909394 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6997 13:09:01.912737 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6998 13:09:01.912813
6999 13:09:01.912871
7000 13:09:01.922207 [DQSOSCAuto] RK1, (LSB)MR18= 0x7bb2, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
7001 13:09:01.922284 CH1 RK1: MR19=C0C, MR18=7BB2
7002 13:09:01.929260 CH1_RK1: MR19=0xC0C, MR18=0x7BB2, DQSOSC=387, MR23=63, INC=394, DEC=262
7003 13:09:01.932197 [RxdqsGatingPostProcess] freq 400
7004 13:09:01.939417 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7005 13:09:01.942067 best DQS0 dly(2T, 0.5T) = (0, 10)
7006 13:09:01.945505 best DQS1 dly(2T, 0.5T) = (0, 10)
7007 13:09:01.949475 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7008 13:09:01.952016 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7009 13:09:01.955641 best DQS0 dly(2T, 0.5T) = (0, 10)
7010 13:09:01.958521 best DQS1 dly(2T, 0.5T) = (0, 10)
7011 13:09:01.961997 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7012 13:09:01.965579 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7013 13:09:01.965656 Pre-setting of DQS Precalculation
7014 13:09:01.971956 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7015 13:09:01.978413 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7016 13:09:01.985028 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7017 13:09:01.985106
7018 13:09:01.985204
7019 13:09:01.988237 [Calibration Summary] 800 Mbps
7020 13:09:01.991535 CH 0, Rank 0
7021 13:09:01.991610 SW Impedance : PASS
7022 13:09:01.995130 DUTY Scan : NO K
7023 13:09:01.998291 ZQ Calibration : PASS
7024 13:09:01.998366 Jitter Meter : NO K
7025 13:09:02.001394 CBT Training : PASS
7026 13:09:02.004674 Write leveling : PASS
7027 13:09:02.004749 RX DQS gating : PASS
7028 13:09:02.008316 RX DQ/DQS(RDDQC) : PASS
7029 13:09:02.011230 TX DQ/DQS : PASS
7030 13:09:02.011306 RX DATLAT : PASS
7031 13:09:02.014631 RX DQ/DQS(Engine): PASS
7032 13:09:02.017940 TX OE : NO K
7033 13:09:02.018015 All Pass.
7034 13:09:02.018074
7035 13:09:02.018129 CH 0, Rank 1
7036 13:09:02.021304 SW Impedance : PASS
7037 13:09:02.024516 DUTY Scan : NO K
7038 13:09:02.024591 ZQ Calibration : PASS
7039 13:09:02.028176 Jitter Meter : NO K
7040 13:09:02.028251 CBT Training : PASS
7041 13:09:02.030968 Write leveling : NO K
7042 13:09:02.034356 RX DQS gating : PASS
7043 13:09:02.034432 RX DQ/DQS(RDDQC) : PASS
7044 13:09:02.037924 TX DQ/DQS : PASS
7045 13:09:02.040765 RX DATLAT : PASS
7046 13:09:02.040840 RX DQ/DQS(Engine): PASS
7047 13:09:02.044732 TX OE : NO K
7048 13:09:02.044808 All Pass.
7049 13:09:02.044866
7050 13:09:02.047281 CH 1, Rank 0
7051 13:09:02.047356 SW Impedance : PASS
7052 13:09:02.050750 DUTY Scan : NO K
7053 13:09:02.054303 ZQ Calibration : PASS
7054 13:09:02.054378 Jitter Meter : NO K
7055 13:09:02.057408 CBT Training : PASS
7056 13:09:02.061000 Write leveling : PASS
7057 13:09:02.061075 RX DQS gating : PASS
7058 13:09:02.063922 RX DQ/DQS(RDDQC) : PASS
7059 13:09:02.067548 TX DQ/DQS : PASS
7060 13:09:02.067624 RX DATLAT : PASS
7061 13:09:02.070637 RX DQ/DQS(Engine): PASS
7062 13:09:02.073917 TX OE : NO K
7063 13:09:02.073992 All Pass.
7064 13:09:02.074050
7065 13:09:02.074104 CH 1, Rank 1
7066 13:09:02.077381 SW Impedance : PASS
7067 13:09:02.080241 DUTY Scan : NO K
7068 13:09:02.080317 ZQ Calibration : PASS
7069 13:09:02.083777 Jitter Meter : NO K
7070 13:09:02.087346 CBT Training : PASS
7071 13:09:02.087422 Write leveling : NO K
7072 13:09:02.090359 RX DQS gating : PASS
7073 13:09:02.093356 RX DQ/DQS(RDDQC) : PASS
7074 13:09:02.093431 TX DQ/DQS : PASS
7075 13:09:02.097014 RX DATLAT : PASS
7076 13:09:02.100039 RX DQ/DQS(Engine): PASS
7077 13:09:02.100114 TX OE : NO K
7078 13:09:02.100174 All Pass.
7079 13:09:02.103495
7080 13:09:02.103570 DramC Write-DBI off
7081 13:09:02.106561 PER_BANK_REFRESH: Hybrid Mode
7082 13:09:02.106636 TX_TRACKING: ON
7083 13:09:02.116673 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7084 13:09:02.120117 [FAST_K] Save calibration result to emmc
7085 13:09:02.123471 dramc_set_vcore_voltage set vcore to 725000
7086 13:09:02.126770 Read voltage for 1600, 0
7087 13:09:02.126845 Vio18 = 0
7088 13:09:02.129826 Vcore = 725000
7089 13:09:02.129902 Vdram = 0
7090 13:09:02.129960 Vddq = 0
7091 13:09:02.133049 Vmddr = 0
7092 13:09:02.136643 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7093 13:09:02.143057 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7094 13:09:02.143133 MEM_TYPE=3, freq_sel=13
7095 13:09:02.146486 sv_algorithm_assistance_LP4_3733
7096 13:09:02.152959 ============ PULL DRAM RESETB DOWN ============
7097 13:09:02.155769 ========== PULL DRAM RESETB DOWN end =========
7098 13:09:02.159193 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7099 13:09:02.162618 ===================================
7100 13:09:02.166074 LPDDR4 DRAM CONFIGURATION
7101 13:09:02.169376 ===================================
7102 13:09:02.172320 EX_ROW_EN[0] = 0x0
7103 13:09:02.172396 EX_ROW_EN[1] = 0x0
7104 13:09:02.175741 LP4Y_EN = 0x0
7105 13:09:02.175816 WORK_FSP = 0x1
7106 13:09:02.179212 WL = 0x5
7107 13:09:02.179288 RL = 0x5
7108 13:09:02.182136 BL = 0x2
7109 13:09:02.182210 RPST = 0x0
7110 13:09:02.185609 RD_PRE = 0x0
7111 13:09:02.185684 WR_PRE = 0x1
7112 13:09:02.188697 WR_PST = 0x1
7113 13:09:02.188773 DBI_WR = 0x0
7114 13:09:02.191962 DBI_RD = 0x0
7115 13:09:02.192037 OTF = 0x1
7116 13:09:02.195418 ===================================
7117 13:09:02.198908 ===================================
7118 13:09:02.202055 ANA top config
7119 13:09:02.205362 ===================================
7120 13:09:02.208802 DLL_ASYNC_EN = 0
7121 13:09:02.208878 ALL_SLAVE_EN = 0
7122 13:09:02.211953 NEW_RANK_MODE = 1
7123 13:09:02.214919 DLL_IDLE_MODE = 1
7124 13:09:02.218175 LP45_APHY_COMB_EN = 1
7125 13:09:02.221939 TX_ODT_DIS = 0
7126 13:09:02.222014 NEW_8X_MODE = 1
7127 13:09:02.225313 ===================================
7128 13:09:02.228466 ===================================
7129 13:09:02.231648 data_rate = 3200
7130 13:09:02.234838 CKR = 1
7131 13:09:02.237902 DQ_P2S_RATIO = 8
7132 13:09:02.241472 ===================================
7133 13:09:02.244694 CA_P2S_RATIO = 8
7134 13:09:02.248189 DQ_CA_OPEN = 0
7135 13:09:02.248264 DQ_SEMI_OPEN = 0
7136 13:09:02.251177 CA_SEMI_OPEN = 0
7137 13:09:02.254602 CA_FULL_RATE = 0
7138 13:09:02.258063 DQ_CKDIV4_EN = 0
7139 13:09:02.261552 CA_CKDIV4_EN = 0
7140 13:09:02.264572 CA_PREDIV_EN = 0
7141 13:09:02.264647 PH8_DLY = 12
7142 13:09:02.267796 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7143 13:09:02.271514 DQ_AAMCK_DIV = 4
7144 13:09:02.274817 CA_AAMCK_DIV = 4
7145 13:09:02.277925 CA_ADMCK_DIV = 4
7146 13:09:02.280932 DQ_TRACK_CA_EN = 0
7147 13:09:02.284460 CA_PICK = 1600
7148 13:09:02.287778 CA_MCKIO = 1600
7149 13:09:02.287854 MCKIO_SEMI = 0
7150 13:09:02.290719 PLL_FREQ = 3068
7151 13:09:02.294406 DQ_UI_PI_RATIO = 32
7152 13:09:02.297823 CA_UI_PI_RATIO = 0
7153 13:09:02.300820 ===================================
7154 13:09:02.304141 ===================================
7155 13:09:02.307251 memory_type:LPDDR4
7156 13:09:02.307327 GP_NUM : 10
7157 13:09:02.310648 SRAM_EN : 1
7158 13:09:02.313938 MD32_EN : 0
7159 13:09:02.317432 ===================================
7160 13:09:02.317508 [ANA_INIT] >>>>>>>>>>>>>>
7161 13:09:02.321012 <<<<<< [CONFIGURE PHASE]: ANA_TX
7162 13:09:02.323739 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7163 13:09:02.327457 ===================================
7164 13:09:02.330875 data_rate = 3200,PCW = 0X7600
7165 13:09:02.333846 ===================================
7166 13:09:02.337152 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7167 13:09:02.343789 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7168 13:09:02.347001 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7169 13:09:02.353771 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7170 13:09:02.356648 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7171 13:09:02.360092 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7172 13:09:02.363036 [ANA_INIT] flow start
7173 13:09:02.363111 [ANA_INIT] PLL >>>>>>>>
7174 13:09:02.366586 [ANA_INIT] PLL <<<<<<<<
7175 13:09:02.370228 [ANA_INIT] MIDPI >>>>>>>>
7176 13:09:02.370304 [ANA_INIT] MIDPI <<<<<<<<
7177 13:09:02.373443 [ANA_INIT] DLL >>>>>>>>
7178 13:09:02.376803 [ANA_INIT] DLL <<<<<<<<
7179 13:09:02.376878 [ANA_INIT] flow end
7180 13:09:02.383271 ============ LP4 DIFF to SE enter ============
7181 13:09:02.386913 ============ LP4 DIFF to SE exit ============
7182 13:09:02.386990 [ANA_INIT] <<<<<<<<<<<<<
7183 13:09:02.389599 [Flow] Enable top DCM control >>>>>
7184 13:09:02.393062 [Flow] Enable top DCM control <<<<<
7185 13:09:02.396565 Enable DLL master slave shuffle
7186 13:09:02.403006 ==============================================================
7187 13:09:02.406085 Gating Mode config
7188 13:09:02.409448 ==============================================================
7189 13:09:02.412716 Config description:
7190 13:09:02.422510 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7191 13:09:02.429416 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7192 13:09:02.432700 SELPH_MODE 0: By rank 1: By Phase
7193 13:09:02.439009 ==============================================================
7194 13:09:02.442421 GAT_TRACK_EN = 1
7195 13:09:02.445612 RX_GATING_MODE = 2
7196 13:09:02.448939 RX_GATING_TRACK_MODE = 2
7197 13:09:02.452193 SELPH_MODE = 1
7198 13:09:02.455523 PICG_EARLY_EN = 1
7199 13:09:02.455599 VALID_LAT_VALUE = 1
7200 13:09:02.462113 ==============================================================
7201 13:09:02.465647 Enter into Gating configuration >>>>
7202 13:09:02.468522 Exit from Gating configuration <<<<
7203 13:09:02.472096 Enter into DVFS_PRE_config >>>>>
7204 13:09:02.482020 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7205 13:09:02.484983 Exit from DVFS_PRE_config <<<<<
7206 13:09:02.488739 Enter into PICG configuration >>>>
7207 13:09:02.492043 Exit from PICG configuration <<<<
7208 13:09:02.495480 [RX_INPUT] configuration >>>>>
7209 13:09:02.498422 [RX_INPUT] configuration <<<<<
7210 13:09:02.504969 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7211 13:09:02.508354 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7212 13:09:02.514794 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7213 13:09:02.521152 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7214 13:09:02.527670 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7215 13:09:02.534570 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7216 13:09:02.537837 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7217 13:09:02.540951 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7218 13:09:02.544403 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7219 13:09:02.550913 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7220 13:09:02.553898 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7221 13:09:02.557667 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7222 13:09:02.560728 ===================================
7223 13:09:02.563742 LPDDR4 DRAM CONFIGURATION
7224 13:09:02.567328 ===================================
7225 13:09:02.570481 EX_ROW_EN[0] = 0x0
7226 13:09:02.570557 EX_ROW_EN[1] = 0x0
7227 13:09:02.573945 LP4Y_EN = 0x0
7228 13:09:02.574020 WORK_FSP = 0x1
7229 13:09:02.577299 WL = 0x5
7230 13:09:02.577400 RL = 0x5
7231 13:09:02.580344 BL = 0x2
7232 13:09:02.580419 RPST = 0x0
7233 13:09:02.584021 RD_PRE = 0x0
7234 13:09:02.584097 WR_PRE = 0x1
7235 13:09:02.587255 WR_PST = 0x1
7236 13:09:02.587330 DBI_WR = 0x0
7237 13:09:02.590674 DBI_RD = 0x0
7238 13:09:02.590749 OTF = 0x1
7239 13:09:02.593687 ===================================
7240 13:09:02.600036 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7241 13:09:02.603698 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7242 13:09:02.606929 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7243 13:09:02.609936 ===================================
7244 13:09:02.613545 LPDDR4 DRAM CONFIGURATION
7245 13:09:02.616574 ===================================
7246 13:09:02.619979 EX_ROW_EN[0] = 0x10
7247 13:09:02.620057 EX_ROW_EN[1] = 0x0
7248 13:09:02.623482 LP4Y_EN = 0x0
7249 13:09:02.623556 WORK_FSP = 0x1
7250 13:09:02.626400 WL = 0x5
7251 13:09:02.626475 RL = 0x5
7252 13:09:02.629987 BL = 0x2
7253 13:09:02.630062 RPST = 0x0
7254 13:09:02.633357 RD_PRE = 0x0
7255 13:09:02.633433 WR_PRE = 0x1
7256 13:09:02.636374 WR_PST = 0x1
7257 13:09:02.639838 DBI_WR = 0x0
7258 13:09:02.639938 DBI_RD = 0x0
7259 13:09:02.642864 OTF = 0x1
7260 13:09:02.646648 ===================================
7261 13:09:02.649668 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7262 13:09:02.652979 ==
7263 13:09:02.653054 Dram Type= 6, Freq= 0, CH_0, rank 0
7264 13:09:02.659164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7265 13:09:02.659241 ==
7266 13:09:02.663049 [Duty_Offset_Calibration]
7267 13:09:02.663125 B0:2 B1:0 CA:4
7268 13:09:02.663184
7269 13:09:02.666211 [DutyScan_Calibration_Flow] k_type=0
7270 13:09:02.675157
7271 13:09:02.675232 ==CLK 0==
7272 13:09:02.678169 Final CLK duty delay cell = -4
7273 13:09:02.681939 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7274 13:09:02.684825 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7275 13:09:02.688234 [-4] AVG Duty = 4922%(X100)
7276 13:09:02.688332
7277 13:09:02.691859 CH0 CLK Duty spec in!! Max-Min= 156%
7278 13:09:02.694744 [DutyScan_Calibration_Flow] ====Done====
7279 13:09:02.694820
7280 13:09:02.698390 [DutyScan_Calibration_Flow] k_type=1
7281 13:09:02.715128
7282 13:09:02.715231 ==DQS 0 ==
7283 13:09:02.718661 Final DQS duty delay cell = 0
7284 13:09:02.722195 [0] MAX Duty = 5218%(X100), DQS PI = 38
7285 13:09:02.725262 [0] MIN Duty = 5093%(X100), DQS PI = 6
7286 13:09:02.728196 [0] AVG Duty = 5155%(X100)
7287 13:09:02.728288
7288 13:09:02.728360 ==DQS 1 ==
7289 13:09:02.731635 Final DQS duty delay cell = 0
7290 13:09:02.735400 [0] MAX Duty = 5187%(X100), DQS PI = 2
7291 13:09:02.738546 [0] MIN Duty = 4969%(X100), DQS PI = 12
7292 13:09:02.741800 [0] AVG Duty = 5078%(X100)
7293 13:09:02.741904
7294 13:09:02.744910 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7295 13:09:02.744986
7296 13:09:02.748579 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7297 13:09:02.751936 [DutyScan_Calibration_Flow] ====Done====
7298 13:09:02.752013
7299 13:09:02.755018 [DutyScan_Calibration_Flow] k_type=3
7300 13:09:02.772741
7301 13:09:02.772819 ==DQM 0 ==
7302 13:09:02.775739 Final DQM duty delay cell = 0
7303 13:09:02.779064 [0] MAX Duty = 5124%(X100), DQS PI = 22
7304 13:09:02.782224 [0] MIN Duty = 4844%(X100), DQS PI = 56
7305 13:09:02.785486 [0] AVG Duty = 4984%(X100)
7306 13:09:02.785563
7307 13:09:02.785622 ==DQM 1 ==
7308 13:09:02.788930 Final DQM duty delay cell = 0
7309 13:09:02.792637 [0] MAX Duty = 5000%(X100), DQS PI = 4
7310 13:09:02.795847 [0] MIN Duty = 4844%(X100), DQS PI = 10
7311 13:09:02.798632 [0] AVG Duty = 4922%(X100)
7312 13:09:02.798707
7313 13:09:02.802385 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7314 13:09:02.802461
7315 13:09:02.805333 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7316 13:09:02.808697 [DutyScan_Calibration_Flow] ====Done====
7317 13:09:02.808773
7318 13:09:02.811997 [DutyScan_Calibration_Flow] k_type=2
7319 13:09:02.829695
7320 13:09:02.829770 ==DQ 0 ==
7321 13:09:02.832884 Final DQ duty delay cell = 0
7322 13:09:02.836319 [0] MAX Duty = 5124%(X100), DQS PI = 20
7323 13:09:02.839670 [0] MIN Duty = 4938%(X100), DQS PI = 10
7324 13:09:02.842363 [0] AVG Duty = 5031%(X100)
7325 13:09:02.842438
7326 13:09:02.842496 ==DQ 1 ==
7327 13:09:02.846071 Final DQ duty delay cell = 0
7328 13:09:02.849167 [0] MAX Duty = 5187%(X100), DQS PI = 2
7329 13:09:02.852157 [0] MIN Duty = 4938%(X100), DQS PI = 12
7330 13:09:02.855773 [0] AVG Duty = 5062%(X100)
7331 13:09:02.855849
7332 13:09:02.858799 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7333 13:09:02.858875
7334 13:09:02.862350 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7335 13:09:02.865574 [DutyScan_Calibration_Flow] ====Done====
7336 13:09:02.865649 ==
7337 13:09:02.868964 Dram Type= 6, Freq= 0, CH_1, rank 0
7338 13:09:02.872082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7339 13:09:02.872158 ==
7340 13:09:02.875381 [Duty_Offset_Calibration]
7341 13:09:02.875456 B0:0 B1:-1 CA:3
7342 13:09:02.875515
7343 13:09:02.878946 [DutyScan_Calibration_Flow] k_type=0
7344 13:09:02.889851
7345 13:09:02.889927 ==CLK 0==
7346 13:09:02.893323 Final CLK duty delay cell = 0
7347 13:09:02.896140 [0] MAX Duty = 5187%(X100), DQS PI = 26
7348 13:09:02.899511 [0] MIN Duty = 5031%(X100), DQS PI = 36
7349 13:09:02.903266 [0] AVG Duty = 5109%(X100)
7350 13:09:02.903341
7351 13:09:02.906219 CH1 CLK Duty spec in!! Max-Min= 156%
7352 13:09:02.909928 [DutyScan_Calibration_Flow] ====Done====
7353 13:09:02.910002
7354 13:09:02.912932 [DutyScan_Calibration_Flow] k_type=1
7355 13:09:02.928791
7356 13:09:02.928867 ==DQS 0 ==
7357 13:09:02.931932 Final DQS duty delay cell = 0
7358 13:09:02.935399 [0] MAX Duty = 5218%(X100), DQS PI = 20
7359 13:09:02.938831 [0] MIN Duty = 4938%(X100), DQS PI = 40
7360 13:09:02.941905 [0] AVG Duty = 5078%(X100)
7361 13:09:02.941980
7362 13:09:02.942038 ==DQS 1 ==
7363 13:09:02.945438 Final DQS duty delay cell = -4
7364 13:09:02.948848 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7365 13:09:02.952059 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7366 13:09:02.955270 [-4] AVG Duty = 4906%(X100)
7367 13:09:02.955345
7368 13:09:02.958462 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7369 13:09:02.958537
7370 13:09:02.961914 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7371 13:09:02.964983 [DutyScan_Calibration_Flow] ====Done====
7372 13:09:02.965081
7373 13:09:02.968424 [DutyScan_Calibration_Flow] k_type=3
7374 13:09:02.986060
7375 13:09:02.986141 ==DQM 0 ==
7376 13:09:02.989295 Final DQM duty delay cell = 0
7377 13:09:02.992448 [0] MAX Duty = 5062%(X100), DQS PI = 30
7378 13:09:02.995558 [0] MIN Duty = 4782%(X100), DQS PI = 40
7379 13:09:02.999067 [0] AVG Duty = 4922%(X100)
7380 13:09:02.999170
7381 13:09:02.999227 ==DQM 1 ==
7382 13:09:03.002777 Final DQM duty delay cell = 0
7383 13:09:03.005934 [0] MAX Duty = 4969%(X100), DQS PI = 30
7384 13:09:03.009069 [0] MIN Duty = 4813%(X100), DQS PI = 60
7385 13:09:03.012275 [0] AVG Duty = 4891%(X100)
7386 13:09:03.012349
7387 13:09:03.015386 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7388 13:09:03.015461
7389 13:09:03.018935 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7390 13:09:03.021995 [DutyScan_Calibration_Flow] ====Done====
7391 13:09:03.022105
7392 13:09:03.025153 [DutyScan_Calibration_Flow] k_type=2
7393 13:09:03.041982
7394 13:09:03.042057 ==DQ 0 ==
7395 13:09:03.045236 Final DQ duty delay cell = -4
7396 13:09:03.048772 [-4] MAX Duty = 4969%(X100), DQS PI = 30
7397 13:09:03.052288 [-4] MIN Duty = 4813%(X100), DQS PI = 20
7398 13:09:03.055129 [-4] AVG Duty = 4891%(X100)
7399 13:09:03.055204
7400 13:09:03.055263 ==DQ 1 ==
7401 13:09:03.058671 Final DQ duty delay cell = 0
7402 13:09:03.061602 [0] MAX Duty = 5031%(X100), DQS PI = 32
7403 13:09:03.065172 [0] MIN Duty = 4813%(X100), DQS PI = 60
7404 13:09:03.068783 [0] AVG Duty = 4922%(X100)
7405 13:09:03.068857
7406 13:09:03.071746 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7407 13:09:03.071821
7408 13:09:03.075301 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7409 13:09:03.078265 [DutyScan_Calibration_Flow] ====Done====
7410 13:09:03.081738 nWR fixed to 30
7411 13:09:03.085347 [ModeRegInit_LP4] CH0 RK0
7412 13:09:03.085421 [ModeRegInit_LP4] CH0 RK1
7413 13:09:03.088182 [ModeRegInit_LP4] CH1 RK0
7414 13:09:03.091507 [ModeRegInit_LP4] CH1 RK1
7415 13:09:03.091582 match AC timing 5
7416 13:09:03.097922 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7417 13:09:03.101630 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7418 13:09:03.104992 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7419 13:09:03.111739 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7420 13:09:03.114263 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7421 13:09:03.117621 [MiockJmeterHQA]
7422 13:09:03.117696
7423 13:09:03.121283 [DramcMiockJmeter] u1RxGatingPI = 0
7424 13:09:03.121358 0 : 4255, 4027
7425 13:09:03.121418 4 : 4252, 4027
7426 13:09:03.124225 8 : 4253, 4026
7427 13:09:03.124300 12 : 4252, 4026
7428 13:09:03.127472 16 : 4252, 4027
7429 13:09:03.127548 20 : 4252, 4027
7430 13:09:03.130814 24 : 4252, 4027
7431 13:09:03.130905 28 : 4362, 4137
7432 13:09:03.130980 32 : 4252, 4027
7433 13:09:03.134362 36 : 4252, 4027
7434 13:09:03.134453 40 : 4253, 4026
7435 13:09:03.137835 44 : 4252, 4027
7436 13:09:03.137910 48 : 4252, 4027
7437 13:09:03.140762 52 : 4361, 4138
7438 13:09:03.140837 56 : 4363, 4140
7439 13:09:03.144350 60 : 4250, 4027
7440 13:09:03.144425 64 : 4250, 4027
7441 13:09:03.144484 68 : 4249, 4027
7442 13:09:03.147250 72 : 4252, 4026
7443 13:09:03.147341 76 : 4250, 4027
7444 13:09:03.150766 80 : 4360, 4137
7445 13:09:03.150856 84 : 4250, 4027
7446 13:09:03.154275 88 : 4249, 4027
7447 13:09:03.154350 92 : 4250, 4026
7448 13:09:03.157143 96 : 4250, 2837
7449 13:09:03.157234 100 : 4249, 0
7450 13:09:03.157293 104 : 4250, 0
7451 13:09:03.160731 108 : 4250, 0
7452 13:09:03.160806 112 : 4360, 0
7453 13:09:03.164241 116 : 4250, 0
7454 13:09:03.164316 120 : 4249, 0
7455 13:09:03.164374 124 : 4250, 0
7456 13:09:03.167146 128 : 4249, 0
7457 13:09:03.167223 132 : 4250, 0
7458 13:09:03.167282 136 : 4250, 0
7459 13:09:03.170578 140 : 4250, 0
7460 13:09:03.170653 144 : 4250, 0
7461 13:09:03.173867 148 : 4250, 0
7462 13:09:03.173943 152 : 4249, 0
7463 13:09:03.174001 156 : 4250, 0
7464 13:09:03.177432 160 : 4361, 0
7465 13:09:03.177508 164 : 4360, 0
7466 13:09:03.180333 168 : 4250, 0
7467 13:09:03.180408 172 : 4250, 0
7468 13:09:03.180466 176 : 4250, 0
7469 13:09:03.184088 180 : 4249, 0
7470 13:09:03.184193 184 : 4250, 0
7471 13:09:03.186882 188 : 4250, 0
7472 13:09:03.186958 192 : 4249, 0
7473 13:09:03.187018 196 : 4250, 0
7474 13:09:03.190385 200 : 4250, 0
7475 13:09:03.190462 204 : 4252, 0
7476 13:09:03.193988 208 : 4250, 0
7477 13:09:03.194065 212 : 4361, 0
7478 13:09:03.194125 216 : 4360, 0
7479 13:09:03.196837 220 : 4361, 740
7480 13:09:03.196913 224 : 4250, 4013
7481 13:09:03.200365 228 : 4360, 4137
7482 13:09:03.200441 232 : 4250, 4027
7483 13:09:03.203509 236 : 4361, 4137
7484 13:09:03.203585 240 : 4360, 4137
7485 13:09:03.206612 244 : 4250, 4027
7486 13:09:03.206688 248 : 4250, 4027
7487 13:09:03.210511 252 : 4360, 4138
7488 13:09:03.210587 256 : 4250, 4027
7489 13:09:03.210646 260 : 4250, 4027
7490 13:09:03.213401 264 : 4250, 4027
7491 13:09:03.213487 268 : 4253, 4029
7492 13:09:03.216955 272 : 4249, 4027
7493 13:09:03.217031 276 : 4250, 4026
7494 13:09:03.220330 280 : 4361, 4137
7495 13:09:03.220406 284 : 4250, 4027
7496 13:09:03.223362 288 : 4249, 4027
7497 13:09:03.223438 292 : 4361, 4137
7498 13:09:03.226837 296 : 4250, 4026
7499 13:09:03.226914 300 : 4250, 4026
7500 13:09:03.229823 304 : 4360, 4138
7501 13:09:03.229899 308 : 4250, 4027
7502 13:09:03.233518 312 : 4250, 4026
7503 13:09:03.233595 316 : 4250, 4027
7504 13:09:03.236960 320 : 4255, 4031
7505 13:09:03.237037 324 : 4249, 4027
7506 13:09:03.237097 328 : 4250, 4026
7507 13:09:03.240220 332 : 4361, 3985
7508 13:09:03.240297 336 : 4250, 1435
7509 13:09:03.240357
7510 13:09:03.243374 MIOCK jitter meter ch=0
7511 13:09:03.243483
7512 13:09:03.246352 1T = (336-100) = 236 dly cells
7513 13:09:03.253025 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7514 13:09:03.253102 ==
7515 13:09:03.256414 Dram Type= 6, Freq= 0, CH_0, rank 0
7516 13:09:03.259499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7517 13:09:03.259575 ==
7518 13:09:03.266210 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7519 13:09:03.269920 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7520 13:09:03.272815 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7521 13:09:03.279534 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7522 13:09:03.288722 [CA 0] Center 44 (14~74) winsize 61
7523 13:09:03.292422 [CA 1] Center 43 (13~74) winsize 62
7524 13:09:03.296081 [CA 2] Center 39 (10~68) winsize 59
7525 13:09:03.298685 [CA 3] Center 38 (9~68) winsize 60
7526 13:09:03.302311 [CA 4] Center 36 (7~66) winsize 60
7527 13:09:03.305705 [CA 5] Center 36 (6~66) winsize 61
7528 13:09:03.305780
7529 13:09:03.308537 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7530 13:09:03.308613
7531 13:09:03.312050 [CATrainingPosCal] consider 1 rank data
7532 13:09:03.315532 u2DelayCellTimex100 = 275/100 ps
7533 13:09:03.321856 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7534 13:09:03.325022 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7535 13:09:03.328533 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7536 13:09:03.332095 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7537 13:09:03.334955 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7538 13:09:03.338273 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7539 13:09:03.338349
7540 13:09:03.342008 CA PerBit enable=1, Macro0, CA PI delay=36
7541 13:09:03.342084
7542 13:09:03.345325 [CBTSetCACLKResult] CA Dly = 36
7543 13:09:03.348791 CS Dly: 11 (0~42)
7544 13:09:03.351440 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7545 13:09:03.354865 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7546 13:09:03.354960 ==
7547 13:09:03.358359 Dram Type= 6, Freq= 0, CH_0, rank 1
7548 13:09:03.364739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7549 13:09:03.364845 ==
7550 13:09:03.368200 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7551 13:09:03.374801 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7552 13:09:03.377794 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7553 13:09:03.384730 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7554 13:09:03.392393 [CA 0] Center 44 (14~75) winsize 62
7555 13:09:03.395823 [CA 1] Center 44 (14~74) winsize 61
7556 13:09:03.398725 [CA 2] Center 39 (10~69) winsize 60
7557 13:09:03.402378 [CA 3] Center 39 (10~68) winsize 59
7558 13:09:03.405818 [CA 4] Center 37 (7~67) winsize 61
7559 13:09:03.408802 [CA 5] Center 36 (7~66) winsize 60
7560 13:09:03.408877
7561 13:09:03.412329 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7562 13:09:03.412405
7563 13:09:03.418793 [CATrainingPosCal] consider 2 rank data
7564 13:09:03.418869 u2DelayCellTimex100 = 275/100 ps
7565 13:09:03.425427 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7566 13:09:03.428637 CA1 delay=44 (14~74),Diff = 8 PI (28 cell)
7567 13:09:03.431862 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7568 13:09:03.435167 CA3 delay=39 (10~68),Diff = 3 PI (10 cell)
7569 13:09:03.438723 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7570 13:09:03.441564 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7571 13:09:03.441641
7572 13:09:03.445106 CA PerBit enable=1, Macro0, CA PI delay=36
7573 13:09:03.448669
7574 13:09:03.448744 [CBTSetCACLKResult] CA Dly = 36
7575 13:09:03.451516 CS Dly: 11 (0~43)
7576 13:09:03.454895 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7577 13:09:03.458277 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7578 13:09:03.461681
7579 13:09:03.464612 ----->DramcWriteLeveling(PI) begin...
7580 13:09:03.464690 ==
7581 13:09:03.468111 Dram Type= 6, Freq= 0, CH_0, rank 0
7582 13:09:03.471339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7583 13:09:03.471416 ==
7584 13:09:03.474860 Write leveling (Byte 0): 33 => 33
7585 13:09:03.477810 Write leveling (Byte 1): 26 => 26
7586 13:09:03.480904 DramcWriteLeveling(PI) end<-----
7587 13:09:03.480988
7588 13:09:03.481070 ==
7589 13:09:03.484308 Dram Type= 6, Freq= 0, CH_0, rank 0
7590 13:09:03.487875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7591 13:09:03.487942 ==
7592 13:09:03.491286 [Gating] SW mode calibration
7593 13:09:03.497833 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7594 13:09:03.504078 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7595 13:09:03.507615 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 13:09:03.511180 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 13:09:03.517658 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7598 13:09:03.520552 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7599 13:09:03.524135 1 4 16 | B1->B0 | 2423 3434 | 1 1 | (0 0) (1 1)
7600 13:09:03.530589 1 4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
7601 13:09:03.534326 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7602 13:09:03.537100 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7603 13:09:03.543693 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7604 13:09:03.546784 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7605 13:09:03.550112 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
7606 13:09:03.556788 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
7607 13:09:03.560044 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7608 13:09:03.563682 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
7609 13:09:03.570000 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 13:09:03.573500 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 13:09:03.576281 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 13:09:03.583259 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 13:09:03.586199 1 6 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7614 13:09:03.589663 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7615 13:09:03.596021 1 6 16 | B1->B0 | 2928 4646 | 1 0 | (1 1) (0 0)
7616 13:09:03.599862 1 6 20 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
7617 13:09:03.603007 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7618 13:09:03.609455 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7619 13:09:03.612445 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 13:09:03.616033 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 13:09:03.622421 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7622 13:09:03.626264 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7623 13:09:03.628974 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7624 13:09:03.635496 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7625 13:09:03.638993 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 13:09:03.642418 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 13:09:03.648875 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 13:09:03.652184 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 13:09:03.658440 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 13:09:03.662031 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 13:09:03.665442 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 13:09:03.671977 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 13:09:03.675410 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 13:09:03.678776 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 13:09:03.681659 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 13:09:03.688245 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 13:09:03.691724 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7638 13:09:03.695344 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7639 13:09:03.701656 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7640 13:09:03.705259 Total UI for P1: 0, mck2ui 16
7641 13:09:03.708143 best dqsien dly found for B0: ( 1, 9, 10)
7642 13:09:03.711589 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7643 13:09:03.714683 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 13:09:03.717863 Total UI for P1: 0, mck2ui 16
7645 13:09:03.721329 best dqsien dly found for B1: ( 1, 9, 20)
7646 13:09:03.727929 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7647 13:09:03.731310 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7648 13:09:03.731378
7649 13:09:03.734394 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7650 13:09:03.737823 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7651 13:09:03.740978 [Gating] SW calibration Done
7652 13:09:03.741066 ==
7653 13:09:03.744315 Dram Type= 6, Freq= 0, CH_0, rank 0
7654 13:09:03.747703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7655 13:09:03.747801 ==
7656 13:09:03.750868 RX Vref Scan: 0
7657 13:09:03.750933
7658 13:09:03.750988 RX Vref 0 -> 0, step: 1
7659 13:09:03.751049
7660 13:09:03.754345 RX Delay 0 -> 252, step: 8
7661 13:09:03.757441 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7662 13:09:03.764267 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7663 13:09:03.767553 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7664 13:09:03.770987 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7665 13:09:03.774181 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7666 13:09:03.777263 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7667 13:09:03.784140 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7668 13:09:03.787399 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7669 13:09:03.790456 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7670 13:09:03.793546 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7671 13:09:03.797251 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7672 13:09:03.803576 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7673 13:09:03.807222 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7674 13:09:03.810025 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7675 13:09:03.813678 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7676 13:09:03.819951 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7677 13:09:03.820029 ==
7678 13:09:03.823343 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 13:09:03.826911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7680 13:09:03.826990 ==
7681 13:09:03.827051 DQS Delay:
7682 13:09:03.830315 DQS0 = 0, DQS1 = 0
7683 13:09:03.830394 DQM Delay:
7684 13:09:03.833245 DQM0 = 131, DQM1 = 127
7685 13:09:03.833322 DQ Delay:
7686 13:09:03.836785 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7687 13:09:03.840223 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7688 13:09:03.843216 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
7689 13:09:03.846831 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7690 13:09:03.846909
7691 13:09:03.846969
7692 13:09:03.849752 ==
7693 13:09:03.849830 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 13:09:03.856496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 13:09:03.856575 ==
7696 13:09:03.856635
7697 13:09:03.856689
7698 13:09:03.859967 TX Vref Scan disable
7699 13:09:03.860045 == TX Byte 0 ==
7700 13:09:03.863235 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7701 13:09:03.869694 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7702 13:09:03.869772 == TX Byte 1 ==
7703 13:09:03.876722 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7704 13:09:03.879558 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7705 13:09:03.879636 ==
7706 13:09:03.883124 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 13:09:03.886415 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 13:09:03.886494 ==
7709 13:09:03.901298
7710 13:09:03.905021 TX Vref early break, caculate TX vref
7711 13:09:03.907857 TX Vref=16, minBit 1, minWin=22, winSum=374
7712 13:09:03.911376 TX Vref=18, minBit 6, minWin=23, winSum=382
7713 13:09:03.914278 TX Vref=20, minBit 8, minWin=23, winSum=387
7714 13:09:03.917964 TX Vref=22, minBit 1, minWin=24, winSum=402
7715 13:09:03.920928 TX Vref=24, minBit 6, minWin=24, winSum=412
7716 13:09:03.927389 TX Vref=26, minBit 1, minWin=25, winSum=417
7717 13:09:03.931370 TX Vref=28, minBit 1, minWin=25, winSum=418
7718 13:09:03.934084 TX Vref=30, minBit 2, minWin=25, winSum=417
7719 13:09:03.937760 TX Vref=32, minBit 1, minWin=24, winSum=410
7720 13:09:03.940900 TX Vref=34, minBit 1, minWin=24, winSum=397
7721 13:09:03.944377 TX Vref=36, minBit 7, minWin=23, winSum=389
7722 13:09:03.950839 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 28
7723 13:09:03.950914
7724 13:09:03.953860 Final TX Range 0 Vref 28
7725 13:09:03.953930
7726 13:09:03.953987 ==
7727 13:09:03.957394 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 13:09:03.960536 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 13:09:03.960626 ==
7730 13:09:03.963575
7731 13:09:03.963652
7732 13:09:03.963712 TX Vref Scan disable
7733 13:09:03.971022 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7734 13:09:03.971099 == TX Byte 0 ==
7735 13:09:03.974127 u2DelayCellOfst[0]=14 cells (4 PI)
7736 13:09:03.977333 u2DelayCellOfst[1]=17 cells (5 PI)
7737 13:09:03.980357 u2DelayCellOfst[2]=10 cells (3 PI)
7738 13:09:03.983470 u2DelayCellOfst[3]=14 cells (4 PI)
7739 13:09:03.986717 u2DelayCellOfst[4]=7 cells (2 PI)
7740 13:09:03.990179 u2DelayCellOfst[5]=0 cells (0 PI)
7741 13:09:03.993821 u2DelayCellOfst[6]=17 cells (5 PI)
7742 13:09:03.996583 u2DelayCellOfst[7]=17 cells (5 PI)
7743 13:09:04.000087 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7744 13:09:04.003268 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7745 13:09:04.006405 == TX Byte 1 ==
7746 13:09:04.009921 u2DelayCellOfst[8]=0 cells (0 PI)
7747 13:09:04.013168 u2DelayCellOfst[9]=3 cells (1 PI)
7748 13:09:04.016554 u2DelayCellOfst[10]=7 cells (2 PI)
7749 13:09:04.019583 u2DelayCellOfst[11]=3 cells (1 PI)
7750 13:09:04.023194 u2DelayCellOfst[12]=14 cells (4 PI)
7751 13:09:04.026392 u2DelayCellOfst[13]=10 cells (3 PI)
7752 13:09:04.029396 u2DelayCellOfst[14]=17 cells (5 PI)
7753 13:09:04.032868 u2DelayCellOfst[15]=14 cells (4 PI)
7754 13:09:04.036426 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7755 13:09:04.039507 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7756 13:09:04.043174 DramC Write-DBI on
7757 13:09:04.043249 ==
7758 13:09:04.046365 Dram Type= 6, Freq= 0, CH_0, rank 0
7759 13:09:04.049377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7760 13:09:04.049455 ==
7761 13:09:04.049515
7762 13:09:04.049569
7763 13:09:04.052644 TX Vref Scan disable
7764 13:09:04.052748 == TX Byte 0 ==
7765 13:09:04.059445 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
7766 13:09:04.059528 == TX Byte 1 ==
7767 13:09:04.065795 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7768 13:09:04.065870 DramC Write-DBI off
7769 13:09:04.065929
7770 13:09:04.065997 [DATLAT]
7771 13:09:04.069380 Freq=1600, CH0 RK0
7772 13:09:04.069457
7773 13:09:04.072795 DATLAT Default: 0xf
7774 13:09:04.072872 0, 0xFFFF, sum = 0
7775 13:09:04.075823 1, 0xFFFF, sum = 0
7776 13:09:04.075901 2, 0xFFFF, sum = 0
7777 13:09:04.079172 3, 0xFFFF, sum = 0
7778 13:09:04.079278 4, 0xFFFF, sum = 0
7779 13:09:04.082699 5, 0xFFFF, sum = 0
7780 13:09:04.082777 6, 0xFFFF, sum = 0
7781 13:09:04.085633 7, 0xFFFF, sum = 0
7782 13:09:04.085711 8, 0xFFFF, sum = 0
7783 13:09:04.089327 9, 0xFFFF, sum = 0
7784 13:09:04.089405 10, 0xFFFF, sum = 0
7785 13:09:04.092325 11, 0xFFFF, sum = 0
7786 13:09:04.092404 12, 0xFFFF, sum = 0
7787 13:09:04.095906 13, 0xFFFF, sum = 0
7788 13:09:04.095985 14, 0x0, sum = 1
7789 13:09:04.099191 15, 0x0, sum = 2
7790 13:09:04.099300 16, 0x0, sum = 3
7791 13:09:04.102422 17, 0x0, sum = 4
7792 13:09:04.102520 best_step = 15
7793 13:09:04.102609
7794 13:09:04.102692 ==
7795 13:09:04.105472 Dram Type= 6, Freq= 0, CH_0, rank 0
7796 13:09:04.111963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7797 13:09:04.112075 ==
7798 13:09:04.112168 RX Vref Scan: 1
7799 13:09:04.112229
7800 13:09:04.115595 Set Vref Range= 24 -> 127
7801 13:09:04.115689
7802 13:09:04.118704 RX Vref 24 -> 127, step: 1
7803 13:09:04.118788
7804 13:09:04.118875 RX Delay 19 -> 252, step: 4
7805 13:09:04.122190
7806 13:09:04.122285 Set Vref, RX VrefLevel [Byte0]: 24
7807 13:09:04.125203 [Byte1]: 24
7808 13:09:04.129964
7809 13:09:04.130059 Set Vref, RX VrefLevel [Byte0]: 25
7810 13:09:04.132829 [Byte1]: 25
7811 13:09:04.137252
7812 13:09:04.137325 Set Vref, RX VrefLevel [Byte0]: 26
7813 13:09:04.140674 [Byte1]: 26
7814 13:09:04.144792
7815 13:09:04.144891 Set Vref, RX VrefLevel [Byte0]: 27
7816 13:09:04.148349 [Byte1]: 27
7817 13:09:04.152395
7818 13:09:04.152495 Set Vref, RX VrefLevel [Byte0]: 28
7819 13:09:04.155630 [Byte1]: 28
7820 13:09:04.160121
7821 13:09:04.160215 Set Vref, RX VrefLevel [Byte0]: 29
7822 13:09:04.163566 [Byte1]: 29
7823 13:09:04.167494
7824 13:09:04.167582 Set Vref, RX VrefLevel [Byte0]: 30
7825 13:09:04.170920 [Byte1]: 30
7826 13:09:04.175478
7827 13:09:04.175576 Set Vref, RX VrefLevel [Byte0]: 31
7828 13:09:04.178429 [Byte1]: 31
7829 13:09:04.182560
7830 13:09:04.182662 Set Vref, RX VrefLevel [Byte0]: 32
7831 13:09:04.186234 [Byte1]: 32
7832 13:09:04.190157
7833 13:09:04.190236 Set Vref, RX VrefLevel [Byte0]: 33
7834 13:09:04.193636 [Byte1]: 33
7835 13:09:04.198180
7836 13:09:04.198257 Set Vref, RX VrefLevel [Byte0]: 34
7837 13:09:04.201253 [Byte1]: 34
7838 13:09:04.205426
7839 13:09:04.205503 Set Vref, RX VrefLevel [Byte0]: 35
7840 13:09:04.208634 [Byte1]: 35
7841 13:09:04.212871
7842 13:09:04.212949 Set Vref, RX VrefLevel [Byte0]: 36
7843 13:09:04.216279 [Byte1]: 36
7844 13:09:04.220606
7845 13:09:04.220683 Set Vref, RX VrefLevel [Byte0]: 37
7846 13:09:04.224077 [Byte1]: 37
7847 13:09:04.228259
7848 13:09:04.228336 Set Vref, RX VrefLevel [Byte0]: 38
7849 13:09:04.231278 [Byte1]: 38
7850 13:09:04.236202
7851 13:09:04.236279 Set Vref, RX VrefLevel [Byte0]: 39
7852 13:09:04.239190 [Byte1]: 39
7853 13:09:04.243280
7854 13:09:04.243357 Set Vref, RX VrefLevel [Byte0]: 40
7855 13:09:04.246826 [Byte1]: 40
7856 13:09:04.250806
7857 13:09:04.250885 Set Vref, RX VrefLevel [Byte0]: 41
7858 13:09:04.253998 [Byte1]: 41
7859 13:09:04.258614
7860 13:09:04.258690 Set Vref, RX VrefLevel [Byte0]: 42
7861 13:09:04.261780 [Byte1]: 42
7862 13:09:04.266040
7863 13:09:04.266145 Set Vref, RX VrefLevel [Byte0]: 43
7864 13:09:04.269367 [Byte1]: 43
7865 13:09:04.273594
7866 13:09:04.273675 Set Vref, RX VrefLevel [Byte0]: 44
7867 13:09:04.276943 [Byte1]: 44
7868 13:09:04.280915
7869 13:09:04.281014 Set Vref, RX VrefLevel [Byte0]: 45
7870 13:09:04.284360 [Byte1]: 45
7871 13:09:04.288652
7872 13:09:04.288750 Set Vref, RX VrefLevel [Byte0]: 46
7873 13:09:04.292082 [Byte1]: 46
7874 13:09:04.296319
7875 13:09:04.296390 Set Vref, RX VrefLevel [Byte0]: 47
7876 13:09:04.299817 [Byte1]: 47
7877 13:09:04.304208
7878 13:09:04.304292 Set Vref, RX VrefLevel [Byte0]: 48
7879 13:09:04.307384 [Byte1]: 48
7880 13:09:04.311520
7881 13:09:04.311620 Set Vref, RX VrefLevel [Byte0]: 49
7882 13:09:04.314626 [Byte1]: 49
7883 13:09:04.319029
7884 13:09:04.319125 Set Vref, RX VrefLevel [Byte0]: 50
7885 13:09:04.322628 [Byte1]: 50
7886 13:09:04.326670
7887 13:09:04.326767 Set Vref, RX VrefLevel [Byte0]: 51
7888 13:09:04.329652 [Byte1]: 51
7889 13:09:04.334216
7890 13:09:04.334313 Set Vref, RX VrefLevel [Byte0]: 52
7891 13:09:04.337328 [Byte1]: 52
7892 13:09:04.341433
7893 13:09:04.341533 Set Vref, RX VrefLevel [Byte0]: 53
7894 13:09:04.344926 [Byte1]: 53
7895 13:09:04.349140
7896 13:09:04.349220 Set Vref, RX VrefLevel [Byte0]: 54
7897 13:09:04.352884 [Byte1]: 54
7898 13:09:04.357128
7899 13:09:04.357214 Set Vref, RX VrefLevel [Byte0]: 55
7900 13:09:04.359999 [Byte1]: 55
7901 13:09:04.364347
7902 13:09:04.364434 Set Vref, RX VrefLevel [Byte0]: 56
7903 13:09:04.367632 [Byte1]: 56
7904 13:09:04.371810
7905 13:09:04.371910 Set Vref, RX VrefLevel [Byte0]: 57
7906 13:09:04.375308 [Byte1]: 57
7907 13:09:04.379635
7908 13:09:04.379730 Set Vref, RX VrefLevel [Byte0]: 58
7909 13:09:04.383140 [Byte1]: 58
7910 13:09:04.387319
7911 13:09:04.387419 Set Vref, RX VrefLevel [Byte0]: 59
7912 13:09:04.390533 [Byte1]: 59
7913 13:09:04.394622
7914 13:09:04.394717 Set Vref, RX VrefLevel [Byte0]: 60
7915 13:09:04.398546 [Byte1]: 60
7916 13:09:04.402389
7917 13:09:04.402462 Set Vref, RX VrefLevel [Byte0]: 61
7918 13:09:04.405826 [Byte1]: 61
7919 13:09:04.409887
7920 13:09:04.409982 Set Vref, RX VrefLevel [Byte0]: 62
7921 13:09:04.413353 [Byte1]: 62
7922 13:09:04.417339
7923 13:09:04.417413 Set Vref, RX VrefLevel [Byte0]: 63
7924 13:09:04.420714 [Byte1]: 63
7925 13:09:04.424932
7926 13:09:04.425030 Set Vref, RX VrefLevel [Byte0]: 64
7927 13:09:04.428620 [Byte1]: 64
7928 13:09:04.432666
7929 13:09:04.432759 Set Vref, RX VrefLevel [Byte0]: 65
7930 13:09:04.435598 [Byte1]: 65
7931 13:09:04.440338
7932 13:09:04.440407 Set Vref, RX VrefLevel [Byte0]: 66
7933 13:09:04.443459 [Byte1]: 66
7934 13:09:04.447634
7935 13:09:04.447736 Set Vref, RX VrefLevel [Byte0]: 67
7936 13:09:04.451159 [Byte1]: 67
7937 13:09:04.455562
7938 13:09:04.455659 Set Vref, RX VrefLevel [Byte0]: 68
7939 13:09:04.458596 [Byte1]: 68
7940 13:09:04.463245
7941 13:09:04.463316 Set Vref, RX VrefLevel [Byte0]: 69
7942 13:09:04.466236 [Byte1]: 69
7943 13:09:04.470837
7944 13:09:04.470931 Set Vref, RX VrefLevel [Byte0]: 70
7945 13:09:04.474213 [Byte1]: 70
7946 13:09:04.477982
7947 13:09:04.478062 Set Vref, RX VrefLevel [Byte0]: 71
7948 13:09:04.481445 [Byte1]: 71
7949 13:09:04.485522
7950 13:09:04.485597 Set Vref, RX VrefLevel [Byte0]: 72
7951 13:09:04.489030 [Byte1]: 72
7952 13:09:04.493155
7953 13:09:04.493275 Set Vref, RX VrefLevel [Byte0]: 73
7954 13:09:04.496884 [Byte1]: 73
7955 13:09:04.500966
7956 13:09:04.501041 Set Vref, RX VrefLevel [Byte0]: 74
7957 13:09:04.504366 [Byte1]: 74
7958 13:09:04.508392
7959 13:09:04.508483 Set Vref, RX VrefLevel [Byte0]: 75
7960 13:09:04.511447 [Byte1]: 75
7961 13:09:04.515982
7962 13:09:04.516059 Final RX Vref Byte 0 = 56 to rank0
7963 13:09:04.519705 Final RX Vref Byte 1 = 59 to rank0
7964 13:09:04.522833 Final RX Vref Byte 0 = 56 to rank1
7965 13:09:04.525777 Final RX Vref Byte 1 = 59 to rank1==
7966 13:09:04.529280 Dram Type= 6, Freq= 0, CH_0, rank 0
7967 13:09:04.535614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7968 13:09:04.535691 ==
7969 13:09:04.535750 DQS Delay:
7970 13:09:04.535805 DQS0 = 0, DQS1 = 0
7971 13:09:04.539189 DQM Delay:
7972 13:09:04.539264 DQM0 = 128, DQM1 = 123
7973 13:09:04.542181 DQ Delay:
7974 13:09:04.545800 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7975 13:09:04.549101 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
7976 13:09:04.552548 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120
7977 13:09:04.555567 DQ12 =130, DQ13 =128, DQ14 =132, DQ15 =130
7978 13:09:04.555643
7979 13:09:04.555701
7980 13:09:04.555754
7981 13:09:04.558974 [DramC_TX_OE_Calibration] TA2
7982 13:09:04.562190 Original DQ_B0 (3 6) =30, OEN = 27
7983 13:09:04.565502 Original DQ_B1 (3 6) =30, OEN = 27
7984 13:09:04.568777 24, 0x0, End_B0=24 End_B1=24
7985 13:09:04.568881 25, 0x0, End_B0=25 End_B1=25
7986 13:09:04.572262 26, 0x0, End_B0=26 End_B1=26
7987 13:09:04.575355 27, 0x0, End_B0=27 End_B1=27
7988 13:09:04.578697 28, 0x0, End_B0=28 End_B1=28
7989 13:09:04.581860 29, 0x0, End_B0=29 End_B1=29
7990 13:09:04.581961 30, 0x0, End_B0=30 End_B1=30
7991 13:09:04.585163 31, 0x4545, End_B0=30 End_B1=30
7992 13:09:04.588819 Byte0 end_step=30 best_step=27
7993 13:09:04.591764 Byte1 end_step=30 best_step=27
7994 13:09:04.595380 Byte0 TX OE(2T, 0.5T) = (3, 3)
7995 13:09:04.598378 Byte1 TX OE(2T, 0.5T) = (3, 3)
7996 13:09:04.598475
7997 13:09:04.598562
7998 13:09:04.605377 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7999 13:09:04.608175 CH0 RK0: MR19=303, MR18=1A17
8000 13:09:04.615131 CH0_RK0: MR19=0x303, MR18=0x1A17, DQSOSC=396, MR23=63, INC=23, DEC=15
8001 13:09:04.615232
8002 13:09:04.618450 ----->DramcWriteLeveling(PI) begin...
8003 13:09:04.618546 ==
8004 13:09:04.621710 Dram Type= 6, Freq= 0, CH_0, rank 1
8005 13:09:04.624991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8006 13:09:04.625092 ==
8007 13:09:04.627862 Write leveling (Byte 0): 34 => 34
8008 13:09:04.631720 Write leveling (Byte 1): 27 => 27
8009 13:09:04.634659 DramcWriteLeveling(PI) end<-----
8010 13:09:04.634759
8011 13:09:04.634845 ==
8012 13:09:04.637932 Dram Type= 6, Freq= 0, CH_0, rank 1
8013 13:09:04.640864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8014 13:09:04.644566 ==
8015 13:09:04.644663 [Gating] SW mode calibration
8016 13:09:04.654346 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8017 13:09:04.658028 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8018 13:09:04.660925 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 13:09:04.667226 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 13:09:04.670544 1 4 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8021 13:09:04.673774 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8022 13:09:04.680445 1 4 16 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8023 13:09:04.684076 1 4 20 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8024 13:09:04.687404 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8025 13:09:04.693562 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 13:09:04.697075 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 13:09:04.703860 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8028 13:09:04.706562 1 5 8 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
8029 13:09:04.710106 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
8030 13:09:04.716574 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8031 13:09:04.720087 1 5 20 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
8032 13:09:04.723164 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8033 13:09:04.729687 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 13:09:04.733310 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 13:09:04.736242 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 13:09:04.743028 1 6 8 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
8037 13:09:04.746519 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8038 13:09:04.749840 1 6 16 | B1->B0 | 3333 4646 | 0 0 | (1 1) (0 0)
8039 13:09:04.756465 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8040 13:09:04.759297 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 13:09:04.762894 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 13:09:04.769637 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 13:09:04.772665 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 13:09:04.776042 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8045 13:09:04.782402 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8046 13:09:04.786163 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8047 13:09:04.789038 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8048 13:09:04.795579 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 13:09:04.799194 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 13:09:04.802039 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 13:09:04.808593 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 13:09:04.812189 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 13:09:04.815523 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 13:09:04.822163 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 13:09:04.825573 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 13:09:04.828630 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 13:09:04.834980 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 13:09:04.838604 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 13:09:04.841957 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8060 13:09:04.848478 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8061 13:09:04.851536 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8062 13:09:04.854650 Total UI for P1: 0, mck2ui 16
8063 13:09:04.858345 best dqsien dly found for B0: ( 1, 9, 6)
8064 13:09:04.861300 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8065 13:09:04.867736 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8066 13:09:04.871160 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 13:09:04.874827 Total UI for P1: 0, mck2ui 16
8068 13:09:04.877898 best dqsien dly found for B1: ( 1, 9, 18)
8069 13:09:04.881324 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8070 13:09:04.884431 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8071 13:09:04.884531
8072 13:09:04.887797 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8073 13:09:04.890842 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8074 13:09:04.894405 [Gating] SW calibration Done
8075 13:09:04.894479 ==
8076 13:09:04.897398 Dram Type= 6, Freq= 0, CH_0, rank 1
8077 13:09:04.900830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8078 13:09:04.904364 ==
8079 13:09:04.904461 RX Vref Scan: 0
8080 13:09:04.904548
8081 13:09:04.907400 RX Vref 0 -> 0, step: 1
8082 13:09:04.907467
8083 13:09:04.910958 RX Delay 0 -> 252, step: 8
8084 13:09:04.913760 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8085 13:09:04.917446 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8086 13:09:04.920537 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8087 13:09:04.923747 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8088 13:09:04.930542 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8089 13:09:04.933637 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8090 13:09:04.937193 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8091 13:09:04.940072 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8092 13:09:04.943641 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8093 13:09:04.950163 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8094 13:09:04.953458 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8095 13:09:04.956912 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8096 13:09:04.960581 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8097 13:09:04.966756 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8098 13:09:04.970330 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8099 13:09:04.973599 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8100 13:09:04.973697 ==
8101 13:09:04.976721 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 13:09:04.979849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 13:09:04.979947 ==
8104 13:09:04.983292 DQS Delay:
8105 13:09:04.983385 DQS0 = 0, DQS1 = 0
8106 13:09:04.986506 DQM Delay:
8107 13:09:04.986602 DQM0 = 130, DQM1 = 127
8108 13:09:04.986702 DQ Delay:
8109 13:09:04.992920 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
8110 13:09:04.996513 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8111 13:09:04.999517 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
8112 13:09:05.003105 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8113 13:09:05.003200
8114 13:09:05.003290
8115 13:09:05.003372 ==
8116 13:09:05.006039 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 13:09:05.009542 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 13:09:05.009612 ==
8119 13:09:05.009669
8120 13:09:05.009727
8121 13:09:05.012556 TX Vref Scan disable
8122 13:09:05.016145 == TX Byte 0 ==
8123 13:09:05.019091 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8124 13:09:05.022709 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8125 13:09:05.026333 == TX Byte 1 ==
8126 13:09:05.029350 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8127 13:09:05.032800 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8128 13:09:05.032896 ==
8129 13:09:05.035852 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 13:09:05.042274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 13:09:05.042374 ==
8132 13:09:05.054805
8133 13:09:05.057932 TX Vref early break, caculate TX vref
8134 13:09:05.061417 TX Vref=16, minBit 1, minWin=23, winSum=382
8135 13:09:05.064404 TX Vref=18, minBit 8, minWin=23, winSum=389
8136 13:09:05.067812 TX Vref=20, minBit 2, minWin=24, winSum=397
8137 13:09:05.071279 TX Vref=22, minBit 9, minWin=24, winSum=405
8138 13:09:05.074215 TX Vref=24, minBit 1, minWin=25, winSum=412
8139 13:09:05.081291 TX Vref=26, minBit 2, minWin=25, winSum=421
8140 13:09:05.084322 TX Vref=28, minBit 1, minWin=26, winSum=422
8141 13:09:05.088019 TX Vref=30, minBit 1, minWin=25, winSum=416
8142 13:09:05.090782 TX Vref=32, minBit 8, minWin=24, winSum=408
8143 13:09:05.094311 TX Vref=34, minBit 0, minWin=24, winSum=398
8144 13:09:05.100562 [TxChooseVref] Worse bit 1, Min win 26, Win sum 422, Final Vref 28
8145 13:09:05.100656
8146 13:09:05.103903 Final TX Range 0 Vref 28
8147 13:09:05.104000
8148 13:09:05.104090 ==
8149 13:09:05.107322 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 13:09:05.110833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 13:09:05.110933 ==
8152 13:09:05.111018
8153 13:09:05.111104
8154 13:09:05.114190 TX Vref Scan disable
8155 13:09:05.120927 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8156 13:09:05.121023 == TX Byte 0 ==
8157 13:09:05.123705 u2DelayCellOfst[0]=14 cells (4 PI)
8158 13:09:05.127445 u2DelayCellOfst[1]=17 cells (5 PI)
8159 13:09:05.130554 u2DelayCellOfst[2]=10 cells (3 PI)
8160 13:09:05.133898 u2DelayCellOfst[3]=10 cells (3 PI)
8161 13:09:05.137399 u2DelayCellOfst[4]=10 cells (3 PI)
8162 13:09:05.140940 u2DelayCellOfst[5]=0 cells (0 PI)
8163 13:09:05.144129 u2DelayCellOfst[6]=17 cells (5 PI)
8164 13:09:05.146928 u2DelayCellOfst[7]=17 cells (5 PI)
8165 13:09:05.150214 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8166 13:09:05.153716 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8167 13:09:05.157229 == TX Byte 1 ==
8168 13:09:05.160170 u2DelayCellOfst[8]=3 cells (1 PI)
8169 13:09:05.163481 u2DelayCellOfst[9]=0 cells (0 PI)
8170 13:09:05.167025 u2DelayCellOfst[10]=7 cells (2 PI)
8171 13:09:05.167123 u2DelayCellOfst[11]=3 cells (1 PI)
8172 13:09:05.170487 u2DelayCellOfst[12]=10 cells (3 PI)
8173 13:09:05.173319 u2DelayCellOfst[13]=10 cells (3 PI)
8174 13:09:05.176654 u2DelayCellOfst[14]=14 cells (4 PI)
8175 13:09:05.180263 u2DelayCellOfst[15]=10 cells (3 PI)
8176 13:09:05.186881 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8177 13:09:05.189764 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8178 13:09:05.189869 DramC Write-DBI on
8179 13:09:05.189963 ==
8180 13:09:05.193501 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 13:09:05.199919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 13:09:05.200018 ==
8183 13:09:05.200118
8184 13:09:05.200204
8185 13:09:05.202918 TX Vref Scan disable
8186 13:09:05.203025 == TX Byte 0 ==
8187 13:09:05.209815 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8188 13:09:05.209913 == TX Byte 1 ==
8189 13:09:05.212969 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8190 13:09:05.216897 DramC Write-DBI off
8191 13:09:05.217004
8192 13:09:05.217092 [DATLAT]
8193 13:09:05.219980 Freq=1600, CH0 RK1
8194 13:09:05.220086
8195 13:09:05.220178 DATLAT Default: 0xf
8196 13:09:05.223031 0, 0xFFFF, sum = 0
8197 13:09:05.223139 1, 0xFFFF, sum = 0
8198 13:09:05.226432 2, 0xFFFF, sum = 0
8199 13:09:05.226531 3, 0xFFFF, sum = 0
8200 13:09:05.229534 4, 0xFFFF, sum = 0
8201 13:09:05.229610 5, 0xFFFF, sum = 0
8202 13:09:05.232915 6, 0xFFFF, sum = 0
8203 13:09:05.233014 7, 0xFFFF, sum = 0
8204 13:09:05.235893 8, 0xFFFF, sum = 0
8205 13:09:05.239418 9, 0xFFFF, sum = 0
8206 13:09:05.239518 10, 0xFFFF, sum = 0
8207 13:09:05.242536 11, 0xFFFF, sum = 0
8208 13:09:05.242645 12, 0xFFFF, sum = 0
8209 13:09:05.246075 13, 0xFFFF, sum = 0
8210 13:09:05.246171 14, 0x0, sum = 1
8211 13:09:05.249619 15, 0x0, sum = 2
8212 13:09:05.249715 16, 0x0, sum = 3
8213 13:09:05.252490 17, 0x0, sum = 4
8214 13:09:05.252561 best_step = 15
8215 13:09:05.252620
8216 13:09:05.252714 ==
8217 13:09:05.255888 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 13:09:05.259409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 13:09:05.262610 ==
8220 13:09:05.262705 RX Vref Scan: 0
8221 13:09:05.262797
8222 13:09:05.265943 RX Vref 0 -> 0, step: 1
8223 13:09:05.266046
8224 13:09:05.269202 RX Delay 11 -> 252, step: 4
8225 13:09:05.272613 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8226 13:09:05.275565 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8227 13:09:05.278860 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8228 13:09:05.285334 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8229 13:09:05.288924 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8230 13:09:05.292349 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8231 13:09:05.295196 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8232 13:09:05.298816 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8233 13:09:05.305195 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8234 13:09:05.308681 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8235 13:09:05.311642 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8236 13:09:05.314938 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8237 13:09:05.318173 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8238 13:09:05.325198 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8239 13:09:05.328488 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8240 13:09:05.331821 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8241 13:09:05.331919 ==
8242 13:09:05.335014 Dram Type= 6, Freq= 0, CH_0, rank 1
8243 13:09:05.337910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 13:09:05.341451 ==
8245 13:09:05.341556 DQS Delay:
8246 13:09:05.341659 DQS0 = 0, DQS1 = 0
8247 13:09:05.344542 DQM Delay:
8248 13:09:05.344638 DQM0 = 128, DQM1 = 124
8249 13:09:05.347943 DQ Delay:
8250 13:09:05.351557 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8251 13:09:05.354910 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =134
8252 13:09:05.357728 DQ8 =114, DQ9 =110, DQ10 =128, DQ11 =118
8253 13:09:05.361189 DQ12 =128, DQ13 =130, DQ14 =134, DQ15 =130
8254 13:09:05.361262
8255 13:09:05.361333
8256 13:09:05.361406
8257 13:09:05.364793 [DramC_TX_OE_Calibration] TA2
8258 13:09:05.367751 Original DQ_B0 (3 6) =30, OEN = 27
8259 13:09:05.371184 Original DQ_B1 (3 6) =30, OEN = 27
8260 13:09:05.374821 24, 0x0, End_B0=24 End_B1=24
8261 13:09:05.374924 25, 0x0, End_B0=25 End_B1=25
8262 13:09:05.377810 26, 0x0, End_B0=26 End_B1=26
8263 13:09:05.381482 27, 0x0, End_B0=27 End_B1=27
8264 13:09:05.384118 28, 0x0, End_B0=28 End_B1=28
8265 13:09:05.387904 29, 0x0, End_B0=29 End_B1=29
8266 13:09:05.388005 30, 0x0, End_B0=30 End_B1=30
8267 13:09:05.391280 31, 0x4545, End_B0=30 End_B1=30
8268 13:09:05.394301 Byte0 end_step=30 best_step=27
8269 13:09:05.397647 Byte1 end_step=30 best_step=27
8270 13:09:05.400919 Byte0 TX OE(2T, 0.5T) = (3, 3)
8271 13:09:05.404090 Byte1 TX OE(2T, 0.5T) = (3, 3)
8272 13:09:05.404162
8273 13:09:05.404220
8274 13:09:05.410797 [DQSOSCAuto] RK1, (LSB)MR18= 0x1715, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
8275 13:09:05.414106 CH0 RK1: MR19=303, MR18=1715
8276 13:09:05.420934 CH0_RK1: MR19=0x303, MR18=0x1715, DQSOSC=398, MR23=63, INC=23, DEC=15
8277 13:09:05.423863 [RxdqsGatingPostProcess] freq 1600
8278 13:09:05.427270 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8279 13:09:05.430748 best DQS0 dly(2T, 0.5T) = (1, 1)
8280 13:09:05.434318 best DQS1 dly(2T, 0.5T) = (1, 1)
8281 13:09:05.437307 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8282 13:09:05.440776 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8283 13:09:05.444077 best DQS0 dly(2T, 0.5T) = (1, 1)
8284 13:09:05.447404 best DQS1 dly(2T, 0.5T) = (1, 1)
8285 13:09:05.450748 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8286 13:09:05.453718 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8287 13:09:05.457474 Pre-setting of DQS Precalculation
8288 13:09:05.460667 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8289 13:09:05.460769 ==
8290 13:09:05.463608 Dram Type= 6, Freq= 0, CH_1, rank 0
8291 13:09:05.467163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 13:09:05.470565 ==
8293 13:09:05.473575 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8294 13:09:05.477101 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8295 13:09:05.483725 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8296 13:09:05.490440 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8297 13:09:05.497198 [CA 0] Center 42 (12~72) winsize 61
8298 13:09:05.500596 [CA 1] Center 42 (12~72) winsize 61
8299 13:09:05.504132 [CA 2] Center 38 (9~68) winsize 60
8300 13:09:05.507113 [CA 3] Center 37 (8~67) winsize 60
8301 13:09:05.510426 [CA 4] Center 38 (8~68) winsize 61
8302 13:09:05.514087 [CA 5] Center 36 (7~66) winsize 60
8303 13:09:05.514161
8304 13:09:05.517005 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8305 13:09:05.517099
8306 13:09:05.523536 [CATrainingPosCal] consider 1 rank data
8307 13:09:05.523633 u2DelayCellTimex100 = 275/100 ps
8308 13:09:05.530533 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8309 13:09:05.533496 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8310 13:09:05.536777 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
8311 13:09:05.540135 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
8312 13:09:05.543739 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8313 13:09:05.546645 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8314 13:09:05.546738
8315 13:09:05.550295 CA PerBit enable=1, Macro0, CA PI delay=36
8316 13:09:05.550361
8317 13:09:05.553819 [CBTSetCACLKResult] CA Dly = 36
8318 13:09:05.557032 CS Dly: 8 (0~39)
8319 13:09:05.560053 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8320 13:09:05.563363 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8321 13:09:05.563459 ==
8322 13:09:05.566656 Dram Type= 6, Freq= 0, CH_1, rank 1
8323 13:09:05.573284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8324 13:09:05.573353 ==
8325 13:09:05.576812 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8326 13:09:05.579893 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8327 13:09:05.586915 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8328 13:09:05.593369 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8329 13:09:05.600420 [CA 0] Center 42 (12~72) winsize 61
8330 13:09:05.603907 [CA 1] Center 42 (13~72) winsize 60
8331 13:09:05.606953 [CA 2] Center 38 (8~68) winsize 61
8332 13:09:05.610512 [CA 3] Center 37 (7~67) winsize 61
8333 13:09:05.613901 [CA 4] Center 38 (8~68) winsize 61
8334 13:09:05.616851 [CA 5] Center 37 (8~67) winsize 60
8335 13:09:05.616940
8336 13:09:05.620209 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8337 13:09:05.620271
8338 13:09:05.623766 [CATrainingPosCal] consider 2 rank data
8339 13:09:05.627127 u2DelayCellTimex100 = 275/100 ps
8340 13:09:05.630389 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8341 13:09:05.636964 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8342 13:09:05.640298 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8343 13:09:05.643451 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8344 13:09:05.647241 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8345 13:09:05.650216 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8346 13:09:05.650284
8347 13:09:05.653600 CA PerBit enable=1, Macro0, CA PI delay=37
8348 13:09:05.653690
8349 13:09:05.656793 [CBTSetCACLKResult] CA Dly = 37
8350 13:09:05.660374 CS Dly: 9 (0~42)
8351 13:09:05.663757 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8352 13:09:05.667199 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8353 13:09:05.667306
8354 13:09:05.670256 ----->DramcWriteLeveling(PI) begin...
8355 13:09:05.670349 ==
8356 13:09:05.673496 Dram Type= 6, Freq= 0, CH_1, rank 0
8357 13:09:05.680238 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8358 13:09:05.680308 ==
8359 13:09:05.683133 Write leveling (Byte 0): 25 => 25
8360 13:09:05.683230 Write leveling (Byte 1): 26 => 26
8361 13:09:05.686879 DramcWriteLeveling(PI) end<-----
8362 13:09:05.686976
8363 13:09:05.687070 ==
8364 13:09:05.689902 Dram Type= 6, Freq= 0, CH_1, rank 0
8365 13:09:05.697009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 13:09:05.697111 ==
8367 13:09:05.699923 [Gating] SW mode calibration
8368 13:09:05.706376 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8369 13:09:05.709954 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8370 13:09:05.716388 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 13:09:05.719969 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 13:09:05.722735 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8373 13:09:05.729513 1 4 12 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
8374 13:09:05.733123 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 13:09:05.736254 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 13:09:05.742634 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 13:09:05.745893 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 13:09:05.749448 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 13:09:05.756137 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 13:09:05.758846 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8381 13:09:05.762404 1 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
8382 13:09:05.769111 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 13:09:05.772220 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 13:09:05.775571 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 13:09:05.782579 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 13:09:05.785475 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 13:09:05.788833 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 13:09:05.795761 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8389 13:09:05.798729 1 6 12 | B1->B0 | 2a2a 4343 | 0 0 | (0 0) (0 0)
8390 13:09:05.801781 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 13:09:05.808593 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 13:09:05.812404 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 13:09:05.815361 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 13:09:05.821753 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 13:09:05.825628 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 13:09:05.828435 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8397 13:09:05.834773 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8398 13:09:05.838183 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8399 13:09:05.841583 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 13:09:05.848429 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 13:09:05.851543 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 13:09:05.855070 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 13:09:05.861491 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 13:09:05.865059 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 13:09:05.867865 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 13:09:05.874461 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 13:09:05.878114 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 13:09:05.881218 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 13:09:05.887557 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 13:09:05.891017 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 13:09:05.894441 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 13:09:05.900906 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8413 13:09:05.904350 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8414 13:09:05.907450 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 13:09:05.911056 Total UI for P1: 0, mck2ui 16
8416 13:09:05.913890 best dqsien dly found for B0: ( 1, 9, 10)
8417 13:09:05.917261 Total UI for P1: 0, mck2ui 16
8418 13:09:05.921000 best dqsien dly found for B1: ( 1, 9, 12)
8419 13:09:05.923966 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8420 13:09:05.927589 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8421 13:09:05.927681
8422 13:09:05.934194 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8423 13:09:05.937467 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8424 13:09:05.940691 [Gating] SW calibration Done
8425 13:09:05.940782 ==
8426 13:09:05.944250 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 13:09:05.947594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8428 13:09:05.947688 ==
8429 13:09:05.947772 RX Vref Scan: 0
8430 13:09:05.947858
8431 13:09:05.950355 RX Vref 0 -> 0, step: 1
8432 13:09:05.950447
8433 13:09:05.954207 RX Delay 0 -> 252, step: 8
8434 13:09:05.957128 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8435 13:09:05.960556 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8436 13:09:05.966976 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8437 13:09:05.970527 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8438 13:09:05.973440 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8439 13:09:05.976887 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8440 13:09:05.980427 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8441 13:09:05.986683 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8442 13:09:05.989932 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8443 13:09:05.993351 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8444 13:09:05.996503 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8445 13:09:05.999829 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8446 13:09:06.006741 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8447 13:09:06.009695 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8448 13:09:06.012991 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8449 13:09:06.016639 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8450 13:09:06.016731 ==
8451 13:09:06.019578 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 13:09:06.026410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 13:09:06.026506 ==
8454 13:09:06.026602 DQS Delay:
8455 13:09:06.029422 DQS0 = 0, DQS1 = 0
8456 13:09:06.029536 DQM Delay:
8457 13:09:06.033026 DQM0 = 135, DQM1 = 130
8458 13:09:06.033126 DQ Delay:
8459 13:09:06.036544 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8460 13:09:06.039533 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =131
8461 13:09:06.042878 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8462 13:09:06.046415 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8463 13:09:06.046528
8464 13:09:06.046634
8465 13:09:06.046770 ==
8466 13:09:06.049149 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 13:09:06.055657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 13:09:06.055766 ==
8469 13:09:06.055854
8470 13:09:06.055938
8471 13:09:06.056018 TX Vref Scan disable
8472 13:09:06.059343 == TX Byte 0 ==
8473 13:09:06.062523 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8474 13:09:06.065940 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8475 13:09:06.069407 == TX Byte 1 ==
8476 13:09:06.072406 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8477 13:09:06.079147 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8478 13:09:06.079245 ==
8479 13:09:06.082548 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 13:09:06.085986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8481 13:09:06.086088 ==
8482 13:09:06.097975
8483 13:09:06.101300 TX Vref early break, caculate TX vref
8484 13:09:06.104681 TX Vref=16, minBit 8, minWin=22, winSum=371
8485 13:09:06.108190 TX Vref=18, minBit 8, minWin=22, winSum=378
8486 13:09:06.111039 TX Vref=20, minBit 8, minWin=22, winSum=383
8487 13:09:06.114475 TX Vref=22, minBit 8, minWin=24, winSum=400
8488 13:09:06.117527 TX Vref=24, minBit 8, minWin=24, winSum=406
8489 13:09:06.124311 TX Vref=26, minBit 9, minWin=24, winSum=414
8490 13:09:06.127444 TX Vref=28, minBit 9, minWin=25, winSum=424
8491 13:09:06.130550 TX Vref=30, minBit 0, minWin=25, winSum=416
8492 13:09:06.134183 TX Vref=32, minBit 0, minWin=24, winSum=403
8493 13:09:06.137810 TX Vref=34, minBit 9, minWin=23, winSum=398
8494 13:09:06.144304 [TxChooseVref] Worse bit 9, Min win 25, Win sum 424, Final Vref 28
8495 13:09:06.144405
8496 13:09:06.147190 Final TX Range 0 Vref 28
8497 13:09:06.147291
8498 13:09:06.147380 ==
8499 13:09:06.150805 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 13:09:06.154330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 13:09:06.154429 ==
8502 13:09:06.154520
8503 13:09:06.154605
8504 13:09:06.157228 TX Vref Scan disable
8505 13:09:06.163808 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8506 13:09:06.163904 == TX Byte 0 ==
8507 13:09:06.167396 u2DelayCellOfst[0]=14 cells (4 PI)
8508 13:09:06.170697 u2DelayCellOfst[1]=10 cells (3 PI)
8509 13:09:06.174298 u2DelayCellOfst[2]=0 cells (0 PI)
8510 13:09:06.177280 u2DelayCellOfst[3]=3 cells (1 PI)
8511 13:09:06.180790 u2DelayCellOfst[4]=10 cells (3 PI)
8512 13:09:06.183852 u2DelayCellOfst[5]=17 cells (5 PI)
8513 13:09:06.187211 u2DelayCellOfst[6]=14 cells (4 PI)
8514 13:09:06.190598 u2DelayCellOfst[7]=7 cells (2 PI)
8515 13:09:06.193963 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8516 13:09:06.197163 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8517 13:09:06.200128 == TX Byte 1 ==
8518 13:09:06.203775 u2DelayCellOfst[8]=0 cells (0 PI)
8519 13:09:06.203875 u2DelayCellOfst[9]=3 cells (1 PI)
8520 13:09:06.207123 u2DelayCellOfst[10]=10 cells (3 PI)
8521 13:09:06.210188 u2DelayCellOfst[11]=3 cells (1 PI)
8522 13:09:06.213286 u2DelayCellOfst[12]=10 cells (3 PI)
8523 13:09:06.216785 u2DelayCellOfst[13]=14 cells (4 PI)
8524 13:09:06.219820 u2DelayCellOfst[14]=17 cells (5 PI)
8525 13:09:06.223304 u2DelayCellOfst[15]=14 cells (4 PI)
8526 13:09:06.229946 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8527 13:09:06.233543 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8528 13:09:06.233636 DramC Write-DBI on
8529 13:09:06.233731 ==
8530 13:09:06.236262 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 13:09:06.242912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 13:09:06.243006 ==
8533 13:09:06.243090
8534 13:09:06.243174
8535 13:09:06.246551 TX Vref Scan disable
8536 13:09:06.246645 == TX Byte 0 ==
8537 13:09:06.252693 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8538 13:09:06.252788 == TX Byte 1 ==
8539 13:09:06.256168 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8540 13:09:06.259530 DramC Write-DBI off
8541 13:09:06.259619
8542 13:09:06.259704 [DATLAT]
8543 13:09:06.263047 Freq=1600, CH1 RK0
8544 13:09:06.263137
8545 13:09:06.263217 DATLAT Default: 0xf
8546 13:09:06.265941 0, 0xFFFF, sum = 0
8547 13:09:06.266043 1, 0xFFFF, sum = 0
8548 13:09:06.269272 2, 0xFFFF, sum = 0
8549 13:09:06.269366 3, 0xFFFF, sum = 0
8550 13:09:06.272686 4, 0xFFFF, sum = 0
8551 13:09:06.272793 5, 0xFFFF, sum = 0
8552 13:09:06.276236 6, 0xFFFF, sum = 0
8553 13:09:06.276335 7, 0xFFFF, sum = 0
8554 13:09:06.279123 8, 0xFFFF, sum = 0
8555 13:09:06.279226 9, 0xFFFF, sum = 0
8556 13:09:06.282489 10, 0xFFFF, sum = 0
8557 13:09:06.286240 11, 0xFFFF, sum = 0
8558 13:09:06.286340 12, 0xFFFF, sum = 0
8559 13:09:06.288992 13, 0xFFFF, sum = 0
8560 13:09:06.289087 14, 0x0, sum = 1
8561 13:09:06.292568 15, 0x0, sum = 2
8562 13:09:06.292690 16, 0x0, sum = 3
8563 13:09:06.296107 17, 0x0, sum = 4
8564 13:09:06.296214 best_step = 15
8565 13:09:06.296295
8566 13:09:06.296363 ==
8567 13:09:06.299006 Dram Type= 6, Freq= 0, CH_1, rank 0
8568 13:09:06.302460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8569 13:09:06.302593 ==
8570 13:09:06.305482 RX Vref Scan: 1
8571 13:09:06.305581
8572 13:09:06.308820 Set Vref Range= 24 -> 127
8573 13:09:06.308957
8574 13:09:06.309042 RX Vref 24 -> 127, step: 1
8575 13:09:06.312422
8576 13:09:06.312521 RX Delay 19 -> 252, step: 4
8577 13:09:06.312605
8578 13:09:06.315324 Set Vref, RX VrefLevel [Byte0]: 24
8579 13:09:06.318795 [Byte1]: 24
8580 13:09:06.322228
8581 13:09:06.322327 Set Vref, RX VrefLevel [Byte0]: 25
8582 13:09:06.325919 [Byte1]: 25
8583 13:09:06.329905
8584 13:09:06.330002 Set Vref, RX VrefLevel [Byte0]: 26
8585 13:09:06.333445 [Byte1]: 26
8586 13:09:06.337543
8587 13:09:06.337613 Set Vref, RX VrefLevel [Byte0]: 27
8588 13:09:06.341108 [Byte1]: 27
8589 13:09:06.345062
8590 13:09:06.345169 Set Vref, RX VrefLevel [Byte0]: 28
8591 13:09:06.348356 [Byte1]: 28
8592 13:09:06.352537
8593 13:09:06.352622 Set Vref, RX VrefLevel [Byte0]: 29
8594 13:09:06.355855 [Byte1]: 29
8595 13:09:06.360136
8596 13:09:06.360248 Set Vref, RX VrefLevel [Byte0]: 30
8597 13:09:06.363510 [Byte1]: 30
8598 13:09:06.367832
8599 13:09:06.367940 Set Vref, RX VrefLevel [Byte0]: 31
8600 13:09:06.371151 [Byte1]: 31
8601 13:09:06.375305
8602 13:09:06.375404 Set Vref, RX VrefLevel [Byte0]: 32
8603 13:09:06.378383 [Byte1]: 32
8604 13:09:06.382896
8605 13:09:06.382996 Set Vref, RX VrefLevel [Byte0]: 33
8606 13:09:06.386233 [Byte1]: 33
8607 13:09:06.390864
8608 13:09:06.390965 Set Vref, RX VrefLevel [Byte0]: 34
8609 13:09:06.393973 [Byte1]: 34
8610 13:09:06.397848
8611 13:09:06.397943 Set Vref, RX VrefLevel [Byte0]: 35
8612 13:09:06.401473 [Byte1]: 35
8613 13:09:06.405961
8614 13:09:06.406059 Set Vref, RX VrefLevel [Byte0]: 36
8615 13:09:06.408810 [Byte1]: 36
8616 13:09:06.413382
8617 13:09:06.413480 Set Vref, RX VrefLevel [Byte0]: 37
8618 13:09:06.416373 [Byte1]: 37
8619 13:09:06.421082
8620 13:09:06.421187 Set Vref, RX VrefLevel [Byte0]: 38
8621 13:09:06.423996 [Byte1]: 38
8622 13:09:06.428310
8623 13:09:06.428380 Set Vref, RX VrefLevel [Byte0]: 39
8624 13:09:06.431521 [Byte1]: 39
8625 13:09:06.435851
8626 13:09:06.439311 Set Vref, RX VrefLevel [Byte0]: 40
8627 13:09:06.442515 [Byte1]: 40
8628 13:09:06.442613
8629 13:09:06.446024 Set Vref, RX VrefLevel [Byte0]: 41
8630 13:09:06.448949 [Byte1]: 41
8631 13:09:06.449043
8632 13:09:06.452240 Set Vref, RX VrefLevel [Byte0]: 42
8633 13:09:06.455346 [Byte1]: 42
8634 13:09:06.455447
8635 13:09:06.458992 Set Vref, RX VrefLevel [Byte0]: 43
8636 13:09:06.462286 [Byte1]: 43
8637 13:09:06.466483
8638 13:09:06.466577 Set Vref, RX VrefLevel [Byte0]: 44
8639 13:09:06.469396 [Byte1]: 44
8640 13:09:06.473946
8641 13:09:06.474042 Set Vref, RX VrefLevel [Byte0]: 45
8642 13:09:06.476857 [Byte1]: 45
8643 13:09:06.481348
8644 13:09:06.481426 Set Vref, RX VrefLevel [Byte0]: 46
8645 13:09:06.484504 [Byte1]: 46
8646 13:09:06.489150
8647 13:09:06.489254 Set Vref, RX VrefLevel [Byte0]: 47
8648 13:09:06.492411 [Byte1]: 47
8649 13:09:06.496465
8650 13:09:06.496543 Set Vref, RX VrefLevel [Byte0]: 48
8651 13:09:06.500140 [Byte1]: 48
8652 13:09:06.504004
8653 13:09:06.504101 Set Vref, RX VrefLevel [Byte0]: 49
8654 13:09:06.507470 [Byte1]: 49
8655 13:09:06.511948
8656 13:09:06.512045 Set Vref, RX VrefLevel [Byte0]: 50
8657 13:09:06.514936 [Byte1]: 50
8658 13:09:06.519378
8659 13:09:06.519472 Set Vref, RX VrefLevel [Byte0]: 51
8660 13:09:06.522498 [Byte1]: 51
8661 13:09:06.527076
8662 13:09:06.527174 Set Vref, RX VrefLevel [Byte0]: 52
8663 13:09:06.530034 [Byte1]: 52
8664 13:09:06.534360
8665 13:09:06.534457 Set Vref, RX VrefLevel [Byte0]: 53
8666 13:09:06.538065 [Byte1]: 53
8667 13:09:06.541984
8668 13:09:06.542083 Set Vref, RX VrefLevel [Byte0]: 54
8669 13:09:06.545465 [Byte1]: 54
8670 13:09:06.549371
8671 13:09:06.549442 Set Vref, RX VrefLevel [Byte0]: 55
8672 13:09:06.552844 [Byte1]: 55
8673 13:09:06.556929
8674 13:09:06.557027 Set Vref, RX VrefLevel [Byte0]: 56
8675 13:09:06.560441 [Byte1]: 56
8676 13:09:06.564418
8677 13:09:06.564489 Set Vref, RX VrefLevel [Byte0]: 57
8678 13:09:06.568022 [Byte1]: 57
8679 13:09:06.572153
8680 13:09:06.572226 Set Vref, RX VrefLevel [Byte0]: 58
8681 13:09:06.575324 [Byte1]: 58
8682 13:09:06.580055
8683 13:09:06.580150 Set Vref, RX VrefLevel [Byte0]: 59
8684 13:09:06.583220 [Byte1]: 59
8685 13:09:06.587630
8686 13:09:06.587730 Set Vref, RX VrefLevel [Byte0]: 60
8687 13:09:06.590564 [Byte1]: 60
8688 13:09:06.594910
8689 13:09:06.595009 Set Vref, RX VrefLevel [Byte0]: 61
8690 13:09:06.598359 [Byte1]: 61
8691 13:09:06.602611
8692 13:09:06.602711 Set Vref, RX VrefLevel [Byte0]: 62
8693 13:09:06.606067 [Byte1]: 62
8694 13:09:06.610123
8695 13:09:06.610236 Set Vref, RX VrefLevel [Byte0]: 63
8696 13:09:06.613551 [Byte1]: 63
8697 13:09:06.617753
8698 13:09:06.617824 Set Vref, RX VrefLevel [Byte0]: 64
8699 13:09:06.621010 [Byte1]: 64
8700 13:09:06.625386
8701 13:09:06.625489 Set Vref, RX VrefLevel [Byte0]: 65
8702 13:09:06.629102 [Byte1]: 65
8703 13:09:06.632851
8704 13:09:06.632950 Set Vref, RX VrefLevel [Byte0]: 66
8705 13:09:06.636497 [Byte1]: 66
8706 13:09:06.640429
8707 13:09:06.640525 Set Vref, RX VrefLevel [Byte0]: 67
8708 13:09:06.643950 [Byte1]: 67
8709 13:09:06.647992
8710 13:09:06.648096 Set Vref, RX VrefLevel [Byte0]: 68
8711 13:09:06.651535 [Byte1]: 68
8712 13:09:06.655824
8713 13:09:06.655930 Set Vref, RX VrefLevel [Byte0]: 69
8714 13:09:06.658651 [Byte1]: 69
8715 13:09:06.663308
8716 13:09:06.663402 Set Vref, RX VrefLevel [Byte0]: 70
8717 13:09:06.666388 [Byte1]: 70
8718 13:09:06.670417
8719 13:09:06.670513 Set Vref, RX VrefLevel [Byte0]: 71
8720 13:09:06.673709 [Byte1]: 71
8721 13:09:06.678523
8722 13:09:06.678618 Set Vref, RX VrefLevel [Byte0]: 72
8723 13:09:06.682064 [Byte1]: 72
8724 13:09:06.685865
8725 13:09:06.685963 Final RX Vref Byte 0 = 62 to rank0
8726 13:09:06.688861 Final RX Vref Byte 1 = 60 to rank0
8727 13:09:06.692467 Final RX Vref Byte 0 = 62 to rank1
8728 13:09:06.695467 Final RX Vref Byte 1 = 60 to rank1==
8729 13:09:06.699434 Dram Type= 6, Freq= 0, CH_1, rank 0
8730 13:09:06.706099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8731 13:09:06.706198 ==
8732 13:09:06.706291 DQS Delay:
8733 13:09:06.708861 DQS0 = 0, DQS1 = 0
8734 13:09:06.708956 DQM Delay:
8735 13:09:06.709048 DQM0 = 132, DQM1 = 127
8736 13:09:06.712233 DQ Delay:
8737 13:09:06.715470 DQ0 =138, DQ1 =132, DQ2 =118, DQ3 =132
8738 13:09:06.718736 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =128
8739 13:09:06.722112 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =120
8740 13:09:06.725577 DQ12 =138, DQ13 =138, DQ14 =134, DQ15 =136
8741 13:09:06.725678
8742 13:09:06.725766
8743 13:09:06.725847
8744 13:09:06.728879 [DramC_TX_OE_Calibration] TA2
8745 13:09:06.731836 Original DQ_B0 (3 6) =30, OEN = 27
8746 13:09:06.735410 Original DQ_B1 (3 6) =30, OEN = 27
8747 13:09:06.739033 24, 0x0, End_B0=24 End_B1=24
8748 13:09:06.739133 25, 0x0, End_B0=25 End_B1=25
8749 13:09:06.741777 26, 0x0, End_B0=26 End_B1=26
8750 13:09:06.745212 27, 0x0, End_B0=27 End_B1=27
8751 13:09:06.748820 28, 0x0, End_B0=28 End_B1=28
8752 13:09:06.751621 29, 0x0, End_B0=29 End_B1=29
8753 13:09:06.751720 30, 0x0, End_B0=30 End_B1=30
8754 13:09:06.754991 31, 0x5151, End_B0=30 End_B1=30
8755 13:09:06.758638 Byte0 end_step=30 best_step=27
8756 13:09:06.762238 Byte1 end_step=30 best_step=27
8757 13:09:06.764989 Byte0 TX OE(2T, 0.5T) = (3, 3)
8758 13:09:06.768366 Byte1 TX OE(2T, 0.5T) = (3, 3)
8759 13:09:06.768436
8760 13:09:06.768494
8761 13:09:06.774962 [DQSOSCAuto] RK0, (LSB)MR18= 0xd17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8762 13:09:06.778546 CH1 RK0: MR19=303, MR18=D17
8763 13:09:06.784517 CH1_RK0: MR19=0x303, MR18=0xD17, DQSOSC=398, MR23=63, INC=23, DEC=15
8764 13:09:06.784613
8765 13:09:06.788215 ----->DramcWriteLeveling(PI) begin...
8766 13:09:06.788292 ==
8767 13:09:06.791198 Dram Type= 6, Freq= 0, CH_1, rank 1
8768 13:09:06.794661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8769 13:09:06.794731 ==
8770 13:09:06.798169 Write leveling (Byte 0): 24 => 24
8771 13:09:06.801426 Write leveling (Byte 1): 26 => 26
8772 13:09:06.804406 DramcWriteLeveling(PI) end<-----
8773 13:09:06.804502
8774 13:09:06.804593 ==
8775 13:09:06.807544 Dram Type= 6, Freq= 0, CH_1, rank 1
8776 13:09:06.811316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8777 13:09:06.814374 ==
8778 13:09:06.814474 [Gating] SW mode calibration
8779 13:09:06.820789 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8780 13:09:06.827489 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8781 13:09:06.831149 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 13:09:06.837818 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 13:09:06.840727 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8784 13:09:06.844315 1 4 12 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
8785 13:09:06.850768 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 13:09:06.854443 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 13:09:06.857370 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 13:09:06.864355 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 13:09:06.867494 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 13:09:06.870870 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8791 13:09:06.877425 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8792 13:09:06.880344 1 5 12 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
8793 13:09:06.883756 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 13:09:06.890324 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 13:09:06.893806 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 13:09:06.896732 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 13:09:06.903466 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 13:09:06.906822 1 6 4 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
8799 13:09:06.910290 1 6 8 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8800 13:09:06.916889 1 6 12 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8801 13:09:06.920086 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 13:09:06.923412 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 13:09:06.929494 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 13:09:06.932932 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 13:09:06.936213 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 13:09:06.942566 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8807 13:09:06.945923 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8808 13:09:06.949565 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8809 13:09:06.956248 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 13:09:06.959126 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 13:09:06.962844 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 13:09:06.969270 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 13:09:06.972697 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 13:09:06.975749 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 13:09:06.982118 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 13:09:06.985467 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 13:09:06.989095 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 13:09:06.995627 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 13:09:06.999016 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 13:09:07.002435 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 13:09:07.008868 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 13:09:07.012044 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8823 13:09:07.015503 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8824 13:09:07.022105 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8825 13:09:07.025396 Total UI for P1: 0, mck2ui 16
8826 13:09:07.028560 best dqsien dly found for B0: ( 1, 9, 6)
8827 13:09:07.031855 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8828 13:09:07.035227 Total UI for P1: 0, mck2ui 16
8829 13:09:07.038382 best dqsien dly found for B1: ( 1, 9, 10)
8830 13:09:07.041633 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8831 13:09:07.045199 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8832 13:09:07.045305
8833 13:09:07.048417 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8834 13:09:07.051653 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8835 13:09:07.054532 [Gating] SW calibration Done
8836 13:09:07.054641 ==
8837 13:09:07.058195 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 13:09:07.064865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 13:09:07.064965 ==
8840 13:09:07.065052 RX Vref Scan: 0
8841 13:09:07.065155
8842 13:09:07.067986 RX Vref 0 -> 0, step: 1
8843 13:09:07.068093
8844 13:09:07.070941 RX Delay 0 -> 252, step: 8
8845 13:09:07.074582 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8846 13:09:07.078012 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8847 13:09:07.081631 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8848 13:09:07.087591 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8849 13:09:07.090995 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8850 13:09:07.094327 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8851 13:09:07.097881 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8852 13:09:07.100803 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8853 13:09:07.107440 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8854 13:09:07.110925 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8855 13:09:07.113801 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8856 13:09:07.117428 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8857 13:09:07.120448 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8858 13:09:07.127358 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8859 13:09:07.130542 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8860 13:09:07.134098 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8861 13:09:07.134188 ==
8862 13:09:07.136958 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 13:09:07.140240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 13:09:07.143604 ==
8865 13:09:07.143697 DQS Delay:
8866 13:09:07.143780 DQS0 = 0, DQS1 = 0
8867 13:09:07.146959 DQM Delay:
8868 13:09:07.147054 DQM0 = 133, DQM1 = 130
8869 13:09:07.150087 DQ Delay:
8870 13:09:07.153538 DQ0 =139, DQ1 =131, DQ2 =119, DQ3 =131
8871 13:09:07.156729 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8872 13:09:07.160103 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8873 13:09:07.163460 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8874 13:09:07.163549
8875 13:09:07.163631
8876 13:09:07.163717 ==
8877 13:09:07.166574 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 13:09:07.170185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 13:09:07.170283 ==
8880 13:09:07.173280
8881 13:09:07.173373
8882 13:09:07.173455 TX Vref Scan disable
8883 13:09:07.176795 == TX Byte 0 ==
8884 13:09:07.179801 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8885 13:09:07.183250 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8886 13:09:07.186693 == TX Byte 1 ==
8887 13:09:07.190100 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8888 13:09:07.193064 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8889 13:09:07.193192 ==
8890 13:09:07.196271 Dram Type= 6, Freq= 0, CH_1, rank 1
8891 13:09:07.203080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8892 13:09:07.203182 ==
8893 13:09:07.215890
8894 13:09:07.219407 TX Vref early break, caculate TX vref
8895 13:09:07.222433 TX Vref=16, minBit 9, minWin=22, winSum=377
8896 13:09:07.225938 TX Vref=18, minBit 5, minWin=23, winSum=385
8897 13:09:07.229588 TX Vref=20, minBit 8, minWin=23, winSum=393
8898 13:09:07.232473 TX Vref=22, minBit 9, minWin=22, winSum=400
8899 13:09:07.235803 TX Vref=24, minBit 9, minWin=24, winSum=411
8900 13:09:07.242368 TX Vref=26, minBit 9, minWin=24, winSum=413
8901 13:09:07.245835 TX Vref=28, minBit 9, minWin=25, winSum=419
8902 13:09:07.249250 TX Vref=30, minBit 8, minWin=25, winSum=417
8903 13:09:07.252150 TX Vref=32, minBit 9, minWin=24, winSum=410
8904 13:09:07.255544 TX Vref=34, minBit 0, minWin=24, winSum=403
8905 13:09:07.258857 TX Vref=36, minBit 9, minWin=22, winSum=396
8906 13:09:07.265742 [TxChooseVref] Worse bit 9, Min win 25, Win sum 419, Final Vref 28
8907 13:09:07.265813
8908 13:09:07.269024 Final TX Range 0 Vref 28
8909 13:09:07.269114
8910 13:09:07.269226 ==
8911 13:09:07.272173 Dram Type= 6, Freq= 0, CH_1, rank 1
8912 13:09:07.275338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8913 13:09:07.275431 ==
8914 13:09:07.275520
8915 13:09:07.278873
8916 13:09:07.278965 TX Vref Scan disable
8917 13:09:07.285584 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8918 13:09:07.285660 == TX Byte 0 ==
8919 13:09:07.288932 u2DelayCellOfst[0]=14 cells (4 PI)
8920 13:09:07.292008 u2DelayCellOfst[1]=10 cells (3 PI)
8921 13:09:07.295578 u2DelayCellOfst[2]=0 cells (0 PI)
8922 13:09:07.298407 u2DelayCellOfst[3]=3 cells (1 PI)
8923 13:09:07.301811 u2DelayCellOfst[4]=7 cells (2 PI)
8924 13:09:07.304990 u2DelayCellOfst[5]=14 cells (4 PI)
8925 13:09:07.308508 u2DelayCellOfst[6]=14 cells (4 PI)
8926 13:09:07.311541 u2DelayCellOfst[7]=7 cells (2 PI)
8927 13:09:07.314918 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8928 13:09:07.318550 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8929 13:09:07.321377 == TX Byte 1 ==
8930 13:09:07.324564 u2DelayCellOfst[8]=0 cells (0 PI)
8931 13:09:07.328093 u2DelayCellOfst[9]=7 cells (2 PI)
8932 13:09:07.331126 u2DelayCellOfst[10]=14 cells (4 PI)
8933 13:09:07.334738 u2DelayCellOfst[11]=7 cells (2 PI)
8934 13:09:07.337685 u2DelayCellOfst[12]=17 cells (5 PI)
8935 13:09:07.341304 u2DelayCellOfst[13]=17 cells (5 PI)
8936 13:09:07.341396 u2DelayCellOfst[14]=21 cells (6 PI)
8937 13:09:07.344809 u2DelayCellOfst[15]=17 cells (5 PI)
8938 13:09:07.350833 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8939 13:09:07.354791 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8940 13:09:07.357634 DramC Write-DBI on
8941 13:09:07.357738 ==
8942 13:09:07.361264 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 13:09:07.364288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 13:09:07.364357 ==
8945 13:09:07.364432
8946 13:09:07.364515
8947 13:09:07.367548 TX Vref Scan disable
8948 13:09:07.367638 == TX Byte 0 ==
8949 13:09:07.373927 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8950 13:09:07.374031 == TX Byte 1 ==
8951 13:09:07.377606 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8952 13:09:07.380860 DramC Write-DBI off
8953 13:09:07.380951
8954 13:09:07.381043 [DATLAT]
8955 13:09:07.383958 Freq=1600, CH1 RK1
8956 13:09:07.384055
8957 13:09:07.384142 DATLAT Default: 0xf
8958 13:09:07.387278 0, 0xFFFF, sum = 0
8959 13:09:07.387384 1, 0xFFFF, sum = 0
8960 13:09:07.390523 2, 0xFFFF, sum = 0
8961 13:09:07.393809 3, 0xFFFF, sum = 0
8962 13:09:07.393907 4, 0xFFFF, sum = 0
8963 13:09:07.397319 5, 0xFFFF, sum = 0
8964 13:09:07.397419 6, 0xFFFF, sum = 0
8965 13:09:07.400781 7, 0xFFFF, sum = 0
8966 13:09:07.400876 8, 0xFFFF, sum = 0
8967 13:09:07.403676 9, 0xFFFF, sum = 0
8968 13:09:07.403768 10, 0xFFFF, sum = 0
8969 13:09:07.407052 11, 0xFFFF, sum = 0
8970 13:09:07.407157 12, 0xFFFF, sum = 0
8971 13:09:07.410393 13, 0xFFFF, sum = 0
8972 13:09:07.410489 14, 0x0, sum = 1
8973 13:09:07.413799 15, 0x0, sum = 2
8974 13:09:07.413896 16, 0x0, sum = 3
8975 13:09:07.417420 17, 0x0, sum = 4
8976 13:09:07.417490 best_step = 15
8977 13:09:07.417547
8978 13:09:07.417612 ==
8979 13:09:07.420335 Dram Type= 6, Freq= 0, CH_1, rank 1
8980 13:09:07.423896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8981 13:09:07.426892 ==
8982 13:09:07.426993 RX Vref Scan: 0
8983 13:09:07.427077
8984 13:09:07.430508 RX Vref 0 -> 0, step: 1
8985 13:09:07.430608
8986 13:09:07.433982 RX Delay 19 -> 252, step: 4
8987 13:09:07.437001 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8988 13:09:07.440524 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
8989 13:09:07.443445 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8990 13:09:07.449993 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8991 13:09:07.453533 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8992 13:09:07.456779 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8993 13:09:07.459797 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8994 13:09:07.463302 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8995 13:09:07.470093 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8996 13:09:07.473463 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8997 13:09:07.476775 iDelay=195, Bit 10, Center 132 (79 ~ 186) 108
8998 13:09:07.480158 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8999 13:09:07.482927 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9000 13:09:07.489645 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9001 13:09:07.493044 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9002 13:09:07.496770 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9003 13:09:07.496868 ==
9004 13:09:07.499487 Dram Type= 6, Freq= 0, CH_1, rank 1
9005 13:09:07.502927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9006 13:09:07.506571 ==
9007 13:09:07.506661 DQS Delay:
9008 13:09:07.506753 DQS0 = 0, DQS1 = 0
9009 13:09:07.509392 DQM Delay:
9010 13:09:07.509482 DQM0 = 131, DQM1 = 128
9011 13:09:07.512682 DQ Delay:
9012 13:09:07.516096 DQ0 =134, DQ1 =128, DQ2 =120, DQ3 =130
9013 13:09:07.519491 DQ4 =128, DQ5 =142, DQ6 =138, DQ7 =128
9014 13:09:07.522848 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
9015 13:09:07.525794 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =136
9016 13:09:07.525885
9017 13:09:07.525982
9018 13:09:07.526074
9019 13:09:07.529357 [DramC_TX_OE_Calibration] TA2
9020 13:09:07.532810 Original DQ_B0 (3 6) =30, OEN = 27
9021 13:09:07.535865 Original DQ_B1 (3 6) =30, OEN = 27
9022 13:09:07.539396 24, 0x0, End_B0=24 End_B1=24
9023 13:09:07.539501 25, 0x0, End_B0=25 End_B1=25
9024 13:09:07.542404 26, 0x0, End_B0=26 End_B1=26
9025 13:09:07.545944 27, 0x0, End_B0=27 End_B1=27
9026 13:09:07.548953 28, 0x0, End_B0=28 End_B1=28
9027 13:09:07.549054 29, 0x0, End_B0=29 End_B1=29
9028 13:09:07.552396 30, 0x0, End_B0=30 End_B1=30
9029 13:09:07.556001 31, 0x4141, End_B0=30 End_B1=30
9030 13:09:07.558976 Byte0 end_step=30 best_step=27
9031 13:09:07.562407 Byte1 end_step=30 best_step=27
9032 13:09:07.565881 Byte0 TX OE(2T, 0.5T) = (3, 3)
9033 13:09:07.569092 Byte1 TX OE(2T, 0.5T) = (3, 3)
9034 13:09:07.569212
9035 13:09:07.569297
9036 13:09:07.575718 [DQSOSCAuto] RK1, (LSB)MR18= 0x121f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
9037 13:09:07.579134 CH1 RK1: MR19=303, MR18=121F
9038 13:09:07.586113 CH1_RK1: MR19=0x303, MR18=0x121F, DQSOSC=394, MR23=63, INC=23, DEC=15
9039 13:09:07.588959 [RxdqsGatingPostProcess] freq 1600
9040 13:09:07.592394 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9041 13:09:07.595642 best DQS0 dly(2T, 0.5T) = (1, 1)
9042 13:09:07.598641 best DQS1 dly(2T, 0.5T) = (1, 1)
9043 13:09:07.602412 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9044 13:09:07.605505 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9045 13:09:07.608762 best DQS0 dly(2T, 0.5T) = (1, 1)
9046 13:09:07.612119 best DQS1 dly(2T, 0.5T) = (1, 1)
9047 13:09:07.615084 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9048 13:09:07.618421 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9049 13:09:07.621831 Pre-setting of DQS Precalculation
9050 13:09:07.625097 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9051 13:09:07.631611 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9052 13:09:07.641793 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9053 13:09:07.641901
9054 13:09:07.642001
9055 13:09:07.644742 [Calibration Summary] 3200 Mbps
9056 13:09:07.644857 CH 0, Rank 0
9057 13:09:07.648373 SW Impedance : PASS
9058 13:09:07.648488 DUTY Scan : NO K
9059 13:09:07.651850 ZQ Calibration : PASS
9060 13:09:07.651956 Jitter Meter : NO K
9061 13:09:07.654968 CBT Training : PASS
9062 13:09:07.658426 Write leveling : PASS
9063 13:09:07.658521 RX DQS gating : PASS
9064 13:09:07.661329 RX DQ/DQS(RDDQC) : PASS
9065 13:09:07.665043 TX DQ/DQS : PASS
9066 13:09:07.665149 RX DATLAT : PASS
9067 13:09:07.668169 RX DQ/DQS(Engine): PASS
9068 13:09:07.671574 TX OE : PASS
9069 13:09:07.671668 All Pass.
9070 13:09:07.671766
9071 13:09:07.671849 CH 0, Rank 1
9072 13:09:07.674594 SW Impedance : PASS
9073 13:09:07.677925 DUTY Scan : NO K
9074 13:09:07.678021 ZQ Calibration : PASS
9075 13:09:07.681308 Jitter Meter : NO K
9076 13:09:07.684514 CBT Training : PASS
9077 13:09:07.684592 Write leveling : PASS
9078 13:09:07.687812 RX DQS gating : PASS
9079 13:09:07.691635 RX DQ/DQS(RDDQC) : PASS
9080 13:09:07.691744 TX DQ/DQS : PASS
9081 13:09:07.694499 RX DATLAT : PASS
9082 13:09:07.697551 RX DQ/DQS(Engine): PASS
9083 13:09:07.697648 TX OE : PASS
9084 13:09:07.700981 All Pass.
9085 13:09:07.701077
9086 13:09:07.701170 CH 1, Rank 0
9087 13:09:07.704429 SW Impedance : PASS
9088 13:09:07.704526 DUTY Scan : NO K
9089 13:09:07.707529 ZQ Calibration : PASS
9090 13:09:07.711267 Jitter Meter : NO K
9091 13:09:07.711369 CBT Training : PASS
9092 13:09:07.714193 Write leveling : PASS
9093 13:09:07.717590 RX DQS gating : PASS
9094 13:09:07.717695 RX DQ/DQS(RDDQC) : PASS
9095 13:09:07.721057 TX DQ/DQS : PASS
9096 13:09:07.721160 RX DATLAT : PASS
9097 13:09:07.724452 RX DQ/DQS(Engine): PASS
9098 13:09:07.727595 TX OE : PASS
9099 13:09:07.727704 All Pass.
9100 13:09:07.727789
9101 13:09:07.730834 CH 1, Rank 1
9102 13:09:07.730933 SW Impedance : PASS
9103 13:09:07.733938 DUTY Scan : NO K
9104 13:09:07.734035 ZQ Calibration : PASS
9105 13:09:07.737278 Jitter Meter : NO K
9106 13:09:07.740784 CBT Training : PASS
9107 13:09:07.740883 Write leveling : PASS
9108 13:09:07.743812 RX DQS gating : PASS
9109 13:09:07.747441 RX DQ/DQS(RDDQC) : PASS
9110 13:09:07.747536 TX DQ/DQS : PASS
9111 13:09:07.750912 RX DATLAT : PASS
9112 13:09:07.754023 RX DQ/DQS(Engine): PASS
9113 13:09:07.754117 TX OE : PASS
9114 13:09:07.756964 All Pass.
9115 13:09:07.757056
9116 13:09:07.757160 DramC Write-DBI on
9117 13:09:07.760392 PER_BANK_REFRESH: Hybrid Mode
9118 13:09:07.760484 TX_TRACKING: ON
9119 13:09:07.770643 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9120 13:09:07.780383 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9121 13:09:07.787064 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9122 13:09:07.789906 [FAST_K] Save calibration result to emmc
9123 13:09:07.793436 sync common calibartion params.
9124 13:09:07.793536 sync cbt_mode0:1, 1:1
9125 13:09:07.796605 dram_init: ddr_geometry: 2
9126 13:09:07.800108 dram_init: ddr_geometry: 2
9127 13:09:07.803283 dram_init: ddr_geometry: 2
9128 13:09:07.803372 0:dram_rank_size:100000000
9129 13:09:07.807143 1:dram_rank_size:100000000
9130 13:09:07.813210 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9131 13:09:07.813313 DFS_SHUFFLE_HW_MODE: ON
9132 13:09:07.819847 dramc_set_vcore_voltage set vcore to 725000
9133 13:09:07.819943 Read voltage for 1600, 0
9134 13:09:07.823119 Vio18 = 0
9135 13:09:07.823217 Vcore = 725000
9136 13:09:07.823306 Vdram = 0
9137 13:09:07.826169 Vddq = 0
9138 13:09:07.826264 Vmddr = 0
9139 13:09:07.829647 switch to 3200 Mbps bootup
9140 13:09:07.829747 [DramcRunTimeConfig]
9141 13:09:07.829841 PHYPLL
9142 13:09:07.832925 DPM_CONTROL_AFTERK: ON
9143 13:09:07.836718 PER_BANK_REFRESH: ON
9144 13:09:07.836827 REFRESH_OVERHEAD_REDUCTION: ON
9145 13:09:07.839442 CMD_PICG_NEW_MODE: OFF
9146 13:09:07.842885 XRTWTW_NEW_MODE: ON
9147 13:09:07.842994 XRTRTR_NEW_MODE: ON
9148 13:09:07.846126 TX_TRACKING: ON
9149 13:09:07.846235 RDSEL_TRACKING: OFF
9150 13:09:07.849292 DQS Precalculation for DVFS: ON
9151 13:09:07.849363 RX_TRACKING: OFF
9152 13:09:07.852962 HW_GATING DBG: ON
9153 13:09:07.853066 ZQCS_ENABLE_LP4: ON
9154 13:09:07.855908 RX_PICG_NEW_MODE: ON
9155 13:09:07.859421 TX_PICG_NEW_MODE: ON
9156 13:09:07.859524 ENABLE_RX_DCM_DPHY: ON
9157 13:09:07.863004 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9158 13:09:07.865959 DUMMY_READ_FOR_TRACKING: OFF
9159 13:09:07.869593 !!! SPM_CONTROL_AFTERK: OFF
9160 13:09:07.872586 !!! SPM could not control APHY
9161 13:09:07.872689 IMPEDANCE_TRACKING: ON
9162 13:09:07.876134 TEMP_SENSOR: ON
9163 13:09:07.876237 HW_SAVE_FOR_SR: OFF
9164 13:09:07.879013 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9165 13:09:07.882232 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9166 13:09:07.885570 Read ODT Tracking: ON
9167 13:09:07.888974 Refresh Rate DeBounce: ON
9168 13:09:07.889085 DFS_NO_QUEUE_FLUSH: ON
9169 13:09:07.891914 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9170 13:09:07.895315 ENABLE_DFS_RUNTIME_MRW: OFF
9171 13:09:07.898787 DDR_RESERVE_NEW_MODE: ON
9172 13:09:07.898897 MR_CBT_SWITCH_FREQ: ON
9173 13:09:07.902154 =========================
9174 13:09:07.920459 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9175 13:09:07.924131 dram_init: ddr_geometry: 2
9176 13:09:07.942352 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9177 13:09:07.945656 dram_init: dram init end (result: 0)
9178 13:09:07.952204 DRAM-K: Full calibration passed in 24394 msecs
9179 13:09:07.955397 MRC: failed to locate region type 0.
9180 13:09:07.955503 DRAM rank0 size:0x100000000,
9181 13:09:07.958882 DRAM rank1 size=0x100000000
9182 13:09:07.968833 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9183 13:09:07.975330 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9184 13:09:07.981644 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9185 13:09:07.991500 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9186 13:09:07.991611 DRAM rank0 size:0x100000000,
9187 13:09:07.995247 DRAM rank1 size=0x100000000
9188 13:09:07.995354 CBMEM:
9189 13:09:07.997983 IMD: root @ 0xfffff000 254 entries.
9190 13:09:08.001386 IMD: root @ 0xffffec00 62 entries.
9191 13:09:08.004869 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9192 13:09:08.011872 WARNING: RO_VPD is uninitialized or empty.
9193 13:09:08.014886 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9194 13:09:08.022170 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9195 13:09:08.034643 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9196 13:09:08.046381 BS: romstage times (exec / console): total (unknown) / 23924 ms
9197 13:09:08.046498
9198 13:09:08.046589
9199 13:09:08.056640 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9200 13:09:08.059328 ARM64: Exception handlers installed.
9201 13:09:08.062611 ARM64: Testing exception
9202 13:09:08.065952 ARM64: Done test exception
9203 13:09:08.066053 Enumerating buses...
9204 13:09:08.069033 Show all devs... Before device enumeration.
9205 13:09:08.072389 Root Device: enabled 1
9206 13:09:08.076056 CPU_CLUSTER: 0: enabled 1
9207 13:09:08.076155 CPU: 00: enabled 1
9208 13:09:08.079091 Compare with tree...
9209 13:09:08.079186 Root Device: enabled 1
9210 13:09:08.082562 CPU_CLUSTER: 0: enabled 1
9211 13:09:08.085512 CPU: 00: enabled 1
9212 13:09:08.085608 Root Device scanning...
9213 13:09:08.088649 scan_static_bus for Root Device
9214 13:09:08.092203 CPU_CLUSTER: 0 enabled
9215 13:09:08.095643 scan_static_bus for Root Device done
9216 13:09:08.099053 scan_bus: bus Root Device finished in 8 msecs
9217 13:09:08.099149 done
9218 13:09:08.105260 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9219 13:09:08.108896 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9220 13:09:08.115229 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9221 13:09:08.121489 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9222 13:09:08.121594 Allocating resources...
9223 13:09:08.125057 Reading resources...
9224 13:09:08.128198 Root Device read_resources bus 0 link: 0
9225 13:09:08.131587 DRAM rank0 size:0x100000000,
9226 13:09:08.131687 DRAM rank1 size=0x100000000
9227 13:09:08.137894 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9228 13:09:08.138001 CPU: 00 missing read_resources
9229 13:09:08.144865 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9230 13:09:08.147933 Root Device read_resources bus 0 link: 0 done
9231 13:09:08.151152 Done reading resources.
9232 13:09:08.154658 Show resources in subtree (Root Device)...After reading.
9233 13:09:08.158222 Root Device child on link 0 CPU_CLUSTER: 0
9234 13:09:08.164547 CPU_CLUSTER: 0 child on link 0 CPU: 00
9235 13:09:08.171236 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9236 13:09:08.173914 CPU: 00
9237 13:09:08.177501 Root Device assign_resources, bus 0 link: 0
9238 13:09:08.181035 CPU_CLUSTER: 0 missing set_resources
9239 13:09:08.184280 Root Device assign_resources, bus 0 link: 0 done
9240 13:09:08.187224 Done setting resources.
9241 13:09:08.190833 Show resources in subtree (Root Device)...After assigning values.
9242 13:09:08.197250 Root Device child on link 0 CPU_CLUSTER: 0
9243 13:09:08.200664 CPU_CLUSTER: 0 child on link 0 CPU: 00
9244 13:09:08.207111 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9245 13:09:08.210421 CPU: 00
9246 13:09:08.210518 Done allocating resources.
9247 13:09:08.217335 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9248 13:09:08.220496 Enabling resources...
9249 13:09:08.220591 done.
9250 13:09:08.223486 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9251 13:09:08.227238 Initializing devices...
9252 13:09:08.227333 Root Device init
9253 13:09:08.229863 init hardware done!
9254 13:09:08.233635 0x00000018: ctrlr->caps
9255 13:09:08.233748 52.000 MHz: ctrlr->f_max
9256 13:09:08.236640 0.400 MHz: ctrlr->f_min
9257 13:09:08.240192 0x40ff8080: ctrlr->voltages
9258 13:09:08.240303 sclk: 390625
9259 13:09:08.240400 Bus Width = 1
9260 13:09:08.243080 sclk: 390625
9261 13:09:08.243179 Bus Width = 1
9262 13:09:08.246774 Early init status = 3
9263 13:09:08.249809 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9264 13:09:08.253931 in-header: 03 fc 00 00 01 00 00 00
9265 13:09:08.257111 in-data: 00
9266 13:09:08.260492 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9267 13:09:08.265120 in-header: 03 fd 00 00 00 00 00 00
9268 13:09:08.268816 in-data:
9269 13:09:08.271790 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9270 13:09:08.276030 in-header: 03 fc 00 00 01 00 00 00
9271 13:09:08.279261 in-data: 00
9272 13:09:08.282791 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9273 13:09:08.288002 in-header: 03 fd 00 00 00 00 00 00
9274 13:09:08.291496 in-data:
9275 13:09:08.294506 [SSUSB] Setting up USB HOST controller...
9276 13:09:08.298191 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9277 13:09:08.301145 [SSUSB] phy power-on done.
9278 13:09:08.304352 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9279 13:09:08.311361 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9280 13:09:08.314209 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9281 13:09:08.320901 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9282 13:09:08.327527 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9283 13:09:08.334281 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9284 13:09:08.340596 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9285 13:09:08.347114 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9286 13:09:08.350781 SPM: binary array size = 0x9dc
9287 13:09:08.354117 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9288 13:09:08.360342 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9289 13:09:08.367426 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9290 13:09:08.373775 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9291 13:09:08.377145 configure_display: Starting display init
9292 13:09:08.411281 anx7625_power_on_init: Init interface.
9293 13:09:08.414194 anx7625_disable_pd_protocol: Disabled PD feature.
9294 13:09:08.417621 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9295 13:09:08.445924 anx7625_start_dp_work: Secure OCM version=00
9296 13:09:08.448859 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9297 13:09:08.463474 sp_tx_get_edid_block: EDID Block = 1
9298 13:09:08.566412 Extracted contents:
9299 13:09:08.569893 header: 00 ff ff ff ff ff ff 00
9300 13:09:08.572826 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9301 13:09:08.576634 version: 01 04
9302 13:09:08.579711 basic params: 95 1f 11 78 0a
9303 13:09:08.582659 chroma info: 76 90 94 55 54 90 27 21 50 54
9304 13:09:08.586116 established: 00 00 00
9305 13:09:08.592711 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9306 13:09:08.599367 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9307 13:09:08.602267 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9308 13:09:08.609267 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9309 13:09:08.615756 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9310 13:09:08.618880 extensions: 00
9311 13:09:08.618975 checksum: fb
9312 13:09:08.619062
9313 13:09:08.625659 Manufacturer: IVO Model 57d Serial Number 0
9314 13:09:08.625748 Made week 0 of 2020
9315 13:09:08.629022 EDID version: 1.4
9316 13:09:08.629115 Digital display
9317 13:09:08.632318 6 bits per primary color channel
9318 13:09:08.635178 DisplayPort interface
9319 13:09:08.635294 Maximum image size: 31 cm x 17 cm
9320 13:09:08.638879 Gamma: 220%
9321 13:09:08.638976 Check DPMS levels
9322 13:09:08.645311 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9323 13:09:08.648925 First detailed timing is preferred timing
9324 13:09:08.651839 Established timings supported:
9325 13:09:08.651940 Standard timings supported:
9326 13:09:08.655371 Detailed timings
9327 13:09:08.658426 Hex of detail: 383680a07038204018303c0035ae10000019
9328 13:09:08.665379 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9329 13:09:08.668391 0780 0798 07c8 0820 hborder 0
9330 13:09:08.671717 0438 043b 0447 0458 vborder 0
9331 13:09:08.674834 -hsync -vsync
9332 13:09:08.674931 Did detailed timing
9333 13:09:08.682047 Hex of detail: 000000000000000000000000000000000000
9334 13:09:08.684695 Manufacturer-specified data, tag 0
9335 13:09:08.688405 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9336 13:09:08.691198 ASCII string: InfoVision
9337 13:09:08.694692 Hex of detail: 000000fe00523134304e574635205248200a
9338 13:09:08.697961 ASCII string: R140NWF5 RH
9339 13:09:08.698056 Checksum
9340 13:09:08.701641 Checksum: 0xfb (valid)
9341 13:09:08.704751 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9342 13:09:08.708092 DSI data_rate: 832800000 bps
9343 13:09:08.714683 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9344 13:09:08.718053 anx7625_parse_edid: pixelclock(138800).
9345 13:09:08.720998 hactive(1920), hsync(48), hfp(24), hbp(88)
9346 13:09:08.724582 vactive(1080), vsync(12), vfp(3), vbp(17)
9347 13:09:08.727524 anx7625_dsi_config: config dsi.
9348 13:09:08.734164 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9349 13:09:08.748160 anx7625_dsi_config: success to config DSI
9350 13:09:08.751700 anx7625_dp_start: MIPI phy setup OK.
9351 13:09:08.755053 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9352 13:09:08.758369 mtk_ddp_mode_set invalid vrefresh 60
9353 13:09:08.761838 main_disp_path_setup
9354 13:09:08.761910 ovl_layer_smi_id_en
9355 13:09:08.764825 ovl_layer_smi_id_en
9356 13:09:08.764916 ccorr_config
9357 13:09:08.765000 aal_config
9358 13:09:08.768498 gamma_config
9359 13:09:08.768590 postmask_config
9360 13:09:08.771350 dither_config
9361 13:09:08.774719 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9362 13:09:08.781141 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9363 13:09:08.784585 Root Device init finished in 553 msecs
9364 13:09:08.788175 CPU_CLUSTER: 0 init
9365 13:09:08.794655 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9366 13:09:08.800963 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9367 13:09:08.801057 APU_MBOX 0x190000b0 = 0x10001
9368 13:09:08.804481 APU_MBOX 0x190001b0 = 0x10001
9369 13:09:08.807859 APU_MBOX 0x190005b0 = 0x10001
9370 13:09:08.811116 APU_MBOX 0x190006b0 = 0x10001
9371 13:09:08.817816 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9372 13:09:08.827036 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9373 13:09:08.839791 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9374 13:09:08.846181 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9375 13:09:08.857703 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9376 13:09:08.867043 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9377 13:09:08.870187 CPU_CLUSTER: 0 init finished in 81 msecs
9378 13:09:08.873569 Devices initialized
9379 13:09:08.877022 Show all devs... After init.
9380 13:09:08.877119 Root Device: enabled 1
9381 13:09:08.880525 CPU_CLUSTER: 0: enabled 1
9382 13:09:08.883480 CPU: 00: enabled 1
9383 13:09:08.886849 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9384 13:09:08.889826 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9385 13:09:08.893232 ELOG: NV offset 0x57f000 size 0x1000
9386 13:09:08.900235 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9387 13:09:08.906705 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9388 13:09:08.910190 ELOG: Event(17) added with size 13 at 2024-07-18 13:09:08 UTC
9389 13:09:08.916560 out: cmd=0x121: 03 db 21 01 00 00 00 00
9390 13:09:08.919983 in-header: 03 63 00 00 2c 00 00 00
9391 13:09:08.929650 in-data: dc 70 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9392 13:09:08.936181 ELOG: Event(A1) added with size 10 at 2024-07-18 13:09:08 UTC
9393 13:09:08.943210 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9394 13:09:08.949768 ELOG: Event(A0) added with size 9 at 2024-07-18 13:09:08 UTC
9395 13:09:08.952893 elog_add_boot_reason: Logged dev mode boot
9396 13:09:08.959604 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9397 13:09:08.959704 Finalize devices...
9398 13:09:08.962966 Devices finalized
9399 13:09:08.965813 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9400 13:09:08.969428 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9401 13:09:08.972761 in-header: 03 07 00 00 08 00 00 00
9402 13:09:08.975910 in-data: aa e4 47 04 13 02 00 00
9403 13:09:08.979096 Chrome EC: UHEPI supported
9404 13:09:08.985980 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9405 13:09:08.988940 in-header: 03 a9 00 00 08 00 00 00
9406 13:09:08.992861 in-data: 84 60 60 08 00 00 00 00
9407 13:09:08.999344 ELOG: Event(91) added with size 10 at 2024-07-18 13:09:09 UTC
9408 13:09:09.002373 Chrome EC: clear events_b mask to 0x0000000020004000
9409 13:09:09.008702 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9410 13:09:09.012833 in-header: 03 fd 00 00 00 00 00 00
9411 13:09:09.016270 in-data:
9412 13:09:09.019695 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9413 13:09:09.022909 Writing coreboot table at 0xffe64000
9414 13:09:09.029752 0. 000000000010a000-0000000000113fff: RAMSTAGE
9415 13:09:09.032787 1. 0000000040000000-00000000400fffff: RAM
9416 13:09:09.036049 2. 0000000040100000-000000004032afff: RAMSTAGE
9417 13:09:09.039163 3. 000000004032b000-00000000545fffff: RAM
9418 13:09:09.042880 4. 0000000054600000-000000005465ffff: BL31
9419 13:09:09.046171 5. 0000000054660000-00000000ffe63fff: RAM
9420 13:09:09.052874 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9421 13:09:09.055791 7. 0000000100000000-000000023fffffff: RAM
9422 13:09:09.059181 Passing 5 GPIOs to payload:
9423 13:09:09.062573 NAME | PORT | POLARITY | VALUE
9424 13:09:09.069058 EC in RW | 0x000000aa | low | undefined
9425 13:09:09.072503 EC interrupt | 0x00000005 | low | undefined
9426 13:09:09.079053 TPM interrupt | 0x000000ab | high | undefined
9427 13:09:09.082654 SD card detect | 0x00000011 | high | undefined
9428 13:09:09.085277 speaker enable | 0x00000093 | high | undefined
9429 13:09:09.092203 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9430 13:09:09.095496 in-header: 03 f9 00 00 02 00 00 00
9431 13:09:09.095596 in-data: 02 00
9432 13:09:09.098471 ADC[4]: Raw value=902216 ID=7
9433 13:09:09.102468 ADC[3]: Raw value=213546 ID=1
9434 13:09:09.102560 RAM Code: 0x71
9435 13:09:09.105091 ADC[6]: Raw value=74630 ID=0
9436 13:09:09.108696 ADC[5]: Raw value=213546 ID=1
9437 13:09:09.108789 SKU Code: 0x1
9438 13:09:09.115059 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum def5
9439 13:09:09.118640 coreboot table: 964 bytes.
9440 13:09:09.121706 IMD ROOT 0. 0xfffff000 0x00001000
9441 13:09:09.125412 IMD SMALL 1. 0xffffe000 0x00001000
9442 13:09:09.128205 RO MCACHE 2. 0xffffc000 0x00001104
9443 13:09:09.131427 CONSOLE 3. 0xfff7c000 0x00080000
9444 13:09:09.135126 FMAP 4. 0xfff7b000 0x00000452
9445 13:09:09.135221 TIME STAMP 5. 0xfff7a000 0x00000910
9446 13:09:09.138458 VBOOT WORK 6. 0xfff66000 0x00014000
9447 13:09:09.141466 RAMOOPS 7. 0xffe66000 0x00100000
9448 13:09:09.144881 COREBOOT 8. 0xffe64000 0x00002000
9449 13:09:09.148276 IMD small region:
9450 13:09:09.151473 IMD ROOT 0. 0xffffec00 0x00000400
9451 13:09:09.154715 VPD 1. 0xffffeb80 0x0000006c
9452 13:09:09.158200 MMC STATUS 2. 0xffffeb60 0x00000004
9453 13:09:09.164787 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9454 13:09:09.170806 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9455 13:09:09.210034 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9456 13:09:09.213584 Checking segment from ROM address 0x40100000
9457 13:09:09.216955 Checking segment from ROM address 0x4010001c
9458 13:09:09.223116 Loading segment from ROM address 0x40100000
9459 13:09:09.223212 code (compression=0)
9460 13:09:09.233620 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9461 13:09:09.240378 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9462 13:09:09.240457 it's not compressed!
9463 13:09:09.246678 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9464 13:09:09.252999 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9465 13:09:09.270648 Loading segment from ROM address 0x4010001c
9466 13:09:09.270757 Entry Point 0x80000000
9467 13:09:09.273778 Loaded segments
9468 13:09:09.276777 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9469 13:09:09.283664 Jumping to boot code at 0x80000000(0xffe64000)
9470 13:09:09.290202 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9471 13:09:09.296644 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9472 13:09:09.305167 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9473 13:09:09.308253 Checking segment from ROM address 0x40100000
9474 13:09:09.311502 Checking segment from ROM address 0x4010001c
9475 13:09:09.318236 Loading segment from ROM address 0x40100000
9476 13:09:09.318340 code (compression=1)
9477 13:09:09.324906 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9478 13:09:09.334759 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9479 13:09:09.334872 using LZMA
9480 13:09:09.343394 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9481 13:09:09.349723 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9482 13:09:09.353216 Loading segment from ROM address 0x4010001c
9483 13:09:09.353290 Entry Point 0x54601000
9484 13:09:09.356938 Loaded segments
9485 13:09:09.359904 NOTICE: MT8192 bl31_setup
9486 13:09:09.367174 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9487 13:09:09.370421 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9488 13:09:09.373361 WARNING: region 0:
9489 13:09:09.376911 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9490 13:09:09.377009 WARNING: region 1:
9491 13:09:09.383198 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9492 13:09:09.386853 WARNING: region 2:
9493 13:09:09.390347 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9494 13:09:09.393196 WARNING: region 3:
9495 13:09:09.396697 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9496 13:09:09.400191 WARNING: region 4:
9497 13:09:09.406588 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9498 13:09:09.406699 WARNING: region 5:
9499 13:09:09.410173 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9500 13:09:09.413574 WARNING: region 6:
9501 13:09:09.416486 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9502 13:09:09.419759 WARNING: region 7:
9503 13:09:09.422882 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9504 13:09:09.430153 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9505 13:09:09.432865 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9506 13:09:09.439894 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9507 13:09:09.442710 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9508 13:09:09.446379 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9509 13:09:09.452786 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9510 13:09:09.456262 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9511 13:09:09.459581 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9512 13:09:09.466138 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9513 13:09:09.469110 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9514 13:09:09.475610 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9515 13:09:09.478897 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9516 13:09:09.482586 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9517 13:09:09.489115 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9518 13:09:09.492463 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9519 13:09:09.495478 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9520 13:09:09.502335 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9521 13:09:09.505658 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9522 13:09:09.512065 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9523 13:09:09.515474 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9524 13:09:09.518877 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9525 13:09:09.525253 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9526 13:09:09.529012 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9527 13:09:09.535129 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9528 13:09:09.538403 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9529 13:09:09.542021 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9530 13:09:09.548373 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9531 13:09:09.551777 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9532 13:09:09.558230 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9533 13:09:09.561486 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9534 13:09:09.568101 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9535 13:09:09.571549 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9536 13:09:09.575230 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9537 13:09:09.578207 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9538 13:09:09.585107 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9539 13:09:09.587909 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9540 13:09:09.591352 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9541 13:09:09.594970 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9542 13:09:09.601109 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9543 13:09:09.604808 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9544 13:09:09.607735 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9545 13:09:09.611098 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9546 13:09:09.617835 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9547 13:09:09.621004 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9548 13:09:09.624527 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9549 13:09:09.631186 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9550 13:09:09.634611 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9551 13:09:09.637647 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9552 13:09:09.644124 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9553 13:09:09.647316 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9554 13:09:09.651109 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9555 13:09:09.657495 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9556 13:09:09.660937 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9557 13:09:09.667410 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9558 13:09:09.670771 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9559 13:09:09.677325 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9560 13:09:09.680251 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9561 13:09:09.683950 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9562 13:09:09.690156 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9563 13:09:09.693743 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9564 13:09:09.699982 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9565 13:09:09.703392 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9566 13:09:09.709906 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9567 13:09:09.713554 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9568 13:09:09.720235 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9569 13:09:09.723229 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9570 13:09:09.730185 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9571 13:09:09.733155 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9572 13:09:09.736832 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9573 13:09:09.743004 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9574 13:09:09.746509 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9575 13:09:09.753150 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9576 13:09:09.756625 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9577 13:09:09.762668 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9578 13:09:09.766225 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9579 13:09:09.772802 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9580 13:09:09.776275 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9581 13:09:09.779724 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9582 13:09:09.786179 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9583 13:09:09.789000 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9584 13:09:09.795950 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9585 13:09:09.798897 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9586 13:09:09.805949 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9587 13:09:09.808980 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9588 13:09:09.815769 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9589 13:09:09.818981 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9590 13:09:09.825651 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9591 13:09:09.828820 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9592 13:09:09.832196 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9593 13:09:09.838508 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9594 13:09:09.841862 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9595 13:09:09.848305 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9596 13:09:09.851833 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9597 13:09:09.858359 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9598 13:09:09.861612 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9599 13:09:09.868205 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9600 13:09:09.871588 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9601 13:09:09.874733 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9602 13:09:09.878453 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9603 13:09:09.884990 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9604 13:09:09.888052 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9605 13:09:09.891526 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9606 13:09:09.898120 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9607 13:09:09.901229 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9608 13:09:09.908050 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9609 13:09:09.911366 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9610 13:09:09.914684 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9611 13:09:09.921506 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9612 13:09:09.924516 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9613 13:09:09.930916 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9614 13:09:09.934573 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9615 13:09:09.937945 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9616 13:09:09.944633 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9617 13:09:09.947656 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9618 13:09:09.954033 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9619 13:09:09.957455 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9620 13:09:09.960617 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9621 13:09:09.967345 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9622 13:09:09.970362 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9623 13:09:09.974067 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9624 13:09:09.977553 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9625 13:09:09.983716 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9626 13:09:09.987199 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9627 13:09:09.990191 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9628 13:09:09.997077 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9629 13:09:10.000219 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9630 13:09:10.003648 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9631 13:09:10.010148 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9632 13:09:10.013090 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9633 13:09:10.020007 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9634 13:09:10.023111 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9635 13:09:10.026703 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9636 13:09:10.033114 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9637 13:09:10.036652 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9638 13:09:10.043174 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9639 13:09:10.046248 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9640 13:09:10.049693 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9641 13:09:10.056068 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9642 13:09:10.059756 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9643 13:09:10.066137 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9644 13:09:10.069913 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9645 13:09:10.072789 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9646 13:09:10.079252 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9647 13:09:10.082829 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9648 13:09:10.088914 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9649 13:09:10.092411 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9650 13:09:10.095792 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9651 13:09:10.102412 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9652 13:09:10.105918 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9653 13:09:10.112530 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9654 13:09:10.115542 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9655 13:09:10.119378 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9656 13:09:10.125239 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9657 13:09:10.129230 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9658 13:09:10.135462 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9659 13:09:10.138925 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9660 13:09:10.142094 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9661 13:09:10.148621 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9662 13:09:10.151683 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9663 13:09:10.158290 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9664 13:09:10.161957 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9665 13:09:10.165230 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9666 13:09:10.171356 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9667 13:09:10.174871 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9668 13:09:10.181518 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9669 13:09:10.184940 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9670 13:09:10.188160 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9671 13:09:10.194609 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9672 13:09:10.197874 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9673 13:09:10.204776 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9674 13:09:10.207788 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9675 13:09:10.214450 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9676 13:09:10.217402 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9677 13:09:10.220762 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9678 13:09:10.227453 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9679 13:09:10.230925 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9680 13:09:10.237361 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9681 13:09:10.240775 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9682 13:09:10.243819 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9683 13:09:10.250458 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9684 13:09:10.253628 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9685 13:09:10.260636 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9686 13:09:10.263651 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9687 13:09:10.267284 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9688 13:09:10.273901 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9689 13:09:10.276908 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9690 13:09:10.280402 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9691 13:09:10.286820 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9692 13:09:10.290187 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9693 13:09:10.296887 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9694 13:09:10.300044 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9695 13:09:10.306469 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9696 13:09:10.310037 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9697 13:09:10.316375 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9698 13:09:10.319855 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9699 13:09:10.322805 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9700 13:09:10.329676 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9701 13:09:10.333008 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9702 13:09:10.339385 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9703 13:09:10.342984 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9704 13:09:10.349343 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9705 13:09:10.352693 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9706 13:09:10.356065 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9707 13:09:10.362869 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9708 13:09:10.365731 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9709 13:09:10.372454 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9710 13:09:10.375490 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9711 13:09:10.381985 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9712 13:09:10.385544 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9713 13:09:10.388920 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9714 13:09:10.395796 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9715 13:09:10.398618 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9716 13:09:10.405041 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9717 13:09:10.408514 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9718 13:09:10.415278 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9719 13:09:10.418289 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9720 13:09:10.421780 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9721 13:09:10.428211 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9722 13:09:10.431508 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9723 13:09:10.438583 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9724 13:09:10.441623 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9725 13:09:10.444866 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9726 13:09:10.451360 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9727 13:09:10.454497 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9728 13:09:10.461536 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9729 13:09:10.464996 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9730 13:09:10.471316 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9731 13:09:10.474914 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9732 13:09:10.477815 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9733 13:09:10.484414 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9734 13:09:10.487645 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9735 13:09:10.491095 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9736 13:09:10.494105 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9737 13:09:10.501044 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9738 13:09:10.504533 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9739 13:09:10.507495 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9740 13:09:10.514386 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9741 13:09:10.517808 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9742 13:09:10.520712 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9743 13:09:10.527634 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9744 13:09:10.530547 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9745 13:09:10.537631 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9746 13:09:10.540504 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9747 13:09:10.543881 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9748 13:09:10.550385 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9749 13:09:10.553786 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9750 13:09:10.560382 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9751 13:09:10.563819 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9752 13:09:10.566709 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9753 13:09:10.573683 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9754 13:09:10.576544 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9755 13:09:10.580278 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9756 13:09:10.586992 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9757 13:09:10.590056 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9758 13:09:10.593785 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9759 13:09:10.599967 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9760 13:09:10.603505 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9761 13:09:10.609953 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9762 13:09:10.613463 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9763 13:09:10.616385 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9764 13:09:10.623323 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9765 13:09:10.626158 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9766 13:09:10.633395 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9767 13:09:10.636330 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9768 13:09:10.639809 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9769 13:09:10.646214 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9770 13:09:10.649398 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9771 13:09:10.652760 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9772 13:09:10.659342 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9773 13:09:10.662793 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9774 13:09:10.665681 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9775 13:09:10.669070 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9776 13:09:10.675937 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9777 13:09:10.679215 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9778 13:09:10.682678 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9779 13:09:10.685626 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9780 13:09:10.692293 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9781 13:09:10.695842 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9782 13:09:10.698839 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9783 13:09:10.702248 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9784 13:09:10.709206 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9785 13:09:10.712187 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9786 13:09:10.715727 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9787 13:09:10.722082 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9788 13:09:10.725479 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9789 13:09:10.732119 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9790 13:09:10.735200 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9791 13:09:10.742208 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9792 13:09:10.745367 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9793 13:09:10.748938 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9794 13:09:10.755264 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9795 13:09:10.758042 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9796 13:09:10.764838 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9797 13:09:10.768609 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9798 13:09:10.771499 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9799 13:09:10.777959 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9800 13:09:10.781451 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9801 13:09:10.788448 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9802 13:09:10.791434 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9803 13:09:10.797904 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9804 13:09:10.801473 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9805 13:09:10.805051 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9806 13:09:10.811162 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9807 13:09:10.814477 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9808 13:09:10.821061 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9809 13:09:10.824799 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9810 13:09:10.827687 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9811 13:09:10.834367 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9812 13:09:10.837247 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9813 13:09:10.843769 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9814 13:09:10.847491 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9815 13:09:10.853876 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9816 13:09:10.857392 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9817 13:09:10.860259 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9818 13:09:10.866831 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9819 13:09:10.870291 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9820 13:09:10.877125 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9821 13:09:10.880120 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9822 13:09:10.886610 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9823 13:09:10.890156 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9824 13:09:10.893557 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9825 13:09:10.900263 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9826 13:09:10.903404 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9827 13:09:10.909835 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9828 13:09:10.913363 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9829 13:09:10.916575 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9830 13:09:10.922895 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9831 13:09:10.926307 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9832 13:09:10.932697 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9833 13:09:10.936272 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9834 13:09:10.942685 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9835 13:09:10.946178 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9836 13:09:10.949151 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9837 13:09:10.955812 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9838 13:09:10.958899 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9839 13:09:10.965541 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9840 13:09:10.969077 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9841 13:09:10.972349 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9842 13:09:10.978773 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9843 13:09:10.982390 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9844 13:09:10.988572 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9845 13:09:10.992080 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9846 13:09:10.998267 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9847 13:09:11.001548 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9848 13:09:11.008083 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9849 13:09:11.011539 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9850 13:09:11.014698 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9851 13:09:11.021288 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9852 13:09:11.024753 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9853 13:09:11.031150 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9854 13:09:11.034465 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9855 13:09:11.040834 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9856 13:09:11.043844 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9857 13:09:11.047499 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9858 13:09:11.054029 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9859 13:09:11.057424 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9860 13:09:11.063720 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9861 13:09:11.067249 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9862 13:09:11.073758 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9863 13:09:11.077177 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9864 13:09:11.083746 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9865 13:09:11.086627 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9866 13:09:11.089954 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9867 13:09:11.096785 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9868 13:09:11.100240 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9869 13:09:11.106935 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9870 13:09:11.109727 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9871 13:09:11.116803 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9872 13:09:11.119937 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9873 13:09:11.126239 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9874 13:09:11.129504 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9875 13:09:11.132970 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9876 13:09:11.139906 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9877 13:09:11.142847 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9878 13:09:11.149760 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9879 13:09:11.152651 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9880 13:09:11.159653 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9881 13:09:11.162752 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9882 13:09:11.169011 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9883 13:09:11.172328 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9884 13:09:11.176236 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9885 13:09:11.182609 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9886 13:09:11.185582 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9887 13:09:11.192749 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9888 13:09:11.195385 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9889 13:09:11.202101 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9890 13:09:11.205549 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9891 13:09:11.211846 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9892 13:09:11.215387 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9893 13:09:11.218882 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9894 13:09:11.225368 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9895 13:09:11.228713 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9896 13:09:11.235063 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9897 13:09:11.238429 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9898 13:09:11.245183 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9899 13:09:11.248409 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9900 13:09:11.255243 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9901 13:09:11.258280 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9902 13:09:11.261872 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9903 13:09:11.268291 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9904 13:09:11.271184 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9905 13:09:11.278272 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9906 13:09:11.281724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9907 13:09:11.284521 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9908 13:09:11.291367 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9909 13:09:11.294735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9910 13:09:11.300960 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9911 13:09:11.304236 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9912 13:09:11.310995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9913 13:09:11.314483 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9914 13:09:11.320589 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9915 13:09:11.324001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9916 13:09:11.330655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9917 13:09:11.334349 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9918 13:09:11.340271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9919 13:09:11.343581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9920 13:09:11.350360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9921 13:09:11.353737 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9922 13:09:11.360173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9923 13:09:11.364061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9924 13:09:11.370545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9925 13:09:11.373550 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9926 13:09:11.379877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9927 13:09:11.383449 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9928 13:09:11.389876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9929 13:09:11.393386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9930 13:09:11.399930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9931 13:09:11.402944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9932 13:09:11.409938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9933 13:09:11.416495 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9934 13:09:11.419779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9935 13:09:11.426225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9936 13:09:11.429309 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9937 13:09:11.435766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9938 13:09:11.439180 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9939 13:09:11.439265 INFO: [APUAPC] vio 0
9940 13:09:11.447000 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9941 13:09:11.449992 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9942 13:09:11.453411 INFO: [APUAPC] D0_APC_0: 0x400510
9943 13:09:11.456845 INFO: [APUAPC] D0_APC_1: 0x0
9944 13:09:11.459963 INFO: [APUAPC] D0_APC_2: 0x1540
9945 13:09:11.463118 INFO: [APUAPC] D0_APC_3: 0x0
9946 13:09:11.466970 INFO: [APUAPC] D1_APC_0: 0xffffffff
9947 13:09:11.469678 INFO: [APUAPC] D1_APC_1: 0xffffffff
9948 13:09:11.473022 INFO: [APUAPC] D1_APC_2: 0x3fffff
9949 13:09:11.476372 INFO: [APUAPC] D1_APC_3: 0x0
9950 13:09:11.479573 INFO: [APUAPC] D2_APC_0: 0xffffffff
9951 13:09:11.483327 INFO: [APUAPC] D2_APC_1: 0xffffffff
9952 13:09:11.486537 INFO: [APUAPC] D2_APC_2: 0x3fffff
9953 13:09:11.489557 INFO: [APUAPC] D2_APC_3: 0x0
9954 13:09:11.492868 INFO: [APUAPC] D3_APC_0: 0xffffffff
9955 13:09:11.496539 INFO: [APUAPC] D3_APC_1: 0xffffffff
9956 13:09:11.499966 INFO: [APUAPC] D3_APC_2: 0x3fffff
9957 13:09:11.502899 INFO: [APUAPC] D3_APC_3: 0x0
9958 13:09:11.506444 INFO: [APUAPC] D4_APC_0: 0xffffffff
9959 13:09:11.509954 INFO: [APUAPC] D4_APC_1: 0xffffffff
9960 13:09:11.513181 INFO: [APUAPC] D4_APC_2: 0x3fffff
9961 13:09:11.516307 INFO: [APUAPC] D4_APC_3: 0x0
9962 13:09:11.519238 INFO: [APUAPC] D5_APC_0: 0xffffffff
9963 13:09:11.522819 INFO: [APUAPC] D5_APC_1: 0xffffffff
9964 13:09:11.526041 INFO: [APUAPC] D5_APC_2: 0x3fffff
9965 13:09:11.526117 INFO: [APUAPC] D5_APC_3: 0x0
9966 13:09:11.532556 INFO: [APUAPC] D6_APC_0: 0xffffffff
9967 13:09:11.536087 INFO: [APUAPC] D6_APC_1: 0xffffffff
9968 13:09:11.539091 INFO: [APUAPC] D6_APC_2: 0x3fffff
9969 13:09:11.539167 INFO: [APUAPC] D6_APC_3: 0x0
9970 13:09:11.542645 INFO: [APUAPC] D7_APC_0: 0xffffffff
9971 13:09:11.549233 INFO: [APUAPC] D7_APC_1: 0xffffffff
9972 13:09:11.552345 INFO: [APUAPC] D7_APC_2: 0x3fffff
9973 13:09:11.552422 INFO: [APUAPC] D7_APC_3: 0x0
9974 13:09:11.555660 INFO: [APUAPC] D8_APC_0: 0xffffffff
9975 13:09:11.558720 INFO: [APUAPC] D8_APC_1: 0xffffffff
9976 13:09:11.562216 INFO: [APUAPC] D8_APC_2: 0x3fffff
9977 13:09:11.565731 INFO: [APUAPC] D8_APC_3: 0x0
9978 13:09:11.568820 INFO: [APUAPC] D9_APC_0: 0xffffffff
9979 13:09:11.572339 INFO: [APUAPC] D9_APC_1: 0xffffffff
9980 13:09:11.575114 INFO: [APUAPC] D9_APC_2: 0x3fffff
9981 13:09:11.578661 INFO: [APUAPC] D9_APC_3: 0x0
9982 13:09:11.582084 INFO: [APUAPC] D10_APC_0: 0xffffffff
9983 13:09:11.585325 INFO: [APUAPC] D10_APC_1: 0xffffffff
9984 13:09:11.588388 INFO: [APUAPC] D10_APC_2: 0x3fffff
9985 13:09:11.591558 INFO: [APUAPC] D10_APC_3: 0x0
9986 13:09:11.595136 INFO: [APUAPC] D11_APC_0: 0xffffffff
9987 13:09:11.601718 INFO: [APUAPC] D11_APC_1: 0xffffffff
9988 13:09:11.604709 INFO: [APUAPC] D11_APC_2: 0x3fffff
9989 13:09:11.604786 INFO: [APUAPC] D11_APC_3: 0x0
9990 13:09:11.611800 INFO: [APUAPC] D12_APC_0: 0xffffffff
9991 13:09:11.614862 INFO: [APUAPC] D12_APC_1: 0xffffffff
9992 13:09:11.618141 INFO: [APUAPC] D12_APC_2: 0x3fffff
9993 13:09:11.618217 INFO: [APUAPC] D12_APC_3: 0x0
9994 13:09:11.624540 INFO: [APUAPC] D13_APC_0: 0xffffffff
9995 13:09:11.627799 INFO: [APUAPC] D13_APC_1: 0xffffffff
9996 13:09:11.631493 INFO: [APUAPC] D13_APC_2: 0x3fffff
9997 13:09:11.634425 INFO: [APUAPC] D13_APC_3: 0x0
9998 13:09:11.637719 INFO: [APUAPC] D14_APC_0: 0xffffffff
9999 13:09:11.641240 INFO: [APUAPC] D14_APC_1: 0xffffffff
10000 13:09:11.644465 INFO: [APUAPC] D14_APC_2: 0x3fffff
10001 13:09:11.647682 INFO: [APUAPC] D14_APC_3: 0x0
10002 13:09:11.651008 INFO: [APUAPC] D15_APC_0: 0xffffffff
10003 13:09:11.654247 INFO: [APUAPC] D15_APC_1: 0xffffffff
10004 13:09:11.657781 INFO: [APUAPC] D15_APC_2: 0x3fffff
10005 13:09:11.661438 INFO: [APUAPC] D15_APC_3: 0x0
10006 13:09:11.661508 INFO: [APUAPC] APC_CON: 0x4
10007 13:09:11.664451 INFO: [NOCDAPC] D0_APC_0: 0x0
10008 13:09:11.667513 INFO: [NOCDAPC] D0_APC_1: 0x0
10009 13:09:11.671079 INFO: [NOCDAPC] D1_APC_0: 0x0
10010 13:09:11.674527 INFO: [NOCDAPC] D1_APC_1: 0xfff
10011 13:09:11.677434 INFO: [NOCDAPC] D2_APC_0: 0x0
10012 13:09:11.680986 INFO: [NOCDAPC] D2_APC_1: 0xfff
10013 13:09:11.684502 INFO: [NOCDAPC] D3_APC_0: 0x0
10014 13:09:11.687260 INFO: [NOCDAPC] D3_APC_1: 0xfff
10015 13:09:11.690883 INFO: [NOCDAPC] D4_APC_0: 0x0
10016 13:09:11.693852 INFO: [NOCDAPC] D4_APC_1: 0xfff
10017 13:09:11.693923 INFO: [NOCDAPC] D5_APC_0: 0x0
10018 13:09:11.697349 INFO: [NOCDAPC] D5_APC_1: 0xfff
10019 13:09:11.700500 INFO: [NOCDAPC] D6_APC_0: 0x0
10020 13:09:11.703725 INFO: [NOCDAPC] D6_APC_1: 0xfff
10021 13:09:11.707278 INFO: [NOCDAPC] D7_APC_0: 0x0
10022 13:09:11.710690 INFO: [NOCDAPC] D7_APC_1: 0xfff
10023 13:09:11.713609 INFO: [NOCDAPC] D8_APC_0: 0x0
10024 13:09:11.717008 INFO: [NOCDAPC] D8_APC_1: 0xfff
10025 13:09:11.720332 INFO: [NOCDAPC] D9_APC_0: 0x0
10026 13:09:11.723804 INFO: [NOCDAPC] D9_APC_1: 0xfff
10027 13:09:11.726830 INFO: [NOCDAPC] D10_APC_0: 0x0
10028 13:09:11.730073 INFO: [NOCDAPC] D10_APC_1: 0xfff
10029 13:09:11.733370 INFO: [NOCDAPC] D11_APC_0: 0x0
10030 13:09:11.737059 INFO: [NOCDAPC] D11_APC_1: 0xfff
10031 13:09:11.737143 INFO: [NOCDAPC] D12_APC_0: 0x0
10032 13:09:11.740382 INFO: [NOCDAPC] D12_APC_1: 0xfff
10033 13:09:11.743204 INFO: [NOCDAPC] D13_APC_0: 0x0
10034 13:09:11.747005 INFO: [NOCDAPC] D13_APC_1: 0xfff
10035 13:09:11.750151 INFO: [NOCDAPC] D14_APC_0: 0x0
10036 13:09:11.753569 INFO: [NOCDAPC] D14_APC_1: 0xfff
10037 13:09:11.756873 INFO: [NOCDAPC] D15_APC_0: 0x0
10038 13:09:11.760117 INFO: [NOCDAPC] D15_APC_1: 0xfff
10039 13:09:11.763359 INFO: [NOCDAPC] APC_CON: 0x4
10040 13:09:11.766626 INFO: [APUAPC] set_apusys_apc done
10041 13:09:11.770272 INFO: [DEVAPC] devapc_init done
10042 13:09:11.773173 INFO: GICv3 without legacy support detected.
10043 13:09:11.776577 INFO: ARM GICv3 driver initialized in EL3
10044 13:09:11.780230 INFO: Maximum SPI INTID supported: 639
10045 13:09:11.786284 INFO: BL31: Initializing runtime services
10046 13:09:11.789871 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10047 13:09:11.793335 INFO: SPM: enable CPC mode
10048 13:09:11.799401 INFO: mcdi ready for mcusys-off-idle and system suspend
10049 13:09:11.802825 INFO: BL31: Preparing for EL3 exit to normal world
10050 13:09:11.806101 INFO: Entry point address = 0x80000000
10051 13:09:11.809388 INFO: SPSR = 0x8
10052 13:09:11.814717
10053 13:09:11.814787
10054 13:09:11.814843
10055 13:09:11.818112 Starting depthcharge on Spherion...
10056 13:09:11.818178
10057 13:09:11.818233 Wipe memory regions:
10058 13:09:11.818285
10059 13:09:11.818933 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10060 13:09:11.819025 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10061 13:09:11.819148 Setting prompt string to ['asurada:']
10062 13:09:11.819213 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10063 13:09:11.821624 [0x00000040000000, 0x00000054600000)
10064 13:09:11.943830
10065 13:09:11.943983 [0x00000054660000, 0x00000080000000)
10066 13:09:12.204116
10067 13:09:12.204255 [0x000000821a7280, 0x000000ffe64000)
10068 13:09:12.949315
10069 13:09:12.949453 [0x00000100000000, 0x00000240000000)
10070 13:09:14.839202
10071 13:09:14.842613 Initializing XHCI USB controller at 0x11200000.
10072 13:09:15.880888
10073 13:09:15.883930 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10074 13:09:15.884025
10075 13:09:15.884088
10076 13:09:15.884352 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10077 13:09:15.884443 Sending line: 'tftpboot 192.168.201.1 14879017/tftp-deploy-1qe5qw7y/kernel/image.itb 14879017/tftp-deploy-1qe5qw7y/kernel/cmdline '
10079 13:09:15.984848 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10080 13:09:15.984942 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10081 13:09:15.989461 asurada: tftpboot 192.168.201.1 14879017/tftp-deploy-1qe5qw7y/kernel/image.itbtp-deploy-1qe5qw7y/kernel/cmdline
10082 13:09:15.989537
10083 13:09:15.989611 Waiting for link
10084 13:09:16.147360
10085 13:09:16.147479 R8152: Initializing
10086 13:09:16.147542
10087 13:09:16.150799 Version 6 (ocp_data = 5c30)
10088 13:09:16.150873
10089 13:09:16.153789 R8152: Done initializing
10090 13:09:16.153855
10091 13:09:16.153911 Adding net device
10092 13:09:18.027742
10093 13:09:18.027912 done.
10094 13:09:18.028004
10095 13:09:18.028070 MAC: 00:24:32:30:7c:7b
10096 13:09:18.028138
10097 13:09:18.030802 Sending DHCP discover... done.
10098 13:09:18.030868
10099 13:09:18.035594 Waiting for reply... done.
10100 13:09:18.035705
10101 13:09:18.037395 Sending DHCP request... done.
10102 13:09:18.037469
10103 13:09:18.037556 Waiting for reply... done.
10104 13:09:18.040942
10105 13:09:18.041028 My ip is 192.168.201.14
10106 13:09:18.041085
10107 13:09:18.043891 The DHCP server ip is 192.168.201.1
10108 13:09:18.043967
10109 13:09:18.047034 TFTP server IP predefined by user: 192.168.201.1
10110 13:09:18.047105
10111 13:09:18.053963 Bootfile predefined by user: 14879017/tftp-deploy-1qe5qw7y/kernel/image.itb
10112 13:09:18.054044
10113 13:09:18.056934 Sending tftp read request... done.
10114 13:09:18.057010
10115 13:09:18.063523 Waiting for the transfer...
10116 13:09:18.063611
10117 13:09:18.586561 00000000 ################################################################
10118 13:09:18.586708
10119 13:09:19.113251 00080000 ################################################################
10120 13:09:19.113390
10121 13:09:19.713959 00100000 ################################################################
10122 13:09:19.714427
10123 13:09:20.335769 00180000 ################################################################
10124 13:09:20.335906
10125 13:09:20.901774 00200000 ################################################################
10126 13:09:20.901910
10127 13:09:21.465367 00280000 ################################################################
10128 13:09:21.465488
10129 13:09:21.994248 00300000 ################################################################
10130 13:09:21.994366
10131 13:09:22.510721 00380000 ################################################################
10132 13:09:22.510839
10133 13:09:23.071808 00400000 ################################################################
10134 13:09:23.071947
10135 13:09:23.619099 00480000 ################################################################
10136 13:09:23.619244
10137 13:09:24.149386 00500000 ################################################################
10138 13:09:24.149538
10139 13:09:24.678303 00580000 ################################################################
10140 13:09:24.678423
10141 13:09:25.210214 00600000 ################################################################
10142 13:09:25.210367
10143 13:09:25.770799 00680000 ################################################################
10144 13:09:25.770925
10145 13:09:26.333581 00700000 ################################################################
10146 13:09:26.333709
10147 13:09:26.952849 00780000 ################################################################
10148 13:09:26.952974
10149 13:09:27.517441 00800000 ################################################################
10150 13:09:27.517571
10151 13:09:28.080348 00880000 ################################################################
10152 13:09:28.080478
10153 13:09:28.666917 00900000 ################################################################
10154 13:09:28.667045
10155 13:09:29.232360 00980000 ################################################################
10156 13:09:29.232486
10157 13:09:29.817360 00a00000 ################################################################
10158 13:09:29.817483
10159 13:09:30.377096 00a80000 ################################################################
10160 13:09:30.377272
10161 13:09:30.967421 00b00000 ################################################################
10162 13:09:30.967568
10163 13:09:31.555862 00b80000 ################################################################
10164 13:09:31.556224
10165 13:09:32.110031 00c00000 ################################################################
10166 13:09:32.110157
10167 13:09:32.660313 00c80000 ################################################################
10168 13:09:32.660472
10169 13:09:33.215745 00d00000 ################################################################
10170 13:09:33.215867
10171 13:09:33.743955 00d80000 ################################################################
10172 13:09:33.744092
10173 13:09:34.298625 00e00000 ################################################################
10174 13:09:34.298758
10175 13:09:34.855535 00e80000 ################################################################
10176 13:09:34.855661
10177 13:09:35.414165 00f00000 ################################################################
10178 13:09:35.414275
10179 13:09:35.974814 00f80000 ################################################################
10180 13:09:35.974947
10181 13:09:36.531981 01000000 ################################################################
10182 13:09:36.532096
10183 13:09:37.089608 01080000 ################################################################
10184 13:09:37.089759
10185 13:09:37.666665 01100000 ################################################################
10186 13:09:37.666778
10187 13:09:38.279508 01180000 ################################################################
10188 13:09:38.279645
10189 13:09:38.850251 01200000 ################################################################
10190 13:09:38.850375
10191 13:09:39.419433 01280000 ################################################################
10192 13:09:39.419558
10193 13:09:39.983843 01300000 ################################################################
10194 13:09:39.983974
10195 13:09:40.542067 01380000 ################################################################
10196 13:09:40.542226
10197 13:09:41.127036 01400000 ################################################################
10198 13:09:41.127173
10199 13:09:41.683635 01480000 ################################################################
10200 13:09:41.683750
10201 13:09:42.261371 01500000 ################################################################
10202 13:09:42.261484
10203 13:09:42.833129 01580000 ################################################################
10204 13:09:42.833305
10205 13:09:43.410662 01600000 ################################################################
10206 13:09:43.410793
10207 13:09:43.984420 01680000 ################################################################
10208 13:09:43.984534
10209 13:09:44.536950 01700000 ################################################################
10210 13:09:44.537071
10211 13:09:45.079848 01780000 ################################################################
10212 13:09:45.079964
10213 13:09:45.630748 01800000 ################################################################
10214 13:09:45.630862
10215 13:09:46.188803 01880000 ################################################################
10216 13:09:46.188955
10217 13:09:46.744833 01900000 ################################################################
10218 13:09:46.744962
10219 13:09:47.304721 01980000 ################################################################
10220 13:09:47.304855
10221 13:09:47.864525 01a00000 ################################################################
10222 13:09:47.864657
10223 13:09:48.432711 01a80000 ################################################################
10224 13:09:48.432829
10225 13:09:48.979482 01b00000 ################################################################
10226 13:09:48.979655
10227 13:09:49.531406 01b80000 ################################################################
10228 13:09:49.531533
10229 13:09:50.092911 01c00000 ################################################################
10230 13:09:50.093047
10231 13:09:50.660458 01c80000 ################################################################
10232 13:09:50.660587
10233 13:09:51.217565 01d00000 ################################################################
10234 13:09:51.217695
10235 13:09:51.774839 01d80000 ################################################################
10236 13:09:51.774969
10237 13:09:52.239187 01e00000 ##################################################### done.
10238 13:09:52.239314
10239 13:09:52.242908 The bootfile was 31886566 bytes long.
10240 13:09:52.242990
10241 13:09:52.246047 Sending tftp read request... done.
10242 13:09:52.246124
10243 13:09:52.246184 Waiting for the transfer...
10244 13:09:52.246239
10245 13:09:52.249110 00000000 # done.
10246 13:09:52.249213
10247 13:09:52.255567 Command line loaded dynamically from TFTP file: 14879017/tftp-deploy-1qe5qw7y/kernel/cmdline
10248 13:09:52.255645
10249 13:09:52.279056 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14879017/extract-nfsrootfs-jt9hskzb,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10250 13:09:52.279145
10251 13:09:52.282186 Loading FIT.
10252 13:09:52.282262
10253 13:09:52.282321 Image ramdisk-1 has 18722811 bytes.
10254 13:09:52.285029
10255 13:09:52.285106 Image fdt-1 has 47258 bytes.
10256 13:09:52.285205
10257 13:09:52.288565 Image kernel-1 has 13114469 bytes.
10258 13:09:52.288641
10259 13:09:52.298394 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10260 13:09:52.298474
10261 13:09:52.314425 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10262 13:09:52.314507
10263 13:09:52.321832 Choosing best match conf-1 for compat google,spherion-rev2.
10264 13:09:52.325355
10265 13:09:52.330035 Connected to device vid:did:rid of 1ae0:0028:00
10266 13:09:52.337894
10267 13:09:52.341075 tpm_get_response: command 0x17b, return code 0x0
10268 13:09:52.341191
10269 13:09:52.344526 ec_init: CrosEC protocol v3 supported (256, 248)
10270 13:09:52.348258
10271 13:09:52.351764 tpm_cleanup: add release locality here.
10272 13:09:52.351840
10273 13:09:52.351898 Shutting down all USB controllers.
10274 13:09:52.355354
10275 13:09:52.355430 Removing current net device
10276 13:09:52.355489
10277 13:09:52.361777 Exiting depthcharge with code 4 at timestamp: 69765344
10278 13:09:52.361855
10279 13:09:52.365256 LZMA decompressing kernel-1 to 0x821a6718
10280 13:09:52.365332
10281 13:09:52.368582 LZMA decompressing kernel-1 to 0x40000000
10282 13:09:53.983814
10283 13:09:53.983952 jumping to kernel
10284 13:09:53.984413 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10285 13:09:53.984515 start: 2.2.5 auto-login-action (timeout 00:03:38) [common]
10286 13:09:53.984581 Setting prompt string to ['Linux version [0-9]']
10287 13:09:53.984651 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10288 13:09:53.984715 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10289 13:09:54.065538
10290 13:09:54.068927 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10291 13:09:54.071841 start: 2.2.5.1 login-action (timeout 00:03:38) [common]
10292 13:09:54.071928 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10293 13:09:54.072005 Setting prompt string to []
10294 13:09:54.072077 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10295 13:09:54.072142 Using line separator: #'\n'#
10296 13:09:54.072202 No login prompt set.
10297 13:09:54.072257 Parsing kernel messages
10298 13:09:54.072305 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10299 13:09:54.072409 [login-action] Waiting for messages, (timeout 00:03:38)
10300 13:09:54.072472 Waiting using forced prompt support (timeout 00:01:49)
10301 13:09:54.091513 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j272990-arm64-gcc-12-defconfig-arm64-chromebook-fgzcq) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024
10302 13:09:54.094838 [ 0.000000] random: crng init done
10303 13:09:54.097999 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10304 13:09:54.101658 [ 0.000000] efi: UEFI not found.
10305 13:09:54.111364 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10306 13:09:54.117591 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10307 13:09:54.127716 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10308 13:09:54.137324 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10309 13:09:54.143856 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10310 13:09:54.150351 [ 0.000000] printk: bootconsole [mtk8250] enabled
10311 13:09:54.156857 [ 0.000000] NUMA: No NUMA configuration found
10312 13:09:54.163784 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10313 13:09:54.167177 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10314 13:09:54.170595 [ 0.000000] Zone ranges:
10315 13:09:54.177022 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10316 13:09:54.180020 [ 0.000000] DMA32 empty
10317 13:09:54.186607 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10318 13:09:54.190775 [ 0.000000] Movable zone start for each node
10319 13:09:54.193020 [ 0.000000] Early memory node ranges
10320 13:09:54.200046 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10321 13:09:54.206631 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10322 13:09:54.213027 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10323 13:09:54.219837 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10324 13:09:54.226115 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10325 13:09:54.232900 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10326 13:09:54.289884 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10327 13:09:54.296631 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10328 13:09:54.303192 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10329 13:09:54.306863 [ 0.000000] psci: probing for conduit method from DT.
10330 13:09:54.313048 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10331 13:09:54.316219 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10332 13:09:54.322793 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10333 13:09:54.326565 [ 0.000000] psci: SMC Calling Convention v1.2
10334 13:09:54.332871 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10335 13:09:54.336365 [ 0.000000] Detected VIPT I-cache on CPU0
10336 13:09:54.342638 [ 0.000000] CPU features: detected: GIC system register CPU interface
10337 13:09:54.349577 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10338 13:09:54.355666 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10339 13:09:54.362618 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10340 13:09:54.372359 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10341 13:09:54.378997 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10342 13:09:54.382730 [ 0.000000] alternatives: applying boot alternatives
10343 13:09:54.389404 [ 0.000000] Fallback order for Node 0: 0
10344 13:09:54.395498 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10345 13:09:54.398922 [ 0.000000] Policy zone: Normal
10346 13:09:54.421849 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14879017/extract-nfsrootfs-jt9hskzb,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10347 13:09:54.431926 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10348 13:09:54.443182 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10349 13:09:54.453205 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10350 13:09:54.459657 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10351 13:09:54.462818 <6>[ 0.000000] software IO TLB: area num 8.
10352 13:09:54.520889 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10353 13:09:54.670425 <6>[ 0.000000] Memory: 7945776K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 406992K reserved, 32768K cma-reserved)
10354 13:09:54.676893 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10355 13:09:54.683480 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10356 13:09:54.686931 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10357 13:09:54.693275 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10358 13:09:54.700127 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10359 13:09:54.703297 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10360 13:09:54.712905 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10361 13:09:54.719727 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10362 13:09:54.726074 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10363 13:09:54.732852 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10364 13:09:54.735957 <6>[ 0.000000] GICv3: 608 SPIs implemented
10365 13:09:54.739603 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10366 13:09:54.745889 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10367 13:09:54.749287 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10368 13:09:54.756382 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10369 13:09:54.768989 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10370 13:09:54.782246 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10371 13:09:54.789145 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10372 13:09:54.797046 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10373 13:09:54.810097 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10374 13:09:54.816499 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10375 13:09:54.823463 <6>[ 0.009185] Console: colour dummy device 80x25
10376 13:09:54.833298 <6>[ 0.013917] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10377 13:09:54.839731 <6>[ 0.024359] pid_max: default: 32768 minimum: 301
10378 13:09:54.842840 <6>[ 0.029232] LSM: Security Framework initializing
10379 13:09:54.853000 <6>[ 0.034172] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10380 13:09:54.859397 <6>[ 0.041985] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10381 13:09:54.869572 <6>[ 0.051408] cblist_init_generic: Setting adjustable number of callback queues.
10382 13:09:54.875996 <6>[ 0.058847] cblist_init_generic: Setting shift to 3 and lim to 1.
10383 13:09:54.882580 <6>[ 0.065186] cblist_init_generic: Setting adjustable number of callback queues.
10384 13:09:54.888756 <6>[ 0.072659] cblist_init_generic: Setting shift to 3 and lim to 1.
10385 13:09:54.892067 <6>[ 0.079060] rcu: Hierarchical SRCU implementation.
10386 13:09:54.898995 <6>[ 0.084075] rcu: Max phase no-delay instances is 1000.
10387 13:09:54.905048 <6>[ 0.091106] EFI services will not be available.
10388 13:09:54.908629 <6>[ 0.096067] smp: Bringing up secondary CPUs ...
10389 13:09:54.917970 <6>[ 0.101147] Detected VIPT I-cache on CPU1
10390 13:09:54.924374 <6>[ 0.101218] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10391 13:09:54.930973 <6>[ 0.101246] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10392 13:09:54.934468 <6>[ 0.101592] Detected VIPT I-cache on CPU2
10393 13:09:54.943987 <6>[ 0.101645] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10394 13:09:54.950464 <6>[ 0.101663] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10395 13:09:54.954167 <6>[ 0.101926] Detected VIPT I-cache on CPU3
10396 13:09:54.960803 <6>[ 0.101974] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10397 13:09:54.967142 <6>[ 0.101988] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10398 13:09:54.970459 <6>[ 0.102293] CPU features: detected: Spectre-v4
10399 13:09:54.977346 <6>[ 0.102300] CPU features: detected: Spectre-BHB
10400 13:09:54.980697 <6>[ 0.102306] Detected PIPT I-cache on CPU4
10401 13:09:54.987142 <6>[ 0.102367] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10402 13:09:54.993609 <6>[ 0.102384] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10403 13:09:55.000264 <6>[ 0.102676] Detected PIPT I-cache on CPU5
10404 13:09:55.006901 <6>[ 0.102741] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10405 13:09:55.013476 <6>[ 0.102757] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10406 13:09:55.016672 <6>[ 0.103039] Detected PIPT I-cache on CPU6
10407 13:09:55.026508 <6>[ 0.103105] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10408 13:09:55.033402 <6>[ 0.103121] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10409 13:09:55.036027 <6>[ 0.103419] Detected PIPT I-cache on CPU7
10410 13:09:55.043101 <6>[ 0.103483] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10411 13:09:55.049207 <6>[ 0.103499] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10412 13:09:55.052572 <6>[ 0.103546] smp: Brought up 1 node, 8 CPUs
10413 13:09:55.059454 <6>[ 0.244981] SMP: Total of 8 processors activated.
10414 13:09:55.065927 <6>[ 0.249933] CPU features: detected: 32-bit EL0 Support
10415 13:09:55.072912 <6>[ 0.255329] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10416 13:09:55.078954 <6>[ 0.264184] CPU features: detected: Common not Private translations
10417 13:09:55.085903 <6>[ 0.270660] CPU features: detected: CRC32 instructions
10418 13:09:55.091991 <6>[ 0.276011] CPU features: detected: RCpc load-acquire (LDAPR)
10419 13:09:55.095408 <6>[ 0.282008] CPU features: detected: LSE atomic instructions
10420 13:09:55.102311 <6>[ 0.287790] CPU features: detected: Privileged Access Never
10421 13:09:55.108601 <6>[ 0.293569] CPU features: detected: RAS Extension Support
10422 13:09:55.115156 <6>[ 0.299178] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10423 13:09:55.118312 <6>[ 0.306444] CPU: All CPU(s) started at EL2
10424 13:09:55.125147 <6>[ 0.310761] alternatives: applying system-wide alternatives
10425 13:09:55.135753 <6>[ 0.321668] devtmpfs: initialized
10426 13:09:55.151204 <6>[ 0.330484] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10427 13:09:55.157578 <6>[ 0.340444] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10428 13:09:55.164381 <6>[ 0.348685] pinctrl core: initialized pinctrl subsystem
10429 13:09:55.167990 <6>[ 0.355348] DMI not present or invalid.
10430 13:09:55.174317 <6>[ 0.359757] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10431 13:09:55.184172 <6>[ 0.366578] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10432 13:09:55.190483 <6>[ 0.374163] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10433 13:09:55.200388 <6>[ 0.382392] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10434 13:09:55.207391 <6>[ 0.390634] audit: initializing netlink subsys (disabled)
10435 13:09:55.213643 <5>[ 0.396328] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10436 13:09:55.220003 <6>[ 0.397042] thermal_sys: Registered thermal governor 'step_wise'
10437 13:09:55.226447 <6>[ 0.404294] thermal_sys: Registered thermal governor 'power_allocator'
10438 13:09:55.230320 <6>[ 0.410547] cpuidle: using governor menu
10439 13:09:55.236948 <6>[ 0.421506] NET: Registered PF_QIPCRTR protocol family
10440 13:09:55.243293 <6>[ 0.427011] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10441 13:09:55.249889 <6>[ 0.434115] ASID allocator initialised with 32768 entries
10442 13:09:55.253039 <6>[ 0.440687] Serial: AMBA PL011 UART driver
10443 13:09:55.264206 <4>[ 0.450026] Trying to register duplicate clock ID: 134
10444 13:09:55.322321 <6>[ 0.511307] KASLR enabled
10445 13:09:55.336261 <6>[ 0.518887] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10446 13:09:55.343112 <6>[ 0.525901] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10447 13:09:55.349766 <6>[ 0.532391] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10448 13:09:55.356019 <6>[ 0.539394] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10449 13:09:55.362850 <6>[ 0.545880] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10450 13:09:55.369350 <6>[ 0.552882] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10451 13:09:55.376156 <6>[ 0.559369] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10452 13:09:55.382449 <6>[ 0.566374] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10453 13:09:55.385860 <6>[ 0.573840] ACPI: Interpreter disabled.
10454 13:09:55.394877 <6>[ 0.580276] iommu: Default domain type: Translated
10455 13:09:55.400767 <6>[ 0.585424] iommu: DMA domain TLB invalidation policy: strict mode
10456 13:09:55.404678 <5>[ 0.592079] SCSI subsystem initialized
10457 13:09:55.411094 <6>[ 0.596326] usbcore: registered new interface driver usbfs
10458 13:09:55.417516 <6>[ 0.602056] usbcore: registered new interface driver hub
10459 13:09:55.420469 <6>[ 0.607607] usbcore: registered new device driver usb
10460 13:09:55.428011 <6>[ 0.613726] pps_core: LinuxPPS API ver. 1 registered
10461 13:09:55.437581 <6>[ 0.618918] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10462 13:09:55.441259 <6>[ 0.628258] PTP clock support registered
10463 13:09:55.444476 <6>[ 0.632501] EDAC MC: Ver: 3.0.0
10464 13:09:55.452020 <6>[ 0.637695] FPGA manager framework
10465 13:09:55.458942 <6>[ 0.641372] Advanced Linux Sound Architecture Driver Initialized.
10466 13:09:55.461905 <6>[ 0.648162] vgaarb: loaded
10467 13:09:55.468483 <6>[ 0.651266] clocksource: Switched to clocksource arch_sys_counter
10468 13:09:55.471951 <5>[ 0.657715] VFS: Disk quotas dquot_6.6.0
10469 13:09:55.478079 <6>[ 0.661899] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10470 13:09:55.481558 <6>[ 0.669089] pnp: PnP ACPI: disabled
10471 13:09:55.489711 <6>[ 0.675787] NET: Registered PF_INET protocol family
10472 13:09:55.499965 <6>[ 0.681377] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10473 13:09:55.511373 <6>[ 0.693723] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10474 13:09:55.521024 <6>[ 0.702539] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10475 13:09:55.527405 <6>[ 0.710510] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10476 13:09:55.537556 <6>[ 0.719209] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10477 13:09:55.543767 <6>[ 0.728961] TCP: Hash tables configured (established 65536 bind 65536)
10478 13:09:55.550705 <6>[ 0.735830] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10479 13:09:55.560297 <6>[ 0.743028] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10480 13:09:55.566791 <6>[ 0.750732] NET: Registered PF_UNIX/PF_LOCAL protocol family
10481 13:09:55.573702 <6>[ 0.756881] RPC: Registered named UNIX socket transport module.
10482 13:09:55.576877 <6>[ 0.763030] RPC: Registered udp transport module.
10483 13:09:55.583345 <6>[ 0.767964] RPC: Registered tcp transport module.
10484 13:09:55.590167 <6>[ 0.772895] RPC: Registered tcp NFSv4.1 backchannel transport module.
10485 13:09:55.593652 <6>[ 0.779562] PCI: CLS 0 bytes, default 64
10486 13:09:55.596887 <6>[ 0.783877] Unpacking initramfs...
10487 13:09:55.606603 <6>[ 0.788026] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10488 13:09:55.613231 <6>[ 0.796655] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10489 13:09:55.620047 <6>[ 0.805451] kvm [1]: IPA Size Limit: 40 bits
10490 13:09:55.622868 <6>[ 0.809979] kvm [1]: GICv3: no GICV resource entry
10491 13:09:55.629946 <6>[ 0.814998] kvm [1]: disabling GICv2 emulation
10492 13:09:55.636404 <6>[ 0.819682] kvm [1]: GIC system register CPU interface enabled
10493 13:09:55.639296 <6>[ 0.825846] kvm [1]: vgic interrupt IRQ18
10494 13:09:55.646319 <6>[ 0.831325] kvm [1]: VHE mode initialized successfully
10495 13:09:55.652749 <5>[ 0.837692] Initialise system trusted keyrings
10496 13:09:55.659240 <6>[ 0.842450] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10497 13:09:55.666709 <6>[ 0.852389] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10498 13:09:55.672915 <5>[ 0.858748] NFS: Registering the id_resolver key type
10499 13:09:55.676271 <5>[ 0.864048] Key type id_resolver registered
10500 13:09:55.682874 <5>[ 0.868464] Key type id_legacy registered
10501 13:09:55.689610 <6>[ 0.872754] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10502 13:09:55.695872 <6>[ 0.879676] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10503 13:09:55.702792 <6>[ 0.887382] 9p: Installing v9fs 9p2000 file system support
10504 13:09:55.739285 <5>[ 0.925042] Key type asymmetric registered
10505 13:09:55.742767 <5>[ 0.929371] Asymmetric key parser 'x509' registered
10506 13:09:55.752513 <6>[ 0.934504] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10507 13:09:55.755950 <6>[ 0.942121] io scheduler mq-deadline registered
10508 13:09:55.758856 <6>[ 0.946882] io scheduler kyber registered
10509 13:09:55.778975 <6>[ 0.964751] EINJ: ACPI disabled.
10510 13:09:55.812218 <4>[ 0.991204] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10511 13:09:55.821626 <4>[ 1.001822] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10512 13:09:55.836759 <6>[ 1.022844] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10513 13:09:55.844802 <6>[ 1.030846] printk: console [ttyS0] disabled
10514 13:09:55.873241 <6>[ 1.055471] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10515 13:09:55.879666 <6>[ 1.064941] printk: console [ttyS0] enabled
10516 13:09:55.883084 <6>[ 1.064941] printk: console [ttyS0] enabled
10517 13:09:55.889417 <6>[ 1.073836] printk: bootconsole [mtk8250] disabled
10518 13:09:55.892657 <6>[ 1.073836] printk: bootconsole [mtk8250] disabled
10519 13:09:55.899724 <6>[ 1.084885] SuperH (H)SCI(F) driver initialized
10520 13:09:55.902747 <6>[ 1.090156] msm_serial: driver initialized
10521 13:09:55.916632 <6>[ 1.099070] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10522 13:09:55.926260 <6>[ 1.107617] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10523 13:09:55.932902 <6>[ 1.116159] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10524 13:09:55.943051 <6>[ 1.124786] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10525 13:09:55.952915 <6>[ 1.133492] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10526 13:09:55.959572 <6>[ 1.142212] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10527 13:09:55.969820 <6>[ 1.150752] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10528 13:09:55.976299 <6>[ 1.159550] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10529 13:09:55.986196 <6>[ 1.168091] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10530 13:09:55.997484 <6>[ 1.183559] loop: module loaded
10531 13:09:56.004330 <6>[ 1.189294] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10532 13:09:56.026502 <4>[ 1.212562] mtk-pmic-keys: Failed to locate of_node [id: -1]
10533 13:09:56.033293 <6>[ 1.219374] megasas: 07.719.03.00-rc1
10534 13:09:56.043452 <6>[ 1.229427] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10535 13:09:56.052721 <6>[ 1.238662] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10536 13:09:56.069518 <6>[ 1.255372] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10537 13:09:56.125510 <6>[ 1.305089] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10538 13:09:56.394898 <6>[ 1.580565] Freeing initrd memory: 18280K
10539 13:09:56.406283 <6>[ 1.592219] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10540 13:09:56.417315 <6>[ 1.603187] tun: Universal TUN/TAP device driver, 1.6
10541 13:09:56.420717 <6>[ 1.609263] thunder_xcv, ver 1.0
10542 13:09:56.423775 <6>[ 1.612768] thunder_bgx, ver 1.0
10543 13:09:56.426946 <6>[ 1.616264] nicpf, ver 1.0
10544 13:09:56.437817 <6>[ 1.620295] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10545 13:09:56.441223 <6>[ 1.627771] hns3: Copyright (c) 2017 Huawei Corporation.
10546 13:09:56.447494 <6>[ 1.633358] hclge is initializing
10547 13:09:56.450912 <6>[ 1.636931] e1000: Intel(R) PRO/1000 Network Driver
10548 13:09:56.457727 <6>[ 1.642061] e1000: Copyright (c) 1999-2006 Intel Corporation.
10549 13:09:56.460878 <6>[ 1.648074] e1000e: Intel(R) PRO/1000 Network Driver
10550 13:09:56.467610 <6>[ 1.653290] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10551 13:09:56.474174 <6>[ 1.659478] igb: Intel(R) Gigabit Ethernet Network Driver
10552 13:09:56.480818 <6>[ 1.665127] igb: Copyright (c) 2007-2014 Intel Corporation.
10553 13:09:56.487814 <6>[ 1.670962] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10554 13:09:56.493815 <6>[ 1.677480] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10555 13:09:56.497670 <6>[ 1.683945] sky2: driver version 1.30
10556 13:09:56.504033 <6>[ 1.688899] usbcore: registered new device driver r8152-cfgselector
10557 13:09:56.510262 <6>[ 1.695435] usbcore: registered new interface driver r8152
10558 13:09:56.516975 <6>[ 1.701253] VFIO - User Level meta-driver version: 0.3
10559 13:09:56.523991 <6>[ 1.709485] usbcore: registered new interface driver usb-storage
10560 13:09:56.530061 <6>[ 1.715931] usbcore: registered new device driver onboard-usb-hub
10561 13:09:56.539109 <6>[ 1.725103] mt6397-rtc mt6359-rtc: registered as rtc0
10562 13:09:56.549076 <6>[ 1.730571] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-18T13:09:56 UTC (1721308196)
10563 13:09:56.552413 <6>[ 1.740138] i2c_dev: i2c /dev entries driver
10564 13:09:56.566375 <4>[ 1.752312] cpu cpu0: supply cpu not found, using dummy regulator
10565 13:09:56.573301 <4>[ 1.758767] cpu cpu1: supply cpu not found, using dummy regulator
10566 13:09:56.579826 <4>[ 1.765164] cpu cpu2: supply cpu not found, using dummy regulator
10567 13:09:56.586216 <4>[ 1.771569] cpu cpu3: supply cpu not found, using dummy regulator
10568 13:09:56.592819 <4>[ 1.777964] cpu cpu4: supply cpu not found, using dummy regulator
10569 13:09:56.599448 <4>[ 1.784362] cpu cpu5: supply cpu not found, using dummy regulator
10570 13:09:56.605765 <4>[ 1.790769] cpu cpu6: supply cpu not found, using dummy regulator
10571 13:09:56.612569 <4>[ 1.797163] cpu cpu7: supply cpu not found, using dummy regulator
10572 13:09:56.633016 <6>[ 1.818805] cpu cpu0: EM: created perf domain
10573 13:09:56.636439 <6>[ 1.823718] cpu cpu4: EM: created perf domain
10574 13:09:56.643550 <6>[ 1.829338] sdhci: Secure Digital Host Controller Interface driver
10575 13:09:56.649953 <6>[ 1.835768] sdhci: Copyright(c) Pierre Ossman
10576 13:09:56.656784 <6>[ 1.840729] Synopsys Designware Multimedia Card Interface Driver
10577 13:09:56.663378 <6>[ 1.847391] sdhci-pltfm: SDHCI platform and OF driver helper
10578 13:09:56.666912 <6>[ 1.847547] mmc0: CQHCI version 5.10
10579 13:09:56.673206 <6>[ 1.857260] ledtrig-cpu: registered to indicate activity on CPUs
10580 13:09:56.679601 <6>[ 1.864192] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10581 13:09:56.686099 <6>[ 1.871285] usbcore: registered new interface driver usbhid
10582 13:09:56.689840 <6>[ 1.877108] usbhid: USB HID core driver
10583 13:09:56.696608 <6>[ 1.881335] spi_master spi0: will run message pump with realtime priority
10584 13:09:56.742098 <6>[ 1.921483] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10585 13:09:56.761315 <6>[ 1.937033] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10586 13:09:56.768295 <6>[ 1.952335] cros-ec-spi spi0.0: Chrome EC device registered
10587 13:09:56.774496 <6>[ 1.953904] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15814
10588 13:09:56.782665 <6>[ 1.968729] mmc0: Command Queue Engine enabled
10589 13:09:56.793060 <6>[ 1.971824] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10590 13:09:56.799580 <6>[ 1.973439] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10591 13:09:56.803054 <6>[ 1.983910] NET: Registered PF_PACKET protocol family
10592 13:09:56.809091 <6>[ 1.990078] mmcblk0: mmc0:0001 DA4128 116 GiB
10593 13:09:56.812534 <6>[ 1.994701] 9pnet: Installing 9P2000 support
10594 13:09:56.815924 <5>[ 2.003886] Key type dns_resolver registered
10595 13:09:56.822695 <6>[ 2.005787] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10596 13:09:56.829427 <6>[ 2.008732] registered taskstats version 1
10597 13:09:56.832211 <6>[ 2.015217] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10598 13:09:56.839075 <5>[ 2.018707] Loading compiled-in X.509 certificates
10599 13:09:56.842116 <6>[ 2.024652] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10600 13:09:56.848942 <6>[ 2.034948] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10601 13:09:56.867219 <4>[ 2.046655] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10602 13:09:56.877024 <4>[ 2.057416] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10603 13:09:56.895185 <6>[ 2.081104] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10604 13:09:56.902140 <6>[ 2.088153] xhci-mtk 11200000.usb: xHCI Host Controller
10605 13:09:56.908676 <6>[ 2.093651] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10606 13:09:56.918853 <6>[ 2.101496] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10607 13:09:56.925718 <6>[ 2.110918] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10608 13:09:56.932472 <6>[ 2.116994] xhci-mtk 11200000.usb: xHCI Host Controller
10609 13:09:56.939139 <6>[ 2.122472] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10610 13:09:56.945324 <6>[ 2.130123] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10611 13:09:56.951895 <6>[ 2.137753] hub 1-0:1.0: USB hub found
10612 13:09:56.955601 <6>[ 2.141782] hub 1-0:1.0: 1 port detected
10613 13:09:56.962059 <6>[ 2.146068] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10614 13:09:56.968999 <6>[ 2.154611] hub 2-0:1.0: USB hub found
10615 13:09:56.972214 <6>[ 2.158634] hub 2-0:1.0: 1 port detected
10616 13:09:56.979437 <6>[ 2.165608] mtk-msdc 11f70000.mmc: Got CD GPIO
10617 13:09:56.997469 <6>[ 2.179826] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10618 13:09:57.007220 <6>[ 2.188218] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10619 13:09:57.013583 <6>[ 2.196560] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10620 13:09:57.023547 <6>[ 2.204899] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10621 13:09:57.030679 <6>[ 2.213239] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10622 13:09:57.040108 <6>[ 2.221579] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10623 13:09:57.046726 <6>[ 2.229918] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10624 13:09:57.056826 <6>[ 2.238258] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10625 13:09:57.063586 <6>[ 2.246597] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10626 13:09:57.073657 <6>[ 2.254936] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10627 13:09:57.080278 <6>[ 2.263294] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10628 13:09:57.089878 <6>[ 2.271636] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10629 13:09:57.096636 <6>[ 2.279975] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10630 13:09:57.106655 <6>[ 2.288314] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10631 13:09:57.113030 <6>[ 2.296663] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10632 13:09:57.119450 <6>[ 2.305357] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10633 13:09:57.126736 <6>[ 2.312554] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10634 13:09:57.133487 <6>[ 2.319342] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10635 13:09:57.143719 <6>[ 2.326113] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10636 13:09:57.149779 <6>[ 2.333080] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10637 13:09:57.156528 <6>[ 2.339938] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10638 13:09:57.166593 <6>[ 2.349072] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10639 13:09:57.176545 <6>[ 2.358195] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10640 13:09:57.186807 <6>[ 2.367490] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10641 13:09:57.196394 <6>[ 2.376967] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10642 13:09:57.202719 <6>[ 2.386435] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10643 13:09:57.213084 <6>[ 2.395555] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10644 13:09:57.223370 <6>[ 2.405023] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10645 13:09:57.232697 <6>[ 2.414142] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10646 13:09:57.243047 <6>[ 2.423437] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10647 13:09:57.252877 <6>[ 2.433598] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10648 13:09:57.262732 <6>[ 2.445386] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10649 13:09:57.270435 <6>[ 2.456572] Trying to probe devices needed for running init ...
10650 13:09:57.281237 <3>[ 2.463867] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10651 13:09:57.361157 <6>[ 2.543786] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10652 13:09:57.388436 <6>[ 2.574550] hub 2-1:1.0: USB hub found
10653 13:09:57.391882 <6>[ 2.578997] hub 2-1:1.0: 3 ports detected
10654 13:09:57.401090 <6>[ 2.587147] hub 2-1:1.0: USB hub found
10655 13:09:57.404368 <6>[ 2.591578] hub 2-1:1.0: 3 ports detected
10656 13:09:57.512611 <6>[ 2.695552] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10657 13:09:57.667516 <6>[ 2.853702] hub 1-1:1.0: USB hub found
10658 13:09:57.670952 <6>[ 2.858196] hub 1-1:1.0: 4 ports detected
10659 13:09:57.684225 <6>[ 2.870134] hub 1-1:1.0: USB hub found
10660 13:09:57.687852 <6>[ 2.874458] hub 1-1:1.0: 4 ports detected
10661 13:09:57.744773 <6>[ 2.927660] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10662 13:09:57.853041 <6>[ 3.035959] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10663 13:09:57.885146 <4>[ 3.068017] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10664 13:09:57.895399 <4>[ 3.077119] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10665 13:09:57.930186 <6>[ 3.116180] r8152 2-1.3:1.0 eth0: v1.12.13
10666 13:09:58.008503 <6>[ 3.191555] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10667 13:09:58.142262 <6>[ 3.328048] hub 1-1.4:1.0: USB hub found
10668 13:09:58.145591 <6>[ 3.332754] hub 1-1.4:1.0: 2 ports detected
10669 13:09:58.158680 <6>[ 3.344880] hub 1-1.4:1.0: USB hub found
10670 13:09:58.161987 <6>[ 3.349476] hub 1-1.4:1.0: 2 ports detected
10671 13:09:58.460706 <6>[ 3.643387] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10672 13:09:58.652457 <6>[ 3.835380] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10673 13:09:59.529639 <6>[ 4.716006] r8152 2-1.3:1.0 eth0: carrier on
10674 13:10:02.520441 <5>[ 4.739375] Sending DHCP requests .., OK
10675 13:10:02.527520 <6>[ 7.711723] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10676 13:10:02.530465 <6>[ 7.720019] IP-Config: Complete:
10677 13:10:02.543908 <6>[ 7.723512] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10678 13:10:02.550501 <6>[ 7.734229] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10679 13:10:02.559896 <6>[ 7.742860] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10680 13:10:02.563643 <6>[ 7.742869] nameserver0=192.168.201.1
10681 13:10:02.566586 <6>[ 7.755039] clk: Disabling unused clocks
10682 13:10:02.571149 <6>[ 7.760560] ALSA device list:
10683 13:10:02.577346 <6>[ 7.763817] No soundcards found.
10684 13:10:02.584969 <6>[ 7.771487] Freeing unused kernel memory: 8512K
10685 13:10:02.587900 <6>[ 7.776481] Run /init as init process
10686 13:10:02.598840 Loading, please wait...
10687 13:10:02.630011 Starting systemd-udevd version 252.22-1~deb12u1
10688 13:10:02.876198 <6>[ 8.059389] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10689 13:10:02.909102 <6>[ 8.092301] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10690 13:10:02.915725 <6>[ 8.100381] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10691 13:10:02.925877 <4>[ 8.108410] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10692 13:10:02.932007 <6>[ 8.112666] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10693 13:10:02.941965 <6>[ 8.117977] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10694 13:10:02.948661 <6>[ 8.118819] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10695 13:10:02.958989 <6>[ 8.118851] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10696 13:10:02.965219 <6>[ 8.118860] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10697 13:10:02.971720 <6>[ 8.141916] remoteproc remoteproc0: scp is available
10698 13:10:02.978688 <6>[ 8.149105] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10699 13:10:02.988331 <6>[ 8.149643] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10700 13:10:02.994722 <3>[ 8.152172] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10701 13:10:03.005407 <3>[ 8.152186] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10702 13:10:03.011541 <3>[ 8.152190] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10703 13:10:03.018474 <3>[ 8.152370] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10704 13:10:03.028524 <3>[ 8.152375] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 13:10:03.035411 <3>[ 8.152378] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 13:10:03.045325 <3>[ 8.152383] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10707 13:10:03.051575 <3>[ 8.152386] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 13:10:03.061718 <3>[ 8.152417] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 13:10:03.068235 <3>[ 8.152456] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10710 13:10:03.078586 <3>[ 8.152459] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10711 13:10:03.085247 <3>[ 8.152465] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10712 13:10:03.091920 <3>[ 8.152497] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 13:10:03.101537 <3>[ 8.152500] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 13:10:03.108132 <3>[ 8.152503] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10715 13:10:03.118087 <3>[ 8.152505] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 13:10:03.125065 <3>[ 8.152508] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10717 13:10:03.134779 <3>[ 8.152532] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10718 13:10:03.141678 <6>[ 8.152856] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10719 13:10:03.147956 <6>[ 8.158095] remoteproc remoteproc0: powering up scp
10720 13:10:03.154700 <6>[ 8.163067] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10721 13:10:03.161074 <4>[ 8.170325] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10722 13:10:03.171493 <6>[ 8.170970] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10723 13:10:03.177687 <4>[ 8.173842] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10724 13:10:03.187643 <4>[ 8.176608] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10725 13:10:03.191360 <4>[ 8.176608] Fallback method does not support PEC.
10726 13:10:03.200930 <6>[ 8.178871] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10727 13:10:03.204151 <6>[ 8.186990] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10728 13:10:03.214065 <6>[ 8.195034] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10729 13:10:03.217149 <6>[ 8.196572] mc: Linux media interface: v0.10
10730 13:10:03.227461 <3>[ 8.214436] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10731 13:10:03.233992 <6>[ 8.241094] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10732 13:10:03.243638 <3>[ 8.267700] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10733 13:10:03.250371 <6>[ 8.269399] pci_bus 0000:00: root bus resource [bus 00-ff]
10734 13:10:03.256688 <6>[ 8.283578] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10735 13:10:03.266944 <6>[ 8.285011] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10736 13:10:03.276531 <6>[ 8.296626] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10737 13:10:03.286686 <6>[ 8.301198] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10738 13:10:03.293396 <6>[ 8.309739] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10739 13:10:03.299677 <6>[ 8.317418] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10740 13:10:03.306611 <6>[ 8.329114] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10741 13:10:03.316063 <6>[ 8.333136] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10742 13:10:03.322865 <6>[ 8.333143] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10743 13:10:03.329484 <6>[ 8.333148] remoteproc remoteproc0: remote processor scp is now up
10744 13:10:03.336036 <6>[ 8.333236] pci 0000:00:00.0: supports D1 D2
10745 13:10:03.342646 <6>[ 8.333238] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10746 13:10:03.346100 <6>[ 8.333999] videodev: Linux video capture interface: v2.00
10747 13:10:03.356071 <6>[ 8.334244] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10748 13:10:03.362622 <6>[ 8.334373] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10749 13:10:03.369002 <6>[ 8.334399] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10750 13:10:03.375803 <6>[ 8.334416] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10751 13:10:03.382472 <6>[ 8.334431] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10752 13:10:03.388868 <6>[ 8.334542] pci 0000:01:00.0: supports D1 D2
10753 13:10:03.395455 <6>[ 8.334545] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10754 13:10:03.402509 <6>[ 8.343500] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10755 13:10:03.405143 <6>[ 8.354529] Bluetooth: Core ver 2.22
10756 13:10:03.415286 <6>[ 8.355842] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10757 13:10:03.422088 <6>[ 8.357845] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10758 13:10:03.432017 <6>[ 8.362351] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10759 13:10:03.435224 <6>[ 8.369690] NET: Registered PF_BLUETOOTH protocol family
10760 13:10:03.444879 <6>[ 8.383247] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10761 13:10:03.451611 <6>[ 8.391062] Bluetooth: HCI device and connection manager initialized
10762 13:10:03.458163 <6>[ 8.396719] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10763 13:10:03.464901 <6>[ 8.405848] Bluetooth: HCI socket layer initialized
10764 13:10:03.471228 <6>[ 8.406806] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10765 13:10:03.484350 <6>[ 8.408114] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10766 13:10:03.487726 <6>[ 8.408355] usbcore: registered new interface driver uvcvideo
10767 13:10:03.498259 <6>[ 8.410362] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10768 13:10:03.501059 <6>[ 8.419124] Bluetooth: L2CAP socket layer initialized
10769 13:10:03.510713 <6>[ 8.425994] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10770 13:10:03.514026 <6>[ 8.434761] Bluetooth: SCO socket layer initialized
10771 13:10:03.520985 <6>[ 8.435258] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10772 13:10:03.527659 <6>[ 8.440497] pci 0000:00:00.0: PCI bridge to [bus 01]
10773 13:10:03.534152 <6>[ 8.508184] usbcore: registered new interface driver btusb
10774 13:10:03.543770 <4>[ 8.509401] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10775 13:10:03.550476 <3>[ 8.509406] Bluetooth: hci0: Failed to load firmware file (-2)
10776 13:10:03.553784 <3>[ 8.509408] Bluetooth: hci0: Failed to set up firmware (-2)
10777 13:10:03.567340 <4>[ 8.509410] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10778 13:10:03.573550 <6>[ 8.515178] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10779 13:10:03.580466 <6>[ 8.765749] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10780 13:10:03.587085 <6>[ 8.772612] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10781 13:10:03.593303 <6>[ 8.779007] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10782 13:10:03.617660 <5>[ 8.801302] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10783 13:10:03.636315 <5>[ 8.819601] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10784 13:10:03.643206 <5>[ 8.827105] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10785 13:10:03.653251 <4>[ 8.835615] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10786 13:10:03.659531 <6>[ 8.844536] cfg80211: failed to load regulatory.db
10787 13:10:03.714576 <6>[ 8.898114] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10788 13:10:03.720963 <6>[ 8.905677] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10789 13:10:03.745558 <6>[ 8.932512] mt7921e 0000:01:00.0: ASIC revision: 79610010
10790 13:10:03.849987 <6>[ 9.033205] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10791 13:10:03.853024 <6>[ 9.033205]
10792 13:10:03.862340 Begin: Loading essential drivers ... done.
10793 13:10:03.865749 Begin: Running /scripts/init-premount ... done.
10794 13:10:03.872481 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10795 13:10:03.882720 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10796 13:10:03.885501 Device /sys/class/net/eth0 found
10797 13:10:03.885593 done.
10798 13:10:03.892053 Begin: Waiting up to 180 secs for any network device to become available ... done.
10799 13:10:03.932815 IP-Config: eth0 hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10800 13:10:03.939069 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10801 13:10:03.945714 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10802 13:10:03.953005 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10803 13:10:03.959042 host : mt8192-asurada-spherion-r0-cbg-2
10804 13:10:03.966034 domain : lava-rack
10805 13:10:03.969657 rootserver: 192.168.201.1 rootpath:
10806 13:10:03.969728 filename :
10807 13:10:03.972175 done.
10808 13:10:03.975574 Begin: Running /scripts/nfs-bottom ... done.
10809 13:10:04.001238 Begin: Running /scripts/init-bottom ... done.
10810 13:10:04.122002 <6>[ 9.305835] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10811 13:10:05.377623 <6>[ 10.564825] NET: Registered PF_INET6 protocol family
10812 13:10:05.385571 <6>[ 10.572309] Segment Routing with IPv6
10813 13:10:05.388803 <6>[ 10.576341] In-situ OAM (IOAM) with IPv6
10814 13:10:05.563551 <30>[ 10.723491] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10815 13:10:05.569581 <30>[ 10.756629] systemd[1]: Detected architecture arm64.
10816 13:10:05.578883
10817 13:10:05.582611 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10818 13:10:05.582691
10819 13:10:05.610232 <30>[ 10.796998] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10820 13:10:06.701600 <30>[ 11.885401] systemd[1]: Queued start job for default target graphical.target.
10821 13:10:06.744565 <30>[ 11.928470] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10822 13:10:06.751356 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10823 13:10:06.773411 <30>[ 11.957359] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10824 13:10:06.783380 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10825 13:10:06.801706 <30>[ 11.985357] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10826 13:10:06.811354 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10827 13:10:06.829341 <30>[ 12.012901] systemd[1]: Created slice user.slice - User and Session Slice.
10828 13:10:06.835432 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10829 13:10:06.860133 <30>[ 12.040435] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10830 13:10:06.869838 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10831 13:10:06.887524 <30>[ 12.067809] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10832 13:10:06.893921 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10833 13:10:06.922222 <30>[ 12.096198] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10834 13:10:06.932074 <30>[ 12.115993] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10835 13:10:06.938668 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10836 13:10:06.955601 <30>[ 12.139462] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10837 13:10:06.962450 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10838 13:10:06.979728 <30>[ 12.163535] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10839 13:10:06.989589 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10840 13:10:07.004341 <30>[ 12.191664] systemd[1]: Reached target paths.target - Path Units.
10841 13:10:07.014539 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10842 13:10:07.032242 <30>[ 12.216020] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10843 13:10:07.038520 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10844 13:10:07.052426 <30>[ 12.239551] systemd[1]: Reached target slices.target - Slice Units.
10845 13:10:07.062790 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10846 13:10:07.076715 <30>[ 12.264041] systemd[1]: Reached target swap.target - Swaps.
10847 13:10:07.083341 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10848 13:10:07.104301 <30>[ 12.288059] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10849 13:10:07.114373 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10850 13:10:07.132317 <30>[ 12.316029] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10851 13:10:07.142075 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10852 13:10:07.163986 <30>[ 12.347489] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10853 13:10:07.173498 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10854 13:10:07.194167 <30>[ 12.377128] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10855 13:10:07.202923 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10856 13:10:07.220265 <30>[ 12.404261] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10857 13:10:07.226808 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10858 13:10:07.245098 <30>[ 12.429131] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10859 13:10:07.255171 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10860 13:10:07.274870 <30>[ 12.458750] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10861 13:10:07.284545 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10862 13:10:07.300178 <30>[ 12.484041] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10863 13:10:07.309894 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10864 13:10:07.351616 <30>[ 12.535643] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10865 13:10:07.358089 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10866 13:10:07.380184 <30>[ 12.564035] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10867 13:10:07.387099 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10868 13:10:07.412956 <30>[ 12.596733] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10869 13:10:07.419469 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10870 13:10:07.446590 <30>[ 12.623848] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10871 13:10:07.500337 <30>[ 12.684329] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10872 13:10:07.510540 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10873 13:10:07.533360 <30>[ 12.717267] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10874 13:10:07.540345 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10875 13:10:07.565347 <30>[ 12.749013] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10876 13:10:07.572669 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10877 13:10:07.596092 <30>[ 12.779755] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10878 13:10:07.602560 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10879 13:10:07.612135 <6>[ 12.793725] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10880 13:10:07.612219
10881 13:10:07.637854 <30>[ 12.821386] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10882 13:10:07.647311 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10883 13:10:07.667859 <30>[ 12.851687] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10884 13:10:07.674182 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10885 13:10:07.697273 <30>[ 12.880932] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10886 13:10:07.707103 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kern<6>[ 12.893629] fuse: init (API version 7.37)
10887 13:10:07.707195 el Module loop...
10888 13:10:07.736779 <30>[ 12.920763] systemd[1]: Starting systemd-journald.service - Journal Service...
10889 13:10:07.743224 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10890 13:10:07.767429 <30>[ 12.951381] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10891 13:10:07.774161 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10892 13:10:07.800316 <30>[ 12.980989] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10893 13:10:07.806636 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10894 13:10:07.832626 <30>[ 13.016731] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10895 13:10:07.842802 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10896 13:10:07.888672 <30>[ 13.072304] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10897 13:10:07.894976 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10898 13:10:07.921685 <30>[ 13.105008] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10899 13:10:07.928611 <3>[ 13.112602] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 13:10:07.938190 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10901 13:10:07.956335 <30>[ 13.140009] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10902 13:10:07.963285 <3>[ 13.141724] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 13:10:07.972852 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10904 13:10:07.992172 <30>[ 13.176088] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10905 13:10:07.999402 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10906 13:10:08.009986 <3>[ 13.194170] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 13:10:08.024783 <30>[ 13.208464] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10908 13:10:08.038547 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate <3>[ 13.222938] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 13:10:08.041973 List of Static Device Nodes.
10910 13:10:08.052515 <30>[ 13.236444] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10911 13:10:08.060184 <30>[ 13.244532] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10912 13:10:08.069568 <3>[ 13.252189] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 13:10:08.079225 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10914 13:10:08.096618 <30>[ 13.280370] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10915 13:10:08.103370 <3>[ 13.283134] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 13:10:08.113493 <30>[ 13.288389] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10917 13:10:08.119651 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10918 13:10:08.134567 <3>[ 13.318462] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 13:10:08.145528 <30>[ 13.329368] systemd[1]: modprobe@drm.service: Deactivated successfully.
10920 13:10:08.152442 <30>[ 13.337189] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10921 13:10:08.169274 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Mod<3>[ 13.351214] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 13:10:08.169399 ule drm.
10923 13:10:08.189210 <30>[ 13.372803] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10924 13:10:08.198867 <30>[ 13.381002] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10925 13:10:08.205662 <3>[ 13.384380] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 13:10:08.215605 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10927 13:10:08.230033 <30>[ 13.416591] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10928 13:10:08.240109 <3>[ 13.422656] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 13:10:08.246639 <30>[ 13.425120] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10930 13:10:08.256605 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10931 13:10:08.274200 <3>[ 13.458356] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 13:10:08.284902 <30>[ 13.469067] systemd[1]: modprobe@loop.service: Deactivated successfully.
10933 13:10:08.291750 <30>[ 13.476699] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10934 13:10:08.308552 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Mo<3>[ 13.490913] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 13:10:08.308664 dule loop.
10936 13:10:08.329179 <30>[ 13.512554] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10937 13:10:08.342957 [[0;32m OK [0m] Finished [0;1;39msystemd-mo<3>[ 13.524075] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 13:10:08.356774 <4>[ 13.533862] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10939 13:10:08.363871 <3>[ 13.549498] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10940 13:10:08.369985 dules-l…service[0m - Load Kernel Modules.
10941 13:10:08.393697 <30>[ 13.574103] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10942 13:10:08.400258 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10943 13:10:08.420525 <30>[ 13.604477] systemd[1]: Started systemd-journald.service - Journal Service.
10944 13:10:08.427310 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10945 13:10:08.448543 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10946 13:10:08.469418 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10947 13:10:08.490504 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10948 13:10:08.540553 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10949 13:10:08.559572 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10950 13:10:08.584561 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10951 13:10:08.614525 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10952 13:10:08.654854 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Ke<46>[ 13.836346] systemd-journald[311]: Received client request to flush runtime journal.
10953 13:10:08.654981 rnel Variables...
10954 13:10:08.720503 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10955 13:10:08.977984 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10956 13:10:08.996700 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10957 13:10:09.016657 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10958 13:10:09.754433 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10959 13:10:10.062644 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10960 13:10:10.086334 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10961 13:10:10.140458 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10962 13:10:10.246743 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10963 13:10:10.263965 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10964 13:10:10.283692 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10965 13:10:10.323956 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10966 13:10:10.345937 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10967 13:10:10.576618 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10968 13:10:10.662136 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10969 13:10:10.719748 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10970 13:10:11.035055 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10971 13:10:11.044269 <6>[ 16.231768] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10972 13:10:11.073051 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10973 13:10:11.141552 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10974 13:10:11.206957 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10975 13:10:11.230591 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10976 13:10:11.272239 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10977 13:10:11.292592 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10978 13:10:11.312469 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10979 13:10:11.333727 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10980 13:10:11.362991 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10981 13:10:11.431992 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10982 13:10:11.465142 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10983 13:10:11.484356 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10984 13:10:11.539739 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10985 13:10:11.556193 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10986 13:10:11.575594 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10987 13:10:11.591548 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10988 13:10:11.626824 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10989 13:10:11.646644 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10990 13:10:11.663966 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10991 13:10:11.682780 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10992 13:10:11.702757 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10993 13:10:11.719408 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10994 13:10:11.737511 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10995 13:10:11.755184 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10996 13:10:11.761655 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10997 13:10:11.813448 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10998 13:10:11.846451 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10999 13:10:11.928312 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11000 13:10:11.954386 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11001 13:10:12.014682 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11002 13:10:12.044712 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11003 13:10:12.063095 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11004 13:10:12.083455 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11005 13:10:12.181360 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11006 13:10:12.219956 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11007 13:10:12.291185 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11008 13:10:12.313472 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11009 13:10:12.331670 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11010 13:10:12.392642 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11011 13:10:12.439428 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11012 13:10:12.542352
11013 13:10:12.545375 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11014 13:10:12.545476
11015 13:10:12.548473 debian-bookworm-arm64 login: root (automatic login)
11016 13:10:12.548544
11017 13:10:12.873083 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024 aarch64
11018 13:10:12.873249
11019 13:10:12.879418 The programs included with the Debian GNU/Linux system are free software;
11020 13:10:12.885819 the exact distribution terms for each program are described in the
11021 13:10:12.889470 individual files in /usr/share/doc/*/copyright.
11022 13:10:12.889542
11023 13:10:12.896078 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11024 13:10:12.899028 permitted by applicable law.
11025 13:10:14.030626 Matched prompt #10: / #
11027 13:10:14.030874 Setting prompt string to ['/ #']
11028 13:10:14.030965 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11030 13:10:14.031145 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11031 13:10:14.031227 start: 2.2.6 expect-shell-connection (timeout 00:03:18) [common]
11032 13:10:14.031290 Setting prompt string to ['/ #']
11033 13:10:14.031346 Forcing a shell prompt, looking for ['/ #']
11034 13:10:14.031405 Sending line: ''
11036 13:10:14.081729 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11037 13:10:14.081802 Waiting using forced prompt support (timeout 00:02:30)
11038 13:10:14.086863 / #
11039 13:10:14.087123 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11040 13:10:14.087212 start: 2.2.7 export-device-env (timeout 00:03:18) [common]
11041 13:10:14.087285 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14879017/extract-nfsrootfs-jt9hskzb'"
11043 13:10:14.192929 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14879017/extract-nfsrootfs-jt9hskzb'
11044 13:10:14.193186 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
11046 13:10:14.299052 / # export NFS_SERVER_IP='192.168.201.1'
11047 13:10:14.299328 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11048 13:10:14.299446 end: 2.2 depthcharge-retry (duration 00:01:42) [common]
11049 13:10:14.299554 end: 2 depthcharge-action (duration 00:01:42) [common]
11050 13:10:14.299665 start: 3 lava-test-retry (timeout 00:07:34) [common]
11051 13:10:14.299775 start: 3.1 lava-test-shell (timeout 00:07:34) [common]
11052 13:10:14.299870 Using namespace: common
11053 13:10:14.299964 Sending line: '#'
11055 13:10:14.400392 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11056 13:10:14.405795 / # #
11057 13:10:14.406045 Using /lava-14879017
11058 13:10:14.406111 Sending line: 'export SHELL=/bin/bash'
11060 13:10:14.512410 / # export SHELL=/bin/bash
11061 13:10:14.513070 Sending line: '. /lava-14879017/environment'
11063 13:10:14.618466 / # . /lava-14879017/environment
11064 13:10:14.624908 Sending line: '/lava-14879017/bin/lava-test-runner /lava-14879017/0'
11066 13:10:14.725399 Test shell timeout: 10s (minimum of the action and connection timeout)
11067 13:10:14.730554 / # /lava-14879017/bin/lava-test-runner /lava-14879017/0
11068 13:10:14.996854 + export TESTRUN_ID=0_timesync-off
11069 13:10:15.000056 + TESTRUN_ID=0_timesync-off
11070 13:10:15.003241 + cd /lava-14879017/0/tests/0_timesync-off
11071 13:10:15.006439 ++ cat uuid
11072 13:10:15.012453 + UUID=14879017_1.6.2.3.1
11073 13:10:15.012523 + set +x
11074 13:10:15.018872 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14879017_1.6.2.3.1>
11075 13:10:15.019138 Received signal: <STARTRUN> 0_timesync-off 14879017_1.6.2.3.1
11076 13:10:15.019206 Starting test lava.0_timesync-off (14879017_1.6.2.3.1)
11077 13:10:15.019284 Skipping test definition patterns.
11078 13:10:15.022087 + systemctl stop systemd-timesyncd
11079 13:10:15.087071 + set +x
11080 13:10:15.090226 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14879017_1.6.2.3.1>
11081 13:10:15.090469 Received signal: <ENDRUN> 0_timesync-off 14879017_1.6.2.3.1
11082 13:10:15.090547 Ending use of test pattern.
11083 13:10:15.090603 Ending test lava.0_timesync-off (14879017_1.6.2.3.1), duration 0.07
11085 13:10:15.177967 + export TESTRUN_ID=1_kselftest-dt
11086 13:10:15.180880 + TESTRUN_ID=1_kselftest-dt
11087 13:10:15.184428 + cd /lava-14879017/0/tests/1_kselftest-dt
11088 13:10:15.187711 ++ cat uuid
11089 13:10:15.194932 + UUID=14879017_1.6.2.3.5
11090 13:10:15.195014 + set +x
11091 13:10:15.201359 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 14879017_1.6.2.3.5>
11092 13:10:15.201607 Received signal: <STARTRUN> 1_kselftest-dt 14879017_1.6.2.3.5
11093 13:10:15.201672 Starting test lava.1_kselftest-dt (14879017_1.6.2.3.5)
11094 13:10:15.201786 Skipping test definition patterns.
11095 13:10:15.204902 + cd ./automated/linux/kselftest/
11096 13:10:15.231024 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
11097 13:10:15.279139 INFO: install_deps skipped
11098 13:10:15.793150 --2024-07-18 13:10:15-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz
11099 13:10:15.799765 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11100 13:10:15.929571 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11101 13:10:16.059751 HTTP request sent, awaiting response... 200 OK
11102 13:10:16.062650 Length: 1919140 (1.8M) [application/octet-stream]
11103 13:10:16.065830 Saving to: 'kselftest_armhf.tar.gz'
11104 13:10:16.065906
11105 13:10:16.065991
11106 13:10:16.318126 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11107 13:10:16.575458 kselftest_armhf.tar 2%[ ] 50.15K 194KB/s
11108 13:10:16.882878 kselftest_armhf.tar 11%[=> ] 217.50K 421KB/s
11109 13:10:17.016908 kselftest_armhf.tar 43%[=======> ] 814.23K 988KB/s
11110 13:10:17.023385 kselftest_armhf.tar 100%[===================>] 1.83M 1.91MB/s in 1.0s
11111 13:10:17.023468
11112 13:10:17.191726 2024-07-18 13:10:16 (1.91 MB/s) - 'kselftest_armhf.tar.gz' saved [1919140/1919140]
11113 13:10:17.191860
11114 13:10:24.256162 skiplist:
11115 13:10:24.259622 ========================================
11116 13:10:24.263134 ========================================
11117 13:10:24.329911 ============== Tests to run ===============
11118 13:10:24.332512 ===========End Tests to run ===============
11119 13:10:24.336831 shardfile-dt fail
11120 13:10:24.362966 ./kselftest.sh: 139: cannot open /lava-14879017/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11121 13:10:24.366363 + ../../utils/send-to-lava.sh ./output/result.txt
11122 13:10:24.434940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11123 13:10:24.435059 + set +x
11124 13:10:24.435295 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11126 13:10:24.441812 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 14879017_1.6.2.3.5>
11127 13:10:24.442058 Received signal: <ENDRUN> 1_kselftest-dt 14879017_1.6.2.3.5
11128 13:10:24.442128 Ending use of test pattern.
11129 13:10:24.442184 Ending test lava.1_kselftest-dt (14879017_1.6.2.3.5), duration 9.24
11131 13:10:24.442375 ok: lava_test_shell seems to have completed
11132 13:10:24.442486 shardfile-dt: fail
11133 13:10:24.442596 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11134 13:10:24.442672 end: 3 lava-test-retry (duration 00:00:10) [common]
11135 13:10:24.442753 start: 4 finalize (timeout 00:07:24) [common]
11136 13:10:24.442834 start: 4.1 power-off (timeout 00:00:30) [common]
11137 13:10:24.442960 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
11138 13:10:26.525103 >> Command sent successfully.
11139 13:10:26.529153 Returned 0 in 2 seconds
11140 13:10:26.529344 end: 4.1 power-off (duration 00:00:02) [common]
11142 13:10:26.529539 start: 4.2 read-feedback (timeout 00:07:22) [common]
11144 13:10:26.529944 Listened to connection for namespace 'common' for up to 1s
11145 13:10:27.530696 Finalising connection for namespace 'common'
11146 13:10:27.530868 Disconnecting from shell: Finalise
11147 13:10:27.530962 / #
11148 13:10:27.631204 end: 4.2 read-feedback (duration 00:00:01) [common]
11149 13:10:27.631359 end: 4 finalize (duration 00:00:03) [common]
11150 13:10:27.631494 Cleaning after the job
11151 13:10:27.631612 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879017/tftp-deploy-1qe5qw7y/ramdisk
11152 13:10:27.633708 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879017/tftp-deploy-1qe5qw7y/kernel
11153 13:10:27.643870 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879017/tftp-deploy-1qe5qw7y/dtb
11154 13:10:27.644070 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879017/tftp-deploy-1qe5qw7y/nfsrootfs
11155 13:10:27.705694 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879017/tftp-deploy-1qe5qw7y/modules
11156 13:10:27.711165 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14879017
11157 13:10:28.304076 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14879017
11158 13:10:28.304259 Job finished correctly