Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 25
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 22
1 13:18:18.387528 lava-dispatcher, installed at version: 2024.05
2 13:18:18.387733 start: 0 validate
3 13:18:18.387848 Start time: 2024-07-18 13:18:18.387842+00:00 (UTC)
4 13:18:18.387978 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:18:18.388119 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 13:18:18.647209 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:18:18.647366 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 13:18:18.904863 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:18:18.905029 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:18:19.163523 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:18:19.163710 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
12 13:18:19.425212 validate duration: 1.04
14 13:18:19.425455 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:18:19.425551 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:18:19.425634 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:18:19.425794 Not decompressing ramdisk as can be used compressed.
18 13:18:19.425883 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 13:18:19.425981 saving as /var/lib/lava/dispatcher/tmp/14879051/tftp-deploy-779tez8t/ramdisk/rootfs.cpio.gz
20 13:18:19.426067 total size: 28105535 (26 MB)
21 13:18:19.427089 progress 0 % (0 MB)
22 13:18:19.434444 progress 5 % (1 MB)
23 13:18:19.441802 progress 10 % (2 MB)
24 13:18:19.448994 progress 15 % (4 MB)
25 13:18:19.456247 progress 20 % (5 MB)
26 13:18:19.463372 progress 25 % (6 MB)
27 13:18:19.470612 progress 30 % (8 MB)
28 13:18:19.477800 progress 35 % (9 MB)
29 13:18:19.484989 progress 40 % (10 MB)
30 13:18:19.492060 progress 45 % (12 MB)
31 13:18:19.499134 progress 50 % (13 MB)
32 13:18:19.506134 progress 55 % (14 MB)
33 13:18:19.513157 progress 60 % (16 MB)
34 13:18:19.520381 progress 65 % (17 MB)
35 13:18:19.527392 progress 70 % (18 MB)
36 13:18:19.534444 progress 75 % (20 MB)
37 13:18:19.541440 progress 80 % (21 MB)
38 13:18:19.548433 progress 85 % (22 MB)
39 13:18:19.555267 progress 90 % (24 MB)
40 13:18:19.562331 progress 95 % (25 MB)
41 13:18:19.569848 progress 100 % (26 MB)
42 13:18:19.570179 26 MB downloaded in 0.14 s (186.00 MB/s)
43 13:18:19.570380 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:18:19.570759 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:18:19.570871 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:18:19.570977 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:18:19.571144 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
49 13:18:19.571238 saving as /var/lib/lava/dispatcher/tmp/14879051/tftp-deploy-779tez8t/kernel/Image
50 13:18:19.571319 total size: 54813184 (52 MB)
51 13:18:19.571400 No compression specified
52 13:18:19.572835 progress 0 % (0 MB)
53 13:18:19.586816 progress 5 % (2 MB)
54 13:18:19.600614 progress 10 % (5 MB)
55 13:18:19.614889 progress 15 % (7 MB)
56 13:18:19.628614 progress 20 % (10 MB)
57 13:18:19.642207 progress 25 % (13 MB)
58 13:18:19.655827 progress 30 % (15 MB)
59 13:18:19.670027 progress 35 % (18 MB)
60 13:18:19.684103 progress 40 % (20 MB)
61 13:18:19.697813 progress 45 % (23 MB)
62 13:18:19.711806 progress 50 % (26 MB)
63 13:18:19.725652 progress 55 % (28 MB)
64 13:18:19.739167 progress 60 % (31 MB)
65 13:18:19.752815 progress 65 % (34 MB)
66 13:18:19.766207 progress 70 % (36 MB)
67 13:18:19.779829 progress 75 % (39 MB)
68 13:18:19.793523 progress 80 % (41 MB)
69 13:18:19.806995 progress 85 % (44 MB)
70 13:18:19.820982 progress 90 % (47 MB)
71 13:18:19.834549 progress 95 % (49 MB)
72 13:18:19.847913 progress 100 % (52 MB)
73 13:18:19.848150 52 MB downloaded in 0.28 s (188.83 MB/s)
74 13:18:19.848301 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:18:19.848513 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:18:19.848595 start: 1.3 download-retry (timeout 00:10:00) [common]
78 13:18:19.848673 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 13:18:19.848811 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:18:19.848878 saving as /var/lib/lava/dispatcher/tmp/14879051/tftp-deploy-779tez8t/dtb/mt8192-asurada-spherion-r0.dtb
81 13:18:19.848932 total size: 47258 (0 MB)
82 13:18:19.848985 No compression specified
83 13:18:19.849989 progress 69 % (0 MB)
84 13:18:19.850257 progress 100 % (0 MB)
85 13:18:19.850403 0 MB downloaded in 0.00 s (30.68 MB/s)
86 13:18:19.850536 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:18:19.850741 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:18:19.850819 start: 1.4 download-retry (timeout 00:10:00) [common]
90 13:18:19.850895 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 13:18:19.851004 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
92 13:18:19.851066 saving as /var/lib/lava/dispatcher/tmp/14879051/tftp-deploy-779tez8t/modules/modules.tar
93 13:18:19.851119 total size: 8611320 (8 MB)
94 13:18:19.851173 Using unxz to decompress xz
95 13:18:19.852474 progress 0 % (0 MB)
96 13:18:19.873198 progress 5 % (0 MB)
97 13:18:19.899672 progress 10 % (0 MB)
98 13:18:19.924119 progress 15 % (1 MB)
99 13:18:19.948343 progress 20 % (1 MB)
100 13:18:19.971629 progress 25 % (2 MB)
101 13:18:19.996210 progress 30 % (2 MB)
102 13:18:20.019216 progress 35 % (2 MB)
103 13:18:20.045445 progress 40 % (3 MB)
104 13:18:20.072008 progress 45 % (3 MB)
105 13:18:20.097869 progress 50 % (4 MB)
106 13:18:20.123495 progress 55 % (4 MB)
107 13:18:20.147640 progress 60 % (4 MB)
108 13:18:20.171629 progress 65 % (5 MB)
109 13:18:20.198599 progress 70 % (5 MB)
110 13:18:20.227378 progress 75 % (6 MB)
111 13:18:20.255390 progress 80 % (6 MB)
112 13:18:20.280233 progress 85 % (7 MB)
113 13:18:20.303733 progress 90 % (7 MB)
114 13:18:20.328080 progress 95 % (7 MB)
115 13:18:20.351342 progress 100 % (8 MB)
116 13:18:20.357034 8 MB downloaded in 0.51 s (16.23 MB/s)
117 13:18:20.357197 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:18:20.357415 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:18:20.357498 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:18:20.357581 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:18:20.357653 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:18:20.357727 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:18:20.357906 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo
125 13:18:20.358035 makedir: /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin
126 13:18:20.358173 makedir: /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/tests
127 13:18:20.358302 makedir: /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/results
128 13:18:20.358423 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-add-keys
129 13:18:20.358559 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-add-sources
130 13:18:20.358681 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-background-process-start
131 13:18:20.358810 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-background-process-stop
132 13:18:20.358940 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-common-functions
133 13:18:20.359058 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-echo-ipv4
134 13:18:20.359173 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-install-packages
135 13:18:20.359287 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-installed-packages
136 13:18:20.359422 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-os-build
137 13:18:20.359597 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-probe-channel
138 13:18:20.359713 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-probe-ip
139 13:18:20.359826 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-target-ip
140 13:18:20.359943 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-target-mac
141 13:18:20.360056 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-target-storage
142 13:18:20.360172 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-test-case
143 13:18:20.360287 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-test-event
144 13:18:20.360399 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-test-feedback
145 13:18:20.360512 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-test-raise
146 13:18:20.360628 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-test-reference
147 13:18:20.360741 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-test-runner
148 13:18:20.360858 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-test-set
149 13:18:20.360971 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-test-shell
150 13:18:20.361086 Updating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-install-packages (oe)
151 13:18:20.361227 Updating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/bin/lava-installed-packages (oe)
152 13:18:20.361343 Creating /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/environment
153 13:18:20.361443 LAVA metadata
154 13:18:20.361507 - LAVA_JOB_ID=14879051
155 13:18:20.361563 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:18:20.361651 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:18:20.361707 skipped lava-vland-overlay
158 13:18:20.361773 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:18:20.361843 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:18:20.361911 skipped lava-multinode-overlay
161 13:18:20.362012 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:18:20.362117 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:18:20.362191 Loading test definitions
164 13:18:20.362287 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:18:20.362350 Using /lava-14879051 at stage 0
166 13:18:20.362660 uuid=14879051_1.5.2.3.1 testdef=None
167 13:18:20.362742 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:18:20.362816 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:18:20.363252 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:18:20.363451 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:18:20.364020 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:18:20.364228 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:18:20.364871 runner path: /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/0/tests/0_v4l2-compliance-uvc test_uuid 14879051_1.5.2.3.1
176 13:18:20.365019 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:18:20.365212 Creating lava-test-runner.conf files
179 13:18:20.365268 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14879051/lava-overlay-2hgtz8oo/lava-14879051/0 for stage 0
180 13:18:20.365349 - 0_v4l2-compliance-uvc
181 13:18:20.365439 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:18:20.365516 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:18:20.372052 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:18:20.372154 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:18:20.372234 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:18:20.372313 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:18:20.372389 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:18:21.203963 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 13:18:21.204124 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 13:18:21.204234 extracting modules file /var/lib/lava/dispatcher/tmp/14879051/tftp-deploy-779tez8t/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14879051/extract-overlay-ramdisk-wt6dtcnt/ramdisk
191 13:18:21.500335 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:18:21.500466 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 13:18:21.500551 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14879051/compress-overlay-0s26ad4y/overlay-1.5.2.4.tar.gz to ramdisk
194 13:18:21.500611 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14879051/compress-overlay-0s26ad4y/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14879051/extract-overlay-ramdisk-wt6dtcnt/ramdisk
195 13:18:21.507277 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:18:21.507391 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 13:18:21.507478 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:18:21.507556 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 13:18:21.507623 Building ramdisk /var/lib/lava/dispatcher/tmp/14879051/extract-overlay-ramdisk-wt6dtcnt/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14879051/extract-overlay-ramdisk-wt6dtcnt/ramdisk
200 13:18:22.120565 >> 275512 blocks
201 13:18:26.525593 rename /var/lib/lava/dispatcher/tmp/14879051/extract-overlay-ramdisk-wt6dtcnt/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14879051/tftp-deploy-779tez8t/ramdisk/ramdisk.cpio.gz
202 13:18:26.525798 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 13:18:26.525927 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 13:18:26.526042 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 13:18:26.526164 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14879051/tftp-deploy-779tez8t/kernel/Image']
206 13:18:40.877721 Returned 0 in 14 seconds
207 13:18:40.877904 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14879051/tftp-deploy-779tez8t/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14879051/tftp-deploy-779tez8t/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14879051/tftp-deploy-779tez8t/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14879051/tftp-deploy-779tez8t/kernel/image.itb
208 13:18:41.480932 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:18:41.481041 output: Created: Thu Jul 18 14:18:41 2024
210 13:18:41.481103 output: Image 0 (kernel-1)
211 13:18:41.481161 output: Description:
212 13:18:41.481214 output: Created: Thu Jul 18 14:18:41 2024
213 13:18:41.481266 output: Type: Kernel Image
214 13:18:41.481322 output: Compression: lzma compressed
215 13:18:41.481376 output: Data Size: 13114469 Bytes = 12807.10 KiB = 12.51 MiB
216 13:18:41.481427 output: Architecture: AArch64
217 13:18:41.481476 output: OS: Linux
218 13:18:41.481526 output: Load Address: 0x00000000
219 13:18:41.481575 output: Entry Point: 0x00000000
220 13:18:41.481624 output: Hash algo: crc32
221 13:18:41.481679 output: Hash value: a47b020b
222 13:18:41.481761 output: Image 1 (fdt-1)
223 13:18:41.481838 output: Description: mt8192-asurada-spherion-r0
224 13:18:41.481918 output: Created: Thu Jul 18 14:18:41 2024
225 13:18:41.481994 output: Type: Flat Device Tree
226 13:18:41.482076 output: Compression: uncompressed
227 13:18:41.482169 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 13:18:41.482250 output: Architecture: AArch64
229 13:18:41.482327 output: Hash algo: crc32
230 13:18:41.482411 output: Hash value: 0f8e4d2e
231 13:18:41.482493 output: Image 2 (ramdisk-1)
232 13:18:41.482570 output: Description: unavailable
233 13:18:41.482649 output: Created: Thu Jul 18 14:18:41 2024
234 13:18:41.482727 output: Type: RAMDisk Image
235 13:18:41.482804 output: Compression: uncompressed
236 13:18:41.482880 output: Data Size: 41200682 Bytes = 40235.04 KiB = 39.29 MiB
237 13:18:41.482959 output: Architecture: AArch64
238 13:18:41.483036 output: OS: Linux
239 13:18:41.483111 output: Load Address: unavailable
240 13:18:41.483186 output: Entry Point: unavailable
241 13:18:41.483261 output: Hash algo: crc32
242 13:18:41.483340 output: Hash value: 28cefef2
243 13:18:41.483416 output: Default Configuration: 'conf-1'
244 13:18:41.483494 output: Configuration 0 (conf-1)
245 13:18:41.483570 output: Description: mt8192-asurada-spherion-r0
246 13:18:41.483646 output: Kernel: kernel-1
247 13:18:41.483723 output: Init Ramdisk: ramdisk-1
248 13:18:41.483799 output: FDT: fdt-1
249 13:18:41.483874 output: Loadables: kernel-1
250 13:18:41.483950 output:
251 13:18:41.484073 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 13:18:41.484153 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 13:18:41.484232 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 13:18:41.484313 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 13:18:41.484372 No LXC device requested
256 13:18:41.484442 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:18:41.484569 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 13:18:41.484702 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:18:41.484813 Checking files for TFTP limit of 4294967296 bytes.
260 13:18:41.485364 end: 1 tftp-deploy (duration 00:00:22) [common]
261 13:18:41.485456 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:18:41.485536 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:18:41.485659 substitutions:
264 13:18:41.485747 - {DTB}: 14879051/tftp-deploy-779tez8t/dtb/mt8192-asurada-spherion-r0.dtb
265 13:18:41.485831 - {INITRD}: 14879051/tftp-deploy-779tez8t/ramdisk/ramdisk.cpio.gz
266 13:18:41.485911 - {KERNEL}: 14879051/tftp-deploy-779tez8t/kernel/Image
267 13:18:41.485990 - {LAVA_MAC}: None
268 13:18:41.486071 - {PRESEED_CONFIG}: None
269 13:18:41.486148 - {PRESEED_LOCAL}: None
270 13:18:41.486201 - {RAMDISK}: 14879051/tftp-deploy-779tez8t/ramdisk/ramdisk.cpio.gz
271 13:18:41.486260 - {ROOT_PART}: None
272 13:18:41.486311 - {ROOT}: None
273 13:18:41.486363 - {SERVER_IP}: 192.168.201.1
274 13:18:41.486419 - {TEE}: None
275 13:18:41.486501 Parsed boot commands:
276 13:18:41.486577 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:18:41.486762 Parsed boot commands: tftpboot 192.168.201.1 14879051/tftp-deploy-779tez8t/kernel/image.itb 14879051/tftp-deploy-779tez8t/kernel/cmdline
278 13:18:41.486869 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:18:41.486972 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:18:41.487072 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:18:41.487175 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:18:41.487260 Not connected, no need to disconnect.
283 13:18:41.487355 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:18:41.487452 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:18:41.487534 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 13:18:41.490485 Setting prompt string to ['lava-test: # ']
287 13:18:41.490801 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:18:41.490932 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:18:41.491052 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:18:41.491161 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:18:41.491454 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=reboot']
292 13:18:50.627346 >> Command sent successfully.
293 13:18:50.630753 Returned 0 in 9 seconds
294 13:18:50.630943 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 13:18:50.631280 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 13:18:50.631404 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 13:18:50.631508 Setting prompt string to 'Starting depthcharge on Spherion...'
299 13:18:50.631591 Changing prompt to 'Starting depthcharge on Spherion...'
300 13:18:50.631685 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 13:18:50.632189 [Enter `^Ec?' for help]
302 13:18:52.071539
303 13:18:52.071681
304 13:18:52.071775 F0: 102B 0000
305 13:18:52.071865
306 13:18:52.071958 F3: 1001 0000 [0200]
307 13:18:52.074755
308 13:18:52.074856 F3: 1001 0000
309 13:18:52.074955
310 13:18:52.075053 F7: 102D 0000
311 13:18:52.075139
312 13:18:52.077938 F1: 0000 0000
313 13:18:52.078040
314 13:18:52.078144 V0: 0000 0000 [0001]
315 13:18:52.078234
316 13:18:52.081310 00: 0007 8000
317 13:18:52.081415
318 13:18:52.081500 01: 0000 0000
319 13:18:52.081583
320 13:18:52.084546 BP: 0C00 0209 [0000]
321 13:18:52.084640
322 13:18:52.084731 G0: 1182 0000
323 13:18:52.084819
324 13:18:52.088401 EC: 0000 0021 [4000]
325 13:18:52.088503
326 13:18:52.088587 S7: 0000 0000 [0000]
327 13:18:52.088666
328 13:18:52.091583 CC: 0000 0000 [0001]
329 13:18:52.091678
330 13:18:52.091765 T0: 0000 0040 [010F]
331 13:18:52.091846
332 13:18:52.094764 Jump to BL
333 13:18:52.094870
334 13:18:52.118200
335 13:18:52.118288
336 13:18:52.128547 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 13:18:52.128637 ARM64: Exception handlers installed.
338 13:18:52.132594 ARM64: Testing exception
339 13:18:52.136120 ARM64: Done test exception
340 13:18:52.143455 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 13:18:52.154128 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 13:18:52.161456 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 13:18:52.168811 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 13:18:52.178613 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 13:18:52.185111 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 13:18:52.194961 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 13:18:52.201706 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 13:18:52.221547 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 13:18:52.224426 WDT: Last reset was cold boot
350 13:18:52.227968 SPI1(PAD0) initialized at 2873684 Hz
351 13:18:52.231253 SPI5(PAD0) initialized at 992727 Hz
352 13:18:52.234794 VBOOT: Loading verstage.
353 13:18:52.241724 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 13:18:52.245011 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 13:18:52.248349 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 13:18:52.251650 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 13:18:52.258931 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 13:18:52.265647 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 13:18:52.276210 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 13:18:52.276330
361 13:18:52.276422
362 13:18:52.286493 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 13:18:52.290129 ARM64: Exception handlers installed.
364 13:18:52.293195 ARM64: Testing exception
365 13:18:52.293335 ARM64: Done test exception
366 13:18:52.299870 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 13:18:52.303282 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 13:18:52.317759 Probing TPM: . done!
369 13:18:52.317881 TPM ready after 0 ms
370 13:18:52.324028 Connected to device vid:did:rid of 1ae0:0028:00
371 13:18:52.330755 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 13:18:52.391002 Initialized TPM device CR50 revision 0
373 13:18:52.395524 tlcl_send_startup: Startup return code is 0
374 13:18:52.402588 TPM: setup succeeded
375 13:18:52.417766 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 13:18:52.425032 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 13:18:52.436720 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 13:18:52.446685 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 13:18:52.449946 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 13:18:52.454228 in-header: 03 07 00 00 08 00 00 00
381 13:18:52.457907 in-data: aa e4 47 04 13 02 00 00
382 13:18:52.458008 Chrome EC: UHEPI supported
383 13:18:52.464971 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 13:18:52.469597 in-header: 03 a9 00 00 08 00 00 00
385 13:18:52.473601 in-data: 84 60 60 08 00 00 00 00
386 13:18:52.473698 Phase 1
387 13:18:52.476961 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 13:18:52.484375 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 13:18:52.491662 VB2:vb2_check_recovery() Recovery was requested manually
390 13:18:52.495569 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 13:18:52.498774 Recovery requested (1009000e)
392 13:18:52.508777 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 13:18:52.512675 tlcl_extend: response is 0
394 13:18:52.522313 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 13:18:52.527685 tlcl_extend: response is 0
396 13:18:52.534955 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 13:18:52.555040 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 13:18:52.563062 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 13:18:52.563170
400 13:18:52.563304
401 13:18:52.570048 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 13:18:52.574012 ARM64: Exception handlers installed.
403 13:18:52.577298 ARM64: Testing exception
404 13:18:52.577402 ARM64: Done test exception
405 13:18:52.597114 pmic_efuse_setting: Set efuses in 11 msecs
406 13:18:52.602539 pmwrap_interface_init: Select PMIF_VLD_RDY
407 13:18:52.609650 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 13:18:52.613682 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 13:18:52.616959 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 13:18:52.624592 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 13:18:52.628249 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 13:18:52.631891 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 13:18:52.639034 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 13:18:52.642292 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 13:18:52.645560 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 13:18:52.652662 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 13:18:52.655856 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 13:18:52.662162 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 13:18:52.665880 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 13:18:52.672500 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 13:18:52.679298 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 13:18:52.682437 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 13:18:52.689244 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 13:18:52.695880 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 13:18:52.699148 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 13:18:52.705747 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 13:18:52.713515 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 13:18:52.717265 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 13:18:52.723951 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 13:18:52.727186 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 13:18:52.734705 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 13:18:52.738267 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 13:18:52.744696 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 13:18:52.748191 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 13:18:52.754641 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 13:18:52.757847 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 13:18:52.765000 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 13:18:52.768241 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 13:18:52.775434 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 13:18:52.778725 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 13:18:52.782233 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 13:18:52.788719 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 13:18:52.795206 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 13:18:52.798871 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 13:18:52.802089 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 13:18:52.808832 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 13:18:52.812133 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 13:18:52.815473 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 13:18:52.821872 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 13:18:52.825191 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 13:18:52.828476 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 13:18:52.835638 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 13:18:52.838933 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 13:18:52.842283 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 13:18:52.845515 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 13:18:52.851763 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 13:18:52.855339 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 13:18:52.862251 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 13:18:52.872245 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 13:18:52.875476 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 13:18:52.885357 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 13:18:52.891739 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 13:18:52.898576 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 13:18:52.901703 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:18:52.905398 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 13:18:52.912452 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 13:18:52.919055 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 13:18:52.922844 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 13:18:52.926126 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 13:18:52.937537 [RTC]rtc_get_frequency_meter,154: input=15, output=794
471 13:18:52.940898 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 13:18:52.947492 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 13:18:52.950184 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 13:18:52.953445 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 13:18:52.956861 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 13:18:52.960615 ADC[4]: Raw value=898890 ID=7
477 13:18:52.963749 ADC[3]: Raw value=213810 ID=1
478 13:18:52.963848 RAM Code: 0x71
479 13:18:52.970694 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 13:18:52.973609 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 13:18:52.983699 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 13:18:52.990843 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 13:18:52.993998 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 13:18:52.997037 in-header: 03 07 00 00 08 00 00 00
485 13:18:53.000525 in-data: aa e4 47 04 13 02 00 00
486 13:18:53.003618 Chrome EC: UHEPI supported
487 13:18:53.010313 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 13:18:53.013886 in-header: 03 a9 00 00 08 00 00 00
489 13:18:53.017051 in-data: 84 60 60 08 00 00 00 00
490 13:18:53.020705 MRC: failed to locate region type 0.
491 13:18:53.027035 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 13:18:53.027136 DRAM-K: Running full calibration
493 13:18:53.034074 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 13:18:53.037542 header.status = 0x0
495 13:18:53.040822 header.version = 0x6 (expected: 0x6)
496 13:18:53.044166 header.size = 0xd00 (expected: 0xd00)
497 13:18:53.044263 header.flags = 0x0
498 13:18:53.050341 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 13:18:53.068914 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
500 13:18:53.075417 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 13:18:53.078910 dram_init: ddr_geometry: 2
502 13:18:53.082397 [EMI] MDL number = 2
503 13:18:53.082500 [EMI] Get MDL freq = 0
504 13:18:53.085505 dram_init: ddr_type: 0
505 13:18:53.085602 is_discrete_lpddr4: 1
506 13:18:53.089311 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 13:18:53.089410
508 13:18:53.089495
509 13:18:53.092327 [Bian_co] ETT version 0.0.0.1
510 13:18:53.099423 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 13:18:53.099525
512 13:18:53.102612 dramc_set_vcore_voltage set vcore to 650000
513 13:18:53.102709 Read voltage for 800, 4
514 13:18:53.105757 Vio18 = 0
515 13:18:53.105853 Vcore = 650000
516 13:18:53.105944 Vdram = 0
517 13:18:53.109467 Vddq = 0
518 13:18:53.109561 Vmddr = 0
519 13:18:53.112640 dram_init: config_dvfs: 1
520 13:18:53.115780 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 13:18:53.122467 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 13:18:53.125588 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 13:18:53.129370 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 13:18:53.132496 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 13:18:53.135994 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 13:18:53.139265 MEM_TYPE=3, freq_sel=18
527 13:18:53.142540 sv_algorithm_assistance_LP4_1600
528 13:18:53.145857 ============ PULL DRAM RESETB DOWN ============
529 13:18:53.149238 ========== PULL DRAM RESETB DOWN end =========
530 13:18:53.155836 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 13:18:53.159022 ===================================
532 13:18:53.159107 LPDDR4 DRAM CONFIGURATION
533 13:18:53.162431 ===================================
534 13:18:53.165816 EX_ROW_EN[0] = 0x0
535 13:18:53.169147 EX_ROW_EN[1] = 0x0
536 13:18:53.169252 LP4Y_EN = 0x0
537 13:18:53.172531 WORK_FSP = 0x0
538 13:18:53.172634 WL = 0x2
539 13:18:53.175730 RL = 0x2
540 13:18:53.175819 BL = 0x2
541 13:18:53.179033 RPST = 0x0
542 13:18:53.179114 RD_PRE = 0x0
543 13:18:53.182228 WR_PRE = 0x1
544 13:18:53.182310 WR_PST = 0x0
545 13:18:53.185886 DBI_WR = 0x0
546 13:18:53.185999 DBI_RD = 0x0
547 13:18:53.189009 OTF = 0x1
548 13:18:53.192703 ===================================
549 13:18:53.195942 ===================================
550 13:18:53.196051 ANA top config
551 13:18:53.199128 ===================================
552 13:18:53.202736 DLL_ASYNC_EN = 0
553 13:18:53.205877 ALL_SLAVE_EN = 1
554 13:18:53.209091 NEW_RANK_MODE = 1
555 13:18:53.209177 DLL_IDLE_MODE = 1
556 13:18:53.212776 LP45_APHY_COMB_EN = 1
557 13:18:53.216086 TX_ODT_DIS = 1
558 13:18:53.219556 NEW_8X_MODE = 1
559 13:18:53.222660 ===================================
560 13:18:53.225725 ===================================
561 13:18:53.225824 data_rate = 1600
562 13:18:53.229389 CKR = 1
563 13:18:53.232619 DQ_P2S_RATIO = 8
564 13:18:53.235832 ===================================
565 13:18:53.239552 CA_P2S_RATIO = 8
566 13:18:53.242601 DQ_CA_OPEN = 0
567 13:18:53.245783 DQ_SEMI_OPEN = 0
568 13:18:53.245882 CA_SEMI_OPEN = 0
569 13:18:53.249141 CA_FULL_RATE = 0
570 13:18:53.252428 DQ_CKDIV4_EN = 1
571 13:18:53.255700 CA_CKDIV4_EN = 1
572 13:18:53.259058 CA_PREDIV_EN = 0
573 13:18:53.262351 PH8_DLY = 0
574 13:18:53.262447 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 13:18:53.266277 DQ_AAMCK_DIV = 4
576 13:18:53.269574 CA_AAMCK_DIV = 4
577 13:18:53.272960 CA_ADMCK_DIV = 4
578 13:18:53.276214 DQ_TRACK_CA_EN = 0
579 13:18:53.279471 CA_PICK = 800
580 13:18:53.279558 CA_MCKIO = 800
581 13:18:53.282764 MCKIO_SEMI = 0
582 13:18:53.286076 PLL_FREQ = 3068
583 13:18:53.289284 DQ_UI_PI_RATIO = 32
584 13:18:53.292836 CA_UI_PI_RATIO = 0
585 13:18:53.296327 ===================================
586 13:18:53.299366 ===================================
587 13:18:53.302583 memory_type:LPDDR4
588 13:18:53.302681 GP_NUM : 10
589 13:18:53.305742 SRAM_EN : 1
590 13:18:53.305831 MD32_EN : 0
591 13:18:53.309694 ===================================
592 13:18:53.312607 [ANA_INIT] >>>>>>>>>>>>>>
593 13:18:53.316190 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 13:18:53.319241 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 13:18:53.322856 ===================================
596 13:18:53.326252 data_rate = 1600,PCW = 0X7600
597 13:18:53.329526 ===================================
598 13:18:53.332640 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 13:18:53.335643 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 13:18:53.342846 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 13:18:53.346045 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 13:18:53.349160 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 13:18:53.356217 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 13:18:53.356320 [ANA_INIT] flow start
605 13:18:53.359445 [ANA_INIT] PLL >>>>>>>>
606 13:18:53.359543 [ANA_INIT] PLL <<<<<<<<
607 13:18:53.362737 [ANA_INIT] MIDPI >>>>>>>>
608 13:18:53.366088 [ANA_INIT] MIDPI <<<<<<<<
609 13:18:53.366192 [ANA_INIT] DLL >>>>>>>>
610 13:18:53.370188 [ANA_INIT] flow end
611 13:18:53.373460 ============ LP4 DIFF to SE enter ============
612 13:18:53.377462 ============ LP4 DIFF to SE exit ============
613 13:18:53.381264 [ANA_INIT] <<<<<<<<<<<<<
614 13:18:53.384531 [Flow] Enable top DCM control >>>>>
615 13:18:53.388494 [Flow] Enable top DCM control <<<<<
616 13:18:53.388588 Enable DLL master slave shuffle
617 13:18:53.395821 ==============================================================
618 13:18:53.395928 Gating Mode config
619 13:18:53.403508 ==============================================================
620 13:18:53.403610 Config description:
621 13:18:53.413551 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 13:18:53.420090 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 13:18:53.427125 SELPH_MODE 0: By rank 1: By Phase
624 13:18:53.430086 ==============================================================
625 13:18:53.433431 GAT_TRACK_EN = 1
626 13:18:53.436726 RX_GATING_MODE = 2
627 13:18:53.439979 RX_GATING_TRACK_MODE = 2
628 13:18:53.443791 SELPH_MODE = 1
629 13:18:53.446900 PICG_EARLY_EN = 1
630 13:18:53.450529 VALID_LAT_VALUE = 1
631 13:18:53.453575 ==============================================================
632 13:18:53.457043 Enter into Gating configuration >>>>
633 13:18:53.459947 Exit from Gating configuration <<<<
634 13:18:53.463804 Enter into DVFS_PRE_config >>>>>
635 13:18:53.476908 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 13:18:53.480237 Exit from DVFS_PRE_config <<<<<
637 13:18:53.483503 Enter into PICG configuration >>>>
638 13:18:53.486722 Exit from PICG configuration <<<<
639 13:18:53.486799 [RX_INPUT] configuration >>>>>
640 13:18:53.490053 [RX_INPUT] configuration <<<<<
641 13:18:53.496709 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 13:18:53.499926 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 13:18:53.506569 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 13:18:53.513533 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 13:18:53.520187 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 13:18:53.526439 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 13:18:53.529730 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 13:18:53.533016 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 13:18:53.540098 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 13:18:53.543096 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 13:18:53.546668 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 13:18:53.549733 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 13:18:53.553037 ===================================
654 13:18:53.556221 LPDDR4 DRAM CONFIGURATION
655 13:18:53.559499 ===================================
656 13:18:53.562937 EX_ROW_EN[0] = 0x0
657 13:18:53.563014 EX_ROW_EN[1] = 0x0
658 13:18:53.565987 LP4Y_EN = 0x0
659 13:18:53.566092 WORK_FSP = 0x0
660 13:18:53.569563 WL = 0x2
661 13:18:53.569658 RL = 0x2
662 13:18:53.572814 BL = 0x2
663 13:18:53.572906 RPST = 0x0
664 13:18:53.576031 RD_PRE = 0x0
665 13:18:53.576126 WR_PRE = 0x1
666 13:18:53.579277 WR_PST = 0x0
667 13:18:53.582602 DBI_WR = 0x0
668 13:18:53.582673 DBI_RD = 0x0
669 13:18:53.585878 OTF = 0x1
670 13:18:53.589100 ===================================
671 13:18:53.592450 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 13:18:53.595776 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 13:18:53.599108 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 13:18:53.603072 ===================================
675 13:18:53.606235 LPDDR4 DRAM CONFIGURATION
676 13:18:53.609519 ===================================
677 13:18:53.612235 EX_ROW_EN[0] = 0x10
678 13:18:53.612327 EX_ROW_EN[1] = 0x0
679 13:18:53.615618 LP4Y_EN = 0x0
680 13:18:53.615709 WORK_FSP = 0x0
681 13:18:53.619524 WL = 0x2
682 13:18:53.619620 RL = 0x2
683 13:18:53.622629 BL = 0x2
684 13:18:53.622723 RPST = 0x0
685 13:18:53.625907 RD_PRE = 0x0
686 13:18:53.625998 WR_PRE = 0x1
687 13:18:53.628999 WR_PST = 0x0
688 13:18:53.629093 DBI_WR = 0x0
689 13:18:53.632632 DBI_RD = 0x0
690 13:18:53.632734 OTF = 0x1
691 13:18:53.635625 ===================================
692 13:18:53.642827 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 13:18:53.647329 nWR fixed to 40
694 13:18:53.650426 [ModeRegInit_LP4] CH0 RK0
695 13:18:53.650524 [ModeRegInit_LP4] CH0 RK1
696 13:18:53.654244 [ModeRegInit_LP4] CH1 RK0
697 13:18:53.657237 [ModeRegInit_LP4] CH1 RK1
698 13:18:53.657305 match AC timing 13
699 13:18:53.663810 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 13:18:53.667497 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 13:18:53.670493 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 13:18:53.677523 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 13:18:53.680555 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 13:18:53.680656 [EMI DOE] emi_dcm 0
705 13:18:53.687401 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 13:18:53.687494 ==
707 13:18:53.690741 Dram Type= 6, Freq= 0, CH_0, rank 0
708 13:18:53.694025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 13:18:53.694128 ==
710 13:18:53.700663 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 13:18:53.707181 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 13:18:53.715133 [CA 0] Center 38 (7~69) winsize 63
713 13:18:53.718471 [CA 1] Center 37 (7~68) winsize 62
714 13:18:53.721723 [CA 2] Center 35 (5~66) winsize 62
715 13:18:53.725119 [CA 3] Center 35 (5~66) winsize 62
716 13:18:53.728225 [CA 4] Center 34 (4~65) winsize 62
717 13:18:53.731573 [CA 5] Center 34 (4~65) winsize 62
718 13:18:53.731663
719 13:18:53.734837 [CmdBusTrainingLP45] Vref(ca) range 1: 34
720 13:18:53.734930
721 13:18:53.737938 [CATrainingPosCal] consider 1 rank data
722 13:18:53.753104 u2DelayCellTimex100 = 270/100 ps
723 13:18:53.753278 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 13:18:53.753388 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 13:18:53.755117 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 13:18:53.758395 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 13:18:53.762350 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 13:18:53.765428 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
729 13:18:53.765537
730 13:18:53.768796 CA PerBit enable=1, Macro0, CA PI delay=34
731 13:18:53.768936
732 13:18:53.772436 [CBTSetCACLKResult] CA Dly = 34
733 13:18:53.772539 CS Dly: 6 (0~37)
734 13:18:53.772629 ==
735 13:18:53.775505 Dram Type= 6, Freq= 0, CH_0, rank 1
736 13:18:53.779148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 13:18:53.782183 ==
738 13:18:53.785773 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 13:18:53.792163 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 13:18:53.801506 [CA 0] Center 38 (7~69) winsize 63
741 13:18:53.804720 [CA 1] Center 38 (7~69) winsize 63
742 13:18:53.808054 [CA 2] Center 35 (5~66) winsize 62
743 13:18:53.811363 [CA 3] Center 35 (5~66) winsize 62
744 13:18:53.814664 [CA 4] Center 34 (4~65) winsize 62
745 13:18:53.817935 [CA 5] Center 34 (4~65) winsize 62
746 13:18:53.818037
747 13:18:53.821238 [CmdBusTrainingLP45] Vref(ca) range 1: 32
748 13:18:53.821331
749 13:18:53.824479 [CATrainingPosCal] consider 2 rank data
750 13:18:53.827776 u2DelayCellTimex100 = 270/100 ps
751 13:18:53.831119 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 13:18:53.834909 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 13:18:53.841464 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 13:18:53.844701 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 13:18:53.847809 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 13:18:53.851515 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
757 13:18:53.851608
758 13:18:53.854593 CA PerBit enable=1, Macro0, CA PI delay=34
759 13:18:53.854686
760 13:18:53.858248 [CBTSetCACLKResult] CA Dly = 34
761 13:18:53.858325 CS Dly: 6 (0~37)
762 13:18:53.858404
763 13:18:53.861320 ----->DramcWriteLeveling(PI) begin...
764 13:18:53.861401 ==
765 13:18:53.864618 Dram Type= 6, Freq= 0, CH_0, rank 0
766 13:18:53.871341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 13:18:53.871425 ==
768 13:18:53.874529 Write leveling (Byte 0): 30 => 30
769 13:18:53.878048 Write leveling (Byte 1): 29 => 29
770 13:18:53.878155 DramcWriteLeveling(PI) end<-----
771 13:18:53.881251
772 13:18:53.881326 ==
773 13:18:53.884476 Dram Type= 6, Freq= 0, CH_0, rank 0
774 13:18:53.888273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 13:18:53.888368 ==
776 13:18:53.891416 [Gating] SW mode calibration
777 13:18:53.898190 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 13:18:53.901267 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 13:18:53.907660 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 13:18:53.911157 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
781 13:18:53.914377 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
782 13:18:53.921088 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
783 13:18:53.924970 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 13:18:53.928326 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 13:18:53.934769 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 13:18:53.938032 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 13:18:53.941349 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 13:18:53.944633 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 13:18:53.951846 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:18:53.955286 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:18:53.958399 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:18:53.965298 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:18:53.968343 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:18:53.972142 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:18:53.978740 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:18:53.981825 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
797 13:18:53.985639 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
798 13:18:53.991765 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
799 13:18:53.995546 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:18:53.998635 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:18:54.005019 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:18:54.008170 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:18:54.011870 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 13:18:54.018520 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 13:18:54.021530 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:18:54.024764 0 9 12 | B1->B0 | 2424 3131 | 1 1 | (1 1) (1 1)
807 13:18:54.028752 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 13:18:54.035322 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 13:18:54.038596 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 13:18:54.041830 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 13:18:54.048518 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 13:18:54.051723 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 13:18:54.055062 0 10 8 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
814 13:18:54.061659 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
815 13:18:54.064822 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 13:18:54.068115 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 13:18:54.075076 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 13:18:54.078109 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 13:18:54.082031 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 13:18:54.088101 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 13:18:54.091792 0 11 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
822 13:18:54.095476 0 11 12 | B1->B0 | 3030 4646 | 0 0 | (1 1) (0 0)
823 13:18:54.101371 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 13:18:54.105064 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 13:18:54.108213 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 13:18:54.114855 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 13:18:54.118117 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 13:18:54.121881 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 13:18:54.125012 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
830 13:18:54.131618 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 13:18:54.135187 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 13:18:54.138256 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 13:18:54.145452 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 13:18:54.148674 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 13:18:54.152035 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 13:18:54.158546 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 13:18:54.161732 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 13:18:54.164937 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:18:54.171526 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:18:54.174790 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:18:54.178085 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:18:54.185030 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:18:54.188301 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:18:54.191542 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:18:54.198560 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
846 13:18:54.198645 Total UI for P1: 0, mck2ui 16
847 13:18:54.204817 best dqsien dly found for B0: ( 0, 14, 6)
848 13:18:54.208488 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
849 13:18:54.211617 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 13:18:54.215311 Total UI for P1: 0, mck2ui 16
851 13:18:54.218561 best dqsien dly found for B1: ( 0, 14, 10)
852 13:18:54.221738 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
853 13:18:54.225055 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
854 13:18:54.225149
855 13:18:54.228375 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
856 13:18:54.234613 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
857 13:18:54.234714 [Gating] SW calibration Done
858 13:18:54.234802 ==
859 13:18:54.238397 Dram Type= 6, Freq= 0, CH_0, rank 0
860 13:18:54.244756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 13:18:54.244887 ==
862 13:18:54.244996 RX Vref Scan: 0
863 13:18:54.245103
864 13:18:54.248029 RX Vref 0 -> 0, step: 1
865 13:18:54.248149
866 13:18:54.251827 RX Delay -130 -> 252, step: 16
867 13:18:54.255174 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
868 13:18:54.258430 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
869 13:18:54.261746 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
870 13:18:54.268306 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
871 13:18:54.271570 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
872 13:18:54.274741 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
873 13:18:54.278459 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 13:18:54.281731 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 13:18:54.288354 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
876 13:18:54.291541 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
877 13:18:54.295238 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 13:18:54.298568 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 13:18:54.301822 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 13:18:54.308162 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 13:18:54.311426 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
882 13:18:54.314682 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 13:18:54.314774 ==
884 13:18:54.318400 Dram Type= 6, Freq= 0, CH_0, rank 0
885 13:18:54.321459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 13:18:54.321554 ==
887 13:18:54.325266 DQS Delay:
888 13:18:54.325355 DQS0 = 0, DQS1 = 0
889 13:18:54.325437 DQM Delay:
890 13:18:54.328448 DQM0 = 83, DQM1 = 69
891 13:18:54.328540 DQ Delay:
892 13:18:54.331714 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
893 13:18:54.334973 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
894 13:18:54.338080 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
895 13:18:54.341874 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
896 13:18:54.341999
897 13:18:54.342119
898 13:18:54.342232 ==
899 13:18:54.344951 Dram Type= 6, Freq= 0, CH_0, rank 0
900 13:18:54.351787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 13:18:54.351901 ==
902 13:18:54.351992
903 13:18:54.352073
904 13:18:54.352155 TX Vref Scan disable
905 13:18:54.355685 == TX Byte 0 ==
906 13:18:54.358401 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
907 13:18:54.365118 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
908 13:18:54.365213 == TX Byte 1 ==
909 13:18:54.379600 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
910 13:18:54.379893 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
911 13:18:54.380011 ==
912 13:18:54.380122 Dram Type= 6, Freq= 0, CH_0, rank 0
913 13:18:54.381954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 13:18:54.382075 ==
915 13:18:54.394544 TX Vref=22, minBit 11, minWin=26, winSum=433
916 13:18:54.397499 TX Vref=24, minBit 11, minWin=26, winSum=434
917 13:18:54.401150 TX Vref=26, minBit 1, minWin=27, winSum=440
918 13:18:54.404329 TX Vref=28, minBit 1, minWin=27, winSum=445
919 13:18:54.407672 TX Vref=30, minBit 1, minWin=27, winSum=444
920 13:18:54.414089 TX Vref=32, minBit 1, minWin=27, winSum=441
921 13:18:54.417466 [TxChooseVref] Worse bit 1, Min win 27, Win sum 445, Final Vref 28
922 13:18:54.417565
923 13:18:54.420789 Final TX Range 1 Vref 28
924 13:18:54.420917
925 13:18:54.421032 ==
926 13:18:54.424526 Dram Type= 6, Freq= 0, CH_0, rank 0
927 13:18:54.427747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 13:18:54.427852 ==
929 13:18:54.430977
930 13:18:54.431071
931 13:18:54.431167 TX Vref Scan disable
932 13:18:54.434788 == TX Byte 0 ==
933 13:18:54.437494 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
934 13:18:54.441264 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
935 13:18:54.444403 == TX Byte 1 ==
936 13:18:54.447406 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
937 13:18:54.454412 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
938 13:18:54.454499
939 13:18:54.454585 [DATLAT]
940 13:18:54.454671 Freq=800, CH0 RK0
941 13:18:54.454755
942 13:18:54.457323 DATLAT Default: 0xa
943 13:18:54.457387 0, 0xFFFF, sum = 0
944 13:18:54.461237 1, 0xFFFF, sum = 0
945 13:18:54.461314 2, 0xFFFF, sum = 0
946 13:18:54.464485 3, 0xFFFF, sum = 0
947 13:18:54.464627 4, 0xFFFF, sum = 0
948 13:18:54.467789 5, 0xFFFF, sum = 0
949 13:18:54.471232 6, 0xFFFF, sum = 0
950 13:18:54.471341 7, 0xFFFF, sum = 0
951 13:18:54.474388 8, 0xFFFF, sum = 0
952 13:18:54.474491 9, 0x0, sum = 1
953 13:18:54.474579 10, 0x0, sum = 2
954 13:18:54.477626 11, 0x0, sum = 3
955 13:18:54.477703 12, 0x0, sum = 4
956 13:18:54.480995 best_step = 10
957 13:18:54.481071
958 13:18:54.481130 ==
959 13:18:54.484171 Dram Type= 6, Freq= 0, CH_0, rank 0
960 13:18:54.487491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 13:18:54.487569 ==
962 13:18:54.490793 RX Vref Scan: 1
963 13:18:54.490894
964 13:18:54.490990 Set Vref Range= 32 -> 127
965 13:18:54.494081
966 13:18:54.494184 RX Vref 32 -> 127, step: 1
967 13:18:54.494280
968 13:18:54.497381 RX Delay -111 -> 252, step: 8
969 13:18:54.497478
970 13:18:54.500625 Set Vref, RX VrefLevel [Byte0]: 32
971 13:18:54.504558 [Byte1]: 32
972 13:18:54.504655
973 13:18:54.507610 Set Vref, RX VrefLevel [Byte0]: 33
974 13:18:54.510598 [Byte1]: 33
975 13:18:54.514903
976 13:18:54.515028 Set Vref, RX VrefLevel [Byte0]: 34
977 13:18:54.518125 [Byte1]: 34
978 13:18:54.522834
979 13:18:54.522933 Set Vref, RX VrefLevel [Byte0]: 35
980 13:18:54.526118 [Byte1]: 35
981 13:18:54.530174
982 13:18:54.530274 Set Vref, RX VrefLevel [Byte0]: 36
983 13:18:54.533932 [Byte1]: 36
984 13:18:54.537622
985 13:18:54.537726 Set Vref, RX VrefLevel [Byte0]: 37
986 13:18:54.541412 [Byte1]: 37
987 13:18:54.545885
988 13:18:54.545986 Set Vref, RX VrefLevel [Byte0]: 38
989 13:18:54.548995 [Byte1]: 38
990 13:18:54.553324
991 13:18:54.553428 Set Vref, RX VrefLevel [Byte0]: 39
992 13:18:54.556494 [Byte1]: 39
993 13:18:54.560987
994 13:18:54.561130 Set Vref, RX VrefLevel [Byte0]: 40
995 13:18:54.563798 [Byte1]: 40
996 13:18:54.568452
997 13:18:54.568553 Set Vref, RX VrefLevel [Byte0]: 41
998 13:18:54.572014 [Byte1]: 41
999 13:18:54.575851
1000 13:18:54.575957 Set Vref, RX VrefLevel [Byte0]: 42
1001 13:18:54.579222 [Byte1]: 42
1002 13:18:54.583884
1003 13:18:54.583982 Set Vref, RX VrefLevel [Byte0]: 43
1004 13:18:54.587273 [Byte1]: 43
1005 13:18:54.591134
1006 13:18:54.591234 Set Vref, RX VrefLevel [Byte0]: 44
1007 13:18:54.594352 [Byte1]: 44
1008 13:18:54.598952
1009 13:18:54.599077 Set Vref, RX VrefLevel [Byte0]: 45
1010 13:18:54.602238 [Byte1]: 45
1011 13:18:54.606946
1012 13:18:54.607049 Set Vref, RX VrefLevel [Byte0]: 46
1013 13:18:54.610191 [Byte1]: 46
1014 13:18:54.614014
1015 13:18:54.614119 Set Vref, RX VrefLevel [Byte0]: 47
1016 13:18:54.617811 [Byte1]: 47
1017 13:18:54.621946
1018 13:18:54.622053 Set Vref, RX VrefLevel [Byte0]: 48
1019 13:18:54.625025 [Byte1]: 48
1020 13:18:54.629518
1021 13:18:54.629631 Set Vref, RX VrefLevel [Byte0]: 49
1022 13:18:54.632785 [Byte1]: 49
1023 13:18:54.637490
1024 13:18:54.637588 Set Vref, RX VrefLevel [Byte0]: 50
1025 13:18:54.640409 [Byte1]: 50
1026 13:18:54.652909
1027 13:18:54.653027 Set Vref, RX VrefLevel [Byte0]: 51
1028 13:18:54.653312 [Byte1]: 51
1029 13:18:54.653424
1030 13:18:54.653530 Set Vref, RX VrefLevel [Byte0]: 52
1031 13:18:54.655554 [Byte1]: 52
1032 13:18:54.660453
1033 13:18:54.660562 Set Vref, RX VrefLevel [Byte0]: 53
1034 13:18:54.663660 [Byte1]: 53
1035 13:18:54.667669
1036 13:18:54.667776 Set Vref, RX VrefLevel [Byte0]: 54
1037 13:18:54.670966 [Byte1]: 54
1038 13:18:54.675459
1039 13:18:54.675531 Set Vref, RX VrefLevel [Byte0]: 55
1040 13:18:54.678479 [Byte1]: 55
1041 13:18:54.683317
1042 13:18:54.683410 Set Vref, RX VrefLevel [Byte0]: 56
1043 13:18:54.686552 [Byte1]: 56
1044 13:18:54.690507
1045 13:18:54.690607 Set Vref, RX VrefLevel [Byte0]: 57
1046 13:18:54.693701 [Byte1]: 57
1047 13:18:54.698293
1048 13:18:54.698369 Set Vref, RX VrefLevel [Byte0]: 58
1049 13:18:54.701589 [Byte1]: 58
1050 13:18:54.706309
1051 13:18:54.706388 Set Vref, RX VrefLevel [Byte0]: 59
1052 13:18:54.708927 [Byte1]: 59
1053 13:18:54.713496
1054 13:18:54.713569 Set Vref, RX VrefLevel [Byte0]: 60
1055 13:18:54.716711 [Byte1]: 60
1056 13:18:54.721437
1057 13:18:54.721534 Set Vref, RX VrefLevel [Byte0]: 61
1058 13:18:54.724734 [Byte1]: 61
1059 13:18:54.729070
1060 13:18:54.729167 Set Vref, RX VrefLevel [Byte0]: 62
1061 13:18:54.732026 [Byte1]: 62
1062 13:18:54.736227
1063 13:18:54.736323 Set Vref, RX VrefLevel [Byte0]: 63
1064 13:18:54.739855 [Byte1]: 63
1065 13:18:54.744332
1066 13:18:54.744414 Set Vref, RX VrefLevel [Byte0]: 64
1067 13:18:54.747497 [Byte1]: 64
1068 13:18:54.752063
1069 13:18:54.752154 Set Vref, RX VrefLevel [Byte0]: 65
1070 13:18:54.755147 [Byte1]: 65
1071 13:18:54.759760
1072 13:18:54.759839 Set Vref, RX VrefLevel [Byte0]: 66
1073 13:18:54.763044 [Byte1]: 66
1074 13:18:54.767365
1075 13:18:54.767442 Set Vref, RX VrefLevel [Byte0]: 67
1076 13:18:54.770744 [Byte1]: 67
1077 13:18:54.774622
1078 13:18:54.774695 Set Vref, RX VrefLevel [Byte0]: 68
1079 13:18:54.777839 [Byte1]: 68
1080 13:18:54.782594
1081 13:18:54.782672 Set Vref, RX VrefLevel [Byte0]: 69
1082 13:18:54.785803 [Byte1]: 69
1083 13:18:54.790148
1084 13:18:54.790230 Set Vref, RX VrefLevel [Byte0]: 70
1085 13:18:54.793126 [Byte1]: 70
1086 13:18:54.797559
1087 13:18:54.797668 Set Vref, RX VrefLevel [Byte0]: 71
1088 13:18:54.800803 [Byte1]: 71
1089 13:18:54.805379
1090 13:18:54.805461 Set Vref, RX VrefLevel [Byte0]: 72
1091 13:18:54.808675 [Byte1]: 72
1092 13:18:54.813218
1093 13:18:54.813318 Set Vref, RX VrefLevel [Byte0]: 73
1094 13:18:54.816474 [Byte1]: 73
1095 13:18:54.820407
1096 13:18:54.820511 Set Vref, RX VrefLevel [Byte0]: 74
1097 13:18:54.823688 [Byte1]: 74
1098 13:18:54.828266
1099 13:18:54.828343 Set Vref, RX VrefLevel [Byte0]: 75
1100 13:18:54.831586 [Byte1]: 75
1101 13:18:54.836060
1102 13:18:54.836150 Set Vref, RX VrefLevel [Byte0]: 76
1103 13:18:54.839186 [Byte1]: 76
1104 13:18:54.843565
1105 13:18:54.843642 Set Vref, RX VrefLevel [Byte0]: 77
1106 13:18:54.846540 [Byte1]: 77
1107 13:18:54.851375
1108 13:18:54.851449 Set Vref, RX VrefLevel [Byte0]: 78
1109 13:18:54.854494 [Byte1]: 78
1110 13:18:54.858755
1111 13:18:54.858828 Set Vref, RX VrefLevel [Byte0]: 79
1112 13:18:54.862403 [Byte1]: 79
1113 13:18:54.866165
1114 13:18:54.866250 Final RX Vref Byte 0 = 56 to rank0
1115 13:18:54.869909 Final RX Vref Byte 1 = 62 to rank0
1116 13:18:54.872950 Final RX Vref Byte 0 = 56 to rank1
1117 13:18:54.876763 Final RX Vref Byte 1 = 62 to rank1==
1118 13:18:54.880119 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 13:18:54.886685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 13:18:54.886798 ==
1121 13:18:54.886861 DQS Delay:
1122 13:18:54.886919 DQS0 = 0, DQS1 = 0
1123 13:18:54.889948 DQM Delay:
1124 13:18:54.890050 DQM0 = 82, DQM1 = 68
1125 13:18:54.893018 DQ Delay:
1126 13:18:54.896268 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1127 13:18:54.896354 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1128 13:18:54.899969 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1129 13:18:54.903118 DQ12 =76, DQ13 =72, DQ14 =80, DQ15 =76
1130 13:18:54.906300
1131 13:18:54.906374
1132 13:18:54.913567 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d2b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
1133 13:18:54.916268 CH0 RK0: MR19=606, MR18=2D2B
1134 13:18:54.923523 CH0_RK0: MR19=0x606, MR18=0x2D2B, DQSOSC=398, MR23=63, INC=93, DEC=62
1135 13:18:54.923635
1136 13:18:54.926972 ----->DramcWriteLeveling(PI) begin...
1137 13:18:54.927046 ==
1138 13:18:54.930279 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 13:18:54.933544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 13:18:54.933641 ==
1141 13:18:54.936736 Write leveling (Byte 0): 31 => 31
1142 13:18:54.940071 Write leveling (Byte 1): 31 => 31
1143 13:18:54.943340 DramcWriteLeveling(PI) end<-----
1144 13:18:54.943410
1145 13:18:54.943469 ==
1146 13:18:54.946661 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 13:18:54.949982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 13:18:54.950083 ==
1149 13:18:54.953257 [Gating] SW mode calibration
1150 13:18:54.960170 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 13:18:54.966586 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 13:18:54.969751 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 13:18:54.973213 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1154 13:18:54.979959 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1155 13:18:54.983094 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 13:18:54.986474 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 13:18:55.034001 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 13:18:55.034094 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 13:18:55.034169 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 13:18:55.034415 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 13:18:55.034519 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 13:18:55.034614 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:18:55.034695 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 13:18:55.034801 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 13:18:55.034895 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 13:18:55.035003 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 13:18:55.038606 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 13:18:55.041819 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 13:18:55.045195 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1170 13:18:55.048489 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1171 13:18:55.054998 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1172 13:18:55.058330 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 13:18:55.061611 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 13:18:55.064764 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 13:18:55.071483 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 13:18:55.074846 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 13:18:55.078026 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 13:18:55.085030 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1179 13:18:55.088284 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1180 13:18:55.091460 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 13:18:55.098152 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 13:18:55.101532 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 13:18:55.105001 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 13:18:55.111645 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 13:18:55.114739 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
1186 13:18:55.118182 0 10 8 | B1->B0 | 3232 2828 | 0 0 | (0 1) (1 0)
1187 13:18:55.124589 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 13:18:55.128570 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 13:18:55.131814 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 13:18:55.138276 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 13:18:55.141696 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 13:18:55.145152 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 13:18:55.151777 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1194 13:18:55.154972 0 11 8 | B1->B0 | 2d2d 4343 | 0 0 | (0 0) (0 0)
1195 13:18:55.158105 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1196 13:18:55.164579 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 13:18:55.168423 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 13:18:55.171554 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 13:18:55.174963 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 13:18:55.181563 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 13:18:55.184831 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 13:18:55.188129 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1203 13:18:55.194952 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 13:18:55.198338 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 13:18:55.201677 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 13:18:55.208015 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:18:55.211588 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 13:18:55.214653 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 13:18:55.221826 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 13:18:55.224647 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 13:18:55.228104 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 13:18:55.235024 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 13:18:55.237988 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 13:18:55.241923 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 13:18:55.248471 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 13:18:55.251763 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 13:18:55.255074 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 13:18:55.258361 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1219 13:18:55.261588 Total UI for P1: 0, mck2ui 16
1220 13:18:55.264774 best dqsien dly found for B0: ( 0, 14, 6)
1221 13:18:55.271361 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1222 13:18:55.275183 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 13:18:55.278269 Total UI for P1: 0, mck2ui 16
1224 13:18:55.281500 best dqsien dly found for B1: ( 0, 14, 10)
1225 13:18:55.284729 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1226 13:18:55.288111 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1227 13:18:55.288189
1228 13:18:55.291474 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1229 13:18:55.294690 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1230 13:18:55.298676 [Gating] SW calibration Done
1231 13:18:55.298753 ==
1232 13:18:55.301620 Dram Type= 6, Freq= 0, CH_0, rank 1
1233 13:18:55.304836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1234 13:18:55.308218 ==
1235 13:18:55.308295 RX Vref Scan: 0
1236 13:18:55.308355
1237 13:18:55.311491 RX Vref 0 -> 0, step: 1
1238 13:18:55.311567
1239 13:18:55.314732 RX Delay -130 -> 252, step: 16
1240 13:18:55.318527 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1241 13:18:55.321684 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1242 13:18:55.324728 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1243 13:18:55.328600 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1244 13:18:55.335092 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1245 13:18:55.337946 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1246 13:18:55.341516 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1247 13:18:55.344933 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1248 13:18:55.348218 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1249 13:18:55.354466 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1250 13:18:55.357837 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1251 13:18:55.361236 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1252 13:18:55.364979 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1253 13:18:55.368029 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1254 13:18:55.374652 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1255 13:18:55.378005 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1256 13:18:55.378107 ==
1257 13:18:55.381884 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 13:18:55.385122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1259 13:18:55.385200 ==
1260 13:18:55.388266 DQS Delay:
1261 13:18:55.388343 DQS0 = 0, DQS1 = 0
1262 13:18:55.388403 DQM Delay:
1263 13:18:55.391628 DQM0 = 80, DQM1 = 72
1264 13:18:55.391705 DQ Delay:
1265 13:18:55.395065 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1266 13:18:55.398247 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =85
1267 13:18:55.401579 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1268 13:18:55.404864 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1269 13:18:55.404936
1270 13:18:55.404995
1271 13:18:55.405055 ==
1272 13:18:55.408017 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 13:18:55.414721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 13:18:55.414800 ==
1275 13:18:55.414884
1276 13:18:55.414941
1277 13:18:55.414994 TX Vref Scan disable
1278 13:18:55.417967 == TX Byte 0 ==
1279 13:18:55.421347 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1280 13:18:55.425238 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1281 13:18:55.428243 == TX Byte 1 ==
1282 13:18:55.431435 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1283 13:18:55.435276 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1284 13:18:55.438536 ==
1285 13:18:55.441812 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 13:18:55.445086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 13:18:55.445181 ==
1288 13:18:55.456965 TX Vref=22, minBit 0, minWin=27, winSum=436
1289 13:18:55.460486 TX Vref=24, minBit 9, minWin=26, winSum=435
1290 13:18:55.463485 TX Vref=26, minBit 13, minWin=26, winSum=440
1291 13:18:55.467060 TX Vref=28, minBit 1, minWin=27, winSum=442
1292 13:18:55.470493 TX Vref=30, minBit 7, minWin=27, winSum=442
1293 13:18:55.476910 TX Vref=32, minBit 11, minWin=26, winSum=442
1294 13:18:55.480179 [TxChooseVref] Worse bit 1, Min win 27, Win sum 442, Final Vref 28
1295 13:18:55.480252
1296 13:18:55.483528 Final TX Range 1 Vref 28
1297 13:18:55.483604
1298 13:18:55.483662 ==
1299 13:18:55.486901 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 13:18:55.490051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 13:18:55.490132 ==
1302 13:18:55.493729
1303 13:18:55.493797
1304 13:18:55.493857 TX Vref Scan disable
1305 13:18:55.497008 == TX Byte 0 ==
1306 13:18:55.500335 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1307 13:18:55.506914 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1308 13:18:55.507016 == TX Byte 1 ==
1309 13:18:55.510206 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1310 13:18:55.517252 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1311 13:18:55.517360
1312 13:18:55.517448 [DATLAT]
1313 13:18:55.517509 Freq=800, CH0 RK1
1314 13:18:55.517563
1315 13:18:55.520378 DATLAT Default: 0xa
1316 13:18:55.520445 0, 0xFFFF, sum = 0
1317 13:18:55.523938 1, 0xFFFF, sum = 0
1318 13:18:55.524034 2, 0xFFFF, sum = 0
1319 13:18:55.527156 3, 0xFFFF, sum = 0
1320 13:18:55.527243 4, 0xFFFF, sum = 0
1321 13:18:55.530382 5, 0xFFFF, sum = 0
1322 13:18:55.533574 6, 0xFFFF, sum = 0
1323 13:18:55.533669 7, 0xFFFF, sum = 0
1324 13:18:55.536902 8, 0xFFFF, sum = 0
1325 13:18:55.536971 9, 0x0, sum = 1
1326 13:18:55.537029 10, 0x0, sum = 2
1327 13:18:55.540163 11, 0x0, sum = 3
1328 13:18:55.540237 12, 0x0, sum = 4
1329 13:18:55.544017 best_step = 10
1330 13:18:55.544114
1331 13:18:55.544215 ==
1332 13:18:55.547278 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 13:18:55.550004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 13:18:55.550114 ==
1335 13:18:55.553910 RX Vref Scan: 0
1336 13:18:55.554005
1337 13:18:55.554091 RX Vref 0 -> 0, step: 1
1338 13:18:55.554182
1339 13:18:55.557249 RX Delay -111 -> 252, step: 8
1340 13:18:55.563722 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1341 13:18:55.567402 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1342 13:18:55.570415 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1343 13:18:55.573495 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1344 13:18:55.577134 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1345 13:18:55.583971 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1346 13:18:55.587137 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1347 13:18:55.590362 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1348 13:18:55.593553 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1349 13:18:55.596788 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1350 13:18:55.603761 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1351 13:18:55.607051 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1352 13:18:55.610344 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1353 13:18:55.613581 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1354 13:18:55.616808 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1355 13:18:55.623945 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1356 13:18:55.624045 ==
1357 13:18:55.627027 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 13:18:55.630216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 13:18:55.630284 ==
1360 13:18:55.630340 DQS Delay:
1361 13:18:55.633759 DQS0 = 0, DQS1 = 0
1362 13:18:55.633836 DQM Delay:
1363 13:18:55.637025 DQM0 = 78, DQM1 = 70
1364 13:18:55.637118 DQ Delay:
1365 13:18:55.640259 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1366 13:18:55.643582 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =88
1367 13:18:55.646759 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1368 13:18:55.650562 DQ12 =72, DQ13 =72, DQ14 =80, DQ15 =80
1369 13:18:55.650663
1370 13:18:55.650749
1371 13:18:55.660474 [DQSOSCAuto] RK1, (LSB)MR18= 0x4f2a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
1372 13:18:55.660556 CH0 RK1: MR19=606, MR18=4F2A
1373 13:18:55.667005 CH0_RK1: MR19=0x606, MR18=0x4F2A, DQSOSC=390, MR23=63, INC=97, DEC=64
1374 13:18:55.670350 [RxdqsGatingPostProcess] freq 800
1375 13:18:55.677202 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1376 13:18:55.680545 Pre-setting of DQS Precalculation
1377 13:18:55.683914 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1378 13:18:55.684007 ==
1379 13:18:55.687109 Dram Type= 6, Freq= 0, CH_1, rank 0
1380 13:18:55.690206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 13:18:55.693209 ==
1382 13:18:55.696690 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1383 13:18:55.703643 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1384 13:18:55.712464 [CA 0] Center 36 (6~67) winsize 62
1385 13:18:55.715694 [CA 1] Center 36 (6~67) winsize 62
1386 13:18:55.719010 [CA 2] Center 34 (4~64) winsize 61
1387 13:18:55.722379 [CA 3] Center 34 (4~64) winsize 61
1388 13:18:55.725594 [CA 4] Center 34 (4~65) winsize 62
1389 13:18:55.728833 [CA 5] Center 34 (4~64) winsize 61
1390 13:18:55.728910
1391 13:18:55.732234 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1392 13:18:55.732311
1393 13:18:55.735978 [CATrainingPosCal] consider 1 rank data
1394 13:18:55.738931 u2DelayCellTimex100 = 270/100 ps
1395 13:18:55.742388 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 13:18:55.745538 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1397 13:18:55.752106 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1398 13:18:55.755310 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1399 13:18:55.759121 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1400 13:18:55.762222 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1401 13:18:55.762289
1402 13:18:55.765501 CA PerBit enable=1, Macro0, CA PI delay=34
1403 13:18:55.765579
1404 13:18:55.768731 [CBTSetCACLKResult] CA Dly = 34
1405 13:18:55.768811 CS Dly: 5 (0~36)
1406 13:18:55.768871 ==
1407 13:18:55.772014 Dram Type= 6, Freq= 0, CH_1, rank 1
1408 13:18:55.778578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1409 13:18:55.778657 ==
1410 13:18:55.782302 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1411 13:18:55.788761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1412 13:18:55.798601 [CA 0] Center 37 (7~67) winsize 61
1413 13:18:55.801708 [CA 1] Center 36 (6~67) winsize 62
1414 13:18:55.804812 [CA 2] Center 35 (5~65) winsize 61
1415 13:18:55.807918 [CA 3] Center 34 (4~64) winsize 61
1416 13:18:55.811347 [CA 4] Center 34 (4~65) winsize 62
1417 13:18:55.814829 [CA 5] Center 33 (3~64) winsize 62
1418 13:18:55.814931
1419 13:18:55.818352 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1420 13:18:55.818449
1421 13:18:55.821463 [CATrainingPosCal] consider 2 rank data
1422 13:18:55.824706 u2DelayCellTimex100 = 270/100 ps
1423 13:18:55.827993 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1424 13:18:55.831428 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1425 13:18:55.838565 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1426 13:18:55.841821 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1427 13:18:55.845142 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 13:18:55.848287 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1429 13:18:55.848356
1430 13:18:55.851416 CA PerBit enable=1, Macro0, CA PI delay=34
1431 13:18:55.851482
1432 13:18:55.854979 [CBTSetCACLKResult] CA Dly = 34
1433 13:18:55.855051 CS Dly: 6 (0~38)
1434 13:18:55.855108
1435 13:18:55.858240 ----->DramcWriteLeveling(PI) begin...
1436 13:18:55.861440 ==
1437 13:18:55.864598 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 13:18:55.868481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 13:18:55.868583 ==
1440 13:18:55.871378 Write leveling (Byte 0): 30 => 30
1441 13:18:55.874711 Write leveling (Byte 1): 30 => 30
1442 13:18:55.877929 DramcWriteLeveling(PI) end<-----
1443 13:18:55.877998
1444 13:18:55.878055 ==
1445 13:18:55.881263 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 13:18:55.885032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 13:18:55.885104 ==
1448 13:18:55.887925 [Gating] SW mode calibration
1449 13:18:55.895099 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1450 13:18:55.898383 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1451 13:18:55.904758 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1452 13:18:55.908207 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1453 13:18:55.911506 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1454 13:18:55.918297 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 13:18:55.921228 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:18:55.924416 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 13:18:55.931557 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 13:18:55.935041 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 13:18:55.937931 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 13:18:55.945137 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 13:18:55.948458 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 13:18:55.951827 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 13:18:55.958218 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 13:18:55.961364 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 13:18:55.965271 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 13:18:55.971967 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 13:18:55.974971 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 13:18:55.978158 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 13:18:55.981865 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1470 13:18:55.988479 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 13:18:55.991647 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 13:18:55.994663 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 13:18:56.001321 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 13:18:56.004603 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 13:18:56.008445 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 13:18:56.014983 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 13:18:56.018245 0 9 8 | B1->B0 | 2b2b 2d2d | 1 1 | (1 1) (1 1)
1478 13:18:56.021598 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 13:18:56.028484 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 13:18:56.031801 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 13:18:56.035078 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 13:18:56.041514 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 13:18:56.045159 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 13:18:56.048228 0 10 4 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
1485 13:18:56.054687 0 10 8 | B1->B0 | 2d2d 2f2f | 0 0 | (0 0) (0 0)
1486 13:18:56.057876 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 13:18:56.061222 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 13:18:56.068139 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 13:18:56.071479 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 13:18:56.074443 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 13:18:56.081331 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 13:18:56.084644 0 11 4 | B1->B0 | 2424 2727 | 0 1 | (0 0) (0 0)
1493 13:18:56.087718 0 11 8 | B1->B0 | 3737 3838 | 0 0 | (0 0) (0 0)
1494 13:18:56.094315 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 13:18:56.097523 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 13:18:56.100967 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 13:18:56.108109 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 13:18:56.111382 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 13:18:56.114639 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 13:18:56.117976 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 13:18:56.124521 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1502 13:18:56.127809 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 13:18:56.131025 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 13:18:56.137928 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 13:18:56.141207 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 13:18:56.144421 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 13:18:56.150946 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 13:18:56.154721 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 13:18:56.157782 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 13:18:56.164357 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 13:18:56.168174 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 13:18:56.171515 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 13:18:56.178117 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 13:18:56.181207 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 13:18:56.184703 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 13:18:56.190995 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1517 13:18:56.194195 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1518 13:18:56.198167 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 13:18:56.201486 Total UI for P1: 0, mck2ui 16
1520 13:18:56.204760 best dqsien dly found for B0: ( 0, 14, 6)
1521 13:18:56.207794 Total UI for P1: 0, mck2ui 16
1522 13:18:56.211478 best dqsien dly found for B1: ( 0, 14, 6)
1523 13:18:56.214216 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1524 13:18:56.217809 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1525 13:18:56.217888
1526 13:18:56.221141 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1527 13:18:56.224328 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1528 13:18:56.227634 [Gating] SW calibration Done
1529 13:18:56.227734 ==
1530 13:18:56.231025 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 13:18:56.237427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1532 13:18:56.237506 ==
1533 13:18:56.237565 RX Vref Scan: 0
1534 13:18:56.237621
1535 13:18:56.241270 RX Vref 0 -> 0, step: 1
1536 13:18:56.241346
1537 13:18:56.244508 RX Delay -130 -> 252, step: 16
1538 13:18:56.247554 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1539 13:18:56.250927 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1540 13:18:56.254233 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1541 13:18:56.257546 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1542 13:18:56.264143 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1543 13:18:56.267810 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1544 13:18:56.270802 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1545 13:18:56.274372 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1546 13:18:56.277340 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1547 13:18:56.284594 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1548 13:18:56.287994 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1549 13:18:56.291045 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1550 13:18:56.294165 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1551 13:18:56.301221 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1552 13:18:56.304022 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1553 13:18:56.307786 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1554 13:18:56.307859 ==
1555 13:18:56.311047 Dram Type= 6, Freq= 0, CH_1, rank 0
1556 13:18:56.314064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1557 13:18:56.314171 ==
1558 13:18:56.317655 DQS Delay:
1559 13:18:56.317748 DQS0 = 0, DQS1 = 0
1560 13:18:56.317835 DQM Delay:
1561 13:18:56.320703 DQM0 = 81, DQM1 = 71
1562 13:18:56.320826 DQ Delay:
1563 13:18:56.324433 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1564 13:18:56.327662 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1565 13:18:56.331031 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1566 13:18:56.334345 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1567 13:18:56.334423
1568 13:18:56.334482
1569 13:18:56.334535 ==
1570 13:18:56.337611 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 13:18:56.344257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 13:18:56.344336 ==
1573 13:18:56.344395
1574 13:18:56.344448
1575 13:18:56.344500 TX Vref Scan disable
1576 13:18:56.347558 == TX Byte 0 ==
1577 13:18:56.351283 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1578 13:18:56.354956 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1579 13:18:56.358240 == TX Byte 1 ==
1580 13:18:56.361614 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1581 13:18:56.364814 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1582 13:18:56.368163 ==
1583 13:18:56.371531 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 13:18:56.374770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 13:18:56.374848 ==
1586 13:18:56.386779 TX Vref=22, minBit 0, minWin=27, winSum=438
1587 13:18:56.390526 TX Vref=24, minBit 0, minWin=27, winSum=439
1588 13:18:56.393926 TX Vref=26, minBit 1, minWin=27, winSum=445
1589 13:18:56.397214 TX Vref=28, minBit 1, minWin=27, winSum=447
1590 13:18:56.400330 TX Vref=30, minBit 9, minWin=27, winSum=449
1591 13:18:56.403583 TX Vref=32, minBit 0, minWin=27, winSum=443
1592 13:18:56.410304 [TxChooseVref] Worse bit 9, Min win 27, Win sum 449, Final Vref 30
1593 13:18:56.410436
1594 13:18:56.413325 Final TX Range 1 Vref 30
1595 13:18:56.413394
1596 13:18:56.413449 ==
1597 13:18:56.416943 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 13:18:56.420421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 13:18:56.420499 ==
1600 13:18:56.420559
1601 13:18:56.423463
1602 13:18:56.423540 TX Vref Scan disable
1603 13:18:56.426673 == TX Byte 0 ==
1604 13:18:56.430212 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1605 13:18:56.433790 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1606 13:18:56.436956 == TX Byte 1 ==
1607 13:18:56.440218 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1608 13:18:56.443559 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1609 13:18:56.443635
1610 13:18:56.446745 [DATLAT]
1611 13:18:56.446821 Freq=800, CH1 RK0
1612 13:18:56.446880
1613 13:18:56.450136 DATLAT Default: 0xa
1614 13:18:56.450212 0, 0xFFFF, sum = 0
1615 13:18:56.453441 1, 0xFFFF, sum = 0
1616 13:18:56.453518 2, 0xFFFF, sum = 0
1617 13:18:56.456643 3, 0xFFFF, sum = 0
1618 13:18:56.456721 4, 0xFFFF, sum = 0
1619 13:18:56.460249 5, 0xFFFF, sum = 0
1620 13:18:56.460353 6, 0xFFFF, sum = 0
1621 13:18:56.463550 7, 0xFFFF, sum = 0
1622 13:18:56.463645 8, 0xFFFF, sum = 0
1623 13:18:56.466925 9, 0x0, sum = 1
1624 13:18:56.467000 10, 0x0, sum = 2
1625 13:18:56.470281 11, 0x0, sum = 3
1626 13:18:56.470355 12, 0x0, sum = 4
1627 13:18:56.473495 best_step = 10
1628 13:18:56.473589
1629 13:18:56.473676 ==
1630 13:18:56.476908 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 13:18:56.480266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 13:18:56.480337 ==
1633 13:18:56.483507 RX Vref Scan: 1
1634 13:18:56.483574
1635 13:18:56.483629 Set Vref Range= 32 -> 127
1636 13:18:56.483686
1637 13:18:56.486622 RX Vref 32 -> 127, step: 1
1638 13:18:56.486691
1639 13:18:56.490208 RX Delay -111 -> 252, step: 8
1640 13:18:56.490309
1641 13:18:56.493311 Set Vref, RX VrefLevel [Byte0]: 32
1642 13:18:56.497009 [Byte1]: 32
1643 13:18:56.497086
1644 13:18:56.500150 Set Vref, RX VrefLevel [Byte0]: 33
1645 13:18:56.503431 [Byte1]: 33
1646 13:18:56.507328
1647 13:18:56.507405 Set Vref, RX VrefLevel [Byte0]: 34
1648 13:18:56.510583 [Byte1]: 34
1649 13:18:56.514578
1650 13:18:56.514678 Set Vref, RX VrefLevel [Byte0]: 35
1651 13:18:56.518541 [Byte1]: 35
1652 13:18:56.522760
1653 13:18:56.522836 Set Vref, RX VrefLevel [Byte0]: 36
1654 13:18:56.525800 [Byte1]: 36
1655 13:18:56.530169
1656 13:18:56.530245 Set Vref, RX VrefLevel [Byte0]: 37
1657 13:18:56.533797 [Byte1]: 37
1658 13:18:56.537907
1659 13:18:56.537991 Set Vref, RX VrefLevel [Byte0]: 38
1660 13:18:56.541393 [Byte1]: 38
1661 13:18:56.545460
1662 13:18:56.545538 Set Vref, RX VrefLevel [Byte0]: 39
1663 13:18:56.548964 [Byte1]: 39
1664 13:18:56.552985
1665 13:18:56.553060 Set Vref, RX VrefLevel [Byte0]: 40
1666 13:18:56.556161 [Byte1]: 40
1667 13:18:56.560707
1668 13:18:56.560784 Set Vref, RX VrefLevel [Byte0]: 41
1669 13:18:56.563947 [Byte1]: 41
1670 13:18:56.568352
1671 13:18:56.568427 Set Vref, RX VrefLevel [Byte0]: 42
1672 13:18:56.571579 [Byte1]: 42
1673 13:18:56.576290
1674 13:18:56.576366 Set Vref, RX VrefLevel [Byte0]: 43
1675 13:18:56.579611 [Byte1]: 43
1676 13:18:56.583583
1677 13:18:56.583659 Set Vref, RX VrefLevel [Byte0]: 44
1678 13:18:56.586953 [Byte1]: 44
1679 13:18:56.591514
1680 13:18:56.591592 Set Vref, RX VrefLevel [Byte0]: 45
1681 13:18:56.594794 [Byte1]: 45
1682 13:18:56.599152
1683 13:18:56.599239 Set Vref, RX VrefLevel [Byte0]: 46
1684 13:18:56.602280 [Byte1]: 46
1685 13:18:56.606589
1686 13:18:56.606690 Set Vref, RX VrefLevel [Byte0]: 47
1687 13:18:56.610269 [Byte1]: 47
1688 13:18:56.614154
1689 13:18:56.614231 Set Vref, RX VrefLevel [Byte0]: 48
1690 13:18:56.617461 [Byte1]: 48
1691 13:18:56.622265
1692 13:18:56.622346 Set Vref, RX VrefLevel [Byte0]: 49
1693 13:18:56.624960 [Byte1]: 49
1694 13:18:56.629587
1695 13:18:56.629687 Set Vref, RX VrefLevel [Byte0]: 50
1696 13:18:56.632805 [Byte1]: 50
1697 13:18:56.637403
1698 13:18:56.637480 Set Vref, RX VrefLevel [Byte0]: 51
1699 13:18:56.640582 [Byte1]: 51
1700 13:18:56.644981
1701 13:18:56.645057 Set Vref, RX VrefLevel [Byte0]: 52
1702 13:18:56.648148 [Byte1]: 52
1703 13:18:56.652600
1704 13:18:56.655564 Set Vref, RX VrefLevel [Byte0]: 53
1705 13:18:56.658811 [Byte1]: 53
1706 13:18:56.658888
1707 13:18:56.662002 Set Vref, RX VrefLevel [Byte0]: 54
1708 13:18:56.665852 [Byte1]: 54
1709 13:18:56.665951
1710 13:18:56.669275 Set Vref, RX VrefLevel [Byte0]: 55
1711 13:18:56.672529 [Byte1]: 55
1712 13:18:56.675832
1713 13:18:56.675907 Set Vref, RX VrefLevel [Byte0]: 56
1714 13:18:56.679143 [Byte1]: 56
1715 13:18:56.683170
1716 13:18:56.683246 Set Vref, RX VrefLevel [Byte0]: 57
1717 13:18:56.686497 [Byte1]: 57
1718 13:18:56.690990
1719 13:18:56.691079 Set Vref, RX VrefLevel [Byte0]: 58
1720 13:18:56.694355 [Byte1]: 58
1721 13:18:56.698328
1722 13:18:56.698405 Set Vref, RX VrefLevel [Byte0]: 59
1723 13:18:56.701601 [Byte1]: 59
1724 13:18:56.705891
1725 13:18:56.705965 Set Vref, RX VrefLevel [Byte0]: 60
1726 13:18:56.709568 [Byte1]: 60
1727 13:18:56.713980
1728 13:18:56.714080 Set Vref, RX VrefLevel [Byte0]: 61
1729 13:18:56.716917 [Byte1]: 61
1730 13:18:56.721202
1731 13:18:56.721278 Set Vref, RX VrefLevel [Byte0]: 62
1732 13:18:56.724590 [Byte1]: 62
1733 13:18:56.729251
1734 13:18:56.729351 Set Vref, RX VrefLevel [Byte0]: 63
1735 13:18:56.732362 [Byte1]: 63
1736 13:18:56.736966
1737 13:18:56.737041 Set Vref, RX VrefLevel [Byte0]: 64
1738 13:18:56.740069 [Byte1]: 64
1739 13:18:56.744019
1740 13:18:56.744095 Set Vref, RX VrefLevel [Byte0]: 65
1741 13:18:56.747933 [Byte1]: 65
1742 13:18:56.751778
1743 13:18:56.751854 Set Vref, RX VrefLevel [Byte0]: 66
1744 13:18:56.754980 [Byte1]: 66
1745 13:18:56.759640
1746 13:18:56.759716 Set Vref, RX VrefLevel [Byte0]: 67
1747 13:18:56.762897 [Byte1]: 67
1748 13:18:56.767390
1749 13:18:56.767467 Set Vref, RX VrefLevel [Byte0]: 68
1750 13:18:56.770356 [Byte1]: 68
1751 13:18:56.775082
1752 13:18:56.775158 Set Vref, RX VrefLevel [Byte0]: 69
1753 13:18:56.777805 [Byte1]: 69
1754 13:18:56.782342
1755 13:18:56.782419 Set Vref, RX VrefLevel [Byte0]: 70
1756 13:18:56.785986 [Byte1]: 70
1757 13:18:56.789944
1758 13:18:56.790022 Set Vref, RX VrefLevel [Byte0]: 71
1759 13:18:56.793269 [Byte1]: 71
1760 13:18:56.797869
1761 13:18:56.797971 Set Vref, RX VrefLevel [Byte0]: 72
1762 13:18:56.801226 [Byte1]: 72
1763 13:18:56.805185
1764 13:18:56.805262 Set Vref, RX VrefLevel [Byte0]: 73
1765 13:18:56.809090 [Byte1]: 73
1766 13:18:56.812977
1767 13:18:56.813053 Set Vref, RX VrefLevel [Byte0]: 74
1768 13:18:56.816105 [Byte1]: 74
1769 13:18:56.820466
1770 13:18:56.820567 Set Vref, RX VrefLevel [Byte0]: 75
1771 13:18:56.824188 [Byte1]: 75
1772 13:18:56.828300
1773 13:18:56.828379 Set Vref, RX VrefLevel [Byte0]: 76
1774 13:18:56.831608 [Byte1]: 76
1775 13:18:56.836083
1776 13:18:56.836159 Final RX Vref Byte 0 = 55 to rank0
1777 13:18:56.839454 Final RX Vref Byte 1 = 56 to rank0
1778 13:18:56.842578 Final RX Vref Byte 0 = 55 to rank1
1779 13:18:56.845929 Final RX Vref Byte 1 = 56 to rank1==
1780 13:18:56.849190 Dram Type= 6, Freq= 0, CH_1, rank 0
1781 13:18:56.855796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1782 13:18:56.855936 ==
1783 13:18:56.856051 DQS Delay:
1784 13:18:56.856137 DQS0 = 0, DQS1 = 0
1785 13:18:56.859695 DQM Delay:
1786 13:18:56.859771 DQM0 = 81, DQM1 = 71
1787 13:18:56.862894 DQ Delay:
1788 13:18:56.866247 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1789 13:18:56.866324 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1790 13:18:56.869510 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1791 13:18:56.872766 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =76
1792 13:18:56.876095
1793 13:18:56.876173
1794 13:18:56.882734 [DQSOSCAuto] RK0, (LSB)MR18= 0x141e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
1795 13:18:56.885922 CH1 RK0: MR19=606, MR18=141E
1796 13:18:56.892829 CH1_RK0: MR19=0x606, MR18=0x141E, DQSOSC=402, MR23=63, INC=91, DEC=60
1797 13:18:56.892906
1798 13:18:56.896207 ----->DramcWriteLeveling(PI) begin...
1799 13:18:56.896287 ==
1800 13:18:56.899392 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 13:18:56.902912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1802 13:18:56.902990 ==
1803 13:18:56.906077 Write leveling (Byte 0): 25 => 25
1804 13:18:56.909333 Write leveling (Byte 1): 30 => 30
1805 13:18:56.912670 DramcWriteLeveling(PI) end<-----
1806 13:18:56.912747
1807 13:18:56.912805 ==
1808 13:18:56.915970 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 13:18:56.919254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 13:18:56.919359 ==
1811 13:18:56.923109 [Gating] SW mode calibration
1812 13:18:56.929287 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1813 13:18:56.936120 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1814 13:18:56.939271 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1815 13:18:56.942685 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1816 13:18:56.949590 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 13:18:56.952797 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 13:18:56.956051 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 13:18:56.962581 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 13:18:56.965852 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 13:18:56.969169 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 13:18:56.976212 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 13:18:56.979506 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 13:18:56.982760 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 13:18:56.986222 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 13:18:56.992838 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 13:18:56.996097 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 13:18:56.999158 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 13:18:57.006438 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 13:18:57.009314 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 13:18:57.013042 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1832 13:18:57.019770 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 13:18:57.022974 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 13:18:57.026371 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 13:18:57.032692 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 13:18:57.035812 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 13:18:57.039613 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 13:18:57.046020 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 13:18:57.049762 0 9 4 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (1 1)
1840 13:18:57.052600 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1841 13:18:57.059342 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 13:18:57.062793 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 13:18:57.066054 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 13:18:57.072725 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 13:18:57.075990 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 13:18:57.079103 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1847 13:18:57.082550 0 10 4 | B1->B0 | 3333 2e2e | 0 0 | (0 1) (1 0)
1848 13:18:57.089676 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1849 13:18:57.092956 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 13:18:57.096132 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 13:18:57.102680 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 13:18:57.105803 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 13:18:57.109714 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 13:18:57.115809 0 11 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1855 13:18:57.119688 0 11 4 | B1->B0 | 2b2b 4040 | 0 1 | (0 0) (0 0)
1856 13:18:57.122550 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1857 13:18:57.129401 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 13:18:57.132561 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 13:18:57.135734 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 13:18:57.142551 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 13:18:57.145665 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 13:18:57.149508 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 13:18:57.156048 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1864 13:18:57.159293 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1865 13:18:57.162332 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 13:18:57.169204 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 13:18:57.172722 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 13:18:57.175650 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 13:18:57.182584 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 13:18:57.185770 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 13:18:57.189136 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 13:18:57.195880 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 13:18:57.199085 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 13:18:57.202518 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 13:18:57.209097 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 13:18:57.212441 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 13:18:57.215739 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 13:18:57.218881 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 13:18:57.225764 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1880 13:18:57.229142 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1881 13:18:57.232451 Total UI for P1: 0, mck2ui 16
1882 13:18:57.235656 best dqsien dly found for B0: ( 0, 14, 4)
1883 13:18:57.238849 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 13:18:57.242617 Total UI for P1: 0, mck2ui 16
1885 13:18:57.245674 best dqsien dly found for B1: ( 0, 14, 8)
1886 13:18:57.248967 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1887 13:18:57.252550 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1888 13:18:57.252627
1889 13:18:57.258925 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1890 13:18:57.262214 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1891 13:18:57.262291 [Gating] SW calibration Done
1892 13:18:57.266036 ==
1893 13:18:57.266120 Dram Type= 6, Freq= 0, CH_1, rank 1
1894 13:18:57.272440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1895 13:18:57.272520 ==
1896 13:18:57.272582 RX Vref Scan: 0
1897 13:18:57.272639
1898 13:18:57.275752 RX Vref 0 -> 0, step: 1
1899 13:18:57.275818
1900 13:18:57.279399 RX Delay -130 -> 252, step: 16
1901 13:18:57.282439 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1902 13:18:57.286048 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1903 13:18:57.289508 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1904 13:18:57.295971 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1905 13:18:57.299272 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1906 13:18:57.302593 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1907 13:18:57.305850 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1908 13:18:57.309181 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1909 13:18:57.315658 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1910 13:18:57.319008 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1911 13:18:57.322369 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1912 13:18:57.325625 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1913 13:18:57.329468 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1914 13:18:57.336071 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1915 13:18:57.339243 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1916 13:18:57.342326 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1917 13:18:57.342404 ==
1918 13:18:57.345580 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 13:18:57.348898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 13:18:57.352586 ==
1921 13:18:57.352664 DQS Delay:
1922 13:18:57.352723 DQS0 = 0, DQS1 = 0
1923 13:18:57.355875 DQM Delay:
1924 13:18:57.355976 DQM0 = 79, DQM1 = 74
1925 13:18:57.356065 DQ Delay:
1926 13:18:57.359054 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1927 13:18:57.362061 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1928 13:18:57.365721 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1929 13:18:57.368744 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1930 13:18:57.368847
1931 13:18:57.368938
1932 13:18:57.372752 ==
1933 13:18:57.375849 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 13:18:57.379137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 13:18:57.379215 ==
1936 13:18:57.379275
1937 13:18:57.379329
1938 13:18:57.382256 TX Vref Scan disable
1939 13:18:57.382335 == TX Byte 0 ==
1940 13:18:57.388686 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1941 13:18:57.391925 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1942 13:18:57.392004 == TX Byte 1 ==
1943 13:18:57.398826 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1944 13:18:57.402408 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1945 13:18:57.402511 ==
1946 13:18:57.405776 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 13:18:57.408438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 13:18:57.408533 ==
1949 13:18:57.422819 TX Vref=22, minBit 9, minWin=27, winSum=454
1950 13:18:57.426126 TX Vref=24, minBit 2, minWin=28, winSum=457
1951 13:18:57.429541 TX Vref=26, minBit 3, minWin=28, winSum=459
1952 13:18:57.432794 TX Vref=28, minBit 1, minWin=28, winSum=466
1953 13:18:57.436107 TX Vref=30, minBit 1, minWin=28, winSum=467
1954 13:18:57.439396 TX Vref=32, minBit 5, minWin=28, winSum=466
1955 13:18:57.446077 [TxChooseVref] Worse bit 1, Min win 28, Win sum 467, Final Vref 30
1956 13:18:57.446184
1957 13:18:57.449789 Final TX Range 1 Vref 30
1958 13:18:57.449866
1959 13:18:57.449926 ==
1960 13:18:57.453025 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 13:18:57.455998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 13:18:57.456102 ==
1963 13:18:57.456192
1964 13:18:57.456278
1965 13:18:57.459137 TX Vref Scan disable
1966 13:18:57.463181 == TX Byte 0 ==
1967 13:18:57.466305 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1968 13:18:57.469477 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1969 13:18:57.473073 == TX Byte 1 ==
1970 13:18:57.475984 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1971 13:18:57.479665 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1972 13:18:57.482617
1973 13:18:57.482716 [DATLAT]
1974 13:18:57.482803 Freq=800, CH1 RK1
1975 13:18:57.482893
1976 13:18:57.486364 DATLAT Default: 0xa
1977 13:18:57.486459 0, 0xFFFF, sum = 0
1978 13:18:57.489593 1, 0xFFFF, sum = 0
1979 13:18:57.489685 2, 0xFFFF, sum = 0
1980 13:18:57.492940 3, 0xFFFF, sum = 0
1981 13:18:57.493041 4, 0xFFFF, sum = 0
1982 13:18:57.496055 5, 0xFFFF, sum = 0
1983 13:18:57.496153 6, 0xFFFF, sum = 0
1984 13:18:57.499239 7, 0xFFFF, sum = 0
1985 13:18:57.503163 8, 0xFFFF, sum = 0
1986 13:18:57.503257 9, 0x0, sum = 1
1987 13:18:57.503346 10, 0x0, sum = 2
1988 13:18:57.506162 11, 0x0, sum = 3
1989 13:18:57.506254 12, 0x0, sum = 4
1990 13:18:57.509854 best_step = 10
1991 13:18:57.509952
1992 13:18:57.510036 ==
1993 13:18:57.513187 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 13:18:57.516397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 13:18:57.516489 ==
1996 13:18:57.519649 RX Vref Scan: 0
1997 13:18:57.519744
1998 13:18:57.519827 RX Vref 0 -> 0, step: 1
1999 13:18:57.519908
2000 13:18:57.522901 RX Delay -95 -> 252, step: 8
2001 13:18:57.529755 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2002 13:18:57.533140 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2003 13:18:57.536587 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2004 13:18:57.540097 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2005 13:18:57.542835 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2006 13:18:57.549536 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2007 13:18:57.553324 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2008 13:18:57.556195 iDelay=209, Bit 7, Center 72 (-47 ~ 192) 240
2009 13:18:57.559517 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2010 13:18:57.562930 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2011 13:18:57.569752 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2012 13:18:57.573248 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2013 13:18:57.576000 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2014 13:18:57.579937 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2015 13:18:57.583216 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2016 13:18:57.589496 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2017 13:18:57.589576 ==
2018 13:18:57.593356 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 13:18:57.596248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 13:18:57.596328 ==
2021 13:18:57.596388 DQS Delay:
2022 13:18:57.599746 DQS0 = 0, DQS1 = 0
2023 13:18:57.599823 DQM Delay:
2024 13:18:57.603076 DQM0 = 76, DQM1 = 73
2025 13:18:57.603176 DQ Delay:
2026 13:18:57.606489 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2027 13:18:57.609719 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =72
2028 13:18:57.613199 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2029 13:18:57.616242 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2030 13:18:57.616319
2031 13:18:57.616392
2032 13:18:57.622959 [DQSOSCAuto] RK1, (LSB)MR18= 0x253c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2033 13:18:57.626220 CH1 RK1: MR19=606, MR18=253C
2034 13:18:57.633364 CH1_RK1: MR19=0x606, MR18=0x253C, DQSOSC=394, MR23=63, INC=95, DEC=63
2035 13:18:57.636479 [RxdqsGatingPostProcess] freq 800
2036 13:18:57.643169 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2037 13:18:57.643276 Pre-setting of DQS Precalculation
2038 13:18:57.649803 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2039 13:18:57.656153 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2040 13:18:57.663070 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2041 13:18:57.663152
2042 13:18:57.663212
2043 13:18:57.666331 [Calibration Summary] 1600 Mbps
2044 13:18:57.669467 CH 0, Rank 0
2045 13:18:57.669568 SW Impedance : PASS
2046 13:18:57.672734 DUTY Scan : NO K
2047 13:18:57.676012 ZQ Calibration : PASS
2048 13:18:57.676107 Jitter Meter : NO K
2049 13:18:57.679319 CBT Training : PASS
2050 13:18:57.682597 Write leveling : PASS
2051 13:18:57.682688 RX DQS gating : PASS
2052 13:18:57.686330 RX DQ/DQS(RDDQC) : PASS
2053 13:18:57.686425 TX DQ/DQS : PASS
2054 13:18:57.689619 RX DATLAT : PASS
2055 13:18:57.692948 RX DQ/DQS(Engine): PASS
2056 13:18:57.693039 TX OE : NO K
2057 13:18:57.696191 All Pass.
2058 13:18:57.696284
2059 13:18:57.696368 CH 0, Rank 1
2060 13:18:57.699295 SW Impedance : PASS
2061 13:18:57.699387 DUTY Scan : NO K
2062 13:18:57.703060 ZQ Calibration : PASS
2063 13:18:57.706230 Jitter Meter : NO K
2064 13:18:57.706322 CBT Training : PASS
2065 13:18:57.709752 Write leveling : PASS
2066 13:18:57.713356 RX DQS gating : PASS
2067 13:18:57.713433 RX DQ/DQS(RDDQC) : PASS
2068 13:18:57.716296 TX DQ/DQS : PASS
2069 13:18:57.716398 RX DATLAT : PASS
2070 13:18:57.719997 RX DQ/DQS(Engine): PASS
2071 13:18:57.722979 TX OE : NO K
2072 13:18:57.723072 All Pass.
2073 13:18:57.723160
2074 13:18:57.723243 CH 1, Rank 0
2075 13:18:57.726173 SW Impedance : PASS
2076 13:18:57.729632 DUTY Scan : NO K
2077 13:18:57.729728 ZQ Calibration : PASS
2078 13:18:57.732885 Jitter Meter : NO K
2079 13:18:57.736160 CBT Training : PASS
2080 13:18:57.736254 Write leveling : PASS
2081 13:18:57.739446 RX DQS gating : PASS
2082 13:18:57.743239 RX DQ/DQS(RDDQC) : PASS
2083 13:18:57.743335 TX DQ/DQS : PASS
2084 13:18:57.746567 RX DATLAT : PASS
2085 13:18:57.749792 RX DQ/DQS(Engine): PASS
2086 13:18:57.749894 TX OE : NO K
2087 13:18:57.749983 All Pass.
2088 13:18:57.753108
2089 13:18:57.753199 CH 1, Rank 1
2090 13:18:57.756329 SW Impedance : PASS
2091 13:18:57.756420 DUTY Scan : NO K
2092 13:18:57.759641 ZQ Calibration : PASS
2093 13:18:57.763422 Jitter Meter : NO K
2094 13:18:57.763522 CBT Training : PASS
2095 13:18:57.766467 Write leveling : PASS
2096 13:18:57.766560 RX DQS gating : PASS
2097 13:18:57.769731 RX DQ/DQS(RDDQC) : PASS
2098 13:18:57.772953 TX DQ/DQS : PASS
2099 13:18:57.773054 RX DATLAT : PASS
2100 13:18:57.776174 RX DQ/DQS(Engine): PASS
2101 13:18:57.779517 TX OE : NO K
2102 13:18:57.779596 All Pass.
2103 13:18:57.779657
2104 13:18:57.783380 DramC Write-DBI off
2105 13:18:57.783450 PER_BANK_REFRESH: Hybrid Mode
2106 13:18:57.786586 TX_TRACKING: ON
2107 13:18:57.789741 [GetDramInforAfterCalByMRR] Vendor 6.
2108 13:18:57.793055 [GetDramInforAfterCalByMRR] Revision 606.
2109 13:18:57.796228 [GetDramInforAfterCalByMRR] Revision 2 0.
2110 13:18:57.796325 MR0 0x3b3b
2111 13:18:57.799553 MR8 0x5151
2112 13:18:57.803416 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2113 13:18:57.803486
2114 13:18:57.803544 MR0 0x3b3b
2115 13:18:57.803605 MR8 0x5151
2116 13:18:57.810010 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2117 13:18:57.810113
2118 13:18:57.816378 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2119 13:18:57.820101 [FAST_K] Save calibration result to emmc
2120 13:18:57.823043 [FAST_K] Save calibration result to emmc
2121 13:18:57.826561 dram_init: config_dvfs: 1
2122 13:18:57.829621 dramc_set_vcore_voltage set vcore to 662500
2123 13:18:57.833354 Read voltage for 1200, 2
2124 13:18:57.833460 Vio18 = 0
2125 13:18:57.836561 Vcore = 662500
2126 13:18:57.836629 Vdram = 0
2127 13:18:57.836685 Vddq = 0
2128 13:18:57.836738 Vmddr = 0
2129 13:18:57.843090 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2130 13:18:57.849472 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2131 13:18:57.849565 MEM_TYPE=3, freq_sel=15
2132 13:18:57.853229 sv_algorithm_assistance_LP4_1600
2133 13:18:57.856444 ============ PULL DRAM RESETB DOWN ============
2134 13:18:57.862967 ========== PULL DRAM RESETB DOWN end =========
2135 13:18:57.866745 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2136 13:18:57.870060 ===================================
2137 13:18:57.873167 LPDDR4 DRAM CONFIGURATION
2138 13:18:57.876388 ===================================
2139 13:18:57.876484 EX_ROW_EN[0] = 0x0
2140 13:18:57.879485 EX_ROW_EN[1] = 0x0
2141 13:18:57.879579 LP4Y_EN = 0x0
2142 13:18:57.883254 WORK_FSP = 0x0
2143 13:18:57.883344 WL = 0x4
2144 13:18:57.886466 RL = 0x4
2145 13:18:57.886534 BL = 0x2
2146 13:18:57.889733 RPST = 0x0
2147 13:18:57.893331 RD_PRE = 0x0
2148 13:18:57.893395 WR_PRE = 0x1
2149 13:18:57.896676 WR_PST = 0x0
2150 13:18:57.896766 DBI_WR = 0x0
2151 13:18:57.899919 DBI_RD = 0x0
2152 13:18:57.899984 OTF = 0x1
2153 13:18:57.903226 ===================================
2154 13:18:57.906491 ===================================
2155 13:18:57.906568 ANA top config
2156 13:18:57.909586 ===================================
2157 13:18:57.913483 DLL_ASYNC_EN = 0
2158 13:18:57.916711 ALL_SLAVE_EN = 0
2159 13:18:57.920050 NEW_RANK_MODE = 1
2160 13:18:57.923249 DLL_IDLE_MODE = 1
2161 13:18:57.923319 LP45_APHY_COMB_EN = 1
2162 13:18:57.926585 TX_ODT_DIS = 1
2163 13:18:57.929718 NEW_8X_MODE = 1
2164 13:18:57.933273 ===================================
2165 13:18:57.936852 ===================================
2166 13:18:57.939934 data_rate = 2400
2167 13:18:57.943616 CKR = 1
2168 13:18:57.943712 DQ_P2S_RATIO = 8
2169 13:18:57.946820 ===================================
2170 13:18:57.950009 CA_P2S_RATIO = 8
2171 13:18:57.953311 DQ_CA_OPEN = 0
2172 13:18:57.956457 DQ_SEMI_OPEN = 0
2173 13:18:57.959704 CA_SEMI_OPEN = 0
2174 13:18:57.959810 CA_FULL_RATE = 0
2175 13:18:57.963149 DQ_CKDIV4_EN = 0
2176 13:18:57.966304 CA_CKDIV4_EN = 0
2177 13:18:57.970077 CA_PREDIV_EN = 0
2178 13:18:57.973457 PH8_DLY = 17
2179 13:18:57.976547 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2180 13:18:57.979797 DQ_AAMCK_DIV = 4
2181 13:18:57.979906 CA_AAMCK_DIV = 4
2182 13:18:57.983438 CA_ADMCK_DIV = 4
2183 13:18:57.986647 DQ_TRACK_CA_EN = 0
2184 13:18:57.989898 CA_PICK = 1200
2185 13:18:57.993006 CA_MCKIO = 1200
2186 13:18:57.996069 MCKIO_SEMI = 0
2187 13:18:57.999945 PLL_FREQ = 2366
2188 13:18:58.000038 DQ_UI_PI_RATIO = 32
2189 13:18:58.003219 CA_UI_PI_RATIO = 0
2190 13:18:58.006530 ===================================
2191 13:18:58.009766 ===================================
2192 13:18:58.012933 memory_type:LPDDR4
2193 13:18:58.016183 GP_NUM : 10
2194 13:18:58.016283 SRAM_EN : 1
2195 13:18:58.019573 MD32_EN : 0
2196 13:18:58.022893 ===================================
2197 13:18:58.026037 [ANA_INIT] >>>>>>>>>>>>>>
2198 13:18:58.026140 <<<<<< [CONFIGURE PHASE]: ANA_TX
2199 13:18:58.029257 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2200 13:18:58.032610 ===================================
2201 13:18:58.035861 data_rate = 2400,PCW = 0X5b00
2202 13:18:58.039113 ===================================
2203 13:18:58.042762 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2204 13:18:58.049457 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 13:18:58.055977 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2206 13:18:58.059394 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2207 13:18:58.062454 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2208 13:18:58.066229 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2209 13:18:58.069570 [ANA_INIT] flow start
2210 13:18:58.069646 [ANA_INIT] PLL >>>>>>>>
2211 13:18:58.072722 [ANA_INIT] PLL <<<<<<<<
2212 13:18:58.075998 [ANA_INIT] MIDPI >>>>>>>>
2213 13:18:58.076101 [ANA_INIT] MIDPI <<<<<<<<
2214 13:18:58.079253 [ANA_INIT] DLL >>>>>>>>
2215 13:18:58.082448 [ANA_INIT] DLL <<<<<<<<
2216 13:18:58.082519 [ANA_INIT] flow end
2217 13:18:58.089403 ============ LP4 DIFF to SE enter ============
2218 13:18:58.092575 ============ LP4 DIFF to SE exit ============
2219 13:18:58.095923 [ANA_INIT] <<<<<<<<<<<<<
2220 13:18:58.099103 [Flow] Enable top DCM control >>>>>
2221 13:18:58.102787 [Flow] Enable top DCM control <<<<<
2222 13:18:58.102862 Enable DLL master slave shuffle
2223 13:18:58.108912 ==============================================================
2224 13:18:58.112126 Gating Mode config
2225 13:18:58.116228 ==============================================================
2226 13:18:58.119207 Config description:
2227 13:18:58.129112 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2228 13:18:58.135635 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2229 13:18:58.138970 SELPH_MODE 0: By rank 1: By Phase
2230 13:18:58.145522 ==============================================================
2231 13:18:58.149048 GAT_TRACK_EN = 1
2232 13:18:58.152858 RX_GATING_MODE = 2
2233 13:18:58.155476 RX_GATING_TRACK_MODE = 2
2234 13:18:58.155570 SELPH_MODE = 1
2235 13:18:58.158799 PICG_EARLY_EN = 1
2236 13:18:58.162630 VALID_LAT_VALUE = 1
2237 13:18:58.169322 ==============================================================
2238 13:18:58.172275 Enter into Gating configuration >>>>
2239 13:18:58.175917 Exit from Gating configuration <<<<
2240 13:18:58.179177 Enter into DVFS_PRE_config >>>>>
2241 13:18:58.189233 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2242 13:18:58.192395 Exit from DVFS_PRE_config <<<<<
2243 13:18:58.195985 Enter into PICG configuration >>>>
2244 13:18:58.199121 Exit from PICG configuration <<<<
2245 13:18:58.202453 [RX_INPUT] configuration >>>>>
2246 13:18:58.205684 [RX_INPUT] configuration <<<<<
2247 13:18:58.208989 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2248 13:18:58.215671 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2249 13:18:58.222218 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 13:18:58.229341 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 13:18:58.232622 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2252 13:18:58.239160 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2253 13:18:58.242530 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2254 13:18:58.249079 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2255 13:18:58.252287 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2256 13:18:58.255954 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2257 13:18:58.259282 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2258 13:18:58.265686 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2259 13:18:58.269033 ===================================
2260 13:18:58.269154 LPDDR4 DRAM CONFIGURATION
2261 13:18:58.272249 ===================================
2262 13:18:58.275420 EX_ROW_EN[0] = 0x0
2263 13:18:58.279035 EX_ROW_EN[1] = 0x0
2264 13:18:58.279120 LP4Y_EN = 0x0
2265 13:18:58.282011 WORK_FSP = 0x0
2266 13:18:58.282098 WL = 0x4
2267 13:18:58.285572 RL = 0x4
2268 13:18:58.285669 BL = 0x2
2269 13:18:58.289170 RPST = 0x0
2270 13:18:58.289250 RD_PRE = 0x0
2271 13:18:58.292419 WR_PRE = 0x1
2272 13:18:58.292501 WR_PST = 0x0
2273 13:18:58.295739 DBI_WR = 0x0
2274 13:18:58.295832 DBI_RD = 0x0
2275 13:18:58.299030 OTF = 0x1
2276 13:18:58.302086 ===================================
2277 13:18:58.305698 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2278 13:18:58.309012 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2279 13:18:58.315599 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2280 13:18:58.318964 ===================================
2281 13:18:58.319051 LPDDR4 DRAM CONFIGURATION
2282 13:18:58.322078 ===================================
2283 13:18:58.325712 EX_ROW_EN[0] = 0x10
2284 13:18:58.328724 EX_ROW_EN[1] = 0x0
2285 13:18:58.328804 LP4Y_EN = 0x0
2286 13:18:58.332439 WORK_FSP = 0x0
2287 13:18:58.332518 WL = 0x4
2288 13:18:58.335658 RL = 0x4
2289 13:18:58.335723 BL = 0x2
2290 13:18:58.338822 RPST = 0x0
2291 13:18:58.338905 RD_PRE = 0x0
2292 13:18:58.342156 WR_PRE = 0x1
2293 13:18:58.342227 WR_PST = 0x0
2294 13:18:58.345348 DBI_WR = 0x0
2295 13:18:58.345412 DBI_RD = 0x0
2296 13:18:58.348803 OTF = 0x1
2297 13:18:58.352094 ===================================
2298 13:18:58.359101 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2299 13:18:58.359181 ==
2300 13:18:58.362182 Dram Type= 6, Freq= 0, CH_0, rank 0
2301 13:18:58.365452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2302 13:18:58.365524 ==
2303 13:18:58.369332 [Duty_Offset_Calibration]
2304 13:18:58.369411 B0:2 B1:0 CA:3
2305 13:18:58.369473
2306 13:18:58.372568 [DutyScan_Calibration_Flow] k_type=0
2307 13:18:58.382437
2308 13:18:58.382549 ==CLK 0==
2309 13:18:58.385582 Final CLK duty delay cell = 0
2310 13:18:58.388773 [0] MAX Duty = 5062%(X100), DQS PI = 20
2311 13:18:58.391804 [0] MIN Duty = 4906%(X100), DQS PI = 54
2312 13:18:58.391913 [0] AVG Duty = 4984%(X100)
2313 13:18:58.395390
2314 13:18:58.399052 CH0 CLK Duty spec in!! Max-Min= 156%
2315 13:18:58.402170 [DutyScan_Calibration_Flow] ====Done====
2316 13:18:58.402247
2317 13:18:58.405421 [DutyScan_Calibration_Flow] k_type=1
2318 13:18:58.420203
2319 13:18:58.420288 ==DQS 0 ==
2320 13:18:58.424084 Final DQS duty delay cell = 0
2321 13:18:58.427337 [0] MAX Duty = 5062%(X100), DQS PI = 12
2322 13:18:58.430680 [0] MIN Duty = 4907%(X100), DQS PI = 2
2323 13:18:58.430795 [0] AVG Duty = 4984%(X100)
2324 13:18:58.433917
2325 13:18:58.433991 ==DQS 1 ==
2326 13:18:58.437180 Final DQS duty delay cell = -4
2327 13:18:58.440239 [-4] MAX Duty = 4969%(X100), DQS PI = 6
2328 13:18:58.443918 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2329 13:18:58.446914 [-4] AVG Duty = 4922%(X100)
2330 13:18:58.446983
2331 13:18:58.450805 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2332 13:18:58.450871
2333 13:18:58.454156 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2334 13:18:58.457328 [DutyScan_Calibration_Flow] ====Done====
2335 13:18:58.457399
2336 13:18:58.460585 [DutyScan_Calibration_Flow] k_type=3
2337 13:18:58.477743
2338 13:18:58.477828 ==DQM 0 ==
2339 13:18:58.481010 Final DQM duty delay cell = 0
2340 13:18:58.484247 [0] MAX Duty = 5124%(X100), DQS PI = 28
2341 13:18:58.488037 [0] MIN Duty = 4876%(X100), DQS PI = 0
2342 13:18:58.488111 [0] AVG Duty = 5000%(X100)
2343 13:18:58.491366
2344 13:18:58.491445 ==DQM 1 ==
2345 13:18:58.494665 Final DQM duty delay cell = 4
2346 13:18:58.497994 [4] MAX Duty = 5124%(X100), DQS PI = 52
2347 13:18:58.501188 [4] MIN Duty = 5000%(X100), DQS PI = 12
2348 13:18:58.504154 [4] AVG Duty = 5062%(X100)
2349 13:18:58.504229
2350 13:18:58.507746 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2351 13:18:58.507818
2352 13:18:58.511000 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2353 13:18:58.514269 [DutyScan_Calibration_Flow] ====Done====
2354 13:18:58.514340
2355 13:18:58.517431 [DutyScan_Calibration_Flow] k_type=2
2356 13:18:58.532745
2357 13:18:58.532819 ==DQ 0 ==
2358 13:18:58.535915 Final DQ duty delay cell = -4
2359 13:18:58.539673 [-4] MAX Duty = 5000%(X100), DQS PI = 12
2360 13:18:58.542849 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2361 13:18:58.546070 [-4] AVG Duty = 4953%(X100)
2362 13:18:58.546157
2363 13:18:58.546217 ==DQ 1 ==
2364 13:18:58.549781 Final DQ duty delay cell = -4
2365 13:18:58.553021 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2366 13:18:58.556285 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2367 13:18:58.556389 [-4] AVG Duty = 4922%(X100)
2368 13:18:58.559469
2369 13:18:58.562777 CH0 DQ 0 Duty spec in!! Max-Min= 93%
2370 13:18:58.562879
2371 13:18:58.566132 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2372 13:18:58.569415 [DutyScan_Calibration_Flow] ====Done====
2373 13:18:58.569489 ==
2374 13:18:58.572629 Dram Type= 6, Freq= 0, CH_1, rank 0
2375 13:18:58.576106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2376 13:18:58.576180 ==
2377 13:18:58.579827 [Duty_Offset_Calibration]
2378 13:18:58.579895 B0:1 B1:-2 CA:0
2379 13:18:58.579954
2380 13:18:58.582905 [DutyScan_Calibration_Flow] k_type=0
2381 13:18:58.593307
2382 13:18:58.593383 ==CLK 0==
2383 13:18:58.596598 Final CLK duty delay cell = 0
2384 13:18:58.599962 [0] MAX Duty = 5031%(X100), DQS PI = 18
2385 13:18:58.603267 [0] MIN Duty = 4844%(X100), DQS PI = 58
2386 13:18:58.603363 [0] AVG Duty = 4937%(X100)
2387 13:18:58.603452
2388 13:18:58.606476 CH1 CLK Duty spec in!! Max-Min= 187%
2389 13:18:58.613479 [DutyScan_Calibration_Flow] ====Done====
2390 13:18:58.613556
2391 13:18:58.616539 [DutyScan_Calibration_Flow] k_type=1
2392 13:18:58.631490
2393 13:18:58.631568 ==DQS 0 ==
2394 13:18:58.635208 Final DQS duty delay cell = -4
2395 13:18:58.638539 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2396 13:18:58.641747 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2397 13:18:58.644854 [-4] AVG Duty = 4953%(X100)
2398 13:18:58.644931
2399 13:18:58.644991 ==DQS 1 ==
2400 13:18:58.648056 Final DQS duty delay cell = 0
2401 13:18:58.651381 [0] MAX Duty = 5062%(X100), DQS PI = 0
2402 13:18:58.654575 [0] MIN Duty = 4875%(X100), DQS PI = 26
2403 13:18:58.658959 [0] AVG Duty = 4968%(X100)
2404 13:18:58.659055
2405 13:18:58.661523 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2406 13:18:58.661600
2407 13:18:58.664601 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2408 13:18:58.667974 [DutyScan_Calibration_Flow] ====Done====
2409 13:18:58.668074
2410 13:18:58.671214 [DutyScan_Calibration_Flow] k_type=3
2411 13:18:58.688447
2412 13:18:58.688552 ==DQM 0 ==
2413 13:18:58.691415 Final DQM duty delay cell = 0
2414 13:18:58.694570 [0] MAX Duty = 5000%(X100), DQS PI = 22
2415 13:18:58.698516 [0] MIN Duty = 4876%(X100), DQS PI = 4
2416 13:18:58.698612 [0] AVG Duty = 4938%(X100)
2417 13:18:58.701850
2418 13:18:58.701940 ==DQM 1 ==
2419 13:18:58.705181 Final DQM duty delay cell = 0
2420 13:18:58.708317 [0] MAX Duty = 5031%(X100), DQS PI = 36
2421 13:18:58.711541 [0] MIN Duty = 4907%(X100), DQS PI = 0
2422 13:18:58.711632 [0] AVG Duty = 4969%(X100)
2423 13:18:58.714582
2424 13:18:58.718448 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2425 13:18:58.718539
2426 13:18:58.721451 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2427 13:18:58.724560 [DutyScan_Calibration_Flow] ====Done====
2428 13:18:58.724654
2429 13:18:58.727845 [DutyScan_Calibration_Flow] k_type=2
2430 13:18:58.744695
2431 13:18:58.744798 ==DQ 0 ==
2432 13:18:58.747755 Final DQ duty delay cell = 0
2433 13:18:58.750970 [0] MAX Duty = 5062%(X100), DQS PI = 12
2434 13:18:58.754389 [0] MIN Duty = 4907%(X100), DQS PI = 56
2435 13:18:58.754486 [0] AVG Duty = 4984%(X100)
2436 13:18:58.757541
2437 13:18:58.757633 ==DQ 1 ==
2438 13:18:58.760774 Final DQ duty delay cell = 0
2439 13:18:58.764027 [0] MAX Duty = 5093%(X100), DQS PI = 20
2440 13:18:58.767845 [0] MIN Duty = 4938%(X100), DQS PI = 26
2441 13:18:58.767946 [0] AVG Duty = 5015%(X100)
2442 13:18:58.768032
2443 13:18:58.774322 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2444 13:18:58.774423
2445 13:18:58.777532 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2446 13:18:58.780868 [DutyScan_Calibration_Flow] ====Done====
2447 13:18:58.784264 nWR fixed to 30
2448 13:18:58.784343 [ModeRegInit_LP4] CH0 RK0
2449 13:18:58.787546 [ModeRegInit_LP4] CH0 RK1
2450 13:18:58.790888 [ModeRegInit_LP4] CH1 RK0
2451 13:18:58.794479 [ModeRegInit_LP4] CH1 RK1
2452 13:18:58.794573 match AC timing 7
2453 13:18:58.797667 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2454 13:18:58.801224 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2455 13:18:58.807882 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2456 13:18:58.811241 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2457 13:18:58.818273 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2458 13:18:58.818356 ==
2459 13:18:58.820984 Dram Type= 6, Freq= 0, CH_0, rank 0
2460 13:18:58.824601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2461 13:18:58.824688 ==
2462 13:18:58.831028 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2463 13:18:58.834246 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2464 13:18:58.844198 [CA 0] Center 40 (10~71) winsize 62
2465 13:18:58.848063 [CA 1] Center 39 (9~70) winsize 62
2466 13:18:58.851249 [CA 2] Center 36 (6~66) winsize 61
2467 13:18:58.854513 [CA 3] Center 35 (5~66) winsize 62
2468 13:18:58.858084 [CA 4] Center 34 (4~65) winsize 62
2469 13:18:58.860997 [CA 5] Center 33 (3~63) winsize 61
2470 13:18:58.861143
2471 13:18:58.864104 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2472 13:18:58.864218
2473 13:18:58.867358 [CATrainingPosCal] consider 1 rank data
2474 13:18:58.871213 u2DelayCellTimex100 = 270/100 ps
2475 13:18:58.874490 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2476 13:18:58.880985 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2477 13:18:58.884226 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2478 13:18:58.887552 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2479 13:18:58.890946 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2480 13:18:58.894365 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2481 13:18:58.894471
2482 13:18:58.897917 CA PerBit enable=1, Macro0, CA PI delay=33
2483 13:18:58.898056
2484 13:18:58.900710 [CBTSetCACLKResult] CA Dly = 33
2485 13:18:58.904262 CS Dly: 7 (0~38)
2486 13:18:58.904346 ==
2487 13:18:58.907303 Dram Type= 6, Freq= 0, CH_0, rank 1
2488 13:18:58.910851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2489 13:18:58.910962 ==
2490 13:18:58.914392 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2491 13:18:58.921078 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2492 13:18:58.930808 [CA 0] Center 40 (10~70) winsize 61
2493 13:18:58.933950 [CA 1] Center 39 (9~70) winsize 62
2494 13:18:58.937299 [CA 2] Center 35 (5~66) winsize 62
2495 13:18:58.940818 [CA 3] Center 35 (5~66) winsize 62
2496 13:18:58.943661 [CA 4] Center 34 (4~65) winsize 62
2497 13:18:58.947114 [CA 5] Center 33 (3~63) winsize 61
2498 13:18:58.947192
2499 13:18:58.950540 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2500 13:18:58.950631
2501 13:18:58.953914 [CATrainingPosCal] consider 2 rank data
2502 13:18:58.957233 u2DelayCellTimex100 = 270/100 ps
2503 13:18:58.960171 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2504 13:18:58.966747 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2505 13:18:58.970578 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2506 13:18:58.973709 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2507 13:18:58.976729 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2508 13:18:58.980487 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2509 13:18:58.980611
2510 13:18:58.983755 CA PerBit enable=1, Macro0, CA PI delay=33
2511 13:18:58.983834
2512 13:18:58.987037 [CBTSetCACLKResult] CA Dly = 33
2513 13:18:58.990450 CS Dly: 8 (0~40)
2514 13:18:58.990537
2515 13:18:58.993867 ----->DramcWriteLeveling(PI) begin...
2516 13:18:58.993942 ==
2517 13:18:58.996693 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 13:18:59.000241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 13:18:59.000345 ==
2520 13:18:59.003719 Write leveling (Byte 0): 32 => 32
2521 13:18:59.007089 Write leveling (Byte 1): 30 => 30
2522 13:18:59.010509 DramcWriteLeveling(PI) end<-----
2523 13:18:59.010594
2524 13:18:59.010660 ==
2525 13:18:59.014033 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 13:18:59.016868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 13:18:59.016946 ==
2528 13:18:59.020090 [Gating] SW mode calibration
2529 13:18:59.026906 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2530 13:18:59.033586 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2531 13:18:59.037024 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2532 13:18:59.040536 0 15 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2533 13:18:59.047122 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 13:18:59.050605 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 13:18:59.053218 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 13:18:59.060452 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 13:18:59.063178 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 13:18:59.066583 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
2539 13:18:59.070116 1 0 0 | B1->B0 | 3333 2c2c | 0 0 | (0 0) (1 0)
2540 13:18:59.076777 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2541 13:18:59.080088 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 13:18:59.083379 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 13:18:59.089835 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 13:18:59.093575 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 13:18:59.096777 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 13:18:59.103680 1 0 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
2547 13:18:59.107136 1 1 0 | B1->B0 | 2a2a 3939 | 0 1 | (0 0) (0 0)
2548 13:18:59.109895 1 1 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2549 13:18:59.116705 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 13:18:59.120215 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 13:18:59.123590 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 13:18:59.130349 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 13:18:59.133675 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 13:18:59.136824 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2555 13:18:59.143298 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2556 13:18:59.147077 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2557 13:18:59.150222 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 13:18:59.156942 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 13:18:59.159929 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 13:18:59.163567 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 13:18:59.170024 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 13:18:59.173410 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 13:18:59.176921 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 13:18:59.180040 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 13:18:59.186973 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 13:18:59.190363 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 13:18:59.193068 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 13:18:59.199987 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 13:18:59.203136 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 13:18:59.207141 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2571 13:18:59.213228 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2572 13:18:59.216623 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2573 13:18:59.219909 Total UI for P1: 0, mck2ui 16
2574 13:18:59.223406 best dqsien dly found for B0: ( 1, 3, 30)
2575 13:18:59.226816 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 13:18:59.229627 Total UI for P1: 0, mck2ui 16
2577 13:18:59.233017 best dqsien dly found for B1: ( 1, 4, 2)
2578 13:18:59.236417 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2579 13:18:59.239794 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2580 13:18:59.239904
2581 13:18:59.246528 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2582 13:18:59.249941 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2583 13:18:59.250042 [Gating] SW calibration Done
2584 13:18:59.253048 ==
2585 13:18:59.253123 Dram Type= 6, Freq= 0, CH_0, rank 0
2586 13:18:59.260080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2587 13:18:59.260192 ==
2588 13:18:59.260294 RX Vref Scan: 0
2589 13:18:59.260384
2590 13:18:59.263385 RX Vref 0 -> 0, step: 1
2591 13:18:59.263480
2592 13:18:59.266447 RX Delay -40 -> 252, step: 8
2593 13:18:59.269688 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2594 13:18:59.272961 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2595 13:18:59.276587 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2596 13:18:59.283263 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2597 13:18:59.286555 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2598 13:18:59.289625 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2599 13:18:59.293096 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2600 13:18:59.296650 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2601 13:18:59.300119 iDelay=200, Bit 8, Center 95 (16 ~ 175) 160
2602 13:18:59.306909 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2603 13:18:59.310054 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2604 13:18:59.313108 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2605 13:18:59.316354 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2606 13:18:59.320274 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2607 13:18:59.326374 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2608 13:18:59.329892 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2609 13:18:59.329996 ==
2610 13:18:59.333254 Dram Type= 6, Freq= 0, CH_0, rank 0
2611 13:18:59.336722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2612 13:18:59.336821 ==
2613 13:18:59.340021 DQS Delay:
2614 13:18:59.340120 DQS0 = 0, DQS1 = 0
2615 13:18:59.340219 DQM Delay:
2616 13:18:59.342807 DQM0 = 112, DQM1 = 104
2617 13:18:59.342900 DQ Delay:
2618 13:18:59.346163 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2619 13:18:59.350069 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2620 13:18:59.352921 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =99
2621 13:18:59.359909 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =111
2622 13:18:59.359990
2623 13:18:59.360052
2624 13:18:59.360109 ==
2625 13:18:59.363419 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 13:18:59.366543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 13:18:59.366639 ==
2628 13:18:59.366722
2629 13:18:59.366801
2630 13:18:59.369803 TX Vref Scan disable
2631 13:18:59.369904 == TX Byte 0 ==
2632 13:18:59.376227 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2633 13:18:59.379576 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2634 13:18:59.379694 == TX Byte 1 ==
2635 13:18:59.386577 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2636 13:18:59.390096 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2637 13:18:59.390210 ==
2638 13:18:59.393447 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 13:18:59.396001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 13:18:59.396103 ==
2641 13:18:59.409067 TX Vref=22, minBit 12, minWin=25, winSum=418
2642 13:18:59.412367 TX Vref=24, minBit 14, minWin=25, winSum=423
2643 13:18:59.415616 TX Vref=26, minBit 7, minWin=26, winSum=426
2644 13:18:59.419007 TX Vref=28, minBit 10, minWin=26, winSum=436
2645 13:18:59.422761 TX Vref=30, minBit 10, minWin=26, winSum=435
2646 13:18:59.428833 TX Vref=32, minBit 10, minWin=25, winSum=431
2647 13:18:59.432259 [TxChooseVref] Worse bit 10, Min win 26, Win sum 436, Final Vref 28
2648 13:18:59.432355
2649 13:18:59.435912 Final TX Range 1 Vref 28
2650 13:18:59.436019
2651 13:18:59.436115 ==
2652 13:18:59.439302 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 13:18:59.442074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 13:18:59.445644 ==
2655 13:18:59.445750
2656 13:18:59.445847
2657 13:18:59.445937 TX Vref Scan disable
2658 13:18:59.449748 == TX Byte 0 ==
2659 13:18:59.452989 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2660 13:18:59.455785 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2661 13:18:59.459200 == TX Byte 1 ==
2662 13:18:59.462628 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2663 13:18:59.465903 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2664 13:18:59.469270
2665 13:18:59.469367 [DATLAT]
2666 13:18:59.469454 Freq=1200, CH0 RK0
2667 13:18:59.469547
2668 13:18:59.472441 DATLAT Default: 0xd
2669 13:18:59.472534 0, 0xFFFF, sum = 0
2670 13:18:59.476206 1, 0xFFFF, sum = 0
2671 13:18:59.476307 2, 0xFFFF, sum = 0
2672 13:18:59.479450 3, 0xFFFF, sum = 0
2673 13:18:59.479520 4, 0xFFFF, sum = 0
2674 13:18:59.482625 5, 0xFFFF, sum = 0
2675 13:18:59.485883 6, 0xFFFF, sum = 0
2676 13:18:59.485990 7, 0xFFFF, sum = 0
2677 13:18:59.489141 8, 0xFFFF, sum = 0
2678 13:18:59.489237 9, 0xFFFF, sum = 0
2679 13:18:59.492471 10, 0xFFFF, sum = 0
2680 13:18:59.492570 11, 0xFFFF, sum = 0
2681 13:18:59.495866 12, 0x0, sum = 1
2682 13:18:59.495967 13, 0x0, sum = 2
2683 13:18:59.499257 14, 0x0, sum = 3
2684 13:18:59.499350 15, 0x0, sum = 4
2685 13:18:59.499451 best_step = 13
2686 13:18:59.499537
2687 13:18:59.502439 ==
2688 13:18:59.505829 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 13:18:59.509176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 13:18:59.509281 ==
2691 13:18:59.509379 RX Vref Scan: 1
2692 13:18:59.509463
2693 13:18:59.512680 Set Vref Range= 32 -> 127
2694 13:18:59.512776
2695 13:18:59.516048 RX Vref 32 -> 127, step: 1
2696 13:18:59.516146
2697 13:18:59.519497 RX Delay -37 -> 252, step: 4
2698 13:18:59.519599
2699 13:18:59.522936 Set Vref, RX VrefLevel [Byte0]: 32
2700 13:18:59.526023 [Byte1]: 32
2701 13:18:59.526121
2702 13:18:59.529139 Set Vref, RX VrefLevel [Byte0]: 33
2703 13:18:59.532352 [Byte1]: 33
2704 13:18:59.536336
2705 13:18:59.536439 Set Vref, RX VrefLevel [Byte0]: 34
2706 13:18:59.539422 [Byte1]: 34
2707 13:18:59.544518
2708 13:18:59.544615 Set Vref, RX VrefLevel [Byte0]: 35
2709 13:18:59.547117 [Byte1]: 35
2710 13:18:59.551916
2711 13:18:59.552013 Set Vref, RX VrefLevel [Byte0]: 36
2712 13:18:59.555270 [Byte1]: 36
2713 13:18:59.559951
2714 13:18:59.560060 Set Vref, RX VrefLevel [Byte0]: 37
2715 13:18:59.563280 [Byte1]: 37
2716 13:18:59.567958
2717 13:18:59.568052 Set Vref, RX VrefLevel [Byte0]: 38
2718 13:18:59.571367 [Byte1]: 38
2719 13:18:59.576331
2720 13:18:59.576428 Set Vref, RX VrefLevel [Byte0]: 39
2721 13:18:59.579515 [Byte1]: 39
2722 13:18:59.584047
2723 13:18:59.584144 Set Vref, RX VrefLevel [Byte0]: 40
2724 13:18:59.587158 [Byte1]: 40
2725 13:18:59.592228
2726 13:18:59.592329 Set Vref, RX VrefLevel [Byte0]: 41
2727 13:18:59.595475 [Byte1]: 41
2728 13:18:59.600135
2729 13:18:59.600238 Set Vref, RX VrefLevel [Byte0]: 42
2730 13:18:59.603343 [Byte1]: 42
2731 13:18:59.608208
2732 13:18:59.608281 Set Vref, RX VrefLevel [Byte0]: 43
2733 13:18:59.610993 [Byte1]: 43
2734 13:18:59.615900
2735 13:18:59.615973 Set Vref, RX VrefLevel [Byte0]: 44
2736 13:18:59.619346 [Byte1]: 44
2737 13:18:59.624097
2738 13:18:59.624198 Set Vref, RX VrefLevel [Byte0]: 45
2739 13:18:59.627626 [Byte1]: 45
2740 13:18:59.632202
2741 13:18:59.632304 Set Vref, RX VrefLevel [Byte0]: 46
2742 13:18:59.635465 [Byte1]: 46
2743 13:18:59.640294
2744 13:18:59.640401 Set Vref, RX VrefLevel [Byte0]: 47
2745 13:18:59.643030 [Byte1]: 47
2746 13:18:59.648206
2747 13:18:59.648308 Set Vref, RX VrefLevel [Byte0]: 48
2748 13:18:59.651556 [Byte1]: 48
2749 13:18:59.656350
2750 13:18:59.656429 Set Vref, RX VrefLevel [Byte0]: 49
2751 13:18:59.659098 [Byte1]: 49
2752 13:18:59.663681
2753 13:18:59.663755 Set Vref, RX VrefLevel [Byte0]: 50
2754 13:18:59.667115 [Byte1]: 50
2755 13:18:59.671979
2756 13:18:59.672072 Set Vref, RX VrefLevel [Byte0]: 51
2757 13:18:59.675408 [Byte1]: 51
2758 13:18:59.680287
2759 13:18:59.680397 Set Vref, RX VrefLevel [Byte0]: 52
2760 13:18:59.683577 [Byte1]: 52
2761 13:18:59.687728
2762 13:18:59.687829 Set Vref, RX VrefLevel [Byte0]: 53
2763 13:18:59.691232 [Byte1]: 53
2764 13:18:59.695747
2765 13:18:59.695854 Set Vref, RX VrefLevel [Byte0]: 54
2766 13:18:59.699138 [Byte1]: 54
2767 13:18:59.704118
2768 13:18:59.704193 Set Vref, RX VrefLevel [Byte0]: 55
2769 13:18:59.707080 [Byte1]: 55
2770 13:18:59.711889
2771 13:18:59.711998 Set Vref, RX VrefLevel [Byte0]: 56
2772 13:18:59.715470 [Byte1]: 56
2773 13:18:59.719981
2774 13:18:59.720093 Set Vref, RX VrefLevel [Byte0]: 57
2775 13:18:59.723349 [Byte1]: 57
2776 13:18:59.728133
2777 13:18:59.728208 Set Vref, RX VrefLevel [Byte0]: 58
2778 13:18:59.731587 [Byte1]: 58
2779 13:18:59.736222
2780 13:18:59.736298 Set Vref, RX VrefLevel [Byte0]: 59
2781 13:18:59.739431 [Byte1]: 59
2782 13:18:59.744193
2783 13:18:59.744293 Set Vref, RX VrefLevel [Byte0]: 60
2784 13:18:59.746945 [Byte1]: 60
2785 13:18:59.751661
2786 13:18:59.751766 Set Vref, RX VrefLevel [Byte0]: 61
2787 13:18:59.755220 [Byte1]: 61
2788 13:18:59.760001
2789 13:18:59.760098 Set Vref, RX VrefLevel [Byte0]: 62
2790 13:18:59.763417 [Byte1]: 62
2791 13:18:59.768086
2792 13:18:59.768174 Set Vref, RX VrefLevel [Byte0]: 63
2793 13:18:59.771313 [Byte1]: 63
2794 13:18:59.775980
2795 13:18:59.776106 Set Vref, RX VrefLevel [Byte0]: 64
2796 13:18:59.779476 [Byte1]: 64
2797 13:18:59.784315
2798 13:18:59.784425 Set Vref, RX VrefLevel [Byte0]: 65
2799 13:18:59.787185 [Byte1]: 65
2800 13:18:59.791919
2801 13:18:59.792028 Set Vref, RX VrefLevel [Byte0]: 66
2802 13:18:59.795393 [Byte1]: 66
2803 13:18:59.800142
2804 13:18:59.800229 Set Vref, RX VrefLevel [Byte0]: 67
2805 13:18:59.803381 [Byte1]: 67
2806 13:18:59.808289
2807 13:18:59.808393 Set Vref, RX VrefLevel [Byte0]: 68
2808 13:18:59.811502 [Byte1]: 68
2809 13:18:59.815764
2810 13:18:59.815865 Set Vref, RX VrefLevel [Byte0]: 69
2811 13:18:59.819381 [Byte1]: 69
2812 13:18:59.823791
2813 13:18:59.823901 Set Vref, RX VrefLevel [Byte0]: 70
2814 13:18:59.826985 [Byte1]: 70
2815 13:18:59.831954
2816 13:18:59.832060 Set Vref, RX VrefLevel [Byte0]: 71
2817 13:18:59.835403 [Byte1]: 71
2818 13:18:59.840178
2819 13:18:59.840254 Set Vref, RX VrefLevel [Byte0]: 72
2820 13:18:59.843524 [Byte1]: 72
2821 13:18:59.847664
2822 13:18:59.847764 Set Vref, RX VrefLevel [Byte0]: 73
2823 13:18:59.851164 [Byte1]: 73
2824 13:18:59.855818
2825 13:18:59.855914 Set Vref, RX VrefLevel [Byte0]: 74
2826 13:18:59.859030 [Byte1]: 74
2827 13:18:59.863809
2828 13:18:59.863911 Final RX Vref Byte 0 = 61 to rank0
2829 13:18:59.867777 Final RX Vref Byte 1 = 53 to rank0
2830 13:18:59.871123 Final RX Vref Byte 0 = 61 to rank1
2831 13:18:59.873881 Final RX Vref Byte 1 = 53 to rank1==
2832 13:18:59.877356 Dram Type= 6, Freq= 0, CH_0, rank 0
2833 13:18:59.880904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2834 13:18:59.884323 ==
2835 13:18:59.884425 DQS Delay:
2836 13:18:59.884513 DQS0 = 0, DQS1 = 0
2837 13:18:59.887974 DQM Delay:
2838 13:18:59.888078 DQM0 = 112, DQM1 = 101
2839 13:18:59.890585 DQ Delay:
2840 13:18:59.894190 DQ0 =112, DQ1 =112, DQ2 =112, DQ3 =108
2841 13:18:59.897485 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2842 13:18:59.900918 DQ8 =92, DQ9 =86, DQ10 =104, DQ11 =94
2843 13:18:59.904341 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =110
2844 13:18:59.904437
2845 13:18:59.904524
2846 13:18:59.911059 [DQSOSCAuto] RK0, (LSB)MR18= 0xfefd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
2847 13:18:59.914243 CH0 RK0: MR19=303, MR18=FEFD
2848 13:18:59.920791 CH0_RK0: MR19=0x303, MR18=0xFEFD, DQSOSC=410, MR23=63, INC=39, DEC=26
2849 13:18:59.920867
2850 13:18:59.923761 ----->DramcWriteLeveling(PI) begin...
2851 13:18:59.923858 ==
2852 13:18:59.927452 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 13:18:59.930484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 13:18:59.930588 ==
2855 13:18:59.933828 Write leveling (Byte 0): 34 => 34
2856 13:18:59.937105 Write leveling (Byte 1): 30 => 30
2857 13:18:59.940849 DramcWriteLeveling(PI) end<-----
2858 13:18:59.940952
2859 13:18:59.941051 ==
2860 13:18:59.943952 Dram Type= 6, Freq= 0, CH_0, rank 1
2861 13:18:59.947422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2862 13:18:59.951079 ==
2863 13:18:59.951182 [Gating] SW mode calibration
2864 13:18:59.960546 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2865 13:18:59.963821 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2866 13:18:59.967624 0 15 0 | B1->B0 | 2423 3434 | 1 0 | (0 0) (0 0)
2867 13:18:59.974137 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2868 13:18:59.977398 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2869 13:18:59.980981 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2870 13:18:59.987151 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2871 13:18:59.990582 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2872 13:18:59.993984 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2873 13:19:00.000775 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2874 13:19:00.004268 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
2875 13:19:00.007712 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2876 13:19:00.014417 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2877 13:19:00.017180 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2878 13:19:00.021014 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2879 13:19:00.027193 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2880 13:19:00.030486 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2881 13:19:00.034144 1 0 28 | B1->B0 | 2424 4343 | 0 0 | (0 0) (0 0)
2882 13:19:00.040915 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2883 13:19:00.043901 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 13:19:00.047200 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 13:19:00.050553 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 13:19:00.057325 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 13:19:00.061012 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 13:19:00.064229 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 13:19:00.070816 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2890 13:19:00.074021 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 13:19:00.077190 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 13:19:00.083971 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 13:19:00.087359 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 13:19:00.090774 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 13:19:00.097622 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 13:19:00.101045 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 13:19:00.104450 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 13:19:00.111259 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 13:19:00.114043 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 13:19:00.117491 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 13:19:00.120968 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 13:19:00.127498 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 13:19:00.130678 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 13:19:00.134035 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 13:19:00.141151 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2906 13:19:00.144558 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2907 13:19:00.147869 Total UI for P1: 0, mck2ui 16
2908 13:19:00.151013 best dqsien dly found for B0: ( 1, 3, 28)
2909 13:19:00.154039 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 13:19:00.157906 Total UI for P1: 0, mck2ui 16
2911 13:19:00.161147 best dqsien dly found for B1: ( 1, 4, 0)
2912 13:19:00.164295 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2913 13:19:00.167363 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2914 13:19:00.167474
2915 13:19:00.174027 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2916 13:19:00.177994 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2917 13:19:00.178127 [Gating] SW calibration Done
2918 13:19:00.181402 ==
2919 13:19:00.181498 Dram Type= 6, Freq= 0, CH_0, rank 1
2920 13:19:00.187893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2921 13:19:00.188003 ==
2922 13:19:00.188066 RX Vref Scan: 0
2923 13:19:00.188135
2924 13:19:00.191014 RX Vref 0 -> 0, step: 1
2925 13:19:00.191116
2926 13:19:00.194713 RX Delay -40 -> 252, step: 8
2927 13:19:00.197380 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2928 13:19:00.200722 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2929 13:19:00.204215 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2930 13:19:00.210857 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2931 13:19:00.214316 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2932 13:19:00.217717 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2933 13:19:00.221114 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2934 13:19:00.224450 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2935 13:19:00.231155 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2936 13:19:00.234351 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2937 13:19:00.237591 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2938 13:19:00.240939 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2939 13:19:00.244297 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2940 13:19:00.250731 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2941 13:19:00.254419 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2942 13:19:00.257404 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2943 13:19:00.257483 ==
2944 13:19:00.260571 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 13:19:00.264165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 13:19:00.264254 ==
2947 13:19:00.267301 DQS Delay:
2948 13:19:00.267380 DQS0 = 0, DQS1 = 0
2949 13:19:00.271036 DQM Delay:
2950 13:19:00.271134 DQM0 = 112, DQM1 = 101
2951 13:19:00.271206 DQ Delay:
2952 13:19:00.274479 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2953 13:19:00.277612 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2954 13:19:00.280905 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2955 13:19:00.287163 DQ12 =111, DQ13 =107, DQ14 =111, DQ15 =107
2956 13:19:00.287260
2957 13:19:00.287332
2958 13:19:00.287390 ==
2959 13:19:00.290507 Dram Type= 6, Freq= 0, CH_0, rank 1
2960 13:19:00.293839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2961 13:19:00.293921 ==
2962 13:19:00.293982
2963 13:19:00.294038
2964 13:19:00.297593 TX Vref Scan disable
2965 13:19:00.297664 == TX Byte 0 ==
2966 13:19:00.303891 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2967 13:19:00.307221 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2968 13:19:00.307331 == TX Byte 1 ==
2969 13:19:00.313953 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2970 13:19:00.317443 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2971 13:19:00.317557 ==
2972 13:19:00.320915 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 13:19:00.324339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 13:19:00.324448 ==
2975 13:19:00.337154 TX Vref=22, minBit 13, minWin=25, winSum=425
2976 13:19:00.340196 TX Vref=24, minBit 2, minWin=26, winSum=431
2977 13:19:00.344051 TX Vref=26, minBit 0, minWin=27, winSum=434
2978 13:19:00.347258 TX Vref=28, minBit 8, minWin=26, winSum=437
2979 13:19:00.350474 TX Vref=30, minBit 8, minWin=26, winSum=440
2980 13:19:00.357187 TX Vref=32, minBit 8, minWin=26, winSum=438
2981 13:19:00.360602 [TxChooseVref] Worse bit 0, Min win 27, Win sum 434, Final Vref 26
2982 13:19:00.360704
2983 13:19:00.363950 Final TX Range 1 Vref 26
2984 13:19:00.364046
2985 13:19:00.364131 ==
2986 13:19:00.367315 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 13:19:00.370510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 13:19:00.373554 ==
2989 13:19:00.373652
2990 13:19:00.373737
2991 13:19:00.373821 TX Vref Scan disable
2992 13:19:00.377208 == TX Byte 0 ==
2993 13:19:00.380382 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2994 13:19:00.383537 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2995 13:19:00.386917 == TX Byte 1 ==
2996 13:19:00.390688 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2997 13:19:00.397199 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2998 13:19:00.397293
2999 13:19:00.397360 [DATLAT]
3000 13:19:00.397417 Freq=1200, CH0 RK1
3001 13:19:00.397471
3002 13:19:00.400199 DATLAT Default: 0xd
3003 13:19:00.400298 0, 0xFFFF, sum = 0
3004 13:19:00.403576 1, 0xFFFF, sum = 0
3005 13:19:00.403648 2, 0xFFFF, sum = 0
3006 13:19:00.407201 3, 0xFFFF, sum = 0
3007 13:19:00.410346 4, 0xFFFF, sum = 0
3008 13:19:00.410424 5, 0xFFFF, sum = 0
3009 13:19:00.413518 6, 0xFFFF, sum = 0
3010 13:19:00.413593 7, 0xFFFF, sum = 0
3011 13:19:00.416960 8, 0xFFFF, sum = 0
3012 13:19:00.417059 9, 0xFFFF, sum = 0
3013 13:19:00.420395 10, 0xFFFF, sum = 0
3014 13:19:00.420504 11, 0xFFFF, sum = 0
3015 13:19:00.423827 12, 0x0, sum = 1
3016 13:19:00.423935 13, 0x0, sum = 2
3017 13:19:00.427235 14, 0x0, sum = 3
3018 13:19:00.427341 15, 0x0, sum = 4
3019 13:19:00.427430 best_step = 13
3020 13:19:00.430271
3021 13:19:00.430358 ==
3022 13:19:00.433452 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 13:19:00.436826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 13:19:00.436930 ==
3025 13:19:00.437023 RX Vref Scan: 0
3026 13:19:00.437108
3027 13:19:00.440246 RX Vref 0 -> 0, step: 1
3028 13:19:00.440342
3029 13:19:00.443669 RX Delay -37 -> 252, step: 4
3030 13:19:00.447064 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3031 13:19:00.453428 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3032 13:19:00.456601 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3033 13:19:00.460248 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3034 13:19:00.463606 iDelay=195, Bit 4, Center 110 (39 ~ 182) 144
3035 13:19:00.466399 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3036 13:19:00.473103 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3037 13:19:00.476515 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3038 13:19:00.479710 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3039 13:19:00.483358 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3040 13:19:00.486308 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3041 13:19:00.493141 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3042 13:19:00.496213 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3043 13:19:00.500253 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3044 13:19:00.503185 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3045 13:19:00.506234 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3046 13:19:00.509818 ==
3047 13:19:00.512825 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 13:19:00.516296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 13:19:00.516412 ==
3050 13:19:00.516498 DQS Delay:
3051 13:19:00.519427 DQS0 = 0, DQS1 = 0
3052 13:19:00.519537 DQM Delay:
3053 13:19:00.523198 DQM0 = 110, DQM1 = 101
3054 13:19:00.523305 DQ Delay:
3055 13:19:00.526561 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3056 13:19:00.530011 DQ4 =110, DQ5 =100, DQ6 =120, DQ7 =118
3057 13:19:00.533221 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3058 13:19:00.536008 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3059 13:19:00.536102
3060 13:19:00.536189
3061 13:19:00.546233 [DQSOSCAuto] RK1, (LSB)MR18= 0x15fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 401 ps
3062 13:19:00.549615 CH0 RK1: MR19=403, MR18=15FE
3063 13:19:00.552905 CH0_RK1: MR19=0x403, MR18=0x15FE, DQSOSC=401, MR23=63, INC=40, DEC=27
3064 13:19:00.556295 [RxdqsGatingPostProcess] freq 1200
3065 13:19:00.562770 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3066 13:19:00.565936 best DQS0 dly(2T, 0.5T) = (0, 11)
3067 13:19:00.569495 best DQS1 dly(2T, 0.5T) = (0, 12)
3068 13:19:00.572722 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3069 13:19:00.576249 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3070 13:19:00.578980 best DQS0 dly(2T, 0.5T) = (0, 11)
3071 13:19:00.582384 best DQS1 dly(2T, 0.5T) = (0, 12)
3072 13:19:00.585685 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3073 13:19:00.588945 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3074 13:19:00.589035 Pre-setting of DQS Precalculation
3075 13:19:00.595810 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3076 13:19:00.595917 ==
3077 13:19:00.599144 Dram Type= 6, Freq= 0, CH_1, rank 0
3078 13:19:00.602119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3079 13:19:00.602208 ==
3080 13:19:00.609277 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3081 13:19:00.615761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3082 13:19:00.623488 [CA 0] Center 37 (7~67) winsize 61
3083 13:19:00.626339 [CA 1] Center 37 (7~68) winsize 62
3084 13:19:00.629782 [CA 2] Center 34 (4~64) winsize 61
3085 13:19:00.633375 [CA 3] Center 34 (4~64) winsize 61
3086 13:19:00.636493 [CA 4] Center 34 (4~64) winsize 61
3087 13:19:00.639787 [CA 5] Center 33 (3~63) winsize 61
3088 13:19:00.639861
3089 13:19:00.643156 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3090 13:19:00.643282
3091 13:19:00.646604 [CATrainingPosCal] consider 1 rank data
3092 13:19:00.649997 u2DelayCellTimex100 = 270/100 ps
3093 13:19:00.653385 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3094 13:19:00.659565 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3095 13:19:00.663702 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3096 13:19:00.666759 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3097 13:19:00.669522 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3098 13:19:00.672806 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3099 13:19:00.672906
3100 13:19:00.676621 CA PerBit enable=1, Macro0, CA PI delay=33
3101 13:19:00.676723
3102 13:19:00.679805 [CBTSetCACLKResult] CA Dly = 33
3103 13:19:00.679909 CS Dly: 6 (0~37)
3104 13:19:00.683228 ==
3105 13:19:00.686658 Dram Type= 6, Freq= 0, CH_1, rank 1
3106 13:19:00.689984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 13:19:00.690084 ==
3108 13:19:00.693399 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3109 13:19:00.699667 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3110 13:19:00.708553 [CA 0] Center 37 (7~67) winsize 61
3111 13:19:00.712369 [CA 1] Center 37 (7~68) winsize 62
3112 13:19:00.715659 [CA 2] Center 34 (4~65) winsize 62
3113 13:19:00.719116 [CA 3] Center 33 (3~64) winsize 62
3114 13:19:00.721820 [CA 4] Center 34 (4~65) winsize 62
3115 13:19:00.725298 [CA 5] Center 32 (2~63) winsize 62
3116 13:19:00.725377
3117 13:19:00.728685 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3118 13:19:00.728763
3119 13:19:00.732031 [CATrainingPosCal] consider 2 rank data
3120 13:19:00.735276 u2DelayCellTimex100 = 270/100 ps
3121 13:19:00.738522 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3122 13:19:00.745195 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3123 13:19:00.748590 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3124 13:19:00.751927 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3125 13:19:00.754759 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3126 13:19:00.758036 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3127 13:19:00.758125
3128 13:19:00.761467 CA PerBit enable=1, Macro0, CA PI delay=33
3129 13:19:00.761539
3130 13:19:00.764938 [CBTSetCACLKResult] CA Dly = 33
3131 13:19:00.768136 CS Dly: 7 (0~40)
3132 13:19:00.768214
3133 13:19:00.771428 ----->DramcWriteLeveling(PI) begin...
3134 13:19:00.771536 ==
3135 13:19:00.774794 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 13:19:00.778265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 13:19:00.778343 ==
3138 13:19:00.781261 Write leveling (Byte 0): 26 => 26
3139 13:19:00.784955 Write leveling (Byte 1): 30 => 30
3140 13:19:00.788026 DramcWriteLeveling(PI) end<-----
3141 13:19:00.788097
3142 13:19:00.788163 ==
3143 13:19:00.791464 Dram Type= 6, Freq= 0, CH_1, rank 0
3144 13:19:00.794970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3145 13:19:00.795042 ==
3146 13:19:00.798217 [Gating] SW mode calibration
3147 13:19:00.804808 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3148 13:19:00.811321 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3149 13:19:00.814654 0 15 0 | B1->B0 | 3131 2d2d | 0 0 | (0 0) (0 0)
3150 13:19:00.818023 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 13:19:00.824275 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3152 13:19:00.827403 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3153 13:19:00.830801 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3154 13:19:00.837635 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3155 13:19:00.840826 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3156 13:19:00.844282 0 15 28 | B1->B0 | 2727 2f2f | 0 0 | (0 0) (0 1)
3157 13:19:00.850960 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3158 13:19:00.854168 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 13:19:00.857856 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 13:19:00.864044 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3161 13:19:00.867388 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3162 13:19:00.870806 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3163 13:19:00.877590 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3164 13:19:00.880489 1 0 28 | B1->B0 | 4343 3e3e | 0 1 | (0 0) (0 0)
3165 13:19:00.883937 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 13:19:00.890577 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 13:19:00.894039 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 13:19:00.897464 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 13:19:00.903825 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 13:19:00.907641 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 13:19:00.910853 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3172 13:19:00.917694 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3173 13:19:00.920297 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3174 13:19:00.923631 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 13:19:00.930882 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 13:19:00.933931 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 13:19:00.936951 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 13:19:00.941024 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 13:19:00.947666 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 13:19:00.950401 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 13:19:00.953816 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 13:19:00.960810 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 13:19:00.963414 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 13:19:00.966826 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 13:19:00.973492 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 13:19:00.977280 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 13:19:00.980482 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 13:19:00.986884 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3189 13:19:00.990378 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3190 13:19:00.993765 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 13:19:00.997076 Total UI for P1: 0, mck2ui 16
3192 13:19:01.000410 best dqsien dly found for B0: ( 1, 3, 30)
3193 13:19:01.003854 Total UI for P1: 0, mck2ui 16
3194 13:19:01.006687 best dqsien dly found for B1: ( 1, 3, 30)
3195 13:19:01.009867 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3196 13:19:01.013098 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3197 13:19:01.016952
3198 13:19:01.020238 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3199 13:19:01.023050 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3200 13:19:01.026574 [Gating] SW calibration Done
3201 13:19:01.026655 ==
3202 13:19:01.029884 Dram Type= 6, Freq= 0, CH_1, rank 0
3203 13:19:01.033413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3204 13:19:01.033518 ==
3205 13:19:01.033608 RX Vref Scan: 0
3206 13:19:01.033690
3207 13:19:01.036591 RX Vref 0 -> 0, step: 1
3208 13:19:01.036681
3209 13:19:01.040031 RX Delay -40 -> 252, step: 8
3210 13:19:01.043266 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3211 13:19:01.046343 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3212 13:19:01.053036 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3213 13:19:01.056601 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3214 13:19:01.060025 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3215 13:19:01.062665 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3216 13:19:01.066118 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3217 13:19:01.073103 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3218 13:19:01.075969 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3219 13:19:01.079730 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3220 13:19:01.082920 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3221 13:19:01.085959 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3222 13:19:01.093056 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3223 13:19:01.095713 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3224 13:19:01.099091 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3225 13:19:01.102490 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3226 13:19:01.102569 ==
3227 13:19:01.105743 Dram Type= 6, Freq= 0, CH_1, rank 0
3228 13:19:01.112592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3229 13:19:01.112668 ==
3230 13:19:01.112728 DQS Delay:
3231 13:19:01.115988 DQS0 = 0, DQS1 = 0
3232 13:19:01.116087 DQM Delay:
3233 13:19:01.119225 DQM0 = 114, DQM1 = 105
3234 13:19:01.119302 DQ Delay:
3235 13:19:01.122468 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3236 13:19:01.125713 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3237 13:19:01.129010 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3238 13:19:01.132369 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3239 13:19:01.132446
3240 13:19:01.132503
3241 13:19:01.132557 ==
3242 13:19:01.135883 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 13:19:01.141985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 13:19:01.142065 ==
3245 13:19:01.142133
3246 13:19:01.142189
3247 13:19:01.142242 TX Vref Scan disable
3248 13:19:01.145507 == TX Byte 0 ==
3249 13:19:01.149019 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3250 13:19:01.155711 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3251 13:19:01.155790 == TX Byte 1 ==
3252 13:19:01.158917 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3253 13:19:01.165099 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3254 13:19:01.165177 ==
3255 13:19:01.168697 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 13:19:01.172132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 13:19:01.172204 ==
3258 13:19:01.183218 TX Vref=22, minBit 11, minWin=24, winSum=413
3259 13:19:01.186696 TX Vref=24, minBit 8, minWin=24, winSum=419
3260 13:19:01.190155 TX Vref=26, minBit 8, minWin=25, winSum=427
3261 13:19:01.193597 TX Vref=28, minBit 1, minWin=26, winSum=428
3262 13:19:01.196788 TX Vref=30, minBit 1, minWin=26, winSum=432
3263 13:19:01.203428 TX Vref=32, minBit 1, minWin=26, winSum=426
3264 13:19:01.206285 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 30
3265 13:19:01.206387
3266 13:19:01.209643 Final TX Range 1 Vref 30
3267 13:19:01.209712
3268 13:19:01.209768 ==
3269 13:19:01.213040 Dram Type= 6, Freq= 0, CH_1, rank 0
3270 13:19:01.216665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3271 13:19:01.219984 ==
3272 13:19:01.220054
3273 13:19:01.220110
3274 13:19:01.220164 TX Vref Scan disable
3275 13:19:01.223132 == TX Byte 0 ==
3276 13:19:01.226419 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3277 13:19:01.233644 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3278 13:19:01.233717 == TX Byte 1 ==
3279 13:19:01.236345 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3280 13:19:01.243288 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3281 13:19:01.243379
3282 13:19:01.243440 [DATLAT]
3283 13:19:01.243495 Freq=1200, CH1 RK0
3284 13:19:01.243548
3285 13:19:01.246768 DATLAT Default: 0xd
3286 13:19:01.246845 0, 0xFFFF, sum = 0
3287 13:19:01.250137 1, 0xFFFF, sum = 0
3288 13:19:01.250215 2, 0xFFFF, sum = 0
3289 13:19:01.253470 3, 0xFFFF, sum = 0
3290 13:19:01.256260 4, 0xFFFF, sum = 0
3291 13:19:01.256339 5, 0xFFFF, sum = 0
3292 13:19:01.259643 6, 0xFFFF, sum = 0
3293 13:19:01.259722 7, 0xFFFF, sum = 0
3294 13:19:01.263182 8, 0xFFFF, sum = 0
3295 13:19:01.263261 9, 0xFFFF, sum = 0
3296 13:19:01.266461 10, 0xFFFF, sum = 0
3297 13:19:01.266539 11, 0xFFFF, sum = 0
3298 13:19:01.269562 12, 0x0, sum = 1
3299 13:19:01.269641 13, 0x0, sum = 2
3300 13:19:01.273273 14, 0x0, sum = 3
3301 13:19:01.273349 15, 0x0, sum = 4
3302 13:19:01.276416 best_step = 13
3303 13:19:01.276518
3304 13:19:01.276612 ==
3305 13:19:01.279602 Dram Type= 6, Freq= 0, CH_1, rank 0
3306 13:19:01.282955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3307 13:19:01.283033 ==
3308 13:19:01.283093 RX Vref Scan: 1
3309 13:19:01.283148
3310 13:19:01.286457 Set Vref Range= 32 -> 127
3311 13:19:01.286541
3312 13:19:01.289826 RX Vref 32 -> 127, step: 1
3313 13:19:01.289903
3314 13:19:01.292706 RX Delay -21 -> 252, step: 4
3315 13:19:01.292774
3316 13:19:01.296190 Set Vref, RX VrefLevel [Byte0]: 32
3317 13:19:01.299631 [Byte1]: 32
3318 13:19:01.299708
3319 13:19:01.303085 Set Vref, RX VrefLevel [Byte0]: 33
3320 13:19:01.306503 [Byte1]: 33
3321 13:19:01.309980
3322 13:19:01.310056 Set Vref, RX VrefLevel [Byte0]: 34
3323 13:19:01.313137 [Byte1]: 34
3324 13:19:01.317814
3325 13:19:01.317910 Set Vref, RX VrefLevel [Byte0]: 35
3326 13:19:01.320908 [Byte1]: 35
3327 13:19:01.325692
3328 13:19:01.325762 Set Vref, RX VrefLevel [Byte0]: 36
3329 13:19:01.328628 [Byte1]: 36
3330 13:19:01.333191
3331 13:19:01.333303 Set Vref, RX VrefLevel [Byte0]: 37
3332 13:19:01.336647 [Byte1]: 37
3333 13:19:01.341153
3334 13:19:01.341229 Set Vref, RX VrefLevel [Byte0]: 38
3335 13:19:01.344704 [Byte1]: 38
3336 13:19:01.349528
3337 13:19:01.349614 Set Vref, RX VrefLevel [Byte0]: 39
3338 13:19:01.352899 [Byte1]: 39
3339 13:19:01.357035
3340 13:19:01.357135 Set Vref, RX VrefLevel [Byte0]: 40
3341 13:19:01.360600 [Byte1]: 40
3342 13:19:01.365322
3343 13:19:01.365397 Set Vref, RX VrefLevel [Byte0]: 41
3344 13:19:01.368741 [Byte1]: 41
3345 13:19:01.372770
3346 13:19:01.376026 Set Vref, RX VrefLevel [Byte0]: 42
3347 13:19:01.379935 [Byte1]: 42
3348 13:19:01.380034
3349 13:19:01.383234 Set Vref, RX VrefLevel [Byte0]: 43
3350 13:19:01.386324 [Byte1]: 43
3351 13:19:01.386418
3352 13:19:01.389583 Set Vref, RX VrefLevel [Byte0]: 44
3353 13:19:01.393055 [Byte1]: 44
3354 13:19:01.397163
3355 13:19:01.397239 Set Vref, RX VrefLevel [Byte0]: 45
3356 13:19:01.400031 [Byte1]: 45
3357 13:19:01.404900
3358 13:19:01.404994 Set Vref, RX VrefLevel [Byte0]: 46
3359 13:19:01.408319 [Byte1]: 46
3360 13:19:01.412472
3361 13:19:01.412577 Set Vref, RX VrefLevel [Byte0]: 47
3362 13:19:01.415850 [Byte1]: 47
3363 13:19:01.420618
3364 13:19:01.420729 Set Vref, RX VrefLevel [Byte0]: 48
3365 13:19:01.424019 [Byte1]: 48
3366 13:19:01.428657
3367 13:19:01.428754 Set Vref, RX VrefLevel [Byte0]: 49
3368 13:19:01.432190 [Byte1]: 49
3369 13:19:01.436233
3370 13:19:01.436328 Set Vref, RX VrefLevel [Byte0]: 50
3371 13:19:01.439788 [Byte1]: 50
3372 13:19:01.444348
3373 13:19:01.444444 Set Vref, RX VrefLevel [Byte0]: 51
3374 13:19:01.447491 [Byte1]: 51
3375 13:19:01.452367
3376 13:19:01.452462 Set Vref, RX VrefLevel [Byte0]: 52
3377 13:19:01.455804 [Byte1]: 52
3378 13:19:01.460302
3379 13:19:01.460404 Set Vref, RX VrefLevel [Byte0]: 53
3380 13:19:01.463525 [Byte1]: 53
3381 13:19:01.468110
3382 13:19:01.468207 Set Vref, RX VrefLevel [Byte0]: 54
3383 13:19:01.471953 [Byte1]: 54
3384 13:19:01.476091
3385 13:19:01.476193 Set Vref, RX VrefLevel [Byte0]: 55
3386 13:19:01.479500 [Byte1]: 55
3387 13:19:01.484132
3388 13:19:01.484203 Set Vref, RX VrefLevel [Byte0]: 56
3389 13:19:01.487425 [Byte1]: 56
3390 13:19:01.491962
3391 13:19:01.492031 Set Vref, RX VrefLevel [Byte0]: 57
3392 13:19:01.494986 [Byte1]: 57
3393 13:19:01.499638
3394 13:19:01.499713 Set Vref, RX VrefLevel [Byte0]: 58
3395 13:19:01.503153 [Byte1]: 58
3396 13:19:01.507942
3397 13:19:01.508011 Set Vref, RX VrefLevel [Byte0]: 59
3398 13:19:01.511528 [Byte1]: 59
3399 13:19:01.515903
3400 13:19:01.515972 Set Vref, RX VrefLevel [Byte0]: 60
3401 13:19:01.519339 [Byte1]: 60
3402 13:19:01.523353
3403 13:19:01.523428 Set Vref, RX VrefLevel [Byte0]: 61
3404 13:19:01.526893 [Byte1]: 61
3405 13:19:01.531526
3406 13:19:01.531624 Set Vref, RX VrefLevel [Byte0]: 62
3407 13:19:01.534938 [Byte1]: 62
3408 13:19:01.539160
3409 13:19:01.539235 Set Vref, RX VrefLevel [Byte0]: 63
3410 13:19:01.543162 [Byte1]: 63
3411 13:19:01.547243
3412 13:19:01.547339 Set Vref, RX VrefLevel [Byte0]: 64
3413 13:19:01.550671 [Byte1]: 64
3414 13:19:01.555547
3415 13:19:01.555617 Set Vref, RX VrefLevel [Byte0]: 65
3416 13:19:01.558307 [Byte1]: 65
3417 13:19:01.563498
3418 13:19:01.563592 Set Vref, RX VrefLevel [Byte0]: 66
3419 13:19:01.566325 [Byte1]: 66
3420 13:19:01.571395
3421 13:19:01.574297 Final RX Vref Byte 0 = 57 to rank0
3422 13:19:01.574395 Final RX Vref Byte 1 = 48 to rank0
3423 13:19:01.577779 Final RX Vref Byte 0 = 57 to rank1
3424 13:19:01.581137 Final RX Vref Byte 1 = 48 to rank1==
3425 13:19:01.584310 Dram Type= 6, Freq= 0, CH_1, rank 0
3426 13:19:01.590959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3427 13:19:01.591036 ==
3428 13:19:01.591095 DQS Delay:
3429 13:19:01.594388 DQS0 = 0, DQS1 = 0
3430 13:19:01.594458 DQM Delay:
3431 13:19:01.594516 DQM0 = 114, DQM1 = 105
3432 13:19:01.597563 DQ Delay:
3433 13:19:01.601127 DQ0 =116, DQ1 =112, DQ2 =104, DQ3 =112
3434 13:19:01.604087 DQ4 =112, DQ5 =124, DQ6 =126, DQ7 =112
3435 13:19:01.607676 DQ8 =92, DQ9 =98, DQ10 =104, DQ11 =100
3436 13:19:01.610931 DQ12 =112, DQ13 =110, DQ14 =114, DQ15 =110
3437 13:19:01.611002
3438 13:19:01.611059
3439 13:19:01.621261 [DQSOSCAuto] RK0, (LSB)MR18= 0xf3f9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 415 ps
3440 13:19:01.621360 CH1 RK0: MR19=303, MR18=F3F9
3441 13:19:01.627467 CH1_RK0: MR19=0x303, MR18=0xF3F9, DQSOSC=412, MR23=63, INC=38, DEC=25
3442 13:19:01.627564
3443 13:19:01.630931 ----->DramcWriteLeveling(PI) begin...
3444 13:19:01.631005 ==
3445 13:19:01.634221 Dram Type= 6, Freq= 0, CH_1, rank 1
3446 13:19:01.640951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 13:19:01.641057 ==
3448 13:19:01.644162 Write leveling (Byte 0): 23 => 23
3449 13:19:01.644231 Write leveling (Byte 1): 27 => 27
3450 13:19:01.647561 DramcWriteLeveling(PI) end<-----
3451 13:19:01.647631
3452 13:19:01.647687 ==
3453 13:19:01.650967 Dram Type= 6, Freq= 0, CH_1, rank 1
3454 13:19:01.657408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3455 13:19:01.657483 ==
3456 13:19:01.660972 [Gating] SW mode calibration
3457 13:19:01.666906 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3458 13:19:01.670414 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3459 13:19:01.677342 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 13:19:01.680121 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 13:19:01.683589 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 13:19:01.690086 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 13:19:01.693778 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 13:19:01.696937 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3465 13:19:01.703615 0 15 24 | B1->B0 | 3131 2424 | 1 0 | (1 0) (0 1)
3466 13:19:01.707303 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
3467 13:19:01.710517 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 13:19:01.717238 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 13:19:01.720377 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 13:19:01.723756 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 13:19:01.726730 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 13:19:01.733414 1 0 20 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
3473 13:19:01.736994 1 0 24 | B1->B0 | 2a2a 4444 | 0 0 | (0 0) (0 0)
3474 13:19:01.740215 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3475 13:19:01.747196 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 13:19:01.750404 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 13:19:01.754087 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 13:19:01.760203 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 13:19:01.763596 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 13:19:01.767109 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 13:19:01.773262 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3482 13:19:01.776697 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3483 13:19:01.780210 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 13:19:01.786508 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 13:19:01.789930 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 13:19:01.793349 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 13:19:01.800200 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 13:19:01.803406 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 13:19:01.806186 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 13:19:01.813193 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 13:19:01.816550 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 13:19:01.819788 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 13:19:01.826471 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 13:19:01.829795 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 13:19:01.833127 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 13:19:01.839528 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 13:19:01.842985 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3498 13:19:01.845974 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 13:19:01.849343 Total UI for P1: 0, mck2ui 16
3500 13:19:01.852673 best dqsien dly found for B0: ( 1, 3, 24)
3501 13:19:01.855991 Total UI for P1: 0, mck2ui 16
3502 13:19:01.859405 best dqsien dly found for B1: ( 1, 3, 24)
3503 13:19:01.862804 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3504 13:19:01.865803 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3505 13:19:01.865900
3506 13:19:01.872586 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3507 13:19:01.875932 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3508 13:19:01.879375 [Gating] SW calibration Done
3509 13:19:01.879455 ==
3510 13:19:01.882761 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 13:19:01.886293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 13:19:01.886367 ==
3513 13:19:01.886426 RX Vref Scan: 0
3514 13:19:01.886482
3515 13:19:01.889024 RX Vref 0 -> 0, step: 1
3516 13:19:01.889101
3517 13:19:01.892638 RX Delay -40 -> 252, step: 8
3518 13:19:01.896151 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3519 13:19:01.899438 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3520 13:19:01.902860 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3521 13:19:01.909463 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3522 13:19:01.912243 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3523 13:19:01.915749 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3524 13:19:01.919142 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3525 13:19:01.922813 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3526 13:19:01.929439 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3527 13:19:01.932617 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3528 13:19:01.935523 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3529 13:19:01.939188 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3530 13:19:01.942516 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3531 13:19:01.949335 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3532 13:19:01.952176 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3533 13:19:01.955464 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3534 13:19:01.955572 ==
3535 13:19:01.959292 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 13:19:01.962401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 13:19:01.965540 ==
3538 13:19:01.965613 DQS Delay:
3539 13:19:01.965672 DQS0 = 0, DQS1 = 0
3540 13:19:01.969267 DQM Delay:
3541 13:19:01.969340 DQM0 = 110, DQM1 = 106
3542 13:19:01.972594 DQ Delay:
3543 13:19:01.975666 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3544 13:19:01.979091 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3545 13:19:01.982761 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3546 13:19:01.985742 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3547 13:19:01.985822
3548 13:19:01.985882
3549 13:19:01.985937 ==
3550 13:19:01.989221 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 13:19:01.992672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 13:19:01.992775 ==
3553 13:19:01.992862
3554 13:19:01.992944
3555 13:19:01.996197 TX Vref Scan disable
3556 13:19:01.996275 == TX Byte 0 ==
3557 13:19:02.002318 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3558 13:19:02.005616 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3559 13:19:02.009146 == TX Byte 1 ==
3560 13:19:02.012394 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3561 13:19:02.015636 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3562 13:19:02.015750 ==
3563 13:19:02.019266 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 13:19:02.022000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 13:19:02.025528 ==
3566 13:19:02.035759 TX Vref=22, minBit 9, minWin=25, winSum=418
3567 13:19:02.039371 TX Vref=24, minBit 0, minWin=26, winSum=421
3568 13:19:02.041982 TX Vref=26, minBit 0, minWin=26, winSum=430
3569 13:19:02.045818 TX Vref=28, minBit 0, minWin=26, winSum=429
3570 13:19:02.048721 TX Vref=30, minBit 1, minWin=26, winSum=433
3571 13:19:02.055201 TX Vref=32, minBit 1, minWin=26, winSum=428
3572 13:19:02.058611 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 30
3573 13:19:02.058692
3574 13:19:02.061903 Final TX Range 1 Vref 30
3575 13:19:02.061982
3576 13:19:02.062075 ==
3577 13:19:02.065143 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 13:19:02.069109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 13:19:02.069190 ==
3580 13:19:02.072092
3581 13:19:02.072192
3582 13:19:02.072278 TX Vref Scan disable
3583 13:19:02.075504 == TX Byte 0 ==
3584 13:19:02.079017 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3585 13:19:02.085453 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3586 13:19:02.085558 == TX Byte 1 ==
3587 13:19:02.088466 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3588 13:19:02.095555 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3589 13:19:02.095650
3590 13:19:02.095711 [DATLAT]
3591 13:19:02.095768 Freq=1200, CH1 RK1
3592 13:19:02.095830
3593 13:19:02.098710 DATLAT Default: 0xd
3594 13:19:02.098802 0, 0xFFFF, sum = 0
3595 13:19:02.102450 1, 0xFFFF, sum = 0
3596 13:19:02.102544 2, 0xFFFF, sum = 0
3597 13:19:02.105038 3, 0xFFFF, sum = 0
3598 13:19:02.108604 4, 0xFFFF, sum = 0
3599 13:19:02.108705 5, 0xFFFF, sum = 0
3600 13:19:02.111864 6, 0xFFFF, sum = 0
3601 13:19:02.111939 7, 0xFFFF, sum = 0
3602 13:19:02.115264 8, 0xFFFF, sum = 0
3603 13:19:02.115339 9, 0xFFFF, sum = 0
3604 13:19:02.118445 10, 0xFFFF, sum = 0
3605 13:19:02.118527 11, 0xFFFF, sum = 0
3606 13:19:02.121752 12, 0x0, sum = 1
3607 13:19:02.121860 13, 0x0, sum = 2
3608 13:19:02.125089 14, 0x0, sum = 3
3609 13:19:02.125182 15, 0x0, sum = 4
3610 13:19:02.125256 best_step = 13
3611 13:19:02.128613
3612 13:19:02.128707 ==
3613 13:19:02.131942 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 13:19:02.135260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 13:19:02.135354 ==
3616 13:19:02.135417 RX Vref Scan: 0
3617 13:19:02.135499
3618 13:19:02.138909 RX Vref 0 -> 0, step: 1
3619 13:19:02.138988
3620 13:19:02.142182 RX Delay -21 -> 252, step: 4
3621 13:19:02.145680 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3622 13:19:02.151802 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3623 13:19:02.155025 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3624 13:19:02.158776 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3625 13:19:02.161916 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3626 13:19:02.164916 iDelay=195, Bit 5, Center 118 (43 ~ 194) 152
3627 13:19:02.171741 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3628 13:19:02.175224 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3629 13:19:02.178516 iDelay=195, Bit 8, Center 90 (23 ~ 158) 136
3630 13:19:02.182021 iDelay=195, Bit 9, Center 100 (31 ~ 170) 140
3631 13:19:02.185512 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3632 13:19:02.191435 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3633 13:19:02.194674 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3634 13:19:02.198001 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3635 13:19:02.201453 iDelay=195, Bit 14, Center 114 (51 ~ 178) 128
3636 13:19:02.207993 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3637 13:19:02.208073 ==
3638 13:19:02.211643 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 13:19:02.214705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 13:19:02.214786 ==
3641 13:19:02.214847 DQS Delay:
3642 13:19:02.218142 DQS0 = 0, DQS1 = 0
3643 13:19:02.218212 DQM Delay:
3644 13:19:02.221438 DQM0 = 111, DQM1 = 108
3645 13:19:02.221507 DQ Delay:
3646 13:19:02.224788 DQ0 =114, DQ1 =110, DQ2 =100, DQ3 =108
3647 13:19:02.228192 DQ4 =108, DQ5 =118, DQ6 =122, DQ7 =110
3648 13:19:02.230935 DQ8 =90, DQ9 =100, DQ10 =110, DQ11 =104
3649 13:19:02.234220 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =116
3650 13:19:02.234326
3651 13:19:02.234411
3652 13:19:02.244559 [DQSOSCAuto] RK1, (LSB)MR18= 0xfd0c, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 411 ps
3653 13:19:02.247993 CH1 RK1: MR19=304, MR18=FD0C
3654 13:19:02.254179 CH1_RK1: MR19=0x304, MR18=0xFD0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3655 13:19:02.254279 [RxdqsGatingPostProcess] freq 1200
3656 13:19:02.260988 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3657 13:19:02.264509 best DQS0 dly(2T, 0.5T) = (0, 11)
3658 13:19:02.267248 best DQS1 dly(2T, 0.5T) = (0, 11)
3659 13:19:02.271220 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3660 13:19:02.274191 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3661 13:19:02.277086 best DQS0 dly(2T, 0.5T) = (0, 11)
3662 13:19:02.280564 best DQS1 dly(2T, 0.5T) = (0, 11)
3663 13:19:02.283768 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3664 13:19:02.287418 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3665 13:19:02.290669 Pre-setting of DQS Precalculation
3666 13:19:02.293991 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3667 13:19:02.300824 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3668 13:19:02.310311 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3669 13:19:02.310411
3670 13:19:02.310500
3671 13:19:02.313615 [Calibration Summary] 2400 Mbps
3672 13:19:02.313690 CH 0, Rank 0
3673 13:19:02.316917 SW Impedance : PASS
3674 13:19:02.317009 DUTY Scan : NO K
3675 13:19:02.320231 ZQ Calibration : PASS
3676 13:19:02.320325 Jitter Meter : NO K
3677 13:19:02.323937 CBT Training : PASS
3678 13:19:02.326928 Write leveling : PASS
3679 13:19:02.326996 RX DQS gating : PASS
3680 13:19:02.329904 RX DQ/DQS(RDDQC) : PASS
3681 13:19:02.333494 TX DQ/DQS : PASS
3682 13:19:02.333563 RX DATLAT : PASS
3683 13:19:02.337014 RX DQ/DQS(Engine): PASS
3684 13:19:02.340118 TX OE : NO K
3685 13:19:02.340189 All Pass.
3686 13:19:02.340246
3687 13:19:02.340300 CH 0, Rank 1
3688 13:19:02.343447 SW Impedance : PASS
3689 13:19:02.346785 DUTY Scan : NO K
3690 13:19:02.346856 ZQ Calibration : PASS
3691 13:19:02.349902 Jitter Meter : NO K
3692 13:19:02.353211 CBT Training : PASS
3693 13:19:02.353301 Write leveling : PASS
3694 13:19:02.356421 RX DQS gating : PASS
3695 13:19:02.359726 RX DQ/DQS(RDDQC) : PASS
3696 13:19:02.359793 TX DQ/DQS : PASS
3697 13:19:02.363015 RX DATLAT : PASS
3698 13:19:02.366247 RX DQ/DQS(Engine): PASS
3699 13:19:02.366320 TX OE : NO K
3700 13:19:02.369581 All Pass.
3701 13:19:02.369647
3702 13:19:02.369699 CH 1, Rank 0
3703 13:19:02.372862 SW Impedance : PASS
3704 13:19:02.372926 DUTY Scan : NO K
3705 13:19:02.376166 ZQ Calibration : PASS
3706 13:19:02.379496 Jitter Meter : NO K
3707 13:19:02.379574 CBT Training : PASS
3708 13:19:02.382826 Write leveling : PASS
3709 13:19:02.386760 RX DQS gating : PASS
3710 13:19:02.386831 RX DQ/DQS(RDDQC) : PASS
3711 13:19:02.389521 TX DQ/DQS : PASS
3712 13:19:02.389611 RX DATLAT : PASS
3713 13:19:02.393347 RX DQ/DQS(Engine): PASS
3714 13:19:02.396256 TX OE : NO K
3715 13:19:02.396326 All Pass.
3716 13:19:02.396382
3717 13:19:02.399727 CH 1, Rank 1
3718 13:19:02.399791 SW Impedance : PASS
3719 13:19:02.402584 DUTY Scan : NO K
3720 13:19:02.402653 ZQ Calibration : PASS
3721 13:19:02.406365 Jitter Meter : NO K
3722 13:19:02.409542 CBT Training : PASS
3723 13:19:02.409606 Write leveling : PASS
3724 13:19:02.412881 RX DQS gating : PASS
3725 13:19:02.416227 RX DQ/DQS(RDDQC) : PASS
3726 13:19:02.416318 TX DQ/DQS : PASS
3727 13:19:02.419721 RX DATLAT : PASS
3728 13:19:02.422558 RX DQ/DQS(Engine): PASS
3729 13:19:02.422632 TX OE : NO K
3730 13:19:02.426174 All Pass.
3731 13:19:02.426274
3732 13:19:02.426360 DramC Write-DBI off
3733 13:19:02.429297 PER_BANK_REFRESH: Hybrid Mode
3734 13:19:02.429361 TX_TRACKING: ON
3735 13:19:02.439431 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3736 13:19:02.442461 [FAST_K] Save calibration result to emmc
3737 13:19:02.446131 dramc_set_vcore_voltage set vcore to 650000
3738 13:19:02.449063 Read voltage for 600, 5
3739 13:19:02.449127 Vio18 = 0
3740 13:19:02.452417 Vcore = 650000
3741 13:19:02.452502 Vdram = 0
3742 13:19:02.452589 Vddq = 0
3743 13:19:02.455844 Vmddr = 0
3744 13:19:02.459188 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3745 13:19:02.465819 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3746 13:19:02.465892 MEM_TYPE=3, freq_sel=19
3747 13:19:02.469320 sv_algorithm_assistance_LP4_1600
3748 13:19:02.472540 ============ PULL DRAM RESETB DOWN ============
3749 13:19:02.478970 ========== PULL DRAM RESETB DOWN end =========
3750 13:19:02.482262 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3751 13:19:02.486311 ===================================
3752 13:19:02.488959 LPDDR4 DRAM CONFIGURATION
3753 13:19:02.492185 ===================================
3754 13:19:02.492259 EX_ROW_EN[0] = 0x0
3755 13:19:02.495449 EX_ROW_EN[1] = 0x0
3756 13:19:02.498818 LP4Y_EN = 0x0
3757 13:19:02.498995 WORK_FSP = 0x0
3758 13:19:02.502304 WL = 0x2
3759 13:19:02.502516 RL = 0x2
3760 13:19:02.505653 BL = 0x2
3761 13:19:02.505744 RPST = 0x0
3762 13:19:02.509113 RD_PRE = 0x0
3763 13:19:02.509268 WR_PRE = 0x1
3764 13:19:02.512529 WR_PST = 0x0
3765 13:19:02.512679 DBI_WR = 0x0
3766 13:19:02.515881 DBI_RD = 0x0
3767 13:19:02.515953 OTF = 0x1
3768 13:19:02.519122 ===================================
3769 13:19:02.522176 ===================================
3770 13:19:02.525295 ANA top config
3771 13:19:02.528926 ===================================
3772 13:19:02.529000 DLL_ASYNC_EN = 0
3773 13:19:02.532324 ALL_SLAVE_EN = 1
3774 13:19:02.535134 NEW_RANK_MODE = 1
3775 13:19:02.538646 DLL_IDLE_MODE = 1
3776 13:19:02.541998 LP45_APHY_COMB_EN = 1
3777 13:19:02.542095 TX_ODT_DIS = 1
3778 13:19:02.545674 NEW_8X_MODE = 1
3779 13:19:02.548998 ===================================
3780 13:19:02.552127 ===================================
3781 13:19:02.555314 data_rate = 1200
3782 13:19:02.558532 CKR = 1
3783 13:19:02.561887 DQ_P2S_RATIO = 8
3784 13:19:02.565365 ===================================
3785 13:19:02.565471 CA_P2S_RATIO = 8
3786 13:19:02.568356 DQ_CA_OPEN = 0
3787 13:19:02.571905 DQ_SEMI_OPEN = 0
3788 13:19:02.575427 CA_SEMI_OPEN = 0
3789 13:19:02.578868 CA_FULL_RATE = 0
3790 13:19:02.581663 DQ_CKDIV4_EN = 1
3791 13:19:02.581759 CA_CKDIV4_EN = 1
3792 13:19:02.585114 CA_PREDIV_EN = 0
3793 13:19:02.588655 PH8_DLY = 0
3794 13:19:02.592119 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3795 13:19:02.595519 DQ_AAMCK_DIV = 4
3796 13:19:02.598372 CA_AAMCK_DIV = 4
3797 13:19:02.598464 CA_ADMCK_DIV = 4
3798 13:19:02.601792 DQ_TRACK_CA_EN = 0
3799 13:19:02.605205 CA_PICK = 600
3800 13:19:02.608765 CA_MCKIO = 600
3801 13:19:02.611585 MCKIO_SEMI = 0
3802 13:19:02.615022 PLL_FREQ = 2288
3803 13:19:02.618554 DQ_UI_PI_RATIO = 32
3804 13:19:02.618624 CA_UI_PI_RATIO = 0
3805 13:19:02.621801 ===================================
3806 13:19:02.625306 ===================================
3807 13:19:02.628464 memory_type:LPDDR4
3808 13:19:02.632006 GP_NUM : 10
3809 13:19:02.632081 SRAM_EN : 1
3810 13:19:02.635397 MD32_EN : 0
3811 13:19:02.638158 ===================================
3812 13:19:02.641617 [ANA_INIT] >>>>>>>>>>>>>>
3813 13:19:02.645173 <<<<<< [CONFIGURE PHASE]: ANA_TX
3814 13:19:02.648455 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3815 13:19:02.651383 ===================================
3816 13:19:02.651461 data_rate = 1200,PCW = 0X5800
3817 13:19:02.655204 ===================================
3818 13:19:02.661458 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3819 13:19:02.665069 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3820 13:19:02.671487 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3821 13:19:02.674464 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3822 13:19:02.678010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3823 13:19:02.681390 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3824 13:19:02.684707 [ANA_INIT] flow start
3825 13:19:02.687854 [ANA_INIT] PLL >>>>>>>>
3826 13:19:02.687930 [ANA_INIT] PLL <<<<<<<<
3827 13:19:02.691387 [ANA_INIT] MIDPI >>>>>>>>
3828 13:19:02.694408 [ANA_INIT] MIDPI <<<<<<<<
3829 13:19:02.694485 [ANA_INIT] DLL >>>>>>>>
3830 13:19:02.698166 [ANA_INIT] flow end
3831 13:19:02.701031 ============ LP4 DIFF to SE enter ============
3832 13:19:02.708130 ============ LP4 DIFF to SE exit ============
3833 13:19:02.708230 [ANA_INIT] <<<<<<<<<<<<<
3834 13:19:02.710888 [Flow] Enable top DCM control >>>>>
3835 13:19:02.714329 [Flow] Enable top DCM control <<<<<
3836 13:19:02.717706 Enable DLL master slave shuffle
3837 13:19:02.724458 ==============================================================
3838 13:19:02.724557 Gating Mode config
3839 13:19:02.731119 ==============================================================
3840 13:19:02.734546 Config description:
3841 13:19:02.740611 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3842 13:19:02.747404 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3843 13:19:02.754061 SELPH_MODE 0: By rank 1: By Phase
3844 13:19:02.760888 ==============================================================
3845 13:19:02.760969 GAT_TRACK_EN = 1
3846 13:19:02.764321 RX_GATING_MODE = 2
3847 13:19:02.767446 RX_GATING_TRACK_MODE = 2
3848 13:19:02.771102 SELPH_MODE = 1
3849 13:19:02.774247 PICG_EARLY_EN = 1
3850 13:19:02.777561 VALID_LAT_VALUE = 1
3851 13:19:02.784372 ==============================================================
3852 13:19:02.787143 Enter into Gating configuration >>>>
3853 13:19:02.790432 Exit from Gating configuration <<<<
3854 13:19:02.794152 Enter into DVFS_PRE_config >>>>>
3855 13:19:02.804135 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3856 13:19:02.806995 Exit from DVFS_PRE_config <<<<<
3857 13:19:02.810363 Enter into PICG configuration >>>>
3858 13:19:02.813659 Exit from PICG configuration <<<<
3859 13:19:02.816979 [RX_INPUT] configuration >>>>>
3860 13:19:02.817086 [RX_INPUT] configuration <<<<<
3861 13:19:02.824145 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3862 13:19:02.830936 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3863 13:19:02.833569 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3864 13:19:02.840270 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3865 13:19:02.847114 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3866 13:19:02.853916 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3867 13:19:02.857284 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3868 13:19:02.860694 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3869 13:19:02.866777 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3870 13:19:02.870277 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3871 13:19:02.873645 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3872 13:19:02.880112 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3873 13:19:02.883367 ===================================
3874 13:19:02.883476 LPDDR4 DRAM CONFIGURATION
3875 13:19:02.887093 ===================================
3876 13:19:02.890356 EX_ROW_EN[0] = 0x0
3877 13:19:02.890431 EX_ROW_EN[1] = 0x0
3878 13:19:02.893194 LP4Y_EN = 0x0
3879 13:19:02.896575 WORK_FSP = 0x0
3880 13:19:02.896679 WL = 0x2
3881 13:19:02.900008 RL = 0x2
3882 13:19:02.900105 BL = 0x2
3883 13:19:02.903437 RPST = 0x0
3884 13:19:02.903539 RD_PRE = 0x0
3885 13:19:02.906973 WR_PRE = 0x1
3886 13:19:02.907074 WR_PST = 0x0
3887 13:19:02.909730 DBI_WR = 0x0
3888 13:19:02.909825 DBI_RD = 0x0
3889 13:19:02.912915 OTF = 0x1
3890 13:19:02.916736 ===================================
3891 13:19:02.919983 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3892 13:19:02.923082 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3893 13:19:02.929673 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3894 13:19:02.933176 ===================================
3895 13:19:02.933275 LPDDR4 DRAM CONFIGURATION
3896 13:19:02.936467 ===================================
3897 13:19:02.939568 EX_ROW_EN[0] = 0x10
3898 13:19:02.939671 EX_ROW_EN[1] = 0x0
3899 13:19:02.942694 LP4Y_EN = 0x0
3900 13:19:02.946050 WORK_FSP = 0x0
3901 13:19:02.946136 WL = 0x2
3902 13:19:02.949496 RL = 0x2
3903 13:19:02.949597 BL = 0x2
3904 13:19:02.952958 RPST = 0x0
3905 13:19:02.953053 RD_PRE = 0x0
3906 13:19:02.956382 WR_PRE = 0x1
3907 13:19:02.956469 WR_PST = 0x0
3908 13:19:02.959675 DBI_WR = 0x0
3909 13:19:02.959774 DBI_RD = 0x0
3910 13:19:02.963086 OTF = 0x1
3911 13:19:02.965822 ===================================
3912 13:19:02.972656 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3913 13:19:02.976179 nWR fixed to 30
3914 13:19:02.976282 [ModeRegInit_LP4] CH0 RK0
3915 13:19:02.979670 [ModeRegInit_LP4] CH0 RK1
3916 13:19:02.982358 [ModeRegInit_LP4] CH1 RK0
3917 13:19:02.986346 [ModeRegInit_LP4] CH1 RK1
3918 13:19:02.986454 match AC timing 17
3919 13:19:02.989561 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3920 13:19:02.996078 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3921 13:19:02.999533 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3922 13:19:03.002912 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3923 13:19:03.009098 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3924 13:19:03.009174 ==
3925 13:19:03.012553 Dram Type= 6, Freq= 0, CH_0, rank 0
3926 13:19:03.016006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3927 13:19:03.016080 ==
3928 13:19:03.022662 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3929 13:19:03.029139 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3930 13:19:03.032651 [CA 0] Center 37 (7~67) winsize 61
3931 13:19:03.035416 [CA 1] Center 37 (7~67) winsize 61
3932 13:19:03.039344 [CA 2] Center 35 (5~65) winsize 61
3933 13:19:03.042450 [CA 3] Center 35 (5~65) winsize 61
3934 13:19:03.045453 [CA 4] Center 34 (4~65) winsize 62
3935 13:19:03.048914 [CA 5] Center 34 (4~64) winsize 61
3936 13:19:03.048986
3937 13:19:03.052317 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3938 13:19:03.052393
3939 13:19:03.055249 [CATrainingPosCal] consider 1 rank data
3940 13:19:03.058831 u2DelayCellTimex100 = 270/100 ps
3941 13:19:03.062351 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3942 13:19:03.065758 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3943 13:19:03.068565 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3944 13:19:03.071846 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3945 13:19:03.075201 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3946 13:19:03.078768 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3947 13:19:03.078864
3948 13:19:03.085086 CA PerBit enable=1, Macro0, CA PI delay=34
3949 13:19:03.085192
3950 13:19:03.085283 [CBTSetCACLKResult] CA Dly = 34
3951 13:19:03.088493 CS Dly: 6 (0~37)
3952 13:19:03.088585 ==
3953 13:19:03.091843 Dram Type= 6, Freq= 0, CH_0, rank 1
3954 13:19:03.095336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3955 13:19:03.095421 ==
3956 13:19:03.101862 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3957 13:19:03.108538 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3958 13:19:03.111919 [CA 0] Center 37 (7~67) winsize 61
3959 13:19:03.115387 [CA 1] Center 37 (7~67) winsize 61
3960 13:19:03.118125 [CA 2] Center 35 (5~65) winsize 61
3961 13:19:03.121635 [CA 3] Center 35 (5~65) winsize 61
3962 13:19:03.125118 [CA 4] Center 34 (4~65) winsize 62
3963 13:19:03.128527 [CA 5] Center 34 (3~65) winsize 63
3964 13:19:03.128625
3965 13:19:03.131621 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3966 13:19:03.131720
3967 13:19:03.134777 [CATrainingPosCal] consider 2 rank data
3968 13:19:03.138307 u2DelayCellTimex100 = 270/100 ps
3969 13:19:03.141666 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3970 13:19:03.145175 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3971 13:19:03.148644 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3972 13:19:03.151334 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3973 13:19:03.154805 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3974 13:19:03.161368 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3975 13:19:03.161447
3976 13:19:03.164962 CA PerBit enable=1, Macro0, CA PI delay=34
3977 13:19:03.165057
3978 13:19:03.168314 [CBTSetCACLKResult] CA Dly = 34
3979 13:19:03.168389 CS Dly: 6 (0~38)
3980 13:19:03.168447
3981 13:19:03.171227 ----->DramcWriteLeveling(PI) begin...
3982 13:19:03.171301 ==
3983 13:19:03.174803 Dram Type= 6, Freq= 0, CH_0, rank 0
3984 13:19:03.181501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3985 13:19:03.181599 ==
3986 13:19:03.184541 Write leveling (Byte 0): 34 => 34
3987 13:19:03.184642 Write leveling (Byte 1): 33 => 33
3988 13:19:03.187790 DramcWriteLeveling(PI) end<-----
3989 13:19:03.187860
3990 13:19:03.187919 ==
3991 13:19:03.191159 Dram Type= 6, Freq= 0, CH_0, rank 0
3992 13:19:03.197587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3993 13:19:03.197689 ==
3994 13:19:03.200920 [Gating] SW mode calibration
3995 13:19:03.208065 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3996 13:19:03.211228 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3997 13:19:03.217774 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3998 13:19:03.221218 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3999 13:19:03.224685 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 13:19:03.231188 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
4001 13:19:03.234547 0 9 16 | B1->B0 | 3030 2727 | 0 0 | (0 0) (0 0)
4002 13:19:03.237894 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 13:19:03.244478 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 13:19:03.247604 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 13:19:03.250892 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 13:19:03.257391 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 13:19:03.260703 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 13:19:03.264071 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4009 13:19:03.270868 0 10 16 | B1->B0 | 3333 3a3a | 0 0 | (1 1) (0 0)
4010 13:19:03.273958 0 10 20 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
4011 13:19:03.277387 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 13:19:03.280688 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 13:19:03.287204 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 13:19:03.290787 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 13:19:03.297181 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 13:19:03.300297 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4017 13:19:03.303950 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 13:19:03.310517 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 13:19:03.313981 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 13:19:03.317082 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 13:19:03.320188 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 13:19:03.327170 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 13:19:03.330729 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 13:19:03.333474 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 13:19:03.340288 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 13:19:03.343864 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 13:19:03.346587 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 13:19:03.353164 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 13:19:03.356299 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 13:19:03.360150 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 13:19:03.366276 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 13:19:03.369571 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4033 13:19:03.373459 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4034 13:19:03.380033 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 13:19:03.383111 Total UI for P1: 0, mck2ui 16
4036 13:19:03.386136 best dqsien dly found for B0: ( 0, 13, 14)
4037 13:19:03.389807 Total UI for P1: 0, mck2ui 16
4038 13:19:03.393170 best dqsien dly found for B1: ( 0, 13, 16)
4039 13:19:03.396495 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4040 13:19:03.399906 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4041 13:19:03.399983
4042 13:19:03.403086 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4043 13:19:03.406180 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4044 13:19:03.409701 [Gating] SW calibration Done
4045 13:19:03.409777 ==
4046 13:19:03.412721 Dram Type= 6, Freq= 0, CH_0, rank 0
4047 13:19:03.416202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4048 13:19:03.416282 ==
4049 13:19:03.419273 RX Vref Scan: 0
4050 13:19:03.419349
4051 13:19:03.422467 RX Vref 0 -> 0, step: 1
4052 13:19:03.422544
4053 13:19:03.422602 RX Delay -230 -> 252, step: 16
4054 13:19:03.429679 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4055 13:19:03.432735 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4056 13:19:03.435627 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4057 13:19:03.439394 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4058 13:19:03.445604 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4059 13:19:03.449070 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4060 13:19:03.452401 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4061 13:19:03.455742 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4062 13:19:03.462500 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4063 13:19:03.465783 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4064 13:19:03.468990 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4065 13:19:03.472375 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4066 13:19:03.478830 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4067 13:19:03.482178 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4068 13:19:03.485369 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4069 13:19:03.488737 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4070 13:19:03.488814 ==
4071 13:19:03.491794 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 13:19:03.498412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 13:19:03.498489 ==
4074 13:19:03.498548 DQS Delay:
4075 13:19:03.502323 DQS0 = 0, DQS1 = 0
4076 13:19:03.502400 DQM Delay:
4077 13:19:03.502458 DQM0 = 38, DQM1 = 30
4078 13:19:03.505617 DQ Delay:
4079 13:19:03.508979 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4080 13:19:03.512293 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4081 13:19:03.515500 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4082 13:19:03.518857 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4083 13:19:03.518923
4084 13:19:03.518980
4085 13:19:03.519031 ==
4086 13:19:03.522487 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 13:19:03.525054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 13:19:03.525128 ==
4089 13:19:03.525185
4090 13:19:03.525238
4091 13:19:03.528432 TX Vref Scan disable
4092 13:19:03.528503 == TX Byte 0 ==
4093 13:19:03.534927 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4094 13:19:03.538786 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4095 13:19:03.541799 == TX Byte 1 ==
4096 13:19:03.545406 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4097 13:19:03.548384 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4098 13:19:03.548457 ==
4099 13:19:03.551879 Dram Type= 6, Freq= 0, CH_0, rank 0
4100 13:19:03.555197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4101 13:19:03.558357 ==
4102 13:19:03.558431
4103 13:19:03.558488
4104 13:19:03.558541 TX Vref Scan disable
4105 13:19:03.561783 == TX Byte 0 ==
4106 13:19:03.565101 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4107 13:19:03.568704 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4108 13:19:03.571990 == TX Byte 1 ==
4109 13:19:03.575330 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4110 13:19:03.582260 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4111 13:19:03.582341
4112 13:19:03.582421 [DATLAT]
4113 13:19:03.582479 Freq=600, CH0 RK0
4114 13:19:03.582531
4115 13:19:03.584966 DATLAT Default: 0x9
4116 13:19:03.585054 0, 0xFFFF, sum = 0
4117 13:19:03.588381 1, 0xFFFF, sum = 0
4118 13:19:03.588472 2, 0xFFFF, sum = 0
4119 13:19:03.591689 3, 0xFFFF, sum = 0
4120 13:19:03.595132 4, 0xFFFF, sum = 0
4121 13:19:03.595216 5, 0xFFFF, sum = 0
4122 13:19:03.598349 6, 0xFFFF, sum = 0
4123 13:19:03.598422 7, 0xFFFF, sum = 0
4124 13:19:03.601983 8, 0x0, sum = 1
4125 13:19:03.602092 9, 0x0, sum = 2
4126 13:19:03.602176 10, 0x0, sum = 3
4127 13:19:03.604990 11, 0x0, sum = 4
4128 13:19:03.605081 best_step = 9
4129 13:19:03.605160
4130 13:19:03.605236 ==
4131 13:19:03.608199 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 13:19:03.614903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 13:19:03.614973 ==
4134 13:19:03.615029 RX Vref Scan: 1
4135 13:19:03.615080
4136 13:19:03.618211 RX Vref 0 -> 0, step: 1
4137 13:19:03.618275
4138 13:19:03.621478 RX Delay -195 -> 252, step: 8
4139 13:19:03.621556
4140 13:19:03.624628 Set Vref, RX VrefLevel [Byte0]: 61
4141 13:19:03.628227 [Byte1]: 53
4142 13:19:03.628314
4143 13:19:03.631270 Final RX Vref Byte 0 = 61 to rank0
4144 13:19:03.634624 Final RX Vref Byte 1 = 53 to rank0
4145 13:19:03.637912 Final RX Vref Byte 0 = 61 to rank1
4146 13:19:03.641235 Final RX Vref Byte 1 = 53 to rank1==
4147 13:19:03.644497 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 13:19:03.648291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 13:19:03.648392 ==
4150 13:19:03.651312 DQS Delay:
4151 13:19:03.651382 DQS0 = 0, DQS1 = 0
4152 13:19:03.654504 DQM Delay:
4153 13:19:03.654599 DQM0 = 33, DQM1 = 28
4154 13:19:03.654683 DQ Delay:
4155 13:19:03.658049 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =28
4156 13:19:03.661023 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =44
4157 13:19:03.664369 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4158 13:19:03.668055 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4159 13:19:03.668126
4160 13:19:03.668183
4161 13:19:03.678249 [DQSOSCAuto] RK0, (LSB)MR18= 0x4544, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
4162 13:19:03.681472 CH0 RK0: MR19=808, MR18=4544
4163 13:19:03.687735 CH0_RK0: MR19=0x808, MR18=0x4544, DQSOSC=396, MR23=63, INC=167, DEC=111
4164 13:19:03.687835
4165 13:19:03.691302 ----->DramcWriteLeveling(PI) begin...
4166 13:19:03.691410 ==
4167 13:19:03.694561 Dram Type= 6, Freq= 0, CH_0, rank 1
4168 13:19:03.697895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 13:19:03.697970 ==
4170 13:19:03.701229 Write leveling (Byte 0): 32 => 32
4171 13:19:03.704474 Write leveling (Byte 1): 32 => 32
4172 13:19:03.707773 DramcWriteLeveling(PI) end<-----
4173 13:19:03.707853
4174 13:19:03.707907 ==
4175 13:19:03.710864 Dram Type= 6, Freq= 0, CH_0, rank 1
4176 13:19:03.714167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 13:19:03.714236 ==
4178 13:19:03.718172 [Gating] SW mode calibration
4179 13:19:03.724064 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4180 13:19:03.730753 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4181 13:19:03.734025 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4182 13:19:03.737689 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4183 13:19:03.744208 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4184 13:19:03.747525 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4185 13:19:03.750938 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
4186 13:19:03.757456 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 13:19:03.760767 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 13:19:03.764132 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 13:19:03.770547 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 13:19:03.773837 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 13:19:03.777043 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 13:19:03.784084 0 10 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
4193 13:19:03.787075 0 10 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
4194 13:19:03.790767 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 13:19:03.797227 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 13:19:03.800520 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 13:19:03.803793 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 13:19:03.810364 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 13:19:03.813502 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 13:19:03.817233 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4201 13:19:03.823465 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4202 13:19:03.826828 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 13:19:03.830203 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 13:19:03.836764 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 13:19:03.839933 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 13:19:03.843247 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 13:19:03.850164 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 13:19:03.853787 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 13:19:03.856806 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 13:19:03.860025 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 13:19:03.866736 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 13:19:03.870124 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 13:19:03.873296 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 13:19:03.879799 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 13:19:03.883668 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 13:19:03.886828 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4217 13:19:03.889787 Total UI for P1: 0, mck2ui 16
4218 13:19:03.893469 best dqsien dly found for B0: ( 0, 13, 10)
4219 13:19:03.899798 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 13:19:03.903089 Total UI for P1: 0, mck2ui 16
4221 13:19:03.906420 best dqsien dly found for B1: ( 0, 13, 12)
4222 13:19:03.909742 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4223 13:19:03.913055 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4224 13:19:03.913130
4225 13:19:03.916287 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4226 13:19:03.919536 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4227 13:19:03.923272 [Gating] SW calibration Done
4228 13:19:03.923347 ==
4229 13:19:03.926397 Dram Type= 6, Freq= 0, CH_0, rank 1
4230 13:19:03.929546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4231 13:19:03.929622 ==
4232 13:19:03.932801 RX Vref Scan: 0
4233 13:19:03.932876
4234 13:19:03.936101 RX Vref 0 -> 0, step: 1
4235 13:19:03.936176
4236 13:19:03.936234 RX Delay -230 -> 252, step: 16
4237 13:19:03.942697 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4238 13:19:03.946011 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4239 13:19:03.949877 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4240 13:19:03.952654 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4241 13:19:03.959515 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4242 13:19:03.963042 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4243 13:19:03.965976 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4244 13:19:03.969623 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4245 13:19:03.972964 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4246 13:19:03.979615 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4247 13:19:03.982872 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4248 13:19:03.986230 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4249 13:19:03.989414 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4250 13:19:03.995777 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4251 13:19:03.999445 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4252 13:19:04.002416 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4253 13:19:04.002492 ==
4254 13:19:04.006241 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 13:19:04.009365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 13:19:04.012588 ==
4257 13:19:04.012663 DQS Delay:
4258 13:19:04.012720 DQS0 = 0, DQS1 = 0
4259 13:19:04.015827 DQM Delay:
4260 13:19:04.015902 DQM0 = 35, DQM1 = 29
4261 13:19:04.019213 DQ Delay:
4262 13:19:04.022506 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4263 13:19:04.022605 DQ4 =33, DQ5 =25, DQ6 =41, DQ7 =49
4264 13:19:04.025850 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4265 13:19:04.029100 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4266 13:19:04.032306
4267 13:19:04.032382
4268 13:19:04.032438 ==
4269 13:19:04.035826 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 13:19:04.039051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 13:19:04.039151 ==
4272 13:19:04.039234
4273 13:19:04.039313
4274 13:19:04.042327 TX Vref Scan disable
4275 13:19:04.042401 == TX Byte 0 ==
4276 13:19:04.048811 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4277 13:19:04.052199 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4278 13:19:04.052275 == TX Byte 1 ==
4279 13:19:04.058793 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4280 13:19:04.062067 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4281 13:19:04.062165 ==
4282 13:19:04.065207 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 13:19:04.068498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 13:19:04.068610 ==
4285 13:19:04.068694
4286 13:19:04.072125
4287 13:19:04.072200 TX Vref Scan disable
4288 13:19:04.075679 == TX Byte 0 ==
4289 13:19:04.078735 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4290 13:19:04.085134 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4291 13:19:04.085213 == TX Byte 1 ==
4292 13:19:04.088514 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4293 13:19:04.094991 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4294 13:19:04.095093
4295 13:19:04.095177 [DATLAT]
4296 13:19:04.095267 Freq=600, CH0 RK1
4297 13:19:04.095347
4298 13:19:04.098306 DATLAT Default: 0x9
4299 13:19:04.098405 0, 0xFFFF, sum = 0
4300 13:19:04.101550 1, 0xFFFF, sum = 0
4301 13:19:04.105380 2, 0xFFFF, sum = 0
4302 13:19:04.105481 3, 0xFFFF, sum = 0
4303 13:19:04.108445 4, 0xFFFF, sum = 0
4304 13:19:04.108541 5, 0xFFFF, sum = 0
4305 13:19:04.111982 6, 0xFFFF, sum = 0
4306 13:19:04.112099 7, 0xFFFF, sum = 0
4307 13:19:04.115164 8, 0x0, sum = 1
4308 13:19:04.115262 9, 0x0, sum = 2
4309 13:19:04.115346 10, 0x0, sum = 3
4310 13:19:04.118223 11, 0x0, sum = 4
4311 13:19:04.118326 best_step = 9
4312 13:19:04.118410
4313 13:19:04.121311 ==
4314 13:19:04.121385 Dram Type= 6, Freq= 0, CH_0, rank 1
4315 13:19:04.128329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4316 13:19:04.128435 ==
4317 13:19:04.128521 RX Vref Scan: 0
4318 13:19:04.128609
4319 13:19:04.131708 RX Vref 0 -> 0, step: 1
4320 13:19:04.131801
4321 13:19:04.135046 RX Delay -195 -> 252, step: 8
4322 13:19:04.141231 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4323 13:19:04.144914 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4324 13:19:04.148019 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4325 13:19:04.151277 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4326 13:19:04.154462 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4327 13:19:04.161019 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4328 13:19:04.165038 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4329 13:19:04.167646 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4330 13:19:04.171140 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4331 13:19:04.177829 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4332 13:19:04.181070 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4333 13:19:04.184874 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4334 13:19:04.187854 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4335 13:19:04.194213 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4336 13:19:04.197881 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4337 13:19:04.201117 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4338 13:19:04.201196 ==
4339 13:19:04.204539 Dram Type= 6, Freq= 0, CH_0, rank 1
4340 13:19:04.207769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 13:19:04.207841 ==
4342 13:19:04.211082 DQS Delay:
4343 13:19:04.211151 DQS0 = 0, DQS1 = 0
4344 13:19:04.214236 DQM Delay:
4345 13:19:04.214301 DQM0 = 33, DQM1 = 27
4346 13:19:04.214355 DQ Delay:
4347 13:19:04.217384 DQ0 =28, DQ1 =36, DQ2 =32, DQ3 =28
4348 13:19:04.220898 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4349 13:19:04.224602 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4350 13:19:04.227809 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4351 13:19:04.227895
4352 13:19:04.227953
4353 13:19:04.237310 [DQSOSCAuto] RK1, (LSB)MR18= 0x7141, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 388 ps
4354 13:19:04.241236 CH0 RK1: MR19=808, MR18=7141
4355 13:19:04.247257 CH0_RK1: MR19=0x808, MR18=0x7141, DQSOSC=388, MR23=63, INC=174, DEC=116
4356 13:19:04.247329 [RxdqsGatingPostProcess] freq 600
4357 13:19:04.254393 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4358 13:19:04.257675 Pre-setting of DQS Precalculation
4359 13:19:04.261139 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4360 13:19:04.264012 ==
4361 13:19:04.264119 Dram Type= 6, Freq= 0, CH_1, rank 0
4362 13:19:04.270690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 13:19:04.270770 ==
4364 13:19:04.274071 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4365 13:19:04.280722 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4366 13:19:04.284436 [CA 0] Center 36 (6~66) winsize 61
4367 13:19:04.287747 [CA 1] Center 36 (6~66) winsize 61
4368 13:19:04.290853 [CA 2] Center 34 (4~65) winsize 62
4369 13:19:04.294660 [CA 3] Center 34 (4~65) winsize 62
4370 13:19:04.297801 [CA 4] Center 34 (4~65) winsize 62
4371 13:19:04.301082 [CA 5] Center 33 (3~64) winsize 62
4372 13:19:04.301150
4373 13:19:04.304184 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4374 13:19:04.304277
4375 13:19:04.307706 [CATrainingPosCal] consider 1 rank data
4376 13:19:04.310914 u2DelayCellTimex100 = 270/100 ps
4377 13:19:04.314236 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4378 13:19:04.320784 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4379 13:19:04.323935 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4380 13:19:04.327755 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4381 13:19:04.330807 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4382 13:19:04.334357 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4383 13:19:04.334434
4384 13:19:04.337405 CA PerBit enable=1, Macro0, CA PI delay=33
4385 13:19:04.337481
4386 13:19:04.340959 [CBTSetCACLKResult] CA Dly = 33
4387 13:19:04.341036 CS Dly: 4 (0~35)
4388 13:19:04.344094 ==
4389 13:19:04.347722 Dram Type= 6, Freq= 0, CH_1, rank 1
4390 13:19:04.350691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4391 13:19:04.350769 ==
4392 13:19:04.354132 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4393 13:19:04.360913 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4394 13:19:04.364634 [CA 0] Center 36 (6~66) winsize 61
4395 13:19:04.367912 [CA 1] Center 36 (5~67) winsize 63
4396 13:19:04.371284 [CA 2] Center 34 (4~65) winsize 62
4397 13:19:04.374567 [CA 3] Center 34 (3~65) winsize 63
4398 13:19:04.377976 [CA 4] Center 34 (4~65) winsize 62
4399 13:19:04.381246 [CA 5] Center 33 (3~64) winsize 62
4400 13:19:04.381322
4401 13:19:04.384514 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4402 13:19:04.384591
4403 13:19:04.387673 [CATrainingPosCal] consider 2 rank data
4404 13:19:04.390841 u2DelayCellTimex100 = 270/100 ps
4405 13:19:04.394202 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4406 13:19:04.400675 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4407 13:19:04.404582 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4408 13:19:04.407592 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4409 13:19:04.410927 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4410 13:19:04.414113 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4411 13:19:04.414195
4412 13:19:04.417240 CA PerBit enable=1, Macro0, CA PI delay=33
4413 13:19:04.417318
4414 13:19:04.420640 [CBTSetCACLKResult] CA Dly = 33
4415 13:19:04.420719 CS Dly: 4 (0~36)
4416 13:19:04.424476
4417 13:19:04.427206 ----->DramcWriteLeveling(PI) begin...
4418 13:19:04.427299 ==
4419 13:19:04.430550 Dram Type= 6, Freq= 0, CH_1, rank 0
4420 13:19:04.433837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 13:19:04.433942 ==
4422 13:19:04.437123 Write leveling (Byte 0): 29 => 29
4423 13:19:04.440881 Write leveling (Byte 1): 29 => 29
4424 13:19:04.443783 DramcWriteLeveling(PI) end<-----
4425 13:19:04.443862
4426 13:19:04.443920 ==
4427 13:19:04.446971 Dram Type= 6, Freq= 0, CH_1, rank 0
4428 13:19:04.450626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4429 13:19:04.450701 ==
4430 13:19:04.453746 [Gating] SW mode calibration
4431 13:19:04.460264 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4432 13:19:04.467140 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4433 13:19:04.470209 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4434 13:19:04.473951 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4435 13:19:04.480650 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4436 13:19:04.483931 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
4437 13:19:04.487241 0 9 16 | B1->B0 | 2424 2525 | 0 1 | (1 0) (1 0)
4438 13:19:04.493725 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 13:19:04.497149 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 13:19:04.500402 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 13:19:04.506790 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 13:19:04.510030 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 13:19:04.513788 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 13:19:04.520154 0 10 12 | B1->B0 | 2e2e 2424 | 0 0 | (1 1) (0 0)
4445 13:19:04.523363 0 10 16 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)
4446 13:19:04.526565 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 13:19:04.533270 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 13:19:04.537306 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 13:19:04.539868 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 13:19:04.543692 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 13:19:04.550051 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 13:19:04.553549 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 13:19:04.556578 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4454 13:19:04.563261 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 13:19:04.566524 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 13:19:04.569889 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 13:19:04.576694 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 13:19:04.580402 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 13:19:04.583589 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 13:19:04.590295 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 13:19:04.593533 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 13:19:04.596623 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 13:19:04.603135 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 13:19:04.606424 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 13:19:04.610282 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 13:19:04.617010 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 13:19:04.620346 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 13:19:04.623313 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4469 13:19:04.629988 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 13:19:04.630088 Total UI for P1: 0, mck2ui 16
4471 13:19:04.636498 best dqsien dly found for B0: ( 0, 13, 12)
4472 13:19:04.636574 Total UI for P1: 0, mck2ui 16
4473 13:19:04.643023 best dqsien dly found for B1: ( 0, 13, 12)
4474 13:19:04.646254 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4475 13:19:04.649589 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4476 13:19:04.649664
4477 13:19:04.652857 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4478 13:19:04.656701 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4479 13:19:04.659842 [Gating] SW calibration Done
4480 13:19:04.659917 ==
4481 13:19:04.663016 Dram Type= 6, Freq= 0, CH_1, rank 0
4482 13:19:04.666495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4483 13:19:04.666587 ==
4484 13:19:04.669733 RX Vref Scan: 0
4485 13:19:04.669809
4486 13:19:04.669868 RX Vref 0 -> 0, step: 1
4487 13:19:04.669921
4488 13:19:04.672908 RX Delay -230 -> 252, step: 16
4489 13:19:04.679498 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4490 13:19:04.682888 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4491 13:19:04.685928 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4492 13:19:04.689702 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4493 13:19:04.693086 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4494 13:19:04.699505 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4495 13:19:04.702577 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4496 13:19:04.705820 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4497 13:19:04.709113 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4498 13:19:04.716266 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4499 13:19:04.719522 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4500 13:19:04.722746 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4501 13:19:04.725833 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4502 13:19:04.732285 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4503 13:19:04.735555 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4504 13:19:04.738942 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4505 13:19:04.739019 ==
4506 13:19:04.742509 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 13:19:04.745728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 13:19:04.745825 ==
4509 13:19:04.749077 DQS Delay:
4510 13:19:04.749167 DQS0 = 0, DQS1 = 0
4511 13:19:04.752201 DQM Delay:
4512 13:19:04.752293 DQM0 = 39, DQM1 = 29
4513 13:19:04.752352 DQ Delay:
4514 13:19:04.755475 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4515 13:19:04.758748 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4516 13:19:04.762023 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4517 13:19:04.765757 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4518 13:19:04.765832
4519 13:19:04.765890
4520 13:19:04.769119 ==
4521 13:19:04.772132 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 13:19:04.775718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 13:19:04.775797 ==
4524 13:19:04.775886
4525 13:19:04.775939
4526 13:19:04.778924 TX Vref Scan disable
4527 13:19:04.779051 == TX Byte 0 ==
4528 13:19:04.785270 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4529 13:19:04.788553 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4530 13:19:04.788630 == TX Byte 1 ==
4531 13:19:04.795349 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4532 13:19:04.798507 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4533 13:19:04.798586 ==
4534 13:19:04.801980 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 13:19:04.805170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 13:19:04.805246 ==
4537 13:19:04.805305
4538 13:19:04.805359
4539 13:19:04.808738 TX Vref Scan disable
4540 13:19:04.812075 == TX Byte 0 ==
4541 13:19:04.815318 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4542 13:19:04.818514 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4543 13:19:04.821766 == TX Byte 1 ==
4544 13:19:04.825096 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4545 13:19:04.828354 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4546 13:19:04.828429
4547 13:19:04.832131 [DATLAT]
4548 13:19:04.832206 Freq=600, CH1 RK0
4549 13:19:04.832265
4550 13:19:04.835290 DATLAT Default: 0x9
4551 13:19:04.835365 0, 0xFFFF, sum = 0
4552 13:19:04.838509 1, 0xFFFF, sum = 0
4553 13:19:04.838587 2, 0xFFFF, sum = 0
4554 13:19:04.842323 3, 0xFFFF, sum = 0
4555 13:19:04.842399 4, 0xFFFF, sum = 0
4556 13:19:04.844991 5, 0xFFFF, sum = 0
4557 13:19:04.845068 6, 0xFFFF, sum = 0
4558 13:19:04.848850 7, 0xFFFF, sum = 0
4559 13:19:04.848926 8, 0x0, sum = 1
4560 13:19:04.852190 9, 0x0, sum = 2
4561 13:19:04.852268 10, 0x0, sum = 3
4562 13:19:04.855451 11, 0x0, sum = 4
4563 13:19:04.855527 best_step = 9
4564 13:19:04.855586
4565 13:19:04.855639 ==
4566 13:19:04.858650 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 13:19:04.861994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 13:19:04.864875 ==
4569 13:19:04.864952 RX Vref Scan: 1
4570 13:19:04.865026
4571 13:19:04.868215 RX Vref 0 -> 0, step: 1
4572 13:19:04.868291
4573 13:19:04.871458 RX Delay -195 -> 252, step: 8
4574 13:19:04.871537
4575 13:19:04.874752 Set Vref, RX VrefLevel [Byte0]: 57
4576 13:19:04.878052 [Byte1]: 48
4577 13:19:04.878175
4578 13:19:04.881376 Final RX Vref Byte 0 = 57 to rank0
4579 13:19:04.885164 Final RX Vref Byte 1 = 48 to rank0
4580 13:19:04.888382 Final RX Vref Byte 0 = 57 to rank1
4581 13:19:04.891586 Final RX Vref Byte 1 = 48 to rank1==
4582 13:19:04.894677 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 13:19:04.897920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 13:19:04.898019 ==
4585 13:19:04.901587 DQS Delay:
4586 13:19:04.901712 DQS0 = 0, DQS1 = 0
4587 13:19:04.901822 DQM Delay:
4588 13:19:04.904786 DQM0 = 39, DQM1 = 29
4589 13:19:04.904861 DQ Delay:
4590 13:19:04.908035 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4591 13:19:04.911158 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4592 13:19:04.914935 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =20
4593 13:19:04.918274 DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =36
4594 13:19:04.918350
4595 13:19:04.918408
4596 13:19:04.928000 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a36, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 401 ps
4597 13:19:04.928076 CH1 RK0: MR19=808, MR18=2A36
4598 13:19:04.934556 CH1_RK0: MR19=0x808, MR18=0x2A36, DQSOSC=399, MR23=63, INC=164, DEC=109
4599 13:19:04.934632
4600 13:19:04.940832 ----->DramcWriteLeveling(PI) begin...
4601 13:19:04.940910 ==
4602 13:19:04.944607 Dram Type= 6, Freq= 0, CH_1, rank 1
4603 13:19:04.947913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 13:19:04.947990 ==
4605 13:19:04.951178 Write leveling (Byte 0): 29 => 29
4606 13:19:04.954317 Write leveling (Byte 1): 30 => 30
4607 13:19:04.957591 DramcWriteLeveling(PI) end<-----
4608 13:19:04.957666
4609 13:19:04.957724 ==
4610 13:19:04.960904 Dram Type= 6, Freq= 0, CH_1, rank 1
4611 13:19:04.963981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 13:19:04.964057 ==
4613 13:19:04.967801 [Gating] SW mode calibration
4614 13:19:04.974277 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4615 13:19:04.980734 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4616 13:19:04.983867 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4617 13:19:04.987560 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4618 13:19:04.994035 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4619 13:19:04.997279 0 9 12 | B1->B0 | 2f2f 2d2d | 0 0 | (0 1) (1 1)
4620 13:19:05.000327 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4621 13:19:05.007222 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 13:19:05.010490 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 13:19:05.013951 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 13:19:05.020301 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 13:19:05.023582 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 13:19:05.027434 0 10 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4627 13:19:05.030738 0 10 12 | B1->B0 | 3131 3a3a | 0 0 | (0 0) (0 0)
4628 13:19:05.037347 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4629 13:19:05.040609 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 13:19:05.043741 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 13:19:05.050125 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 13:19:05.054126 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 13:19:05.056874 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 13:19:05.063779 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 13:19:05.066861 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4636 13:19:05.070185 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 13:19:05.076682 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 13:19:05.080012 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 13:19:05.083704 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 13:19:05.090027 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 13:19:05.093071 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 13:19:05.096984 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 13:19:05.102895 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 13:19:05.106660 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 13:19:05.110005 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 13:19:05.116076 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 13:19:05.119529 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 13:19:05.123285 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 13:19:05.129789 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 13:19:05.133251 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 13:19:05.136478 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4652 13:19:05.139794 Total UI for P1: 0, mck2ui 16
4653 13:19:05.143084 best dqsien dly found for B0: ( 0, 13, 10)
4654 13:19:05.149625 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 13:19:05.149699 Total UI for P1: 0, mck2ui 16
4656 13:19:05.156005 best dqsien dly found for B1: ( 0, 13, 12)
4657 13:19:05.159304 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4658 13:19:05.162679 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4659 13:19:05.162762
4660 13:19:05.166128 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4661 13:19:05.169235 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4662 13:19:05.172424 [Gating] SW calibration Done
4663 13:19:05.172495 ==
4664 13:19:05.176058 Dram Type= 6, Freq= 0, CH_1, rank 1
4665 13:19:05.179169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4666 13:19:05.179240 ==
4667 13:19:05.182522 RX Vref Scan: 0
4668 13:19:05.182639
4669 13:19:05.182713 RX Vref 0 -> 0, step: 1
4670 13:19:05.186265
4671 13:19:05.186340 RX Delay -230 -> 252, step: 16
4672 13:19:05.192217 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4673 13:19:05.196023 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4674 13:19:05.198981 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4675 13:19:05.202703 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4676 13:19:05.209271 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4677 13:19:05.212696 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4678 13:19:05.216038 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4679 13:19:05.219178 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4680 13:19:05.222259 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4681 13:19:05.228995 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4682 13:19:05.232535 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4683 13:19:05.235638 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4684 13:19:05.238945 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4685 13:19:05.245611 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4686 13:19:05.248893 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4687 13:19:05.252134 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4688 13:19:05.252203 ==
4689 13:19:05.255273 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 13:19:05.259158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 13:19:05.262350 ==
4692 13:19:05.262431 DQS Delay:
4693 13:19:05.262500 DQS0 = 0, DQS1 = 0
4694 13:19:05.265593 DQM Delay:
4695 13:19:05.265668 DQM0 = 35, DQM1 = 29
4696 13:19:05.268834 DQ Delay:
4697 13:19:05.272150 DQ0 =33, DQ1 =33, DQ2 =25, DQ3 =33
4698 13:19:05.272219 DQ4 =33, DQ5 =49, DQ6 =41, DQ7 =33
4699 13:19:05.275425 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4700 13:19:05.278664 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4701 13:19:05.281843
4702 13:19:05.281920
4703 13:19:05.281975 ==
4704 13:19:05.285559 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 13:19:05.288302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 13:19:05.288376 ==
4707 13:19:05.288454
4708 13:19:05.288526
4709 13:19:05.292099 TX Vref Scan disable
4710 13:19:05.292170 == TX Byte 0 ==
4711 13:19:05.298503 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4712 13:19:05.302268 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4713 13:19:05.302342 == TX Byte 1 ==
4714 13:19:05.308428 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4715 13:19:05.311771 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4716 13:19:05.311858 ==
4717 13:19:05.315051 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 13:19:05.318312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 13:19:05.318405 ==
4720 13:19:05.318498
4721 13:19:05.318580
4722 13:19:05.321568 TX Vref Scan disable
4723 13:19:05.325444 == TX Byte 0 ==
4724 13:19:05.328668 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4725 13:19:05.332068 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4726 13:19:05.335098 == TX Byte 1 ==
4727 13:19:05.338650 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4728 13:19:05.341525 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4729 13:19:05.341623
4730 13:19:05.345012 [DATLAT]
4731 13:19:05.345109 Freq=600, CH1 RK1
4732 13:19:05.345198
4733 13:19:05.348457 DATLAT Default: 0x9
4734 13:19:05.348610 0, 0xFFFF, sum = 0
4735 13:19:05.351865 1, 0xFFFF, sum = 0
4736 13:19:05.351933 2, 0xFFFF, sum = 0
4737 13:19:05.355144 3, 0xFFFF, sum = 0
4738 13:19:05.355216 4, 0xFFFF, sum = 0
4739 13:19:05.358303 5, 0xFFFF, sum = 0
4740 13:19:05.358387 6, 0xFFFF, sum = 0
4741 13:19:05.361597 7, 0xFFFF, sum = 0
4742 13:19:05.361695 8, 0x0, sum = 1
4743 13:19:05.364747 9, 0x0, sum = 2
4744 13:19:05.364815 10, 0x0, sum = 3
4745 13:19:05.368607 11, 0x0, sum = 4
4746 13:19:05.368677 best_step = 9
4747 13:19:05.368732
4748 13:19:05.368783 ==
4749 13:19:05.371963 Dram Type= 6, Freq= 0, CH_1, rank 1
4750 13:19:05.378401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4751 13:19:05.378501 ==
4752 13:19:05.378590 RX Vref Scan: 0
4753 13:19:05.378680
4754 13:19:05.381711 RX Vref 0 -> 0, step: 1
4755 13:19:05.381777
4756 13:19:05.385132 RX Delay -195 -> 252, step: 8
4757 13:19:05.388348 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4758 13:19:05.394650 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4759 13:19:05.398262 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4760 13:19:05.401414 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4761 13:19:05.404618 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4762 13:19:05.408349 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4763 13:19:05.414776 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4764 13:19:05.418232 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4765 13:19:05.421501 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4766 13:19:05.424811 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4767 13:19:05.431317 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4768 13:19:05.434554 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4769 13:19:05.437870 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4770 13:19:05.441223 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4771 13:19:05.447848 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4772 13:19:05.450944 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4773 13:19:05.451148 ==
4774 13:19:05.454616 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 13:19:05.457841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 13:19:05.457929 ==
4777 13:19:05.461169 DQS Delay:
4778 13:19:05.461269 DQS0 = 0, DQS1 = 0
4779 13:19:05.461360 DQM Delay:
4780 13:19:05.464446 DQM0 = 36, DQM1 = 30
4781 13:19:05.464530 DQ Delay:
4782 13:19:05.467771 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4783 13:19:05.471049 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4784 13:19:05.474309 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4785 13:19:05.477634 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4786 13:19:05.477731
4787 13:19:05.477830
4788 13:19:05.487546 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e5e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4789 13:19:05.490933 CH1 RK1: MR19=808, MR18=3E5E
4790 13:19:05.494169 CH1_RK1: MR19=0x808, MR18=0x3E5E, DQSOSC=392, MR23=63, INC=170, DEC=113
4791 13:19:05.497464 [RxdqsGatingPostProcess] freq 600
4792 13:19:05.503747 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4793 13:19:05.507722 Pre-setting of DQS Precalculation
4794 13:19:05.510708 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4795 13:19:05.520343 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4796 13:19:05.527225 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4797 13:19:05.527320
4798 13:19:05.527416
4799 13:19:05.530505 [Calibration Summary] 1200 Mbps
4800 13:19:05.530574 CH 0, Rank 0
4801 13:19:05.533698 SW Impedance : PASS
4802 13:19:05.533776 DUTY Scan : NO K
4803 13:19:05.537039 ZQ Calibration : PASS
4804 13:19:05.540267 Jitter Meter : NO K
4805 13:19:05.540361 CBT Training : PASS
4806 13:19:05.543610 Write leveling : PASS
4807 13:19:05.546853 RX DQS gating : PASS
4808 13:19:05.546927 RX DQ/DQS(RDDQC) : PASS
4809 13:19:05.550023 TX DQ/DQS : PASS
4810 13:19:05.553930 RX DATLAT : PASS
4811 13:19:05.554030 RX DQ/DQS(Engine): PASS
4812 13:19:05.557137 TX OE : NO K
4813 13:19:05.557227 All Pass.
4814 13:19:05.557283
4815 13:19:05.560260 CH 0, Rank 1
4816 13:19:05.560334 SW Impedance : PASS
4817 13:19:05.563262 DUTY Scan : NO K
4818 13:19:05.566988 ZQ Calibration : PASS
4819 13:19:05.567077 Jitter Meter : NO K
4820 13:19:05.569985 CBT Training : PASS
4821 13:19:05.570054 Write leveling : PASS
4822 13:19:05.573340 RX DQS gating : PASS
4823 13:19:05.577180 RX DQ/DQS(RDDQC) : PASS
4824 13:19:05.577265 TX DQ/DQS : PASS
4825 13:19:05.579948 RX DATLAT : PASS
4826 13:19:05.583271 RX DQ/DQS(Engine): PASS
4827 13:19:05.583356 TX OE : NO K
4828 13:19:05.586506 All Pass.
4829 13:19:05.586576
4830 13:19:05.586632 CH 1, Rank 0
4831 13:19:05.589717 SW Impedance : PASS
4832 13:19:05.589784 DUTY Scan : NO K
4833 13:19:05.593129 ZQ Calibration : PASS
4834 13:19:05.596351 Jitter Meter : NO K
4835 13:19:05.596433 CBT Training : PASS
4836 13:19:05.600233 Write leveling : PASS
4837 13:19:05.603563 RX DQS gating : PASS
4838 13:19:05.603633 RX DQ/DQS(RDDQC) : PASS
4839 13:19:05.606796 TX DQ/DQS : PASS
4840 13:19:05.610055 RX DATLAT : PASS
4841 13:19:05.610163 RX DQ/DQS(Engine): PASS
4842 13:19:05.613340 TX OE : NO K
4843 13:19:05.613408 All Pass.
4844 13:19:05.613488
4845 13:19:05.616558 CH 1, Rank 1
4846 13:19:05.616625 SW Impedance : PASS
4847 13:19:05.619747 DUTY Scan : NO K
4848 13:19:05.619815 ZQ Calibration : PASS
4849 13:19:05.623495 Jitter Meter : NO K
4850 13:19:05.626607 CBT Training : PASS
4851 13:19:05.626676 Write leveling : PASS
4852 13:19:05.630020 RX DQS gating : PASS
4853 13:19:05.633110 RX DQ/DQS(RDDQC) : PASS
4854 13:19:05.633190 TX DQ/DQS : PASS
4855 13:19:05.636438 RX DATLAT : PASS
4856 13:19:05.639691 RX DQ/DQS(Engine): PASS
4857 13:19:05.639759 TX OE : NO K
4858 13:19:05.643018 All Pass.
4859 13:19:05.643086
4860 13:19:05.643141 DramC Write-DBI off
4861 13:19:05.646192 PER_BANK_REFRESH: Hybrid Mode
4862 13:19:05.646259 TX_TRACKING: ON
4863 13:19:05.656728 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4864 13:19:05.660024 [FAST_K] Save calibration result to emmc
4865 13:19:05.663292 dramc_set_vcore_voltage set vcore to 662500
4866 13:19:05.666522 Read voltage for 933, 3
4867 13:19:05.666596 Vio18 = 0
4868 13:19:05.669749 Vcore = 662500
4869 13:19:05.669833 Vdram = 0
4870 13:19:05.669892 Vddq = 0
4871 13:19:05.672940 Vmddr = 0
4872 13:19:05.676421 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4873 13:19:05.683044 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4874 13:19:05.683118 MEM_TYPE=3, freq_sel=17
4875 13:19:05.686469 sv_algorithm_assistance_LP4_1600
4876 13:19:05.689568 ============ PULL DRAM RESETB DOWN ============
4877 13:19:05.696199 ========== PULL DRAM RESETB DOWN end =========
4878 13:19:05.700201 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4879 13:19:05.702904 ===================================
4880 13:19:05.706235 LPDDR4 DRAM CONFIGURATION
4881 13:19:05.709516 ===================================
4882 13:19:05.709588 EX_ROW_EN[0] = 0x0
4883 13:19:05.713358 EX_ROW_EN[1] = 0x0
4884 13:19:05.713463 LP4Y_EN = 0x0
4885 13:19:05.716576 WORK_FSP = 0x0
4886 13:19:05.719729 WL = 0x3
4887 13:19:05.719804 RL = 0x3
4888 13:19:05.723227 BL = 0x2
4889 13:19:05.723321 RPST = 0x0
4890 13:19:05.726433 RD_PRE = 0x0
4891 13:19:05.726524 WR_PRE = 0x1
4892 13:19:05.729630 WR_PST = 0x0
4893 13:19:05.729700 DBI_WR = 0x0
4894 13:19:05.732939 DBI_RD = 0x0
4895 13:19:05.733007 OTF = 0x1
4896 13:19:05.736064 ===================================
4897 13:19:05.739620 ===================================
4898 13:19:05.742845 ANA top config
4899 13:19:05.746063 ===================================
4900 13:19:05.746171 DLL_ASYNC_EN = 0
4901 13:19:05.749294 ALL_SLAVE_EN = 1
4902 13:19:05.752494 NEW_RANK_MODE = 1
4903 13:19:05.755871 DLL_IDLE_MODE = 1
4904 13:19:05.759695 LP45_APHY_COMB_EN = 1
4905 13:19:05.759787 TX_ODT_DIS = 1
4906 13:19:05.763061 NEW_8X_MODE = 1
4907 13:19:05.766384 ===================================
4908 13:19:05.769617 ===================================
4909 13:19:05.772745 data_rate = 1866
4910 13:19:05.775875 CKR = 1
4911 13:19:05.779282 DQ_P2S_RATIO = 8
4912 13:19:05.782434 ===================================
4913 13:19:05.782506 CA_P2S_RATIO = 8
4914 13:19:05.786081 DQ_CA_OPEN = 0
4915 13:19:05.789085 DQ_SEMI_OPEN = 0
4916 13:19:05.792605 CA_SEMI_OPEN = 0
4917 13:19:05.796006 CA_FULL_RATE = 0
4918 13:19:05.799199 DQ_CKDIV4_EN = 1
4919 13:19:05.799291 CA_CKDIV4_EN = 1
4920 13:19:05.802375 CA_PREDIV_EN = 0
4921 13:19:05.805710 PH8_DLY = 0
4922 13:19:05.808943 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4923 13:19:05.812295 DQ_AAMCK_DIV = 4
4924 13:19:05.815601 CA_AAMCK_DIV = 4
4925 13:19:05.815677 CA_ADMCK_DIV = 4
4926 13:19:05.819490 DQ_TRACK_CA_EN = 0
4927 13:19:05.822517 CA_PICK = 933
4928 13:19:05.825837 CA_MCKIO = 933
4929 13:19:05.829133 MCKIO_SEMI = 0
4930 13:19:05.832336 PLL_FREQ = 3732
4931 13:19:05.835508 DQ_UI_PI_RATIO = 32
4932 13:19:05.835598 CA_UI_PI_RATIO = 0
4933 13:19:05.838707 ===================================
4934 13:19:05.842007 ===================================
4935 13:19:05.845803 memory_type:LPDDR4
4936 13:19:05.848898 GP_NUM : 10
4937 13:19:05.849011 SRAM_EN : 1
4938 13:19:05.852009 MD32_EN : 0
4939 13:19:05.855266 ===================================
4940 13:19:05.858636 [ANA_INIT] >>>>>>>>>>>>>>
4941 13:19:05.862213 <<<<<< [CONFIGURE PHASE]: ANA_TX
4942 13:19:05.865295 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4943 13:19:05.868565 ===================================
4944 13:19:05.868639 data_rate = 1866,PCW = 0X8f00
4945 13:19:05.871815 ===================================
4946 13:19:05.875116 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4947 13:19:05.881662 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4948 13:19:05.888883 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4949 13:19:05.892114 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4950 13:19:05.895485 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4951 13:19:05.898749 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4952 13:19:05.901907 [ANA_INIT] flow start
4953 13:19:05.904990 [ANA_INIT] PLL >>>>>>>>
4954 13:19:05.905083 [ANA_INIT] PLL <<<<<<<<
4955 13:19:05.908478 [ANA_INIT] MIDPI >>>>>>>>
4956 13:19:05.911824 [ANA_INIT] MIDPI <<<<<<<<
4957 13:19:05.911916 [ANA_INIT] DLL >>>>>>>>
4958 13:19:05.915354 [ANA_INIT] flow end
4959 13:19:05.918494 ============ LP4 DIFF to SE enter ============
4960 13:19:05.921713 ============ LP4 DIFF to SE exit ============
4961 13:19:05.924906 [ANA_INIT] <<<<<<<<<<<<<
4962 13:19:05.928069 [Flow] Enable top DCM control >>>>>
4963 13:19:05.931481 [Flow] Enable top DCM control <<<<<
4964 13:19:05.934838 Enable DLL master slave shuffle
4965 13:19:05.941267 ==============================================================
4966 13:19:05.941340 Gating Mode config
4967 13:19:05.948350 ==============================================================
4968 13:19:05.948423 Config description:
4969 13:19:05.957837 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4970 13:19:05.965085 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4971 13:19:05.971310 SELPH_MODE 0: By rank 1: By Phase
4972 13:19:05.978216 ==============================================================
4973 13:19:05.978289 GAT_TRACK_EN = 1
4974 13:19:05.981369 RX_GATING_MODE = 2
4975 13:19:05.984619 RX_GATING_TRACK_MODE = 2
4976 13:19:05.988029 SELPH_MODE = 1
4977 13:19:05.991372 PICG_EARLY_EN = 1
4978 13:19:05.994656 VALID_LAT_VALUE = 1
4979 13:19:06.001115 ==============================================================
4980 13:19:06.004434 Enter into Gating configuration >>>>
4981 13:19:06.007717 Exit from Gating configuration <<<<
4982 13:19:06.011161 Enter into DVFS_PRE_config >>>>>
4983 13:19:06.020808 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4984 13:19:06.024425 Exit from DVFS_PRE_config <<<<<
4985 13:19:06.027710 Enter into PICG configuration >>>>
4986 13:19:06.031071 Exit from PICG configuration <<<<
4987 13:19:06.034442 [RX_INPUT] configuration >>>>>
4988 13:19:06.034528 [RX_INPUT] configuration <<<<<
4989 13:19:06.040598 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4990 13:19:06.047801 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4991 13:19:06.050745 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4992 13:19:06.057439 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4993 13:19:06.063891 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4994 13:19:06.070926 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4995 13:19:06.074137 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4996 13:19:06.077314 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4997 13:19:06.084483 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4998 13:19:06.087598 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4999 13:19:06.090886 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5000 13:19:06.097504 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5001 13:19:06.100826 ===================================
5002 13:19:06.100910 LPDDR4 DRAM CONFIGURATION
5003 13:19:06.104258 ===================================
5004 13:19:06.107570 EX_ROW_EN[0] = 0x0
5005 13:19:06.107645 EX_ROW_EN[1] = 0x0
5006 13:19:06.110897 LP4Y_EN = 0x0
5007 13:19:06.110973 WORK_FSP = 0x0
5008 13:19:06.113920 WL = 0x3
5009 13:19:06.113995 RL = 0x3
5010 13:19:06.117150 BL = 0x2
5011 13:19:06.120534 RPST = 0x0
5012 13:19:06.120608 RD_PRE = 0x0
5013 13:19:06.123800 WR_PRE = 0x1
5014 13:19:06.123875 WR_PST = 0x0
5015 13:19:06.127187 DBI_WR = 0x0
5016 13:19:06.127261 DBI_RD = 0x0
5017 13:19:06.130509 OTF = 0x1
5018 13:19:06.133777 ===================================
5019 13:19:06.137397 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5020 13:19:06.140434 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5021 13:19:06.143926 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5022 13:19:06.147422 ===================================
5023 13:19:06.150457 LPDDR4 DRAM CONFIGURATION
5024 13:19:06.153673 ===================================
5025 13:19:06.156942 EX_ROW_EN[0] = 0x10
5026 13:19:06.157017 EX_ROW_EN[1] = 0x0
5027 13:19:06.160576 LP4Y_EN = 0x0
5028 13:19:06.160652 WORK_FSP = 0x0
5029 13:19:06.163786 WL = 0x3
5030 13:19:06.163861 RL = 0x3
5031 13:19:06.167081 BL = 0x2
5032 13:19:06.167156 RPST = 0x0
5033 13:19:06.170451 RD_PRE = 0x0
5034 13:19:06.173576 WR_PRE = 0x1
5035 13:19:06.173657 WR_PST = 0x0
5036 13:19:06.176830 DBI_WR = 0x0
5037 13:19:06.176900 DBI_RD = 0x0
5038 13:19:06.180094 OTF = 0x1
5039 13:19:06.183379 ===================================
5040 13:19:06.186532 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5041 13:19:06.192030 nWR fixed to 30
5042 13:19:06.195713 [ModeRegInit_LP4] CH0 RK0
5043 13:19:06.195841 [ModeRegInit_LP4] CH0 RK1
5044 13:19:06.199048 [ModeRegInit_LP4] CH1 RK0
5045 13:19:06.202223 [ModeRegInit_LP4] CH1 RK1
5046 13:19:06.202299 match AC timing 9
5047 13:19:06.208973 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5048 13:19:06.212245 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5049 13:19:06.215539 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5050 13:19:06.221997 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5051 13:19:06.225225 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5052 13:19:06.225301 ==
5053 13:19:06.228516 Dram Type= 6, Freq= 0, CH_0, rank 0
5054 13:19:06.231826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5055 13:19:06.231902 ==
5056 13:19:06.238613 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5057 13:19:06.245073 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5058 13:19:06.248240 [CA 0] Center 38 (7~69) winsize 63
5059 13:19:06.251900 [CA 1] Center 38 (8~69) winsize 62
5060 13:19:06.255075 [CA 2] Center 35 (5~66) winsize 62
5061 13:19:06.258224 [CA 3] Center 35 (5~66) winsize 62
5062 13:19:06.261907 [CA 4] Center 34 (4~65) winsize 62
5063 13:19:06.264808 [CA 5] Center 33 (3~64) winsize 62
5064 13:19:06.264884
5065 13:19:06.267934 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5066 13:19:06.268011
5067 13:19:06.271572 [CATrainingPosCal] consider 1 rank data
5068 13:19:06.274970 u2DelayCellTimex100 = 270/100 ps
5069 13:19:06.278290 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5070 13:19:06.281419 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5071 13:19:06.285110 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5072 13:19:06.288456 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5073 13:19:06.294353 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5074 13:19:06.298092 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5075 13:19:06.298192
5076 13:19:06.301264 CA PerBit enable=1, Macro0, CA PI delay=33
5077 13:19:06.301339
5078 13:19:06.304397 [CBTSetCACLKResult] CA Dly = 33
5079 13:19:06.304473 CS Dly: 7 (0~38)
5080 13:19:06.304531 ==
5081 13:19:06.308217 Dram Type= 6, Freq= 0, CH_0, rank 1
5082 13:19:06.314830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5083 13:19:06.314911 ==
5084 13:19:06.318013 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5085 13:19:06.324454 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5086 13:19:06.327633 [CA 0] Center 38 (8~69) winsize 62
5087 13:19:06.331016 [CA 1] Center 38 (7~69) winsize 63
5088 13:19:06.334294 [CA 2] Center 35 (5~66) winsize 62
5089 13:19:06.337596 [CA 3] Center 35 (5~66) winsize 62
5090 13:19:06.340844 [CA 4] Center 34 (3~65) winsize 63
5091 13:19:06.344773 [CA 5] Center 33 (3~64) winsize 62
5092 13:19:06.344848
5093 13:19:06.348017 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5094 13:19:06.348091
5095 13:19:06.351239 [CATrainingPosCal] consider 2 rank data
5096 13:19:06.354489 u2DelayCellTimex100 = 270/100 ps
5097 13:19:06.357494 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5098 13:19:06.361327 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5099 13:19:06.367531 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5100 13:19:06.371196 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5101 13:19:06.374395 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5102 13:19:06.377516 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5103 13:19:06.377580
5104 13:19:06.380705 CA PerBit enable=1, Macro0, CA PI delay=33
5105 13:19:06.380791
5106 13:19:06.384076 [CBTSetCACLKResult] CA Dly = 33
5107 13:19:06.384146 CS Dly: 7 (0~38)
5108 13:19:06.384203
5109 13:19:06.387816 ----->DramcWriteLeveling(PI) begin...
5110 13:19:06.390934 ==
5111 13:19:06.394183 Dram Type= 6, Freq= 0, CH_0, rank 0
5112 13:19:06.397399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5113 13:19:06.397469 ==
5114 13:19:06.400681 Write leveling (Byte 0): 33 => 33
5115 13:19:06.403914 Write leveling (Byte 1): 30 => 30
5116 13:19:06.407813 DramcWriteLeveling(PI) end<-----
5117 13:19:06.407899
5118 13:19:06.407958 ==
5119 13:19:06.410988 Dram Type= 6, Freq= 0, CH_0, rank 0
5120 13:19:06.414026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5121 13:19:06.414130 ==
5122 13:19:06.417244 [Gating] SW mode calibration
5123 13:19:06.424373 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5124 13:19:06.430774 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5125 13:19:06.433931 0 14 0 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (1 1)
5126 13:19:06.437148 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5127 13:19:06.443719 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 13:19:06.446954 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 13:19:06.450255 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 13:19:06.454246 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 13:19:06.460666 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 13:19:06.463770 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5133 13:19:06.466922 0 15 0 | B1->B0 | 3131 2828 | 0 0 | (0 0) (0 1)
5134 13:19:06.473364 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 13:19:06.476959 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 13:19:06.480602 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 13:19:06.486646 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 13:19:06.490007 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 13:19:06.493860 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 13:19:06.499940 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5141 13:19:06.503140 1 0 0 | B1->B0 | 2828 3f3f | 0 0 | (0 0) (0 0)
5142 13:19:06.506904 1 0 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5143 13:19:06.513645 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 13:19:06.516768 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 13:19:06.520079 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 13:19:06.526422 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 13:19:06.529716 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 13:19:06.533069 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5149 13:19:06.539991 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5150 13:19:06.543348 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 13:19:06.546643 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 13:19:06.553215 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 13:19:06.556622 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 13:19:06.559938 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 13:19:06.566321 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 13:19:06.569444 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 13:19:06.572990 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 13:19:06.579429 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 13:19:06.582809 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 13:19:06.586378 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 13:19:06.592858 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 13:19:06.596035 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 13:19:06.599251 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 13:19:06.606408 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5165 13:19:06.609338 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5166 13:19:06.612581 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5167 13:19:06.615870 Total UI for P1: 0, mck2ui 16
5168 13:19:06.619634 best dqsien dly found for B0: ( 1, 2, 30)
5169 13:19:06.626146 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 13:19:06.626238 Total UI for P1: 0, mck2ui 16
5171 13:19:06.632503 best dqsien dly found for B1: ( 1, 3, 4)
5172 13:19:06.635762 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5173 13:19:06.639230 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5174 13:19:06.639306
5175 13:19:06.642436 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5176 13:19:06.646282 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5177 13:19:06.649419 [Gating] SW calibration Done
5178 13:19:06.649495 ==
5179 13:19:06.652794 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 13:19:06.656045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 13:19:06.656121 ==
5182 13:19:06.659214 RX Vref Scan: 0
5183 13:19:06.659291
5184 13:19:06.659348 RX Vref 0 -> 0, step: 1
5185 13:19:06.659403
5186 13:19:06.662507 RX Delay -80 -> 252, step: 8
5187 13:19:06.665755 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5188 13:19:06.672436 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5189 13:19:06.675643 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5190 13:19:06.678774 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5191 13:19:06.682543 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5192 13:19:06.685845 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5193 13:19:06.689187 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5194 13:19:06.695184 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5195 13:19:06.698957 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5196 13:19:06.702213 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5197 13:19:06.705386 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5198 13:19:06.708949 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5199 13:19:06.715128 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5200 13:19:06.718684 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5201 13:19:06.721599 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5202 13:19:06.725559 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5203 13:19:06.725630 ==
5204 13:19:06.728699 Dram Type= 6, Freq= 0, CH_0, rank 0
5205 13:19:06.735215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5206 13:19:06.735300 ==
5207 13:19:06.735361 DQS Delay:
5208 13:19:06.738521 DQS0 = 0, DQS1 = 0
5209 13:19:06.738667 DQM Delay:
5210 13:19:06.738763 DQM0 = 94, DQM1 = 82
5211 13:19:06.741771 DQ Delay:
5212 13:19:06.745117 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5213 13:19:06.748385 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5214 13:19:06.751501 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =75
5215 13:19:06.754751 DQ12 =83, DQ13 =87, DQ14 =91, DQ15 =91
5216 13:19:06.754833
5217 13:19:06.754904
5218 13:19:06.754996 ==
5219 13:19:06.758013 Dram Type= 6, Freq= 0, CH_0, rank 0
5220 13:19:06.761323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5221 13:19:06.761405 ==
5222 13:19:06.761489
5223 13:19:06.761588
5224 13:19:06.764594 TX Vref Scan disable
5225 13:19:06.767941 == TX Byte 0 ==
5226 13:19:06.771691 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5227 13:19:06.775066 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5228 13:19:06.778369 == TX Byte 1 ==
5229 13:19:06.781540 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5230 13:19:06.784706 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5231 13:19:06.784858 ==
5232 13:19:06.788227 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 13:19:06.791560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 13:19:06.791628 ==
5235 13:19:06.794778
5236 13:19:06.794853
5237 13:19:06.794909 TX Vref Scan disable
5238 13:19:06.797957 == TX Byte 0 ==
5239 13:19:06.801534 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5240 13:19:06.807938 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5241 13:19:06.808014 == TX Byte 1 ==
5242 13:19:06.811040 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5243 13:19:06.817762 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5244 13:19:06.817854
5245 13:19:06.817945 [DATLAT]
5246 13:19:06.818030 Freq=933, CH0 RK0
5247 13:19:06.818177
5248 13:19:06.821043 DATLAT Default: 0xd
5249 13:19:06.821133 0, 0xFFFF, sum = 0
5250 13:19:06.824727 1, 0xFFFF, sum = 0
5251 13:19:06.827729 2, 0xFFFF, sum = 0
5252 13:19:06.827798 3, 0xFFFF, sum = 0
5253 13:19:06.831369 4, 0xFFFF, sum = 0
5254 13:19:06.831450 5, 0xFFFF, sum = 0
5255 13:19:06.834734 6, 0xFFFF, sum = 0
5256 13:19:06.834808 7, 0xFFFF, sum = 0
5257 13:19:06.837641 8, 0xFFFF, sum = 0
5258 13:19:06.837788 9, 0xFFFF, sum = 0
5259 13:19:06.840937 10, 0x0, sum = 1
5260 13:19:06.841006 11, 0x0, sum = 2
5261 13:19:06.844145 12, 0x0, sum = 3
5262 13:19:06.844214 13, 0x0, sum = 4
5263 13:19:06.844282 best_step = 11
5264 13:19:06.847994
5265 13:19:06.848100 ==
5266 13:19:06.851085 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 13:19:06.854465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 13:19:06.854548 ==
5269 13:19:06.854605 RX Vref Scan: 1
5270 13:19:06.854658
5271 13:19:06.857638 RX Vref 0 -> 0, step: 1
5272 13:19:06.857705
5273 13:19:06.860872 RX Delay -69 -> 252, step: 4
5274 13:19:06.860946
5275 13:19:06.864259 Set Vref, RX VrefLevel [Byte0]: 61
5276 13:19:06.867386 [Byte1]: 53
5277 13:19:06.867457
5278 13:19:06.870777 Final RX Vref Byte 0 = 61 to rank0
5279 13:19:06.874073 Final RX Vref Byte 1 = 53 to rank0
5280 13:19:06.877320 Final RX Vref Byte 0 = 61 to rank1
5281 13:19:06.880728 Final RX Vref Byte 1 = 53 to rank1==
5282 13:19:06.883915 Dram Type= 6, Freq= 0, CH_0, rank 0
5283 13:19:06.887178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 13:19:06.891150 ==
5285 13:19:06.891259 DQS Delay:
5286 13:19:06.891348 DQS0 = 0, DQS1 = 0
5287 13:19:06.894047 DQM Delay:
5288 13:19:06.894159 DQM0 = 95, DQM1 = 82
5289 13:19:06.897621 DQ Delay:
5290 13:19:06.901058 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5291 13:19:06.901136 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5292 13:19:06.904329 DQ8 =78, DQ9 =70, DQ10 =84, DQ11 =76
5293 13:19:06.910562 DQ12 =86, DQ13 =86, DQ14 =92, DQ15 =90
5294 13:19:06.910637
5295 13:19:06.910695
5296 13:19:06.917625 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5297 13:19:06.920645 CH0 RK0: MR19=505, MR18=1414
5298 13:19:06.926964 CH0_RK0: MR19=0x505, MR18=0x1414, DQSOSC=415, MR23=63, INC=62, DEC=41
5299 13:19:06.927041
5300 13:19:06.930286 ----->DramcWriteLeveling(PI) begin...
5301 13:19:06.930364 ==
5302 13:19:06.934183 Dram Type= 6, Freq= 0, CH_0, rank 1
5303 13:19:06.937399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 13:19:06.937475 ==
5305 13:19:06.940673 Write leveling (Byte 0): 32 => 32
5306 13:19:06.943774 Write leveling (Byte 1): 30 => 30
5307 13:19:06.947112 DramcWriteLeveling(PI) end<-----
5308 13:19:06.947187
5309 13:19:06.947244 ==
5310 13:19:06.950482 Dram Type= 6, Freq= 0, CH_0, rank 1
5311 13:19:06.954258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5312 13:19:06.954336 ==
5313 13:19:06.957412 [Gating] SW mode calibration
5314 13:19:06.963789 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5315 13:19:06.970282 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5316 13:19:06.974090 0 14 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
5317 13:19:06.977426 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 13:19:06.983783 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 13:19:06.987287 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 13:19:06.990541 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 13:19:06.997168 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 13:19:07.000415 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 13:19:07.003408 0 14 28 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (1 0)
5324 13:19:07.009898 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5325 13:19:07.013239 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 13:19:07.017040 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 13:19:07.023436 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 13:19:07.026544 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 13:19:07.030027 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 13:19:07.036882 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 13:19:07.040235 0 15 28 | B1->B0 | 2525 3636 | 0 0 | (0 0) (1 1)
5332 13:19:07.043530 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5333 13:19:07.050201 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 13:19:07.053374 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 13:19:07.056519 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 13:19:07.063152 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 13:19:07.066750 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 13:19:07.070039 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 13:19:07.077057 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5340 13:19:07.079939 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5341 13:19:07.083122 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 13:19:07.089805 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 13:19:07.093076 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 13:19:07.096355 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 13:19:07.102933 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 13:19:07.106571 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 13:19:07.109633 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 13:19:07.116536 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 13:19:07.119688 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 13:19:07.122977 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 13:19:07.129465 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 13:19:07.132761 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 13:19:07.135956 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 13:19:07.142965 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 13:19:07.145901 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5356 13:19:07.149755 Total UI for P1: 0, mck2ui 16
5357 13:19:07.153143 best dqsien dly found for B0: ( 1, 2, 26)
5358 13:19:07.155739 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5359 13:19:07.159077 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 13:19:07.162397 Total UI for P1: 0, mck2ui 16
5361 13:19:07.166276 best dqsien dly found for B1: ( 1, 2, 30)
5362 13:19:07.169501 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5363 13:19:07.175694 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5364 13:19:07.175787
5365 13:19:07.179385 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5366 13:19:07.182443 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5367 13:19:07.185735 [Gating] SW calibration Done
5368 13:19:07.185849 ==
5369 13:19:07.189493 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 13:19:07.192456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 13:19:07.192534 ==
5372 13:19:07.196220 RX Vref Scan: 0
5373 13:19:07.196298
5374 13:19:07.196356 RX Vref 0 -> 0, step: 1
5375 13:19:07.196413
5376 13:19:07.198943 RX Delay -80 -> 252, step: 8
5377 13:19:07.202256 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5378 13:19:07.205603 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5379 13:19:07.212159 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5380 13:19:07.215989 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5381 13:19:07.219042 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5382 13:19:07.222196 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5383 13:19:07.226023 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5384 13:19:07.232579 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5385 13:19:07.235781 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5386 13:19:07.239118 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5387 13:19:07.242465 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5388 13:19:07.245622 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5389 13:19:07.252432 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5390 13:19:07.255371 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5391 13:19:07.258740 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5392 13:19:07.261917 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5393 13:19:07.261987 ==
5394 13:19:07.265204 Dram Type= 6, Freq= 0, CH_0, rank 1
5395 13:19:07.269048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5396 13:19:07.272267 ==
5397 13:19:07.272336 DQS Delay:
5398 13:19:07.272392 DQS0 = 0, DQS1 = 0
5399 13:19:07.275635 DQM Delay:
5400 13:19:07.275709 DQM0 = 90, DQM1 = 84
5401 13:19:07.278998 DQ Delay:
5402 13:19:07.279099 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5403 13:19:07.281778 DQ4 =91, DQ5 =75, DQ6 =99, DQ7 =103
5404 13:19:07.285040 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =75
5405 13:19:07.288636 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5406 13:19:07.291835
5407 13:19:07.291912
5408 13:19:07.291988 ==
5409 13:19:07.295271 Dram Type= 6, Freq= 0, CH_0, rank 1
5410 13:19:07.298503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5411 13:19:07.298582 ==
5412 13:19:07.298658
5413 13:19:07.298730
5414 13:19:07.301628 TX Vref Scan disable
5415 13:19:07.301705 == TX Byte 0 ==
5416 13:19:07.308391 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5417 13:19:07.311933 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5418 13:19:07.312012 == TX Byte 1 ==
5419 13:19:07.318276 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5420 13:19:07.321588 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5421 13:19:07.321661 ==
5422 13:19:07.325320 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 13:19:07.328366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 13:19:07.328447 ==
5425 13:19:07.328505
5426 13:19:07.328558
5427 13:19:07.331861 TX Vref Scan disable
5428 13:19:07.335142 == TX Byte 0 ==
5429 13:19:07.338463 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5430 13:19:07.341793 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5431 13:19:07.345090 == TX Byte 1 ==
5432 13:19:07.348508 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5433 13:19:07.351934 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5434 13:19:07.352002
5435 13:19:07.354552 [DATLAT]
5436 13:19:07.354634 Freq=933, CH0 RK1
5437 13:19:07.354692
5438 13:19:07.358460 DATLAT Default: 0xb
5439 13:19:07.358544 0, 0xFFFF, sum = 0
5440 13:19:07.361734 1, 0xFFFF, sum = 0
5441 13:19:07.361803 2, 0xFFFF, sum = 0
5442 13:19:07.364771 3, 0xFFFF, sum = 0
5443 13:19:07.364851 4, 0xFFFF, sum = 0
5444 13:19:07.367784 5, 0xFFFF, sum = 0
5445 13:19:07.367866 6, 0xFFFF, sum = 0
5446 13:19:07.371277 7, 0xFFFF, sum = 0
5447 13:19:07.371355 8, 0xFFFF, sum = 0
5448 13:19:07.374752 9, 0xFFFF, sum = 0
5449 13:19:07.374830 10, 0x0, sum = 1
5450 13:19:07.378137 11, 0x0, sum = 2
5451 13:19:07.378216 12, 0x0, sum = 3
5452 13:19:07.381357 13, 0x0, sum = 4
5453 13:19:07.381440 best_step = 11
5454 13:19:07.381504
5455 13:19:07.381558 ==
5456 13:19:07.384846 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 13:19:07.391435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 13:19:07.391523 ==
5459 13:19:07.391581 RX Vref Scan: 0
5460 13:19:07.391636
5461 13:19:07.394448 RX Vref 0 -> 0, step: 1
5462 13:19:07.394523
5463 13:19:07.397562 RX Delay -69 -> 252, step: 4
5464 13:19:07.401460 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5465 13:19:07.404702 iDelay=199, Bit 1, Center 96 (7 ~ 186) 180
5466 13:19:07.411087 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5467 13:19:07.414325 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5468 13:19:07.418015 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5469 13:19:07.421170 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5470 13:19:07.424293 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5471 13:19:07.431317 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5472 13:19:07.434611 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5473 13:19:07.437751 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5474 13:19:07.441078 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5475 13:19:07.444008 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5476 13:19:07.451257 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5477 13:19:07.454481 iDelay=199, Bit 13, Center 90 (-5 ~ 186) 192
5478 13:19:07.457834 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5479 13:19:07.460546 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5480 13:19:07.460625 ==
5481 13:19:07.464430 Dram Type= 6, Freq= 0, CH_0, rank 1
5482 13:19:07.467317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5483 13:19:07.470785 ==
5484 13:19:07.470878 DQS Delay:
5485 13:19:07.470940 DQS0 = 0, DQS1 = 0
5486 13:19:07.474121 DQM Delay:
5487 13:19:07.474206 DQM0 = 93, DQM1 = 84
5488 13:19:07.474285 DQ Delay:
5489 13:19:07.477276 DQ0 =90, DQ1 =96, DQ2 =88, DQ3 =88
5490 13:19:07.480917 DQ4 =90, DQ5 =82, DQ6 =106, DQ7 =104
5491 13:19:07.483847 DQ8 =78, DQ9 =68, DQ10 =86, DQ11 =76
5492 13:19:07.487575 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =94
5493 13:19:07.487725
5494 13:19:07.490615
5495 13:19:07.497496 [DQSOSCAuto] RK1, (LSB)MR18= 0x3113, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
5496 13:19:07.500562 CH0 RK1: MR19=505, MR18=3113
5497 13:19:07.507488 CH0_RK1: MR19=0x505, MR18=0x3113, DQSOSC=406, MR23=63, INC=65, DEC=43
5498 13:19:07.510916 [RxdqsGatingPostProcess] freq 933
5499 13:19:07.514391 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5500 13:19:07.517121 best DQS0 dly(2T, 0.5T) = (0, 10)
5501 13:19:07.520412 best DQS1 dly(2T, 0.5T) = (0, 11)
5502 13:19:07.523823 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5503 13:19:07.527307 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5504 13:19:07.530454 best DQS0 dly(2T, 0.5T) = (0, 10)
5505 13:19:07.534236 best DQS1 dly(2T, 0.5T) = (0, 10)
5506 13:19:07.537498 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5507 13:19:07.540315 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5508 13:19:07.543805 Pre-setting of DQS Precalculation
5509 13:19:07.547055 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5510 13:19:07.547133 ==
5511 13:19:07.550772 Dram Type= 6, Freq= 0, CH_1, rank 0
5512 13:19:07.553985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5513 13:19:07.556839 ==
5514 13:19:07.560752 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5515 13:19:07.567526 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5516 13:19:07.570267 [CA 0] Center 36 (7~66) winsize 60
5517 13:19:07.573679 [CA 1] Center 37 (7~67) winsize 61
5518 13:19:07.577290 [CA 2] Center 34 (5~64) winsize 60
5519 13:19:07.580564 [CA 3] Center 34 (4~64) winsize 61
5520 13:19:07.584095 [CA 4] Center 34 (5~64) winsize 60
5521 13:19:07.586816 [CA 5] Center 33 (4~63) winsize 60
5522 13:19:07.586944
5523 13:19:07.589970 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5524 13:19:07.590071
5525 13:19:07.593793 [CATrainingPosCal] consider 1 rank data
5526 13:19:07.596789 u2DelayCellTimex100 = 270/100 ps
5527 13:19:07.600452 CA0 delay=36 (7~66),Diff = 3 PI (18 cell)
5528 13:19:07.603598 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5529 13:19:07.606957 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5530 13:19:07.613640 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5531 13:19:07.616772 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5532 13:19:07.620360 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5533 13:19:07.620438
5534 13:19:07.623480 CA PerBit enable=1, Macro0, CA PI delay=33
5535 13:19:07.623559
5536 13:19:07.626818 [CBTSetCACLKResult] CA Dly = 33
5537 13:19:07.626914 CS Dly: 6 (0~37)
5538 13:19:07.626993 ==
5539 13:19:07.630069 Dram Type= 6, Freq= 0, CH_1, rank 1
5540 13:19:07.636673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 13:19:07.636752 ==
5542 13:19:07.639984 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5543 13:19:07.646900 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5544 13:19:07.650179 [CA 0] Center 37 (7~68) winsize 62
5545 13:19:07.653529 [CA 1] Center 37 (7~68) winsize 62
5546 13:19:07.656996 [CA 2] Center 35 (5~65) winsize 61
5547 13:19:07.660100 [CA 3] Center 34 (4~64) winsize 61
5548 13:19:07.663314 [CA 4] Center 34 (4~64) winsize 61
5549 13:19:07.666751 [CA 5] Center 33 (3~64) winsize 62
5550 13:19:07.666829
5551 13:19:07.670195 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5552 13:19:07.670274
5553 13:19:07.673479 [CATrainingPosCal] consider 2 rank data
5554 13:19:07.676733 u2DelayCellTimex100 = 270/100 ps
5555 13:19:07.680153 CA0 delay=36 (7~66),Diff = 3 PI (18 cell)
5556 13:19:07.683475 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5557 13:19:07.689626 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5558 13:19:07.693282 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5559 13:19:07.696679 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5560 13:19:07.699926 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5561 13:19:07.700005
5562 13:19:07.702987 CA PerBit enable=1, Macro0, CA PI delay=33
5563 13:19:07.703065
5564 13:19:07.705993 [CBTSetCACLKResult] CA Dly = 33
5565 13:19:07.706094 CS Dly: 6 (0~38)
5566 13:19:07.706169
5567 13:19:07.709751 ----->DramcWriteLeveling(PI) begin...
5568 13:19:07.712924 ==
5569 13:19:07.716167 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 13:19:07.719704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 13:19:07.719783 ==
5572 13:19:07.723043 Write leveling (Byte 0): 28 => 28
5573 13:19:07.726303 Write leveling (Byte 1): 29 => 29
5574 13:19:07.729761 DramcWriteLeveling(PI) end<-----
5575 13:19:07.729834
5576 13:19:07.729892 ==
5577 13:19:07.733284 Dram Type= 6, Freq= 0, CH_1, rank 0
5578 13:19:07.736042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5579 13:19:07.736121 ==
5580 13:19:07.739566 [Gating] SW mode calibration
5581 13:19:07.746355 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5582 13:19:07.749646 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5583 13:19:07.756292 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (0 0) (1 1)
5584 13:19:07.759547 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 13:19:07.762941 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 13:19:07.769715 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 13:19:07.773245 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 13:19:07.776498 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 13:19:07.782773 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 13:19:07.786308 0 14 28 | B1->B0 | 2f2f 2e2e | 1 1 | (1 1) (1 1)
5591 13:19:07.789675 0 15 0 | B1->B0 | 2828 2525 | 0 0 | (1 0) (0 0)
5592 13:19:07.796032 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 13:19:07.799278 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 13:19:07.802784 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 13:19:07.809546 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 13:19:07.812890 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 13:19:07.816101 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 13:19:07.822852 0 15 28 | B1->B0 | 2f2f 3030 | 1 1 | (1 1) (0 0)
5599 13:19:07.825579 1 0 0 | B1->B0 | 4646 3f3f | 0 1 | (0 0) (0 0)
5600 13:19:07.829325 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 13:19:07.835545 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 13:19:07.839249 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 13:19:07.842492 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 13:19:07.849180 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 13:19:07.852454 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 13:19:07.855892 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5607 13:19:07.862217 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 13:19:07.865729 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5609 13:19:07.869210 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 13:19:07.875322 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 13:19:07.878773 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 13:19:07.882185 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 13:19:07.888925 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 13:19:07.892057 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 13:19:07.895257 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 13:19:07.901731 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 13:19:07.905493 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 13:19:07.908209 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 13:19:07.914721 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 13:19:07.918203 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 13:19:07.921460 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 13:19:07.928032 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5623 13:19:07.931540 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 13:19:07.935041 Total UI for P1: 0, mck2ui 16
5625 13:19:07.938418 best dqsien dly found for B0: ( 1, 2, 30)
5626 13:19:07.941287 Total UI for P1: 0, mck2ui 16
5627 13:19:07.944598 best dqsien dly found for B1: ( 1, 2, 28)
5628 13:19:07.948052 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5629 13:19:07.951155 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5630 13:19:07.951243
5631 13:19:07.954711 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5632 13:19:07.958429 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5633 13:19:07.961472 [Gating] SW calibration Done
5634 13:19:07.961550 ==
5635 13:19:07.964808 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 13:19:07.968148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 13:19:07.968230 ==
5638 13:19:07.971740 RX Vref Scan: 0
5639 13:19:07.971819
5640 13:19:07.974284 RX Vref 0 -> 0, step: 1
5641 13:19:07.974388
5642 13:19:07.978067 RX Delay -80 -> 252, step: 8
5643 13:19:07.980888 iDelay=208, Bit 0, Center 103 (0 ~ 207) 208
5644 13:19:07.984332 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5645 13:19:07.987954 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5646 13:19:07.991305 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5647 13:19:07.993969 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5648 13:19:08.000796 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5649 13:19:08.003894 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5650 13:19:08.007850 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5651 13:19:08.011108 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5652 13:19:08.014003 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5653 13:19:08.020983 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5654 13:19:08.024347 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5655 13:19:08.027631 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5656 13:19:08.030621 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5657 13:19:08.034108 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5658 13:19:08.040443 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5659 13:19:08.040542 ==
5660 13:19:08.043893 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 13:19:08.046761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 13:19:08.046838 ==
5663 13:19:08.046911 DQS Delay:
5664 13:19:08.050138 DQS0 = 0, DQS1 = 0
5665 13:19:08.050203 DQM Delay:
5666 13:19:08.053629 DQM0 = 95, DQM1 = 89
5667 13:19:08.053707 DQ Delay:
5668 13:19:08.056941 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =91
5669 13:19:08.060077 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5670 13:19:08.063548 DQ8 =79, DQ9 =83, DQ10 =87, DQ11 =87
5671 13:19:08.066965 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5672 13:19:08.067069
5673 13:19:08.067158
5674 13:19:08.067244 ==
5675 13:19:08.070432 Dram Type= 6, Freq= 0, CH_1, rank 0
5676 13:19:08.073523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5677 13:19:08.076903 ==
5678 13:19:08.077003
5679 13:19:08.077089
5680 13:19:08.077182 TX Vref Scan disable
5681 13:19:08.080093 == TX Byte 0 ==
5682 13:19:08.083016 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5683 13:19:08.086508 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5684 13:19:08.089757 == TX Byte 1 ==
5685 13:19:08.093326 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5686 13:19:08.096495 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5687 13:19:08.099898 ==
5688 13:19:08.100012 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 13:19:08.106759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 13:19:08.106834 ==
5691 13:19:08.106893
5692 13:19:08.106947
5693 13:19:08.110126 TX Vref Scan disable
5694 13:19:08.110190 == TX Byte 0 ==
5695 13:19:08.116167 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5696 13:19:08.119439 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5697 13:19:08.119538 == TX Byte 1 ==
5698 13:19:08.126450 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5699 13:19:08.129379 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5700 13:19:08.129489
5701 13:19:08.129578 [DATLAT]
5702 13:19:08.132865 Freq=933, CH1 RK0
5703 13:19:08.132972
5704 13:19:08.133059 DATLAT Default: 0xd
5705 13:19:08.136396 0, 0xFFFF, sum = 0
5706 13:19:08.136498 1, 0xFFFF, sum = 0
5707 13:19:08.139614 2, 0xFFFF, sum = 0
5708 13:19:08.139711 3, 0xFFFF, sum = 0
5709 13:19:08.142792 4, 0xFFFF, sum = 0
5710 13:19:08.142887 5, 0xFFFF, sum = 0
5711 13:19:08.146358 6, 0xFFFF, sum = 0
5712 13:19:08.146459 7, 0xFFFF, sum = 0
5713 13:19:08.149250 8, 0xFFFF, sum = 0
5714 13:19:08.152648 9, 0xFFFF, sum = 0
5715 13:19:08.152746 10, 0x0, sum = 1
5716 13:19:08.152836 11, 0x0, sum = 2
5717 13:19:08.156100 12, 0x0, sum = 3
5718 13:19:08.156169 13, 0x0, sum = 4
5719 13:19:08.159502 best_step = 11
5720 13:19:08.159602
5721 13:19:08.159689 ==
5722 13:19:08.162831 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 13:19:08.165803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 13:19:08.165895 ==
5725 13:19:08.169771 RX Vref Scan: 1
5726 13:19:08.169864
5727 13:19:08.169946 RX Vref 0 -> 0, step: 1
5728 13:19:08.170026
5729 13:19:08.172446 RX Delay -61 -> 252, step: 4
5730 13:19:08.172533
5731 13:19:08.175855 Set Vref, RX VrefLevel [Byte0]: 57
5732 13:19:08.179373 [Byte1]: 48
5733 13:19:08.183854
5734 13:19:08.183917 Final RX Vref Byte 0 = 57 to rank0
5735 13:19:08.186509 Final RX Vref Byte 1 = 48 to rank0
5736 13:19:08.190345 Final RX Vref Byte 0 = 57 to rank1
5737 13:19:08.193574 Final RX Vref Byte 1 = 48 to rank1==
5738 13:19:08.196589 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 13:19:08.203353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 13:19:08.203422 ==
5741 13:19:08.203478 DQS Delay:
5742 13:19:08.206388 DQS0 = 0, DQS1 = 0
5743 13:19:08.206459 DQM Delay:
5744 13:19:08.206516 DQM0 = 95, DQM1 = 87
5745 13:19:08.210042 DQ Delay:
5746 13:19:08.212973 DQ0 =100, DQ1 =90, DQ2 =84, DQ3 =92
5747 13:19:08.216566 DQ4 =94, DQ5 =104, DQ6 =104, DQ7 =92
5748 13:19:08.219846 DQ8 =74, DQ9 =78, DQ10 =86, DQ11 =82
5749 13:19:08.223271 DQ12 =96, DQ13 =94, DQ14 =94, DQ15 =94
5750 13:19:08.223358
5751 13:19:08.223455
5752 13:19:08.229745 [DQSOSCAuto] RK0, (LSB)MR18= 0x30b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5753 13:19:08.232892 CH1 RK0: MR19=505, MR18=30B
5754 13:19:08.239970 CH1_RK0: MR19=0x505, MR18=0x30B, DQSOSC=418, MR23=63, INC=62, DEC=41
5755 13:19:08.240073
5756 13:19:08.242979 ----->DramcWriteLeveling(PI) begin...
5757 13:19:08.243073 ==
5758 13:19:08.246426 Dram Type= 6, Freq= 0, CH_1, rank 1
5759 13:19:08.249652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 13:19:08.249745 ==
5761 13:19:08.252755 Write leveling (Byte 0): 23 => 23
5762 13:19:08.256527 Write leveling (Byte 1): 31 => 31
5763 13:19:08.259816 DramcWriteLeveling(PI) end<-----
5764 13:19:08.259879
5765 13:19:08.259934 ==
5766 13:19:08.263223 Dram Type= 6, Freq= 0, CH_1, rank 1
5767 13:19:08.265907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 13:19:08.265996 ==
5769 13:19:08.269746 [Gating] SW mode calibration
5770 13:19:08.275957 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5771 13:19:08.282540 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5772 13:19:08.285800 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5773 13:19:08.292452 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 13:19:08.296438 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 13:19:08.299113 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 13:19:08.306388 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 13:19:08.309587 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5778 13:19:08.312821 0 14 24 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 1)
5779 13:19:08.319011 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5780 13:19:08.322800 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 13:19:08.325610 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 13:19:08.332102 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 13:19:08.336070 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 13:19:08.339288 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 13:19:08.345816 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 13:19:08.348765 0 15 24 | B1->B0 | 2a2a 3636 | 1 0 | (0 0) (0 0)
5787 13:19:08.352498 0 15 28 | B1->B0 | 3a3a 4545 | 1 1 | (0 0) (0 0)
5788 13:19:08.358929 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 13:19:08.362218 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 13:19:08.365243 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 13:19:08.369090 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 13:19:08.375339 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 13:19:08.378651 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 13:19:08.381749 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 13:19:08.388604 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 13:19:08.391902 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 13:19:08.395395 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 13:19:08.401519 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 13:19:08.405052 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 13:19:08.408305 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 13:19:08.415282 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 13:19:08.418474 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 13:19:08.421999 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 13:19:08.428055 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 13:19:08.431654 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 13:19:08.434775 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 13:19:08.441158 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 13:19:08.444841 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 13:19:08.448335 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 13:19:08.454554 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 13:19:08.458006 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 13:19:08.461493 Total UI for P1: 0, mck2ui 16
5813 13:19:08.464644 best dqsien dly found for B0: ( 1, 2, 26)
5814 13:19:08.467772 Total UI for P1: 0, mck2ui 16
5815 13:19:08.471286 best dqsien dly found for B1: ( 1, 2, 26)
5816 13:19:08.474422 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5817 13:19:08.478056 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5818 13:19:08.478194
5819 13:19:08.481158 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5820 13:19:08.484536 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5821 13:19:08.488115 [Gating] SW calibration Done
5822 13:19:08.488251 ==
5823 13:19:08.491281 Dram Type= 6, Freq= 0, CH_1, rank 1
5824 13:19:08.497639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5825 13:19:08.497742 ==
5826 13:19:08.497829 RX Vref Scan: 0
5827 13:19:08.497913
5828 13:19:08.501015 RX Vref 0 -> 0, step: 1
5829 13:19:08.501109
5830 13:19:08.504382 RX Delay -80 -> 252, step: 8
5831 13:19:08.507784 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5832 13:19:08.511117 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5833 13:19:08.514238 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5834 13:19:08.518096 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5835 13:19:08.524512 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5836 13:19:08.527799 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5837 13:19:08.531039 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5838 13:19:08.534302 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5839 13:19:08.537544 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5840 13:19:08.540863 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5841 13:19:08.547855 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5842 13:19:08.551156 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5843 13:19:08.554405 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5844 13:19:08.557449 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5845 13:19:08.560927 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5846 13:19:08.564458 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5847 13:19:08.567691 ==
5848 13:19:08.571050 Dram Type= 6, Freq= 0, CH_1, rank 1
5849 13:19:08.574223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5850 13:19:08.574301 ==
5851 13:19:08.574360 DQS Delay:
5852 13:19:08.577521 DQS0 = 0, DQS1 = 0
5853 13:19:08.577598 DQM Delay:
5854 13:19:08.580589 DQM0 = 94, DQM1 = 88
5855 13:19:08.580665 DQ Delay:
5856 13:19:08.584105 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =91
5857 13:19:08.587339 DQ4 =91, DQ5 =103, DQ6 =107, DQ7 =91
5858 13:19:08.590603 DQ8 =75, DQ9 =75, DQ10 =95, DQ11 =79
5859 13:19:08.594198 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5860 13:19:08.594295
5861 13:19:08.594366
5862 13:19:08.594423 ==
5863 13:19:08.597604 Dram Type= 6, Freq= 0, CH_1, rank 1
5864 13:19:08.600450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5865 13:19:08.600552 ==
5866 13:19:08.600642
5867 13:19:08.600724
5868 13:19:08.604287 TX Vref Scan disable
5869 13:19:08.607501 == TX Byte 0 ==
5870 13:19:08.610792 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5871 13:19:08.613984 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5872 13:19:08.617287 == TX Byte 1 ==
5873 13:19:08.620549 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5874 13:19:08.623842 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5875 13:19:08.623938 ==
5876 13:19:08.627285 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 13:19:08.633652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 13:19:08.633796 ==
5879 13:19:08.633919
5880 13:19:08.633998
5881 13:19:08.634077 TX Vref Scan disable
5882 13:19:08.638295 == TX Byte 0 ==
5883 13:19:08.641014 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5884 13:19:08.647636 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5885 13:19:08.647740 == TX Byte 1 ==
5886 13:19:08.651404 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5887 13:19:08.657921 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5888 13:19:08.658022
5889 13:19:08.658116 [DATLAT]
5890 13:19:08.658205 Freq=933, CH1 RK1
5891 13:19:08.658281
5892 13:19:08.661203 DATLAT Default: 0xb
5893 13:19:08.661292 0, 0xFFFF, sum = 0
5894 13:19:08.664531 1, 0xFFFF, sum = 0
5895 13:19:08.667839 2, 0xFFFF, sum = 0
5896 13:19:08.667938 3, 0xFFFF, sum = 0
5897 13:19:08.670966 4, 0xFFFF, sum = 0
5898 13:19:08.671067 5, 0xFFFF, sum = 0
5899 13:19:08.674594 6, 0xFFFF, sum = 0
5900 13:19:08.674692 7, 0xFFFF, sum = 0
5901 13:19:08.677568 8, 0xFFFF, sum = 0
5902 13:19:08.677649 9, 0xFFFF, sum = 0
5903 13:19:08.681216 10, 0x0, sum = 1
5904 13:19:08.681313 11, 0x0, sum = 2
5905 13:19:08.684608 12, 0x0, sum = 3
5906 13:19:08.684714 13, 0x0, sum = 4
5907 13:19:08.684800 best_step = 11
5908 13:19:08.684882
5909 13:19:08.687898 ==
5910 13:19:08.691112 Dram Type= 6, Freq= 0, CH_1, rank 1
5911 13:19:08.694258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5912 13:19:08.694330 ==
5913 13:19:08.694386 RX Vref Scan: 0
5914 13:19:08.694448
5915 13:19:08.697762 RX Vref 0 -> 0, step: 1
5916 13:19:08.697851
5917 13:19:08.700803 RX Delay -69 -> 252, step: 4
5918 13:19:08.707354 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5919 13:19:08.711019 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5920 13:19:08.713819 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5921 13:19:08.717192 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5922 13:19:08.720343 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5923 13:19:08.723675 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5924 13:19:08.730425 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5925 13:19:08.733656 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5926 13:19:08.736911 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5927 13:19:08.740640 iDelay=203, Bit 9, Center 78 (-17 ~ 174) 192
5928 13:19:08.743856 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5929 13:19:08.750493 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5930 13:19:08.753708 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5931 13:19:08.756955 iDelay=203, Bit 13, Center 94 (-1 ~ 190) 192
5932 13:19:08.760743 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5933 13:19:08.764152 iDelay=203, Bit 15, Center 94 (-1 ~ 190) 192
5934 13:19:08.764246 ==
5935 13:19:08.767428 Dram Type= 6, Freq= 0, CH_1, rank 1
5936 13:19:08.773928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5937 13:19:08.774023 ==
5938 13:19:08.774134 DQS Delay:
5939 13:19:08.777079 DQS0 = 0, DQS1 = 0
5940 13:19:08.777170 DQM Delay:
5941 13:19:08.777261 DQM0 = 93, DQM1 = 89
5942 13:19:08.780263 DQ Delay:
5943 13:19:08.783620 DQ0 =96, DQ1 =90, DQ2 =82, DQ3 =90
5944 13:19:08.787382 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =90
5945 13:19:08.790260 DQ8 =76, DQ9 =78, DQ10 =92, DQ11 =82
5946 13:19:08.793930 DQ12 =98, DQ13 =94, DQ14 =98, DQ15 =94
5947 13:19:08.794027
5948 13:19:08.794155
5949 13:19:08.800487 [DQSOSCAuto] RK1, (LSB)MR18= 0x1225, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
5950 13:19:08.803640 CH1 RK1: MR19=505, MR18=1225
5951 13:19:08.810220 CH1_RK1: MR19=0x505, MR18=0x1225, DQSOSC=410, MR23=63, INC=64, DEC=42
5952 13:19:08.813826 [RxdqsGatingPostProcess] freq 933
5953 13:19:08.817103 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5954 13:19:08.820232 best DQS0 dly(2T, 0.5T) = (0, 10)
5955 13:19:08.823331 best DQS1 dly(2T, 0.5T) = (0, 10)
5956 13:19:08.826839 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5957 13:19:08.830546 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5958 13:19:08.833752 best DQS0 dly(2T, 0.5T) = (0, 10)
5959 13:19:08.837018 best DQS1 dly(2T, 0.5T) = (0, 10)
5960 13:19:08.840399 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5961 13:19:08.843686 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5962 13:19:08.847070 Pre-setting of DQS Precalculation
5963 13:19:08.850228 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5964 13:19:08.860076 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5965 13:19:08.866957 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5966 13:19:08.867048
5967 13:19:08.867106
5968 13:19:08.870285 [Calibration Summary] 1866 Mbps
5969 13:19:08.870361 CH 0, Rank 0
5970 13:19:08.873615 SW Impedance : PASS
5971 13:19:08.873690 DUTY Scan : NO K
5972 13:19:08.876801 ZQ Calibration : PASS
5973 13:19:08.880132 Jitter Meter : NO K
5974 13:19:08.880206 CBT Training : PASS
5975 13:19:08.883246 Write leveling : PASS
5976 13:19:08.887100 RX DQS gating : PASS
5977 13:19:08.887175 RX DQ/DQS(RDDQC) : PASS
5978 13:19:08.890335 TX DQ/DQS : PASS
5979 13:19:08.890411 RX DATLAT : PASS
5980 13:19:08.893563 RX DQ/DQS(Engine): PASS
5981 13:19:08.896794 TX OE : NO K
5982 13:19:08.896869 All Pass.
5983 13:19:08.896927
5984 13:19:08.896980 CH 0, Rank 1
5985 13:19:08.899958 SW Impedance : PASS
5986 13:19:08.903463 DUTY Scan : NO K
5987 13:19:08.903539 ZQ Calibration : PASS
5988 13:19:08.906744 Jitter Meter : NO K
5989 13:19:08.909818 CBT Training : PASS
5990 13:19:08.909893 Write leveling : PASS
5991 13:19:08.913035 RX DQS gating : PASS
5992 13:19:08.916773 RX DQ/DQS(RDDQC) : PASS
5993 13:19:08.916871 TX DQ/DQS : PASS
5994 13:19:08.919710 RX DATLAT : PASS
5995 13:19:08.923012 RX DQ/DQS(Engine): PASS
5996 13:19:08.923088 TX OE : NO K
5997 13:19:08.926260 All Pass.
5998 13:19:08.926334
5999 13:19:08.926416 CH 1, Rank 0
6000 13:19:08.929999 SW Impedance : PASS
6001 13:19:08.930090 DUTY Scan : NO K
6002 13:19:08.933115 ZQ Calibration : PASS
6003 13:19:08.936667 Jitter Meter : NO K
6004 13:19:08.936772 CBT Training : PASS
6005 13:19:08.939810 Write leveling : PASS
6006 13:19:08.939880 RX DQS gating : PASS
6007 13:19:08.943098 RX DQ/DQS(RDDQC) : PASS
6008 13:19:08.946425 TX DQ/DQS : PASS
6009 13:19:08.946503 RX DATLAT : PASS
6010 13:19:08.949780 RX DQ/DQS(Engine): PASS
6011 13:19:08.953544 TX OE : NO K
6012 13:19:08.953646 All Pass.
6013 13:19:08.953731
6014 13:19:08.953810 CH 1, Rank 1
6015 13:19:08.956714 SW Impedance : PASS
6016 13:19:08.959779 DUTY Scan : NO K
6017 13:19:08.959880 ZQ Calibration : PASS
6018 13:19:08.962964 Jitter Meter : NO K
6019 13:19:08.966319 CBT Training : PASS
6020 13:19:08.966407 Write leveling : PASS
6021 13:19:08.969485 RX DQS gating : PASS
6022 13:19:08.973471 RX DQ/DQS(RDDQC) : PASS
6023 13:19:08.973564 TX DQ/DQS : PASS
6024 13:19:08.976770 RX DATLAT : PASS
6025 13:19:08.980090 RX DQ/DQS(Engine): PASS
6026 13:19:08.980182 TX OE : NO K
6027 13:19:08.980265 All Pass.
6028 13:19:08.983366
6029 13:19:08.983457 DramC Write-DBI off
6030 13:19:08.986492 PER_BANK_REFRESH: Hybrid Mode
6031 13:19:08.986595 TX_TRACKING: ON
6032 13:19:08.996457 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6033 13:19:08.999713 [FAST_K] Save calibration result to emmc
6034 13:19:09.003027 dramc_set_vcore_voltage set vcore to 650000
6035 13:19:09.006276 Read voltage for 400, 6
6036 13:19:09.006345 Vio18 = 0
6037 13:19:09.009608 Vcore = 650000
6038 13:19:09.009700 Vdram = 0
6039 13:19:09.009781 Vddq = 0
6040 13:19:09.012716 Vmddr = 0
6041 13:19:09.016371 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6042 13:19:09.022552 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6043 13:19:09.022645 MEM_TYPE=3, freq_sel=20
6044 13:19:09.026209 sv_algorithm_assistance_LP4_800
6045 13:19:09.029283 ============ PULL DRAM RESETB DOWN ============
6046 13:19:09.036127 ========== PULL DRAM RESETB DOWN end =========
6047 13:19:09.039308 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6048 13:19:09.042320 ===================================
6049 13:19:09.045864 LPDDR4 DRAM CONFIGURATION
6050 13:19:09.049003 ===================================
6051 13:19:09.049086 EX_ROW_EN[0] = 0x0
6052 13:19:09.052570 EX_ROW_EN[1] = 0x0
6053 13:19:09.055682 LP4Y_EN = 0x0
6054 13:19:09.055783 WORK_FSP = 0x0
6055 13:19:09.059093 WL = 0x2
6056 13:19:09.059178 RL = 0x2
6057 13:19:09.062349 BL = 0x2
6058 13:19:09.062417 RPST = 0x0
6059 13:19:09.065411 RD_PRE = 0x0
6060 13:19:09.065504 WR_PRE = 0x1
6061 13:19:09.069115 WR_PST = 0x0
6062 13:19:09.069218 DBI_WR = 0x0
6063 13:19:09.072401 DBI_RD = 0x0
6064 13:19:09.072491 OTF = 0x1
6065 13:19:09.075499 ===================================
6066 13:19:09.078855 ===================================
6067 13:19:09.082198 ANA top config
6068 13:19:09.085510 ===================================
6069 13:19:09.085603 DLL_ASYNC_EN = 0
6070 13:19:09.088759 ALL_SLAVE_EN = 1
6071 13:19:09.092018 NEW_RANK_MODE = 1
6072 13:19:09.095341 DLL_IDLE_MODE = 1
6073 13:19:09.098678 LP45_APHY_COMB_EN = 1
6074 13:19:09.098764 TX_ODT_DIS = 1
6075 13:19:09.102049 NEW_8X_MODE = 1
6076 13:19:09.105289 ===================================
6077 13:19:09.109149 ===================================
6078 13:19:09.112393 data_rate = 800
6079 13:19:09.115758 CKR = 1
6080 13:19:09.118967 DQ_P2S_RATIO = 4
6081 13:19:09.122188 ===================================
6082 13:19:09.122267 CA_P2S_RATIO = 4
6083 13:19:09.125257 DQ_CA_OPEN = 0
6084 13:19:09.128786 DQ_SEMI_OPEN = 1
6085 13:19:09.131966 CA_SEMI_OPEN = 1
6086 13:19:09.135099 CA_FULL_RATE = 0
6087 13:19:09.138805 DQ_CKDIV4_EN = 0
6088 13:19:09.138902 CA_CKDIV4_EN = 1
6089 13:19:09.142309 CA_PREDIV_EN = 0
6090 13:19:09.145650 PH8_DLY = 0
6091 13:19:09.148901 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6092 13:19:09.152085 DQ_AAMCK_DIV = 0
6093 13:19:09.155062 CA_AAMCK_DIV = 0
6094 13:19:09.155158 CA_ADMCK_DIV = 4
6095 13:19:09.158093 DQ_TRACK_CA_EN = 0
6096 13:19:09.161866 CA_PICK = 800
6097 13:19:09.165123 CA_MCKIO = 400
6098 13:19:09.168365 MCKIO_SEMI = 400
6099 13:19:09.171559 PLL_FREQ = 3016
6100 13:19:09.174653 DQ_UI_PI_RATIO = 32
6101 13:19:09.178045 CA_UI_PI_RATIO = 32
6102 13:19:09.181183 ===================================
6103 13:19:09.184683 ===================================
6104 13:19:09.184761 memory_type:LPDDR4
6105 13:19:09.188089 GP_NUM : 10
6106 13:19:09.191293 SRAM_EN : 1
6107 13:19:09.191397 MD32_EN : 0
6108 13:19:09.194547 ===================================
6109 13:19:09.197789 [ANA_INIT] >>>>>>>>>>>>>>
6110 13:19:09.201092 <<<<<< [CONFIGURE PHASE]: ANA_TX
6111 13:19:09.204470 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6112 13:19:09.207668 ===================================
6113 13:19:09.211068 data_rate = 800,PCW = 0X7400
6114 13:19:09.214391 ===================================
6115 13:19:09.217686 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6116 13:19:09.221512 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6117 13:19:09.234539 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6118 13:19:09.237750 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6119 13:19:09.240919 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6120 13:19:09.244162 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6121 13:19:09.247858 [ANA_INIT] flow start
6122 13:19:09.251033 [ANA_INIT] PLL >>>>>>>>
6123 13:19:09.251106 [ANA_INIT] PLL <<<<<<<<
6124 13:19:09.254489 [ANA_INIT] MIDPI >>>>>>>>
6125 13:19:09.257790 [ANA_INIT] MIDPI <<<<<<<<
6126 13:19:09.257867 [ANA_INIT] DLL >>>>>>>>
6127 13:19:09.261056 [ANA_INIT] flow end
6128 13:19:09.264026 ============ LP4 DIFF to SE enter ============
6129 13:19:09.267204 ============ LP4 DIFF to SE exit ============
6130 13:19:09.270747 [ANA_INIT] <<<<<<<<<<<<<
6131 13:19:09.273924 [Flow] Enable top DCM control >>>>>
6132 13:19:09.277641 [Flow] Enable top DCM control <<<<<
6133 13:19:09.281001 Enable DLL master slave shuffle
6134 13:19:09.287449 ==============================================================
6135 13:19:09.287559 Gating Mode config
6136 13:19:09.293770 ==============================================================
6137 13:19:09.293858 Config description:
6138 13:19:09.304107 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6139 13:19:09.310660 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6140 13:19:09.317425 SELPH_MODE 0: By rank 1: By Phase
6141 13:19:09.320713 ==============================================================
6142 13:19:09.324029 GAT_TRACK_EN = 0
6143 13:19:09.327264 RX_GATING_MODE = 2
6144 13:19:09.330527 RX_GATING_TRACK_MODE = 2
6145 13:19:09.333848 SELPH_MODE = 1
6146 13:19:09.337175 PICG_EARLY_EN = 1
6147 13:19:09.340344 VALID_LAT_VALUE = 1
6148 13:19:09.346803 ==============================================================
6149 13:19:09.349977 Enter into Gating configuration >>>>
6150 13:19:09.353668 Exit from Gating configuration <<<<
6151 13:19:09.357266 Enter into DVFS_PRE_config >>>>>
6152 13:19:09.366910 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6153 13:19:09.369999 Exit from DVFS_PRE_config <<<<<
6154 13:19:09.373556 Enter into PICG configuration >>>>
6155 13:19:09.377042 Exit from PICG configuration <<<<
6156 13:19:09.380142 [RX_INPUT] configuration >>>>>
6157 13:19:09.380210 [RX_INPUT] configuration <<<<<
6158 13:19:09.386752 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6159 13:19:09.393132 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6160 13:19:09.396800 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6161 13:19:09.403520 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6162 13:19:09.409947 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6163 13:19:09.416544 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6164 13:19:09.419856 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6165 13:19:09.423210 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6166 13:19:09.429653 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6167 13:19:09.433112 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6168 13:19:09.436489 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6169 13:19:09.442953 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6170 13:19:09.446286 ===================================
6171 13:19:09.446356 LPDDR4 DRAM CONFIGURATION
6172 13:19:09.449394 ===================================
6173 13:19:09.453313 EX_ROW_EN[0] = 0x0
6174 13:19:09.453382 EX_ROW_EN[1] = 0x0
6175 13:19:09.456632 LP4Y_EN = 0x0
6176 13:19:09.459838 WORK_FSP = 0x0
6177 13:19:09.459909 WL = 0x2
6178 13:19:09.462915 RL = 0x2
6179 13:19:09.462988 BL = 0x2
6180 13:19:09.466534 RPST = 0x0
6181 13:19:09.466627 RD_PRE = 0x0
6182 13:19:09.469816 WR_PRE = 0x1
6183 13:19:09.469906 WR_PST = 0x0
6184 13:19:09.472575 DBI_WR = 0x0
6185 13:19:09.472642 DBI_RD = 0x0
6186 13:19:09.475911 OTF = 0x1
6187 13:19:09.479749 ===================================
6188 13:19:09.482992 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6189 13:19:09.486367 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6190 13:19:09.489384 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6191 13:19:09.493056 ===================================
6192 13:19:09.496082 LPDDR4 DRAM CONFIGURATION
6193 13:19:09.499191 ===================================
6194 13:19:09.502919 EX_ROW_EN[0] = 0x10
6195 13:19:09.503012 EX_ROW_EN[1] = 0x0
6196 13:19:09.506188 LP4Y_EN = 0x0
6197 13:19:09.506252 WORK_FSP = 0x0
6198 13:19:09.509388 WL = 0x2
6199 13:19:09.509455 RL = 0x2
6200 13:19:09.512475 BL = 0x2
6201 13:19:09.516185 RPST = 0x0
6202 13:19:09.516309 RD_PRE = 0x0
6203 13:19:09.519385 WR_PRE = 0x1
6204 13:19:09.519460 WR_PST = 0x0
6205 13:19:09.522707 DBI_WR = 0x0
6206 13:19:09.522782 DBI_RD = 0x0
6207 13:19:09.526036 OTF = 0x1
6208 13:19:09.529434 ===================================
6209 13:19:09.532517 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6210 13:19:09.537790 nWR fixed to 30
6211 13:19:09.541246 [ModeRegInit_LP4] CH0 RK0
6212 13:19:09.541320 [ModeRegInit_LP4] CH0 RK1
6213 13:19:09.544518 [ModeRegInit_LP4] CH1 RK0
6214 13:19:09.547791 [ModeRegInit_LP4] CH1 RK1
6215 13:19:09.547866 match AC timing 19
6216 13:19:09.555054 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6217 13:19:09.558343 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6218 13:19:09.561640 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6219 13:19:09.568119 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6220 13:19:09.571217 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6221 13:19:09.571289 ==
6222 13:19:09.574270 Dram Type= 6, Freq= 0, CH_0, rank 0
6223 13:19:09.578084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6224 13:19:09.578215 ==
6225 13:19:09.584682 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6226 13:19:09.591236 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6227 13:19:09.594323 [CA 0] Center 36 (8~64) winsize 57
6228 13:19:09.597518 [CA 1] Center 36 (8~64) winsize 57
6229 13:19:09.601270 [CA 2] Center 36 (8~64) winsize 57
6230 13:19:09.604430 [CA 3] Center 36 (8~64) winsize 57
6231 13:19:09.604545 [CA 4] Center 36 (8~64) winsize 57
6232 13:19:09.607987 [CA 5] Center 36 (8~64) winsize 57
6233 13:19:09.608062
6234 13:19:09.614500 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6235 13:19:09.614574
6236 13:19:09.617743 [CATrainingPosCal] consider 1 rank data
6237 13:19:09.620971 u2DelayCellTimex100 = 270/100 ps
6238 13:19:09.624042 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 13:19:09.627598 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 13:19:09.631039 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 13:19:09.634441 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 13:19:09.637583 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 13:19:09.640728 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 13:19:09.640803
6245 13:19:09.644016 CA PerBit enable=1, Macro0, CA PI delay=36
6246 13:19:09.644107
6247 13:19:09.647326 [CBTSetCACLKResult] CA Dly = 36
6248 13:19:09.651121 CS Dly: 1 (0~32)
6249 13:19:09.651195 ==
6250 13:19:09.654282 Dram Type= 6, Freq= 0, CH_0, rank 1
6251 13:19:09.657511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6252 13:19:09.657589 ==
6253 13:19:09.664557 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6254 13:19:09.667706 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6255 13:19:09.671046 [CA 0] Center 36 (8~64) winsize 57
6256 13:19:09.674396 [CA 1] Center 36 (8~64) winsize 57
6257 13:19:09.677647 [CA 2] Center 36 (8~64) winsize 57
6258 13:19:09.680789 [CA 3] Center 36 (8~64) winsize 57
6259 13:19:09.684426 [CA 4] Center 36 (8~64) winsize 57
6260 13:19:09.687719 [CA 5] Center 36 (8~64) winsize 57
6261 13:19:09.687816
6262 13:19:09.691052 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6263 13:19:09.691128
6264 13:19:09.694372 [CATrainingPosCal] consider 2 rank data
6265 13:19:09.697720 u2DelayCellTimex100 = 270/100 ps
6266 13:19:09.700938 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 13:19:09.704138 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 13:19:09.710773 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 13:19:09.713996 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 13:19:09.717027 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 13:19:09.720533 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 13:19:09.720635
6273 13:19:09.724173 CA PerBit enable=1, Macro0, CA PI delay=36
6274 13:19:09.724248
6275 13:19:09.727239 [CBTSetCACLKResult] CA Dly = 36
6276 13:19:09.727334 CS Dly: 1 (0~32)
6277 13:19:09.727421
6278 13:19:09.730449 ----->DramcWriteLeveling(PI) begin...
6279 13:19:09.734247 ==
6280 13:19:09.734345 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 13:19:09.740802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 13:19:09.740883 ==
6283 13:19:09.744152 Write leveling (Byte 0): 40 => 8
6284 13:19:09.747548 Write leveling (Byte 1): 40 => 8
6285 13:19:09.747665 DramcWriteLeveling(PI) end<-----
6286 13:19:09.750188
6287 13:19:09.750285 ==
6288 13:19:09.753669 Dram Type= 6, Freq= 0, CH_0, rank 0
6289 13:19:09.756935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 13:19:09.757033 ==
6291 13:19:09.760226 [Gating] SW mode calibration
6292 13:19:09.767103 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6293 13:19:09.773168 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6294 13:19:09.776672 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6295 13:19:09.780086 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6296 13:19:09.783498 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6297 13:19:09.789893 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6298 13:19:09.793006 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6299 13:19:09.799755 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 13:19:09.803103 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6301 13:19:09.806397 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 13:19:09.812967 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6303 13:19:09.813041 Total UI for P1: 0, mck2ui 16
6304 13:19:09.816125 best dqsien dly found for B0: ( 0, 14, 24)
6305 13:19:09.819416 Total UI for P1: 0, mck2ui 16
6306 13:19:09.823213 best dqsien dly found for B1: ( 0, 14, 24)
6307 13:19:09.826366 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6308 13:19:09.832660 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6309 13:19:09.832732
6310 13:19:09.836112 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6311 13:19:09.839799 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6312 13:19:09.842990 [Gating] SW calibration Done
6313 13:19:09.843060 ==
6314 13:19:09.846195 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 13:19:09.849422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 13:19:09.849489 ==
6317 13:19:09.852746 RX Vref Scan: 0
6318 13:19:09.852824
6319 13:19:09.852882 RX Vref 0 -> 0, step: 1
6320 13:19:09.852936
6321 13:19:09.856186 RX Delay -410 -> 252, step: 16
6322 13:19:09.859400 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6323 13:19:09.866208 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6324 13:19:09.869497 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6325 13:19:09.872762 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6326 13:19:09.876128 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6327 13:19:09.883010 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6328 13:19:09.886291 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6329 13:19:09.889607 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6330 13:19:09.892926 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6331 13:19:09.899054 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6332 13:19:09.902659 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6333 13:19:09.906009 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6334 13:19:09.912413 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6335 13:19:09.915560 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6336 13:19:09.919270 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6337 13:19:09.922597 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6338 13:19:09.922671 ==
6339 13:19:09.925853 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 13:19:09.932213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 13:19:09.932289 ==
6342 13:19:09.932348 DQS Delay:
6343 13:19:09.935525 DQS0 = 59, DQS1 = 59
6344 13:19:09.935599 DQM Delay:
6345 13:19:09.939372 DQM0 = 18, DQM1 = 10
6346 13:19:09.939447 DQ Delay:
6347 13:19:09.942424 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6348 13:19:09.945934 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6349 13:19:09.949377 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6350 13:19:09.952322 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6351 13:19:09.952396
6352 13:19:09.952453
6353 13:19:09.952506 ==
6354 13:19:09.956088 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 13:19:09.959129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 13:19:09.959222 ==
6357 13:19:09.959279
6358 13:19:09.959330
6359 13:19:09.962488 TX Vref Scan disable
6360 13:19:09.962562 == TX Byte 0 ==
6361 13:19:09.965640 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6362 13:19:09.972207 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6363 13:19:09.972282 == TX Byte 1 ==
6364 13:19:09.975591 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6365 13:19:09.982160 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6366 13:19:09.982235 ==
6367 13:19:09.985354 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 13:19:09.989207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 13:19:09.989282 ==
6370 13:19:09.989339
6371 13:19:09.989392
6372 13:19:09.991963 TX Vref Scan disable
6373 13:19:09.992038 == TX Byte 0 ==
6374 13:19:09.999142 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6375 13:19:10.002488 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6376 13:19:10.002563 == TX Byte 1 ==
6377 13:19:10.008625 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6378 13:19:10.012139 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6379 13:19:10.012229
6380 13:19:10.012287 [DATLAT]
6381 13:19:10.015431 Freq=400, CH0 RK0
6382 13:19:10.015505
6383 13:19:10.015561 DATLAT Default: 0xf
6384 13:19:10.018647 0, 0xFFFF, sum = 0
6385 13:19:10.018723 1, 0xFFFF, sum = 0
6386 13:19:10.021795 2, 0xFFFF, sum = 0
6387 13:19:10.021870 3, 0xFFFF, sum = 0
6388 13:19:10.025180 4, 0xFFFF, sum = 0
6389 13:19:10.025256 5, 0xFFFF, sum = 0
6390 13:19:10.028438 6, 0xFFFF, sum = 0
6391 13:19:10.028514 7, 0xFFFF, sum = 0
6392 13:19:10.032300 8, 0xFFFF, sum = 0
6393 13:19:10.032376 9, 0xFFFF, sum = 0
6394 13:19:10.035665 10, 0xFFFF, sum = 0
6395 13:19:10.035741 11, 0xFFFF, sum = 0
6396 13:19:10.038919 12, 0xFFFF, sum = 0
6397 13:19:10.042258 13, 0x0, sum = 1
6398 13:19:10.042344 14, 0x0, sum = 2
6399 13:19:10.042403 15, 0x0, sum = 3
6400 13:19:10.045480 16, 0x0, sum = 4
6401 13:19:10.045556 best_step = 14
6402 13:19:10.045613
6403 13:19:10.045665 ==
6404 13:19:10.048773 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 13:19:10.055032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 13:19:10.055113 ==
6407 13:19:10.055172 RX Vref Scan: 1
6408 13:19:10.055225
6409 13:19:10.058255 RX Vref 0 -> 0, step: 1
6410 13:19:10.058329
6411 13:19:10.061817 RX Delay -359 -> 252, step: 8
6412 13:19:10.061920
6413 13:19:10.065373 Set Vref, RX VrefLevel [Byte0]: 61
6414 13:19:10.068046 [Byte1]: 53
6415 13:19:10.072082
6416 13:19:10.072156 Final RX Vref Byte 0 = 61 to rank0
6417 13:19:10.075070 Final RX Vref Byte 1 = 53 to rank0
6418 13:19:10.078445 Final RX Vref Byte 0 = 61 to rank1
6419 13:19:10.081576 Final RX Vref Byte 1 = 53 to rank1==
6420 13:19:10.085029 Dram Type= 6, Freq= 0, CH_0, rank 0
6421 13:19:10.091590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 13:19:10.091676 ==
6423 13:19:10.091734 DQS Delay:
6424 13:19:10.094843 DQS0 = 60, DQS1 = 68
6425 13:19:10.094917 DQM Delay:
6426 13:19:10.094974 DQM0 = 13, DQM1 = 13
6427 13:19:10.098146 DQ Delay:
6428 13:19:10.102066 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6429 13:19:10.102163 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6430 13:19:10.105300 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6431 13:19:10.108551 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6432 13:19:10.111941
6433 13:19:10.112015
6434 13:19:10.118126 [DQSOSCAuto] RK0, (LSB)MR18= 0x8684, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6435 13:19:10.121218 CH0 RK0: MR19=C0C, MR18=8684
6436 13:19:10.128218 CH0_RK0: MR19=0xC0C, MR18=0x8684, DQSOSC=393, MR23=63, INC=382, DEC=254
6437 13:19:10.128298 ==
6438 13:19:10.131470 Dram Type= 6, Freq= 0, CH_0, rank 1
6439 13:19:10.134651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6440 13:19:10.134725 ==
6441 13:19:10.137952 [Gating] SW mode calibration
6442 13:19:10.144557 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6443 13:19:10.151124 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6444 13:19:10.154429 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6445 13:19:10.157669 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6446 13:19:10.164867 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6447 13:19:10.168150 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6448 13:19:10.171450 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 13:19:10.177550 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 13:19:10.181141 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 13:19:10.184537 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 13:19:10.190941 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6453 13:19:10.191020 Total UI for P1: 0, mck2ui 16
6454 13:19:10.194567 best dqsien dly found for B0: ( 0, 14, 24)
6455 13:19:10.197672 Total UI for P1: 0, mck2ui 16
6456 13:19:10.201015 best dqsien dly found for B1: ( 0, 14, 24)
6457 13:19:10.207558 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6458 13:19:10.210840 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6459 13:19:10.210917
6460 13:19:10.214048 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6461 13:19:10.217359 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6462 13:19:10.220716 [Gating] SW calibration Done
6463 13:19:10.220793 ==
6464 13:19:10.224048 Dram Type= 6, Freq= 0, CH_0, rank 1
6465 13:19:10.227540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 13:19:10.227620 ==
6467 13:19:10.231159 RX Vref Scan: 0
6468 13:19:10.231235
6469 13:19:10.231313 RX Vref 0 -> 0, step: 1
6470 13:19:10.231384
6471 13:19:10.234351 RX Delay -410 -> 252, step: 16
6472 13:19:10.241100 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6473 13:19:10.244143 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6474 13:19:10.247471 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6475 13:19:10.250742 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6476 13:19:10.257293 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6477 13:19:10.260480 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6478 13:19:10.263776 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6479 13:19:10.267114 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6480 13:19:10.273774 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6481 13:19:10.277136 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6482 13:19:10.280407 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6483 13:19:10.283723 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6484 13:19:10.290376 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6485 13:19:10.294174 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6486 13:19:10.297247 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6487 13:19:10.299999 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6488 13:19:10.303750 ==
6489 13:19:10.307179 Dram Type= 6, Freq= 0, CH_0, rank 1
6490 13:19:10.310462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 13:19:10.310540 ==
6492 13:19:10.310599 DQS Delay:
6493 13:19:10.313542 DQS0 = 59, DQS1 = 59
6494 13:19:10.313619 DQM Delay:
6495 13:19:10.317195 DQM0 = 16, DQM1 = 10
6496 13:19:10.317272 DQ Delay:
6497 13:19:10.320416 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6498 13:19:10.323790 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6499 13:19:10.327025 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6500 13:19:10.330255 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6501 13:19:10.330333
6502 13:19:10.330392
6503 13:19:10.330446 ==
6504 13:19:10.333951 Dram Type= 6, Freq= 0, CH_0, rank 1
6505 13:19:10.336821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6506 13:19:10.336900 ==
6507 13:19:10.336959
6508 13:19:10.337014
6509 13:19:10.340110 TX Vref Scan disable
6510 13:19:10.340186 == TX Byte 0 ==
6511 13:19:10.346839 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6512 13:19:10.349833 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6513 13:19:10.349911 == TX Byte 1 ==
6514 13:19:10.356504 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6515 13:19:10.359760 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6516 13:19:10.359838 ==
6517 13:19:10.363175 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 13:19:10.366364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 13:19:10.366445 ==
6520 13:19:10.366522
6521 13:19:10.369667
6522 13:19:10.369734 TX Vref Scan disable
6523 13:19:10.372955 == TX Byte 0 ==
6524 13:19:10.376318 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6525 13:19:10.379529 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6526 13:19:10.382896 == TX Byte 1 ==
6527 13:19:10.386176 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6528 13:19:10.389556 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6529 13:19:10.389635
6530 13:19:10.389713 [DATLAT]
6531 13:19:10.393567 Freq=400, CH0 RK1
6532 13:19:10.393647
6533 13:19:10.396179 DATLAT Default: 0xe
6534 13:19:10.396257 0, 0xFFFF, sum = 0
6535 13:19:10.400106 1, 0xFFFF, sum = 0
6536 13:19:10.400186 2, 0xFFFF, sum = 0
6537 13:19:10.403474 3, 0xFFFF, sum = 0
6538 13:19:10.403554 4, 0xFFFF, sum = 0
6539 13:19:10.406595 5, 0xFFFF, sum = 0
6540 13:19:10.406675 6, 0xFFFF, sum = 0
6541 13:19:10.409790 7, 0xFFFF, sum = 0
6542 13:19:10.409885 8, 0xFFFF, sum = 0
6543 13:19:10.413028 9, 0xFFFF, sum = 0
6544 13:19:10.413107 10, 0xFFFF, sum = 0
6545 13:19:10.416684 11, 0xFFFF, sum = 0
6546 13:19:10.416763 12, 0xFFFF, sum = 0
6547 13:19:10.420067 13, 0x0, sum = 1
6548 13:19:10.420145 14, 0x0, sum = 2
6549 13:19:10.422872 15, 0x0, sum = 3
6550 13:19:10.422974 16, 0x0, sum = 4
6551 13:19:10.426597 best_step = 14
6552 13:19:10.426695
6553 13:19:10.426788 ==
6554 13:19:10.429777 Dram Type= 6, Freq= 0, CH_0, rank 1
6555 13:19:10.432877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6556 13:19:10.432958 ==
6557 13:19:10.436234 RX Vref Scan: 0
6558 13:19:10.436311
6559 13:19:10.436385 RX Vref 0 -> 0, step: 1
6560 13:19:10.436522
6561 13:19:10.439950 RX Delay -359 -> 252, step: 8
6562 13:19:10.447464 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6563 13:19:10.450949 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6564 13:19:10.453589 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6565 13:19:10.460663 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6566 13:19:10.463582 iDelay=217, Bit 4, Center -48 (-295 ~ 200) 496
6567 13:19:10.467538 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6568 13:19:10.470311 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6569 13:19:10.473734 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6570 13:19:10.480710 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6571 13:19:10.483992 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6572 13:19:10.487483 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6573 13:19:10.493549 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6574 13:19:10.496976 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6575 13:19:10.500383 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6576 13:19:10.503969 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6577 13:19:10.510036 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6578 13:19:10.510126 ==
6579 13:19:10.513455 Dram Type= 6, Freq= 0, CH_0, rank 1
6580 13:19:10.516893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6581 13:19:10.516987 ==
6582 13:19:10.517061 DQS Delay:
6583 13:19:10.520142 DQS0 = 60, DQS1 = 72
6584 13:19:10.520219 DQM Delay:
6585 13:19:10.523368 DQM0 = 12, DQM1 = 17
6586 13:19:10.523446 DQ Delay:
6587 13:19:10.526540 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6588 13:19:10.530367 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =24
6589 13:19:10.533497 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6590 13:19:10.536593 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6591 13:19:10.536697
6592 13:19:10.536783
6593 13:19:10.543097 [DQSOSCAuto] RK1, (LSB)MR18= 0xd087, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 384 ps
6594 13:19:10.546434 CH0 RK1: MR19=C0C, MR18=D087
6595 13:19:10.553592 CH0_RK1: MR19=0xC0C, MR18=0xD087, DQSOSC=384, MR23=63, INC=400, DEC=267
6596 13:19:10.556385 [RxdqsGatingPostProcess] freq 400
6597 13:19:10.563091 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6598 13:19:10.566787 best DQS0 dly(2T, 0.5T) = (0, 10)
6599 13:19:10.566891 best DQS1 dly(2T, 0.5T) = (0, 10)
6600 13:19:10.569946 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6601 13:19:10.572961 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6602 13:19:10.576663 best DQS0 dly(2T, 0.5T) = (0, 10)
6603 13:19:10.579754 best DQS1 dly(2T, 0.5T) = (0, 10)
6604 13:19:10.583202 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6605 13:19:10.586544 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6606 13:19:10.589913 Pre-setting of DQS Precalculation
6607 13:19:10.596685 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6608 13:19:10.596766 ==
6609 13:19:10.599419 Dram Type= 6, Freq= 0, CH_1, rank 0
6610 13:19:10.602930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 13:19:10.603013 ==
6612 13:19:10.609984 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6613 13:19:10.612647 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6614 13:19:10.616082 [CA 0] Center 36 (8~64) winsize 57
6615 13:19:10.619355 [CA 1] Center 36 (8~64) winsize 57
6616 13:19:10.622777 [CA 2] Center 36 (8~64) winsize 57
6617 13:19:10.626039 [CA 3] Center 36 (8~64) winsize 57
6618 13:19:10.629445 [CA 4] Center 36 (8~64) winsize 57
6619 13:19:10.632710 [CA 5] Center 36 (8~64) winsize 57
6620 13:19:10.632787
6621 13:19:10.636233 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6622 13:19:10.636311
6623 13:19:10.639679 [CATrainingPosCal] consider 1 rank data
6624 13:19:10.642772 u2DelayCellTimex100 = 270/100 ps
6625 13:19:10.645781 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 13:19:10.649403 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 13:19:10.655790 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 13:19:10.659435 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 13:19:10.662690 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 13:19:10.665966 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 13:19:10.666044
6632 13:19:10.669490 CA PerBit enable=1, Macro0, CA PI delay=36
6633 13:19:10.669568
6634 13:19:10.672914 [CBTSetCACLKResult] CA Dly = 36
6635 13:19:10.672992 CS Dly: 1 (0~32)
6636 13:19:10.675624 ==
6637 13:19:10.675701 Dram Type= 6, Freq= 0, CH_1, rank 1
6638 13:19:10.682349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6639 13:19:10.682428 ==
6640 13:19:10.685622 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6641 13:19:10.692127 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6642 13:19:10.696096 [CA 0] Center 36 (8~64) winsize 57
6643 13:19:10.698853 [CA 1] Center 36 (8~64) winsize 57
6644 13:19:10.702337 [CA 2] Center 36 (8~64) winsize 57
6645 13:19:10.705664 [CA 3] Center 36 (8~64) winsize 57
6646 13:19:10.709204 [CA 4] Center 36 (8~64) winsize 57
6647 13:19:10.712516 [CA 5] Center 36 (8~64) winsize 57
6648 13:19:10.712593
6649 13:19:10.715867 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6650 13:19:10.715944
6651 13:19:10.718656 [CATrainingPosCal] consider 2 rank data
6652 13:19:10.722136 u2DelayCellTimex100 = 270/100 ps
6653 13:19:10.725374 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 13:19:10.728886 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 13:19:10.732365 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 13:19:10.735640 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 13:19:10.742256 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 13:19:10.745644 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 13:19:10.745721
6660 13:19:10.748404 CA PerBit enable=1, Macro0, CA PI delay=36
6661 13:19:10.748481
6662 13:19:10.751619 [CBTSetCACLKResult] CA Dly = 36
6663 13:19:10.751696 CS Dly: 1 (0~32)
6664 13:19:10.751756
6665 13:19:10.755505 ----->DramcWriteLeveling(PI) begin...
6666 13:19:10.755583 ==
6667 13:19:10.758511 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 13:19:10.765450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 13:19:10.765529 ==
6670 13:19:10.768466 Write leveling (Byte 0): 40 => 8
6671 13:19:10.768543 Write leveling (Byte 1): 40 => 8
6672 13:19:10.771456 DramcWriteLeveling(PI) end<-----
6673 13:19:10.771533
6674 13:19:10.774973 ==
6675 13:19:10.775076 Dram Type= 6, Freq= 0, CH_1, rank 0
6676 13:19:10.781477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 13:19:10.781556 ==
6678 13:19:10.784901 [Gating] SW mode calibration
6679 13:19:10.791822 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6680 13:19:10.795099 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6681 13:19:10.801468 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6682 13:19:10.804538 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6683 13:19:10.807944 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6684 13:19:10.814956 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6685 13:19:10.818371 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6686 13:19:10.821692 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 13:19:10.828341 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6688 13:19:10.831182 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 13:19:10.834500 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6690 13:19:10.837976 Total UI for P1: 0, mck2ui 16
6691 13:19:10.841340 best dqsien dly found for B0: ( 0, 14, 24)
6692 13:19:10.844566 Total UI for P1: 0, mck2ui 16
6693 13:19:10.847979 best dqsien dly found for B1: ( 0, 14, 24)
6694 13:19:10.851444 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6695 13:19:10.854372 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6696 13:19:10.854449
6697 13:19:10.861287 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6698 13:19:10.864646 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6699 13:19:10.864723 [Gating] SW calibration Done
6700 13:19:10.867765 ==
6701 13:19:10.867842 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 13:19:10.874719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 13:19:10.874797 ==
6704 13:19:10.874856 RX Vref Scan: 0
6705 13:19:10.874912
6706 13:19:10.877900 RX Vref 0 -> 0, step: 1
6707 13:19:10.877976
6708 13:19:10.881249 RX Delay -410 -> 252, step: 16
6709 13:19:10.884439 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6710 13:19:10.887575 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6711 13:19:10.894543 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6712 13:19:10.897553 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6713 13:19:10.900959 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6714 13:19:10.904460 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6715 13:19:10.911031 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6716 13:19:10.914127 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6717 13:19:10.917437 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6718 13:19:10.920726 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6719 13:19:10.927545 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6720 13:19:10.930954 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6721 13:19:10.934357 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6722 13:19:10.940551 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6723 13:19:10.943920 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6724 13:19:10.946953 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6725 13:19:10.947032 ==
6726 13:19:10.950317 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 13:19:10.954040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 13:19:10.957324 ==
6729 13:19:10.957392 DQS Delay:
6730 13:19:10.957464 DQS0 = 51, DQS1 = 67
6731 13:19:10.960755 DQM Delay:
6732 13:19:10.960835 DQM0 = 12, DQM1 = 17
6733 13:19:10.964098 DQ Delay:
6734 13:19:10.964198 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6735 13:19:10.966945 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6736 13:19:10.970250 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6737 13:19:10.973593 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6738 13:19:10.973668
6739 13:19:10.973726
6740 13:19:10.977280 ==
6741 13:19:10.980530 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 13:19:10.983357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 13:19:10.983441 ==
6744 13:19:10.983519
6745 13:19:10.983590
6746 13:19:10.986697 TX Vref Scan disable
6747 13:19:10.986770 == TX Byte 0 ==
6748 13:19:10.990264 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6749 13:19:10.996855 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6750 13:19:10.996968 == TX Byte 1 ==
6751 13:19:11.000192 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6752 13:19:11.007091 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6753 13:19:11.007169 ==
6754 13:19:11.009954 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 13:19:11.013361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 13:19:11.013435 ==
6757 13:19:11.013495
6758 13:19:11.013549
6759 13:19:11.016924 TX Vref Scan disable
6760 13:19:11.016993 == TX Byte 0 ==
6761 13:19:11.019853 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6762 13:19:11.026525 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6763 13:19:11.026622 == TX Byte 1 ==
6764 13:19:11.030005 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6765 13:19:11.036803 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6766 13:19:11.036886
6767 13:19:11.036947 [DATLAT]
6768 13:19:11.037002 Freq=400, CH1 RK0
6769 13:19:11.037055
6770 13:19:11.040221 DATLAT Default: 0xf
6771 13:19:11.043002 0, 0xFFFF, sum = 0
6772 13:19:11.043102 1, 0xFFFF, sum = 0
6773 13:19:11.046529 2, 0xFFFF, sum = 0
6774 13:19:11.046599 3, 0xFFFF, sum = 0
6775 13:19:11.049855 4, 0xFFFF, sum = 0
6776 13:19:11.049951 5, 0xFFFF, sum = 0
6777 13:19:11.053194 6, 0xFFFF, sum = 0
6778 13:19:11.053272 7, 0xFFFF, sum = 0
6779 13:19:11.056744 8, 0xFFFF, sum = 0
6780 13:19:11.056822 9, 0xFFFF, sum = 0
6781 13:19:11.060206 10, 0xFFFF, sum = 0
6782 13:19:11.060283 11, 0xFFFF, sum = 0
6783 13:19:11.063002 12, 0xFFFF, sum = 0
6784 13:19:11.063080 13, 0x0, sum = 1
6785 13:19:11.066203 14, 0x0, sum = 2
6786 13:19:11.066280 15, 0x0, sum = 3
6787 13:19:11.069628 16, 0x0, sum = 4
6788 13:19:11.069731 best_step = 14
6789 13:19:11.069816
6790 13:19:11.069897 ==
6791 13:19:11.073225 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 13:19:11.079949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 13:19:11.080037 ==
6794 13:19:11.080132 RX Vref Scan: 1
6795 13:19:11.080223
6796 13:19:11.083224 RX Vref 0 -> 0, step: 1
6797 13:19:11.083308
6798 13:19:11.086601 RX Delay -375 -> 252, step: 8
6799 13:19:11.086696
6800 13:19:11.089622 Set Vref, RX VrefLevel [Byte0]: 57
6801 13:19:11.092689 [Byte1]: 48
6802 13:19:11.092771
6803 13:19:11.096571 Final RX Vref Byte 0 = 57 to rank0
6804 13:19:11.100001 Final RX Vref Byte 1 = 48 to rank0
6805 13:19:11.102585 Final RX Vref Byte 0 = 57 to rank1
6806 13:19:11.106132 Final RX Vref Byte 1 = 48 to rank1==
6807 13:19:11.109610 Dram Type= 6, Freq= 0, CH_1, rank 0
6808 13:19:11.112975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 13:19:11.116275 ==
6810 13:19:11.116354 DQS Delay:
6811 13:19:11.116433 DQS0 = 56, DQS1 = 68
6812 13:19:11.119679 DQM Delay:
6813 13:19:11.119758 DQM0 = 13, DQM1 = 14
6814 13:19:11.122602 DQ Delay:
6815 13:19:11.122681 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6816 13:19:11.126406 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6817 13:19:11.129210 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6818 13:19:11.133058 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6819 13:19:11.133161
6820 13:19:11.133247
6821 13:19:11.143153 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c6e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
6822 13:19:11.146373 CH1 RK0: MR19=C0C, MR18=5C6E
6823 13:19:11.149230 CH1_RK0: MR19=0xC0C, MR18=0x5C6E, DQSOSC=395, MR23=63, INC=378, DEC=252
6824 13:19:11.152624 ==
6825 13:19:11.155805 Dram Type= 6, Freq= 0, CH_1, rank 1
6826 13:19:11.159235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6827 13:19:11.159309 ==
6828 13:19:11.162713 [Gating] SW mode calibration
6829 13:19:11.169303 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6830 13:19:11.172603 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6831 13:19:11.179538 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6832 13:19:11.182966 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6833 13:19:11.186119 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6834 13:19:11.192368 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6835 13:19:11.195659 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6836 13:19:11.199482 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 13:19:11.205706 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6838 13:19:11.208975 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 13:19:11.212335 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6840 13:19:11.215708 Total UI for P1: 0, mck2ui 16
6841 13:19:11.219188 best dqsien dly found for B0: ( 0, 14, 24)
6842 13:19:11.222579 Total UI for P1: 0, mck2ui 16
6843 13:19:11.225265 best dqsien dly found for B1: ( 0, 14, 24)
6844 13:19:11.229153 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6845 13:19:11.232264 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6846 13:19:11.235238
6847 13:19:11.238729 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6848 13:19:11.242170 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6849 13:19:11.245023 [Gating] SW calibration Done
6850 13:19:11.245100 ==
6851 13:19:11.248424 Dram Type= 6, Freq= 0, CH_1, rank 1
6852 13:19:11.252259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 13:19:11.252336 ==
6854 13:19:11.252396 RX Vref Scan: 0
6855 13:19:11.254964
6856 13:19:11.255040 RX Vref 0 -> 0, step: 1
6857 13:19:11.255100
6858 13:19:11.258938 RX Delay -410 -> 252, step: 16
6859 13:19:11.261772 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6860 13:19:11.268257 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6861 13:19:11.272037 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6862 13:19:11.274776 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6863 13:19:11.278192 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6864 13:19:11.284935 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6865 13:19:11.288211 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6866 13:19:11.291532 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6867 13:19:11.295015 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6868 13:19:11.301697 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6869 13:19:11.305040 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6870 13:19:11.308347 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6871 13:19:11.314693 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6872 13:19:11.317907 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6873 13:19:11.321239 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6874 13:19:11.324547 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6875 13:19:11.324628 ==
6876 13:19:11.328003 Dram Type= 6, Freq= 0, CH_1, rank 1
6877 13:19:11.334637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 13:19:11.334740 ==
6879 13:19:11.334812 DQS Delay:
6880 13:19:11.337771 DQS0 = 59, DQS1 = 59
6881 13:19:11.337848 DQM Delay:
6882 13:19:11.341213 DQM0 = 19, DQM1 = 12
6883 13:19:11.341290 DQ Delay:
6884 13:19:11.344216 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6885 13:19:11.347868 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6886 13:19:11.351145 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6887 13:19:11.354411 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6888 13:19:11.354502
6889 13:19:11.354586
6890 13:19:11.354643 ==
6891 13:19:11.357170 Dram Type= 6, Freq= 0, CH_1, rank 1
6892 13:19:11.360542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6893 13:19:11.360619 ==
6894 13:19:11.360685
6895 13:19:11.360750
6896 13:19:11.364092 TX Vref Scan disable
6897 13:19:11.364166 == TX Byte 0 ==
6898 13:19:11.370936 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6899 13:19:11.374230 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6900 13:19:11.374304 == TX Byte 1 ==
6901 13:19:11.380379 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6902 13:19:11.383873 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6903 13:19:11.383946 ==
6904 13:19:11.387254 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 13:19:11.390306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 13:19:11.390394 ==
6907 13:19:11.390467
6908 13:19:11.393981
6909 13:19:11.394057 TX Vref Scan disable
6910 13:19:11.397362 == TX Byte 0 ==
6911 13:19:11.400748 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6912 13:19:11.404017 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6913 13:19:11.406560 == TX Byte 1 ==
6914 13:19:11.410066 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6915 13:19:11.413415 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6916 13:19:11.413488
6917 13:19:11.416834 [DATLAT]
6918 13:19:11.416911 Freq=400, CH1 RK1
6919 13:19:11.416971
6920 13:19:11.420016 DATLAT Default: 0xe
6921 13:19:11.420092 0, 0xFFFF, sum = 0
6922 13:19:11.423221 1, 0xFFFF, sum = 0
6923 13:19:11.423316 2, 0xFFFF, sum = 0
6924 13:19:11.427022 3, 0xFFFF, sum = 0
6925 13:19:11.427101 4, 0xFFFF, sum = 0
6926 13:19:11.430395 5, 0xFFFF, sum = 0
6927 13:19:11.430473 6, 0xFFFF, sum = 0
6928 13:19:11.433210 7, 0xFFFF, sum = 0
6929 13:19:11.433288 8, 0xFFFF, sum = 0
6930 13:19:11.436521 9, 0xFFFF, sum = 0
6931 13:19:11.436599 10, 0xFFFF, sum = 0
6932 13:19:11.439899 11, 0xFFFF, sum = 0
6933 13:19:11.440004 12, 0xFFFF, sum = 0
6934 13:19:11.443329 13, 0x0, sum = 1
6935 13:19:11.443415 14, 0x0, sum = 2
6936 13:19:11.446734 15, 0x0, sum = 3
6937 13:19:11.446803 16, 0x0, sum = 4
6938 13:19:11.450208 best_step = 14
6939 13:19:11.450278
6940 13:19:11.450352 ==
6941 13:19:11.453239 Dram Type= 6, Freq= 0, CH_1, rank 1
6942 13:19:11.456415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6943 13:19:11.456520 ==
6944 13:19:11.459664 RX Vref Scan: 0
6945 13:19:11.459735
6946 13:19:11.459792 RX Vref 0 -> 0, step: 1
6947 13:19:11.459846
6948 13:19:11.462755 RX Delay -359 -> 252, step: 8
6949 13:19:11.471369 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6950 13:19:11.474898 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6951 13:19:11.478232 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6952 13:19:11.484424 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6953 13:19:11.487764 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6954 13:19:11.491055 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6955 13:19:11.494129 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6956 13:19:11.500709 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6957 13:19:11.504279 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6958 13:19:11.508035 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6959 13:19:11.511066 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6960 13:19:11.517463 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6961 13:19:11.520914 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6962 13:19:11.524412 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6963 13:19:11.527376 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6964 13:19:11.533795 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6965 13:19:11.533904 ==
6966 13:19:11.537092 Dram Type= 6, Freq= 0, CH_1, rank 1
6967 13:19:11.540457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6968 13:19:11.540528 ==
6969 13:19:11.540585 DQS Delay:
6970 13:19:11.543779 DQS0 = 60, DQS1 = 64
6971 13:19:11.543843 DQM Delay:
6972 13:19:11.547080 DQM0 = 12, DQM1 = 10
6973 13:19:11.547143 DQ Delay:
6974 13:19:11.550400 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6975 13:19:11.553674 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6976 13:19:11.557053 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6977 13:19:11.560298 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6978 13:19:11.560367
6979 13:19:11.560430
6980 13:19:11.567109 [DQSOSCAuto] RK1, (LSB)MR18= 0x81b1, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
6981 13:19:11.570425 CH1 RK1: MR19=C0C, MR18=81B1
6982 13:19:11.577261 CH1_RK1: MR19=0xC0C, MR18=0x81B1, DQSOSC=387, MR23=63, INC=394, DEC=262
6983 13:19:11.580372 [RxdqsGatingPostProcess] freq 400
6984 13:19:11.587061 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6985 13:19:11.590357 best DQS0 dly(2T, 0.5T) = (0, 10)
6986 13:19:11.593673 best DQS1 dly(2T, 0.5T) = (0, 10)
6987 13:19:11.596874 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6988 13:19:11.600172 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6989 13:19:11.600252 best DQS0 dly(2T, 0.5T) = (0, 10)
6990 13:19:11.603349 best DQS1 dly(2T, 0.5T) = (0, 10)
6991 13:19:11.606754 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6992 13:19:11.609915 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6993 13:19:11.613706 Pre-setting of DQS Precalculation
6994 13:19:11.620019 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6995 13:19:11.626626 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6996 13:19:11.633568 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6997 13:19:11.633645
6998 13:19:11.633703
6999 13:19:11.636661 [Calibration Summary] 800 Mbps
7000 13:19:11.636737 CH 0, Rank 0
7001 13:19:11.639769 SW Impedance : PASS
7002 13:19:11.642974 DUTY Scan : NO K
7003 13:19:11.643050 ZQ Calibration : PASS
7004 13:19:11.646238 Jitter Meter : NO K
7005 13:19:11.649526 CBT Training : PASS
7006 13:19:11.649602 Write leveling : PASS
7007 13:19:11.653469 RX DQS gating : PASS
7008 13:19:11.656657 RX DQ/DQS(RDDQC) : PASS
7009 13:19:11.656733 TX DQ/DQS : PASS
7010 13:19:11.659916 RX DATLAT : PASS
7011 13:19:11.663114 RX DQ/DQS(Engine): PASS
7012 13:19:11.663182 TX OE : NO K
7013 13:19:11.666408 All Pass.
7014 13:19:11.666478
7015 13:19:11.666536 CH 0, Rank 1
7016 13:19:11.669668 SW Impedance : PASS
7017 13:19:11.669732 DUTY Scan : NO K
7018 13:19:11.672790 ZQ Calibration : PASS
7019 13:19:11.672856 Jitter Meter : NO K
7020 13:19:11.676595 CBT Training : PASS
7021 13:19:11.679759 Write leveling : NO K
7022 13:19:11.679864 RX DQS gating : PASS
7023 13:19:11.682934 RX DQ/DQS(RDDQC) : PASS
7024 13:19:11.686074 TX DQ/DQS : PASS
7025 13:19:11.686194 RX DATLAT : PASS
7026 13:19:11.689969 RX DQ/DQS(Engine): PASS
7027 13:19:11.692630 TX OE : NO K
7028 13:19:11.692702 All Pass.
7029 13:19:11.692768
7030 13:19:11.692838 CH 1, Rank 0
7031 13:19:11.696592 SW Impedance : PASS
7032 13:19:11.699952 DUTY Scan : NO K
7033 13:19:11.700028 ZQ Calibration : PASS
7034 13:19:11.703124 Jitter Meter : NO K
7035 13:19:11.706265 CBT Training : PASS
7036 13:19:11.706341 Write leveling : PASS
7037 13:19:11.709411 RX DQS gating : PASS
7038 13:19:11.712704 RX DQ/DQS(RDDQC) : PASS
7039 13:19:11.712780 TX DQ/DQS : PASS
7040 13:19:11.715984 RX DATLAT : PASS
7041 13:19:11.719233 RX DQ/DQS(Engine): PASS
7042 13:19:11.719308 TX OE : NO K
7043 13:19:11.723044 All Pass.
7044 13:19:11.723119
7045 13:19:11.723178 CH 1, Rank 1
7046 13:19:11.726234 SW Impedance : PASS
7047 13:19:11.726309 DUTY Scan : NO K
7048 13:19:11.729337 ZQ Calibration : PASS
7049 13:19:11.732496 Jitter Meter : NO K
7050 13:19:11.732586 CBT Training : PASS
7051 13:19:11.736151 Write leveling : NO K
7052 13:19:11.736226 RX DQS gating : PASS
7053 13:19:11.739313 RX DQ/DQS(RDDQC) : PASS
7054 13:19:11.742864 TX DQ/DQS : PASS
7055 13:19:11.742947 RX DATLAT : PASS
7056 13:19:11.745809 RX DQ/DQS(Engine): PASS
7057 13:19:11.748912 TX OE : NO K
7058 13:19:11.748981 All Pass.
7059 13:19:11.749037
7060 13:19:11.752887 DramC Write-DBI off
7061 13:19:11.752962 PER_BANK_REFRESH: Hybrid Mode
7062 13:19:11.756116 TX_TRACKING: ON
7063 13:19:11.765948 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7064 13:19:11.769250 [FAST_K] Save calibration result to emmc
7065 13:19:11.772386 dramc_set_vcore_voltage set vcore to 725000
7066 13:19:11.772455 Read voltage for 1600, 0
7067 13:19:11.775642 Vio18 = 0
7068 13:19:11.775709 Vcore = 725000
7069 13:19:11.775764 Vdram = 0
7070 13:19:11.778874 Vddq = 0
7071 13:19:11.778954 Vmddr = 0
7072 13:19:11.782520 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7073 13:19:11.789059 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7074 13:19:11.792269 MEM_TYPE=3, freq_sel=13
7075 13:19:11.795937 sv_algorithm_assistance_LP4_3733
7076 13:19:11.799324 ============ PULL DRAM RESETB DOWN ============
7077 13:19:11.802563 ========== PULL DRAM RESETB DOWN end =========
7078 13:19:11.808985 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7079 13:19:11.812178 ===================================
7080 13:19:11.812248 LPDDR4 DRAM CONFIGURATION
7081 13:19:11.815495 ===================================
7082 13:19:11.818634 EX_ROW_EN[0] = 0x0
7083 13:19:11.818717 EX_ROW_EN[1] = 0x0
7084 13:19:11.822416 LP4Y_EN = 0x0
7085 13:19:11.825638 WORK_FSP = 0x1
7086 13:19:11.825714 WL = 0x5
7087 13:19:11.828918 RL = 0x5
7088 13:19:11.828987 BL = 0x2
7089 13:19:11.832176 RPST = 0x0
7090 13:19:11.832266 RD_PRE = 0x0
7091 13:19:11.835352 WR_PRE = 0x1
7092 13:19:11.835428 WR_PST = 0x1
7093 13:19:11.838552 DBI_WR = 0x0
7094 13:19:11.838627 DBI_RD = 0x0
7095 13:19:11.841889 OTF = 0x1
7096 13:19:11.845610 ===================================
7097 13:19:11.848683 ===================================
7098 13:19:11.848759 ANA top config
7099 13:19:11.852235 ===================================
7100 13:19:11.855531 DLL_ASYNC_EN = 0
7101 13:19:11.858638 ALL_SLAVE_EN = 0
7102 13:19:11.858709 NEW_RANK_MODE = 1
7103 13:19:11.861874 DLL_IDLE_MODE = 1
7104 13:19:11.865213 LP45_APHY_COMB_EN = 1
7105 13:19:11.868536 TX_ODT_DIS = 0
7106 13:19:11.871789 NEW_8X_MODE = 1
7107 13:19:11.875122 ===================================
7108 13:19:11.878424 ===================================
7109 13:19:11.878493 data_rate = 3200
7110 13:19:11.881756 CKR = 1
7111 13:19:11.884868 DQ_P2S_RATIO = 8
7112 13:19:11.888567 ===================================
7113 13:19:11.891772 CA_P2S_RATIO = 8
7114 13:19:11.895053 DQ_CA_OPEN = 0
7115 13:19:11.898472 DQ_SEMI_OPEN = 0
7116 13:19:11.898543 CA_SEMI_OPEN = 0
7117 13:19:11.901509 CA_FULL_RATE = 0
7118 13:19:11.904777 DQ_CKDIV4_EN = 0
7119 13:19:11.908033 CA_CKDIV4_EN = 0
7120 13:19:11.911273 CA_PREDIV_EN = 0
7121 13:19:11.915069 PH8_DLY = 12
7122 13:19:11.915138 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7123 13:19:11.918267 DQ_AAMCK_DIV = 4
7124 13:19:11.921564 CA_AAMCK_DIV = 4
7125 13:19:11.924786 CA_ADMCK_DIV = 4
7126 13:19:11.928096 DQ_TRACK_CA_EN = 0
7127 13:19:11.931321 CA_PICK = 1600
7128 13:19:11.934535 CA_MCKIO = 1600
7129 13:19:11.934613 MCKIO_SEMI = 0
7130 13:19:11.938333 PLL_FREQ = 3068
7131 13:19:11.941397 DQ_UI_PI_RATIO = 32
7132 13:19:11.944827 CA_UI_PI_RATIO = 0
7133 13:19:11.948090 ===================================
7134 13:19:11.951391 ===================================
7135 13:19:11.954635 memory_type:LPDDR4
7136 13:19:11.954711 GP_NUM : 10
7137 13:19:11.957645 SRAM_EN : 1
7138 13:19:11.961403 MD32_EN : 0
7139 13:19:11.964371 ===================================
7140 13:19:11.964447 [ANA_INIT] >>>>>>>>>>>>>>
7141 13:19:11.967604 <<<<<< [CONFIGURE PHASE]: ANA_TX
7142 13:19:11.970808 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7143 13:19:11.974217 ===================================
7144 13:19:11.977510 data_rate = 3200,PCW = 0X7600
7145 13:19:11.980822 ===================================
7146 13:19:11.984183 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7147 13:19:11.991313 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7148 13:19:11.994428 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7149 13:19:12.000672 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7150 13:19:12.003917 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7151 13:19:12.007203 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7152 13:19:12.011110 [ANA_INIT] flow start
7153 13:19:12.011185 [ANA_INIT] PLL >>>>>>>>
7154 13:19:12.014171 [ANA_INIT] PLL <<<<<<<<
7155 13:19:12.017260 [ANA_INIT] MIDPI >>>>>>>>
7156 13:19:12.017336 [ANA_INIT] MIDPI <<<<<<<<
7157 13:19:12.021041 [ANA_INIT] DLL >>>>>>>>
7158 13:19:12.024351 [ANA_INIT] DLL <<<<<<<<
7159 13:19:12.024426 [ANA_INIT] flow end
7160 13:19:12.027633 ============ LP4 DIFF to SE enter ============
7161 13:19:12.034223 ============ LP4 DIFF to SE exit ============
7162 13:19:12.034300 [ANA_INIT] <<<<<<<<<<<<<
7163 13:19:12.037475 [Flow] Enable top DCM control >>>>>
7164 13:19:12.040655 [Flow] Enable top DCM control <<<<<
7165 13:19:12.043873 Enable DLL master slave shuffle
7166 13:19:12.050791 ==============================================================
7167 13:19:12.054142 Gating Mode config
7168 13:19:12.057375 ==============================================================
7169 13:19:12.060615 Config description:
7170 13:19:12.070369 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7171 13:19:12.076753 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7172 13:19:12.080546 SELPH_MODE 0: By rank 1: By Phase
7173 13:19:12.087092 ==============================================================
7174 13:19:12.090381 GAT_TRACK_EN = 1
7175 13:19:12.093737 RX_GATING_MODE = 2
7176 13:19:12.097164 RX_GATING_TRACK_MODE = 2
7177 13:19:12.097240 SELPH_MODE = 1
7178 13:19:12.100379 PICG_EARLY_EN = 1
7179 13:19:12.103332 VALID_LAT_VALUE = 1
7180 13:19:12.109890 ==============================================================
7181 13:19:12.113183 Enter into Gating configuration >>>>
7182 13:19:12.116908 Exit from Gating configuration <<<<
7183 13:19:12.119947 Enter into DVFS_PRE_config >>>>>
7184 13:19:12.129726 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7185 13:19:12.132886 Exit from DVFS_PRE_config <<<<<
7186 13:19:12.136700 Enter into PICG configuration >>>>
7187 13:19:12.139725 Exit from PICG configuration <<<<
7188 13:19:12.143205 [RX_INPUT] configuration >>>>>
7189 13:19:12.146678 [RX_INPUT] configuration <<<<<
7190 13:19:12.149846 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7191 13:19:12.156304 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7192 13:19:12.162822 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7193 13:19:12.169436 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7194 13:19:12.176543 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7195 13:19:12.179737 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7196 13:19:12.186360 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7197 13:19:12.189452 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7198 13:19:12.192630 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7199 13:19:12.195998 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7200 13:19:12.202629 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7201 13:19:12.205919 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7202 13:19:12.209023 ===================================
7203 13:19:12.212694 LPDDR4 DRAM CONFIGURATION
7204 13:19:12.215992 ===================================
7205 13:19:12.216093 EX_ROW_EN[0] = 0x0
7206 13:19:12.219231 EX_ROW_EN[1] = 0x0
7207 13:19:12.219314 LP4Y_EN = 0x0
7208 13:19:12.222549 WORK_FSP = 0x1
7209 13:19:12.222616 WL = 0x5
7210 13:19:12.225822 RL = 0x5
7211 13:19:12.229008 BL = 0x2
7212 13:19:12.229078 RPST = 0x0
7213 13:19:12.232511 RD_PRE = 0x0
7214 13:19:12.232583 WR_PRE = 0x1
7215 13:19:12.235543 WR_PST = 0x1
7216 13:19:12.235612 DBI_WR = 0x0
7217 13:19:12.238962 DBI_RD = 0x0
7218 13:19:12.239040 OTF = 0x1
7219 13:19:12.241951 ===================================
7220 13:19:12.245530 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7221 13:19:12.252151 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7222 13:19:12.255294 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7223 13:19:12.258385 ===================================
7224 13:19:12.262242 LPDDR4 DRAM CONFIGURATION
7225 13:19:12.265419 ===================================
7226 13:19:12.265506 EX_ROW_EN[0] = 0x10
7227 13:19:12.268702 EX_ROW_EN[1] = 0x0
7228 13:19:12.268778 LP4Y_EN = 0x0
7229 13:19:12.271997 WORK_FSP = 0x1
7230 13:19:12.275281 WL = 0x5
7231 13:19:12.275353 RL = 0x5
7232 13:19:12.278530 BL = 0x2
7233 13:19:12.278607 RPST = 0x0
7234 13:19:12.281958 RD_PRE = 0x0
7235 13:19:12.282025 WR_PRE = 0x1
7236 13:19:12.285209 WR_PST = 0x1
7237 13:19:12.285287 DBI_WR = 0x0
7238 13:19:12.288381 DBI_RD = 0x0
7239 13:19:12.288448 OTF = 0x1
7240 13:19:12.291651 ===================================
7241 13:19:12.298233 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7242 13:19:12.298362 ==
7243 13:19:12.301982 Dram Type= 6, Freq= 0, CH_0, rank 0
7244 13:19:12.304742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7245 13:19:12.304821 ==
7246 13:19:12.308080 [Duty_Offset_Calibration]
7247 13:19:12.311963 B0:2 B1:0 CA:3
7248 13:19:12.312027
7249 13:19:12.315089 [DutyScan_Calibration_Flow] k_type=0
7250 13:19:12.323246
7251 13:19:12.323313 ==CLK 0==
7252 13:19:12.326580 Final CLK duty delay cell = 0
7253 13:19:12.330396 [0] MAX Duty = 5062%(X100), DQS PI = 22
7254 13:19:12.333564 [0] MIN Duty = 4907%(X100), DQS PI = 6
7255 13:19:12.333637 [0] AVG Duty = 4984%(X100)
7256 13:19:12.336827
7257 13:19:12.340125 CH0 CLK Duty spec in!! Max-Min= 155%
7258 13:19:12.343418 [DutyScan_Calibration_Flow] ====Done====
7259 13:19:12.343504
7260 13:19:12.346444 [DutyScan_Calibration_Flow] k_type=1
7261 13:19:12.363175
7262 13:19:12.363259 ==DQS 0 ==
7263 13:19:12.366714 Final DQS duty delay cell = 0
7264 13:19:12.369904 [0] MAX Duty = 5093%(X100), DQS PI = 30
7265 13:19:12.373302 [0] MIN Duty = 4875%(X100), DQS PI = 50
7266 13:19:12.376580 [0] AVG Duty = 4984%(X100)
7267 13:19:12.376657
7268 13:19:12.376715 ==DQS 1 ==
7269 13:19:12.379784 Final DQS duty delay cell = 0
7270 13:19:12.383105 [0] MAX Duty = 5156%(X100), DQS PI = 32
7271 13:19:12.386384 [0] MIN Duty = 5031%(X100), DQS PI = 10
7272 13:19:12.390335 [0] AVG Duty = 5093%(X100)
7273 13:19:12.390409
7274 13:19:12.392889 CH0 DQS 0 Duty spec in!! Max-Min= 218%
7275 13:19:12.392984
7276 13:19:12.396774 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7277 13:19:12.400020 [DutyScan_Calibration_Flow] ====Done====
7278 13:19:12.400095
7279 13:19:12.403157 [DutyScan_Calibration_Flow] k_type=3
7280 13:19:12.421451
7281 13:19:12.421529 ==DQM 0 ==
7282 13:19:12.424657 Final DQM duty delay cell = 0
7283 13:19:12.428216 [0] MAX Duty = 5156%(X100), DQS PI = 30
7284 13:19:12.431535 [0] MIN Duty = 4875%(X100), DQS PI = 0
7285 13:19:12.434917 [0] AVG Duty = 5015%(X100)
7286 13:19:12.434991
7287 13:19:12.435049 ==DQM 1 ==
7288 13:19:12.438013 Final DQM duty delay cell = 4
7289 13:19:12.441489 [4] MAX Duty = 5187%(X100), DQS PI = 62
7290 13:19:12.444533 [4] MIN Duty = 5000%(X100), DQS PI = 14
7291 13:19:12.447813 [4] AVG Duty = 5093%(X100)
7292 13:19:12.447888
7293 13:19:12.451162 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7294 13:19:12.451267
7295 13:19:12.454361 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7296 13:19:12.457474 [DutyScan_Calibration_Flow] ====Done====
7297 13:19:12.457563
7298 13:19:12.461204 [DutyScan_Calibration_Flow] k_type=2
7299 13:19:12.477783
7300 13:19:12.477892 ==DQ 0 ==
7301 13:19:12.480951 Final DQ duty delay cell = -4
7302 13:19:12.484129 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7303 13:19:12.488077 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7304 13:19:12.491338 [-4] AVG Duty = 4938%(X100)
7305 13:19:12.491413
7306 13:19:12.491505 ==DQ 1 ==
7307 13:19:12.494675 Final DQ duty delay cell = 0
7308 13:19:12.497913 [0] MAX Duty = 5156%(X100), DQS PI = 60
7309 13:19:12.501206 [0] MIN Duty = 5000%(X100), DQS PI = 16
7310 13:19:12.504493 [0] AVG Duty = 5078%(X100)
7311 13:19:12.504593
7312 13:19:12.507799 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7313 13:19:12.507910
7314 13:19:12.511042 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7315 13:19:12.514250 [DutyScan_Calibration_Flow] ====Done====
7316 13:19:12.514328 ==
7317 13:19:12.517120 Dram Type= 6, Freq= 0, CH_1, rank 0
7318 13:19:12.520797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7319 13:19:12.520896 ==
7320 13:19:12.524005 [Duty_Offset_Calibration]
7321 13:19:12.524101 B0:1 B1:-2 CA:0
7322 13:19:12.524185
7323 13:19:12.527328 [DutyScan_Calibration_Flow] k_type=0
7324 13:19:12.538647
7325 13:19:12.538746 ==CLK 0==
7326 13:19:12.541886 Final CLK duty delay cell = 0
7327 13:19:12.545134 [0] MAX Duty = 5062%(X100), DQS PI = 20
7328 13:19:12.548404 [0] MIN Duty = 4844%(X100), DQS PI = 2
7329 13:19:12.548502 [0] AVG Duty = 4953%(X100)
7330 13:19:12.551735
7331 13:19:12.554913 CH1 CLK Duty spec in!! Max-Min= 218%
7332 13:19:12.558234 [DutyScan_Calibration_Flow] ====Done====
7333 13:19:12.558300
7334 13:19:12.561516 [DutyScan_Calibration_Flow] k_type=1
7335 13:19:12.577866
7336 13:19:12.577978 ==DQS 0 ==
7337 13:19:12.581569 Final DQS duty delay cell = 0
7338 13:19:12.584418 [0] MAX Duty = 5187%(X100), DQS PI = 24
7339 13:19:12.588042 [0] MIN Duty = 5062%(X100), DQS PI = 0
7340 13:19:12.590918 [0] AVG Duty = 5124%(X100)
7341 13:19:12.591010
7342 13:19:12.591091 ==DQS 1 ==
7343 13:19:12.594380 Final DQS duty delay cell = 0
7344 13:19:12.598218 [0] MAX Duty = 5093%(X100), DQS PI = 62
7345 13:19:12.600923 [0] MIN Duty = 4844%(X100), DQS PI = 24
7346 13:19:12.604662 [0] AVG Duty = 4968%(X100)
7347 13:19:12.604733
7348 13:19:12.608159 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7349 13:19:12.608253
7350 13:19:12.611342 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7351 13:19:12.614594 [DutyScan_Calibration_Flow] ====Done====
7352 13:19:12.614687
7353 13:19:12.617818 [DutyScan_Calibration_Flow] k_type=3
7354 13:19:12.634654
7355 13:19:12.634747 ==DQM 0 ==
7356 13:19:12.637977 Final DQM duty delay cell = 0
7357 13:19:12.641161 [0] MAX Duty = 5031%(X100), DQS PI = 26
7358 13:19:12.644897 [0] MIN Duty = 4813%(X100), DQS PI = 54
7359 13:19:12.648084 [0] AVG Duty = 4922%(X100)
7360 13:19:12.648190
7361 13:19:12.648330 ==DQM 1 ==
7362 13:19:12.651225 Final DQM duty delay cell = 0
7363 13:19:12.654521 [0] MAX Duty = 5093%(X100), DQS PI = 36
7364 13:19:12.657743 [0] MIN Duty = 4875%(X100), DQS PI = 26
7365 13:19:12.661009 [0] AVG Duty = 4984%(X100)
7366 13:19:12.661071
7367 13:19:12.664383 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7368 13:19:12.664472
7369 13:19:12.667656 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7370 13:19:12.670952 [DutyScan_Calibration_Flow] ====Done====
7371 13:19:12.671014
7372 13:19:12.674138 [DutyScan_Calibration_Flow] k_type=2
7373 13:19:12.691675
7374 13:19:12.691774 ==DQ 0 ==
7375 13:19:12.694932 Final DQ duty delay cell = 0
7376 13:19:12.698586 [0] MAX Duty = 5093%(X100), DQS PI = 22
7377 13:19:12.701607 [0] MIN Duty = 4907%(X100), DQS PI = 62
7378 13:19:12.701698 [0] AVG Duty = 5000%(X100)
7379 13:19:12.705038
7380 13:19:12.705111 ==DQ 1 ==
7381 13:19:12.708099 Final DQ duty delay cell = 0
7382 13:19:12.711757 [0] MAX Duty = 5125%(X100), DQS PI = 34
7383 13:19:12.715164 [0] MIN Duty = 4969%(X100), DQS PI = 24
7384 13:19:12.715230 [0] AVG Duty = 5047%(X100)
7385 13:19:12.718440
7386 13:19:12.721775 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7387 13:19:12.721869
7388 13:19:12.725052 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7389 13:19:12.728268 [DutyScan_Calibration_Flow] ====Done====
7390 13:19:12.731524 nWR fixed to 30
7391 13:19:12.731598 [ModeRegInit_LP4] CH0 RK0
7392 13:19:12.734672 [ModeRegInit_LP4] CH0 RK1
7393 13:19:12.738747 [ModeRegInit_LP4] CH1 RK0
7394 13:19:12.741148 [ModeRegInit_LP4] CH1 RK1
7395 13:19:12.741235 match AC timing 5
7396 13:19:12.748083 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7397 13:19:12.751128 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7398 13:19:12.754675 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7399 13:19:12.760870 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7400 13:19:12.764855 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7401 13:19:12.764948 [MiockJmeterHQA]
7402 13:19:12.765029
7403 13:19:12.768074 [DramcMiockJmeter] u1RxGatingPI = 0
7404 13:19:12.771424 0 : 4365, 4140
7405 13:19:12.771526 4 : 4252, 4026
7406 13:19:12.774748 8 : 4363, 4137
7407 13:19:12.774825 12 : 4253, 4026
7408 13:19:12.774885 16 : 4252, 4027
7409 13:19:12.778036 20 : 4363, 4137
7410 13:19:12.778181 24 : 4363, 4137
7411 13:19:12.781254 28 : 4253, 4027
7412 13:19:12.781330 32 : 4253, 4026
7413 13:19:12.784350 36 : 4250, 4027
7414 13:19:12.784467 40 : 4362, 4137
7415 13:19:12.787590 44 : 4250, 4026
7416 13:19:12.787669 48 : 4360, 4138
7417 13:19:12.787746 52 : 4250, 4026
7418 13:19:12.790866 56 : 4250, 4027
7419 13:19:12.790944 60 : 4250, 4027
7420 13:19:12.794753 64 : 4253, 4029
7421 13:19:12.794831 68 : 4250, 4027
7422 13:19:12.797784 72 : 4250, 4026
7423 13:19:12.797862 76 : 4363, 4140
7424 13:19:12.800986 80 : 4250, 4027
7425 13:19:12.801064 84 : 4253, 4029
7426 13:19:12.801141 88 : 4250, 4027
7427 13:19:12.804185 92 : 4360, 4137
7428 13:19:12.804262 96 : 4250, 4026
7429 13:19:12.807511 100 : 4360, 4138
7430 13:19:12.807589 104 : 4360, 3684
7431 13:19:12.811390 108 : 4250, 0
7432 13:19:12.811468 112 : 4250, 0
7433 13:19:12.811545 116 : 4250, 0
7434 13:19:12.814328 120 : 4252, 0
7435 13:19:12.814406 124 : 4250, 0
7436 13:19:12.817956 128 : 4250, 0
7437 13:19:12.818033 132 : 4253, 0
7438 13:19:12.818150 136 : 4361, 0
7439 13:19:12.820949 140 : 4361, 0
7440 13:19:12.821050 144 : 4363, 0
7441 13:19:12.821146 148 : 4250, 0
7442 13:19:12.824638 152 : 4361, 0
7443 13:19:12.824716 156 : 4360, 0
7444 13:19:12.827892 160 : 4250, 0
7445 13:19:12.827969 164 : 4249, 0
7446 13:19:12.828046 168 : 4249, 0
7447 13:19:12.831164 172 : 4253, 0
7448 13:19:12.831241 176 : 4250, 0
7449 13:19:12.834415 180 : 4250, 0
7450 13:19:12.834493 184 : 4252, 0
7451 13:19:12.834573 188 : 4363, 0
7452 13:19:12.837691 192 : 4361, 0
7453 13:19:12.837768 196 : 4363, 0
7454 13:19:12.841077 200 : 4250, 0
7455 13:19:12.841193 204 : 4249, 0
7456 13:19:12.841269 208 : 4250, 0
7457 13:19:12.844219 212 : 4253, 0
7458 13:19:12.844296 216 : 4249, 0
7459 13:19:12.844371 220 : 4249, 0
7460 13:19:12.847372 224 : 4253, 0
7461 13:19:12.847449 228 : 4361, 0
7462 13:19:12.850959 232 : 4250, 0
7463 13:19:12.851037 236 : 4250, 1045
7464 13:19:12.854403 240 : 4250, 4027
7465 13:19:12.854517 244 : 4249, 4027
7466 13:19:12.857415 248 : 4250, 4026
7467 13:19:12.857492 252 : 4250, 4026
7468 13:19:12.857586 256 : 4250, 4027
7469 13:19:12.860586 260 : 4360, 4138
7470 13:19:12.860663 264 : 4361, 4137
7471 13:19:12.864074 268 : 4250, 4026
7472 13:19:12.864152 272 : 4363, 4140
7473 13:19:12.867640 276 : 4250, 4027
7474 13:19:12.867714 280 : 4250, 4027
7475 13:19:12.870603 284 : 4250, 4026
7476 13:19:12.870715 288 : 4253, 4029
7477 13:19:12.873882 292 : 4250, 4027
7478 13:19:12.873971 296 : 4249, 4027
7479 13:19:12.877223 300 : 4250, 4026
7480 13:19:12.877317 304 : 4253, 4029
7481 13:19:12.881139 308 : 4250, 4027
7482 13:19:12.881228 312 : 4360, 4138
7483 13:19:12.881308 316 : 4361, 4137
7484 13:19:12.884484 320 : 4250, 4026
7485 13:19:12.884555 324 : 4363, 4140
7486 13:19:12.887672 328 : 4250, 4027
7487 13:19:12.887737 332 : 4250, 4027
7488 13:19:12.890933 336 : 4250, 4026
7489 13:19:12.891034 340 : 4253, 4029
7490 13:19:12.894176 344 : 4250, 4027
7491 13:19:12.894285 348 : 4249, 4027
7492 13:19:12.897586 352 : 4250, 4015
7493 13:19:12.897703 356 : 4253, 2741
7494 13:19:12.900938 360 : 4250, 0
7495 13:19:12.901040
7496 13:19:12.901126 MIOCK jitter meter ch=0
7497 13:19:12.901205
7498 13:19:12.904208 1T = (360-108) = 252 dly cells
7499 13:19:12.910640 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7500 13:19:12.910718 ==
7501 13:19:12.914024 Dram Type= 6, Freq= 0, CH_0, rank 0
7502 13:19:12.917630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7503 13:19:12.917747 ==
7504 13:19:12.923894 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7505 13:19:12.927518 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7506 13:19:12.930458 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7507 13:19:12.937164 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7508 13:19:12.946825 [CA 0] Center 44 (14~75) winsize 62
7509 13:19:12.950295 [CA 1] Center 43 (13~74) winsize 62
7510 13:19:12.953507 [CA 2] Center 40 (11~69) winsize 59
7511 13:19:12.956725 [CA 3] Center 39 (10~68) winsize 59
7512 13:19:12.959944 [CA 4] Center 37 (8~67) winsize 60
7513 13:19:12.963596 [CA 5] Center 37 (7~67) winsize 61
7514 13:19:12.963673
7515 13:19:12.966502 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7516 13:19:12.966579
7517 13:19:12.973478 [CATrainingPosCal] consider 1 rank data
7518 13:19:12.973555 u2DelayCellTimex100 = 258/100 ps
7519 13:19:12.980014 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7520 13:19:12.983510 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7521 13:19:12.986599 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7522 13:19:12.989812 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7523 13:19:12.993247 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7524 13:19:12.996453 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7525 13:19:12.996542
7526 13:19:13.000155 CA PerBit enable=1, Macro0, CA PI delay=37
7527 13:19:13.000224
7528 13:19:13.003260 [CBTSetCACLKResult] CA Dly = 37
7529 13:19:13.006603 CS Dly: 11 (0~42)
7530 13:19:13.009871 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7531 13:19:13.013137 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7532 13:19:13.013210 ==
7533 13:19:13.016295 Dram Type= 6, Freq= 0, CH_0, rank 1
7534 13:19:13.023119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7535 13:19:13.023264 ==
7536 13:19:13.026553 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7537 13:19:13.032952 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7538 13:19:13.036118 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7539 13:19:13.042963 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7540 13:19:13.050810 [CA 0] Center 44 (13~75) winsize 63
7541 13:19:13.054143 [CA 1] Center 43 (13~74) winsize 62
7542 13:19:13.057625 [CA 2] Center 39 (10~69) winsize 60
7543 13:19:13.061045 [CA 3] Center 39 (10~68) winsize 59
7544 13:19:13.063749 [CA 4] Center 37 (8~67) winsize 60
7545 13:19:13.067133 [CA 5] Center 37 (8~66) winsize 59
7546 13:19:13.067234
7547 13:19:13.070547 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7548 13:19:13.070639
7549 13:19:13.076807 [CATrainingPosCal] consider 2 rank data
7550 13:19:13.076902 u2DelayCellTimex100 = 258/100 ps
7551 13:19:13.083947 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7552 13:19:13.087032 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7553 13:19:13.089974 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7554 13:19:13.093497 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7555 13:19:13.096971 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7556 13:19:13.100104 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7557 13:19:13.100199
7558 13:19:13.103321 CA PerBit enable=1, Macro0, CA PI delay=37
7559 13:19:13.103411
7560 13:19:13.107082 [CBTSetCACLKResult] CA Dly = 37
7561 13:19:13.110212 CS Dly: 11 (0~42)
7562 13:19:13.113470 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7563 13:19:13.116852 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7564 13:19:13.116945
7565 13:19:13.120006 ----->DramcWriteLeveling(PI) begin...
7566 13:19:13.123070 ==
7567 13:19:13.126800 Dram Type= 6, Freq= 0, CH_0, rank 0
7568 13:19:13.129997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 13:19:13.130097 ==
7570 13:19:13.133333 Write leveling (Byte 0): 37 => 37
7571 13:19:13.136557 Write leveling (Byte 1): 28 => 28
7572 13:19:13.139804 DramcWriteLeveling(PI) end<-----
7573 13:19:13.139898
7574 13:19:13.139981 ==
7575 13:19:13.143047 Dram Type= 6, Freq= 0, CH_0, rank 0
7576 13:19:13.146108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7577 13:19:13.146213 ==
7578 13:19:13.149946 [Gating] SW mode calibration
7579 13:19:13.156034 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7580 13:19:13.162606 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7581 13:19:13.165887 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 13:19:13.169185 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 13:19:13.175760 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 13:19:13.179171 1 4 12 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7585 13:19:13.182334 1 4 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7586 13:19:13.189109 1 4 20 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7587 13:19:13.192266 1 4 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7588 13:19:13.195639 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7589 13:19:13.202504 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 13:19:13.205613 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 13:19:13.209056 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 13:19:13.215597 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 13:19:13.219090 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
7594 13:19:13.222222 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 0) (1 0)
7595 13:19:13.228741 1 5 24 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
7596 13:19:13.232343 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 13:19:13.235446 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 13:19:13.242145 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 13:19:13.245404 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 13:19:13.248500 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 13:19:13.255025 1 6 16 | B1->B0 | 2323 3837 | 0 1 | (0 0) (0 0)
7602 13:19:13.258709 1 6 20 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
7603 13:19:13.261952 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7604 13:19:13.265164 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 13:19:13.271724 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 13:19:13.275156 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 13:19:13.278453 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 13:19:13.285730 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 13:19:13.288196 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7610 13:19:13.291984 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7611 13:19:13.298746 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7612 13:19:13.301999 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 13:19:13.305462 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 13:19:13.312033 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 13:19:13.315325 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 13:19:13.318328 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 13:19:13.324619 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 13:19:13.328342 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 13:19:13.331424 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 13:19:13.338201 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 13:19:13.341331 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 13:19:13.344442 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 13:19:13.351710 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 13:19:13.354907 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 13:19:13.358067 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7626 13:19:13.364406 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7627 13:19:13.367596 Total UI for P1: 0, mck2ui 16
7628 13:19:13.371349 best dqsien dly found for B0: ( 1, 9, 16)
7629 13:19:13.374598 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7630 13:19:13.377829 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 13:19:13.381071 Total UI for P1: 0, mck2ui 16
7632 13:19:13.384246 best dqsien dly found for B1: ( 1, 9, 22)
7633 13:19:13.387566 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7634 13:19:13.390936 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7635 13:19:13.391029
7636 13:19:13.397427 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7637 13:19:13.401177 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7638 13:19:13.404146 [Gating] SW calibration Done
7639 13:19:13.404243 ==
7640 13:19:13.407744 Dram Type= 6, Freq= 0, CH_0, rank 0
7641 13:19:13.410955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7642 13:19:13.411026 ==
7643 13:19:13.411083 RX Vref Scan: 0
7644 13:19:13.411146
7645 13:19:13.414171 RX Vref 0 -> 0, step: 1
7646 13:19:13.414235
7647 13:19:13.418042 RX Delay 0 -> 252, step: 8
7648 13:19:13.421113 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7649 13:19:13.424293 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7650 13:19:13.427640 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7651 13:19:13.434083 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7652 13:19:13.437713 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7653 13:19:13.440713 iDelay=200, Bit 5, Center 115 (64 ~ 167) 104
7654 13:19:13.444150 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7655 13:19:13.447382 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7656 13:19:13.454153 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7657 13:19:13.457648 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7658 13:19:13.460771 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7659 13:19:13.464019 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7660 13:19:13.467202 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7661 13:19:13.474373 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
7662 13:19:13.477653 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7663 13:19:13.481079 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7664 13:19:13.481153 ==
7665 13:19:13.484319 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 13:19:13.487614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 13:19:13.491001 ==
7668 13:19:13.491070 DQS Delay:
7669 13:19:13.491127 DQS0 = 0, DQS1 = 0
7670 13:19:13.494196 DQM Delay:
7671 13:19:13.494285 DQM0 = 129, DQM1 = 123
7672 13:19:13.497383 DQ Delay:
7673 13:19:13.500632 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7674 13:19:13.504052 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =143
7675 13:19:13.507217 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7676 13:19:13.510271 DQ12 =127, DQ13 =127, DQ14 =135, DQ15 =131
7677 13:19:13.510337
7678 13:19:13.510392
7679 13:19:13.510460 ==
7680 13:19:13.513950 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 13:19:13.516987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 13:19:13.520607 ==
7683 13:19:13.520674
7684 13:19:13.520727
7685 13:19:13.520787 TX Vref Scan disable
7686 13:19:13.523741 == TX Byte 0 ==
7687 13:19:13.526810 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7688 13:19:13.530594 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7689 13:19:13.533757 == TX Byte 1 ==
7690 13:19:13.537046 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7691 13:19:13.540298 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7692 13:19:13.543627 ==
7693 13:19:13.543712 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 13:19:13.550050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 13:19:13.550167 ==
7696 13:19:13.563037
7697 13:19:13.566676 TX Vref early break, caculate TX vref
7698 13:19:13.569478 TX Vref=16, minBit 8, minWin=21, winSum=362
7699 13:19:13.572921 TX Vref=18, minBit 8, minWin=22, winSum=375
7700 13:19:13.576529 TX Vref=20, minBit 8, minWin=23, winSum=386
7701 13:19:13.579756 TX Vref=22, minBit 8, minWin=22, winSum=390
7702 13:19:13.582961 TX Vref=24, minBit 8, minWin=23, winSum=401
7703 13:19:13.589577 TX Vref=26, minBit 8, minWin=24, winSum=408
7704 13:19:13.592923 TX Vref=28, minBit 8, minWin=24, winSum=410
7705 13:19:13.596121 TX Vref=30, minBit 8, minWin=24, winSum=400
7706 13:19:13.599533 TX Vref=32, minBit 8, minWin=22, winSum=395
7707 13:19:13.602812 TX Vref=34, minBit 8, minWin=21, winSum=382
7708 13:19:13.609453 [TxChooseVref] Worse bit 8, Min win 24, Win sum 410, Final Vref 28
7709 13:19:13.609535
7710 13:19:13.612679 Final TX Range 0 Vref 28
7711 13:19:13.612752
7712 13:19:13.612808 ==
7713 13:19:13.616478 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 13:19:13.619687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 13:19:13.619755 ==
7716 13:19:13.619820
7717 13:19:13.619887
7718 13:19:13.622789 TX Vref Scan disable
7719 13:19:13.629565 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7720 13:19:13.629640 == TX Byte 0 ==
7721 13:19:13.632699 u2DelayCellOfst[0]=11 cells (3 PI)
7722 13:19:13.636146 u2DelayCellOfst[1]=15 cells (4 PI)
7723 13:19:13.639529 u2DelayCellOfst[2]=11 cells (3 PI)
7724 13:19:13.642617 u2DelayCellOfst[3]=11 cells (3 PI)
7725 13:19:13.645920 u2DelayCellOfst[4]=3 cells (1 PI)
7726 13:19:13.649233 u2DelayCellOfst[5]=0 cells (0 PI)
7727 13:19:13.652449 u2DelayCellOfst[6]=15 cells (4 PI)
7728 13:19:13.655766 u2DelayCellOfst[7]=15 cells (4 PI)
7729 13:19:13.659368 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7730 13:19:13.662551 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7731 13:19:13.665693 == TX Byte 1 ==
7732 13:19:13.665780 u2DelayCellOfst[8]=0 cells (0 PI)
7733 13:19:13.669383 u2DelayCellOfst[9]=3 cells (1 PI)
7734 13:19:13.672600 u2DelayCellOfst[10]=7 cells (2 PI)
7735 13:19:13.675891 u2DelayCellOfst[11]=3 cells (1 PI)
7736 13:19:13.679193 u2DelayCellOfst[12]=11 cells (3 PI)
7737 13:19:13.682135 u2DelayCellOfst[13]=11 cells (3 PI)
7738 13:19:13.685716 u2DelayCellOfst[14]=15 cells (4 PI)
7739 13:19:13.689127 u2DelayCellOfst[15]=11 cells (3 PI)
7740 13:19:13.692112 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7741 13:19:13.698577 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7742 13:19:13.698705 DramC Write-DBI on
7743 13:19:13.698797 ==
7744 13:19:13.701916 Dram Type= 6, Freq= 0, CH_0, rank 0
7745 13:19:13.708558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7746 13:19:13.708636 ==
7747 13:19:13.708714
7748 13:19:13.708769
7749 13:19:13.708821 TX Vref Scan disable
7750 13:19:13.712534 == TX Byte 0 ==
7751 13:19:13.715868 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
7752 13:19:13.719752 == TX Byte 1 ==
7753 13:19:13.722475 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7754 13:19:13.725869 DramC Write-DBI off
7755 13:19:13.725974
7756 13:19:13.726110 [DATLAT]
7757 13:19:13.726203 Freq=1600, CH0 RK0
7758 13:19:13.726269
7759 13:19:13.729008 DATLAT Default: 0xf
7760 13:19:13.729103 0, 0xFFFF, sum = 0
7761 13:19:13.732713 1, 0xFFFF, sum = 0
7762 13:19:13.735951 2, 0xFFFF, sum = 0
7763 13:19:13.736036 3, 0xFFFF, sum = 0
7764 13:19:13.739203 4, 0xFFFF, sum = 0
7765 13:19:13.739273 5, 0xFFFF, sum = 0
7766 13:19:13.742346 6, 0xFFFF, sum = 0
7767 13:19:13.742415 7, 0xFFFF, sum = 0
7768 13:19:13.746090 8, 0xFFFF, sum = 0
7769 13:19:13.746202 9, 0xFFFF, sum = 0
7770 13:19:13.748981 10, 0xFFFF, sum = 0
7771 13:19:13.749061 11, 0xFFFF, sum = 0
7772 13:19:13.752614 12, 0xFFFF, sum = 0
7773 13:19:13.752686 13, 0xEFFF, sum = 0
7774 13:19:13.755977 14, 0x0, sum = 1
7775 13:19:13.756047 15, 0x0, sum = 2
7776 13:19:13.759135 16, 0x0, sum = 3
7777 13:19:13.759226 17, 0x0, sum = 4
7778 13:19:13.762877 best_step = 15
7779 13:19:13.762942
7780 13:19:13.762997 ==
7781 13:19:13.765493 Dram Type= 6, Freq= 0, CH_0, rank 0
7782 13:19:13.769394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7783 13:19:13.769467 ==
7784 13:19:13.772417 RX Vref Scan: 1
7785 13:19:13.772492
7786 13:19:13.772555 Set Vref Range= 24 -> 127
7787 13:19:13.772618
7788 13:19:13.775456 RX Vref 24 -> 127, step: 1
7789 13:19:13.775526
7790 13:19:13.779138 RX Delay 11 -> 252, step: 4
7791 13:19:13.779223
7792 13:19:13.782379 Set Vref, RX VrefLevel [Byte0]: 24
7793 13:19:13.785558 [Byte1]: 24
7794 13:19:13.785627
7795 13:19:13.788718 Set Vref, RX VrefLevel [Byte0]: 25
7796 13:19:13.792615 [Byte1]: 25
7797 13:19:13.792698
7798 13:19:13.795771 Set Vref, RX VrefLevel [Byte0]: 26
7799 13:19:13.798645 [Byte1]: 26
7800 13:19:13.802982
7801 13:19:13.803053 Set Vref, RX VrefLevel [Byte0]: 27
7802 13:19:13.806215 [Byte1]: 27
7803 13:19:13.810984
7804 13:19:13.811082 Set Vref, RX VrefLevel [Byte0]: 28
7805 13:19:13.813645 [Byte1]: 28
7806 13:19:13.818354
7807 13:19:13.818435 Set Vref, RX VrefLevel [Byte0]: 29
7808 13:19:13.821670 [Byte1]: 29
7809 13:19:13.825706
7810 13:19:13.825824 Set Vref, RX VrefLevel [Byte0]: 30
7811 13:19:13.829173 [Byte1]: 30
7812 13:19:13.833166
7813 13:19:13.833251 Set Vref, RX VrefLevel [Byte0]: 31
7814 13:19:13.837194 [Byte1]: 31
7815 13:19:13.841139
7816 13:19:13.841238 Set Vref, RX VrefLevel [Byte0]: 32
7817 13:19:13.844650 [Byte1]: 32
7818 13:19:13.848965
7819 13:19:13.849040 Set Vref, RX VrefLevel [Byte0]: 33
7820 13:19:13.852256 [Byte1]: 33
7821 13:19:13.856074
7822 13:19:13.856148 Set Vref, RX VrefLevel [Byte0]: 34
7823 13:19:13.859687 [Byte1]: 34
7824 13:19:13.864077
7825 13:19:13.864152 Set Vref, RX VrefLevel [Byte0]: 35
7826 13:19:13.867037 [Byte1]: 35
7827 13:19:13.871525
7828 13:19:13.871634 Set Vref, RX VrefLevel [Byte0]: 36
7829 13:19:13.874868 [Byte1]: 36
7830 13:19:13.879398
7831 13:19:13.879468 Set Vref, RX VrefLevel [Byte0]: 37
7832 13:19:13.882569 [Byte1]: 37
7833 13:19:13.886871
7834 13:19:13.886943 Set Vref, RX VrefLevel [Byte0]: 38
7835 13:19:13.890054 [Byte1]: 38
7836 13:19:13.894112
7837 13:19:13.894225 Set Vref, RX VrefLevel [Byte0]: 39
7838 13:19:13.897455 [Byte1]: 39
7839 13:19:13.902018
7840 13:19:13.902098 Set Vref, RX VrefLevel [Byte0]: 40
7841 13:19:13.905149 [Byte1]: 40
7842 13:19:13.909462
7843 13:19:13.909542 Set Vref, RX VrefLevel [Byte0]: 41
7844 13:19:13.912954 [Byte1]: 41
7845 13:19:13.917046
7846 13:19:13.917135 Set Vref, RX VrefLevel [Byte0]: 42
7847 13:19:13.920957 [Byte1]: 42
7848 13:19:13.924926
7849 13:19:13.925012 Set Vref, RX VrefLevel [Byte0]: 43
7850 13:19:13.928473 [Byte1]: 43
7851 13:19:13.932555
7852 13:19:13.932636 Set Vref, RX VrefLevel [Byte0]: 44
7853 13:19:13.936064 [Byte1]: 44
7854 13:19:13.940147
7855 13:19:13.940234 Set Vref, RX VrefLevel [Byte0]: 45
7856 13:19:13.943231 [Byte1]: 45
7857 13:19:13.947529
7858 13:19:13.947603 Set Vref, RX VrefLevel [Byte0]: 46
7859 13:19:13.950846 [Byte1]: 46
7860 13:19:13.955687
7861 13:19:13.955772 Set Vref, RX VrefLevel [Byte0]: 47
7862 13:19:13.958403 [Byte1]: 47
7863 13:19:13.963002
7864 13:19:13.963093 Set Vref, RX VrefLevel [Byte0]: 48
7865 13:19:13.966060 [Byte1]: 48
7866 13:19:13.970879
7867 13:19:13.970953 Set Vref, RX VrefLevel [Byte0]: 49
7868 13:19:13.973971 [Byte1]: 49
7869 13:19:13.978319
7870 13:19:13.978402 Set Vref, RX VrefLevel [Byte0]: 50
7871 13:19:13.981459 [Byte1]: 50
7872 13:19:13.985801
7873 13:19:13.985871 Set Vref, RX VrefLevel [Byte0]: 51
7874 13:19:13.989023 [Byte1]: 51
7875 13:19:13.993391
7876 13:19:13.993473 Set Vref, RX VrefLevel [Byte0]: 52
7877 13:19:13.996879 [Byte1]: 52
7878 13:19:14.000964
7879 13:19:14.001071 Set Vref, RX VrefLevel [Byte0]: 53
7880 13:19:14.004418 [Byte1]: 53
7881 13:19:14.008509
7882 13:19:14.008588 Set Vref, RX VrefLevel [Byte0]: 54
7883 13:19:14.011888 [Byte1]: 54
7884 13:19:14.016198
7885 13:19:14.016269 Set Vref, RX VrefLevel [Byte0]: 55
7886 13:19:14.019339 [Byte1]: 55
7887 13:19:14.023642
7888 13:19:14.023711 Set Vref, RX VrefLevel [Byte0]: 56
7889 13:19:14.026862 [Byte1]: 56
7890 13:19:14.031456
7891 13:19:14.031526 Set Vref, RX VrefLevel [Byte0]: 57
7892 13:19:14.034892 [Byte1]: 57
7893 13:19:14.038968
7894 13:19:14.039039 Set Vref, RX VrefLevel [Byte0]: 58
7895 13:19:14.042166 [Byte1]: 58
7896 13:19:14.046731
7897 13:19:14.046821 Set Vref, RX VrefLevel [Byte0]: 59
7898 13:19:14.049882 [Byte1]: 59
7899 13:19:14.054422
7900 13:19:14.054501 Set Vref, RX VrefLevel [Byte0]: 60
7901 13:19:14.057773 [Byte1]: 60
7902 13:19:14.061669
7903 13:19:14.061751 Set Vref, RX VrefLevel [Byte0]: 61
7904 13:19:14.064919 [Byte1]: 61
7905 13:19:14.069378
7906 13:19:14.069455 Set Vref, RX VrefLevel [Byte0]: 62
7907 13:19:14.073099 [Byte1]: 62
7908 13:19:14.077045
7909 13:19:14.077133 Set Vref, RX VrefLevel [Byte0]: 63
7910 13:19:14.080281 [Byte1]: 63
7911 13:19:14.084759
7912 13:19:14.084857 Set Vref, RX VrefLevel [Byte0]: 64
7913 13:19:14.088067 [Byte1]: 64
7914 13:19:14.092504
7915 13:19:14.092575 Set Vref, RX VrefLevel [Byte0]: 65
7916 13:19:14.095540 [Byte1]: 65
7917 13:19:14.100113
7918 13:19:14.100200 Set Vref, RX VrefLevel [Byte0]: 66
7919 13:19:14.103318 [Byte1]: 66
7920 13:19:14.107512
7921 13:19:14.107594 Set Vref, RX VrefLevel [Byte0]: 67
7922 13:19:14.110855 [Byte1]: 67
7923 13:19:14.115028
7924 13:19:14.115124 Set Vref, RX VrefLevel [Byte0]: 68
7925 13:19:14.118276 [Byte1]: 68
7926 13:19:14.122992
7927 13:19:14.123077 Set Vref, RX VrefLevel [Byte0]: 69
7928 13:19:14.126473 [Byte1]: 69
7929 13:19:14.130397
7930 13:19:14.130476 Set Vref, RX VrefLevel [Byte0]: 70
7931 13:19:14.133653 [Byte1]: 70
7932 13:19:14.138256
7933 13:19:14.138331 Set Vref, RX VrefLevel [Byte0]: 71
7934 13:19:14.141362 [Byte1]: 71
7935 13:19:14.145467
7936 13:19:14.145537 Set Vref, RX VrefLevel [Byte0]: 72
7937 13:19:14.148686 [Byte1]: 72
7938 13:19:14.153393
7939 13:19:14.153465 Set Vref, RX VrefLevel [Byte0]: 73
7940 13:19:14.156679 [Byte1]: 73
7941 13:19:14.160672
7942 13:19:14.160750 Set Vref, RX VrefLevel [Byte0]: 74
7943 13:19:14.164082 [Byte1]: 74
7944 13:19:14.168273
7945 13:19:14.168356 Set Vref, RX VrefLevel [Byte0]: 75
7946 13:19:14.171740 [Byte1]: 75
7947 13:19:14.176124
7948 13:19:14.176199 Set Vref, RX VrefLevel [Byte0]: 76
7949 13:19:14.179483 [Byte1]: 76
7950 13:19:14.183475
7951 13:19:14.183560 Set Vref, RX VrefLevel [Byte0]: 77
7952 13:19:14.186776 [Byte1]: 77
7953 13:19:14.191279
7954 13:19:14.191357 Set Vref, RX VrefLevel [Byte0]: 78
7955 13:19:14.194671 [Byte1]: 78
7956 13:19:14.198755
7957 13:19:14.198833 Final RX Vref Byte 0 = 62 to rank0
7958 13:19:14.202148 Final RX Vref Byte 1 = 58 to rank0
7959 13:19:14.205323 Final RX Vref Byte 0 = 62 to rank1
7960 13:19:14.208770 Final RX Vref Byte 1 = 58 to rank1==
7961 13:19:14.212002 Dram Type= 6, Freq= 0, CH_0, rank 0
7962 13:19:14.218828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7963 13:19:14.218938 ==
7964 13:19:14.219027 DQS Delay:
7965 13:19:14.222007 DQS0 = 0, DQS1 = 0
7966 13:19:14.222112 DQM Delay:
7967 13:19:14.222200 DQM0 = 126, DQM1 = 120
7968 13:19:14.225265 DQ Delay:
7969 13:19:14.228463 DQ0 =124, DQ1 =128, DQ2 =126, DQ3 =122
7970 13:19:14.231827 DQ4 =128, DQ5 =112, DQ6 =132, DQ7 =138
7971 13:19:14.235296 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
7972 13:19:14.238664 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7973 13:19:14.238742
7974 13:19:14.238802
7975 13:19:14.238857
7976 13:19:14.242149 [DramC_TX_OE_Calibration] TA2
7977 13:19:14.244764 Original DQ_B0 (3 6) =30, OEN = 27
7978 13:19:14.248666 Original DQ_B1 (3 6) =30, OEN = 27
7979 13:19:14.251708 24, 0x0, End_B0=24 End_B1=24
7980 13:19:14.251786 25, 0x0, End_B0=25 End_B1=25
7981 13:19:14.255305 26, 0x0, End_B0=26 End_B1=26
7982 13:19:14.258213 27, 0x0, End_B0=27 End_B1=27
7983 13:19:14.261761 28, 0x0, End_B0=28 End_B1=28
7984 13:19:14.264881 29, 0x0, End_B0=29 End_B1=29
7985 13:19:14.264959 30, 0x0, End_B0=30 End_B1=30
7986 13:19:14.268050 31, 0x4141, End_B0=30 End_B1=30
7987 13:19:14.271351 Byte0 end_step=30 best_step=27
7988 13:19:14.274651 Byte1 end_step=30 best_step=27
7989 13:19:14.277998 Byte0 TX OE(2T, 0.5T) = (3, 3)
7990 13:19:14.281248 Byte1 TX OE(2T, 0.5T) = (3, 3)
7991 13:19:14.281325
7992 13:19:14.281385
7993 13:19:14.288095 [DQSOSCAuto] RK0, (LSB)MR18= 0x1615, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
7994 13:19:14.291399 CH0 RK0: MR19=303, MR18=1615
7995 13:19:14.298122 CH0_RK0: MR19=0x303, MR18=0x1615, DQSOSC=398, MR23=63, INC=23, DEC=15
7996 13:19:14.298229
7997 13:19:14.301479 ----->DramcWriteLeveling(PI) begin...
7998 13:19:14.301558 ==
7999 13:19:14.304622 Dram Type= 6, Freq= 0, CH_0, rank 1
8000 13:19:14.307953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8001 13:19:14.308032 ==
8002 13:19:14.311180 Write leveling (Byte 0): 33 => 33
8003 13:19:14.314454 Write leveling (Byte 1): 28 => 28
8004 13:19:14.317735 DramcWriteLeveling(PI) end<-----
8005 13:19:14.317812
8006 13:19:14.317872 ==
8007 13:19:14.321006 Dram Type= 6, Freq= 0, CH_0, rank 1
8008 13:19:14.324199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8009 13:19:14.327898 ==
8010 13:19:14.327976 [Gating] SW mode calibration
8011 13:19:14.334111 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8012 13:19:14.340777 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8013 13:19:14.344107 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 13:19:14.350616 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 13:19:14.353988 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 13:19:14.357303 1 4 12 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
8017 13:19:14.364226 1 4 16 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
8018 13:19:14.367607 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8019 13:19:14.370658 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 13:19:14.376920 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 13:19:14.380316 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8022 13:19:14.383628 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8023 13:19:14.390097 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 0)
8024 13:19:14.393889 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 1)
8025 13:19:14.396901 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8026 13:19:14.404083 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
8027 13:19:14.407202 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 13:19:14.410742 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 13:19:14.416929 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 13:19:14.420141 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 13:19:14.423429 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8032 13:19:14.429968 1 6 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8033 13:19:14.433705 1 6 16 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
8034 13:19:14.436499 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 13:19:14.442957 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 13:19:14.446723 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 13:19:14.449989 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 13:19:14.456542 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 13:19:14.459945 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8040 13:19:14.463222 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8041 13:19:14.469704 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8042 13:19:14.473247 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8043 13:19:14.476556 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 13:19:14.483215 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 13:19:14.486207 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 13:19:14.489415 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 13:19:14.495980 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 13:19:14.499668 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 13:19:14.502618 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 13:19:14.509477 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 13:19:14.512612 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 13:19:14.515997 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 13:19:14.522546 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 13:19:14.525652 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 13:19:14.529050 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 13:19:14.535551 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8057 13:19:14.538866 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8058 13:19:14.542563 Total UI for P1: 0, mck2ui 16
8059 13:19:14.545709 best dqsien dly found for B0: ( 1, 9, 12)
8060 13:19:14.548899 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8061 13:19:14.555608 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 13:19:14.555686 Total UI for P1: 0, mck2ui 16
8063 13:19:14.558886 best dqsien dly found for B1: ( 1, 9, 18)
8064 13:19:14.565704 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8065 13:19:14.568440 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8066 13:19:14.568517
8067 13:19:14.572010 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8068 13:19:14.575336 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8069 13:19:14.578506 [Gating] SW calibration Done
8070 13:19:14.578583 ==
8071 13:19:14.582253 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 13:19:14.585353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 13:19:14.585432 ==
8074 13:19:14.588742 RX Vref Scan: 0
8075 13:19:14.588806
8076 13:19:14.588859 RX Vref 0 -> 0, step: 1
8077 13:19:14.588910
8078 13:19:14.591909 RX Delay 0 -> 252, step: 8
8079 13:19:14.595445 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8080 13:19:14.601912 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8081 13:19:14.605212 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8082 13:19:14.608375 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8083 13:19:14.611505 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8084 13:19:14.614681 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8085 13:19:14.621493 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8086 13:19:14.624745 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8087 13:19:14.628093 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8088 13:19:14.631316 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8089 13:19:14.634524 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
8090 13:19:14.641032 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8091 13:19:14.644362 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8092 13:19:14.647643 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8093 13:19:14.650898 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8094 13:19:14.658125 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8095 13:19:14.658210 ==
8096 13:19:14.661273 Dram Type= 6, Freq= 0, CH_0, rank 1
8097 13:19:14.664268 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8098 13:19:14.664337 ==
8099 13:19:14.664394 DQS Delay:
8100 13:19:14.668006 DQS0 = 0, DQS1 = 0
8101 13:19:14.668114 DQM Delay:
8102 13:19:14.671424 DQM0 = 128, DQM1 = 120
8103 13:19:14.671524 DQ Delay:
8104 13:19:14.674182 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8105 13:19:14.677505 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8106 13:19:14.680771 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
8107 13:19:14.684124 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8108 13:19:14.684220
8109 13:19:14.687255
8110 13:19:14.687352 ==
8111 13:19:14.690545 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 13:19:14.693777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 13:19:14.693849 ==
8114 13:19:14.693913
8115 13:19:14.693998
8116 13:19:14.697157 TX Vref Scan disable
8117 13:19:14.697229 == TX Byte 0 ==
8118 13:19:14.704209 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8119 13:19:14.707310 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8120 13:19:14.707413 == TX Byte 1 ==
8121 13:19:14.714047 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8122 13:19:14.717058 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8123 13:19:14.717158 ==
8124 13:19:14.720756 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 13:19:14.724365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 13:19:14.724465 ==
8127 13:19:14.737474
8128 13:19:14.740914 TX Vref early break, caculate TX vref
8129 13:19:14.744359 TX Vref=16, minBit 1, minWin=22, winSum=363
8130 13:19:14.747684 TX Vref=18, minBit 8, minWin=22, winSum=377
8131 13:19:14.751142 TX Vref=20, minBit 0, minWin=23, winSum=381
8132 13:19:14.753852 TX Vref=22, minBit 11, minWin=23, winSum=390
8133 13:19:14.757708 TX Vref=24, minBit 8, minWin=24, winSum=398
8134 13:19:14.764365 TX Vref=26, minBit 8, minWin=24, winSum=405
8135 13:19:14.767548 TX Vref=28, minBit 8, minWin=24, winSum=409
8136 13:19:14.770632 TX Vref=30, minBit 9, minWin=23, winSum=405
8137 13:19:14.774272 TX Vref=32, minBit 8, minWin=22, winSum=396
8138 13:19:14.777545 TX Vref=34, minBit 8, minWin=23, winSum=387
8139 13:19:14.784253 [TxChooseVref] Worse bit 8, Min win 24, Win sum 409, Final Vref 28
8140 13:19:14.784351
8141 13:19:14.787759 Final TX Range 0 Vref 28
8142 13:19:14.787851
8143 13:19:14.787934 ==
8144 13:19:14.791003 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 13:19:14.794142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 13:19:14.794209 ==
8147 13:19:14.794264
8148 13:19:14.794347
8149 13:19:14.797791 TX Vref Scan disable
8150 13:19:14.804369 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8151 13:19:14.804447 == TX Byte 0 ==
8152 13:19:14.807591 u2DelayCellOfst[0]=11 cells (3 PI)
8153 13:19:14.810846 u2DelayCellOfst[1]=18 cells (5 PI)
8154 13:19:14.814188 u2DelayCellOfst[2]=7 cells (2 PI)
8155 13:19:14.817309 u2DelayCellOfst[3]=11 cells (3 PI)
8156 13:19:14.821085 u2DelayCellOfst[4]=7 cells (2 PI)
8157 13:19:14.823948 u2DelayCellOfst[5]=0 cells (0 PI)
8158 13:19:14.827393 u2DelayCellOfst[6]=18 cells (5 PI)
8159 13:19:14.827475 u2DelayCellOfst[7]=18 cells (5 PI)
8160 13:19:14.834419 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8161 13:19:14.837374 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8162 13:19:14.837467 == TX Byte 1 ==
8163 13:19:14.840416 u2DelayCellOfst[8]=0 cells (0 PI)
8164 13:19:14.843921 u2DelayCellOfst[9]=0 cells (0 PI)
8165 13:19:14.847680 u2DelayCellOfst[10]=11 cells (3 PI)
8166 13:19:14.850974 u2DelayCellOfst[11]=7 cells (2 PI)
8167 13:19:14.854265 u2DelayCellOfst[12]=15 cells (4 PI)
8168 13:19:14.857527 u2DelayCellOfst[13]=15 cells (4 PI)
8169 13:19:14.860662 u2DelayCellOfst[14]=15 cells (4 PI)
8170 13:19:14.863816 u2DelayCellOfst[15]=11 cells (3 PI)
8171 13:19:14.867054 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8172 13:19:14.873663 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8173 13:19:14.873742 DramC Write-DBI on
8174 13:19:14.873802 ==
8175 13:19:14.877355 Dram Type= 6, Freq= 0, CH_0, rank 1
8176 13:19:14.880442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8177 13:19:14.883535 ==
8178 13:19:14.883614
8179 13:19:14.883673
8180 13:19:14.883726 TX Vref Scan disable
8181 13:19:14.887369 == TX Byte 0 ==
8182 13:19:14.890740 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8183 13:19:14.893946 == TX Byte 1 ==
8184 13:19:14.897298 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8185 13:19:14.900652 DramC Write-DBI off
8186 13:19:14.900732
8187 13:19:14.900793 [DATLAT]
8188 13:19:14.900850 Freq=1600, CH0 RK1
8189 13:19:14.900904
8190 13:19:14.903605 DATLAT Default: 0xf
8191 13:19:14.903706 0, 0xFFFF, sum = 0
8192 13:19:14.907286 1, 0xFFFF, sum = 0
8193 13:19:14.910624 2, 0xFFFF, sum = 0
8194 13:19:14.910703 3, 0xFFFF, sum = 0
8195 13:19:14.913994 4, 0xFFFF, sum = 0
8196 13:19:14.914071 5, 0xFFFF, sum = 0
8197 13:19:14.917354 6, 0xFFFF, sum = 0
8198 13:19:14.917432 7, 0xFFFF, sum = 0
8199 13:19:14.920529 8, 0xFFFF, sum = 0
8200 13:19:14.920607 9, 0xFFFF, sum = 0
8201 13:19:14.923851 10, 0xFFFF, sum = 0
8202 13:19:14.923929 11, 0xFFFF, sum = 0
8203 13:19:14.927260 12, 0xFFFF, sum = 0
8204 13:19:14.927338 13, 0xCFFF, sum = 0
8205 13:19:14.930006 14, 0x0, sum = 1
8206 13:19:14.930084 15, 0x0, sum = 2
8207 13:19:14.933801 16, 0x0, sum = 3
8208 13:19:14.933878 17, 0x0, sum = 4
8209 13:19:14.936895 best_step = 15
8210 13:19:14.936971
8211 13:19:14.937029 ==
8212 13:19:14.940390 Dram Type= 6, Freq= 0, CH_0, rank 1
8213 13:19:14.943453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8214 13:19:14.943530 ==
8215 13:19:14.946712 RX Vref Scan: 0
8216 13:19:14.946813
8217 13:19:14.946905 RX Vref 0 -> 0, step: 1
8218 13:19:14.946989
8219 13:19:14.949902 RX Delay 3 -> 252, step: 4
8220 13:19:14.956681 iDelay=191, Bit 0, Center 122 (67 ~ 178) 112
8221 13:19:14.959528 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8222 13:19:14.962968 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8223 13:19:14.966466 iDelay=191, Bit 3, Center 120 (63 ~ 178) 116
8224 13:19:14.969547 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8225 13:19:14.976455 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8226 13:19:14.979785 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8227 13:19:14.982999 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8228 13:19:14.985982 iDelay=191, Bit 8, Center 110 (51 ~ 170) 120
8229 13:19:14.989616 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8230 13:19:14.996049 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8231 13:19:14.999374 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8232 13:19:15.002673 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8233 13:19:15.006033 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8234 13:19:15.009361 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8235 13:19:15.016025 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8236 13:19:15.016121 ==
8237 13:19:15.019528 Dram Type= 6, Freq= 0, CH_0, rank 1
8238 13:19:15.022724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8239 13:19:15.022796 ==
8240 13:19:15.022869 DQS Delay:
8241 13:19:15.025974 DQS0 = 0, DQS1 = 0
8242 13:19:15.026071 DQM Delay:
8243 13:19:15.029209 DQM0 = 124, DQM1 = 118
8244 13:19:15.029271 DQ Delay:
8245 13:19:15.032536 DQ0 =122, DQ1 =126, DQ2 =120, DQ3 =120
8246 13:19:15.035844 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8247 13:19:15.039183 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8248 13:19:15.045693 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8249 13:19:15.045790
8250 13:19:15.045873
8251 13:19:15.045951
8252 13:19:15.046035 [DramC_TX_OE_Calibration] TA2
8253 13:19:15.049054 Original DQ_B0 (3 6) =30, OEN = 27
8254 13:19:15.052324 Original DQ_B1 (3 6) =30, OEN = 27
8255 13:19:15.055975 24, 0x0, End_B0=24 End_B1=24
8256 13:19:15.058914 25, 0x0, End_B0=25 End_B1=25
8257 13:19:15.062245 26, 0x0, End_B0=26 End_B1=26
8258 13:19:15.062347 27, 0x0, End_B0=27 End_B1=27
8259 13:19:15.065504 28, 0x0, End_B0=28 End_B1=28
8260 13:19:15.069175 29, 0x0, End_B0=29 End_B1=29
8261 13:19:15.072014 30, 0x0, End_B0=30 End_B1=30
8262 13:19:15.075726 31, 0x5151, End_B0=30 End_B1=30
8263 13:19:15.078655 Byte0 end_step=30 best_step=27
8264 13:19:15.078729 Byte1 end_step=30 best_step=27
8265 13:19:15.082253 Byte0 TX OE(2T, 0.5T) = (3, 3)
8266 13:19:15.085585 Byte1 TX OE(2T, 0.5T) = (3, 3)
8267 13:19:15.085701
8268 13:19:15.085789
8269 13:19:15.095598 [DQSOSCAuto] RK1, (LSB)MR18= 0x2311, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8270 13:19:15.095687 CH0 RK1: MR19=303, MR18=2311
8271 13:19:15.102488 CH0_RK1: MR19=0x303, MR18=0x2311, DQSOSC=392, MR23=63, INC=24, DEC=16
8272 13:19:15.105159 [RxdqsGatingPostProcess] freq 1600
8273 13:19:15.111898 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8274 13:19:15.115182 best DQS0 dly(2T, 0.5T) = (1, 1)
8275 13:19:15.118538 best DQS1 dly(2T, 0.5T) = (1, 1)
8276 13:19:15.121774 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8277 13:19:15.124989 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8278 13:19:15.125068 best DQS0 dly(2T, 0.5T) = (1, 1)
8279 13:19:15.128566 best DQS1 dly(2T, 0.5T) = (1, 1)
8280 13:19:15.131728 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8281 13:19:15.134955 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8282 13:19:15.138813 Pre-setting of DQS Precalculation
8283 13:19:15.145436 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8284 13:19:15.145514 ==
8285 13:19:15.148746 Dram Type= 6, Freq= 0, CH_1, rank 0
8286 13:19:15.152089 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8287 13:19:15.152166 ==
8288 13:19:15.158678 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8289 13:19:15.162023 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8290 13:19:15.165240 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8291 13:19:15.171560 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8292 13:19:15.180313 [CA 0] Center 41 (12~71) winsize 60
8293 13:19:15.184068 [CA 1] Center 42 (13~72) winsize 60
8294 13:19:15.187183 [CA 2] Center 37 (9~66) winsize 58
8295 13:19:15.190286 [CA 3] Center 36 (7~66) winsize 60
8296 13:19:15.193863 [CA 4] Center 37 (8~66) winsize 59
8297 13:19:15.196688 [CA 5] Center 36 (7~66) winsize 60
8298 13:19:15.196785
8299 13:19:15.200082 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8300 13:19:15.200157
8301 13:19:15.203617 [CATrainingPosCal] consider 1 rank data
8302 13:19:15.207059 u2DelayCellTimex100 = 258/100 ps
8303 13:19:15.210621 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8304 13:19:15.216917 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8305 13:19:15.220351 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8306 13:19:15.223538 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8307 13:19:15.226861 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8308 13:19:15.230066 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8309 13:19:15.230195
8310 13:19:15.233240 CA PerBit enable=1, Macro0, CA PI delay=36
8311 13:19:15.233305
8312 13:19:15.236962 [CBTSetCACLKResult] CA Dly = 36
8313 13:19:15.240040 CS Dly: 9 (0~40)
8314 13:19:15.243318 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8315 13:19:15.246614 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8316 13:19:15.246702 ==
8317 13:19:15.249935 Dram Type= 6, Freq= 0, CH_1, rank 1
8318 13:19:15.253229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8319 13:19:15.256558 ==
8320 13:19:15.259761 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8321 13:19:15.263030 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8322 13:19:15.269805 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8323 13:19:15.273222 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8324 13:19:15.283724 [CA 0] Center 42 (12~72) winsize 61
8325 13:19:15.286789 [CA 1] Center 42 (12~72) winsize 61
8326 13:19:15.290214 [CA 2] Center 38 (9~67) winsize 59
8327 13:19:15.293171 [CA 3] Center 36 (7~66) winsize 60
8328 13:19:15.296931 [CA 4] Center 38 (8~68) winsize 61
8329 13:19:15.300307 [CA 5] Center 36 (7~66) winsize 60
8330 13:19:15.300383
8331 13:19:15.303536 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8332 13:19:15.303606
8333 13:19:15.306598 [CATrainingPosCal] consider 2 rank data
8334 13:19:15.309634 u2DelayCellTimex100 = 258/100 ps
8335 13:19:15.316511 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8336 13:19:15.319778 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8337 13:19:15.323022 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8338 13:19:15.326503 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8339 13:19:15.329747 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8340 13:19:15.333282 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8341 13:19:15.333379
8342 13:19:15.336240 CA PerBit enable=1, Macro0, CA PI delay=36
8343 13:19:15.336314
8344 13:19:15.339512 [CBTSetCACLKResult] CA Dly = 36
8345 13:19:15.343259 CS Dly: 10 (0~43)
8346 13:19:15.346664 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8347 13:19:15.349974 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8348 13:19:15.350048
8349 13:19:15.353229 ----->DramcWriteLeveling(PI) begin...
8350 13:19:15.353303 ==
8351 13:19:15.356609 Dram Type= 6, Freq= 0, CH_1, rank 0
8352 13:19:15.363266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8353 13:19:15.363350 ==
8354 13:19:15.366520 Write leveling (Byte 0): 26 => 26
8355 13:19:15.366610 Write leveling (Byte 1): 27 => 27
8356 13:19:15.369833 DramcWriteLeveling(PI) end<-----
8357 13:19:15.369920
8358 13:19:15.373226 ==
8359 13:19:15.373290 Dram Type= 6, Freq= 0, CH_1, rank 0
8360 13:19:15.379491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8361 13:19:15.379562 ==
8362 13:19:15.382697 [Gating] SW mode calibration
8363 13:19:15.389431 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8364 13:19:15.392725 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8365 13:19:15.399682 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 13:19:15.402712 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 13:19:15.405720 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 13:19:15.412682 1 4 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8369 13:19:15.415722 1 4 16 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
8370 13:19:15.419399 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 13:19:15.425961 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 13:19:15.429129 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 13:19:15.432521 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 13:19:15.438846 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 13:19:15.442448 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 13:19:15.445847 1 5 12 | B1->B0 | 3030 3434 | 1 1 | (1 0) (1 0)
8377 13:19:15.452487 1 5 16 | B1->B0 | 2424 2525 | 0 0 | (0 0) (1 0)
8378 13:19:15.455949 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 13:19:15.458593 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 13:19:15.465615 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 13:19:15.468916 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 13:19:15.472175 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 13:19:15.478945 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 13:19:15.482215 1 6 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8385 13:19:15.485599 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8386 13:19:15.492136 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 13:19:15.495490 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 13:19:15.498694 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 13:19:15.505115 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 13:19:15.508360 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 13:19:15.511604 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 13:19:15.518272 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 13:19:15.521636 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8394 13:19:15.524674 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8395 13:19:15.531922 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 13:19:15.534899 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 13:19:15.538280 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 13:19:15.545096 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 13:19:15.548349 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 13:19:15.551611 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 13:19:15.557779 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 13:19:15.561492 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 13:19:15.564603 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 13:19:15.568194 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 13:19:15.574761 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 13:19:15.578108 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 13:19:15.581366 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 13:19:15.588070 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8409 13:19:15.591235 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8410 13:19:15.594543 Total UI for P1: 0, mck2ui 16
8411 13:19:15.597827 best dqsien dly found for B1: ( 1, 9, 14)
8412 13:19:15.601072 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 13:19:15.604246 Total UI for P1: 0, mck2ui 16
8414 13:19:15.608064 best dqsien dly found for B0: ( 1, 9, 14)
8415 13:19:15.611300 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8416 13:19:15.614520 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8417 13:19:15.617859
8418 13:19:15.620978 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8419 13:19:15.624658 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8420 13:19:15.628006 [Gating] SW calibration Done
8421 13:19:15.628094 ==
8422 13:19:15.631323 Dram Type= 6, Freq= 0, CH_1, rank 0
8423 13:19:15.634466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8424 13:19:15.634557 ==
8425 13:19:15.634639 RX Vref Scan: 0
8426 13:19:15.637481
8427 13:19:15.637573 RX Vref 0 -> 0, step: 1
8428 13:19:15.637653
8429 13:19:15.641175 RX Delay 0 -> 252, step: 8
8430 13:19:15.644093 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8431 13:19:15.647853 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8432 13:19:15.654352 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8433 13:19:15.657608 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8434 13:19:15.660878 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8435 13:19:15.664049 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8436 13:19:15.667582 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8437 13:19:15.674244 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8438 13:19:15.677210 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8439 13:19:15.680715 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8440 13:19:15.684282 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8441 13:19:15.687444 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8442 13:19:15.694177 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8443 13:19:15.697379 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8444 13:19:15.700519 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8445 13:19:15.703798 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8446 13:19:15.703867 ==
8447 13:19:15.707152 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 13:19:15.713648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 13:19:15.713722 ==
8450 13:19:15.713799 DQS Delay:
8451 13:19:15.716949 DQS0 = 0, DQS1 = 0
8452 13:19:15.717015 DQM Delay:
8453 13:19:15.717073 DQM0 = 133, DQM1 = 126
8454 13:19:15.720110 DQ Delay:
8455 13:19:15.723516 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8456 13:19:15.727356 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8457 13:19:15.730465 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =119
8458 13:19:15.733664 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8459 13:19:15.733768
8460 13:19:15.733851
8461 13:19:15.733932 ==
8462 13:19:15.736974 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 13:19:15.740212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 13:19:15.743913 ==
8465 13:19:15.743999
8466 13:19:15.744085
8467 13:19:15.744165 TX Vref Scan disable
8468 13:19:15.747094 == TX Byte 0 ==
8469 13:19:15.750329 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8470 13:19:15.753546 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8471 13:19:15.757195 == TX Byte 1 ==
8472 13:19:15.760258 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8473 13:19:15.763356 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8474 13:19:15.766706 ==
8475 13:19:15.766801 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 13:19:15.773417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 13:19:15.773520 ==
8478 13:19:15.786844
8479 13:19:15.789899 TX Vref early break, caculate TX vref
8480 13:19:15.793013 TX Vref=16, minBit 13, minWin=21, winSum=364
8481 13:19:15.796338 TX Vref=18, minBit 12, minWin=22, winSum=376
8482 13:19:15.799984 TX Vref=20, minBit 11, minWin=23, winSum=386
8483 13:19:15.803268 TX Vref=22, minBit 0, minWin=24, winSum=396
8484 13:19:15.806528 TX Vref=24, minBit 5, minWin=24, winSum=406
8485 13:19:15.813070 TX Vref=26, minBit 0, minWin=25, winSum=413
8486 13:19:15.816297 TX Vref=28, minBit 1, minWin=25, winSum=420
8487 13:19:15.819658 TX Vref=30, minBit 0, minWin=25, winSum=416
8488 13:19:15.822940 TX Vref=32, minBit 0, minWin=24, winSum=408
8489 13:19:15.826214 TX Vref=34, minBit 0, minWin=24, winSum=401
8490 13:19:15.832667 TX Vref=36, minBit 0, minWin=23, winSum=387
8491 13:19:15.836427 [TxChooseVref] Worse bit 1, Min win 25, Win sum 420, Final Vref 28
8492 13:19:15.836524
8493 13:19:15.839572 Final TX Range 0 Vref 28
8494 13:19:15.839643
8495 13:19:15.839699 ==
8496 13:19:15.842886 Dram Type= 6, Freq= 0, CH_1, rank 0
8497 13:19:15.846128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8498 13:19:15.846241 ==
8499 13:19:15.849311
8500 13:19:15.849401
8501 13:19:15.849485 TX Vref Scan disable
8502 13:19:15.856138 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8503 13:19:15.856239 == TX Byte 0 ==
8504 13:19:15.859440 u2DelayCellOfst[0]=18 cells (5 PI)
8505 13:19:15.862639 u2DelayCellOfst[1]=11 cells (3 PI)
8506 13:19:15.865711 u2DelayCellOfst[2]=0 cells (0 PI)
8507 13:19:15.869491 u2DelayCellOfst[3]=7 cells (2 PI)
8508 13:19:15.872793 u2DelayCellOfst[4]=7 cells (2 PI)
8509 13:19:15.876096 u2DelayCellOfst[5]=18 cells (5 PI)
8510 13:19:15.879238 u2DelayCellOfst[6]=18 cells (5 PI)
8511 13:19:15.882688 u2DelayCellOfst[7]=3 cells (1 PI)
8512 13:19:15.885774 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8513 13:19:15.888988 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8514 13:19:15.892311 == TX Byte 1 ==
8515 13:19:15.895543 u2DelayCellOfst[8]=0 cells (0 PI)
8516 13:19:15.899244 u2DelayCellOfst[9]=7 cells (2 PI)
8517 13:19:15.902323 u2DelayCellOfst[10]=15 cells (4 PI)
8518 13:19:15.906030 u2DelayCellOfst[11]=7 cells (2 PI)
8519 13:19:15.909101 u2DelayCellOfst[12]=15 cells (4 PI)
8520 13:19:15.909194 u2DelayCellOfst[13]=22 cells (6 PI)
8521 13:19:15.912415 u2DelayCellOfst[14]=22 cells (6 PI)
8522 13:19:15.915727 u2DelayCellOfst[15]=22 cells (6 PI)
8523 13:19:15.922199 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8524 13:19:15.925445 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8525 13:19:15.925542 DramC Write-DBI on
8526 13:19:15.928748 ==
8527 13:19:15.932153 Dram Type= 6, Freq= 0, CH_1, rank 0
8528 13:19:15.935356 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8529 13:19:15.935452 ==
8530 13:19:15.935534
8531 13:19:15.935616
8532 13:19:15.938604 TX Vref Scan disable
8533 13:19:15.938694 == TX Byte 0 ==
8534 13:19:15.945361 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8535 13:19:15.945435 == TX Byte 1 ==
8536 13:19:15.948611 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8537 13:19:15.951714 DramC Write-DBI off
8538 13:19:15.951807
8539 13:19:15.951889 [DATLAT]
8540 13:19:15.955027 Freq=1600, CH1 RK0
8541 13:19:15.955123
8542 13:19:15.955204 DATLAT Default: 0xf
8543 13:19:15.958899 0, 0xFFFF, sum = 0
8544 13:19:15.959000 1, 0xFFFF, sum = 0
8545 13:19:15.962086 2, 0xFFFF, sum = 0
8546 13:19:15.962195 3, 0xFFFF, sum = 0
8547 13:19:15.965297 4, 0xFFFF, sum = 0
8548 13:19:15.965365 5, 0xFFFF, sum = 0
8549 13:19:15.968661 6, 0xFFFF, sum = 0
8550 13:19:15.968758 7, 0xFFFF, sum = 0
8551 13:19:15.971721 8, 0xFFFF, sum = 0
8552 13:19:15.974862 9, 0xFFFF, sum = 0
8553 13:19:15.974943 10, 0xFFFF, sum = 0
8554 13:19:15.978618 11, 0xFFFF, sum = 0
8555 13:19:15.978711 12, 0xFFFF, sum = 0
8556 13:19:15.981855 13, 0x8FFF, sum = 0
8557 13:19:15.981955 14, 0x0, sum = 1
8558 13:19:15.985130 15, 0x0, sum = 2
8559 13:19:15.985223 16, 0x0, sum = 3
8560 13:19:15.988313 17, 0x0, sum = 4
8561 13:19:15.988392 best_step = 15
8562 13:19:15.988474
8563 13:19:15.988529 ==
8564 13:19:15.991917 Dram Type= 6, Freq= 0, CH_1, rank 0
8565 13:19:15.995084 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8566 13:19:15.995165 ==
8567 13:19:15.998193 RX Vref Scan: 1
8568 13:19:15.998281
8569 13:19:16.002019 Set Vref Range= 24 -> 127
8570 13:19:16.002140
8571 13:19:16.002200 RX Vref 24 -> 127, step: 1
8572 13:19:16.002263
8573 13:19:16.005265 RX Delay 11 -> 252, step: 4
8574 13:19:16.005356
8575 13:19:16.008300 Set Vref, RX VrefLevel [Byte0]: 24
8576 13:19:16.011300 [Byte1]: 24
8577 13:19:16.015115
8578 13:19:16.015221 Set Vref, RX VrefLevel [Byte0]: 25
8579 13:19:16.018348 [Byte1]: 25
8580 13:19:16.022864
8581 13:19:16.022961 Set Vref, RX VrefLevel [Byte0]: 26
8582 13:19:16.026235 [Byte1]: 26
8583 13:19:16.030056
8584 13:19:16.030159 Set Vref, RX VrefLevel [Byte0]: 27
8585 13:19:16.033487 [Byte1]: 27
8586 13:19:16.037997
8587 13:19:16.038116 Set Vref, RX VrefLevel [Byte0]: 28
8588 13:19:16.041228 [Byte1]: 28
8589 13:19:16.045262
8590 13:19:16.045362 Set Vref, RX VrefLevel [Byte0]: 29
8591 13:19:16.049121 [Byte1]: 29
8592 13:19:16.052951
8593 13:19:16.053045 Set Vref, RX VrefLevel [Byte0]: 30
8594 13:19:16.056300 [Byte1]: 30
8595 13:19:16.061000
8596 13:19:16.064048 Set Vref, RX VrefLevel [Byte0]: 31
8597 13:19:16.067183 [Byte1]: 31
8598 13:19:16.067276
8599 13:19:16.070539 Set Vref, RX VrefLevel [Byte0]: 32
8600 13:19:16.073755 [Byte1]: 32
8601 13:19:16.073848
8602 13:19:16.077125 Set Vref, RX VrefLevel [Byte0]: 33
8603 13:19:16.080388 [Byte1]: 33
8604 13:19:16.080475
8605 13:19:16.083889 Set Vref, RX VrefLevel [Byte0]: 34
8606 13:19:16.087042 [Byte1]: 34
8607 13:19:16.091002
8608 13:19:16.091094 Set Vref, RX VrefLevel [Byte0]: 35
8609 13:19:16.094322 [Byte1]: 35
8610 13:19:16.098719
8611 13:19:16.098823 Set Vref, RX VrefLevel [Byte0]: 36
8612 13:19:16.101868 [Byte1]: 36
8613 13:19:16.106232
8614 13:19:16.106358 Set Vref, RX VrefLevel [Byte0]: 37
8615 13:19:16.109863 [Byte1]: 37
8616 13:19:16.114202
8617 13:19:16.114306 Set Vref, RX VrefLevel [Byte0]: 38
8618 13:19:16.117383 [Byte1]: 38
8619 13:19:16.121693
8620 13:19:16.121789 Set Vref, RX VrefLevel [Byte0]: 39
8621 13:19:16.124830 [Byte1]: 39
8622 13:19:16.129178
8623 13:19:16.129254 Set Vref, RX VrefLevel [Byte0]: 40
8624 13:19:16.132387 [Byte1]: 40
8625 13:19:16.136896
8626 13:19:16.136988 Set Vref, RX VrefLevel [Byte0]: 41
8627 13:19:16.140188 [Byte1]: 41
8628 13:19:16.144770
8629 13:19:16.144864 Set Vref, RX VrefLevel [Byte0]: 42
8630 13:19:16.148043 [Byte1]: 42
8631 13:19:16.151920
8632 13:19:16.152013 Set Vref, RX VrefLevel [Byte0]: 43
8633 13:19:16.155745 [Byte1]: 43
8634 13:19:16.159972
8635 13:19:16.160063 Set Vref, RX VrefLevel [Byte0]: 44
8636 13:19:16.163092 [Byte1]: 44
8637 13:19:16.167188
8638 13:19:16.167282 Set Vref, RX VrefLevel [Byte0]: 45
8639 13:19:16.170399 [Byte1]: 45
8640 13:19:16.174856
8641 13:19:16.174954 Set Vref, RX VrefLevel [Byte0]: 46
8642 13:19:16.177995 [Byte1]: 46
8643 13:19:16.182571
8644 13:19:16.182651 Set Vref, RX VrefLevel [Byte0]: 47
8645 13:19:16.185762 [Byte1]: 47
8646 13:19:16.190215
8647 13:19:16.190285 Set Vref, RX VrefLevel [Byte0]: 48
8648 13:19:16.193267 [Byte1]: 48
8649 13:19:16.198121
8650 13:19:16.198258 Set Vref, RX VrefLevel [Byte0]: 49
8651 13:19:16.201391 [Byte1]: 49
8652 13:19:16.205504
8653 13:19:16.205602 Set Vref, RX VrefLevel [Byte0]: 50
8654 13:19:16.208834 [Byte1]: 50
8655 13:19:16.212770
8656 13:19:16.212861 Set Vref, RX VrefLevel [Byte0]: 51
8657 13:19:16.216485 [Byte1]: 51
8658 13:19:16.220575
8659 13:19:16.220666 Set Vref, RX VrefLevel [Byte0]: 52
8660 13:19:16.224284 [Byte1]: 52
8661 13:19:16.228094
8662 13:19:16.228217 Set Vref, RX VrefLevel [Byte0]: 53
8663 13:19:16.231298 [Byte1]: 53
8664 13:19:16.236002
8665 13:19:16.236091 Set Vref, RX VrefLevel [Byte0]: 54
8666 13:19:16.238992 [Byte1]: 54
8667 13:19:16.243522
8668 13:19:16.243630 Set Vref, RX VrefLevel [Byte0]: 55
8669 13:19:16.246812 [Byte1]: 55
8670 13:19:16.250813
8671 13:19:16.250909 Set Vref, RX VrefLevel [Byte0]: 56
8672 13:19:16.254715 [Byte1]: 56
8673 13:19:16.258608
8674 13:19:16.258701 Set Vref, RX VrefLevel [Byte0]: 57
8675 13:19:16.261831 [Byte1]: 57
8676 13:19:16.266012
8677 13:19:16.266130 Set Vref, RX VrefLevel [Byte0]: 58
8678 13:19:16.269512 [Byte1]: 58
8679 13:19:16.273728
8680 13:19:16.273830 Set Vref, RX VrefLevel [Byte0]: 59
8681 13:19:16.277022 [Byte1]: 59
8682 13:19:16.281579
8683 13:19:16.281677 Set Vref, RX VrefLevel [Byte0]: 60
8684 13:19:16.284606 [Byte1]: 60
8685 13:19:16.289188
8686 13:19:16.289261 Set Vref, RX VrefLevel [Byte0]: 61
8687 13:19:16.292526 [Byte1]: 61
8688 13:19:16.296870
8689 13:19:16.296974 Set Vref, RX VrefLevel [Byte0]: 62
8690 13:19:16.299956 [Byte1]: 62
8691 13:19:16.304377
8692 13:19:16.304449 Set Vref, RX VrefLevel [Byte0]: 63
8693 13:19:16.307617 [Byte1]: 63
8694 13:19:16.312174
8695 13:19:16.312241 Set Vref, RX VrefLevel [Byte0]: 64
8696 13:19:16.315465 [Byte1]: 64
8697 13:19:16.319414
8698 13:19:16.319504 Set Vref, RX VrefLevel [Byte0]: 65
8699 13:19:16.323194 [Byte1]: 65
8700 13:19:16.327009
8701 13:19:16.327075 Set Vref, RX VrefLevel [Byte0]: 66
8702 13:19:16.330696 [Byte1]: 66
8703 13:19:16.334700
8704 13:19:16.334775 Set Vref, RX VrefLevel [Byte0]: 67
8705 13:19:16.337925 [Byte1]: 67
8706 13:19:16.342146
8707 13:19:16.342231 Set Vref, RX VrefLevel [Byte0]: 68
8708 13:19:16.345680 [Byte1]: 68
8709 13:19:16.349999
8710 13:19:16.350121 Set Vref, RX VrefLevel [Byte0]: 69
8711 13:19:16.353287 [Byte1]: 69
8712 13:19:16.357430
8713 13:19:16.357527 Set Vref, RX VrefLevel [Byte0]: 70
8714 13:19:16.361022 [Byte1]: 70
8715 13:19:16.365049
8716 13:19:16.365146 Set Vref, RX VrefLevel [Byte0]: 71
8717 13:19:16.368899 [Byte1]: 71
8718 13:19:16.372837
8719 13:19:16.372935 Set Vref, RX VrefLevel [Byte0]: 72
8720 13:19:16.376393 [Byte1]: 72
8721 13:19:16.380638
8722 13:19:16.380734 Set Vref, RX VrefLevel [Byte0]: 73
8723 13:19:16.383451 [Byte1]: 73
8724 13:19:16.388071
8725 13:19:16.388164 Final RX Vref Byte 0 = 55 to rank0
8726 13:19:16.391135 Final RX Vref Byte 1 = 52 to rank0
8727 13:19:16.394857 Final RX Vref Byte 0 = 55 to rank1
8728 13:19:16.398045 Final RX Vref Byte 1 = 52 to rank1==
8729 13:19:16.401379 Dram Type= 6, Freq= 0, CH_1, rank 0
8730 13:19:16.408174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8731 13:19:16.408251 ==
8732 13:19:16.408310 DQS Delay:
8733 13:19:16.411132 DQS0 = 0, DQS1 = 0
8734 13:19:16.411226 DQM Delay:
8735 13:19:16.411344 DQM0 = 130, DQM1 = 123
8736 13:19:16.414469 DQ Delay:
8737 13:19:16.417890 DQ0 =134, DQ1 =126, DQ2 =118, DQ3 =128
8738 13:19:16.421289 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =126
8739 13:19:16.424449 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8740 13:19:16.427715 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8741 13:19:16.427807
8742 13:19:16.427895
8743 13:19:16.427974
8744 13:19:16.431111 [DramC_TX_OE_Calibration] TA2
8745 13:19:16.434380 Original DQ_B0 (3 6) =30, OEN = 27
8746 13:19:16.437642 Original DQ_B1 (3 6) =30, OEN = 27
8747 13:19:16.440749 24, 0x0, End_B0=24 End_B1=24
8748 13:19:16.440844 25, 0x0, End_B0=25 End_B1=25
8749 13:19:16.444237 26, 0x0, End_B0=26 End_B1=26
8750 13:19:16.447632 27, 0x0, End_B0=27 End_B1=27
8751 13:19:16.450767 28, 0x0, End_B0=28 End_B1=28
8752 13:19:16.454491 29, 0x0, End_B0=29 End_B1=29
8753 13:19:16.454565 30, 0x0, End_B0=30 End_B1=30
8754 13:19:16.457525 31, 0x4141, End_B0=30 End_B1=30
8755 13:19:16.460796 Byte0 end_step=30 best_step=27
8756 13:19:16.464122 Byte1 end_step=30 best_step=27
8757 13:19:16.467408 Byte0 TX OE(2T, 0.5T) = (3, 3)
8758 13:19:16.470697 Byte1 TX OE(2T, 0.5T) = (3, 3)
8759 13:19:16.470765
8760 13:19:16.470819
8761 13:19:16.477438 [DQSOSCAuto] RK0, (LSB)MR18= 0x80c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8762 13:19:16.480735 CH1 RK0: MR19=303, MR18=80C
8763 13:19:16.487177 CH1_RK0: MR19=0x303, MR18=0x80C, DQSOSC=403, MR23=63, INC=22, DEC=15
8764 13:19:16.487272
8765 13:19:16.490931 ----->DramcWriteLeveling(PI) begin...
8766 13:19:16.491028 ==
8767 13:19:16.494032 Dram Type= 6, Freq= 0, CH_1, rank 1
8768 13:19:16.497303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8769 13:19:16.497412 ==
8770 13:19:16.500985 Write leveling (Byte 0): 24 => 24
8771 13:19:16.504322 Write leveling (Byte 1): 28 => 28
8772 13:19:16.507661 DramcWriteLeveling(PI) end<-----
8773 13:19:16.507758
8774 13:19:16.507840 ==
8775 13:19:16.511063 Dram Type= 6, Freq= 0, CH_1, rank 1
8776 13:19:16.514249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8777 13:19:16.514348 ==
8778 13:19:16.517355 [Gating] SW mode calibration
8779 13:19:16.523987 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8780 13:19:16.530518 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8781 13:19:16.533838 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 13:19:16.536966 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 13:19:16.543560 1 4 8 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
8784 13:19:16.547417 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8785 13:19:16.550585 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 13:19:16.557237 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 13:19:16.560254 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 13:19:16.563927 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 13:19:16.570444 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 13:19:16.573652 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 13:19:16.577049 1 5 8 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
8792 13:19:16.583653 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8793 13:19:16.586895 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 13:19:16.590236 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 13:19:16.596628 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 13:19:16.600326 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 13:19:16.603681 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 13:19:16.610019 1 6 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8799 13:19:16.613384 1 6 8 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
8800 13:19:16.616694 1 6 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8801 13:19:16.623298 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 13:19:16.626421 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 13:19:16.630010 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 13:19:16.636752 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 13:19:16.639888 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 13:19:16.643269 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 13:19:16.649929 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8808 13:19:16.653218 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8809 13:19:16.656386 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 13:19:16.663178 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 13:19:16.666920 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 13:19:16.669896 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 13:19:16.676736 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 13:19:16.679936 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 13:19:16.683222 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 13:19:16.689912 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 13:19:16.693185 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 13:19:16.696493 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 13:19:16.699837 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 13:19:16.706614 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 13:19:16.709783 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 13:19:16.712964 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 13:19:16.720012 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8824 13:19:16.723147 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8825 13:19:16.726413 Total UI for P1: 0, mck2ui 16
8826 13:19:16.729753 best dqsien dly found for B0: ( 1, 9, 8)
8827 13:19:16.732882 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8828 13:19:16.736079 Total UI for P1: 0, mck2ui 16
8829 13:19:16.739256 best dqsien dly found for B1: ( 1, 9, 10)
8830 13:19:16.742947 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8831 13:19:16.745836 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8832 13:19:16.745927
8833 13:19:16.752574 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8834 13:19:16.755908 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8835 13:19:16.759329 [Gating] SW calibration Done
8836 13:19:16.759426 ==
8837 13:19:16.762754 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 13:19:16.766036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 13:19:16.766160 ==
8840 13:19:16.766248 RX Vref Scan: 0
8841 13:19:16.769209
8842 13:19:16.769314 RX Vref 0 -> 0, step: 1
8843 13:19:16.769406
8844 13:19:16.772767 RX Delay 0 -> 252, step: 8
8845 13:19:16.776265 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8846 13:19:16.779383 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8847 13:19:16.786327 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8848 13:19:16.788862 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8849 13:19:16.792820 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8850 13:19:16.796028 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8851 13:19:16.799331 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8852 13:19:16.805902 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8853 13:19:16.809100 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8854 13:19:16.812240 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8855 13:19:16.815733 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8856 13:19:16.818875 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8857 13:19:16.825290 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8858 13:19:16.828514 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8859 13:19:16.832428 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8860 13:19:16.835621 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8861 13:19:16.835713 ==
8862 13:19:16.838879 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 13:19:16.845429 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 13:19:16.845527 ==
8865 13:19:16.845617 DQS Delay:
8866 13:19:16.848676 DQS0 = 0, DQS1 = 0
8867 13:19:16.848764 DQM Delay:
8868 13:19:16.848849 DQM0 = 130, DQM1 = 127
8869 13:19:16.851975 DQ Delay:
8870 13:19:16.855066 DQ0 =131, DQ1 =127, DQ2 =119, DQ3 =127
8871 13:19:16.858891 DQ4 =123, DQ5 =143, DQ6 =143, DQ7 =127
8872 13:19:16.861747 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8873 13:19:16.865153 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8874 13:19:16.865222
8875 13:19:16.865277
8876 13:19:16.865329 ==
8877 13:19:16.868394 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 13:19:16.874892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 13:19:16.874990 ==
8880 13:19:16.875073
8881 13:19:16.875156
8882 13:19:16.875242 TX Vref Scan disable
8883 13:19:16.878495 == TX Byte 0 ==
8884 13:19:16.881938 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8885 13:19:16.885096 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8886 13:19:16.888232 == TX Byte 1 ==
8887 13:19:16.891930 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8888 13:19:16.898379 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8889 13:19:16.898476 ==
8890 13:19:16.901621 Dram Type= 6, Freq= 0, CH_1, rank 1
8891 13:19:16.905107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8892 13:19:16.905205 ==
8893 13:19:16.917570
8894 13:19:16.920662 TX Vref early break, caculate TX vref
8895 13:19:16.924297 TX Vref=16, minBit 0, minWin=23, winSum=388
8896 13:19:16.927215 TX Vref=18, minBit 0, minWin=24, winSum=396
8897 13:19:16.930942 TX Vref=20, minBit 14, minWin=24, winSum=403
8898 13:19:16.934260 TX Vref=22, minBit 0, minWin=24, winSum=411
8899 13:19:16.937470 TX Vref=24, minBit 0, minWin=25, winSum=417
8900 13:19:16.943793 TX Vref=26, minBit 13, minWin=25, winSum=421
8901 13:19:16.947097 TX Vref=28, minBit 0, minWin=26, winSum=424
8902 13:19:16.950415 TX Vref=30, minBit 1, minWin=25, winSum=419
8903 13:19:16.953727 TX Vref=32, minBit 1, minWin=24, winSum=414
8904 13:19:16.957070 TX Vref=34, minBit 5, minWin=23, winSum=401
8905 13:19:16.963912 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
8906 13:19:16.964020
8907 13:19:16.967012 Final TX Range 0 Vref 28
8908 13:19:16.967120
8909 13:19:16.967197 ==
8910 13:19:16.970570 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 13:19:16.973720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 13:19:16.973799 ==
8913 13:19:16.973876
8914 13:19:16.974012
8915 13:19:16.977064 TX Vref Scan disable
8916 13:19:16.984078 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8917 13:19:16.984157 == TX Byte 0 ==
8918 13:19:16.987147 u2DelayCellOfst[0]=18 cells (5 PI)
8919 13:19:16.990594 u2DelayCellOfst[1]=11 cells (3 PI)
8920 13:19:16.993687 u2DelayCellOfst[2]=0 cells (0 PI)
8921 13:19:16.997075 u2DelayCellOfst[3]=7 cells (2 PI)
8922 13:19:17.000007 u2DelayCellOfst[4]=7 cells (2 PI)
8923 13:19:17.003730 u2DelayCellOfst[5]=18 cells (5 PI)
8924 13:19:17.006971 u2DelayCellOfst[6]=18 cells (5 PI)
8925 13:19:17.009970 u2DelayCellOfst[7]=7 cells (2 PI)
8926 13:19:17.013766 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8927 13:19:17.017069 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8928 13:19:17.020428 == TX Byte 1 ==
8929 13:19:17.023682 u2DelayCellOfst[8]=0 cells (0 PI)
8930 13:19:17.023761 u2DelayCellOfst[9]=7 cells (2 PI)
8931 13:19:17.026921 u2DelayCellOfst[10]=11 cells (3 PI)
8932 13:19:17.030067 u2DelayCellOfst[11]=7 cells (2 PI)
8933 13:19:17.033624 u2DelayCellOfst[12]=15 cells (4 PI)
8934 13:19:17.036441 u2DelayCellOfst[13]=18 cells (5 PI)
8935 13:19:17.039696 u2DelayCellOfst[14]=22 cells (6 PI)
8936 13:19:17.043088 u2DelayCellOfst[15]=22 cells (6 PI)
8937 13:19:17.046868 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8938 13:19:17.053465 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8939 13:19:17.053557 DramC Write-DBI on
8940 13:19:17.053635 ==
8941 13:19:17.056651 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 13:19:17.063250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 13:19:17.063329 ==
8944 13:19:17.063407
8945 13:19:17.063480
8946 13:19:17.063550 TX Vref Scan disable
8947 13:19:17.067204 == TX Byte 0 ==
8948 13:19:17.070381 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8949 13:19:17.073546 == TX Byte 1 ==
8950 13:19:17.076630 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8951 13:19:17.080375 DramC Write-DBI off
8952 13:19:17.080453
8953 13:19:17.080529 [DATLAT]
8954 13:19:17.080601 Freq=1600, CH1 RK1
8955 13:19:17.080672
8956 13:19:17.083627 DATLAT Default: 0xf
8957 13:19:17.083704 0, 0xFFFF, sum = 0
8958 13:19:17.086846 1, 0xFFFF, sum = 0
8959 13:19:17.090045 2, 0xFFFF, sum = 0
8960 13:19:17.090177 3, 0xFFFF, sum = 0
8961 13:19:17.093256 4, 0xFFFF, sum = 0
8962 13:19:17.093334 5, 0xFFFF, sum = 0
8963 13:19:17.096420 6, 0xFFFF, sum = 0
8964 13:19:17.096499 7, 0xFFFF, sum = 0
8965 13:19:17.099712 8, 0xFFFF, sum = 0
8966 13:19:17.099791 9, 0xFFFF, sum = 0
8967 13:19:17.103508 10, 0xFFFF, sum = 0
8968 13:19:17.103588 11, 0xFFFF, sum = 0
8969 13:19:17.106464 12, 0xFFFF, sum = 0
8970 13:19:17.106543 13, 0x8FFF, sum = 0
8971 13:19:17.110119 14, 0x0, sum = 1
8972 13:19:17.110215 15, 0x0, sum = 2
8973 13:19:17.113253 16, 0x0, sum = 3
8974 13:19:17.113331 17, 0x0, sum = 4
8975 13:19:17.116489 best_step = 15
8976 13:19:17.116565
8977 13:19:17.116642 ==
8978 13:19:17.119634 Dram Type= 6, Freq= 0, CH_1, rank 1
8979 13:19:17.123508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8980 13:19:17.123587 ==
8981 13:19:17.126223 RX Vref Scan: 0
8982 13:19:17.126300
8983 13:19:17.126376 RX Vref 0 -> 0, step: 1
8984 13:19:17.126448
8985 13:19:17.130061 RX Delay 11 -> 252, step: 4
8986 13:19:17.133286 iDelay=195, Bit 0, Center 130 (75 ~ 186) 112
8987 13:19:17.139702 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8988 13:19:17.143346 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8989 13:19:17.146383 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8990 13:19:17.149705 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8991 13:19:17.152854 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8992 13:19:17.159421 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8993 13:19:17.162786 iDelay=195, Bit 7, Center 122 (67 ~ 178) 112
8994 13:19:17.166051 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
8995 13:19:17.169298 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
8996 13:19:17.173230 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8997 13:19:17.179687 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8998 13:19:17.182863 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8999 13:19:17.186536 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9000 13:19:17.189652 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9001 13:19:17.196118 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9002 13:19:17.196210 ==
9003 13:19:17.199380 Dram Type= 6, Freq= 0, CH_1, rank 1
9004 13:19:17.203097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9005 13:19:17.203171 ==
9006 13:19:17.203301 DQS Delay:
9007 13:19:17.206412 DQS0 = 0, DQS1 = 0
9008 13:19:17.206480 DQM Delay:
9009 13:19:17.209796 DQM0 = 127, DQM1 = 125
9010 13:19:17.209877 DQ Delay:
9011 13:19:17.212996 DQ0 =130, DQ1 =126, DQ2 =116, DQ3 =124
9012 13:19:17.216103 DQ4 =124, DQ5 =140, DQ6 =138, DQ7 =122
9013 13:19:17.219731 DQ8 =110, DQ9 =114, DQ10 =128, DQ11 =120
9014 13:19:17.222924 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =134
9015 13:19:17.223001
9016 13:19:17.223060
9017 13:19:17.223114
9018 13:19:17.226056 [DramC_TX_OE_Calibration] TA2
9019 13:19:17.229247 Original DQ_B0 (3 6) =30, OEN = 27
9020 13:19:17.232559 Original DQ_B1 (3 6) =30, OEN = 27
9021 13:19:17.235852 24, 0x0, End_B0=24 End_B1=24
9022 13:19:17.239072 25, 0x0, End_B0=25 End_B1=25
9023 13:19:17.239148 26, 0x0, End_B0=26 End_B1=26
9024 13:19:17.242389 27, 0x0, End_B0=27 End_B1=27
9025 13:19:17.245720 28, 0x0, End_B0=28 End_B1=28
9026 13:19:17.248988 29, 0x0, End_B0=29 End_B1=29
9027 13:19:17.252136 30, 0x0, End_B0=30 End_B1=30
9028 13:19:17.255710 31, 0x4141, End_B0=30 End_B1=30
9029 13:19:17.255788 Byte0 end_step=30 best_step=27
9030 13:19:17.258655 Byte1 end_step=30 best_step=27
9031 13:19:17.262205 Byte0 TX OE(2T, 0.5T) = (3, 3)
9032 13:19:17.265574 Byte1 TX OE(2T, 0.5T) = (3, 3)
9033 13:19:17.265682
9034 13:19:17.265754
9035 13:19:17.271944 [DQSOSCAuto] RK1, (LSB)MR18= 0x101b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
9036 13:19:17.275234 CH1 RK1: MR19=303, MR18=101B
9037 13:19:17.282365 CH1_RK1: MR19=0x303, MR18=0x101B, DQSOSC=396, MR23=63, INC=23, DEC=15
9038 13:19:17.285499 [RxdqsGatingPostProcess] freq 1600
9039 13:19:17.291827 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9040 13:19:17.295457 best DQS0 dly(2T, 0.5T) = (1, 1)
9041 13:19:17.298597 best DQS1 dly(2T, 0.5T) = (1, 1)
9042 13:19:17.298674 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9043 13:19:17.301725 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9044 13:19:17.305433 best DQS0 dly(2T, 0.5T) = (1, 1)
9045 13:19:17.308622 best DQS1 dly(2T, 0.5T) = (1, 1)
9046 13:19:17.311853 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9047 13:19:17.315262 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9048 13:19:17.318559 Pre-setting of DQS Precalculation
9049 13:19:17.324770 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9050 13:19:17.331451 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9051 13:19:17.338408 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9052 13:19:17.338487
9053 13:19:17.338563
9054 13:19:17.341634 [Calibration Summary] 3200 Mbps
9055 13:19:17.341709 CH 0, Rank 0
9056 13:19:17.344981 SW Impedance : PASS
9057 13:19:17.348177 DUTY Scan : NO K
9058 13:19:17.348253 ZQ Calibration : PASS
9059 13:19:17.351480 Jitter Meter : NO K
9060 13:19:17.354792 CBT Training : PASS
9061 13:19:17.354867 Write leveling : PASS
9062 13:19:17.358305 RX DQS gating : PASS
9063 13:19:17.361472 RX DQ/DQS(RDDQC) : PASS
9064 13:19:17.361562 TX DQ/DQS : PASS
9065 13:19:17.364771 RX DATLAT : PASS
9066 13:19:17.364864 RX DQ/DQS(Engine): PASS
9067 13:19:17.367859 TX OE : PASS
9068 13:19:17.367959 All Pass.
9069 13:19:17.368043
9070 13:19:17.371463 CH 0, Rank 1
9071 13:19:17.371540 SW Impedance : PASS
9072 13:19:17.374720 DUTY Scan : NO K
9073 13:19:17.377837 ZQ Calibration : PASS
9074 13:19:17.377947 Jitter Meter : NO K
9075 13:19:17.380956 CBT Training : PASS
9076 13:19:17.384475 Write leveling : PASS
9077 13:19:17.384581 RX DQS gating : PASS
9078 13:19:17.387680 RX DQ/DQS(RDDQC) : PASS
9079 13:19:17.390900 TX DQ/DQS : PASS
9080 13:19:17.390975 RX DATLAT : PASS
9081 13:19:17.394250 RX DQ/DQS(Engine): PASS
9082 13:19:17.397464 TX OE : PASS
9083 13:19:17.397538 All Pass.
9084 13:19:17.397611
9085 13:19:17.397678 CH 1, Rank 0
9086 13:19:17.400672 SW Impedance : PASS
9087 13:19:17.404287 DUTY Scan : NO K
9088 13:19:17.404362 ZQ Calibration : PASS
9089 13:19:17.407517 Jitter Meter : NO K
9090 13:19:17.410612 CBT Training : PASS
9091 13:19:17.410687 Write leveling : PASS
9092 13:19:17.414301 RX DQS gating : PASS
9093 13:19:17.417535 RX DQ/DQS(RDDQC) : PASS
9094 13:19:17.417610 TX DQ/DQS : PASS
9095 13:19:17.420696 RX DATLAT : PASS
9096 13:19:17.424017 RX DQ/DQS(Engine): PASS
9097 13:19:17.424116 TX OE : PASS
9098 13:19:17.424206 All Pass.
9099 13:19:17.427272
9100 13:19:17.427369 CH 1, Rank 1
9101 13:19:17.430445 SW Impedance : PASS
9102 13:19:17.430542 DUTY Scan : NO K
9103 13:19:17.434127 ZQ Calibration : PASS
9104 13:19:17.437206 Jitter Meter : NO K
9105 13:19:17.437309 CBT Training : PASS
9106 13:19:17.440353 Write leveling : PASS
9107 13:19:17.440460 RX DQS gating : PASS
9108 13:19:17.444243 RX DQ/DQS(RDDQC) : PASS
9109 13:19:17.447448 TX DQ/DQS : PASS
9110 13:19:17.447523 RX DATLAT : PASS
9111 13:19:17.450702 RX DQ/DQS(Engine): PASS
9112 13:19:17.453988 TX OE : PASS
9113 13:19:17.454067 All Pass.
9114 13:19:17.454184
9115 13:19:17.457366 DramC Write-DBI on
9116 13:19:17.457443 PER_BANK_REFRESH: Hybrid Mode
9117 13:19:17.460640 TX_TRACKING: ON
9118 13:19:17.470445 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9119 13:19:17.476982 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9120 13:19:17.483641 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9121 13:19:17.487213 [FAST_K] Save calibration result to emmc
9122 13:19:17.489988 sync common calibartion params.
9123 13:19:17.493530 sync cbt_mode0:1, 1:1
9124 13:19:17.493649 dram_init: ddr_geometry: 2
9125 13:19:17.496754 dram_init: ddr_geometry: 2
9126 13:19:17.500248 dram_init: ddr_geometry: 2
9127 13:19:17.503454 0:dram_rank_size:100000000
9128 13:19:17.503527 1:dram_rank_size:100000000
9129 13:19:17.509838 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9130 13:19:17.512866 DFS_SHUFFLE_HW_MODE: ON
9131 13:19:17.516727 dramc_set_vcore_voltage set vcore to 725000
9132 13:19:17.519870 Read voltage for 1600, 0
9133 13:19:17.519937 Vio18 = 0
9134 13:19:17.519992 Vcore = 725000
9135 13:19:17.522989 Vdram = 0
9136 13:19:17.523052 Vddq = 0
9137 13:19:17.523142 Vmddr = 0
9138 13:19:17.526078 switch to 3200 Mbps bootup
9139 13:19:17.526184 [DramcRunTimeConfig]
9140 13:19:17.529423 PHYPLL
9141 13:19:17.529485 DPM_CONTROL_AFTERK: ON
9142 13:19:17.532740 PER_BANK_REFRESH: ON
9143 13:19:17.536107 REFRESH_OVERHEAD_REDUCTION: ON
9144 13:19:17.536187 CMD_PICG_NEW_MODE: OFF
9145 13:19:17.539958 XRTWTW_NEW_MODE: ON
9146 13:19:17.540035 XRTRTR_NEW_MODE: ON
9147 13:19:17.543036 TX_TRACKING: ON
9148 13:19:17.543127 RDSEL_TRACKING: OFF
9149 13:19:17.546207 DQS Precalculation for DVFS: ON
9150 13:19:17.549293 RX_TRACKING: OFF
9151 13:19:17.549356 HW_GATING DBG: ON
9152 13:19:17.552639 ZQCS_ENABLE_LP4: ON
9153 13:19:17.552707 RX_PICG_NEW_MODE: ON
9154 13:19:17.556395 TX_PICG_NEW_MODE: ON
9155 13:19:17.559649 ENABLE_RX_DCM_DPHY: ON
9156 13:19:17.559717 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9157 13:19:17.562879 DUMMY_READ_FOR_TRACKING: OFF
9158 13:19:17.566179 !!! SPM_CONTROL_AFTERK: OFF
9159 13:19:17.569588 !!! SPM could not control APHY
9160 13:19:17.569656 IMPEDANCE_TRACKING: ON
9161 13:19:17.572896 TEMP_SENSOR: ON
9162 13:19:17.572960 HW_SAVE_FOR_SR: OFF
9163 13:19:17.576180 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9164 13:19:17.579473 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9165 13:19:17.582716 Read ODT Tracking: ON
9166 13:19:17.586001 Refresh Rate DeBounce: ON
9167 13:19:17.586092 DFS_NO_QUEUE_FLUSH: ON
9168 13:19:17.589136 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9169 13:19:17.592476 ENABLE_DFS_RUNTIME_MRW: OFF
9170 13:19:17.596119 DDR_RESERVE_NEW_MODE: ON
9171 13:19:17.596184 MR_CBT_SWITCH_FREQ: ON
9172 13:19:17.599132 =========================
9173 13:19:17.618365 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9174 13:19:17.621425 dram_init: ddr_geometry: 2
9175 13:19:17.639944 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9176 13:19:17.643184 dram_init: dram init end (result: 0)
9177 13:19:17.650013 DRAM-K: Full calibration passed in 24609 msecs
9178 13:19:17.653113 MRC: failed to locate region type 0.
9179 13:19:17.653192 DRAM rank0 size:0x100000000,
9180 13:19:17.656267 DRAM rank1 size=0x100000000
9181 13:19:17.666656 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9182 13:19:17.673186 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9183 13:19:17.679634 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9184 13:19:17.686072 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9185 13:19:17.689306 DRAM rank0 size:0x100000000,
9186 13:19:17.692582 DRAM rank1 size=0x100000000
9187 13:19:17.692658 CBMEM:
9188 13:19:17.695938 IMD: root @ 0xfffff000 254 entries.
9189 13:19:17.699165 IMD: root @ 0xffffec00 62 entries.
9190 13:19:17.702482 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9191 13:19:17.709364 WARNING: RO_VPD is uninitialized or empty.
9192 13:19:17.712403 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9193 13:19:17.720079 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9194 13:19:17.732690 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9195 13:19:17.743942 BS: romstage times (exec / console): total (unknown) / 24067 ms
9196 13:19:17.744023
9197 13:19:17.744082
9198 13:19:17.754124 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9199 13:19:17.757172 ARM64: Exception handlers installed.
9200 13:19:17.760883 ARM64: Testing exception
9201 13:19:17.764085 ARM64: Done test exception
9202 13:19:17.764178 Enumerating buses...
9203 13:19:17.767255 Show all devs... Before device enumeration.
9204 13:19:17.770460 Root Device: enabled 1
9205 13:19:17.773812 CPU_CLUSTER: 0: enabled 1
9206 13:19:17.773911 CPU: 00: enabled 1
9207 13:19:17.777132 Compare with tree...
9208 13:19:17.777234 Root Device: enabled 1
9209 13:19:17.780371 CPU_CLUSTER: 0: enabled 1
9210 13:19:17.783698 CPU: 00: enabled 1
9211 13:19:17.783796 Root Device scanning...
9212 13:19:17.787000 scan_static_bus for Root Device
9213 13:19:17.790228 CPU_CLUSTER: 0 enabled
9214 13:19:17.793465 scan_static_bus for Root Device done
9215 13:19:17.796895 scan_bus: bus Root Device finished in 8 msecs
9216 13:19:17.796970 done
9217 13:19:17.803577 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9218 13:19:17.806865 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9219 13:19:17.813248 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9220 13:19:17.816492 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9221 13:19:17.819839 Allocating resources...
9222 13:19:17.823654 Reading resources...
9223 13:19:17.826854 Root Device read_resources bus 0 link: 0
9224 13:19:17.829851 DRAM rank0 size:0x100000000,
9225 13:19:17.829926 DRAM rank1 size=0x100000000
9226 13:19:17.833414 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9227 13:19:17.836639 CPU: 00 missing read_resources
9228 13:19:17.842903 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9229 13:19:17.846681 Root Device read_resources bus 0 link: 0 done
9230 13:19:17.846772 Done reading resources.
9231 13:19:17.853179 Show resources in subtree (Root Device)...After reading.
9232 13:19:17.856697 Root Device child on link 0 CPU_CLUSTER: 0
9233 13:19:17.860084 CPU_CLUSTER: 0 child on link 0 CPU: 00
9234 13:19:17.869697 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9235 13:19:17.869777 CPU: 00
9236 13:19:17.872869 Root Device assign_resources, bus 0 link: 0
9237 13:19:17.876397 CPU_CLUSTER: 0 missing set_resources
9238 13:19:17.882874 Root Device assign_resources, bus 0 link: 0 done
9239 13:19:17.882952 Done setting resources.
9240 13:19:17.889447 Show resources in subtree (Root Device)...After assigning values.
9241 13:19:17.892773 Root Device child on link 0 CPU_CLUSTER: 0
9242 13:19:17.896067 CPU_CLUSTER: 0 child on link 0 CPU: 00
9243 13:19:17.906002 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9244 13:19:17.906089 CPU: 00
9245 13:19:17.909355 Done allocating resources.
9246 13:19:17.915687 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9247 13:19:17.915764 Enabling resources...
9248 13:19:17.919121 done.
9249 13:19:17.922367 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9250 13:19:17.925747 Initializing devices...
9251 13:19:17.925813 Root Device init
9252 13:19:17.929177 init hardware done!
9253 13:19:17.929241 0x00000018: ctrlr->caps
9254 13:19:17.932391 52.000 MHz: ctrlr->f_max
9255 13:19:17.935413 0.400 MHz: ctrlr->f_min
9256 13:19:17.935487 0x40ff8080: ctrlr->voltages
9257 13:19:17.939138 sclk: 390625
9258 13:19:17.939202 Bus Width = 1
9259 13:19:17.942065 sclk: 390625
9260 13:19:17.942183 Bus Width = 1
9261 13:19:17.945156 Early init status = 3
9262 13:19:17.948321 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9263 13:19:17.952336 in-header: 03 fc 00 00 01 00 00 00
9264 13:19:17.955653 in-data: 00
9265 13:19:17.959416 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9266 13:19:17.964531 in-header: 03 fd 00 00 00 00 00 00
9267 13:19:17.968205 in-data:
9268 13:19:17.971430 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9269 13:19:17.975834 in-header: 03 fc 00 00 01 00 00 00
9270 13:19:17.978753 in-data: 00
9271 13:19:17.982437 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9272 13:19:17.987698 in-header: 03 fd 00 00 00 00 00 00
9273 13:19:17.991172 in-data:
9274 13:19:17.994204 [SSUSB] Setting up USB HOST controller...
9275 13:19:17.997864 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9276 13:19:18.001096 [SSUSB] phy power-on done.
9277 13:19:18.004500 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9278 13:19:18.011083 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9279 13:19:18.014382 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9280 13:19:18.020937 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9281 13:19:18.027557 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9282 13:19:18.034149 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9283 13:19:18.041054 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9284 13:19:18.047473 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9285 13:19:18.051016 SPM: binary array size = 0x9dc
9286 13:19:18.053892 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9287 13:19:18.061301 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9288 13:19:18.067622 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9289 13:19:18.074037 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9290 13:19:18.077250 configure_display: Starting display init
9291 13:19:18.111143 anx7625_power_on_init: Init interface.
9292 13:19:18.114269 anx7625_disable_pd_protocol: Disabled PD feature.
9293 13:19:18.118178 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9294 13:19:18.145523 anx7625_start_dp_work: Secure OCM version=00
9295 13:19:18.148655 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9296 13:19:18.163803 sp_tx_get_edid_block: EDID Block = 1
9297 13:19:18.265951 Extracted contents:
9298 13:19:18.269659 header: 00 ff ff ff ff ff ff 00
9299 13:19:18.272630 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9300 13:19:18.276270 version: 01 04
9301 13:19:18.279186 basic params: 95 1f 11 78 0a
9302 13:19:18.282951 chroma info: 76 90 94 55 54 90 27 21 50 54
9303 13:19:18.286087 established: 00 00 00
9304 13:19:18.292523 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9305 13:19:18.299249 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9306 13:19:18.302611 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9307 13:19:18.309219 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9308 13:19:18.315863 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9309 13:19:18.319045 extensions: 00
9310 13:19:18.319155 checksum: fb
9311 13:19:18.319246
9312 13:19:18.322394 Manufacturer: IVO Model 57d Serial Number 0
9313 13:19:18.325596 Made week 0 of 2020
9314 13:19:18.328694 EDID version: 1.4
9315 13:19:18.328807 Digital display
9316 13:19:18.332493 6 bits per primary color channel
9317 13:19:18.332605 DisplayPort interface
9318 13:19:18.335272 Maximum image size: 31 cm x 17 cm
9319 13:19:18.338687 Gamma: 220%
9320 13:19:18.338794 Check DPMS levels
9321 13:19:18.342072 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9322 13:19:18.348987 First detailed timing is preferred timing
9323 13:19:18.349125 Established timings supported:
9324 13:19:18.352000 Standard timings supported:
9325 13:19:18.355157 Detailed timings
9326 13:19:18.358473 Hex of detail: 383680a07038204018303c0035ae10000019
9327 13:19:18.365122 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9328 13:19:18.368298 0780 0798 07c8 0820 hborder 0
9329 13:19:18.371582 0438 043b 0447 0458 vborder 0
9330 13:19:18.374878 -hsync -vsync
9331 13:19:18.374992 Did detailed timing
9332 13:19:18.381604 Hex of detail: 000000000000000000000000000000000000
9333 13:19:18.384898 Manufacturer-specified data, tag 0
9334 13:19:18.388329 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9335 13:19:18.391124 ASCII string: InfoVision
9336 13:19:18.394833 Hex of detail: 000000fe00523134304e574635205248200a
9337 13:19:18.397940 ASCII string: R140NWF5 RH
9338 13:19:18.398009 Checksum
9339 13:19:18.401217 Checksum: 0xfb (valid)
9340 13:19:18.404485 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9341 13:19:18.407825 DSI data_rate: 832800000 bps
9342 13:19:18.414453 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9343 13:19:18.417653 anx7625_parse_edid: pixelclock(138800).
9344 13:19:18.420968 hactive(1920), hsync(48), hfp(24), hbp(88)
9345 13:19:18.424193 vactive(1080), vsync(12), vfp(3), vbp(17)
9346 13:19:18.427466 anx7625_dsi_config: config dsi.
9347 13:19:18.434060 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9348 13:19:18.448179 anx7625_dsi_config: success to config DSI
9349 13:19:18.451583 anx7625_dp_start: MIPI phy setup OK.
9350 13:19:18.454688 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9351 13:19:18.457999 mtk_ddp_mode_set invalid vrefresh 60
9352 13:19:18.461094 main_disp_path_setup
9353 13:19:18.461163 ovl_layer_smi_id_en
9354 13:19:18.464521 ovl_layer_smi_id_en
9355 13:19:18.464592 ccorr_config
9356 13:19:18.464648 aal_config
9357 13:19:18.468172 gamma_config
9358 13:19:18.468239 postmask_config
9359 13:19:18.471174 dither_config
9360 13:19:18.474302 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9361 13:19:18.481153 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9362 13:19:18.484426 Root Device init finished in 555 msecs
9363 13:19:18.487565 CPU_CLUSTER: 0 init
9364 13:19:18.494603 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9365 13:19:18.497696 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9366 13:19:18.501226 APU_MBOX 0x190000b0 = 0x10001
9367 13:19:18.504032 APU_MBOX 0x190001b0 = 0x10001
9368 13:19:18.507807 APU_MBOX 0x190005b0 = 0x10001
9369 13:19:18.510689 APU_MBOX 0x190006b0 = 0x10001
9370 13:19:18.517146 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9371 13:19:18.527020 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9372 13:19:18.539662 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9373 13:19:18.546348 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9374 13:19:18.558004 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9375 13:19:18.567121 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9376 13:19:18.570350 CPU_CLUSTER: 0 init finished in 81 msecs
9377 13:19:18.573584 Devices initialized
9378 13:19:18.576753 Show all devs... After init.
9379 13:19:18.576820 Root Device: enabled 1
9380 13:19:18.580436 CPU_CLUSTER: 0: enabled 1
9381 13:19:18.583438 CPU: 00: enabled 1
9382 13:19:18.586379 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9383 13:19:18.589999 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9384 13:19:18.593547 ELOG: NV offset 0x57f000 size 0x1000
9385 13:19:18.600386 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9386 13:19:18.606956 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9387 13:19:18.610248 ELOG: Event(17) added with size 13 at 2024-07-18 13:19:18 UTC
9388 13:19:18.616568 out: cmd=0x121: 03 db 21 01 00 00 00 00
9389 13:19:18.619455 in-header: 03 5f 00 00 2c 00 00 00
9390 13:19:18.629930 in-data: de 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9391 13:19:18.636565 ELOG: Event(A1) added with size 10 at 2024-07-18 13:19:18 UTC
9392 13:19:18.643068 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9393 13:19:18.649565 ELOG: Event(A0) added with size 9 at 2024-07-18 13:19:18 UTC
9394 13:19:18.652795 elog_add_boot_reason: Logged dev mode boot
9395 13:19:18.659253 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9396 13:19:18.659325 Finalize devices...
9397 13:19:18.662522 Devices finalized
9398 13:19:18.665826 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9399 13:19:18.668969 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9400 13:19:18.672800 in-header: 03 07 00 00 08 00 00 00
9401 13:19:18.676027 in-data: aa e4 47 04 13 02 00 00
9402 13:19:18.679356 Chrome EC: UHEPI supported
9403 13:19:18.685966 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9404 13:19:18.689115 in-header: 03 a9 00 00 08 00 00 00
9405 13:19:18.692473 in-data: 84 60 60 08 00 00 00 00
9406 13:19:18.699047 ELOG: Event(91) added with size 10 at 2024-07-18 13:19:18 UTC
9407 13:19:18.702393 Chrome EC: clear events_b mask to 0x0000000020004000
9408 13:19:18.708914 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9409 13:19:18.712657 in-header: 03 fd 00 00 00 00 00 00
9410 13:19:18.712739 in-data:
9411 13:19:18.719249 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9412 13:19:18.723139 Writing coreboot table at 0xffe64000
9413 13:19:18.726222 0. 000000000010a000-0000000000113fff: RAMSTAGE
9414 13:19:18.729215 1. 0000000040000000-00000000400fffff: RAM
9415 13:19:18.735978 2. 0000000040100000-000000004032afff: RAMSTAGE
9416 13:19:18.739077 3. 000000004032b000-00000000545fffff: RAM
9417 13:19:18.742314 4. 0000000054600000-000000005465ffff: BL31
9418 13:19:18.745597 5. 0000000054660000-00000000ffe63fff: RAM
9419 13:19:18.752226 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9420 13:19:18.755511 7. 0000000100000000-000000023fffffff: RAM
9421 13:19:18.759407 Passing 5 GPIOs to payload:
9422 13:19:18.762509 NAME | PORT | POLARITY | VALUE
9423 13:19:18.765832 EC in RW | 0x000000aa | low | undefined
9424 13:19:18.772442 EC interrupt | 0x00000005 | low | undefined
9425 13:19:18.775520 TPM interrupt | 0x000000ab | high | undefined
9426 13:19:18.782051 SD card detect | 0x00000011 | high | undefined
9427 13:19:18.785301 speaker enable | 0x00000093 | high | undefined
9428 13:19:18.788614 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9429 13:19:18.792482 in-header: 03 f9 00 00 02 00 00 00
9430 13:19:18.795684 in-data: 02 00
9431 13:19:18.795751 ADC[4]: Raw value=897040 ID=7
9432 13:19:18.799008 ADC[3]: Raw value=213070 ID=1
9433 13:19:18.802298 RAM Code: 0x71
9434 13:19:18.802374 ADC[6]: Raw value=75092 ID=0
9435 13:19:18.805574 ADC[5]: Raw value=212330 ID=1
9436 13:19:18.808715 SKU Code: 0x1
9437 13:19:18.811873 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b289
9438 13:19:18.815578 coreboot table: 964 bytes.
9439 13:19:18.818535 IMD ROOT 0. 0xfffff000 0x00001000
9440 13:19:18.822036 IMD SMALL 1. 0xffffe000 0x00001000
9441 13:19:18.825517 RO MCACHE 2. 0xffffc000 0x00001104
9442 13:19:18.828278 CONSOLE 3. 0xfff7c000 0x00080000
9443 13:19:18.831875 FMAP 4. 0xfff7b000 0x00000452
9444 13:19:18.834790 TIME STAMP 5. 0xfff7a000 0x00000910
9445 13:19:18.837997 VBOOT WORK 6. 0xfff66000 0x00014000
9446 13:19:18.841549 RAMOOPS 7. 0xffe66000 0x00100000
9447 13:19:18.844560 COREBOOT 8. 0xffe64000 0x00002000
9448 13:19:18.848015 IMD small region:
9449 13:19:18.851473 IMD ROOT 0. 0xffffec00 0x00000400
9450 13:19:18.854892 VPD 1. 0xffffeb80 0x0000006c
9451 13:19:18.857967 MMC STATUS 2. 0xffffeb60 0x00000004
9452 13:19:18.861299 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9453 13:19:18.867644 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9454 13:19:18.909010 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9455 13:19:18.912264 Checking segment from ROM address 0x40100000
9456 13:19:18.918824 Checking segment from ROM address 0x4010001c
9457 13:19:18.922194 Loading segment from ROM address 0x40100000
9458 13:19:18.922263 code (compression=0)
9459 13:19:18.931773 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9460 13:19:18.938521 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9461 13:19:18.938625 it's not compressed!
9462 13:19:18.945134 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9463 13:19:18.951355 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9464 13:19:18.969492 Loading segment from ROM address 0x4010001c
9465 13:19:18.969584 Entry Point 0x80000000
9466 13:19:18.972723 Loaded segments
9467 13:19:18.975966 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9468 13:19:18.982287 Jumping to boot code at 0x80000000(0xffe64000)
9469 13:19:18.989154 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9470 13:19:18.995869 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9471 13:19:19.003607 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9472 13:19:19.006841 Checking segment from ROM address 0x40100000
9473 13:19:19.010278 Checking segment from ROM address 0x4010001c
9474 13:19:19.016749 Loading segment from ROM address 0x40100000
9475 13:19:19.016820 code (compression=1)
9476 13:19:19.023384 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9477 13:19:19.033149 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9478 13:19:19.033221 using LZMA
9479 13:19:19.042156 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9480 13:19:19.048763 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9481 13:19:19.052065 Loading segment from ROM address 0x4010001c
9482 13:19:19.052141 Entry Point 0x54601000
9483 13:19:19.055073 Loaded segments
9484 13:19:19.058380 NOTICE: MT8192 bl31_setup
9485 13:19:19.065458 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9486 13:19:19.069032 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9487 13:19:19.072042 WARNING: region 0:
9488 13:19:19.075529 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 13:19:19.075626 WARNING: region 1:
9490 13:19:19.082614 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9491 13:19:19.085653 WARNING: region 2:
9492 13:19:19.088955 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9493 13:19:19.092396 WARNING: region 3:
9494 13:19:19.095606 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9495 13:19:19.098968 WARNING: region 4:
9496 13:19:19.105531 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9497 13:19:19.105636 WARNING: region 5:
9498 13:19:19.108707 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 13:19:19.111977 WARNING: region 6:
9500 13:19:19.115170 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9501 13:19:19.118462 WARNING: region 7:
9502 13:19:19.121711 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9503 13:19:19.128276 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9504 13:19:19.131587 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9505 13:19:19.138600 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9506 13:19:19.141653 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9507 13:19:19.144948 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9508 13:19:19.151533 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9509 13:19:19.154847 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9510 13:19:19.158088 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9511 13:19:19.165272 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9512 13:19:19.168256 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9513 13:19:19.174929 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9514 13:19:19.178183 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9515 13:19:19.181467 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9516 13:19:19.187977 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9517 13:19:19.191657 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9518 13:19:19.194754 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9519 13:19:19.201594 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9520 13:19:19.204762 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9521 13:19:19.210910 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9522 13:19:19.214563 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9523 13:19:19.217660 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9524 13:19:19.224642 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9525 13:19:19.227698 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9526 13:19:19.234267 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9527 13:19:19.237481 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9528 13:19:19.240765 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9529 13:19:19.247890 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9530 13:19:19.250914 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9531 13:19:19.257343 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9532 13:19:19.260555 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9533 13:19:19.264402 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9534 13:19:19.270903 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9535 13:19:19.274087 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9536 13:19:19.277327 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9537 13:19:19.283838 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9538 13:19:19.287225 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9539 13:19:19.291184 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9540 13:19:19.294480 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9541 13:19:19.297671 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9542 13:19:19.304148 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9543 13:19:19.307479 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9544 13:19:19.310750 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9545 13:19:19.314122 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9546 13:19:19.320723 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9547 13:19:19.323854 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9548 13:19:19.327627 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9549 13:19:19.334064 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9550 13:19:19.337086 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9551 13:19:19.340587 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9552 13:19:19.347157 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9553 13:19:19.350319 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9554 13:19:19.356958 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9555 13:19:19.360031 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9556 13:19:19.363392 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9557 13:19:19.370511 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9558 13:19:19.373764 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9559 13:19:19.380351 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9560 13:19:19.383539 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9561 13:19:19.390166 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9562 13:19:19.393513 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9563 13:19:19.400137 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9564 13:19:19.403487 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9565 13:19:19.406671 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9566 13:19:19.413125 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9567 13:19:19.416416 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9568 13:19:19.423001 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9569 13:19:19.426261 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9570 13:19:19.432968 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9571 13:19:19.436178 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9572 13:19:19.443293 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9573 13:19:19.446391 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9574 13:19:19.449975 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9575 13:19:19.456433 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9576 13:19:19.459597 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9577 13:19:19.466533 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9578 13:19:19.469593 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9579 13:19:19.475884 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9580 13:19:19.479149 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9581 13:19:19.485761 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9582 13:19:19.489527 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9583 13:19:19.492726 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9584 13:19:19.499342 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9585 13:19:19.502597 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9586 13:19:19.509148 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9587 13:19:19.512249 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9588 13:19:19.519173 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9589 13:19:19.522425 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9590 13:19:19.529055 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9591 13:19:19.532293 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9592 13:19:19.535583 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9593 13:19:19.542154 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9594 13:19:19.545450 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9595 13:19:19.552080 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9596 13:19:19.555416 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9597 13:19:19.561804 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9598 13:19:19.565432 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9599 13:19:19.568480 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9600 13:19:19.575515 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9601 13:19:19.578633 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9602 13:19:19.582091 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9603 13:19:19.584989 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9604 13:19:19.592293 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9605 13:19:19.595446 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9606 13:19:19.602066 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9607 13:19:19.605448 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9608 13:19:19.608895 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9609 13:19:19.615494 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9610 13:19:19.618146 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9611 13:19:19.625099 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9612 13:19:19.628476 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9613 13:19:19.631731 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9614 13:19:19.638433 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9615 13:19:19.641682 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9616 13:19:19.648001 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9617 13:19:19.651599 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9618 13:19:19.654480 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9619 13:19:19.660928 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9620 13:19:19.664248 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9621 13:19:19.668021 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9622 13:19:19.674356 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9623 13:19:19.677531 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9624 13:19:19.680809 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9625 13:19:19.684404 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9626 13:19:19.690592 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9627 13:19:19.694167 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9628 13:19:19.700688 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9629 13:19:19.703993 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9630 13:19:19.707341 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9631 13:19:19.713986 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9632 13:19:19.717273 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9633 13:19:19.723718 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9634 13:19:19.726888 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9635 13:19:19.730132 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9636 13:19:19.736720 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9637 13:19:19.740087 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9638 13:19:19.746723 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9639 13:19:19.750043 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9640 13:19:19.753354 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9641 13:19:19.760232 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9642 13:19:19.763436 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9643 13:19:19.769569 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9644 13:19:19.773326 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9645 13:19:19.776500 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9646 13:19:19.783023 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9647 13:19:19.786193 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9648 13:19:19.792918 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9649 13:19:19.796226 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9650 13:19:19.799447 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9651 13:19:19.806164 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9652 13:19:19.809532 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9653 13:19:19.816247 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9654 13:19:19.819406 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9655 13:19:19.822691 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9656 13:19:19.829087 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9657 13:19:19.832322 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9658 13:19:19.839010 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9659 13:19:19.842298 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9660 13:19:19.845730 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9661 13:19:19.852451 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9662 13:19:19.855640 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9663 13:19:19.861991 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9664 13:19:19.865804 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9665 13:19:19.869069 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9666 13:19:19.875450 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9667 13:19:19.879076 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9668 13:19:19.885212 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9669 13:19:19.888389 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9670 13:19:19.891838 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9671 13:19:19.898229 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9672 13:19:19.901584 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9673 13:19:19.908302 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9674 13:19:19.911487 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9675 13:19:19.915276 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9676 13:19:19.921802 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9677 13:19:19.924938 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9678 13:19:19.931229 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9679 13:19:19.934916 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9680 13:19:19.937988 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9681 13:19:19.944518 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9682 13:19:19.947842 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9683 13:19:19.954537 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9684 13:19:19.957813 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9685 13:19:19.961208 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9686 13:19:19.967659 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9687 13:19:19.970764 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9688 13:19:19.977310 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9689 13:19:19.981170 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9690 13:19:19.984398 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9691 13:19:19.990737 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9692 13:19:19.993817 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9693 13:19:20.000380 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9694 13:19:20.003944 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9695 13:19:20.010432 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9696 13:19:20.013679 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9697 13:19:20.016979 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9698 13:19:20.023548 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9699 13:19:20.026861 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9700 13:19:20.033767 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9701 13:19:20.036708 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9702 13:19:20.043106 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9703 13:19:20.046511 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9704 13:19:20.050125 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9705 13:19:20.056685 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9706 13:19:20.059920 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9707 13:19:20.066471 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9708 13:19:20.069697 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9709 13:19:20.076703 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9710 13:19:20.079837 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9711 13:19:20.082966 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9712 13:19:20.089685 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9713 13:19:20.092921 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9714 13:19:20.099506 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9715 13:19:20.102569 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9716 13:19:20.109471 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9717 13:19:20.112455 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9718 13:19:20.116293 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9719 13:19:20.122858 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9720 13:19:20.126056 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9721 13:19:20.132896 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9722 13:19:20.135991 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9723 13:19:20.139294 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9724 13:19:20.145919 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9725 13:19:20.149124 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9726 13:19:20.155293 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9727 13:19:20.158718 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9728 13:19:20.165277 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9729 13:19:20.168465 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9730 13:19:20.171805 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9731 13:19:20.179058 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9732 13:19:20.181803 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9733 13:19:20.185169 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9734 13:19:20.188997 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9735 13:19:20.194952 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9736 13:19:20.198765 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9737 13:19:20.202042 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9738 13:19:20.208436 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9739 13:19:20.211625 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9740 13:19:20.218279 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9741 13:19:20.221607 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9742 13:19:20.224861 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9743 13:19:20.231406 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9744 13:19:20.234801 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9745 13:19:20.238050 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9746 13:19:20.244705 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9747 13:19:20.247869 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9748 13:19:20.251183 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9749 13:19:20.258381 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9750 13:19:20.261388 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9751 13:19:20.268105 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9752 13:19:20.271301 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9753 13:19:20.274305 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9754 13:19:20.281351 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9755 13:19:20.284512 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9756 13:19:20.287967 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9757 13:19:20.294931 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9758 13:19:20.298157 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9759 13:19:20.304210 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9760 13:19:20.307356 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9761 13:19:20.310662 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9762 13:19:20.317682 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9763 13:19:20.320860 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9764 13:19:20.327137 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9765 13:19:20.330443 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9766 13:19:20.333729 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9767 13:19:20.340282 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9768 13:19:20.343613 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9769 13:19:20.346967 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9770 13:19:20.353298 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9771 13:19:20.356516 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9772 13:19:20.359903 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9773 13:19:20.363743 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9774 13:19:20.370063 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9775 13:19:20.373373 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9776 13:19:20.376504 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9777 13:19:20.379615 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9778 13:19:20.386498 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9779 13:19:20.390069 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9780 13:19:20.393450 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9781 13:19:20.396621 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9782 13:19:20.403047 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9783 13:19:20.406275 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9784 13:19:20.409459 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9785 13:19:20.416503 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9786 13:19:20.419776 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9787 13:19:20.426212 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9788 13:19:20.429358 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9789 13:19:20.436038 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9790 13:19:20.439406 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9791 13:19:20.442638 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9792 13:19:20.449258 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9793 13:19:20.452581 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9794 13:19:20.459536 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9795 13:19:20.462794 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9796 13:19:20.466221 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9797 13:19:20.472486 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9798 13:19:20.475554 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9799 13:19:20.482012 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9800 13:19:20.485250 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9801 13:19:20.488592 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9802 13:19:20.495641 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9803 13:19:20.498520 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9804 13:19:20.505382 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9805 13:19:20.508739 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9806 13:19:20.515345 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9807 13:19:20.518557 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9808 13:19:20.521642 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9809 13:19:20.528121 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9810 13:19:20.531931 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9811 13:19:20.538433 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9812 13:19:20.541544 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9813 13:19:20.547859 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9814 13:19:20.551080 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9815 13:19:20.554469 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9816 13:19:20.561493 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9817 13:19:20.564674 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9818 13:19:20.571193 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9819 13:19:20.574487 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9820 13:19:20.581327 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9821 13:19:20.584566 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9822 13:19:20.587720 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9823 13:19:20.594320 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9824 13:19:20.597606 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9825 13:19:20.604063 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9826 13:19:20.607690 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9827 13:19:20.610628 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9828 13:19:20.617341 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9829 13:19:20.620444 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9830 13:19:20.627504 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9831 13:19:20.630579 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9832 13:19:20.633855 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9833 13:19:20.640848 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9834 13:19:20.643472 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9835 13:19:20.650567 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9836 13:19:20.653704 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9837 13:19:20.660282 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9838 13:19:20.663494 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9839 13:19:20.666729 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9840 13:19:20.673191 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9841 13:19:20.676990 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9842 13:19:20.683428 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9843 13:19:20.686620 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9844 13:19:20.689898 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9845 13:19:20.696330 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9846 13:19:20.700355 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9847 13:19:20.706331 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9848 13:19:20.709676 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9849 13:19:20.716072 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9850 13:19:20.719713 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9851 13:19:20.722664 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9852 13:19:20.729531 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9853 13:19:20.732594 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9854 13:19:20.739428 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9855 13:19:20.742523 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9856 13:19:20.746204 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9857 13:19:20.752739 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9858 13:19:20.755942 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9859 13:19:20.762277 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9860 13:19:20.766051 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9861 13:19:20.772550 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9862 13:19:20.775794 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9863 13:19:20.782491 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9864 13:19:20.785762 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9865 13:19:20.789003 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9866 13:19:20.795994 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9867 13:19:20.799092 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9868 13:19:20.805477 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9869 13:19:20.808850 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9870 13:19:20.815388 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9871 13:19:20.818581 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9872 13:19:20.821872 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9873 13:19:20.828595 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9874 13:19:20.832278 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9875 13:19:20.838607 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9876 13:19:20.841964 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9877 13:19:20.848365 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9878 13:19:20.852092 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9879 13:19:20.858734 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9880 13:19:20.862018 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9881 13:19:20.865275 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9882 13:19:20.871948 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9883 13:19:20.875068 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9884 13:19:20.881546 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9885 13:19:20.884934 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9886 13:19:20.891406 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9887 13:19:20.895186 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9888 13:19:20.898255 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9889 13:19:20.905164 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9890 13:19:20.908204 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9891 13:19:20.914773 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9892 13:19:20.918191 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9893 13:19:20.924761 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9894 13:19:20.928010 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9895 13:19:20.934679 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9896 13:19:20.937893 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9897 13:19:20.940998 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9898 13:19:20.948097 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9899 13:19:20.951293 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9900 13:19:20.957891 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9901 13:19:20.960942 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9902 13:19:20.967828 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9903 13:19:20.970985 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9904 13:19:20.977490 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9905 13:19:20.981086 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9906 13:19:20.984173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9907 13:19:20.990647 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9908 13:19:20.993926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9909 13:19:21.000354 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9910 13:19:21.004434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9911 13:19:21.010788 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9912 13:19:21.013779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9913 13:19:21.020885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9914 13:19:21.024247 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9915 13:19:21.030132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9916 13:19:21.033480 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9917 13:19:21.040353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9918 13:19:21.043459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9919 13:19:21.050350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9920 13:19:21.053530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9921 13:19:21.060150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9922 13:19:21.063527 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9923 13:19:21.069992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9924 13:19:21.073634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9925 13:19:21.080195 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9926 13:19:21.083450 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9927 13:19:21.090122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9928 13:19:21.093148 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9929 13:19:21.099693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9930 13:19:21.102961 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9931 13:19:21.109612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9932 13:19:21.112820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9933 13:19:21.119974 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9934 13:19:21.122877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9935 13:19:21.129332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9936 13:19:21.132626 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9937 13:19:21.136007 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9938 13:19:21.139208 INFO: [APUAPC] vio 0
9939 13:19:21.145990 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9940 13:19:21.149098 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9941 13:19:21.152752 INFO: [APUAPC] D0_APC_0: 0x400510
9942 13:19:21.156003 INFO: [APUAPC] D0_APC_1: 0x0
9943 13:19:21.159396 INFO: [APUAPC] D0_APC_2: 0x1540
9944 13:19:21.162578 INFO: [APUAPC] D0_APC_3: 0x0
9945 13:19:21.165806 INFO: [APUAPC] D1_APC_0: 0xffffffff
9946 13:19:21.169001 INFO: [APUAPC] D1_APC_1: 0xffffffff
9947 13:19:21.172743 INFO: [APUAPC] D1_APC_2: 0x3fffff
9948 13:19:21.176041 INFO: [APUAPC] D1_APC_3: 0x0
9949 13:19:21.179330 INFO: [APUAPC] D2_APC_0: 0xffffffff
9950 13:19:21.182541 INFO: [APUAPC] D2_APC_1: 0xffffffff
9951 13:19:21.185741 INFO: [APUAPC] D2_APC_2: 0x3fffff
9952 13:19:21.185817 INFO: [APUAPC] D2_APC_3: 0x0
9953 13:19:21.192321 INFO: [APUAPC] D3_APC_0: 0xffffffff
9954 13:19:21.195970 INFO: [APUAPC] D3_APC_1: 0xffffffff
9955 13:19:21.198990 INFO: [APUAPC] D3_APC_2: 0x3fffff
9956 13:19:21.199066 INFO: [APUAPC] D3_APC_3: 0x0
9957 13:19:21.202134 INFO: [APUAPC] D4_APC_0: 0xffffffff
9958 13:19:21.208641 INFO: [APUAPC] D4_APC_1: 0xffffffff
9959 13:19:21.211829 INFO: [APUAPC] D4_APC_2: 0x3fffff
9960 13:19:21.211911 INFO: [APUAPC] D4_APC_3: 0x0
9961 13:19:21.215156 INFO: [APUAPC] D5_APC_0: 0xffffffff
9962 13:19:21.218523 INFO: [APUAPC] D5_APC_1: 0xffffffff
9963 13:19:21.222472 INFO: [APUAPC] D5_APC_2: 0x3fffff
9964 13:19:21.225356 INFO: [APUAPC] D5_APC_3: 0x0
9965 13:19:21.228631 INFO: [APUAPC] D6_APC_0: 0xffffffff
9966 13:19:21.232215 INFO: [APUAPC] D6_APC_1: 0xffffffff
9967 13:19:21.235390 INFO: [APUAPC] D6_APC_2: 0x3fffff
9968 13:19:21.238763 INFO: [APUAPC] D6_APC_3: 0x0
9969 13:19:21.242077 INFO: [APUAPC] D7_APC_0: 0xffffffff
9970 13:19:21.245316 INFO: [APUAPC] D7_APC_1: 0xffffffff
9971 13:19:21.248591 INFO: [APUAPC] D7_APC_2: 0x3fffff
9972 13:19:21.251733 INFO: [APUAPC] D7_APC_3: 0x0
9973 13:19:21.254866 INFO: [APUAPC] D8_APC_0: 0xffffffff
9974 13:19:21.258451 INFO: [APUAPC] D8_APC_1: 0xffffffff
9975 13:19:21.261743 INFO: [APUAPC] D8_APC_2: 0x3fffff
9976 13:19:21.264981 INFO: [APUAPC] D8_APC_3: 0x0
9977 13:19:21.268283 INFO: [APUAPC] D9_APC_0: 0xffffffff
9978 13:19:21.271521 INFO: [APUAPC] D9_APC_1: 0xffffffff
9979 13:19:21.274766 INFO: [APUAPC] D9_APC_2: 0x3fffff
9980 13:19:21.277998 INFO: [APUAPC] D9_APC_3: 0x0
9981 13:19:21.281635 INFO: [APUAPC] D10_APC_0: 0xffffffff
9982 13:19:21.284553 INFO: [APUAPC] D10_APC_1: 0xffffffff
9983 13:19:21.288107 INFO: [APUAPC] D10_APC_2: 0x3fffff
9984 13:19:21.291283 INFO: [APUAPC] D10_APC_3: 0x0
9985 13:19:21.294497 INFO: [APUAPC] D11_APC_0: 0xffffffff
9986 13:19:21.297949 INFO: [APUAPC] D11_APC_1: 0xffffffff
9987 13:19:21.301054 INFO: [APUAPC] D11_APC_2: 0x3fffff
9988 13:19:21.304869 INFO: [APUAPC] D11_APC_3: 0x0
9989 13:19:21.307903 INFO: [APUAPC] D12_APC_0: 0xffffffff
9990 13:19:21.311139 INFO: [APUAPC] D12_APC_1: 0xffffffff
9991 13:19:21.314463 INFO: [APUAPC] D12_APC_2: 0x3fffff
9992 13:19:21.317727 INFO: [APUAPC] D12_APC_3: 0x0
9993 13:19:21.321165 INFO: [APUAPC] D13_APC_0: 0xffffffff
9994 13:19:21.324422 INFO: [APUAPC] D13_APC_1: 0xffffffff
9995 13:19:21.327551 INFO: [APUAPC] D13_APC_2: 0x3fffff
9996 13:19:21.330798 INFO: [APUAPC] D13_APC_3: 0x0
9997 13:19:21.334178 INFO: [APUAPC] D14_APC_0: 0xffffffff
9998 13:19:21.337857 INFO: [APUAPC] D14_APC_1: 0xffffffff
9999 13:19:21.340826 INFO: [APUAPC] D14_APC_2: 0x3fffff
10000 13:19:21.344054 INFO: [APUAPC] D14_APC_3: 0x0
10001 13:19:21.347331 INFO: [APUAPC] D15_APC_0: 0xffffffff
10002 13:19:21.350623 INFO: [APUAPC] D15_APC_1: 0xffffffff
10003 13:19:21.353918 INFO: [APUAPC] D15_APC_2: 0x3fffff
10004 13:19:21.357721 INFO: [APUAPC] D15_APC_3: 0x0
10005 13:19:21.360923 INFO: [APUAPC] APC_CON: 0x4
10006 13:19:21.363926 INFO: [NOCDAPC] D0_APC_0: 0x0
10007 13:19:21.367655 INFO: [NOCDAPC] D0_APC_1: 0x0
10008 13:19:21.370408 INFO: [NOCDAPC] D1_APC_0: 0x0
10009 13:19:21.373848 INFO: [NOCDAPC] D1_APC_1: 0xfff
10010 13:19:21.377651 INFO: [NOCDAPC] D2_APC_0: 0x0
10011 13:19:21.380341 INFO: [NOCDAPC] D2_APC_1: 0xfff
10012 13:19:21.380439 INFO: [NOCDAPC] D3_APC_0: 0x0
10013 13:19:21.384221 INFO: [NOCDAPC] D3_APC_1: 0xfff
10014 13:19:21.387445 INFO: [NOCDAPC] D4_APC_0: 0x0
10015 13:19:21.390609 INFO: [NOCDAPC] D4_APC_1: 0xfff
10016 13:19:21.393978 INFO: [NOCDAPC] D5_APC_0: 0x0
10017 13:19:21.397093 INFO: [NOCDAPC] D5_APC_1: 0xfff
10018 13:19:21.400655 INFO: [NOCDAPC] D6_APC_0: 0x0
10019 13:19:21.403875 INFO: [NOCDAPC] D6_APC_1: 0xfff
10020 13:19:21.407161 INFO: [NOCDAPC] D7_APC_0: 0x0
10021 13:19:21.410380 INFO: [NOCDAPC] D7_APC_1: 0xfff
10022 13:19:21.413994 INFO: [NOCDAPC] D8_APC_0: 0x0
10023 13:19:21.417153 INFO: [NOCDAPC] D8_APC_1: 0xfff
10024 13:19:21.417248 INFO: [NOCDAPC] D9_APC_0: 0x0
10025 13:19:21.420508 INFO: [NOCDAPC] D9_APC_1: 0xfff
10026 13:19:21.423864 INFO: [NOCDAPC] D10_APC_0: 0x0
10027 13:19:21.427032 INFO: [NOCDAPC] D10_APC_1: 0xfff
10028 13:19:21.430255 INFO: [NOCDAPC] D11_APC_0: 0x0
10029 13:19:21.433992 INFO: [NOCDAPC] D11_APC_1: 0xfff
10030 13:19:21.437363 INFO: [NOCDAPC] D12_APC_0: 0x0
10031 13:19:21.440022 INFO: [NOCDAPC] D12_APC_1: 0xfff
10032 13:19:21.443343 INFO: [NOCDAPC] D13_APC_0: 0x0
10033 13:19:21.446897 INFO: [NOCDAPC] D13_APC_1: 0xfff
10034 13:19:21.450241 INFO: [NOCDAPC] D14_APC_0: 0x0
10035 13:19:21.453514 INFO: [NOCDAPC] D14_APC_1: 0xfff
10036 13:19:21.456862 INFO: [NOCDAPC] D15_APC_0: 0x0
10037 13:19:21.460102 INFO: [NOCDAPC] D15_APC_1: 0xfff
10038 13:19:21.460196 INFO: [NOCDAPC] APC_CON: 0x4
10039 13:19:21.463454 INFO: [APUAPC] set_apusys_apc done
10040 13:19:21.466675 INFO: [DEVAPC] devapc_init done
10041 13:19:21.473509 INFO: GICv3 without legacy support detected.
10042 13:19:21.476719 INFO: ARM GICv3 driver initialized in EL3
10043 13:19:21.479986 INFO: Maximum SPI INTID supported: 639
10044 13:19:21.483919 INFO: BL31: Initializing runtime services
10045 13:19:21.490328 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10046 13:19:21.493601 INFO: SPM: enable CPC mode
10047 13:19:21.496720 INFO: mcdi ready for mcusys-off-idle and system suspend
10048 13:19:21.503172 INFO: BL31: Preparing for EL3 exit to normal world
10049 13:19:21.506317 INFO: Entry point address = 0x80000000
10050 13:19:21.506421 INFO: SPSR = 0x8
10051 13:19:21.513606
10052 13:19:21.513713
10053 13:19:21.513797
10054 13:19:21.516773 Starting depthcharge on Spherion...
10055 13:19:21.516870
10056 13:19:21.516963 Wipe memory regions:
10057 13:19:21.517044
10058 13:19:21.517924 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10059 13:19:21.518052 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10060 13:19:21.518161 Setting prompt string to ['asurada:']
10061 13:19:21.518230 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10062 13:19:21.520402 [0x00000040000000, 0x00000054600000)
10063 13:19:21.642394
10064 13:19:21.642531 [0x00000054660000, 0x00000080000000)
10065 13:19:21.903503
10066 13:19:21.903638 [0x000000821a7280, 0x000000ffe64000)
10067 13:19:22.648286
10068 13:19:22.648427 [0x00000100000000, 0x00000240000000)
10069 13:19:24.538415
10070 13:19:24.541815 Initializing XHCI USB controller at 0x11200000.
10071 13:19:25.580193
10072 13:19:25.583362 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10073 13:19:25.583439
10074 13:19:25.583561
10075 13:19:25.583870 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10076 13:19:25.583959 Sending line: 'tftpboot 192.168.201.1 14879051/tftp-deploy-779tez8t/kernel/image.itb 14879051/tftp-deploy-779tez8t/kernel/cmdline '
10078 13:19:25.684457 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10079 13:19:25.684550 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10080 13:19:25.688830 asurada: tftpboot 192.168.201.1 14879051/tftp-deploy-779tez8t/kernel/image.itp-deploy-779tez8t/kernel/cmdline
10081 13:19:25.688908
10082 13:19:25.688967 Waiting for link
10083 13:19:25.847247
10084 13:19:25.847368 R8152: Initializing
10085 13:19:25.847429
10086 13:19:25.850723 Version 6 (ocp_data = 5c30)
10087 13:19:25.850837
10088 13:19:25.853597 R8152: Done initializing
10089 13:19:25.853672
10090 13:19:25.853731 Adding net device
10091 13:19:27.885438
10092 13:19:27.885589 done.
10093 13:19:27.885662
10094 13:19:27.885718 MAC: 00:24:32:30:78:ff
10095 13:19:27.885787
10096 13:19:27.888638 Sending DHCP discover... done.
10097 13:19:27.888731
10098 13:19:30.971134 Waiting for reply... done.
10099 13:19:30.971264
10100 13:19:30.971324 Sending DHCP request... done.
10101 13:19:30.974179
10102 13:19:30.974303 Waiting for reply... done.
10103 13:19:30.974378
10104 13:19:30.977399 My ip is 192.168.201.21
10105 13:19:30.977524
10106 13:19:30.980996 The DHCP server ip is 192.168.201.1
10107 13:19:30.981086
10108 13:19:30.984371 TFTP server IP predefined by user: 192.168.201.1
10109 13:19:30.984447
10110 13:19:30.990933 Bootfile predefined by user: 14879051/tftp-deploy-779tez8t/kernel/image.itb
10111 13:19:30.991009
10112 13:19:30.994392 Sending tftp read request... done.
10113 13:19:30.994503
10114 13:19:30.997286 Waiting for the transfer...
10115 13:19:30.997398
10116 13:19:31.517886 00000000 ################################################################
10117 13:19:31.518011
10118 13:19:32.036549 00080000 ################################################################
10119 13:19:32.036666
10120 13:19:32.583264 00100000 ################################################################
10121 13:19:32.583381
10122 13:19:33.105223 00180000 ################################################################
10123 13:19:33.105371
10124 13:19:33.636008 00200000 ################################################################
10125 13:19:33.636145
10126 13:19:34.187343 00280000 ################################################################
10127 13:19:34.187470
10128 13:19:34.729478 00300000 ################################################################
10129 13:19:34.729590
10130 13:19:35.272128 00380000 ################################################################
10131 13:19:35.272253
10132 13:19:35.827036 00400000 ################################################################
10133 13:19:35.827194
10134 13:19:36.376977 00480000 ################################################################
10135 13:19:36.377093
10136 13:19:36.905690 00500000 ################################################################
10137 13:19:36.905829
10138 13:19:37.446052 00580000 ################################################################
10139 13:19:37.446223
10140 13:19:37.977240 00600000 ################################################################
10141 13:19:37.977377
10142 13:19:38.505071 00680000 ################################################################
10143 13:19:38.505185
10144 13:19:39.031345 00700000 ################################################################
10145 13:19:39.031463
10146 13:19:39.569929 00780000 ################################################################
10147 13:19:39.570040
10148 13:19:40.114362 00800000 ################################################################
10149 13:19:40.114477
10150 13:19:40.666439 00880000 ################################################################
10151 13:19:40.666556
10152 13:19:41.226809 00900000 ################################################################
10153 13:19:41.226920
10154 13:19:41.789807 00980000 ################################################################
10155 13:19:41.789918
10156 13:19:42.317845 00a00000 ################################################################
10157 13:19:42.317963
10158 13:19:42.839406 00a80000 ################################################################
10159 13:19:42.839565
10160 13:19:43.370995 00b00000 ################################################################
10161 13:19:43.371128
10162 13:19:43.899321 00b80000 ################################################################
10163 13:19:43.899475
10164 13:19:44.426278 00c00000 ################################################################
10165 13:19:44.426407
10166 13:19:44.959657 00c80000 ################################################################
10167 13:19:44.959772
10168 13:19:45.485097 00d00000 ################################################################
10169 13:19:45.485240
10170 13:19:46.007322 00d80000 ################################################################
10171 13:19:46.007492
10172 13:19:46.535354 00e00000 ################################################################
10173 13:19:46.535498
10174 13:19:47.073120 00e80000 ################################################################
10175 13:19:47.073250
10176 13:19:47.605344 00f00000 ################################################################
10177 13:19:47.605472
10178 13:19:48.128810 00f80000 ################################################################
10179 13:19:48.128933
10180 13:19:48.656341 01000000 ################################################################
10181 13:19:48.656475
10182 13:19:49.201666 01080000 ################################################################
10183 13:19:49.201811
10184 13:19:49.749733 01100000 ################################################################
10185 13:19:49.749862
10186 13:19:50.294447 01180000 ################################################################
10187 13:19:50.294576
10188 13:19:50.834347 01200000 ################################################################
10189 13:19:50.834496
10190 13:19:51.381339 01280000 ################################################################
10191 13:19:51.381474
10192 13:19:51.917010 01300000 ################################################################
10193 13:19:51.917150
10194 13:19:52.451392 01380000 ################################################################
10195 13:19:52.451573
10196 13:19:52.988477 01400000 ################################################################
10197 13:19:52.988590
10198 13:19:53.524728 01480000 ################################################################
10199 13:19:53.524868
10200 13:19:54.056017 01500000 ################################################################
10201 13:19:54.056143
10202 13:19:54.589975 01580000 ################################################################
10203 13:19:54.590115
10204 13:19:55.117485 01600000 ################################################################
10205 13:19:55.117611
10206 13:19:55.647732 01680000 ################################################################
10207 13:19:55.647873
10208 13:19:56.190331 01700000 ################################################################
10209 13:19:56.190505
10210 13:19:56.732662 01780000 ################################################################
10211 13:19:56.732816
10212 13:19:57.278845 01800000 ################################################################
10213 13:19:57.278997
10214 13:19:57.825034 01880000 ################################################################
10215 13:19:57.825185
10216 13:19:58.360754 01900000 ################################################################
10217 13:19:58.360920
10218 13:19:58.892325 01980000 ################################################################
10219 13:19:58.892491
10220 13:19:59.413050 01a00000 ################################################################
10221 13:19:59.413166
10222 13:19:59.937745 01a80000 ################################################################
10223 13:19:59.937865
10224 13:20:00.480726 01b00000 ################################################################
10225 13:20:00.480868
10226 13:20:01.023848 01b80000 ################################################################
10227 13:20:01.023985
10228 13:20:01.584557 01c00000 ################################################################
10229 13:20:01.584695
10230 13:20:02.139429 01c80000 ################################################################
10231 13:20:02.139543
10232 13:20:02.690821 01d00000 ################################################################
10233 13:20:02.690961
10234 13:20:03.246409 01d80000 ################################################################
10235 13:20:03.246535
10236 13:20:03.793468 01e00000 ################################################################
10237 13:20:03.793580
10238 13:20:04.334849 01e80000 ################################################################
10239 13:20:04.334995
10240 13:20:04.871781 01f00000 ################################################################
10241 13:20:04.871899
10242 13:20:05.408862 01f80000 ################################################################
10243 13:20:05.409002
10244 13:20:05.952255 02000000 ################################################################
10245 13:20:05.952400
10246 13:20:06.497308 02080000 ################################################################
10247 13:20:06.497424
10248 13:20:07.054739 02100000 ################################################################
10249 13:20:07.054869
10250 13:20:07.617687 02180000 ################################################################
10251 13:20:07.617840
10252 13:20:08.179702 02200000 ################################################################
10253 13:20:08.179815
10254 13:20:08.724383 02280000 ################################################################
10255 13:20:08.724534
10256 13:20:09.277274 02300000 ################################################################
10257 13:20:09.277415
10258 13:20:09.814704 02380000 ################################################################
10259 13:20:09.814871
10260 13:20:10.356500 02400000 ################################################################
10261 13:20:10.356639
10262 13:20:10.892749 02480000 ################################################################
10263 13:20:10.892863
10264 13:20:11.431610 02500000 ################################################################
10265 13:20:11.431724
10266 13:20:11.967981 02580000 ################################################################
10267 13:20:11.968096
10268 13:20:12.524851 02600000 ################################################################
10269 13:20:12.525002
10270 13:20:13.096798 02680000 ################################################################
10271 13:20:13.096918
10272 13:20:13.660436 02700000 ################################################################
10273 13:20:13.660548
10274 13:20:14.231949 02780000 ################################################################
10275 13:20:14.232063
10276 13:20:14.788745 02800000 ################################################################
10277 13:20:14.788860
10278 13:20:15.329136 02880000 ################################################################
10279 13:20:15.329287
10280 13:20:15.874182 02900000 ################################################################
10281 13:20:15.874300
10282 13:20:16.398777 02980000 ################################################################
10283 13:20:16.398936
10284 13:20:16.944309 02a00000 ################################################################
10285 13:20:16.944451
10286 13:20:17.490330 02a80000 ################################################################
10287 13:20:17.490472
10288 13:20:18.017542 02b00000 ################################################################
10289 13:20:18.017658
10290 13:20:18.540160 02b80000 ################################################################
10291 13:20:18.540279
10292 13:20:19.064495 02c00000 ################################################################
10293 13:20:19.064630
10294 13:20:19.588166 02c80000 ################################################################
10295 13:20:19.588302
10296 13:20:20.117428 02d00000 ################################################################
10297 13:20:20.117544
10298 13:20:20.645958 02d80000 ################################################################
10299 13:20:20.646069
10300 13:20:21.177123 02e00000 ################################################################
10301 13:20:21.177237
10302 13:20:21.698462 02e80000 ################################################################
10303 13:20:21.698594
10304 13:20:22.221221 02f00000 ################################################################
10305 13:20:22.221339
10306 13:20:22.751156 02f80000 ################################################################
10307 13:20:22.751274
10308 13:20:23.280594 03000000 ################################################################
10309 13:20:23.280734
10310 13:20:23.806789 03080000 ################################################################
10311 13:20:23.806903
10312 13:20:24.349115 03100000 ################################################################
10313 13:20:24.349259
10314 13:20:24.887124 03180000 ################################################################
10315 13:20:24.887251
10316 13:20:25.448023 03200000 ################################################################
10317 13:20:25.448136
10318 13:20:25.992568 03280000 ################################################################
10319 13:20:25.992697
10320 13:20:26.535232 03300000 ################################################################
10321 13:20:26.535353
10322 13:20:26.909331 03380000 ############################################# done.
10323 13:20:26.909450
10324 13:20:26.912517 The bootfile was 54364438 bytes long.
10325 13:20:26.912602
10326 13:20:26.915673 Sending tftp read request... done.
10327 13:20:26.915779
10328 13:20:26.919063 Waiting for the transfer...
10329 13:20:26.919144
10330 13:20:26.922533 00000000 # done.
10331 13:20:26.922610
10332 13:20:26.928799 Command line loaded dynamically from TFTP file: 14879051/tftp-deploy-779tez8t/kernel/cmdline
10333 13:20:26.928879
10334 13:20:26.942295 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10335 13:20:26.942380
10336 13:20:26.942451 Loading FIT.
10337 13:20:26.942510
10338 13:20:26.945613 Image ramdisk-1 has 41200682 bytes.
10339 13:20:26.945683
10340 13:20:26.949329 Image fdt-1 has 47258 bytes.
10341 13:20:26.949398
10342 13:20:26.952522 Image kernel-1 has 13114469 bytes.
10343 13:20:26.952592
10344 13:20:26.962028 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10345 13:20:26.962162
10346 13:20:26.978673 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10347 13:20:26.978775
10348 13:20:26.985641 Choosing best match conf-1 for compat google,spherion-rev2.
10349 13:20:26.985717
10350 13:20:26.993339 Connected to device vid:did:rid of 1ae0:0028:00
10351 13:20:27.001144
10352 13:20:27.004917 tpm_get_response: command 0x17b, return code 0x0
10353 13:20:27.004992
10354 13:20:27.007909 ec_init: CrosEC protocol v3 supported (256, 248)
10355 13:20:27.011649
10356 13:20:27.014978 tpm_cleanup: add release locality here.
10357 13:20:27.015055
10358 13:20:27.015113 Shutting down all USB controllers.
10359 13:20:27.018927
10360 13:20:27.019003 Removing current net device
10361 13:20:27.019061
10362 13:20:27.025385 Exiting depthcharge with code 4 at timestamp: 94902895
10363 13:20:27.025460
10364 13:20:27.028505 LZMA decompressing kernel-1 to 0x821a6718
10365 13:20:27.028581
10366 13:20:27.032172 LZMA decompressing kernel-1 to 0x40000000
10367 13:20:28.647467
10368 13:20:28.647589 jumping to kernel
10369 13:20:28.648107 end: 2.2.4 bootloader-commands (duration 00:01:07) [common]
10370 13:20:28.648200 start: 2.2.5 auto-login-action (timeout 00:03:13) [common]
10371 13:20:28.648268 Setting prompt string to ['Linux version [0-9]']
10372 13:20:28.648330 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10373 13:20:28.648396 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10374 13:20:28.728154
10375 13:20:28.731477 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10376 13:20:28.734778 start: 2.2.5.1 login-action (timeout 00:03:13) [common]
10377 13:20:28.734871 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10378 13:20:28.734938 Setting prompt string to []
10379 13:20:28.735010 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10380 13:20:28.735081 Using line separator: #'\n'#
10381 13:20:28.735133 No login prompt set.
10382 13:20:28.735189 Parsing kernel messages
10383 13:20:28.735240 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10384 13:20:28.735334 [login-action] Waiting for messages, (timeout 00:03:13)
10385 13:20:28.735393 Waiting using forced prompt support (timeout 00:01:36)
10386 13:20:28.754158 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j272990-arm64-gcc-12-defconfig-arm64-chromebook-fgzcq) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024
10387 13:20:28.757665 [ 0.000000] random: crng init done
10388 13:20:28.760680 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10389 13:20:28.763854 [ 0.000000] efi: UEFI not found.
10390 13:20:28.774054 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10391 13:20:28.780478 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10392 13:20:28.790737 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10393 13:20:28.800326 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10394 13:20:28.806870 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10395 13:20:28.810090 [ 0.000000] printk: bootconsole [mtk8250] enabled
10396 13:20:28.819280 [ 0.000000] NUMA: No NUMA configuration found
10397 13:20:28.825678 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10398 13:20:28.875925 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10399 13:20:28.876072 [ 0.000000] Zone ranges:
10400 13:20:28.876159 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10401 13:20:28.876245 [ 0.000000] DMA32 empty
10402 13:20:28.876332 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10403 13:20:28.876411 [ 0.000000] Movable zone start for each node
10404 13:20:28.876493 [ 0.000000] Early memory node ranges
10405 13:20:28.876572 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10406 13:20:28.876682 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10407 13:20:28.876801 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10408 13:20:28.882187 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10409 13:20:28.888442 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10410 13:20:28.894996 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10411 13:20:28.952559 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10412 13:20:28.959046 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10413 13:20:28.965526 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10414 13:20:28.968794 [ 0.000000] psci: probing for conduit method from DT.
10415 13:20:28.975756 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10416 13:20:28.978865 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10417 13:20:28.985288 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10418 13:20:28.988876 [ 0.000000] psci: SMC Calling Convention v1.2
10419 13:20:28.995413 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10420 13:20:28.998871 [ 0.000000] Detected VIPT I-cache on CPU0
10421 13:20:29.005685 [ 0.000000] CPU features: detected: GIC system register CPU interface
10422 13:20:29.012296 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10423 13:20:29.018671 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10424 13:20:29.025273 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10425 13:20:29.031791 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10426 13:20:29.038738 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10427 13:20:29.045174 [ 0.000000] alternatives: applying boot alternatives
10428 13:20:29.048564 [ 0.000000] Fallback order for Node 0: 0
10429 13:20:29.054915 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10430 13:20:29.058165 [ 0.000000] Policy zone: Normal
10431 13:20:29.074933 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10432 13:20:29.084432 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10433 13:20:29.096169 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10434 13:20:29.106054 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10435 13:20:29.112536 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10436 13:20:29.116189 <6>[ 0.000000] software IO TLB: area num 8.
10437 13:20:29.173073 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10438 13:20:29.322167 <6>[ 0.000000] Memory: 7923824K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 428944K reserved, 32768K cma-reserved)
10439 13:20:29.329327 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10440 13:20:29.335441 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10441 13:20:29.338882 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10442 13:20:29.345731 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10443 13:20:29.352176 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10444 13:20:29.355692 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10445 13:20:29.365301 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10446 13:20:29.371911 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10447 13:20:29.378402 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10448 13:20:29.385495 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10449 13:20:29.388760 <6>[ 0.000000] GICv3: 608 SPIs implemented
10450 13:20:29.391939 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10451 13:20:29.398277 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10452 13:20:29.402056 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10453 13:20:29.408339 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10454 13:20:29.421454 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10455 13:20:29.435286 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10456 13:20:29.441153 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10457 13:20:29.448740 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10458 13:20:29.461843 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10459 13:20:29.468579 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10460 13:20:29.475213 <6>[ 0.009180] Console: colour dummy device 80x25
10461 13:20:29.485456 <6>[ 0.013941] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10462 13:20:29.491970 <6>[ 0.024448] pid_max: default: 32768 minimum: 301
10463 13:20:29.495287 <6>[ 0.029321] LSM: Security Framework initializing
10464 13:20:29.501731 <6>[ 0.034260] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10465 13:20:29.511950 <6>[ 0.042073] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10466 13:20:29.518621 <6>[ 0.051496] cblist_init_generic: Setting adjustable number of callback queues.
10467 13:20:29.525485 <6>[ 0.058983] cblist_init_generic: Setting shift to 3 and lim to 1.
10468 13:20:29.535332 <6>[ 0.065361] cblist_init_generic: Setting adjustable number of callback queues.
10469 13:20:29.541893 <6>[ 0.072788] cblist_init_generic: Setting shift to 3 and lim to 1.
10470 13:20:29.545073 <6>[ 0.079190] rcu: Hierarchical SRCU implementation.
10471 13:20:29.551874 <6>[ 0.084206] rcu: Max phase no-delay instances is 1000.
10472 13:20:29.558016 <6>[ 0.091259] EFI services will not be available.
10473 13:20:29.561288 <6>[ 0.096246] smp: Bringing up secondary CPUs ...
10474 13:20:29.569508 <6>[ 0.101297] Detected VIPT I-cache on CPU1
10475 13:20:29.576457 <6>[ 0.101366] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10476 13:20:29.582872 <6>[ 0.101397] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10477 13:20:29.586599 <6>[ 0.101742] Detected VIPT I-cache on CPU2
10478 13:20:29.592752 <6>[ 0.101794] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10479 13:20:29.603085 <6>[ 0.101812] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10480 13:20:29.606362 <6>[ 0.102073] Detected VIPT I-cache on CPU3
10481 13:20:29.612711 <6>[ 0.102121] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10482 13:20:29.619234 <6>[ 0.102136] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10483 13:20:29.622515 <6>[ 0.102441] CPU features: detected: Spectre-v4
10484 13:20:29.629314 <6>[ 0.102448] CPU features: detected: Spectre-BHB
10485 13:20:29.632509 <6>[ 0.102454] Detected PIPT I-cache on CPU4
10486 13:20:29.639032 <6>[ 0.102515] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10487 13:20:29.646133 <6>[ 0.102533] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10488 13:20:29.652499 <6>[ 0.102826] Detected PIPT I-cache on CPU5
10489 13:20:29.658959 <6>[ 0.102887] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10490 13:20:29.665763 <6>[ 0.102903] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10491 13:20:29.668948 <6>[ 0.103183] Detected PIPT I-cache on CPU6
10492 13:20:29.675962 <6>[ 0.103249] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10493 13:20:29.682291 <6>[ 0.103265] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10494 13:20:29.688819 <6>[ 0.103566] Detected PIPT I-cache on CPU7
10495 13:20:29.695385 <6>[ 0.103632] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10496 13:20:29.702232 <6>[ 0.103647] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10497 13:20:29.705848 <6>[ 0.103694] smp: Brought up 1 node, 8 CPUs
10498 13:20:29.711865 <6>[ 0.245005] SMP: Total of 8 processors activated.
10499 13:20:29.715479 <6>[ 0.249925] CPU features: detected: 32-bit EL0 Support
10500 13:20:29.725770 <6>[ 0.255288] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10501 13:20:29.732155 <6>[ 0.264088] CPU features: detected: Common not Private translations
10502 13:20:29.738363 <6>[ 0.270564] CPU features: detected: CRC32 instructions
10503 13:20:29.741643 <6>[ 0.275948] CPU features: detected: RCpc load-acquire (LDAPR)
10504 13:20:29.748283 <6>[ 0.281908] CPU features: detected: LSE atomic instructions
10505 13:20:29.754831 <6>[ 0.287690] CPU features: detected: Privileged Access Never
10506 13:20:29.761941 <6>[ 0.293506] CPU features: detected: RAS Extension Support
10507 13:20:29.768256 <6>[ 0.299149] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10508 13:20:29.771877 <6>[ 0.306369] CPU: All CPU(s) started at EL2
10509 13:20:29.777882 <6>[ 0.310686] alternatives: applying system-wide alternatives
10510 13:20:29.787551 <6>[ 0.321556] devtmpfs: initialized
10511 13:20:29.803147 <6>[ 0.330356] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10512 13:20:29.809631 <6>[ 0.340312] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10513 13:20:29.816605 <6>[ 0.348475] pinctrl core: initialized pinctrl subsystem
10514 13:20:29.819556 <6>[ 0.355200] DMI not present or invalid.
10515 13:20:29.826376 <6>[ 0.359608] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10516 13:20:29.835845 <6>[ 0.366492] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10517 13:20:29.842752 <6>[ 0.374075] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10518 13:20:29.852501 <6>[ 0.382293] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10519 13:20:29.855761 <6>[ 0.390531] audit: initializing netlink subsys (disabled)
10520 13:20:29.866245 <5>[ 0.396221] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10521 13:20:29.872769 <6>[ 0.396946] thermal_sys: Registered thermal governor 'step_wise'
10522 13:20:29.878877 <6>[ 0.404188] thermal_sys: Registered thermal governor 'power_allocator'
10523 13:20:29.882365 <6>[ 0.410440] cpuidle: using governor menu
10524 13:20:29.889373 <6>[ 0.421403] NET: Registered PF_QIPCRTR protocol family
10525 13:20:29.895534 <6>[ 0.426890] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10526 13:20:29.902576 <6>[ 0.433991] ASID allocator initialised with 32768 entries
10527 13:20:29.905847 <6>[ 0.440589] Serial: AMBA PL011 UART driver
10528 13:20:29.916433 <4>[ 0.450319] Trying to register duplicate clock ID: 134
10529 13:20:29.974599 <6>[ 0.511748] KASLR enabled
10530 13:20:29.988710 <6>[ 0.519387] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10531 13:20:29.995401 <6>[ 0.526400] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10532 13:20:30.002070 <6>[ 0.532887] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10533 13:20:30.008438 <6>[ 0.539893] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10534 13:20:30.014787 <6>[ 0.546383] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10535 13:20:30.021443 <6>[ 0.553389] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10536 13:20:30.028039 <6>[ 0.559875] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10537 13:20:30.035106 <6>[ 0.566878] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10538 13:20:30.038330 <6>[ 0.574402] ACPI: Interpreter disabled.
10539 13:20:30.046738 <6>[ 0.580838] iommu: Default domain type: Translated
10540 13:20:30.053299 <6>[ 0.585948] iommu: DMA domain TLB invalidation policy: strict mode
10541 13:20:30.057184 <5>[ 0.592601] SCSI subsystem initialized
10542 13:20:30.063163 <6>[ 0.596765] usbcore: registered new interface driver usbfs
10543 13:20:30.069970 <6>[ 0.602495] usbcore: registered new interface driver hub
10544 13:20:30.073101 <6>[ 0.608049] usbcore: registered new device driver usb
10545 13:20:30.080282 <6>[ 0.614150] pps_core: LinuxPPS API ver. 1 registered
10546 13:20:30.090393 <6>[ 0.619345] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10547 13:20:30.093527 <6>[ 0.628686] PTP clock support registered
10548 13:20:30.096745 <6>[ 0.632933] EDAC MC: Ver: 3.0.0
10549 13:20:30.104136 <6>[ 0.638096] FPGA manager framework
10550 13:20:30.107298 <6>[ 0.641779] Advanced Linux Sound Architecture Driver Initialized.
10551 13:20:30.111636 <6>[ 0.648571] vgaarb: loaded
10552 13:20:30.117980 <6>[ 0.651744] clocksource: Switched to clocksource arch_sys_counter
10553 13:20:30.124521 <5>[ 0.658192] VFS: Disk quotas dquot_6.6.0
10554 13:20:30.131357 <6>[ 0.662379] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10555 13:20:30.134438 <6>[ 0.669568] pnp: PnP ACPI: disabled
10556 13:20:30.142202 <6>[ 0.676264] NET: Registered PF_INET protocol family
10557 13:20:30.152312 <6>[ 0.681853] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10558 13:20:30.163720 <6>[ 0.694162] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10559 13:20:30.173438 <6>[ 0.702979] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10560 13:20:30.180152 <6>[ 0.710949] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10561 13:20:30.189890 <6>[ 0.719645] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10562 13:20:30.196412 <6>[ 0.729395] TCP: Hash tables configured (established 65536 bind 65536)
10563 13:20:30.203168 <6>[ 0.736262] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10564 13:20:30.213080 <6>[ 0.743464] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10565 13:20:30.219503 <6>[ 0.751164] NET: Registered PF_UNIX/PF_LOCAL protocol family
10566 13:20:30.223119 <6>[ 0.757318] RPC: Registered named UNIX socket transport module.
10567 13:20:30.229912 <6>[ 0.763470] RPC: Registered udp transport module.
10568 13:20:30.233087 <6>[ 0.768401] RPC: Registered tcp transport module.
10569 13:20:30.242877 <6>[ 0.773335] RPC: Registered tcp NFSv4.1 backchannel transport module.
10570 13:20:30.245999 <6>[ 0.780003] PCI: CLS 0 bytes, default 64
10571 13:20:30.249165 <6>[ 0.784262] Unpacking initramfs...
10572 13:20:30.265800 <6>[ 0.796265] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10573 13:20:30.275496 <6>[ 0.804902] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10574 13:20:30.278778 <6>[ 0.813742] kvm [1]: IPA Size Limit: 40 bits
10575 13:20:30.285383 <6>[ 0.818266] kvm [1]: GICv3: no GICV resource entry
10576 13:20:30.288599 <6>[ 0.823289] kvm [1]: disabling GICv2 emulation
10577 13:20:30.295275 <6>[ 0.827971] kvm [1]: GIC system register CPU interface enabled
10578 13:20:30.301796 <6>[ 0.835798] kvm [1]: vgic interrupt IRQ18
10579 13:20:30.305067 <6>[ 0.840175] kvm [1]: VHE mode initialized successfully
10580 13:20:30.312466 <5>[ 0.846604] Initialise system trusted keyrings
10581 13:20:30.318938 <6>[ 0.851363] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10582 13:20:30.327244 <6>[ 0.861303] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10583 13:20:30.334001 <5>[ 0.867685] NFS: Registering the id_resolver key type
10584 13:20:30.337595 <5>[ 0.872998] Key type id_resolver registered
10585 13:20:30.343796 <5>[ 0.877412] Key type id_legacy registered
10586 13:20:30.350276 <6>[ 0.881693] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10587 13:20:30.357351 <6>[ 0.888616] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10588 13:20:30.363687 <6>[ 0.896320] 9p: Installing v9fs 9p2000 file system support
10589 13:20:30.401238 <5>[ 0.935028] Key type asymmetric registered
10590 13:20:30.404476 <5>[ 0.939360] Asymmetric key parser 'x509' registered
10591 13:20:30.414298 <6>[ 0.944503] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10592 13:20:30.417287 <6>[ 0.952129] io scheduler mq-deadline registered
10593 13:20:30.421177 <6>[ 0.956889] io scheduler kyber registered
10594 13:20:30.440055 <6>[ 0.974082] EINJ: ACPI disabled.
10595 13:20:30.473333 <4>[ 1.000410] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10596 13:20:30.482752 <4>[ 1.011031] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10597 13:20:30.497711 <6>[ 1.032023] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10598 13:20:30.505925 <6>[ 1.040111] printk: console [ttyS0] disabled
10599 13:20:30.534050 <6>[ 1.064749] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10600 13:20:30.540461 <6>[ 1.074227] printk: console [ttyS0] enabled
10601 13:20:30.544300 <6>[ 1.074227] printk: console [ttyS0] enabled
10602 13:20:30.550781 <6>[ 1.083123] printk: bootconsole [mtk8250] disabled
10603 13:20:30.554121 <6>[ 1.083123] printk: bootconsole [mtk8250] disabled
10604 13:20:30.560613 <6>[ 1.094352] SuperH (H)SCI(F) driver initialized
10605 13:20:30.563797 <6>[ 1.099632] msm_serial: driver initialized
10606 13:20:30.577961 <6>[ 1.108656] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10607 13:20:30.588271 <6>[ 1.117202] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10608 13:20:30.594729 <6>[ 1.125743] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10609 13:20:30.604441 <6>[ 1.134370] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10610 13:20:30.614002 <6>[ 1.143088] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10611 13:20:30.621151 <6>[ 1.151803] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10612 13:20:30.630656 <6>[ 1.160343] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10613 13:20:30.637643 <6>[ 1.169159] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10614 13:20:30.647440 <6>[ 1.177702] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10615 13:20:30.659082 <6>[ 1.193287] loop: module loaded
10616 13:20:30.666184 <6>[ 1.199313] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10617 13:20:30.688711 <4>[ 1.222667] mtk-pmic-keys: Failed to locate of_node [id: -1]
10618 13:20:30.695280 <6>[ 1.229545] megasas: 07.719.03.00-rc1
10619 13:20:30.704902 <6>[ 1.239061] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10620 13:20:30.713013 <6>[ 1.247132] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10621 13:20:30.729951 <6>[ 1.263938] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10622 13:20:30.787035 <6>[ 1.314068] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10623 13:20:31.995677 <6>[ 2.529854] Freeing initrd memory: 40232K
10624 13:20:32.007714 <6>[ 2.541689] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10625 13:20:32.018649 <6>[ 2.552782] tun: Universal TUN/TAP device driver, 1.6
10626 13:20:32.021723 <6>[ 2.558863] thunder_xcv, ver 1.0
10627 13:20:32.025391 <6>[ 2.562369] thunder_bgx, ver 1.0
10628 13:20:32.028410 <6>[ 2.565865] nicpf, ver 1.0
10629 13:20:32.039441 <6>[ 2.569893] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10630 13:20:32.042572 <6>[ 2.577369] hns3: Copyright (c) 2017 Huawei Corporation.
10631 13:20:32.048981 <6>[ 2.582958] hclge is initializing
10632 13:20:32.052265 <6>[ 2.586541] e1000: Intel(R) PRO/1000 Network Driver
10633 13:20:32.058709 <6>[ 2.591670] e1000: Copyright (c) 1999-2006 Intel Corporation.
10634 13:20:32.062442 <6>[ 2.597683] e1000e: Intel(R) PRO/1000 Network Driver
10635 13:20:32.068893 <6>[ 2.602898] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10636 13:20:32.075585 <6>[ 2.609086] igb: Intel(R) Gigabit Ethernet Network Driver
10637 13:20:32.082021 <6>[ 2.614737] igb: Copyright (c) 2007-2014 Intel Corporation.
10638 13:20:32.088953 <6>[ 2.620572] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10639 13:20:32.095076 <6>[ 2.627089] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10640 13:20:32.098709 <6>[ 2.633551] sky2: driver version 1.30
10641 13:20:32.105373 <6>[ 2.638477] usbcore: registered new device driver r8152-cfgselector
10642 13:20:32.111802 <6>[ 2.645012] usbcore: registered new interface driver r8152
10643 13:20:32.118790 <6>[ 2.650835] VFIO - User Level meta-driver version: 0.3
10644 13:20:32.125168 <6>[ 2.659082] usbcore: registered new interface driver usb-storage
10645 13:20:32.131714 <6>[ 2.665534] usbcore: registered new device driver onboard-usb-hub
10646 13:20:32.140714 <6>[ 2.674681] mt6397-rtc mt6359-rtc: registered as rtc0
10647 13:20:32.150463 <6>[ 2.680148] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-18T13:20:32 UTC (1721308832)
10648 13:20:32.153931 <6>[ 2.689715] i2c_dev: i2c /dev entries driver
10649 13:20:32.167353 <4>[ 2.701706] cpu cpu0: supply cpu not found, using dummy regulator
10650 13:20:32.174381 <4>[ 2.708135] cpu cpu1: supply cpu not found, using dummy regulator
10651 13:20:32.180693 <4>[ 2.714540] cpu cpu2: supply cpu not found, using dummy regulator
10652 13:20:32.187146 <4>[ 2.720969] cpu cpu3: supply cpu not found, using dummy regulator
10653 13:20:32.194018 <4>[ 2.727365] cpu cpu4: supply cpu not found, using dummy regulator
10654 13:20:32.200964 <4>[ 2.733760] cpu cpu5: supply cpu not found, using dummy regulator
10655 13:20:32.207347 <4>[ 2.740156] cpu cpu6: supply cpu not found, using dummy regulator
10656 13:20:32.213793 <4>[ 2.746554] cpu cpu7: supply cpu not found, using dummy regulator
10657 13:20:32.233183 <6>[ 2.767200] cpu cpu0: EM: created perf domain
10658 13:20:32.236347 <6>[ 2.772117] cpu cpu4: EM: created perf domain
10659 13:20:32.243478 <6>[ 2.777731] sdhci: Secure Digital Host Controller Interface driver
10660 13:20:32.249988 <6>[ 2.784163] sdhci: Copyright(c) Pierre Ossman
10661 13:20:32.256982 <6>[ 2.789117] Synopsys Designware Multimedia Card Interface Driver
10662 13:20:32.263207 <6>[ 2.795744] sdhci-pltfm: SDHCI platform and OF driver helper
10663 13:20:32.266785 <6>[ 2.795790] mmc0: CQHCI version 5.10
10664 13:20:32.273183 <6>[ 2.805983] ledtrig-cpu: registered to indicate activity on CPUs
10665 13:20:32.280062 <6>[ 2.812990] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10666 13:20:32.286686 <6>[ 2.820048] usbcore: registered new interface driver usbhid
10667 13:20:32.289775 <6>[ 2.825871] usbhid: USB HID core driver
10668 13:20:32.296212 <6>[ 2.830080] spi_master spi0: will run message pump with realtime priority
10669 13:20:32.345265 <6>[ 2.873120] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10670 13:20:32.365622 <6>[ 2.889391] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10671 13:20:32.368866 <6>[ 2.902440] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15814
10672 13:20:32.375962 <6>[ 2.904575] cros-ec-spi spi0.0: Chrome EC device registered
10673 13:20:32.379114 <6>[ 2.914866] mmc0: Command Queue Engine enabled
10674 13:20:32.385527 <6>[ 2.919600] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10675 13:20:32.393357 <6>[ 2.927449] mmcblk0: mmc0:0001 DA4128 116 GiB
10676 13:20:32.402998 <6>[ 2.927566] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10677 13:20:32.409869 <6>[ 2.936280] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10678 13:20:32.412874 <6>[ 2.942619] NET: Registered PF_PACKET protocol family
10679 13:20:32.419796 <6>[ 2.948796] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10680 13:20:32.422945 <6>[ 2.952783] 9pnet: Installing 9P2000 support
10681 13:20:32.429908 <6>[ 2.958604] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10682 13:20:32.433140 <5>[ 2.962479] Key type dns_resolver registered
10683 13:20:32.440059 <6>[ 2.968357] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10684 13:20:32.442832 <6>[ 2.972801] registered taskstats version 1
10685 13:20:32.449715 <5>[ 2.983086] Loading compiled-in X.509 certificates
10686 13:20:32.477637 <4>[ 3.005150] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10687 13:20:32.487162 <4>[ 3.015972] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10688 13:20:32.501662 <6>[ 3.036183] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10689 13:20:32.509186 <6>[ 3.043100] xhci-mtk 11200000.usb: xHCI Host Controller
10690 13:20:32.515355 <6>[ 3.048632] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10691 13:20:32.525266 <6>[ 3.056540] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10692 13:20:32.532271 <6>[ 3.065983] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10693 13:20:32.538775 <6>[ 3.072174] xhci-mtk 11200000.usb: xHCI Host Controller
10694 13:20:32.545256 <6>[ 3.077665] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10695 13:20:32.552190 <6>[ 3.085325] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10696 13:20:32.559261 <6>[ 3.093104] hub 1-0:1.0: USB hub found
10697 13:20:32.562483 <6>[ 3.097119] hub 1-0:1.0: 1 port detected
10698 13:20:32.571924 <6>[ 3.101406] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10699 13:20:32.575290 <6>[ 3.110098] hub 2-0:1.0: USB hub found
10700 13:20:32.578428 <6>[ 3.114121] hub 2-0:1.0: 1 port detected
10701 13:20:32.586819 <6>[ 3.121286] mtk-msdc 11f70000.mmc: Got CD GPIO
10702 13:20:32.600914 <6>[ 3.132054] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10703 13:20:32.611409 <6>[ 3.140442] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10704 13:20:32.617695 <6>[ 3.148785] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10705 13:20:32.627704 <6>[ 3.157124] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10706 13:20:32.634272 <6>[ 3.165466] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10707 13:20:32.644291 <6>[ 3.173804] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10708 13:20:32.650927 <6>[ 3.182143] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10709 13:20:32.660422 <6>[ 3.190482] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10710 13:20:32.666996 <6>[ 3.198824] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10711 13:20:32.676875 <6>[ 3.207163] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10712 13:20:32.683899 <6>[ 3.215507] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10713 13:20:32.693724 <6>[ 3.223855] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10714 13:20:32.700491 <6>[ 3.232193] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10715 13:20:32.709829 <6>[ 3.240531] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10716 13:20:32.716419 <6>[ 3.248876] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10717 13:20:32.723445 <6>[ 3.257586] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10718 13:20:32.730623 <6>[ 3.264620] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10719 13:20:32.737123 <6>[ 3.271375] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10720 13:20:32.747412 <6>[ 3.278173] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10721 13:20:32.753554 <6>[ 3.285108] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10722 13:20:32.760219 <6>[ 3.291983] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10723 13:20:32.770553 <6>[ 3.301118] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10724 13:20:32.780142 <6>[ 3.310242] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10725 13:20:32.790477 <6>[ 3.319536] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10726 13:20:32.799800 <6>[ 3.329004] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10727 13:20:32.809992 <6>[ 3.338472] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10728 13:20:32.816430 <6>[ 3.347592] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10729 13:20:32.826262 <6>[ 3.357059] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10730 13:20:32.836493 <6>[ 3.366178] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10731 13:20:32.846135 <6>[ 3.375473] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10732 13:20:32.856347 <6>[ 3.385634] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10733 13:20:32.866688 <6>[ 3.397366] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10734 13:20:32.993078 <6>[ 3.524020] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10735 13:20:33.147962 <6>[ 3.682033] hub 1-1:1.0: USB hub found
10736 13:20:33.151227 <6>[ 3.686545] hub 1-1:1.0: 4 ports detected
10737 13:20:33.163239 <6>[ 3.697465] hub 1-1:1.0: USB hub found
10738 13:20:33.166219 <6>[ 3.701911] hub 1-1:1.0: 4 ports detected
10739 13:20:33.273213 <6>[ 3.804410] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10740 13:20:33.299541 <6>[ 3.833902] hub 2-1:1.0: USB hub found
10741 13:20:33.302804 <6>[ 3.838458] hub 2-1:1.0: 3 ports detected
10742 13:20:33.314112 <6>[ 3.848644] hub 2-1:1.0: USB hub found
10743 13:20:33.317298 <6>[ 3.853087] hub 2-1:1.0: 3 ports detected
10744 13:20:33.489051 <6>[ 4.019999] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10745 13:20:33.620373 <6>[ 4.154812] hub 1-1.4:1.0: USB hub found
10746 13:20:33.623502 <6>[ 4.159355] hub 1-1.4:1.0: 2 ports detected
10747 13:20:33.637998 <6>[ 4.172500] hub 1-1.4:1.0: USB hub found
10748 13:20:33.641140 <6>[ 4.177045] hub 1-1.4:1.0: 2 ports detected
10749 13:20:33.708956 <6>[ 4.240067] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10750 13:20:33.817181 <6>[ 4.348489] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10751 13:20:33.849839 <4>[ 4.380904] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10752 13:20:33.859855 <4>[ 4.390018] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10753 13:20:33.894856 <6>[ 4.429090] r8152 2-1.3:1.0 eth0: v1.12.13
10754 13:20:33.944567 <6>[ 4.475920] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10755 13:20:34.141180 <6>[ 4.672070] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10756 13:20:35.473219 <6>[ 6.007643] r8152 2-1.3:1.0 eth0: carrier on
10757 13:20:37.677032 <5>[ 6.027870] Sending DHCP requests .., OK
10758 13:20:37.683569 <6>[ 8.216193] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10759 13:20:37.687417 <6>[ 8.224492] IP-Config: Complete:
10760 13:20:37.700505 <6>[ 8.227988] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10761 13:20:37.706733 <6>[ 8.238717] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10762 13:20:37.713447 <6>[ 8.247338] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10763 13:20:37.720040 <6>[ 8.247349] nameserver0=192.168.201.1
10764 13:20:37.723297 <6>[ 8.259514] clk: Disabling unused clocks
10765 13:20:37.727139 <6>[ 8.265136] ALSA device list:
10766 13:20:37.733598 <6>[ 8.268414] No soundcards found.
10767 13:20:37.741716 <6>[ 8.275966] Freeing unused kernel memory: 8512K
10768 13:20:37.744837 <6>[ 8.280838] Run /init as init process
10769 13:20:37.774401 <6>[ 8.309317] NET: Registered PF_INET6 protocol family
10770 13:20:37.781219 <6>[ 8.316192] Segment Routing with IPv6
10771 13:20:37.784953 <6>[ 8.320136] In-situ OAM (IOAM) with IPv6
10772 13:20:37.825330 <30>[ 8.333645] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10773 13:20:37.832076 <30>[ 8.366676] systemd[1]: Detected architecture arm64.
10774 13:20:37.832196
10775 13:20:37.838819 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10776 13:20:37.838932
10777 13:20:37.857429 <30>[ 8.392126] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10778 13:20:37.977606 <30>[ 8.509120] systemd[1]: Queued start job for default target graphical.target.
10779 13:20:38.013977 <30>[ 8.545313] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10780 13:20:38.020334 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10781 13:20:38.041022 <30>[ 8.572428] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10782 13:20:38.047525 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10783 13:20:38.069176 <30>[ 8.600747] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10784 13:20:38.078988 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10785 13:20:38.097388 <30>[ 8.628796] systemd[1]: Created slice user.slice - User and Session Slice.
10786 13:20:38.103901 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10787 13:20:38.124139 <30>[ 8.652035] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10788 13:20:38.130557 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10789 13:20:38.152326 <30>[ 8.680556] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10790 13:20:38.158759 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10791 13:20:38.186951 <30>[ 8.708377] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10792 13:20:38.196655 <30>[ 8.728226] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10793 13:20:38.203227 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10794 13:20:38.220835 <30>[ 8.752334] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10795 13:20:38.230774 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10796 13:20:38.244473 <30>[ 8.776039] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10797 13:20:38.254056 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10798 13:20:38.269973 <30>[ 8.804643] systemd[1]: Reached target paths.target - Path Units.
10799 13:20:38.279900 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10800 13:20:38.297233 <30>[ 8.828513] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10801 13:20:38.303912 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10802 13:20:38.317608 <30>[ 8.852119] systemd[1]: Reached target slices.target - Slice Units.
10803 13:20:38.327583 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10804 13:20:38.341197 <30>[ 8.876208] systemd[1]: Reached target swap.target - Swaps.
10805 13:20:38.347953 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10806 13:20:38.368767 <30>[ 8.900175] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10807 13:20:38.378765 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10808 13:20:38.397236 <30>[ 8.928595] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10809 13:20:38.406962 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10810 13:20:38.426505 <30>[ 8.958281] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10811 13:20:38.436421 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10812 13:20:38.453340 <30>[ 8.984743] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10813 13:20:38.463155 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10814 13:20:38.480928 <30>[ 9.012791] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10815 13:20:38.487723 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10816 13:20:38.505440 <30>[ 9.036816] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10817 13:20:38.515102 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10818 13:20:38.533941 <30>[ 9.065589] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10819 13:20:38.543926 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10820 13:20:38.561980 <30>[ 9.093266] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10821 13:20:38.571800 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10822 13:20:38.624851 <30>[ 9.156254] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10823 13:20:38.631122 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10824 13:20:38.653336 <30>[ 9.184737] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10825 13:20:38.660186 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10826 13:20:38.704385 <30>[ 9.236149] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10827 13:20:38.711413 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10828 13:20:38.735222 <30>[ 9.260600] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10829 13:20:38.749967 <30>[ 9.281535] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10830 13:20:38.759868 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10831 13:20:38.781951 <30>[ 9.313416] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10832 13:20:38.788328 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10833 13:20:38.814044 <30>[ 9.345687] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10834 13:20:38.827262 Starting [0;1;39mmodprobe@dm_mod.s…[<6>[ 9.358239] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10835 13:20:38.830399 0m - Load Kernel Module dm_mod...
10836 13:20:38.854341 <30>[ 9.385818] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10837 13:20:38.860840 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10838 13:20:38.885721 <30>[ 9.417523] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10839 13:20:38.895926 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10840 13:20:38.952803 <30>[ 9.484503] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10841 13:20:38.959224 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10842 13:20:38.990465 <30>[ 9.521814] systemd[1]: Starting systemd-journald.service - Journal Service...
10843 13:20:38.996718 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10844 13:20:39.015840 <30>[ 9.547361] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10845 13:20:39.022191 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10846 13:20:39.048908 <30>[ 9.577100] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10847 13:20:39.055355 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10848 13:20:39.077238 <30>[ 9.608745] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10849 13:20:39.087084 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10850 13:20:39.107486 <30>[ 9.639450] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10851 13:20:39.117868 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10852 13:20:39.145298 <30>[ 9.676653] systemd[1]: Started systemd-journald.service - Journal Service.
10853 13:20:39.151729 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10854 13:20:39.171439 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10855 13:20:39.191424 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10856 13:20:39.209689 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10857 13:20:39.230286 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10858 13:20:39.252746 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10859 13:20:39.272233 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10860 13:20:39.291806 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10861 13:20:39.314242 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10862 13:20:39.341050 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10863 13:20:39.362819 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10864 13:20:39.386352 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10865 13:20:39.407592 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10866 13:20:39.425446 See 'systemctl status systemd-remount-fs.service' for details.
10867 13:20:39.436349 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10868 13:20:39.459516 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10869 13:20:39.504641 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10870 13:20:39.530215 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10871 13:20:39.550786 <46>[ 10.082687] systemd-journald[188]: Received client request to flush runtime journal.
10872 13:20:39.563871 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10873 13:20:39.587711 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10874 13:20:39.611483 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10875 13:20:39.637919 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10876 13:20:39.661908 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10877 13:20:39.685837 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10878 13:20:39.705791 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10879 13:20:39.726192 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10880 13:20:39.776712 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10881 13:20:39.812384 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10882 13:20:39.829015 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10883 13:20:39.848865 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10884 13:20:39.896878 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10885 13:20:39.921950 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10886 13:20:39.944730 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10887 13:20:39.989765 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10888 13:20:40.021234 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10889 13:20:40.043419 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10890 13:20:40.105103 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10891 13:20:40.145472 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10892 13:20:40.192578 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10893 13:20:40.304421 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10894 13:20:40.321623 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10895 13:20:40.341372 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10896 13:20:40.348323 <6>[ 10.880243] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10897 13:20:40.358940 <6>[ 10.890650] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10898 13:20:40.369266 <6>[ 10.898873] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10899 13:20:40.375676 <6>[ 10.903675] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10900 13:20:40.385503 <6>[ 10.907871] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10901 13:20:40.392289 <6>[ 10.915665] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10902 13:20:40.398598 <6>[ 10.921016] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10903 13:20:40.412052 [[0;32m OK [<4>[ 10.940784] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10904 13:20:40.421788 0m] Started [0;<4>[ 10.947811] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10905 13:20:40.425594 <4>[ 10.947811] Fallback method does not support PEC.
10906 13:20:40.435322 <6>[ 10.951568] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10907 13:20:40.441637 <6>[ 10.968043] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10908 13:20:40.452446 1;39mfstrim.time<6>[ 10.974162] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10909 13:20:40.458876 r[0m - Discard <6>[ 10.974488] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10910 13:20:40.468807 unused blocks on<3>[ 10.985312] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10911 13:20:40.472202 ce a week.
10912 13:20:40.479122 <6>[ 10.990963] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10913 13:20:40.488735 <3>[ 10.998064] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 13:20:40.495331 <3>[ 11.000080] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10915 13:20:40.505742 <3>[ 11.000097] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10916 13:20:40.512308 <4>[ 11.001169] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10917 13:20:40.518997 <3>[ 11.008303] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10918 13:20:40.528900 <3>[ 11.008314] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10919 13:20:40.535166 <3>[ 11.008318] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10920 13:20:40.542384 <3>[ 11.008323] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10921 13:20:40.553069 <3>[ 11.008327] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10922 13:20:40.559637 <3>[ 11.008355] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10923 13:20:40.569458 <3>[ 11.008377] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10924 13:20:40.576787 <3>[ 11.008380] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10925 13:20:40.583371 <3>[ 11.008382] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10926 13:20:40.593020 <3>[ 11.008400] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10927 13:20:40.599850 <3>[ 11.008403] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10928 13:20:40.607128 <3>[ 11.008405] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10929 13:20:40.617374 <3>[ 11.008408] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10930 13:20:40.624051 <3>[ 11.008411] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10931 13:20:40.633973 <3>[ 11.008421] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10932 13:20:40.640298 <6>[ 11.009836] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10933 13:20:40.647347 <6>[ 11.017450] remoteproc remoteproc0: scp is available
10934 13:20:40.650359 <6>[ 11.017522] remoteproc remoteproc0: powering up scp
10935 13:20:40.660616 <6>[ 11.017526] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10936 13:20:40.663906 <6>[ 11.017548] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10937 13:20:40.673654 <4>[ 11.018990] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10938 13:20:40.680202 <6>[ 11.027351] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10939 13:20:40.687063 <6>[ 11.047447] mc: Linux media interface: v0.10
10940 13:20:40.693613 <6>[ 11.052299] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10941 13:20:40.700257 <3>[ 11.085668] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 13:20:40.706518 <6>[ 11.092222] pci_bus 0000:00: root bus resource [bus 00-ff]
10943 13:20:40.716577 <3>[ 11.120243] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 13:20:40.722948 <6>[ 11.124361] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10945 13:20:40.733173 <6>[ 11.124364] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10946 13:20:40.739717 <6>[ 11.124404] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10947 13:20:40.746001 <6>[ 11.147005] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10948 13:20:40.756256 <6>[ 11.147024] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10949 13:20:40.762546 <6>[ 11.147032] remoteproc remoteproc0: remote processor scp is now up
10950 13:20:40.769087 <6>[ 11.148614] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10951 13:20:40.772429 <6>[ 11.148679] pci 0000:00:00.0: supports D1 D2
10952 13:20:40.782304 <3>[ 11.162722] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 13:20:40.789392 <6>[ 11.164796] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10954 13:20:40.798929 <6>[ 11.164990] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10955 13:20:40.805582 <6>[ 11.165812] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10956 13:20:40.812482 <6>[ 11.165880] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10957 13:20:40.818856 <6>[ 11.165904] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10958 13:20:40.829113 <6>[ 11.165920] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10959 13:20:40.835769 <6>[ 11.165935] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10960 13:20:40.839124 <6>[ 11.166035] pci 0000:01:00.0: supports D1 D2
10961 13:20:40.845269 <6>[ 11.166037] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10962 13:20:40.855152 <6>[ 11.166420] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10963 13:20:40.865339 <6>[ 11.166759] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10964 13:20:40.871691 <6>[ 11.183935] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10965 13:20:40.878125 <6>[ 11.200062] videodev: Linux video capture interface: v2.00
10966 13:20:40.885100 <6>[ 11.201320] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10967 13:20:40.894963 <6>[ 11.203698] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10968 13:20:40.901506 <6>[ 11.205196] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10969 13:20:40.907903 <6>[ 11.222167] Bluetooth: Core ver 2.22
10970 13:20:40.914316 <6>[ 11.226112] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10971 13:20:40.921173 <6>[ 11.226129] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10972 13:20:40.927712 <6>[ 11.233067] NET: Registered PF_BLUETOOTH protocol family
10973 13:20:40.937730 <6>[ 11.241766] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10974 13:20:40.944190 <6>[ 11.247493] Bluetooth: HCI device and connection manager initialized
10975 13:20:40.950746 <6>[ 11.256277] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10976 13:20:40.957584 <6>[ 11.263404] Bluetooth: HCI socket layer initialized
10977 13:20:40.960768 <6>[ 11.273299] pci 0000:00:00.0: PCI bridge to [bus 01]
10978 13:20:40.967376 <6>[ 11.274291] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10979 13:20:40.980967 <6>[ 11.275383] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10980 13:20:40.987303 <6>[ 11.275489] usbcore: registered new interface driver uvcvideo
10981 13:20:40.990783 <6>[ 11.279553] Bluetooth: L2CAP socket layer initialized
10982 13:20:41.000325 <6>[ 11.286591] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10983 13:20:41.003446 <6>[ 11.295106] Bluetooth: SCO socket layer initialized
10984 13:20:41.010269 <6>[ 11.301739] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10985 13:20:41.016744 <6>[ 11.302227] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10986 13:20:41.023983 <6>[ 11.368350] usbcore: registered new interface driver btusb
10987 13:20:41.033744 <4>[ 11.369500] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10988 13:20:41.040092 <3>[ 11.369506] Bluetooth: hci0: Failed to load firmware file (-2)
10989 13:20:41.046743 <3>[ 11.369509] Bluetooth: hci0: Failed to set up firmware (-2)
10990 13:20:41.056438 <4>[ 11.369511] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10991 13:20:41.063056 <6>[ 11.375813] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10992 13:20:41.069974 [[0;32m OK [<6>[ 11.603520] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10993 13:20:41.076206 0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10994 13:20:41.089312 <5>[ 11.620714] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10995 13:20:41.098998 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10996 13:20:41.112232 <5>[ 11.643797] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10997 13:20:41.118667 <5>[ 11.651214] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10998 13:20:41.129114 <4>[ 11.659641] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10999 13:20:41.132393 <6>[ 11.668534] cfg80211: failed to load regulatory.db
11000 13:20:41.148715 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m -<3>[ 11.678940] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11001 13:20:41.148831 Socket Units.
11002 13:20:41.189880 <6>[ 11.721712] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11003 13:20:41.197003 <3>[ 11.723268] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11004 13:20:41.203422 <6>[ 11.729239] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11005 13:20:41.227000 <3>[ 11.759048] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11006 13:20:41.233610 <6>[ 11.765453] mt7921e 0000:01:00.0: ASIC revision: 79610010
11007 13:20:41.240732 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11008 13:20:41.267282 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - B<3>[ 11.796353] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11009 13:20:41.267419 asic System.
11010 13:20:41.311945 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11011 13:20:41.339108 <6>[ 11.871001] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11012 13:20:41.342315 <6>[ 11.871001]
11013 13:20:41.353428 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11014 13:20:41.377634 [[0;32m OK [0m] Started [0;<3>[ 11.908211] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11015 13:20:41.380993 1;39msystemd-networkd.service[0m - Network Configuration.
11016 13:20:41.411770 [[0;32m OK [0m] Started [0;<3>[ 11.941629] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11017 13:20:41.414935 1;39mdbus.service[0m - D-Bus System Message Bus.
11018 13:20:41.459042 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11019 13:20:41.481938 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11020 13:20:41.499772 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11021 13:20:41.517784 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11022 13:20:41.537811 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11023 13:20:41.593116 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11024 13:20:41.607189 <6>[ 12.139146] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11025 13:20:41.625515 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11026 13:20:41.652932 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11027 13:20:41.674068 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11028 13:20:41.722900 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11029 13:20:41.742097 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11030 13:20:41.759306 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11031 13:20:41.776100 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11032 13:20:41.796209 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11033 13:20:41.847113 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11034 13:20:41.874671 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11035 13:20:41.896995 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11036 13:20:41.941587 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11037 13:20:42.018161
11038 13:20:42.021902 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11039 13:20:42.021980
11040 13:20:42.024878 debian-bookworm-arm64 login: root (automatic login)
11041 13:20:42.024953
11042 13:20:42.042657 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024 aarch64
11043 13:20:42.042743
11044 13:20:42.049050 The programs included with the Debian GNU/Linux system are free software;
11045 13:20:42.055642 the exact distribution terms for each program are described in the
11046 13:20:42.059176 individual files in /usr/share/doc/*/copyright.
11047 13:20:42.059273
11048 13:20:42.065448 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11049 13:20:42.068673 permitted by applicable law.
11050 13:20:42.069264 Matched prompt #10: / #
11052 13:20:42.069563 Setting prompt string to ['/ #']
11053 13:20:42.069677 end: 2.2.5.1 login-action (duration 00:00:13) [common]
11055 13:20:42.069974 end: 2.2.5 auto-login-action (duration 00:00:13) [common]
11056 13:20:42.070090 start: 2.2.6 expect-shell-connection (timeout 00:02:59) [common]
11057 13:20:42.070222 Setting prompt string to ['/ #']
11058 13:20:42.070302 Forcing a shell prompt, looking for ['/ #']
11059 13:20:42.070387 Sending line: ''
11061 13:20:42.120752 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11062 13:20:42.120838 Waiting using forced prompt support (timeout 00:02:30)
11063 13:20:42.125766 / #
11064 13:20:42.126062 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11065 13:20:42.126223 start: 2.2.7 export-device-env (timeout 00:02:59) [common]
11066 13:20:42.126336 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11067 13:20:42.126439 end: 2.2 depthcharge-retry (duration 00:02:01) [common]
11068 13:20:42.126564 end: 2 depthcharge-action (duration 00:02:01) [common]
11069 13:20:42.126683 start: 3 lava-test-retry (timeout 00:07:37) [common]
11070 13:20:42.126789 start: 3.1 lava-test-shell (timeout 00:07:37) [common]
11071 13:20:42.126872 Using namespace: common
11072 13:20:42.126957 Sending line: '#'
11074 13:20:42.227435 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11075 13:20:42.232112 / # #
11076 13:20:42.232392 Using /lava-14879051
11077 13:20:42.232481 Sending line: 'export SHELL=/bin/sh'
11079 13:20:42.338195 / # export SHELL=/bin/sh
11080 13:20:42.338448 Sending line: '. /lava-14879051/environment'
11082 13:20:42.443856 / # . /lava-14879051/environment
11083 13:20:42.451055 Sending line: '/lava-14879051/bin/lava-test-runner /lava-14879051/0'
11085 13:20:42.551524 Test shell timeout: 10s (minimum of the action and connection timeout)
11086 13:20:42.551792 / # <6>[ 13.027407] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11087 13:20:42.556511 /lava-14879051/bin/lava-test-runner /lava-14879051/0
11088 13:20:42.598268 + export TESTRUN_ID=0_v4l2-compliance-uvc
11089 13:20:42.598364 + cd /lava-14879051/0/tests/0_v4l2-compliance-uvc
11090 13:20:42.598426 + cat uuid
11091 13:20:42.598480 + UUID=14879051_1.5.2.3.1
11092 13:20:42.598533 + set +x
11093 13:20:42.599632 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 14879051_1.5.2.3.1>
11094 13:20:42.599882 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 14879051_1.5.2.3.1
11095 13:20:42.599945 Starting test lava.0_v4l2-compliance-uvc (14879051_1.5.2.3.1)
11096 13:20:42.600016 Skipping test definition patterns.
11097 13:20:42.602680 + /usr/bin/v4l2-parser.sh -d uvcvideo
11098 13:20:42.609917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11099 13:20:42.610142 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11101 13:20:42.613072 device: /dev/video0
11102 13:20:49.236385 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11103 13:20:49.250858 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11104 13:20:49.259655
11105 13:20:49.278884 Compliance test for uvcvideo device /dev/video0:
11106 13:20:49.287066
11107 13:20:49.302580 Driver Info:
11108 13:20:49.312682 Driver name : uvcvideo
11109 13:20:49.326714 Card type : HD User Facing: HD User Facing
11110 13:20:49.338425 Bus info : usb-11200000.usb-1.4.1
11111 13:20:49.348800 Driver version : 6.1.96
11112 13:20:49.360789 Capabilities : 0x84a00001
11113 13:20:49.373460 Metadata Capture
11114 13:20:49.383894 Streaming
11115 13:20:49.396701 Extended Pix Format
11116 13:20:49.411135 Device Capabilities
11117 13:20:49.421324 Device Caps : 0x04200001
11118 13:20:49.435343 Streaming
11119 13:20:49.450240 Extended Pix Format
11120 13:20:49.460322 Media Driver Info:
11121 13:20:49.474390 Driver name : uvcvideo
11122 13:20:49.489226 Model : HD User Facing: HD User Facing
11123 13:20:49.501807 Serial : 200901010001
11124 13:20:49.517469 Bus info : usb-11200000.usb-1.4.1
11125 13:20:49.530336 Media version : 6.1.96
11126 13:20:49.545420 Hardware revision: 0x00009758 (38744)
11127 13:20:49.551513 Driver version : 6.1.96
11128 13:20:49.567755 Interface Info:
11129 13:20:49.594483 <LAVA_SIGNAL_TESTSET START Interface-Info>
11130 13:20:49.594593 ID : 0x03000002
11131 13:20:49.594858 Received signal: <TESTSET> START Interface-Info
11132 13:20:49.594927 Starting test_set Interface-Info
11133 13:20:49.599886 Type : V4L Video
11134 13:20:49.616151 Entity Info:
11135 13:20:49.623046 <LAVA_SIGNAL_TESTSET STOP>
11136 13:20:49.623298 Received signal: <TESTSET> STOP
11137 13:20:49.623362 Closing test_set Interface-Info
11138 13:20:49.633624 <LAVA_SIGNAL_TESTSET START Entity-Info>
11139 13:20:49.633900 Received signal: <TESTSET> START Entity-Info
11140 13:20:49.634008 Starting test_set Entity-Info
11141 13:20:49.636896 ID : 0x00000001 (1)
11142 13:20:49.647259 Name : HD User Facing: HD User Facing
11143 13:20:49.655056 Function : V4L2 I/O
11144 13:20:49.669637 Flags : default
11145 13:20:49.680766 Pad 0x01000007 : 0: Sink
11146 13:20:49.700963 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11147 13:20:49.701091
11148 13:20:49.712360 Required ioctls:
11149 13:20:49.722624 <LAVA_SIGNAL_TESTSET STOP>
11150 13:20:49.722871 Received signal: <TESTSET> STOP
11151 13:20:49.722933 Closing test_set Entity-Info
11152 13:20:49.733464 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11153 13:20:49.733735 Received signal: <TESTSET> START Required-ioctls
11154 13:20:49.733821 Starting test_set Required-ioctls
11155 13:20:49.739789 test MC information (see 'Media Driver Info' above): OK
11156 13:20:49.765897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11157 13:20:49.766205 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11159 13:20:49.768503 test VIDIOC_QUERYCAP: OK
11160 13:20:49.792437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11161 13:20:49.792730 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11163 13:20:49.796234 test invalid ioctls: OK
11164 13:20:49.817104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11165 13:20:49.817206
11166 13:20:49.817433 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11168 13:20:49.828843 Allow for multiple opens:
11169 13:20:49.837379 <LAVA_SIGNAL_TESTSET STOP>
11170 13:20:49.837658 Received signal: <TESTSET> STOP
11171 13:20:49.837748 Closing test_set Required-ioctls
11172 13:20:49.850504 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11173 13:20:49.850774 Received signal: <TESTSET> START Allow-for-multiple-opens
11174 13:20:49.850863 Starting test_set Allow-for-multiple-opens
11175 13:20:49.854219 test second /dev/video0 open: OK
11176 13:20:49.876438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11177 13:20:49.876723 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11179 13:20:49.879797 test VIDIOC_QUERYCAP: OK
11180 13:20:49.901999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11181 13:20:49.902286 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11183 13:20:49.905554 test VIDIOC_G/S_PRIORITY: OK
11184 13:20:49.927707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11185 13:20:49.927994 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11187 13:20:49.930887 test for unlimited opens: OK
11188 13:20:49.956879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11189 13:20:49.956976
11190 13:20:49.957202 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11192 13:20:49.969522 Debug ioctls:
11193 13:20:49.976540 <LAVA_SIGNAL_TESTSET STOP>
11194 13:20:49.976786 Received signal: <TESTSET> STOP
11195 13:20:49.976848 Closing test_set Allow-for-multiple-opens
11196 13:20:49.986959 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11197 13:20:49.987203 Received signal: <TESTSET> START Debug-ioctls
11198 13:20:49.987265 Starting test_set Debug-ioctls
11199 13:20:49.990138 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11200 13:20:50.011906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11201 13:20:50.012161 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11203 13:20:50.018714 test VIDIOC_LOG_STATUS: OK (Not Supported)
11204 13:20:50.042033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11205 13:20:50.042173
11206 13:20:50.042402 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11208 13:20:50.053528 Input ioctls:
11209 13:20:50.061842 <LAVA_SIGNAL_TESTSET STOP>
11210 13:20:50.062105 Received signal: <TESTSET> STOP
11211 13:20:50.062181 Closing test_set Debug-ioctls
11212 13:20:50.071258 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11213 13:20:50.071523 Received signal: <TESTSET> START Input-ioctls
11214 13:20:50.071585 Starting test_set Input-ioctls
11215 13:20:50.074492 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11216 13:20:50.100364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11217 13:20:50.100630 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11219 13:20:50.103634 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11220 13:20:50.122890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11221 13:20:50.123140 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11223 13:20:50.129279 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11224 13:20:50.147926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11225 13:20:50.148228 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11227 13:20:50.154558 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11228 13:20:50.176228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11229 13:20:50.176489 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11231 13:20:50.179391 test VIDIOC_G/S/ENUMINPUT: OK
11232 13:20:50.201136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11233 13:20:50.201428 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11235 13:20:50.204196 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11236 13:20:50.224700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11237 13:20:50.224959 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11239 13:20:50.228552 Inputs: 1 Audio Inputs: 0 Tuners: 0
11240 13:20:50.236923
11241 13:20:50.252587 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11242 13:20:50.274415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11243 13:20:50.274692 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11245 13:20:50.281296 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11246 13:20:50.298796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11247 13:20:50.299076 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11249 13:20:50.305293 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11250 13:20:50.328552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11251 13:20:50.328811 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11253 13:20:50.335059 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11254 13:20:50.353437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11255 13:20:50.353719 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11257 13:20:50.359883 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11258 13:20:50.378050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11259 13:20:50.378395 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11261 13:20:50.382961
11262 13:20:50.403558 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11263 13:20:50.423534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11264 13:20:50.423818 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11266 13:20:50.430033 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11267 13:20:50.452614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11268 13:20:50.452922 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11270 13:20:50.455586 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11271 13:20:50.472542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11272 13:20:50.472867 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11274 13:20:50.475869 test VIDIOC_G/S_EDID: OK (Not Supported)
11275 13:20:50.497217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11276 13:20:50.497310
11277 13:20:50.497533 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11279 13:20:50.508772 Control ioctls (Input 0):
11280 13:20:50.515801 <LAVA_SIGNAL_TESTSET STOP>
11281 13:20:50.516043 Received signal: <TESTSET> STOP
11282 13:20:50.516103 Closing test_set Input-ioctls
11283 13:20:50.526088 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11284 13:20:50.526367 Received signal: <TESTSET> START Control-ioctls-Input-0
11285 13:20:50.526443 Starting test_set Control-ioctls-Input-0
11286 13:20:50.529167 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11287 13:20:50.555900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11288 13:20:50.555999 test VIDIOC_QUERYCTRL: OK
11289 13:20:50.556225 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11291 13:20:50.575516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11292 13:20:50.575777 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11294 13:20:50.578533 test VIDIOC_G/S_CTRL: OK
11295 13:20:50.600296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11296 13:20:50.600627 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11298 13:20:50.603672 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11299 13:20:50.625075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11300 13:20:50.625337 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11302 13:20:50.631416 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11303 13:20:50.652825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11304 13:20:50.653099 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11306 13:20:50.655914 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11307 13:20:50.674308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11308 13:20:50.674618 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11310 13:20:50.678015 Standard Controls: 16 Private Controls: 0
11311 13:20:50.684810
11312 13:20:50.695028 Format ioctls (Input 0):
11313 13:20:50.703057 <LAVA_SIGNAL_TESTSET STOP>
11314 13:20:50.703316 Received signal: <TESTSET> STOP
11315 13:20:50.703394 Closing test_set Control-ioctls-Input-0
11316 13:20:50.712386 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11317 13:20:50.712651 Received signal: <TESTSET> START Format-ioctls-Input-0
11318 13:20:50.712716 Starting test_set Format-ioctls-Input-0
11319 13:20:50.715624 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11320 13:20:50.746859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11321 13:20:50.747139 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11323 13:20:50.749871 test VIDIOC_G/S_PARM: OK
11324 13:20:50.768461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11325 13:20:50.768748 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11327 13:20:50.772186 test VIDIOC_G_FBUF: OK (Not Supported)
11328 13:20:50.792344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11329 13:20:50.792634 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11331 13:20:50.796050 test VIDIOC_G_FMT: OK
11332 13:20:50.822300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11333 13:20:50.822591 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11335 13:20:50.825604 test VIDIOC_TRY_FMT: OK
11336 13:20:50.847747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11337 13:20:50.848042 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11339 13:20:50.854158 warn: v4l2-test-formats.cpp(1046): Could not set fmt2
11340 13:20:50.858735 test VIDIOC_S_FMT: OK
11341 13:20:50.884180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11342 13:20:50.884469 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11344 13:20:50.887407 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11345 13:20:50.910113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11346 13:20:50.910401 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11348 13:20:50.913440 test Cropping: OK (Not Supported)
11349 13:20:50.934682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11350 13:20:50.934971 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11352 13:20:50.937576 test Composing: OK (Not Supported)
11353 13:20:50.959321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11354 13:20:50.959645 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11356 13:20:50.962627 test Scaling: OK (Not Supported)
11357 13:20:50.983780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11358 13:20:50.983910
11359 13:20:50.984173 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11361 13:20:50.995226 Codec ioctls (Input 0):
11362 13:20:51.002831 <LAVA_SIGNAL_TESTSET STOP>
11363 13:20:51.003176 Received signal: <TESTSET> STOP
11364 13:20:51.003239 Closing test_set Format-ioctls-Input-0
11365 13:20:51.012351 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11366 13:20:51.012608 Received signal: <TESTSET> START Codec-ioctls-Input-0
11367 13:20:51.012672 Starting test_set Codec-ioctls-Input-0
11368 13:20:51.015500 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11369 13:20:51.038681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11370 13:20:51.038974 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11372 13:20:51.045153 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11373 13:20:51.064720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11374 13:20:51.065011 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11376 13:20:51.070890 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11377 13:20:51.095718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11378 13:20:51.095840
11379 13:20:51.096066 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11381 13:20:51.111619 Buffer ioctls (Input 0):
11382 13:20:51.117862 <LAVA_SIGNAL_TESTSET STOP>
11383 13:20:51.118141 Received signal: <TESTSET> STOP
11384 13:20:51.118217 Closing test_set Codec-ioctls-Input-0
11385 13:20:51.127305 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11386 13:20:51.127672 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11387 13:20:51.127760 Starting test_set Buffer-ioctls-Input-0
11388 13:20:51.130615 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11389 13:20:51.155823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11390 13:20:51.156105 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11392 13:20:51.158969 test CREATE_BUFS maximum buffers: OK
11393 13:20:51.184676 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11395 13:20:51.187367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11396 13:20:51.187493 test VIDIOC_EXPBUF: OK
11397 13:20:51.208479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11398 13:20:51.208764 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11400 13:20:51.212289 test Requests: OK (Not Supported)
11401 13:20:51.233401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11402 13:20:51.233505
11403 13:20:51.233765 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11405 13:20:51.242726 Test input 0:
11406 13:20:51.252979
11407 13:20:51.263936 Streaming ioctls:
11408 13:20:51.269848 <LAVA_SIGNAL_TESTSET STOP>
11409 13:20:51.270107 Received signal: <TESTSET> STOP
11410 13:20:51.270214 Closing test_set Buffer-ioctls-Input-0
11411 13:20:51.280656 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11412 13:20:51.280902 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11413 13:20:51.281000 Starting test_set Streaming-ioctls_Test-input-0
11414 13:20:51.283832 test read/write: OK (Not Supported)
11415 13:20:51.305988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11416 13:20:51.306254 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11418 13:20:51.308998 test blocking wait: OK
11419 13:20:51.330836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11420 13:20:51.331102 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11422 13:20:51.337318 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11423 13:20:51.345692 test MMAP (no poll): FAIL
11424 13:20:51.367235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11425 13:20:51.367507 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11427 13:20:51.373777 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11428 13:20:51.377494 test MMAP (select): FAIL
11429 13:20:51.400650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11430 13:20:51.400912 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11432 13:20:51.406977 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11433 13:20:51.414763 test MMAP (epoll): FAIL
11434 13:20:51.437454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11435 13:20:51.437579
11436 13:20:51.437844 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11438 13:20:51.449806
11439 13:20:51.632430
11440 13:20:51.641240 test USERPTR (no poll): OK
11441 13:20:51.670982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11442 13:20:51.671117
11443 13:20:51.671389 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11445 13:20:51.686370
11446 13:20:51.859658
11447 13:20:51.866008 test USERPTR (select): OK
11448 13:20:51.890890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11449 13:20:51.891161 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11451 13:20:51.897269 test DMABUF: Cannot test, specify --expbuf-device
11452 13:20:51.902362
11453 13:20:51.919628 Total for uvcvideo device /dev/video0: 54, Succeeded: 51, Failed: 3, Warnings: 3
11454 13:20:51.922569 <LAVA_TEST_RUNNER EXIT>
11455 13:20:51.922863 ok: lava_test_shell seems to have completed
11456 13:20:51.922957 Marking unfinished test run as failed
11458 13:20:51.924907 device-presence: pass
MC-information-see-Media-Driver-Info-above:
set: Required-ioctls
result: pass
VIDIOC_QUERYCAP:
set: Allow-for-multiple-opens
result: pass
invalid-ioctls:
set: Required-ioctls
result: pass
second-/dev/video0-open:
set: Allow-for-multiple-opens
result: pass
VIDIOC_G/S_PRIORITY:
set: Allow-for-multiple-opens
result: pass
for-unlimited-opens:
set: Allow-for-multiple-opens
result: pass
VIDIOC_DBG_G/S_REGISTER:
set: Debug-ioctls
result: pass
VIDIOC_LOG_STATUS:
set: Debug-ioctls
result: pass
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
set: Input-ioctls
result: pass
VIDIOC_G/S_FREQUENCY:
set: Input-ioctls
result: pass
VIDIOC_S_HW_FREQ_SEEK:
set: Input-ioctls
result: pass
VIDIOC_ENUMAUDIO:
set: Input-ioctls
result: pass
VIDIOC_G/S/ENUMINPUT:
set: Input-ioctls
result: pass
VIDIOC_G/S_AUDIO:
set: Input-ioctls
result: pass
VIDIOC_G/S_MODULATOR:
set: Input-ioctls
result: pass
VIDIOC_ENUMAUDOUT:
set: Input-ioctls
result: pass
VIDIOC_G/S/ENUMOUTPUT:
set: Input-ioctls
result: pass
VIDIOC_G/S_AUDOUT:
set: Input-ioctls
result: pass
VIDIOC_ENUM/G/S/QUERY_STD:
set: Input-ioctls
result: pass
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
set: Input-ioctls
result: pass
VIDIOC_DV_TIMINGS_CAP:
set: Input-ioctls
result: pass
VIDIOC_G/S_EDID:
set: Input-ioctls
result: pass
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
set: Control-ioctls-Input-0
result: pass
VIDIOC_QUERYCTRL:
set: Control-ioctls-Input-0
result: pass
VIDIOC_G/S_CTRL:
set: Control-ioctls-Input-0
result: pass
VIDIOC_G/S/TRY_EXT_CTRLS:
set: Control-ioctls-Input-0
result: pass
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
set: Control-ioctls-Input-0
result: pass
VIDIOC_G/S_JPEGCOMP:
set: Control-ioctls-Input-0
result: pass
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
set: Format-ioctls-Input-0
result: pass
VIDIOC_G/S_PARM:
set: Format-ioctls-Input-0
result: pass
VIDIOC_G_FBUF:
set: Format-ioctls-Input-0
result: pass
VIDIOC_G_FMT:
set: Format-ioctls-Input-0
result: pass
VIDIOC_TRY_FMT:
set: Format-ioctls-Input-0
result: pass
VIDIOC_S_FMT:
set: Format-ioctls-Input-0
result: pass
VIDIOC_G_SLICED_VBI_CAP:
set: Format-ioctls-Input-0
result: pass
Cropping:
set: Format-ioctls-Input-0
result: pass
Composing:
set: Format-ioctls-Input-0
result: pass
Scaling:
set: Format-ioctls-Input-0
result: pass
VIDIOC_TRY_ENCODER_CMD:
set: Codec-ioctls-Input-0
result: pass
VIDIOC_G_ENC_INDEX:
set: Codec-ioctls-Input-0
result: pass
VIDIOC_TRY_DECODER_CMD:
set: Codec-ioctls-Input-0
result: pass
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
set: Buffer-ioctls-Input-0
result: pass
CREATE_BUFS-maximum-buffers:
set: Buffer-ioctls-Input-0
result: pass
VIDIOC_EXPBUF:
set: Buffer-ioctls-Input-0
result: pass
Requests:
set: Buffer-ioctls-Input-0
result: pass
read/write:
set: Streaming-ioctls_Test-input-0
result: pass
blocking-wait:
set: Streaming-ioctls_Test-input-0
result: pass
MMAP-no-poll:
set: Streaming-ioctls_Test-input-0
result: fail
MMAP-select:
set: Streaming-ioctls_Test-input-0
result: fail
MMAP-epoll:
set: Streaming-ioctls_Test-input-0
result: fail
USERPTR-no-poll:
set: Streaming-ioctls_Test-input-0
result: pass
USERPTR-select:
set: Streaming-ioctls_Test-input-0
result: pass
11459 13:20:51.925089 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11460 13:20:51.925189 end: 3 lava-test-retry (duration 00:00:10) [common]
11461 13:20:51.925269 start: 4 finalize (timeout 00:07:28) [common]
11462 13:20:51.925360 start: 4.1 power-off (timeout 00:00:30) [common]
11463 13:20:51.925483 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
11464 13:20:54.003395 >> Command sent successfully.
11465 13:20:54.007561 Returned 0 in 2 seconds
11466 13:20:54.007741 end: 4.1 power-off (duration 00:00:02) [common]
11468 13:20:54.008067 start: 4.2 read-feedback (timeout 00:07:25) [common]
11469 13:20:54.008251 Listened to connection for namespace 'common' for up to 1s
11470 13:20:55.008309 Finalising connection for namespace 'common'
11471 13:20:55.008440 Disconnecting from shell: Finalise
11472 13:20:55.008503 / #
11473 13:20:55.108726 end: 4.2 read-feedback (duration 00:00:01) [common]
11474 13:20:55.108870 end: 4 finalize (duration 00:00:03) [common]
11475 13:20:55.108961 Cleaning after the job
11476 13:20:55.109044 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879051/tftp-deploy-779tez8t/ramdisk
11477 13:20:55.113604 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879051/tftp-deploy-779tez8t/kernel
11478 13:20:55.127581 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879051/tftp-deploy-779tez8t/dtb
11479 13:20:55.127796 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879051/tftp-deploy-779tez8t/modules
11480 13:20:55.133523 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14879051
11481 13:20:55.199795 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14879051
11482 13:20:55.199952 Job finished correctly