Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 24
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 13:07:13.881594 lava-dispatcher, installed at version: 2024.05
2 13:07:13.881810 start: 0 validate
3 13:07:13.881951 Start time: 2024-07-18 13:07:13.881945+00:00 (UTC)
4 13:07:13.882151 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:07:13.882335 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 13:07:14.141495 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:07:14.141714 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 13:07:26.145533 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:07:26.146451 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:07:26.406646 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:07:26.407209 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
12 13:07:29.662213 validate duration: 15.78
14 13:07:29.662450 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:07:29.662542 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:07:29.662620 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:07:29.662760 Not decompressing ramdisk as can be used compressed.
18 13:07:29.662838 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 13:07:29.662901 saving as /var/lib/lava/dispatcher/tmp/14878991/tftp-deploy-74ffm5nz/ramdisk/rootfs.cpio.gz
20 13:07:29.662963 total size: 8181887 (7 MB)
21 13:07:29.919974 progress 0 % (0 MB)
22 13:07:29.922322 progress 5 % (0 MB)
23 13:07:29.924424 progress 10 % (0 MB)
24 13:07:29.926601 progress 15 % (1 MB)
25 13:07:29.928740 progress 20 % (1 MB)
26 13:07:29.930885 progress 25 % (1 MB)
27 13:07:29.932893 progress 30 % (2 MB)
28 13:07:29.935096 progress 35 % (2 MB)
29 13:07:29.937085 progress 40 % (3 MB)
30 13:07:29.939398 progress 45 % (3 MB)
31 13:07:29.941579 progress 50 % (3 MB)
32 13:07:29.943862 progress 55 % (4 MB)
33 13:07:29.945853 progress 60 % (4 MB)
34 13:07:29.948028 progress 65 % (5 MB)
35 13:07:29.950201 progress 70 % (5 MB)
36 13:07:29.952258 progress 75 % (5 MB)
37 13:07:29.954308 progress 80 % (6 MB)
38 13:07:29.956552 progress 85 % (6 MB)
39 13:07:29.958717 progress 90 % (7 MB)
40 13:07:29.960913 progress 95 % (7 MB)
41 13:07:29.963003 progress 100 % (7 MB)
42 13:07:29.963205 7 MB downloaded in 0.30 s (25.99 MB/s)
43 13:07:29.963354 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:07:29.963574 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:07:29.963653 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:07:29.963728 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:07:29.963861 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
49 13:07:29.963924 saving as /var/lib/lava/dispatcher/tmp/14878991/tftp-deploy-74ffm5nz/kernel/Image
50 13:07:29.963977 total size: 54813184 (52 MB)
51 13:07:29.964030 No compression specified
52 13:07:29.965192 progress 0 % (0 MB)
53 13:07:29.978973 progress 5 % (2 MB)
54 13:07:29.993317 progress 10 % (5 MB)
55 13:07:30.006922 progress 15 % (7 MB)
56 13:07:30.020661 progress 20 % (10 MB)
57 13:07:30.034172 progress 25 % (13 MB)
58 13:07:30.047591 progress 30 % (15 MB)
59 13:07:30.061468 progress 35 % (18 MB)
60 13:07:30.075168 progress 40 % (20 MB)
61 13:07:30.088821 progress 45 % (23 MB)
62 13:07:30.102435 progress 50 % (26 MB)
63 13:07:30.116108 progress 55 % (28 MB)
64 13:07:30.129593 progress 60 % (31 MB)
65 13:07:30.143274 progress 65 % (34 MB)
66 13:07:30.156632 progress 70 % (36 MB)
67 13:07:30.170578 progress 75 % (39 MB)
68 13:07:30.184702 progress 80 % (41 MB)
69 13:07:30.198268 progress 85 % (44 MB)
70 13:07:30.211947 progress 90 % (47 MB)
71 13:07:30.225567 progress 95 % (49 MB)
72 13:07:30.238928 progress 100 % (52 MB)
73 13:07:30.239172 52 MB downloaded in 0.28 s (189.96 MB/s)
74 13:07:30.239327 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:07:30.239540 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:07:30.239619 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:07:30.239695 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:07:30.239826 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:07:30.239887 saving as /var/lib/lava/dispatcher/tmp/14878991/tftp-deploy-74ffm5nz/dtb/mt8192-asurada-spherion-r0.dtb
81 13:07:30.239940 total size: 47258 (0 MB)
82 13:07:30.239993 No compression specified
83 13:07:30.241091 progress 69 % (0 MB)
84 13:07:30.241347 progress 100 % (0 MB)
85 13:07:30.241492 0 MB downloaded in 0.00 s (29.10 MB/s)
86 13:07:30.241606 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:07:30.241809 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:07:30.241885 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:07:30.241960 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:07:30.242086 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
92 13:07:30.242150 saving as /var/lib/lava/dispatcher/tmp/14878991/tftp-deploy-74ffm5nz/modules/modules.tar
93 13:07:30.242204 total size: 8611320 (8 MB)
94 13:07:30.242259 Using unxz to decompress xz
95 13:07:30.243582 progress 0 % (0 MB)
96 13:07:30.264870 progress 5 % (0 MB)
97 13:07:30.291731 progress 10 % (0 MB)
98 13:07:30.316369 progress 15 % (1 MB)
99 13:07:30.340582 progress 20 % (1 MB)
100 13:07:30.364009 progress 25 % (2 MB)
101 13:07:30.387539 progress 30 % (2 MB)
102 13:07:30.410052 progress 35 % (2 MB)
103 13:07:30.436228 progress 40 % (3 MB)
104 13:07:30.460433 progress 45 % (3 MB)
105 13:07:30.484289 progress 50 % (4 MB)
106 13:07:30.508691 progress 55 % (4 MB)
107 13:07:30.532843 progress 60 % (4 MB)
108 13:07:30.555955 progress 65 % (5 MB)
109 13:07:30.581827 progress 70 % (5 MB)
110 13:07:30.610042 progress 75 % (6 MB)
111 13:07:30.638660 progress 80 % (6 MB)
112 13:07:30.663556 progress 85 % (7 MB)
113 13:07:30.687171 progress 90 % (7 MB)
114 13:07:30.710410 progress 95 % (7 MB)
115 13:07:30.733393 progress 100 % (8 MB)
116 13:07:30.739019 8 MB downloaded in 0.50 s (16.53 MB/s)
117 13:07:30.739206 end: 1.4.1 http-download (duration 00:00:00) [common]
119 13:07:30.739431 end: 1.4 download-retry (duration 00:00:00) [common]
120 13:07:30.739513 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:07:30.739591 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:07:30.739662 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:07:30.739738 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:07:30.739911 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r
125 13:07:30.740032 makedir: /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin
126 13:07:30.740123 makedir: /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/tests
127 13:07:30.740217 makedir: /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/results
128 13:07:30.740304 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-add-keys
129 13:07:30.740432 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-add-sources
130 13:07:30.740550 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-background-process-start
131 13:07:30.740688 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-background-process-stop
132 13:07:30.740853 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-common-functions
133 13:07:30.740973 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-echo-ipv4
134 13:07:30.741090 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-install-packages
135 13:07:30.741210 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-installed-packages
136 13:07:30.741321 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-os-build
137 13:07:30.741433 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-probe-channel
138 13:07:30.741551 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-probe-ip
139 13:07:30.741666 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-target-ip
140 13:07:30.741779 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-target-mac
141 13:07:30.741891 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-target-storage
142 13:07:30.742023 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-test-case
143 13:07:30.742139 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-test-event
144 13:07:30.742250 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-test-feedback
145 13:07:30.742362 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-test-raise
146 13:07:30.742498 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-test-reference
147 13:07:30.742654 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-test-runner
148 13:07:30.742770 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-test-set
149 13:07:30.742886 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-test-shell
150 13:07:30.743004 Updating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-install-packages (oe)
151 13:07:30.743145 Updating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/bin/lava-installed-packages (oe)
152 13:07:30.743256 Creating /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/environment
153 13:07:30.743347 LAVA metadata
154 13:07:30.743417 - LAVA_JOB_ID=14878991
155 13:07:30.743475 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:07:30.743567 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:07:30.743625 skipped lava-vland-overlay
158 13:07:30.743692 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:07:30.743763 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:07:30.743819 skipped lava-multinode-overlay
161 13:07:30.743892 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:07:30.743963 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:07:30.744027 Loading test definitions
164 13:07:30.744103 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:07:30.744166 Using /lava-14878991 at stage 0
166 13:07:30.744566 uuid=14878991_1.5.2.3.1 testdef=None
167 13:07:30.744650 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:07:30.744731 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:07:30.745187 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:07:30.745397 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:07:30.746010 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:07:30.746296 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:07:30.746900 runner path: /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/0/tests/0_dmesg test_uuid 14878991_1.5.2.3.1
176 13:07:30.747052 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:07:30.747246 Creating lava-test-runner.conf files
179 13:07:30.747303 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14878991/lava-overlay-5mmwlq2r/lava-14878991/0 for stage 0
180 13:07:30.747384 - 0_dmesg
181 13:07:30.747476 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:07:30.747562 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:07:30.754120 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:07:30.754257 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:07:30.754370 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:07:30.754477 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:07:30.754584 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:07:30.969988 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 13:07:30.970147 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
190 13:07:30.970226 extracting modules file /var/lib/lava/dispatcher/tmp/14878991/tftp-deploy-74ffm5nz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14878991/extract-overlay-ramdisk-s4qdog8o/ramdisk
191 13:07:31.187805 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:07:31.187950 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 13:07:31.188034 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14878991/compress-overlay-r_0o90mv/overlay-1.5.2.4.tar.gz to ramdisk
194 13:07:31.188095 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14878991/compress-overlay-r_0o90mv/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14878991/extract-overlay-ramdisk-s4qdog8o/ramdisk
195 13:07:31.194647 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:07:31.194782 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 13:07:31.194891 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:07:31.194996 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 13:07:31.195075 Building ramdisk /var/lib/lava/dispatcher/tmp/14878991/extract-overlay-ramdisk-s4qdog8o/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14878991/extract-overlay-ramdisk-s4qdog8o/ramdisk
200 13:07:31.500107 >> 144748 blocks
201 13:07:33.919143 rename /var/lib/lava/dispatcher/tmp/14878991/extract-overlay-ramdisk-s4qdog8o/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14878991/tftp-deploy-74ffm5nz/ramdisk/ramdisk.cpio.gz
202 13:07:33.919304 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 13:07:33.919396 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
204 13:07:33.919479 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
205 13:07:33.919563 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14878991/tftp-deploy-74ffm5nz/kernel/Image']
206 13:07:49.326168 Returned 0 in 15 seconds
207 13:07:49.326348 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14878991/tftp-deploy-74ffm5nz/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14878991/tftp-deploy-74ffm5nz/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14878991/tftp-deploy-74ffm5nz/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14878991/tftp-deploy-74ffm5nz/kernel/image.itb
208 13:07:49.681169 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:07:49.681289 output: Created: Thu Jul 18 14:07:49 2024
210 13:07:49.681355 output: Image 0 (kernel-1)
211 13:07:49.681414 output: Description:
212 13:07:49.681481 output: Created: Thu Jul 18 14:07:49 2024
213 13:07:49.681535 output: Type: Kernel Image
214 13:07:49.681586 output: Compression: lzma compressed
215 13:07:49.681638 output: Data Size: 13114469 Bytes = 12807.10 KiB = 12.51 MiB
216 13:07:49.681688 output: Architecture: AArch64
217 13:07:49.681737 output: OS: Linux
218 13:07:49.681786 output: Load Address: 0x00000000
219 13:07:49.681835 output: Entry Point: 0x00000000
220 13:07:49.681887 output: Hash algo: crc32
221 13:07:49.681936 output: Hash value: a47b020b
222 13:07:49.681985 output: Image 1 (fdt-1)
223 13:07:49.682051 output: Description: mt8192-asurada-spherion-r0
224 13:07:49.682100 output: Created: Thu Jul 18 14:07:49 2024
225 13:07:49.682149 output: Type: Flat Device Tree
226 13:07:49.682198 output: Compression: uncompressed
227 13:07:49.682247 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 13:07:49.682295 output: Architecture: AArch64
229 13:07:49.682344 output: Hash algo: crc32
230 13:07:49.682393 output: Hash value: 0f8e4d2e
231 13:07:49.682441 output: Image 2 (ramdisk-1)
232 13:07:49.682489 output: Description: unavailable
233 13:07:49.682538 output: Created: Thu Jul 18 14:07:49 2024
234 13:07:49.682586 output: Type: RAMDisk Image
235 13:07:49.682634 output: Compression: uncompressed
236 13:07:49.682681 output: Data Size: 21345581 Bytes = 20845.29 KiB = 20.36 MiB
237 13:07:49.682730 output: Architecture: AArch64
238 13:07:49.682778 output: OS: Linux
239 13:07:49.682826 output: Load Address: unavailable
240 13:07:49.682874 output: Entry Point: unavailable
241 13:07:49.682921 output: Hash algo: crc32
242 13:07:49.682968 output: Hash value: ce576c93
243 13:07:49.683017 output: Default Configuration: 'conf-1'
244 13:07:49.683074 output: Configuration 0 (conf-1)
245 13:07:49.683134 output: Description: mt8192-asurada-spherion-r0
246 13:07:49.683183 output: Kernel: kernel-1
247 13:07:49.683231 output: Init Ramdisk: ramdisk-1
248 13:07:49.683281 output: FDT: fdt-1
249 13:07:49.683329 output: Loadables: kernel-1
250 13:07:49.683378 output:
251 13:07:49.683485 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 13:07:49.683560 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 13:07:49.683637 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 13:07:49.683712 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 13:07:49.683769 No LXC device requested
256 13:07:49.683839 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:07:49.683911 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 13:07:49.683979 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:07:49.684035 Checking files for TFTP limit of 4294967296 bytes.
260 13:07:49.684413 end: 1 tftp-deploy (duration 00:00:20) [common]
261 13:07:49.684502 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:07:49.684581 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:07:49.684671 substitutions:
264 13:07:49.684730 - {DTB}: 14878991/tftp-deploy-74ffm5nz/dtb/mt8192-asurada-spherion-r0.dtb
265 13:07:49.684786 - {INITRD}: 14878991/tftp-deploy-74ffm5nz/ramdisk/ramdisk.cpio.gz
266 13:07:49.684838 - {KERNEL}: 14878991/tftp-deploy-74ffm5nz/kernel/Image
267 13:07:49.684890 - {LAVA_MAC}: None
268 13:07:49.684940 - {PRESEED_CONFIG}: None
269 13:07:49.684991 - {PRESEED_LOCAL}: None
270 13:07:49.685040 - {RAMDISK}: 14878991/tftp-deploy-74ffm5nz/ramdisk/ramdisk.cpio.gz
271 13:07:49.685098 - {ROOT_PART}: None
272 13:07:49.685150 - {ROOT}: None
273 13:07:49.685200 - {SERVER_IP}: 192.168.201.1
274 13:07:49.685249 - {TEE}: None
275 13:07:49.685298 Parsed boot commands:
276 13:07:49.685346 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:07:49.685492 Parsed boot commands: tftpboot 192.168.201.1 14878991/tftp-deploy-74ffm5nz/kernel/image.itb 14878991/tftp-deploy-74ffm5nz/kernel/cmdline
278 13:07:49.685572 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:07:49.685647 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:07:49.685719 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:07:49.685790 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:07:49.685846 Not connected, no need to disconnect.
283 13:07:49.685912 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:07:49.685981 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:07:49.686050 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 13:07:49.688701 Setting prompt string to ['lava-test: # ']
287 13:07:49.689041 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:07:49.689172 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:07:49.689308 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:07:49.689426 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:07:49.689723 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
292 13:07:58.851935 >> Command sent successfully.
293 13:07:58.855828 Returned 0 in 9 seconds
294 13:07:58.855998 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 13:07:58.856208 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 13:07:58.856298 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 13:07:58.856368 Setting prompt string to 'Starting depthcharge on Spherion...'
299 13:07:58.856427 Changing prompt to 'Starting depthcharge on Spherion...'
300 13:07:58.856492 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 13:07:58.856836 [Enter `^Ec?' for help]
302 13:08:00.090396
303 13:08:00.090528
304 13:08:00.090596 F0: 102B 0000
305 13:08:00.090659
306 13:08:00.090717 F3: 1001 0000 [0200]
307 13:08:00.090774
308 13:08:00.094405 F3: 1001 0000
309 13:08:00.094528
310 13:08:00.094587 F7: 102D 0000
311 13:08:00.094641
312 13:08:00.094693 F1: 0000 0000
313 13:08:00.094743
314 13:08:00.098097 V0: 0000 0000 [0001]
315 13:08:00.098176
316 13:08:00.098236 00: 0007 8000
317 13:08:00.098322
318 13:08:00.102257 01: 0000 0000
319 13:08:00.102341
320 13:08:00.102430 BP: 0C00 0209 [0000]
321 13:08:00.102484
322 13:08:00.102535 G0: 1182 0000
323 13:08:00.102603
324 13:08:00.106072 EC: 0000 0021 [4000]
325 13:08:00.106168
326 13:08:00.106227 S7: 0000 0000 [0000]
327 13:08:00.106281
328 13:08:00.109366 CC: 0000 0000 [0001]
329 13:08:00.109438
330 13:08:00.109511 T0: 0000 0040 [010F]
331 13:08:00.109578
332 13:08:00.112826 Jump to BL
333 13:08:00.112935
334 13:08:00.136859
335 13:08:00.136990
336 13:08:00.144497 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 13:08:00.147585 ARM64: Exception handlers installed.
338 13:08:00.151510 ARM64: Testing exception
339 13:08:00.155096 ARM64: Done test exception
340 13:08:00.163015 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 13:08:00.170309 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 13:08:00.177154 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 13:08:00.188570 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 13:08:00.196012 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 13:08:00.202964 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 13:08:00.214582 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 13:08:00.221722 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 13:08:00.241014 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 13:08:00.244964 WDT: Last reset was cold boot
350 13:08:00.248811 SPI1(PAD0) initialized at 2873684 Hz
351 13:08:00.252124 SPI5(PAD0) initialized at 992727 Hz
352 13:08:00.252214 VBOOT: Loading verstage.
353 13:08:00.259483 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 13:08:00.263057 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 13:08:00.266341 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 13:08:00.269695 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 13:08:00.277359 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 13:08:00.284219 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 13:08:00.294729 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 13:08:00.294851
361 13:08:00.294936
362 13:08:00.305300 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 13:08:00.308645 ARM64: Exception handlers installed.
364 13:08:00.311418 ARM64: Testing exception
365 13:08:00.311506 ARM64: Done test exception
366 13:08:00.318678 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 13:08:00.321584 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 13:08:00.335656 Probing TPM: . done!
369 13:08:00.335785 TPM ready after 0 ms
370 13:08:00.342781 Connected to device vid:did:rid of 1ae0:0028:00
371 13:08:00.350310 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 13:08:00.400081 Initialized TPM device CR50 revision 0
373 13:08:00.412065 tlcl_send_startup: Startup return code is 0
374 13:08:00.412191 TPM: setup succeeded
375 13:08:00.423655 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 13:08:00.432065 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 13:08:00.442428 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 13:08:00.450981 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 13:08:00.454417 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 13:08:00.457785 in-header: 03 07 00 00 08 00 00 00
381 13:08:00.461079 in-data: aa e4 47 04 13 02 00 00
382 13:08:00.464393 Chrome EC: UHEPI supported
383 13:08:00.471077 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 13:08:00.474427 in-header: 03 a9 00 00 08 00 00 00
385 13:08:00.477675 in-data: 84 60 60 08 00 00 00 00
386 13:08:00.477770 Phase 1
387 13:08:00.480880 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 13:08:00.487524 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 13:08:00.494347 VB2:vb2_check_recovery() Recovery was requested manually
390 13:08:00.497664 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 13:08:00.501499 Recovery requested (1009000e)
392 13:08:00.511901 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 13:08:00.514857 tlcl_extend: response is 0
394 13:08:00.523191 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 13:08:00.528647 tlcl_extend: response is 0
396 13:08:00.534566 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 13:08:00.555504 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 13:08:00.562433 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 13:08:00.562571
400 13:08:00.562663
401 13:08:00.572658 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 13:08:00.575784 ARM64: Exception handlers installed.
403 13:08:00.578636 ARM64: Testing exception
404 13:08:00.578723 ARM64: Done test exception
405 13:08:00.601145 pmic_efuse_setting: Set efuses in 11 msecs
406 13:08:00.604556 pmwrap_interface_init: Select PMIF_VLD_RDY
407 13:08:00.611169 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 13:08:00.614401 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 13:08:00.621389 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 13:08:00.624941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 13:08:00.631193 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 13:08:00.634257 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 13:08:00.637527 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 13:08:00.644262 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 13:08:00.647654 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 13:08:00.654595 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 13:08:00.657870 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 13:08:00.661356 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 13:08:00.668261 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 13:08:00.674594 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 13:08:00.678309 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 13:08:00.684789 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 13:08:00.691613 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 13:08:00.694833 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 13:08:00.701293 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 13:08:00.708093 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 13:08:00.711392 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 13:08:00.718056 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 13:08:00.724788 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 13:08:00.728135 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 13:08:00.734941 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 13:08:00.741689 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 13:08:00.745346 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 13:08:00.751888 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 13:08:00.755030 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 13:08:00.758294 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 13:08:00.765018 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 13:08:00.771661 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 13:08:00.775070 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 13:08:00.782166 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 13:08:00.785213 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 13:08:00.788518 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 13:08:00.795635 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 13:08:00.799243 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 13:08:00.805921 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 13:08:00.809591 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 13:08:00.812711 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 13:08:00.816266 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 13:08:00.822977 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 13:08:00.826409 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 13:08:00.829188 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 13:08:00.836482 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 13:08:00.839184 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 13:08:00.842891 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 13:08:00.849459 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 13:08:00.852899 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 13:08:00.856114 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 13:08:00.862947 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 13:08:00.872659 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 13:08:00.875890 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 13:08:00.885911 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 13:08:00.892852 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 13:08:00.899561 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 13:08:00.902855 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:08:00.906282 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 13:08:00.913749 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 13:08:00.920881 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 13:08:00.924361 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 13:08:00.927957 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 13:08:00.938532 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 13:08:00.947864 [RTC]rtc_get_frequency_meter,154: input=23, output=941
472 13:08:00.958099 [RTC]rtc_get_frequency_meter,154: input=19, output=851
473 13:08:00.966659 [RTC]rtc_get_frequency_meter,154: input=17, output=804
474 13:08:00.976366 [RTC]rtc_get_frequency_meter,154: input=16, output=783
475 13:08:00.986245 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 13:08:00.995529 [RTC]rtc_get_frequency_meter,154: input=17, output=803
477 13:08:00.998872 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 13:08:01.006085 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 13:08:01.009425 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 13:08:01.012863 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 13:08:01.019360 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 13:08:01.022611 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 13:08:01.025824 ADC[4]: Raw value=905465 ID=7
484 13:08:01.025936 ADC[3]: Raw value=213441 ID=1
485 13:08:01.029206 RAM Code: 0x71
486 13:08:01.033102 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 13:08:01.039603 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 13:08:01.046051 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 13:08:01.053198 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 13:08:01.056329 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 13:08:01.059622 in-header: 03 07 00 00 08 00 00 00
492 13:08:01.062610 in-data: aa e4 47 04 13 02 00 00
493 13:08:01.066615 Chrome EC: UHEPI supported
494 13:08:01.073279 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 13:08:01.076604 in-header: 03 a9 00 00 08 00 00 00
496 13:08:01.079830 in-data: 84 60 60 08 00 00 00 00
497 13:08:01.082845 MRC: failed to locate region type 0.
498 13:08:01.089885 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 13:08:01.093365 DRAM-K: Running full calibration
500 13:08:01.100090 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 13:08:01.100219 header.status = 0x0
502 13:08:01.103542 header.version = 0x6 (expected: 0x6)
503 13:08:01.106162 header.size = 0xd00 (expected: 0xd00)
504 13:08:01.109851 header.flags = 0x0
505 13:08:01.116465 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 13:08:01.133066 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 13:08:01.140330 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 13:08:01.143594 dram_init: ddr_geometry: 2
509 13:08:01.143706 [EMI] MDL number = 2
510 13:08:01.147054 [EMI] Get MDL freq = 0
511 13:08:01.150412 dram_init: ddr_type: 0
512 13:08:01.150525 is_discrete_lpddr4: 1
513 13:08:01.153487 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 13:08:01.153600
515 13:08:01.153686
516 13:08:01.157266 [Bian_co] ETT version 0.0.0.1
517 13:08:01.163714 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 13:08:01.163845
519 13:08:01.167018 dramc_set_vcore_voltage set vcore to 650000
520 13:08:01.167130 Read voltage for 800, 4
521 13:08:01.170121 Vio18 = 0
522 13:08:01.170218 Vcore = 650000
523 13:08:01.170280 Vdram = 0
524 13:08:01.173794 Vddq = 0
525 13:08:01.173910 Vmddr = 0
526 13:08:01.176835 dram_init: config_dvfs: 1
527 13:08:01.180103 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 13:08:01.186859 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 13:08:01.190153 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 13:08:01.193948 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 13:08:01.196927 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 13:08:01.200773 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 13:08:01.204066 MEM_TYPE=3, freq_sel=18
534 13:08:01.207473 sv_algorithm_assistance_LP4_1600
535 13:08:01.210670 ============ PULL DRAM RESETB DOWN ============
536 13:08:01.214139 ========== PULL DRAM RESETB DOWN end =========
537 13:08:01.220749 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 13:08:01.224053 ===================================
539 13:08:01.224175 LPDDR4 DRAM CONFIGURATION
540 13:08:01.227465 ===================================
541 13:08:01.230772 EX_ROW_EN[0] = 0x0
542 13:08:01.233792 EX_ROW_EN[1] = 0x0
543 13:08:01.233897 LP4Y_EN = 0x0
544 13:08:01.237254 WORK_FSP = 0x0
545 13:08:01.237353 WL = 0x2
546 13:08:01.240644 RL = 0x2
547 13:08:01.240745 BL = 0x2
548 13:08:01.243657 RPST = 0x0
549 13:08:01.243756 RD_PRE = 0x0
550 13:08:01.247016 WR_PRE = 0x1
551 13:08:01.247119 WR_PST = 0x0
552 13:08:01.250417 DBI_WR = 0x0
553 13:08:01.250510 DBI_RD = 0x0
554 13:08:01.253706 OTF = 0x1
555 13:08:01.257116 ===================================
556 13:08:01.260632 ===================================
557 13:08:01.260731 ANA top config
558 13:08:01.263919 ===================================
559 13:08:01.267250 DLL_ASYNC_EN = 0
560 13:08:01.270960 ALL_SLAVE_EN = 1
561 13:08:01.271049 NEW_RANK_MODE = 1
562 13:08:01.273930 DLL_IDLE_MODE = 1
563 13:08:01.277489 LP45_APHY_COMB_EN = 1
564 13:08:01.281042 TX_ODT_DIS = 1
565 13:08:01.281155 NEW_8X_MODE = 1
566 13:08:01.284197 ===================================
567 13:08:01.287185 ===================================
568 13:08:01.290847 data_rate = 1600
569 13:08:01.294478 CKR = 1
570 13:08:01.297492 DQ_P2S_RATIO = 8
571 13:08:01.300881 ===================================
572 13:08:01.304553 CA_P2S_RATIO = 8
573 13:08:01.307734 DQ_CA_OPEN = 0
574 13:08:01.307842 DQ_SEMI_OPEN = 0
575 13:08:01.310901 CA_SEMI_OPEN = 0
576 13:08:01.314194 CA_FULL_RATE = 0
577 13:08:01.317723 DQ_CKDIV4_EN = 1
578 13:08:01.321012 CA_CKDIV4_EN = 1
579 13:08:01.321115 CA_PREDIV_EN = 0
580 13:08:01.324815 PH8_DLY = 0
581 13:08:01.327921 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 13:08:01.331246 DQ_AAMCK_DIV = 4
583 13:08:01.334577 CA_AAMCK_DIV = 4
584 13:08:01.337718 CA_ADMCK_DIV = 4
585 13:08:01.337821 DQ_TRACK_CA_EN = 0
586 13:08:01.341153 CA_PICK = 800
587 13:08:01.344447 CA_MCKIO = 800
588 13:08:01.347848 MCKIO_SEMI = 0
589 13:08:01.351093 PLL_FREQ = 3068
590 13:08:01.354446 DQ_UI_PI_RATIO = 32
591 13:08:01.357869 CA_UI_PI_RATIO = 0
592 13:08:01.361294 ===================================
593 13:08:01.364696 ===================================
594 13:08:01.364798 memory_type:LPDDR4
595 13:08:01.368096 GP_NUM : 10
596 13:08:01.368193 SRAM_EN : 1
597 13:08:01.371413 MD32_EN : 0
598 13:08:01.374764 ===================================
599 13:08:01.378147 [ANA_INIT] >>>>>>>>>>>>>>
600 13:08:01.381356 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 13:08:01.385149 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 13:08:01.388204 ===================================
603 13:08:01.388292 data_rate = 1600,PCW = 0X7600
604 13:08:01.391669 ===================================
605 13:08:01.395391 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 13:08:01.401602 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 13:08:01.408536 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 13:08:01.411528 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 13:08:01.415066 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 13:08:01.418686 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 13:08:01.421684 [ANA_INIT] flow start
612 13:08:01.421788 [ANA_INIT] PLL >>>>>>>>
613 13:08:01.425581 [ANA_INIT] PLL <<<<<<<<
614 13:08:01.428304 [ANA_INIT] MIDPI >>>>>>>>
615 13:08:01.431619 [ANA_INIT] MIDPI <<<<<<<<
616 13:08:01.431700 [ANA_INIT] DLL >>>>>>>>
617 13:08:01.435487 [ANA_INIT] flow end
618 13:08:01.438388 ============ LP4 DIFF to SE enter ============
619 13:08:01.441849 ============ LP4 DIFF to SE exit ============
620 13:08:01.445113 [ANA_INIT] <<<<<<<<<<<<<
621 13:08:01.448434 [Flow] Enable top DCM control >>>>>
622 13:08:01.451886 [Flow] Enable top DCM control <<<<<
623 13:08:01.455189 Enable DLL master slave shuffle
624 13:08:01.458435 ==============================================================
625 13:08:01.461917 Gating Mode config
626 13:08:01.468585 ==============================================================
627 13:08:01.468690 Config description:
628 13:08:01.478650 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 13:08:01.485410 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 13:08:01.488769 SELPH_MODE 0: By rank 1: By Phase
631 13:08:01.495334 ==============================================================
632 13:08:01.499127 GAT_TRACK_EN = 1
633 13:08:01.502091 RX_GATING_MODE = 2
634 13:08:01.505943 RX_GATING_TRACK_MODE = 2
635 13:08:01.508948 SELPH_MODE = 1
636 13:08:01.512077 PICG_EARLY_EN = 1
637 13:08:01.512172 VALID_LAT_VALUE = 1
638 13:08:01.519379 ==============================================================
639 13:08:01.521933 Enter into Gating configuration >>>>
640 13:08:01.525582 Exit from Gating configuration <<<<
641 13:08:01.528689 Enter into DVFS_PRE_config >>>>>
642 13:08:01.538995 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 13:08:01.542341 Exit from DVFS_PRE_config <<<<<
644 13:08:01.545618 Enter into PICG configuration >>>>
645 13:08:01.548793 Exit from PICG configuration <<<<
646 13:08:01.552316 [RX_INPUT] configuration >>>>>
647 13:08:01.555929 [RX_INPUT] configuration <<<<<
648 13:08:01.559267 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 13:08:01.565903 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 13:08:01.572688 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 13:08:01.579466 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 13:08:01.585575 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 13:08:01.589608 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 13:08:01.593126 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 13:08:01.599961 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 13:08:01.604025 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 13:08:01.608164 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 13:08:01.611199 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 13:08:01.615606 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 13:08:01.618757 ===================================
661 13:08:01.622524 LPDDR4 DRAM CONFIGURATION
662 13:08:01.626235 ===================================
663 13:08:01.626332 EX_ROW_EN[0] = 0x0
664 13:08:01.629631 EX_ROW_EN[1] = 0x0
665 13:08:01.629712 LP4Y_EN = 0x0
666 13:08:01.633042 WORK_FSP = 0x0
667 13:08:01.633127 WL = 0x2
668 13:08:01.636277 RL = 0x2
669 13:08:01.636359 BL = 0x2
670 13:08:01.639499 RPST = 0x0
671 13:08:01.639579 RD_PRE = 0x0
672 13:08:01.642869 WR_PRE = 0x1
673 13:08:01.642952 WR_PST = 0x0
674 13:08:01.646311 DBI_WR = 0x0
675 13:08:01.646387 DBI_RD = 0x0
676 13:08:01.649291 OTF = 0x1
677 13:08:01.652458 ===================================
678 13:08:01.656346 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 13:08:01.659410 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 13:08:01.666078 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 13:08:01.669900 ===================================
682 13:08:01.670026 LPDDR4 DRAM CONFIGURATION
683 13:08:01.673157 ===================================
684 13:08:01.676428 EX_ROW_EN[0] = 0x10
685 13:08:01.676507 EX_ROW_EN[1] = 0x0
686 13:08:01.679824 LP4Y_EN = 0x0
687 13:08:01.679903 WORK_FSP = 0x0
688 13:08:01.683303 WL = 0x2
689 13:08:01.686856 RL = 0x2
690 13:08:01.686937 BL = 0x2
691 13:08:01.689570 RPST = 0x0
692 13:08:01.689639 RD_PRE = 0x0
693 13:08:01.692899 WR_PRE = 0x1
694 13:08:01.692975 WR_PST = 0x0
695 13:08:01.696342 DBI_WR = 0x0
696 13:08:01.696418 DBI_RD = 0x0
697 13:08:01.699624 OTF = 0x1
698 13:08:01.703287 ===================================
699 13:08:01.706584 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 13:08:01.712024 nWR fixed to 40
701 13:08:01.715146 [ModeRegInit_LP4] CH0 RK0
702 13:08:01.715267 [ModeRegInit_LP4] CH0 RK1
703 13:08:01.718252 [ModeRegInit_LP4] CH1 RK0
704 13:08:01.722384 [ModeRegInit_LP4] CH1 RK1
705 13:08:01.722499 match AC timing 13
706 13:08:01.728446 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 13:08:01.732294 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 13:08:01.735398 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 13:08:01.742172 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 13:08:01.745579 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 13:08:01.745712 [EMI DOE] emi_dcm 0
712 13:08:01.752155 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 13:08:01.752261 ==
714 13:08:01.755131 Dram Type= 6, Freq= 0, CH_0, rank 0
715 13:08:01.758443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 13:08:01.758524 ==
717 13:08:01.765703 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 13:08:01.768730 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 13:08:01.779445 [CA 0] Center 36 (6~67) winsize 62
720 13:08:01.782687 [CA 1] Center 36 (6~67) winsize 62
721 13:08:01.785918 [CA 2] Center 34 (4~65) winsize 62
722 13:08:01.789510 [CA 3] Center 33 (3~64) winsize 62
723 13:08:01.792430 [CA 4] Center 33 (3~63) winsize 61
724 13:08:01.796475 [CA 5] Center 33 (3~63) winsize 61
725 13:08:01.796594
726 13:08:01.800090 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 13:08:01.800207
728 13:08:01.803485 [CATrainingPosCal] consider 1 rank data
729 13:08:01.806291 u2DelayCellTimex100 = 270/100 ps
730 13:08:01.809858 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
731 13:08:01.813380 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
732 13:08:01.816717 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 13:08:01.820224 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
734 13:08:01.826766 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
735 13:08:01.830102 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
736 13:08:01.830222
737 13:08:01.832875 CA PerBit enable=1, Macro0, CA PI delay=33
738 13:08:01.832984
739 13:08:01.836352 [CBTSetCACLKResult] CA Dly = 33
740 13:08:01.836443 CS Dly: 4 (0~35)
741 13:08:01.836504 ==
742 13:08:01.839768 Dram Type= 6, Freq= 0, CH_0, rank 1
743 13:08:01.843058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 13:08:01.846482 ==
745 13:08:01.849521 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 13:08:01.856556 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 13:08:01.865360 [CA 0] Center 36 (6~67) winsize 62
748 13:08:01.868481 [CA 1] Center 36 (6~67) winsize 62
749 13:08:01.872289 [CA 2] Center 34 (4~65) winsize 62
750 13:08:01.875630 [CA 3] Center 34 (4~65) winsize 62
751 13:08:01.878968 [CA 4] Center 33 (2~64) winsize 63
752 13:08:01.881893 [CA 5] Center 32 (2~63) winsize 62
753 13:08:01.882001
754 13:08:01.885553 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 13:08:01.885655
756 13:08:01.888927 [CATrainingPosCal] consider 2 rank data
757 13:08:01.892384 u2DelayCellTimex100 = 270/100 ps
758 13:08:01.895789 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
759 13:08:01.898863 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
760 13:08:01.901981 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 13:08:01.909383 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
762 13:08:01.912104 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
763 13:08:01.915597 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
764 13:08:01.915690
765 13:08:01.918904 CA PerBit enable=1, Macro0, CA PI delay=33
766 13:08:01.918992
767 13:08:01.922237 [CBTSetCACLKResult] CA Dly = 33
768 13:08:01.922321 CS Dly: 5 (0~37)
769 13:08:01.922382
770 13:08:01.925629 ----->DramcWriteLeveling(PI) begin...
771 13:08:01.925742 ==
772 13:08:01.929084 Dram Type= 6, Freq= 0, CH_0, rank 0
773 13:08:01.936038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 13:08:01.936191 ==
775 13:08:01.939415 Write leveling (Byte 0): 33 => 33
776 13:08:01.939522 Write leveling (Byte 1): 33 => 33
777 13:08:01.942826 DramcWriteLeveling(PI) end<-----
778 13:08:01.942926
779 13:08:01.946188 ==
780 13:08:01.946287 Dram Type= 6, Freq= 0, CH_0, rank 0
781 13:08:01.952365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 13:08:01.952481 ==
783 13:08:01.955592 [Gating] SW mode calibration
784 13:08:01.962433 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 13:08:01.965781 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 13:08:01.972683 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 13:08:01.975926 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 13:08:01.979114 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 13:08:01.985789 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:08:01.989144 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:08:01.992420 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:08:01.996230 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:08:02.002463 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:08:02.005969 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:08:02.009135 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:08:02.016185 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:08:02.019297 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:08:02.022791 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:08:02.029371 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:08:02.032631 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:08:02.035974 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:08:02.042484 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 13:08:02.046167 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 13:08:02.049444 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 13:08:02.056192 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 13:08:02.059366 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:08:02.062747 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:08:02.066262 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:08:02.072828 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:08:02.076215 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 13:08:02.079909 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 13:08:02.085890 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
813 13:08:02.089354 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
814 13:08:02.092806 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 13:08:02.099665 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 13:08:02.102943 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 13:08:02.106124 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 13:08:02.112884 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 13:08:02.116924 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (1 0)
820 13:08:02.119666 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
821 13:08:02.126481 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 13:08:02.130238 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 13:08:02.133098 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 13:08:02.136283 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 13:08:02.143084 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 13:08:02.146329 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 13:08:02.150128 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 13:08:02.156270 0 11 8 | B1->B0 | 2d2d 4343 | 0 0 | (0 0) (0 0)
829 13:08:02.159715 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
830 13:08:02.163141 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 13:08:02.169882 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 13:08:02.173919 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 13:08:02.177405 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 13:08:02.180616 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 13:08:02.187610 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 13:08:02.190404 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
837 13:08:02.193686 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 13:08:02.200477 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:08:02.204059 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:08:02.207478 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:08:02.213952 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:08:02.217182 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:08:02.220510 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:08:02.227458 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:08:02.230712 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:08:02.233915 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:08:02.237237 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:08:02.243907 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:08:02.247763 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:08:02.250929 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:08:02.257405 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 13:08:02.260835 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 13:08:02.264215 Total UI for P1: 0, mck2ui 16
854 13:08:02.267558 best dqsien dly found for B0: ( 0, 14, 6)
855 13:08:02.271026 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 13:08:02.274320 Total UI for P1: 0, mck2ui 16
857 13:08:02.277698 best dqsien dly found for B1: ( 0, 14, 8)
858 13:08:02.281067 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 13:08:02.284522 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 13:08:02.284629
861 13:08:02.287904 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 13:08:02.294301 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 13:08:02.294395 [Gating] SW calibration Done
864 13:08:02.294487 ==
865 13:08:02.297565 Dram Type= 6, Freq= 0, CH_0, rank 0
866 13:08:02.304372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 13:08:02.304490 ==
868 13:08:02.304582 RX Vref Scan: 0
869 13:08:02.304722
870 13:08:02.308272 RX Vref 0 -> 0, step: 1
871 13:08:02.308377
872 13:08:02.310956 RX Delay -130 -> 252, step: 16
873 13:08:02.314907 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
874 13:08:02.318075 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
875 13:08:02.321091 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
876 13:08:02.328124 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
877 13:08:02.331434 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
878 13:08:02.334350 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
879 13:08:02.338215 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
880 13:08:02.341430 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
881 13:08:02.344778 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
882 13:08:02.351229 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
883 13:08:02.355132 iDelay=206, Bit 10, Center 85 (-18 ~ 189) 208
884 13:08:02.358223 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
885 13:08:02.361242 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
886 13:08:02.364755 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
887 13:08:02.371467 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
888 13:08:02.374831 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
889 13:08:02.374928 ==
890 13:08:02.378237 Dram Type= 6, Freq= 0, CH_0, rank 0
891 13:08:02.381711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 13:08:02.381857 ==
893 13:08:02.385180 DQS Delay:
894 13:08:02.385317 DQS0 = 0, DQS1 = 0
895 13:08:02.385408 DQM Delay:
896 13:08:02.388558 DQM0 = 90, DQM1 = 86
897 13:08:02.388695 DQ Delay:
898 13:08:02.391951 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =93
899 13:08:02.395255 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
900 13:08:02.398370 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
901 13:08:02.401500 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
902 13:08:02.401614
903 13:08:02.401703
904 13:08:02.401786 ==
905 13:08:02.404801 Dram Type= 6, Freq= 0, CH_0, rank 0
906 13:08:02.408315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 13:08:02.412243 ==
908 13:08:02.412339
909 13:08:02.412411
910 13:08:02.412498 TX Vref Scan disable
911 13:08:02.415438 == TX Byte 0 ==
912 13:08:02.418760 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
913 13:08:02.421990 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
914 13:08:02.425378 == TX Byte 1 ==
915 13:08:02.428752 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
916 13:08:02.431991 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
917 13:08:02.432078 ==
918 13:08:02.435014 Dram Type= 6, Freq= 0, CH_0, rank 0
919 13:08:02.441519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 13:08:02.441651 ==
921 13:08:02.453703 TX Vref=22, minBit 8, minWin=27, winSum=447
922 13:08:02.456974 TX Vref=24, minBit 8, minWin=27, winSum=448
923 13:08:02.460545 TX Vref=26, minBit 10, minWin=27, winSum=454
924 13:08:02.463643 TX Vref=28, minBit 10, minWin=27, winSum=454
925 13:08:02.467357 TX Vref=30, minBit 4, minWin=28, winSum=455
926 13:08:02.474020 TX Vref=32, minBit 11, minWin=27, winSum=451
927 13:08:02.477328 [TxChooseVref] Worse bit 4, Min win 28, Win sum 455, Final Vref 30
928 13:08:02.477448
929 13:08:02.480708 Final TX Range 1 Vref 30
930 13:08:02.480814
931 13:08:02.480905 ==
932 13:08:02.483869 Dram Type= 6, Freq= 0, CH_0, rank 0
933 13:08:02.487345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 13:08:02.487434 ==
935 13:08:02.490684
936 13:08:02.490766
937 13:08:02.490826 TX Vref Scan disable
938 13:08:02.494203 == TX Byte 0 ==
939 13:08:02.496926 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
940 13:08:02.500376 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
941 13:08:02.503750 == TX Byte 1 ==
942 13:08:02.507053 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
943 13:08:02.510595 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
944 13:08:02.513803
945 13:08:02.513925 [DATLAT]
946 13:08:02.514028 Freq=800, CH0 RK0
947 13:08:02.514089
948 13:08:02.517222 DATLAT Default: 0xa
949 13:08:02.517303 0, 0xFFFF, sum = 0
950 13:08:02.520611 1, 0xFFFF, sum = 0
951 13:08:02.520695 2, 0xFFFF, sum = 0
952 13:08:02.524036 3, 0xFFFF, sum = 0
953 13:08:02.524127 4, 0xFFFF, sum = 0
954 13:08:02.527331 5, 0xFFFF, sum = 0
955 13:08:02.527450 6, 0xFFFF, sum = 0
956 13:08:02.530743 7, 0xFFFF, sum = 0
957 13:08:02.534146 8, 0xFFFF, sum = 0
958 13:08:02.534245 9, 0x0, sum = 1
959 13:08:02.534308 10, 0x0, sum = 2
960 13:08:02.537536 11, 0x0, sum = 3
961 13:08:02.537630 12, 0x0, sum = 4
962 13:08:02.540848 best_step = 10
963 13:08:02.540971
964 13:08:02.541060 ==
965 13:08:02.544251 Dram Type= 6, Freq= 0, CH_0, rank 0
966 13:08:02.547431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 13:08:02.547556 ==
968 13:08:02.550449 RX Vref Scan: 1
969 13:08:02.550557
970 13:08:02.550654 Set Vref Range= 32 -> 127
971 13:08:02.550737
972 13:08:02.554141 RX Vref 32 -> 127, step: 1
973 13:08:02.554247
974 13:08:02.557626 RX Delay -79 -> 252, step: 8
975 13:08:02.557735
976 13:08:02.560786 Set Vref, RX VrefLevel [Byte0]: 32
977 13:08:02.564291 [Byte1]: 32
978 13:08:02.564377
979 13:08:02.567132 Set Vref, RX VrefLevel [Byte0]: 33
980 13:08:02.570624 [Byte1]: 33
981 13:08:02.574187
982 13:08:02.574279 Set Vref, RX VrefLevel [Byte0]: 34
983 13:08:02.577029 [Byte1]: 34
984 13:08:02.581612
985 13:08:02.581707 Set Vref, RX VrefLevel [Byte0]: 35
986 13:08:02.585095 [Byte1]: 35
987 13:08:02.589557
988 13:08:02.589648 Set Vref, RX VrefLevel [Byte0]: 36
989 13:08:02.592168 [Byte1]: 36
990 13:08:02.596409
991 13:08:02.596532 Set Vref, RX VrefLevel [Byte0]: 37
992 13:08:02.599751 [Byte1]: 37
993 13:08:02.604488
994 13:08:02.604609 Set Vref, RX VrefLevel [Byte0]: 38
995 13:08:02.608032 [Byte1]: 38
996 13:08:02.612027
997 13:08:02.612116 Set Vref, RX VrefLevel [Byte0]: 39
998 13:08:02.615362 [Byte1]: 39
999 13:08:02.619272
1000 13:08:02.619359 Set Vref, RX VrefLevel [Byte0]: 40
1001 13:08:02.622669 [Byte1]: 40
1002 13:08:02.627047
1003 13:08:02.627140 Set Vref, RX VrefLevel [Byte0]: 41
1004 13:08:02.630253 [Byte1]: 41
1005 13:08:02.634442
1006 13:08:02.634521 Set Vref, RX VrefLevel [Byte0]: 42
1007 13:08:02.637923 [Byte1]: 42
1008 13:08:02.642096
1009 13:08:02.642174 Set Vref, RX VrefLevel [Byte0]: 43
1010 13:08:02.645411 [Byte1]: 43
1011 13:08:02.649478
1012 13:08:02.649587 Set Vref, RX VrefLevel [Byte0]: 44
1013 13:08:02.653029 [Byte1]: 44
1014 13:08:02.657544
1015 13:08:02.657650 Set Vref, RX VrefLevel [Byte0]: 45
1016 13:08:02.660572 [Byte1]: 45
1017 13:08:02.664400
1018 13:08:02.664481 Set Vref, RX VrefLevel [Byte0]: 46
1019 13:08:02.667687 [Byte1]: 46
1020 13:08:02.672432
1021 13:08:02.672503 Set Vref, RX VrefLevel [Byte0]: 47
1022 13:08:02.675693 [Byte1]: 47
1023 13:08:02.679630
1024 13:08:02.679734 Set Vref, RX VrefLevel [Byte0]: 48
1025 13:08:02.682769 [Byte1]: 48
1026 13:08:02.687567
1027 13:08:02.687648 Set Vref, RX VrefLevel [Byte0]: 49
1028 13:08:02.690869 [Byte1]: 49
1029 13:08:02.694788
1030 13:08:02.694868 Set Vref, RX VrefLevel [Byte0]: 50
1031 13:08:02.697901 [Byte1]: 50
1032 13:08:02.702361
1033 13:08:02.702467 Set Vref, RX VrefLevel [Byte0]: 51
1034 13:08:02.705481 [Byte1]: 51
1035 13:08:02.709720
1036 13:08:02.709799 Set Vref, RX VrefLevel [Byte0]: 52
1037 13:08:02.713189 [Byte1]: 52
1038 13:08:02.717527
1039 13:08:02.717607 Set Vref, RX VrefLevel [Byte0]: 53
1040 13:08:02.720967 [Byte1]: 53
1041 13:08:02.725399
1042 13:08:02.725507 Set Vref, RX VrefLevel [Byte0]: 54
1043 13:08:02.728813 [Byte1]: 54
1044 13:08:02.732506
1045 13:08:02.732585 Set Vref, RX VrefLevel [Byte0]: 55
1046 13:08:02.735997 [Byte1]: 55
1047 13:08:02.740545
1048 13:08:02.740654 Set Vref, RX VrefLevel [Byte0]: 56
1049 13:08:02.743273 [Byte1]: 56
1050 13:08:02.748025
1051 13:08:02.748104 Set Vref, RX VrefLevel [Byte0]: 57
1052 13:08:02.750842 [Byte1]: 57
1053 13:08:02.755612
1054 13:08:02.755691 Set Vref, RX VrefLevel [Byte0]: 58
1055 13:08:02.758429 [Byte1]: 58
1056 13:08:02.763110
1057 13:08:02.763189 Set Vref, RX VrefLevel [Byte0]: 59
1058 13:08:02.766414 [Byte1]: 59
1059 13:08:02.770369
1060 13:08:02.770448 Set Vref, RX VrefLevel [Byte0]: 60
1061 13:08:02.773376 [Byte1]: 60
1062 13:08:02.777992
1063 13:08:02.778105 Set Vref, RX VrefLevel [Byte0]: 61
1064 13:08:02.781230 [Byte1]: 61
1065 13:08:02.785206
1066 13:08:02.785303 Set Vref, RX VrefLevel [Byte0]: 62
1067 13:08:02.788480 [Byte1]: 62
1068 13:08:02.792694
1069 13:08:02.792797 Set Vref, RX VrefLevel [Byte0]: 63
1070 13:08:02.796119 [Byte1]: 63
1071 13:08:02.800377
1072 13:08:02.800482 Set Vref, RX VrefLevel [Byte0]: 64
1073 13:08:02.803699 [Byte1]: 64
1074 13:08:02.808398
1075 13:08:02.808479 Set Vref, RX VrefLevel [Byte0]: 65
1076 13:08:02.811610 [Byte1]: 65
1077 13:08:02.815692
1078 13:08:02.815798 Set Vref, RX VrefLevel [Byte0]: 66
1079 13:08:02.818937 [Byte1]: 66
1080 13:08:02.823203
1081 13:08:02.823308 Set Vref, RX VrefLevel [Byte0]: 67
1082 13:08:02.826765 [Byte1]: 67
1083 13:08:02.830888
1084 13:08:02.830967 Set Vref, RX VrefLevel [Byte0]: 68
1085 13:08:02.833785 [Byte1]: 68
1086 13:08:02.838388
1087 13:08:02.838468 Set Vref, RX VrefLevel [Byte0]: 69
1088 13:08:02.841557 [Byte1]: 69
1089 13:08:02.845868
1090 13:08:02.845971 Set Vref, RX VrefLevel [Byte0]: 70
1091 13:08:02.848858 [Byte1]: 70
1092 13:08:02.853560
1093 13:08:02.853639 Set Vref, RX VrefLevel [Byte0]: 71
1094 13:08:02.857011 [Byte1]: 71
1095 13:08:02.861162
1096 13:08:02.861265 Set Vref, RX VrefLevel [Byte0]: 72
1097 13:08:02.864476 [Byte1]: 72
1098 13:08:02.868522
1099 13:08:02.868631 Set Vref, RX VrefLevel [Byte0]: 73
1100 13:08:02.871968 [Byte1]: 73
1101 13:08:02.875960
1102 13:08:02.876040 Set Vref, RX VrefLevel [Byte0]: 74
1103 13:08:02.879522 [Byte1]: 74
1104 13:08:02.883282
1105 13:08:02.883371 Set Vref, RX VrefLevel [Byte0]: 75
1106 13:08:02.886585 [Byte1]: 75
1107 13:08:02.891492
1108 13:08:02.891585 Set Vref, RX VrefLevel [Byte0]: 76
1109 13:08:02.894734 [Byte1]: 76
1110 13:08:02.898436
1111 13:08:02.898516 Set Vref, RX VrefLevel [Byte0]: 77
1112 13:08:02.901892 [Byte1]: 77
1113 13:08:02.906524
1114 13:08:02.906609 Set Vref, RX VrefLevel [Byte0]: 78
1115 13:08:02.909793 [Byte1]: 78
1116 13:08:02.913767
1117 13:08:02.913875 Final RX Vref Byte 0 = 58 to rank0
1118 13:08:02.917329 Final RX Vref Byte 1 = 57 to rank0
1119 13:08:02.920859 Final RX Vref Byte 0 = 58 to rank1
1120 13:08:02.923500 Final RX Vref Byte 1 = 57 to rank1==
1121 13:08:02.926945 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 13:08:02.933627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 13:08:02.933737 ==
1124 13:08:02.933839 DQS Delay:
1125 13:08:02.933923 DQS0 = 0, DQS1 = 0
1126 13:08:02.936780 DQM Delay:
1127 13:08:02.936883 DQM0 = 92, DQM1 = 85
1128 13:08:02.940538 DQ Delay:
1129 13:08:02.943522 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1130 13:08:02.947065 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1131 13:08:02.947181 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76
1132 13:08:02.953949 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1133 13:08:02.954047
1134 13:08:02.954109
1135 13:08:02.960792 [DQSOSCAuto] RK0, (LSB)MR18= 0x5147, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
1136 13:08:02.963832 CH0 RK0: MR19=606, MR18=5147
1137 13:08:02.970704 CH0_RK0: MR19=0x606, MR18=0x5147, DQSOSC=389, MR23=63, INC=97, DEC=65
1138 13:08:02.970816
1139 13:08:02.974060 ----->DramcWriteLeveling(PI) begin...
1140 13:08:02.974159 ==
1141 13:08:02.977400 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 13:08:02.980655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 13:08:02.980761 ==
1144 13:08:02.984142 Write leveling (Byte 0): 33 => 33
1145 13:08:02.987395 Write leveling (Byte 1): 30 => 30
1146 13:08:02.990550 DramcWriteLeveling(PI) end<-----
1147 13:08:02.990652
1148 13:08:02.990739 ==
1149 13:08:02.994059 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 13:08:02.997396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 13:08:02.997489 ==
1152 13:08:03.000755 [Gating] SW mode calibration
1153 13:08:03.007095 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 13:08:03.054508 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 13:08:03.054650 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 13:08:03.055125 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1157 13:08:03.055413 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1158 13:08:03.055511 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 13:08:03.055614 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 13:08:03.055701 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 13:08:03.055798 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 13:08:03.056065 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:08:03.056152 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 13:08:03.098772 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 13:08:03.098897 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 13:08:03.099349 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 13:08:03.099606 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 13:08:03.099670 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 13:08:03.099738 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 13:08:03.099795 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 13:08:03.099857 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 13:08:03.100548 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1173 13:08:03.100782 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1174 13:08:03.124555 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 13:08:03.124673 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 13:08:03.124736 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 13:08:03.124977 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 13:08:03.125038 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 13:08:03.128291 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 13:08:03.128370 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 13:08:03.131614 0 9 8 | B1->B0 | 2e2e 2b2a | 1 1 | (1 1) (0 0)
1182 13:08:03.135196 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 13:08:03.141270 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 13:08:03.144556 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 13:08:03.147995 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 13:08:03.154705 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 13:08:03.158017 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 13:08:03.161350 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
1189 13:08:03.168363 0 10 8 | B1->B0 | 2727 2424 | 0 0 | (1 0) (0 0)
1190 13:08:03.171834 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 13:08:03.175149 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 13:08:03.178551 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 13:08:03.185190 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 13:08:03.188622 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 13:08:03.191662 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 13:08:03.198262 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 13:08:03.202183 0 11 8 | B1->B0 | 4545 3a3a | 0 0 | (0 0) (0 0)
1198 13:08:03.205165 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 13:08:03.211944 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 13:08:03.214816 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 13:08:03.218180 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 13:08:03.225459 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 13:08:03.228899 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 13:08:03.231918 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 13:08:03.238639 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1206 13:08:03.242017 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:08:03.245274 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 13:08:03.248608 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 13:08:03.255531 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 13:08:03.258831 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 13:08:03.262274 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 13:08:03.268393 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 13:08:03.272092 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 13:08:03.275456 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 13:08:03.282131 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 13:08:03.285590 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 13:08:03.289001 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 13:08:03.295164 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 13:08:03.298600 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 13:08:03.301956 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1221 13:08:03.309011 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1222 13:08:03.312210 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 13:08:03.315596 Total UI for P1: 0, mck2ui 16
1224 13:08:03.319030 best dqsien dly found for B0: ( 0, 14, 8)
1225 13:08:03.322131 Total UI for P1: 0, mck2ui 16
1226 13:08:03.325301 best dqsien dly found for B1: ( 0, 14, 6)
1227 13:08:03.328791 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1228 13:08:03.332170 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1229 13:08:03.332249
1230 13:08:03.335739 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1231 13:08:03.339007 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1232 13:08:03.342167 [Gating] SW calibration Done
1233 13:08:03.342265 ==
1234 13:08:03.345228 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 13:08:03.348660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 13:08:03.348759 ==
1237 13:08:03.352030 RX Vref Scan: 0
1238 13:08:03.352140
1239 13:08:03.352237 RX Vref 0 -> 0, step: 1
1240 13:08:03.355395
1241 13:08:03.355497 RX Delay -130 -> 252, step: 16
1242 13:08:03.362136 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1243 13:08:03.365297 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1244 13:08:03.368546 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1245 13:08:03.372002 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1246 13:08:03.375340 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1247 13:08:03.381821 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1248 13:08:03.385156 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1249 13:08:03.388520 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1250 13:08:03.391928 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1251 13:08:03.395358 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1252 13:08:03.402227 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1253 13:08:03.405438 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1254 13:08:03.408868 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1255 13:08:03.411686 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1256 13:08:03.415657 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1257 13:08:03.421939 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1258 13:08:03.422056 ==
1259 13:08:03.425270 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 13:08:03.428780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 13:08:03.428862 ==
1262 13:08:03.428939 DQS Delay:
1263 13:08:03.432185 DQS0 = 0, DQS1 = 0
1264 13:08:03.432263 DQM Delay:
1265 13:08:03.435562 DQM0 = 93, DQM1 = 84
1266 13:08:03.435643 DQ Delay:
1267 13:08:03.438910 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1268 13:08:03.442313 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1269 13:08:03.445181 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1270 13:08:03.449063 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1271 13:08:03.449153
1272 13:08:03.449229
1273 13:08:03.449300 ==
1274 13:08:03.452375 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 13:08:03.455480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 13:08:03.455564 ==
1277 13:08:03.455643
1278 13:08:03.458603
1279 13:08:03.458684 TX Vref Scan disable
1280 13:08:03.462112 == TX Byte 0 ==
1281 13:08:03.465422 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1282 13:08:03.468891 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1283 13:08:03.472135 == TX Byte 1 ==
1284 13:08:03.475104 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1285 13:08:03.478481 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1286 13:08:03.478562 ==
1287 13:08:03.481860 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 13:08:03.488740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 13:08:03.488857 ==
1290 13:08:03.501084 TX Vref=22, minBit 8, minWin=27, winSum=446
1291 13:08:03.504380 TX Vref=24, minBit 9, minWin=27, winSum=452
1292 13:08:03.507567 TX Vref=26, minBit 1, minWin=28, winSum=454
1293 13:08:03.511123 TX Vref=28, minBit 1, minWin=28, winSum=458
1294 13:08:03.514392 TX Vref=30, minBit 4, minWin=28, winSum=455
1295 13:08:03.517745 TX Vref=32, minBit 8, minWin=27, winSum=451
1296 13:08:03.523854 [TxChooseVref] Worse bit 1, Min win 28, Win sum 458, Final Vref 28
1297 13:08:03.523963
1298 13:08:03.527658 Final TX Range 1 Vref 28
1299 13:08:03.527741
1300 13:08:03.527804 ==
1301 13:08:03.530795 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 13:08:03.534209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 13:08:03.534290 ==
1304 13:08:03.534350
1305 13:08:03.534405
1306 13:08:03.537537 TX Vref Scan disable
1307 13:08:03.541093 == TX Byte 0 ==
1308 13:08:03.544377 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1309 13:08:03.547717 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1310 13:08:03.551234 == TX Byte 1 ==
1311 13:08:03.554329 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1312 13:08:03.557355 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1313 13:08:03.557525
1314 13:08:03.560778 [DATLAT]
1315 13:08:03.560894 Freq=800, CH0 RK1
1316 13:08:03.560982
1317 13:08:03.564144 DATLAT Default: 0xa
1318 13:08:03.564319 0, 0xFFFF, sum = 0
1319 13:08:03.567301 1, 0xFFFF, sum = 0
1320 13:08:03.567392 2, 0xFFFF, sum = 0
1321 13:08:03.570841 3, 0xFFFF, sum = 0
1322 13:08:03.570936 4, 0xFFFF, sum = 0
1323 13:08:03.574224 5, 0xFFFF, sum = 0
1324 13:08:03.574342 6, 0xFFFF, sum = 0
1325 13:08:03.577452 7, 0xFFFF, sum = 0
1326 13:08:03.577584 8, 0xFFFF, sum = 0
1327 13:08:03.580720 9, 0x0, sum = 1
1328 13:08:03.580849 10, 0x0, sum = 2
1329 13:08:03.584066 11, 0x0, sum = 3
1330 13:08:03.584210 12, 0x0, sum = 4
1331 13:08:03.587277 best_step = 10
1332 13:08:03.587378
1333 13:08:03.587440 ==
1334 13:08:03.590840 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 13:08:03.593872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 13:08:03.594025 ==
1337 13:08:03.597619 RX Vref Scan: 0
1338 13:08:03.597771
1339 13:08:03.597861 RX Vref 0 -> 0, step: 1
1340 13:08:03.597943
1341 13:08:03.600668 RX Delay -95 -> 252, step: 8
1342 13:08:03.607237 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1343 13:08:03.610703 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1344 13:08:03.613995 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1345 13:08:03.617242 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1346 13:08:03.620705 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1347 13:08:03.627214 iDelay=209, Bit 5, Center 84 (-31 ~ 200) 232
1348 13:08:03.630631 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1349 13:08:03.633797 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1350 13:08:03.637090 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1351 13:08:03.641088 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1352 13:08:03.647249 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1353 13:08:03.650708 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1354 13:08:03.654145 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1355 13:08:03.657364 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1356 13:08:03.661033 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1357 13:08:03.667618 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1358 13:08:03.667737 ==
1359 13:08:03.670863 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 13:08:03.674324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 13:08:03.674427 ==
1362 13:08:03.674488 DQS Delay:
1363 13:08:03.677555 DQS0 = 0, DQS1 = 0
1364 13:08:03.677638 DQM Delay:
1365 13:08:03.680938 DQM0 = 92, DQM1 = 83
1366 13:08:03.681021 DQ Delay:
1367 13:08:03.684229 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1368 13:08:03.687572 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1369 13:08:03.691054 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1370 13:08:03.694458 DQ12 =84, DQ13 =92, DQ14 =92, DQ15 =88
1371 13:08:03.694555
1372 13:08:03.694615
1373 13:08:03.700809 [DQSOSCAuto] RK1, (LSB)MR18= 0x4516, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1374 13:08:03.704563 CH0 RK1: MR19=606, MR18=4516
1375 13:08:03.711349 CH0_RK1: MR19=0x606, MR18=0x4516, DQSOSC=392, MR23=63, INC=96, DEC=64
1376 13:08:03.714056 [RxdqsGatingPostProcess] freq 800
1377 13:08:03.720951 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 13:08:03.721075 Pre-setting of DQS Precalculation
1379 13:08:03.727360 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 13:08:03.727477 ==
1381 13:08:03.731158 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 13:08:03.734318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 13:08:03.734444 ==
1384 13:08:03.740956 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 13:08:03.747754 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 13:08:03.755696 [CA 0] Center 36 (6~67) winsize 62
1387 13:08:03.758884 [CA 1] Center 36 (6~67) winsize 62
1388 13:08:03.762448 [CA 2] Center 35 (4~66) winsize 63
1389 13:08:03.765683 [CA 3] Center 34 (4~65) winsize 62
1390 13:08:03.769456 [CA 4] Center 34 (4~65) winsize 62
1391 13:08:03.772757 [CA 5] Center 34 (4~65) winsize 62
1392 13:08:03.772857
1393 13:08:03.775808 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1394 13:08:03.775895
1395 13:08:03.779284 [CATrainingPosCal] consider 1 rank data
1396 13:08:03.782681 u2DelayCellTimex100 = 270/100 ps
1397 13:08:03.785930 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 13:08:03.789322 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1399 13:08:03.792739 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1400 13:08:03.799504 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 13:08:03.802704 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1402 13:08:03.805868 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1403 13:08:03.805992
1404 13:08:03.809577 CA PerBit enable=1, Macro0, CA PI delay=34
1405 13:08:03.809687
1406 13:08:03.812638 [CBTSetCACLKResult] CA Dly = 34
1407 13:08:03.812740 CS Dly: 6 (0~37)
1408 13:08:03.812838 ==
1409 13:08:03.816095 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 13:08:03.823171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 13:08:03.823258 ==
1412 13:08:03.826348 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 13:08:03.832756 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 13:08:03.841767 [CA 0] Center 36 (6~67) winsize 62
1415 13:08:03.845110 [CA 1] Center 36 (6~67) winsize 62
1416 13:08:03.848429 [CA 2] Center 35 (4~66) winsize 63
1417 13:08:03.852184 [CA 3] Center 34 (4~65) winsize 62
1418 13:08:03.855253 [CA 4] Center 35 (5~66) winsize 62
1419 13:08:03.858338 [CA 5] Center 34 (4~65) winsize 62
1420 13:08:03.858424
1421 13:08:03.862342 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1422 13:08:03.862421
1423 13:08:03.865156 [CATrainingPosCal] consider 2 rank data
1424 13:08:03.868931 u2DelayCellTimex100 = 270/100 ps
1425 13:08:03.871903 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 13:08:03.875496 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 13:08:03.878515 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1428 13:08:03.885596 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 13:08:03.888662 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1430 13:08:03.891823 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1431 13:08:03.891921
1432 13:08:03.895793 CA PerBit enable=1, Macro0, CA PI delay=34
1433 13:08:03.895873
1434 13:08:03.898485 [CBTSetCACLKResult] CA Dly = 34
1435 13:08:03.898586 CS Dly: 6 (0~38)
1436 13:08:03.898679
1437 13:08:03.901876 ----->DramcWriteLeveling(PI) begin...
1438 13:08:03.901975 ==
1439 13:08:03.905199 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 13:08:03.912025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 13:08:03.912148 ==
1442 13:08:03.915744 Write leveling (Byte 0): 26 => 26
1443 13:08:03.918797 Write leveling (Byte 1): 26 => 26
1444 13:08:03.918898 DramcWriteLeveling(PI) end<-----
1445 13:08:03.922017
1446 13:08:03.922095 ==
1447 13:08:03.925395 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 13:08:03.928663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 13:08:03.928765 ==
1450 13:08:03.932326 [Gating] SW mode calibration
1451 13:08:03.938951 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 13:08:03.942276 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 13:08:03.949091 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 13:08:03.951855 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1455 13:08:03.955103 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:08:03.962017 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 13:08:03.965286 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 13:08:03.968644 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 13:08:03.975553 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 13:08:03.978672 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 13:08:03.981901 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 13:08:03.985637 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 13:08:03.992048 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 13:08:03.995720 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 13:08:03.998925 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 13:08:04.005568 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 13:08:04.009201 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 13:08:04.011873 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 13:08:04.018825 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1470 13:08:04.022034 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1471 13:08:04.025743 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 13:08:04.032321 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 13:08:04.035488 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 13:08:04.038793 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 13:08:04.045638 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 13:08:04.049127 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 13:08:04.052466 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 13:08:04.058742 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
1479 13:08:04.062094 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1480 13:08:04.065351 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 13:08:04.072152 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 13:08:04.075560 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 13:08:04.078719 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 13:08:04.082103 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 13:08:04.089233 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
1486 13:08:04.092543 0 10 4 | B1->B0 | 3232 2d2d | 1 1 | (1 0) (1 0)
1487 13:08:04.095657 0 10 8 | B1->B0 | 2727 2323 | 1 0 | (0 0) (1 0)
1488 13:08:04.102495 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 13:08:04.105781 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 13:08:04.109014 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 13:08:04.116080 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 13:08:04.119183 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 13:08:04.122101 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 13:08:04.128849 0 11 4 | B1->B0 | 2e2e 3838 | 0 0 | (0 0) (0 0)
1495 13:08:04.132617 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1496 13:08:04.136165 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 13:08:04.142437 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 13:08:04.146198 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 13:08:04.149071 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 13:08:04.153083 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 13:08:04.159241 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 13:08:04.162238 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1503 13:08:04.166110 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 13:08:04.172729 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 13:08:04.176139 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 13:08:04.179546 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 13:08:04.186112 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 13:08:04.189411 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 13:08:04.192689 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 13:08:04.199237 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 13:08:04.202674 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 13:08:04.205991 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 13:08:04.212837 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 13:08:04.216162 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 13:08:04.219473 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 13:08:04.225953 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 13:08:04.229360 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1518 13:08:04.232808 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1519 13:08:04.236191 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 13:08:04.239567 Total UI for P1: 0, mck2ui 16
1521 13:08:04.242922 best dqsien dly found for B0: ( 0, 14, 6)
1522 13:08:04.246218 Total UI for P1: 0, mck2ui 16
1523 13:08:04.249890 best dqsien dly found for B1: ( 0, 14, 2)
1524 13:08:04.252932 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1525 13:08:04.256393 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1526 13:08:04.256503
1527 13:08:04.262977 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1528 13:08:04.265982 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1529 13:08:04.266127 [Gating] SW calibration Done
1530 13:08:04.269622 ==
1531 13:08:04.269729 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 13:08:04.276140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 13:08:04.276266 ==
1534 13:08:04.276359 RX Vref Scan: 0
1535 13:08:04.276451
1536 13:08:04.279622 RX Vref 0 -> 0, step: 1
1537 13:08:04.279718
1538 13:08:04.283064 RX Delay -130 -> 252, step: 16
1539 13:08:04.286466 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1540 13:08:04.289962 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1541 13:08:04.293044 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1542 13:08:04.299381 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1543 13:08:04.302672 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1544 13:08:04.306633 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1545 13:08:04.309377 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1546 13:08:04.313271 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1547 13:08:04.319462 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1548 13:08:04.322610 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1549 13:08:04.326029 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1550 13:08:04.329710 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1551 13:08:04.333173 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1552 13:08:04.339851 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1553 13:08:04.343252 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1554 13:08:04.346053 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1555 13:08:04.346142 ==
1556 13:08:04.349452 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 13:08:04.352789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 13:08:04.356165 ==
1559 13:08:04.356277 DQS Delay:
1560 13:08:04.356375 DQS0 = 0, DQS1 = 0
1561 13:08:04.359265 DQM Delay:
1562 13:08:04.359351 DQM0 = 95, DQM1 = 90
1563 13:08:04.363259 DQ Delay:
1564 13:08:04.363348 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1565 13:08:04.366397 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1566 13:08:04.369736 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1567 13:08:04.373042 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =101
1568 13:08:04.376410
1569 13:08:04.376522
1570 13:08:04.376611 ==
1571 13:08:04.379767 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 13:08:04.382823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 13:08:04.382902 ==
1574 13:08:04.383001
1575 13:08:04.383074
1576 13:08:04.385974 TX Vref Scan disable
1577 13:08:04.386091 == TX Byte 0 ==
1578 13:08:04.392866 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1579 13:08:04.396397 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1580 13:08:04.396508 == TX Byte 1 ==
1581 13:08:04.399682 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1582 13:08:04.406502 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1583 13:08:04.406630 ==
1584 13:08:04.409427 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 13:08:04.413257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 13:08:04.413357 ==
1587 13:08:04.426101 TX Vref=22, minBit 1, minWin=26, winSum=433
1588 13:08:04.429393 TX Vref=24, minBit 1, minWin=26, winSum=440
1589 13:08:04.432633 TX Vref=26, minBit 1, minWin=27, winSum=446
1590 13:08:04.435946 TX Vref=28, minBit 2, minWin=27, winSum=448
1591 13:08:04.439365 TX Vref=30, minBit 1, minWin=27, winSum=448
1592 13:08:04.445880 TX Vref=32, minBit 0, minWin=27, winSum=444
1593 13:08:04.449492 [TxChooseVref] Worse bit 2, Min win 27, Win sum 448, Final Vref 28
1594 13:08:04.449607
1595 13:08:04.452836 Final TX Range 1 Vref 28
1596 13:08:04.452936
1597 13:08:04.453025 ==
1598 13:08:04.455615 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 13:08:04.459354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 13:08:04.459459 ==
1601 13:08:04.462811
1602 13:08:04.462911
1603 13:08:04.462997 TX Vref Scan disable
1604 13:08:04.466171 == TX Byte 0 ==
1605 13:08:04.469186 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1606 13:08:04.472336 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1607 13:08:04.475938 == TX Byte 1 ==
1608 13:08:04.479317 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1609 13:08:04.482673 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1610 13:08:04.485903
1611 13:08:04.486025 [DATLAT]
1612 13:08:04.486113 Freq=800, CH1 RK0
1613 13:08:04.486175
1614 13:08:04.489772 DATLAT Default: 0xa
1615 13:08:04.489879 0, 0xFFFF, sum = 0
1616 13:08:04.492853 1, 0xFFFF, sum = 0
1617 13:08:04.492954 2, 0xFFFF, sum = 0
1618 13:08:04.496091 3, 0xFFFF, sum = 0
1619 13:08:04.496200 4, 0xFFFF, sum = 0
1620 13:08:04.499396 5, 0xFFFF, sum = 0
1621 13:08:04.499505 6, 0xFFFF, sum = 0
1622 13:08:04.502879 7, 0xFFFF, sum = 0
1623 13:08:04.506267 8, 0xFFFF, sum = 0
1624 13:08:04.506349 9, 0x0, sum = 1
1625 13:08:04.506429 10, 0x0, sum = 2
1626 13:08:04.509500 11, 0x0, sum = 3
1627 13:08:04.509581 12, 0x0, sum = 4
1628 13:08:04.512868 best_step = 10
1629 13:08:04.512969
1630 13:08:04.513050 ==
1631 13:08:04.515956 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 13:08:04.519455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 13:08:04.519537 ==
1634 13:08:04.522869 RX Vref Scan: 1
1635 13:08:04.522948
1636 13:08:04.523007 Set Vref Range= 32 -> 127
1637 13:08:04.523089
1638 13:08:04.526471 RX Vref 32 -> 127, step: 1
1639 13:08:04.526555
1640 13:08:04.529479 RX Delay -63 -> 252, step: 8
1641 13:08:04.529558
1642 13:08:04.533190 Set Vref, RX VrefLevel [Byte0]: 32
1643 13:08:04.536130 [Byte1]: 32
1644 13:08:04.536214
1645 13:08:04.539574 Set Vref, RX VrefLevel [Byte0]: 33
1646 13:08:04.542607 [Byte1]: 33
1647 13:08:04.546327
1648 13:08:04.546430 Set Vref, RX VrefLevel [Byte0]: 34
1649 13:08:04.549373 [Byte1]: 34
1650 13:08:04.553521
1651 13:08:04.553633 Set Vref, RX VrefLevel [Byte0]: 35
1652 13:08:04.556846 [Byte1]: 35
1653 13:08:04.561461
1654 13:08:04.561547 Set Vref, RX VrefLevel [Byte0]: 36
1655 13:08:04.564747 [Byte1]: 36
1656 13:08:04.568687
1657 13:08:04.568793 Set Vref, RX VrefLevel [Byte0]: 37
1658 13:08:04.571548 [Byte1]: 37
1659 13:08:04.576117
1660 13:08:04.576226 Set Vref, RX VrefLevel [Byte0]: 38
1661 13:08:04.579398 [Byte1]: 38
1662 13:08:04.584000
1663 13:08:04.584087 Set Vref, RX VrefLevel [Byte0]: 39
1664 13:08:04.586680 [Byte1]: 39
1665 13:08:04.590814
1666 13:08:04.590915 Set Vref, RX VrefLevel [Byte0]: 40
1667 13:08:04.594764 [Byte1]: 40
1668 13:08:04.598507
1669 13:08:04.598629 Set Vref, RX VrefLevel [Byte0]: 41
1670 13:08:04.601811 [Byte1]: 41
1671 13:08:04.606229
1672 13:08:04.606336 Set Vref, RX VrefLevel [Byte0]: 42
1673 13:08:04.609548 [Byte1]: 42
1674 13:08:04.613571
1675 13:08:04.613691 Set Vref, RX VrefLevel [Byte0]: 43
1676 13:08:04.617090 [Byte1]: 43
1677 13:08:04.621248
1678 13:08:04.621361 Set Vref, RX VrefLevel [Byte0]: 44
1679 13:08:04.624570 [Byte1]: 44
1680 13:08:04.628310
1681 13:08:04.628414 Set Vref, RX VrefLevel [Byte0]: 45
1682 13:08:04.631875 [Byte1]: 45
1683 13:08:04.636369
1684 13:08:04.636503 Set Vref, RX VrefLevel [Byte0]: 46
1685 13:08:04.639724 [Byte1]: 46
1686 13:08:04.643371
1687 13:08:04.643468 Set Vref, RX VrefLevel [Byte0]: 47
1688 13:08:04.646928 [Byte1]: 47
1689 13:08:04.651313
1690 13:08:04.651441 Set Vref, RX VrefLevel [Byte0]: 48
1691 13:08:04.654745 [Byte1]: 48
1692 13:08:04.658838
1693 13:08:04.658948 Set Vref, RX VrefLevel [Byte0]: 49
1694 13:08:04.662020 [Byte1]: 49
1695 13:08:04.666030
1696 13:08:04.666111 Set Vref, RX VrefLevel [Byte0]: 50
1697 13:08:04.669409 [Byte1]: 50
1698 13:08:04.673445
1699 13:08:04.673520 Set Vref, RX VrefLevel [Byte0]: 51
1700 13:08:04.676908 [Byte1]: 51
1701 13:08:04.681071
1702 13:08:04.681179 Set Vref, RX VrefLevel [Byte0]: 52
1703 13:08:04.684477 [Byte1]: 52
1704 13:08:04.688788
1705 13:08:04.688876 Set Vref, RX VrefLevel [Byte0]: 53
1706 13:08:04.692165 [Byte1]: 53
1707 13:08:04.696060
1708 13:08:04.696138 Set Vref, RX VrefLevel [Byte0]: 54
1709 13:08:04.699362 [Byte1]: 54
1710 13:08:04.703193
1711 13:08:04.703269 Set Vref, RX VrefLevel [Byte0]: 55
1712 13:08:04.706518 [Byte1]: 55
1713 13:08:04.711139
1714 13:08:04.711218 Set Vref, RX VrefLevel [Byte0]: 56
1715 13:08:04.714381 [Byte1]: 56
1716 13:08:04.718491
1717 13:08:04.718594 Set Vref, RX VrefLevel [Byte0]: 57
1718 13:08:04.721924 [Byte1]: 57
1719 13:08:04.726028
1720 13:08:04.726130 Set Vref, RX VrefLevel [Byte0]: 58
1721 13:08:04.729502 [Byte1]: 58
1722 13:08:04.733432
1723 13:08:04.733522 Set Vref, RX VrefLevel [Byte0]: 59
1724 13:08:04.736766 [Byte1]: 59
1725 13:08:04.741544
1726 13:08:04.741631 Set Vref, RX VrefLevel [Byte0]: 60
1727 13:08:04.744439 [Byte1]: 60
1728 13:08:04.748749
1729 13:08:04.748830 Set Vref, RX VrefLevel [Byte0]: 61
1730 13:08:04.752014 [Byte1]: 61
1731 13:08:04.755847
1732 13:08:04.755933 Set Vref, RX VrefLevel [Byte0]: 62
1733 13:08:04.759204 [Byte1]: 62
1734 13:08:04.763726
1735 13:08:04.763804 Set Vref, RX VrefLevel [Byte0]: 63
1736 13:08:04.766653 [Byte1]: 63
1737 13:08:04.770798
1738 13:08:04.770905 Set Vref, RX VrefLevel [Byte0]: 64
1739 13:08:04.774061 [Byte1]: 64
1740 13:08:04.778910
1741 13:08:04.779017 Set Vref, RX VrefLevel [Byte0]: 65
1742 13:08:04.782028 [Byte1]: 65
1743 13:08:04.786110
1744 13:08:04.786188 Set Vref, RX VrefLevel [Byte0]: 66
1745 13:08:04.789509 [Byte1]: 66
1746 13:08:04.793332
1747 13:08:04.793401 Set Vref, RX VrefLevel [Byte0]: 67
1748 13:08:04.796561 [Byte1]: 67
1749 13:08:04.801086
1750 13:08:04.801168 Set Vref, RX VrefLevel [Byte0]: 68
1751 13:08:04.804332 [Byte1]: 68
1752 13:08:04.808816
1753 13:08:04.808924 Set Vref, RX VrefLevel [Byte0]: 69
1754 13:08:04.811587 [Byte1]: 69
1755 13:08:04.816217
1756 13:08:04.816299 Set Vref, RX VrefLevel [Byte0]: 70
1757 13:08:04.819509 [Byte1]: 70
1758 13:08:04.823362
1759 13:08:04.823457 Set Vref, RX VrefLevel [Byte0]: 71
1760 13:08:04.826556 [Byte1]: 71
1761 13:08:04.831371
1762 13:08:04.831476 Set Vref, RX VrefLevel [Byte0]: 72
1763 13:08:04.834051 [Byte1]: 72
1764 13:08:04.838798
1765 13:08:04.838883 Final RX Vref Byte 0 = 55 to rank0
1766 13:08:04.842107 Final RX Vref Byte 1 = 55 to rank0
1767 13:08:04.845421 Final RX Vref Byte 0 = 55 to rank1
1768 13:08:04.848758 Final RX Vref Byte 1 = 55 to rank1==
1769 13:08:04.852046 Dram Type= 6, Freq= 0, CH_1, rank 0
1770 13:08:04.855332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1771 13:08:04.858447 ==
1772 13:08:04.858548 DQS Delay:
1773 13:08:04.858639 DQS0 = 0, DQS1 = 0
1774 13:08:04.862303 DQM Delay:
1775 13:08:04.862409 DQM0 = 94, DQM1 = 90
1776 13:08:04.865687 DQ Delay:
1777 13:08:04.865788 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1778 13:08:04.869074 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
1779 13:08:04.872399 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1780 13:08:04.875770 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1781 13:08:04.875874
1782 13:08:04.875962
1783 13:08:04.885626 [DQSOSCAuto] RK0, (LSB)MR18= 0x3652, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1784 13:08:04.889107 CH1 RK0: MR19=606, MR18=3652
1785 13:08:04.892524 CH1_RK0: MR19=0x606, MR18=0x3652, DQSOSC=389, MR23=63, INC=97, DEC=65
1786 13:08:04.895473
1787 13:08:04.898910 ----->DramcWriteLeveling(PI) begin...
1788 13:08:04.899010 ==
1789 13:08:04.902307 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 13:08:04.905808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 13:08:04.905914 ==
1792 13:08:04.909257 Write leveling (Byte 0): 27 => 27
1793 13:08:04.912448 Write leveling (Byte 1): 32 => 32
1794 13:08:04.915920 DramcWriteLeveling(PI) end<-----
1795 13:08:04.916028
1796 13:08:04.916115 ==
1797 13:08:04.919158 Dram Type= 6, Freq= 0, CH_1, rank 1
1798 13:08:04.922492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 13:08:04.922572 ==
1800 13:08:04.925816 [Gating] SW mode calibration
1801 13:08:04.932270 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1802 13:08:04.939151 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1803 13:08:04.942472 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1804 13:08:04.945624 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1805 13:08:04.949185 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 13:08:04.956033 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 13:08:04.959282 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 13:08:04.962573 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 13:08:04.969597 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 13:08:04.972436 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 13:08:04.975881 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 13:08:04.982554 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 13:08:04.986070 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 13:08:04.989283 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 13:08:04.995727 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 13:08:04.999430 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 13:08:05.002379 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 13:08:05.008938 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 13:08:05.012375 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1820 13:08:05.015810 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1821 13:08:05.022431 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1822 13:08:05.026226 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 13:08:05.029753 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 13:08:05.035823 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 13:08:05.038856 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 13:08:05.042802 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 13:08:05.048760 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 13:08:05.052480 0 9 4 | B1->B0 | 2c2c 2323 | 1 0 | (1 1) (0 0)
1829 13:08:05.055617 0 9 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
1830 13:08:05.059574 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 13:08:05.065626 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 13:08:05.068940 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 13:08:05.072275 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 13:08:05.079103 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 13:08:05.082447 0 10 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1836 13:08:05.085727 0 10 4 | B1->B0 | 2626 3030 | 0 1 | (1 0) (1 1)
1837 13:08:05.092565 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 13:08:05.096051 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 13:08:05.098811 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 13:08:05.105955 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 13:08:05.109327 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 13:08:05.112042 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 13:08:05.118639 0 11 0 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1844 13:08:05.122310 0 11 4 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 0)
1845 13:08:05.125654 0 11 8 | B1->B0 | 4646 4141 | 0 1 | (0 0) (0 0)
1846 13:08:05.132295 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 13:08:05.135360 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 13:08:05.138708 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 13:08:05.145463 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 13:08:05.149070 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 13:08:05.152403 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1852 13:08:05.155797 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1853 13:08:05.162276 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 13:08:05.166119 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 13:08:05.169531 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 13:08:05.175678 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 13:08:05.179206 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 13:08:05.182161 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 13:08:05.189070 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 13:08:05.192393 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 13:08:05.195853 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 13:08:05.202627 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 13:08:05.205992 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 13:08:05.209233 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 13:08:05.215744 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 13:08:05.219139 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 13:08:05.222555 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 13:08:05.225865 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1869 13:08:05.229416 Total UI for P1: 0, mck2ui 16
1870 13:08:05.232732 best dqsien dly found for B1: ( 0, 14, 2)
1871 13:08:05.239255 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1872 13:08:05.242870 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 13:08:05.245873 Total UI for P1: 0, mck2ui 16
1874 13:08:05.249313 best dqsien dly found for B0: ( 0, 14, 6)
1875 13:08:05.252842 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1876 13:08:05.256166 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1877 13:08:05.256260
1878 13:08:05.259196 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1879 13:08:05.262628 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1880 13:08:05.266153 [Gating] SW calibration Done
1881 13:08:05.266230 ==
1882 13:08:05.269296 Dram Type= 6, Freq= 0, CH_1, rank 1
1883 13:08:05.272657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1884 13:08:05.276203 ==
1885 13:08:05.276311 RX Vref Scan: 0
1886 13:08:05.276400
1887 13:08:05.279392 RX Vref 0 -> 0, step: 1
1888 13:08:05.279498
1889 13:08:05.282743 RX Delay -130 -> 252, step: 16
1890 13:08:05.286191 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1891 13:08:05.289406 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1892 13:08:05.292809 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1893 13:08:05.296651 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1894 13:08:05.302869 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1895 13:08:05.306351 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1896 13:08:05.309677 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1897 13:08:05.313066 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1898 13:08:05.316202 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1899 13:08:05.319569 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1900 13:08:05.326278 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1901 13:08:05.329646 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1902 13:08:05.333110 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1903 13:08:05.336397 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1904 13:08:05.339760 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1905 13:08:05.346418 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1906 13:08:05.346502 ==
1907 13:08:05.349855 Dram Type= 6, Freq= 0, CH_1, rank 1
1908 13:08:05.353155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1909 13:08:05.353250 ==
1910 13:08:05.353323 DQS Delay:
1911 13:08:05.356512 DQS0 = 0, DQS1 = 0
1912 13:08:05.356589 DQM Delay:
1913 13:08:05.359772 DQM0 = 93, DQM1 = 90
1914 13:08:05.359848 DQ Delay:
1915 13:08:05.363520 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1916 13:08:05.366989 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1917 13:08:05.370358 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1918 13:08:05.373468 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1919 13:08:05.373547
1920 13:08:05.373606
1921 13:08:05.373661 ==
1922 13:08:05.376679 Dram Type= 6, Freq= 0, CH_1, rank 1
1923 13:08:05.380349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1924 13:08:05.380433 ==
1925 13:08:05.383559
1926 13:08:05.383628
1927 13:08:05.383686 TX Vref Scan disable
1928 13:08:05.386520 == TX Byte 0 ==
1929 13:08:05.390040 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1930 13:08:05.393093 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1931 13:08:05.396979 == TX Byte 1 ==
1932 13:08:05.400473 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1933 13:08:05.403758 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1934 13:08:05.403840 ==
1935 13:08:05.406866 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 13:08:05.413830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 13:08:05.413929 ==
1938 13:08:05.425463 TX Vref=22, minBit 1, minWin=26, winSum=436
1939 13:08:05.428772 TX Vref=24, minBit 0, minWin=27, winSum=443
1940 13:08:05.431861 TX Vref=26, minBit 2, minWin=27, winSum=445
1941 13:08:05.435528 TX Vref=28, minBit 0, minWin=27, winSum=448
1942 13:08:05.438791 TX Vref=30, minBit 2, minWin=27, winSum=446
1943 13:08:05.441829 TX Vref=32, minBit 2, minWin=27, winSum=449
1944 13:08:05.448525 [TxChooseVref] Worse bit 2, Min win 27, Win sum 449, Final Vref 32
1945 13:08:05.448668
1946 13:08:05.452002 Final TX Range 1 Vref 32
1947 13:08:05.452153
1948 13:08:05.452262 ==
1949 13:08:05.455326 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 13:08:05.459197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 13:08:05.459375 ==
1952 13:08:05.459471
1953 13:08:05.462590
1954 13:08:05.462746 TX Vref Scan disable
1955 13:08:05.465765 == TX Byte 0 ==
1956 13:08:05.468926 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1957 13:08:05.472505 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1958 13:08:05.475159 == TX Byte 1 ==
1959 13:08:05.479106 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1960 13:08:05.482455 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1961 13:08:05.485769
1962 13:08:05.485872 [DATLAT]
1963 13:08:05.485962 Freq=800, CH1 RK1
1964 13:08:05.486057
1965 13:08:05.488538 DATLAT Default: 0xa
1966 13:08:05.488636 0, 0xFFFF, sum = 0
1967 13:08:05.491907 1, 0xFFFF, sum = 0
1968 13:08:05.492003 2, 0xFFFF, sum = 0
1969 13:08:05.495785 3, 0xFFFF, sum = 0
1970 13:08:05.495892 4, 0xFFFF, sum = 0
1971 13:08:05.498929 5, 0xFFFF, sum = 0
1972 13:08:05.499043 6, 0xFFFF, sum = 0
1973 13:08:05.501916 7, 0xFFFF, sum = 0
1974 13:08:05.505594 8, 0xFFFF, sum = 0
1975 13:08:05.505729 9, 0x0, sum = 1
1976 13:08:05.505823 10, 0x0, sum = 2
1977 13:08:05.508811 11, 0x0, sum = 3
1978 13:08:05.508915 12, 0x0, sum = 4
1979 13:08:05.512022 best_step = 10
1980 13:08:05.512118
1981 13:08:05.512209 ==
1982 13:08:05.515896 Dram Type= 6, Freq= 0, CH_1, rank 1
1983 13:08:05.518768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1984 13:08:05.518871 ==
1985 13:08:05.522080 RX Vref Scan: 0
1986 13:08:05.522178
1987 13:08:05.522265 RX Vref 0 -> 0, step: 1
1988 13:08:05.522350
1989 13:08:05.525468 RX Delay -63 -> 252, step: 8
1990 13:08:05.532050 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1991 13:08:05.535460 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1992 13:08:05.538799 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1993 13:08:05.542365 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1994 13:08:05.545430 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1995 13:08:05.549256 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1996 13:08:05.555504 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1997 13:08:05.558814 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1998 13:08:05.562750 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1999 13:08:05.566174 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2000 13:08:05.569502 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2001 13:08:05.572230 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2002 13:08:05.579248 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2003 13:08:05.582327 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2004 13:08:05.585752 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2005 13:08:05.589408 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2006 13:08:05.589492 ==
2007 13:08:05.592704 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 13:08:05.599313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 13:08:05.599405 ==
2010 13:08:05.599467 DQS Delay:
2011 13:08:05.599522 DQS0 = 0, DQS1 = 0
2012 13:08:05.602640 DQM Delay:
2013 13:08:05.602719 DQM0 = 97, DQM1 = 91
2014 13:08:05.605875 DQ Delay:
2015 13:08:05.609062 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2016 13:08:05.612839 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2017 13:08:05.616138 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2018 13:08:05.619287 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2019 13:08:05.619372
2020 13:08:05.619433
2021 13:08:05.625799 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
2022 13:08:05.629388 CH1 RK1: MR19=606, MR18=4C15
2023 13:08:05.636421 CH1_RK1: MR19=0x606, MR18=0x4C15, DQSOSC=390, MR23=63, INC=97, DEC=64
2024 13:08:05.639669 [RxdqsGatingPostProcess] freq 800
2025 13:08:05.642947 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2026 13:08:05.646165 Pre-setting of DQS Precalculation
2027 13:08:05.652898 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2028 13:08:05.660111 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2029 13:08:05.666633 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2030 13:08:05.666759
2031 13:08:05.666824
2032 13:08:05.670090 [Calibration Summary] 1600 Mbps
2033 13:08:05.670180 CH 0, Rank 0
2034 13:08:05.673394 SW Impedance : PASS
2035 13:08:05.676130 DUTY Scan : NO K
2036 13:08:05.676273 ZQ Calibration : PASS
2037 13:08:05.679366 Jitter Meter : NO K
2038 13:08:05.679510 CBT Training : PASS
2039 13:08:05.683234 Write leveling : PASS
2040 13:08:05.686070 RX DQS gating : PASS
2041 13:08:05.686190 RX DQ/DQS(RDDQC) : PASS
2042 13:08:05.689937 TX DQ/DQS : PASS
2043 13:08:05.693176 RX DATLAT : PASS
2044 13:08:05.693299 RX DQ/DQS(Engine): PASS
2045 13:08:05.696037 TX OE : NO K
2046 13:08:05.696150 All Pass.
2047 13:08:05.696242
2048 13:08:05.699492 CH 0, Rank 1
2049 13:08:05.699579 SW Impedance : PASS
2050 13:08:05.703183 DUTY Scan : NO K
2051 13:08:05.706495 ZQ Calibration : PASS
2052 13:08:05.706604 Jitter Meter : NO K
2053 13:08:05.709832 CBT Training : PASS
2054 13:08:05.713296 Write leveling : PASS
2055 13:08:05.713383 RX DQS gating : PASS
2056 13:08:05.716368 RX DQ/DQS(RDDQC) : PASS
2057 13:08:05.716450 TX DQ/DQS : PASS
2058 13:08:05.719595 RX DATLAT : PASS
2059 13:08:05.723390 RX DQ/DQS(Engine): PASS
2060 13:08:05.723507 TX OE : NO K
2061 13:08:05.726572 All Pass.
2062 13:08:05.726683
2063 13:08:05.726769 CH 1, Rank 0
2064 13:08:05.730026 SW Impedance : PASS
2065 13:08:05.730125 DUTY Scan : NO K
2066 13:08:05.733283 ZQ Calibration : PASS
2067 13:08:05.736506 Jitter Meter : NO K
2068 13:08:05.736618 CBT Training : PASS
2069 13:08:05.739813 Write leveling : PASS
2070 13:08:05.743323 RX DQS gating : PASS
2071 13:08:05.743443 RX DQ/DQS(RDDQC) : PASS
2072 13:08:05.746548 TX DQ/DQS : PASS
2073 13:08:05.749880 RX DATLAT : PASS
2074 13:08:05.749979 RX DQ/DQS(Engine): PASS
2075 13:08:05.753310 TX OE : NO K
2076 13:08:05.753409 All Pass.
2077 13:08:05.753494
2078 13:08:05.753577 CH 1, Rank 1
2079 13:08:05.756330 SW Impedance : PASS
2080 13:08:05.760288 DUTY Scan : NO K
2081 13:08:05.760380 ZQ Calibration : PASS
2082 13:08:05.763619 Jitter Meter : NO K
2083 13:08:05.766863 CBT Training : PASS
2084 13:08:05.766978 Write leveling : PASS
2085 13:08:05.770242 RX DQS gating : PASS
2086 13:08:05.773649 RX DQ/DQS(RDDQC) : PASS
2087 13:08:05.773754 TX DQ/DQS : PASS
2088 13:08:05.777184 RX DATLAT : PASS
2089 13:08:05.779838 RX DQ/DQS(Engine): PASS
2090 13:08:05.779934 TX OE : NO K
2091 13:08:05.779995 All Pass.
2092 13:08:05.783147
2093 13:08:05.783256 DramC Write-DBI off
2094 13:08:05.787096 PER_BANK_REFRESH: Hybrid Mode
2095 13:08:05.787181 TX_TRACKING: ON
2096 13:08:05.790338 [GetDramInforAfterCalByMRR] Vendor 6.
2097 13:08:05.793691 [GetDramInforAfterCalByMRR] Revision 606.
2098 13:08:05.800455 [GetDramInforAfterCalByMRR] Revision 2 0.
2099 13:08:05.800541 MR0 0x3b3b
2100 13:08:05.800603 MR8 0x5151
2101 13:08:05.803807 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2102 13:08:05.803888
2103 13:08:05.807131 MR0 0x3b3b
2104 13:08:05.807209 MR8 0x5151
2105 13:08:05.810149 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2106 13:08:05.810227
2107 13:08:05.820611 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2108 13:08:05.823728 [FAST_K] Save calibration result to emmc
2109 13:08:05.826872 [FAST_K] Save calibration result to emmc
2110 13:08:05.830164 dram_init: config_dvfs: 1
2111 13:08:05.833376 dramc_set_vcore_voltage set vcore to 662500
2112 13:08:05.833447 Read voltage for 1200, 2
2113 13:08:05.836710 Vio18 = 0
2114 13:08:05.836783 Vcore = 662500
2115 13:08:05.836845 Vdram = 0
2116 13:08:05.840079 Vddq = 0
2117 13:08:05.840147 Vmddr = 0
2118 13:08:05.843484 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2119 13:08:05.850341 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2120 13:08:05.853332 MEM_TYPE=3, freq_sel=15
2121 13:08:05.856925 sv_algorithm_assistance_LP4_1600
2122 13:08:05.860651 ============ PULL DRAM RESETB DOWN ============
2123 13:08:05.863990 ========== PULL DRAM RESETB DOWN end =========
2124 13:08:05.867244 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2125 13:08:05.870323 ===================================
2126 13:08:05.873623 LPDDR4 DRAM CONFIGURATION
2127 13:08:05.877482 ===================================
2128 13:08:05.880786 EX_ROW_EN[0] = 0x0
2129 13:08:05.880866 EX_ROW_EN[1] = 0x0
2130 13:08:05.883441 LP4Y_EN = 0x0
2131 13:08:05.883543 WORK_FSP = 0x0
2132 13:08:05.887405 WL = 0x4
2133 13:08:05.887504 RL = 0x4
2134 13:08:05.890804 BL = 0x2
2135 13:08:05.890920 RPST = 0x0
2136 13:08:05.893908 RD_PRE = 0x0
2137 13:08:05.894032 WR_PRE = 0x1
2138 13:08:05.897489 WR_PST = 0x0
2139 13:08:05.897570 DBI_WR = 0x0
2140 13:08:05.900831 DBI_RD = 0x0
2141 13:08:05.904119 OTF = 0x1
2142 13:08:05.904223 ===================================
2143 13:08:05.907199 ===================================
2144 13:08:05.910716 ANA top config
2145 13:08:05.914115 ===================================
2146 13:08:05.917458 DLL_ASYNC_EN = 0
2147 13:08:05.917536 ALL_SLAVE_EN = 0
2148 13:08:05.920533 NEW_RANK_MODE = 1
2149 13:08:05.923663 DLL_IDLE_MODE = 1
2150 13:08:05.927004 LP45_APHY_COMB_EN = 1
2151 13:08:05.930457 TX_ODT_DIS = 1
2152 13:08:05.930609 NEW_8X_MODE = 1
2153 13:08:05.933968 ===================================
2154 13:08:05.937259 ===================================
2155 13:08:05.940542 data_rate = 2400
2156 13:08:05.944105 CKR = 1
2157 13:08:05.947579 DQ_P2S_RATIO = 8
2158 13:08:05.950988 ===================================
2159 13:08:05.954207 CA_P2S_RATIO = 8
2160 13:08:05.954295 DQ_CA_OPEN = 0
2161 13:08:05.957632 DQ_SEMI_OPEN = 0
2162 13:08:05.960352 CA_SEMI_OPEN = 0
2163 13:08:05.964236 CA_FULL_RATE = 0
2164 13:08:05.967243 DQ_CKDIV4_EN = 0
2165 13:08:05.970658 CA_CKDIV4_EN = 0
2166 13:08:05.970764 CA_PREDIV_EN = 0
2167 13:08:05.974187 PH8_DLY = 17
2168 13:08:05.977470 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2169 13:08:05.980761 DQ_AAMCK_DIV = 4
2170 13:08:05.983754 CA_AAMCK_DIV = 4
2171 13:08:05.987405 CA_ADMCK_DIV = 4
2172 13:08:05.987488 DQ_TRACK_CA_EN = 0
2173 13:08:05.990411 CA_PICK = 1200
2174 13:08:05.994409 CA_MCKIO = 1200
2175 13:08:05.997561 MCKIO_SEMI = 0
2176 13:08:06.000510 PLL_FREQ = 2366
2177 13:08:06.004083 DQ_UI_PI_RATIO = 32
2178 13:08:06.007385 CA_UI_PI_RATIO = 0
2179 13:08:06.010510 ===================================
2180 13:08:06.013816 ===================================
2181 13:08:06.013914 memory_type:LPDDR4
2182 13:08:06.017267 GP_NUM : 10
2183 13:08:06.020648 SRAM_EN : 1
2184 13:08:06.020747 MD32_EN : 0
2185 13:08:06.023978 ===================================
2186 13:08:06.027170 [ANA_INIT] >>>>>>>>>>>>>>
2187 13:08:06.030436 <<<<<< [CONFIGURE PHASE]: ANA_TX
2188 13:08:06.033692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2189 13:08:06.037556 ===================================
2190 13:08:06.040772 data_rate = 2400,PCW = 0X5b00
2191 13:08:06.040892 ===================================
2192 13:08:06.047654 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2193 13:08:06.050937 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2194 13:08:06.057638 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2195 13:08:06.061127 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2196 13:08:06.064491 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2197 13:08:06.067793 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2198 13:08:06.071130 [ANA_INIT] flow start
2199 13:08:06.073990 [ANA_INIT] PLL >>>>>>>>
2200 13:08:06.074116 [ANA_INIT] PLL <<<<<<<<
2201 13:08:06.077532 [ANA_INIT] MIDPI >>>>>>>>
2202 13:08:06.080811 [ANA_INIT] MIDPI <<<<<<<<
2203 13:08:06.080904 [ANA_INIT] DLL >>>>>>>>
2204 13:08:06.084074 [ANA_INIT] DLL <<<<<<<<
2205 13:08:06.087661 [ANA_INIT] flow end
2206 13:08:06.090731 ============ LP4 DIFF to SE enter ============
2207 13:08:06.094120 ============ LP4 DIFF to SE exit ============
2208 13:08:06.097800 [ANA_INIT] <<<<<<<<<<<<<
2209 13:08:06.101049 [Flow] Enable top DCM control >>>>>
2210 13:08:06.104303 [Flow] Enable top DCM control <<<<<
2211 13:08:06.107526 Enable DLL master slave shuffle
2212 13:08:06.110946 ==============================================================
2213 13:08:06.114711 Gating Mode config
2214 13:08:06.117618 ==============================================================
2215 13:08:06.121112 Config description:
2216 13:08:06.131244 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2217 13:08:06.137607 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2218 13:08:06.140905 SELPH_MODE 0: By rank 1: By Phase
2219 13:08:06.147937 ==============================================================
2220 13:08:06.150843 GAT_TRACK_EN = 1
2221 13:08:06.154739 RX_GATING_MODE = 2
2222 13:08:06.157927 RX_GATING_TRACK_MODE = 2
2223 13:08:06.161290 SELPH_MODE = 1
2224 13:08:06.161395 PICG_EARLY_EN = 1
2225 13:08:06.164740 VALID_LAT_VALUE = 1
2226 13:08:06.170682 ==============================================================
2227 13:08:06.174097 Enter into Gating configuration >>>>
2228 13:08:06.177756 Exit from Gating configuration <<<<
2229 13:08:06.181065 Enter into DVFS_PRE_config >>>>>
2230 13:08:06.191324 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2231 13:08:06.194723 Exit from DVFS_PRE_config <<<<<
2232 13:08:06.197989 Enter into PICG configuration >>>>
2233 13:08:06.200773 Exit from PICG configuration <<<<
2234 13:08:06.204086 [RX_INPUT] configuration >>>>>
2235 13:08:06.207917 [RX_INPUT] configuration <<<<<
2236 13:08:06.210927 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2237 13:08:06.218208 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2238 13:08:06.224401 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2239 13:08:06.231208 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2240 13:08:06.234464 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2241 13:08:06.241296 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2242 13:08:06.244823 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2243 13:08:06.251335 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2244 13:08:06.254333 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2245 13:08:06.258093 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2246 13:08:06.261241 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2247 13:08:06.268170 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2248 13:08:06.271428 ===================================
2249 13:08:06.271519 LPDDR4 DRAM CONFIGURATION
2250 13:08:06.274845 ===================================
2251 13:08:06.278217 EX_ROW_EN[0] = 0x0
2252 13:08:06.281487 EX_ROW_EN[1] = 0x0
2253 13:08:06.281565 LP4Y_EN = 0x0
2254 13:08:06.284848 WORK_FSP = 0x0
2255 13:08:06.284926 WL = 0x4
2256 13:08:06.288220 RL = 0x4
2257 13:08:06.288299 BL = 0x2
2258 13:08:06.291612 RPST = 0x0
2259 13:08:06.291712 RD_PRE = 0x0
2260 13:08:06.294896 WR_PRE = 0x1
2261 13:08:06.294974 WR_PST = 0x0
2262 13:08:06.298297 DBI_WR = 0x0
2263 13:08:06.298373 DBI_RD = 0x0
2264 13:08:06.301767 OTF = 0x1
2265 13:08:06.305113 ===================================
2266 13:08:06.307876 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2267 13:08:06.311219 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2268 13:08:06.315256 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2269 13:08:06.318681 ===================================
2270 13:08:06.321283 LPDDR4 DRAM CONFIGURATION
2271 13:08:06.324642 ===================================
2272 13:08:06.328457 EX_ROW_EN[0] = 0x10
2273 13:08:06.328559 EX_ROW_EN[1] = 0x0
2274 13:08:06.331686 LP4Y_EN = 0x0
2275 13:08:06.331790 WORK_FSP = 0x0
2276 13:08:06.335042 WL = 0x4
2277 13:08:06.335145 RL = 0x4
2278 13:08:06.338298 BL = 0x2
2279 13:08:06.338378 RPST = 0x0
2280 13:08:06.341542 RD_PRE = 0x0
2281 13:08:06.341627 WR_PRE = 0x1
2282 13:08:06.345220 WR_PST = 0x0
2283 13:08:06.345298 DBI_WR = 0x0
2284 13:08:06.348175 DBI_RD = 0x0
2285 13:08:06.351875 OTF = 0x1
2286 13:08:06.351974 ===================================
2287 13:08:06.358701 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2288 13:08:06.358795 ==
2289 13:08:06.362044 Dram Type= 6, Freq= 0, CH_0, rank 0
2290 13:08:06.368791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2291 13:08:06.368882 ==
2292 13:08:06.368942 [Duty_Offset_Calibration]
2293 13:08:06.371902 B0:2 B1:1 CA:1
2294 13:08:06.371979
2295 13:08:06.375278 [DutyScan_Calibration_Flow] k_type=0
2296 13:08:06.383910
2297 13:08:06.384003 ==CLK 0==
2298 13:08:06.387794 Final CLK duty delay cell = 0
2299 13:08:06.390867 [0] MAX Duty = 5218%(X100), DQS PI = 24
2300 13:08:06.394410 [0] MIN Duty = 4875%(X100), DQS PI = 0
2301 13:08:06.394490 [0] AVG Duty = 5046%(X100)
2302 13:08:06.394549
2303 13:08:06.414488 CH0 CLK Duty spec in!! Max-Min= 343%
2304 13:08:06.414663 [DutyScan_Calibration_Flow] ====Done====
2305 13:08:06.414783
2306 13:08:06.414942 [DutyScan_Calibration_Flow] k_type=1
2307 13:08:06.422736
2308 13:08:06.422886 ==DQS 0 ==
2309 13:08:06.425988 Final DQS duty delay cell = -4
2310 13:08:06.429473 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2311 13:08:06.432864 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2312 13:08:06.436201 [-4] AVG Duty = 4937%(X100)
2313 13:08:06.436285
2314 13:08:06.436344 ==DQS 1 ==
2315 13:08:06.439120 Final DQS duty delay cell = 0
2316 13:08:06.442422 [0] MAX Duty = 5156%(X100), DQS PI = 0
2317 13:08:06.446286 [0] MIN Duty = 5000%(X100), DQS PI = 32
2318 13:08:06.449220 [0] AVG Duty = 5078%(X100)
2319 13:08:06.449411
2320 13:08:06.452644 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2321 13:08:06.452802
2322 13:08:06.455992 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2323 13:08:06.459482 [DutyScan_Calibration_Flow] ====Done====
2324 13:08:06.459647
2325 13:08:06.462793 [DutyScan_Calibration_Flow] k_type=3
2326 13:08:06.479721
2327 13:08:06.479885 ==DQM 0 ==
2328 13:08:06.482844 Final DQM duty delay cell = 0
2329 13:08:06.486548 [0] MAX Duty = 5156%(X100), DQS PI = 30
2330 13:08:06.489477 [0] MIN Duty = 4906%(X100), DQS PI = 58
2331 13:08:06.489564 [0] AVG Duty = 5031%(X100)
2332 13:08:06.493212
2333 13:08:06.493288 ==DQM 1 ==
2334 13:08:06.496368 Final DQM duty delay cell = 0
2335 13:08:06.499649 [0] MAX Duty = 5093%(X100), DQS PI = 0
2336 13:08:06.502902 [0] MIN Duty = 5031%(X100), DQS PI = 16
2337 13:08:06.502984 [0] AVG Duty = 5062%(X100)
2338 13:08:06.503042
2339 13:08:06.506467 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2340 13:08:06.509668
2341 13:08:06.513089 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2342 13:08:06.516282 [DutyScan_Calibration_Flow] ====Done====
2343 13:08:06.516428
2344 13:08:06.519582 [DutyScan_Calibration_Flow] k_type=2
2345 13:08:06.535660
2346 13:08:06.535839 ==DQ 0 ==
2347 13:08:06.539019 Final DQ duty delay cell = 0
2348 13:08:06.543110 [0] MAX Duty = 5062%(X100), DQS PI = 32
2349 13:08:06.545696 [0] MIN Duty = 4844%(X100), DQS PI = 62
2350 13:08:06.545861 [0] AVG Duty = 4953%(X100)
2351 13:08:06.545973
2352 13:08:06.549489 ==DQ 1 ==
2353 13:08:06.553014 Final DQ duty delay cell = 0
2354 13:08:06.556333 [0] MAX Duty = 5093%(X100), DQS PI = 24
2355 13:08:06.559675 [0] MIN Duty = 4907%(X100), DQS PI = 34
2356 13:08:06.559775 [0] AVG Duty = 5000%(X100)
2357 13:08:06.559836
2358 13:08:06.563012 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2359 13:08:06.563112
2360 13:08:06.566375 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2361 13:08:06.572887 [DutyScan_Calibration_Flow] ====Done====
2362 13:08:06.573006 ==
2363 13:08:06.576176 Dram Type= 6, Freq= 0, CH_1, rank 0
2364 13:08:06.579571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2365 13:08:06.579652 ==
2366 13:08:06.582927 [Duty_Offset_Calibration]
2367 13:08:06.583005 B0:1 B1:0 CA:0
2368 13:08:06.583065
2369 13:08:06.586256 [DutyScan_Calibration_Flow] k_type=0
2370 13:08:06.595166
2371 13:08:06.595254 ==CLK 0==
2372 13:08:06.598412 Final CLK duty delay cell = -4
2373 13:08:06.601588 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2374 13:08:06.605214 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2375 13:08:06.608608 [-4] AVG Duty = 4953%(X100)
2376 13:08:06.608729
2377 13:08:06.611722 CH1 CLK Duty spec in!! Max-Min= 93%
2378 13:08:06.615001 [DutyScan_Calibration_Flow] ====Done====
2379 13:08:06.615080
2380 13:08:06.618692 [DutyScan_Calibration_Flow] k_type=1
2381 13:08:06.634875
2382 13:08:06.635017 ==DQS 0 ==
2383 13:08:06.637911 Final DQS duty delay cell = 0
2384 13:08:06.641652 [0] MAX Duty = 5062%(X100), DQS PI = 24
2385 13:08:06.644952 [0] MIN Duty = 4844%(X100), DQS PI = 0
2386 13:08:06.645085 [0] AVG Duty = 4953%(X100)
2387 13:08:06.648281
2388 13:08:06.648427 ==DQS 1 ==
2389 13:08:06.651498 Final DQS duty delay cell = 0
2390 13:08:06.654718 [0] MAX Duty = 5218%(X100), DQS PI = 20
2391 13:08:06.657880 [0] MIN Duty = 4969%(X100), DQS PI = 10
2392 13:08:06.658002 [0] AVG Duty = 5093%(X100)
2393 13:08:06.661123
2394 13:08:06.665290 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2395 13:08:06.665394
2396 13:08:06.668073 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2397 13:08:06.671327 [DutyScan_Calibration_Flow] ====Done====
2398 13:08:06.671434
2399 13:08:06.674693 [DutyScan_Calibration_Flow] k_type=3
2400 13:08:06.691269
2401 13:08:06.691389 ==DQM 0 ==
2402 13:08:06.694592 Final DQM duty delay cell = 0
2403 13:08:06.698091 [0] MAX Duty = 5156%(X100), DQS PI = 8
2404 13:08:06.701436 [0] MIN Duty = 5031%(X100), DQS PI = 0
2405 13:08:06.701532 [0] AVG Duty = 5093%(X100)
2406 13:08:06.701620
2407 13:08:06.704943 ==DQM 1 ==
2408 13:08:06.708287 Final DQM duty delay cell = 0
2409 13:08:06.711475 [0] MAX Duty = 5031%(X100), DQS PI = 16
2410 13:08:06.714948 [0] MIN Duty = 4875%(X100), DQS PI = 36
2411 13:08:06.715054 [0] AVG Duty = 4953%(X100)
2412 13:08:06.715145
2413 13:08:06.721712 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2414 13:08:06.721823
2415 13:08:06.725058 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2416 13:08:06.728478 [DutyScan_Calibration_Flow] ====Done====
2417 13:08:06.728573
2418 13:08:06.731707 [DutyScan_Calibration_Flow] k_type=2
2419 13:08:06.747158
2420 13:08:06.747281 ==DQ 0 ==
2421 13:08:06.750567 Final DQ duty delay cell = -4
2422 13:08:06.754058 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2423 13:08:06.757282 [-4] MIN Duty = 4906%(X100), DQS PI = 38
2424 13:08:06.760554 [-4] AVG Duty = 4984%(X100)
2425 13:08:06.760658
2426 13:08:06.760745 ==DQ 1 ==
2427 13:08:06.763771 Final DQ duty delay cell = 0
2428 13:08:06.766908 [0] MAX Duty = 5125%(X100), DQS PI = 20
2429 13:08:06.770815 [0] MIN Duty = 4938%(X100), DQS PI = 34
2430 13:08:06.770916 [0] AVG Duty = 5031%(X100)
2431 13:08:06.774114
2432 13:08:06.777402 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2433 13:08:06.777500
2434 13:08:06.780722 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2435 13:08:06.783663 [DutyScan_Calibration_Flow] ====Done====
2436 13:08:06.787059 nWR fixed to 30
2437 13:08:06.787161 [ModeRegInit_LP4] CH0 RK0
2438 13:08:06.790411 [ModeRegInit_LP4] CH0 RK1
2439 13:08:06.793617 [ModeRegInit_LP4] CH1 RK0
2440 13:08:06.793717 [ModeRegInit_LP4] CH1 RK1
2441 13:08:06.797152 match AC timing 7
2442 13:08:06.800500 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2443 13:08:06.803984 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2444 13:08:06.810817 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2445 13:08:06.814177 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2446 13:08:06.820768 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2447 13:08:06.820878 ==
2448 13:08:06.823967 Dram Type= 6, Freq= 0, CH_0, rank 0
2449 13:08:06.827116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2450 13:08:06.827217 ==
2451 13:08:06.833877 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2452 13:08:06.837502 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2453 13:08:06.847663 [CA 0] Center 39 (8~70) winsize 63
2454 13:08:06.850996 [CA 1] Center 39 (8~70) winsize 63
2455 13:08:06.853737 [CA 2] Center 35 (5~66) winsize 62
2456 13:08:06.857601 [CA 3] Center 34 (4~65) winsize 62
2457 13:08:06.861207 [CA 4] Center 33 (3~64) winsize 62
2458 13:08:06.864284 [CA 5] Center 32 (3~62) winsize 60
2459 13:08:06.864386
2460 13:08:06.867333 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2461 13:08:06.867434
2462 13:08:06.870858 [CATrainingPosCal] consider 1 rank data
2463 13:08:06.874259 u2DelayCellTimex100 = 270/100 ps
2464 13:08:06.877474 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2465 13:08:06.880847 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2466 13:08:06.887669 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2467 13:08:06.890741 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2468 13:08:06.894244 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2469 13:08:06.897390 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2470 13:08:06.897489
2471 13:08:06.900671 CA PerBit enable=1, Macro0, CA PI delay=32
2472 13:08:06.900769
2473 13:08:06.904157 [CBTSetCACLKResult] CA Dly = 32
2474 13:08:06.904253 CS Dly: 6 (0~37)
2475 13:08:06.904336 ==
2476 13:08:06.907411 Dram Type= 6, Freq= 0, CH_0, rank 1
2477 13:08:06.914426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2478 13:08:06.914528 ==
2479 13:08:06.917817 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2480 13:08:06.924483 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2481 13:08:06.933243 [CA 0] Center 38 (8~69) winsize 62
2482 13:08:06.936520 [CA 1] Center 38 (8~69) winsize 62
2483 13:08:06.939637 [CA 2] Center 35 (5~66) winsize 62
2484 13:08:06.943359 [CA 3] Center 34 (4~65) winsize 62
2485 13:08:06.946438 [CA 4] Center 33 (3~63) winsize 61
2486 13:08:06.949894 [CA 5] Center 32 (2~62) winsize 61
2487 13:08:06.949971
2488 13:08:06.952903 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2489 13:08:06.952979
2490 13:08:06.956315 [CATrainingPosCal] consider 2 rank data
2491 13:08:06.959967 u2DelayCellTimex100 = 270/100 ps
2492 13:08:06.963181 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2493 13:08:06.966654 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2494 13:08:06.973428 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2495 13:08:06.976804 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2496 13:08:06.980187 CA4 delay=33 (3~63),Diff = 1 PI (4 cell)
2497 13:08:06.983586 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2498 13:08:06.983666
2499 13:08:06.986727 CA PerBit enable=1, Macro0, CA PI delay=32
2500 13:08:06.986805
2501 13:08:06.989818 [CBTSetCACLKResult] CA Dly = 32
2502 13:08:06.989895 CS Dly: 6 (0~38)
2503 13:08:06.989955
2504 13:08:06.993180 ----->DramcWriteLeveling(PI) begin...
2505 13:08:06.993281 ==
2506 13:08:06.996617 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 13:08:07.003484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 13:08:07.003559 ==
2509 13:08:07.006801 Write leveling (Byte 0): 33 => 33
2510 13:08:07.010182 Write leveling (Byte 1): 29 => 29
2511 13:08:07.010281 DramcWriteLeveling(PI) end<-----
2512 13:08:07.013391
2513 13:08:07.013461 ==
2514 13:08:07.016570 Dram Type= 6, Freq= 0, CH_0, rank 0
2515 13:08:07.019843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2516 13:08:07.019955 ==
2517 13:08:07.023326 [Gating] SW mode calibration
2518 13:08:07.029915 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2519 13:08:07.033341 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2520 13:08:07.040179 0 15 0 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
2521 13:08:07.043603 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2522 13:08:07.046717 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 13:08:07.053448 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 13:08:07.056585 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 13:08:07.059832 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 13:08:07.066616 0 15 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
2527 13:08:07.070323 0 15 28 | B1->B0 | 3434 2525 | 0 0 | (0 0) (1 0)
2528 13:08:07.073700 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2529 13:08:07.080398 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 13:08:07.083681 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 13:08:07.087017 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 13:08:07.090486 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 13:08:07.097016 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 13:08:07.100308 1 0 24 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
2535 13:08:07.103613 1 0 28 | B1->B0 | 2727 4545 | 0 1 | (1 1) (0 0)
2536 13:08:07.110530 1 1 0 | B1->B0 | 3a3a 4545 | 1 0 | (0 0) (0 0)
2537 13:08:07.113220 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 13:08:07.117141 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 13:08:07.123204 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 13:08:07.126685 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 13:08:07.130173 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 13:08:07.137092 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 13:08:07.140504 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2544 13:08:07.143760 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2545 13:08:07.150438 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 13:08:07.153483 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 13:08:07.157355 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 13:08:07.160667 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 13:08:07.167439 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 13:08:07.170152 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 13:08:07.173803 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 13:08:07.180765 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 13:08:07.183888 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 13:08:07.187173 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 13:08:07.193921 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 13:08:07.197473 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 13:08:07.200499 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 13:08:07.207249 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 13:08:07.210452 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2560 13:08:07.214133 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2561 13:08:07.217044 Total UI for P1: 0, mck2ui 16
2562 13:08:07.220352 best dqsien dly found for B0: ( 1, 3, 28)
2563 13:08:07.227099 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 13:08:07.227204 Total UI for P1: 0, mck2ui 16
2565 13:08:07.230330 best dqsien dly found for B1: ( 1, 3, 30)
2566 13:08:07.237350 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2567 13:08:07.240457 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2568 13:08:07.240556
2569 13:08:07.244081 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2570 13:08:07.247221 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2571 13:08:07.250443 [Gating] SW calibration Done
2572 13:08:07.250523 ==
2573 13:08:07.254127 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 13:08:07.257303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 13:08:07.257378 ==
2576 13:08:07.260589 RX Vref Scan: 0
2577 13:08:07.260666
2578 13:08:07.260725 RX Vref 0 -> 0, step: 1
2579 13:08:07.260778
2580 13:08:07.263927 RX Delay -40 -> 252, step: 8
2581 13:08:07.267245 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2582 13:08:07.270582 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2583 13:08:07.277187 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2584 13:08:07.280597 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2585 13:08:07.284513 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2586 13:08:07.287733 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2587 13:08:07.291061 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2588 13:08:07.297350 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2589 13:08:07.300797 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2590 13:08:07.304046 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2591 13:08:07.307376 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2592 13:08:07.310778 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2593 13:08:07.317397 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2594 13:08:07.320588 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2595 13:08:07.324462 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2596 13:08:07.327373 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2597 13:08:07.327450 ==
2598 13:08:07.331361 Dram Type= 6, Freq= 0, CH_0, rank 0
2599 13:08:07.334521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2600 13:08:07.337941 ==
2601 13:08:07.338072 DQS Delay:
2602 13:08:07.338162 DQS0 = 0, DQS1 = 0
2603 13:08:07.341371 DQM Delay:
2604 13:08:07.341468 DQM0 = 121, DQM1 = 113
2605 13:08:07.344865 DQ Delay:
2606 13:08:07.347728 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2607 13:08:07.350981 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2608 13:08:07.354741 DQ8 =99, DQ9 =107, DQ10 =115, DQ11 =107
2609 13:08:07.357860 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2610 13:08:07.357986
2611 13:08:07.358111
2612 13:08:07.358181 ==
2613 13:08:07.361171 Dram Type= 6, Freq= 0, CH_0, rank 0
2614 13:08:07.364171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2615 13:08:07.364327 ==
2616 13:08:07.364435
2617 13:08:07.364526
2618 13:08:07.367784 TX Vref Scan disable
2619 13:08:07.371560 == TX Byte 0 ==
2620 13:08:07.374274 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2621 13:08:07.377910 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2622 13:08:07.381183 == TX Byte 1 ==
2623 13:08:07.384542 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2624 13:08:07.387818 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2625 13:08:07.387948 ==
2626 13:08:07.390891 Dram Type= 6, Freq= 0, CH_0, rank 0
2627 13:08:07.397867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2628 13:08:07.398022 ==
2629 13:08:07.408488 TX Vref=22, minBit 0, minWin=25, winSum=407
2630 13:08:07.411838 TX Vref=24, minBit 0, minWin=25, winSum=412
2631 13:08:07.414610 TX Vref=26, minBit 7, minWin=25, winSum=421
2632 13:08:07.417916 TX Vref=28, minBit 4, minWin=26, winSum=426
2633 13:08:07.421366 TX Vref=30, minBit 13, minWin=25, winSum=425
2634 13:08:07.427924 TX Vref=32, minBit 0, minWin=26, winSum=422
2635 13:08:07.431345 [TxChooseVref] Worse bit 4, Min win 26, Win sum 426, Final Vref 28
2636 13:08:07.431424
2637 13:08:07.434639 Final TX Range 1 Vref 28
2638 13:08:07.434716
2639 13:08:07.434775 ==
2640 13:08:07.437831 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 13:08:07.441129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 13:08:07.441240 ==
2643 13:08:07.441336
2644 13:08:07.445104
2645 13:08:07.445181 TX Vref Scan disable
2646 13:08:07.448472 == TX Byte 0 ==
2647 13:08:07.451065 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2648 13:08:07.455064 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2649 13:08:07.458201 == TX Byte 1 ==
2650 13:08:07.461294 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2651 13:08:07.464628 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2652 13:08:07.464749
2653 13:08:07.468161 [DATLAT]
2654 13:08:07.468288 Freq=1200, CH0 RK0
2655 13:08:07.468378
2656 13:08:07.471370 DATLAT Default: 0xd
2657 13:08:07.471481 0, 0xFFFF, sum = 0
2658 13:08:07.474836 1, 0xFFFF, sum = 0
2659 13:08:07.474946 2, 0xFFFF, sum = 0
2660 13:08:07.477952 3, 0xFFFF, sum = 0
2661 13:08:07.478086 4, 0xFFFF, sum = 0
2662 13:08:07.481664 5, 0xFFFF, sum = 0
2663 13:08:07.481802 6, 0xFFFF, sum = 0
2664 13:08:07.485388 7, 0xFFFF, sum = 0
2665 13:08:07.485535 8, 0xFFFF, sum = 0
2666 13:08:07.488402 9, 0xFFFF, sum = 0
2667 13:08:07.491569 10, 0xFFFF, sum = 0
2668 13:08:07.491688 11, 0xFFFF, sum = 0
2669 13:08:07.494753 12, 0x0, sum = 1
2670 13:08:07.494860 13, 0x0, sum = 2
2671 13:08:07.494926 14, 0x0, sum = 3
2672 13:08:07.497885 15, 0x0, sum = 4
2673 13:08:07.498074 best_step = 13
2674 13:08:07.498184
2675 13:08:07.501642 ==
2676 13:08:07.501801 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 13:08:07.507927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 13:08:07.508057 ==
2679 13:08:07.508122 RX Vref Scan: 1
2680 13:08:07.508178
2681 13:08:07.511258 Set Vref Range= 32 -> 127
2682 13:08:07.511374
2683 13:08:07.514599 RX Vref 32 -> 127, step: 1
2684 13:08:07.514682
2685 13:08:07.517852 RX Delay -13 -> 252, step: 4
2686 13:08:07.517933
2687 13:08:07.521894 Set Vref, RX VrefLevel [Byte0]: 32
2688 13:08:07.524630 [Byte1]: 32
2689 13:08:07.524709
2690 13:08:07.528110 Set Vref, RX VrefLevel [Byte0]: 33
2691 13:08:07.531543 [Byte1]: 33
2692 13:08:07.531622
2693 13:08:07.534743 Set Vref, RX VrefLevel [Byte0]: 34
2694 13:08:07.537976 [Byte1]: 34
2695 13:08:07.541825
2696 13:08:07.541939 Set Vref, RX VrefLevel [Byte0]: 35
2697 13:08:07.545344 [Byte1]: 35
2698 13:08:07.550154
2699 13:08:07.550236 Set Vref, RX VrefLevel [Byte0]: 36
2700 13:08:07.553674 [Byte1]: 36
2701 13:08:07.557749
2702 13:08:07.557831 Set Vref, RX VrefLevel [Byte0]: 37
2703 13:08:07.561088 [Byte1]: 37
2704 13:08:07.566117
2705 13:08:07.566195 Set Vref, RX VrefLevel [Byte0]: 38
2706 13:08:07.569268 [Byte1]: 38
2707 13:08:07.574164
2708 13:08:07.574264 Set Vref, RX VrefLevel [Byte0]: 39
2709 13:08:07.577215 [Byte1]: 39
2710 13:08:07.581748
2711 13:08:07.581868 Set Vref, RX VrefLevel [Byte0]: 40
2712 13:08:07.585067 [Byte1]: 40
2713 13:08:07.589207
2714 13:08:07.589347 Set Vref, RX VrefLevel [Byte0]: 41
2715 13:08:07.592572 [Byte1]: 41
2716 13:08:07.597016
2717 13:08:07.597151 Set Vref, RX VrefLevel [Byte0]: 42
2718 13:08:07.600625 [Byte1]: 42
2719 13:08:07.605218
2720 13:08:07.605298 Set Vref, RX VrefLevel [Byte0]: 43
2721 13:08:07.608820 [Byte1]: 43
2722 13:08:07.613457
2723 13:08:07.613538 Set Vref, RX VrefLevel [Byte0]: 44
2724 13:08:07.616526 [Byte1]: 44
2725 13:08:07.621184
2726 13:08:07.621263 Set Vref, RX VrefLevel [Byte0]: 45
2727 13:08:07.624550 [Byte1]: 45
2728 13:08:07.629075
2729 13:08:07.629155 Set Vref, RX VrefLevel [Byte0]: 46
2730 13:08:07.632456 [Byte1]: 46
2731 13:08:07.636964
2732 13:08:07.637044 Set Vref, RX VrefLevel [Byte0]: 47
2733 13:08:07.640250 [Byte1]: 47
2734 13:08:07.645033
2735 13:08:07.645126 Set Vref, RX VrefLevel [Byte0]: 48
2736 13:08:07.648398 [Byte1]: 48
2737 13:08:07.652249
2738 13:08:07.652330 Set Vref, RX VrefLevel [Byte0]: 49
2739 13:08:07.656072 [Byte1]: 49
2740 13:08:07.660171
2741 13:08:07.660251 Set Vref, RX VrefLevel [Byte0]: 50
2742 13:08:07.663502 [Byte1]: 50
2743 13:08:07.668843
2744 13:08:07.668922 Set Vref, RX VrefLevel [Byte0]: 51
2745 13:08:07.671659 [Byte1]: 51
2746 13:08:07.676329
2747 13:08:07.676405 Set Vref, RX VrefLevel [Byte0]: 52
2748 13:08:07.679620 [Byte1]: 52
2749 13:08:07.684218
2750 13:08:07.684320 Set Vref, RX VrefLevel [Byte0]: 53
2751 13:08:07.687465 [Byte1]: 53
2752 13:08:07.692214
2753 13:08:07.692316 Set Vref, RX VrefLevel [Byte0]: 54
2754 13:08:07.695729 [Byte1]: 54
2755 13:08:07.699657
2756 13:08:07.699758 Set Vref, RX VrefLevel [Byte0]: 55
2757 13:08:07.703020 [Byte1]: 55
2758 13:08:07.707583
2759 13:08:07.707702 Set Vref, RX VrefLevel [Byte0]: 56
2760 13:08:07.710855 [Byte1]: 56
2761 13:08:07.715897
2762 13:08:07.715981 Set Vref, RX VrefLevel [Byte0]: 57
2763 13:08:07.719194 [Byte1]: 57
2764 13:08:07.723781
2765 13:08:07.723865 Set Vref, RX VrefLevel [Byte0]: 58
2766 13:08:07.727126 [Byte1]: 58
2767 13:08:07.731597
2768 13:08:07.731676 Set Vref, RX VrefLevel [Byte0]: 59
2769 13:08:07.734613 [Byte1]: 59
2770 13:08:07.739735
2771 13:08:07.739814 Set Vref, RX VrefLevel [Byte0]: 60
2772 13:08:07.742602 [Byte1]: 60
2773 13:08:07.747509
2774 13:08:07.747591 Set Vref, RX VrefLevel [Byte0]: 61
2775 13:08:07.750912 [Byte1]: 61
2776 13:08:07.754938
2777 13:08:07.755019 Set Vref, RX VrefLevel [Byte0]: 62
2778 13:08:07.758709 [Byte1]: 62
2779 13:08:07.763191
2780 13:08:07.763299 Set Vref, RX VrefLevel [Byte0]: 63
2781 13:08:07.766450 [Byte1]: 63
2782 13:08:07.771087
2783 13:08:07.771184 Set Vref, RX VrefLevel [Byte0]: 64
2784 13:08:07.774466 [Byte1]: 64
2785 13:08:07.779194
2786 13:08:07.779291 Set Vref, RX VrefLevel [Byte0]: 65
2787 13:08:07.782586 [Byte1]: 65
2788 13:08:07.786578
2789 13:08:07.786681 Set Vref, RX VrefLevel [Byte0]: 66
2790 13:08:07.790484 [Byte1]: 66
2791 13:08:07.794372
2792 13:08:07.794454 Set Vref, RX VrefLevel [Byte0]: 67
2793 13:08:07.798103 [Byte1]: 67
2794 13:08:07.802886
2795 13:08:07.802965 Final RX Vref Byte 0 = 55 to rank0
2796 13:08:07.805673 Final RX Vref Byte 1 = 48 to rank0
2797 13:08:07.809158 Final RX Vref Byte 0 = 55 to rank1
2798 13:08:07.812392 Final RX Vref Byte 1 = 48 to rank1==
2799 13:08:07.815699 Dram Type= 6, Freq= 0, CH_0, rank 0
2800 13:08:07.822244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2801 13:08:07.822328 ==
2802 13:08:07.822389 DQS Delay:
2803 13:08:07.825532 DQS0 = 0, DQS1 = 0
2804 13:08:07.825610 DQM Delay:
2805 13:08:07.825669 DQM0 = 120, DQM1 = 111
2806 13:08:07.828726 DQ Delay:
2807 13:08:07.831982 DQ0 =120, DQ1 =120, DQ2 =120, DQ3 =118
2808 13:08:07.835412 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2809 13:08:07.838775 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =104
2810 13:08:07.841959 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2811 13:08:07.842079
2812 13:08:07.842165
2813 13:08:07.852516 [DQSOSCAuto] RK0, (LSB)MR18= 0x160f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2814 13:08:07.852604 CH0 RK0: MR19=404, MR18=160F
2815 13:08:07.859235 CH0_RK0: MR19=0x404, MR18=0x160F, DQSOSC=401, MR23=63, INC=40, DEC=27
2816 13:08:07.859316
2817 13:08:07.862261 ----->DramcWriteLeveling(PI) begin...
2818 13:08:07.862339 ==
2819 13:08:07.865943 Dram Type= 6, Freq= 0, CH_0, rank 1
2820 13:08:07.869011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2821 13:08:07.872274 ==
2822 13:08:07.875726 Write leveling (Byte 0): 34 => 34
2823 13:08:07.875803 Write leveling (Byte 1): 29 => 29
2824 13:08:07.879015 DramcWriteLeveling(PI) end<-----
2825 13:08:07.879091
2826 13:08:07.879150 ==
2827 13:08:07.882434 Dram Type= 6, Freq= 0, CH_0, rank 1
2828 13:08:07.889202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2829 13:08:07.889281 ==
2830 13:08:07.892243 [Gating] SW mode calibration
2831 13:08:07.899002 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2832 13:08:07.902620 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2833 13:08:07.905933 0 15 0 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 0)
2834 13:08:07.912488 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 13:08:07.915827 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 13:08:07.919213 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 13:08:07.925747 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 13:08:07.929158 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 13:08:07.932313 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 13:08:07.939418 0 15 28 | B1->B0 | 2f2f 2d2d | 1 1 | (1 0) (1 0)
2841 13:08:07.942590 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2842 13:08:07.946092 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 13:08:07.952746 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 13:08:07.956200 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 13:08:07.959554 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 13:08:07.965964 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 13:08:07.969668 1 0 24 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
2848 13:08:07.972954 1 0 28 | B1->B0 | 3c3c 3939 | 0 0 | (0 0) (0 0)
2849 13:08:07.976386 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 13:08:07.982824 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 13:08:07.985931 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 13:08:07.989426 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 13:08:07.996268 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 13:08:07.999728 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 13:08:08.003025 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2856 13:08:08.009913 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2857 13:08:08.012917 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2858 13:08:08.016856 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 13:08:08.022985 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 13:08:08.026349 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 13:08:08.030205 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 13:08:08.036215 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 13:08:08.039348 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 13:08:08.043110 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 13:08:08.049669 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 13:08:08.053021 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 13:08:08.056525 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 13:08:08.059874 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 13:08:08.066649 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 13:08:08.070167 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 13:08:08.072821 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2872 13:08:08.079597 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2873 13:08:08.083303 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2874 13:08:08.086426 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 13:08:08.089961 Total UI for P1: 0, mck2ui 16
2876 13:08:08.092959 best dqsien dly found for B0: ( 1, 3, 30)
2877 13:08:08.096849 Total UI for P1: 0, mck2ui 16
2878 13:08:08.099856 best dqsien dly found for B1: ( 1, 3, 28)
2879 13:08:08.103089 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2880 13:08:08.106552 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2881 13:08:08.106631
2882 13:08:08.109772 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2883 13:08:08.116444 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2884 13:08:08.116524 [Gating] SW calibration Done
2885 13:08:08.120329 ==
2886 13:08:08.120407 Dram Type= 6, Freq= 0, CH_0, rank 1
2887 13:08:08.126652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 13:08:08.126734 ==
2889 13:08:08.126794 RX Vref Scan: 0
2890 13:08:08.126847
2891 13:08:08.129787 RX Vref 0 -> 0, step: 1
2892 13:08:08.129864
2893 13:08:08.133676 RX Delay -40 -> 252, step: 8
2894 13:08:08.136675 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2895 13:08:08.139664 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2896 13:08:08.143594 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2897 13:08:08.150138 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2898 13:08:08.153209 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2899 13:08:08.157087 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2900 13:08:08.160453 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2901 13:08:08.163237 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2902 13:08:08.166711 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2903 13:08:08.173473 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2904 13:08:08.176842 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2905 13:08:08.180284 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2906 13:08:08.183651 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2907 13:08:08.187025 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2908 13:08:08.193668 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2909 13:08:08.197063 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2910 13:08:08.197141 ==
2911 13:08:08.200397 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 13:08:08.203430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 13:08:08.203507 ==
2914 13:08:08.206992 DQS Delay:
2915 13:08:08.207069 DQS0 = 0, DQS1 = 0
2916 13:08:08.207130 DQM Delay:
2917 13:08:08.210350 DQM0 = 122, DQM1 = 111
2918 13:08:08.210428 DQ Delay:
2919 13:08:08.213599 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2920 13:08:08.216635 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2921 13:08:08.220710 DQ8 =99, DQ9 =103, DQ10 =107, DQ11 =103
2922 13:08:08.226749 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2923 13:08:08.226831
2924 13:08:08.226889
2925 13:08:08.226942 ==
2926 13:08:08.230189 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 13:08:08.233355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 13:08:08.233432 ==
2929 13:08:08.233492
2930 13:08:08.233546
2931 13:08:08.236644 TX Vref Scan disable
2932 13:08:08.236720 == TX Byte 0 ==
2933 13:08:08.243963 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2934 13:08:08.247123 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2935 13:08:08.247202 == TX Byte 1 ==
2936 13:08:08.253393 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2937 13:08:08.257098 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2938 13:08:08.257179 ==
2939 13:08:08.260350 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 13:08:08.263451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 13:08:08.263530 ==
2942 13:08:08.276784 TX Vref=22, minBit 1, minWin=25, winSum=408
2943 13:08:08.280171 TX Vref=24, minBit 1, minWin=25, winSum=416
2944 13:08:08.283473 TX Vref=26, minBit 3, minWin=25, winSum=420
2945 13:08:08.286666 TX Vref=28, minBit 0, minWin=26, winSum=422
2946 13:08:08.290063 TX Vref=30, minBit 3, minWin=26, winSum=426
2947 13:08:08.296744 TX Vref=32, minBit 12, minWin=25, winSum=422
2948 13:08:08.300141 [TxChooseVref] Worse bit 3, Min win 26, Win sum 426, Final Vref 30
2949 13:08:08.300223
2950 13:08:08.303509 Final TX Range 1 Vref 30
2951 13:08:08.303613
2952 13:08:08.303700 ==
2953 13:08:08.306933 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 13:08:08.310291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 13:08:08.310368 ==
2956 13:08:08.310427
2957 13:08:08.313657
2958 13:08:08.313732 TX Vref Scan disable
2959 13:08:08.316862 == TX Byte 0 ==
2960 13:08:08.320295 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2961 13:08:08.323283 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2962 13:08:08.326840 == TX Byte 1 ==
2963 13:08:08.329951 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2964 13:08:08.333438 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2965 13:08:08.333515
2966 13:08:08.336622 [DATLAT]
2967 13:08:08.336697 Freq=1200, CH0 RK1
2968 13:08:08.336757
2969 13:08:08.340124 DATLAT Default: 0xd
2970 13:08:08.340200 0, 0xFFFF, sum = 0
2971 13:08:08.343389 1, 0xFFFF, sum = 0
2972 13:08:08.343468 2, 0xFFFF, sum = 0
2973 13:08:08.346735 3, 0xFFFF, sum = 0
2974 13:08:08.346813 4, 0xFFFF, sum = 0
2975 13:08:08.350283 5, 0xFFFF, sum = 0
2976 13:08:08.350360 6, 0xFFFF, sum = 0
2977 13:08:08.353599 7, 0xFFFF, sum = 0
2978 13:08:08.356939 8, 0xFFFF, sum = 0
2979 13:08:08.357017 9, 0xFFFF, sum = 0
2980 13:08:08.359842 10, 0xFFFF, sum = 0
2981 13:08:08.359920 11, 0xFFFF, sum = 0
2982 13:08:08.363151 12, 0x0, sum = 1
2983 13:08:08.363228 13, 0x0, sum = 2
2984 13:08:08.363287 14, 0x0, sum = 3
2985 13:08:08.367013 15, 0x0, sum = 4
2986 13:08:08.367090 best_step = 13
2987 13:08:08.367149
2988 13:08:08.370288 ==
2989 13:08:08.370367 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 13:08:08.376983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 13:08:08.377065 ==
2992 13:08:08.377124 RX Vref Scan: 0
2993 13:08:08.377179
2994 13:08:08.380359 RX Vref 0 -> 0, step: 1
2995 13:08:08.380438
2996 13:08:08.383657 RX Delay -13 -> 252, step: 4
2997 13:08:08.386973 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
2998 13:08:08.390427 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
2999 13:08:08.397186 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3000 13:08:08.400391 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3001 13:08:08.403762 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3002 13:08:08.407221 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3003 13:08:08.410674 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3004 13:08:08.416790 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3005 13:08:08.420134 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3006 13:08:08.423533 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3007 13:08:08.426742 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3008 13:08:08.430587 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3009 13:08:08.437088 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3010 13:08:08.440094 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3011 13:08:08.444036 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3012 13:08:08.446911 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3013 13:08:08.446993 ==
3014 13:08:08.450456 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 13:08:08.453951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 13:08:08.457099 ==
3017 13:08:08.457175 DQS Delay:
3018 13:08:08.457234 DQS0 = 0, DQS1 = 0
3019 13:08:08.460295 DQM Delay:
3020 13:08:08.460370 DQM0 = 121, DQM1 = 110
3021 13:08:08.463683 DQ Delay:
3022 13:08:08.467600 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3023 13:08:08.470937 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3024 13:08:08.473800 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3025 13:08:08.477176 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =118
3026 13:08:08.477253
3027 13:08:08.477311
3028 13:08:08.483872 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 403 ps
3029 13:08:08.487590 CH0 RK1: MR19=403, MR18=10F1
3030 13:08:08.494225 CH0_RK1: MR19=0x403, MR18=0x10F1, DQSOSC=403, MR23=63, INC=40, DEC=26
3031 13:08:08.497118 [RxdqsGatingPostProcess] freq 1200
3032 13:08:08.504126 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3033 13:08:08.504214 best DQS0 dly(2T, 0.5T) = (0, 11)
3034 13:08:08.507405 best DQS1 dly(2T, 0.5T) = (0, 11)
3035 13:08:08.510779 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3036 13:08:08.514212 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3037 13:08:08.517512 best DQS0 dly(2T, 0.5T) = (0, 11)
3038 13:08:08.520947 best DQS1 dly(2T, 0.5T) = (0, 11)
3039 13:08:08.524343 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3040 13:08:08.527778 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3041 13:08:08.531194 Pre-setting of DQS Precalculation
3042 13:08:08.534471 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3043 13:08:08.537642 ==
3044 13:08:08.537747 Dram Type= 6, Freq= 0, CH_1, rank 0
3045 13:08:08.544048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 13:08:08.544202 ==
3047 13:08:08.547347 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3048 13:08:08.554124 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3049 13:08:08.563214 [CA 0] Center 37 (7~68) winsize 62
3050 13:08:08.566362 [CA 1] Center 37 (7~68) winsize 62
3051 13:08:08.569877 [CA 2] Center 35 (5~65) winsize 61
3052 13:08:08.573368 [CA 3] Center 34 (4~64) winsize 61
3053 13:08:08.576394 [CA 4] Center 34 (4~64) winsize 61
3054 13:08:08.580156 [CA 5] Center 33 (3~63) winsize 61
3055 13:08:08.580233
3056 13:08:08.583319 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3057 13:08:08.583395
3058 13:08:08.586558 [CATrainingPosCal] consider 1 rank data
3059 13:08:08.589783 u2DelayCellTimex100 = 270/100 ps
3060 13:08:08.592836 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3061 13:08:08.596751 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3062 13:08:08.603368 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3063 13:08:08.606575 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3064 13:08:08.609565 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3065 13:08:08.613097 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3066 13:08:08.613174
3067 13:08:08.616378 CA PerBit enable=1, Macro0, CA PI delay=33
3068 13:08:08.616455
3069 13:08:08.619553 [CBTSetCACLKResult] CA Dly = 33
3070 13:08:08.619631 CS Dly: 8 (0~39)
3071 13:08:08.623018 ==
3072 13:08:08.623097 Dram Type= 6, Freq= 0, CH_1, rank 1
3073 13:08:08.629707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 13:08:08.629785 ==
3075 13:08:08.632569 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3076 13:08:08.639357 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3077 13:08:08.648824 [CA 0] Center 37 (7~68) winsize 62
3078 13:08:08.652089 [CA 1] Center 37 (7~68) winsize 62
3079 13:08:08.655396 [CA 2] Center 35 (5~65) winsize 61
3080 13:08:08.658852 [CA 3] Center 34 (4~65) winsize 62
3081 13:08:08.662083 [CA 4] Center 34 (4~65) winsize 62
3082 13:08:08.665400 [CA 5] Center 34 (4~64) winsize 61
3083 13:08:08.665496
3084 13:08:08.668658 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3085 13:08:08.668747
3086 13:08:08.671930 [CATrainingPosCal] consider 2 rank data
3087 13:08:08.675721 u2DelayCellTimex100 = 270/100 ps
3088 13:08:08.678905 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3089 13:08:08.682074 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3090 13:08:08.688423 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3091 13:08:08.691997 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3092 13:08:08.695544 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3093 13:08:08.698607 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3094 13:08:08.698685
3095 13:08:08.702282 CA PerBit enable=1, Macro0, CA PI delay=33
3096 13:08:08.702373
3097 13:08:08.705455 [CBTSetCACLKResult] CA Dly = 33
3098 13:08:08.705531 CS Dly: 9 (0~41)
3099 13:08:08.705589
3100 13:08:08.708788 ----->DramcWriteLeveling(PI) begin...
3101 13:08:08.711990 ==
3102 13:08:08.715459 Dram Type= 6, Freq= 0, CH_1, rank 0
3103 13:08:08.718903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 13:08:08.718981 ==
3105 13:08:08.722035 Write leveling (Byte 0): 24 => 24
3106 13:08:08.725155 Write leveling (Byte 1): 27 => 27
3107 13:08:08.728566 DramcWriteLeveling(PI) end<-----
3108 13:08:08.728657
3109 13:08:08.728717 ==
3110 13:08:08.732009 Dram Type= 6, Freq= 0, CH_1, rank 0
3111 13:08:08.734965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 13:08:08.735046 ==
3113 13:08:08.738297 [Gating] SW mode calibration
3114 13:08:08.744962 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3115 13:08:08.751555 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3116 13:08:08.755205 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 13:08:08.758381 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 13:08:08.765085 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 13:08:08.768456 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 13:08:08.771748 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 13:08:08.778435 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 13:08:08.781680 0 15 24 | B1->B0 | 3131 2a2a | 1 0 | (0 1) (0 1)
3123 13:08:08.785035 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3124 13:08:08.791073 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 13:08:08.794438 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 13:08:08.797714 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 13:08:08.804370 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 13:08:08.808015 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 13:08:08.811154 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3130 13:08:08.814779 1 0 24 | B1->B0 | 3737 4343 | 0 0 | (0 0) (0 0)
3131 13:08:08.821255 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3132 13:08:08.824556 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 13:08:08.827887 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 13:08:08.834351 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 13:08:08.838122 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 13:08:08.841322 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 13:08:08.847831 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 13:08:08.851085 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3139 13:08:08.854469 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3140 13:08:08.861151 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 13:08:08.864662 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 13:08:08.867653 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 13:08:08.874215 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 13:08:08.877566 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 13:08:08.880689 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 13:08:08.887383 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 13:08:08.891304 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 13:08:08.894314 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 13:08:08.901148 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 13:08:08.904466 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 13:08:08.907722 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 13:08:08.914600 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 13:08:08.917947 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 13:08:08.921417 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3155 13:08:08.928014 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3156 13:08:08.928095 Total UI for P1: 0, mck2ui 16
3157 13:08:08.931053 best dqsien dly found for B1: ( 1, 3, 24)
3158 13:08:08.937579 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 13:08:08.940843 Total UI for P1: 0, mck2ui 16
3160 13:08:08.944675 best dqsien dly found for B0: ( 1, 3, 26)
3161 13:08:08.947377 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3162 13:08:08.950810 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3163 13:08:08.950894
3164 13:08:08.954508 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3165 13:08:08.957635 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3166 13:08:08.960659 [Gating] SW calibration Done
3167 13:08:08.960735 ==
3168 13:08:08.964525 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 13:08:08.967831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 13:08:08.967904 ==
3171 13:08:08.971141 RX Vref Scan: 0
3172 13:08:08.971216
3173 13:08:08.974237 RX Vref 0 -> 0, step: 1
3174 13:08:08.974313
3175 13:08:08.974372 RX Delay -40 -> 252, step: 8
3176 13:08:08.980597 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3177 13:08:08.983814 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3178 13:08:08.987236 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3179 13:08:08.990629 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3180 13:08:08.994201 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3181 13:08:09.000676 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3182 13:08:09.003849 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3183 13:08:09.007282 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3184 13:08:09.010625 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3185 13:08:09.013838 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3186 13:08:09.020912 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3187 13:08:09.024390 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3188 13:08:09.027174 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3189 13:08:09.031129 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3190 13:08:09.034192 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3191 13:08:09.040296 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3192 13:08:09.040378 ==
3193 13:08:09.044175 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 13:08:09.047320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 13:08:09.047400 ==
3196 13:08:09.047460 DQS Delay:
3197 13:08:09.050757 DQS0 = 0, DQS1 = 0
3198 13:08:09.050834 DQM Delay:
3199 13:08:09.054047 DQM0 = 119, DQM1 = 116
3200 13:08:09.054139 DQ Delay:
3201 13:08:09.057481 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3202 13:08:09.060735 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3203 13:08:09.064150 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3204 13:08:09.067460 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3205 13:08:09.067538
3206 13:08:09.070625
3207 13:08:09.070701 ==
3208 13:08:09.073521 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 13:08:09.077267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 13:08:09.077345 ==
3211 13:08:09.077404
3212 13:08:09.077458
3213 13:08:09.080908 TX Vref Scan disable
3214 13:08:09.081025 == TX Byte 0 ==
3215 13:08:09.087165 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3216 13:08:09.090762 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3217 13:08:09.090842 == TX Byte 1 ==
3218 13:08:09.097487 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3219 13:08:09.100204 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3220 13:08:09.100284 ==
3221 13:08:09.103504 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 13:08:09.106844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 13:08:09.106920 ==
3224 13:08:09.118839 TX Vref=22, minBit 11, minWin=24, winSum=410
3225 13:08:09.122228 TX Vref=24, minBit 0, minWin=26, winSum=422
3226 13:08:09.125554 TX Vref=26, minBit 10, minWin=25, winSum=425
3227 13:08:09.129417 TX Vref=28, minBit 1, minWin=26, winSum=427
3228 13:08:09.132073 TX Vref=30, minBit 1, minWin=26, winSum=428
3229 13:08:09.138803 TX Vref=32, minBit 0, minWin=26, winSum=425
3230 13:08:09.142527 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 30
3231 13:08:09.142603
3232 13:08:09.145560 Final TX Range 1 Vref 30
3233 13:08:09.145637
3234 13:08:09.145696 ==
3235 13:08:09.148766 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 13:08:09.152245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 13:08:09.152322 ==
3238 13:08:09.155810
3239 13:08:09.155886
3240 13:08:09.155945 TX Vref Scan disable
3241 13:08:09.159266 == TX Byte 0 ==
3242 13:08:09.162616 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3243 13:08:09.166072 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3244 13:08:09.168737 == TX Byte 1 ==
3245 13:08:09.172196 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3246 13:08:09.175532 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3247 13:08:09.179414
3248 13:08:09.179489 [DATLAT]
3249 13:08:09.179547 Freq=1200, CH1 RK0
3250 13:08:09.179601
3251 13:08:09.182594 DATLAT Default: 0xd
3252 13:08:09.182670 0, 0xFFFF, sum = 0
3253 13:08:09.185585 1, 0xFFFF, sum = 0
3254 13:08:09.185663 2, 0xFFFF, sum = 0
3255 13:08:09.189200 3, 0xFFFF, sum = 0
3256 13:08:09.189292 4, 0xFFFF, sum = 0
3257 13:08:09.192333 5, 0xFFFF, sum = 0
3258 13:08:09.195714 6, 0xFFFF, sum = 0
3259 13:08:09.195791 7, 0xFFFF, sum = 0
3260 13:08:09.199417 8, 0xFFFF, sum = 0
3261 13:08:09.199494 9, 0xFFFF, sum = 0
3262 13:08:09.202381 10, 0xFFFF, sum = 0
3263 13:08:09.202458 11, 0xFFFF, sum = 0
3264 13:08:09.205614 12, 0x0, sum = 1
3265 13:08:09.205690 13, 0x0, sum = 2
3266 13:08:09.209539 14, 0x0, sum = 3
3267 13:08:09.209615 15, 0x0, sum = 4
3268 13:08:09.209675 best_step = 13
3269 13:08:09.209729
3270 13:08:09.212145 ==
3271 13:08:09.215942 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 13:08:09.219350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 13:08:09.219429 ==
3274 13:08:09.219506 RX Vref Scan: 1
3275 13:08:09.219578
3276 13:08:09.222723 Set Vref Range= 32 -> 127
3277 13:08:09.222802
3278 13:08:09.225968 RX Vref 32 -> 127, step: 1
3279 13:08:09.226094
3280 13:08:09.229317 RX Delay -5 -> 252, step: 4
3281 13:08:09.229395
3282 13:08:09.232410 Set Vref, RX VrefLevel [Byte0]: 32
3283 13:08:09.235535 [Byte1]: 32
3284 13:08:09.235613
3285 13:08:09.238827 Set Vref, RX VrefLevel [Byte0]: 33
3286 13:08:09.242355 [Byte1]: 33
3287 13:08:09.242433
3288 13:08:09.245629 Set Vref, RX VrefLevel [Byte0]: 34
3289 13:08:09.248936 [Byte1]: 34
3290 13:08:09.253418
3291 13:08:09.253496 Set Vref, RX VrefLevel [Byte0]: 35
3292 13:08:09.256650 [Byte1]: 35
3293 13:08:09.261031
3294 13:08:09.261109 Set Vref, RX VrefLevel [Byte0]: 36
3295 13:08:09.264549 [Byte1]: 36
3296 13:08:09.269152
3297 13:08:09.269230 Set Vref, RX VrefLevel [Byte0]: 37
3298 13:08:09.272511 [Byte1]: 37
3299 13:08:09.276617
3300 13:08:09.276694 Set Vref, RX VrefLevel [Byte0]: 38
3301 13:08:09.279835 [Byte1]: 38
3302 13:08:09.284586
3303 13:08:09.284663 Set Vref, RX VrefLevel [Byte0]: 39
3304 13:08:09.287899 [Byte1]: 39
3305 13:08:09.292522
3306 13:08:09.292596 Set Vref, RX VrefLevel [Byte0]: 40
3307 13:08:09.295859 [Byte1]: 40
3308 13:08:09.300345
3309 13:08:09.300420 Set Vref, RX VrefLevel [Byte0]: 41
3310 13:08:09.303442 [Byte1]: 41
3311 13:08:09.307863
3312 13:08:09.307938 Set Vref, RX VrefLevel [Byte0]: 42
3313 13:08:09.311452 [Byte1]: 42
3314 13:08:09.316059
3315 13:08:09.316129 Set Vref, RX VrefLevel [Byte0]: 43
3316 13:08:09.319321 [Byte1]: 43
3317 13:08:09.323813
3318 13:08:09.323911 Set Vref, RX VrefLevel [Byte0]: 44
3319 13:08:09.327369 [Byte1]: 44
3320 13:08:09.331697
3321 13:08:09.331794 Set Vref, RX VrefLevel [Byte0]: 45
3322 13:08:09.335062 [Byte1]: 45
3323 13:08:09.339491
3324 13:08:09.339567 Set Vref, RX VrefLevel [Byte0]: 46
3325 13:08:09.342578 [Byte1]: 46
3326 13:08:09.347340
3327 13:08:09.347416 Set Vref, RX VrefLevel [Byte0]: 47
3328 13:08:09.350696 [Byte1]: 47
3329 13:08:09.355177
3330 13:08:09.355252 Set Vref, RX VrefLevel [Byte0]: 48
3331 13:08:09.358191 [Byte1]: 48
3332 13:08:09.363279
3333 13:08:09.363379 Set Vref, RX VrefLevel [Byte0]: 49
3334 13:08:09.366488 [Byte1]: 49
3335 13:08:09.370959
3336 13:08:09.371033 Set Vref, RX VrefLevel [Byte0]: 50
3337 13:08:09.373976 [Byte1]: 50
3338 13:08:09.378668
3339 13:08:09.378762 Set Vref, RX VrefLevel [Byte0]: 51
3340 13:08:09.382107 [Byte1]: 51
3341 13:08:09.386824
3342 13:08:09.386914 Set Vref, RX VrefLevel [Byte0]: 52
3343 13:08:09.390258 [Byte1]: 52
3344 13:08:09.394130
3345 13:08:09.394205 Set Vref, RX VrefLevel [Byte0]: 53
3346 13:08:09.398143 [Byte1]: 53
3347 13:08:09.402251
3348 13:08:09.402352 Set Vref, RX VrefLevel [Byte0]: 54
3349 13:08:09.405608 [Byte1]: 54
3350 13:08:09.410350
3351 13:08:09.410442 Set Vref, RX VrefLevel [Byte0]: 55
3352 13:08:09.413718 [Byte1]: 55
3353 13:08:09.417770
3354 13:08:09.417860 Set Vref, RX VrefLevel [Byte0]: 56
3355 13:08:09.421119 [Byte1]: 56
3356 13:08:09.425669
3357 13:08:09.425795 Set Vref, RX VrefLevel [Byte0]: 57
3358 13:08:09.429563 [Byte1]: 57
3359 13:08:09.433907
3360 13:08:09.433982 Set Vref, RX VrefLevel [Byte0]: 58
3361 13:08:09.437133 [Byte1]: 58
3362 13:08:09.441402
3363 13:08:09.441476 Set Vref, RX VrefLevel [Byte0]: 59
3364 13:08:09.444666 [Byte1]: 59
3365 13:08:09.449477
3366 13:08:09.449553 Set Vref, RX VrefLevel [Byte0]: 60
3367 13:08:09.452834 [Byte1]: 60
3368 13:08:09.457008
3369 13:08:09.457108 Set Vref, RX VrefLevel [Byte0]: 61
3370 13:08:09.460637 [Byte1]: 61
3371 13:08:09.465182
3372 13:08:09.465258 Set Vref, RX VrefLevel [Byte0]: 62
3373 13:08:09.468334 [Byte1]: 62
3374 13:08:09.473016
3375 13:08:09.473091 Set Vref, RX VrefLevel [Byte0]: 63
3376 13:08:09.475954 [Byte1]: 63
3377 13:08:09.480623
3378 13:08:09.480699 Set Vref, RX VrefLevel [Byte0]: 64
3379 13:08:09.484270 [Byte1]: 64
3380 13:08:09.488438
3381 13:08:09.488515 Set Vref, RX VrefLevel [Byte0]: 65
3382 13:08:09.491820 [Byte1]: 65
3383 13:08:09.496442
3384 13:08:09.496519 Set Vref, RX VrefLevel [Byte0]: 66
3385 13:08:09.499952 [Byte1]: 66
3386 13:08:09.504576
3387 13:08:09.504710 Set Vref, RX VrefLevel [Byte0]: 67
3388 13:08:09.507941 [Byte1]: 67
3389 13:08:09.512779
3390 13:08:09.512898 Set Vref, RX VrefLevel [Byte0]: 68
3391 13:08:09.515488 [Byte1]: 68
3392 13:08:09.520194
3393 13:08:09.520276 Final RX Vref Byte 0 = 55 to rank0
3394 13:08:09.523487 Final RX Vref Byte 1 = 53 to rank0
3395 13:08:09.526753 Final RX Vref Byte 0 = 55 to rank1
3396 13:08:09.530207 Final RX Vref Byte 1 = 53 to rank1==
3397 13:08:09.533501 Dram Type= 6, Freq= 0, CH_1, rank 0
3398 13:08:09.540133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3399 13:08:09.540240 ==
3400 13:08:09.540302 DQS Delay:
3401 13:08:09.540357 DQS0 = 0, DQS1 = 0
3402 13:08:09.543435 DQM Delay:
3403 13:08:09.543512 DQM0 = 120, DQM1 = 117
3404 13:08:09.546584 DQ Delay:
3405 13:08:09.550229 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3406 13:08:09.553330 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3407 13:08:09.556666 DQ8 =104, DQ9 =108, DQ10 =118, DQ11 =112
3408 13:08:09.559772 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3409 13:08:09.559851
3410 13:08:09.559929
3411 13:08:09.569585 [DQSOSCAuto] RK0, (LSB)MR18= 0x517, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3412 13:08:09.569669 CH1 RK0: MR19=404, MR18=517
3413 13:08:09.576131 CH1_RK0: MR19=0x404, MR18=0x517, DQSOSC=401, MR23=63, INC=40, DEC=27
3414 13:08:09.576208
3415 13:08:09.579466 ----->DramcWriteLeveling(PI) begin...
3416 13:08:09.579542 ==
3417 13:08:09.583287 Dram Type= 6, Freq= 0, CH_1, rank 1
3418 13:08:09.586459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3419 13:08:09.589630 ==
3420 13:08:09.593127 Write leveling (Byte 0): 26 => 26
3421 13:08:09.593208 Write leveling (Byte 1): 28 => 28
3422 13:08:09.596513 DramcWriteLeveling(PI) end<-----
3423 13:08:09.596588
3424 13:08:09.596647 ==
3425 13:08:09.599519 Dram Type= 6, Freq= 0, CH_1, rank 1
3426 13:08:09.606318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3427 13:08:09.606400 ==
3428 13:08:09.609630 [Gating] SW mode calibration
3429 13:08:09.616336 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3430 13:08:09.619751 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3431 13:08:09.625824 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3432 13:08:09.629154 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3433 13:08:09.632567 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3434 13:08:09.639352 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 13:08:09.642715 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 13:08:09.646128 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3437 13:08:09.652795 0 15 24 | B1->B0 | 2b2b 3333 | 0 0 | (0 1) (0 0)
3438 13:08:09.655849 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3439 13:08:09.659081 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3440 13:08:09.662387 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3441 13:08:09.669641 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3442 13:08:09.672879 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 13:08:09.676086 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 13:08:09.682791 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3445 13:08:09.686171 1 0 24 | B1->B0 | 4343 2c2c | 0 1 | (0 0) (0 0)
3446 13:08:09.689525 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3447 13:08:09.696175 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3448 13:08:09.699455 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 13:08:09.702438 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 13:08:09.709236 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 13:08:09.712574 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 13:08:09.716281 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3453 13:08:09.722360 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3454 13:08:09.726188 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3455 13:08:09.729334 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 13:08:09.735943 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 13:08:09.739244 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 13:08:09.742773 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 13:08:09.749575 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 13:08:09.752299 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 13:08:09.755520 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 13:08:09.762531 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 13:08:09.765733 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 13:08:09.769123 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 13:08:09.775537 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 13:08:09.778827 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 13:08:09.782129 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 13:08:09.788840 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3469 13:08:09.792154 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3470 13:08:09.795486 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3471 13:08:09.798801 Total UI for P1: 0, mck2ui 16
3472 13:08:09.802282 best dqsien dly found for B1: ( 1, 3, 22)
3473 13:08:09.805647 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 13:08:09.809015 Total UI for P1: 0, mck2ui 16
3475 13:08:09.812283 best dqsien dly found for B0: ( 1, 3, 26)
3476 13:08:09.815727 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3477 13:08:09.819169 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3478 13:08:09.822483
3479 13:08:09.825713 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3480 13:08:09.828930 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3481 13:08:09.832632 [Gating] SW calibration Done
3482 13:08:09.832715 ==
3483 13:08:09.835894 Dram Type= 6, Freq= 0, CH_1, rank 1
3484 13:08:09.839265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3485 13:08:09.839360 ==
3486 13:08:09.839422 RX Vref Scan: 0
3487 13:08:09.839477
3488 13:08:09.842052 RX Vref 0 -> 0, step: 1
3489 13:08:09.842195
3490 13:08:09.845476 RX Delay -40 -> 252, step: 8
3491 13:08:09.848558 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3492 13:08:09.852179 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3493 13:08:09.858468 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3494 13:08:09.862421 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3495 13:08:09.865634 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3496 13:08:09.868698 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3497 13:08:09.872073 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3498 13:08:09.878702 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3499 13:08:09.882227 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3500 13:08:09.885565 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3501 13:08:09.888864 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3502 13:08:09.892227 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3503 13:08:09.898843 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3504 13:08:09.902032 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3505 13:08:09.905588 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3506 13:08:09.908844 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3507 13:08:09.908977 ==
3508 13:08:09.911640 Dram Type= 6, Freq= 0, CH_1, rank 1
3509 13:08:09.918487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3510 13:08:09.918644 ==
3511 13:08:09.918759 DQS Delay:
3512 13:08:09.921905 DQS0 = 0, DQS1 = 0
3513 13:08:09.922068 DQM Delay:
3514 13:08:09.925364 DQM0 = 119, DQM1 = 117
3515 13:08:09.925509 DQ Delay:
3516 13:08:09.928672 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115
3517 13:08:09.932010 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3518 13:08:09.935438 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3519 13:08:09.938827 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3520 13:08:09.938951
3521 13:08:09.939046
3522 13:08:09.939133 ==
3523 13:08:09.942224 Dram Type= 6, Freq= 0, CH_1, rank 1
3524 13:08:09.945467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3525 13:08:09.948287 ==
3526 13:08:09.948386
3527 13:08:09.948458
3528 13:08:09.948526 TX Vref Scan disable
3529 13:08:09.951755 == TX Byte 0 ==
3530 13:08:09.955102 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3531 13:08:09.958363 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3532 13:08:09.961929 == TX Byte 1 ==
3533 13:08:09.965042 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3534 13:08:09.968597 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3535 13:08:09.971829 ==
3536 13:08:09.971910 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 13:08:09.977938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 13:08:09.978064 ==
3539 13:08:09.988887 TX Vref=22, minBit 9, minWin=25, winSum=420
3540 13:08:09.992424 TX Vref=24, minBit 9, minWin=25, winSum=426
3541 13:08:09.995492 TX Vref=26, minBit 1, minWin=26, winSum=425
3542 13:08:09.999142 TX Vref=28, minBit 1, minWin=26, winSum=430
3543 13:08:10.002317 TX Vref=30, minBit 2, minWin=26, winSum=431
3544 13:08:10.006118 TX Vref=32, minBit 9, minWin=26, winSum=434
3545 13:08:10.012429 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 32
3546 13:08:10.012651
3547 13:08:10.016380 Final TX Range 1 Vref 32
3548 13:08:10.016507
3549 13:08:10.016569 ==
3550 13:08:10.019234 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 13:08:10.022484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 13:08:10.022616 ==
3553 13:08:10.022700
3554 13:08:10.025769
3555 13:08:10.025896 TX Vref Scan disable
3556 13:08:10.029253 == TX Byte 0 ==
3557 13:08:10.032604 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3558 13:08:10.036038 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3559 13:08:10.039338 == TX Byte 1 ==
3560 13:08:10.042658 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3561 13:08:10.046017 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3562 13:08:10.046115
3563 13:08:10.049184 [DATLAT]
3564 13:08:10.049267 Freq=1200, CH1 RK1
3565 13:08:10.049344
3566 13:08:10.052584 DATLAT Default: 0xd
3567 13:08:10.052662 0, 0xFFFF, sum = 0
3568 13:08:10.055996 1, 0xFFFF, sum = 0
3569 13:08:10.056076 2, 0xFFFF, sum = 0
3570 13:08:10.059479 3, 0xFFFF, sum = 0
3571 13:08:10.059559 4, 0xFFFF, sum = 0
3572 13:08:10.062713 5, 0xFFFF, sum = 0
3573 13:08:10.062795 6, 0xFFFF, sum = 0
3574 13:08:10.065909 7, 0xFFFF, sum = 0
3575 13:08:10.065989 8, 0xFFFF, sum = 0
3576 13:08:10.069404 9, 0xFFFF, sum = 0
3577 13:08:10.072773 10, 0xFFFF, sum = 0
3578 13:08:10.072852 11, 0xFFFF, sum = 0
3579 13:08:10.075473 12, 0x0, sum = 1
3580 13:08:10.075556 13, 0x0, sum = 2
3581 13:08:10.078793 14, 0x0, sum = 3
3582 13:08:10.078869 15, 0x0, sum = 4
3583 13:08:10.078929 best_step = 13
3584 13:08:10.078983
3585 13:08:10.082197 ==
3586 13:08:10.085632 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 13:08:10.089016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 13:08:10.089092 ==
3589 13:08:10.089152 RX Vref Scan: 0
3590 13:08:10.089206
3591 13:08:10.092438 RX Vref 0 -> 0, step: 1
3592 13:08:10.092538
3593 13:08:10.095789 RX Delay -5 -> 252, step: 4
3594 13:08:10.098749 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3595 13:08:10.102437 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3596 13:08:10.108954 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3597 13:08:10.112555 iDelay=195, Bit 3, Center 114 (55 ~ 174) 120
3598 13:08:10.115552 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3599 13:08:10.118890 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3600 13:08:10.122876 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3601 13:08:10.128952 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3602 13:08:10.132182 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3603 13:08:10.135880 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3604 13:08:10.139265 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3605 13:08:10.142429 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3606 13:08:10.148977 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3607 13:08:10.152419 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3608 13:08:10.155809 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3609 13:08:10.159341 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3610 13:08:10.159725 ==
3611 13:08:10.161961 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 13:08:10.168734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 13:08:10.169066 ==
3614 13:08:10.169320 DQS Delay:
3615 13:08:10.172283 DQS0 = 0, DQS1 = 0
3616 13:08:10.172609 DQM Delay:
3617 13:08:10.175833 DQM0 = 119, DQM1 = 118
3618 13:08:10.176160 DQ Delay:
3619 13:08:10.179288 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =114
3620 13:08:10.181860 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3621 13:08:10.185902 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3622 13:08:10.188709 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3623 13:08:10.189037
3624 13:08:10.189289
3625 13:08:10.198970 [DQSOSCAuto] RK1, (LSB)MR18= 0x13f0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3626 13:08:10.199348 CH1 RK1: MR19=403, MR18=13F0
3627 13:08:10.205740 CH1_RK1: MR19=0x403, MR18=0x13F0, DQSOSC=402, MR23=63, INC=40, DEC=27
3628 13:08:10.209061 [RxdqsGatingPostProcess] freq 1200
3629 13:08:10.215495 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3630 13:08:10.218904 best DQS0 dly(2T, 0.5T) = (0, 11)
3631 13:08:10.221609 best DQS1 dly(2T, 0.5T) = (0, 11)
3632 13:08:10.224997 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3633 13:08:10.228312 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3634 13:08:10.232124 best DQS0 dly(2T, 0.5T) = (0, 11)
3635 13:08:10.235361 best DQS1 dly(2T, 0.5T) = (0, 11)
3636 13:08:10.235497 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3637 13:08:10.238582 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3638 13:08:10.241501 Pre-setting of DQS Precalculation
3639 13:08:10.248791 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3640 13:08:10.254975 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3641 13:08:10.261940 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3642 13:08:10.262042
3643 13:08:10.262133
3644 13:08:10.265319 [Calibration Summary] 2400 Mbps
3645 13:08:10.268743 CH 0, Rank 0
3646 13:08:10.268823 SW Impedance : PASS
3647 13:08:10.271855 DUTY Scan : NO K
3648 13:08:10.271938 ZQ Calibration : PASS
3649 13:08:10.275150 Jitter Meter : NO K
3650 13:08:10.278705 CBT Training : PASS
3651 13:08:10.278791 Write leveling : PASS
3652 13:08:10.281612 RX DQS gating : PASS
3653 13:08:10.285009 RX DQ/DQS(RDDQC) : PASS
3654 13:08:10.285102 TX DQ/DQS : PASS
3655 13:08:10.288224 RX DATLAT : PASS
3656 13:08:10.291616 RX DQ/DQS(Engine): PASS
3657 13:08:10.291718 TX OE : NO K
3658 13:08:10.295029 All Pass.
3659 13:08:10.295140
3660 13:08:10.295225 CH 0, Rank 1
3661 13:08:10.298476 SW Impedance : PASS
3662 13:08:10.298601 DUTY Scan : NO K
3663 13:08:10.301817 ZQ Calibration : PASS
3664 13:08:10.305316 Jitter Meter : NO K
3665 13:08:10.305455 CBT Training : PASS
3666 13:08:10.308423 Write leveling : PASS
3667 13:08:10.311787 RX DQS gating : PASS
3668 13:08:10.311946 RX DQ/DQS(RDDQC) : PASS
3669 13:08:10.315222 TX DQ/DQS : PASS
3670 13:08:10.315407 RX DATLAT : PASS
3671 13:08:10.318557 RX DQ/DQS(Engine): PASS
3672 13:08:10.321925 TX OE : NO K
3673 13:08:10.322172 All Pass.
3674 13:08:10.322345
3675 13:08:10.322504 CH 1, Rank 0
3676 13:08:10.325369 SW Impedance : PASS
3677 13:08:10.328186 DUTY Scan : NO K
3678 13:08:10.328513 ZQ Calibration : PASS
3679 13:08:10.332186 Jitter Meter : NO K
3680 13:08:10.335004 CBT Training : PASS
3681 13:08:10.335431 Write leveling : PASS
3682 13:08:10.339029 RX DQS gating : PASS
3683 13:08:10.341721 RX DQ/DQS(RDDQC) : PASS
3684 13:08:10.342059 TX DQ/DQS : PASS
3685 13:08:10.345077 RX DATLAT : PASS
3686 13:08:10.348224 RX DQ/DQS(Engine): PASS
3687 13:08:10.348657 TX OE : NO K
3688 13:08:10.351682 All Pass.
3689 13:08:10.352005
3690 13:08:10.352259 CH 1, Rank 1
3691 13:08:10.355026 SW Impedance : PASS
3692 13:08:10.355354 DUTY Scan : NO K
3693 13:08:10.358412 ZQ Calibration : PASS
3694 13:08:10.361729 Jitter Meter : NO K
3695 13:08:10.362124 CBT Training : PASS
3696 13:08:10.365121 Write leveling : PASS
3697 13:08:10.368367 RX DQS gating : PASS
3698 13:08:10.368714 RX DQ/DQS(RDDQC) : PASS
3699 13:08:10.371727 TX DQ/DQS : PASS
3700 13:08:10.374983 RX DATLAT : PASS
3701 13:08:10.375348 RX DQ/DQS(Engine): PASS
3702 13:08:10.377988 TX OE : NO K
3703 13:08:10.378355 All Pass.
3704 13:08:10.378614
3705 13:08:10.381758 DramC Write-DBI off
3706 13:08:10.382123 PER_BANK_REFRESH: Hybrid Mode
3707 13:08:10.385441 TX_TRACKING: ON
3708 13:08:10.394873 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3709 13:08:10.398146 [FAST_K] Save calibration result to emmc
3710 13:08:10.401392 dramc_set_vcore_voltage set vcore to 650000
3711 13:08:10.401720 Read voltage for 600, 5
3712 13:08:10.404871 Vio18 = 0
3713 13:08:10.405234 Vcore = 650000
3714 13:08:10.405496 Vdram = 0
3715 13:08:10.407915 Vddq = 0
3716 13:08:10.408245 Vmddr = 0
3717 13:08:10.414996 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3718 13:08:10.417841 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3719 13:08:10.421691 MEM_TYPE=3, freq_sel=19
3720 13:08:10.424906 sv_algorithm_assistance_LP4_1600
3721 13:08:10.428409 ============ PULL DRAM RESETB DOWN ============
3722 13:08:10.431860 ========== PULL DRAM RESETB DOWN end =========
3723 13:08:10.437806 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3724 13:08:10.441130 ===================================
3725 13:08:10.441459 LPDDR4 DRAM CONFIGURATION
3726 13:08:10.444479 ===================================
3727 13:08:10.447971 EX_ROW_EN[0] = 0x0
3728 13:08:10.448300 EX_ROW_EN[1] = 0x0
3729 13:08:10.451261 LP4Y_EN = 0x0
3730 13:08:10.451668 WORK_FSP = 0x0
3731 13:08:10.454604 WL = 0x2
3732 13:08:10.457979 RL = 0x2
3733 13:08:10.458351 BL = 0x2
3734 13:08:10.461360 RPST = 0x0
3735 13:08:10.461697 RD_PRE = 0x0
3736 13:08:10.465330 WR_PRE = 0x1
3737 13:08:10.465666 WR_PST = 0x0
3738 13:08:10.468623 DBI_WR = 0x0
3739 13:08:10.469026 DBI_RD = 0x0
3740 13:08:10.472073 OTF = 0x1
3741 13:08:10.474835 ===================================
3742 13:08:10.478170 ===================================
3743 13:08:10.478508 ANA top config
3744 13:08:10.481552 ===================================
3745 13:08:10.485481 DLL_ASYNC_EN = 0
3746 13:08:10.485884 ALL_SLAVE_EN = 1
3747 13:08:10.488074 NEW_RANK_MODE = 1
3748 13:08:10.491488 DLL_IDLE_MODE = 1
3749 13:08:10.494795 LP45_APHY_COMB_EN = 1
3750 13:08:10.498592 TX_ODT_DIS = 1
3751 13:08:10.499019 NEW_8X_MODE = 1
3752 13:08:10.501934 ===================================
3753 13:08:10.505227 ===================================
3754 13:08:10.508429 data_rate = 1200
3755 13:08:10.511606 CKR = 1
3756 13:08:10.514757 DQ_P2S_RATIO = 8
3757 13:08:10.518103 ===================================
3758 13:08:10.521569 CA_P2S_RATIO = 8
3759 13:08:10.524924 DQ_CA_OPEN = 0
3760 13:08:10.525249 DQ_SEMI_OPEN = 0
3761 13:08:10.528398 CA_SEMI_OPEN = 0
3762 13:08:10.531699 CA_FULL_RATE = 0
3763 13:08:10.535035 DQ_CKDIV4_EN = 1
3764 13:08:10.538226 CA_CKDIV4_EN = 1
3765 13:08:10.541475 CA_PREDIV_EN = 0
3766 13:08:10.541824 PH8_DLY = 0
3767 13:08:10.544613 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3768 13:08:10.548375 DQ_AAMCK_DIV = 4
3769 13:08:10.551486 CA_AAMCK_DIV = 4
3770 13:08:10.554849 CA_ADMCK_DIV = 4
3771 13:08:10.558086 DQ_TRACK_CA_EN = 0
3772 13:08:10.558439 CA_PICK = 600
3773 13:08:10.561292 CA_MCKIO = 600
3774 13:08:10.564839 MCKIO_SEMI = 0
3775 13:08:10.568169 PLL_FREQ = 2288
3776 13:08:10.571634 DQ_UI_PI_RATIO = 32
3777 13:08:10.574593 CA_UI_PI_RATIO = 0
3778 13:08:10.577830 ===================================
3779 13:08:10.581248 ===================================
3780 13:08:10.584599 memory_type:LPDDR4
3781 13:08:10.584951 GP_NUM : 10
3782 13:08:10.587927 SRAM_EN : 1
3783 13:08:10.588284 MD32_EN : 0
3784 13:08:10.591249 ===================================
3785 13:08:10.594573 [ANA_INIT] >>>>>>>>>>>>>>
3786 13:08:10.597954 <<<<<< [CONFIGURE PHASE]: ANA_TX
3787 13:08:10.601153 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3788 13:08:10.604030 ===================================
3789 13:08:10.607444 data_rate = 1200,PCW = 0X5800
3790 13:08:10.610767 ===================================
3791 13:08:10.614087 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3792 13:08:10.617923 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3793 13:08:10.624574 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3794 13:08:10.627718 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3795 13:08:10.634502 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3796 13:08:10.637965 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3797 13:08:10.638327 [ANA_INIT] flow start
3798 13:08:10.641371 [ANA_INIT] PLL >>>>>>>>
3799 13:08:10.644700 [ANA_INIT] PLL <<<<<<<<
3800 13:08:10.645022 [ANA_INIT] MIDPI >>>>>>>>
3801 13:08:10.647479 [ANA_INIT] MIDPI <<<<<<<<
3802 13:08:10.650691 [ANA_INIT] DLL >>>>>>>>
3803 13:08:10.651014 [ANA_INIT] flow end
3804 13:08:10.654325 ============ LP4 DIFF to SE enter ============
3805 13:08:10.660631 ============ LP4 DIFF to SE exit ============
3806 13:08:10.661074 [ANA_INIT] <<<<<<<<<<<<<
3807 13:08:10.664361 [Flow] Enable top DCM control >>>>>
3808 13:08:10.667511 [Flow] Enable top DCM control <<<<<
3809 13:08:10.671045 Enable DLL master slave shuffle
3810 13:08:10.677714 ==============================================================
3811 13:08:10.678089 Gating Mode config
3812 13:08:10.683786 ==============================================================
3813 13:08:10.687396 Config description:
3814 13:08:10.697503 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3815 13:08:10.704187 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3816 13:08:10.707569 SELPH_MODE 0: By rank 1: By Phase
3817 13:08:10.714390 ==============================================================
3818 13:08:10.717076 GAT_TRACK_EN = 1
3819 13:08:10.720406 RX_GATING_MODE = 2
3820 13:08:10.720734 RX_GATING_TRACK_MODE = 2
3821 13:08:10.723726 SELPH_MODE = 1
3822 13:08:10.727531 PICG_EARLY_EN = 1
3823 13:08:10.730587 VALID_LAT_VALUE = 1
3824 13:08:10.737437 ==============================================================
3825 13:08:10.740239 Enter into Gating configuration >>>>
3826 13:08:10.743656 Exit from Gating configuration <<<<
3827 13:08:10.747072 Enter into DVFS_PRE_config >>>>>
3828 13:08:10.757224 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3829 13:08:10.760498 Exit from DVFS_PRE_config <<<<<
3830 13:08:10.764074 Enter into PICG configuration >>>>
3831 13:08:10.767574 Exit from PICG configuration <<<<
3832 13:08:10.770839 [RX_INPUT] configuration >>>>>
3833 13:08:10.774049 [RX_INPUT] configuration <<<<<
3834 13:08:10.777045 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3835 13:08:10.783849 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3836 13:08:10.790338 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3837 13:08:10.793868 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3838 13:08:10.800395 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3839 13:08:10.806939 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3840 13:08:10.810074 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3841 13:08:10.816802 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3842 13:08:10.820213 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3843 13:08:10.823494 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3844 13:08:10.827155 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3845 13:08:10.833814 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3846 13:08:10.837067 ===================================
3847 13:08:10.837528 LPDDR4 DRAM CONFIGURATION
3848 13:08:10.839954 ===================================
3849 13:08:10.843694 EX_ROW_EN[0] = 0x0
3850 13:08:10.846742 EX_ROW_EN[1] = 0x0
3851 13:08:10.847093 LP4Y_EN = 0x0
3852 13:08:10.850096 WORK_FSP = 0x0
3853 13:08:10.850448 WL = 0x2
3854 13:08:10.853464 RL = 0x2
3855 13:08:10.853813 BL = 0x2
3856 13:08:10.856957 RPST = 0x0
3857 13:08:10.857303 RD_PRE = 0x0
3858 13:08:10.860301 WR_PRE = 0x1
3859 13:08:10.860656 WR_PST = 0x0
3860 13:08:10.863665 DBI_WR = 0x0
3861 13:08:10.864015 DBI_RD = 0x0
3862 13:08:10.867006 OTF = 0x1
3863 13:08:10.870496 ===================================
3864 13:08:10.873278 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3865 13:08:10.876641 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3866 13:08:10.883739 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3867 13:08:10.887009 ===================================
3868 13:08:10.887362 LPDDR4 DRAM CONFIGURATION
3869 13:08:10.890311 ===================================
3870 13:08:10.893546 EX_ROW_EN[0] = 0x10
3871 13:08:10.893930 EX_ROW_EN[1] = 0x0
3872 13:08:10.896838 LP4Y_EN = 0x0
3873 13:08:10.900030 WORK_FSP = 0x0
3874 13:08:10.900382 WL = 0x2
3875 13:08:10.903377 RL = 0x2
3876 13:08:10.903729 BL = 0x2
3877 13:08:10.906772 RPST = 0x0
3878 13:08:10.907125 RD_PRE = 0x0
3879 13:08:10.910087 WR_PRE = 0x1
3880 13:08:10.910438 WR_PST = 0x0
3881 13:08:10.913461 DBI_WR = 0x0
3882 13:08:10.913814 DBI_RD = 0x0
3883 13:08:10.916767 OTF = 0x1
3884 13:08:10.920128 ===================================
3885 13:08:10.926546 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3886 13:08:10.930421 nWR fixed to 30
3887 13:08:10.930785 [ModeRegInit_LP4] CH0 RK0
3888 13:08:10.933414 [ModeRegInit_LP4] CH0 RK1
3889 13:08:10.936858 [ModeRegInit_LP4] CH1 RK0
3890 13:08:10.937220 [ModeRegInit_LP4] CH1 RK1
3891 13:08:10.939829 match AC timing 17
3892 13:08:10.943131 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3893 13:08:10.946889 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3894 13:08:10.953147 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3895 13:08:10.956823 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3896 13:08:10.963171 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3897 13:08:10.963551 ==
3898 13:08:10.966984 Dram Type= 6, Freq= 0, CH_0, rank 0
3899 13:08:10.970120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3900 13:08:10.970480 ==
3901 13:08:10.976920 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3902 13:08:10.980305 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3903 13:08:10.984492 [CA 0] Center 35 (5~66) winsize 62
3904 13:08:10.987737 [CA 1] Center 35 (5~66) winsize 62
3905 13:08:10.990856 [CA 2] Center 33 (3~64) winsize 62
3906 13:08:10.994379 [CA 3] Center 33 (2~64) winsize 63
3907 13:08:10.997705 [CA 4] Center 33 (2~64) winsize 63
3908 13:08:11.000830 [CA 5] Center 32 (2~63) winsize 62
3909 13:08:11.001179
3910 13:08:11.004064 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3911 13:08:11.004419
3912 13:08:11.007597 [CATrainingPosCal] consider 1 rank data
3913 13:08:11.010994 u2DelayCellTimex100 = 270/100 ps
3914 13:08:11.014430 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3915 13:08:11.017647 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3916 13:08:11.024446 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3917 13:08:11.027796 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3918 13:08:11.030621 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3919 13:08:11.033978 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3920 13:08:11.034376
3921 13:08:11.037512 CA PerBit enable=1, Macro0, CA PI delay=32
3922 13:08:11.037872
3923 13:08:11.040897 [CBTSetCACLKResult] CA Dly = 32
3924 13:08:11.041256 CS Dly: 4 (0~35)
3925 13:08:11.044309 ==
3926 13:08:11.044672 Dram Type= 6, Freq= 0, CH_0, rank 1
3927 13:08:11.051046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3928 13:08:11.051408 ==
3929 13:08:11.054225 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3930 13:08:11.060533 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3931 13:08:11.064383 [CA 0] Center 35 (5~66) winsize 62
3932 13:08:11.067485 [CA 1] Center 35 (5~66) winsize 62
3933 13:08:11.070995 [CA 2] Center 33 (3~64) winsize 62
3934 13:08:11.074297 [CA 3] Center 33 (3~64) winsize 62
3935 13:08:11.077522 [CA 4] Center 33 (2~64) winsize 63
3936 13:08:11.081164 [CA 5] Center 32 (2~63) winsize 62
3937 13:08:11.081523
3938 13:08:11.084460 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3939 13:08:11.084812
3940 13:08:11.087527 [CATrainingPosCal] consider 2 rank data
3941 13:08:11.090920 u2DelayCellTimex100 = 270/100 ps
3942 13:08:11.094133 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3943 13:08:11.097708 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3944 13:08:11.104231 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3945 13:08:11.107551 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3946 13:08:11.110952 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3947 13:08:11.114243 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3948 13:08:11.114711
3949 13:08:11.117436 CA PerBit enable=1, Macro0, CA PI delay=32
3950 13:08:11.117826
3951 13:08:11.120755 [CBTSetCACLKResult] CA Dly = 32
3952 13:08:11.121246 CS Dly: 4 (0~36)
3953 13:08:11.121567
3954 13:08:11.124292 ----->DramcWriteLeveling(PI) begin...
3955 13:08:11.127558 ==
3956 13:08:11.130819 Dram Type= 6, Freq= 0, CH_0, rank 0
3957 13:08:11.134052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3958 13:08:11.134416 ==
3959 13:08:11.137633 Write leveling (Byte 0): 34 => 34
3960 13:08:11.140990 Write leveling (Byte 1): 31 => 31
3961 13:08:11.144269 DramcWriteLeveling(PI) end<-----
3962 13:08:11.144617
3963 13:08:11.144885 ==
3964 13:08:11.147552 Dram Type= 6, Freq= 0, CH_0, rank 0
3965 13:08:11.150964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 13:08:11.151422 ==
3967 13:08:11.154426 [Gating] SW mode calibration
3968 13:08:11.160492 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3969 13:08:11.164003 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3970 13:08:11.170873 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3971 13:08:11.174397 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3972 13:08:11.177035 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3973 13:08:11.183927 0 9 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
3974 13:08:11.187370 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
3975 13:08:11.190666 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 13:08:11.197707 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 13:08:11.200641 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 13:08:11.204037 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 13:08:11.210686 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 13:08:11.214033 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3981 13:08:11.217515 0 10 12 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
3982 13:08:11.223769 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
3983 13:08:11.227255 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 13:08:11.230365 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 13:08:11.237376 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 13:08:11.240351 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 13:08:11.243919 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 13:08:11.250453 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 13:08:11.253745 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3990 13:08:11.257118 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3991 13:08:11.263611 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 13:08:11.267116 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 13:08:11.270564 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 13:08:11.276654 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 13:08:11.280146 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 13:08:11.283554 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 13:08:11.290310 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 13:08:11.293731 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 13:08:11.297094 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 13:08:11.303753 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 13:08:11.306471 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 13:08:11.310076 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 13:08:11.316751 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 13:08:11.319836 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 13:08:11.323497 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 13:08:11.329670 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4007 13:08:11.333142 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 13:08:11.336591 Total UI for P1: 0, mck2ui 16
4009 13:08:11.339993 best dqsien dly found for B0: ( 0, 13, 16)
4010 13:08:11.343326 Total UI for P1: 0, mck2ui 16
4011 13:08:11.346362 best dqsien dly found for B1: ( 0, 13, 18)
4012 13:08:11.350037 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4013 13:08:11.353117 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4014 13:08:11.353374
4015 13:08:11.356645 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4016 13:08:11.359632 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4017 13:08:11.362861 [Gating] SW calibration Done
4018 13:08:11.363200 ==
4019 13:08:11.366423 Dram Type= 6, Freq= 0, CH_0, rank 0
4020 13:08:11.369527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 13:08:11.369787 ==
4022 13:08:11.373028 RX Vref Scan: 0
4023 13:08:11.373284
4024 13:08:11.376241 RX Vref 0 -> 0, step: 1
4025 13:08:11.376499
4026 13:08:11.376755 RX Delay -230 -> 252, step: 16
4027 13:08:11.382866 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4028 13:08:11.386750 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4029 13:08:11.390065 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4030 13:08:11.393202 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4031 13:08:11.399989 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4032 13:08:11.403311 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4033 13:08:11.406816 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4034 13:08:11.409542 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4035 13:08:11.412949 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4036 13:08:11.419759 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4037 13:08:11.423043 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4038 13:08:11.426265 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4039 13:08:11.429642 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4040 13:08:11.436162 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4041 13:08:11.439986 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4042 13:08:11.443094 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4043 13:08:11.443481 ==
4044 13:08:11.446310 Dram Type= 6, Freq= 0, CH_0, rank 0
4045 13:08:11.449776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 13:08:11.453199 ==
4047 13:08:11.453592 DQS Delay:
4048 13:08:11.454108 DQS0 = 0, DQS1 = 0
4049 13:08:11.456484 DQM Delay:
4050 13:08:11.456880 DQM0 = 48, DQM1 = 45
4051 13:08:11.459867 DQ Delay:
4052 13:08:11.460260 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4053 13:08:11.463230 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4054 13:08:11.466488 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4055 13:08:11.469911 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4056 13:08:11.470354
4057 13:08:11.472853
4058 13:08:11.473244 ==
4059 13:08:11.476313 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 13:08:11.479536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 13:08:11.479933 ==
4062 13:08:11.480324
4063 13:08:11.480690
4064 13:08:11.482852 TX Vref Scan disable
4065 13:08:11.483246 == TX Byte 0 ==
4066 13:08:11.489800 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4067 13:08:11.492937 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4068 13:08:11.493329 == TX Byte 1 ==
4069 13:08:11.499807 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4070 13:08:11.503279 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4071 13:08:11.503715 ==
4072 13:08:11.506041 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 13:08:11.509301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 13:08:11.509687 ==
4075 13:08:11.509991
4076 13:08:11.510329
4077 13:08:11.512715 TX Vref Scan disable
4078 13:08:11.516245 == TX Byte 0 ==
4079 13:08:11.519832 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4080 13:08:11.523016 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4081 13:08:11.526462 == TX Byte 1 ==
4082 13:08:11.529652 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4083 13:08:11.532928 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4084 13:08:11.533321
4085 13:08:11.536356 [DATLAT]
4086 13:08:11.536837 Freq=600, CH0 RK0
4087 13:08:11.537150
4088 13:08:11.539756 DATLAT Default: 0x9
4089 13:08:11.540259 0, 0xFFFF, sum = 0
4090 13:08:11.542862 1, 0xFFFF, sum = 0
4091 13:08:11.543368 2, 0xFFFF, sum = 0
4092 13:08:11.546087 3, 0xFFFF, sum = 0
4093 13:08:11.546523 4, 0xFFFF, sum = 0
4094 13:08:11.549467 5, 0xFFFF, sum = 0
4095 13:08:11.550045 6, 0xFFFF, sum = 0
4096 13:08:11.552762 7, 0xFFFF, sum = 0
4097 13:08:11.553155 8, 0x0, sum = 1
4098 13:08:11.555882 9, 0x0, sum = 2
4099 13:08:11.556276 10, 0x0, sum = 3
4100 13:08:11.559502 11, 0x0, sum = 4
4101 13:08:11.560018 best_step = 9
4102 13:08:11.560480
4103 13:08:11.560927 ==
4104 13:08:11.562974 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 13:08:11.566505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 13:08:11.569157 ==
4107 13:08:11.569641 RX Vref Scan: 1
4108 13:08:11.570122
4109 13:08:11.572667 RX Vref 0 -> 0, step: 1
4110 13:08:11.573049
4111 13:08:11.575906 RX Delay -163 -> 252, step: 8
4112 13:08:11.576287
4113 13:08:11.579238 Set Vref, RX VrefLevel [Byte0]: 55
4114 13:08:11.582687 [Byte1]: 48
4115 13:08:11.583069
4116 13:08:11.586108 Final RX Vref Byte 0 = 55 to rank0
4117 13:08:11.589618 Final RX Vref Byte 1 = 48 to rank0
4118 13:08:11.592352 Final RX Vref Byte 0 = 55 to rank1
4119 13:08:11.595635 Final RX Vref Byte 1 = 48 to rank1==
4120 13:08:11.599471 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 13:08:11.602505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 13:08:11.602961 ==
4123 13:08:11.605877 DQS Delay:
4124 13:08:11.606316 DQS0 = 0, DQS1 = 0
4125 13:08:11.606622 DQM Delay:
4126 13:08:11.609220 DQM0 = 54, DQM1 = 46
4127 13:08:11.609610 DQ Delay:
4128 13:08:11.612509 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4129 13:08:11.616000 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4130 13:08:11.619092 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4131 13:08:11.622311 DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =52
4132 13:08:11.622713
4133 13:08:11.623013
4134 13:08:11.632842 [DQSOSCAuto] RK0, (LSB)MR18= 0x7467, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4135 13:08:11.633230 CH0 RK0: MR19=808, MR18=7467
4136 13:08:11.639110 CH0_RK0: MR19=0x808, MR18=0x7467, DQSOSC=388, MR23=63, INC=174, DEC=116
4137 13:08:11.639497
4138 13:08:11.642340 ----->DramcWriteLeveling(PI) begin...
4139 13:08:11.642695 ==
4140 13:08:11.645747 Dram Type= 6, Freq= 0, CH_0, rank 1
4141 13:08:11.652314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 13:08:11.652712 ==
4143 13:08:11.655938 Write leveling (Byte 0): 33 => 33
4144 13:08:11.659122 Write leveling (Byte 1): 33 => 33
4145 13:08:11.659602 DramcWriteLeveling(PI) end<-----
4146 13:08:11.659886
4147 13:08:11.662502 ==
4148 13:08:11.665638 Dram Type= 6, Freq= 0, CH_0, rank 1
4149 13:08:11.669263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 13:08:11.669616 ==
4151 13:08:11.672755 [Gating] SW mode calibration
4152 13:08:11.679113 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4153 13:08:11.682604 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4154 13:08:11.689362 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4155 13:08:11.692905 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4156 13:08:11.695648 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4157 13:08:11.702607 0 9 12 | B1->B0 | 3333 3232 | 1 1 | (1 0) (1 0)
4158 13:08:11.705801 0 9 16 | B1->B0 | 2e2e 2828 | 1 0 | (1 0) (0 0)
4159 13:08:11.708872 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4160 13:08:11.715756 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 13:08:11.719043 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 13:08:11.722568 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 13:08:11.729190 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 13:08:11.732560 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 13:08:11.735830 0 10 12 | B1->B0 | 2828 2a2a | 0 1 | (0 0) (0 0)
4166 13:08:11.742073 0 10 16 | B1->B0 | 4343 4343 | 0 1 | (0 0) (0 0)
4167 13:08:11.745408 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 13:08:11.748791 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 13:08:11.752046 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 13:08:11.758767 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 13:08:11.762273 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 13:08:11.765516 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 13:08:11.772194 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4174 13:08:11.775489 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 13:08:11.778799 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 13:08:11.785330 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 13:08:11.788904 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 13:08:11.791822 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 13:08:11.798831 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 13:08:11.802126 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 13:08:11.805496 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 13:08:11.812395 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 13:08:11.815515 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 13:08:11.818851 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 13:08:11.831398 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 13:08:11.831872 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 13:08:11.832538 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 13:08:11.838638 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 13:08:11.842157 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4190 13:08:11.845562 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4191 13:08:11.848621 Total UI for P1: 0, mck2ui 16
4192 13:08:11.851956 best dqsien dly found for B1: ( 0, 13, 12)
4193 13:08:11.855440 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 13:08:11.858748 Total UI for P1: 0, mck2ui 16
4195 13:08:11.861464 best dqsien dly found for B0: ( 0, 13, 14)
4196 13:08:11.868262 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4197 13:08:11.871575 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4198 13:08:11.871692
4199 13:08:11.874945 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4200 13:08:11.878445 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4201 13:08:11.881627 [Gating] SW calibration Done
4202 13:08:11.881745 ==
4203 13:08:11.885006 Dram Type= 6, Freq= 0, CH_0, rank 1
4204 13:08:11.888310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4205 13:08:11.888388 ==
4206 13:08:11.891411 RX Vref Scan: 0
4207 13:08:11.891488
4208 13:08:11.891548 RX Vref 0 -> 0, step: 1
4209 13:08:11.891603
4210 13:08:11.895175 RX Delay -230 -> 252, step: 16
4211 13:08:11.897958 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4212 13:08:11.904644 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4213 13:08:11.907876 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4214 13:08:11.911309 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4215 13:08:11.914482 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4216 13:08:11.921128 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4217 13:08:11.924637 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4218 13:08:11.927913 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4219 13:08:11.931363 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4220 13:08:11.934537 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4221 13:08:11.941102 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4222 13:08:11.944691 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4223 13:08:11.947919 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4224 13:08:11.951002 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4225 13:08:11.957723 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4226 13:08:11.961305 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4227 13:08:11.961384 ==
4228 13:08:11.964780 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 13:08:11.968111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 13:08:11.968190 ==
4231 13:08:11.971507 DQS Delay:
4232 13:08:11.971586 DQS0 = 0, DQS1 = 0
4233 13:08:11.971661 DQM Delay:
4234 13:08:11.974835 DQM0 = 50, DQM1 = 43
4235 13:08:11.974911 DQ Delay:
4236 13:08:11.978175 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4237 13:08:11.981667 DQ4 =57, DQ5 =41, DQ6 =49, DQ7 =57
4238 13:08:11.984368 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4239 13:08:11.988248 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4240 13:08:11.988324
4241 13:08:11.988382
4242 13:08:11.988436 ==
4243 13:08:11.991003 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 13:08:11.997757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 13:08:11.997835 ==
4246 13:08:11.997894
4247 13:08:11.997948
4248 13:08:11.998000 TX Vref Scan disable
4249 13:08:12.001872 == TX Byte 0 ==
4250 13:08:12.004615 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4251 13:08:12.011281 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4252 13:08:12.011358 == TX Byte 1 ==
4253 13:08:12.014516 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4254 13:08:12.017939 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4255 13:08:12.021297 ==
4256 13:08:12.025124 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 13:08:12.028157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 13:08:12.028233 ==
4259 13:08:12.028294
4260 13:08:12.028350
4261 13:08:12.031247 TX Vref Scan disable
4262 13:08:12.031344 == TX Byte 0 ==
4263 13:08:12.037789 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4264 13:08:12.041233 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4265 13:08:12.041310 == TX Byte 1 ==
4266 13:08:12.048194 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4267 13:08:12.051117 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4268 13:08:12.051193
4269 13:08:12.051252 [DATLAT]
4270 13:08:12.054589 Freq=600, CH0 RK1
4271 13:08:12.054667
4272 13:08:12.054726 DATLAT Default: 0x9
4273 13:08:12.058293 0, 0xFFFF, sum = 0
4274 13:08:12.058370 1, 0xFFFF, sum = 0
4275 13:08:12.061081 2, 0xFFFF, sum = 0
4276 13:08:12.061158 3, 0xFFFF, sum = 0
4277 13:08:12.064693 4, 0xFFFF, sum = 0
4278 13:08:12.068272 5, 0xFFFF, sum = 0
4279 13:08:12.068349 6, 0xFFFF, sum = 0
4280 13:08:12.071134 7, 0xFFFF, sum = 0
4281 13:08:12.071212 8, 0x0, sum = 1
4282 13:08:12.071271 9, 0x0, sum = 2
4283 13:08:12.074722 10, 0x0, sum = 3
4284 13:08:12.074799 11, 0x0, sum = 4
4285 13:08:12.078341 best_step = 9
4286 13:08:12.078418
4287 13:08:12.078476 ==
4288 13:08:12.081257 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 13:08:12.084514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 13:08:12.084590 ==
4291 13:08:12.087920 RX Vref Scan: 0
4292 13:08:12.087997
4293 13:08:12.088056 RX Vref 0 -> 0, step: 1
4294 13:08:12.088111
4295 13:08:12.091174 RX Delay -163 -> 252, step: 8
4296 13:08:12.098467 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4297 13:08:12.101986 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4298 13:08:12.105420 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4299 13:08:12.108692 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4300 13:08:12.111542 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4301 13:08:12.118173 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4302 13:08:12.121465 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4303 13:08:12.124871 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4304 13:08:12.128273 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4305 13:08:12.131659 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4306 13:08:12.138153 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4307 13:08:12.141756 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4308 13:08:12.144707 iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272
4309 13:08:12.148511 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4310 13:08:12.154623 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4311 13:08:12.157863 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4312 13:08:12.157950 ==
4313 13:08:12.161767 Dram Type= 6, Freq= 0, CH_0, rank 1
4314 13:08:12.165156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4315 13:08:12.165232 ==
4316 13:08:12.167922 DQS Delay:
4317 13:08:12.167997 DQS0 = 0, DQS1 = 0
4318 13:08:12.168054 DQM Delay:
4319 13:08:12.171288 DQM0 = 53, DQM1 = 46
4320 13:08:12.171363 DQ Delay:
4321 13:08:12.174570 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4322 13:08:12.178032 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =56
4323 13:08:12.181459 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4324 13:08:12.184455 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4325 13:08:12.184530
4326 13:08:12.184588
4327 13:08:12.194562 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e2e, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 389 ps
4328 13:08:12.194639 CH0 RK1: MR19=808, MR18=6E2E
4329 13:08:12.201207 CH0_RK1: MR19=0x808, MR18=0x6E2E, DQSOSC=389, MR23=63, INC=173, DEC=115
4330 13:08:12.204681 [RxdqsGatingPostProcess] freq 600
4331 13:08:12.211206 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4332 13:08:12.214774 Pre-setting of DQS Precalculation
4333 13:08:12.217824 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4334 13:08:12.217900 ==
4335 13:08:12.221186 Dram Type= 6, Freq= 0, CH_1, rank 0
4336 13:08:12.224637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 13:08:12.228009 ==
4338 13:08:12.231368 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4339 13:08:12.238205 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4340 13:08:12.241632 [CA 0] Center 35 (5~66) winsize 62
4341 13:08:12.244316 [CA 1] Center 36 (5~67) winsize 63
4342 13:08:12.247707 [CA 2] Center 34 (4~65) winsize 62
4343 13:08:12.250913 [CA 3] Center 34 (4~65) winsize 62
4344 13:08:12.254654 [CA 4] Center 34 (4~65) winsize 62
4345 13:08:12.257610 [CA 5] Center 33 (3~64) winsize 62
4346 13:08:12.257687
4347 13:08:12.261396 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4348 13:08:12.261473
4349 13:08:12.264689 [CATrainingPosCal] consider 1 rank data
4350 13:08:12.268050 u2DelayCellTimex100 = 270/100 ps
4351 13:08:12.271491 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4352 13:08:12.274204 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4353 13:08:12.277562 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4354 13:08:12.284416 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4355 13:08:12.287251 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4356 13:08:12.290613 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4357 13:08:12.290688
4358 13:08:12.294079 CA PerBit enable=1, Macro0, CA PI delay=33
4359 13:08:12.294155
4360 13:08:12.297462 [CBTSetCACLKResult] CA Dly = 33
4361 13:08:12.297538 CS Dly: 5 (0~36)
4362 13:08:12.297597 ==
4363 13:08:12.300811 Dram Type= 6, Freq= 0, CH_1, rank 1
4364 13:08:12.307323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 13:08:12.307400 ==
4366 13:08:12.310697 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4367 13:08:12.317062 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4368 13:08:12.320523 [CA 0] Center 36 (5~67) winsize 63
4369 13:08:12.324044 [CA 1] Center 36 (5~67) winsize 63
4370 13:08:12.327587 [CA 2] Center 34 (4~65) winsize 62
4371 13:08:12.330607 [CA 3] Center 34 (4~65) winsize 62
4372 13:08:12.333907 [CA 4] Center 35 (4~66) winsize 63
4373 13:08:12.337268 [CA 5] Center 34 (3~65) winsize 63
4374 13:08:12.337345
4375 13:08:12.340537 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4376 13:08:12.340629
4377 13:08:12.343870 [CATrainingPosCal] consider 2 rank data
4378 13:08:12.347376 u2DelayCellTimex100 = 270/100 ps
4379 13:08:12.350722 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4380 13:08:12.354052 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4381 13:08:12.360745 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4382 13:08:12.364519 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4383 13:08:12.367642 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4384 13:08:12.371205 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4385 13:08:12.371281
4386 13:08:12.374196 CA PerBit enable=1, Macro0, CA PI delay=33
4387 13:08:12.374272
4388 13:08:12.377640 [CBTSetCACLKResult] CA Dly = 33
4389 13:08:12.377715 CS Dly: 6 (0~39)
4390 13:08:12.377775
4391 13:08:12.380898 ----->DramcWriteLeveling(PI) begin...
4392 13:08:12.380975 ==
4393 13:08:12.384252 Dram Type= 6, Freq= 0, CH_1, rank 0
4394 13:08:12.391211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4395 13:08:12.391287 ==
4396 13:08:12.394591 Write leveling (Byte 0): 29 => 29
4397 13:08:12.397863 Write leveling (Byte 1): 30 => 30
4398 13:08:12.397938 DramcWriteLeveling(PI) end<-----
4399 13:08:12.401365
4400 13:08:12.401440 ==
4401 13:08:12.404072 Dram Type= 6, Freq= 0, CH_1, rank 0
4402 13:08:12.407521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4403 13:08:12.407619 ==
4404 13:08:12.410841 [Gating] SW mode calibration
4405 13:08:12.417587 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4406 13:08:12.421001 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4407 13:08:12.427820 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4408 13:08:12.431125 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4409 13:08:12.434342 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 1)
4410 13:08:12.440859 0 9 12 | B1->B0 | 2e2e 2f2f | 1 1 | (1 0) (0 0)
4411 13:08:12.444186 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 13:08:12.448012 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 13:08:12.454485 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 13:08:12.457655 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 13:08:12.460507 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 13:08:12.467281 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 13:08:12.471157 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4418 13:08:12.473845 0 10 12 | B1->B0 | 3b3b 3939 | 0 0 | (1 1) (0 0)
4419 13:08:12.480616 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 13:08:12.483750 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 13:08:12.487450 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 13:08:12.493709 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 13:08:12.497160 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 13:08:12.500884 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 13:08:12.507136 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4426 13:08:12.510464 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4427 13:08:12.513802 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 13:08:12.520486 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 13:08:12.523858 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 13:08:12.527220 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 13:08:12.534174 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 13:08:12.537412 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 13:08:12.540541 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 13:08:12.543680 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 13:08:12.550258 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 13:08:12.553574 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 13:08:12.557162 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 13:08:12.563781 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 13:08:12.567274 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 13:08:12.570676 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 13:08:12.577617 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 13:08:12.580632 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 13:08:12.583868 Total UI for P1: 0, mck2ui 16
4444 13:08:12.586957 best dqsien dly found for B0: ( 0, 13, 10)
4445 13:08:12.590572 Total UI for P1: 0, mck2ui 16
4446 13:08:12.594112 best dqsien dly found for B1: ( 0, 13, 10)
4447 13:08:12.597498 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4448 13:08:12.600602 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4449 13:08:12.600825
4450 13:08:12.604045 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4451 13:08:12.607060 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4452 13:08:12.610563 [Gating] SW calibration Done
4453 13:08:12.610867 ==
4454 13:08:12.613670 Dram Type= 6, Freq= 0, CH_1, rank 0
4455 13:08:12.620799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4456 13:08:12.621194 ==
4457 13:08:12.621501 RX Vref Scan: 0
4458 13:08:12.621780
4459 13:08:12.623769 RX Vref 0 -> 0, step: 1
4460 13:08:12.624159
4461 13:08:12.626926 RX Delay -230 -> 252, step: 16
4462 13:08:12.630211 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4463 13:08:12.634175 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4464 13:08:12.636887 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4465 13:08:12.643808 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4466 13:08:12.647122 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4467 13:08:12.650273 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4468 13:08:12.653671 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4469 13:08:12.656815 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4470 13:08:12.663854 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4471 13:08:12.666581 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4472 13:08:12.670169 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4473 13:08:12.673485 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4474 13:08:12.680203 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4475 13:08:12.683603 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4476 13:08:12.687141 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4477 13:08:12.690434 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4478 13:08:12.690980 ==
4479 13:08:12.693692 Dram Type= 6, Freq= 0, CH_1, rank 0
4480 13:08:12.700475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4481 13:08:12.700976 ==
4482 13:08:12.701441 DQS Delay:
4483 13:08:12.703325 DQS0 = 0, DQS1 = 0
4484 13:08:12.703808 DQM Delay:
4485 13:08:12.704250 DQM0 = 52, DQM1 = 49
4486 13:08:12.706800 DQ Delay:
4487 13:08:12.710279 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4488 13:08:12.713728 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4489 13:08:12.717110 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4490 13:08:12.720433 DQ12 =65, DQ13 =57, DQ14 =49, DQ15 =65
4491 13:08:12.720819
4492 13:08:12.721107
4493 13:08:12.721376 ==
4494 13:08:12.723742 Dram Type= 6, Freq= 0, CH_1, rank 0
4495 13:08:12.726980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 13:08:12.727497 ==
4497 13:08:12.727979
4498 13:08:12.728432
4499 13:08:12.730557 TX Vref Scan disable
4500 13:08:12.731040 == TX Byte 0 ==
4501 13:08:12.736787 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4502 13:08:12.740496 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4503 13:08:12.741005 == TX Byte 1 ==
4504 13:08:12.747011 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4505 13:08:12.750067 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4506 13:08:12.750459 ==
4507 13:08:12.753370 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 13:08:12.756650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 13:08:12.757039 ==
4510 13:08:12.757405
4511 13:08:12.757690
4512 13:08:12.759819 TX Vref Scan disable
4513 13:08:12.763611 == TX Byte 0 ==
4514 13:08:12.766717 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4515 13:08:12.770322 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4516 13:08:12.773743 == TX Byte 1 ==
4517 13:08:12.776584 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4518 13:08:12.780021 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4519 13:08:12.783412
4520 13:08:12.783794 [DATLAT]
4521 13:08:12.784126 Freq=600, CH1 RK0
4522 13:08:12.784407
4523 13:08:12.786887 DATLAT Default: 0x9
4524 13:08:12.787304 0, 0xFFFF, sum = 0
4525 13:08:12.790257 1, 0xFFFF, sum = 0
4526 13:08:12.790643 2, 0xFFFF, sum = 0
4527 13:08:12.793652 3, 0xFFFF, sum = 0
4528 13:08:12.794165 4, 0xFFFF, sum = 0
4529 13:08:12.797041 5, 0xFFFF, sum = 0
4530 13:08:12.797487 6, 0xFFFF, sum = 0
4531 13:08:12.799784 7, 0xFFFF, sum = 0
4532 13:08:12.800179 8, 0x0, sum = 1
4533 13:08:12.803704 9, 0x0, sum = 2
4534 13:08:12.804098 10, 0x0, sum = 3
4535 13:08:12.807106 11, 0x0, sum = 4
4536 13:08:12.807499 best_step = 9
4537 13:08:12.807807
4538 13:08:12.808088 ==
4539 13:08:12.809901 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 13:08:12.816441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 13:08:12.816832 ==
4542 13:08:12.817155 RX Vref Scan: 1
4543 13:08:12.817436
4544 13:08:12.820180 RX Vref 0 -> 0, step: 1
4545 13:08:12.820720
4546 13:08:12.823630 RX Delay -163 -> 252, step: 8
4547 13:08:12.824017
4548 13:08:12.826268 Set Vref, RX VrefLevel [Byte0]: 55
4549 13:08:12.830078 [Byte1]: 53
4550 13:08:12.830540
4551 13:08:12.833039 Final RX Vref Byte 0 = 55 to rank0
4552 13:08:12.836707 Final RX Vref Byte 1 = 53 to rank0
4553 13:08:12.840015 Final RX Vref Byte 0 = 55 to rank1
4554 13:08:12.843315 Final RX Vref Byte 1 = 53 to rank1==
4555 13:08:12.846752 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 13:08:12.849961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 13:08:12.850651 ==
4558 13:08:12.852760 DQS Delay:
4559 13:08:12.853305 DQS0 = 0, DQS1 = 0
4560 13:08:12.853845 DQM Delay:
4561 13:08:12.856517 DQM0 = 48, DQM1 = 44
4562 13:08:12.856981 DQ Delay:
4563 13:08:12.859602 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =48
4564 13:08:12.863160 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4565 13:08:12.866629 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4566 13:08:12.869664 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4567 13:08:12.870233
4568 13:08:12.870551
4569 13:08:12.879827 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b70, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4570 13:08:12.880357 CH1 RK0: MR19=808, MR18=4B70
4571 13:08:12.886238 CH1_RK0: MR19=0x808, MR18=0x4B70, DQSOSC=388, MR23=63, INC=174, DEC=116
4572 13:08:12.886765
4573 13:08:12.889711 ----->DramcWriteLeveling(PI) begin...
4574 13:08:12.893014 ==
4575 13:08:12.893685 Dram Type= 6, Freq= 0, CH_1, rank 1
4576 13:08:12.899956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 13:08:12.900615 ==
4578 13:08:12.902653 Write leveling (Byte 0): 29 => 29
4579 13:08:12.906696 Write leveling (Byte 1): 31 => 31
4580 13:08:12.909146 DramcWriteLeveling(PI) end<-----
4581 13:08:12.909424
4582 13:08:12.909640 ==
4583 13:08:12.913341 Dram Type= 6, Freq= 0, CH_1, rank 1
4584 13:08:12.915949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 13:08:12.916190 ==
4586 13:08:12.919357 [Gating] SW mode calibration
4587 13:08:12.926276 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4588 13:08:12.929709 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4589 13:08:12.936038 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4590 13:08:12.939306 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4591 13:08:12.942600 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4592 13:08:12.949268 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (0 0) (0 0)
4593 13:08:12.952754 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4594 13:08:12.955856 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4595 13:08:12.962634 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 13:08:12.965998 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 13:08:12.969505 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 13:08:12.975848 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 13:08:12.979252 0 10 8 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
4600 13:08:12.982549 0 10 12 | B1->B0 | 3a3a 3838 | 0 0 | (0 0) (0 0)
4601 13:08:12.989356 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4602 13:08:12.992817 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 13:08:12.995800 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 13:08:13.002763 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 13:08:13.006344 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 13:08:13.009671 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 13:08:13.015758 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 13:08:13.019247 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 13:08:13.022609 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 13:08:13.029619 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 13:08:13.032792 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 13:08:13.036312 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 13:08:13.042798 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 13:08:13.045524 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 13:08:13.048984 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 13:08:13.052475 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 13:08:13.059451 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 13:08:13.062575 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 13:08:13.066039 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 13:08:13.072660 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 13:08:13.076279 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 13:08:13.079235 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 13:08:13.085807 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 13:08:13.089529 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 13:08:13.092726 Total UI for P1: 0, mck2ui 16
4626 13:08:13.096335 best dqsien dly found for B0: ( 0, 13, 10)
4627 13:08:13.099745 Total UI for P1: 0, mck2ui 16
4628 13:08:13.103016 best dqsien dly found for B1: ( 0, 13, 10)
4629 13:08:13.106208 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4630 13:08:13.109269 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4631 13:08:13.109723
4632 13:08:13.113063 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4633 13:08:13.115733 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4634 13:08:13.119715 [Gating] SW calibration Done
4635 13:08:13.120315 ==
4636 13:08:13.122607 Dram Type= 6, Freq= 0, CH_1, rank 1
4637 13:08:13.125891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 13:08:13.128844 ==
4639 13:08:13.129107 RX Vref Scan: 0
4640 13:08:13.129338
4641 13:08:13.132463 RX Vref 0 -> 0, step: 1
4642 13:08:13.132673
4643 13:08:13.135744 RX Delay -230 -> 252, step: 16
4644 13:08:13.139098 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4645 13:08:13.142550 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4646 13:08:13.145898 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4647 13:08:13.149216 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4648 13:08:13.156015 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4649 13:08:13.159373 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4650 13:08:13.162272 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4651 13:08:13.165626 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4652 13:08:13.172597 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4653 13:08:13.175950 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4654 13:08:13.179371 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4655 13:08:13.182839 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4656 13:08:13.185577 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4657 13:08:13.192690 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4658 13:08:13.195361 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4659 13:08:13.199176 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4660 13:08:13.199387 ==
4661 13:08:13.202079 Dram Type= 6, Freq= 0, CH_1, rank 1
4662 13:08:13.208918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4663 13:08:13.209176 ==
4664 13:08:13.209375 DQS Delay:
4665 13:08:13.209562 DQS0 = 0, DQS1 = 0
4666 13:08:13.212076 DQM Delay:
4667 13:08:13.212332 DQM0 = 50, DQM1 = 48
4668 13:08:13.215318 DQ Delay:
4669 13:08:13.218700 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =49
4670 13:08:13.222512 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4671 13:08:13.225406 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4672 13:08:13.228687 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4673 13:08:13.229100
4674 13:08:13.229365
4675 13:08:13.229602 ==
4676 13:08:13.232289 Dram Type= 6, Freq= 0, CH_1, rank 1
4677 13:08:13.235322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4678 13:08:13.235726 ==
4679 13:08:13.235988
4680 13:08:13.236225
4681 13:08:13.238897 TX Vref Scan disable
4682 13:08:13.239265 == TX Byte 0 ==
4683 13:08:13.245725 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4684 13:08:13.248851 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4685 13:08:13.249179 == TX Byte 1 ==
4686 13:08:13.256097 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4687 13:08:13.258660 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4688 13:08:13.258995 ==
4689 13:08:13.262313 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 13:08:13.265782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 13:08:13.266256 ==
4692 13:08:13.266576
4693 13:08:13.266859
4694 13:08:13.268900 TX Vref Scan disable
4695 13:08:13.272474 == TX Byte 0 ==
4696 13:08:13.275809 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4697 13:08:13.279060 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4698 13:08:13.282735 == TX Byte 1 ==
4699 13:08:13.285309 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4700 13:08:13.288678 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4701 13:08:13.289117
4702 13:08:13.292132 [DATLAT]
4703 13:08:13.292569 Freq=600, CH1 RK1
4704 13:08:13.292956
4705 13:08:13.295558 DATLAT Default: 0x9
4706 13:08:13.295998 0, 0xFFFF, sum = 0
4707 13:08:13.298868 1, 0xFFFF, sum = 0
4708 13:08:13.299288 2, 0xFFFF, sum = 0
4709 13:08:13.302448 3, 0xFFFF, sum = 0
4710 13:08:13.302898 4, 0xFFFF, sum = 0
4711 13:08:13.305801 5, 0xFFFF, sum = 0
4712 13:08:13.306312 6, 0xFFFF, sum = 0
4713 13:08:13.309130 7, 0xFFFF, sum = 0
4714 13:08:13.309447 8, 0x0, sum = 1
4715 13:08:13.312442 9, 0x0, sum = 2
4716 13:08:13.312896 10, 0x0, sum = 3
4717 13:08:13.315870 11, 0x0, sum = 4
4718 13:08:13.316309 best_step = 9
4719 13:08:13.316715
4720 13:08:13.317089 ==
4721 13:08:13.318550 Dram Type= 6, Freq= 0, CH_1, rank 1
4722 13:08:13.325666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4723 13:08:13.326177 ==
4724 13:08:13.326498 RX Vref Scan: 0
4725 13:08:13.326843
4726 13:08:13.328934 RX Vref 0 -> 0, step: 1
4727 13:08:13.329410
4728 13:08:13.331767 RX Delay -163 -> 252, step: 8
4729 13:08:13.335442 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4730 13:08:13.338872 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4731 13:08:13.345588 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4732 13:08:13.348631 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4733 13:08:13.351854 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4734 13:08:13.355209 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4735 13:08:13.358389 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4736 13:08:13.364978 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4737 13:08:13.368457 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4738 13:08:13.371523 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4739 13:08:13.375224 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4740 13:08:13.381838 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4741 13:08:13.385314 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4742 13:08:13.388816 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4743 13:08:13.391539 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4744 13:08:13.395410 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4745 13:08:13.398231 ==
4746 13:08:13.401633 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 13:08:13.404783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 13:08:13.405219 ==
4749 13:08:13.405517 DQS Delay:
4750 13:08:13.408284 DQS0 = 0, DQS1 = 0
4751 13:08:13.408730 DQM Delay:
4752 13:08:13.411538 DQM0 = 48, DQM1 = 45
4753 13:08:13.411975 DQ Delay:
4754 13:08:13.415091 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4755 13:08:13.418471 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4756 13:08:13.421508 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4757 13:08:13.424927 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4758 13:08:13.425389
4759 13:08:13.425828
4760 13:08:13.431703 [DQSOSCAuto] RK1, (LSB)MR18= 0x7026, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 388 ps
4761 13:08:13.435102 CH1 RK1: MR19=808, MR18=7026
4762 13:08:13.441880 CH1_RK1: MR19=0x808, MR18=0x7026, DQSOSC=388, MR23=63, INC=174, DEC=116
4763 13:08:13.444917 [RxdqsGatingPostProcess] freq 600
4764 13:08:13.451241 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4765 13:08:13.451691 Pre-setting of DQS Precalculation
4766 13:08:13.457911 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4767 13:08:13.464551 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4768 13:08:13.471614 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4769 13:08:13.472066
4770 13:08:13.472484
4771 13:08:13.474647 [Calibration Summary] 1200 Mbps
4772 13:08:13.477757 CH 0, Rank 0
4773 13:08:13.478208 SW Impedance : PASS
4774 13:08:13.481667 DUTY Scan : NO K
4775 13:08:13.482178 ZQ Calibration : PASS
4776 13:08:13.484944 Jitter Meter : NO K
4777 13:08:13.488257 CBT Training : PASS
4778 13:08:13.488379 Write leveling : PASS
4779 13:08:13.491037 RX DQS gating : PASS
4780 13:08:13.494458 RX DQ/DQS(RDDQC) : PASS
4781 13:08:13.494557 TX DQ/DQS : PASS
4782 13:08:13.497795 RX DATLAT : PASS
4783 13:08:13.501350 RX DQ/DQS(Engine): PASS
4784 13:08:13.501450 TX OE : NO K
4785 13:08:13.504657 All Pass.
4786 13:08:13.504750
4787 13:08:13.504833 CH 0, Rank 1
4788 13:08:13.507962 SW Impedance : PASS
4789 13:08:13.508060 DUTY Scan : NO K
4790 13:08:13.511566 ZQ Calibration : PASS
4791 13:08:13.514264 Jitter Meter : NO K
4792 13:08:13.514357 CBT Training : PASS
4793 13:08:13.517620 Write leveling : PASS
4794 13:08:13.521025 RX DQS gating : PASS
4795 13:08:13.521117 RX DQ/DQS(RDDQC) : PASS
4796 13:08:13.524397 TX DQ/DQS : PASS
4797 13:08:13.524497 RX DATLAT : PASS
4798 13:08:13.527811 RX DQ/DQS(Engine): PASS
4799 13:08:13.531101 TX OE : NO K
4800 13:08:13.531212 All Pass.
4801 13:08:13.531308
4802 13:08:13.531402 CH 1, Rank 0
4803 13:08:13.534416 SW Impedance : PASS
4804 13:08:13.537667 DUTY Scan : NO K
4805 13:08:13.537785 ZQ Calibration : PASS
4806 13:08:13.541132 Jitter Meter : NO K
4807 13:08:13.544630 CBT Training : PASS
4808 13:08:13.544769 Write leveling : PASS
4809 13:08:13.547410 RX DQS gating : PASS
4810 13:08:13.550829 RX DQ/DQS(RDDQC) : PASS
4811 13:08:13.550980 TX DQ/DQS : PASS
4812 13:08:13.554507 RX DATLAT : PASS
4813 13:08:13.557909 RX DQ/DQS(Engine): PASS
4814 13:08:13.558096 TX OE : NO K
4815 13:08:13.561232 All Pass.
4816 13:08:13.561390
4817 13:08:13.561572 CH 1, Rank 1
4818 13:08:13.564416 SW Impedance : PASS
4819 13:08:13.564664 DUTY Scan : NO K
4820 13:08:13.567781 ZQ Calibration : PASS
4821 13:08:13.571054 Jitter Meter : NO K
4822 13:08:13.571273 CBT Training : PASS
4823 13:08:13.574644 Write leveling : PASS
4824 13:08:13.575016 RX DQS gating : PASS
4825 13:08:13.577604 RX DQ/DQS(RDDQC) : PASS
4826 13:08:13.581242 TX DQ/DQS : PASS
4827 13:08:13.581716 RX DATLAT : PASS
4828 13:08:13.584259 RX DQ/DQS(Engine): PASS
4829 13:08:13.588002 TX OE : NO K
4830 13:08:13.588586 All Pass.
4831 13:08:13.589055
4832 13:08:13.590886 DramC Write-DBI off
4833 13:08:13.591375 PER_BANK_REFRESH: Hybrid Mode
4834 13:08:13.594677 TX_TRACKING: ON
4835 13:08:13.604440 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4836 13:08:13.607415 [FAST_K] Save calibration result to emmc
4837 13:08:13.610907 dramc_set_vcore_voltage set vcore to 662500
4838 13:08:13.611454 Read voltage for 933, 3
4839 13:08:13.614977 Vio18 = 0
4840 13:08:13.615483 Vcore = 662500
4841 13:08:13.615959 Vdram = 0
4842 13:08:13.617587 Vddq = 0
4843 13:08:13.618153 Vmddr = 0
4844 13:08:13.621069 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4845 13:08:13.627770 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4846 13:08:13.630958 MEM_TYPE=3, freq_sel=17
4847 13:08:13.634390 sv_algorithm_assistance_LP4_1600
4848 13:08:13.637684 ============ PULL DRAM RESETB DOWN ============
4849 13:08:13.641123 ========== PULL DRAM RESETB DOWN end =========
4850 13:08:13.647854 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4851 13:08:13.650548 ===================================
4852 13:08:13.651007 LPDDR4 DRAM CONFIGURATION
4853 13:08:13.654089 ===================================
4854 13:08:13.657576 EX_ROW_EN[0] = 0x0
4855 13:08:13.657978 EX_ROW_EN[1] = 0x0
4856 13:08:13.660899 LP4Y_EN = 0x0
4857 13:08:13.661345 WORK_FSP = 0x0
4858 13:08:13.664328 WL = 0x3
4859 13:08:13.664717 RL = 0x3
4860 13:08:13.667721 BL = 0x2
4861 13:08:13.668184 RPST = 0x0
4862 13:08:13.671092 RD_PRE = 0x0
4863 13:08:13.674253 WR_PRE = 0x1
4864 13:08:13.674950 WR_PST = 0x0
4865 13:08:13.678262 DBI_WR = 0x0
4866 13:08:13.678648 DBI_RD = 0x0
4867 13:08:13.680777 OTF = 0x1
4868 13:08:13.684672 ===================================
4869 13:08:13.687725 ===================================
4870 13:08:13.688113 ANA top config
4871 13:08:13.691198 ===================================
4872 13:08:13.694397 DLL_ASYNC_EN = 0
4873 13:08:13.697614 ALL_SLAVE_EN = 1
4874 13:08:13.698040 NEW_RANK_MODE = 1
4875 13:08:13.700837 DLL_IDLE_MODE = 1
4876 13:08:13.704573 LP45_APHY_COMB_EN = 1
4877 13:08:13.708189 TX_ODT_DIS = 1
4878 13:08:13.708585 NEW_8X_MODE = 1
4879 13:08:13.711160 ===================================
4880 13:08:13.714279 ===================================
4881 13:08:13.717830 data_rate = 1866
4882 13:08:13.721157 CKR = 1
4883 13:08:13.724122 DQ_P2S_RATIO = 8
4884 13:08:13.727577 ===================================
4885 13:08:13.731237 CA_P2S_RATIO = 8
4886 13:08:13.734238 DQ_CA_OPEN = 0
4887 13:08:13.734714 DQ_SEMI_OPEN = 0
4888 13:08:13.737327 CA_SEMI_OPEN = 0
4889 13:08:13.741216 CA_FULL_RATE = 0
4890 13:08:13.744511 DQ_CKDIV4_EN = 1
4891 13:08:13.747967 CA_CKDIV4_EN = 1
4892 13:08:13.748352 CA_PREDIV_EN = 0
4893 13:08:13.751409 PH8_DLY = 0
4894 13:08:13.754267 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4895 13:08:13.757565 DQ_AAMCK_DIV = 4
4896 13:08:13.761026 CA_AAMCK_DIV = 4
4897 13:08:13.764543 CA_ADMCK_DIV = 4
4898 13:08:13.764928 DQ_TRACK_CA_EN = 0
4899 13:08:13.768106 CA_PICK = 933
4900 13:08:13.770764 CA_MCKIO = 933
4901 13:08:13.774726 MCKIO_SEMI = 0
4902 13:08:13.777458 PLL_FREQ = 3732
4903 13:08:13.781232 DQ_UI_PI_RATIO = 32
4904 13:08:13.784471 CA_UI_PI_RATIO = 0
4905 13:08:13.787785 ===================================
4906 13:08:13.790977 ===================================
4907 13:08:13.791389 memory_type:LPDDR4
4908 13:08:13.794281 GP_NUM : 10
4909 13:08:13.797435 SRAM_EN : 1
4910 13:08:13.797840 MD32_EN : 0
4911 13:08:13.800627 ===================================
4912 13:08:13.804006 [ANA_INIT] >>>>>>>>>>>>>>
4913 13:08:13.807400 <<<<<< [CONFIGURE PHASE]: ANA_TX
4914 13:08:13.810764 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4915 13:08:13.813957 ===================================
4916 13:08:13.817611 data_rate = 1866,PCW = 0X8f00
4917 13:08:13.820715 ===================================
4918 13:08:13.824282 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4919 13:08:13.827208 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4920 13:08:13.833836 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4921 13:08:13.837718 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4922 13:08:13.840776 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4923 13:08:13.843925 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4924 13:08:13.847487 [ANA_INIT] flow start
4925 13:08:13.850345 [ANA_INIT] PLL >>>>>>>>
4926 13:08:13.850963 [ANA_INIT] PLL <<<<<<<<
4927 13:08:13.854042 [ANA_INIT] MIDPI >>>>>>>>
4928 13:08:13.856841 [ANA_INIT] MIDPI <<<<<<<<
4929 13:08:13.860625 [ANA_INIT] DLL >>>>>>>>
4930 13:08:13.861048 [ANA_INIT] flow end
4931 13:08:13.864042 ============ LP4 DIFF to SE enter ============
4932 13:08:13.870929 ============ LP4 DIFF to SE exit ============
4933 13:08:13.871483 [ANA_INIT] <<<<<<<<<<<<<
4934 13:08:13.873642 [Flow] Enable top DCM control >>>>>
4935 13:08:13.876980 [Flow] Enable top DCM control <<<<<
4936 13:08:13.880397 Enable DLL master slave shuffle
4937 13:08:13.887301 ==============================================================
4938 13:08:13.887752 Gating Mode config
4939 13:08:13.893609 ==============================================================
4940 13:08:13.896784 Config description:
4941 13:08:13.906670 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4942 13:08:13.913337 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4943 13:08:13.917088 SELPH_MODE 0: By rank 1: By Phase
4944 13:08:13.923405 ==============================================================
4945 13:08:13.926842 GAT_TRACK_EN = 1
4946 13:08:13.927361 RX_GATING_MODE = 2
4947 13:08:13.929943 RX_GATING_TRACK_MODE = 2
4948 13:08:13.933187 SELPH_MODE = 1
4949 13:08:13.936786 PICG_EARLY_EN = 1
4950 13:08:13.939980 VALID_LAT_VALUE = 1
4951 13:08:13.946951 ==============================================================
4952 13:08:13.949631 Enter into Gating configuration >>>>
4953 13:08:13.952937 Exit from Gating configuration <<<<
4954 13:08:13.956422 Enter into DVFS_PRE_config >>>>>
4955 13:08:13.966208 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4956 13:08:13.969842 Exit from DVFS_PRE_config <<<<<
4957 13:08:13.973134 Enter into PICG configuration >>>>
4958 13:08:13.976404 Exit from PICG configuration <<<<
4959 13:08:13.979638 [RX_INPUT] configuration >>>>>
4960 13:08:13.982988 [RX_INPUT] configuration <<<<<
4961 13:08:13.986324 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4962 13:08:13.993138 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4963 13:08:13.999463 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4964 13:08:14.005771 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4965 13:08:14.009092 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4966 13:08:14.015604 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4967 13:08:14.019020 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4968 13:08:14.025643 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4969 13:08:14.029024 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4970 13:08:14.032353 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4971 13:08:14.035616 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4972 13:08:14.042647 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4973 13:08:14.045776 ===================================
4974 13:08:14.045846 LPDDR4 DRAM CONFIGURATION
4975 13:08:14.048948 ===================================
4976 13:08:14.052341 EX_ROW_EN[0] = 0x0
4977 13:08:14.055723 EX_ROW_EN[1] = 0x0
4978 13:08:14.055795 LP4Y_EN = 0x0
4979 13:08:14.059168 WORK_FSP = 0x0
4980 13:08:14.059241 WL = 0x3
4981 13:08:14.062367 RL = 0x3
4982 13:08:14.062441 BL = 0x2
4983 13:08:14.065808 RPST = 0x0
4984 13:08:14.065876 RD_PRE = 0x0
4985 13:08:14.068548 WR_PRE = 0x1
4986 13:08:14.068617 WR_PST = 0x0
4987 13:08:14.072042 DBI_WR = 0x0
4988 13:08:14.072108 DBI_RD = 0x0
4989 13:08:14.075387 OTF = 0x1
4990 13:08:14.078701 ===================================
4991 13:08:14.081954 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4992 13:08:14.085783 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4993 13:08:14.092169 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4994 13:08:14.095129 ===================================
4995 13:08:14.095209 LPDDR4 DRAM CONFIGURATION
4996 13:08:14.098714 ===================================
4997 13:08:14.101997 EX_ROW_EN[0] = 0x10
4998 13:08:14.105208 EX_ROW_EN[1] = 0x0
4999 13:08:14.105298 LP4Y_EN = 0x0
5000 13:08:14.108833 WORK_FSP = 0x0
5001 13:08:14.108924 WL = 0x3
5002 13:08:14.111902 RL = 0x3
5003 13:08:14.111973 BL = 0x2
5004 13:08:14.115164 RPST = 0x0
5005 13:08:14.115232 RD_PRE = 0x0
5006 13:08:14.118480 WR_PRE = 0x1
5007 13:08:14.118546 WR_PST = 0x0
5008 13:08:14.121813 DBI_WR = 0x0
5009 13:08:14.121892 DBI_RD = 0x0
5010 13:08:14.125221 OTF = 0x1
5011 13:08:14.128597 ===================================
5012 13:08:14.135146 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5013 13:08:14.138409 nWR fixed to 30
5014 13:08:14.138521 [ModeRegInit_LP4] CH0 RK0
5015 13:08:14.141739 [ModeRegInit_LP4] CH0 RK1
5016 13:08:14.145141 [ModeRegInit_LP4] CH1 RK0
5017 13:08:14.148390 [ModeRegInit_LP4] CH1 RK1
5018 13:08:14.148466 match AC timing 9
5019 13:08:14.155339 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5020 13:08:14.158732 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5021 13:08:14.162036 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5022 13:08:14.168166 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5023 13:08:14.171582 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5024 13:08:14.171671 ==
5025 13:08:14.175090 Dram Type= 6, Freq= 0, CH_0, rank 0
5026 13:08:14.178415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5027 13:08:14.178493 ==
5028 13:08:14.185354 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5029 13:08:14.191432 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5030 13:08:14.194788 [CA 0] Center 37 (6~68) winsize 63
5031 13:08:14.198001 [CA 1] Center 37 (7~68) winsize 62
5032 13:08:14.201792 [CA 2] Center 34 (4~65) winsize 62
5033 13:08:14.204864 [CA 3] Center 34 (3~65) winsize 63
5034 13:08:14.208135 [CA 4] Center 33 (3~64) winsize 62
5035 13:08:14.211734 [CA 5] Center 32 (2~62) winsize 61
5036 13:08:14.211845
5037 13:08:14.214781 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5038 13:08:14.214856
5039 13:08:14.218357 [CATrainingPosCal] consider 1 rank data
5040 13:08:14.221179 u2DelayCellTimex100 = 270/100 ps
5041 13:08:14.224705 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5042 13:08:14.228332 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5043 13:08:14.231410 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5044 13:08:14.234554 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5045 13:08:14.237961 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5046 13:08:14.241144 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5047 13:08:14.241213
5048 13:08:14.248077 CA PerBit enable=1, Macro0, CA PI delay=32
5049 13:08:14.248154
5050 13:08:14.248213 [CBTSetCACLKResult] CA Dly = 32
5051 13:08:14.251283 CS Dly: 5 (0~36)
5052 13:08:14.251357 ==
5053 13:08:14.254813 Dram Type= 6, Freq= 0, CH_0, rank 1
5054 13:08:14.258293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5055 13:08:14.258393 ==
5056 13:08:14.264824 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5057 13:08:14.271725 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5058 13:08:14.275171 [CA 0] Center 37 (6~68) winsize 63
5059 13:08:14.278577 [CA 1] Center 37 (6~68) winsize 63
5060 13:08:14.281314 [CA 2] Center 34 (4~65) winsize 62
5061 13:08:14.284788 [CA 3] Center 34 (3~65) winsize 63
5062 13:08:14.288065 [CA 4] Center 33 (3~63) winsize 61
5063 13:08:14.291508 [CA 5] Center 32 (2~62) winsize 61
5064 13:08:14.291602
5065 13:08:14.294827 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5066 13:08:14.294928
5067 13:08:14.298237 [CATrainingPosCal] consider 2 rank data
5068 13:08:14.301594 u2DelayCellTimex100 = 270/100 ps
5069 13:08:14.305147 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5070 13:08:14.308388 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5071 13:08:14.311754 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5072 13:08:14.315079 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5073 13:08:14.318620 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5074 13:08:14.321326 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5075 13:08:14.321510
5076 13:08:14.328477 CA PerBit enable=1, Macro0, CA PI delay=32
5077 13:08:14.328843
5078 13:08:14.331490 [CBTSetCACLKResult] CA Dly = 32
5079 13:08:14.331852 CS Dly: 5 (0~37)
5080 13:08:14.332181
5081 13:08:14.334769 ----->DramcWriteLeveling(PI) begin...
5082 13:08:14.335109 ==
5083 13:08:14.338496 Dram Type= 6, Freq= 0, CH_0, rank 0
5084 13:08:14.341639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5085 13:08:14.342088 ==
5086 13:08:14.344976 Write leveling (Byte 0): 30 => 30
5087 13:08:14.348334 Write leveling (Byte 1): 29 => 29
5088 13:08:14.351297 DramcWriteLeveling(PI) end<-----
5089 13:08:14.351680
5090 13:08:14.351981 ==
5091 13:08:14.354909 Dram Type= 6, Freq= 0, CH_0, rank 0
5092 13:08:14.361149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5093 13:08:14.361682 ==
5094 13:08:14.361994 [Gating] SW mode calibration
5095 13:08:14.371770 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5096 13:08:14.375032 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5097 13:08:14.378479 0 14 0 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
5098 13:08:14.384920 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5099 13:08:14.388267 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5100 13:08:14.391581 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5101 13:08:14.398568 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 13:08:14.401173 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5103 13:08:14.404656 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5104 13:08:14.411342 0 14 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
5105 13:08:14.414759 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5106 13:08:14.418028 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 13:08:14.424723 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5108 13:08:14.428200 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 13:08:14.430879 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 13:08:14.437476 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 13:08:14.441280 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5112 13:08:14.444326 0 15 28 | B1->B0 | 2828 3a3a | 0 1 | (0 0) (0 0)
5113 13:08:14.451318 1 0 0 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
5114 13:08:14.454637 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 13:08:14.457355 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 13:08:14.464024 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 13:08:14.467247 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 13:08:14.470809 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 13:08:14.477564 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5120 13:08:14.480596 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5121 13:08:14.483876 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5122 13:08:14.490898 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 13:08:14.494141 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 13:08:14.497106 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 13:08:14.503821 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 13:08:14.507310 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 13:08:14.510542 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 13:08:14.517359 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 13:08:14.520756 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 13:08:14.523876 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 13:08:14.530765 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 13:08:14.534324 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 13:08:14.536978 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 13:08:14.543822 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 13:08:14.546980 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 13:08:14.550953 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5137 13:08:14.553954 Total UI for P1: 0, mck2ui 16
5138 13:08:14.557274 best dqsien dly found for B0: ( 1, 2, 26)
5139 13:08:14.560390 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5140 13:08:14.567072 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 13:08:14.570626 Total UI for P1: 0, mck2ui 16
5142 13:08:14.573923 best dqsien dly found for B1: ( 1, 2, 30)
5143 13:08:14.577303 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5144 13:08:14.580774 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5145 13:08:14.581309
5146 13:08:14.584132 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5147 13:08:14.587305 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5148 13:08:14.590554 [Gating] SW calibration Done
5149 13:08:14.590939 ==
5150 13:08:14.593654 Dram Type= 6, Freq= 0, CH_0, rank 0
5151 13:08:14.596885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5152 13:08:14.597306 ==
5153 13:08:14.600439 RX Vref Scan: 0
5154 13:08:14.600961
5155 13:08:14.601402 RX Vref 0 -> 0, step: 1
5156 13:08:14.604204
5157 13:08:14.604589 RX Delay -80 -> 252, step: 8
5158 13:08:14.610286 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5159 13:08:14.613846 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5160 13:08:14.616865 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5161 13:08:14.620150 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5162 13:08:14.623577 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5163 13:08:14.627164 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5164 13:08:14.633601 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5165 13:08:14.637093 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5166 13:08:14.640513 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5167 13:08:14.643516 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5168 13:08:14.647106 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5169 13:08:14.650581 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5170 13:08:14.656969 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5171 13:08:14.660286 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5172 13:08:14.663972 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5173 13:08:14.667131 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5174 13:08:14.667555 ==
5175 13:08:14.670451 Dram Type= 6, Freq= 0, CH_0, rank 0
5176 13:08:14.673708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5177 13:08:14.677195 ==
5178 13:08:14.677603 DQS Delay:
5179 13:08:14.678171 DQS0 = 0, DQS1 = 0
5180 13:08:14.680001 DQM Delay:
5181 13:08:14.680392 DQM0 = 105, DQM1 = 95
5182 13:08:14.683358 DQ Delay:
5183 13:08:14.686767 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =103
5184 13:08:14.690201 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5185 13:08:14.693341 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5186 13:08:14.696794 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5187 13:08:14.697179
5188 13:08:14.697478
5189 13:08:14.697753 ==
5190 13:08:14.700057 Dram Type= 6, Freq= 0, CH_0, rank 0
5191 13:08:14.703495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5192 13:08:14.704025 ==
5193 13:08:14.704489
5194 13:08:14.704921
5195 13:08:14.706658 TX Vref Scan disable
5196 13:08:14.709941 == TX Byte 0 ==
5197 13:08:14.712711 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5198 13:08:14.716281 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5199 13:08:14.719722 == TX Byte 1 ==
5200 13:08:14.723330 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5201 13:08:14.726384 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5202 13:08:14.726496 ==
5203 13:08:14.729782 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 13:08:14.733459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 13:08:14.733537 ==
5206 13:08:14.736566
5207 13:08:14.736642
5208 13:08:14.736701 TX Vref Scan disable
5209 13:08:14.739695 == TX Byte 0 ==
5210 13:08:14.743206 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5211 13:08:14.749501 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5212 13:08:14.749611 == TX Byte 1 ==
5213 13:08:14.752589 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5214 13:08:14.759773 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5215 13:08:14.759864
5216 13:08:14.759939 [DATLAT]
5217 13:08:14.760014 Freq=933, CH0 RK0
5218 13:08:14.760118
5219 13:08:14.762792 DATLAT Default: 0xd
5220 13:08:14.762874 0, 0xFFFF, sum = 0
5221 13:08:14.766163 1, 0xFFFF, sum = 0
5222 13:08:14.769101 2, 0xFFFF, sum = 0
5223 13:08:14.769170 3, 0xFFFF, sum = 0
5224 13:08:14.772954 4, 0xFFFF, sum = 0
5225 13:08:14.773027 5, 0xFFFF, sum = 0
5226 13:08:14.776040 6, 0xFFFF, sum = 0
5227 13:08:14.776106 7, 0xFFFF, sum = 0
5228 13:08:14.779575 8, 0xFFFF, sum = 0
5229 13:08:14.779667 9, 0xFFFF, sum = 0
5230 13:08:14.782844 10, 0x0, sum = 1
5231 13:08:14.782941 11, 0x0, sum = 2
5232 13:08:14.786387 12, 0x0, sum = 3
5233 13:08:14.786522 13, 0x0, sum = 4
5234 13:08:14.786595 best_step = 11
5235 13:08:14.786674
5236 13:08:14.789277 ==
5237 13:08:14.792480 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 13:08:14.795848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 13:08:14.795938 ==
5240 13:08:14.796019 RX Vref Scan: 1
5241 13:08:14.796141
5242 13:08:14.799157 RX Vref 0 -> 0, step: 1
5243 13:08:14.799249
5244 13:08:14.802484 RX Delay -45 -> 252, step: 4
5245 13:08:14.802592
5246 13:08:14.805914 Set Vref, RX VrefLevel [Byte0]: 55
5247 13:08:14.809326 [Byte1]: 48
5248 13:08:14.809426
5249 13:08:14.812722 Final RX Vref Byte 0 = 55 to rank0
5250 13:08:14.816157 Final RX Vref Byte 1 = 48 to rank0
5251 13:08:14.819670 Final RX Vref Byte 0 = 55 to rank1
5252 13:08:14.822982 Final RX Vref Byte 1 = 48 to rank1==
5253 13:08:14.826280 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 13:08:14.829655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 13:08:14.829754 ==
5256 13:08:14.833121 DQS Delay:
5257 13:08:14.833197 DQS0 = 0, DQS1 = 0
5258 13:08:14.836636 DQM Delay:
5259 13:08:14.836734 DQM0 = 104, DQM1 = 95
5260 13:08:14.836818 DQ Delay:
5261 13:08:14.839346 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5262 13:08:14.842782 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5263 13:08:14.846133 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =90
5264 13:08:14.852914 DQ12 =102, DQ13 =100, DQ14 =104, DQ15 =104
5265 13:08:14.852990
5266 13:08:14.853048
5267 13:08:14.859294 [DQSOSCAuto] RK0, (LSB)MR18= 0x342b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5268 13:08:14.863005 CH0 RK0: MR19=505, MR18=342B
5269 13:08:14.869328 CH0_RK0: MR19=0x505, MR18=0x342B, DQSOSC=405, MR23=63, INC=66, DEC=44
5270 13:08:14.869406
5271 13:08:14.872988 ----->DramcWriteLeveling(PI) begin...
5272 13:08:14.873065 ==
5273 13:08:14.875989 Dram Type= 6, Freq= 0, CH_0, rank 1
5274 13:08:14.879516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 13:08:14.879626 ==
5276 13:08:14.882716 Write leveling (Byte 0): 33 => 33
5277 13:08:14.886319 Write leveling (Byte 1): 29 => 29
5278 13:08:14.889348 DramcWriteLeveling(PI) end<-----
5279 13:08:14.889423
5280 13:08:14.889480 ==
5281 13:08:14.892888 Dram Type= 6, Freq= 0, CH_0, rank 1
5282 13:08:14.896111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 13:08:14.896187 ==
5284 13:08:14.899419 [Gating] SW mode calibration
5285 13:08:14.906262 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5286 13:08:14.912882 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5287 13:08:14.915750 0 14 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5288 13:08:14.922667 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5289 13:08:14.926159 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5290 13:08:14.929446 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5291 13:08:14.932910 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 13:08:14.939553 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 13:08:14.942335 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5294 13:08:14.945723 0 14 28 | B1->B0 | 2727 2a2a | 0 0 | (0 0) (0 0)
5295 13:08:14.953005 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5296 13:08:14.955696 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5297 13:08:14.959186 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5298 13:08:14.965914 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5299 13:08:14.969297 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 13:08:14.972594 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 13:08:14.979231 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5302 13:08:14.982622 0 15 28 | B1->B0 | 3b3b 3939 | 0 1 | (0 0) (0 0)
5303 13:08:14.985938 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 13:08:14.992685 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 13:08:14.995822 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5306 13:08:14.999069 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 13:08:15.005586 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 13:08:15.008895 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 13:08:15.012205 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 13:08:15.019117 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5311 13:08:15.022607 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5312 13:08:15.025788 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 13:08:15.032611 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 13:08:15.035628 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 13:08:15.039210 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 13:08:15.045907 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 13:08:15.049385 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 13:08:15.052196 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 13:08:15.056114 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 13:08:15.062287 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 13:08:15.065664 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 13:08:15.069013 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 13:08:15.075617 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 13:08:15.078906 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 13:08:15.082273 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 13:08:15.089155 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5327 13:08:15.092534 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 13:08:15.095902 Total UI for P1: 0, mck2ui 16
5329 13:08:15.099065 best dqsien dly found for B0: ( 1, 2, 28)
5330 13:08:15.102279 Total UI for P1: 0, mck2ui 16
5331 13:08:15.105574 best dqsien dly found for B1: ( 1, 2, 28)
5332 13:08:15.108871 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5333 13:08:15.112112 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5334 13:08:15.112188
5335 13:08:15.115648 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5336 13:08:15.119039 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5337 13:08:15.122393 [Gating] SW calibration Done
5338 13:08:15.122468 ==
5339 13:08:15.125831 Dram Type= 6, Freq= 0, CH_0, rank 1
5340 13:08:15.129177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5341 13:08:15.132438 ==
5342 13:08:15.132513 RX Vref Scan: 0
5343 13:08:15.132571
5344 13:08:15.135798 RX Vref 0 -> 0, step: 1
5345 13:08:15.135873
5346 13:08:15.135931 RX Delay -80 -> 252, step: 8
5347 13:08:15.142434 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5348 13:08:15.145976 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5349 13:08:15.149230 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5350 13:08:15.152718 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5351 13:08:15.156015 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5352 13:08:15.159097 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5353 13:08:15.165885 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5354 13:08:15.169418 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5355 13:08:15.172883 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5356 13:08:15.175870 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5357 13:08:15.179240 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5358 13:08:15.182635 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5359 13:08:15.189067 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5360 13:08:15.192352 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5361 13:08:15.195819 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5362 13:08:15.199345 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5363 13:08:15.199578 ==
5364 13:08:15.202839 Dram Type= 6, Freq= 0, CH_0, rank 1
5365 13:08:15.206146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5366 13:08:15.209433 ==
5367 13:08:15.209834 DQS Delay:
5368 13:08:15.210157 DQS0 = 0, DQS1 = 0
5369 13:08:15.212800 DQM Delay:
5370 13:08:15.213206 DQM0 = 104, DQM1 = 94
5371 13:08:15.216155 DQ Delay:
5372 13:08:15.219406 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5373 13:08:15.223002 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5374 13:08:15.226100 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5375 13:08:15.228846 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5376 13:08:15.229365
5377 13:08:15.229824
5378 13:08:15.230274 ==
5379 13:08:15.232195 Dram Type= 6, Freq= 0, CH_0, rank 1
5380 13:08:15.235712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 13:08:15.236277 ==
5382 13:08:15.236745
5383 13:08:15.237178
5384 13:08:15.238940 TX Vref Scan disable
5385 13:08:15.242986 == TX Byte 0 ==
5386 13:08:15.245720 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5387 13:08:15.249032 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5388 13:08:15.249579 == TX Byte 1 ==
5389 13:08:15.255836 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5390 13:08:15.259038 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5391 13:08:15.259347 ==
5392 13:08:15.262783 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 13:08:15.265908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 13:08:15.266201 ==
5395 13:08:15.266416
5396 13:08:15.269333
5397 13:08:15.269526 TX Vref Scan disable
5398 13:08:15.272540 == TX Byte 0 ==
5399 13:08:15.275771 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5400 13:08:15.282109 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5401 13:08:15.282290 == TX Byte 1 ==
5402 13:08:15.286036 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5403 13:08:15.292105 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5404 13:08:15.292212
5405 13:08:15.292285 [DATLAT]
5406 13:08:15.292352 Freq=933, CH0 RK1
5407 13:08:15.292418
5408 13:08:15.295535 DATLAT Default: 0xb
5409 13:08:15.295613 0, 0xFFFF, sum = 0
5410 13:08:15.298934 1, 0xFFFF, sum = 0
5411 13:08:15.299012 2, 0xFFFF, sum = 0
5412 13:08:15.302054 3, 0xFFFF, sum = 0
5413 13:08:15.305605 4, 0xFFFF, sum = 0
5414 13:08:15.305682 5, 0xFFFF, sum = 0
5415 13:08:15.308604 6, 0xFFFF, sum = 0
5416 13:08:15.308681 7, 0xFFFF, sum = 0
5417 13:08:15.312362 8, 0xFFFF, sum = 0
5418 13:08:15.312443 9, 0xFFFF, sum = 0
5419 13:08:15.315535 10, 0x0, sum = 1
5420 13:08:15.315616 11, 0x0, sum = 2
5421 13:08:15.315678 12, 0x0, sum = 3
5422 13:08:15.318507 13, 0x0, sum = 4
5423 13:08:15.318585 best_step = 11
5424 13:08:15.318643
5425 13:08:15.322411 ==
5426 13:08:15.322495 Dram Type= 6, Freq= 0, CH_0, rank 1
5427 13:08:15.329183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5428 13:08:15.329266 ==
5429 13:08:15.329329 RX Vref Scan: 0
5430 13:08:15.329386
5431 13:08:15.332579 RX Vref 0 -> 0, step: 1
5432 13:08:15.332660
5433 13:08:15.335196 RX Delay -45 -> 252, step: 4
5434 13:08:15.338670 iDelay=195, Bit 0, Center 102 (15 ~ 190) 176
5435 13:08:15.345497 iDelay=195, Bit 1, Center 104 (19 ~ 190) 172
5436 13:08:15.348838 iDelay=195, Bit 2, Center 102 (15 ~ 190) 176
5437 13:08:15.352180 iDelay=195, Bit 3, Center 102 (15 ~ 190) 176
5438 13:08:15.355543 iDelay=195, Bit 4, Center 106 (19 ~ 194) 176
5439 13:08:15.358968 iDelay=195, Bit 5, Center 98 (11 ~ 186) 176
5440 13:08:15.362367 iDelay=195, Bit 6, Center 112 (31 ~ 194) 164
5441 13:08:15.369058 iDelay=195, Bit 7, Center 110 (27 ~ 194) 168
5442 13:08:15.372259 iDelay=195, Bit 8, Center 86 (3 ~ 170) 168
5443 13:08:15.375412 iDelay=195, Bit 9, Center 82 (-1 ~ 166) 168
5444 13:08:15.379587 iDelay=195, Bit 10, Center 94 (11 ~ 178) 168
5445 13:08:15.382265 iDelay=195, Bit 11, Center 88 (7 ~ 170) 164
5446 13:08:15.385824 iDelay=195, Bit 12, Center 98 (15 ~ 182) 168
5447 13:08:15.392685 iDelay=195, Bit 13, Center 98 (15 ~ 182) 168
5448 13:08:15.396149 iDelay=195, Bit 14, Center 104 (23 ~ 186) 164
5449 13:08:15.399402 iDelay=195, Bit 15, Center 102 (19 ~ 186) 168
5450 13:08:15.399792 ==
5451 13:08:15.402801 Dram Type= 6, Freq= 0, CH_0, rank 1
5452 13:08:15.405856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5453 13:08:15.406323 ==
5454 13:08:15.409667 DQS Delay:
5455 13:08:15.410122 DQS0 = 0, DQS1 = 0
5456 13:08:15.412744 DQM Delay:
5457 13:08:15.413131 DQM0 = 104, DQM1 = 94
5458 13:08:15.416257 DQ Delay:
5459 13:08:15.419129 DQ0 =102, DQ1 =104, DQ2 =102, DQ3 =102
5460 13:08:15.422424 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =110
5461 13:08:15.425848 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =88
5462 13:08:15.429375 DQ12 =98, DQ13 =98, DQ14 =104, DQ15 =102
5463 13:08:15.429652
5464 13:08:15.429868
5465 13:08:15.435786 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b04, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5466 13:08:15.439333 CH0 RK1: MR19=505, MR18=2B04
5467 13:08:15.445505 CH0_RK1: MR19=0x505, MR18=0x2B04, DQSOSC=408, MR23=63, INC=65, DEC=43
5468 13:08:15.449253 [RxdqsGatingPostProcess] freq 933
5469 13:08:15.452791 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5470 13:08:15.455747 best DQS0 dly(2T, 0.5T) = (0, 10)
5471 13:08:15.459504 best DQS1 dly(2T, 0.5T) = (0, 10)
5472 13:08:15.463005 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5473 13:08:15.465702 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5474 13:08:15.469258 best DQS0 dly(2T, 0.5T) = (0, 10)
5475 13:08:15.472737 best DQS1 dly(2T, 0.5T) = (0, 10)
5476 13:08:15.475958 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5477 13:08:15.479184 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5478 13:08:15.482927 Pre-setting of DQS Precalculation
5479 13:08:15.486174 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5480 13:08:15.486571 ==
5481 13:08:15.489471 Dram Type= 6, Freq= 0, CH_1, rank 0
5482 13:08:15.495589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5483 13:08:15.496066 ==
5484 13:08:15.499723 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5485 13:08:15.505873 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5486 13:08:15.509301 [CA 0] Center 36 (6~67) winsize 62
5487 13:08:15.512744 [CA 1] Center 36 (6~67) winsize 62
5488 13:08:15.515964 [CA 2] Center 34 (4~65) winsize 62
5489 13:08:15.519094 [CA 3] Center 34 (4~65) winsize 62
5490 13:08:15.522391 [CA 4] Center 34 (4~64) winsize 61
5491 13:08:15.525838 [CA 5] Center 33 (3~64) winsize 62
5492 13:08:15.526321
5493 13:08:15.529162 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5494 13:08:15.529666
5495 13:08:15.532650 [CATrainingPosCal] consider 1 rank data
5496 13:08:15.535823 u2DelayCellTimex100 = 270/100 ps
5497 13:08:15.539255 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5498 13:08:15.542634 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5499 13:08:15.545938 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5500 13:08:15.552503 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5501 13:08:15.556185 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5502 13:08:15.559152 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5503 13:08:15.559563
5504 13:08:15.562737 CA PerBit enable=1, Macro0, CA PI delay=33
5505 13:08:15.563129
5506 13:08:15.565600 [CBTSetCACLKResult] CA Dly = 33
5507 13:08:15.565991 CS Dly: 7 (0~38)
5508 13:08:15.566387 ==
5509 13:08:15.568923 Dram Type= 6, Freq= 0, CH_1, rank 1
5510 13:08:15.575931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5511 13:08:15.576456 ==
5512 13:08:15.578971 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5513 13:08:15.585423 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5514 13:08:15.589018 [CA 0] Center 36 (6~67) winsize 62
5515 13:08:15.592641 [CA 1] Center 37 (7~68) winsize 62
5516 13:08:15.595878 [CA 2] Center 35 (5~65) winsize 61
5517 13:08:15.599083 [CA 3] Center 34 (4~65) winsize 62
5518 13:08:15.602475 [CA 4] Center 34 (4~65) winsize 62
5519 13:08:15.605822 [CA 5] Center 33 (3~64) winsize 62
5520 13:08:15.606260
5521 13:08:15.609265 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5522 13:08:15.609656
5523 13:08:15.612548 [CATrainingPosCal] consider 2 rank data
5524 13:08:15.616014 u2DelayCellTimex100 = 270/100 ps
5525 13:08:15.618726 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5526 13:08:15.622048 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5527 13:08:15.628971 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5528 13:08:15.632290 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5529 13:08:15.635492 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5530 13:08:15.638919 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5531 13:08:15.639381
5532 13:08:15.642417 CA PerBit enable=1, Macro0, CA PI delay=33
5533 13:08:15.642990
5534 13:08:15.645553 [CBTSetCACLKResult] CA Dly = 33
5535 13:08:15.645939 CS Dly: 8 (0~40)
5536 13:08:15.646335
5537 13:08:15.648903 ----->DramcWriteLeveling(PI) begin...
5538 13:08:15.652334 ==
5539 13:08:15.655903 Dram Type= 6, Freq= 0, CH_1, rank 0
5540 13:08:15.659323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 13:08:15.659893 ==
5542 13:08:15.662042 Write leveling (Byte 0): 27 => 27
5543 13:08:15.665373 Write leveling (Byte 1): 27 => 27
5544 13:08:15.668677 DramcWriteLeveling(PI) end<-----
5545 13:08:15.669083
5546 13:08:15.669386 ==
5547 13:08:15.671841 Dram Type= 6, Freq= 0, CH_1, rank 0
5548 13:08:15.675225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5549 13:08:15.675617 ==
5550 13:08:15.678640 [Gating] SW mode calibration
5551 13:08:15.685226 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5552 13:08:15.688764 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5553 13:08:15.695675 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 13:08:15.698584 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5555 13:08:15.701973 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 13:08:15.708708 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 13:08:15.711842 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 13:08:15.715253 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 13:08:15.722123 0 14 24 | B1->B0 | 3333 2e2e | 0 0 | (0 1) (0 1)
5560 13:08:15.725376 0 14 28 | B1->B0 | 2727 2323 | 1 0 | (0 0) (0 0)
5561 13:08:15.728823 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 13:08:15.735509 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 13:08:15.738595 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 13:08:15.742439 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 13:08:15.748671 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 13:08:15.751913 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 13:08:15.755301 0 15 24 | B1->B0 | 2828 3333 | 0 1 | (0 0) (0 0)
5568 13:08:15.762206 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5569 13:08:15.765457 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 13:08:15.768516 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 13:08:15.775575 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 13:08:15.778764 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 13:08:15.782072 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 13:08:15.785474 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 13:08:15.792273 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5576 13:08:15.795691 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5577 13:08:15.799061 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 13:08:15.805174 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 13:08:15.808593 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 13:08:15.812047 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 13:08:15.818858 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 13:08:15.822131 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 13:08:15.825044 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 13:08:15.831979 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 13:08:15.835210 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 13:08:15.838564 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 13:08:15.845217 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 13:08:15.848016 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 13:08:15.852107 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 13:08:15.858464 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 13:08:15.861862 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5592 13:08:15.864964 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5593 13:08:15.868139 Total UI for P1: 0, mck2ui 16
5594 13:08:15.871653 best dqsien dly found for B1: ( 1, 2, 24)
5595 13:08:15.877996 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 13:08:15.878428 Total UI for P1: 0, mck2ui 16
5597 13:08:15.884945 best dqsien dly found for B0: ( 1, 2, 26)
5598 13:08:15.888119 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5599 13:08:15.891517 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5600 13:08:15.891917
5601 13:08:15.894937 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5602 13:08:15.898080 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5603 13:08:15.901718 [Gating] SW calibration Done
5604 13:08:15.902149 ==
5605 13:08:15.905069 Dram Type= 6, Freq= 0, CH_1, rank 0
5606 13:08:15.908503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5607 13:08:15.908890 ==
5608 13:08:15.911201 RX Vref Scan: 0
5609 13:08:15.911602
5610 13:08:15.911903 RX Vref 0 -> 0, step: 1
5611 13:08:15.912231
5612 13:08:15.915320 RX Delay -80 -> 252, step: 8
5613 13:08:15.918183 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5614 13:08:15.924738 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5615 13:08:15.928084 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5616 13:08:15.931602 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5617 13:08:15.935094 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5618 13:08:15.937756 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5619 13:08:15.941464 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5620 13:08:15.948383 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5621 13:08:15.951616 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5622 13:08:15.954585 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5623 13:08:15.957849 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5624 13:08:15.961019 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5625 13:08:15.964846 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5626 13:08:15.971487 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5627 13:08:15.974566 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5628 13:08:15.977892 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5629 13:08:15.978364 ==
5630 13:08:15.981226 Dram Type= 6, Freq= 0, CH_1, rank 0
5631 13:08:15.984303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5632 13:08:15.987750 ==
5633 13:08:15.988142 DQS Delay:
5634 13:08:15.988547 DQS0 = 0, DQS1 = 0
5635 13:08:15.990919 DQM Delay:
5636 13:08:15.991500 DQM0 = 102, DQM1 = 98
5637 13:08:15.994345 DQ Delay:
5638 13:08:15.997349 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5639 13:08:16.000655 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5640 13:08:16.004325 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5641 13:08:16.007802 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5642 13:08:16.008371
5643 13:08:16.008958
5644 13:08:16.009509 ==
5645 13:08:16.011135 Dram Type= 6, Freq= 0, CH_1, rank 0
5646 13:08:16.014085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5647 13:08:16.014627 ==
5648 13:08:16.015307
5649 13:08:16.015812
5650 13:08:16.018297 TX Vref Scan disable
5651 13:08:16.018685 == TX Byte 0 ==
5652 13:08:16.024211 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5653 13:08:16.027564 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5654 13:08:16.031033 == TX Byte 1 ==
5655 13:08:16.034446 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5656 13:08:16.037275 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5657 13:08:16.037657 ==
5658 13:08:16.040810 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 13:08:16.043929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 13:08:16.044344 ==
5661 13:08:16.047242
5662 13:08:16.047638
5663 13:08:16.047937 TX Vref Scan disable
5664 13:08:16.050502 == TX Byte 0 ==
5665 13:08:16.053875 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5666 13:08:16.060486 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5667 13:08:16.060915 == TX Byte 1 ==
5668 13:08:16.063831 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5669 13:08:16.071027 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5670 13:08:16.071478
5671 13:08:16.071784 [DATLAT]
5672 13:08:16.072061 Freq=933, CH1 RK0
5673 13:08:16.072384
5674 13:08:16.073685 DATLAT Default: 0xd
5675 13:08:16.074190 0, 0xFFFF, sum = 0
5676 13:08:16.077121 1, 0xFFFF, sum = 0
5677 13:08:16.077625 2, 0xFFFF, sum = 0
5678 13:08:16.080554 3, 0xFFFF, sum = 0
5679 13:08:16.080947 4, 0xFFFF, sum = 0
5680 13:08:16.084074 5, 0xFFFF, sum = 0
5681 13:08:16.087348 6, 0xFFFF, sum = 0
5682 13:08:16.087742 7, 0xFFFF, sum = 0
5683 13:08:16.090754 8, 0xFFFF, sum = 0
5684 13:08:16.091152 9, 0xFFFF, sum = 0
5685 13:08:16.094153 10, 0x0, sum = 1
5686 13:08:16.094524 11, 0x0, sum = 2
5687 13:08:16.094869 12, 0x0, sum = 3
5688 13:08:16.097422 13, 0x0, sum = 4
5689 13:08:16.097761 best_step = 11
5690 13:08:16.098089
5691 13:08:16.098365 ==
5692 13:08:16.100916 Dram Type= 6, Freq= 0, CH_1, rank 0
5693 13:08:16.107480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5694 13:08:16.107871 ==
5695 13:08:16.108188 RX Vref Scan: 1
5696 13:08:16.108467
5697 13:08:16.110704 RX Vref 0 -> 0, step: 1
5698 13:08:16.111117
5699 13:08:16.113848 RX Delay -45 -> 252, step: 4
5700 13:08:16.114288
5701 13:08:16.117388 Set Vref, RX VrefLevel [Byte0]: 55
5702 13:08:16.120641 [Byte1]: 53
5703 13:08:16.121138
5704 13:08:16.123943 Final RX Vref Byte 0 = 55 to rank0
5705 13:08:16.127573 Final RX Vref Byte 1 = 53 to rank0
5706 13:08:16.130815 Final RX Vref Byte 0 = 55 to rank1
5707 13:08:16.133910 Final RX Vref Byte 1 = 53 to rank1==
5708 13:08:16.137014 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 13:08:16.140455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 13:08:16.140862 ==
5711 13:08:16.143805 DQS Delay:
5712 13:08:16.144339 DQS0 = 0, DQS1 = 0
5713 13:08:16.147483 DQM Delay:
5714 13:08:16.147880 DQM0 = 103, DQM1 = 99
5715 13:08:16.148239 DQ Delay:
5716 13:08:16.150648 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5717 13:08:16.153822 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =104
5718 13:08:16.157124 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =92
5719 13:08:16.163981 DQ12 =106, DQ13 =104, DQ14 =108, DQ15 =106
5720 13:08:16.164505
5721 13:08:16.164969
5722 13:08:16.170420 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5723 13:08:16.173708 CH1 RK0: MR19=505, MR18=1A32
5724 13:08:16.180304 CH1_RK0: MR19=0x505, MR18=0x1A32, DQSOSC=406, MR23=63, INC=65, DEC=43
5725 13:08:16.180819
5726 13:08:16.183795 ----->DramcWriteLeveling(PI) begin...
5727 13:08:16.184297 ==
5728 13:08:16.187263 Dram Type= 6, Freq= 0, CH_1, rank 1
5729 13:08:16.190725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 13:08:16.191263 ==
5731 13:08:16.194237 Write leveling (Byte 0): 29 => 29
5732 13:08:16.197520 Write leveling (Byte 1): 28 => 28
5733 13:08:16.200826 DramcWriteLeveling(PI) end<-----
5734 13:08:16.201303
5735 13:08:16.201752 ==
5736 13:08:16.203699 Dram Type= 6, Freq= 0, CH_1, rank 1
5737 13:08:16.207229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 13:08:16.207728 ==
5739 13:08:16.210472 [Gating] SW mode calibration
5740 13:08:16.217383 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5741 13:08:16.223530 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5742 13:08:16.226990 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5743 13:08:16.230274 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5744 13:08:16.237510 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5745 13:08:16.240749 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 13:08:16.243532 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 13:08:16.250646 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5748 13:08:16.253690 0 14 24 | B1->B0 | 2c2c 3232 | 0 0 | (0 0) (0 1)
5749 13:08:16.257328 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 13:08:16.263426 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 13:08:16.267149 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5752 13:08:16.269982 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 13:08:16.276973 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 13:08:16.280588 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 13:08:16.283753 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5756 13:08:16.290071 0 15 24 | B1->B0 | 3a3a 2b2a | 0 1 | (1 1) (0 0)
5757 13:08:16.293324 0 15 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5758 13:08:16.296629 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 13:08:16.303982 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5760 13:08:16.306775 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 13:08:16.310162 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 13:08:16.316848 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 13:08:16.320153 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 13:08:16.323559 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5765 13:08:16.330528 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5766 13:08:16.333223 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 13:08:16.336484 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 13:08:16.343586 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 13:08:16.346975 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 13:08:16.349729 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 13:08:16.356696 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 13:08:16.360106 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 13:08:16.363417 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 13:08:16.366746 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 13:08:16.373480 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 13:08:16.376840 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 13:08:16.380136 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 13:08:16.386649 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 13:08:16.390201 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 13:08:16.393429 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5781 13:08:16.399723 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5782 13:08:16.403325 Total UI for P1: 0, mck2ui 16
5783 13:08:16.406758 best dqsien dly found for B1: ( 1, 2, 24)
5784 13:08:16.409973 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 13:08:16.412996 Total UI for P1: 0, mck2ui 16
5786 13:08:16.416632 best dqsien dly found for B0: ( 1, 2, 28)
5787 13:08:16.419581 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5788 13:08:16.422922 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5789 13:08:16.423319
5790 13:08:16.426755 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5791 13:08:16.429706 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5792 13:08:16.432865 [Gating] SW calibration Done
5793 13:08:16.433397 ==
5794 13:08:16.436198 Dram Type= 6, Freq= 0, CH_1, rank 1
5795 13:08:16.439593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5796 13:08:16.442993 ==
5797 13:08:16.443496 RX Vref Scan: 0
5798 13:08:16.443924
5799 13:08:16.446264 RX Vref 0 -> 0, step: 1
5800 13:08:16.446661
5801 13:08:16.449513 RX Delay -80 -> 252, step: 8
5802 13:08:16.452785 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5803 13:08:16.456227 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5804 13:08:16.459860 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5805 13:08:16.463168 iDelay=208, Bit 3, Center 99 (16 ~ 183) 168
5806 13:08:16.469883 iDelay=208, Bit 4, Center 99 (16 ~ 183) 168
5807 13:08:16.472491 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5808 13:08:16.475984 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5809 13:08:16.479105 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5810 13:08:16.482686 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5811 13:08:16.486105 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5812 13:08:16.492864 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5813 13:08:16.496309 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5814 13:08:16.499667 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5815 13:08:16.502584 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5816 13:08:16.505808 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5817 13:08:16.512757 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5818 13:08:16.513150 ==
5819 13:08:16.516054 Dram Type= 6, Freq= 0, CH_1, rank 1
5820 13:08:16.519362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 13:08:16.519906 ==
5822 13:08:16.520351 DQS Delay:
5823 13:08:16.522861 DQS0 = 0, DQS1 = 0
5824 13:08:16.523250 DQM Delay:
5825 13:08:16.526079 DQM0 = 104, DQM1 = 98
5826 13:08:16.526467 DQ Delay:
5827 13:08:16.529027 DQ0 =107, DQ1 =103, DQ2 =95, DQ3 =99
5828 13:08:16.532647 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5829 13:08:16.536147 DQ8 =83, DQ9 =91, DQ10 =99, DQ11 =91
5830 13:08:16.539219 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5831 13:08:16.539609
5832 13:08:16.539915
5833 13:08:16.540194 ==
5834 13:08:16.542561 Dram Type= 6, Freq= 0, CH_1, rank 1
5835 13:08:16.549239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5836 13:08:16.549632 ==
5837 13:08:16.549935
5838 13:08:16.550272
5839 13:08:16.550538 TX Vref Scan disable
5840 13:08:16.552887 == TX Byte 0 ==
5841 13:08:16.556032 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5842 13:08:16.562529 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5843 13:08:16.563013 == TX Byte 1 ==
5844 13:08:16.566164 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5845 13:08:16.572868 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5846 13:08:16.573263 ==
5847 13:08:16.576050 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 13:08:16.580000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 13:08:16.580482 ==
5850 13:08:16.580802
5851 13:08:16.581081
5852 13:08:16.582711 TX Vref Scan disable
5853 13:08:16.583100 == TX Byte 0 ==
5854 13:08:16.589367 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5855 13:08:16.592776 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5856 13:08:16.593165 == TX Byte 1 ==
5857 13:08:16.599572 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5858 13:08:16.602844 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5859 13:08:16.603235
5860 13:08:16.603542 [DATLAT]
5861 13:08:16.606323 Freq=933, CH1 RK1
5862 13:08:16.606712
5863 13:08:16.607031 DATLAT Default: 0xb
5864 13:08:16.609845 0, 0xFFFF, sum = 0
5865 13:08:16.610357 1, 0xFFFF, sum = 0
5866 13:08:16.613163 2, 0xFFFF, sum = 0
5867 13:08:16.613558 3, 0xFFFF, sum = 0
5868 13:08:16.616020 4, 0xFFFF, sum = 0
5869 13:08:16.616415 5, 0xFFFF, sum = 0
5870 13:08:16.619313 6, 0xFFFF, sum = 0
5871 13:08:16.619707 7, 0xFFFF, sum = 0
5872 13:08:16.623315 8, 0xFFFF, sum = 0
5873 13:08:16.623768 9, 0xFFFF, sum = 0
5874 13:08:16.626053 10, 0x0, sum = 1
5875 13:08:16.626514 11, 0x0, sum = 2
5876 13:08:16.629459 12, 0x0, sum = 3
5877 13:08:16.629855 13, 0x0, sum = 4
5878 13:08:16.632717 best_step = 11
5879 13:08:16.633103
5880 13:08:16.633402 ==
5881 13:08:16.636167 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 13:08:16.639689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 13:08:16.640079 ==
5884 13:08:16.643077 RX Vref Scan: 0
5885 13:08:16.643463
5886 13:08:16.643763 RX Vref 0 -> 0, step: 1
5887 13:08:16.644044
5888 13:08:16.646277 RX Delay -53 -> 252, step: 4
5889 13:08:16.652802 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5890 13:08:16.656212 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5891 13:08:16.659627 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5892 13:08:16.663340 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5893 13:08:16.666635 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5894 13:08:16.673334 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5895 13:08:16.676242 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5896 13:08:16.679675 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5897 13:08:16.683356 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5898 13:08:16.686408 iDelay=203, Bit 9, Center 92 (7 ~ 178) 172
5899 13:08:16.693195 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5900 13:08:16.696574 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5901 13:08:16.699854 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5902 13:08:16.702762 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5903 13:08:16.706055 iDelay=203, Bit 14, Center 108 (27 ~ 190) 164
5904 13:08:16.713013 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5905 13:08:16.713485 ==
5906 13:08:16.716280 Dram Type= 6, Freq= 0, CH_1, rank 1
5907 13:08:16.719751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5908 13:08:16.720211 ==
5909 13:08:16.720602 DQS Delay:
5910 13:08:16.723051 DQS0 = 0, DQS1 = 0
5911 13:08:16.723472 DQM Delay:
5912 13:08:16.726451 DQM0 = 104, DQM1 = 100
5913 13:08:16.726846 DQ Delay:
5914 13:08:16.729702 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5915 13:08:16.733020 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5916 13:08:16.736469 DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =94
5917 13:08:16.739772 DQ12 =108, DQ13 =106, DQ14 =108, DQ15 =108
5918 13:08:16.740168
5919 13:08:16.740553
5920 13:08:16.749826 [DQSOSCAuto] RK1, (LSB)MR18= 0x3204, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 406 ps
5921 13:08:16.752706 CH1 RK1: MR19=505, MR18=3204
5922 13:08:16.756531 CH1_RK1: MR19=0x505, MR18=0x3204, DQSOSC=406, MR23=63, INC=65, DEC=43
5923 13:08:16.759579 [RxdqsGatingPostProcess] freq 933
5924 13:08:16.766548 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5925 13:08:16.769897 best DQS0 dly(2T, 0.5T) = (0, 10)
5926 13:08:16.773192 best DQS1 dly(2T, 0.5T) = (0, 10)
5927 13:08:16.776551 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5928 13:08:16.779882 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5929 13:08:16.782507 best DQS0 dly(2T, 0.5T) = (0, 10)
5930 13:08:16.785928 best DQS1 dly(2T, 0.5T) = (0, 10)
5931 13:08:16.789331 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5932 13:08:16.792883 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5933 13:08:16.793274 Pre-setting of DQS Precalculation
5934 13:08:16.799209 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5935 13:08:16.806373 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5936 13:08:16.812498 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5937 13:08:16.812884
5938 13:08:16.813215
5939 13:08:16.815656 [Calibration Summary] 1866 Mbps
5940 13:08:16.819304 CH 0, Rank 0
5941 13:08:16.819682 SW Impedance : PASS
5942 13:08:16.822773 DUTY Scan : NO K
5943 13:08:16.826240 ZQ Calibration : PASS
5944 13:08:16.826650 Jitter Meter : NO K
5945 13:08:16.829032 CBT Training : PASS
5946 13:08:16.832414 Write leveling : PASS
5947 13:08:16.832794 RX DQS gating : PASS
5948 13:08:16.836022 RX DQ/DQS(RDDQC) : PASS
5949 13:08:16.836479 TX DQ/DQS : PASS
5950 13:08:16.839785 RX DATLAT : PASS
5951 13:08:16.842662 RX DQ/DQS(Engine): PASS
5952 13:08:16.843049 TX OE : NO K
5953 13:08:16.845752 All Pass.
5954 13:08:16.846227
5955 13:08:16.846615 CH 0, Rank 1
5956 13:08:16.849559 SW Impedance : PASS
5957 13:08:16.849949 DUTY Scan : NO K
5958 13:08:16.852842 ZQ Calibration : PASS
5959 13:08:16.856260 Jitter Meter : NO K
5960 13:08:16.856650 CBT Training : PASS
5961 13:08:16.859704 Write leveling : PASS
5962 13:08:16.862960 RX DQS gating : PASS
5963 13:08:16.863347 RX DQ/DQS(RDDQC) : PASS
5964 13:08:16.866121 TX DQ/DQS : PASS
5965 13:08:16.869194 RX DATLAT : PASS
5966 13:08:16.869648 RX DQ/DQS(Engine): PASS
5967 13:08:16.872648 TX OE : NO K
5968 13:08:16.873075 All Pass.
5969 13:08:16.873561
5970 13:08:16.875968 CH 1, Rank 0
5971 13:08:16.876358 SW Impedance : PASS
5972 13:08:16.879280 DUTY Scan : NO K
5973 13:08:16.882684 ZQ Calibration : PASS
5974 13:08:16.883289 Jitter Meter : NO K
5975 13:08:16.885587 CBT Training : PASS
5976 13:08:16.885974 Write leveling : PASS
5977 13:08:16.889000 RX DQS gating : PASS
5978 13:08:16.892319 RX DQ/DQS(RDDQC) : PASS
5979 13:08:16.892711 TX DQ/DQS : PASS
5980 13:08:16.895709 RX DATLAT : PASS
5981 13:08:16.899160 RX DQ/DQS(Engine): PASS
5982 13:08:16.899549 TX OE : NO K
5983 13:08:16.902400 All Pass.
5984 13:08:16.902789
5985 13:08:16.903091 CH 1, Rank 1
5986 13:08:16.905701 SW Impedance : PASS
5987 13:08:16.906152 DUTY Scan : NO K
5988 13:08:16.908808 ZQ Calibration : PASS
5989 13:08:16.912494 Jitter Meter : NO K
5990 13:08:16.912891 CBT Training : PASS
5991 13:08:16.915622 Write leveling : PASS
5992 13:08:16.918922 RX DQS gating : PASS
5993 13:08:16.919306 RX DQ/DQS(RDDQC) : PASS
5994 13:08:16.922300 TX DQ/DQS : PASS
5995 13:08:16.925217 RX DATLAT : PASS
5996 13:08:16.925599 RX DQ/DQS(Engine): PASS
5997 13:08:16.928555 TX OE : NO K
5998 13:08:16.928966 All Pass.
5999 13:08:16.929267
6000 13:08:16.931767 DramC Write-DBI off
6001 13:08:16.935758 PER_BANK_REFRESH: Hybrid Mode
6002 13:08:16.936145 TX_TRACKING: ON
6003 13:08:16.945708 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6004 13:08:16.949062 [FAST_K] Save calibration result to emmc
6005 13:08:16.952058 dramc_set_vcore_voltage set vcore to 650000
6006 13:08:16.955712 Read voltage for 400, 6
6007 13:08:16.956229 Vio18 = 0
6008 13:08:16.956689 Vcore = 650000
6009 13:08:16.958716 Vdram = 0
6010 13:08:16.959102 Vddq = 0
6011 13:08:16.959435 Vmddr = 0
6012 13:08:16.965591 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6013 13:08:16.968944 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6014 13:08:16.971992 MEM_TYPE=3, freq_sel=20
6015 13:08:16.975547 sv_algorithm_assistance_LP4_800
6016 13:08:16.978580 ============ PULL DRAM RESETB DOWN ============
6017 13:08:16.982432 ========== PULL DRAM RESETB DOWN end =========
6018 13:08:16.988578 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6019 13:08:16.992071 ===================================
6020 13:08:16.992470 LPDDR4 DRAM CONFIGURATION
6021 13:08:16.995268 ===================================
6022 13:08:16.998669 EX_ROW_EN[0] = 0x0
6023 13:08:16.998961 EX_ROW_EN[1] = 0x0
6024 13:08:17.002240 LP4Y_EN = 0x0
6025 13:08:17.004782 WORK_FSP = 0x0
6026 13:08:17.004992 WL = 0x2
6027 13:08:17.008159 RL = 0x2
6028 13:08:17.008359 BL = 0x2
6029 13:08:17.011596 RPST = 0x0
6030 13:08:17.011778 RD_PRE = 0x0
6031 13:08:17.014898 WR_PRE = 0x1
6032 13:08:17.015084 WR_PST = 0x0
6033 13:08:17.018157 DBI_WR = 0x0
6034 13:08:17.018375 DBI_RD = 0x0
6035 13:08:17.021861 OTF = 0x1
6036 13:08:17.024805 ===================================
6037 13:08:17.028527 ===================================
6038 13:08:17.028735 ANA top config
6039 13:08:17.031824 ===================================
6040 13:08:17.035254 DLL_ASYNC_EN = 0
6041 13:08:17.038803 ALL_SLAVE_EN = 1
6042 13:08:17.038972 NEW_RANK_MODE = 1
6043 13:08:17.041411 DLL_IDLE_MODE = 1
6044 13:08:17.044828 LP45_APHY_COMB_EN = 1
6045 13:08:17.048135 TX_ODT_DIS = 1
6046 13:08:17.051357 NEW_8X_MODE = 1
6047 13:08:17.054789 ===================================
6048 13:08:17.058259 ===================================
6049 13:08:17.058488 data_rate = 800
6050 13:08:17.061683 CKR = 1
6051 13:08:17.065124 DQ_P2S_RATIO = 4
6052 13:08:17.068440 ===================================
6053 13:08:17.071567 CA_P2S_RATIO = 4
6054 13:08:17.074806 DQ_CA_OPEN = 0
6055 13:08:17.077965 DQ_SEMI_OPEN = 1
6056 13:08:17.078247 CA_SEMI_OPEN = 1
6057 13:08:17.081173 CA_FULL_RATE = 0
6058 13:08:17.084908 DQ_CKDIV4_EN = 0
6059 13:08:17.087873 CA_CKDIV4_EN = 1
6060 13:08:17.091275 CA_PREDIV_EN = 0
6061 13:08:17.094622 PH8_DLY = 0
6062 13:08:17.094798 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6063 13:08:17.098100 DQ_AAMCK_DIV = 0
6064 13:08:17.101073 CA_AAMCK_DIV = 0
6065 13:08:17.104904 CA_ADMCK_DIV = 4
6066 13:08:17.107811 DQ_TRACK_CA_EN = 0
6067 13:08:17.111112 CA_PICK = 800
6068 13:08:17.111199 CA_MCKIO = 400
6069 13:08:17.114576 MCKIO_SEMI = 400
6070 13:08:17.117885 PLL_FREQ = 3016
6071 13:08:17.121390 DQ_UI_PI_RATIO = 32
6072 13:08:17.124790 CA_UI_PI_RATIO = 32
6073 13:08:17.128022 ===================================
6074 13:08:17.131345 ===================================
6075 13:08:17.134516 memory_type:LPDDR4
6076 13:08:17.134630 GP_NUM : 10
6077 13:08:17.137606 SRAM_EN : 1
6078 13:08:17.137718 MD32_EN : 0
6079 13:08:17.140881 ===================================
6080 13:08:17.144182 [ANA_INIT] >>>>>>>>>>>>>>
6081 13:08:17.147481 <<<<<< [CONFIGURE PHASE]: ANA_TX
6082 13:08:17.151005 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6083 13:08:17.154396 ===================================
6084 13:08:17.157762 data_rate = 800,PCW = 0X7400
6085 13:08:17.161019 ===================================
6086 13:08:17.164582 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6087 13:08:17.171514 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6088 13:08:17.180626 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6089 13:08:17.184001 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6090 13:08:17.187254 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6091 13:08:17.194253 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6092 13:08:17.194405 [ANA_INIT] flow start
6093 13:08:17.197699 [ANA_INIT] PLL >>>>>>>>
6094 13:08:17.197781 [ANA_INIT] PLL <<<<<<<<
6095 13:08:17.201092 [ANA_INIT] MIDPI >>>>>>>>
6096 13:08:17.204335 [ANA_INIT] MIDPI <<<<<<<<
6097 13:08:17.207569 [ANA_INIT] DLL >>>>>>>>
6098 13:08:17.207687 [ANA_INIT] flow end
6099 13:08:17.210724 ============ LP4 DIFF to SE enter ============
6100 13:08:17.217691 ============ LP4 DIFF to SE exit ============
6101 13:08:17.217787 [ANA_INIT] <<<<<<<<<<<<<
6102 13:08:17.220677 [Flow] Enable top DCM control >>>>>
6103 13:08:17.224021 [Flow] Enable top DCM control <<<<<
6104 13:08:17.227403 Enable DLL master slave shuffle
6105 13:08:17.234223 ==============================================================
6106 13:08:17.234303 Gating Mode config
6107 13:08:17.240917 ==============================================================
6108 13:08:17.244183 Config description:
6109 13:08:17.250787 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6110 13:08:17.257396 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6111 13:08:17.264463 SELPH_MODE 0: By rank 1: By Phase
6112 13:08:17.270657 ==============================================================
6113 13:08:17.270739 GAT_TRACK_EN = 0
6114 13:08:17.274131 RX_GATING_MODE = 2
6115 13:08:17.277491 RX_GATING_TRACK_MODE = 2
6116 13:08:17.280803 SELPH_MODE = 1
6117 13:08:17.284090 PICG_EARLY_EN = 1
6118 13:08:17.287572 VALID_LAT_VALUE = 1
6119 13:08:17.294164 ==============================================================
6120 13:08:17.297597 Enter into Gating configuration >>>>
6121 13:08:17.301019 Exit from Gating configuration <<<<
6122 13:08:17.304355 Enter into DVFS_PRE_config >>>>>
6123 13:08:17.314078 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6124 13:08:17.317337 Exit from DVFS_PRE_config <<<<<
6125 13:08:17.320687 Enter into PICG configuration >>>>
6126 13:08:17.324515 Exit from PICG configuration <<<<
6127 13:08:17.327207 [RX_INPUT] configuration >>>>>
6128 13:08:17.327279 [RX_INPUT] configuration <<<<<
6129 13:08:17.333917 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6130 13:08:17.340590 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6131 13:08:17.344438 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6132 13:08:17.350880 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6133 13:08:17.357185 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6134 13:08:17.363772 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6135 13:08:17.367294 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6136 13:08:17.370949 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6137 13:08:17.377339 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6138 13:08:17.380958 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6139 13:08:17.384120 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6140 13:08:17.390696 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6141 13:08:17.394160 ===================================
6142 13:08:17.394247 LPDDR4 DRAM CONFIGURATION
6143 13:08:17.397188 ===================================
6144 13:08:17.400684 EX_ROW_EN[0] = 0x0
6145 13:08:17.400758 EX_ROW_EN[1] = 0x0
6146 13:08:17.404015 LP4Y_EN = 0x0
6147 13:08:17.404082 WORK_FSP = 0x0
6148 13:08:17.407500 WL = 0x2
6149 13:08:17.407580 RL = 0x2
6150 13:08:17.410835 BL = 0x2
6151 13:08:17.413640 RPST = 0x0
6152 13:08:17.413707 RD_PRE = 0x0
6153 13:08:17.417024 WR_PRE = 0x1
6154 13:08:17.417089 WR_PST = 0x0
6155 13:08:17.420514 DBI_WR = 0x0
6156 13:08:17.420586 DBI_RD = 0x0
6157 13:08:17.423866 OTF = 0x1
6158 13:08:17.427094 ===================================
6159 13:08:17.430598 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6160 13:08:17.433970 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6161 13:08:17.437470 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6162 13:08:17.440647 ===================================
6163 13:08:17.444184 LPDDR4 DRAM CONFIGURATION
6164 13:08:17.447403 ===================================
6165 13:08:17.450699 EX_ROW_EN[0] = 0x10
6166 13:08:17.450774 EX_ROW_EN[1] = 0x0
6167 13:08:17.454082 LP4Y_EN = 0x0
6168 13:08:17.454159 WORK_FSP = 0x0
6169 13:08:17.457439 WL = 0x2
6170 13:08:17.457507 RL = 0x2
6171 13:08:17.460872 BL = 0x2
6172 13:08:17.460940 RPST = 0x0
6173 13:08:17.463539 RD_PRE = 0x0
6174 13:08:17.463613 WR_PRE = 0x1
6175 13:08:17.466881 WR_PST = 0x0
6176 13:08:17.466947 DBI_WR = 0x0
6177 13:08:17.470348 DBI_RD = 0x0
6178 13:08:17.473633 OTF = 0x1
6179 13:08:17.476896 ===================================
6180 13:08:17.480078 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6181 13:08:17.485442 nWR fixed to 30
6182 13:08:17.489090 [ModeRegInit_LP4] CH0 RK0
6183 13:08:17.489173 [ModeRegInit_LP4] CH0 RK1
6184 13:08:17.492236 [ModeRegInit_LP4] CH1 RK0
6185 13:08:17.495879 [ModeRegInit_LP4] CH1 RK1
6186 13:08:17.495978 match AC timing 19
6187 13:08:17.502156 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6188 13:08:17.505943 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6189 13:08:17.508932 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6190 13:08:17.515431 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6191 13:08:17.519298 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6192 13:08:17.519371 ==
6193 13:08:17.522544 Dram Type= 6, Freq= 0, CH_0, rank 0
6194 13:08:17.525364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6195 13:08:17.525429 ==
6196 13:08:17.532125 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6197 13:08:17.538803 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6198 13:08:17.541992 [CA 0] Center 36 (8~64) winsize 57
6199 13:08:17.545478 [CA 1] Center 36 (8~64) winsize 57
6200 13:08:17.545544 [CA 2] Center 36 (8~64) winsize 57
6201 13:08:17.548795 [CA 3] Center 36 (8~64) winsize 57
6202 13:08:17.552250 [CA 4] Center 36 (8~64) winsize 57
6203 13:08:17.555431 [CA 5] Center 36 (8~64) winsize 57
6204 13:08:17.555533
6205 13:08:17.559355 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6206 13:08:17.559458
6207 13:08:17.565813 [CATrainingPosCal] consider 1 rank data
6208 13:08:17.565923 u2DelayCellTimex100 = 270/100 ps
6209 13:08:17.568734 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 13:08:17.575515 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6211 13:08:17.578879 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 13:08:17.582119 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 13:08:17.585511 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 13:08:17.588868 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 13:08:17.588935
6216 13:08:17.592356 CA PerBit enable=1, Macro0, CA PI delay=36
6217 13:08:17.592422
6218 13:08:17.595584 [CBTSetCACLKResult] CA Dly = 36
6219 13:08:17.598894 CS Dly: 1 (0~32)
6220 13:08:17.598963 ==
6221 13:08:17.602323 Dram Type= 6, Freq= 0, CH_0, rank 1
6222 13:08:17.605705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6223 13:08:17.605777 ==
6224 13:08:17.608945 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6225 13:08:17.615757 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6226 13:08:17.618672 [CA 0] Center 36 (8~64) winsize 57
6227 13:08:17.622166 [CA 1] Center 36 (8~64) winsize 57
6228 13:08:17.625245 [CA 2] Center 36 (8~64) winsize 57
6229 13:08:17.628910 [CA 3] Center 36 (8~64) winsize 57
6230 13:08:17.632324 [CA 4] Center 36 (8~64) winsize 57
6231 13:08:17.635316 [CA 5] Center 36 (8~64) winsize 57
6232 13:08:17.635384
6233 13:08:17.638851 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6234 13:08:17.638917
6235 13:08:17.642378 [CATrainingPosCal] consider 2 rank data
6236 13:08:17.645610 u2DelayCellTimex100 = 270/100 ps
6237 13:08:17.649107 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 13:08:17.652103 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 13:08:17.655576 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 13:08:17.659043 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 13:08:17.662351 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 13:08:17.669096 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 13:08:17.669226
6244 13:08:17.671717 CA PerBit enable=1, Macro0, CA PI delay=36
6245 13:08:17.671783
6246 13:08:17.675120 [CBTSetCACLKResult] CA Dly = 36
6247 13:08:17.675192 CS Dly: 1 (0~32)
6248 13:08:17.675257
6249 13:08:17.678522 ----->DramcWriteLeveling(PI) begin...
6250 13:08:17.678595 ==
6251 13:08:17.681895 Dram Type= 6, Freq= 0, CH_0, rank 0
6252 13:08:17.688558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6253 13:08:17.688637 ==
6254 13:08:17.692077 Write leveling (Byte 0): 40 => 8
6255 13:08:17.692144 Write leveling (Byte 1): 40 => 8
6256 13:08:17.695428 DramcWriteLeveling(PI) end<-----
6257 13:08:17.695497
6258 13:08:17.695552 ==
6259 13:08:17.698683 Dram Type= 6, Freq= 0, CH_0, rank 0
6260 13:08:17.705512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6261 13:08:17.705588 ==
6262 13:08:17.709021 [Gating] SW mode calibration
6263 13:08:17.714928 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6264 13:08:17.718345 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6265 13:08:17.725196 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6266 13:08:17.728677 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6267 13:08:17.732064 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6268 13:08:17.738527 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6269 13:08:17.741663 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6270 13:08:17.745321 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6271 13:08:17.751651 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 13:08:17.754911 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 13:08:17.758684 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 13:08:17.761571 Total UI for P1: 0, mck2ui 16
6275 13:08:17.764967 best dqsien dly found for B0: ( 0, 14, 24)
6276 13:08:17.768308 Total UI for P1: 0, mck2ui 16
6277 13:08:17.771741 best dqsien dly found for B1: ( 0, 14, 24)
6278 13:08:17.774850 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6279 13:08:17.778672 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6280 13:08:17.778776
6281 13:08:17.781644 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6282 13:08:17.787941 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6283 13:08:17.788043 [Gating] SW calibration Done
6284 13:08:17.788140 ==
6285 13:08:17.791480 Dram Type= 6, Freq= 0, CH_0, rank 0
6286 13:08:17.798464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6287 13:08:17.798549 ==
6288 13:08:17.798608 RX Vref Scan: 0
6289 13:08:17.798664
6290 13:08:17.801403 RX Vref 0 -> 0, step: 1
6291 13:08:17.801465
6292 13:08:17.804745 RX Delay -410 -> 252, step: 16
6293 13:08:17.808260 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6294 13:08:17.811674 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6295 13:08:17.817798 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6296 13:08:17.821901 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6297 13:08:17.824585 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6298 13:08:17.828014 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6299 13:08:17.834893 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6300 13:08:17.838375 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6301 13:08:17.841722 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6302 13:08:17.845076 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6303 13:08:17.851341 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6304 13:08:17.854578 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6305 13:08:17.858534 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6306 13:08:17.861286 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6307 13:08:17.868202 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6308 13:08:17.871617 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6309 13:08:17.871705 ==
6310 13:08:17.875033 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 13:08:17.878282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 13:08:17.878351 ==
6313 13:08:17.881432 DQS Delay:
6314 13:08:17.881502 DQS0 = 27, DQS1 = 35
6315 13:08:17.881558 DQM Delay:
6316 13:08:17.884630 DQM0 = 9, DQM1 = 11
6317 13:08:17.884720 DQ Delay:
6318 13:08:17.888036 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6319 13:08:17.891513 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6320 13:08:17.894708 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6321 13:08:17.897970 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6322 13:08:17.898073
6323 13:08:17.898132
6324 13:08:17.898196 ==
6325 13:08:17.901061 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 13:08:17.904641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 13:08:17.908415 ==
6328 13:08:17.908510
6329 13:08:17.908592
6330 13:08:17.908675 TX Vref Scan disable
6331 13:08:17.911071 == TX Byte 0 ==
6332 13:08:17.915103 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6333 13:08:17.917966 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6334 13:08:17.921397 == TX Byte 1 ==
6335 13:08:17.924505 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6336 13:08:17.928064 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6337 13:08:17.928169 ==
6338 13:08:17.931188 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 13:08:17.934256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 13:08:17.937829 ==
6341 13:08:17.937900
6342 13:08:17.937961
6343 13:08:17.938043 TX Vref Scan disable
6344 13:08:17.941144 == TX Byte 0 ==
6345 13:08:17.944666 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6346 13:08:17.948177 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6347 13:08:17.950781 == TX Byte 1 ==
6348 13:08:17.954590 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6349 13:08:17.957932 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6350 13:08:17.958088
6351 13:08:17.961133 [DATLAT]
6352 13:08:17.961224 Freq=400, CH0 RK0
6353 13:08:17.961283
6354 13:08:17.964360 DATLAT Default: 0xf
6355 13:08:17.964449 0, 0xFFFF, sum = 0
6356 13:08:17.967848 1, 0xFFFF, sum = 0
6357 13:08:17.967981 2, 0xFFFF, sum = 0
6358 13:08:17.971220 3, 0xFFFF, sum = 0
6359 13:08:17.971327 4, 0xFFFF, sum = 0
6360 13:08:17.974152 5, 0xFFFF, sum = 0
6361 13:08:17.974225 6, 0xFFFF, sum = 0
6362 13:08:17.977572 7, 0xFFFF, sum = 0
6363 13:08:17.977640 8, 0xFFFF, sum = 0
6364 13:08:17.981094 9, 0xFFFF, sum = 0
6365 13:08:17.981164 10, 0xFFFF, sum = 0
6366 13:08:17.984393 11, 0xFFFF, sum = 0
6367 13:08:17.984459 12, 0xFFFF, sum = 0
6368 13:08:17.987605 13, 0x0, sum = 1
6369 13:08:17.987672 14, 0x0, sum = 2
6370 13:08:17.991241 15, 0x0, sum = 3
6371 13:08:17.991310 16, 0x0, sum = 4
6372 13:08:17.993935 best_step = 14
6373 13:08:17.994068
6374 13:08:17.994126 ==
6375 13:08:17.997373 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 13:08:18.000818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 13:08:18.000886 ==
6378 13:08:18.003963 RX Vref Scan: 1
6379 13:08:18.004034
6380 13:08:18.004092 RX Vref 0 -> 0, step: 1
6381 13:08:18.004145
6382 13:08:18.007304 RX Delay -311 -> 252, step: 8
6383 13:08:18.007386
6384 13:08:18.010728 Set Vref, RX VrefLevel [Byte0]: 55
6385 13:08:18.014024 [Byte1]: 48
6386 13:08:18.018815
6387 13:08:18.018880 Final RX Vref Byte 0 = 55 to rank0
6388 13:08:18.022246 Final RX Vref Byte 1 = 48 to rank0
6389 13:08:18.025641 Final RX Vref Byte 0 = 55 to rank1
6390 13:08:18.028950 Final RX Vref Byte 1 = 48 to rank1==
6391 13:08:18.032264 Dram Type= 6, Freq= 0, CH_0, rank 0
6392 13:08:18.038562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6393 13:08:18.038634 ==
6394 13:08:18.038691 DQS Delay:
6395 13:08:18.038744 DQS0 = 28, DQS1 = 36
6396 13:08:18.042256 DQM Delay:
6397 13:08:18.042338 DQM0 = 10, DQM1 = 13
6398 13:08:18.045126 DQ Delay:
6399 13:08:18.048773 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6400 13:08:18.048856 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6401 13:08:18.052162 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6402 13:08:18.055625 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6403 13:08:18.055696
6404 13:08:18.055754
6405 13:08:18.065486 [DQSOSCAuto] RK0, (LSB)MR18= 0xd7c4, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 383 ps
6406 13:08:18.068704 CH0 RK0: MR19=C0C, MR18=D7C4
6407 13:08:18.072395 CH0_RK0: MR19=0xC0C, MR18=0xD7C4, DQSOSC=383, MR23=63, INC=402, DEC=268
6408 13:08:18.075441 ==
6409 13:08:18.078604 Dram Type= 6, Freq= 0, CH_0, rank 1
6410 13:08:18.082209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 13:08:18.082285 ==
6412 13:08:18.085490 [Gating] SW mode calibration
6413 13:08:18.092119 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6414 13:08:18.095409 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6415 13:08:18.101623 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6416 13:08:18.105136 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6417 13:08:18.108402 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6418 13:08:18.115211 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6419 13:08:18.118482 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6420 13:08:18.121683 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6421 13:08:18.128590 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6422 13:08:18.131892 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 13:08:18.135266 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6424 13:08:18.138606 Total UI for P1: 0, mck2ui 16
6425 13:08:18.141862 best dqsien dly found for B0: ( 0, 14, 24)
6426 13:08:18.145288 Total UI for P1: 0, mck2ui 16
6427 13:08:18.148164 best dqsien dly found for B1: ( 0, 14, 24)
6428 13:08:18.151482 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6429 13:08:18.158159 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6430 13:08:18.158249
6431 13:08:18.161601 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6432 13:08:18.165066 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6433 13:08:18.168113 [Gating] SW calibration Done
6434 13:08:18.168216 ==
6435 13:08:18.171337 Dram Type= 6, Freq= 0, CH_0, rank 1
6436 13:08:18.174404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 13:08:18.174506 ==
6438 13:08:18.177804 RX Vref Scan: 0
6439 13:08:18.177930
6440 13:08:18.178051 RX Vref 0 -> 0, step: 1
6441 13:08:18.178133
6442 13:08:18.181279 RX Delay -410 -> 252, step: 16
6443 13:08:18.184626 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6444 13:08:18.191363 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6445 13:08:18.194858 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6446 13:08:18.197496 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6447 13:08:18.201361 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6448 13:08:18.207797 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6449 13:08:18.211378 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6450 13:08:18.214595 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6451 13:08:18.218396 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6452 13:08:18.224142 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6453 13:08:18.227526 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6454 13:08:18.230845 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6455 13:08:18.234215 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6456 13:08:18.241061 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6457 13:08:18.244422 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6458 13:08:18.247625 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6459 13:08:18.247696 ==
6460 13:08:18.251023 Dram Type= 6, Freq= 0, CH_0, rank 1
6461 13:08:18.257186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 13:08:18.257274 ==
6463 13:08:18.257333 DQS Delay:
6464 13:08:18.260691 DQS0 = 27, DQS1 = 35
6465 13:08:18.260760 DQM Delay:
6466 13:08:18.260818 DQM0 = 12, DQM1 = 12
6467 13:08:18.264179 DQ Delay:
6468 13:08:18.267465 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6469 13:08:18.267533 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6470 13:08:18.270915 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6471 13:08:18.273641 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6472 13:08:18.277066
6473 13:08:18.277131
6474 13:08:18.277185 ==
6475 13:08:18.280452 Dram Type= 6, Freq= 0, CH_0, rank 1
6476 13:08:18.283741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 13:08:18.283806 ==
6478 13:08:18.283860
6479 13:08:18.283911
6480 13:08:18.287233 TX Vref Scan disable
6481 13:08:18.287347 == TX Byte 0 ==
6482 13:08:18.290709 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6483 13:08:18.297432 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6484 13:08:18.297517 == TX Byte 1 ==
6485 13:08:18.300749 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6486 13:08:18.306963 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6487 13:08:18.307046 ==
6488 13:08:18.310392 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 13:08:18.313848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 13:08:18.313956 ==
6491 13:08:18.314084
6492 13:08:18.314158
6493 13:08:18.317225 TX Vref Scan disable
6494 13:08:18.317299 == TX Byte 0 ==
6495 13:08:18.320662 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6496 13:08:18.327133 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6497 13:08:18.327206 == TX Byte 1 ==
6498 13:08:18.330644 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6499 13:08:18.337486 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6500 13:08:18.337574
6501 13:08:18.337671 [DATLAT]
6502 13:08:18.337772 Freq=400, CH0 RK1
6503 13:08:18.337876
6504 13:08:18.340741 DATLAT Default: 0xe
6505 13:08:18.340835 0, 0xFFFF, sum = 0
6506 13:08:18.343847 1, 0xFFFF, sum = 0
6507 13:08:18.343947 2, 0xFFFF, sum = 0
6508 13:08:18.347124 3, 0xFFFF, sum = 0
6509 13:08:18.350755 4, 0xFFFF, sum = 0
6510 13:08:18.350828 5, 0xFFFF, sum = 0
6511 13:08:18.353847 6, 0xFFFF, sum = 0
6512 13:08:18.353926 7, 0xFFFF, sum = 0
6513 13:08:18.357127 8, 0xFFFF, sum = 0
6514 13:08:18.357204 9, 0xFFFF, sum = 0
6515 13:08:18.360421 10, 0xFFFF, sum = 0
6516 13:08:18.360544 11, 0xFFFF, sum = 0
6517 13:08:18.363622 12, 0xFFFF, sum = 0
6518 13:08:18.363732 13, 0x0, sum = 1
6519 13:08:18.366998 14, 0x0, sum = 2
6520 13:08:18.367093 15, 0x0, sum = 3
6521 13:08:18.370338 16, 0x0, sum = 4
6522 13:08:18.370442 best_step = 14
6523 13:08:18.370529
6524 13:08:18.370608 ==
6525 13:08:18.373708 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 13:08:18.377175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 13:08:18.380527 ==
6528 13:08:18.380632 RX Vref Scan: 0
6529 13:08:18.380721
6530 13:08:18.383823 RX Vref 0 -> 0, step: 1
6531 13:08:18.383891
6532 13:08:18.387175 RX Delay -311 -> 252, step: 8
6533 13:08:18.390610 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6534 13:08:18.397246 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6535 13:08:18.400386 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6536 13:08:18.403749 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6537 13:08:18.406588 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6538 13:08:18.413367 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6539 13:08:18.416768 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6540 13:08:18.420055 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6541 13:08:18.423509 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6542 13:08:18.430209 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6543 13:08:18.433547 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6544 13:08:18.436901 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6545 13:08:18.439904 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6546 13:08:18.447100 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6547 13:08:18.449739 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6548 13:08:18.453483 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6549 13:08:18.453559 ==
6550 13:08:18.456962 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 13:08:18.463294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 13:08:18.463374 ==
6553 13:08:18.463433 DQS Delay:
6554 13:08:18.466689 DQS0 = 24, DQS1 = 36
6555 13:08:18.466764 DQM Delay:
6556 13:08:18.466822 DQM0 = 9, DQM1 = 13
6557 13:08:18.470234 DQ Delay:
6558 13:08:18.473341 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6559 13:08:18.473439 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6560 13:08:18.476575 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6561 13:08:18.479944 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6562 13:08:18.480020
6563 13:08:18.480077
6564 13:08:18.489895 [DQSOSCAuto] RK1, (LSB)MR18= 0xc767, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 385 ps
6565 13:08:18.493826 CH0 RK1: MR19=C0C, MR18=C767
6566 13:08:18.499943 CH0_RK1: MR19=0xC0C, MR18=0xC767, DQSOSC=385, MR23=63, INC=398, DEC=265
6567 13:08:18.500019 [RxdqsGatingPostProcess] freq 400
6568 13:08:18.506659 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6569 13:08:18.510149 best DQS0 dly(2T, 0.5T) = (0, 10)
6570 13:08:18.513529 best DQS1 dly(2T, 0.5T) = (0, 10)
6571 13:08:18.516878 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6572 13:08:18.520223 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6573 13:08:18.523567 best DQS0 dly(2T, 0.5T) = (0, 10)
6574 13:08:18.526849 best DQS1 dly(2T, 0.5T) = (0, 10)
6575 13:08:18.530222 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6576 13:08:18.533565 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6577 13:08:18.537042 Pre-setting of DQS Precalculation
6578 13:08:18.540595 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6579 13:08:18.540675 ==
6580 13:08:18.543352 Dram Type= 6, Freq= 0, CH_1, rank 0
6581 13:08:18.546659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6582 13:08:18.546746 ==
6583 13:08:18.553335 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6584 13:08:18.560255 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6585 13:08:18.563381 [CA 0] Center 36 (8~64) winsize 57
6586 13:08:18.566606 [CA 1] Center 36 (8~64) winsize 57
6587 13:08:18.570071 [CA 2] Center 36 (8~64) winsize 57
6588 13:08:18.573583 [CA 3] Center 36 (8~64) winsize 57
6589 13:08:18.577029 [CA 4] Center 36 (8~64) winsize 57
6590 13:08:18.580333 [CA 5] Center 36 (8~64) winsize 57
6591 13:08:18.580595
6592 13:08:18.583301 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6593 13:08:18.583387
6594 13:08:18.586715 [CATrainingPosCal] consider 1 rank data
6595 13:08:18.589988 u2DelayCellTimex100 = 270/100 ps
6596 13:08:18.593343 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 13:08:18.596436 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6598 13:08:18.599754 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 13:08:18.603083 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 13:08:18.606383 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 13:08:18.609876 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 13:08:18.609993
6603 13:08:18.613018 CA PerBit enable=1, Macro0, CA PI delay=36
6604 13:08:18.613134
6605 13:08:18.616573 [CBTSetCACLKResult] CA Dly = 36
6606 13:08:18.620007 CS Dly: 1 (0~32)
6607 13:08:18.620227 ==
6608 13:08:18.622947 Dram Type= 6, Freq= 0, CH_1, rank 1
6609 13:08:18.626271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6610 13:08:18.626477 ==
6611 13:08:18.632961 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6612 13:08:18.639907 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6613 13:08:18.640233 [CA 0] Center 36 (8~64) winsize 57
6614 13:08:18.643408 [CA 1] Center 36 (8~64) winsize 57
6615 13:08:18.646810 [CA 2] Center 36 (8~64) winsize 57
6616 13:08:18.650405 [CA 3] Center 36 (8~64) winsize 57
6617 13:08:18.653582 [CA 4] Center 36 (8~64) winsize 57
6618 13:08:18.657026 [CA 5] Center 36 (8~64) winsize 57
6619 13:08:18.657515
6620 13:08:18.660293 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6621 13:08:18.660690
6622 13:08:18.663580 [CATrainingPosCal] consider 2 rank data
6623 13:08:18.666587 u2DelayCellTimex100 = 270/100 ps
6624 13:08:18.670107 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 13:08:18.673413 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 13:08:18.680464 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 13:08:18.683794 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 13:08:18.687118 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 13:08:18.690237 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 13:08:18.690624
6631 13:08:18.693528 CA PerBit enable=1, Macro0, CA PI delay=36
6632 13:08:18.693915
6633 13:08:18.696907 [CBTSetCACLKResult] CA Dly = 36
6634 13:08:18.697329 CS Dly: 1 (0~32)
6635 13:08:18.697631
6636 13:08:18.700469 ----->DramcWriteLeveling(PI) begin...
6637 13:08:18.703078 ==
6638 13:08:18.706203 Dram Type= 6, Freq= 0, CH_1, rank 0
6639 13:08:18.709499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6640 13:08:18.709704 ==
6641 13:08:18.713023 Write leveling (Byte 0): 40 => 8
6642 13:08:18.716239 Write leveling (Byte 1): 40 => 8
6643 13:08:18.719530 DramcWriteLeveling(PI) end<-----
6644 13:08:18.719670
6645 13:08:18.719777 ==
6646 13:08:18.723197 Dram Type= 6, Freq= 0, CH_1, rank 0
6647 13:08:18.726302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 13:08:18.726448 ==
6649 13:08:18.729960 [Gating] SW mode calibration
6650 13:08:18.736304 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6651 13:08:18.739755 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6652 13:08:18.746177 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6653 13:08:18.749811 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6654 13:08:18.753177 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6655 13:08:18.759458 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6656 13:08:18.762788 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6657 13:08:18.766232 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6658 13:08:18.772881 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6659 13:08:18.776200 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 13:08:18.779472 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6661 13:08:18.783082 Total UI for P1: 0, mck2ui 16
6662 13:08:18.786236 best dqsien dly found for B0: ( 0, 14, 24)
6663 13:08:18.789483 Total UI for P1: 0, mck2ui 16
6664 13:08:18.792964 best dqsien dly found for B1: ( 0, 14, 24)
6665 13:08:18.796205 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6666 13:08:18.799979 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6667 13:08:18.800201
6668 13:08:18.806232 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6669 13:08:18.809666 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6670 13:08:18.813181 [Gating] SW calibration Done
6671 13:08:18.813566 ==
6672 13:08:18.816623 Dram Type= 6, Freq= 0, CH_1, rank 0
6673 13:08:18.819969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6674 13:08:18.820356 ==
6675 13:08:18.820654 RX Vref Scan: 0
6676 13:08:18.820932
6677 13:08:18.823454 RX Vref 0 -> 0, step: 1
6678 13:08:18.823839
6679 13:08:18.826818 RX Delay -410 -> 252, step: 16
6680 13:08:18.830135 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6681 13:08:18.836776 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6682 13:08:18.839968 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6683 13:08:18.843247 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6684 13:08:18.846713 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6685 13:08:18.849980 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6686 13:08:18.856486 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6687 13:08:18.859526 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6688 13:08:18.863076 iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448
6689 13:08:18.866426 iDelay=230, Bit 9, Center -27 (-250 ~ 197) 448
6690 13:08:18.873364 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6691 13:08:18.876709 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6692 13:08:18.880096 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6693 13:08:18.883402 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6694 13:08:18.889866 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6695 13:08:18.893205 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6696 13:08:18.893601 ==
6697 13:08:18.896219 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 13:08:18.899478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 13:08:18.899924 ==
6700 13:08:18.902713 DQS Delay:
6701 13:08:18.903094 DQS0 = 27, DQS1 = 27
6702 13:08:18.906482 DQM Delay:
6703 13:08:18.906891 DQM0 = 11, DQM1 = 8
6704 13:08:18.907196 DQ Delay:
6705 13:08:18.909605 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6706 13:08:18.913050 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6707 13:08:18.916414 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6708 13:08:18.919609 DQ12 =16, DQ13 =8, DQ14 =8, DQ15 =16
6709 13:08:18.920024
6710 13:08:18.920334
6711 13:08:18.920608 ==
6712 13:08:18.923015 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 13:08:18.929698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 13:08:18.930116 ==
6715 13:08:18.930421
6716 13:08:18.930696
6717 13:08:18.930960 TX Vref Scan disable
6718 13:08:18.933024 == TX Byte 0 ==
6719 13:08:18.936353 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6720 13:08:18.939753 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6721 13:08:18.942974 == TX Byte 1 ==
6722 13:08:18.945910 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6723 13:08:18.949114 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6724 13:08:18.949496 ==
6725 13:08:18.952581 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 13:08:18.959399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 13:08:18.959787 ==
6728 13:08:18.960087
6729 13:08:18.960363
6730 13:08:18.960625 TX Vref Scan disable
6731 13:08:18.962708 == TX Byte 0 ==
6732 13:08:18.966142 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6733 13:08:18.969572 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6734 13:08:18.972983 == TX Byte 1 ==
6735 13:08:18.976247 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6736 13:08:18.979459 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6737 13:08:18.979842
6738 13:08:18.982450 [DATLAT]
6739 13:08:18.982832 Freq=400, CH1 RK0
6740 13:08:18.983131
6741 13:08:18.985926 DATLAT Default: 0xf
6742 13:08:18.986342 0, 0xFFFF, sum = 0
6743 13:08:18.989544 1, 0xFFFF, sum = 0
6744 13:08:18.989931 2, 0xFFFF, sum = 0
6745 13:08:18.992679 3, 0xFFFF, sum = 0
6746 13:08:18.993183 4, 0xFFFF, sum = 0
6747 13:08:18.996123 5, 0xFFFF, sum = 0
6748 13:08:18.996559 6, 0xFFFF, sum = 0
6749 13:08:18.999214 7, 0xFFFF, sum = 0
6750 13:08:18.999608 8, 0xFFFF, sum = 0
6751 13:08:19.002307 9, 0xFFFF, sum = 0
6752 13:08:19.002843 10, 0xFFFF, sum = 0
6753 13:08:19.005581 11, 0xFFFF, sum = 0
6754 13:08:19.008987 12, 0xFFFF, sum = 0
6755 13:08:19.009438 13, 0x0, sum = 1
6756 13:08:19.009749 14, 0x0, sum = 2
6757 13:08:19.012505 15, 0x0, sum = 3
6758 13:08:19.012898 16, 0x0, sum = 4
6759 13:08:19.015980 best_step = 14
6760 13:08:19.016362
6761 13:08:19.016662 ==
6762 13:08:19.018850 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 13:08:19.022670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 13:08:19.023057 ==
6765 13:08:19.025745 RX Vref Scan: 1
6766 13:08:19.026180
6767 13:08:19.026484 RX Vref 0 -> 0, step: 1
6768 13:08:19.028740
6769 13:08:19.029123 RX Delay -295 -> 252, step: 8
6770 13:08:19.029426
6771 13:08:19.032609 Set Vref, RX VrefLevel [Byte0]: 55
6772 13:08:19.035217 [Byte1]: 53
6773 13:08:19.040758
6774 13:08:19.041138 Final RX Vref Byte 0 = 55 to rank0
6775 13:08:19.043981 Final RX Vref Byte 1 = 53 to rank0
6776 13:08:19.047334 Final RX Vref Byte 0 = 55 to rank1
6777 13:08:19.050664 Final RX Vref Byte 1 = 53 to rank1==
6778 13:08:19.053872 Dram Type= 6, Freq= 0, CH_1, rank 0
6779 13:08:19.060636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6780 13:08:19.061031 ==
6781 13:08:19.061487 DQS Delay:
6782 13:08:19.063486 DQS0 = 28, DQS1 = 32
6783 13:08:19.063877 DQM Delay:
6784 13:08:19.064184 DQM0 = 9, DQM1 = 11
6785 13:08:19.066830 DQ Delay:
6786 13:08:19.070135 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6787 13:08:19.070557 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6788 13:08:19.073619 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6789 13:08:19.077083 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6790 13:08:19.077560
6791 13:08:19.077867
6792 13:08:19.087205 [DQSOSCAuto] RK0, (LSB)MR18= 0x9ad2, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6793 13:08:19.090560 CH1 RK0: MR19=C0C, MR18=9AD2
6794 13:08:19.096792 CH1_RK0: MR19=0xC0C, MR18=0x9AD2, DQSOSC=383, MR23=63, INC=402, DEC=268
6795 13:08:19.097235 ==
6796 13:08:19.100227 Dram Type= 6, Freq= 0, CH_1, rank 1
6797 13:08:19.103863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 13:08:19.104256 ==
6799 13:08:19.106901 [Gating] SW mode calibration
6800 13:08:19.113243 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6801 13:08:19.116708 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6802 13:08:19.123150 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6803 13:08:19.126591 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6804 13:08:19.130257 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6805 13:08:19.136549 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6806 13:08:19.139871 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6807 13:08:19.143502 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6808 13:08:19.149666 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6809 13:08:19.153127 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 13:08:19.156663 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6811 13:08:19.159953 Total UI for P1: 0, mck2ui 16
6812 13:08:19.163100 best dqsien dly found for B0: ( 0, 14, 24)
6813 13:08:19.166786 Total UI for P1: 0, mck2ui 16
6814 13:08:19.169468 best dqsien dly found for B1: ( 0, 14, 24)
6815 13:08:19.172853 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6816 13:08:19.176419 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6817 13:08:19.179951
6818 13:08:19.183798 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6819 13:08:19.186116 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6820 13:08:19.189647 [Gating] SW calibration Done
6821 13:08:19.190058 ==
6822 13:08:19.193075 Dram Type= 6, Freq= 0, CH_1, rank 1
6823 13:08:19.196529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 13:08:19.196926 ==
6825 13:08:19.197227 RX Vref Scan: 0
6826 13:08:19.197514
6827 13:08:19.199949 RX Vref 0 -> 0, step: 1
6828 13:08:19.200343
6829 13:08:19.203409 RX Delay -410 -> 252, step: 16
6830 13:08:19.206926 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6831 13:08:19.212941 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6832 13:08:19.216272 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6833 13:08:19.219450 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6834 13:08:19.223179 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6835 13:08:19.230001 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6836 13:08:19.233043 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6837 13:08:19.236270 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6838 13:08:19.239740 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6839 13:08:19.246103 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6840 13:08:19.249468 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6841 13:08:19.252842 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6842 13:08:19.255976 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6843 13:08:19.262857 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6844 13:08:19.266142 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6845 13:08:19.269492 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6846 13:08:19.269886 ==
6847 13:08:19.272524 Dram Type= 6, Freq= 0, CH_1, rank 1
6848 13:08:19.275701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 13:08:19.279333 ==
6850 13:08:19.279722 DQS Delay:
6851 13:08:19.280025 DQS0 = 35, DQS1 = 35
6852 13:08:19.282548 DQM Delay:
6853 13:08:19.282935 DQM0 = 18, DQM1 = 15
6854 13:08:19.286067 DQ Delay:
6855 13:08:19.289443 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6856 13:08:19.289861 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6857 13:08:19.292453 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6858 13:08:19.295995 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6859 13:08:19.296374
6860 13:08:19.296670
6861 13:08:19.298973 ==
6862 13:08:19.302652 Dram Type= 6, Freq= 0, CH_1, rank 1
6863 13:08:19.305986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 13:08:19.306420 ==
6865 13:08:19.306784
6866 13:08:19.307089
6867 13:08:19.309313 TX Vref Scan disable
6868 13:08:19.309701 == TX Byte 0 ==
6869 13:08:19.312693 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6870 13:08:19.319520 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6871 13:08:19.319983 == TX Byte 1 ==
6872 13:08:19.322820 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6873 13:08:19.329499 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6874 13:08:19.329995 ==
6875 13:08:19.332732 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 13:08:19.336060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 13:08:19.336546 ==
6878 13:08:19.336856
6879 13:08:19.337231
6880 13:08:19.339581 TX Vref Scan disable
6881 13:08:19.340005 == TX Byte 0 ==
6882 13:08:19.342798 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6883 13:08:19.349262 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6884 13:08:19.349689 == TX Byte 1 ==
6885 13:08:19.352490 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6886 13:08:19.359329 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6887 13:08:19.359729
6888 13:08:19.360027 [DATLAT]
6889 13:08:19.360306 Freq=400, CH1 RK1
6890 13:08:19.360576
6891 13:08:19.362439 DATLAT Default: 0xe
6892 13:08:19.362901 0, 0xFFFF, sum = 0
6893 13:08:19.365700 1, 0xFFFF, sum = 0
6894 13:08:19.366263 2, 0xFFFF, sum = 0
6895 13:08:19.369107 3, 0xFFFF, sum = 0
6896 13:08:19.372438 4, 0xFFFF, sum = 0
6897 13:08:19.372914 5, 0xFFFF, sum = 0
6898 13:08:19.375906 6, 0xFFFF, sum = 0
6899 13:08:19.376354 7, 0xFFFF, sum = 0
6900 13:08:19.379385 8, 0xFFFF, sum = 0
6901 13:08:19.379780 9, 0xFFFF, sum = 0
6902 13:08:19.382705 10, 0xFFFF, sum = 0
6903 13:08:19.383234 11, 0xFFFF, sum = 0
6904 13:08:19.386156 12, 0xFFFF, sum = 0
6905 13:08:19.386672 13, 0x0, sum = 1
6906 13:08:19.389495 14, 0x0, sum = 2
6907 13:08:19.389890 15, 0x0, sum = 3
6908 13:08:19.392665 16, 0x0, sum = 4
6909 13:08:19.393054 best_step = 14
6910 13:08:19.393358
6911 13:08:19.393635 ==
6912 13:08:19.395878 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 13:08:19.399178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 13:08:19.399566 ==
6915 13:08:19.402781 RX Vref Scan: 0
6916 13:08:19.403192
6917 13:08:19.406193 RX Vref 0 -> 0, step: 1
6918 13:08:19.406579
6919 13:08:19.406880 RX Delay -311 -> 252, step: 8
6920 13:08:19.414631 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6921 13:08:19.417807 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6922 13:08:19.421163 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6923 13:08:19.424475 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6924 13:08:19.431583 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6925 13:08:19.434544 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6926 13:08:19.437961 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6927 13:08:19.441402 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6928 13:08:19.447851 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6929 13:08:19.451630 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6930 13:08:19.454783 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6931 13:08:19.458122 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6932 13:08:19.465007 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6933 13:08:19.468448 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6934 13:08:19.471825 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6935 13:08:19.474592 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6936 13:08:19.477926 ==
6937 13:08:19.478398 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 13:08:19.484641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 13:08:19.485072 ==
6940 13:08:19.485420 DQS Delay:
6941 13:08:19.487953 DQS0 = 28, DQS1 = 36
6942 13:08:19.488434 DQM Delay:
6943 13:08:19.491567 DQM0 = 10, DQM1 = 15
6944 13:08:19.491954 DQ Delay:
6945 13:08:19.494780 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6946 13:08:19.498134 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6947 13:08:19.501612 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6948 13:08:19.505068 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6949 13:08:19.505499
6950 13:08:19.505812
6951 13:08:19.511305 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf60, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 384 ps
6952 13:08:19.514690 CH1 RK1: MR19=C0C, MR18=CF60
6953 13:08:19.520899 CH1_RK1: MR19=0xC0C, MR18=0xCF60, DQSOSC=384, MR23=63, INC=400, DEC=267
6954 13:08:19.525120 [RxdqsGatingPostProcess] freq 400
6955 13:08:19.528122 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6956 13:08:19.531199 best DQS0 dly(2T, 0.5T) = (0, 10)
6957 13:08:19.534831 best DQS1 dly(2T, 0.5T) = (0, 10)
6958 13:08:19.537844 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6959 13:08:19.540868 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6960 13:08:19.544372 best DQS0 dly(2T, 0.5T) = (0, 10)
6961 13:08:19.547835 best DQS1 dly(2T, 0.5T) = (0, 10)
6962 13:08:19.551165 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6963 13:08:19.554636 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6964 13:08:19.557826 Pre-setting of DQS Precalculation
6965 13:08:19.560937 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6966 13:08:19.570932 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6967 13:08:19.577839 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6968 13:08:19.578261
6969 13:08:19.578563
6970 13:08:19.581020 [Calibration Summary] 800 Mbps
6971 13:08:19.581401 CH 0, Rank 0
6972 13:08:19.584505 SW Impedance : PASS
6973 13:08:19.584974 DUTY Scan : NO K
6974 13:08:19.587323 ZQ Calibration : PASS
6975 13:08:19.590602 Jitter Meter : NO K
6976 13:08:19.590990 CBT Training : PASS
6977 13:08:19.594076 Write leveling : PASS
6978 13:08:19.597432 RX DQS gating : PASS
6979 13:08:19.597815 RX DQ/DQS(RDDQC) : PASS
6980 13:08:19.600708 TX DQ/DQS : PASS
6981 13:08:19.604028 RX DATLAT : PASS
6982 13:08:19.604490 RX DQ/DQS(Engine): PASS
6983 13:08:19.607586 TX OE : NO K
6984 13:08:19.607998 All Pass.
6985 13:08:19.608375
6986 13:08:19.610939 CH 0, Rank 1
6987 13:08:19.611350 SW Impedance : PASS
6988 13:08:19.614380 DUTY Scan : NO K
6989 13:08:19.614803 ZQ Calibration : PASS
6990 13:08:19.617685 Jitter Meter : NO K
6991 13:08:19.621455 CBT Training : PASS
6992 13:08:19.621929 Write leveling : NO K
6993 13:08:19.624625 RX DQS gating : PASS
6994 13:08:19.628199 RX DQ/DQS(RDDQC) : PASS
6995 13:08:19.628708 TX DQ/DQS : PASS
6996 13:08:19.631183 RX DATLAT : PASS
6997 13:08:19.634616 RX DQ/DQS(Engine): PASS
6998 13:08:19.635076 TX OE : NO K
6999 13:08:19.637302 All Pass.
7000 13:08:19.637772
7001 13:08:19.638153 CH 1, Rank 0
7002 13:08:19.640628 SW Impedance : PASS
7003 13:08:19.641115 DUTY Scan : NO K
7004 13:08:19.644489 ZQ Calibration : PASS
7005 13:08:19.647800 Jitter Meter : NO K
7006 13:08:19.648256 CBT Training : PASS
7007 13:08:19.651080 Write leveling : PASS
7008 13:08:19.654317 RX DQS gating : PASS
7009 13:08:19.654813 RX DQ/DQS(RDDQC) : PASS
7010 13:08:19.657875 TX DQ/DQS : PASS
7011 13:08:19.658385 RX DATLAT : PASS
7012 13:08:19.661153 RX DQ/DQS(Engine): PASS
7013 13:08:19.664600 TX OE : NO K
7014 13:08:19.665072 All Pass.
7015 13:08:19.665481
7016 13:08:19.665776 CH 1, Rank 1
7017 13:08:19.667291 SW Impedance : PASS
7018 13:08:19.670801 DUTY Scan : NO K
7019 13:08:19.671205 ZQ Calibration : PASS
7020 13:08:19.673910 Jitter Meter : NO K
7021 13:08:19.677391 CBT Training : PASS
7022 13:08:19.677784 Write leveling : NO K
7023 13:08:19.680815 RX DQS gating : PASS
7024 13:08:19.684055 RX DQ/DQS(RDDQC) : PASS
7025 13:08:19.684495 TX DQ/DQS : PASS
7026 13:08:19.687767 RX DATLAT : PASS
7027 13:08:19.690776 RX DQ/DQS(Engine): PASS
7028 13:08:19.691165 TX OE : NO K
7029 13:08:19.694221 All Pass.
7030 13:08:19.694611
7031 13:08:19.694910 DramC Write-DBI off
7032 13:08:19.697388 PER_BANK_REFRESH: Hybrid Mode
7033 13:08:19.697773 TX_TRACKING: ON
7034 13:08:19.707383 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7035 13:08:19.710620 [FAST_K] Save calibration result to emmc
7036 13:08:19.713775 dramc_set_vcore_voltage set vcore to 725000
7037 13:08:19.716858 Read voltage for 1600, 0
7038 13:08:19.717247 Vio18 = 0
7039 13:08:19.720437 Vcore = 725000
7040 13:08:19.720943 Vdram = 0
7041 13:08:19.721320 Vddq = 0
7042 13:08:19.723908 Vmddr = 0
7043 13:08:19.726693 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7044 13:08:19.733337 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7045 13:08:19.733732 MEM_TYPE=3, freq_sel=13
7046 13:08:19.737421 sv_algorithm_assistance_LP4_3733
7047 13:08:19.743522 ============ PULL DRAM RESETB DOWN ============
7048 13:08:19.747246 ========== PULL DRAM RESETB DOWN end =========
7049 13:08:19.750596 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7050 13:08:19.753255 ===================================
7051 13:08:19.756645 LPDDR4 DRAM CONFIGURATION
7052 13:08:19.760183 ===================================
7053 13:08:19.760648 EX_ROW_EN[0] = 0x0
7054 13:08:19.763301 EX_ROW_EN[1] = 0x0
7055 13:08:19.766897 LP4Y_EN = 0x0
7056 13:08:19.767376 WORK_FSP = 0x1
7057 13:08:19.770315 WL = 0x5
7058 13:08:19.770850 RL = 0x5
7059 13:08:19.773544 BL = 0x2
7060 13:08:19.773933 RPST = 0x0
7061 13:08:19.776755 RD_PRE = 0x0
7062 13:08:19.777156 WR_PRE = 0x1
7063 13:08:19.779771 WR_PST = 0x1
7064 13:08:19.780161 DBI_WR = 0x0
7065 13:08:19.783424 DBI_RD = 0x0
7066 13:08:19.783865 OTF = 0x1
7067 13:08:19.786841 ===================================
7068 13:08:19.790363 ===================================
7069 13:08:19.793794 ANA top config
7070 13:08:19.797111 ===================================
7071 13:08:19.797569 DLL_ASYNC_EN = 0
7072 13:08:19.799773 ALL_SLAVE_EN = 0
7073 13:08:19.803200 NEW_RANK_MODE = 1
7074 13:08:19.806540 DLL_IDLE_MODE = 1
7075 13:08:19.809805 LP45_APHY_COMB_EN = 1
7076 13:08:19.810358 TX_ODT_DIS = 0
7077 13:08:19.813663 NEW_8X_MODE = 1
7078 13:08:19.816718 ===================================
7079 13:08:19.819824 ===================================
7080 13:08:19.823185 data_rate = 3200
7081 13:08:19.826614 CKR = 1
7082 13:08:19.829890 DQ_P2S_RATIO = 8
7083 13:08:19.833222 ===================================
7084 13:08:19.833615 CA_P2S_RATIO = 8
7085 13:08:19.836262 DQ_CA_OPEN = 0
7086 13:08:19.839826 DQ_SEMI_OPEN = 0
7087 13:08:19.843369 CA_SEMI_OPEN = 0
7088 13:08:19.846649 CA_FULL_RATE = 0
7089 13:08:19.849709 DQ_CKDIV4_EN = 0
7090 13:08:19.850242 CA_CKDIV4_EN = 0
7091 13:08:19.852719 CA_PREDIV_EN = 0
7092 13:08:19.856701 PH8_DLY = 12
7093 13:08:19.860008 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7094 13:08:19.863431 DQ_AAMCK_DIV = 4
7095 13:08:19.866491 CA_AAMCK_DIV = 4
7096 13:08:19.866881 CA_ADMCK_DIV = 4
7097 13:08:19.869687 DQ_TRACK_CA_EN = 0
7098 13:08:19.872816 CA_PICK = 1600
7099 13:08:19.876292 CA_MCKIO = 1600
7100 13:08:19.879756 MCKIO_SEMI = 0
7101 13:08:19.883116 PLL_FREQ = 3068
7102 13:08:19.886389 DQ_UI_PI_RATIO = 32
7103 13:08:19.889551 CA_UI_PI_RATIO = 0
7104 13:08:19.893271 ===================================
7105 13:08:19.896587 ===================================
7106 13:08:19.896977 memory_type:LPDDR4
7107 13:08:19.899978 GP_NUM : 10
7108 13:08:19.900365 SRAM_EN : 1
7109 13:08:19.902698 MD32_EN : 0
7110 13:08:19.906170 ===================================
7111 13:08:19.909646 [ANA_INIT] >>>>>>>>>>>>>>
7112 13:08:19.913414 <<<<<< [CONFIGURE PHASE]: ANA_TX
7113 13:08:19.916726 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7114 13:08:19.919473 ===================================
7115 13:08:19.922664 data_rate = 3200,PCW = 0X7600
7116 13:08:19.926212 ===================================
7117 13:08:19.929294 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7118 13:08:19.932832 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7119 13:08:19.939606 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7120 13:08:19.942826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7121 13:08:19.946241 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7122 13:08:19.949354 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7123 13:08:19.953082 [ANA_INIT] flow start
7124 13:08:19.956444 [ANA_INIT] PLL >>>>>>>>
7125 13:08:19.956921 [ANA_INIT] PLL <<<<<<<<
7126 13:08:19.959207 [ANA_INIT] MIDPI >>>>>>>>
7127 13:08:19.962768 [ANA_INIT] MIDPI <<<<<<<<
7128 13:08:19.963158 [ANA_INIT] DLL >>>>>>>>
7129 13:08:19.965949 [ANA_INIT] DLL <<<<<<<<
7130 13:08:19.969325 [ANA_INIT] flow end
7131 13:08:19.972595 ============ LP4 DIFF to SE enter ============
7132 13:08:19.976166 ============ LP4 DIFF to SE exit ============
7133 13:08:19.979124 [ANA_INIT] <<<<<<<<<<<<<
7134 13:08:19.983084 [Flow] Enable top DCM control >>>>>
7135 13:08:19.986188 [Flow] Enable top DCM control <<<<<
7136 13:08:19.989086 Enable DLL master slave shuffle
7137 13:08:19.992673 ==============================================================
7138 13:08:19.995678 Gating Mode config
7139 13:08:20.002578 ==============================================================
7140 13:08:20.002969 Config description:
7141 13:08:20.012532 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7142 13:08:20.019295 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7143 13:08:20.022506 SELPH_MODE 0: By rank 1: By Phase
7144 13:08:20.029015 ==============================================================
7145 13:08:20.032155 GAT_TRACK_EN = 1
7146 13:08:20.036164 RX_GATING_MODE = 2
7147 13:08:20.039609 RX_GATING_TRACK_MODE = 2
7148 13:08:20.042730 SELPH_MODE = 1
7149 13:08:20.045788 PICG_EARLY_EN = 1
7150 13:08:20.049432 VALID_LAT_VALUE = 1
7151 13:08:20.052722 ==============================================================
7152 13:08:20.056020 Enter into Gating configuration >>>>
7153 13:08:20.059481 Exit from Gating configuration <<<<
7154 13:08:20.062750 Enter into DVFS_PRE_config >>>>>
7155 13:08:20.072251 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7156 13:08:20.075756 Exit from DVFS_PRE_config <<<<<
7157 13:08:20.079246 Enter into PICG configuration >>>>
7158 13:08:20.082526 Exit from PICG configuration <<<<
7159 13:08:20.085806 [RX_INPUT] configuration >>>>>
7160 13:08:20.089001 [RX_INPUT] configuration <<<<<
7161 13:08:20.095988 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7162 13:08:20.099189 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7163 13:08:20.105865 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7164 13:08:20.112406 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7165 13:08:20.119072 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7166 13:08:20.125864 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7167 13:08:20.128865 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7168 13:08:20.132599 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7169 13:08:20.135740 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7170 13:08:20.142729 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7171 13:08:20.146001 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7172 13:08:20.148973 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7173 13:08:20.152250 ===================================
7174 13:08:20.155608 LPDDR4 DRAM CONFIGURATION
7175 13:08:20.158997 ===================================
7176 13:08:20.159572 EX_ROW_EN[0] = 0x0
7177 13:08:20.162388 EX_ROW_EN[1] = 0x0
7178 13:08:20.163007 LP4Y_EN = 0x0
7179 13:08:20.165804 WORK_FSP = 0x1
7180 13:08:20.168513 WL = 0x5
7181 13:08:20.168919 RL = 0x5
7182 13:08:20.171836 BL = 0x2
7183 13:08:20.172248 RPST = 0x0
7184 13:08:20.175712 RD_PRE = 0x0
7185 13:08:20.176104 WR_PRE = 0x1
7186 13:08:20.178730 WR_PST = 0x1
7187 13:08:20.179124 DBI_WR = 0x0
7188 13:08:20.181817 DBI_RD = 0x0
7189 13:08:20.182306 OTF = 0x1
7190 13:08:20.185204 ===================================
7191 13:08:20.188617 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7192 13:08:20.195641 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7193 13:08:20.199038 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7194 13:08:20.202317 ===================================
7195 13:08:20.206208 LPDDR4 DRAM CONFIGURATION
7196 13:08:20.208975 ===================================
7197 13:08:20.209476 EX_ROW_EN[0] = 0x10
7198 13:08:20.212057 EX_ROW_EN[1] = 0x0
7199 13:08:20.212449 LP4Y_EN = 0x0
7200 13:08:20.215288 WORK_FSP = 0x1
7201 13:08:20.215677 WL = 0x5
7202 13:08:20.218655 RL = 0x5
7203 13:08:20.219072 BL = 0x2
7204 13:08:20.221911 RPST = 0x0
7205 13:08:20.225038 RD_PRE = 0x0
7206 13:08:20.225426 WR_PRE = 0x1
7207 13:08:20.228947 WR_PST = 0x1
7208 13:08:20.229388 DBI_WR = 0x0
7209 13:08:20.231770 DBI_RD = 0x0
7210 13:08:20.232154 OTF = 0x1
7211 13:08:20.235020 ===================================
7212 13:08:20.241598 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7213 13:08:20.241983 ==
7214 13:08:20.245273 Dram Type= 6, Freq= 0, CH_0, rank 0
7215 13:08:20.248107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7216 13:08:20.248501 ==
7217 13:08:20.252232 [Duty_Offset_Calibration]
7218 13:08:20.255017 B0:2 B1:1 CA:1
7219 13:08:20.255401
7220 13:08:20.258169 [DutyScan_Calibration_Flow] k_type=0
7221 13:08:20.266580
7222 13:08:20.266963 ==CLK 0==
7223 13:08:20.270136 Final CLK duty delay cell = 0
7224 13:08:20.273362 [0] MAX Duty = 5156%(X100), DQS PI = 22
7225 13:08:20.276674 [0] MIN Duty = 4907%(X100), DQS PI = 0
7226 13:08:20.277066 [0] AVG Duty = 5031%(X100)
7227 13:08:20.277372
7228 13:08:20.280009 CH0 CLK Duty spec in!! Max-Min= 249%
7229 13:08:20.286631 [DutyScan_Calibration_Flow] ====Done====
7230 13:08:20.287127
7231 13:08:20.290283 [DutyScan_Calibration_Flow] k_type=1
7232 13:08:20.306221
7233 13:08:20.306659 ==DQS 0 ==
7234 13:08:20.308950 Final DQS duty delay cell = -4
7235 13:08:20.312372 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7236 13:08:20.315745 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7237 13:08:20.319153 [-4] AVG Duty = 4891%(X100)
7238 13:08:20.319548
7239 13:08:20.319851 ==DQS 1 ==
7240 13:08:20.322728 Final DQS duty delay cell = 0
7241 13:08:20.325813 [0] MAX Duty = 5187%(X100), DQS PI = 20
7242 13:08:20.329198 [0] MIN Duty = 5031%(X100), DQS PI = 52
7243 13:08:20.332562 [0] AVG Duty = 5109%(X100)
7244 13:08:20.333051
7245 13:08:20.335613 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7246 13:08:20.336007
7247 13:08:20.338876 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7248 13:08:20.342049 [DutyScan_Calibration_Flow] ====Done====
7249 13:08:20.342443
7250 13:08:20.345431 [DutyScan_Calibration_Flow] k_type=3
7251 13:08:20.363576
7252 13:08:20.364067 ==DQM 0 ==
7253 13:08:20.366785 Final DQM duty delay cell = 0
7254 13:08:20.370171 [0] MAX Duty = 5187%(X100), DQS PI = 32
7255 13:08:20.372908 [0] MIN Duty = 4875%(X100), DQS PI = 58
7256 13:08:20.376704 [0] AVG Duty = 5031%(X100)
7257 13:08:20.377097
7258 13:08:20.377402 ==DQM 1 ==
7259 13:08:20.379791 Final DQM duty delay cell = 0
7260 13:08:20.382912 [0] MAX Duty = 5187%(X100), DQS PI = 20
7261 13:08:20.386302 [0] MIN Duty = 5062%(X100), DQS PI = 14
7262 13:08:20.389760 [0] AVG Duty = 5124%(X100)
7263 13:08:20.390185
7264 13:08:20.392894 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7265 13:08:20.393278
7266 13:08:20.396197 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7267 13:08:20.399376 [DutyScan_Calibration_Flow] ====Done====
7268 13:08:20.399914
7269 13:08:20.402817 [DutyScan_Calibration_Flow] k_type=2
7270 13:08:20.420252
7271 13:08:20.420799 ==DQ 0 ==
7272 13:08:20.423596 Final DQ duty delay cell = 0
7273 13:08:20.426988 [0] MAX Duty = 5062%(X100), DQS PI = 26
7274 13:08:20.429937 [0] MIN Duty = 4907%(X100), DQS PI = 0
7275 13:08:20.430058 [0] AVG Duty = 4984%(X100)
7276 13:08:20.430142
7277 13:08:20.433415 ==DQ 1 ==
7278 13:08:20.436747 Final DQ duty delay cell = 0
7279 13:08:20.439882 [0] MAX Duty = 5093%(X100), DQS PI = 6
7280 13:08:20.443663 [0] MIN Duty = 4907%(X100), DQS PI = 34
7281 13:08:20.443729 [0] AVG Duty = 5000%(X100)
7282 13:08:20.443785
7283 13:08:20.446826 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7284 13:08:20.446888
7285 13:08:20.450357 CH0 DQ 1 Duty spec in!! Max-Min= 186%
7286 13:08:20.456998 [DutyScan_Calibration_Flow] ====Done====
7287 13:08:20.457068 ==
7288 13:08:20.460445 Dram Type= 6, Freq= 0, CH_1, rank 0
7289 13:08:20.463168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7290 13:08:20.463232 ==
7291 13:08:20.466443 [Duty_Offset_Calibration]
7292 13:08:20.466503 B0:1 B1:0 CA:0
7293 13:08:20.466559
7294 13:08:20.469755 [DutyScan_Calibration_Flow] k_type=0
7295 13:08:20.479422
7296 13:08:20.479486 ==CLK 0==
7297 13:08:20.482849 Final CLK duty delay cell = -4
7298 13:08:20.486161 [-4] MAX Duty = 4969%(X100), DQS PI = 20
7299 13:08:20.489585 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7300 13:08:20.492875 [-4] AVG Duty = 4906%(X100)
7301 13:08:20.492961
7302 13:08:20.496337 CH1 CLK Duty spec in!! Max-Min= 125%
7303 13:08:20.499047 [DutyScan_Calibration_Flow] ====Done====
7304 13:08:20.499133
7305 13:08:20.502403 [DutyScan_Calibration_Flow] k_type=1
7306 13:08:20.519534
7307 13:08:20.519631 ==DQS 0 ==
7308 13:08:20.522810 Final DQS duty delay cell = 0
7309 13:08:20.525875 [0] MAX Duty = 5094%(X100), DQS PI = 30
7310 13:08:20.529070 [0] MIN Duty = 4844%(X100), DQS PI = 48
7311 13:08:20.532680 [0] AVG Duty = 4969%(X100)
7312 13:08:20.532770
7313 13:08:20.532851 ==DQS 1 ==
7314 13:08:20.535878 Final DQS duty delay cell = 0
7315 13:08:20.539033 [0] MAX Duty = 5249%(X100), DQS PI = 16
7316 13:08:20.542358 [0] MIN Duty = 4938%(X100), DQS PI = 10
7317 13:08:20.545818 [0] AVG Duty = 5093%(X100)
7318 13:08:20.545931
7319 13:08:20.549195 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7320 13:08:20.549285
7321 13:08:20.552522 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7322 13:08:20.555853 [DutyScan_Calibration_Flow] ====Done====
7323 13:08:20.555942
7324 13:08:20.559248 [DutyScan_Calibration_Flow] k_type=3
7325 13:08:20.576378
7326 13:08:20.576471 ==DQM 0 ==
7327 13:08:20.579916 Final DQM duty delay cell = 0
7328 13:08:20.582669 [0] MAX Duty = 5187%(X100), DQS PI = 10
7329 13:08:20.586169 [0] MIN Duty = 4969%(X100), DQS PI = 48
7330 13:08:20.586253 [0] AVG Duty = 5078%(X100)
7331 13:08:20.589590
7332 13:08:20.589674 ==DQM 1 ==
7333 13:08:20.593051 Final DQM duty delay cell = 0
7334 13:08:20.596496 [0] MAX Duty = 5093%(X100), DQS PI = 40
7335 13:08:20.599903 [0] MIN Duty = 4907%(X100), DQS PI = 34
7336 13:08:20.599992 [0] AVG Duty = 5000%(X100)
7337 13:08:20.603270
7338 13:08:20.606558 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7339 13:08:20.606645
7340 13:08:20.609776 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7341 13:08:20.613083 [DutyScan_Calibration_Flow] ====Done====
7342 13:08:20.613175
7343 13:08:20.616585 [DutyScan_Calibration_Flow] k_type=2
7344 13:08:20.632654
7345 13:08:20.632747 ==DQ 0 ==
7346 13:08:20.636074 Final DQ duty delay cell = -4
7347 13:08:20.639491 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7348 13:08:20.642839 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7349 13:08:20.646186 [-4] AVG Duty = 4953%(X100)
7350 13:08:20.646251
7351 13:08:20.646308 ==DQ 1 ==
7352 13:08:20.649314 Final DQ duty delay cell = 0
7353 13:08:20.652918 [0] MAX Duty = 5124%(X100), DQS PI = 18
7354 13:08:20.655701 [0] MIN Duty = 4938%(X100), DQS PI = 10
7355 13:08:20.655766 [0] AVG Duty = 5031%(X100)
7356 13:08:20.659166
7357 13:08:20.662801 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7358 13:08:20.662882
7359 13:08:20.665921 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7360 13:08:20.669786 [DutyScan_Calibration_Flow] ====Done====
7361 13:08:20.672521 nWR fixed to 30
7362 13:08:20.672610 [ModeRegInit_LP4] CH0 RK0
7363 13:08:20.676197 [ModeRegInit_LP4] CH0 RK1
7364 13:08:20.679543 [ModeRegInit_LP4] CH1 RK0
7365 13:08:20.682622 [ModeRegInit_LP4] CH1 RK1
7366 13:08:20.682715 match AC timing 5
7367 13:08:20.686392 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7368 13:08:20.692619 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7369 13:08:20.695694 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7370 13:08:20.702553 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7371 13:08:20.706085 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7372 13:08:20.706205 [MiockJmeterHQA]
7373 13:08:20.706352
7374 13:08:20.708972 [DramcMiockJmeter] u1RxGatingPI = 0
7375 13:08:20.712412 0 : 4363, 4137
7376 13:08:20.712508 4 : 4255, 4029
7377 13:08:20.712594 8 : 4252, 4026
7378 13:08:20.715805 12 : 4253, 4027
7379 13:08:20.715896 16 : 4252, 4027
7380 13:08:20.719146 20 : 4253, 4027
7381 13:08:20.719238 24 : 4363, 4138
7382 13:08:20.722481 28 : 4363, 4138
7383 13:08:20.722569 32 : 4253, 4026
7384 13:08:20.725758 36 : 4252, 4027
7385 13:08:20.725847 40 : 4253, 4027
7386 13:08:20.729169 44 : 4363, 4137
7387 13:08:20.729231 48 : 4252, 4027
7388 13:08:20.729284 52 : 4362, 4137
7389 13:08:20.732523 56 : 4253, 4027
7390 13:08:20.732587 60 : 4252, 4026
7391 13:08:20.736045 64 : 4250, 4026
7392 13:08:20.736132 68 : 4252, 4030
7393 13:08:20.738625 72 : 4361, 4137
7394 13:08:20.738709 76 : 4250, 4027
7395 13:08:20.738766 80 : 4361, 4137
7396 13:08:20.742138 84 : 4250, 4026
7397 13:08:20.742199 88 : 4249, 66
7398 13:08:20.745627 92 : 4250, 0
7399 13:08:20.745721 96 : 4360, 0
7400 13:08:20.745804 100 : 4252, 0
7401 13:08:20.748938 104 : 4252, 0
7402 13:08:20.749026 108 : 4361, 0
7403 13:08:20.752503 112 : 4249, 0
7404 13:08:20.752588 116 : 4250, 0
7405 13:08:20.752670 120 : 4250, 0
7406 13:08:20.755893 124 : 4361, 0
7407 13:08:20.755979 128 : 4361, 0
7408 13:08:20.758734 132 : 4250, 0
7409 13:08:20.758816 136 : 4250, 0
7410 13:08:20.758875 140 : 4249, 0
7411 13:08:20.761904 144 : 4252, 0
7412 13:08:20.761987 148 : 4250, 0
7413 13:08:20.762087 152 : 4249, 0
7414 13:08:20.765193 156 : 4252, 0
7415 13:08:20.765277 160 : 4361, 0
7416 13:08:20.768570 164 : 4250, 0
7417 13:08:20.768654 168 : 4250, 0
7418 13:08:20.768734 172 : 4250, 0
7419 13:08:20.771995 176 : 4360, 0
7420 13:08:20.772080 180 : 4360, 0
7421 13:08:20.775247 184 : 4250, 0
7422 13:08:20.775330 188 : 4361, 0
7423 13:08:20.775411 192 : 4249, 0
7424 13:08:20.778782 196 : 4250, 0
7425 13:08:20.778842 200 : 4250, 0
7426 13:08:20.782140 204 : 4249, 1484
7427 13:08:20.782230 208 : 4250, 4011
7428 13:08:20.785441 212 : 4361, 4137
7429 13:08:20.785535 216 : 4250, 4027
7430 13:08:20.789019 220 : 4250, 4027
7431 13:08:20.789111 224 : 4361, 4138
7432 13:08:20.789174 228 : 4361, 4137
7433 13:08:20.792416 232 : 4250, 4027
7434 13:08:20.792503 236 : 4363, 4140
7435 13:08:20.795114 240 : 4361, 4137
7436 13:08:20.795202 244 : 4250, 4026
7437 13:08:20.798473 248 : 4250, 4027
7438 13:08:20.798535 252 : 4250, 4027
7439 13:08:20.801772 256 : 4249, 4027
7440 13:08:20.801857 260 : 4250, 4026
7441 13:08:20.805571 264 : 4250, 4027
7442 13:08:20.805662 268 : 4252, 4030
7443 13:08:20.808968 272 : 4249, 4027
7444 13:08:20.809059 276 : 4361, 4137
7445 13:08:20.812179 280 : 4361, 4137
7446 13:08:20.812270 284 : 4250, 4027
7447 13:08:20.812352 288 : 4363, 4140
7448 13:08:20.815451 292 : 4361, 4138
7449 13:08:20.815516 296 : 4250, 4026
7450 13:08:20.818708 300 : 4250, 4027
7451 13:08:20.818797 304 : 4252, 4030
7452 13:08:20.822082 308 : 4250, 3914
7453 13:08:20.822144 312 : 4250, 1837
7454 13:08:20.822197
7455 13:08:20.825436 MIOCK jitter meter ch=0
7456 13:08:20.825536
7457 13:08:20.828684 1T = (312-88) = 224 dly cells
7458 13:08:20.835374 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7459 13:08:20.835473 ==
7460 13:08:20.838292 Dram Type= 6, Freq= 0, CH_0, rank 0
7461 13:08:20.841873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7462 13:08:20.841966 ==
7463 13:08:20.845318 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7464 13:08:20.851860 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7465 13:08:20.855265 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7466 13:08:20.861731 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7467 13:08:20.870472 [CA 0] Center 43 (13~74) winsize 62
7468 13:08:20.873254 [CA 1] Center 43 (12~74) winsize 63
7469 13:08:20.877368 [CA 2] Center 38 (9~68) winsize 60
7470 13:08:20.880039 [CA 3] Center 38 (8~68) winsize 61
7471 13:08:20.883364 [CA 4] Center 36 (6~66) winsize 61
7472 13:08:20.886763 [CA 5] Center 35 (6~65) winsize 60
7473 13:08:20.886854
7474 13:08:20.889926 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7475 13:08:20.890019
7476 13:08:20.893443 [CATrainingPosCal] consider 1 rank data
7477 13:08:20.896848 u2DelayCellTimex100 = 290/100 ps
7478 13:08:20.900251 CA0 delay=43 (13~74),Diff = 8 PI (26 cell)
7479 13:08:20.906985 CA1 delay=43 (12~74),Diff = 8 PI (26 cell)
7480 13:08:20.910338 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7481 13:08:20.913687 CA3 delay=38 (8~68),Diff = 3 PI (10 cell)
7482 13:08:20.917146 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7483 13:08:20.920558 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7484 13:08:20.920647
7485 13:08:20.923216 CA PerBit enable=1, Macro0, CA PI delay=35
7486 13:08:20.923302
7487 13:08:20.926646 [CBTSetCACLKResult] CA Dly = 35
7488 13:08:20.929986 CS Dly: 9 (0~40)
7489 13:08:20.933452 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7490 13:08:20.936867 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7491 13:08:20.936956 ==
7492 13:08:20.940121 Dram Type= 6, Freq= 0, CH_0, rank 1
7493 13:08:20.943333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7494 13:08:20.943433 ==
7495 13:08:20.949852 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7496 13:08:20.953718 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7497 13:08:20.960032 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7498 13:08:20.963118 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7499 13:08:20.973587 [CA 0] Center 43 (13~73) winsize 61
7500 13:08:20.977039 [CA 1] Center 43 (13~73) winsize 61
7501 13:08:20.979993 [CA 2] Center 38 (8~68) winsize 61
7502 13:08:20.983628 [CA 3] Center 38 (8~68) winsize 61
7503 13:08:20.986967 [CA 4] Center 36 (6~66) winsize 61
7504 13:08:20.990261 [CA 5] Center 35 (6~65) winsize 60
7505 13:08:20.990335
7506 13:08:20.993750 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7507 13:08:20.993825
7508 13:08:20.996630 [CATrainingPosCal] consider 2 rank data
7509 13:08:21.000525 u2DelayCellTimex100 = 290/100 ps
7510 13:08:21.003360 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7511 13:08:21.009960 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7512 13:08:21.013406 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7513 13:08:21.016846 CA3 delay=38 (8~68),Diff = 3 PI (10 cell)
7514 13:08:21.020171 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7515 13:08:21.023622 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7516 13:08:21.023696
7517 13:08:21.026784 CA PerBit enable=1, Macro0, CA PI delay=35
7518 13:08:21.026859
7519 13:08:21.030249 [CBTSetCACLKResult] CA Dly = 35
7520 13:08:21.033582 CS Dly: 10 (0~42)
7521 13:08:21.037005 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7522 13:08:21.040567 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7523 13:08:21.040641
7524 13:08:21.043240 ----->DramcWriteLeveling(PI) begin...
7525 13:08:21.043316 ==
7526 13:08:21.046428 Dram Type= 6, Freq= 0, CH_0, rank 0
7527 13:08:21.053294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7528 13:08:21.053373 ==
7529 13:08:21.056475 Write leveling (Byte 0): 34 => 34
7530 13:08:21.056574 Write leveling (Byte 1): 26 => 26
7531 13:08:21.060108 DramcWriteLeveling(PI) end<-----
7532 13:08:21.060182
7533 13:08:21.060239 ==
7534 13:08:21.063542 Dram Type= 6, Freq= 0, CH_0, rank 0
7535 13:08:21.070190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 13:08:21.070266 ==
7537 13:08:21.073590 [Gating] SW mode calibration
7538 13:08:21.080255 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7539 13:08:21.083480 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7540 13:08:21.089913 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7541 13:08:21.093155 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7542 13:08:21.096510 1 4 8 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7543 13:08:21.102977 1 4 12 | B1->B0 | 2323 3a39 | 0 1 | (0 0) (0 0)
7544 13:08:21.106682 1 4 16 | B1->B0 | 2323 3838 | 0 0 | (0 0) (1 1)
7545 13:08:21.110238 1 4 20 | B1->B0 | 3434 3737 | 0 0 | (0 0) (1 1)
7546 13:08:21.113216 1 4 24 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 0)
7547 13:08:21.119955 1 4 28 | B1->B0 | 3434 3a3a | 1 1 | (1 1) (0 0)
7548 13:08:21.123269 1 5 0 | B1->B0 | 3434 3939 | 1 1 | (1 1) (1 1)
7549 13:08:21.126601 1 5 4 | B1->B0 | 3434 3939 | 1 1 | (1 1) (1 1)
7550 13:08:21.133078 1 5 8 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 0)
7551 13:08:21.136599 1 5 12 | B1->B0 | 3434 2c2b | 1 1 | (1 1) (1 0)
7552 13:08:21.139945 1 5 16 | B1->B0 | 3434 2c2b | 0 1 | (0 0) (1 0)
7553 13:08:21.146807 1 5 20 | B1->B0 | 2626 2929 | 0 0 | (0 0) (0 0)
7554 13:08:21.150261 1 5 24 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7555 13:08:21.153427 1 5 28 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (1 1)
7556 13:08:21.160107 1 6 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
7557 13:08:21.163200 1 6 4 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7558 13:08:21.166426 1 6 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7559 13:08:21.173071 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7560 13:08:21.176471 1 6 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
7561 13:08:21.179849 1 6 20 | B1->B0 | 4545 4645 | 0 1 | (0 0) (0 0)
7562 13:08:21.186526 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7563 13:08:21.189984 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7564 13:08:21.193256 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 13:08:21.199920 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 13:08:21.203234 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 13:08:21.206722 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7568 13:08:21.213291 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7569 13:08:21.216018 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7570 13:08:21.220050 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 13:08:21.222842 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 13:08:21.229843 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 13:08:21.232911 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 13:08:21.236169 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 13:08:21.242990 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 13:08:21.246454 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 13:08:21.249997 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 13:08:21.256563 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 13:08:21.259845 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 13:08:21.263154 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 13:08:21.269943 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 13:08:21.273039 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 13:08:21.276311 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7584 13:08:21.283024 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7585 13:08:21.283100 Total UI for P1: 0, mck2ui 16
7586 13:08:21.289775 best dqsien dly found for B0: ( 1, 9, 12)
7587 13:08:21.293194 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7588 13:08:21.296641 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 13:08:21.299490 Total UI for P1: 0, mck2ui 16
7590 13:08:21.302619 best dqsien dly found for B1: ( 1, 9, 20)
7591 13:08:21.306445 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7592 13:08:21.309290 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7593 13:08:21.309365
7594 13:08:21.316134 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7595 13:08:21.319422 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7596 13:08:21.322801 [Gating] SW calibration Done
7597 13:08:21.322876 ==
7598 13:08:21.326148 Dram Type= 6, Freq= 0, CH_0, rank 0
7599 13:08:21.329453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7600 13:08:21.329527 ==
7601 13:08:21.329585 RX Vref Scan: 0
7602 13:08:21.329638
7603 13:08:21.332911 RX Vref 0 -> 0, step: 1
7604 13:08:21.332985
7605 13:08:21.335695 RX Delay 0 -> 252, step: 8
7606 13:08:21.339704 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7607 13:08:21.342272 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7608 13:08:21.345681 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7609 13:08:21.352517 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7610 13:08:21.355884 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7611 13:08:21.359317 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7612 13:08:21.362503 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7613 13:08:21.365529 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7614 13:08:21.372069 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7615 13:08:21.375551 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7616 13:08:21.379384 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7617 13:08:21.382331 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7618 13:08:21.385774 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7619 13:08:21.391976 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7620 13:08:21.395710 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7621 13:08:21.399177 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7622 13:08:21.399270 ==
7623 13:08:21.401902 Dram Type= 6, Freq= 0, CH_0, rank 0
7624 13:08:21.405289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 13:08:21.408757 ==
7626 13:08:21.408854 DQS Delay:
7627 13:08:21.408938 DQS0 = 0, DQS1 = 0
7628 13:08:21.412260 DQM Delay:
7629 13:08:21.412356 DQM0 = 137, DQM1 = 129
7630 13:08:21.415553 DQ Delay:
7631 13:08:21.418670 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135
7632 13:08:21.422150 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7633 13:08:21.425556 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7634 13:08:21.428723 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7635 13:08:21.428813
7636 13:08:21.428908
7637 13:08:21.428990 ==
7638 13:08:21.432002 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 13:08:21.435467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 13:08:21.435568 ==
7641 13:08:21.435652
7642 13:08:21.438699
7643 13:08:21.438794 TX Vref Scan disable
7644 13:08:21.442286 == TX Byte 0 ==
7645 13:08:21.445588 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7646 13:08:21.448754 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7647 13:08:21.451916 == TX Byte 1 ==
7648 13:08:21.455350 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7649 13:08:21.458641 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7650 13:08:21.458735 ==
7651 13:08:21.462035 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 13:08:21.468847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 13:08:21.468924 ==
7654 13:08:21.480873
7655 13:08:21.484541 TX Vref early break, caculate TX vref
7656 13:08:21.487570 TX Vref=16, minBit 0, minWin=23, winSum=382
7657 13:08:21.490583 TX Vref=18, minBit 7, minWin=23, winSum=388
7658 13:08:21.494185 TX Vref=20, minBit 4, minWin=24, winSum=403
7659 13:08:21.497929 TX Vref=22, minBit 0, minWin=25, winSum=409
7660 13:08:21.501151 TX Vref=24, minBit 0, minWin=25, winSum=422
7661 13:08:21.507641 TX Vref=26, minBit 6, minWin=25, winSum=425
7662 13:08:21.511251 TX Vref=28, minBit 6, minWin=25, winSum=424
7663 13:08:21.514479 TX Vref=30, minBit 1, minWin=25, winSum=414
7664 13:08:21.517141 TX Vref=32, minBit 0, minWin=24, winSum=404
7665 13:08:21.520653 TX Vref=34, minBit 1, minWin=23, winSum=392
7666 13:08:21.527400 [TxChooseVref] Worse bit 6, Min win 25, Win sum 425, Final Vref 26
7667 13:08:21.527490
7668 13:08:21.530683 Final TX Range 0 Vref 26
7669 13:08:21.530774
7670 13:08:21.530858 ==
7671 13:08:21.534272 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 13:08:21.537363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 13:08:21.537457 ==
7674 13:08:21.537541
7675 13:08:21.537621
7676 13:08:21.540927 TX Vref Scan disable
7677 13:08:21.547313 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7678 13:08:21.547403 == TX Byte 0 ==
7679 13:08:21.550573 u2DelayCellOfst[0]=10 cells (3 PI)
7680 13:08:21.553893 u2DelayCellOfst[1]=13 cells (4 PI)
7681 13:08:21.557771 u2DelayCellOfst[2]=10 cells (3 PI)
7682 13:08:21.560735 u2DelayCellOfst[3]=10 cells (3 PI)
7683 13:08:21.564049 u2DelayCellOfst[4]=6 cells (2 PI)
7684 13:08:21.567507 u2DelayCellOfst[5]=0 cells (0 PI)
7685 13:08:21.567602 u2DelayCellOfst[6]=16 cells (5 PI)
7686 13:08:21.571144 u2DelayCellOfst[7]=16 cells (5 PI)
7687 13:08:21.577870 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7688 13:08:21.580571 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7689 13:08:21.580637 == TX Byte 1 ==
7690 13:08:21.584119 u2DelayCellOfst[8]=3 cells (1 PI)
7691 13:08:21.587585 u2DelayCellOfst[9]=0 cells (0 PI)
7692 13:08:21.590855 u2DelayCellOfst[10]=6 cells (2 PI)
7693 13:08:21.594116 u2DelayCellOfst[11]=3 cells (1 PI)
7694 13:08:21.597233 u2DelayCellOfst[12]=10 cells (3 PI)
7695 13:08:21.600491 u2DelayCellOfst[13]=10 cells (3 PI)
7696 13:08:21.604396 u2DelayCellOfst[14]=13 cells (4 PI)
7697 13:08:21.607218 u2DelayCellOfst[15]=10 cells (3 PI)
7698 13:08:21.611074 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7699 13:08:21.617333 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7700 13:08:21.617419 DramC Write-DBI on
7701 13:08:21.617485 ==
7702 13:08:21.620585 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 13:08:21.624644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 13:08:21.625027 ==
7705 13:08:21.627511
7706 13:08:21.627905
7707 13:08:21.628204 TX Vref Scan disable
7708 13:08:21.630744 == TX Byte 0 ==
7709 13:08:21.633949 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7710 13:08:21.637459 == TX Byte 1 ==
7711 13:08:21.640711 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7712 13:08:21.644113 DramC Write-DBI off
7713 13:08:21.644492
7714 13:08:21.644782 [DATLAT]
7715 13:08:21.645052 Freq=1600, CH0 RK0
7716 13:08:21.645313
7717 13:08:21.647555 DATLAT Default: 0xf
7718 13:08:21.647936 0, 0xFFFF, sum = 0
7719 13:08:21.650586 1, 0xFFFF, sum = 0
7720 13:08:21.650971 2, 0xFFFF, sum = 0
7721 13:08:21.654201 3, 0xFFFF, sum = 0
7722 13:08:21.657780 4, 0xFFFF, sum = 0
7723 13:08:21.658222 5, 0xFFFF, sum = 0
7724 13:08:21.660967 6, 0xFFFF, sum = 0
7725 13:08:21.661354 7, 0xFFFF, sum = 0
7726 13:08:21.664266 8, 0xFFFF, sum = 0
7727 13:08:21.664654 9, 0xFFFF, sum = 0
7728 13:08:21.667569 10, 0xFFFF, sum = 0
7729 13:08:21.667959 11, 0xFFFF, sum = 0
7730 13:08:21.670673 12, 0xFFFF, sum = 0
7731 13:08:21.671064 13, 0xFFFF, sum = 0
7732 13:08:21.674177 14, 0x0, sum = 1
7733 13:08:21.674574 15, 0x0, sum = 2
7734 13:08:21.677461 16, 0x0, sum = 3
7735 13:08:21.677996 17, 0x0, sum = 4
7736 13:08:21.680841 best_step = 15
7737 13:08:21.681346
7738 13:08:21.681759 ==
7739 13:08:21.684296 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 13:08:21.687767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 13:08:21.688156 ==
7742 13:08:21.688458 RX Vref Scan: 1
7743 13:08:21.691102
7744 13:08:21.691486 Set Vref Range= 24 -> 127
7745 13:08:21.691789
7746 13:08:21.693695 RX Vref 24 -> 127, step: 1
7747 13:08:21.694106
7748 13:08:21.697067 RX Delay 19 -> 252, step: 4
7749 13:08:21.697450
7750 13:08:21.700545 Set Vref, RX VrefLevel [Byte0]: 24
7751 13:08:21.703881 [Byte1]: 24
7752 13:08:21.704264
7753 13:08:21.707222 Set Vref, RX VrefLevel [Byte0]: 25
7754 13:08:21.710556 [Byte1]: 25
7755 13:08:21.710950
7756 13:08:21.713888 Set Vref, RX VrefLevel [Byte0]: 26
7757 13:08:21.717487 [Byte1]: 26
7758 13:08:21.721158
7759 13:08:21.721629 Set Vref, RX VrefLevel [Byte0]: 27
7760 13:08:21.724213 [Byte1]: 27
7761 13:08:21.728884
7762 13:08:21.729335 Set Vref, RX VrefLevel [Byte0]: 28
7763 13:08:21.732057 [Byte1]: 28
7764 13:08:21.736297
7765 13:08:21.736685 Set Vref, RX VrefLevel [Byte0]: 29
7766 13:08:21.739364 [Byte1]: 29
7767 13:08:21.744185
7768 13:08:21.744637 Set Vref, RX VrefLevel [Byte0]: 30
7769 13:08:21.747647 [Byte1]: 30
7770 13:08:21.751485
7771 13:08:21.751940 Set Vref, RX VrefLevel [Byte0]: 31
7772 13:08:21.754917 [Byte1]: 31
7773 13:08:21.758808
7774 13:08:21.759203 Set Vref, RX VrefLevel [Byte0]: 32
7775 13:08:21.762065 [Byte1]: 32
7776 13:08:21.766375
7777 13:08:21.766787 Set Vref, RX VrefLevel [Byte0]: 33
7778 13:08:21.769665 [Byte1]: 33
7779 13:08:21.774366
7780 13:08:21.774751 Set Vref, RX VrefLevel [Byte0]: 34
7781 13:08:21.777724 [Byte1]: 34
7782 13:08:21.781582
7783 13:08:21.781976 Set Vref, RX VrefLevel [Byte0]: 35
7784 13:08:21.784805 [Byte1]: 35
7785 13:08:21.789541
7786 13:08:21.789930 Set Vref, RX VrefLevel [Byte0]: 36
7787 13:08:21.793257 [Byte1]: 36
7788 13:08:21.797104
7789 13:08:21.797490 Set Vref, RX VrefLevel [Byte0]: 37
7790 13:08:21.800563 [Byte1]: 37
7791 13:08:21.804667
7792 13:08:21.805061 Set Vref, RX VrefLevel [Byte0]: 38
7793 13:08:21.808000 [Byte1]: 38
7794 13:08:21.812151
7795 13:08:21.812542 Set Vref, RX VrefLevel [Byte0]: 39
7796 13:08:21.815761 [Byte1]: 39
7797 13:08:21.819521
7798 13:08:21.819910 Set Vref, RX VrefLevel [Byte0]: 40
7799 13:08:21.822895 [Byte1]: 40
7800 13:08:21.827485
7801 13:08:21.827868 Set Vref, RX VrefLevel [Byte0]: 41
7802 13:08:21.830591 [Byte1]: 41
7803 13:08:21.834579
7804 13:08:21.834963 Set Vref, RX VrefLevel [Byte0]: 42
7805 13:08:21.837762 [Byte1]: 42
7806 13:08:21.842227
7807 13:08:21.842628 Set Vref, RX VrefLevel [Byte0]: 43
7808 13:08:21.845470 [Byte1]: 43
7809 13:08:21.849947
7810 13:08:21.850382 Set Vref, RX VrefLevel [Byte0]: 44
7811 13:08:21.852923 [Byte1]: 44
7812 13:08:21.857398
7813 13:08:21.857790 Set Vref, RX VrefLevel [Byte0]: 45
7814 13:08:21.860651 [Byte1]: 45
7815 13:08:21.865447
7816 13:08:21.865834 Set Vref, RX VrefLevel [Byte0]: 46
7817 13:08:21.868232 [Byte1]: 46
7818 13:08:21.872371
7819 13:08:21.872864 Set Vref, RX VrefLevel [Byte0]: 47
7820 13:08:21.876030 [Byte1]: 47
7821 13:08:21.880291
7822 13:08:21.880784 Set Vref, RX VrefLevel [Byte0]: 48
7823 13:08:21.883046 [Byte1]: 48
7824 13:08:21.887958
7825 13:08:21.888343 Set Vref, RX VrefLevel [Byte0]: 49
7826 13:08:21.891207 [Byte1]: 49
7827 13:08:21.895793
7828 13:08:21.896180 Set Vref, RX VrefLevel [Byte0]: 50
7829 13:08:21.898850 [Byte1]: 50
7830 13:08:21.903296
7831 13:08:21.903732 Set Vref, RX VrefLevel [Byte0]: 51
7832 13:08:21.905987 [Byte1]: 51
7833 13:08:21.910830
7834 13:08:21.911282 Set Vref, RX VrefLevel [Byte0]: 52
7835 13:08:21.913452 [Byte1]: 52
7836 13:08:21.918100
7837 13:08:21.918516 Set Vref, RX VrefLevel [Byte0]: 53
7838 13:08:21.921183 [Byte1]: 53
7839 13:08:21.925430
7840 13:08:21.925819 Set Vref, RX VrefLevel [Byte0]: 54
7841 13:08:21.928761 [Byte1]: 54
7842 13:08:21.932881
7843 13:08:21.933268 Set Vref, RX VrefLevel [Byte0]: 55
7844 13:08:21.936244 [Byte1]: 55
7845 13:08:21.940481
7846 13:08:21.940868 Set Vref, RX VrefLevel [Byte0]: 56
7847 13:08:21.944674 [Byte1]: 56
7848 13:08:21.948271
7849 13:08:21.948726 Set Vref, RX VrefLevel [Byte0]: 57
7850 13:08:21.951659 [Byte1]: 57
7851 13:08:21.956138
7852 13:08:21.956574 Set Vref, RX VrefLevel [Byte0]: 58
7853 13:08:21.959582 [Byte1]: 58
7854 13:08:21.963292
7855 13:08:21.963684 Set Vref, RX VrefLevel [Byte0]: 59
7856 13:08:21.966395 [Byte1]: 59
7857 13:08:21.971200
7858 13:08:21.971588 Set Vref, RX VrefLevel [Byte0]: 60
7859 13:08:21.974227 [Byte1]: 60
7860 13:08:21.979064
7861 13:08:21.979451 Set Vref, RX VrefLevel [Byte0]: 61
7862 13:08:21.981741 [Byte1]: 61
7863 13:08:21.986259
7864 13:08:21.986653 Set Vref, RX VrefLevel [Byte0]: 62
7865 13:08:21.989370 [Byte1]: 62
7866 13:08:21.993682
7867 13:08:21.993973 Set Vref, RX VrefLevel [Byte0]: 63
7868 13:08:21.996933 [Byte1]: 63
7869 13:08:22.001127
7870 13:08:22.001398 Set Vref, RX VrefLevel [Byte0]: 64
7871 13:08:22.004348 [Byte1]: 64
7872 13:08:22.008609
7873 13:08:22.008883 Set Vref, RX VrefLevel [Byte0]: 65
7874 13:08:22.011888 [Byte1]: 65
7875 13:08:22.016112
7876 13:08:22.016382 Set Vref, RX VrefLevel [Byte0]: 66
7877 13:08:22.019515 [Byte1]: 66
7878 13:08:22.024391
7879 13:08:22.024820 Set Vref, RX VrefLevel [Byte0]: 67
7880 13:08:22.027542 [Byte1]: 67
7881 13:08:22.031758
7882 13:08:22.032136 Set Vref, RX VrefLevel [Byte0]: 68
7883 13:08:22.035201 [Byte1]: 68
7884 13:08:22.039322
7885 13:08:22.039700 Set Vref, RX VrefLevel [Byte0]: 69
7886 13:08:22.042637 [Byte1]: 69
7887 13:08:22.046703
7888 13:08:22.047083 Set Vref, RX VrefLevel [Byte0]: 70
7889 13:08:22.049667 [Byte1]: 70
7890 13:08:22.054535
7891 13:08:22.054960 Set Vref, RX VrefLevel [Byte0]: 71
7892 13:08:22.057904 [Byte1]: 71
7893 13:08:22.061825
7894 13:08:22.062250 Set Vref, RX VrefLevel [Byte0]: 72
7895 13:08:22.064970 [Byte1]: 72
7896 13:08:22.069429
7897 13:08:22.069827 Set Vref, RX VrefLevel [Byte0]: 73
7898 13:08:22.072626 [Byte1]: 73
7899 13:08:22.077644
7900 13:08:22.078192 Set Vref, RX VrefLevel [Byte0]: 74
7901 13:08:22.080796 [Byte1]: 74
7902 13:08:22.084740
7903 13:08:22.085124 Set Vref, RX VrefLevel [Byte0]: 75
7904 13:08:22.088247 [Byte1]: 75
7905 13:08:22.092262
7906 13:08:22.092646 Final RX Vref Byte 0 = 53 to rank0
7907 13:08:22.095234 Final RX Vref Byte 1 = 60 to rank0
7908 13:08:22.098490 Final RX Vref Byte 0 = 53 to rank1
7909 13:08:22.102122 Final RX Vref Byte 1 = 60 to rank1==
7910 13:08:22.105408 Dram Type= 6, Freq= 0, CH_0, rank 0
7911 13:08:22.111991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7912 13:08:22.112424 ==
7913 13:08:22.112727 DQS Delay:
7914 13:08:22.113005 DQS0 = 0, DQS1 = 0
7915 13:08:22.115790 DQM Delay:
7916 13:08:22.116389 DQM0 = 133, DQM1 = 127
7917 13:08:22.118840 DQ Delay:
7918 13:08:22.122238 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7919 13:08:22.125270 DQ4 =132, DQ5 =122, DQ6 =142, DQ7 =138
7920 13:08:22.128882 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7921 13:08:22.131880 DQ12 =130, DQ13 =134, DQ14 =138, DQ15 =134
7922 13:08:22.132273
7923 13:08:22.132575
7924 13:08:22.132851
7925 13:08:22.135214 [DramC_TX_OE_Calibration] TA2
7926 13:08:22.138458 Original DQ_B0 (3 6) =30, OEN = 27
7927 13:08:22.141720 Original DQ_B1 (3 6) =30, OEN = 27
7928 13:08:22.144964 24, 0x0, End_B0=24 End_B1=24
7929 13:08:22.145046 25, 0x0, End_B0=25 End_B1=25
7930 13:08:22.148474 26, 0x0, End_B0=26 End_B1=26
7931 13:08:22.151723 27, 0x0, End_B0=27 End_B1=27
7932 13:08:22.154722 28, 0x0, End_B0=28 End_B1=28
7933 13:08:22.158051 29, 0x0, End_B0=29 End_B1=29
7934 13:08:22.158128 30, 0x0, End_B0=30 End_B1=30
7935 13:08:22.161511 31, 0x4141, End_B0=30 End_B1=30
7936 13:08:22.164694 Byte0 end_step=30 best_step=27
7937 13:08:22.168046 Byte1 end_step=30 best_step=27
7938 13:08:22.171255 Byte0 TX OE(2T, 0.5T) = (3, 3)
7939 13:08:22.174953 Byte1 TX OE(2T, 0.5T) = (3, 3)
7940 13:08:22.175029
7941 13:08:22.175087
7942 13:08:22.181162 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a25, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
7943 13:08:22.184992 CH0 RK0: MR19=303, MR18=2A25
7944 13:08:22.191088 CH0_RK0: MR19=0x303, MR18=0x2A25, DQSOSC=388, MR23=63, INC=24, DEC=16
7945 13:08:22.191163
7946 13:08:22.194765 ----->DramcWriteLeveling(PI) begin...
7947 13:08:22.194833 ==
7948 13:08:22.198250 Dram Type= 6, Freq= 0, CH_0, rank 1
7949 13:08:22.201078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7950 13:08:22.201173 ==
7951 13:08:22.204864 Write leveling (Byte 0): 37 => 37
7952 13:08:22.207979 Write leveling (Byte 1): 29 => 29
7953 13:08:22.211473 DramcWriteLeveling(PI) end<-----
7954 13:08:22.211549
7955 13:08:22.211606 ==
7956 13:08:22.214802 Dram Type= 6, Freq= 0, CH_0, rank 1
7957 13:08:22.218109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7958 13:08:22.218185 ==
7959 13:08:22.221552 [Gating] SW mode calibration
7960 13:08:22.227622 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7961 13:08:22.234695 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7962 13:08:22.237915 1 4 0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7963 13:08:22.241275 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7964 13:08:22.248096 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7965 13:08:22.250954 1 4 12 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
7966 13:08:22.254303 1 4 16 | B1->B0 | 3333 3736 | 1 1 | (0 0) (1 1)
7967 13:08:22.261540 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7968 13:08:22.264733 1 4 24 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
7969 13:08:22.267988 1 4 28 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7970 13:08:22.274795 1 5 0 | B1->B0 | 3434 3737 | 1 1 | (1 1) (0 0)
7971 13:08:22.277610 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7972 13:08:22.281065 1 5 8 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
7973 13:08:22.287913 1 5 12 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
7974 13:08:22.291020 1 5 16 | B1->B0 | 2d2d 2d2c | 1 1 | (1 1) (0 0)
7975 13:08:22.294220 1 5 20 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7976 13:08:22.300977 1 5 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7977 13:08:22.304267 1 5 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7978 13:08:22.307680 1 6 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7979 13:08:22.314186 1 6 4 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7980 13:08:22.317763 1 6 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7981 13:08:22.321127 1 6 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7982 13:08:22.324637 1 6 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
7983 13:08:22.331455 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7984 13:08:22.334816 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7985 13:08:22.337849 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7986 13:08:22.344525 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 13:08:22.347740 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7988 13:08:22.350962 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 13:08:22.357369 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7990 13:08:22.360753 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7991 13:08:22.364152 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 13:08:22.370768 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 13:08:22.374227 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 13:08:22.377615 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 13:08:22.384337 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 13:08:22.387680 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 13:08:22.390442 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 13:08:22.397433 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 13:08:22.400611 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 13:08:22.403789 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 13:08:22.410998 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 13:08:22.413705 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 13:08:22.417158 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 13:08:22.423800 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8005 13:08:22.427566 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8006 13:08:22.430433 Total UI for P1: 0, mck2ui 16
8007 13:08:22.433920 best dqsien dly found for B0: ( 1, 9, 8)
8008 13:08:22.437326 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8009 13:08:22.443770 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8010 13:08:22.443847 Total UI for P1: 0, mck2ui 16
8011 13:08:22.447192 best dqsien dly found for B1: ( 1, 9, 12)
8012 13:08:22.454019 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8013 13:08:22.457277 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8014 13:08:22.457353
8015 13:08:22.460459 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8016 13:08:22.464343 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8017 13:08:22.467380 [Gating] SW calibration Done
8018 13:08:22.467457 ==
8019 13:08:22.470429 Dram Type= 6, Freq= 0, CH_0, rank 1
8020 13:08:22.473709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8021 13:08:22.473809 ==
8022 13:08:22.477490 RX Vref Scan: 0
8023 13:08:22.477580
8024 13:08:22.477638 RX Vref 0 -> 0, step: 1
8025 13:08:22.477693
8026 13:08:22.480718 RX Delay 0 -> 252, step: 8
8027 13:08:22.483613 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8028 13:08:22.487084 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8029 13:08:22.494102 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8030 13:08:22.497357 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8031 13:08:22.500642 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8032 13:08:22.503857 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8033 13:08:22.507216 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8034 13:08:22.513702 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8035 13:08:22.516998 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8036 13:08:22.520414 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8037 13:08:22.523744 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8038 13:08:22.527173 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8039 13:08:22.534110 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8040 13:08:22.537306 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8041 13:08:22.540638 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8042 13:08:22.543701 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8043 13:08:22.543771 ==
8044 13:08:22.547227 Dram Type= 6, Freq= 0, CH_0, rank 1
8045 13:08:22.553518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8046 13:08:22.553588 ==
8047 13:08:22.553655 DQS Delay:
8048 13:08:22.557181 DQS0 = 0, DQS1 = 0
8049 13:08:22.557249 DQM Delay:
8050 13:08:22.557313 DQM0 = 136, DQM1 = 128
8051 13:08:22.560557 DQ Delay:
8052 13:08:22.563603 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8053 13:08:22.566751 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8054 13:08:22.569947 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8055 13:08:22.573504 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8056 13:08:22.573576
8057 13:08:22.573633
8058 13:08:22.573687 ==
8059 13:08:22.576660 Dram Type= 6, Freq= 0, CH_0, rank 1
8060 13:08:22.583332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8061 13:08:22.583403 ==
8062 13:08:22.583461
8063 13:08:22.583514
8064 13:08:22.583564 TX Vref Scan disable
8065 13:08:22.586966 == TX Byte 0 ==
8066 13:08:22.590242 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8067 13:08:22.593653 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8068 13:08:22.597134 == TX Byte 1 ==
8069 13:08:22.600594 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8070 13:08:22.603832 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8071 13:08:22.607083 ==
8072 13:08:22.610497 Dram Type= 6, Freq= 0, CH_0, rank 1
8073 13:08:22.613774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8074 13:08:22.613850 ==
8075 13:08:22.626269
8076 13:08:22.630185 TX Vref early break, caculate TX vref
8077 13:08:22.632950 TX Vref=16, minBit 4, minWin=22, winSum=387
8078 13:08:22.636381 TX Vref=18, minBit 1, minWin=23, winSum=393
8079 13:08:22.639779 TX Vref=20, minBit 1, minWin=23, winSum=404
8080 13:08:22.643137 TX Vref=22, minBit 0, minWin=24, winSum=411
8081 13:08:22.646591 TX Vref=24, minBit 0, minWin=25, winSum=420
8082 13:08:22.653361 TX Vref=26, minBit 3, minWin=25, winSum=423
8083 13:08:22.656505 TX Vref=28, minBit 4, minWin=25, winSum=423
8084 13:08:22.659994 TX Vref=30, minBit 1, minWin=25, winSum=418
8085 13:08:22.662783 TX Vref=32, minBit 0, minWin=25, winSum=409
8086 13:08:22.666071 TX Vref=34, minBit 0, minWin=24, winSum=398
8087 13:08:22.672920 [TxChooseVref] Worse bit 3, Min win 25, Win sum 423, Final Vref 26
8088 13:08:22.672995
8089 13:08:22.676458 Final TX Range 0 Vref 26
8090 13:08:22.676527
8091 13:08:22.676592 ==
8092 13:08:22.679837 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 13:08:22.682655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 13:08:22.682721 ==
8095 13:08:22.682776
8096 13:08:22.682829
8097 13:08:22.685901 TX Vref Scan disable
8098 13:08:22.693154 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8099 13:08:22.693224 == TX Byte 0 ==
8100 13:08:22.696160 u2DelayCellOfst[0]=13 cells (4 PI)
8101 13:08:22.699547 u2DelayCellOfst[1]=16 cells (5 PI)
8102 13:08:22.702653 u2DelayCellOfst[2]=10 cells (3 PI)
8103 13:08:22.705920 u2DelayCellOfst[3]=10 cells (3 PI)
8104 13:08:22.709239 u2DelayCellOfst[4]=10 cells (3 PI)
8105 13:08:22.712684 u2DelayCellOfst[5]=0 cells (0 PI)
8106 13:08:22.716097 u2DelayCellOfst[6]=16 cells (5 PI)
8107 13:08:22.719352 u2DelayCellOfst[7]=16 cells (5 PI)
8108 13:08:22.722619 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8109 13:08:22.726160 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8110 13:08:22.729400 == TX Byte 1 ==
8111 13:08:22.729474 u2DelayCellOfst[8]=0 cells (0 PI)
8112 13:08:22.732718 u2DelayCellOfst[9]=0 cells (0 PI)
8113 13:08:22.736100 u2DelayCellOfst[10]=6 cells (2 PI)
8114 13:08:22.739457 u2DelayCellOfst[11]=3 cells (1 PI)
8115 13:08:22.742174 u2DelayCellOfst[12]=10 cells (3 PI)
8116 13:08:22.745623 u2DelayCellOfst[13]=10 cells (3 PI)
8117 13:08:22.749087 u2DelayCellOfst[14]=13 cells (4 PI)
8118 13:08:22.752458 u2DelayCellOfst[15]=10 cells (3 PI)
8119 13:08:22.755819 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8120 13:08:22.762252 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8121 13:08:22.762360 DramC Write-DBI on
8122 13:08:22.762436 ==
8123 13:08:22.766277 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 13:08:22.772175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 13:08:22.772253 ==
8126 13:08:22.772335
8127 13:08:22.772406
8128 13:08:22.772476 TX Vref Scan disable
8129 13:08:22.775907 == TX Byte 0 ==
8130 13:08:22.779514 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8131 13:08:22.782718 == TX Byte 1 ==
8132 13:08:22.785910 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8133 13:08:22.789304 DramC Write-DBI off
8134 13:08:22.789380
8135 13:08:22.789456 [DATLAT]
8136 13:08:22.789526 Freq=1600, CH0 RK1
8137 13:08:22.789595
8138 13:08:22.792974 DATLAT Default: 0xf
8139 13:08:22.793050 0, 0xFFFF, sum = 0
8140 13:08:22.795890 1, 0xFFFF, sum = 0
8141 13:08:22.799467 2, 0xFFFF, sum = 0
8142 13:08:22.799546 3, 0xFFFF, sum = 0
8143 13:08:22.802487 4, 0xFFFF, sum = 0
8144 13:08:22.802577 5, 0xFFFF, sum = 0
8145 13:08:22.806182 6, 0xFFFF, sum = 0
8146 13:08:22.806259 7, 0xFFFF, sum = 0
8147 13:08:22.809470 8, 0xFFFF, sum = 0
8148 13:08:22.809548 9, 0xFFFF, sum = 0
8149 13:08:22.812615 10, 0xFFFF, sum = 0
8150 13:08:22.812693 11, 0xFFFF, sum = 0
8151 13:08:22.816210 12, 0xFFFF, sum = 0
8152 13:08:22.816288 13, 0xFFFF, sum = 0
8153 13:08:22.818993 14, 0x0, sum = 1
8154 13:08:22.819076 15, 0x0, sum = 2
8155 13:08:22.822732 16, 0x0, sum = 3
8156 13:08:22.822810 17, 0x0, sum = 4
8157 13:08:22.825818 best_step = 15
8158 13:08:22.825919
8159 13:08:22.826049 ==
8160 13:08:22.829376 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 13:08:22.832448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 13:08:22.832553 ==
8163 13:08:22.835756 RX Vref Scan: 0
8164 13:08:22.835855
8165 13:08:22.835949 RX Vref 0 -> 0, step: 1
8166 13:08:22.836038
8167 13:08:22.839134 RX Delay 19 -> 252, step: 4
8168 13:08:22.842466 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8169 13:08:22.848902 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8170 13:08:22.852432 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8171 13:08:22.855759 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8172 13:08:22.859161 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8173 13:08:22.862559 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8174 13:08:22.869502 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8175 13:08:22.872186 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8176 13:08:22.875658 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8177 13:08:22.878900 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8178 13:08:22.882138 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8179 13:08:22.889034 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8180 13:08:22.892238 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8181 13:08:22.895608 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8182 13:08:22.899053 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8183 13:08:22.902439 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8184 13:08:22.905679 ==
8185 13:08:22.905752 Dram Type= 6, Freq= 0, CH_0, rank 1
8186 13:08:22.912350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8187 13:08:22.912426 ==
8188 13:08:22.912483 DQS Delay:
8189 13:08:22.915932 DQS0 = 0, DQS1 = 0
8190 13:08:22.916034 DQM Delay:
8191 13:08:22.918980 DQM0 = 134, DQM1 = 127
8192 13:08:22.919047 DQ Delay:
8193 13:08:22.922377 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8194 13:08:22.925812 DQ4 =134, DQ5 =124, DQ6 =138, DQ7 =142
8195 13:08:22.929115 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8196 13:08:22.932265 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8197 13:08:22.932330
8198 13:08:22.932386
8199 13:08:22.932445
8200 13:08:22.935390 [DramC_TX_OE_Calibration] TA2
8201 13:08:22.938975 Original DQ_B0 (3 6) =30, OEN = 27
8202 13:08:22.942388 Original DQ_B1 (3 6) =30, OEN = 27
8203 13:08:22.945840 24, 0x0, End_B0=24 End_B1=24
8204 13:08:22.948846 25, 0x0, End_B0=25 End_B1=25
8205 13:08:22.948917 26, 0x0, End_B0=26 End_B1=26
8206 13:08:22.952273 27, 0x0, End_B0=27 End_B1=27
8207 13:08:22.955624 28, 0x0, End_B0=28 End_B1=28
8208 13:08:22.959313 29, 0x0, End_B0=29 End_B1=29
8209 13:08:22.959427 30, 0x0, End_B0=30 End_B1=30
8210 13:08:22.962644 31, 0x4545, End_B0=30 End_B1=30
8211 13:08:22.965530 Byte0 end_step=30 best_step=27
8212 13:08:22.968945 Byte1 end_step=30 best_step=27
8213 13:08:22.972417 Byte0 TX OE(2T, 0.5T) = (3, 3)
8214 13:08:22.975723 Byte1 TX OE(2T, 0.5T) = (3, 3)
8215 13:08:22.975789
8216 13:08:22.975855
8217 13:08:22.981894 [DQSOSCAuto] RK1, (LSB)MR18= 0x220a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8218 13:08:22.985909 CH0 RK1: MR19=303, MR18=220A
8219 13:08:22.992464 CH0_RK1: MR19=0x303, MR18=0x220A, DQSOSC=392, MR23=63, INC=24, DEC=16
8220 13:08:22.995567 [RxdqsGatingPostProcess] freq 1600
8221 13:08:22.998719 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8222 13:08:23.001835 best DQS0 dly(2T, 0.5T) = (1, 1)
8223 13:08:23.005334 best DQS1 dly(2T, 0.5T) = (1, 1)
8224 13:08:23.008706 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8225 13:08:23.012129 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8226 13:08:23.015601 best DQS0 dly(2T, 0.5T) = (1, 1)
8227 13:08:23.018745 best DQS1 dly(2T, 0.5T) = (1, 1)
8228 13:08:23.021740 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8229 13:08:23.025063 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8230 13:08:23.028684 Pre-setting of DQS Precalculation
8231 13:08:23.032245 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8232 13:08:23.032338 ==
8233 13:08:23.035485 Dram Type= 6, Freq= 0, CH_1, rank 0
8234 13:08:23.038893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8235 13:08:23.042378 ==
8236 13:08:23.045723 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8237 13:08:23.048400 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8238 13:08:23.055480 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8239 13:08:23.058565 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8240 13:08:23.068911 [CA 0] Center 41 (12~71) winsize 60
8241 13:08:23.072297 [CA 1] Center 41 (12~71) winsize 60
8242 13:08:23.075478 [CA 2] Center 38 (9~68) winsize 60
8243 13:08:23.078909 [CA 3] Center 37 (8~66) winsize 59
8244 13:08:23.082427 [CA 4] Center 37 (8~67) winsize 60
8245 13:08:23.085210 [CA 5] Center 36 (7~66) winsize 60
8246 13:08:23.085285
8247 13:08:23.088627 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8248 13:08:23.088694
8249 13:08:23.091976 [CATrainingPosCal] consider 1 rank data
8250 13:08:23.095271 u2DelayCellTimex100 = 290/100 ps
8251 13:08:23.099245 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8252 13:08:23.105751 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8253 13:08:23.109078 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8254 13:08:23.112357 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8255 13:08:23.115217 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8256 13:08:23.118765 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8257 13:08:23.118842
8258 13:08:23.122030 CA PerBit enable=1, Macro0, CA PI delay=36
8259 13:08:23.122130
8260 13:08:23.125561 [CBTSetCACLKResult] CA Dly = 36
8261 13:08:23.128820 CS Dly: 10 (0~41)
8262 13:08:23.132172 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8263 13:08:23.135532 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8264 13:08:23.135611 ==
8265 13:08:23.138597 Dram Type= 6, Freq= 0, CH_1, rank 1
8266 13:08:23.141794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8267 13:08:23.145626 ==
8268 13:08:23.149000 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8269 13:08:23.151650 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8270 13:08:23.158402 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8271 13:08:23.161769 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8272 13:08:23.172331 [CA 0] Center 42 (13~72) winsize 60
8273 13:08:23.175528 [CA 1] Center 42 (13~72) winsize 60
8274 13:08:23.178628 [CA 2] Center 38 (9~68) winsize 60
8275 13:08:23.182462 [CA 3] Center 38 (8~68) winsize 61
8276 13:08:23.185685 [CA 4] Center 38 (9~68) winsize 60
8277 13:08:23.188370 [CA 5] Center 37 (8~67) winsize 60
8278 13:08:23.188448
8279 13:08:23.192323 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8280 13:08:23.192399
8281 13:08:23.195353 [CATrainingPosCal] consider 2 rank data
8282 13:08:23.198285 u2DelayCellTimex100 = 290/100 ps
8283 13:08:23.201697 CA0 delay=42 (13~71),Diff = 5 PI (16 cell)
8284 13:08:23.208953 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8285 13:08:23.212055 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8286 13:08:23.215322 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8287 13:08:23.218604 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8288 13:08:23.222014 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8289 13:08:23.222105
8290 13:08:23.224768 CA PerBit enable=1, Macro0, CA PI delay=37
8291 13:08:23.224845
8292 13:08:23.228121 [CBTSetCACLKResult] CA Dly = 37
8293 13:08:23.231947 CS Dly: 12 (0~45)
8294 13:08:23.235375 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8295 13:08:23.238779 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8296 13:08:23.238856
8297 13:08:23.241505 ----->DramcWriteLeveling(PI) begin...
8298 13:08:23.241605 ==
8299 13:08:23.244904 Dram Type= 6, Freq= 0, CH_1, rank 0
8300 13:08:23.251635 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 13:08:23.251712 ==
8302 13:08:23.254815 Write leveling (Byte 0): 26 => 26
8303 13:08:23.254893 Write leveling (Byte 1): 28 => 28
8304 13:08:23.258161 DramcWriteLeveling(PI) end<-----
8305 13:08:23.258259
8306 13:08:23.258341 ==
8307 13:08:23.261519 Dram Type= 6, Freq= 0, CH_1, rank 0
8308 13:08:23.268124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8309 13:08:23.268245 ==
8310 13:08:23.271658 [Gating] SW mode calibration
8311 13:08:23.278512 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8312 13:08:23.281167 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8313 13:08:23.288311 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8314 13:08:23.291652 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8315 13:08:23.295005 1 4 8 | B1->B0 | 2423 2e2e | 1 0 | (0 0) (1 1)
8316 13:08:23.301806 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8317 13:08:23.304564 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 13:08:23.307958 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 13:08:23.314747 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 13:08:23.317833 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8321 13:08:23.321457 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 13:08:23.327933 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8323 13:08:23.331400 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
8324 13:08:23.334321 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
8325 13:08:23.341467 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 13:08:23.344689 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 13:08:23.348085 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 13:08:23.354026 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 13:08:23.358014 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 13:08:23.361322 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 13:08:23.364678 1 6 8 | B1->B0 | 2828 4343 | 0 0 | (0 0) (0 0)
8332 13:08:23.371011 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 13:08:23.374471 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 13:08:23.377821 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 13:08:23.384168 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 13:08:23.387495 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 13:08:23.390877 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 13:08:23.397376 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 13:08:23.400809 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8340 13:08:23.404111 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8341 13:08:23.411175 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 13:08:23.414592 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 13:08:23.417911 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 13:08:23.424172 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 13:08:23.427539 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 13:08:23.430990 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 13:08:23.437750 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 13:08:23.440855 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 13:08:23.443854 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 13:08:23.450702 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 13:08:23.454743 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 13:08:23.457327 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 13:08:23.464285 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 13:08:23.467664 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 13:08:23.470863 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8356 13:08:23.477387 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8357 13:08:23.477462 Total UI for P1: 0, mck2ui 16
8358 13:08:23.483626 best dqsien dly found for B0: ( 1, 9, 8)
8359 13:08:23.487353 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 13:08:23.490298 Total UI for P1: 0, mck2ui 16
8361 13:08:23.493786 best dqsien dly found for B1: ( 1, 9, 10)
8362 13:08:23.497289 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8363 13:08:23.500541 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8364 13:08:23.500696
8365 13:08:23.503962 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8366 13:08:23.506977 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8367 13:08:23.510477 [Gating] SW calibration Done
8368 13:08:23.510586 ==
8369 13:08:23.513884 Dram Type= 6, Freq= 0, CH_1, rank 0
8370 13:08:23.517346 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8371 13:08:23.517480 ==
8372 13:08:23.520919 RX Vref Scan: 0
8373 13:08:23.521067
8374 13:08:23.523679 RX Vref 0 -> 0, step: 1
8375 13:08:23.523851
8376 13:08:23.523964 RX Delay 0 -> 252, step: 8
8377 13:08:23.530563 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8378 13:08:23.534017 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8379 13:08:23.537156 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8380 13:08:23.540806 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8381 13:08:23.544134 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8382 13:08:23.550892 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8383 13:08:23.553496 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8384 13:08:23.557221 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8385 13:08:23.560030 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8386 13:08:23.563379 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8387 13:08:23.570627 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8388 13:08:23.573723 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8389 13:08:23.577238 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8390 13:08:23.579867 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8391 13:08:23.583610 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8392 13:08:23.590279 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8393 13:08:23.590423 ==
8394 13:08:23.593699 Dram Type= 6, Freq= 0, CH_1, rank 0
8395 13:08:23.597207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8396 13:08:23.597335 ==
8397 13:08:23.597432 DQS Delay:
8398 13:08:23.600353 DQS0 = 0, DQS1 = 0
8399 13:08:23.600494 DQM Delay:
8400 13:08:23.603549 DQM0 = 136, DQM1 = 132
8401 13:08:23.603627 DQ Delay:
8402 13:08:23.607067 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8403 13:08:23.610478 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8404 13:08:23.613257 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8405 13:08:23.616701 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8406 13:08:23.616802
8407 13:08:23.616886
8408 13:08:23.620219 ==
8409 13:08:23.620316 Dram Type= 6, Freq= 0, CH_1, rank 0
8410 13:08:23.626614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8411 13:08:23.626694 ==
8412 13:08:23.626755
8413 13:08:23.626811
8414 13:08:23.630276 TX Vref Scan disable
8415 13:08:23.630353 == TX Byte 0 ==
8416 13:08:23.633650 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8417 13:08:23.639895 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8418 13:08:23.639970 == TX Byte 1 ==
8419 13:08:23.643375 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8420 13:08:23.650457 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8421 13:08:23.650534 ==
8422 13:08:23.653242 Dram Type= 6, Freq= 0, CH_1, rank 0
8423 13:08:23.656846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8424 13:08:23.656922 ==
8425 13:08:23.669506
8426 13:08:23.672846 TX Vref early break, caculate TX vref
8427 13:08:23.675819 TX Vref=16, minBit 1, minWin=22, winSum=375
8428 13:08:23.679216 TX Vref=18, minBit 1, minWin=23, winSum=385
8429 13:08:23.682712 TX Vref=20, minBit 1, minWin=23, winSum=397
8430 13:08:23.686482 TX Vref=22, minBit 0, minWin=25, winSum=410
8431 13:08:23.689654 TX Vref=24, minBit 0, minWin=25, winSum=414
8432 13:08:23.695861 TX Vref=26, minBit 1, minWin=25, winSum=428
8433 13:08:23.699339 TX Vref=28, minBit 0, minWin=25, winSum=429
8434 13:08:23.702594 TX Vref=30, minBit 0, minWin=25, winSum=421
8435 13:08:23.705839 TX Vref=32, minBit 0, minWin=25, winSum=414
8436 13:08:23.709222 TX Vref=34, minBit 0, minWin=23, winSum=401
8437 13:08:23.715971 [TxChooseVref] Worse bit 0, Min win 25, Win sum 429, Final Vref 28
8438 13:08:23.716177
8439 13:08:23.719155 Final TX Range 0 Vref 28
8440 13:08:23.719249
8441 13:08:23.719308 ==
8442 13:08:23.722281 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 13:08:23.725459 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 13:08:23.725532 ==
8445 13:08:23.725591
8446 13:08:23.725644
8447 13:08:23.729357 TX Vref Scan disable
8448 13:08:23.735996 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8449 13:08:23.736078 == TX Byte 0 ==
8450 13:08:23.739458 u2DelayCellOfst[0]=16 cells (5 PI)
8451 13:08:23.742350 u2DelayCellOfst[1]=6 cells (2 PI)
8452 13:08:23.745660 u2DelayCellOfst[2]=0 cells (0 PI)
8453 13:08:23.749248 u2DelayCellOfst[3]=3 cells (1 PI)
8454 13:08:23.752616 u2DelayCellOfst[4]=6 cells (2 PI)
8455 13:08:23.755984 u2DelayCellOfst[5]=16 cells (5 PI)
8456 13:08:23.759347 u2DelayCellOfst[6]=16 cells (5 PI)
8457 13:08:23.759445 u2DelayCellOfst[7]=3 cells (1 PI)
8458 13:08:23.765456 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8459 13:08:23.769034 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8460 13:08:23.769184 == TX Byte 1 ==
8461 13:08:23.772708 u2DelayCellOfst[8]=0 cells (0 PI)
8462 13:08:23.776103 u2DelayCellOfst[9]=3 cells (1 PI)
8463 13:08:23.779308 u2DelayCellOfst[10]=13 cells (4 PI)
8464 13:08:23.782720 u2DelayCellOfst[11]=3 cells (1 PI)
8465 13:08:23.785524 u2DelayCellOfst[12]=16 cells (5 PI)
8466 13:08:23.788996 u2DelayCellOfst[13]=16 cells (5 PI)
8467 13:08:23.792441 u2DelayCellOfst[14]=20 cells (6 PI)
8468 13:08:23.795702 u2DelayCellOfst[15]=16 cells (5 PI)
8469 13:08:23.798953 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8470 13:08:23.805783 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8471 13:08:23.806096 DramC Write-DBI on
8472 13:08:23.806318 ==
8473 13:08:23.808789 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 13:08:23.812923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 13:08:23.813281 ==
8476 13:08:23.816197
8477 13:08:23.816583
8478 13:08:23.816938 TX Vref Scan disable
8479 13:08:23.819493 == TX Byte 0 ==
8480 13:08:23.822353 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8481 13:08:23.825995 == TX Byte 1 ==
8482 13:08:23.829144 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8483 13:08:23.829535 DramC Write-DBI off
8484 13:08:23.829836
8485 13:08:23.832971 [DATLAT]
8486 13:08:23.833359 Freq=1600, CH1 RK0
8487 13:08:23.833663
8488 13:08:23.835702 DATLAT Default: 0xf
8489 13:08:23.836092 0, 0xFFFF, sum = 0
8490 13:08:23.839218 1, 0xFFFF, sum = 0
8491 13:08:23.839628 2, 0xFFFF, sum = 0
8492 13:08:23.842443 3, 0xFFFF, sum = 0
8493 13:08:23.842838 4, 0xFFFF, sum = 0
8494 13:08:23.845619 5, 0xFFFF, sum = 0
8495 13:08:23.849266 6, 0xFFFF, sum = 0
8496 13:08:23.849671 7, 0xFFFF, sum = 0
8497 13:08:23.852203 8, 0xFFFF, sum = 0
8498 13:08:23.852603 9, 0xFFFF, sum = 0
8499 13:08:23.855694 10, 0xFFFF, sum = 0
8500 13:08:23.856086 11, 0xFFFF, sum = 0
8501 13:08:23.859105 12, 0xFFFF, sum = 0
8502 13:08:23.859500 13, 0xFFFF, sum = 0
8503 13:08:23.862220 14, 0x0, sum = 1
8504 13:08:23.862768 15, 0x0, sum = 2
8505 13:08:23.865856 16, 0x0, sum = 3
8506 13:08:23.866304 17, 0x0, sum = 4
8507 13:08:23.869053 best_step = 15
8508 13:08:23.869438
8509 13:08:23.869737 ==
8510 13:08:23.872652 Dram Type= 6, Freq= 0, CH_1, rank 0
8511 13:08:23.875715 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8512 13:08:23.876107 ==
8513 13:08:23.876408 RX Vref Scan: 1
8514 13:08:23.876687
8515 13:08:23.879112 Set Vref Range= 24 -> 127
8516 13:08:23.879501
8517 13:08:23.882444 RX Vref 24 -> 127, step: 1
8518 13:08:23.882830
8519 13:08:23.885466 RX Delay 27 -> 252, step: 4
8520 13:08:23.885542
8521 13:08:23.888149 Set Vref, RX VrefLevel [Byte0]: 24
8522 13:08:23.891747 [Byte1]: 24
8523 13:08:23.891823
8524 13:08:23.895027 Set Vref, RX VrefLevel [Byte0]: 25
8525 13:08:23.898353 [Byte1]: 25
8526 13:08:23.898432
8527 13:08:23.902383 Set Vref, RX VrefLevel [Byte0]: 26
8528 13:08:23.905164 [Byte1]: 26
8529 13:08:23.908503
8530 13:08:23.908609 Set Vref, RX VrefLevel [Byte0]: 27
8531 13:08:23.911849 [Byte1]: 27
8532 13:08:23.916577
8533 13:08:23.916679 Set Vref, RX VrefLevel [Byte0]: 28
8534 13:08:23.919576 [Byte1]: 28
8535 13:08:23.924161
8536 13:08:23.924274 Set Vref, RX VrefLevel [Byte0]: 29
8537 13:08:23.927281 [Byte1]: 29
8538 13:08:23.931347
8539 13:08:23.931531 Set Vref, RX VrefLevel [Byte0]: 30
8540 13:08:23.934726 [Byte1]: 30
8541 13:08:23.939109
8542 13:08:23.939323 Set Vref, RX VrefLevel [Byte0]: 31
8543 13:08:23.942630 [Byte1]: 31
8544 13:08:23.946508
8545 13:08:23.946757 Set Vref, RX VrefLevel [Byte0]: 32
8546 13:08:23.950243 [Byte1]: 32
8547 13:08:23.954141
8548 13:08:23.954542 Set Vref, RX VrefLevel [Byte0]: 33
8549 13:08:23.957429 [Byte1]: 33
8550 13:08:23.961933
8551 13:08:23.962370 Set Vref, RX VrefLevel [Byte0]: 34
8552 13:08:23.964950 [Byte1]: 34
8553 13:08:23.969145
8554 13:08:23.969532 Set Vref, RX VrefLevel [Byte0]: 35
8555 13:08:23.972602 [Byte1]: 35
8556 13:08:23.976674
8557 13:08:23.977090 Set Vref, RX VrefLevel [Byte0]: 36
8558 13:08:23.980313 [Byte1]: 36
8559 13:08:23.984244
8560 13:08:23.984702 Set Vref, RX VrefLevel [Byte0]: 37
8561 13:08:23.987678 [Byte1]: 37
8562 13:08:23.992421
8563 13:08:23.992892 Set Vref, RX VrefLevel [Byte0]: 38
8564 13:08:23.994993 [Byte1]: 38
8565 13:08:23.999815
8566 13:08:24.000202 Set Vref, RX VrefLevel [Byte0]: 39
8567 13:08:24.002517 [Byte1]: 39
8568 13:08:24.007235
8569 13:08:24.007621 Set Vref, RX VrefLevel [Byte0]: 40
8570 13:08:24.010611 [Byte1]: 40
8571 13:08:24.014717
8572 13:08:24.015104 Set Vref, RX VrefLevel [Byte0]: 41
8573 13:08:24.018036 [Byte1]: 41
8574 13:08:24.022278
8575 13:08:24.022756 Set Vref, RX VrefLevel [Byte0]: 42
8576 13:08:24.025728 [Byte1]: 42
8577 13:08:24.030257
8578 13:08:24.030803 Set Vref, RX VrefLevel [Byte0]: 43
8579 13:08:24.033160 [Byte1]: 43
8580 13:08:24.037567
8581 13:08:24.037953 Set Vref, RX VrefLevel [Byte0]: 44
8582 13:08:24.040665 [Byte1]: 44
8583 13:08:24.044715
8584 13:08:24.045102 Set Vref, RX VrefLevel [Byte0]: 45
8585 13:08:24.048034 [Byte1]: 45
8586 13:08:24.052066
8587 13:08:24.052454 Set Vref, RX VrefLevel [Byte0]: 46
8588 13:08:24.056041 [Byte1]: 46
8589 13:08:24.059681
8590 13:08:24.060068 Set Vref, RX VrefLevel [Byte0]: 47
8591 13:08:24.063312 [Byte1]: 47
8592 13:08:24.067494
8593 13:08:24.067878 Set Vref, RX VrefLevel [Byte0]: 48
8594 13:08:24.070700 [Byte1]: 48
8595 13:08:24.074891
8596 13:08:24.075276 Set Vref, RX VrefLevel [Byte0]: 49
8597 13:08:24.078647 [Byte1]: 49
8598 13:08:24.082254
8599 13:08:24.082643 Set Vref, RX VrefLevel [Byte0]: 50
8600 13:08:24.085838 [Byte1]: 50
8601 13:08:24.089875
8602 13:08:24.090325 Set Vref, RX VrefLevel [Byte0]: 51
8603 13:08:24.093678 [Byte1]: 51
8604 13:08:24.097155
8605 13:08:24.097545 Set Vref, RX VrefLevel [Byte0]: 52
8606 13:08:24.101115 [Byte1]: 52
8607 13:08:24.105625
8608 13:08:24.106125 Set Vref, RX VrefLevel [Byte0]: 53
8609 13:08:24.108066 [Byte1]: 53
8610 13:08:24.113095
8611 13:08:24.113561 Set Vref, RX VrefLevel [Byte0]: 54
8612 13:08:24.115627 [Byte1]: 54
8613 13:08:24.120713
8614 13:08:24.121222 Set Vref, RX VrefLevel [Byte0]: 55
8615 13:08:24.123113 [Byte1]: 55
8616 13:08:24.127672
8617 13:08:24.128058 Set Vref, RX VrefLevel [Byte0]: 56
8618 13:08:24.130608 [Byte1]: 56
8619 13:08:24.134695
8620 13:08:24.134771 Set Vref, RX VrefLevel [Byte0]: 57
8621 13:08:24.137964 [Byte1]: 57
8622 13:08:24.142606
8623 13:08:24.142681 Set Vref, RX VrefLevel [Byte0]: 58
8624 13:08:24.145844 [Byte1]: 58
8625 13:08:24.150072
8626 13:08:24.150230 Set Vref, RX VrefLevel [Byte0]: 59
8627 13:08:24.153261 [Byte1]: 59
8628 13:08:24.157501
8629 13:08:24.157656 Set Vref, RX VrefLevel [Byte0]: 60
8630 13:08:24.160529 [Byte1]: 60
8631 13:08:24.165030
8632 13:08:24.165213 Set Vref, RX VrefLevel [Byte0]: 61
8633 13:08:24.168188 [Byte1]: 61
8634 13:08:24.172581
8635 13:08:24.172772 Set Vref, RX VrefLevel [Byte0]: 62
8636 13:08:24.175629 [Byte1]: 62
8637 13:08:24.180601
8638 13:08:24.180845 Set Vref, RX VrefLevel [Byte0]: 63
8639 13:08:24.183185 [Byte1]: 63
8640 13:08:24.187463
8641 13:08:24.190669 Set Vref, RX VrefLevel [Byte0]: 64
8642 13:08:24.194381 [Byte1]: 64
8643 13:08:24.194744
8644 13:08:24.197847 Set Vref, RX VrefLevel [Byte0]: 65
8645 13:08:24.201070 [Byte1]: 65
8646 13:08:24.201433
8647 13:08:24.204080 Set Vref, RX VrefLevel [Byte0]: 66
8648 13:08:24.207622 [Byte1]: 66
8649 13:08:24.208070
8650 13:08:24.210868 Set Vref, RX VrefLevel [Byte0]: 67
8651 13:08:24.214182 [Byte1]: 67
8652 13:08:24.217844
8653 13:08:24.218275 Set Vref, RX VrefLevel [Byte0]: 68
8654 13:08:24.221028 [Byte1]: 68
8655 13:08:24.225664
8656 13:08:24.226078 Set Vref, RX VrefLevel [Byte0]: 69
8657 13:08:24.229152 [Byte1]: 69
8658 13:08:24.233618
8659 13:08:24.234151 Set Vref, RX VrefLevel [Byte0]: 70
8660 13:08:24.236667 [Byte1]: 70
8661 13:08:24.240729
8662 13:08:24.241122 Set Vref, RX VrefLevel [Byte0]: 71
8663 13:08:24.244177 [Byte1]: 71
8664 13:08:24.248069
8665 13:08:24.248563 Set Vref, RX VrefLevel [Byte0]: 72
8666 13:08:24.251222 [Byte1]: 72
8667 13:08:24.255403
8668 13:08:24.255830 Set Vref, RX VrefLevel [Byte0]: 73
8669 13:08:24.258737 [Byte1]: 73
8670 13:08:24.262925
8671 13:08:24.263353 Set Vref, RX VrefLevel [Byte0]: 74
8672 13:08:24.266234 [Byte1]: 74
8673 13:08:24.271050
8674 13:08:24.271489 Set Vref, RX VrefLevel [Byte0]: 75
8675 13:08:24.274183 [Byte1]: 75
8676 13:08:24.278632
8677 13:08:24.279047 Set Vref, RX VrefLevel [Byte0]: 76
8678 13:08:24.281805 [Byte1]: 76
8679 13:08:24.285987
8680 13:08:24.286521 Set Vref, RX VrefLevel [Byte0]: 77
8681 13:08:24.289178 [Byte1]: 77
8682 13:08:24.293268
8683 13:08:24.293875 Set Vref, RX VrefLevel [Byte0]: 78
8684 13:08:24.296677 [Byte1]: 78
8685 13:08:24.300703
8686 13:08:24.301264 Final RX Vref Byte 0 = 59 to rank0
8687 13:08:24.304073 Final RX Vref Byte 1 = 58 to rank0
8688 13:08:24.307627 Final RX Vref Byte 0 = 59 to rank1
8689 13:08:24.310995 Final RX Vref Byte 1 = 58 to rank1==
8690 13:08:24.314374 Dram Type= 6, Freq= 0, CH_1, rank 0
8691 13:08:24.317704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8692 13:08:24.321004 ==
8693 13:08:24.321546 DQS Delay:
8694 13:08:24.322153 DQS0 = 0, DQS1 = 0
8695 13:08:24.323950 DQM Delay:
8696 13:08:24.324452 DQM0 = 134, DQM1 = 131
8697 13:08:24.327892 DQ Delay:
8698 13:08:24.330907 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8699 13:08:24.333823 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132
8700 13:08:24.337265 DQ8 =118, DQ9 =122, DQ10 =132, DQ11 =122
8701 13:08:24.340939 DQ12 =140, DQ13 =138, DQ14 =138, DQ15 =140
8702 13:08:24.341389
8703 13:08:24.341826
8704 13:08:24.342326
8705 13:08:24.343928 [DramC_TX_OE_Calibration] TA2
8706 13:08:24.347637 Original DQ_B0 (3 6) =30, OEN = 27
8707 13:08:24.350962 Original DQ_B1 (3 6) =30, OEN = 27
8708 13:08:24.354118 24, 0x0, End_B0=24 End_B1=24
8709 13:08:24.354511 25, 0x0, End_B0=25 End_B1=25
8710 13:08:24.357361 26, 0x0, End_B0=26 End_B1=26
8711 13:08:24.361258 27, 0x0, End_B0=27 End_B1=27
8712 13:08:24.363979 28, 0x0, End_B0=28 End_B1=28
8713 13:08:24.364370 29, 0x0, End_B0=29 End_B1=29
8714 13:08:24.367861 30, 0x0, End_B0=30 End_B1=30
8715 13:08:24.371225 31, 0x4545, End_B0=30 End_B1=30
8716 13:08:24.374534 Byte0 end_step=30 best_step=27
8717 13:08:24.377405 Byte1 end_step=30 best_step=27
8718 13:08:24.380738 Byte0 TX OE(2T, 0.5T) = (3, 3)
8719 13:08:24.381260 Byte1 TX OE(2T, 0.5T) = (3, 3)
8720 13:08:24.381693
8721 13:08:24.382148
8722 13:08:24.390647 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a28, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8723 13:08:24.394319 CH1 RK0: MR19=303, MR18=1A28
8724 13:08:24.400845 CH1_RK0: MR19=0x303, MR18=0x1A28, DQSOSC=389, MR23=63, INC=24, DEC=16
8725 13:08:24.401320
8726 13:08:24.404211 ----->DramcWriteLeveling(PI) begin...
8727 13:08:24.404684 ==
8728 13:08:24.407615 Dram Type= 6, Freq= 0, CH_1, rank 1
8729 13:08:24.410995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8730 13:08:24.411386 ==
8731 13:08:24.413770 Write leveling (Byte 0): 26 => 26
8732 13:08:24.417217 Write leveling (Byte 1): 30 => 30
8733 13:08:24.420854 DramcWriteLeveling(PI) end<-----
8734 13:08:24.421329
8735 13:08:24.421645 ==
8736 13:08:24.424070 Dram Type= 6, Freq= 0, CH_1, rank 1
8737 13:08:24.427448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8738 13:08:24.427894 ==
8739 13:08:24.430685 [Gating] SW mode calibration
8740 13:08:24.437383 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8741 13:08:24.444094 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8742 13:08:24.447229 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 13:08:24.450808 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 13:08:24.457111 1 4 8 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
8745 13:08:24.460902 1 4 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
8746 13:08:24.463888 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8747 13:08:24.470547 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8748 13:08:24.473699 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8749 13:08:24.477221 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 13:08:24.484014 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8751 13:08:24.487497 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8752 13:08:24.490831 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
8753 13:08:24.496953 1 5 12 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 0)
8754 13:08:24.500833 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 13:08:24.503812 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 13:08:24.506918 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 13:08:24.514410 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 13:08:24.516882 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 13:08:24.520530 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 13:08:24.527612 1 6 8 | B1->B0 | 3f3f 2323 | 1 0 | (0 0) (0 0)
8761 13:08:24.530794 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 13:08:24.534060 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8763 13:08:24.540035 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 13:08:24.543480 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 13:08:24.546906 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 13:08:24.553787 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 13:08:24.557164 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8768 13:08:24.560326 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8769 13:08:24.566744 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8770 13:08:24.570096 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 13:08:24.573422 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 13:08:24.580622 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 13:08:24.583798 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 13:08:24.586867 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 13:08:24.593332 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 13:08:24.596615 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 13:08:24.600154 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 13:08:24.606862 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 13:08:24.609999 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 13:08:24.613555 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 13:08:24.620186 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 13:08:24.623201 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 13:08:24.626833 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8784 13:08:24.632991 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8785 13:08:24.637063 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8786 13:08:24.639693 Total UI for P1: 0, mck2ui 16
8787 13:08:24.643077 best dqsien dly found for B1: ( 1, 9, 6)
8788 13:08:24.646259 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 13:08:24.649689 Total UI for P1: 0, mck2ui 16
8790 13:08:24.653358 best dqsien dly found for B0: ( 1, 9, 10)
8791 13:08:24.656459 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8792 13:08:24.660031 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8793 13:08:24.660573
8794 13:08:24.663340 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8795 13:08:24.669958 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8796 13:08:24.670503 [Gating] SW calibration Done
8797 13:08:24.670871 ==
8798 13:08:24.673522 Dram Type= 6, Freq= 0, CH_1, rank 1
8799 13:08:24.679693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8800 13:08:24.680222 ==
8801 13:08:24.680692 RX Vref Scan: 0
8802 13:08:24.680993
8803 13:08:24.683577 RX Vref 0 -> 0, step: 1
8804 13:08:24.683962
8805 13:08:24.686909 RX Delay 0 -> 252, step: 8
8806 13:08:24.689851 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8807 13:08:24.693320 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8808 13:08:24.696758 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8809 13:08:24.699998 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8810 13:08:24.706523 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8811 13:08:24.709757 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8812 13:08:24.713338 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8813 13:08:24.716442 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8814 13:08:24.719440 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8815 13:08:24.726706 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8816 13:08:24.729811 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8817 13:08:24.733332 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8818 13:08:24.736403 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8819 13:08:24.739722 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8820 13:08:24.746445 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8821 13:08:24.749564 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8822 13:08:24.749955 ==
8823 13:08:24.753233 Dram Type= 6, Freq= 0, CH_1, rank 1
8824 13:08:24.756654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 13:08:24.757045 ==
8826 13:08:24.760167 DQS Delay:
8827 13:08:24.760555 DQS0 = 0, DQS1 = 0
8828 13:08:24.760858 DQM Delay:
8829 13:08:24.762907 DQM0 = 136, DQM1 = 133
8830 13:08:24.763293 DQ Delay:
8831 13:08:24.766363 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8832 13:08:24.769682 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8833 13:08:24.776240 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8834 13:08:24.779400 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8835 13:08:24.779874
8836 13:08:24.780241
8837 13:08:24.780695 ==
8838 13:08:24.783194 Dram Type= 6, Freq= 0, CH_1, rank 1
8839 13:08:24.785902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8840 13:08:24.786409 ==
8841 13:08:24.786809
8842 13:08:24.787157
8843 13:08:24.789856 TX Vref Scan disable
8844 13:08:24.790434 == TX Byte 0 ==
8845 13:08:24.796507 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8846 13:08:24.799949 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8847 13:08:24.800513 == TX Byte 1 ==
8848 13:08:24.806145 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8849 13:08:24.809631 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8850 13:08:24.810054 ==
8851 13:08:24.813205 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 13:08:24.816448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 13:08:24.816840 ==
8854 13:08:24.831293
8855 13:08:24.834815 TX Vref early break, caculate TX vref
8856 13:08:24.838292 TX Vref=16, minBit 0, minWin=22, winSum=381
8857 13:08:24.841583 TX Vref=18, minBit 1, minWin=23, winSum=395
8858 13:08:24.844668 TX Vref=20, minBit 0, minWin=23, winSum=404
8859 13:08:24.847844 TX Vref=22, minBit 0, minWin=24, winSum=411
8860 13:08:24.851463 TX Vref=24, minBit 0, minWin=25, winSum=419
8861 13:08:24.857952 TX Vref=26, minBit 0, minWin=25, winSum=423
8862 13:08:24.861389 TX Vref=28, minBit 0, minWin=25, winSum=425
8863 13:08:24.864287 TX Vref=30, minBit 0, minWin=25, winSum=420
8864 13:08:24.867717 TX Vref=32, minBit 0, minWin=25, winSum=413
8865 13:08:24.871382 TX Vref=34, minBit 0, minWin=24, winSum=403
8866 13:08:24.874904 TX Vref=36, minBit 0, minWin=24, winSum=397
8867 13:08:24.881097 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 28
8868 13:08:24.881515
8869 13:08:24.884312 Final TX Range 0 Vref 28
8870 13:08:24.884764
8871 13:08:24.885064 ==
8872 13:08:24.887569 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 13:08:24.890840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 13:08:24.891395 ==
8875 13:08:24.891883
8876 13:08:24.894254
8877 13:08:24.894736 TX Vref Scan disable
8878 13:08:24.900767 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8879 13:08:24.901157 == TX Byte 0 ==
8880 13:08:24.904288 u2DelayCellOfst[0]=16 cells (5 PI)
8881 13:08:24.907673 u2DelayCellOfst[1]=10 cells (3 PI)
8882 13:08:24.911024 u2DelayCellOfst[2]=0 cells (0 PI)
8883 13:08:24.914383 u2DelayCellOfst[3]=6 cells (2 PI)
8884 13:08:24.917750 u2DelayCellOfst[4]=6 cells (2 PI)
8885 13:08:24.921383 u2DelayCellOfst[5]=16 cells (5 PI)
8886 13:08:24.924339 u2DelayCellOfst[6]=20 cells (6 PI)
8887 13:08:24.927589 u2DelayCellOfst[7]=3 cells (1 PI)
8888 13:08:24.930883 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8889 13:08:24.934247 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8890 13:08:24.937828 == TX Byte 1 ==
8891 13:08:24.940830 u2DelayCellOfst[8]=0 cells (0 PI)
8892 13:08:24.941335 u2DelayCellOfst[9]=3 cells (1 PI)
8893 13:08:24.944167 u2DelayCellOfst[10]=10 cells (3 PI)
8894 13:08:24.947672 u2DelayCellOfst[11]=3 cells (1 PI)
8895 13:08:24.950915 u2DelayCellOfst[12]=13 cells (4 PI)
8896 13:08:24.954190 u2DelayCellOfst[13]=16 cells (5 PI)
8897 13:08:24.957463 u2DelayCellOfst[14]=16 cells (5 PI)
8898 13:08:24.960851 u2DelayCellOfst[15]=16 cells (5 PI)
8899 13:08:24.967864 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8900 13:08:24.970710 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8901 13:08:24.971039 DramC Write-DBI on
8902 13:08:24.971258 ==
8903 13:08:24.974121 Dram Type= 6, Freq= 0, CH_1, rank 1
8904 13:08:24.980845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8905 13:08:24.981283 ==
8906 13:08:24.981538
8907 13:08:24.981758
8908 13:08:24.982090 TX Vref Scan disable
8909 13:08:24.984333 == TX Byte 0 ==
8910 13:08:24.987760 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8911 13:08:24.991013 == TX Byte 1 ==
8912 13:08:24.994808 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8913 13:08:24.997406 DramC Write-DBI off
8914 13:08:24.997679
8915 13:08:24.997891 [DATLAT]
8916 13:08:24.998116 Freq=1600, CH1 RK1
8917 13:08:24.998312
8918 13:08:25.001215 DATLAT Default: 0xf
8919 13:08:25.001562 0, 0xFFFF, sum = 0
8920 13:08:25.004518 1, 0xFFFF, sum = 0
8921 13:08:25.007747 2, 0xFFFF, sum = 0
8922 13:08:25.008038 3, 0xFFFF, sum = 0
8923 13:08:25.011032 4, 0xFFFF, sum = 0
8924 13:08:25.011315 5, 0xFFFF, sum = 0
8925 13:08:25.014442 6, 0xFFFF, sum = 0
8926 13:08:25.014723 7, 0xFFFF, sum = 0
8927 13:08:25.017864 8, 0xFFFF, sum = 0
8928 13:08:25.018188 9, 0xFFFF, sum = 0
8929 13:08:25.021246 10, 0xFFFF, sum = 0
8930 13:08:25.021674 11, 0xFFFF, sum = 0
8931 13:08:25.024560 12, 0xFFFF, sum = 0
8932 13:08:25.024927 13, 0xFFFF, sum = 0
8933 13:08:25.027321 14, 0x0, sum = 1
8934 13:08:25.027702 15, 0x0, sum = 2
8935 13:08:25.031229 16, 0x0, sum = 3
8936 13:08:25.031601 17, 0x0, sum = 4
8937 13:08:25.034530 best_step = 15
8938 13:08:25.034903
8939 13:08:25.035227 ==
8940 13:08:25.037841 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 13:08:25.041330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 13:08:25.041672 ==
8943 13:08:25.041886 RX Vref Scan: 0
8944 13:08:25.043776
8945 13:08:25.044140 RX Vref 0 -> 0, step: 1
8946 13:08:25.044396
8947 13:08:25.047727 RX Delay 19 -> 252, step: 4
8948 13:08:25.050481 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8949 13:08:25.057314 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8950 13:08:25.060678 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8951 13:08:25.063707 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8952 13:08:25.067174 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8953 13:08:25.070503 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8954 13:08:25.077366 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8955 13:08:25.080237 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8956 13:08:25.083774 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8957 13:08:25.087004 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8958 13:08:25.090384 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8959 13:08:25.096831 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8960 13:08:25.100572 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8961 13:08:25.103518 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8962 13:08:25.106950 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8963 13:08:25.110400 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8964 13:08:25.113755 ==
8965 13:08:25.116589 Dram Type= 6, Freq= 0, CH_1, rank 1
8966 13:08:25.120307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8967 13:08:25.120583 ==
8968 13:08:25.120802 DQS Delay:
8969 13:08:25.124087 DQS0 = 0, DQS1 = 0
8970 13:08:25.124362 DQM Delay:
8971 13:08:25.126692 DQM0 = 134, DQM1 = 130
8972 13:08:25.126967 DQ Delay:
8973 13:08:25.130192 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =130
8974 13:08:25.133732 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8975 13:08:25.136983 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8976 13:08:25.140624 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8977 13:08:25.140973
8978 13:08:25.141207
8979 13:08:25.141408
8980 13:08:25.142923 [DramC_TX_OE_Calibration] TA2
8981 13:08:25.146882 Original DQ_B0 (3 6) =30, OEN = 27
8982 13:08:25.150138 Original DQ_B1 (3 6) =30, OEN = 27
8983 13:08:25.153422 24, 0x0, End_B0=24 End_B1=24
8984 13:08:25.156922 25, 0x0, End_B0=25 End_B1=25
8985 13:08:25.157243 26, 0x0, End_B0=26 End_B1=26
8986 13:08:25.160470 27, 0x0, End_B0=27 End_B1=27
8987 13:08:25.163781 28, 0x0, End_B0=28 End_B1=28
8988 13:08:25.167120 29, 0x0, End_B0=29 End_B1=29
8989 13:08:25.169688 30, 0x0, End_B0=30 End_B1=30
8990 13:08:25.169997 31, 0x4141, End_B0=30 End_B1=30
8991 13:08:25.173085 Byte0 end_step=30 best_step=27
8992 13:08:25.176591 Byte1 end_step=30 best_step=27
8993 13:08:25.179936 Byte0 TX OE(2T, 0.5T) = (3, 3)
8994 13:08:25.183078 Byte1 TX OE(2T, 0.5T) = (3, 3)
8995 13:08:25.183399
8996 13:08:25.183614
8997 13:08:25.189641 [DQSOSCAuto] RK1, (LSB)MR18= 0x260c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 390 ps
8998 13:08:25.193183 CH1 RK1: MR19=303, MR18=260C
8999 13:08:25.199912 CH1_RK1: MR19=0x303, MR18=0x260C, DQSOSC=390, MR23=63, INC=24, DEC=16
9000 13:08:25.203440 [RxdqsGatingPostProcess] freq 1600
9001 13:08:25.209474 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9002 13:08:25.209795 best DQS0 dly(2T, 0.5T) = (1, 1)
9003 13:08:25.213339 best DQS1 dly(2T, 0.5T) = (1, 1)
9004 13:08:25.216310 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9005 13:08:25.219550 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9006 13:08:25.223350 best DQS0 dly(2T, 0.5T) = (1, 1)
9007 13:08:25.226059 best DQS1 dly(2T, 0.5T) = (1, 1)
9008 13:08:25.229361 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9009 13:08:25.232908 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9010 13:08:25.236361 Pre-setting of DQS Precalculation
9011 13:08:25.239826 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9012 13:08:25.249399 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9013 13:08:25.256591 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9014 13:08:25.256870
9015 13:08:25.257083
9016 13:08:25.260010 [Calibration Summary] 3200 Mbps
9017 13:08:25.260342 CH 0, Rank 0
9018 13:08:25.263397 SW Impedance : PASS
9019 13:08:25.263673 DUTY Scan : NO K
9020 13:08:25.266509 ZQ Calibration : PASS
9021 13:08:25.269739 Jitter Meter : NO K
9022 13:08:25.270117 CBT Training : PASS
9023 13:08:25.273284 Write leveling : PASS
9024 13:08:25.276168 RX DQS gating : PASS
9025 13:08:25.276526 RX DQ/DQS(RDDQC) : PASS
9026 13:08:25.279423 TX DQ/DQS : PASS
9027 13:08:25.279781 RX DATLAT : PASS
9028 13:08:25.282864 RX DQ/DQS(Engine): PASS
9029 13:08:25.286321 TX OE : PASS
9030 13:08:25.286728 All Pass.
9031 13:08:25.287008
9032 13:08:25.287267 CH 0, Rank 1
9033 13:08:25.289487 SW Impedance : PASS
9034 13:08:25.292936 DUTY Scan : NO K
9035 13:08:25.293294 ZQ Calibration : PASS
9036 13:08:25.296085 Jitter Meter : NO K
9037 13:08:25.300117 CBT Training : PASS
9038 13:08:25.300520 Write leveling : PASS
9039 13:08:25.303341 RX DQS gating : PASS
9040 13:08:25.306716 RX DQ/DQS(RDDQC) : PASS
9041 13:08:25.307117 TX DQ/DQS : PASS
9042 13:08:25.309985 RX DATLAT : PASS
9043 13:08:25.312785 RX DQ/DQS(Engine): PASS
9044 13:08:25.313140 TX OE : PASS
9045 13:08:25.316203 All Pass.
9046 13:08:25.316557
9047 13:08:25.316833 CH 1, Rank 0
9048 13:08:25.319492 SW Impedance : PASS
9049 13:08:25.319846 DUTY Scan : NO K
9050 13:08:25.322788 ZQ Calibration : PASS
9051 13:08:25.326078 Jitter Meter : NO K
9052 13:08:25.326488 CBT Training : PASS
9053 13:08:25.330048 Write leveling : PASS
9054 13:08:25.330412 RX DQS gating : PASS
9055 13:08:25.333180 RX DQ/DQS(RDDQC) : PASS
9056 13:08:25.336518 TX DQ/DQS : PASS
9057 13:08:25.337096 RX DATLAT : PASS
9058 13:08:25.339877 RX DQ/DQS(Engine): PASS
9059 13:08:25.343257 TX OE : PASS
9060 13:08:25.343833 All Pass.
9061 13:08:25.344348
9062 13:08:25.344831 CH 1, Rank 1
9063 13:08:25.346452 SW Impedance : PASS
9064 13:08:25.349538 DUTY Scan : NO K
9065 13:08:25.350076 ZQ Calibration : PASS
9066 13:08:25.353190 Jitter Meter : NO K
9067 13:08:25.356149 CBT Training : PASS
9068 13:08:25.356521 Write leveling : PASS
9069 13:08:25.359588 RX DQS gating : PASS
9070 13:08:25.362615 RX DQ/DQS(RDDQC) : PASS
9071 13:08:25.362985 TX DQ/DQS : PASS
9072 13:08:25.366074 RX DATLAT : PASS
9073 13:08:25.369531 RX DQ/DQS(Engine): PASS
9074 13:08:25.369893 TX OE : PASS
9075 13:08:25.370247 All Pass.
9076 13:08:25.372607
9077 13:08:25.372960 DramC Write-DBI on
9078 13:08:25.376041 PER_BANK_REFRESH: Hybrid Mode
9079 13:08:25.376398 TX_TRACKING: ON
9080 13:08:25.386316 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9081 13:08:25.393038 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9082 13:08:25.402844 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9083 13:08:25.406328 [FAST_K] Save calibration result to emmc
9084 13:08:25.409276 sync common calibartion params.
9085 13:08:25.409631 sync cbt_mode0:1, 1:1
9086 13:08:25.412822 dram_init: ddr_geometry: 2
9087 13:08:25.416303 dram_init: ddr_geometry: 2
9088 13:08:25.416657 dram_init: ddr_geometry: 2
9089 13:08:25.419730 0:dram_rank_size:100000000
9090 13:08:25.423172 1:dram_rank_size:100000000
9091 13:08:25.426383 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9092 13:08:25.430166 DFS_SHUFFLE_HW_MODE: ON
9093 13:08:25.433153 dramc_set_vcore_voltage set vcore to 725000
9094 13:08:25.436513 Read voltage for 1600, 0
9095 13:08:25.436882 Vio18 = 0
9096 13:08:25.439658 Vcore = 725000
9097 13:08:25.440026 Vdram = 0
9098 13:08:25.440394 Vddq = 0
9099 13:08:25.440740 Vmddr = 0
9100 13:08:25.442863 switch to 3200 Mbps bootup
9101 13:08:25.446335 [DramcRunTimeConfig]
9102 13:08:25.446703 PHYPLL
9103 13:08:25.447068 DPM_CONTROL_AFTERK: ON
9104 13:08:25.449713 PER_BANK_REFRESH: ON
9105 13:08:25.452958 REFRESH_OVERHEAD_REDUCTION: ON
9106 13:08:25.456362 CMD_PICG_NEW_MODE: OFF
9107 13:08:25.456825 XRTWTW_NEW_MODE: ON
9108 13:08:25.459579 XRTRTR_NEW_MODE: ON
9109 13:08:25.459947 TX_TRACKING: ON
9110 13:08:25.462669 RDSEL_TRACKING: OFF
9111 13:08:25.463037 DQS Precalculation for DVFS: ON
9112 13:08:25.466172 RX_TRACKING: OFF
9113 13:08:25.466541 HW_GATING DBG: ON
9114 13:08:25.469530 ZQCS_ENABLE_LP4: ON
9115 13:08:25.472926 RX_PICG_NEW_MODE: ON
9116 13:08:25.473396 TX_PICG_NEW_MODE: ON
9117 13:08:25.476064 ENABLE_RX_DCM_DPHY: ON
9118 13:08:25.479204 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9119 13:08:25.479557 DUMMY_READ_FOR_TRACKING: OFF
9120 13:08:25.482964 !!! SPM_CONTROL_AFTERK: OFF
9121 13:08:25.485870 !!! SPM could not control APHY
9122 13:08:25.489598 IMPEDANCE_TRACKING: ON
9123 13:08:25.489955 TEMP_SENSOR: ON
9124 13:08:25.492504 HW_SAVE_FOR_SR: OFF
9125 13:08:25.492857 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9126 13:08:25.499284 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9127 13:08:25.499637 Read ODT Tracking: ON
9128 13:08:25.503003 Refresh Rate DeBounce: ON
9129 13:08:25.506038 DFS_NO_QUEUE_FLUSH: ON
9130 13:08:25.509235 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9131 13:08:25.509587 ENABLE_DFS_RUNTIME_MRW: OFF
9132 13:08:25.512495 DDR_RESERVE_NEW_MODE: ON
9133 13:08:25.515761 MR_CBT_SWITCH_FREQ: ON
9134 13:08:25.516156 =========================
9135 13:08:25.535523 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9136 13:08:25.538871 dram_init: ddr_geometry: 2
9137 13:08:25.557190 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9138 13:08:25.560465 dram_init: dram init end (result: 0)
9139 13:08:25.567106 DRAM-K: Full calibration passed in 24461 msecs
9140 13:08:25.570154 MRC: failed to locate region type 0.
9141 13:08:25.570512 DRAM rank0 size:0x100000000,
9142 13:08:25.574111 DRAM rank1 size=0x100000000
9143 13:08:25.583878 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9144 13:08:25.591019 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9145 13:08:25.596959 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9146 13:08:25.603996 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9147 13:08:25.607049 DRAM rank0 size:0x100000000,
9148 13:08:25.610371 DRAM rank1 size=0x100000000
9149 13:08:25.610725 CBMEM:
9150 13:08:25.614041 IMD: root @ 0xfffff000 254 entries.
9151 13:08:25.617031 IMD: root @ 0xffffec00 62 entries.
9152 13:08:25.620224 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9153 13:08:25.623871 WARNING: RO_VPD is uninitialized or empty.
9154 13:08:25.630296 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9155 13:08:25.637527 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9156 13:08:25.650106 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9157 13:08:25.661255 BS: romstage times (exec / console): total (unknown) / 23995 ms
9158 13:08:25.661695
9159 13:08:25.661993
9160 13:08:25.671767 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9161 13:08:25.674743 ARM64: Exception handlers installed.
9162 13:08:25.677934 ARM64: Testing exception
9163 13:08:25.681748 ARM64: Done test exception
9164 13:08:25.682327 Enumerating buses...
9165 13:08:25.684972 Show all devs... Before device enumeration.
9166 13:08:25.688247 Root Device: enabled 1
9167 13:08:25.691669 CPU_CLUSTER: 0: enabled 1
9168 13:08:25.692178 CPU: 00: enabled 1
9169 13:08:25.695097 Compare with tree...
9170 13:08:25.695566 Root Device: enabled 1
9171 13:08:25.698490 CPU_CLUSTER: 0: enabled 1
9172 13:08:25.701281 CPU: 00: enabled 1
9173 13:08:25.701667 Root Device scanning...
9174 13:08:25.704672 scan_static_bus for Root Device
9175 13:08:25.708194 CPU_CLUSTER: 0 enabled
9176 13:08:25.711452 scan_static_bus for Root Device done
9177 13:08:25.715053 scan_bus: bus Root Device finished in 8 msecs
9178 13:08:25.715440 done
9179 13:08:25.721336 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9180 13:08:25.724567 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9181 13:08:25.731274 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9182 13:08:25.734695 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9183 13:08:25.738139 Allocating resources...
9184 13:08:25.741437 Reading resources...
9185 13:08:25.744801 Root Device read_resources bus 0 link: 0
9186 13:08:25.745282 DRAM rank0 size:0x100000000,
9187 13:08:25.747850 DRAM rank1 size=0x100000000
9188 13:08:25.751535 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9189 13:08:25.754386 CPU: 00 missing read_resources
9190 13:08:25.758197 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9191 13:08:25.764479 Root Device read_resources bus 0 link: 0 done
9192 13:08:25.764988 Done reading resources.
9193 13:08:25.771427 Show resources in subtree (Root Device)...After reading.
9194 13:08:25.774852 Root Device child on link 0 CPU_CLUSTER: 0
9195 13:08:25.777402 CPU_CLUSTER: 0 child on link 0 CPU: 00
9196 13:08:25.787577 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9197 13:08:25.787967 CPU: 00
9198 13:08:25.791077 Root Device assign_resources, bus 0 link: 0
9199 13:08:25.794340 CPU_CLUSTER: 0 missing set_resources
9200 13:08:25.797979 Root Device assign_resources, bus 0 link: 0 done
9201 13:08:25.801455 Done setting resources.
9202 13:08:25.807470 Show resources in subtree (Root Device)...After assigning values.
9203 13:08:25.810779 Root Device child on link 0 CPU_CLUSTER: 0
9204 13:08:25.814906 CPU_CLUSTER: 0 child on link 0 CPU: 00
9205 13:08:25.824479 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9206 13:08:25.824920 CPU: 00
9207 13:08:25.827610 Done allocating resources.
9208 13:08:25.831270 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9209 13:08:25.834494 Enabling resources...
9210 13:08:25.834877 done.
9211 13:08:25.841672 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9212 13:08:25.842113 Initializing devices...
9213 13:08:25.844278 Root Device init
9214 13:08:25.844661 init hardware done!
9215 13:08:25.847735 0x00000018: ctrlr->caps
9216 13:08:25.851348 52.000 MHz: ctrlr->f_max
9217 13:08:25.851880 0.400 MHz: ctrlr->f_min
9218 13:08:25.854097 0x40ff8080: ctrlr->voltages
9219 13:08:25.854485 sclk: 390625
9220 13:08:25.857451 Bus Width = 1
9221 13:08:25.857829 sclk: 390625
9222 13:08:25.858172 Bus Width = 1
9223 13:08:25.860918 Early init status = 3
9224 13:08:25.864316 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9225 13:08:25.869020 in-header: 03 fc 00 00 01 00 00 00
9226 13:08:25.872222 in-data: 00
9227 13:08:25.875713 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9228 13:08:25.880380 in-header: 03 fd 00 00 00 00 00 00
9229 13:08:25.883956 in-data:
9230 13:08:25.887390 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9231 13:08:25.891220 in-header: 03 fc 00 00 01 00 00 00
9232 13:08:25.894351 in-data: 00
9233 13:08:25.897517 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9234 13:08:25.903290 in-header: 03 fd 00 00 00 00 00 00
9235 13:08:25.906926 in-data:
9236 13:08:25.909899 [SSUSB] Setting up USB HOST controller...
9237 13:08:25.913065 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9238 13:08:25.916634 [SSUSB] phy power-on done.
9239 13:08:25.919985 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9240 13:08:25.926830 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9241 13:08:25.930257 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9242 13:08:25.936246 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9243 13:08:25.943272 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9244 13:08:25.949942 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9245 13:08:25.956541 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9246 13:08:25.963260 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9247 13:08:25.966096 SPM: binary array size = 0x9dc
9248 13:08:25.969744 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9249 13:08:25.976202 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9250 13:08:25.983278 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9251 13:08:25.986567 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9252 13:08:25.992800 configure_display: Starting display init
9253 13:08:26.026631 anx7625_power_on_init: Init interface.
9254 13:08:26.029499 anx7625_disable_pd_protocol: Disabled PD feature.
9255 13:08:26.033162 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9256 13:08:26.061231 anx7625_start_dp_work: Secure OCM version=00
9257 13:08:26.063898 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9258 13:08:26.079059 sp_tx_get_edid_block: EDID Block = 1
9259 13:08:26.181676 Extracted contents:
9260 13:08:26.185079 header: 00 ff ff ff ff ff ff 00
9261 13:08:26.188429 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9262 13:08:26.191092 version: 01 04
9263 13:08:26.194486 basic params: 95 1f 11 78 0a
9264 13:08:26.198098 chroma info: 76 90 94 55 54 90 27 21 50 54
9265 13:08:26.201415 established: 00 00 00
9266 13:08:26.208356 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9267 13:08:26.211606 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9268 13:08:26.218112 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9269 13:08:26.224407 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9270 13:08:26.231187 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9271 13:08:26.234623 extensions: 00
9272 13:08:26.235004 checksum: fb
9273 13:08:26.235298
9274 13:08:26.238107 Manufacturer: IVO Model 57d Serial Number 0
9275 13:08:26.241357 Made week 0 of 2020
9276 13:08:26.241740 EDID version: 1.4
9277 13:08:26.244713 Digital display
9278 13:08:26.247509 6 bits per primary color channel
9279 13:08:26.247897 DisplayPort interface
9280 13:08:26.250842 Maximum image size: 31 cm x 17 cm
9281 13:08:26.254360 Gamma: 220%
9282 13:08:26.254788 Check DPMS levels
9283 13:08:26.257806 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9284 13:08:26.261276 First detailed timing is preferred timing
9285 13:08:26.264279 Established timings supported:
9286 13:08:26.267754 Standard timings supported:
9287 13:08:26.271166 Detailed timings
9288 13:08:26.274431 Hex of detail: 383680a07038204018303c0035ae10000019
9289 13:08:26.277636 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9290 13:08:26.284797 0780 0798 07c8 0820 hborder 0
9291 13:08:26.287784 0438 043b 0447 0458 vborder 0
9292 13:08:26.291509 -hsync -vsync
9293 13:08:26.291948 Did detailed timing
9294 13:08:26.294470 Hex of detail: 000000000000000000000000000000000000
9295 13:08:26.297965 Manufacturer-specified data, tag 0
9296 13:08:26.304264 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9297 13:08:26.304655 ASCII string: InfoVision
9298 13:08:26.311153 Hex of detail: 000000fe00523134304e574635205248200a
9299 13:08:26.314518 ASCII string: R140NWF5 RH
9300 13:08:26.314912 Checksum
9301 13:08:26.315210 Checksum: 0xfb (valid)
9302 13:08:26.321168 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9303 13:08:26.324626 DSI data_rate: 832800000 bps
9304 13:08:26.327843 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9305 13:08:26.330997 anx7625_parse_edid: pixelclock(138800).
9306 13:08:26.337646 hactive(1920), hsync(48), hfp(24), hbp(88)
9307 13:08:26.341037 vactive(1080), vsync(12), vfp(3), vbp(17)
9308 13:08:26.344473 anx7625_dsi_config: config dsi.
9309 13:08:26.350791 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9310 13:08:26.363134 anx7625_dsi_config: success to config DSI
9311 13:08:26.366488 anx7625_dp_start: MIPI phy setup OK.
9312 13:08:26.369682 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9313 13:08:26.373235 mtk_ddp_mode_set invalid vrefresh 60
9314 13:08:26.376562 main_disp_path_setup
9315 13:08:26.376649 ovl_layer_smi_id_en
9316 13:08:26.379881 ovl_layer_smi_id_en
9317 13:08:26.380006 ccorr_config
9318 13:08:26.380118 aal_config
9319 13:08:26.383181 gamma_config
9320 13:08:26.383257 postmask_config
9321 13:08:26.386614 dither_config
9322 13:08:26.389909 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9323 13:08:26.396434 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9324 13:08:26.399795 Root Device init finished in 553 msecs
9325 13:08:26.399876 CPU_CLUSTER: 0 init
9326 13:08:26.410294 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9327 13:08:26.413510 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9328 13:08:26.416666 APU_MBOX 0x190000b0 = 0x10001
9329 13:08:26.420327 APU_MBOX 0x190001b0 = 0x10001
9330 13:08:26.423415 APU_MBOX 0x190005b0 = 0x10001
9331 13:08:26.426909 APU_MBOX 0x190006b0 = 0x10001
9332 13:08:26.430334 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9333 13:08:26.442679 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9334 13:08:26.455194 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9335 13:08:26.461670 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9336 13:08:26.473153 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9337 13:08:26.482645 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9338 13:08:26.485854 CPU_CLUSTER: 0 init finished in 81 msecs
9339 13:08:26.489350 Devices initialized
9340 13:08:26.492131 Show all devs... After init.
9341 13:08:26.492514 Root Device: enabled 1
9342 13:08:26.495520 CPU_CLUSTER: 0: enabled 1
9343 13:08:26.498779 CPU: 00: enabled 1
9344 13:08:26.502708 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9345 13:08:26.506188 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9346 13:08:26.508896 ELOG: NV offset 0x57f000 size 0x1000
9347 13:08:26.515785 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9348 13:08:26.522497 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9349 13:08:26.525748 ELOG: Event(17) added with size 13 at 2024-07-18 13:08:10 UTC
9350 13:08:26.529198 out: cmd=0x121: 03 db 21 01 00 00 00 00
9351 13:08:26.532662 in-header: 03 f3 00 00 2c 00 00 00
9352 13:08:26.546218 in-data: 4b 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9353 13:08:26.552587 ELOG: Event(A1) added with size 10 at 2024-07-18 13:08:10 UTC
9354 13:08:26.559714 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9355 13:08:26.565779 ELOG: Event(A0) added with size 9 at 2024-07-18 13:08:10 UTC
9356 13:08:26.569561 elog_add_boot_reason: Logged dev mode boot
9357 13:08:26.572580 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9358 13:08:26.576287 Finalize devices...
9359 13:08:26.576778 Devices finalized
9360 13:08:26.582771 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9361 13:08:26.585946 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9362 13:08:26.589261 in-header: 03 07 00 00 08 00 00 00
9363 13:08:26.592479 in-data: aa e4 47 04 13 02 00 00
9364 13:08:26.595776 Chrome EC: UHEPI supported
9365 13:08:26.602711 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9366 13:08:26.605758 in-header: 03 a9 00 00 08 00 00 00
9367 13:08:26.609071 in-data: 84 60 60 08 00 00 00 00
9368 13:08:26.612299 ELOG: Event(91) added with size 10 at 2024-07-18 13:08:10 UTC
9369 13:08:26.619009 Chrome EC: clear events_b mask to 0x0000000020004000
9370 13:08:26.625894 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9371 13:08:26.630191 in-header: 03 fd 00 00 00 00 00 00
9372 13:08:26.630690 in-data:
9373 13:08:26.636116 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9374 13:08:26.639564 Writing coreboot table at 0xffe64000
9375 13:08:26.642883 0. 000000000010a000-0000000000113fff: RAMSTAGE
9376 13:08:26.646578 1. 0000000040000000-00000000400fffff: RAM
9377 13:08:26.649280 2. 0000000040100000-000000004032afff: RAMSTAGE
9378 13:08:26.656115 3. 000000004032b000-00000000545fffff: RAM
9379 13:08:26.659338 4. 0000000054600000-000000005465ffff: BL31
9380 13:08:26.663270 5. 0000000054660000-00000000ffe63fff: RAM
9381 13:08:26.666047 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9382 13:08:26.672534 7. 0000000100000000-000000023fffffff: RAM
9383 13:08:26.672923 Passing 5 GPIOs to payload:
9384 13:08:26.679267 NAME | PORT | POLARITY | VALUE
9385 13:08:26.682615 EC in RW | 0x000000aa | low | undefined
9386 13:08:26.689647 EC interrupt | 0x00000005 | low | undefined
9387 13:08:26.692890 TPM interrupt | 0x000000ab | high | undefined
9388 13:08:26.695801 SD card detect | 0x00000011 | high | undefined
9389 13:08:26.702656 speaker enable | 0x00000093 | high | undefined
9390 13:08:26.706512 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9391 13:08:26.709625 in-header: 03 f9 00 00 02 00 00 00
9392 13:08:26.710111 in-data: 02 00
9393 13:08:26.712489 ADC[4]: Raw value=904726 ID=7
9394 13:08:26.716024 ADC[3]: Raw value=213441 ID=1
9395 13:08:26.716410 RAM Code: 0x71
9396 13:08:26.719361 ADC[6]: Raw value=75332 ID=0
9397 13:08:26.723017 ADC[5]: Raw value=212703 ID=1
9398 13:08:26.723415 SKU Code: 0x1
9399 13:08:26.729967 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 316f
9400 13:08:26.732845 coreboot table: 964 bytes.
9401 13:08:26.736555 IMD ROOT 0. 0xfffff000 0x00001000
9402 13:08:26.740009 IMD SMALL 1. 0xffffe000 0x00001000
9403 13:08:26.742808 RO MCACHE 2. 0xffffc000 0x00001104
9404 13:08:26.746505 CONSOLE 3. 0xfff7c000 0x00080000
9405 13:08:26.749921 FMAP 4. 0xfff7b000 0x00000452
9406 13:08:26.753349 TIME STAMP 5. 0xfff7a000 0x00000910
9407 13:08:26.756636 VBOOT WORK 6. 0xfff66000 0x00014000
9408 13:08:26.757025 RAMOOPS 7. 0xffe66000 0x00100000
9409 13:08:26.759359 COREBOOT 8. 0xffe64000 0x00002000
9410 13:08:26.762672 IMD small region:
9411 13:08:26.766580 IMD ROOT 0. 0xffffec00 0x00000400
9412 13:08:26.769957 VPD 1. 0xffffeb80 0x0000006c
9413 13:08:26.773339 MMC STATUS 2. 0xffffeb60 0x00000004
9414 13:08:26.779667 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9415 13:08:26.786530 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9416 13:08:26.824885 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9417 13:08:26.828648 Checking segment from ROM address 0x40100000
9418 13:08:26.831801 Checking segment from ROM address 0x4010001c
9419 13:08:26.838248 Loading segment from ROM address 0x40100000
9420 13:08:26.838657 code (compression=0)
9421 13:08:26.848600 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9422 13:08:26.854903 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9423 13:08:26.855308 it's not compressed!
9424 13:08:26.861518 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9425 13:08:26.868072 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9426 13:08:26.885621 Loading segment from ROM address 0x4010001c
9427 13:08:26.886116 Entry Point 0x80000000
9428 13:08:26.888941 Loaded segments
9429 13:08:26.892365 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9430 13:08:26.898956 Jumping to boot code at 0x80000000(0xffe64000)
9431 13:08:26.905483 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9432 13:08:26.911921 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9433 13:08:26.919784 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9434 13:08:26.923324 Checking segment from ROM address 0x40100000
9435 13:08:26.926692 Checking segment from ROM address 0x4010001c
9436 13:08:26.932847 Loading segment from ROM address 0x40100000
9437 13:08:26.933249 code (compression=1)
9438 13:08:26.939910 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9439 13:08:26.949797 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9440 13:08:26.950234 using LZMA
9441 13:08:26.957987 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9442 13:08:26.964734 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9443 13:08:26.967922 Loading segment from ROM address 0x4010001c
9444 13:08:26.968326 Entry Point 0x54601000
9445 13:08:26.971595 Loaded segments
9446 13:08:26.974439 NOTICE: MT8192 bl31_setup
9447 13:08:26.981656 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9448 13:08:26.984952 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9449 13:08:26.988191 WARNING: region 0:
9450 13:08:26.991920 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9451 13:08:26.992408 WARNING: region 1:
9452 13:08:26.998556 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9453 13:08:27.001652 WARNING: region 2:
9454 13:08:27.004732 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9455 13:08:27.008674 WARNING: region 3:
9456 13:08:27.012098 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9457 13:08:27.014861 WARNING: region 4:
9458 13:08:27.021906 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9459 13:08:27.022440 WARNING: region 5:
9460 13:08:27.025126 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9461 13:08:27.028393 WARNING: region 6:
9462 13:08:27.032242 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9463 13:08:27.035399 WARNING: region 7:
9464 13:08:27.037979 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9465 13:08:27.045723 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9466 13:08:27.048131 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9467 13:08:27.051430 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9468 13:08:27.058141 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9469 13:08:27.061804 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9470 13:08:27.064949 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9471 13:08:27.071412 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9472 13:08:27.074736 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9473 13:08:27.081633 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9474 13:08:27.084517 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9475 13:08:27.087898 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9476 13:08:27.094583 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9477 13:08:27.097755 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9478 13:08:27.101279 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9479 13:08:27.107910 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9480 13:08:27.111609 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9481 13:08:27.118103 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9482 13:08:27.121288 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9483 13:08:27.124584 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9484 13:08:27.131434 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9485 13:08:27.134873 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9486 13:08:27.138156 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9487 13:08:27.144668 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9488 13:08:27.148053 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9489 13:08:27.154807 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9490 13:08:27.157946 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9491 13:08:27.164738 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9492 13:08:27.168103 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9493 13:08:27.171772 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9494 13:08:27.177959 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9495 13:08:27.181136 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9496 13:08:27.184856 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9497 13:08:27.191492 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9498 13:08:27.194828 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9499 13:08:27.198238 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9500 13:08:27.201833 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9501 13:08:27.208067 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9502 13:08:27.211597 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9503 13:08:27.214870 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9504 13:08:27.217921 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9505 13:08:27.224352 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9506 13:08:27.227664 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9507 13:08:27.231035 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9508 13:08:27.234255 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9509 13:08:27.240801 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9510 13:08:27.244267 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9511 13:08:27.247448 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9512 13:08:27.254184 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9513 13:08:27.257769 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9514 13:08:27.261106 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9515 13:08:27.267567 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9516 13:08:27.270797 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9517 13:08:27.277232 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9518 13:08:27.281069 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9519 13:08:27.287504 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9520 13:08:27.290844 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9521 13:08:27.294406 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9522 13:08:27.301217 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9523 13:08:27.304000 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9524 13:08:27.310812 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9525 13:08:27.314044 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9526 13:08:27.320487 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9527 13:08:27.323890 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9528 13:08:27.330806 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9529 13:08:27.333973 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9530 13:08:27.337370 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9531 13:08:27.344045 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9532 13:08:27.347274 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9533 13:08:27.353702 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9534 13:08:27.357182 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9535 13:08:27.360771 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9536 13:08:27.367570 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9537 13:08:27.370334 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9538 13:08:27.377669 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9539 13:08:27.380646 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9540 13:08:27.387055 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9541 13:08:27.390683 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9542 13:08:27.397265 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9543 13:08:27.400716 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9544 13:08:27.403916 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9545 13:08:27.410555 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9546 13:08:27.414208 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9547 13:08:27.420652 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9548 13:08:27.423646 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9549 13:08:27.430224 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9550 13:08:27.433671 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9551 13:08:27.437036 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9552 13:08:27.444045 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9553 13:08:27.447442 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9554 13:08:27.453413 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9555 13:08:27.457417 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9556 13:08:27.463618 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9557 13:08:27.466807 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9558 13:08:27.470062 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9559 13:08:27.476960 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9560 13:08:27.480476 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9561 13:08:27.487264 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9562 13:08:27.490562 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9563 13:08:27.493856 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9564 13:08:27.496972 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9565 13:08:27.503301 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9566 13:08:27.506718 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9567 13:08:27.509892 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9568 13:08:27.516809 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9569 13:08:27.520342 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9570 13:08:27.523814 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9571 13:08:27.530131 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9572 13:08:27.533646 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9573 13:08:27.540128 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9574 13:08:27.543523 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9575 13:08:27.547002 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9576 13:08:27.553735 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9577 13:08:27.557027 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9578 13:08:27.563691 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9579 13:08:27.566830 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9580 13:08:27.569910 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9581 13:08:27.576518 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9582 13:08:27.579902 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9583 13:08:27.583517 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9584 13:08:27.590377 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9585 13:08:27.593582 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9586 13:08:27.597058 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9587 13:08:27.600462 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9588 13:08:27.607183 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9589 13:08:27.610258 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9590 13:08:27.613564 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9591 13:08:27.620346 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9592 13:08:27.623712 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9593 13:08:27.630430 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9594 13:08:27.633425 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9595 13:08:27.636662 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9596 13:08:27.643115 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9597 13:08:27.647203 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9598 13:08:27.653617 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9599 13:08:27.656725 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9600 13:08:27.660185 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9601 13:08:27.666737 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9602 13:08:27.670386 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9603 13:08:27.673330 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9604 13:08:27.680246 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9605 13:08:27.683289 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9606 13:08:27.689813 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9607 13:08:27.693364 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9608 13:08:27.696520 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9609 13:08:27.703258 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9610 13:08:27.706618 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9611 13:08:27.709997 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9612 13:08:27.716485 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9613 13:08:27.720317 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9614 13:08:27.727027 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9615 13:08:27.730427 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9616 13:08:27.733155 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9617 13:08:27.739877 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9618 13:08:27.743641 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9619 13:08:27.750373 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9620 13:08:27.753717 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9621 13:08:27.757224 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9622 13:08:27.763438 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9623 13:08:27.766920 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9624 13:08:27.770332 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9625 13:08:27.777062 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9626 13:08:27.780338 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9627 13:08:27.786815 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9628 13:08:27.789960 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9629 13:08:27.793651 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9630 13:08:27.800208 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9631 13:08:27.803105 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9632 13:08:27.809916 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9633 13:08:27.813300 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9634 13:08:27.816695 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9635 13:08:27.823603 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9636 13:08:27.826872 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9637 13:08:27.830304 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9638 13:08:27.836890 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9639 13:08:27.840262 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9640 13:08:27.846910 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9641 13:08:27.850141 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9642 13:08:27.853310 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9643 13:08:27.860058 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9644 13:08:27.863586 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9645 13:08:27.870363 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9646 13:08:27.873836 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9647 13:08:27.876570 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9648 13:08:27.883535 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9649 13:08:27.886869 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9650 13:08:27.893572 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9651 13:08:27.896816 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9652 13:08:27.900221 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9653 13:08:27.906261 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9654 13:08:27.909622 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9655 13:08:27.916558 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9656 13:08:27.920031 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9657 13:08:27.923214 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9658 13:08:27.930273 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9659 13:08:27.933238 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9660 13:08:27.939977 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9661 13:08:27.943460 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9662 13:08:27.946881 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9663 13:08:27.953411 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9664 13:08:27.956616 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9665 13:08:27.963384 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9666 13:08:27.966383 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9667 13:08:27.969815 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9668 13:08:27.976518 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9669 13:08:27.979734 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9670 13:08:27.986410 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9671 13:08:27.989854 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9672 13:08:27.996810 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9673 13:08:27.999514 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9674 13:08:28.002902 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9675 13:08:28.010165 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9676 13:08:28.012787 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9677 13:08:28.019444 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9678 13:08:28.022752 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9679 13:08:28.026622 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9680 13:08:28.033440 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9681 13:08:28.036790 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9682 13:08:28.042772 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9683 13:08:28.045984 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9684 13:08:28.052829 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9685 13:08:28.056640 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9686 13:08:28.059655 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9687 13:08:28.066490 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9688 13:08:28.069542 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9689 13:08:28.076076 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9690 13:08:28.079685 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9691 13:08:28.083042 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9692 13:08:28.089557 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9693 13:08:28.092518 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9694 13:08:28.096571 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9695 13:08:28.102825 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9696 13:08:28.106148 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9697 13:08:28.109486 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9698 13:08:28.112765 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9699 13:08:28.119494 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9700 13:08:28.122829 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9701 13:08:28.129565 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9702 13:08:28.132900 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9703 13:08:28.136309 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9704 13:08:28.143030 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9705 13:08:28.146270 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9706 13:08:28.149426 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9707 13:08:28.156151 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9708 13:08:28.159531 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9709 13:08:28.163083 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9710 13:08:28.169562 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9711 13:08:28.172844 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9712 13:08:28.179541 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9713 13:08:28.182995 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9714 13:08:28.186359 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9715 13:08:28.192371 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9716 13:08:28.196115 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9717 13:08:28.199207 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9718 13:08:28.206085 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9719 13:08:28.209184 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9720 13:08:28.212861 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9721 13:08:28.219307 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9722 13:08:28.223118 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9723 13:08:28.225619 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9724 13:08:28.232429 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9725 13:08:28.236322 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9726 13:08:28.242290 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9727 13:08:28.245823 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9728 13:08:28.249114 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9729 13:08:28.255632 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9730 13:08:28.259021 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9731 13:08:28.262434 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9732 13:08:28.268953 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9733 13:08:28.272314 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9734 13:08:28.276027 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9735 13:08:28.279245 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9736 13:08:28.285896 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9737 13:08:28.289412 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9738 13:08:28.292660 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9739 13:08:28.296087 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9740 13:08:28.302206 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9741 13:08:28.306285 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9742 13:08:28.308960 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9743 13:08:28.312401 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9744 13:08:28.319091 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9745 13:08:28.322365 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9746 13:08:28.325528 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9747 13:08:28.332604 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9748 13:08:28.335744 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9749 13:08:28.339346 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9750 13:08:28.345709 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9751 13:08:28.348713 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9752 13:08:28.355327 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9753 13:08:28.359237 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9754 13:08:28.362473 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9755 13:08:28.369186 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9756 13:08:28.372005 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9757 13:08:28.379384 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9758 13:08:28.382421 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9759 13:08:28.389235 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9760 13:08:28.392667 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9761 13:08:28.396032 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9762 13:08:28.402262 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9763 13:08:28.405626 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9764 13:08:28.412354 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9765 13:08:28.415791 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9766 13:08:28.419157 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9767 13:08:28.425314 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9768 13:08:28.428693 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9769 13:08:28.435530 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9770 13:08:28.438855 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9771 13:08:28.442277 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9772 13:08:28.448785 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9773 13:08:28.452083 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9774 13:08:28.458459 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9775 13:08:28.462186 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9776 13:08:28.465351 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9777 13:08:28.472251 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9778 13:08:28.475254 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9779 13:08:28.481577 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9780 13:08:28.484864 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9781 13:08:28.492178 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9782 13:08:28.495309 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9783 13:08:28.498440 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9784 13:08:28.505364 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9785 13:08:28.508638 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9786 13:08:28.511468 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9787 13:08:28.518220 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9788 13:08:28.521564 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9789 13:08:28.528534 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9790 13:08:28.531383 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9791 13:08:28.538435 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9792 13:08:28.541864 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9793 13:08:28.545510 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9794 13:08:28.551354 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9795 13:08:28.554594 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9796 13:08:28.561415 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9797 13:08:28.564981 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9798 13:08:28.568420 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9799 13:08:28.574931 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9800 13:08:28.578574 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9801 13:08:28.584581 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9802 13:08:28.588262 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9803 13:08:28.591316 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9804 13:08:28.598462 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9805 13:08:28.601340 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9806 13:08:28.608234 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9807 13:08:28.611518 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9808 13:08:28.617761 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9809 13:08:28.621116 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9810 13:08:28.625003 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9811 13:08:28.631425 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9812 13:08:28.634993 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9813 13:08:28.641258 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9814 13:08:28.644863 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9815 13:08:28.648178 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9816 13:08:28.654634 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9817 13:08:28.657814 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9818 13:08:28.664852 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9819 13:08:28.667651 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9820 13:08:28.671029 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9821 13:08:28.677990 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9822 13:08:28.681471 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9823 13:08:28.687734 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9824 13:08:28.690873 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9825 13:08:28.697972 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9826 13:08:28.701214 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9827 13:08:28.704627 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9828 13:08:28.711274 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9829 13:08:28.714298 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9830 13:08:28.720817 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9831 13:08:28.724508 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9832 13:08:28.731099 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9833 13:08:28.734301 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9834 13:08:28.737870 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9835 13:08:28.744152 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9836 13:08:28.747401 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9837 13:08:28.754537 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9838 13:08:28.757889 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9839 13:08:28.764424 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9840 13:08:28.767709 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9841 13:08:28.774505 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9842 13:08:28.777816 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9843 13:08:28.781236 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9844 13:08:28.787435 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9845 13:08:28.790819 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9846 13:08:28.797547 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9847 13:08:28.800834 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9848 13:08:28.807922 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9849 13:08:28.811349 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9850 13:08:28.814053 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9851 13:08:28.820862 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9852 13:08:28.824315 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9853 13:08:28.830752 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9854 13:08:28.833993 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9855 13:08:28.840755 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9856 13:08:28.844401 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9857 13:08:28.847383 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9858 13:08:28.854337 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9859 13:08:28.857398 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9860 13:08:28.863970 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9861 13:08:28.867206 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9862 13:08:28.874205 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9863 13:08:28.877737 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9864 13:08:28.880878 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9865 13:08:28.887690 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9866 13:08:28.891085 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9867 13:08:28.894469 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9868 13:08:28.900644 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9869 13:08:28.903923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9870 13:08:28.910653 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9871 13:08:28.913803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9872 13:08:28.920485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9873 13:08:28.923873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9874 13:08:28.930725 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9875 13:08:28.934117 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9876 13:08:28.940683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9877 13:08:28.944002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9878 13:08:28.950846 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9879 13:08:28.954293 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9880 13:08:28.960533 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9881 13:08:28.963843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9882 13:08:28.970382 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9883 13:08:28.973767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9884 13:08:28.981044 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9885 13:08:28.983801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9886 13:08:28.990251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9887 13:08:28.993733 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9888 13:08:29.000099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9889 13:08:29.003548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9890 13:08:29.009994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9891 13:08:29.013733 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9892 13:08:29.020288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9893 13:08:29.023430 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9894 13:08:29.030017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9895 13:08:29.033341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9896 13:08:29.040249 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9897 13:08:29.043551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9898 13:08:29.050257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9899 13:08:29.053733 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9900 13:08:29.053825 INFO: [APUAPC] vio 0
9901 13:08:29.061156 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9902 13:08:29.064666 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9903 13:08:29.067923 INFO: [APUAPC] D0_APC_0: 0x400510
9904 13:08:29.071277 INFO: [APUAPC] D0_APC_1: 0x0
9905 13:08:29.074140 INFO: [APUAPC] D0_APC_2: 0x1540
9906 13:08:29.077415 INFO: [APUAPC] D0_APC_3: 0x0
9907 13:08:29.080871 INFO: [APUAPC] D1_APC_0: 0xffffffff
9908 13:08:29.084302 INFO: [APUAPC] D1_APC_1: 0xffffffff
9909 13:08:29.087652 INFO: [APUAPC] D1_APC_2: 0x3fffff
9910 13:08:29.091071 INFO: [APUAPC] D1_APC_3: 0x0
9911 13:08:29.094538 INFO: [APUAPC] D2_APC_0: 0xffffffff
9912 13:08:29.097896 INFO: [APUAPC] D2_APC_1: 0xffffffff
9913 13:08:29.101228 INFO: [APUAPC] D2_APC_2: 0x3fffff
9914 13:08:29.104433 INFO: [APUAPC] D2_APC_3: 0x0
9915 13:08:29.107435 INFO: [APUAPC] D3_APC_0: 0xffffffff
9916 13:08:29.110842 INFO: [APUAPC] D3_APC_1: 0xffffffff
9917 13:08:29.114313 INFO: [APUAPC] D3_APC_2: 0x3fffff
9918 13:08:29.114404 INFO: [APUAPC] D3_APC_3: 0x0
9919 13:08:29.120968 INFO: [APUAPC] D4_APC_0: 0xffffffff
9920 13:08:29.124164 INFO: [APUAPC] D4_APC_1: 0xffffffff
9921 13:08:29.127831 INFO: [APUAPC] D4_APC_2: 0x3fffff
9922 13:08:29.127919 INFO: [APUAPC] D4_APC_3: 0x0
9923 13:08:29.130794 INFO: [APUAPC] D5_APC_0: 0xffffffff
9924 13:08:29.137620 INFO: [APUAPC] D5_APC_1: 0xffffffff
9925 13:08:29.140798 INFO: [APUAPC] D5_APC_2: 0x3fffff
9926 13:08:29.140873 INFO: [APUAPC] D5_APC_3: 0x0
9927 13:08:29.144440 INFO: [APUAPC] D6_APC_0: 0xffffffff
9928 13:08:29.147288 INFO: [APUAPC] D6_APC_1: 0xffffffff
9929 13:08:29.150884 INFO: [APUAPC] D6_APC_2: 0x3fffff
9930 13:08:29.153829 INFO: [APUAPC] D6_APC_3: 0x0
9931 13:08:29.157307 INFO: [APUAPC] D7_APC_0: 0xffffffff
9932 13:08:29.160591 INFO: [APUAPC] D7_APC_1: 0xffffffff
9933 13:08:29.164024 INFO: [APUAPC] D7_APC_2: 0x3fffff
9934 13:08:29.167371 INFO: [APUAPC] D7_APC_3: 0x0
9935 13:08:29.170630 INFO: [APUAPC] D8_APC_0: 0xffffffff
9936 13:08:29.173871 INFO: [APUAPC] D8_APC_1: 0xffffffff
9937 13:08:29.177345 INFO: [APUAPC] D8_APC_2: 0x3fffff
9938 13:08:29.180622 INFO: [APUAPC] D8_APC_3: 0x0
9939 13:08:29.184447 INFO: [APUAPC] D9_APC_0: 0xffffffff
9940 13:08:29.187211 INFO: [APUAPC] D9_APC_1: 0xffffffff
9941 13:08:29.190594 INFO: [APUAPC] D9_APC_2: 0x3fffff
9942 13:08:29.193901 INFO: [APUAPC] D9_APC_3: 0x0
9943 13:08:29.197266 INFO: [APUAPC] D10_APC_0: 0xffffffff
9944 13:08:29.200690 INFO: [APUAPC] D10_APC_1: 0xffffffff
9945 13:08:29.204029 INFO: [APUAPC] D10_APC_2: 0x3fffff
9946 13:08:29.207484 INFO: [APUAPC] D10_APC_3: 0x0
9947 13:08:29.211023 INFO: [APUAPC] D11_APC_0: 0xffffffff
9948 13:08:29.214319 INFO: [APUAPC] D11_APC_1: 0xffffffff
9949 13:08:29.217768 INFO: [APUAPC] D11_APC_2: 0x3fffff
9950 13:08:29.220865 INFO: [APUAPC] D11_APC_3: 0x0
9951 13:08:29.224043 INFO: [APUAPC] D12_APC_0: 0xffffffff
9952 13:08:29.228066 INFO: [APUAPC] D12_APC_1: 0xffffffff
9953 13:08:29.230844 INFO: [APUAPC] D12_APC_2: 0x3fffff
9954 13:08:29.234313 INFO: [APUAPC] D12_APC_3: 0x0
9955 13:08:29.237681 INFO: [APUAPC] D13_APC_0: 0xffffffff
9956 13:08:29.241128 INFO: [APUAPC] D13_APC_1: 0xffffffff
9957 13:08:29.244469 INFO: [APUAPC] D13_APC_2: 0x3fffff
9958 13:08:29.247786 INFO: [APUAPC] D13_APC_3: 0x0
9959 13:08:29.251128 INFO: [APUAPC] D14_APC_0: 0xffffffff
9960 13:08:29.254422 INFO: [APUAPC] D14_APC_1: 0xffffffff
9961 13:08:29.257542 INFO: [APUAPC] D14_APC_2: 0x3fffff
9962 13:08:29.261137 INFO: [APUAPC] D14_APC_3: 0x0
9963 13:08:29.264394 INFO: [APUAPC] D15_APC_0: 0xffffffff
9964 13:08:29.267414 INFO: [APUAPC] D15_APC_1: 0xffffffff
9965 13:08:29.271171 INFO: [APUAPC] D15_APC_2: 0x3fffff
9966 13:08:29.274282 INFO: [APUAPC] D15_APC_3: 0x0
9967 13:08:29.277661 INFO: [APUAPC] APC_CON: 0x4
9968 13:08:29.280861 INFO: [NOCDAPC] D0_APC_0: 0x0
9969 13:08:29.284313 INFO: [NOCDAPC] D0_APC_1: 0x0
9970 13:08:29.284388 INFO: [NOCDAPC] D1_APC_0: 0x0
9971 13:08:29.287771 INFO: [NOCDAPC] D1_APC_1: 0xfff
9972 13:08:29.290831 INFO: [NOCDAPC] D2_APC_0: 0x0
9973 13:08:29.294413 INFO: [NOCDAPC] D2_APC_1: 0xfff
9974 13:08:29.297646 INFO: [NOCDAPC] D3_APC_0: 0x0
9975 13:08:29.300869 INFO: [NOCDAPC] D3_APC_1: 0xfff
9976 13:08:29.304177 INFO: [NOCDAPC] D4_APC_0: 0x0
9977 13:08:29.307511 INFO: [NOCDAPC] D4_APC_1: 0xfff
9978 13:08:29.310940 INFO: [NOCDAPC] D5_APC_0: 0x0
9979 13:08:29.314287 INFO: [NOCDAPC] D5_APC_1: 0xfff
9980 13:08:29.314362 INFO: [NOCDAPC] D6_APC_0: 0x0
9981 13:08:29.317708 INFO: [NOCDAPC] D6_APC_1: 0xfff
9982 13:08:29.321008 INFO: [NOCDAPC] D7_APC_0: 0x0
9983 13:08:29.324284 INFO: [NOCDAPC] D7_APC_1: 0xfff
9984 13:08:29.327629 INFO: [NOCDAPC] D8_APC_0: 0x0
9985 13:08:29.330883 INFO: [NOCDAPC] D8_APC_1: 0xfff
9986 13:08:29.334501 INFO: [NOCDAPC] D9_APC_0: 0x0
9987 13:08:29.337943 INFO: [NOCDAPC] D9_APC_1: 0xfff
9988 13:08:29.341420 INFO: [NOCDAPC] D10_APC_0: 0x0
9989 13:08:29.344744 INFO: [NOCDAPC] D10_APC_1: 0xfff
9990 13:08:29.347483 INFO: [NOCDAPC] D11_APC_0: 0x0
9991 13:08:29.350909 INFO: [NOCDAPC] D11_APC_1: 0xfff
9992 13:08:29.350986 INFO: [NOCDAPC] D12_APC_0: 0x0
9993 13:08:29.354237 INFO: [NOCDAPC] D12_APC_1: 0xfff
9994 13:08:29.357658 INFO: [NOCDAPC] D13_APC_0: 0x0
9995 13:08:29.361042 INFO: [NOCDAPC] D13_APC_1: 0xfff
9996 13:08:29.364548 INFO: [NOCDAPC] D14_APC_0: 0x0
9997 13:08:29.368103 INFO: [NOCDAPC] D14_APC_1: 0xfff
9998 13:08:29.370765 INFO: [NOCDAPC] D15_APC_0: 0x0
9999 13:08:29.374041 INFO: [NOCDAPC] D15_APC_1: 0xfff
10000 13:08:29.377893 INFO: [NOCDAPC] APC_CON: 0x4
10001 13:08:29.380593 INFO: [APUAPC] set_apusys_apc done
10002 13:08:29.384614 INFO: [DEVAPC] devapc_init done
10003 13:08:29.387285 INFO: GICv3 without legacy support detected.
10004 13:08:29.391210 INFO: ARM GICv3 driver initialized in EL3
10005 13:08:29.394530 INFO: Maximum SPI INTID supported: 639
10006 13:08:29.401253 INFO: BL31: Initializing runtime services
10007 13:08:29.404537 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10008 13:08:29.407542 INFO: SPM: enable CPC mode
10009 13:08:29.413998 INFO: mcdi ready for mcusys-off-idle and system suspend
10010 13:08:29.417841 INFO: BL31: Preparing for EL3 exit to normal world
10011 13:08:29.421118 INFO: Entry point address = 0x80000000
10012 13:08:29.424163 INFO: SPSR = 0x8
10013 13:08:29.428916
10014 13:08:29.428992
10015 13:08:29.429067
10016 13:08:29.432699 Starting depthcharge on Spherion...
10017 13:08:29.432775
10018 13:08:29.432851 Wipe memory regions:
10019 13:08:29.432922
10020 13:08:29.433630 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10021 13:08:29.433746 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10022 13:08:29.433850 Setting prompt string to ['asurada:']
10023 13:08:29.433951 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10024 13:08:29.435854 [0x00000040000000, 0x00000054600000)
10025 13:08:29.558196
10026 13:08:29.558340 [0x00000054660000, 0x00000080000000)
10027 13:08:29.818623
10028 13:08:29.818755 [0x000000821a7280, 0x000000ffe64000)
10029 13:08:30.563365
10030 13:08:30.563548 [0x00000100000000, 0x00000240000000)
10031 13:08:32.453096
10032 13:08:32.456359 Initializing XHCI USB controller at 0x11200000.
10033 13:08:33.494068
10034 13:08:33.497312 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10035 13:08:33.497398
10036 13:08:33.497461
10037 13:08:33.497722 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10038 13:08:33.497796 Sending line: 'tftpboot 192.168.201.1 14878991/tftp-deploy-74ffm5nz/kernel/image.itb 14878991/tftp-deploy-74ffm5nz/kernel/cmdline '
10040 13:08:33.598230 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10041 13:08:33.598327 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10042 13:08:33.602026 asurada: tftpboot 192.168.201.1 14878991/tftp-deploy-74ffm5nz/kernel/image.ittp-deploy-74ffm5nz/kernel/cmdline
10043 13:08:33.602105
10044 13:08:33.602166 Waiting for link
10045 13:08:33.760836
10046 13:08:33.760959 R8152: Initializing
10047 13:08:33.761024
10048 13:08:33.764032 Version 9 (ocp_data = 6010)
10049 13:08:33.764102
10050 13:08:33.767192 R8152: Done initializing
10051 13:08:33.767264
10052 13:08:33.767323 Adding net device
10053 13:08:35.715858
10054 13:08:35.716005 done.
10055 13:08:35.716105
10056 13:08:35.716190 MAC: 00:e0:4c:78:7a:aa
10057 13:08:35.716288
10058 13:08:35.719490 Sending DHCP discover... done.
10059 13:08:35.719586
10060 13:08:43.013993 Waiting for reply... done.
10061 13:08:43.014200
10062 13:08:43.014390 Sending DHCP request... done.
10063 13:08:43.017620
10064 13:08:43.022473 Waiting for reply... done.
10065 13:08:43.022550
10066 13:08:43.022609 My ip is 192.168.201.12
10067 13:08:43.022663
10068 13:08:43.025829 The DHCP server ip is 192.168.201.1
10069 13:08:43.025905
10070 13:08:43.032494 TFTP server IP predefined by user: 192.168.201.1
10071 13:08:43.032632
10072 13:08:43.039272 Bootfile predefined by user: 14878991/tftp-deploy-74ffm5nz/kernel/image.itb
10073 13:08:43.039383
10074 13:08:43.039499 Sending tftp read request... done.
10075 13:08:43.042325
10076 13:08:43.045930 Waiting for the transfer...
10077 13:08:43.046069
10078 13:08:43.310587 00000000 ################################################################
10079 13:08:43.310707
10080 13:08:43.559072 00080000 ################################################################
10081 13:08:43.559193
10082 13:08:43.812518 00100000 ################################################################
10083 13:08:43.812722
10084 13:08:44.068942 00180000 ################################################################
10085 13:08:44.069071
10086 13:08:44.330757 00200000 ################################################################
10087 13:08:44.330913
10088 13:08:44.688968 00280000 ################################################################
10089 13:08:44.689108
10090 13:08:45.030060 00300000 ################################################################
10091 13:08:45.030203
10092 13:08:45.368609 00380000 ################################################################
10093 13:08:45.368752
10094 13:08:45.696778 00400000 ################################################################
10095 13:08:45.696897
10096 13:08:45.993533 00480000 ################################################################
10097 13:08:45.993650
10098 13:08:46.328193 00500000 ################################################################
10099 13:08:46.328345
10100 13:08:46.666158 00580000 ################################################################
10101 13:08:46.666282
10102 13:08:47.010494 00600000 ################################################################
10103 13:08:47.010649
10104 13:08:47.312984 00680000 ################################################################
10105 13:08:47.313104
10106 13:08:47.659891 00700000 ################################################################
10107 13:08:47.660011
10108 13:08:48.005752 00780000 ################################################################
10109 13:08:48.005914
10110 13:08:48.344800 00800000 ################################################################
10111 13:08:48.344947
10112 13:08:48.610599 00880000 ################################################################
10113 13:08:48.610746
10114 13:08:48.875816 00900000 ################################################################
10115 13:08:48.875963
10116 13:08:49.134216 00980000 ################################################################
10117 13:08:49.134359
10118 13:08:49.385495 00a00000 ################################################################
10119 13:08:49.385645
10120 13:08:49.642568 00a80000 ################################################################
10121 13:08:49.642715
10122 13:08:49.943632 00b00000 ################################################################
10123 13:08:49.943857
10124 13:08:50.289078 00b80000 ################################################################
10125 13:08:50.289239
10126 13:08:50.633017 00c00000 ################################################################
10127 13:08:50.633160
10128 13:08:50.977228 00c80000 ################################################################
10129 13:08:50.977380
10130 13:08:51.316704 00d00000 ################################################################
10131 13:08:51.316827
10132 13:08:51.656448 00d80000 ################################################################
10133 13:08:51.656564
10134 13:08:51.998512 00e00000 ################################################################
10135 13:08:51.998646
10136 13:08:52.338238 00e80000 ################################################################
10137 13:08:52.338387
10138 13:08:52.679662 00f00000 ################################################################
10139 13:08:52.679817
10140 13:08:53.016427 00f80000 ################################################################
10141 13:08:53.016576
10142 13:08:53.361042 01000000 ################################################################
10143 13:08:53.361183
10144 13:08:53.702787 01080000 ################################################################
10145 13:08:53.702935
10146 13:08:54.072589 01100000 ################################################################
10147 13:08:54.072735
10148 13:08:54.434634 01180000 ################################################################
10149 13:08:54.434771
10150 13:08:54.793956 01200000 ################################################################
10151 13:08:54.794097
10152 13:08:55.146976 01280000 ################################################################
10153 13:08:55.147107
10154 13:08:55.496395 01300000 ################################################################
10155 13:08:55.496550
10156 13:08:55.840570 01380000 ################################################################
10157 13:08:55.840726
10158 13:08:56.184354 01400000 ################################################################
10159 13:08:56.184502
10160 13:08:56.530731 01480000 ################################################################
10161 13:08:56.530874
10162 13:08:56.871822 01500000 ################################################################
10163 13:08:56.871937
10164 13:08:57.139244 01580000 ################################################################
10165 13:08:57.139366
10166 13:08:57.415490 01600000 ################################################################
10167 13:08:57.415613
10168 13:08:57.768860 01680000 ################################################################
10169 13:08:57.768975
10170 13:08:58.120635 01700000 ################################################################
10171 13:08:58.120763
10172 13:08:58.475785 01780000 ################################################################
10173 13:08:58.475911
10174 13:08:58.822727 01800000 ################################################################
10175 13:08:58.822863
10176 13:08:59.168218 01880000 ################################################################
10177 13:08:59.168361
10178 13:08:59.516528 01900000 ################################################################
10179 13:08:59.516697
10180 13:08:59.878400 01980000 ################################################################
10181 13:08:59.878520
10182 13:09:00.196991 01a00000 ################################################################
10183 13:09:00.197129
10184 13:09:00.454739 01a80000 ################################################################
10185 13:09:00.454882
10186 13:09:00.720163 01b00000 ################################################################
10187 13:09:00.720313
10188 13:09:01.062697 01b80000 ################################################################
10189 13:09:01.062844
10190 13:09:01.411777 01c00000 ################################################################
10191 13:09:01.411893
10192 13:09:01.763417 01c80000 ################################################################
10193 13:09:01.763555
10194 13:09:02.109060 01d00000 ################################################################
10195 13:09:02.109195
10196 13:09:02.455281 01d80000 ################################################################
10197 13:09:02.455429
10198 13:09:02.814228 01e00000 ################################################################
10199 13:09:02.814373
10200 13:09:03.161772 01e80000 ################################################################
10201 13:09:03.161912
10202 13:09:03.507546 01f00000 ################################################################
10203 13:09:03.507700
10204 13:09:03.808495 01f80000 ################################################################
10205 13:09:03.808617
10206 13:09:04.133441 02000000 ################################################################
10207 13:09:04.133565
10208 13:09:04.422736 02080000 ##################################################### done.
10209 13:09:04.422855
10210 13:09:04.426141 The bootfile was 34509338 bytes long.
10211 13:09:04.426244
10212 13:09:04.428955 Sending tftp read request... done.
10213 13:09:04.429033
10214 13:09:04.429093 Waiting for the transfer...
10215 13:09:04.429149
10216 13:09:04.432308 00000000 # done.
10217 13:09:04.432414
10218 13:09:04.439146 Command line loaded dynamically from TFTP file: 14878991/tftp-deploy-74ffm5nz/kernel/cmdline
10219 13:09:04.439250
10220 13:09:04.452692 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10221 13:09:04.452797
10222 13:09:04.456037 Loading FIT.
10223 13:09:04.456107
10224 13:09:04.459256 Image ramdisk-1 has 21345581 bytes.
10225 13:09:04.459349
10226 13:09:04.459433 Image fdt-1 has 47258 bytes.
10227 13:09:04.459514
10228 13:09:04.462514 Image kernel-1 has 13114469 bytes.
10229 13:09:04.462592
10230 13:09:04.472202 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10231 13:09:04.472304
10232 13:09:04.489098 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10233 13:09:04.489188
10234 13:09:04.495484 Choosing best match conf-1 for compat google,spherion-rev2.
10235 13:09:04.499212
10236 13:09:04.504617 Connected to device vid:did:rid of 1ae0:0028:00
10237 13:09:04.512688
10238 13:09:04.515808 tpm_get_response: command 0x17b, return code 0x0
10239 13:09:04.515917
10240 13:09:04.519097 ec_init: CrosEC protocol v3 supported (256, 248)
10241 13:09:04.522801
10242 13:09:04.526133 tpm_cleanup: add release locality here.
10243 13:09:04.526232
10244 13:09:04.526326 Shutting down all USB controllers.
10245 13:09:04.526412
10246 13:09:04.529605 Removing current net device
10247 13:09:04.529673
10248 13:09:04.536427 Exiting depthcharge with code 4 at timestamp: 64395378
10249 13:09:04.536509
10250 13:09:04.539614 LZMA decompressing kernel-1 to 0x821a6718
10251 13:09:04.539687
10252 13:09:04.542917 LZMA decompressing kernel-1 to 0x40000000
10253 13:09:06.158194
10254 13:09:06.158336 jumping to kernel
10255 13:09:06.158832 end: 2.2.4 bootloader-commands (duration 00:00:37) [common]
10256 13:09:06.158928 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10257 13:09:06.158999 Setting prompt string to ['Linux version [0-9]']
10258 13:09:06.159072 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10259 13:09:06.159154 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10260 13:09:06.239252
10261 13:09:06.242798 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10262 13:09:06.246097 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10263 13:09:06.246215 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10264 13:09:06.246311 Setting prompt string to []
10265 13:09:06.246414 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10266 13:09:06.246509 Using line separator: #'\n'#
10267 13:09:06.246588 No login prompt set.
10268 13:09:06.246673 Parsing kernel messages
10269 13:09:06.246753 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10270 13:09:06.246926 [login-action] Waiting for messages, (timeout 00:03:43)
10271 13:09:06.247010 Waiting using forced prompt support (timeout 00:01:52)
10272 13:09:06.265502 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j272990-arm64-gcc-12-defconfig-arm64-chromebook-fgzcq) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024
10273 13:09:06.268829 [ 0.000000] random: crng init done
10274 13:09:06.272322 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10275 13:09:06.275637 [ 0.000000] efi: UEFI not found.
10276 13:09:06.285680 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10277 13:09:06.292309 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10278 13:09:06.302216 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10279 13:09:06.312215 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10280 13:09:06.318936 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10281 13:09:06.321606 [ 0.000000] printk: bootconsole [mtk8250] enabled
10282 13:09:06.330093 [ 0.000000] NUMA: No NUMA configuration found
10283 13:09:06.336683 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10284 13:09:06.343299 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10285 13:09:06.343379 [ 0.000000] Zone ranges:
10286 13:09:06.349728 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10287 13:09:06.353037 [ 0.000000] DMA32 empty
10288 13:09:06.360139 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10289 13:09:06.362962 [ 0.000000] Movable zone start for each node
10290 13:09:06.366257 [ 0.000000] Early memory node ranges
10291 13:09:06.373402 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10292 13:09:06.379664 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10293 13:09:06.386525 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10294 13:09:06.393230 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10295 13:09:06.399655 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10296 13:09:06.406448 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10297 13:09:06.463226 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10298 13:09:06.469615 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10299 13:09:06.476338 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10300 13:09:06.479930 [ 0.000000] psci: probing for conduit method from DT.
10301 13:09:06.486220 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10302 13:09:06.489943 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10303 13:09:06.496313 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10304 13:09:06.499490 [ 0.000000] psci: SMC Calling Convention v1.2
10305 13:09:06.506061 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10306 13:09:06.509453 [ 0.000000] Detected VIPT I-cache on CPU0
10307 13:09:06.515901 [ 0.000000] CPU features: detected: GIC system register CPU interface
10308 13:09:06.523084 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10309 13:09:06.529397 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10310 13:09:06.536080 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10311 13:09:06.542729 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10312 13:09:06.552540 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10313 13:09:06.555867 [ 0.000000] alternatives: applying boot alternatives
10314 13:09:06.562668 [ 0.000000] Fallback order for Node 0: 0
10315 13:09:06.569365 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10316 13:09:06.572646 [ 0.000000] Policy zone: Normal
10317 13:09:06.585973 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10318 13:09:06.596294 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10319 13:09:06.607555 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10320 13:09:06.617417 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10321 13:09:06.624480 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10322 13:09:06.627528 <6>[ 0.000000] software IO TLB: area num 8.
10323 13:09:06.684703 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10324 13:09:06.833823 <6>[ 0.000000] Memory: 7943216K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 409552K reserved, 32768K cma-reserved)
10325 13:09:06.839869 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10326 13:09:06.847065 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10327 13:09:06.850451 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10328 13:09:06.856613 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10329 13:09:06.863576 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10330 13:09:06.866469 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10331 13:09:06.876775 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10332 13:09:06.883110 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10333 13:09:06.889569 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10334 13:09:06.896225 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10335 13:09:06.899393 <6>[ 0.000000] GICv3: 608 SPIs implemented
10336 13:09:06.902723 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10337 13:09:06.909189 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10338 13:09:06.912714 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10339 13:09:06.919248 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10340 13:09:06.932672 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10341 13:09:06.945995 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10342 13:09:06.952482 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10343 13:09:06.959888 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10344 13:09:06.973406 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10345 13:09:06.979613 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10346 13:09:06.986485 <6>[ 0.009232] Console: colour dummy device 80x25
10347 13:09:06.996708 <6>[ 0.013991] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10348 13:09:07.003080 <6>[ 0.024433] pid_max: default: 32768 minimum: 301
10349 13:09:07.006192 <6>[ 0.029335] LSM: Security Framework initializing
10350 13:09:07.012795 <6>[ 0.034302] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10351 13:09:07.022820 <6>[ 0.042115] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10352 13:09:07.033039 <6>[ 0.051543] cblist_init_generic: Setting adjustable number of callback queues.
10353 13:09:07.036145 <6>[ 0.059030] cblist_init_generic: Setting shift to 3 and lim to 1.
10354 13:09:07.046115 <6>[ 0.065370] cblist_init_generic: Setting adjustable number of callback queues.
10355 13:09:07.052633 <6>[ 0.072797] cblist_init_generic: Setting shift to 3 and lim to 1.
10356 13:09:07.056583 <6>[ 0.079197] rcu: Hierarchical SRCU implementation.
10357 13:09:07.062541 <6>[ 0.084244] rcu: Max phase no-delay instances is 1000.
10358 13:09:07.069125 <6>[ 0.091264] EFI services will not be available.
10359 13:09:07.072625 <6>[ 0.096252] smp: Bringing up secondary CPUs ...
10360 13:09:07.081352 <6>[ 0.101302] Detected VIPT I-cache on CPU1
10361 13:09:07.087840 <6>[ 0.101372] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10362 13:09:07.094126 <6>[ 0.101404] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10363 13:09:07.097614 <6>[ 0.101748] Detected VIPT I-cache on CPU2
10364 13:09:07.104321 <6>[ 0.101803] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10365 13:09:07.111011 <6>[ 0.101821] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10366 13:09:07.117583 <6>[ 0.102086] Detected VIPT I-cache on CPU3
10367 13:09:07.123940 <6>[ 0.102135] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10368 13:09:07.130631 <6>[ 0.102150] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10369 13:09:07.133829 <6>[ 0.102455] CPU features: detected: Spectre-v4
10370 13:09:07.141011 <6>[ 0.102461] CPU features: detected: Spectre-BHB
10371 13:09:07.144092 <6>[ 0.102467] Detected PIPT I-cache on CPU4
10372 13:09:07.150688 <6>[ 0.102529] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10373 13:09:07.157335 <6>[ 0.102546] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10374 13:09:07.163856 <6>[ 0.102841] Detected PIPT I-cache on CPU5
10375 13:09:07.170704 <6>[ 0.102904] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10376 13:09:07.177406 <6>[ 0.102922] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10377 13:09:07.180789 <6>[ 0.103201] Detected PIPT I-cache on CPU6
10378 13:09:07.187456 <6>[ 0.103267] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10379 13:09:07.194126 <6>[ 0.103282] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10380 13:09:07.200818 <6>[ 0.103582] Detected PIPT I-cache on CPU7
10381 13:09:07.207473 <6>[ 0.103647] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10382 13:09:07.213962 <6>[ 0.103663] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10383 13:09:07.217402 <6>[ 0.103711] smp: Brought up 1 node, 8 CPUs
10384 13:09:07.224333 <6>[ 0.245144] SMP: Total of 8 processors activated.
10385 13:09:07.227229 <6>[ 0.250065] CPU features: detected: 32-bit EL0 Support
10386 13:09:07.237517 <6>[ 0.255461] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10387 13:09:07.244254 <6>[ 0.264261] CPU features: detected: Common not Private translations
10388 13:09:07.247600 <6>[ 0.270737] CPU features: detected: CRC32 instructions
10389 13:09:07.253726 <6>[ 0.276122] CPU features: detected: RCpc load-acquire (LDAPR)
10390 13:09:07.260759 <6>[ 0.282082] CPU features: detected: LSE atomic instructions
10391 13:09:07.267147 <6>[ 0.287863] CPU features: detected: Privileged Access Never
10392 13:09:07.270863 <6>[ 0.293643] CPU features: detected: RAS Extension Support
10393 13:09:07.277049 <6>[ 0.299251] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10394 13:09:07.283673 <6>[ 0.306471] CPU: All CPU(s) started at EL2
10395 13:09:07.290620 <6>[ 0.310787] alternatives: applying system-wide alternatives
10396 13:09:07.299069 <6>[ 0.321668] devtmpfs: initialized
10397 13:09:07.311573 <6>[ 0.330556] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10398 13:09:07.321041 <6>[ 0.340517] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10399 13:09:07.327569 <6>[ 0.348773] pinctrl core: initialized pinctrl subsystem
10400 13:09:07.330964 <6>[ 0.355441] DMI not present or invalid.
10401 13:09:07.337249 <6>[ 0.359861] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10402 13:09:07.347216 <6>[ 0.366743] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10403 13:09:07.353943 <6>[ 0.374330] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10404 13:09:07.364082 <6>[ 0.382559] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10405 13:09:07.367458 <6>[ 0.390805] audit: initializing netlink subsys (disabled)
10406 13:09:07.377839 <5>[ 0.396507] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10407 13:09:07.383791 <6>[ 0.397237] thermal_sys: Registered thermal governor 'step_wise'
10408 13:09:07.390455 <6>[ 0.404475] thermal_sys: Registered thermal governor 'power_allocator'
10409 13:09:07.394047 <6>[ 0.410728] cpuidle: using governor menu
10410 13:09:07.400508 <6>[ 0.421690] NET: Registered PF_QIPCRTR protocol family
10411 13:09:07.407492 <6>[ 0.427209] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10412 13:09:07.413919 <6>[ 0.434309] ASID allocator initialised with 32768 entries
10413 13:09:07.416637 <6>[ 0.440903] Serial: AMBA PL011 UART driver
10414 13:09:07.427669 <4>[ 0.450340] Trying to register duplicate clock ID: 134
10415 13:09:07.487445 <6>[ 0.513328] KASLR enabled
10416 13:09:07.501668 <6>[ 0.520944] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10417 13:09:07.508121 <6>[ 0.527961] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10418 13:09:07.514970 <6>[ 0.534447] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10419 13:09:07.521644 <6>[ 0.541451] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10420 13:09:07.528103 <6>[ 0.547938] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10421 13:09:07.534852 <6>[ 0.554943] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10422 13:09:07.541099 <6>[ 0.561430] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10423 13:09:07.547708 <6>[ 0.568437] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10424 13:09:07.551289 <6>[ 0.575905] ACPI: Interpreter disabled.
10425 13:09:07.560201 <6>[ 0.582339] iommu: Default domain type: Translated
10426 13:09:07.565941 <6>[ 0.587488] iommu: DMA domain TLB invalidation policy: strict mode
10427 13:09:07.569963 <5>[ 0.594139] SCSI subsystem initialized
10428 13:09:07.576269 <6>[ 0.598392] usbcore: registered new interface driver usbfs
10429 13:09:07.582663 <6>[ 0.604125] usbcore: registered new interface driver hub
10430 13:09:07.586155 <6>[ 0.609675] usbcore: registered new device driver usb
10431 13:09:07.592811 <6>[ 0.615801] pps_core: LinuxPPS API ver. 1 registered
10432 13:09:07.602938 <6>[ 0.620993] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10433 13:09:07.606151 <6>[ 0.630337] PTP clock support registered
10434 13:09:07.609466 <6>[ 0.634580] EDAC MC: Ver: 3.0.0
10435 13:09:07.616939 <6>[ 0.639782] FPGA manager framework
10436 13:09:07.620333 <6>[ 0.643462] Advanced Linux Sound Architecture Driver Initialized.
10437 13:09:07.624329 <6>[ 0.650260] vgaarb: loaded
10438 13:09:07.630999 <6>[ 0.653424] clocksource: Switched to clocksource arch_sys_counter
10439 13:09:07.637943 <5>[ 0.659865] VFS: Disk quotas dquot_6.6.0
10440 13:09:07.644132 <6>[ 0.664051] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10441 13:09:07.647466 <6>[ 0.671245] pnp: PnP ACPI: disabled
10442 13:09:07.655612 <6>[ 0.677971] NET: Registered PF_INET protocol family
10443 13:09:07.664809 <6>[ 0.683561] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10444 13:09:07.676732 <6>[ 0.695897] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10445 13:09:07.686310 <6>[ 0.704708] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10446 13:09:07.693512 <6>[ 0.712676] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10447 13:09:07.699584 <6>[ 0.721375] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10448 13:09:07.711912 <6>[ 0.731122] TCP: Hash tables configured (established 65536 bind 65536)
10449 13:09:07.718507 <6>[ 0.737992] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10450 13:09:07.724633 <6>[ 0.745188] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10451 13:09:07.731261 <6>[ 0.752890] NET: Registered PF_UNIX/PF_LOCAL protocol family
10452 13:09:07.738084 <6>[ 0.759044] RPC: Registered named UNIX socket transport module.
10453 13:09:07.741402 <6>[ 0.765197] RPC: Registered udp transport module.
10454 13:09:07.747806 <6>[ 0.770130] RPC: Registered tcp transport module.
10455 13:09:07.754416 <6>[ 0.775059] RPC: Registered tcp NFSv4.1 backchannel transport module.
10456 13:09:07.758031 <6>[ 0.781726] PCI: CLS 0 bytes, default 64
10457 13:09:07.761373 <6>[ 0.786084] Unpacking initramfs...
10458 13:09:07.771296 <6>[ 0.789801] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10459 13:09:07.778204 <6>[ 0.798424] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10460 13:09:07.784828 <6>[ 0.807221] kvm [1]: IPA Size Limit: 40 bits
10461 13:09:07.788125 <6>[ 0.811745] kvm [1]: GICv3: no GICV resource entry
10462 13:09:07.794791 <6>[ 0.816764] kvm [1]: disabling GICv2 emulation
10463 13:09:07.800865 <6>[ 0.821448] kvm [1]: GIC system register CPU interface enabled
10464 13:09:07.804122 <6>[ 0.827609] kvm [1]: vgic interrupt IRQ18
10465 13:09:07.811092 <6>[ 0.833496] kvm [1]: VHE mode initialized successfully
10466 13:09:07.817612 <5>[ 0.839865] Initialise system trusted keyrings
10467 13:09:07.824057 <6>[ 0.844659] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10468 13:09:07.831716 <6>[ 0.854638] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10469 13:09:07.838564 <5>[ 0.860997] NFS: Registering the id_resolver key type
10470 13:09:07.841926 <5>[ 0.866298] Key type id_resolver registered
10471 13:09:07.848394 <5>[ 0.870710] Key type id_legacy registered
10472 13:09:07.855285 <6>[ 0.874984] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10473 13:09:07.861651 <6>[ 0.881906] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10474 13:09:07.868520 <6>[ 0.889621] 9p: Installing v9fs 9p2000 file system support
10475 13:09:07.904778 <5>[ 0.927425] Key type asymmetric registered
10476 13:09:07.908247 <5>[ 0.931756] Asymmetric key parser 'x509' registered
10477 13:09:07.918329 <6>[ 0.936895] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10478 13:09:07.921583 <6>[ 0.944507] io scheduler mq-deadline registered
10479 13:09:07.925084 <6>[ 0.949270] io scheduler kyber registered
10480 13:09:07.943312 <6>[ 0.966309] EINJ: ACPI disabled.
10481 13:09:07.975963 <4>[ 0.992262] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10482 13:09:07.986323 <4>[ 1.002878] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10483 13:09:08.001511 <6>[ 1.023875] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10484 13:09:08.008801 <6>[ 1.031866] printk: console [ttyS0] disabled
10485 13:09:08.037215 <6>[ 1.056499] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10486 13:09:08.043834 <6>[ 1.065966] printk: console [ttyS0] enabled
10487 13:09:08.047167 <6>[ 1.065966] printk: console [ttyS0] enabled
10488 13:09:08.053805 <6>[ 1.074860] printk: bootconsole [mtk8250] disabled
10489 13:09:08.057311 <6>[ 1.074860] printk: bootconsole [mtk8250] disabled
10490 13:09:08.064003 <6>[ 1.085893] SuperH (H)SCI(F) driver initialized
10491 13:09:08.067001 <6>[ 1.091153] msm_serial: driver initialized
10492 13:09:08.080741 <6>[ 1.100090] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10493 13:09:08.090725 <6>[ 1.108635] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10494 13:09:08.097618 <6>[ 1.117178] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10495 13:09:08.107222 <6>[ 1.125806] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10496 13:09:08.113815 <6>[ 1.134513] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10497 13:09:08.124142 <6>[ 1.143234] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10498 13:09:08.133598 <6>[ 1.151774] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10499 13:09:08.140124 <6>[ 1.160585] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10500 13:09:08.150641 <6>[ 1.169128] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10501 13:09:08.161908 <6>[ 1.184553] loop: module loaded
10502 13:09:08.168675 <6>[ 1.190532] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10503 13:09:08.190892 <4>[ 1.213900] mtk-pmic-keys: Failed to locate of_node [id: -1]
10504 13:09:08.198168 <6>[ 1.220714] megasas: 07.719.03.00-rc1
10505 13:09:08.207466 <6>[ 1.230448] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10506 13:09:08.218231 <6>[ 1.240817] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10507 13:09:08.233690 <6>[ 1.256641] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10508 13:09:08.288870 <6>[ 1.305391] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10509 13:09:08.674744 <6>[ 1.697719] Freeing initrd memory: 20840K
10510 13:09:08.690695 <6>[ 1.713287] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10511 13:09:08.701423 <6>[ 1.724284] tun: Universal TUN/TAP device driver, 1.6
10512 13:09:08.704571 <6>[ 1.730339] thunder_xcv, ver 1.0
10513 13:09:08.708480 <6>[ 1.733845] thunder_bgx, ver 1.0
10514 13:09:08.711287 <6>[ 1.737336] nicpf, ver 1.0
10515 13:09:08.722172 <6>[ 1.741362] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10516 13:09:08.725595 <6>[ 1.748839] hns3: Copyright (c) 2017 Huawei Corporation.
10517 13:09:08.728250 <6>[ 1.754426] hclge is initializing
10518 13:09:08.735555 <6>[ 1.758006] e1000: Intel(R) PRO/1000 Network Driver
10519 13:09:08.742096 <6>[ 1.763135] e1000: Copyright (c) 1999-2006 Intel Corporation.
10520 13:09:08.745421 <6>[ 1.769149] e1000e: Intel(R) PRO/1000 Network Driver
10521 13:09:08.751796 <6>[ 1.774365] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10522 13:09:08.758486 <6>[ 1.780553] igb: Intel(R) Gigabit Ethernet Network Driver
10523 13:09:08.765015 <6>[ 1.786204] igb: Copyright (c) 2007-2014 Intel Corporation.
10524 13:09:08.771682 <6>[ 1.792040] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10525 13:09:08.775296 <6>[ 1.798557] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10526 13:09:08.782557 <6>[ 1.805016] sky2: driver version 1.30
10527 13:09:08.789098 <6>[ 1.809961] usbcore: registered new device driver r8152-cfgselector
10528 13:09:08.795685 <6>[ 1.816497] usbcore: registered new interface driver r8152
10529 13:09:08.799322 <6>[ 1.822323] VFIO - User Level meta-driver version: 0.3
10530 13:09:08.808082 <6>[ 1.830571] usbcore: registered new interface driver usb-storage
10531 13:09:08.814284 <6>[ 1.837016] usbcore: registered new device driver onboard-usb-hub
10532 13:09:08.823593 <6>[ 1.846195] mt6397-rtc mt6359-rtc: registered as rtc0
10533 13:09:08.833440 <6>[ 1.851672] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-18T13:08:52 UTC (1721308132)
10534 13:09:08.836762 <6>[ 1.861267] i2c_dev: i2c /dev entries driver
10535 13:09:08.850622 <4>[ 1.873249] cpu cpu0: supply cpu not found, using dummy regulator
10536 13:09:08.857247 <4>[ 1.879695] cpu cpu1: supply cpu not found, using dummy regulator
10537 13:09:08.864046 <4>[ 1.886105] cpu cpu2: supply cpu not found, using dummy regulator
10538 13:09:08.870563 <4>[ 1.892507] cpu cpu3: supply cpu not found, using dummy regulator
10539 13:09:08.877670 <4>[ 1.898908] cpu cpu4: supply cpu not found, using dummy regulator
10540 13:09:08.884133 <4>[ 1.905302] cpu cpu5: supply cpu not found, using dummy regulator
10541 13:09:08.890336 <4>[ 1.911714] cpu cpu6: supply cpu not found, using dummy regulator
10542 13:09:08.896948 <4>[ 1.918111] cpu cpu7: supply cpu not found, using dummy regulator
10543 13:09:08.916663 <6>[ 1.939739] cpu cpu0: EM: created perf domain
10544 13:09:08.920435 <6>[ 1.944650] cpu cpu4: EM: created perf domain
10545 13:09:08.927870 <6>[ 1.950227] sdhci: Secure Digital Host Controller Interface driver
10546 13:09:08.933899 <6>[ 1.956659] sdhci: Copyright(c) Pierre Ossman
10547 13:09:08.940772 <6>[ 1.961622] Synopsys Designware Multimedia Card Interface Driver
10548 13:09:08.947692 <6>[ 1.968247] sdhci-pltfm: SDHCI platform and OF driver helper
10549 13:09:08.950972 <6>[ 1.968261] mmc0: CQHCI version 5.10
10550 13:09:08.957605 <6>[ 1.978443] ledtrig-cpu: registered to indicate activity on CPUs
10551 13:09:08.964530 <6>[ 1.985412] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10552 13:09:08.971074 <6>[ 1.992470] usbcore: registered new interface driver usbhid
10553 13:09:08.974271 <6>[ 1.998291] usbhid: USB HID core driver
10554 13:09:08.980522 <6>[ 2.002496] spi_master spi0: will run message pump with realtime priority
10555 13:09:09.026864 <6>[ 2.042830] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10556 13:09:09.042311 <6>[ 2.058440] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10557 13:09:09.048947 <6>[ 2.067823] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16014
10558 13:09:09.057167 <6>[ 2.079874] cros-ec-spi spi0.0: Chrome EC device registered
10559 13:09:09.063798 <6>[ 2.085909] mmc0: Command Queue Engine enabled
10560 13:09:09.070411 <6>[ 2.090684] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10561 13:09:09.073874 <6>[ 2.098461] mmcblk0: mmc0:0001 DA4128 116 GiB
10562 13:09:09.086680 <6>[ 2.109726] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10563 13:09:09.097055 <6>[ 2.113459] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10564 13:09:09.103942 <6>[ 2.117035] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10565 13:09:09.107021 <6>[ 2.126230] NET: Registered PF_PACKET protocol family
10566 13:09:09.113542 <6>[ 2.130951] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10567 13:09:09.116780 <6>[ 2.135545] 9pnet: Installing 9P2000 support
10568 13:09:09.123683 <6>[ 2.141383] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10569 13:09:09.130013 <5>[ 2.145249] Key type dns_resolver registered
10570 13:09:09.133160 <6>[ 2.156739] registered taskstats version 1
10571 13:09:09.136704 <5>[ 2.161125] Loading compiled-in X.509 certificates
10572 13:09:09.167113 <4>[ 2.183112] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10573 13:09:09.176706 <4>[ 2.194023] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10574 13:09:09.195744 <6>[ 2.218548] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10575 13:09:09.203055 <6>[ 2.225410] xhci-mtk 11200000.usb: xHCI Host Controller
10576 13:09:09.209017 <6>[ 2.230919] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10577 13:09:09.219605 <6>[ 2.238781] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10578 13:09:09.226359 <6>[ 2.248208] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10579 13:09:09.232541 <6>[ 2.254404] xhci-mtk 11200000.usb: xHCI Host Controller
10580 13:09:09.238997 <6>[ 2.259898] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10581 13:09:09.245531 <6>[ 2.267561] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10582 13:09:09.252515 <6>[ 2.275415] hub 1-0:1.0: USB hub found
10583 13:09:09.256351 <6>[ 2.279440] hub 1-0:1.0: 1 port detected
10584 13:09:09.262816 <6>[ 2.283734] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10585 13:09:09.269566 <6>[ 2.292493] hub 2-0:1.0: USB hub found
10586 13:09:09.272931 <6>[ 2.296520] hub 2-0:1.0: 1 port detected
10587 13:09:09.280767 <6>[ 2.303463] mtk-msdc 11f70000.mmc: Got CD GPIO
10588 13:09:09.299390 <6>[ 2.318917] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10589 13:09:09.309020 <6>[ 2.327298] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10590 13:09:09.315702 <6>[ 2.335642] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10591 13:09:09.325916 <6>[ 2.343983] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10592 13:09:09.332521 <6>[ 2.352326] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10593 13:09:09.342622 <6>[ 2.360666] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10594 13:09:09.348670 <6>[ 2.369007] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10595 13:09:09.358865 <6>[ 2.377348] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10596 13:09:09.365824 <6>[ 2.385688] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10597 13:09:09.375687 <6>[ 2.394027] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10598 13:09:09.382388 <6>[ 2.402377] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10599 13:09:09.391856 <6>[ 2.410716] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10600 13:09:09.398580 <6>[ 2.419055] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10601 13:09:09.408409 <6>[ 2.427394] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10602 13:09:09.415169 <6>[ 2.435733] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10603 13:09:09.421722 <6>[ 2.444420] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10604 13:09:09.428502 <6>[ 2.451611] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10605 13:09:09.435216 <6>[ 2.458372] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10606 13:09:09.442429 <6>[ 2.465132] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10607 13:09:09.452358 <6>[ 2.472104] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10608 13:09:09.459002 <6>[ 2.478958] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10609 13:09:09.469024 <6>[ 2.488093] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10610 13:09:09.479102 <6>[ 2.497214] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10611 13:09:09.489267 <6>[ 2.506522] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10612 13:09:09.499303 <6>[ 2.515990] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10613 13:09:09.505483 <6>[ 2.525458] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10614 13:09:09.515309 <6>[ 2.534579] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10615 13:09:09.525230 <6>[ 2.544046] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10616 13:09:09.535632 <6>[ 2.553166] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10617 13:09:09.545509 <6>[ 2.562464] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10618 13:09:09.554970 <6>[ 2.572625] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10619 13:09:09.564905 <6>[ 2.584208] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10620 13:09:09.662229 <6>[ 2.681916] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10621 13:09:09.690320 <6>[ 2.712707] hub 2-1:1.0: USB hub found
10622 13:09:09.693023 <6>[ 2.717164] hub 2-1:1.0: 3 ports detected
10623 13:09:09.702749 <6>[ 2.725339] hub 2-1:1.0: USB hub found
10624 13:09:09.705463 <6>[ 2.729773] hub 2-1:1.0: 3 ports detected
10625 13:09:09.814313 <6>[ 2.833707] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10626 13:09:09.968829 <6>[ 2.991440] hub 1-1:1.0: USB hub found
10627 13:09:09.971559 <6>[ 2.995958] hub 1-1:1.0: 4 ports detected
10628 13:09:09.984000 <6>[ 3.006774] hub 1-1:1.0: USB hub found
10629 13:09:09.987198 <6>[ 3.011132] hub 1-1:1.0: 4 ports detected
10630 13:09:10.046453 <6>[ 3.065832] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10631 13:09:10.150156 <6>[ 3.170132] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10632 13:09:10.182280 <4>[ 3.201942] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10633 13:09:10.191948 <4>[ 3.211040] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10634 13:09:10.232052 <6>[ 3.254692] r8152 2-1.3:1.0 eth0: v1.12.13
10635 13:09:10.306025 <6>[ 3.325789] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10636 13:09:10.438818 <6>[ 3.461763] hub 1-1.4:1.0: USB hub found
10637 13:09:10.441885 <6>[ 3.466435] hub 1-1.4:1.0: 2 ports detected
10638 13:09:10.457052 <6>[ 3.479921] hub 1-1.4:1.0: USB hub found
10639 13:09:10.460373 <6>[ 3.484515] hub 1-1.4:1.0: 2 ports detected
10640 13:09:10.757922 <6>[ 3.777712] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10641 13:09:10.953909 <6>[ 3.973767] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10642 13:09:11.928786 <6>[ 4.951831] r8152 2-1.3:1.0 eth0: carrier on
10643 13:09:13.432328 <5>[ 4.981554] Sending DHCP requests .
10644 13:09:13.439549 <3>[ 6.455868] DHCP/BOOTP: Reply not for us on eth0, op[2] xid[65f912a5]
10645 13:09:13.445488 <3>[ 6.466446] DHCP/BOOTP: Reply not for us on eth0, op[2] xid[65f912a5]
10646 13:09:14.906878 <4>[ 7.917738] ., OK
10647 13:09:14.916844 <6>[ 7.935868] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10648 13:09:14.920519 <6>[ 7.944163] IP-Config: Complete:
10649 13:09:14.930296 <6>[ 7.947660] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10650 13:09:14.936646 <6>[ 7.958463] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10651 13:09:14.946905 <6>[ 7.967087] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10652 13:09:14.950119 <6>[ 7.967097] nameserver0=192.168.201.1
10653 13:09:14.953478 <6>[ 7.979244] clk: Disabling unused clocks
10654 13:09:14.957980 <6>[ 7.984796] ALSA device list:
10655 13:09:14.964641 <6>[ 7.988111] No soundcards found.
10656 13:09:14.972054 <6>[ 7.995517] Freeing unused kernel memory: 8512K
10657 13:09:14.975267 <6>[ 8.000389] Run /init as init process
10658 13:09:15.004736 Starting syslogd: OK
10659 13:09:15.010242 Starting klogd: OK
10660 13:09:15.018872 Running sysctl: OK
10661 13:09:15.028409 Populating /dev using udev: <30>[ 8.051192] udevd[198]: starting version 3.2.9
10662 13:09:15.037030 <27>[ 8.059954] udevd[198]: specified user 'tss' unknown
10663 13:09:15.043397 <27>[ 8.065406] udevd[198]: specified group 'tss' unknown
10664 13:09:15.049419 <30>[ 8.072017] udevd[199]: starting eudev-3.2.9
10665 13:09:15.087815 <27>[ 8.111292] udevd[199]: specified user 'tss' unknown
10666 13:09:15.094582 <27>[ 8.116671] udevd[199]: specified group 'tss' unknown
10667 13:09:15.173598 <6>[ 8.193658] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10668 13:09:15.180377 <6>[ 8.194291] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10669 13:09:15.192258 <6>[ 8.212730] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10670 13:09:15.202495 <6>[ 8.221837] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10671 13:09:15.209081 <6>[ 8.224522] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10672 13:09:15.215556 <6>[ 8.227384] remoteproc remoteproc0: scp is available
10673 13:09:15.218869 <6>[ 8.227496] remoteproc remoteproc0: powering up scp
10674 13:09:15.229021 <6>[ 8.227504] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10675 13:09:15.235697 <6>[ 8.227554] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10676 13:09:15.242431 <4>[ 8.247982] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10677 13:09:15.248855 <6>[ 8.253491] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10678 13:09:15.258988 <4>[ 8.262392] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10679 13:09:15.265699 <6>[ 8.263406] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10680 13:09:15.272227 <3>[ 8.276144] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10681 13:09:15.282177 <4>[ 8.278757] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10682 13:09:15.288967 <3>[ 8.286950] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 13:09:15.299258 <6>[ 8.294497] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10684 13:09:15.305521 <3>[ 8.301889] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 13:09:15.311887 <6>[ 8.302052] mc: Linux media interface: v0.10
10686 13:09:15.318749 <6>[ 8.310951] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10687 13:09:15.328517 <3>[ 8.319272] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 13:09:15.332022 <6>[ 8.319465] videodev: Linux video capture interface: v2.00
10689 13:09:15.341671 <6>[ 8.327224] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10690 13:09:15.349174 <3>[ 8.335199] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 13:09:15.355641 <6>[ 8.335722] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10692 13:09:15.365511 <6>[ 8.339672] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10693 13:09:15.372441 <3>[ 8.347576] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 13:09:15.379617 <6>[ 8.350741] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10695 13:09:15.386677 <6>[ 8.350748] pci_bus 0000:00: root bus resource [bus 00-ff]
10696 13:09:15.393322 <6>[ 8.350753] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10697 13:09:15.402892 <6>[ 8.350759] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10698 13:09:15.409632 <6>[ 8.350793] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10699 13:09:15.416133 <6>[ 8.350813] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10700 13:09:15.419339 <6>[ 8.350890] pci 0000:00:00.0: supports D1 D2
10701 13:09:15.426290 <6>[ 8.350893] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10702 13:09:15.436069 <6>[ 8.352504] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10703 13:09:15.442687 <6>[ 8.352612] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10704 13:09:15.449466 <6>[ 8.352644] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10705 13:09:15.455939 <6>[ 8.352664] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10706 13:09:15.462335 <6>[ 8.352682] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10707 13:09:15.469605 <6>[ 8.352799] pci 0000:01:00.0: supports D1 D2
10708 13:09:15.475641 <6>[ 8.352803] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10709 13:09:15.485547 <6>[ 8.354327] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10710 13:09:15.488912 <6>[ 8.354335] remoteproc remoteproc0: remote processor scp is now up
10711 13:09:15.498887 <6>[ 8.354337] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10712 13:09:15.506115 <6>[ 8.355646] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10713 13:09:15.512414 <3>[ 8.361380] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 13:09:15.522416 <4>[ 8.363553] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10715 13:09:15.525720 <4>[ 8.363553] Fallback method does not support PEC.
10716 13:09:15.535629 <6>[ 8.365522] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10717 13:09:15.542177 <6>[ 8.365602] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10718 13:09:15.548889 <6>[ 8.365630] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10719 13:09:15.558639 <6>[ 8.365645] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10720 13:09:15.565280 <6>[ 8.365662] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10721 13:09:15.575249 <6>[ 8.365678] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10722 13:09:15.578898 <6>[ 8.365864] pci 0000:00:00.0: PCI bridge to [bus 01]
10723 13:09:15.588351 <6>[ 8.365873] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10724 13:09:15.594930 <6>[ 8.366051] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10725 13:09:15.598377 <6>[ 8.368560] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10726 13:09:15.605031 <6>[ 8.368807] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10727 13:09:15.614739 <6>[ 8.369282] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10728 13:09:15.621905 <3>[ 8.377359] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 13:09:15.632038 <6>[ 8.377555] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10730 13:09:15.641643 <3>[ 8.378998] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10731 13:09:15.648262 <6>[ 8.386432] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10732 13:09:15.658441 <3>[ 8.392864] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10733 13:09:15.667816 <6>[ 8.393933] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10734 13:09:15.674750 <6>[ 8.394225] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10735 13:09:15.684402 <6>[ 8.404866] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10736 13:09:15.691160 <3>[ 8.408099] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10737 13:09:15.701333 <3>[ 8.412866] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10738 13:09:15.708252 <5>[ 8.415703] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10739 13:09:15.718257 <3>[ 8.420855] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 13:09:15.721366 <6>[ 8.449884] Bluetooth: Core ver 2.22
10741 13:09:15.728345 <6>[ 8.451176] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10742 13:09:15.741495 <6>[ 8.452423] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10743 13:09:15.748043 <6>[ 8.452621] usbcore: registered new interface driver uvcvideo
10744 13:09:15.754267 <3>[ 8.455893] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 13:09:15.761385 <5>[ 8.459977] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10746 13:09:15.770912 <5>[ 8.460433] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10747 13:09:15.777515 <4>[ 8.460510] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10748 13:09:15.784061 <6>[ 8.460517] cfg80211: failed to load regulatory.db
10749 13:09:15.787392 <6>[ 8.464197] NET: Registered PF_BLUETOOTH protocol family
10750 13:09:15.797704 <3>[ 8.470492] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10751 13:09:15.804108 <6>[ 8.477866] Bluetooth: HCI device and connection manager initialized
10752 13:09:15.807572 <6>[ 8.477886] Bluetooth: HCI socket layer initialized
10753 13:09:15.814173 <6>[ 8.479500] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10754 13:09:15.824233 <3>[ 8.485343] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10755 13:09:15.827405 <6>[ 8.492819] Bluetooth: L2CAP socket layer initialized
10756 13:09:15.837290 <3>[ 8.497333] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10757 13:09:15.840420 <6>[ 8.504201] Bluetooth: SCO socket layer initialized
10758 13:09:15.850523 <3>[ 8.512707] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 13:09:15.857256 <6>[ 8.561331] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10760 13:09:15.866934 <3>[ 8.562569] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 13:09:15.870555 <6>[ 8.570771] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10762 13:09:15.877100 <6>[ 8.571355] usbcore: registered new interface driver btusb
10763 13:09:15.887400 <4>[ 8.572512] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10764 13:09:15.893427 <3>[ 8.572532] Bluetooth: hci0: Failed to load firmware file (-2)
10765 13:09:15.900079 <3>[ 8.572537] Bluetooth: hci0: Failed to set up firmware (-2)
10766 13:09:15.910199 <4>[ 8.572541] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10767 13:09:15.920073 <3>[ 8.578672] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 13:09:15.941965 <6>[ 8.965638] mt7921e 0000:01:00.0: ASIC revision: 79610010
10769 13:09:16.044984 <6>[ 9.065232] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10770 13:09:16.048114 <6>[ 9.065232]
10771 13:09:16.055066 done
10772 13:09:16.069706 Saving random seed: OK
10773 13:09:16.081854 Starting network: ip: RTNETLINK answers: File exists
10774 13:09:16.084800 FAIL
10775 13:09:16.128878 Starting dropbear sshd: <6>[ 9.152392] NET: Registered PF_INET6 protocol family
10776 13:09:16.136084 <6>[ 9.159461] Segment Routing with IPv6
10777 13:09:16.139283 <6>[ 9.163419] In-situ OAM (IOAM) with IPv6
10778 13:09:16.143208 OK
10779 13:09:16.153260 /bin/sh: can't access tty; job control turned off
10780 13:09:16.153576 Matched prompt #10: / #
10782 13:09:16.153772 Setting prompt string to ['/ #']
10783 13:09:16.153860 end: 2.2.5.1 login-action (duration 00:00:10) [common]
10785 13:09:16.154092 end: 2.2.5 auto-login-action (duration 00:00:10) [common]
10786 13:09:16.154220 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
10787 13:09:16.154283 Setting prompt string to ['/ #']
10788 13:09:16.154341 Forcing a shell prompt, looking for ['/ #']
10789 13:09:16.154404 Sending line: ''
10791 13:09:16.204696 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10792 13:09:16.204783 Waiting using forced prompt support (timeout 00:02:30)
10793 13:09:16.209735 / #
10794 13:09:16.209989 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10795 13:09:16.210088 start: 2.2.7 export-device-env (timeout 00:03:33) [common]
10796 13:09:16.210181 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10797 13:09:16.210301 end: 2.2 depthcharge-retry (duration 00:01:27) [common]
10798 13:09:16.210380 end: 2 depthcharge-action (duration 00:01:27) [common]
10799 13:09:16.210466 start: 3 lava-test-retry (timeout 00:01:00) [common]
10800 13:09:16.210544 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10801 13:09:16.210612 Using namespace: common
10802 13:09:16.210684 Sending line: '#'
10804 13:09:16.311181 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10805 13:09:16.354128 / # #<6>[ 9.335717] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10806 13:09:16.354230
10807 13:09:16.354479 Using /lava-14878991
10808 13:09:16.354547 Sending line: 'export SHELL=/bin/sh'
10810 13:09:16.460035 / # export SHELL=/bin/sh
10811 13:09:16.460284 Sending line: '. /lava-14878991/environment'
10813 13:09:16.566320 / # . /lava-14878991/environment
10814 13:09:16.566602 Sending line: '/lava-14878991/bin/lava-test-runner /lava-14878991/0'
10816 13:09:16.667089 Test shell timeout: 10s (minimum of the action and connection timeout)
10817 13:09:16.672700 / # /lava-14878991/bin/lava-test-runner /lava-14878991/0
10818 13:09:16.691720 + export 'TESTRUN_ID=0_dmesg'
10819 13:09:16.698402 +<8>[ 9.720404] <LAVA_SIGNAL_STARTRUN 0_dmesg 14878991_1.5.2.3.1>
10820 13:09:16.698662 Received signal: <STARTRUN> 0_dmesg 14878991_1.5.2.3.1
10821 13:09:16.698737 Starting test lava.0_dmesg (14878991_1.5.2.3.1)
10822 13:09:16.698815 Skipping test definition patterns.
10823 13:09:16.701936 cd /lava-14878991/0/tests/0_dmesg
10824 13:09:16.702069 + cat uuid
10825 13:09:16.705629 + UUID=14878991_1.5.2.3.1
10826 13:09:16.706071 + set +x
10827 13:09:16.712519 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10828 13:09:16.718519 <8>[ 9.739438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10829 13:09:16.719164 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10831 13:09:16.740077 <8>[ 9.760232] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10832 13:09:16.740707 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10834 13:09:16.760213 <8>[ 9.780453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10835 13:09:16.760919 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10837 13:09:16.764050 + set +x
10838 13:09:16.767352 <8>[ 9.790372] <LAVA_SIGNAL_ENDRUN 0_dmesg 14878991_1.5.2.3.1>
10839 13:09:16.767970 Received signal: <ENDRUN> 0_dmesg 14878991_1.5.2.3.1
10840 13:09:16.768321 Ending use of test pattern.
10841 13:09:16.768604 Ending test lava.0_dmesg (14878991_1.5.2.3.1), duration 0.07
10843 13:09:16.771575 <LAVA_TEST_RUNNER EXIT>
10844 13:09:16.772200 ok: lava_test_shell seems to have completed
10845 13:09:16.772771 crit: pass
alert: pass
emerg: pass
10846 13:09:16.773220 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10847 13:09:16.773697 end: 3 lava-test-retry (duration 00:00:01) [common]
10848 13:09:16.774310 start: 4 finalize (timeout 00:08:13) [common]
10849 13:09:16.774804 start: 4.1 power-off (timeout 00:00:30) [common]
10850 13:09:16.775479 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
10851 13:09:18.886971 >> Command sent successfully.
10852 13:09:18.890152 Returned 0 in 2 seconds
10853 13:09:18.890287 end: 4.1 power-off (duration 00:00:02) [common]
10855 13:09:18.890499 start: 4.2 read-feedback (timeout 00:08:11) [common]
10856 13:09:18.890653 Listened to connection for namespace 'common' for up to 1s
10857 13:09:19.891653 Finalising connection for namespace 'common'
10858 13:09:19.891799 Disconnecting from shell: Finalise
10859 13:09:19.891869 / #
10860 13:09:19.992135 end: 4.2 read-feedback (duration 00:00:01) [common]
10861 13:09:19.992346 end: 4 finalize (duration 00:00:03) [common]
10862 13:09:19.992520 Cleaning after the job
10863 13:09:19.992669 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14878991/tftp-deploy-74ffm5nz/ramdisk
10864 13:09:19.996571 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14878991/tftp-deploy-74ffm5nz/kernel
10865 13:09:20.003874 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14878991/tftp-deploy-74ffm5nz/dtb
10866 13:09:20.004061 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14878991/tftp-deploy-74ffm5nz/modules
10867 13:09:20.009312 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14878991
10868 13:09:20.053145 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14878991
10869 13:09:20.053307 Job finished correctly