Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 119
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 61
1 13:07:20.851886 lava-dispatcher, installed at version: 2024.05
2 13:07:20.852097 start: 0 validate
3 13:07:20.852246 Start time: 2024-07-18 13:07:20.852240+00:00 (UTC)
4 13:07:20.852432 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:07:20.852614 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 13:07:21.113209 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:07:21.113400 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 13:07:45.372453 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:07:45.372645 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:07:45.630358 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:07:45.630885 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:07:46.142658 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:07:46.143312 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 13:07:48.651649 validate duration: 27.80
16 13:07:48.652050 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:07:48.652189 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:07:48.652328 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:07:48.652538 Not decompressing ramdisk as can be used compressed.
20 13:07:48.652654 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 13:07:48.652740 saving as /var/lib/lava/dispatcher/tmp/14878975/tftp-deploy-49h2gz7q/ramdisk/initrd.cpio.gz
22 13:07:48.652826 total size: 5628182 (5 MB)
23 13:07:48.909819 progress 0 % (0 MB)
24 13:07:48.911415 progress 5 % (0 MB)
25 13:07:48.912912 progress 10 % (0 MB)
26 13:07:48.914293 progress 15 % (0 MB)
27 13:07:48.915925 progress 20 % (1 MB)
28 13:07:48.917315 progress 25 % (1 MB)
29 13:07:48.918790 progress 30 % (1 MB)
30 13:07:48.920356 progress 35 % (1 MB)
31 13:07:48.921720 progress 40 % (2 MB)
32 13:07:48.923201 progress 45 % (2 MB)
33 13:07:48.924503 progress 50 % (2 MB)
34 13:07:48.926025 progress 55 % (2 MB)
35 13:07:48.927488 progress 60 % (3 MB)
36 13:07:48.928780 progress 65 % (3 MB)
37 13:07:48.930299 progress 70 % (3 MB)
38 13:07:48.931630 progress 75 % (4 MB)
39 13:07:48.933072 progress 80 % (4 MB)
40 13:07:48.934403 progress 85 % (4 MB)
41 13:07:48.935850 progress 90 % (4 MB)
42 13:07:48.937381 progress 95 % (5 MB)
43 13:07:48.938689 progress 100 % (5 MB)
44 13:07:48.938890 5 MB downloaded in 0.29 s (18.76 MB/s)
45 13:07:48.939041 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:07:48.939263 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:07:48.939343 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:07:48.939418 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:07:48.939554 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 13:07:48.939618 saving as /var/lib/lava/dispatcher/tmp/14878975/tftp-deploy-49h2gz7q/kernel/Image
52 13:07:48.939670 total size: 54813184 (52 MB)
53 13:07:48.939724 No compression specified
54 13:07:48.940763 progress 0 % (0 MB)
55 13:07:48.954019 progress 5 % (2 MB)
56 13:07:48.967365 progress 10 % (5 MB)
57 13:07:48.980320 progress 15 % (7 MB)
58 13:07:48.993608 progress 20 % (10 MB)
59 13:07:49.006843 progress 25 % (13 MB)
60 13:07:49.019918 progress 30 % (15 MB)
61 13:07:49.033279 progress 35 % (18 MB)
62 13:07:49.046443 progress 40 % (20 MB)
63 13:07:49.059526 progress 45 % (23 MB)
64 13:07:49.072851 progress 50 % (26 MB)
65 13:07:49.086036 progress 55 % (28 MB)
66 13:07:49.099160 progress 60 % (31 MB)
67 13:07:49.112310 progress 65 % (34 MB)
68 13:07:49.125318 progress 70 % (36 MB)
69 13:07:49.138644 progress 75 % (39 MB)
70 13:07:49.151976 progress 80 % (41 MB)
71 13:07:49.164961 progress 85 % (44 MB)
72 13:07:49.178508 progress 90 % (47 MB)
73 13:07:49.191753 progress 95 % (49 MB)
74 13:07:49.204661 progress 100 % (52 MB)
75 13:07:49.204902 52 MB downloaded in 0.27 s (197.09 MB/s)
76 13:07:49.205055 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:07:49.205333 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:07:49.205414 start: 1.3 download-retry (timeout 00:09:59) [common]
80 13:07:49.205521 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 13:07:49.205653 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:07:49.205717 saving as /var/lib/lava/dispatcher/tmp/14878975/tftp-deploy-49h2gz7q/dtb/mt8192-asurada-spherion-r0.dtb
83 13:07:49.205769 total size: 47258 (0 MB)
84 13:07:49.205822 No compression specified
85 13:07:49.206914 progress 69 % (0 MB)
86 13:07:49.207167 progress 100 % (0 MB)
87 13:07:49.207314 0 MB downloaded in 0.00 s (29.22 MB/s)
88 13:07:49.207427 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:07:49.207625 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:07:49.207700 start: 1.4 download-retry (timeout 00:09:59) [common]
92 13:07:49.207775 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 13:07:49.207882 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 13:07:49.207942 saving as /var/lib/lava/dispatcher/tmp/14878975/tftp-deploy-49h2gz7q/nfsrootfs/full.rootfs.tar
95 13:07:49.207994 total size: 107552908 (102 MB)
96 13:07:49.208049 Using unxz to decompress xz
97 13:07:49.209227 progress 0 % (0 MB)
98 13:07:49.487439 progress 5 % (5 MB)
99 13:07:49.812211 progress 10 % (10 MB)
100 13:07:50.112706 progress 15 % (15 MB)
101 13:07:50.415971 progress 20 % (20 MB)
102 13:07:50.688178 progress 25 % (25 MB)
103 13:07:50.981888 progress 30 % (30 MB)
104 13:07:51.288346 progress 35 % (35 MB)
105 13:07:51.462324 progress 40 % (41 MB)
106 13:07:51.672409 progress 45 % (46 MB)
107 13:07:51.977643 progress 50 % (51 MB)
108 13:07:52.262057 progress 55 % (56 MB)
109 13:07:52.592395 progress 60 % (61 MB)
110 13:07:52.921591 progress 65 % (66 MB)
111 13:07:53.244249 progress 70 % (71 MB)
112 13:07:53.567726 progress 75 % (76 MB)
113 13:07:53.886504 progress 80 % (82 MB)
114 13:07:54.212963 progress 85 % (87 MB)
115 13:07:54.496439 progress 90 % (92 MB)
116 13:07:54.795793 progress 95 % (97 MB)
117 13:07:55.103127 progress 100 % (102 MB)
118 13:07:55.108133 102 MB downloaded in 5.90 s (17.38 MB/s)
119 13:07:55.108341 end: 1.4.1 http-download (duration 00:00:06) [common]
121 13:07:55.108688 end: 1.4 download-retry (duration 00:00:06) [common]
122 13:07:55.108808 start: 1.5 download-retry (timeout 00:09:54) [common]
123 13:07:55.108925 start: 1.5.1 http-download (timeout 00:09:54) [common]
124 13:07:55.109112 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 13:07:55.109216 saving as /var/lib/lava/dispatcher/tmp/14878975/tftp-deploy-49h2gz7q/modules/modules.tar
126 13:07:55.109307 total size: 8611320 (8 MB)
127 13:07:55.109398 Using unxz to decompress xz
128 13:07:55.111013 progress 0 % (0 MB)
129 13:07:55.131069 progress 5 % (0 MB)
130 13:07:55.154872 progress 10 % (0 MB)
131 13:07:55.178103 progress 15 % (1 MB)
132 13:07:55.201366 progress 20 % (1 MB)
133 13:07:55.223901 progress 25 % (2 MB)
134 13:07:55.246598 progress 30 % (2 MB)
135 13:07:55.268387 progress 35 % (2 MB)
136 13:07:55.293785 progress 40 % (3 MB)
137 13:07:55.317733 progress 45 % (3 MB)
138 13:07:55.341057 progress 50 % (4 MB)
139 13:07:55.364981 progress 55 % (4 MB)
140 13:07:55.387961 progress 60 % (4 MB)
141 13:07:55.410244 progress 65 % (5 MB)
142 13:07:55.434360 progress 70 % (5 MB)
143 13:07:55.460500 progress 75 % (6 MB)
144 13:07:55.486636 progress 80 % (6 MB)
145 13:07:55.509364 progress 85 % (7 MB)
146 13:07:55.531651 progress 90 % (7 MB)
147 13:07:55.554142 progress 95 % (7 MB)
148 13:07:55.576116 progress 100 % (8 MB)
149 13:07:55.581433 8 MB downloaded in 0.47 s (17.39 MB/s)
150 13:07:55.581587 end: 1.5.1 http-download (duration 00:00:00) [common]
152 13:07:55.581798 end: 1.5 download-retry (duration 00:00:00) [common]
153 13:07:55.581877 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 13:07:55.581964 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 13:07:57.631314 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14878975/extract-nfsrootfs-uz7mtp0l
156 13:07:57.631480 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 13:07:57.631576 start: 1.6.2 lava-overlay (timeout 00:09:51) [common]
158 13:07:57.631732 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu
159 13:07:57.631852 makedir: /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin
160 13:07:57.631944 makedir: /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/tests
161 13:07:57.632035 makedir: /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/results
162 13:07:57.632116 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-add-keys
163 13:07:57.632242 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-add-sources
164 13:07:57.632363 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-background-process-start
165 13:07:57.632479 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-background-process-stop
166 13:07:57.632603 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-common-functions
167 13:07:57.632721 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-echo-ipv4
168 13:07:57.632835 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-install-packages
169 13:07:57.632948 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-installed-packages
170 13:07:57.633060 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-os-build
171 13:07:57.633214 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-probe-channel
172 13:07:57.633327 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-probe-ip
173 13:07:57.633439 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-target-ip
174 13:07:57.633551 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-target-mac
175 13:07:57.633664 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-target-storage
176 13:07:57.633780 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-test-case
177 13:07:57.633893 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-test-event
178 13:07:57.634005 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-test-feedback
179 13:07:57.634117 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-test-raise
180 13:07:57.634228 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-test-reference
181 13:07:57.634340 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-test-runner
182 13:07:57.634452 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-test-set
183 13:07:57.634562 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-test-shell
184 13:07:57.634674 Updating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-install-packages (oe)
185 13:07:57.634815 Updating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/bin/lava-installed-packages (oe)
186 13:07:57.634926 Creating /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/environment
187 13:07:57.635012 LAVA metadata
188 13:07:57.635076 - LAVA_JOB_ID=14878975
189 13:07:57.635132 - LAVA_DISPATCHER_IP=192.168.201.1
190 13:07:57.635225 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:51) [common]
191 13:07:57.635282 skipped lava-vland-overlay
192 13:07:57.635348 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 13:07:57.635419 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:51) [common]
194 13:07:57.635474 skipped lava-multinode-overlay
195 13:07:57.635540 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 13:07:57.635610 start: 1.6.2.3 test-definition (timeout 00:09:51) [common]
197 13:07:57.635673 Loading test definitions
198 13:07:57.635748 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:51) [common]
199 13:07:57.635806 Using /lava-14878975 at stage 0
200 13:07:57.636105 uuid=14878975_1.6.2.3.1 testdef=None
201 13:07:57.636187 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 13:07:57.636263 start: 1.6.2.3.2 test-overlay (timeout 00:09:51) [common]
203 13:07:57.636717 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 13:07:57.636918 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:51) [common]
206 13:07:57.637543 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 13:07:57.637778 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:51) [common]
209 13:07:57.638545 runner path: /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/0/tests/0_dmesg test_uuid 14878975_1.6.2.3.1
210 13:07:57.638694 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 13:07:57.638878 Creating lava-test-runner.conf files
213 13:07:57.638934 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14878975/lava-overlay-6yncv0zu/lava-14878975/0 for stage 0
214 13:07:57.639014 - 0_dmesg
215 13:07:57.639102 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 13:07:57.639178 start: 1.6.2.4 compress-overlay (timeout 00:09:51) [common]
217 13:07:57.644711 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 13:07:57.644805 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:51) [common]
219 13:07:57.644883 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 13:07:57.644961 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 13:07:57.645037 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:51) [common]
222 13:07:57.789681 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 13:07:57.789821 start: 1.6.4 extract-modules (timeout 00:09:51) [common]
224 13:07:57.789899 extracting modules file /var/lib/lava/dispatcher/tmp/14878975/tftp-deploy-49h2gz7q/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14878975/extract-nfsrootfs-uz7mtp0l
225 13:07:58.006589 extracting modules file /var/lib/lava/dispatcher/tmp/14878975/tftp-deploy-49h2gz7q/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14878975/extract-overlay-ramdisk-qtl0nb4l/ramdisk
226 13:07:58.227361 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 13:07:58.227580 start: 1.6.5 apply-overlay-tftp (timeout 00:09:50) [common]
228 13:07:58.227674 [common] Applying overlay to NFS
229 13:07:58.227742 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14878975/compress-overlay-bbrhxt2b/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14878975/extract-nfsrootfs-uz7mtp0l
230 13:07:58.233857 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 13:07:58.233960 start: 1.6.6 configure-preseed-file (timeout 00:09:50) [common]
232 13:07:58.234052 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 13:07:58.234141 start: 1.6.7 compress-ramdisk (timeout 00:09:50) [common]
234 13:07:58.234214 Building ramdisk /var/lib/lava/dispatcher/tmp/14878975/extract-overlay-ramdisk-qtl0nb4l/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14878975/extract-overlay-ramdisk-qtl0nb4l/ramdisk
235 13:07:58.506104 >> 129966 blocks
236 13:08:00.585528 rename /var/lib/lava/dispatcher/tmp/14878975/extract-overlay-ramdisk-qtl0nb4l/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14878975/tftp-deploy-49h2gz7q/ramdisk/ramdisk.cpio.gz
237 13:08:00.585746 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 13:08:00.585873 start: 1.6.8 prepare-kernel (timeout 00:09:48) [common]
239 13:08:00.585990 start: 1.6.8.1 prepare-fit (timeout 00:09:48) [common]
240 13:08:00.586103 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14878975/tftp-deploy-49h2gz7q/kernel/Image']
241 13:08:14.464394 Returned 0 in 13 seconds
242 13:08:14.464549 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14878975/tftp-deploy-49h2gz7q/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14878975/tftp-deploy-49h2gz7q/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14878975/tftp-deploy-49h2gz7q/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14878975/tftp-deploy-49h2gz7q/kernel/image.itb
243 13:08:14.857198 output: FIT description: Kernel Image image with one or more FDT blobs
244 13:08:14.857354 output: Created: Thu Jul 18 14:08:14 2024
245 13:08:14.857450 output: Image 0 (kernel-1)
246 13:08:14.857536 output: Description:
247 13:08:14.857621 output: Created: Thu Jul 18 14:08:14 2024
248 13:08:14.857706 output: Type: Kernel Image
249 13:08:14.857788 output: Compression: lzma compressed
250 13:08:14.857868 output: Data Size: 13114469 Bytes = 12807.10 KiB = 12.51 MiB
251 13:08:14.857947 output: Architecture: AArch64
252 13:08:14.858024 output: OS: Linux
253 13:08:14.858101 output: Load Address: 0x00000000
254 13:08:14.858178 output: Entry Point: 0x00000000
255 13:08:14.858255 output: Hash algo: crc32
256 13:08:14.858335 output: Hash value: a47b020b
257 13:08:14.858412 output: Image 1 (fdt-1)
258 13:08:14.858488 output: Description: mt8192-asurada-spherion-r0
259 13:08:14.858565 output: Created: Thu Jul 18 14:08:14 2024
260 13:08:14.858646 output: Type: Flat Device Tree
261 13:08:14.858727 output: Compression: uncompressed
262 13:08:14.858808 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 13:08:14.858889 output: Architecture: AArch64
264 13:08:14.858972 output: Hash algo: crc32
265 13:08:14.859052 output: Hash value: 0f8e4d2e
266 13:08:14.859132 output: Image 2 (ramdisk-1)
267 13:08:14.859213 output: Description: unavailable
268 13:08:14.859295 output: Created: Thu Jul 18 14:08:14 2024
269 13:08:14.859376 output: Type: RAMDisk Image
270 13:08:14.859457 output: Compression: uncompressed
271 13:08:14.859536 output: Data Size: 18722872 Bytes = 18284.05 KiB = 17.86 MiB
272 13:08:14.859617 output: Architecture: AArch64
273 13:08:14.859697 output: OS: Linux
274 13:08:14.859777 output: Load Address: unavailable
275 13:08:14.859857 output: Entry Point: unavailable
276 13:08:14.859937 output: Hash algo: crc32
277 13:08:14.860017 output: Hash value: 4cce0c55
278 13:08:14.860097 output: Default Configuration: 'conf-1'
279 13:08:14.860177 output: Configuration 0 (conf-1)
280 13:08:14.860257 output: Description: mt8192-asurada-spherion-r0
281 13:08:14.860337 output: Kernel: kernel-1
282 13:08:14.860416 output: Init Ramdisk: ramdisk-1
283 13:08:14.860496 output: FDT: fdt-1
284 13:08:14.860576 output: Loadables: kernel-1
285 13:08:14.860652 output:
286 13:08:14.860790 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 13:08:14.860899 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 13:08:14.861009 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
289 13:08:14.861118 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:34) [common]
290 13:08:14.861225 No LXC device requested
291 13:08:14.861312 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 13:08:14.861387 start: 1.8 deploy-device-env (timeout 00:09:34) [common]
293 13:08:14.861456 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 13:08:14.861511 Checking files for TFTP limit of 4294967296 bytes.
295 13:08:14.862005 end: 1 tftp-deploy (duration 00:00:26) [common]
296 13:08:14.862103 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 13:08:14.862222 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 13:08:14.862359 substitutions:
299 13:08:14.862450 - {DTB}: 14878975/tftp-deploy-49h2gz7q/dtb/mt8192-asurada-spherion-r0.dtb
300 13:08:14.862540 - {INITRD}: 14878975/tftp-deploy-49h2gz7q/ramdisk/ramdisk.cpio.gz
301 13:08:14.862625 - {KERNEL}: 14878975/tftp-deploy-49h2gz7q/kernel/Image
302 13:08:14.862713 - {LAVA_MAC}: None
303 13:08:14.862800 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14878975/extract-nfsrootfs-uz7mtp0l
304 13:08:14.862898 - {NFS_SERVER_IP}: 192.168.201.1
305 13:08:14.862981 - {PRESEED_CONFIG}: None
306 13:08:14.863077 - {PRESEED_LOCAL}: None
307 13:08:14.863161 - {RAMDISK}: 14878975/tftp-deploy-49h2gz7q/ramdisk/ramdisk.cpio.gz
308 13:08:14.863247 - {ROOT_PART}: None
309 13:08:14.863329 - {ROOT}: None
310 13:08:14.863407 - {SERVER_IP}: 192.168.201.1
311 13:08:14.863484 - {TEE}: None
312 13:08:14.863561 Parsed boot commands:
313 13:08:14.863637 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 13:08:14.863833 Parsed boot commands: tftpboot 192.168.201.1 14878975/tftp-deploy-49h2gz7q/kernel/image.itb 14878975/tftp-deploy-49h2gz7q/kernel/cmdline
315 13:08:14.863943 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 13:08:14.864046 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 13:08:14.864148 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 13:08:14.864246 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 13:08:14.864327 Not connected, no need to disconnect.
320 13:08:14.864421 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 13:08:14.864518 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 13:08:14.864599 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
323 13:08:14.867715 Setting prompt string to ['lava-test: # ']
324 13:08:14.868062 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 13:08:14.868167 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 13:08:14.868257 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 13:08:14.868339 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 13:08:14.868519 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=reboot']
329 13:08:24.042166 >> Command sent successfully.
330 13:08:24.045291 Returned 0 in 9 seconds
331 13:08:24.045443 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
333 13:08:24.045654 end: 2.2.2 reset-device (duration 00:00:09) [common]
334 13:08:24.045739 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
335 13:08:24.045813 Setting prompt string to 'Starting depthcharge on Spherion...'
336 13:08:24.045866 Changing prompt to 'Starting depthcharge on Spherion...'
337 13:08:24.045927 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 13:08:24.046269 [Enter `^Ec?' for help]
339 13:08:25.242177
340 13:08:25.242342
341 13:08:25.242404 F0: 102B 0000
342 13:08:25.242461
343 13:08:25.242512 F3: 1001 0000 [0200]
344 13:08:25.245496
345 13:08:25.245603 F3: 1001 0000
346 13:08:25.245662
347 13:08:25.245715 F7: 102D 0000
348 13:08:25.245769
349 13:08:25.249025 F1: 0000 0000
350 13:08:25.249116
351 13:08:25.249198 V0: 0000 0000 [0001]
352 13:08:25.249251
353 13:08:25.251995 00: 0007 8000
354 13:08:25.252073
355 13:08:25.252130 01: 0000 0000
356 13:08:25.252185
357 13:08:25.255819 BP: 0C00 0209 [0000]
358 13:08:25.255895
359 13:08:25.255952 G0: 1182 0000
360 13:08:25.256020
361 13:08:25.259000 EC: 0000 0021 [4000]
362 13:08:25.259076
363 13:08:25.259135 S7: 0000 0000 [0000]
364 13:08:25.259195
365 13:08:25.262255 CC: 0000 0000 [0001]
366 13:08:25.262329
367 13:08:25.262386 T0: 0000 0040 [010F]
368 13:08:25.262440
369 13:08:25.265547 Jump to BL
370 13:08:25.265622
371 13:08:25.288894
372 13:08:25.289032
373 13:08:25.298943 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
374 13:08:25.302106 ARM64: Exception handlers installed.
375 13:08:25.302182 ARM64: Testing exception
376 13:08:25.305769 ARM64: Done test exception
377 13:08:25.312273 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
378 13:08:25.322657 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
379 13:08:25.329458 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
380 13:08:25.340219 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
381 13:08:25.346687 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
382 13:08:25.353818 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
383 13:08:25.366589 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
384 13:08:25.373491 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
385 13:08:25.393428 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
386 13:08:25.397237 WDT: Last reset was cold boot
387 13:08:25.401422 SPI1(PAD0) initialized at 2873684 Hz
388 13:08:25.404896 SPI5(PAD0) initialized at 992727 Hz
389 13:08:25.404990 VBOOT: Loading verstage.
390 13:08:25.412350 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
391 13:08:25.415874 FMAP: Found "FLASH" version 1.1 at 0x20000.
392 13:08:25.419014 FMAP: base = 0x0 size = 0x800000 #areas = 25
393 13:08:25.422187 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
394 13:08:25.429386 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
395 13:08:25.436070 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
396 13:08:25.447011 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
397 13:08:25.447110
398 13:08:25.447188
399 13:08:25.457743 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
400 13:08:25.460730 ARM64: Exception handlers installed.
401 13:08:25.463955 ARM64: Testing exception
402 13:08:25.464034 ARM64: Done test exception
403 13:08:25.470991 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
404 13:08:25.474786 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
405 13:08:25.489218 Probing TPM: . done!
406 13:08:25.489301 TPM ready after 0 ms
407 13:08:25.494152 Connected to device vid:did:rid of 1ae0:0028:00
408 13:08:25.504246 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
409 13:08:25.542088 Initialized TPM device CR50 revision 0
410 13:08:25.555940 tlcl_send_startup: Startup return code is 0
411 13:08:25.556105 TPM: setup succeeded
412 13:08:25.571782 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
413 13:08:25.579302 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
414 13:08:25.588158 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
415 13:08:25.596816 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
416 13:08:25.599806 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
417 13:08:25.604041 in-header: 03 07 00 00 08 00 00 00
418 13:08:25.606787 in-data: aa e4 47 04 13 02 00 00
419 13:08:25.610135 Chrome EC: UHEPI supported
420 13:08:25.616615 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
421 13:08:25.619860 in-header: 03 a9 00 00 08 00 00 00
422 13:08:25.623298 in-data: 84 60 60 08 00 00 00 00
423 13:08:25.623392 Phase 1
424 13:08:25.627069 FMAP: area GBB found @ 3f5000 (12032 bytes)
425 13:08:25.633408 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
426 13:08:25.639831 VB2:vb2_check_recovery() Recovery was requested manually
427 13:08:25.643313 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
428 13:08:25.646853 Recovery requested (1009000e)
429 13:08:25.654886 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 13:08:25.660997 tlcl_extend: response is 0
431 13:08:25.668356 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 13:08:25.673879 tlcl_extend: response is 0
433 13:08:25.680363 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 13:08:25.700981 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
435 13:08:25.707670 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 13:08:25.707761
437 13:08:25.707839
438 13:08:25.717962 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 13:08:25.721004 ARM64: Exception handlers installed.
440 13:08:25.724369 ARM64: Testing exception
441 13:08:25.724478 ARM64: Done test exception
442 13:08:25.743800 pmic_efuse_setting: Set efuses in 11 msecs
443 13:08:25.752882 pmwrap_interface_init: Select PMIF_VLD_RDY
444 13:08:25.756494 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 13:08:25.760419 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 13:08:25.767831 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 13:08:25.771470 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 13:08:25.774845 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 13:08:25.781874 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 13:08:25.785422 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 13:08:25.789908 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 13:08:25.793393 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 13:08:25.800586 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 13:08:25.804312 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 13:08:25.808062 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 13:08:25.811483 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 13:08:25.819075 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 13:08:25.826660 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 13:08:25.830856 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 13:08:25.837911 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 13:08:25.842024 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 13:08:25.849579 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 13:08:25.853461 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 13:08:25.856762 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 13:08:25.864214 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 13:08:25.871472 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 13:08:25.875033 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 13:08:25.879763 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 13:08:25.886701 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 13:08:25.890160 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 13:08:25.897890 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 13:08:25.901374 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 13:08:25.905307 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 13:08:25.909321 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 13:08:25.916746 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 13:08:25.920610 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 13:08:25.927913 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 13:08:25.931668 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 13:08:25.935893 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 13:08:25.942586 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 13:08:25.946722 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 13:08:25.949933 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 13:08:25.953589 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 13:08:25.957774 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 13:08:25.964959 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 13:08:25.968795 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 13:08:25.972186 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 13:08:25.975767 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 13:08:25.979361 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 13:08:25.986737 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 13:08:25.990210 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 13:08:25.994112 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 13:08:25.997814 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 13:08:26.001734 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 13:08:26.008826 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
496 13:08:26.018870 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 13:08:26.022509 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 13:08:26.032699 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 13:08:26.039042 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 13:08:26.042475 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 13:08:26.049118 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 13:08:26.053122 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 13:08:26.059626 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
504 13:08:26.066740 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 13:08:26.069435 [RTC]rtc_osc_init,62: osc32con val = 0xde70
506 13:08:26.073120 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 13:08:26.083938 [RTC]rtc_get_frequency_meter,154: input=15, output=772
508 13:08:26.093379 [RTC]rtc_get_frequency_meter,154: input=23, output=957
509 13:08:26.102769 [RTC]rtc_get_frequency_meter,154: input=19, output=867
510 13:08:26.112258 [RTC]rtc_get_frequency_meter,154: input=17, output=819
511 13:08:26.121862 [RTC]rtc_get_frequency_meter,154: input=16, output=797
512 13:08:26.131541 [RTC]rtc_get_frequency_meter,154: input=15, output=773
513 13:08:26.141937 [RTC]rtc_get_frequency_meter,154: input=16, output=794
514 13:08:26.145474 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
515 13:08:26.152331 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
516 13:08:26.155824 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 13:08:26.158946 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 13:08:26.162719 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 13:08:26.166249 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 13:08:26.169540 ADC[4]: Raw value=902876 ID=7
521 13:08:26.173437 ADC[3]: Raw value=213179 ID=1
522 13:08:26.173507 RAM Code: 0x71
523 13:08:26.179533 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 13:08:26.183184 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 13:08:26.192994 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 13:08:26.199776 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 13:08:26.203037 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 13:08:26.206307 in-header: 03 07 00 00 08 00 00 00
529 13:08:26.209814 in-data: aa e4 47 04 13 02 00 00
530 13:08:26.209898 Chrome EC: UHEPI supported
531 13:08:26.216272 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 13:08:26.220470 in-header: 03 a9 00 00 08 00 00 00
533 13:08:26.223348 in-data: 84 60 60 08 00 00 00 00
534 13:08:26.227151 MRC: failed to locate region type 0.
535 13:08:26.233563 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 13:08:26.236850 DRAM-K: Running full calibration
537 13:08:26.243569 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 13:08:26.247527 header.status = 0x0
539 13:08:26.250495 header.version = 0x6 (expected: 0x6)
540 13:08:26.253651 header.size = 0xd00 (expected: 0xd00)
541 13:08:26.253794 header.flags = 0x0
542 13:08:26.260500 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 13:08:26.278136 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
544 13:08:26.284278 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 13:08:26.287757 dram_init: ddr_geometry: 2
546 13:08:26.291305 [EMI] MDL number = 2
547 13:08:26.291425 [EMI] Get MDL freq = 0
548 13:08:26.294492 dram_init: ddr_type: 0
549 13:08:26.294614 is_discrete_lpddr4: 1
550 13:08:26.297700 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 13:08:26.297811
552 13:08:26.297911
553 13:08:26.301007 [Bian_co] ETT version 0.0.0.1
554 13:08:26.308015 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 13:08:26.308156
556 13:08:26.311535 dramc_set_vcore_voltage set vcore to 650000
557 13:08:26.311643 Read voltage for 800, 4
558 13:08:26.314726 Vio18 = 0
559 13:08:26.314835 Vcore = 650000
560 13:08:26.314917 Vdram = 0
561 13:08:26.318139 Vddq = 0
562 13:08:26.318279 Vmddr = 0
563 13:08:26.321380 dram_init: config_dvfs: 1
564 13:08:26.324931 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 13:08:26.331889 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 13:08:26.334668 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
567 13:08:26.338244 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
568 13:08:26.341366 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
569 13:08:26.344714 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
570 13:08:26.348262 MEM_TYPE=3, freq_sel=18
571 13:08:26.351455 sv_algorithm_assistance_LP4_1600
572 13:08:26.355138 ============ PULL DRAM RESETB DOWN ============
573 13:08:26.358389 ========== PULL DRAM RESETB DOWN end =========
574 13:08:26.365097 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 13:08:26.368372 ===================================
576 13:08:26.368457 LPDDR4 DRAM CONFIGURATION
577 13:08:26.371790 ===================================
578 13:08:26.375448 EX_ROW_EN[0] = 0x0
579 13:08:26.378655 EX_ROW_EN[1] = 0x0
580 13:08:26.378735 LP4Y_EN = 0x0
581 13:08:26.381762 WORK_FSP = 0x0
582 13:08:26.381851 WL = 0x2
583 13:08:26.385780 RL = 0x2
584 13:08:26.385878 BL = 0x2
585 13:08:26.388457 RPST = 0x0
586 13:08:26.388536 RD_PRE = 0x0
587 13:08:26.392047 WR_PRE = 0x1
588 13:08:26.392126 WR_PST = 0x0
589 13:08:26.395537 DBI_WR = 0x0
590 13:08:26.395623 DBI_RD = 0x0
591 13:08:26.398581 OTF = 0x1
592 13:08:26.401888 ===================================
593 13:08:26.405414 ===================================
594 13:08:26.405516 ANA top config
595 13:08:26.408676 ===================================
596 13:08:26.412277 DLL_ASYNC_EN = 0
597 13:08:26.415949 ALL_SLAVE_EN = 1
598 13:08:26.416056 NEW_RANK_MODE = 1
599 13:08:26.419039 DLL_IDLE_MODE = 1
600 13:08:26.422148 LP45_APHY_COMB_EN = 1
601 13:08:26.425442 TX_ODT_DIS = 1
602 13:08:26.425522 NEW_8X_MODE = 1
603 13:08:26.428550 ===================================
604 13:08:26.432359 ===================================
605 13:08:26.435315 data_rate = 1600
606 13:08:26.438947 CKR = 1
607 13:08:26.442200 DQ_P2S_RATIO = 8
608 13:08:26.445577 ===================================
609 13:08:26.448689 CA_P2S_RATIO = 8
610 13:08:26.452290 DQ_CA_OPEN = 0
611 13:08:26.452360 DQ_SEMI_OPEN = 0
612 13:08:26.455662 CA_SEMI_OPEN = 0
613 13:08:26.458899 CA_FULL_RATE = 0
614 13:08:26.461903 DQ_CKDIV4_EN = 1
615 13:08:26.465423 CA_CKDIV4_EN = 1
616 13:08:26.468769 CA_PREDIV_EN = 0
617 13:08:26.468865 PH8_DLY = 0
618 13:08:26.472254 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 13:08:26.475399 DQ_AAMCK_DIV = 4
620 13:08:26.478851 CA_AAMCK_DIV = 4
621 13:08:26.482035 CA_ADMCK_DIV = 4
622 13:08:26.485368 DQ_TRACK_CA_EN = 0
623 13:08:26.485487 CA_PICK = 800
624 13:08:26.488560 CA_MCKIO = 800
625 13:08:26.491819 MCKIO_SEMI = 0
626 13:08:26.495121 PLL_FREQ = 3068
627 13:08:26.498652 DQ_UI_PI_RATIO = 32
628 13:08:26.502020 CA_UI_PI_RATIO = 0
629 13:08:26.505421 ===================================
630 13:08:26.508455 ===================================
631 13:08:26.508537 memory_type:LPDDR4
632 13:08:26.511877 GP_NUM : 10
633 13:08:26.515528 SRAM_EN : 1
634 13:08:26.515598 MD32_EN : 0
635 13:08:26.518447 ===================================
636 13:08:26.522068 [ANA_INIT] >>>>>>>>>>>>>>
637 13:08:26.525222 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 13:08:26.529217 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 13:08:26.531947 ===================================
640 13:08:26.535402 data_rate = 1600,PCW = 0X7600
641 13:08:26.538732 ===================================
642 13:08:26.542316 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 13:08:26.545420 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 13:08:26.552055 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 13:08:26.555826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 13:08:26.558776 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 13:08:26.562117 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 13:08:26.565384 [ANA_INIT] flow start
649 13:08:26.568695 [ANA_INIT] PLL >>>>>>>>
650 13:08:26.568817 [ANA_INIT] PLL <<<<<<<<
651 13:08:26.572404 [ANA_INIT] MIDPI >>>>>>>>
652 13:08:26.575978 [ANA_INIT] MIDPI <<<<<<<<
653 13:08:26.576088 [ANA_INIT] DLL >>>>>>>>
654 13:08:26.579139 [ANA_INIT] flow end
655 13:08:26.582472 ============ LP4 DIFF to SE enter ============
656 13:08:26.585583 ============ LP4 DIFF to SE exit ============
657 13:08:26.588978 [ANA_INIT] <<<<<<<<<<<<<
658 13:08:26.592123 [Flow] Enable top DCM control >>>>>
659 13:08:26.595955 [Flow] Enable top DCM control <<<<<
660 13:08:26.598904 Enable DLL master slave shuffle
661 13:08:26.605904 ==============================================================
662 13:08:26.605984 Gating Mode config
663 13:08:26.612376 ==============================================================
664 13:08:26.612457 Config description:
665 13:08:26.622505 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 13:08:26.629139 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 13:08:26.635866 SELPH_MODE 0: By rank 1: By Phase
668 13:08:26.639385 ==============================================================
669 13:08:26.642725 GAT_TRACK_EN = 1
670 13:08:26.646074 RX_GATING_MODE = 2
671 13:08:26.649275 RX_GATING_TRACK_MODE = 2
672 13:08:26.652925 SELPH_MODE = 1
673 13:08:26.655903 PICG_EARLY_EN = 1
674 13:08:26.659159 VALID_LAT_VALUE = 1
675 13:08:26.662557 ==============================================================
676 13:08:26.665813 Enter into Gating configuration >>>>
677 13:08:26.669077 Exit from Gating configuration <<<<
678 13:08:26.672682 Enter into DVFS_PRE_config >>>>>
679 13:08:26.686201 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 13:08:26.686281 Exit from DVFS_PRE_config <<<<<
681 13:08:26.689755 Enter into PICG configuration >>>>
682 13:08:26.692688 Exit from PICG configuration <<<<
683 13:08:26.696371 [RX_INPUT] configuration >>>>>
684 13:08:26.699405 [RX_INPUT] configuration <<<<<
685 13:08:26.706006 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 13:08:26.709648 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 13:08:26.716136 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 13:08:26.723151 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 13:08:26.729612 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 13:08:26.736353 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 13:08:26.739770 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 13:08:26.742827 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 13:08:26.746419 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 13:08:26.753045 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 13:08:26.756540 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 13:08:26.759461 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 13:08:26.763112 ===================================
698 13:08:26.766439 LPDDR4 DRAM CONFIGURATION
699 13:08:26.769639 ===================================
700 13:08:26.769716 EX_ROW_EN[0] = 0x0
701 13:08:26.773059 EX_ROW_EN[1] = 0x0
702 13:08:26.773142 LP4Y_EN = 0x0
703 13:08:26.776496 WORK_FSP = 0x0
704 13:08:26.776572 WL = 0x2
705 13:08:26.779523 RL = 0x2
706 13:08:26.782887 BL = 0x2
707 13:08:26.782963 RPST = 0x0
708 13:08:26.786353 RD_PRE = 0x0
709 13:08:26.786429 WR_PRE = 0x1
710 13:08:26.789601 WR_PST = 0x0
711 13:08:26.789677 DBI_WR = 0x0
712 13:08:26.792916 DBI_RD = 0x0
713 13:08:26.792992 OTF = 0x1
714 13:08:26.796322 ===================================
715 13:08:26.799932 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 13:08:26.803510 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 13:08:26.810999 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 13:08:26.815171 ===================================
719 13:08:26.815248 LPDDR4 DRAM CONFIGURATION
720 13:08:26.818532 ===================================
721 13:08:26.822736 EX_ROW_EN[0] = 0x10
722 13:08:26.822813 EX_ROW_EN[1] = 0x0
723 13:08:26.822872 LP4Y_EN = 0x0
724 13:08:26.826383 WORK_FSP = 0x0
725 13:08:26.826461 WL = 0x2
726 13:08:26.829934 RL = 0x2
727 13:08:26.830032 BL = 0x2
728 13:08:26.833846 RPST = 0x0
729 13:08:26.833923 RD_PRE = 0x0
730 13:08:26.837036 WR_PRE = 0x1
731 13:08:26.837115 WR_PST = 0x0
732 13:08:26.840286 DBI_WR = 0x0
733 13:08:26.840363 DBI_RD = 0x0
734 13:08:26.843668 OTF = 0x1
735 13:08:26.846897 ===================================
736 13:08:26.853500 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 13:08:26.856928 nWR fixed to 40
738 13:08:26.857032 [ModeRegInit_LP4] CH0 RK0
739 13:08:26.860119 [ModeRegInit_LP4] CH0 RK1
740 13:08:26.863602 [ModeRegInit_LP4] CH1 RK0
741 13:08:26.866923 [ModeRegInit_LP4] CH1 RK1
742 13:08:26.867023 match AC timing 13
743 13:08:26.870663 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 13:08:26.873581 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 13:08:26.880669 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 13:08:26.883643 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 13:08:26.890562 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 13:08:26.890661 [EMI DOE] emi_dcm 0
749 13:08:26.893791 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 13:08:26.897005 ==
751 13:08:26.900509 Dram Type= 6, Freq= 0, CH_0, rank 0
752 13:08:26.903732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 13:08:26.903832 ==
754 13:08:26.907629 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 13:08:26.914021 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 13:08:26.923814 [CA 0] Center 38 (7~69) winsize 63
757 13:08:26.927536 [CA 1] Center 38 (7~69) winsize 63
758 13:08:26.930331 [CA 2] Center 35 (5~66) winsize 62
759 13:08:26.934102 [CA 3] Center 35 (5~66) winsize 62
760 13:08:26.937120 [CA 4] Center 35 (4~66) winsize 63
761 13:08:26.940716 [CA 5] Center 33 (3~64) winsize 62
762 13:08:26.940810
763 13:08:26.944281 [CmdBusTrainingLP45] Vref(ca) range 1: 32
764 13:08:26.944376
765 13:08:26.948216 [CATrainingPosCal] consider 1 rank data
766 13:08:26.951447 u2DelayCellTimex100 = 270/100 ps
767 13:08:26.954625 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
768 13:08:26.958256 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
769 13:08:26.961434 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
770 13:08:26.964670 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
771 13:08:26.971363 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
772 13:08:26.974881 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
773 13:08:26.974960
774 13:08:26.978013 CA PerBit enable=1, Macro0, CA PI delay=33
775 13:08:26.978092
776 13:08:26.981369 [CBTSetCACLKResult] CA Dly = 33
777 13:08:26.981447 CS Dly: 5 (0~36)
778 13:08:26.981507 ==
779 13:08:26.984761 Dram Type= 6, Freq= 0, CH_0, rank 1
780 13:08:26.988753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 13:08:26.991510 ==
782 13:08:26.995088 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 13:08:27.001683 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 13:08:27.010238 [CA 0] Center 38 (7~69) winsize 63
785 13:08:27.013735 [CA 1] Center 38 (7~69) winsize 63
786 13:08:27.017265 [CA 2] Center 36 (6~67) winsize 62
787 13:08:27.020317 [CA 3] Center 35 (5~66) winsize 62
788 13:08:27.023972 [CA 4] Center 35 (4~66) winsize 63
789 13:08:27.027433 [CA 5] Center 34 (4~65) winsize 62
790 13:08:27.027534
791 13:08:27.030252 [CmdBusTrainingLP45] Vref(ca) range 1: 30
792 13:08:27.030344
793 13:08:27.034441 [CATrainingPosCal] consider 2 rank data
794 13:08:27.037318 u2DelayCellTimex100 = 270/100 ps
795 13:08:27.040735 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
796 13:08:27.043917 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
797 13:08:27.050740 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
798 13:08:27.053952 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
799 13:08:27.057641 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
800 13:08:27.060535 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
801 13:08:27.060612
802 13:08:27.064072 CA PerBit enable=1, Macro0, CA PI delay=34
803 13:08:27.064150
804 13:08:27.067665 [CBTSetCACLKResult] CA Dly = 34
805 13:08:27.067741 CS Dly: 6 (0~38)
806 13:08:27.067804
807 13:08:27.071299 ----->DramcWriteLeveling(PI) begin...
808 13:08:27.071377 ==
809 13:08:27.074453 Dram Type= 6, Freq= 0, CH_0, rank 0
810 13:08:27.081113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 13:08:27.081223 ==
812 13:08:27.084495 Write leveling (Byte 0): 31 => 31
813 13:08:27.087661 Write leveling (Byte 1): 31 => 31
814 13:08:27.087739 DramcWriteLeveling(PI) end<-----
815 13:08:27.087800
816 13:08:27.090787 ==
817 13:08:27.090864 Dram Type= 6, Freq= 0, CH_0, rank 0
818 13:08:27.097643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 13:08:27.097725 ==
820 13:08:27.101432 [Gating] SW mode calibration
821 13:08:27.107673 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 13:08:27.111095 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 13:08:27.117865 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
824 13:08:27.121171 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
825 13:08:27.124705 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
826 13:08:27.128362 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 13:08:27.134471 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 13:08:27.137736 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 13:08:27.141497 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 13:08:27.147926 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 13:08:27.151141 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 13:08:27.154593 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 13:08:27.161082 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 13:08:27.165220 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 13:08:27.168102 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 13:08:27.174810 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 13:08:27.178024 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 13:08:27.181372 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 13:08:27.187908 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 13:08:27.191369 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
841 13:08:27.194617 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
842 13:08:27.201734 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 13:08:27.205102 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 13:08:27.208235 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 13:08:27.211243 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 13:08:27.218493 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 13:08:27.221659 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 13:08:27.224983 0 9 4 | B1->B0 | 2323 2827 | 0 1 | (0 0) (1 1)
849 13:08:27.231545 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
850 13:08:27.234844 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
851 13:08:27.238286 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 13:08:27.245033 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 13:08:27.248514 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 13:08:27.252303 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 13:08:27.258421 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
856 13:08:27.261640 0 10 4 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
857 13:08:27.265112 0 10 8 | B1->B0 | 3131 2323 | 1 0 | (1 0) (1 0)
858 13:08:27.268575 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 13:08:27.275309 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 13:08:27.278649 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 13:08:27.281816 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 13:08:27.288615 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 13:08:27.291887 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 13:08:27.295404 0 11 4 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
865 13:08:27.302141 0 11 8 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
866 13:08:27.305457 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
867 13:08:27.308633 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 13:08:27.315361 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 13:08:27.318477 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 13:08:27.321793 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 13:08:27.328873 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
872 13:08:27.332202 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
873 13:08:27.335283 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
874 13:08:27.338829 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 13:08:27.345310 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 13:08:27.348791 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 13:08:27.352409 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 13:08:27.358986 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 13:08:27.362072 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 13:08:27.372505 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 13:08:27.372600 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 13:08:27.375349 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 13:08:27.378652 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 13:08:27.386090 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 13:08:27.389915 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 13:08:27.393169 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 13:08:27.396188 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 13:08:27.403247 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
889 13:08:27.406428 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
890 13:08:27.409705 Total UI for P1: 0, mck2ui 16
891 13:08:27.413395 best dqsien dly found for B0: ( 0, 14, 4)
892 13:08:27.416543 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 13:08:27.419787 Total UI for P1: 0, mck2ui 16
894 13:08:27.423011 best dqsien dly found for B1: ( 0, 14, 8)
895 13:08:27.426588 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
896 13:08:27.429731 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
897 13:08:27.429887
898 13:08:27.432933 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
899 13:08:27.439957 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
900 13:08:27.440038 [Gating] SW calibration Done
901 13:08:27.440098 ==
902 13:08:27.443216 Dram Type= 6, Freq= 0, CH_0, rank 0
903 13:08:27.449907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 13:08:27.450010 ==
905 13:08:27.450098 RX Vref Scan: 0
906 13:08:27.450180
907 13:08:27.453616 RX Vref 0 -> 0, step: 1
908 13:08:27.453694
909 13:08:27.456565 RX Delay -130 -> 252, step: 16
910 13:08:27.460117 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
911 13:08:27.463147 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
912 13:08:27.466555 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
913 13:08:27.473137 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
914 13:08:27.476366 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
915 13:08:27.480127 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
916 13:08:27.483426 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
917 13:08:27.486574 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
918 13:08:27.489793 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
919 13:08:27.496734 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
920 13:08:27.500262 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
921 13:08:27.503547 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
922 13:08:27.506728 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
923 13:08:27.509985 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
924 13:08:27.516929 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
925 13:08:27.520487 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
926 13:08:27.520646 ==
927 13:08:27.523584 Dram Type= 6, Freq= 0, CH_0, rank 0
928 13:08:27.527048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 13:08:27.527150 ==
930 13:08:27.530776 DQS Delay:
931 13:08:27.530871 DQS0 = 0, DQS1 = 0
932 13:08:27.530959 DQM Delay:
933 13:08:27.533859 DQM0 = 93, DQM1 = 81
934 13:08:27.533957 DQ Delay:
935 13:08:27.537545 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
936 13:08:27.540529 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
937 13:08:27.544180 DQ8 =77, DQ9 =61, DQ10 =85, DQ11 =77
938 13:08:27.547329 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
939 13:08:27.547438
940 13:08:27.547537
941 13:08:27.547632 ==
942 13:08:27.550542 Dram Type= 6, Freq= 0, CH_0, rank 0
943 13:08:27.557121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 13:08:27.557271 ==
945 13:08:27.557388
946 13:08:27.557504
947 13:08:27.557616 TX Vref Scan disable
948 13:08:27.560440 == TX Byte 0 ==
949 13:08:27.564070 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
950 13:08:27.567176 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
951 13:08:27.570664 == TX Byte 1 ==
952 13:08:27.574076 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
953 13:08:27.577518 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
954 13:08:27.580617 ==
955 13:08:27.580698 Dram Type= 6, Freq= 0, CH_0, rank 0
956 13:08:27.587408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 13:08:27.587538 ==
958 13:08:27.599293 TX Vref=22, minBit 6, minWin=27, winSum=443
959 13:08:27.602687 TX Vref=24, minBit 7, minWin=27, winSum=445
960 13:08:27.606028 TX Vref=26, minBit 8, minWin=27, winSum=451
961 13:08:27.609166 TX Vref=28, minBit 8, minWin=27, winSum=454
962 13:08:27.612882 TX Vref=30, minBit 8, minWin=27, winSum=457
963 13:08:27.616334 TX Vref=32, minBit 4, minWin=28, winSum=455
964 13:08:27.622877 [TxChooseVref] Worse bit 4, Min win 28, Win sum 455, Final Vref 32
965 13:08:27.622957
966 13:08:27.626115 Final TX Range 1 Vref 32
967 13:08:27.626192
968 13:08:27.626252 ==
969 13:08:27.629181 Dram Type= 6, Freq= 0, CH_0, rank 0
970 13:08:27.633053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 13:08:27.633217 ==
972 13:08:27.633280
973 13:08:27.636163
974 13:08:27.636240 TX Vref Scan disable
975 13:08:27.639431 == TX Byte 0 ==
976 13:08:27.642754 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
977 13:08:27.646024 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
978 13:08:27.649169 == TX Byte 1 ==
979 13:08:27.652801 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
980 13:08:27.655911 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
981 13:08:27.656021
982 13:08:27.659377 [DATLAT]
983 13:08:27.659549 Freq=800, CH0 RK0
984 13:08:27.659721
985 13:08:27.662744 DATLAT Default: 0xa
986 13:08:27.662899 0, 0xFFFF, sum = 0
987 13:08:27.666220 1, 0xFFFF, sum = 0
988 13:08:27.666356 2, 0xFFFF, sum = 0
989 13:08:27.669502 3, 0xFFFF, sum = 0
990 13:08:27.669582 4, 0xFFFF, sum = 0
991 13:08:27.672661 5, 0xFFFF, sum = 0
992 13:08:27.672741 6, 0xFFFF, sum = 0
993 13:08:27.675864 7, 0xFFFF, sum = 0
994 13:08:27.679466 8, 0xFFFF, sum = 0
995 13:08:27.679545 9, 0x0, sum = 1
996 13:08:27.679623 10, 0x0, sum = 2
997 13:08:27.682466 11, 0x0, sum = 3
998 13:08:27.682546 12, 0x0, sum = 4
999 13:08:27.685791 best_step = 10
1000 13:08:27.685870
1001 13:08:27.685946 ==
1002 13:08:27.689568 Dram Type= 6, Freq= 0, CH_0, rank 0
1003 13:08:27.692678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1004 13:08:27.692759 ==
1005 13:08:27.696129 RX Vref Scan: 1
1006 13:08:27.696207
1007 13:08:27.696284 Set Vref Range= 32 -> 127
1008 13:08:27.696356
1009 13:08:27.699195 RX Vref 32 -> 127, step: 1
1010 13:08:27.699276
1011 13:08:27.702831 RX Delay -95 -> 252, step: 8
1012 13:08:27.702907
1013 13:08:27.706070 Set Vref, RX VrefLevel [Byte0]: 32
1014 13:08:27.709496 [Byte1]: 32
1015 13:08:27.709592
1016 13:08:27.712625 Set Vref, RX VrefLevel [Byte0]: 33
1017 13:08:27.716246 [Byte1]: 33
1018 13:08:27.719868
1019 13:08:27.719943 Set Vref, RX VrefLevel [Byte0]: 34
1020 13:08:27.722972 [Byte1]: 34
1021 13:08:27.726913
1022 13:08:27.726990 Set Vref, RX VrefLevel [Byte0]: 35
1023 13:08:27.730315 [Byte1]: 35
1024 13:08:27.734676
1025 13:08:27.734752 Set Vref, RX VrefLevel [Byte0]: 36
1026 13:08:27.737900 [Byte1]: 36
1027 13:08:27.742406
1028 13:08:27.742481 Set Vref, RX VrefLevel [Byte0]: 37
1029 13:08:27.745724 [Byte1]: 37
1030 13:08:27.750136
1031 13:08:27.750212 Set Vref, RX VrefLevel [Byte0]: 38
1032 13:08:27.753295 [Byte1]: 38
1033 13:08:27.757287
1034 13:08:27.757363 Set Vref, RX VrefLevel [Byte0]: 39
1035 13:08:27.760922 [Byte1]: 39
1036 13:08:27.765005
1037 13:08:27.765098 Set Vref, RX VrefLevel [Byte0]: 40
1038 13:08:27.768895 [Byte1]: 40
1039 13:08:27.772690
1040 13:08:27.772765 Set Vref, RX VrefLevel [Byte0]: 41
1041 13:08:27.775953 [Byte1]: 41
1042 13:08:27.780499
1043 13:08:27.780598 Set Vref, RX VrefLevel [Byte0]: 42
1044 13:08:27.783519 [Byte1]: 42
1045 13:08:27.787892
1046 13:08:27.787992 Set Vref, RX VrefLevel [Byte0]: 43
1047 13:08:27.791312 [Byte1]: 43
1048 13:08:27.795615
1049 13:08:27.795692 Set Vref, RX VrefLevel [Byte0]: 44
1050 13:08:27.798709 [Byte1]: 44
1051 13:08:27.803523
1052 13:08:27.803599 Set Vref, RX VrefLevel [Byte0]: 45
1053 13:08:27.806439 [Byte1]: 45
1054 13:08:27.810521
1055 13:08:27.810597 Set Vref, RX VrefLevel [Byte0]: 46
1056 13:08:27.813867 [Byte1]: 46
1057 13:08:27.818455
1058 13:08:27.818531 Set Vref, RX VrefLevel [Byte0]: 47
1059 13:08:27.821632 [Byte1]: 47
1060 13:08:27.825999
1061 13:08:27.826090 Set Vref, RX VrefLevel [Byte0]: 48
1062 13:08:27.829041 [Byte1]: 48
1063 13:08:27.833422
1064 13:08:27.833497 Set Vref, RX VrefLevel [Byte0]: 49
1065 13:08:27.837110 [Byte1]: 49
1066 13:08:27.841059
1067 13:08:27.841178 Set Vref, RX VrefLevel [Byte0]: 50
1068 13:08:27.844305 [Byte1]: 50
1069 13:08:27.848476
1070 13:08:27.848551 Set Vref, RX VrefLevel [Byte0]: 51
1071 13:08:27.852127 [Byte1]: 51
1072 13:08:27.856415
1073 13:08:27.856493 Set Vref, RX VrefLevel [Byte0]: 52
1074 13:08:27.859402 [Byte1]: 52
1075 13:08:27.863622
1076 13:08:27.863700 Set Vref, RX VrefLevel [Byte0]: 53
1077 13:08:27.867123 [Byte1]: 53
1078 13:08:27.871398
1079 13:08:27.871493 Set Vref, RX VrefLevel [Byte0]: 54
1080 13:08:27.874639 [Byte1]: 54
1081 13:08:27.879288
1082 13:08:27.879467 Set Vref, RX VrefLevel [Byte0]: 55
1083 13:08:27.882135 [Byte1]: 55
1084 13:08:27.886739
1085 13:08:27.886896 Set Vref, RX VrefLevel [Byte0]: 56
1086 13:08:27.889784 [Byte1]: 56
1087 13:08:27.894051
1088 13:08:27.894147 Set Vref, RX VrefLevel [Byte0]: 57
1089 13:08:27.897394 [Byte1]: 57
1090 13:08:27.901890
1091 13:08:27.901983 Set Vref, RX VrefLevel [Byte0]: 58
1092 13:08:27.905017 [Byte1]: 58
1093 13:08:27.909439
1094 13:08:27.909565 Set Vref, RX VrefLevel [Byte0]: 59
1095 13:08:27.912768 [Byte1]: 59
1096 13:08:27.916763
1097 13:08:27.916839 Set Vref, RX VrefLevel [Byte0]: 60
1098 13:08:27.920271 [Byte1]: 60
1099 13:08:27.924517
1100 13:08:27.924591 Set Vref, RX VrefLevel [Byte0]: 61
1101 13:08:27.927919 [Byte1]: 61
1102 13:08:27.932133
1103 13:08:27.932231 Set Vref, RX VrefLevel [Byte0]: 62
1104 13:08:27.935292 [Byte1]: 62
1105 13:08:27.939779
1106 13:08:27.939870 Set Vref, RX VrefLevel [Byte0]: 63
1107 13:08:27.943098 [Byte1]: 63
1108 13:08:27.947242
1109 13:08:27.947311 Set Vref, RX VrefLevel [Byte0]: 64
1110 13:08:27.950756 [Byte1]: 64
1111 13:08:27.955057
1112 13:08:27.955126 Set Vref, RX VrefLevel [Byte0]: 65
1113 13:08:27.958373 [Byte1]: 65
1114 13:08:27.962447
1115 13:08:27.962519 Set Vref, RX VrefLevel [Byte0]: 66
1116 13:08:27.965775 [Byte1]: 66
1117 13:08:27.970245
1118 13:08:27.970318 Set Vref, RX VrefLevel [Byte0]: 67
1119 13:08:27.973382 [Byte1]: 67
1120 13:08:27.977650
1121 13:08:27.977718 Set Vref, RX VrefLevel [Byte0]: 68
1122 13:08:27.981354 [Byte1]: 68
1123 13:08:27.985815
1124 13:08:27.985906 Set Vref, RX VrefLevel [Byte0]: 69
1125 13:08:27.989027 [Byte1]: 69
1126 13:08:27.992731
1127 13:08:27.992795 Set Vref, RX VrefLevel [Byte0]: 70
1128 13:08:27.996202 [Byte1]: 70
1129 13:08:28.000693
1130 13:08:28.000757 Set Vref, RX VrefLevel [Byte0]: 71
1131 13:08:28.004078 [Byte1]: 71
1132 13:08:28.008125
1133 13:08:28.008188 Set Vref, RX VrefLevel [Byte0]: 72
1134 13:08:28.011539 [Byte1]: 72
1135 13:08:28.015839
1136 13:08:28.015901 Set Vref, RX VrefLevel [Byte0]: 73
1137 13:08:28.019165 [Byte1]: 73
1138 13:08:28.023205
1139 13:08:28.023269 Set Vref, RX VrefLevel [Byte0]: 74
1140 13:08:28.026560 [Byte1]: 74
1141 13:08:28.030939
1142 13:08:28.031005 Set Vref, RX VrefLevel [Byte0]: 75
1143 13:08:28.034112 [Byte1]: 75
1144 13:08:28.038715
1145 13:08:28.038795 Set Vref, RX VrefLevel [Byte0]: 76
1146 13:08:28.041673 [Byte1]: 76
1147 13:08:28.046126
1148 13:08:28.046204 Set Vref, RX VrefLevel [Byte0]: 77
1149 13:08:28.049469 [Byte1]: 77
1150 13:08:28.053752
1151 13:08:28.053830 Set Vref, RX VrefLevel [Byte0]: 78
1152 13:08:28.057742 [Byte1]: 78
1153 13:08:28.061378
1154 13:08:28.061457 Final RX Vref Byte 0 = 62 to rank0
1155 13:08:28.064832 Final RX Vref Byte 1 = 52 to rank0
1156 13:08:28.068029 Final RX Vref Byte 0 = 62 to rank1
1157 13:08:28.071559 Final RX Vref Byte 1 = 52 to rank1==
1158 13:08:28.074819 Dram Type= 6, Freq= 0, CH_0, rank 0
1159 13:08:28.081648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1160 13:08:28.081728 ==
1161 13:08:28.081805 DQS Delay:
1162 13:08:28.081877 DQS0 = 0, DQS1 = 0
1163 13:08:28.084747 DQM Delay:
1164 13:08:28.084871 DQM0 = 93, DQM1 = 81
1165 13:08:28.088152 DQ Delay:
1166 13:08:28.091167 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1167 13:08:28.091264 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1168 13:08:28.094903 DQ8 =76, DQ9 =68, DQ10 =80, DQ11 =76
1169 13:08:28.097986 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1170 13:08:28.101757
1171 13:08:28.101825
1172 13:08:28.108231 [DQSOSCAuto] RK0, (LSB)MR18= 0x403b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
1173 13:08:28.111699 CH0 RK0: MR19=606, MR18=403B
1174 13:08:28.118175 CH0_RK0: MR19=0x606, MR18=0x403B, DQSOSC=393, MR23=63, INC=95, DEC=63
1175 13:08:28.118253
1176 13:08:28.121577 ----->DramcWriteLeveling(PI) begin...
1177 13:08:28.121655 ==
1178 13:08:28.124877 Dram Type= 6, Freq= 0, CH_0, rank 1
1179 13:08:28.128309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1180 13:08:28.128389 ==
1181 13:08:28.131816 Write leveling (Byte 0): 30 => 30
1182 13:08:28.135148 Write leveling (Byte 1): 29 => 29
1183 13:08:28.138491 DramcWriteLeveling(PI) end<-----
1184 13:08:28.138567
1185 13:08:28.138625 ==
1186 13:08:28.141709 Dram Type= 6, Freq= 0, CH_0, rank 1
1187 13:08:28.145064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1188 13:08:28.145163 ==
1189 13:08:28.148274 [Gating] SW mode calibration
1190 13:08:28.155186 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1191 13:08:28.162105 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1192 13:08:28.164887 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1193 13:08:28.208999 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1194 13:08:28.209444 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1195 13:08:28.209887 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 13:08:28.209956 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 13:08:28.210229 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 13:08:28.210682 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 13:08:28.210939 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 13:08:28.211198 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 13:08:28.211263 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 13:08:28.211636 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 13:08:28.253153 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 13:08:28.253466 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 13:08:28.253533 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 13:08:28.253590 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 13:08:28.253822 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 13:08:28.254246 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 13:08:28.254525 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1210 13:08:28.254852 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1211 13:08:28.254951 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 13:08:28.255212 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 13:08:28.261243 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 13:08:28.264726 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 13:08:28.267890 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 13:08:28.271309 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 13:08:28.274817 0 9 4 | B1->B0 | 2323 2525 | 1 1 | (0 0) (0 0)
1218 13:08:28.278116 0 9 8 | B1->B0 | 2c2c 3333 | 1 1 | (0 0) (1 1)
1219 13:08:28.284784 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 13:08:28.287906 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 13:08:28.291355 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 13:08:28.297796 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1223 13:08:28.301348 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1224 13:08:28.304742 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1225 13:08:28.311126 0 10 4 | B1->B0 | 3434 3333 | 0 0 | (0 1) (0 1)
1226 13:08:28.314807 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1227 13:08:28.317926 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 13:08:28.324630 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 13:08:28.327612 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 13:08:28.331494 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 13:08:28.337997 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 13:08:28.340972 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 13:08:28.344817 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1234 13:08:28.347671 0 11 8 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
1235 13:08:28.354765 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 13:08:28.357883 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 13:08:28.360930 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 13:08:28.368167 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 13:08:28.371066 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 13:08:28.374985 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 13:08:28.381302 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1242 13:08:28.384659 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1243 13:08:28.388096 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 13:08:28.394609 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 13:08:28.398806 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 13:08:28.401402 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 13:08:28.408001 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 13:08:28.411400 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 13:08:28.414744 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 13:08:28.421459 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 13:08:28.424651 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 13:08:28.427827 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 13:08:28.431629 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 13:08:28.438141 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 13:08:28.441554 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 13:08:28.444732 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1257 13:08:28.451232 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1258 13:08:28.454656 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 13:08:28.458205 Total UI for P1: 0, mck2ui 16
1260 13:08:28.461689 best dqsien dly found for B0: ( 0, 14, 2)
1261 13:08:28.465072 Total UI for P1: 0, mck2ui 16
1262 13:08:28.468041 best dqsien dly found for B1: ( 0, 14, 4)
1263 13:08:28.471961 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1264 13:08:28.474871 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1265 13:08:28.474948
1266 13:08:28.478011 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1267 13:08:28.481640 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1268 13:08:28.484860 [Gating] SW calibration Done
1269 13:08:28.484935 ==
1270 13:08:28.488094 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 13:08:28.491566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 13:08:28.491643 ==
1273 13:08:28.494935 RX Vref Scan: 0
1274 13:08:28.495011
1275 13:08:28.498661 RX Vref 0 -> 0, step: 1
1276 13:08:28.498737
1277 13:08:28.498802 RX Delay -130 -> 252, step: 16
1278 13:08:28.504832 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1279 13:08:28.508012 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1280 13:08:28.511618 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1281 13:08:28.515227 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1282 13:08:28.518278 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1283 13:08:28.525000 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1284 13:08:28.528147 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1285 13:08:28.531460 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1286 13:08:28.534772 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1287 13:08:28.538426 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1288 13:08:28.544810 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1289 13:08:28.548530 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1290 13:08:28.551597 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1291 13:08:28.555175 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
1292 13:08:28.558506 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1293 13:08:28.564994 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1294 13:08:28.565071 ==
1295 13:08:28.568391 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 13:08:28.572404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 13:08:28.572481 ==
1298 13:08:28.572539 DQS Delay:
1299 13:08:28.575026 DQS0 = 0, DQS1 = 0
1300 13:08:28.575101 DQM Delay:
1301 13:08:28.578744 DQM0 = 89, DQM1 = 78
1302 13:08:28.578819 DQ Delay:
1303 13:08:28.581982 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1304 13:08:28.584994 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1305 13:08:28.588490 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1306 13:08:28.591522 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =85
1307 13:08:28.591599
1308 13:08:28.591659
1309 13:08:28.591715 ==
1310 13:08:28.595322 Dram Type= 6, Freq= 0, CH_0, rank 1
1311 13:08:28.598598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1312 13:08:28.601953 ==
1313 13:08:28.602029
1314 13:08:28.602087
1315 13:08:28.602141 TX Vref Scan disable
1316 13:08:28.604879 == TX Byte 0 ==
1317 13:08:28.608645 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1318 13:08:28.612161 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1319 13:08:28.615270 == TX Byte 1 ==
1320 13:08:28.618341 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1321 13:08:28.621800 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1322 13:08:28.621868 ==
1323 13:08:28.625251 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 13:08:28.631544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 13:08:28.631621 ==
1326 13:08:28.643768 TX Vref=22, minBit 3, minWin=27, winSum=447
1327 13:08:28.647191 TX Vref=24, minBit 8, minWin=27, winSum=446
1328 13:08:28.650405 TX Vref=26, minBit 8, minWin=27, winSum=449
1329 13:08:28.653863 TX Vref=28, minBit 8, minWin=27, winSum=451
1330 13:08:28.657305 TX Vref=30, minBit 8, minWin=27, winSum=455
1331 13:08:28.660540 TX Vref=32, minBit 8, minWin=27, winSum=452
1332 13:08:28.667404 [TxChooseVref] Worse bit 8, Min win 27, Win sum 455, Final Vref 30
1333 13:08:28.667481
1334 13:08:28.670224 Final TX Range 1 Vref 30
1335 13:08:28.670300
1336 13:08:28.670358 ==
1337 13:08:28.674129 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 13:08:28.676936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 13:08:28.677013 ==
1340 13:08:28.677070
1341 13:08:28.677131
1342 13:08:28.680614 TX Vref Scan disable
1343 13:08:28.684197 == TX Byte 0 ==
1344 13:08:28.687411 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1345 13:08:28.690582 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1346 13:08:28.693975 == TX Byte 1 ==
1347 13:08:28.697378 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1348 13:08:28.700737 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1349 13:08:28.700836
1350 13:08:28.703819 [DATLAT]
1351 13:08:28.703894 Freq=800, CH0 RK1
1352 13:08:28.703953
1353 13:08:28.707237 DATLAT Default: 0xa
1354 13:08:28.707312 0, 0xFFFF, sum = 0
1355 13:08:28.710615 1, 0xFFFF, sum = 0
1356 13:08:28.710692 2, 0xFFFF, sum = 0
1357 13:08:28.714064 3, 0xFFFF, sum = 0
1358 13:08:28.714140 4, 0xFFFF, sum = 0
1359 13:08:28.717715 5, 0xFFFF, sum = 0
1360 13:08:28.717792 6, 0xFFFF, sum = 0
1361 13:08:28.720990 7, 0xFFFF, sum = 0
1362 13:08:28.721067 8, 0xFFFF, sum = 0
1363 13:08:28.724519 9, 0x0, sum = 1
1364 13:08:28.724595 10, 0x0, sum = 2
1365 13:08:28.727391 11, 0x0, sum = 3
1366 13:08:28.727467 12, 0x0, sum = 4
1367 13:08:28.730820 best_step = 10
1368 13:08:28.730897
1369 13:08:28.730955 ==
1370 13:08:28.734527 Dram Type= 6, Freq= 0, CH_0, rank 1
1371 13:08:28.737274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1372 13:08:28.737350 ==
1373 13:08:28.740650 RX Vref Scan: 0
1374 13:08:28.740730
1375 13:08:28.740792 RX Vref 0 -> 0, step: 1
1376 13:08:28.740849
1377 13:08:28.744131 RX Delay -95 -> 252, step: 8
1378 13:08:28.747923 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1379 13:08:28.754171 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1380 13:08:28.757853 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1381 13:08:28.761142 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1382 13:08:28.764293 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1383 13:08:28.768078 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1384 13:08:28.774355 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1385 13:08:28.777774 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1386 13:08:28.780778 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1387 13:08:28.784598 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1388 13:08:28.787978 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1389 13:08:28.794917 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1390 13:08:28.798525 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1391 13:08:28.801557 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1392 13:08:28.804902 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1393 13:08:28.808178 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1394 13:08:28.811378 ==
1395 13:08:28.811868 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 13:08:28.818514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 13:08:28.818899 ==
1398 13:08:28.819194 DQS Delay:
1399 13:08:28.821641 DQS0 = 0, DQS1 = 0
1400 13:08:28.822107 DQM Delay:
1401 13:08:28.822450 DQM0 = 90, DQM1 = 82
1402 13:08:28.824823 DQ Delay:
1403 13:08:28.828587 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1404 13:08:28.831490 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1405 13:08:28.834987 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =80
1406 13:08:28.838331 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1407 13:08:28.838713
1408 13:08:28.839007
1409 13:08:28.845072 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
1410 13:08:28.848328 CH0 RK1: MR19=606, MR18=4C26
1411 13:08:28.854957 CH0_RK1: MR19=0x606, MR18=0x4C26, DQSOSC=390, MR23=63, INC=97, DEC=64
1412 13:08:28.858706 [RxdqsGatingPostProcess] freq 800
1413 13:08:28.862054 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1414 13:08:28.864932 Pre-setting of DQS Precalculation
1415 13:08:28.871938 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1416 13:08:28.872324 ==
1417 13:08:28.875196 Dram Type= 6, Freq= 0, CH_1, rank 0
1418 13:08:28.878521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1419 13:08:28.878905 ==
1420 13:08:28.885202 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1421 13:08:28.888499 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1422 13:08:28.899052 [CA 0] Center 36 (6~67) winsize 62
1423 13:08:28.902542 [CA 1] Center 36 (6~67) winsize 62
1424 13:08:28.905682 [CA 2] Center 34 (4~65) winsize 62
1425 13:08:28.909187 [CA 3] Center 34 (3~65) winsize 63
1426 13:08:28.912623 [CA 4] Center 34 (4~65) winsize 62
1427 13:08:28.915610 [CA 5] Center 34 (3~65) winsize 63
1428 13:08:28.916076
1429 13:08:28.919105 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1430 13:08:28.919501
1431 13:08:28.922339 [CATrainingPosCal] consider 1 rank data
1432 13:08:28.926027 u2DelayCellTimex100 = 270/100 ps
1433 13:08:28.929578 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1434 13:08:28.932425 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1435 13:08:28.939253 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1436 13:08:28.942553 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1437 13:08:28.946200 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1438 13:08:28.949122 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1439 13:08:28.949614
1440 13:08:28.952495 CA PerBit enable=1, Macro0, CA PI delay=34
1441 13:08:28.952885
1442 13:08:28.956038 [CBTSetCACLKResult] CA Dly = 34
1443 13:08:28.956426 CS Dly: 5 (0~36)
1444 13:08:28.956726 ==
1445 13:08:28.959072 Dram Type= 6, Freq= 0, CH_1, rank 1
1446 13:08:28.966494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 13:08:28.966884 ==
1448 13:08:28.968944 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1449 13:08:28.976125 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1450 13:08:28.985199 [CA 0] Center 36 (6~67) winsize 62
1451 13:08:28.989046 [CA 1] Center 36 (6~67) winsize 62
1452 13:08:28.992262 [CA 2] Center 35 (4~66) winsize 63
1453 13:08:28.995366 [CA 3] Center 34 (4~65) winsize 62
1454 13:08:28.999020 [CA 4] Center 34 (4~65) winsize 62
1455 13:08:29.002011 [CA 5] Center 34 (4~65) winsize 62
1456 13:08:29.002400
1457 13:08:29.005743 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1458 13:08:29.006131
1459 13:08:29.009062 [CATrainingPosCal] consider 2 rank data
1460 13:08:29.012217 u2DelayCellTimex100 = 270/100 ps
1461 13:08:29.016154 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1462 13:08:29.018941 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1463 13:08:29.022651 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1464 13:08:29.025962 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1465 13:08:29.032542 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1466 13:08:29.035713 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1467 13:08:29.036101
1468 13:08:29.039212 CA PerBit enable=1, Macro0, CA PI delay=34
1469 13:08:29.039600
1470 13:08:29.042601 [CBTSetCACLKResult] CA Dly = 34
1471 13:08:29.042988 CS Dly: 5 (0~37)
1472 13:08:29.043288
1473 13:08:29.046191 ----->DramcWriteLeveling(PI) begin...
1474 13:08:29.046580 ==
1475 13:08:29.049546 Dram Type= 6, Freq= 0, CH_1, rank 0
1476 13:08:29.055807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1477 13:08:29.056341 ==
1478 13:08:29.059197 Write leveling (Byte 0): 29 => 29
1479 13:08:29.059602 Write leveling (Byte 1): 30 => 30
1480 13:08:29.062035 DramcWriteLeveling(PI) end<-----
1481 13:08:29.062110
1482 13:08:29.062169 ==
1483 13:08:29.065468 Dram Type= 6, Freq= 0, CH_1, rank 0
1484 13:08:29.072989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1485 13:08:29.073071 ==
1486 13:08:29.075661 [Gating] SW mode calibration
1487 13:08:29.082452 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1488 13:08:29.085649 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1489 13:08:29.088935 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1490 13:08:29.095906 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1491 13:08:29.099258 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1492 13:08:29.102654 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 13:08:29.109140 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 13:08:29.112427 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 13:08:29.115922 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 13:08:29.122444 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 13:08:29.125639 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 13:08:29.129111 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 13:08:29.136135 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 13:08:29.139038 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 13:08:29.142730 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 13:08:29.149095 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 13:08:29.152361 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 13:08:29.156155 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1505 13:08:29.162648 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1506 13:08:29.166082 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1507 13:08:29.169046 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 13:08:29.172670 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 13:08:29.179197 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 13:08:29.182728 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 13:08:29.185999 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 13:08:29.192842 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 13:08:29.196096 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 13:08:29.199505 0 9 4 | B1->B0 | 2525 2c2c | 1 1 | (1 1) (1 1)
1515 13:08:29.206485 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1516 13:08:29.209636 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 13:08:29.213087 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 13:08:29.219570 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 13:08:29.223145 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 13:08:29.226001 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1521 13:08:29.233043 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1522 13:08:29.236140 0 10 4 | B1->B0 | 2e2e 2b2b | 0 0 | (1 0) (1 0)
1523 13:08:29.239352 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 13:08:29.243000 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 13:08:29.249920 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 13:08:29.253086 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 13:08:29.256726 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 13:08:29.263641 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 13:08:29.266765 0 11 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
1530 13:08:29.269824 0 11 4 | B1->B0 | 3636 3939 | 0 0 | (0 0) (1 1)
1531 13:08:29.276417 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
1532 13:08:29.279810 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 13:08:29.283118 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 13:08:29.289923 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 13:08:29.293531 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 13:08:29.296709 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 13:08:29.303206 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1538 13:08:29.306405 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 13:08:29.309966 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 13:08:29.313415 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 13:08:29.320163 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 13:08:29.323305 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 13:08:29.326792 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 13:08:29.333205 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 13:08:29.337008 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 13:08:29.340343 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 13:08:29.347272 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 13:08:29.350285 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 13:08:29.353785 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 13:08:29.360590 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 13:08:29.363738 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 13:08:29.367255 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 13:08:29.370882 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1554 13:08:29.377225 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1555 13:08:29.381221 Total UI for P1: 0, mck2ui 16
1556 13:08:29.383846 best dqsien dly found for B0: ( 0, 14, 0)
1557 13:08:29.387053 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 13:08:29.390365 Total UI for P1: 0, mck2ui 16
1559 13:08:29.393765 best dqsien dly found for B1: ( 0, 14, 2)
1560 13:08:29.396891 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1561 13:08:29.400680 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1562 13:08:29.400812
1563 13:08:29.403454 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1564 13:08:29.407039 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1565 13:08:29.410220 [Gating] SW calibration Done
1566 13:08:29.410295 ==
1567 13:08:29.413830 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 13:08:29.417312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 13:08:29.420758 ==
1570 13:08:29.420845 RX Vref Scan: 0
1571 13:08:29.420911
1572 13:08:29.423786 RX Vref 0 -> 0, step: 1
1573 13:08:29.423873
1574 13:08:29.427201 RX Delay -130 -> 252, step: 16
1575 13:08:29.431053 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1576 13:08:29.433917 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1577 13:08:29.437605 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1578 13:08:29.440997 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1579 13:08:29.443824 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1580 13:08:29.450490 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1581 13:08:29.454512 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1582 13:08:29.457566 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1583 13:08:29.460926 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1584 13:08:29.463971 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1585 13:08:29.470917 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1586 13:08:29.473852 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1587 13:08:29.477174 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1588 13:08:29.480642 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1589 13:08:29.484321 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1590 13:08:29.490979 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1591 13:08:29.491112 ==
1592 13:08:29.494042 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 13:08:29.497729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 13:08:29.497832 ==
1595 13:08:29.497912 DQS Delay:
1596 13:08:29.500804 DQS0 = 0, DQS1 = 0
1597 13:08:29.500917 DQM Delay:
1598 13:08:29.504562 DQM0 = 86, DQM1 = 81
1599 13:08:29.504686 DQ Delay:
1600 13:08:29.507927 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1601 13:08:29.511618 DQ4 =77, DQ5 =93, DQ6 =101, DQ7 =85
1602 13:08:29.514401 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1603 13:08:29.517612 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1604 13:08:29.517690
1605 13:08:29.517748
1606 13:08:29.517811 ==
1607 13:08:29.520963 Dram Type= 6, Freq= 0, CH_1, rank 0
1608 13:08:29.524113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1609 13:08:29.524195 ==
1610 13:08:29.524258
1611 13:08:29.527709
1612 13:08:29.527795 TX Vref Scan disable
1613 13:08:29.531386 == TX Byte 0 ==
1614 13:08:29.534344 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1615 13:08:29.537709 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1616 13:08:29.541669 == TX Byte 1 ==
1617 13:08:29.544605 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1618 13:08:29.547744 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1619 13:08:29.547875 ==
1620 13:08:29.551045 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 13:08:29.557396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 13:08:29.557473 ==
1623 13:08:29.569305 TX Vref=22, minBit 0, minWin=27, winSum=445
1624 13:08:29.572508 TX Vref=24, minBit 15, minWin=27, winSum=452
1625 13:08:29.575750 TX Vref=26, minBit 15, minWin=27, winSum=451
1626 13:08:29.579403 TX Vref=28, minBit 15, minWin=27, winSum=453
1627 13:08:29.582654 TX Vref=30, minBit 3, minWin=28, winSum=457
1628 13:08:29.589289 TX Vref=32, minBit 9, minWin=27, winSum=451
1629 13:08:29.592847 [TxChooseVref] Worse bit 3, Min win 28, Win sum 457, Final Vref 30
1630 13:08:29.592986
1631 13:08:29.595728 Final TX Range 1 Vref 30
1632 13:08:29.595889
1633 13:08:29.596012 ==
1634 13:08:29.599349 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 13:08:29.602868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 13:08:29.603099 ==
1637 13:08:29.603303
1638 13:08:29.606002
1639 13:08:29.606222 TX Vref Scan disable
1640 13:08:29.609443 == TX Byte 0 ==
1641 13:08:29.613261 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1642 13:08:29.616510 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1643 13:08:29.619611 == TX Byte 1 ==
1644 13:08:29.622984 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1645 13:08:29.626405 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1646 13:08:29.626794
1647 13:08:29.629534 [DATLAT]
1648 13:08:29.630077 Freq=800, CH1 RK0
1649 13:08:29.630557
1650 13:08:29.633311 DATLAT Default: 0xa
1651 13:08:29.633387 0, 0xFFFF, sum = 0
1652 13:08:29.636281 1, 0xFFFF, sum = 0
1653 13:08:29.636363 2, 0xFFFF, sum = 0
1654 13:08:29.639435 3, 0xFFFF, sum = 0
1655 13:08:29.639517 4, 0xFFFF, sum = 0
1656 13:08:29.642836 5, 0xFFFF, sum = 0
1657 13:08:29.642931 6, 0xFFFF, sum = 0
1658 13:08:29.646124 7, 0xFFFF, sum = 0
1659 13:08:29.646220 8, 0xFFFF, sum = 0
1660 13:08:29.649874 9, 0x0, sum = 1
1661 13:08:29.650000 10, 0x0, sum = 2
1662 13:08:29.652803 11, 0x0, sum = 3
1663 13:08:29.652945 12, 0x0, sum = 4
1664 13:08:29.655965 best_step = 10
1665 13:08:29.656058
1666 13:08:29.656143 ==
1667 13:08:29.659677 Dram Type= 6, Freq= 0, CH_1, rank 0
1668 13:08:29.662722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1669 13:08:29.662823 ==
1670 13:08:29.666199 RX Vref Scan: 1
1671 13:08:29.666305
1672 13:08:29.666400 Set Vref Range= 32 -> 127
1673 13:08:29.666496
1674 13:08:29.669760 RX Vref 32 -> 127, step: 1
1675 13:08:29.669861
1676 13:08:29.672792 RX Delay -95 -> 252, step: 8
1677 13:08:29.672901
1678 13:08:29.676146 Set Vref, RX VrefLevel [Byte0]: 32
1679 13:08:29.679998 [Byte1]: 32
1680 13:08:29.680127
1681 13:08:29.682827 Set Vref, RX VrefLevel [Byte0]: 33
1682 13:08:29.686228 [Byte1]: 33
1683 13:08:29.689709
1684 13:08:29.689809 Set Vref, RX VrefLevel [Byte0]: 34
1685 13:08:29.692657 [Byte1]: 34
1686 13:08:29.697461
1687 13:08:29.697580 Set Vref, RX VrefLevel [Byte0]: 35
1688 13:08:29.700532 [Byte1]: 35
1689 13:08:29.704829
1690 13:08:29.704955 Set Vref, RX VrefLevel [Byte0]: 36
1691 13:08:29.707976 [Byte1]: 36
1692 13:08:29.712307
1693 13:08:29.712401 Set Vref, RX VrefLevel [Byte0]: 37
1694 13:08:29.715628 [Byte1]: 37
1695 13:08:29.719795
1696 13:08:29.719888 Set Vref, RX VrefLevel [Byte0]: 38
1697 13:08:29.723074 [Byte1]: 38
1698 13:08:29.727501
1699 13:08:29.727618 Set Vref, RX VrefLevel [Byte0]: 39
1700 13:08:29.730699 [Byte1]: 39
1701 13:08:29.735224
1702 13:08:29.735350 Set Vref, RX VrefLevel [Byte0]: 40
1703 13:08:29.738874 [Byte1]: 40
1704 13:08:29.742784
1705 13:08:29.742924 Set Vref, RX VrefLevel [Byte0]: 41
1706 13:08:29.745972 [Byte1]: 41
1707 13:08:29.750203
1708 13:08:29.750361 Set Vref, RX VrefLevel [Byte0]: 42
1709 13:08:29.753671 [Byte1]: 42
1710 13:08:29.757902
1711 13:08:29.758055 Set Vref, RX VrefLevel [Byte0]: 43
1712 13:08:29.761267 [Byte1]: 43
1713 13:08:29.765671
1714 13:08:29.765892 Set Vref, RX VrefLevel [Byte0]: 44
1715 13:08:29.769085 [Byte1]: 44
1716 13:08:29.773210
1717 13:08:29.773565 Set Vref, RX VrefLevel [Byte0]: 45
1718 13:08:29.776892 [Byte1]: 45
1719 13:08:29.781184
1720 13:08:29.781701 Set Vref, RX VrefLevel [Byte0]: 46
1721 13:08:29.784482 [Byte1]: 46
1722 13:08:29.788887
1723 13:08:29.789427 Set Vref, RX VrefLevel [Byte0]: 47
1724 13:08:29.792090 [Byte1]: 47
1725 13:08:29.796169
1726 13:08:29.796740 Set Vref, RX VrefLevel [Byte0]: 48
1727 13:08:29.799719 [Byte1]: 48
1728 13:08:29.804286
1729 13:08:29.804669 Set Vref, RX VrefLevel [Byte0]: 49
1730 13:08:29.807167 [Byte1]: 49
1731 13:08:29.811520
1732 13:08:29.811902 Set Vref, RX VrefLevel [Byte0]: 50
1733 13:08:29.814828 [Byte1]: 50
1734 13:08:29.818969
1735 13:08:29.819515 Set Vref, RX VrefLevel [Byte0]: 51
1736 13:08:29.822433 [Byte1]: 51
1737 13:08:29.827060
1738 13:08:29.827593 Set Vref, RX VrefLevel [Byte0]: 52
1739 13:08:29.830107 [Byte1]: 52
1740 13:08:29.834461
1741 13:08:29.834886 Set Vref, RX VrefLevel [Byte0]: 53
1742 13:08:29.837552 [Byte1]: 53
1743 13:08:29.841717
1744 13:08:29.842286 Set Vref, RX VrefLevel [Byte0]: 54
1745 13:08:29.845015 [Byte1]: 54
1746 13:08:29.849352
1747 13:08:29.849871 Set Vref, RX VrefLevel [Byte0]: 55
1748 13:08:29.852806 [Byte1]: 55
1749 13:08:29.856852
1750 13:08:29.857398 Set Vref, RX VrefLevel [Byte0]: 56
1751 13:08:29.860556 [Byte1]: 56
1752 13:08:29.864408
1753 13:08:29.864916 Set Vref, RX VrefLevel [Byte0]: 57
1754 13:08:29.868026 [Byte1]: 57
1755 13:08:29.872276
1756 13:08:29.872813 Set Vref, RX VrefLevel [Byte0]: 58
1757 13:08:29.875463 [Byte1]: 58
1758 13:08:29.879627
1759 13:08:29.880105 Set Vref, RX VrefLevel [Byte0]: 59
1760 13:08:29.883296 [Byte1]: 59
1761 13:08:29.887889
1762 13:08:29.888412 Set Vref, RX VrefLevel [Byte0]: 60
1763 13:08:29.890605 [Byte1]: 60
1764 13:08:29.895340
1765 13:08:29.895865 Set Vref, RX VrefLevel [Byte0]: 61
1766 13:08:29.898314 [Byte1]: 61
1767 13:08:29.902680
1768 13:08:29.903070 Set Vref, RX VrefLevel [Byte0]: 62
1769 13:08:29.905686 [Byte1]: 62
1770 13:08:29.910428
1771 13:08:29.910814 Set Vref, RX VrefLevel [Byte0]: 63
1772 13:08:29.913318 [Byte1]: 63
1773 13:08:29.917783
1774 13:08:29.918246 Set Vref, RX VrefLevel [Byte0]: 64
1775 13:08:29.921074 [Byte1]: 64
1776 13:08:29.925754
1777 13:08:29.926145 Set Vref, RX VrefLevel [Byte0]: 65
1778 13:08:29.928587 [Byte1]: 65
1779 13:08:29.933013
1780 13:08:29.933636 Set Vref, RX VrefLevel [Byte0]: 66
1781 13:08:29.936256 [Byte1]: 66
1782 13:08:29.940662
1783 13:08:29.941045 Set Vref, RX VrefLevel [Byte0]: 67
1784 13:08:29.943797 [Byte1]: 67
1785 13:08:29.947977
1786 13:08:29.948500 Set Vref, RX VrefLevel [Byte0]: 68
1787 13:08:29.951327 [Byte1]: 68
1788 13:08:29.955966
1789 13:08:29.956550 Set Vref, RX VrefLevel [Byte0]: 69
1790 13:08:29.958938 [Byte1]: 69
1791 13:08:29.963739
1792 13:08:29.964263 Set Vref, RX VrefLevel [Byte0]: 70
1793 13:08:29.966654 [Byte1]: 70
1794 13:08:29.970933
1795 13:08:29.971276 Set Vref, RX VrefLevel [Byte0]: 71
1796 13:08:29.974344 [Byte1]: 71
1797 13:08:29.978919
1798 13:08:29.979189 Set Vref, RX VrefLevel [Byte0]: 72
1799 13:08:29.982075 [Byte1]: 72
1800 13:08:29.986089
1801 13:08:29.986362 Set Vref, RX VrefLevel [Byte0]: 73
1802 13:08:29.989447 [Byte1]: 73
1803 13:08:29.993580
1804 13:08:29.993850 Set Vref, RX VrefLevel [Byte0]: 74
1805 13:08:29.996885 [Byte1]: 74
1806 13:08:30.001294
1807 13:08:30.001566 Set Vref, RX VrefLevel [Byte0]: 75
1808 13:08:30.004758 [Byte1]: 75
1809 13:08:30.008666
1810 13:08:30.009021 Set Vref, RX VrefLevel [Byte0]: 76
1811 13:08:30.012395 [Byte1]: 76
1812 13:08:30.016685
1813 13:08:30.016958 Final RX Vref Byte 0 = 57 to rank0
1814 13:08:30.020067 Final RX Vref Byte 1 = 63 to rank0
1815 13:08:30.023820 Final RX Vref Byte 0 = 57 to rank1
1816 13:08:30.026290 Final RX Vref Byte 1 = 63 to rank1==
1817 13:08:30.029576 Dram Type= 6, Freq= 0, CH_1, rank 0
1818 13:08:30.036766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1819 13:08:30.037150 ==
1820 13:08:30.037493 DQS Delay:
1821 13:08:30.037804 DQS0 = 0, DQS1 = 0
1822 13:08:30.040062 DQM Delay:
1823 13:08:30.040391 DQM0 = 89, DQM1 = 81
1824 13:08:30.043072 DQ Delay:
1825 13:08:30.046306 DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =88
1826 13:08:30.049666 DQ4 =88, DQ5 =96, DQ6 =100, DQ7 =88
1827 13:08:30.052781 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1828 13:08:30.056306 DQ12 =92, DQ13 =84, DQ14 =84, DQ15 =84
1829 13:08:30.056646
1830 13:08:30.056972
1831 13:08:30.063178 [DQSOSCAuto] RK0, (LSB)MR18= 0x3855, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
1832 13:08:30.066481 CH1 RK0: MR19=606, MR18=3855
1833 13:08:30.072813 CH1_RK0: MR19=0x606, MR18=0x3855, DQSOSC=388, MR23=63, INC=98, DEC=65
1834 13:08:30.072890
1835 13:08:30.076538 ----->DramcWriteLeveling(PI) begin...
1836 13:08:30.076620 ==
1837 13:08:30.079740 Dram Type= 6, Freq= 0, CH_1, rank 1
1838 13:08:30.083087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1839 13:08:30.083205 ==
1840 13:08:30.086214 Write leveling (Byte 0): 25 => 25
1841 13:08:30.089686 Write leveling (Byte 1): 31 => 31
1842 13:08:30.093221 DramcWriteLeveling(PI) end<-----
1843 13:08:30.093349
1844 13:08:30.093460 ==
1845 13:08:30.096545 Dram Type= 6, Freq= 0, CH_1, rank 1
1846 13:08:30.099968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1847 13:08:30.100108 ==
1848 13:08:30.102961 [Gating] SW mode calibration
1849 13:08:30.109755 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1850 13:08:30.116662 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1851 13:08:30.120081 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1852 13:08:30.123154 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1853 13:08:30.130259 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 13:08:30.133655 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 13:08:30.137002 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 13:08:30.143757 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 13:08:30.146968 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 13:08:30.149647 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 13:08:30.153116 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 13:08:30.159931 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 13:08:30.163281 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 13:08:30.166828 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 13:08:30.173260 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 13:08:30.176663 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 13:08:30.180276 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 13:08:30.186994 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 13:08:30.189971 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 13:08:30.193637 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1869 13:08:30.200277 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1870 13:08:30.203766 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 13:08:30.207082 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 13:08:30.214230 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 13:08:30.217379 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 13:08:30.220334 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 13:08:30.224152 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 13:08:30.230454 0 9 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1877 13:08:30.233564 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
1878 13:08:30.236820 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1879 13:08:30.243619 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1880 13:08:30.247368 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1881 13:08:30.250166 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1882 13:08:30.257113 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1883 13:08:30.260638 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1884 13:08:30.263702 0 10 4 | B1->B0 | 2f2f 2f2f | 0 0 | (1 1) (1 1)
1885 13:08:30.270421 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 13:08:30.273991 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 13:08:30.277619 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 13:08:30.283932 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 13:08:30.287283 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 13:08:30.290578 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 13:08:30.293834 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 13:08:30.300924 0 11 4 | B1->B0 | 3636 2727 | 0 0 | (0 0) (0 0)
1893 13:08:30.304764 0 11 8 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (1 1)
1894 13:08:30.307534 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1895 13:08:30.314251 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1896 13:08:30.317760 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1897 13:08:30.320806 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1898 13:08:30.328095 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1899 13:08:30.331174 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1900 13:08:30.334510 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1901 13:08:30.341181 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1902 13:08:30.344633 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 13:08:30.347800 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 13:08:30.351365 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 13:08:30.357992 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 13:08:30.361882 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 13:08:30.364658 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 13:08:30.371747 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 13:08:30.374742 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 13:08:30.378165 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 13:08:30.384620 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 13:08:30.388330 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 13:08:30.391537 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 13:08:30.398390 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 13:08:30.401592 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 13:08:30.404809 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1917 13:08:30.411343 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 13:08:30.411736 Total UI for P1: 0, mck2ui 16
1919 13:08:30.415064 best dqsien dly found for B0: ( 0, 14, 4)
1920 13:08:30.417997 Total UI for P1: 0, mck2ui 16
1921 13:08:30.421580 best dqsien dly found for B1: ( 0, 14, 4)
1922 13:08:30.428201 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1923 13:08:30.431583 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1924 13:08:30.431976
1925 13:08:30.435041 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1926 13:08:30.438310 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1927 13:08:30.441800 [Gating] SW calibration Done
1928 13:08:30.442188 ==
1929 13:08:30.445174 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 13:08:30.448244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 13:08:30.448637 ==
1932 13:08:30.448936 RX Vref Scan: 0
1933 13:08:30.449253
1934 13:08:30.451449 RX Vref 0 -> 0, step: 1
1935 13:08:30.451838
1936 13:08:30.455060 RX Delay -130 -> 252, step: 16
1937 13:08:30.458038 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1938 13:08:30.461765 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1939 13:08:30.468099 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1940 13:08:30.471656 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1941 13:08:30.475018 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1942 13:08:30.478638 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1943 13:08:30.481705 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1944 13:08:30.488236 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1945 13:08:30.491930 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1946 13:08:30.495036 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1947 13:08:30.498330 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1948 13:08:30.501555 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1949 13:08:30.508252 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1950 13:08:30.511588 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1951 13:08:30.515320 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1952 13:08:30.518381 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1953 13:08:30.518768 ==
1954 13:08:30.521692 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 13:08:30.525306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 13:08:30.528552 ==
1957 13:08:30.528932 DQS Delay:
1958 13:08:30.529260 DQS0 = 0, DQS1 = 0
1959 13:08:30.531531 DQM Delay:
1960 13:08:30.531910 DQM0 = 88, DQM1 = 80
1961 13:08:30.535333 DQ Delay:
1962 13:08:30.535716 DQ0 =101, DQ1 =77, DQ2 =77, DQ3 =85
1963 13:08:30.538587 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =77
1964 13:08:30.542101 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1965 13:08:30.545615 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1966 13:08:30.548800
1967 13:08:30.549217
1968 13:08:30.549527 ==
1969 13:08:30.551960 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 13:08:30.555187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 13:08:30.555582 ==
1972 13:08:30.555875
1973 13:08:30.556147
1974 13:08:30.558613 TX Vref Scan disable
1975 13:08:30.559019 == TX Byte 0 ==
1976 13:08:30.565189 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1977 13:08:30.568625 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1978 13:08:30.569014 == TX Byte 1 ==
1979 13:08:30.575286 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1980 13:08:30.578824 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1981 13:08:30.579212 ==
1982 13:08:30.582083 Dram Type= 6, Freq= 0, CH_1, rank 1
1983 13:08:30.585625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1984 13:08:30.586014 ==
1985 13:08:30.599598 TX Vref=22, minBit 5, minWin=27, winSum=445
1986 13:08:30.602666 TX Vref=24, minBit 0, minWin=27, winSum=451
1987 13:08:30.606166 TX Vref=26, minBit 1, minWin=28, winSum=454
1988 13:08:30.609613 TX Vref=28, minBit 1, minWin=28, winSum=456
1989 13:08:30.613021 TX Vref=30, minBit 1, minWin=28, winSum=455
1990 13:08:30.615858 TX Vref=32, minBit 1, minWin=28, winSum=453
1991 13:08:30.622965 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 28
1992 13:08:30.623351
1993 13:08:30.626113 Final TX Range 1 Vref 28
1994 13:08:30.626495
1995 13:08:30.626792 ==
1996 13:08:30.629328 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 13:08:30.632735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 13:08:30.633154 ==
1999 13:08:30.633460
2000 13:08:30.633733
2001 13:08:30.636210 TX Vref Scan disable
2002 13:08:30.639362 == TX Byte 0 ==
2003 13:08:30.642749 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
2004 13:08:30.646447 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
2005 13:08:30.649311 == TX Byte 1 ==
2006 13:08:30.652677 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2007 13:08:30.656042 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2008 13:08:30.659323
2009 13:08:30.659706 [DATLAT]
2010 13:08:30.660003 Freq=800, CH1 RK1
2011 13:08:30.660278
2012 13:08:30.662514 DATLAT Default: 0xa
2013 13:08:30.662896 0, 0xFFFF, sum = 0
2014 13:08:30.665894 1, 0xFFFF, sum = 0
2015 13:08:30.666330 2, 0xFFFF, sum = 0
2016 13:08:30.669120 3, 0xFFFF, sum = 0
2017 13:08:30.669540 4, 0xFFFF, sum = 0
2018 13:08:30.672505 5, 0xFFFF, sum = 0
2019 13:08:30.672892 6, 0xFFFF, sum = 0
2020 13:08:30.676170 7, 0xFFFF, sum = 0
2021 13:08:30.679599 8, 0xFFFF, sum = 0
2022 13:08:30.679987 9, 0x0, sum = 1
2023 13:08:30.680287 10, 0x0, sum = 2
2024 13:08:30.682546 11, 0x0, sum = 3
2025 13:08:30.682934 12, 0x0, sum = 4
2026 13:08:30.686483 best_step = 10
2027 13:08:30.686861
2028 13:08:30.687152 ==
2029 13:08:30.689935 Dram Type= 6, Freq= 0, CH_1, rank 1
2030 13:08:30.692983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2031 13:08:30.693456 ==
2032 13:08:30.696334 RX Vref Scan: 0
2033 13:08:30.696723
2034 13:08:30.697026 RX Vref 0 -> 0, step: 1
2035 13:08:30.697342
2036 13:08:30.699303 RX Delay -95 -> 252, step: 8
2037 13:08:30.706474 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2038 13:08:30.709857 iDelay=209, Bit 1, Center 84 (-23 ~ 192) 216
2039 13:08:30.712654 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2040 13:08:30.716622 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
2041 13:08:30.719378 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2042 13:08:30.723080 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2043 13:08:30.729501 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
2044 13:08:30.732859 iDelay=209, Bit 7, Center 84 (-23 ~ 192) 216
2045 13:08:30.736682 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2046 13:08:30.739955 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2047 13:08:30.743031 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2048 13:08:30.749786 iDelay=209, Bit 11, Center 76 (-39 ~ 192) 232
2049 13:08:30.753288 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2050 13:08:30.756569 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2051 13:08:30.759777 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2052 13:08:30.763111 iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232
2053 13:08:30.766318 ==
2054 13:08:30.769531 Dram Type= 6, Freq= 0, CH_1, rank 1
2055 13:08:30.773023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2056 13:08:30.773508 ==
2057 13:08:30.773822 DQS Delay:
2058 13:08:30.776194 DQS0 = 0, DQS1 = 0
2059 13:08:30.776739 DQM Delay:
2060 13:08:30.779646 DQM0 = 90, DQM1 = 82
2061 13:08:30.780045 DQ Delay:
2062 13:08:30.783341 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
2063 13:08:30.786380 DQ4 =92, DQ5 =100, DQ6 =100, DQ7 =84
2064 13:08:30.789936 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =76
2065 13:08:30.793539 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =92
2066 13:08:30.793929
2067 13:08:30.794229
2068 13:08:30.799793 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
2069 13:08:30.803138 CH1 RK1: MR19=606, MR18=3F14
2070 13:08:30.810085 CH1_RK1: MR19=0x606, MR18=0x3F14, DQSOSC=393, MR23=63, INC=95, DEC=63
2071 13:08:30.813042 [RxdqsGatingPostProcess] freq 800
2072 13:08:30.816818 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2073 13:08:30.820208 Pre-setting of DQS Precalculation
2074 13:08:30.826683 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2075 13:08:30.833460 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2076 13:08:30.839768 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2077 13:08:30.840272
2078 13:08:30.840724
2079 13:08:30.843096 [Calibration Summary] 1600 Mbps
2080 13:08:30.846822 CH 0, Rank 0
2081 13:08:30.847203 SW Impedance : PASS
2082 13:08:30.849830 DUTY Scan : NO K
2083 13:08:30.850211 ZQ Calibration : PASS
2084 13:08:30.853564 Jitter Meter : NO K
2085 13:08:30.856760 CBT Training : PASS
2086 13:08:30.857292 Write leveling : PASS
2087 13:08:30.860204 RX DQS gating : PASS
2088 13:08:30.863556 RX DQ/DQS(RDDQC) : PASS
2089 13:08:30.863933 TX DQ/DQS : PASS
2090 13:08:30.866507 RX DATLAT : PASS
2091 13:08:30.869965 RX DQ/DQS(Engine): PASS
2092 13:08:30.870353 TX OE : NO K
2093 13:08:30.870654 All Pass.
2094 13:08:30.873251
2095 13:08:30.873723 CH 0, Rank 1
2096 13:08:30.876884 SW Impedance : PASS
2097 13:08:30.877413 DUTY Scan : NO K
2098 13:08:30.880179 ZQ Calibration : PASS
2099 13:08:30.880672 Jitter Meter : NO K
2100 13:08:30.883416 CBT Training : PASS
2101 13:08:30.886658 Write leveling : PASS
2102 13:08:30.887153 RX DQS gating : PASS
2103 13:08:30.889989 RX DQ/DQS(RDDQC) : PASS
2104 13:08:30.893657 TX DQ/DQS : PASS
2105 13:08:30.894044 RX DATLAT : PASS
2106 13:08:30.896808 RX DQ/DQS(Engine): PASS
2107 13:08:30.900265 TX OE : NO K
2108 13:08:30.900649 All Pass.
2109 13:08:30.900947
2110 13:08:30.901267 CH 1, Rank 0
2111 13:08:30.903580 SW Impedance : PASS
2112 13:08:30.907222 DUTY Scan : NO K
2113 13:08:30.907608 ZQ Calibration : PASS
2114 13:08:30.910334 Jitter Meter : NO K
2115 13:08:30.913673 CBT Training : PASS
2116 13:08:30.914057 Write leveling : PASS
2117 13:08:30.917301 RX DQS gating : PASS
2118 13:08:30.917685 RX DQ/DQS(RDDQC) : PASS
2119 13:08:30.920293 TX DQ/DQS : PASS
2120 13:08:30.923924 RX DATLAT : PASS
2121 13:08:30.924305 RX DQ/DQS(Engine): PASS
2122 13:08:30.926929 TX OE : NO K
2123 13:08:30.927311 All Pass.
2124 13:08:30.927605
2125 13:08:30.930699 CH 1, Rank 1
2126 13:08:30.931077 SW Impedance : PASS
2127 13:08:30.933744 DUTY Scan : NO K
2128 13:08:30.937010 ZQ Calibration : PASS
2129 13:08:30.937447 Jitter Meter : NO K
2130 13:08:30.940531 CBT Training : PASS
2131 13:08:30.943876 Write leveling : PASS
2132 13:08:30.944292 RX DQS gating : PASS
2133 13:08:30.946855 RX DQ/DQS(RDDQC) : PASS
2134 13:08:30.950375 TX DQ/DQS : PASS
2135 13:08:30.950764 RX DATLAT : PASS
2136 13:08:30.953760 RX DQ/DQS(Engine): PASS
2137 13:08:30.954146 TX OE : NO K
2138 13:08:30.956978 All Pass.
2139 13:08:30.957424
2140 13:08:30.957729 DramC Write-DBI off
2141 13:08:30.960567 PER_BANK_REFRESH: Hybrid Mode
2142 13:08:30.963537 TX_TRACKING: ON
2143 13:08:30.966854 [GetDramInforAfterCalByMRR] Vendor 6.
2144 13:08:30.970623 [GetDramInforAfterCalByMRR] Revision 606.
2145 13:08:30.973942 [GetDramInforAfterCalByMRR] Revision 2 0.
2146 13:08:30.974831 MR0 0x3b3b
2147 13:08:30.975175 MR8 0x5151
2148 13:08:30.980382 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2149 13:08:30.980968
2150 13:08:30.981413 MR0 0x3b3b
2151 13:08:30.981706 MR8 0x5151
2152 13:08:30.983696 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2153 13:08:30.984246
2154 13:08:30.993895 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2155 13:08:30.997053 [FAST_K] Save calibration result to emmc
2156 13:08:31.000413 [FAST_K] Save calibration result to emmc
2157 13:08:31.003904 dram_init: config_dvfs: 1
2158 13:08:31.007292 dramc_set_vcore_voltage set vcore to 662500
2159 13:08:31.010621 Read voltage for 1200, 2
2160 13:08:31.010800 Vio18 = 0
2161 13:08:31.010951 Vcore = 662500
2162 13:08:31.013660 Vdram = 0
2163 13:08:31.013830 Vddq = 0
2164 13:08:31.013999 Vmddr = 0
2165 13:08:31.020581 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2166 13:08:31.024093 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2167 13:08:31.027202 MEM_TYPE=3, freq_sel=15
2168 13:08:31.030588 sv_algorithm_assistance_LP4_1600
2169 13:08:31.034357 ============ PULL DRAM RESETB DOWN ============
2170 13:08:31.037231 ========== PULL DRAM RESETB DOWN end =========
2171 13:08:31.044397 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2172 13:08:31.047509 ===================================
2173 13:08:31.047614 LPDDR4 DRAM CONFIGURATION
2174 13:08:31.050524 ===================================
2175 13:08:31.053856 EX_ROW_EN[0] = 0x0
2176 13:08:31.057507 EX_ROW_EN[1] = 0x0
2177 13:08:31.057584 LP4Y_EN = 0x0
2178 13:08:31.060374 WORK_FSP = 0x0
2179 13:08:31.060450 WL = 0x4
2180 13:08:31.064037 RL = 0x4
2181 13:08:31.064122 BL = 0x2
2182 13:08:31.067253 RPST = 0x0
2183 13:08:31.067342 RD_PRE = 0x0
2184 13:08:31.071044 WR_PRE = 0x1
2185 13:08:31.071139 WR_PST = 0x0
2186 13:08:31.074055 DBI_WR = 0x0
2187 13:08:31.074150 DBI_RD = 0x0
2188 13:08:31.077545 OTF = 0x1
2189 13:08:31.080838 ===================================
2190 13:08:31.084743 ===================================
2191 13:08:31.084858 ANA top config
2192 13:08:31.087403 ===================================
2193 13:08:31.091370 DLL_ASYNC_EN = 0
2194 13:08:31.094485 ALL_SLAVE_EN = 0
2195 13:08:31.094659 NEW_RANK_MODE = 1
2196 13:08:31.098050 DLL_IDLE_MODE = 1
2197 13:08:31.100849 LP45_APHY_COMB_EN = 1
2198 13:08:31.104403 TX_ODT_DIS = 1
2199 13:08:31.104637 NEW_8X_MODE = 1
2200 13:08:31.107718 ===================================
2201 13:08:31.111130 ===================================
2202 13:08:31.114567 data_rate = 2400
2203 13:08:31.118356 CKR = 1
2204 13:08:31.121353 DQ_P2S_RATIO = 8
2205 13:08:31.124778 ===================================
2206 13:08:31.128005 CA_P2S_RATIO = 8
2207 13:08:31.131340 DQ_CA_OPEN = 0
2208 13:08:31.131829 DQ_SEMI_OPEN = 0
2209 13:08:31.134411 CA_SEMI_OPEN = 0
2210 13:08:31.137973 CA_FULL_RATE = 0
2211 13:08:31.141540 DQ_CKDIV4_EN = 0
2212 13:08:31.144510 CA_CKDIV4_EN = 0
2213 13:08:31.148180 CA_PREDIV_EN = 0
2214 13:08:31.148672 PH8_DLY = 17
2215 13:08:31.151228 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2216 13:08:31.154405 DQ_AAMCK_DIV = 4
2217 13:08:31.157694 CA_AAMCK_DIV = 4
2218 13:08:31.161581 CA_ADMCK_DIV = 4
2219 13:08:31.164867 DQ_TRACK_CA_EN = 0
2220 13:08:31.165273 CA_PICK = 1200
2221 13:08:31.167983 CA_MCKIO = 1200
2222 13:08:31.171345 MCKIO_SEMI = 0
2223 13:08:31.174817 PLL_FREQ = 2366
2224 13:08:31.177987 DQ_UI_PI_RATIO = 32
2225 13:08:31.181357 CA_UI_PI_RATIO = 0
2226 13:08:31.184993 ===================================
2227 13:08:31.188077 ===================================
2228 13:08:31.188464 memory_type:LPDDR4
2229 13:08:31.191315 GP_NUM : 10
2230 13:08:31.194684 SRAM_EN : 1
2231 13:08:31.195071 MD32_EN : 0
2232 13:08:31.198153 ===================================
2233 13:08:31.201707 [ANA_INIT] >>>>>>>>>>>>>>
2234 13:08:31.205009 <<<<<< [CONFIGURE PHASE]: ANA_TX
2235 13:08:31.208159 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2236 13:08:31.211390 ===================================
2237 13:08:31.214257 data_rate = 2400,PCW = 0X5b00
2238 13:08:31.217685 ===================================
2239 13:08:31.221144 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2240 13:08:31.224224 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2241 13:08:31.231043 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2242 13:08:31.234713 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2243 13:08:31.237906 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2244 13:08:31.241396 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2245 13:08:31.244568 [ANA_INIT] flow start
2246 13:08:31.247821 [ANA_INIT] PLL >>>>>>>>
2247 13:08:31.247906 [ANA_INIT] PLL <<<<<<<<
2248 13:08:31.251254 [ANA_INIT] MIDPI >>>>>>>>
2249 13:08:31.254668 [ANA_INIT] MIDPI <<<<<<<<
2250 13:08:31.254759 [ANA_INIT] DLL >>>>>>>>
2251 13:08:31.258212 [ANA_INIT] DLL <<<<<<<<
2252 13:08:31.261191 [ANA_INIT] flow end
2253 13:08:31.264781 ============ LP4 DIFF to SE enter ============
2254 13:08:31.267812 ============ LP4 DIFF to SE exit ============
2255 13:08:31.271284 [ANA_INIT] <<<<<<<<<<<<<
2256 13:08:31.274404 [Flow] Enable top DCM control >>>>>
2257 13:08:31.278180 [Flow] Enable top DCM control <<<<<
2258 13:08:31.281309 Enable DLL master slave shuffle
2259 13:08:31.284701 ==============================================================
2260 13:08:31.287845 Gating Mode config
2261 13:08:31.294859 ==============================================================
2262 13:08:31.295033 Config description:
2263 13:08:31.304895 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2264 13:08:31.311414 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2265 13:08:31.314923 SELPH_MODE 0: By rank 1: By Phase
2266 13:08:31.321676 ==============================================================
2267 13:08:31.324698 GAT_TRACK_EN = 1
2268 13:08:31.328348 RX_GATING_MODE = 2
2269 13:08:31.331606 RX_GATING_TRACK_MODE = 2
2270 13:08:31.334922 SELPH_MODE = 1
2271 13:08:31.338953 PICG_EARLY_EN = 1
2272 13:08:31.339342 VALID_LAT_VALUE = 1
2273 13:08:31.345452 ==============================================================
2274 13:08:31.348836 Enter into Gating configuration >>>>
2275 13:08:31.352017 Exit from Gating configuration <<<<
2276 13:08:31.355408 Enter into DVFS_PRE_config >>>>>
2277 13:08:31.365496 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2278 13:08:31.368801 Exit from DVFS_PRE_config <<<<<
2279 13:08:31.372060 Enter into PICG configuration >>>>
2280 13:08:31.375236 Exit from PICG configuration <<<<
2281 13:08:31.378618 [RX_INPUT] configuration >>>>>
2282 13:08:31.382291 [RX_INPUT] configuration <<<<<
2283 13:08:31.385407 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2284 13:08:31.391902 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2285 13:08:31.398921 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2286 13:08:31.405470 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2287 13:08:31.409079 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2288 13:08:31.415591 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2289 13:08:31.418694 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2290 13:08:31.425537 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2291 13:08:31.428704 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2292 13:08:31.432027 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2293 13:08:31.435574 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2294 13:08:31.442370 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2295 13:08:31.445534 ===================================
2296 13:08:31.445920 LPDDR4 DRAM CONFIGURATION
2297 13:08:31.449228 ===================================
2298 13:08:31.452335 EX_ROW_EN[0] = 0x0
2299 13:08:31.455463 EX_ROW_EN[1] = 0x0
2300 13:08:31.455862 LP4Y_EN = 0x0
2301 13:08:31.459101 WORK_FSP = 0x0
2302 13:08:31.459482 WL = 0x4
2303 13:08:31.462199 RL = 0x4
2304 13:08:31.462606 BL = 0x2
2305 13:08:31.465806 RPST = 0x0
2306 13:08:31.466190 RD_PRE = 0x0
2307 13:08:31.469399 WR_PRE = 0x1
2308 13:08:31.469784 WR_PST = 0x0
2309 13:08:31.472260 DBI_WR = 0x0
2310 13:08:31.472641 DBI_RD = 0x0
2311 13:08:31.475751 OTF = 0x1
2312 13:08:31.478908 ===================================
2313 13:08:31.482386 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2314 13:08:31.485667 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2315 13:08:31.492591 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2316 13:08:31.496123 ===================================
2317 13:08:31.496512 LPDDR4 DRAM CONFIGURATION
2318 13:08:31.499032 ===================================
2319 13:08:31.502570 EX_ROW_EN[0] = 0x10
2320 13:08:31.505713 EX_ROW_EN[1] = 0x0
2321 13:08:31.506097 LP4Y_EN = 0x0
2322 13:08:31.509246 WORK_FSP = 0x0
2323 13:08:31.509635 WL = 0x4
2324 13:08:31.512271 RL = 0x4
2325 13:08:31.512654 BL = 0x2
2326 13:08:31.515935 RPST = 0x0
2327 13:08:31.516324 RD_PRE = 0x0
2328 13:08:31.519060 WR_PRE = 0x1
2329 13:08:31.519445 WR_PST = 0x0
2330 13:08:31.522128 DBI_WR = 0x0
2331 13:08:31.522516 DBI_RD = 0x0
2332 13:08:31.525875 OTF = 0x1
2333 13:08:31.528945 ===================================
2334 13:08:31.535768 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2335 13:08:31.536161 ==
2336 13:08:31.539114 Dram Type= 6, Freq= 0, CH_0, rank 0
2337 13:08:31.542706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2338 13:08:31.542783 ==
2339 13:08:31.546016 [Duty_Offset_Calibration]
2340 13:08:31.546091 B0:2 B1:0 CA:1
2341 13:08:31.546150
2342 13:08:31.548705 [DutyScan_Calibration_Flow] k_type=0
2343 13:08:31.557601
2344 13:08:31.557688 ==CLK 0==
2345 13:08:31.561344 Final CLK duty delay cell = -4
2346 13:08:31.564077 [-4] MAX Duty = 5031%(X100), DQS PI = 26
2347 13:08:31.567485 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2348 13:08:31.571322 [-4] AVG Duty = 4953%(X100)
2349 13:08:31.571402
2350 13:08:31.574727 CH0 CLK Duty spec in!! Max-Min= 156%
2351 13:08:31.577520 [DutyScan_Calibration_Flow] ====Done====
2352 13:08:31.577607
2353 13:08:31.580909 [DutyScan_Calibration_Flow] k_type=1
2354 13:08:31.596712
2355 13:08:31.596837 ==DQS 0 ==
2356 13:08:31.599857 Final DQS duty delay cell = 0
2357 13:08:31.603042 [0] MAX Duty = 5187%(X100), DQS PI = 32
2358 13:08:31.606517 [0] MIN Duty = 4938%(X100), DQS PI = 0
2359 13:08:31.606677 [0] AVG Duty = 5062%(X100)
2360 13:08:31.609970
2361 13:08:31.610129 ==DQS 1 ==
2362 13:08:31.613166 Final DQS duty delay cell = -4
2363 13:08:31.616507 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2364 13:08:31.619911 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2365 13:08:31.623588 [-4] AVG Duty = 5015%(X100)
2366 13:08:31.623844
2367 13:08:31.626667 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2368 13:08:31.626969
2369 13:08:31.629913 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2370 13:08:31.633658 [DutyScan_Calibration_Flow] ====Done====
2371 13:08:31.634045
2372 13:08:31.636656 [DutyScan_Calibration_Flow] k_type=3
2373 13:08:31.653412
2374 13:08:31.653795 ==DQM 0 ==
2375 13:08:31.657225 Final DQM duty delay cell = 0
2376 13:08:31.660375 [0] MAX Duty = 5062%(X100), DQS PI = 24
2377 13:08:31.663572 [0] MIN Duty = 4813%(X100), DQS PI = 2
2378 13:08:31.663957 [0] AVG Duty = 4937%(X100)
2379 13:08:31.666956
2380 13:08:31.667337 ==DQM 1 ==
2381 13:08:31.670181 Final DQM duty delay cell = 0
2382 13:08:31.673847 [0] MAX Duty = 5187%(X100), DQS PI = 46
2383 13:08:31.676969 [0] MIN Duty = 5000%(X100), DQS PI = 12
2384 13:08:31.677391 [0] AVG Duty = 5093%(X100)
2385 13:08:31.680332
2386 13:08:31.683649 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2387 13:08:31.684033
2388 13:08:31.687226 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2389 13:08:31.690081 [DutyScan_Calibration_Flow] ====Done====
2390 13:08:31.690463
2391 13:08:31.693429 [DutyScan_Calibration_Flow] k_type=2
2392 13:08:31.709362
2393 13:08:31.709437 ==DQ 0 ==
2394 13:08:31.713108 Final DQ duty delay cell = -4
2395 13:08:31.716290 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2396 13:08:31.719839 [-4] MIN Duty = 4844%(X100), DQS PI = 14
2397 13:08:31.723123 [-4] AVG Duty = 4937%(X100)
2398 13:08:31.723216
2399 13:08:31.723288 ==DQ 1 ==
2400 13:08:31.726825 Final DQ duty delay cell = 4
2401 13:08:31.729909 [4] MAX Duty = 5093%(X100), DQS PI = 4
2402 13:08:31.733173 [4] MIN Duty = 5031%(X100), DQS PI = 0
2403 13:08:31.733287 [4] AVG Duty = 5062%(X100)
2404 13:08:31.733373
2405 13:08:31.736494 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2406 13:08:31.740139
2407 13:08:31.740306 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2408 13:08:31.746838 [DutyScan_Calibration_Flow] ====Done====
2409 13:08:31.746995 ==
2410 13:08:31.750189 Dram Type= 6, Freq= 0, CH_1, rank 0
2411 13:08:31.753389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2412 13:08:31.753576 ==
2413 13:08:31.756537 [Duty_Offset_Calibration]
2414 13:08:31.756755 B0:0 B1:-1 CA:2
2415 13:08:31.756925
2416 13:08:31.759780 [DutyScan_Calibration_Flow] k_type=0
2417 13:08:31.770162
2418 13:08:31.770548 ==CLK 0==
2419 13:08:31.773617 Final CLK duty delay cell = 0
2420 13:08:31.776688 [0] MAX Duty = 5156%(X100), DQS PI = 16
2421 13:08:31.780337 [0] MIN Duty = 4938%(X100), DQS PI = 44
2422 13:08:31.780763 [0] AVG Duty = 5047%(X100)
2423 13:08:31.783382
2424 13:08:31.783934 CH1 CLK Duty spec in!! Max-Min= 218%
2425 13:08:31.790522 [DutyScan_Calibration_Flow] ====Done====
2426 13:08:31.790946
2427 13:08:31.793783 [DutyScan_Calibration_Flow] k_type=1
2428 13:08:31.809682
2429 13:08:31.810064 ==DQS 0 ==
2430 13:08:31.813076 Final DQS duty delay cell = 0
2431 13:08:31.816069 [0] MAX Duty = 5093%(X100), DQS PI = 24
2432 13:08:31.819609 [0] MIN Duty = 4969%(X100), DQS PI = 0
2433 13:08:31.819995 [0] AVG Duty = 5031%(X100)
2434 13:08:31.823010
2435 13:08:31.823431 ==DQS 1 ==
2436 13:08:31.826719 Final DQS duty delay cell = 0
2437 13:08:31.829826 [0] MAX Duty = 5156%(X100), DQS PI = 0
2438 13:08:31.832763 [0] MIN Duty = 4844%(X100), DQS PI = 36
2439 13:08:31.833175 [0] AVG Duty = 5000%(X100)
2440 13:08:31.833483
2441 13:08:31.839744 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2442 13:08:31.840173
2443 13:08:31.842892 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2444 13:08:31.846368 [DutyScan_Calibration_Flow] ====Done====
2445 13:08:31.846755
2446 13:08:31.849673 [DutyScan_Calibration_Flow] k_type=3
2447 13:08:31.866618
2448 13:08:31.867038 ==DQM 0 ==
2449 13:08:31.869981 Final DQM duty delay cell = 4
2450 13:08:31.872889 [4] MAX Duty = 5093%(X100), DQS PI = 22
2451 13:08:31.876187 [4] MIN Duty = 4938%(X100), DQS PI = 30
2452 13:08:31.879982 [4] AVG Duty = 5015%(X100)
2453 13:08:31.880068
2454 13:08:31.880134 ==DQM 1 ==
2455 13:08:31.883176 Final DQM duty delay cell = 0
2456 13:08:31.886392 [0] MAX Duty = 5249%(X100), DQS PI = 0
2457 13:08:31.889717 [0] MIN Duty = 4875%(X100), DQS PI = 36
2458 13:08:31.889814 [0] AVG Duty = 5062%(X100)
2459 13:08:31.893111
2460 13:08:31.896342 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2461 13:08:31.896455
2462 13:08:31.899555 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2463 13:08:31.902952 [DutyScan_Calibration_Flow] ====Done====
2464 13:08:31.903078
2465 13:08:31.906549 [DutyScan_Calibration_Flow] k_type=2
2466 13:08:31.922796
2467 13:08:31.923026 ==DQ 0 ==
2468 13:08:31.926587 Final DQ duty delay cell = 0
2469 13:08:31.930060 [0] MAX Duty = 5062%(X100), DQS PI = 20
2470 13:08:31.933381 [0] MIN Duty = 4938%(X100), DQS PI = 0
2471 13:08:31.933764 [0] AVG Duty = 5000%(X100)
2472 13:08:31.934057
2473 13:08:31.936667 ==DQ 1 ==
2474 13:08:31.937170 Final DQ duty delay cell = 0
2475 13:08:31.940248 [0] MAX Duty = 5031%(X100), DQS PI = 2
2476 13:08:31.947189 [0] MIN Duty = 4813%(X100), DQS PI = 34
2477 13:08:31.947749 [0] AVG Duty = 4922%(X100)
2478 13:08:31.948219
2479 13:08:31.950212 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2480 13:08:31.950601
2481 13:08:31.953433 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2482 13:08:31.956788 [DutyScan_Calibration_Flow] ====Done====
2483 13:08:31.962339 nWR fixed to 30
2484 13:08:31.965406 [ModeRegInit_LP4] CH0 RK0
2485 13:08:31.965799 [ModeRegInit_LP4] CH0 RK1
2486 13:08:31.968985 [ModeRegInit_LP4] CH1 RK0
2487 13:08:31.972281 [ModeRegInit_LP4] CH1 RK1
2488 13:08:31.972791 match AC timing 7
2489 13:08:31.978786 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2490 13:08:31.982140 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2491 13:08:31.985685 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2492 13:08:31.992486 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2493 13:08:31.995617 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2494 13:08:31.996026 ==
2495 13:08:31.999088 Dram Type= 6, Freq= 0, CH_0, rank 0
2496 13:08:32.002394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2497 13:08:32.002790 ==
2498 13:08:32.008823 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2499 13:08:32.015869 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2500 13:08:32.022975 [CA 0] Center 38 (8~69) winsize 62
2501 13:08:32.026403 [CA 1] Center 38 (8~69) winsize 62
2502 13:08:32.029807 [CA 2] Center 35 (5~66) winsize 62
2503 13:08:32.032940 [CA 3] Center 35 (4~66) winsize 63
2504 13:08:32.036267 [CA 4] Center 34 (4~65) winsize 62
2505 13:08:32.040030 [CA 5] Center 33 (3~64) winsize 62
2506 13:08:32.040637
2507 13:08:32.043326 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2508 13:08:32.043784
2509 13:08:32.046560 [CATrainingPosCal] consider 1 rank data
2510 13:08:32.049598 u2DelayCellTimex100 = 270/100 ps
2511 13:08:32.053505 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2512 13:08:32.056590 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2513 13:08:32.059785 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2514 13:08:32.066436 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2515 13:08:32.070082 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2516 13:08:32.073444 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2517 13:08:32.073831
2518 13:08:32.076707 CA PerBit enable=1, Macro0, CA PI delay=33
2519 13:08:32.077093
2520 13:08:32.079997 [CBTSetCACLKResult] CA Dly = 33
2521 13:08:32.080385 CS Dly: 6 (0~37)
2522 13:08:32.080688 ==
2523 13:08:32.083339 Dram Type= 6, Freq= 0, CH_0, rank 1
2524 13:08:32.090137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 13:08:32.090602 ==
2526 13:08:32.093526 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2527 13:08:32.100005 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2528 13:08:32.108714 [CA 0] Center 39 (8~70) winsize 63
2529 13:08:32.112381 [CA 1] Center 38 (8~69) winsize 62
2530 13:08:32.115418 [CA 2] Center 35 (5~66) winsize 62
2531 13:08:32.118880 [CA 3] Center 35 (5~66) winsize 62
2532 13:08:32.122161 [CA 4] Center 34 (4~65) winsize 62
2533 13:08:32.125584 [CA 5] Center 34 (4~64) winsize 61
2534 13:08:32.125983
2535 13:08:32.129218 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2536 13:08:32.129618
2537 13:08:32.132012 [CATrainingPosCal] consider 2 rank data
2538 13:08:32.135374 u2DelayCellTimex100 = 270/100 ps
2539 13:08:32.138587 CA0 delay=38 (8~69),Diff = 4 PI (19 cell)
2540 13:08:32.141999 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
2541 13:08:32.148606 CA2 delay=35 (5~66),Diff = 1 PI (4 cell)
2542 13:08:32.151990 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2543 13:08:32.155395 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2544 13:08:32.158829 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2545 13:08:32.159379
2546 13:08:32.162354 CA PerBit enable=1, Macro0, CA PI delay=34
2547 13:08:32.162754
2548 13:08:32.165332 [CBTSetCACLKResult] CA Dly = 34
2549 13:08:32.165732 CS Dly: 7 (0~39)
2550 13:08:32.166125
2551 13:08:32.168606 ----->DramcWriteLeveling(PI) begin...
2552 13:08:32.172040 ==
2553 13:08:32.175232 Dram Type= 6, Freq= 0, CH_0, rank 0
2554 13:08:32.178598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2555 13:08:32.179049 ==
2556 13:08:32.182328 Write leveling (Byte 0): 34 => 34
2557 13:08:32.185772 Write leveling (Byte 1): 32 => 32
2558 13:08:32.188623 DramcWriteLeveling(PI) end<-----
2559 13:08:32.189014
2560 13:08:32.189369 ==
2561 13:08:32.191922 Dram Type= 6, Freq= 0, CH_0, rank 0
2562 13:08:32.195243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2563 13:08:32.195806 ==
2564 13:08:32.198592 [Gating] SW mode calibration
2565 13:08:32.205244 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2566 13:08:32.211765 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2567 13:08:32.215519 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2568 13:08:32.218613 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2569 13:08:32.222038 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2570 13:08:32.228823 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2571 13:08:32.231874 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2572 13:08:32.235477 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2573 13:08:32.241666 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2574 13:08:32.245171 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2575 13:08:32.248604 1 0 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
2576 13:08:32.255742 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2577 13:08:32.259035 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2578 13:08:32.262027 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2579 13:08:32.268752 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2580 13:08:32.271947 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2581 13:08:32.275348 1 0 24 | B1->B0 | 2323 3a3a | 0 1 | (0 0) (0 0)
2582 13:08:32.282140 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2583 13:08:32.285517 1 1 0 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)
2584 13:08:32.288925 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 13:08:32.292467 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2586 13:08:32.298887 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2587 13:08:32.302344 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2588 13:08:32.305578 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2589 13:08:32.312698 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2590 13:08:32.315492 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2591 13:08:32.319208 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2592 13:08:32.325627 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 13:08:32.329196 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 13:08:32.332312 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 13:08:32.338868 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 13:08:32.342214 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 13:08:32.345755 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 13:08:32.352443 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 13:08:32.355907 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 13:08:32.359083 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 13:08:32.362428 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 13:08:32.369075 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 13:08:32.372570 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 13:08:32.376219 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 13:08:32.382453 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 13:08:32.386022 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2607 13:08:32.389262 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2608 13:08:32.392270 Total UI for P1: 0, mck2ui 16
2609 13:08:32.395752 best dqsien dly found for B0: ( 1, 3, 28)
2610 13:08:32.403039 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 13:08:32.403433 Total UI for P1: 0, mck2ui 16
2612 13:08:32.409545 best dqsien dly found for B1: ( 1, 3, 30)
2613 13:08:32.412777 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2614 13:08:32.416021 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2615 13:08:32.416409
2616 13:08:32.419673 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2617 13:08:32.422925 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2618 13:08:32.426043 [Gating] SW calibration Done
2619 13:08:32.426469 ==
2620 13:08:32.429991 Dram Type= 6, Freq= 0, CH_0, rank 0
2621 13:08:32.432647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2622 13:08:32.433042 ==
2623 13:08:32.436561 RX Vref Scan: 0
2624 13:08:32.436950
2625 13:08:32.437287 RX Vref 0 -> 0, step: 1
2626 13:08:32.437573
2627 13:08:32.439427 RX Delay -40 -> 252, step: 8
2628 13:08:32.443055 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
2629 13:08:32.446238 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2630 13:08:32.452872 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2631 13:08:32.455862 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2632 13:08:32.459361 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2633 13:08:32.462530 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2634 13:08:32.465970 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2635 13:08:32.472804 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2636 13:08:32.476309 iDelay=208, Bit 8, Center 103 (40 ~ 167) 128
2637 13:08:32.479274 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2638 13:08:32.482892 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2639 13:08:32.485976 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2640 13:08:32.493253 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2641 13:08:32.496102 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2642 13:08:32.499371 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2643 13:08:32.502850 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2644 13:08:32.503011 ==
2645 13:08:32.506200 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 13:08:32.509517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 13:08:32.512914 ==
2648 13:08:32.513159 DQS Delay:
2649 13:08:32.513387 DQS0 = 0, DQS1 = 0
2650 13:08:32.516439 DQM Delay:
2651 13:08:32.516724 DQM0 = 122, DQM1 = 110
2652 13:08:32.519463 DQ Delay:
2653 13:08:32.522821 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2654 13:08:32.526453 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2655 13:08:32.529719 DQ8 =103, DQ9 =99, DQ10 =107, DQ11 =107
2656 13:08:32.533106 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2657 13:08:32.533198
2658 13:08:32.533280
2659 13:08:32.533359 ==
2660 13:08:32.536380 Dram Type= 6, Freq= 0, CH_0, rank 0
2661 13:08:32.539473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2662 13:08:32.539563 ==
2663 13:08:32.539654
2664 13:08:32.539737
2665 13:08:32.542890 TX Vref Scan disable
2666 13:08:32.546505 == TX Byte 0 ==
2667 13:08:32.549868 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2668 13:08:32.553302 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2669 13:08:32.556531 == TX Byte 1 ==
2670 13:08:32.559474 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2671 13:08:32.562928 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2672 13:08:32.563072 ==
2673 13:08:32.566289 Dram Type= 6, Freq= 0, CH_0, rank 0
2674 13:08:32.569626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2675 13:08:32.572710 ==
2676 13:08:32.583501 TX Vref=22, minBit 3, minWin=23, winSum=401
2677 13:08:32.586545 TX Vref=24, minBit 0, minWin=24, winSum=413
2678 13:08:32.590188 TX Vref=26, minBit 7, minWin=24, winSum=415
2679 13:08:32.593330 TX Vref=28, minBit 1, minWin=25, winSum=418
2680 13:08:32.596928 TX Vref=30, minBit 3, minWin=25, winSum=419
2681 13:08:32.600094 TX Vref=32, minBit 0, minWin=25, winSum=415
2682 13:08:32.607087 [TxChooseVref] Worse bit 3, Min win 25, Win sum 419, Final Vref 30
2683 13:08:32.607478
2684 13:08:32.610512 Final TX Range 1 Vref 30
2685 13:08:32.610907
2686 13:08:32.611213 ==
2687 13:08:32.613661 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 13:08:32.617437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 13:08:32.617831 ==
2690 13:08:32.618138
2691 13:08:32.618418
2692 13:08:32.620948 TX Vref Scan disable
2693 13:08:32.623483 == TX Byte 0 ==
2694 13:08:32.626848 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2695 13:08:32.630315 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2696 13:08:32.633622 == TX Byte 1 ==
2697 13:08:32.637209 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2698 13:08:32.639869 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2699 13:08:32.640041
2700 13:08:32.643220 [DATLAT]
2701 13:08:32.643421 Freq=1200, CH0 RK0
2702 13:08:32.643622
2703 13:08:32.647034 DATLAT Default: 0xd
2704 13:08:32.647278 0, 0xFFFF, sum = 0
2705 13:08:32.650283 1, 0xFFFF, sum = 0
2706 13:08:32.650580 2, 0xFFFF, sum = 0
2707 13:08:32.653389 3, 0xFFFF, sum = 0
2708 13:08:32.653703 4, 0xFFFF, sum = 0
2709 13:08:32.656757 5, 0xFFFF, sum = 0
2710 13:08:32.657193 6, 0xFFFF, sum = 0
2711 13:08:32.660427 7, 0xFFFF, sum = 0
2712 13:08:32.660833 8, 0xFFFF, sum = 0
2713 13:08:32.663569 9, 0xFFFF, sum = 0
2714 13:08:32.663973 10, 0xFFFF, sum = 0
2715 13:08:32.666913 11, 0xFFFF, sum = 0
2716 13:08:32.667317 12, 0x0, sum = 1
2717 13:08:32.670823 13, 0x0, sum = 2
2718 13:08:32.671228 14, 0x0, sum = 3
2719 13:08:32.673453 15, 0x0, sum = 4
2720 13:08:32.673856 best_step = 13
2721 13:08:32.674249
2722 13:08:32.674615 ==
2723 13:08:32.677061 Dram Type= 6, Freq= 0, CH_0, rank 0
2724 13:08:32.683646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2725 13:08:32.683722 ==
2726 13:08:32.683782 RX Vref Scan: 1
2727 13:08:32.683837
2728 13:08:32.686793 Set Vref Range= 32 -> 127
2729 13:08:32.686869
2730 13:08:32.690228 RX Vref 32 -> 127, step: 1
2731 13:08:32.690304
2732 13:08:32.693365 RX Delay -13 -> 252, step: 4
2733 13:08:32.693446
2734 13:08:32.696384 Set Vref, RX VrefLevel [Byte0]: 32
2735 13:08:32.696471 [Byte1]: 32
2736 13:08:32.701329
2737 13:08:32.701456 Set Vref, RX VrefLevel [Byte0]: 33
2738 13:08:32.704501 [Byte1]: 33
2739 13:08:32.709699
2740 13:08:32.709801 Set Vref, RX VrefLevel [Byte0]: 34
2741 13:08:32.712479 [Byte1]: 34
2742 13:08:32.717020
2743 13:08:32.717153 Set Vref, RX VrefLevel [Byte0]: 35
2744 13:08:32.720590 [Byte1]: 35
2745 13:08:32.724813
2746 13:08:32.724952 Set Vref, RX VrefLevel [Byte0]: 36
2747 13:08:32.728601 [Byte1]: 36
2748 13:08:32.732859
2749 13:08:32.733043 Set Vref, RX VrefLevel [Byte0]: 37
2750 13:08:32.736381 [Byte1]: 37
2751 13:08:32.740899
2752 13:08:32.741190 Set Vref, RX VrefLevel [Byte0]: 38
2753 13:08:32.744126 [Byte1]: 38
2754 13:08:32.749098
2755 13:08:32.749483 Set Vref, RX VrefLevel [Byte0]: 39
2756 13:08:32.752321 [Byte1]: 39
2757 13:08:32.757075
2758 13:08:32.757490 Set Vref, RX VrefLevel [Byte0]: 40
2759 13:08:32.760153 [Byte1]: 40
2760 13:08:32.764345
2761 13:08:32.764747 Set Vref, RX VrefLevel [Byte0]: 41
2762 13:08:32.768165 [Byte1]: 41
2763 13:08:32.772821
2764 13:08:32.773254 Set Vref, RX VrefLevel [Byte0]: 42
2765 13:08:32.775799 [Byte1]: 42
2766 13:08:32.780368
2767 13:08:32.780767 Set Vref, RX VrefLevel [Byte0]: 43
2768 13:08:32.783718 [Byte1]: 43
2769 13:08:32.788118
2770 13:08:32.788629 Set Vref, RX VrefLevel [Byte0]: 44
2771 13:08:32.791763 [Byte1]: 44
2772 13:08:32.796565
2773 13:08:32.796961 Set Vref, RX VrefLevel [Byte0]: 45
2774 13:08:32.799773 [Byte1]: 45
2775 13:08:32.803958
2776 13:08:32.804347 Set Vref, RX VrefLevel [Byte0]: 46
2777 13:08:32.807592 [Byte1]: 46
2778 13:08:32.812140
2779 13:08:32.812530 Set Vref, RX VrefLevel [Byte0]: 47
2780 13:08:32.815350 [Byte1]: 47
2781 13:08:32.819925
2782 13:08:32.820338 Set Vref, RX VrefLevel [Byte0]: 48
2783 13:08:32.826140 [Byte1]: 48
2784 13:08:32.826651
2785 13:08:32.829722 Set Vref, RX VrefLevel [Byte0]: 49
2786 13:08:32.833308 [Byte1]: 49
2787 13:08:32.833750
2788 13:08:32.836237 Set Vref, RX VrefLevel [Byte0]: 50
2789 13:08:32.839418 [Byte1]: 50
2790 13:08:32.843281
2791 13:08:32.843797 Set Vref, RX VrefLevel [Byte0]: 51
2792 13:08:32.846540 [Byte1]: 51
2793 13:08:32.851046
2794 13:08:32.851255 Set Vref, RX VrefLevel [Byte0]: 52
2795 13:08:32.854554 [Byte1]: 52
2796 13:08:32.859129
2797 13:08:32.859339 Set Vref, RX VrefLevel [Byte0]: 53
2798 13:08:32.862289 [Byte1]: 53
2799 13:08:32.866920
2800 13:08:32.867129 Set Vref, RX VrefLevel [Byte0]: 54
2801 13:08:32.870432 [Byte1]: 54
2802 13:08:32.875056
2803 13:08:32.875267 Set Vref, RX VrefLevel [Byte0]: 55
2804 13:08:32.878498 [Byte1]: 55
2805 13:08:32.883137
2806 13:08:32.883469 Set Vref, RX VrefLevel [Byte0]: 56
2807 13:08:32.886074 [Byte1]: 56
2808 13:08:32.890904
2809 13:08:32.891293 Set Vref, RX VrefLevel [Byte0]: 57
2810 13:08:32.894216 [Byte1]: 57
2811 13:08:32.898651
2812 13:08:32.899059 Set Vref, RX VrefLevel [Byte0]: 58
2813 13:08:32.902143 [Byte1]: 58
2814 13:08:32.906904
2815 13:08:32.907389 Set Vref, RX VrefLevel [Byte0]: 59
2816 13:08:32.910165 [Byte1]: 59
2817 13:08:32.914271
2818 13:08:32.917636 Set Vref, RX VrefLevel [Byte0]: 60
2819 13:08:32.918091 [Byte1]: 60
2820 13:08:32.922761
2821 13:08:32.923153 Set Vref, RX VrefLevel [Byte0]: 61
2822 13:08:32.926035 [Byte1]: 61
2823 13:08:32.930394
2824 13:08:32.930865 Set Vref, RX VrefLevel [Byte0]: 62
2825 13:08:32.933838 [Byte1]: 62
2826 13:08:32.938235
2827 13:08:32.938753 Set Vref, RX VrefLevel [Byte0]: 63
2828 13:08:32.941475 [Byte1]: 63
2829 13:08:32.946364
2830 13:08:32.946769 Set Vref, RX VrefLevel [Byte0]: 64
2831 13:08:32.949442 [Byte1]: 64
2832 13:08:32.953410
2833 13:08:32.953510 Set Vref, RX VrefLevel [Byte0]: 65
2834 13:08:32.957081 [Byte1]: 65
2835 13:08:32.961473
2836 13:08:32.961552 Set Vref, RX VrefLevel [Byte0]: 66
2837 13:08:32.964687 [Byte1]: 66
2838 13:08:32.969465
2839 13:08:32.969541 Set Vref, RX VrefLevel [Byte0]: 67
2840 13:08:32.972795 [Byte1]: 67
2841 13:08:32.977110
2842 13:08:32.977216 Set Vref, RX VrefLevel [Byte0]: 68
2843 13:08:32.980678 [Byte1]: 68
2844 13:08:32.985001
2845 13:08:32.985102 Set Vref, RX VrefLevel [Byte0]: 69
2846 13:08:32.988324 [Byte1]: 69
2847 13:08:32.993046
2848 13:08:32.993183 Set Vref, RX VrefLevel [Byte0]: 70
2849 13:08:32.996153 [Byte1]: 70
2850 13:08:33.000979
2851 13:08:33.001080 Final RX Vref Byte 0 = 54 to rank0
2852 13:08:33.004263 Final RX Vref Byte 1 = 49 to rank0
2853 13:08:33.007670 Final RX Vref Byte 0 = 54 to rank1
2854 13:08:33.010921 Final RX Vref Byte 1 = 49 to rank1==
2855 13:08:33.014118 Dram Type= 6, Freq= 0, CH_0, rank 0
2856 13:08:33.021169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2857 13:08:33.021261 ==
2858 13:08:33.021322 DQS Delay:
2859 13:08:33.021376 DQS0 = 0, DQS1 = 0
2860 13:08:33.024200 DQM Delay:
2861 13:08:33.024275 DQM0 = 122, DQM1 = 109
2862 13:08:33.027602 DQ Delay:
2863 13:08:33.030913 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =118
2864 13:08:33.034780 DQ4 =122, DQ5 =116, DQ6 =130, DQ7 =128
2865 13:08:33.037697 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =108
2866 13:08:33.041413 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2867 13:08:33.041491
2868 13:08:33.041550
2869 13:08:33.047937 [DQSOSCAuto] RK0, (LSB)MR18= 0xd0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2870 13:08:33.051190 CH0 RK0: MR19=404, MR18=D0A
2871 13:08:33.058250 CH0_RK0: MR19=0x404, MR18=0xD0A, DQSOSC=405, MR23=63, INC=39, DEC=26
2872 13:08:33.058328
2873 13:08:33.061721 ----->DramcWriteLeveling(PI) begin...
2874 13:08:33.061800 ==
2875 13:08:33.064900 Dram Type= 6, Freq= 0, CH_0, rank 1
2876 13:08:33.068200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2877 13:08:33.068294 ==
2878 13:08:33.071340 Write leveling (Byte 0): 36 => 36
2879 13:08:33.074560 Write leveling (Byte 1): 29 => 29
2880 13:08:33.078047 DramcWriteLeveling(PI) end<-----
2881 13:08:33.078216
2882 13:08:33.078319 ==
2883 13:08:33.081070 Dram Type= 6, Freq= 0, CH_0, rank 1
2884 13:08:33.084943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2885 13:08:33.085053 ==
2886 13:08:33.088379 [Gating] SW mode calibration
2887 13:08:33.094535 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2888 13:08:33.101766 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2889 13:08:33.104590 0 15 0 | B1->B0 | 3131 3434 | 0 0 | (1 1) (0 0)
2890 13:08:33.111497 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2891 13:08:33.114711 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2892 13:08:33.118067 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 13:08:33.121326 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 13:08:33.128250 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 13:08:33.131387 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 13:08:33.134703 0 15 28 | B1->B0 | 2e2e 2c2c | 0 0 | (1 0) (1 0)
2897 13:08:33.141473 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2898 13:08:33.145073 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2899 13:08:33.148789 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2900 13:08:33.154825 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 13:08:33.158408 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 13:08:33.161705 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 13:08:33.168347 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2904 13:08:33.171330 1 0 28 | B1->B0 | 3838 4040 | 0 1 | (0 0) (0 0)
2905 13:08:33.175000 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 13:08:33.181818 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 13:08:33.184815 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 13:08:33.188810 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 13:08:33.195051 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 13:08:33.198460 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 13:08:33.201742 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 13:08:33.204986 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2913 13:08:33.211761 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 13:08:33.215208 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 13:08:33.218618 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 13:08:33.224810 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 13:08:33.228149 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 13:08:33.231609 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 13:08:33.238559 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 13:08:33.241548 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 13:08:33.245439 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 13:08:33.252053 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 13:08:33.255246 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 13:08:33.258536 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 13:08:33.265013 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 13:08:33.268692 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 13:08:33.271713 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 13:08:33.278605 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2929 13:08:33.281542 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2930 13:08:33.285608 Total UI for P1: 0, mck2ui 16
2931 13:08:33.288606 best dqsien dly found for B1: ( 1, 3, 28)
2932 13:08:33.292114 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 13:08:33.295161 Total UI for P1: 0, mck2ui 16
2934 13:08:33.298566 best dqsien dly found for B0: ( 1, 3, 30)
2935 13:08:33.302180 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2936 13:08:33.305024 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2937 13:08:33.305122
2938 13:08:33.309029 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2939 13:08:33.312004 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2940 13:08:33.315168 [Gating] SW calibration Done
2941 13:08:33.315310 ==
2942 13:08:33.318763 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 13:08:33.325093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 13:08:33.325278 ==
2945 13:08:33.325374 RX Vref Scan: 0
2946 13:08:33.325463
2947 13:08:33.328686 RX Vref 0 -> 0, step: 1
2948 13:08:33.328879
2949 13:08:33.331855 RX Delay -40 -> 252, step: 8
2950 13:08:33.335348 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2951 13:08:33.338670 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2952 13:08:33.342217 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2953 13:08:33.345365 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2954 13:08:33.352126 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2955 13:08:33.355303 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2956 13:08:33.358882 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2957 13:08:33.361901 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2958 13:08:33.365777 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2959 13:08:33.368540 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2960 13:08:33.375184 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2961 13:08:33.378792 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2962 13:08:33.382408 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2963 13:08:33.385409 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2964 13:08:33.392157 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2965 13:08:33.395667 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2966 13:08:33.395792 ==
2967 13:08:33.398572 Dram Type= 6, Freq= 0, CH_0, rank 1
2968 13:08:33.402473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2969 13:08:33.402577 ==
2970 13:08:33.402665 DQS Delay:
2971 13:08:33.405312 DQS0 = 0, DQS1 = 0
2972 13:08:33.405407 DQM Delay:
2973 13:08:33.408689 DQM0 = 119, DQM1 = 108
2974 13:08:33.408790 DQ Delay:
2975 13:08:33.412046 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2976 13:08:33.415970 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2977 13:08:33.418799 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2978 13:08:33.422561 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2979 13:08:33.422661
2980 13:08:33.425244
2981 13:08:33.425339 ==
2982 13:08:33.428857 Dram Type= 6, Freq= 0, CH_0, rank 1
2983 13:08:33.432098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2984 13:08:33.432193 ==
2985 13:08:33.432283
2986 13:08:33.432365
2987 13:08:33.435560 TX Vref Scan disable
2988 13:08:33.435654 == TX Byte 0 ==
2989 13:08:33.442061 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2990 13:08:33.445577 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2991 13:08:33.445684 == TX Byte 1 ==
2992 13:08:33.448623 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2993 13:08:33.455653 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2994 13:08:33.455799 ==
2995 13:08:33.458871 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 13:08:33.462067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 13:08:33.462167 ==
2998 13:08:33.475075 TX Vref=22, minBit 5, minWin=24, winSum=417
2999 13:08:33.478200 TX Vref=24, minBit 0, minWin=25, winSum=419
3000 13:08:33.481568 TX Vref=26, minBit 0, minWin=26, winSum=424
3001 13:08:33.484763 TX Vref=28, minBit 0, minWin=26, winSum=432
3002 13:08:33.488481 TX Vref=30, minBit 1, minWin=26, winSum=432
3003 13:08:33.491823 TX Vref=32, minBit 0, minWin=26, winSum=430
3004 13:08:33.498440 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
3005 13:08:33.498521
3006 13:08:33.501575 Final TX Range 1 Vref 28
3007 13:08:33.501647
3008 13:08:33.501708 ==
3009 13:08:33.504946 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 13:08:33.508040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 13:08:33.508115 ==
3012 13:08:33.508176
3013 13:08:33.508265
3014 13:08:33.511402 TX Vref Scan disable
3015 13:08:33.515283 == TX Byte 0 ==
3016 13:08:33.518293 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3017 13:08:33.522099 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3018 13:08:33.525099 == TX Byte 1 ==
3019 13:08:33.528450 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3020 13:08:33.531931 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3021 13:08:33.532027
3022 13:08:33.535042 [DATLAT]
3023 13:08:33.535119 Freq=1200, CH0 RK1
3024 13:08:33.535184
3025 13:08:33.538774 DATLAT Default: 0xd
3026 13:08:33.538878 0, 0xFFFF, sum = 0
3027 13:08:33.542106 1, 0xFFFF, sum = 0
3028 13:08:33.542185 2, 0xFFFF, sum = 0
3029 13:08:33.545265 3, 0xFFFF, sum = 0
3030 13:08:33.545345 4, 0xFFFF, sum = 0
3031 13:08:33.548522 5, 0xFFFF, sum = 0
3032 13:08:33.548629 6, 0xFFFF, sum = 0
3033 13:08:33.551805 7, 0xFFFF, sum = 0
3034 13:08:33.551904 8, 0xFFFF, sum = 0
3035 13:08:33.555093 9, 0xFFFF, sum = 0
3036 13:08:33.555178 10, 0xFFFF, sum = 0
3037 13:08:33.558420 11, 0xFFFF, sum = 0
3038 13:08:33.558500 12, 0x0, sum = 1
3039 13:08:33.562044 13, 0x0, sum = 2
3040 13:08:33.562124 14, 0x0, sum = 3
3041 13:08:33.565053 15, 0x0, sum = 4
3042 13:08:33.565150 best_step = 13
3043 13:08:33.565214
3044 13:08:33.565271 ==
3045 13:08:33.568509 Dram Type= 6, Freq= 0, CH_0, rank 1
3046 13:08:33.575051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3047 13:08:33.575130 ==
3048 13:08:33.575194 RX Vref Scan: 0
3049 13:08:33.575251
3050 13:08:33.578182 RX Vref 0 -> 0, step: 1
3051 13:08:33.578286
3052 13:08:33.581620 RX Delay -21 -> 252, step: 4
3053 13:08:33.584930 iDelay=195, Bit 0, Center 116 (51 ~ 182) 132
3054 13:08:33.588674 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3055 13:08:33.595337 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3056 13:08:33.598867 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3057 13:08:33.602209 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3058 13:08:33.605228 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3059 13:08:33.608715 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3060 13:08:33.611738 iDelay=195, Bit 7, Center 124 (59 ~ 190) 132
3061 13:08:33.619168 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3062 13:08:33.622106 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3063 13:08:33.625064 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3064 13:08:33.628581 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3065 13:08:33.632220 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3066 13:08:33.638548 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3067 13:08:33.641817 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3068 13:08:33.645769 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3069 13:08:33.645865 ==
3070 13:08:33.648774 Dram Type= 6, Freq= 0, CH_0, rank 1
3071 13:08:33.652188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 13:08:33.652286 ==
3073 13:08:33.655612 DQS Delay:
3074 13:08:33.655713 DQS0 = 0, DQS1 = 0
3075 13:08:33.659044 DQM Delay:
3076 13:08:33.659156 DQM0 = 119, DQM1 = 107
3077 13:08:33.659292 DQ Delay:
3078 13:08:33.665418 DQ0 =116, DQ1 =122, DQ2 =116, DQ3 =114
3079 13:08:33.669006 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3080 13:08:33.672386 DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =106
3081 13:08:33.675883 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3082 13:08:33.675977
3083 13:08:33.676062
3084 13:08:33.682337 [DQSOSCAuto] RK1, (LSB)MR18= 0x15fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 401 ps
3085 13:08:33.685540 CH0 RK1: MR19=403, MR18=15FB
3086 13:08:33.692199 CH0_RK1: MR19=0x403, MR18=0x15FB, DQSOSC=401, MR23=63, INC=40, DEC=27
3087 13:08:33.695558 [RxdqsGatingPostProcess] freq 1200
3088 13:08:33.698896 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3089 13:08:33.702418 best DQS0 dly(2T, 0.5T) = (0, 11)
3090 13:08:33.705473 best DQS1 dly(2T, 0.5T) = (0, 11)
3091 13:08:33.708926 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3092 13:08:33.712483 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3093 13:08:33.715078 best DQS0 dly(2T, 0.5T) = (0, 11)
3094 13:08:33.718963 best DQS1 dly(2T, 0.5T) = (0, 11)
3095 13:08:33.722243 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3096 13:08:33.725347 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3097 13:08:33.728651 Pre-setting of DQS Precalculation
3098 13:08:33.732137 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3099 13:08:33.735415 ==
3100 13:08:33.735492 Dram Type= 6, Freq= 0, CH_1, rank 0
3101 13:08:33.742389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 13:08:33.742467 ==
3103 13:08:33.745726 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3104 13:08:33.752114 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3105 13:08:33.761112 [CA 0] Center 38 (8~68) winsize 61
3106 13:08:33.764399 [CA 1] Center 37 (7~68) winsize 62
3107 13:08:33.767664 [CA 2] Center 35 (5~65) winsize 61
3108 13:08:33.771150 [CA 3] Center 34 (4~65) winsize 62
3109 13:08:33.774592 [CA 4] Center 34 (4~65) winsize 62
3110 13:08:33.777766 [CA 5] Center 33 (3~64) winsize 62
3111 13:08:33.777842
3112 13:08:33.781354 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3113 13:08:33.781430
3114 13:08:33.784845 [CATrainingPosCal] consider 1 rank data
3115 13:08:33.787805 u2DelayCellTimex100 = 270/100 ps
3116 13:08:33.791118 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3117 13:08:33.794620 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3118 13:08:33.801516 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3119 13:08:33.804353 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3120 13:08:33.807890 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3121 13:08:33.811228 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3122 13:08:33.811305
3123 13:08:33.814690 CA PerBit enable=1, Macro0, CA PI delay=33
3124 13:08:33.814767
3125 13:08:33.817877 [CBTSetCACLKResult] CA Dly = 33
3126 13:08:33.817953 CS Dly: 5 (0~36)
3127 13:08:33.818014 ==
3128 13:08:33.821021 Dram Type= 6, Freq= 0, CH_1, rank 1
3129 13:08:33.827489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 13:08:33.827567 ==
3131 13:08:33.831279 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3132 13:08:33.837798 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3133 13:08:33.846808 [CA 0] Center 38 (8~68) winsize 61
3134 13:08:33.850108 [CA 1] Center 38 (8~68) winsize 61
3135 13:08:33.853351 [CA 2] Center 35 (5~66) winsize 62
3136 13:08:33.856819 [CA 3] Center 34 (4~65) winsize 62
3137 13:08:33.860348 [CA 4] Center 35 (5~65) winsize 61
3138 13:08:33.863355 [CA 5] Center 34 (4~65) winsize 62
3139 13:08:33.863431
3140 13:08:33.866733 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3141 13:08:33.866809
3142 13:08:33.869896 [CATrainingPosCal] consider 2 rank data
3143 13:08:33.873474 u2DelayCellTimex100 = 270/100 ps
3144 13:08:33.876863 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3145 13:08:33.879937 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3146 13:08:33.887012 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3147 13:08:33.890749 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3148 13:08:33.893787 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3149 13:08:33.897025 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3150 13:08:33.897102
3151 13:08:33.899954 CA PerBit enable=1, Macro0, CA PI delay=34
3152 13:08:33.900031
3153 13:08:33.903493 [CBTSetCACLKResult] CA Dly = 34
3154 13:08:33.903571 CS Dly: 6 (0~39)
3155 13:08:33.903648
3156 13:08:33.906539 ----->DramcWriteLeveling(PI) begin...
3157 13:08:33.910035 ==
3158 13:08:33.910112 Dram Type= 6, Freq= 0, CH_1, rank 0
3159 13:08:33.916316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3160 13:08:33.916395 ==
3161 13:08:33.920168 Write leveling (Byte 0): 25 => 25
3162 13:08:33.923081 Write leveling (Byte 1): 28 => 28
3163 13:08:33.926723 DramcWriteLeveling(PI) end<-----
3164 13:08:33.926799
3165 13:08:33.926858 ==
3166 13:08:33.929877 Dram Type= 6, Freq= 0, CH_1, rank 0
3167 13:08:33.933498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3168 13:08:33.933576 ==
3169 13:08:33.936787 [Gating] SW mode calibration
3170 13:08:33.943091 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3171 13:08:33.949755 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3172 13:08:33.953344 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3173 13:08:33.956215 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3174 13:08:33.963000 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3175 13:08:33.966374 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 13:08:33.969613 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 13:08:33.972939 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 13:08:33.979952 0 15 24 | B1->B0 | 2929 2828 | 0 0 | (0 0) (1 0)
3179 13:08:33.982802 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3180 13:08:33.986093 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3181 13:08:33.992844 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3182 13:08:33.996240 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 13:08:33.999736 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 13:08:34.006004 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 13:08:34.009480 1 0 20 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
3186 13:08:34.012904 1 0 24 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
3187 13:08:34.019151 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 13:08:34.022543 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 13:08:34.026228 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 13:08:34.032585 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 13:08:34.035741 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 13:08:34.039143 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 13:08:34.045643 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 13:08:34.049566 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3195 13:08:34.053052 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 13:08:34.059028 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 13:08:34.062477 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 13:08:34.065660 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 13:08:34.073434 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 13:08:34.076046 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 13:08:34.078939 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 13:08:34.085448 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 13:08:34.088886 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 13:08:34.092294 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 13:08:34.098914 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 13:08:34.102548 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 13:08:34.106105 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 13:08:34.112224 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 13:08:34.115684 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 13:08:34.119235 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3211 13:08:34.122265 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3212 13:08:34.125513 Total UI for P1: 0, mck2ui 16
3213 13:08:34.128849 best dqsien dly found for B0: ( 1, 3, 24)
3214 13:08:34.135782 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 13:08:34.139018 Total UI for P1: 0, mck2ui 16
3216 13:08:34.142703 best dqsien dly found for B1: ( 1, 3, 26)
3217 13:08:34.145619 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3218 13:08:34.148923 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3219 13:08:34.149002
3220 13:08:34.152566 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3221 13:08:34.155703 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3222 13:08:34.159212 [Gating] SW calibration Done
3223 13:08:34.159288 ==
3224 13:08:34.162300 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 13:08:34.165878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 13:08:34.165956 ==
3227 13:08:34.169313 RX Vref Scan: 0
3228 13:08:34.169389
3229 13:08:34.169449 RX Vref 0 -> 0, step: 1
3230 13:08:34.169601
3231 13:08:34.172433 RX Delay -40 -> 252, step: 8
3232 13:08:34.179249 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3233 13:08:34.182451 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3234 13:08:34.185951 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3235 13:08:34.188979 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3236 13:08:34.192034 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3237 13:08:34.199011 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3238 13:08:34.202302 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3239 13:08:34.205860 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3240 13:08:34.209071 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3241 13:08:34.212474 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3242 13:08:34.215680 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3243 13:08:34.222297 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3244 13:08:34.225633 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3245 13:08:34.228865 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3246 13:08:34.232480 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3247 13:08:34.238940 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3248 13:08:34.239020 ==
3249 13:08:34.242293 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 13:08:34.245753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 13:08:34.245830 ==
3252 13:08:34.245891 DQS Delay:
3253 13:08:34.248586 DQS0 = 0, DQS1 = 0
3254 13:08:34.248663 DQM Delay:
3255 13:08:34.251969 DQM0 = 119, DQM1 = 112
3256 13:08:34.252046 DQ Delay:
3257 13:08:34.255792 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3258 13:08:34.259123 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3259 13:08:34.262491 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3260 13:08:34.265611 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3261 13:08:34.265688
3262 13:08:34.265747
3263 13:08:34.265801 ==
3264 13:08:34.268928 Dram Type= 6, Freq= 0, CH_1, rank 0
3265 13:08:34.275678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3266 13:08:34.275785 ==
3267 13:08:34.275848
3268 13:08:34.275903
3269 13:08:34.275956 TX Vref Scan disable
3270 13:08:34.278940 == TX Byte 0 ==
3271 13:08:34.282748 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3272 13:08:34.288992 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3273 13:08:34.289094 == TX Byte 1 ==
3274 13:08:34.292240 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3275 13:08:34.296247 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3276 13:08:34.299315 ==
3277 13:08:34.302568 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 13:08:34.305393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 13:08:34.305470 ==
3280 13:08:34.316895 TX Vref=22, minBit 8, minWin=24, winSum=405
3281 13:08:34.320156 TX Vref=24, minBit 11, minWin=24, winSum=410
3282 13:08:34.323457 TX Vref=26, minBit 3, minWin=25, winSum=416
3283 13:08:34.326901 TX Vref=28, minBit 9, minWin=25, winSum=420
3284 13:08:34.330038 TX Vref=30, minBit 10, minWin=25, winSum=423
3285 13:08:34.336998 TX Vref=32, minBit 12, minWin=25, winSum=424
3286 13:08:34.340122 [TxChooseVref] Worse bit 12, Min win 25, Win sum 424, Final Vref 32
3287 13:08:34.340199
3288 13:08:34.343309 Final TX Range 1 Vref 32
3289 13:08:34.343385
3290 13:08:34.343448 ==
3291 13:08:34.346429 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 13:08:34.350121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 13:08:34.353246 ==
3294 13:08:34.353322
3295 13:08:34.353382
3296 13:08:34.353436 TX Vref Scan disable
3297 13:08:34.356696 == TX Byte 0 ==
3298 13:08:34.360396 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3299 13:08:34.367026 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3300 13:08:34.367103 == TX Byte 1 ==
3301 13:08:34.369998 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3302 13:08:34.376451 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3303 13:08:34.376529
3304 13:08:34.376589 [DATLAT]
3305 13:08:34.376645 Freq=1200, CH1 RK0
3306 13:08:34.376699
3307 13:08:34.380107 DATLAT Default: 0xd
3308 13:08:34.380183 0, 0xFFFF, sum = 0
3309 13:08:34.383632 1, 0xFFFF, sum = 0
3310 13:08:34.386615 2, 0xFFFF, sum = 0
3311 13:08:34.386693 3, 0xFFFF, sum = 0
3312 13:08:34.390127 4, 0xFFFF, sum = 0
3313 13:08:34.390276 5, 0xFFFF, sum = 0
3314 13:08:34.393303 6, 0xFFFF, sum = 0
3315 13:08:34.393407 7, 0xFFFF, sum = 0
3316 13:08:34.396909 8, 0xFFFF, sum = 0
3317 13:08:34.396992 9, 0xFFFF, sum = 0
3318 13:08:34.400055 10, 0xFFFF, sum = 0
3319 13:08:34.400133 11, 0xFFFF, sum = 0
3320 13:08:34.403230 12, 0x0, sum = 1
3321 13:08:34.403309 13, 0x0, sum = 2
3322 13:08:34.406741 14, 0x0, sum = 3
3323 13:08:34.406820 15, 0x0, sum = 4
3324 13:08:34.406881 best_step = 13
3325 13:08:34.409887
3326 13:08:34.409980 ==
3327 13:08:34.413314 Dram Type= 6, Freq= 0, CH_1, rank 0
3328 13:08:34.416722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3329 13:08:34.416823 ==
3330 13:08:34.416910 RX Vref Scan: 1
3331 13:08:34.416972
3332 13:08:34.419878 Set Vref Range= 32 -> 127
3333 13:08:34.419967
3334 13:08:34.423009 RX Vref 32 -> 127, step: 1
3335 13:08:34.423074
3336 13:08:34.426810 RX Delay -13 -> 252, step: 4
3337 13:08:34.426887
3338 13:08:34.429868 Set Vref, RX VrefLevel [Byte0]: 32
3339 13:08:34.433315 [Byte1]: 32
3340 13:08:34.433393
3341 13:08:34.436595 Set Vref, RX VrefLevel [Byte0]: 33
3342 13:08:34.439698 [Byte1]: 33
3343 13:08:34.443716
3344 13:08:34.443784 Set Vref, RX VrefLevel [Byte0]: 34
3345 13:08:34.446440 [Byte1]: 34
3346 13:08:34.451083
3347 13:08:34.451172 Set Vref, RX VrefLevel [Byte0]: 35
3348 13:08:34.454332 [Byte1]: 35
3349 13:08:34.458981
3350 13:08:34.459070 Set Vref, RX VrefLevel [Byte0]: 36
3351 13:08:34.462140 [Byte1]: 36
3352 13:08:34.466747
3353 13:08:34.466839 Set Vref, RX VrefLevel [Byte0]: 37
3354 13:08:34.470141 [Byte1]: 37
3355 13:08:34.474868
3356 13:08:34.474933 Set Vref, RX VrefLevel [Byte0]: 38
3357 13:08:34.477765 [Byte1]: 38
3358 13:08:34.482585
3359 13:08:34.482655 Set Vref, RX VrefLevel [Byte0]: 39
3360 13:08:34.486272 [Byte1]: 39
3361 13:08:34.490691
3362 13:08:34.490790 Set Vref, RX VrefLevel [Byte0]: 40
3363 13:08:34.494062 [Byte1]: 40
3364 13:08:34.498671
3365 13:08:34.498773 Set Vref, RX VrefLevel [Byte0]: 41
3366 13:08:34.501423 [Byte1]: 41
3367 13:08:34.505992
3368 13:08:34.506083 Set Vref, RX VrefLevel [Byte0]: 42
3369 13:08:34.509440 [Byte1]: 42
3370 13:08:34.514081
3371 13:08:34.514182 Set Vref, RX VrefLevel [Byte0]: 43
3372 13:08:34.517377 [Byte1]: 43
3373 13:08:34.521794
3374 13:08:34.521869 Set Vref, RX VrefLevel [Byte0]: 44
3375 13:08:34.525953 [Byte1]: 44
3376 13:08:34.529938
3377 13:08:34.530014 Set Vref, RX VrefLevel [Byte0]: 45
3378 13:08:34.533218 [Byte1]: 45
3379 13:08:34.537787
3380 13:08:34.537863 Set Vref, RX VrefLevel [Byte0]: 46
3381 13:08:34.541608 [Byte1]: 46
3382 13:08:34.546082
3383 13:08:34.546181 Set Vref, RX VrefLevel [Byte0]: 47
3384 13:08:34.548810 [Byte1]: 47
3385 13:08:34.553594
3386 13:08:34.553673 Set Vref, RX VrefLevel [Byte0]: 48
3387 13:08:34.556790 [Byte1]: 48
3388 13:08:34.561300
3389 13:08:34.561376 Set Vref, RX VrefLevel [Byte0]: 49
3390 13:08:34.564770 [Byte1]: 49
3391 13:08:34.568967
3392 13:08:34.569060 Set Vref, RX VrefLevel [Byte0]: 50
3393 13:08:34.572430 [Byte1]: 50
3394 13:08:34.577250
3395 13:08:34.577346 Set Vref, RX VrefLevel [Byte0]: 51
3396 13:08:34.580462 [Byte1]: 51
3397 13:08:34.584977
3398 13:08:34.585069 Set Vref, RX VrefLevel [Byte0]: 52
3399 13:08:34.588231 [Byte1]: 52
3400 13:08:34.593015
3401 13:08:34.593119 Set Vref, RX VrefLevel [Byte0]: 53
3402 13:08:34.596194 [Byte1]: 53
3403 13:08:34.601306
3404 13:08:34.601423 Set Vref, RX VrefLevel [Byte0]: 54
3405 13:08:34.604187 [Byte1]: 54
3406 13:08:34.608692
3407 13:08:34.608783 Set Vref, RX VrefLevel [Byte0]: 55
3408 13:08:34.611888 [Byte1]: 55
3409 13:08:34.616608
3410 13:08:34.616697 Set Vref, RX VrefLevel [Byte0]: 56
3411 13:08:34.620646 [Byte1]: 56
3412 13:08:34.624520
3413 13:08:34.624614 Set Vref, RX VrefLevel [Byte0]: 57
3414 13:08:34.627540 [Byte1]: 57
3415 13:08:34.632601
3416 13:08:34.632695 Set Vref, RX VrefLevel [Byte0]: 58
3417 13:08:34.635671 [Byte1]: 58
3418 13:08:34.640483
3419 13:08:34.640576 Set Vref, RX VrefLevel [Byte0]: 59
3420 13:08:34.643632 [Byte1]: 59
3421 13:08:34.648339
3422 13:08:34.648421 Set Vref, RX VrefLevel [Byte0]: 60
3423 13:08:34.651441 [Byte1]: 60
3424 13:08:34.656236
3425 13:08:34.656308 Set Vref, RX VrefLevel [Byte0]: 61
3426 13:08:34.659592 [Byte1]: 61
3427 13:08:34.663821
3428 13:08:34.663912 Set Vref, RX VrefLevel [Byte0]: 62
3429 13:08:34.667239 [Byte1]: 62
3430 13:08:34.672104
3431 13:08:34.672176 Set Vref, RX VrefLevel [Byte0]: 63
3432 13:08:34.675270 [Byte1]: 63
3433 13:08:34.679797
3434 13:08:34.679889 Set Vref, RX VrefLevel [Byte0]: 64
3435 13:08:34.683197 [Byte1]: 64
3436 13:08:34.687476
3437 13:08:34.687544 Set Vref, RX VrefLevel [Byte0]: 65
3438 13:08:34.690852 [Byte1]: 65
3439 13:08:34.695607
3440 13:08:34.695699 Set Vref, RX VrefLevel [Byte0]: 66
3441 13:08:34.699524 [Byte1]: 66
3442 13:08:34.703171
3443 13:08:34.703238 Set Vref, RX VrefLevel [Byte0]: 67
3444 13:08:34.709745 [Byte1]: 67
3445 13:08:34.709837
3446 13:08:34.713042 Final RX Vref Byte 0 = 49 to rank0
3447 13:08:34.716542 Final RX Vref Byte 1 = 53 to rank0
3448 13:08:34.719624 Final RX Vref Byte 0 = 49 to rank1
3449 13:08:34.722933 Final RX Vref Byte 1 = 53 to rank1==
3450 13:08:34.726766 Dram Type= 6, Freq= 0, CH_1, rank 0
3451 13:08:34.729995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3452 13:08:34.730061 ==
3453 13:08:34.730219 DQS Delay:
3454 13:08:34.732933 DQS0 = 0, DQS1 = 0
3455 13:08:34.732997 DQM Delay:
3456 13:08:34.736614 DQM0 = 119, DQM1 = 112
3457 13:08:34.736678 DQ Delay:
3458 13:08:34.739544 DQ0 =120, DQ1 =114, DQ2 =112, DQ3 =116
3459 13:08:34.742870 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =116
3460 13:08:34.746362 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3461 13:08:34.749673 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =118
3462 13:08:34.752935
3463 13:08:34.753010
3464 13:08:34.759956 [DQSOSCAuto] RK0, (LSB)MR18= 0x81b, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 406 ps
3465 13:08:34.763107 CH1 RK0: MR19=404, MR18=81B
3466 13:08:34.769738 CH1_RK0: MR19=0x404, MR18=0x81B, DQSOSC=399, MR23=63, INC=41, DEC=27
3467 13:08:34.769814
3468 13:08:34.772874 ----->DramcWriteLeveling(PI) begin...
3469 13:08:34.772982 ==
3470 13:08:34.775892 Dram Type= 6, Freq= 0, CH_1, rank 1
3471 13:08:34.779612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3472 13:08:34.779690 ==
3473 13:08:34.782652 Write leveling (Byte 0): 25 => 25
3474 13:08:34.786176 Write leveling (Byte 1): 27 => 27
3475 13:08:34.789521 DramcWriteLeveling(PI) end<-----
3476 13:08:34.789597
3477 13:08:34.789656 ==
3478 13:08:34.792820 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 13:08:34.796533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 13:08:34.796610 ==
3481 13:08:34.799386 [Gating] SW mode calibration
3482 13:08:34.806068 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3483 13:08:34.812559 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3484 13:08:34.816358 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 13:08:34.819775 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 13:08:34.826000 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 13:08:34.829569 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 13:08:34.832745 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 13:08:34.839179 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3490 13:08:34.842863 0 15 24 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 0)
3491 13:08:34.846139 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
3492 13:08:34.852565 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 13:08:34.855748 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 13:08:34.859140 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 13:08:34.865901 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 13:08:34.869165 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 13:08:34.872506 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3498 13:08:34.879478 1 0 24 | B1->B0 | 3f3f 2d2d | 0 0 | (0 0) (1 1)
3499 13:08:34.882804 1 0 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
3500 13:08:34.886061 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 13:08:34.889056 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 13:08:34.896000 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 13:08:34.899387 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 13:08:34.902289 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 13:08:34.908991 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 13:08:34.912357 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3507 13:08:34.915772 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3508 13:08:34.922238 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 13:08:34.925493 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 13:08:34.929028 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 13:08:34.935558 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 13:08:34.939165 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 13:08:34.942199 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 13:08:34.948893 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 13:08:34.952416 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 13:08:34.955560 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 13:08:34.962006 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 13:08:34.965405 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 13:08:34.968734 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 13:08:34.975581 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 13:08:34.978688 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 13:08:34.982016 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3523 13:08:34.988627 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3524 13:08:34.992237 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 13:08:34.995588 Total UI for P1: 0, mck2ui 16
3526 13:08:34.998565 best dqsien dly found for B0: ( 1, 3, 26)
3527 13:08:35.002060 Total UI for P1: 0, mck2ui 16
3528 13:08:35.005453 best dqsien dly found for B1: ( 1, 3, 26)
3529 13:08:35.008696 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3530 13:08:35.012216 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3531 13:08:35.012293
3532 13:08:35.015400 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3533 13:08:35.018864 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3534 13:08:35.022419 [Gating] SW calibration Done
3535 13:08:35.022496 ==
3536 13:08:35.025746 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 13:08:35.028631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 13:08:35.028709 ==
3539 13:08:35.032307 RX Vref Scan: 0
3540 13:08:35.032384
3541 13:08:35.035415 RX Vref 0 -> 0, step: 1
3542 13:08:35.035492
3543 13:08:35.035551 RX Delay -40 -> 252, step: 8
3544 13:08:35.042393 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3545 13:08:35.045655 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3546 13:08:35.048673 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3547 13:08:35.052002 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3548 13:08:35.055789 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3549 13:08:35.061923 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3550 13:08:35.065740 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3551 13:08:35.069096 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3552 13:08:35.071989 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3553 13:08:35.075341 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3554 13:08:35.081918 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3555 13:08:35.085060 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3556 13:08:35.088374 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3557 13:08:35.092266 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3558 13:08:35.094982 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3559 13:08:35.101713 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3560 13:08:35.101811 ==
3561 13:08:35.105071 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 13:08:35.108755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 13:08:35.108846 ==
3564 13:08:35.108934 DQS Delay:
3565 13:08:35.111781 DQS0 = 0, DQS1 = 0
3566 13:08:35.111874 DQM Delay:
3567 13:08:35.115310 DQM0 = 118, DQM1 = 112
3568 13:08:35.115404 DQ Delay:
3569 13:08:35.118233 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3570 13:08:35.121619 DQ4 =119, DQ5 =131, DQ6 =123, DQ7 =115
3571 13:08:35.125358 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3572 13:08:35.128491 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3573 13:08:35.128593
3574 13:08:35.131913
3575 13:08:35.132005 ==
3576 13:08:35.134805 Dram Type= 6, Freq= 0, CH_1, rank 1
3577 13:08:35.138382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3578 13:08:35.138475 ==
3579 13:08:35.138562
3580 13:08:35.138643
3581 13:08:35.141687 TX Vref Scan disable
3582 13:08:35.141765 == TX Byte 0 ==
3583 13:08:35.145638 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3584 13:08:35.151742 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3585 13:08:35.151839 == TX Byte 1 ==
3586 13:08:35.155075 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3587 13:08:35.161808 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3588 13:08:35.161911 ==
3589 13:08:35.165600 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 13:08:35.168319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 13:08:35.168406 ==
3592 13:08:35.180400 TX Vref=22, minBit 1, minWin=25, winSum=416
3593 13:08:35.183616 TX Vref=24, minBit 8, minWin=25, winSum=422
3594 13:08:35.186975 TX Vref=26, minBit 1, minWin=26, winSum=424
3595 13:08:35.190470 TX Vref=28, minBit 3, minWin=26, winSum=427
3596 13:08:35.194201 TX Vref=30, minBit 8, minWin=26, winSum=430
3597 13:08:35.200270 TX Vref=32, minBit 10, minWin=25, winSum=427
3598 13:08:35.203468 [TxChooseVref] Worse bit 8, Min win 26, Win sum 430, Final Vref 30
3599 13:08:35.203596
3600 13:08:35.206804 Final TX Range 1 Vref 30
3601 13:08:35.206881
3602 13:08:35.206941 ==
3603 13:08:35.210385 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 13:08:35.213701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 13:08:35.213779 ==
3606 13:08:35.216909
3607 13:08:35.216985
3608 13:08:35.217044 TX Vref Scan disable
3609 13:08:35.220461 == TX Byte 0 ==
3610 13:08:35.223707 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3611 13:08:35.230232 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3612 13:08:35.230310 == TX Byte 1 ==
3613 13:08:35.233302 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3614 13:08:35.239849 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3615 13:08:35.239926
3616 13:08:35.239986 [DATLAT]
3617 13:08:35.240041 Freq=1200, CH1 RK1
3618 13:08:35.240094
3619 13:08:35.243197 DATLAT Default: 0xd
3620 13:08:35.243276 0, 0xFFFF, sum = 0
3621 13:08:35.246686 1, 0xFFFF, sum = 0
3622 13:08:35.250263 2, 0xFFFF, sum = 0
3623 13:08:35.250343 3, 0xFFFF, sum = 0
3624 13:08:35.253341 4, 0xFFFF, sum = 0
3625 13:08:35.253421 5, 0xFFFF, sum = 0
3626 13:08:35.256359 6, 0xFFFF, sum = 0
3627 13:08:35.256438 7, 0xFFFF, sum = 0
3628 13:08:35.260354 8, 0xFFFF, sum = 0
3629 13:08:35.260434 9, 0xFFFF, sum = 0
3630 13:08:35.263534 10, 0xFFFF, sum = 0
3631 13:08:35.263613 11, 0xFFFF, sum = 0
3632 13:08:35.266463 12, 0x0, sum = 1
3633 13:08:35.266543 13, 0x0, sum = 2
3634 13:08:35.269867 14, 0x0, sum = 3
3635 13:08:35.269947 15, 0x0, sum = 4
3636 13:08:35.273197 best_step = 13
3637 13:08:35.273299
3638 13:08:35.273386 ==
3639 13:08:35.276579 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 13:08:35.280273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 13:08:35.280353 ==
3642 13:08:35.280414 RX Vref Scan: 0
3643 13:08:35.280471
3644 13:08:35.283235 RX Vref 0 -> 0, step: 1
3645 13:08:35.283313
3646 13:08:35.286507 RX Delay -13 -> 252, step: 4
3647 13:08:35.289837 iDelay=191, Bit 0, Center 124 (67 ~ 182) 116
3648 13:08:35.296608 iDelay=191, Bit 1, Center 114 (55 ~ 174) 120
3649 13:08:35.300004 iDelay=191, Bit 2, Center 108 (51 ~ 166) 116
3650 13:08:35.303099 iDelay=191, Bit 3, Center 118 (59 ~ 178) 120
3651 13:08:35.306369 iDelay=191, Bit 4, Center 122 (63 ~ 182) 120
3652 13:08:35.309868 iDelay=191, Bit 5, Center 128 (67 ~ 190) 124
3653 13:08:35.316649 iDelay=191, Bit 6, Center 126 (67 ~ 186) 120
3654 13:08:35.320014 iDelay=191, Bit 7, Center 116 (55 ~ 178) 124
3655 13:08:35.323149 iDelay=191, Bit 8, Center 100 (39 ~ 162) 124
3656 13:08:35.326352 iDelay=191, Bit 9, Center 102 (39 ~ 166) 128
3657 13:08:35.329762 iDelay=191, Bit 10, Center 112 (47 ~ 178) 132
3658 13:08:35.336371 iDelay=191, Bit 11, Center 106 (43 ~ 170) 128
3659 13:08:35.339569 iDelay=191, Bit 12, Center 122 (59 ~ 186) 128
3660 13:08:35.342888 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3661 13:08:35.346617 iDelay=191, Bit 14, Center 122 (59 ~ 186) 128
3662 13:08:35.349578 iDelay=191, Bit 15, Center 122 (59 ~ 186) 128
3663 13:08:35.353268 ==
3664 13:08:35.356499 Dram Type= 6, Freq= 0, CH_1, rank 1
3665 13:08:35.359529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3666 13:08:35.359616 ==
3667 13:08:35.359678 DQS Delay:
3668 13:08:35.362815 DQS0 = 0, DQS1 = 0
3669 13:08:35.362891 DQM Delay:
3670 13:08:35.366223 DQM0 = 119, DQM1 = 113
3671 13:08:35.366300 DQ Delay:
3672 13:08:35.369673 DQ0 =124, DQ1 =114, DQ2 =108, DQ3 =118
3673 13:08:35.373035 DQ4 =122, DQ5 =128, DQ6 =126, DQ7 =116
3674 13:08:35.376236 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
3675 13:08:35.379588 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =122
3676 13:08:35.379664
3677 13:08:35.379724
3678 13:08:35.389929 [DQSOSCAuto] RK1, (LSB)MR18= 0xff3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 404 ps
3679 13:08:35.390006 CH1 RK1: MR19=403, MR18=FF3
3680 13:08:35.396466 CH1_RK1: MR19=0x403, MR18=0xFF3, DQSOSC=404, MR23=63, INC=40, DEC=26
3681 13:08:35.400068 [RxdqsGatingPostProcess] freq 1200
3682 13:08:35.406498 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3683 13:08:35.409833 best DQS0 dly(2T, 0.5T) = (0, 11)
3684 13:08:35.412874 best DQS1 dly(2T, 0.5T) = (0, 11)
3685 13:08:35.416775 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3686 13:08:35.419815 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3687 13:08:35.422774 best DQS0 dly(2T, 0.5T) = (0, 11)
3688 13:08:35.422850 best DQS1 dly(2T, 0.5T) = (0, 11)
3689 13:08:35.426307 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3690 13:08:35.429611 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3691 13:08:35.433030 Pre-setting of DQS Precalculation
3692 13:08:35.439625 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3693 13:08:35.446215 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3694 13:08:35.452835 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3695 13:08:35.452913
3696 13:08:35.452972
3697 13:08:35.456062 [Calibration Summary] 2400 Mbps
3698 13:08:35.459948 CH 0, Rank 0
3699 13:08:35.460025 SW Impedance : PASS
3700 13:08:35.462863 DUTY Scan : NO K
3701 13:08:35.462940 ZQ Calibration : PASS
3702 13:08:35.466379 Jitter Meter : NO K
3703 13:08:35.469457 CBT Training : PASS
3704 13:08:35.469534 Write leveling : PASS
3705 13:08:35.473119 RX DQS gating : PASS
3706 13:08:35.476251 RX DQ/DQS(RDDQC) : PASS
3707 13:08:35.476328 TX DQ/DQS : PASS
3708 13:08:35.479757 RX DATLAT : PASS
3709 13:08:35.483104 RX DQ/DQS(Engine): PASS
3710 13:08:35.483180 TX OE : NO K
3711 13:08:35.486370 All Pass.
3712 13:08:35.486448
3713 13:08:35.486508 CH 0, Rank 1
3714 13:08:35.489903 SW Impedance : PASS
3715 13:08:35.489979 DUTY Scan : NO K
3716 13:08:35.493122 ZQ Calibration : PASS
3717 13:08:35.496365 Jitter Meter : NO K
3718 13:08:35.496442 CBT Training : PASS
3719 13:08:35.499836 Write leveling : PASS
3720 13:08:35.499913 RX DQS gating : PASS
3721 13:08:35.503039 RX DQ/DQS(RDDQC) : PASS
3722 13:08:35.506311 TX DQ/DQS : PASS
3723 13:08:35.506390 RX DATLAT : PASS
3724 13:08:35.509713 RX DQ/DQS(Engine): PASS
3725 13:08:35.513423 TX OE : NO K
3726 13:08:35.513501 All Pass.
3727 13:08:35.513560
3728 13:08:35.513615 CH 1, Rank 0
3729 13:08:35.516230 SW Impedance : PASS
3730 13:08:35.519969 DUTY Scan : NO K
3731 13:08:35.520046 ZQ Calibration : PASS
3732 13:08:35.523219 Jitter Meter : NO K
3733 13:08:35.526477 CBT Training : PASS
3734 13:08:35.526554 Write leveling : PASS
3735 13:08:35.529802 RX DQS gating : PASS
3736 13:08:35.533133 RX DQ/DQS(RDDQC) : PASS
3737 13:08:35.533239 TX DQ/DQS : PASS
3738 13:08:35.536300 RX DATLAT : PASS
3739 13:08:35.539385 RX DQ/DQS(Engine): PASS
3740 13:08:35.539461 TX OE : NO K
3741 13:08:35.539522 All Pass.
3742 13:08:35.543198
3743 13:08:35.543274 CH 1, Rank 1
3744 13:08:35.546421 SW Impedance : PASS
3745 13:08:35.546498 DUTY Scan : NO K
3746 13:08:35.550019 ZQ Calibration : PASS
3747 13:08:35.550095 Jitter Meter : NO K
3748 13:08:35.552957 CBT Training : PASS
3749 13:08:35.556650 Write leveling : PASS
3750 13:08:35.556726 RX DQS gating : PASS
3751 13:08:35.559309 RX DQ/DQS(RDDQC) : PASS
3752 13:08:35.562932 TX DQ/DQS : PASS
3753 13:08:35.563034 RX DATLAT : PASS
3754 13:08:35.566035 RX DQ/DQS(Engine): PASS
3755 13:08:35.569252 TX OE : NO K
3756 13:08:35.569328 All Pass.
3757 13:08:35.569388
3758 13:08:35.572528 DramC Write-DBI off
3759 13:08:35.572605 PER_BANK_REFRESH: Hybrid Mode
3760 13:08:35.576079 TX_TRACKING: ON
3761 13:08:35.582781 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3762 13:08:35.589272 [FAST_K] Save calibration result to emmc
3763 13:08:35.593008 dramc_set_vcore_voltage set vcore to 650000
3764 13:08:35.593085 Read voltage for 600, 5
3765 13:08:35.595814 Vio18 = 0
3766 13:08:35.595879 Vcore = 650000
3767 13:08:35.595934 Vdram = 0
3768 13:08:35.599109 Vddq = 0
3769 13:08:35.599185 Vmddr = 0
3770 13:08:35.602624 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3771 13:08:35.609047 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3772 13:08:35.613213 MEM_TYPE=3, freq_sel=19
3773 13:08:35.615909 sv_algorithm_assistance_LP4_1600
3774 13:08:35.619508 ============ PULL DRAM RESETB DOWN ============
3775 13:08:35.622539 ========== PULL DRAM RESETB DOWN end =========
3776 13:08:35.629435 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3777 13:08:35.632373 ===================================
3778 13:08:35.632452 LPDDR4 DRAM CONFIGURATION
3779 13:08:35.635712 ===================================
3780 13:08:35.639548 EX_ROW_EN[0] = 0x0
3781 13:08:35.639625 EX_ROW_EN[1] = 0x0
3782 13:08:35.642321 LP4Y_EN = 0x0
3783 13:08:35.642398 WORK_FSP = 0x0
3784 13:08:35.645595 WL = 0x2
3785 13:08:35.645695 RL = 0x2
3786 13:08:35.649013 BL = 0x2
3787 13:08:35.652306 RPST = 0x0
3788 13:08:35.652383 RD_PRE = 0x0
3789 13:08:35.655605 WR_PRE = 0x1
3790 13:08:35.655681 WR_PST = 0x0
3791 13:08:35.658987 DBI_WR = 0x0
3792 13:08:35.659064 DBI_RD = 0x0
3793 13:08:35.662356 OTF = 0x1
3794 13:08:35.665793 ===================================
3795 13:08:35.669036 ===================================
3796 13:08:35.669112 ANA top config
3797 13:08:35.672446 ===================================
3798 13:08:35.675951 DLL_ASYNC_EN = 0
3799 13:08:35.679272 ALL_SLAVE_EN = 1
3800 13:08:35.679350 NEW_RANK_MODE = 1
3801 13:08:35.682575 DLL_IDLE_MODE = 1
3802 13:08:35.686017 LP45_APHY_COMB_EN = 1
3803 13:08:35.689067 TX_ODT_DIS = 1
3804 13:08:35.689181 NEW_8X_MODE = 1
3805 13:08:35.692395 ===================================
3806 13:08:35.695548 ===================================
3807 13:08:35.699293 data_rate = 1200
3808 13:08:35.702537 CKR = 1
3809 13:08:35.705949 DQ_P2S_RATIO = 8
3810 13:08:35.709291 ===================================
3811 13:08:35.712208 CA_P2S_RATIO = 8
3812 13:08:35.715609 DQ_CA_OPEN = 0
3813 13:08:35.715687 DQ_SEMI_OPEN = 0
3814 13:08:35.719143 CA_SEMI_OPEN = 0
3815 13:08:35.722693 CA_FULL_RATE = 0
3816 13:08:35.725784 DQ_CKDIV4_EN = 1
3817 13:08:35.728826 CA_CKDIV4_EN = 1
3818 13:08:35.732372 CA_PREDIV_EN = 0
3819 13:08:35.732449 PH8_DLY = 0
3820 13:08:35.735945 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3821 13:08:35.738788 DQ_AAMCK_DIV = 4
3822 13:08:35.742353 CA_AAMCK_DIV = 4
3823 13:08:35.745489 CA_ADMCK_DIV = 4
3824 13:08:35.748826 DQ_TRACK_CA_EN = 0
3825 13:08:35.748927 CA_PICK = 600
3826 13:08:35.752115 CA_MCKIO = 600
3827 13:08:35.755411 MCKIO_SEMI = 0
3828 13:08:35.758820 PLL_FREQ = 2288
3829 13:08:35.762338 DQ_UI_PI_RATIO = 32
3830 13:08:35.765600 CA_UI_PI_RATIO = 0
3831 13:08:35.768906 ===================================
3832 13:08:35.772164 ===================================
3833 13:08:35.775385 memory_type:LPDDR4
3834 13:08:35.775462 GP_NUM : 10
3835 13:08:35.778531 SRAM_EN : 1
3836 13:08:35.778608 MD32_EN : 0
3837 13:08:35.781860 ===================================
3838 13:08:35.785533 [ANA_INIT] >>>>>>>>>>>>>>
3839 13:08:35.788793 <<<<<< [CONFIGURE PHASE]: ANA_TX
3840 13:08:35.791746 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3841 13:08:35.795443 ===================================
3842 13:08:35.798853 data_rate = 1200,PCW = 0X5800
3843 13:08:35.802006 ===================================
3844 13:08:35.805289 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3845 13:08:35.808414 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3846 13:08:35.815382 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3847 13:08:35.819009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3848 13:08:35.821834 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3849 13:08:35.828742 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3850 13:08:35.828820 [ANA_INIT] flow start
3851 13:08:35.831647 [ANA_INIT] PLL >>>>>>>>
3852 13:08:35.835244 [ANA_INIT] PLL <<<<<<<<
3853 13:08:35.835320 [ANA_INIT] MIDPI >>>>>>>>
3854 13:08:35.838803 [ANA_INIT] MIDPI <<<<<<<<
3855 13:08:35.841814 [ANA_INIT] DLL >>>>>>>>
3856 13:08:35.841891 [ANA_INIT] flow end
3857 13:08:35.845238 ============ LP4 DIFF to SE enter ============
3858 13:08:35.851625 ============ LP4 DIFF to SE exit ============
3859 13:08:35.851703 [ANA_INIT] <<<<<<<<<<<<<
3860 13:08:35.854942 [Flow] Enable top DCM control >>>>>
3861 13:08:35.858669 [Flow] Enable top DCM control <<<<<
3862 13:08:35.861787 Enable DLL master slave shuffle
3863 13:08:35.868476 ==============================================================
3864 13:08:35.868553 Gating Mode config
3865 13:08:35.875099 ==============================================================
3866 13:08:35.878608 Config description:
3867 13:08:35.888533 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3868 13:08:35.895170 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3869 13:08:35.898488 SELPH_MODE 0: By rank 1: By Phase
3870 13:08:35.904997 ==============================================================
3871 13:08:35.908473 GAT_TRACK_EN = 1
3872 13:08:35.908551 RX_GATING_MODE = 2
3873 13:08:35.911784 RX_GATING_TRACK_MODE = 2
3874 13:08:35.914859 SELPH_MODE = 1
3875 13:08:35.918475 PICG_EARLY_EN = 1
3876 13:08:35.921486 VALID_LAT_VALUE = 1
3877 13:08:35.928429 ==============================================================
3878 13:08:35.931551 Enter into Gating configuration >>>>
3879 13:08:35.934856 Exit from Gating configuration <<<<
3880 13:08:35.938164 Enter into DVFS_PRE_config >>>>>
3881 13:08:35.948299 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3882 13:08:35.951535 Exit from DVFS_PRE_config <<<<<
3883 13:08:35.955013 Enter into PICG configuration >>>>
3884 13:08:35.958968 Exit from PICG configuration <<<<
3885 13:08:35.961555 [RX_INPUT] configuration >>>>>
3886 13:08:35.961632 [RX_INPUT] configuration <<<<<
3887 13:08:35.968338 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3888 13:08:35.975012 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3889 13:08:35.982011 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3890 13:08:35.985297 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3891 13:08:35.991413 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3892 13:08:35.998378 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3893 13:08:36.001785 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3894 13:08:36.004656 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3895 13:08:36.011517 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3896 13:08:36.014998 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3897 13:08:36.018431 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3898 13:08:36.024896 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3899 13:08:36.028751 ===================================
3900 13:08:36.028820 LPDDR4 DRAM CONFIGURATION
3901 13:08:36.031634 ===================================
3902 13:08:36.034942 EX_ROW_EN[0] = 0x0
3903 13:08:36.035019 EX_ROW_EN[1] = 0x0
3904 13:08:36.038325 LP4Y_EN = 0x0
3905 13:08:36.038402 WORK_FSP = 0x0
3906 13:08:36.041551 WL = 0x2
3907 13:08:36.044619 RL = 0x2
3908 13:08:36.044696 BL = 0x2
3909 13:08:36.048124 RPST = 0x0
3910 13:08:36.048202 RD_PRE = 0x0
3911 13:08:36.051653 WR_PRE = 0x1
3912 13:08:36.051731 WR_PST = 0x0
3913 13:08:36.054789 DBI_WR = 0x0
3914 13:08:36.054867 DBI_RD = 0x0
3915 13:08:36.058048 OTF = 0x1
3916 13:08:36.061719 ===================================
3917 13:08:36.065051 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3918 13:08:36.068108 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3919 13:08:36.071735 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3920 13:08:36.074732 ===================================
3921 13:08:36.078515 LPDDR4 DRAM CONFIGURATION
3922 13:08:36.081733 ===================================
3923 13:08:36.084894 EX_ROW_EN[0] = 0x10
3924 13:08:36.084970 EX_ROW_EN[1] = 0x0
3925 13:08:36.088891 LP4Y_EN = 0x0
3926 13:08:36.088967 WORK_FSP = 0x0
3927 13:08:36.092108 WL = 0x2
3928 13:08:36.092184 RL = 0x2
3929 13:08:36.095128 BL = 0x2
3930 13:08:36.095204 RPST = 0x0
3931 13:08:36.098402 RD_PRE = 0x0
3932 13:08:36.098478 WR_PRE = 0x1
3933 13:08:36.101556 WR_PST = 0x0
3934 13:08:36.101632 DBI_WR = 0x0
3935 13:08:36.105029 DBI_RD = 0x0
3936 13:08:36.108194 OTF = 0x1
3937 13:08:36.111343 ===================================
3938 13:08:36.114793 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3939 13:08:36.120193 nWR fixed to 30
3940 13:08:36.123628 [ModeRegInit_LP4] CH0 RK0
3941 13:08:36.123704 [ModeRegInit_LP4] CH0 RK1
3942 13:08:36.126420 [ModeRegInit_LP4] CH1 RK0
3943 13:08:36.130023 [ModeRegInit_LP4] CH1 RK1
3944 13:08:36.130100 match AC timing 17
3945 13:08:36.136836 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3946 13:08:36.139528 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3947 13:08:36.142877 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3948 13:08:36.149601 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3949 13:08:36.153247 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3950 13:08:36.153329 ==
3951 13:08:36.156362 Dram Type= 6, Freq= 0, CH_0, rank 0
3952 13:08:36.159749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3953 13:08:36.159826 ==
3954 13:08:36.166336 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3955 13:08:36.173227 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3956 13:08:36.176575 [CA 0] Center 36 (5~67) winsize 63
3957 13:08:36.179681 [CA 1] Center 36 (6~67) winsize 62
3958 13:08:36.183039 [CA 2] Center 34 (4~65) winsize 62
3959 13:08:36.186311 [CA 3] Center 34 (3~65) winsize 63
3960 13:08:36.189667 [CA 4] Center 33 (3~64) winsize 62
3961 13:08:36.192912 [CA 5] Center 33 (2~64) winsize 63
3962 13:08:36.192989
3963 13:08:36.196416 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3964 13:08:36.196510
3965 13:08:36.199488 [CATrainingPosCal] consider 1 rank data
3966 13:08:36.202936 u2DelayCellTimex100 = 270/100 ps
3967 13:08:36.206155 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3968 13:08:36.209443 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3969 13:08:36.213344 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3970 13:08:36.216222 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3971 13:08:36.219512 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3972 13:08:36.223210 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3973 13:08:36.223277
3974 13:08:36.229783 CA PerBit enable=1, Macro0, CA PI delay=33
3975 13:08:36.229861
3976 13:08:36.233012 [CBTSetCACLKResult] CA Dly = 33
3977 13:08:36.233089 CS Dly: 5 (0~36)
3978 13:08:36.233189 ==
3979 13:08:36.236254 Dram Type= 6, Freq= 0, CH_0, rank 1
3980 13:08:36.239801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 13:08:36.239878 ==
3982 13:08:36.246158 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3983 13:08:36.253123 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3984 13:08:36.256377 [CA 0] Center 36 (6~67) winsize 62
3985 13:08:36.259925 [CA 1] Center 36 (6~67) winsize 62
3986 13:08:36.263132 [CA 2] Center 35 (5~65) winsize 61
3987 13:08:36.266461 [CA 3] Center 34 (4~65) winsize 62
3988 13:08:36.269739 [CA 4] Center 34 (3~65) winsize 63
3989 13:08:36.273403 [CA 5] Center 33 (3~64) winsize 62
3990 13:08:36.273480
3991 13:08:36.276329 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3992 13:08:36.276405
3993 13:08:36.279976 [CATrainingPosCal] consider 2 rank data
3994 13:08:36.282987 u2DelayCellTimex100 = 270/100 ps
3995 13:08:36.286242 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3996 13:08:36.289886 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3997 13:08:36.292977 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3998 13:08:36.296305 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3999 13:08:36.299584 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4000 13:08:36.306508 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4001 13:08:36.306585
4002 13:08:36.309580 CA PerBit enable=1, Macro0, CA PI delay=33
4003 13:08:36.309658
4004 13:08:36.312988 [CBTSetCACLKResult] CA Dly = 33
4005 13:08:36.313065 CS Dly: 5 (0~37)
4006 13:08:36.313130
4007 13:08:36.316569 ----->DramcWriteLeveling(PI) begin...
4008 13:08:36.316647 ==
4009 13:08:36.319674 Dram Type= 6, Freq= 0, CH_0, rank 0
4010 13:08:36.322922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4011 13:08:36.326229 ==
4012 13:08:36.326306 Write leveling (Byte 0): 32 => 32
4013 13:08:36.329680 Write leveling (Byte 1): 32 => 32
4014 13:08:36.333088 DramcWriteLeveling(PI) end<-----
4015 13:08:36.333172
4016 13:08:36.333233 ==
4017 13:08:36.336544 Dram Type= 6, Freq= 0, CH_0, rank 0
4018 13:08:36.342840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 13:08:36.342917 ==
4020 13:08:36.342977 [Gating] SW mode calibration
4021 13:08:36.353043 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4022 13:08:36.356274 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4023 13:08:36.359365 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4024 13:08:36.365958 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4025 13:08:36.369367 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4026 13:08:36.372728 0 9 12 | B1->B0 | 3333 2e2e | 1 0 | (0 0) (0 0)
4027 13:08:36.379435 0 9 16 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
4028 13:08:36.382850 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 13:08:36.386368 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 13:08:36.392933 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 13:08:36.396472 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 13:08:36.399578 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 13:08:36.406291 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4034 13:08:36.409354 0 10 12 | B1->B0 | 2f2f 4545 | 0 0 | (0 0) (0 0)
4035 13:08:36.412603 0 10 16 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
4036 13:08:36.419138 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 13:08:36.423082 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 13:08:36.426005 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 13:08:36.432688 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 13:08:36.435919 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 13:08:36.439202 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 13:08:36.446361 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4043 13:08:36.449231 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 13:08:36.452520 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 13:08:36.458960 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 13:08:36.462456 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 13:08:36.465571 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 13:08:36.472202 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 13:08:36.476179 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 13:08:36.479379 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 13:08:36.485568 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 13:08:36.488867 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 13:08:36.492709 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 13:08:36.498838 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 13:08:36.502185 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 13:08:36.505586 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 13:08:36.508816 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 13:08:36.515485 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4059 13:08:36.518941 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 13:08:36.521986 Total UI for P1: 0, mck2ui 16
4061 13:08:36.525510 best dqsien dly found for B0: ( 0, 13, 12)
4062 13:08:36.529162 Total UI for P1: 0, mck2ui 16
4063 13:08:36.532532 best dqsien dly found for B1: ( 0, 13, 12)
4064 13:08:36.535708 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4065 13:08:36.538920 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4066 13:08:36.538997
4067 13:08:36.542234 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4068 13:08:36.548763 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4069 13:08:36.548840 [Gating] SW calibration Done
4070 13:08:36.548900 ==
4071 13:08:36.551955 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 13:08:36.558632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 13:08:36.558710 ==
4074 13:08:36.558771 RX Vref Scan: 0
4075 13:08:36.558826
4076 13:08:36.561902 RX Vref 0 -> 0, step: 1
4077 13:08:36.561979
4078 13:08:36.565853 RX Delay -230 -> 252, step: 16
4079 13:08:36.568842 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4080 13:08:36.572131 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4081 13:08:36.575396 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4082 13:08:36.581859 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4083 13:08:36.585157 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4084 13:08:36.588658 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4085 13:08:36.591999 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4086 13:08:36.595660 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4087 13:08:36.602229 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4088 13:08:36.605276 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4089 13:08:36.608922 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4090 13:08:36.612287 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4091 13:08:36.618660 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4092 13:08:36.621865 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4093 13:08:36.625228 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4094 13:08:36.628741 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4095 13:08:36.631601 ==
4096 13:08:36.631677 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 13:08:36.638463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 13:08:36.638541 ==
4099 13:08:36.638601 DQS Delay:
4100 13:08:36.642074 DQS0 = 0, DQS1 = 0
4101 13:08:36.642151 DQM Delay:
4102 13:08:36.642211 DQM0 = 51, DQM1 = 40
4103 13:08:36.645052 DQ Delay:
4104 13:08:36.648416 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4105 13:08:36.651759 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4106 13:08:36.655332 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4107 13:08:36.658730 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4108 13:08:36.658807
4109 13:08:36.658867
4110 13:08:36.658922 ==
4111 13:08:36.661997 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 13:08:36.665340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 13:08:36.665417 ==
4114 13:08:36.665476
4115 13:08:36.665531
4116 13:08:36.668350 TX Vref Scan disable
4117 13:08:36.671718 == TX Byte 0 ==
4118 13:08:36.675235 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4119 13:08:36.678962 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4120 13:08:36.681857 == TX Byte 1 ==
4121 13:08:36.685872 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4122 13:08:36.688961 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4123 13:08:36.689038 ==
4124 13:08:36.691752 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 13:08:36.695301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 13:08:36.695378 ==
4127 13:08:36.695438
4128 13:08:36.698489
4129 13:08:36.698565 TX Vref Scan disable
4130 13:08:36.701963 == TX Byte 0 ==
4131 13:08:36.705645 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4132 13:08:36.711903 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4133 13:08:36.711980 == TX Byte 1 ==
4134 13:08:36.715272 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4135 13:08:36.719103 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4136 13:08:36.721874
4137 13:08:36.721950 [DATLAT]
4138 13:08:36.722010 Freq=600, CH0 RK0
4139 13:08:36.722066
4140 13:08:36.725506 DATLAT Default: 0x9
4141 13:08:36.725582 0, 0xFFFF, sum = 0
4142 13:08:36.728846 1, 0xFFFF, sum = 0
4143 13:08:36.728924 2, 0xFFFF, sum = 0
4144 13:08:36.731827 3, 0xFFFF, sum = 0
4145 13:08:36.731905 4, 0xFFFF, sum = 0
4146 13:08:36.735280 5, 0xFFFF, sum = 0
4147 13:08:36.735358 6, 0xFFFF, sum = 0
4148 13:08:36.738535 7, 0xFFFF, sum = 0
4149 13:08:36.738613 8, 0x0, sum = 1
4150 13:08:36.742172 9, 0x0, sum = 2
4151 13:08:36.742251 10, 0x0, sum = 3
4152 13:08:36.745605 11, 0x0, sum = 4
4153 13:08:36.745683 best_step = 9
4154 13:08:36.745743
4155 13:08:36.745797 ==
4156 13:08:36.748611 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 13:08:36.755628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 13:08:36.755706 ==
4159 13:08:36.755766 RX Vref Scan: 1
4160 13:08:36.755822
4161 13:08:36.759128 RX Vref 0 -> 0, step: 1
4162 13:08:36.759207
4163 13:08:36.762319 RX Delay -179 -> 252, step: 8
4164 13:08:36.762395
4165 13:08:36.765884 Set Vref, RX VrefLevel [Byte0]: 54
4166 13:08:36.768834 [Byte1]: 49
4167 13:08:36.768910
4168 13:08:36.772269 Final RX Vref Byte 0 = 54 to rank0
4169 13:08:36.775516 Final RX Vref Byte 1 = 49 to rank0
4170 13:08:36.779065 Final RX Vref Byte 0 = 54 to rank1
4171 13:08:36.782110 Final RX Vref Byte 1 = 49 to rank1==
4172 13:08:36.785388 Dram Type= 6, Freq= 0, CH_0, rank 0
4173 13:08:36.788982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 13:08:36.789060 ==
4175 13:08:36.789166 DQS Delay:
4176 13:08:36.792261 DQS0 = 0, DQS1 = 0
4177 13:08:36.792337 DQM Delay:
4178 13:08:36.795716 DQM0 = 49, DQM1 = 36
4179 13:08:36.795792 DQ Delay:
4180 13:08:36.798996 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =48
4181 13:08:36.802145 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4182 13:08:36.805348 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4183 13:08:36.808949 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =44
4184 13:08:36.809025
4185 13:08:36.809086
4186 13:08:36.819307 [DQSOSCAuto] RK0, (LSB)MR18= 0x645e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
4187 13:08:36.819384 CH0 RK0: MR19=808, MR18=645E
4188 13:08:36.825544 CH0_RK0: MR19=0x808, MR18=0x645E, DQSOSC=391, MR23=63, INC=171, DEC=114
4189 13:08:36.825644
4190 13:08:36.828832 ----->DramcWriteLeveling(PI) begin...
4191 13:08:36.828909 ==
4192 13:08:36.832422 Dram Type= 6, Freq= 0, CH_0, rank 1
4193 13:08:36.838775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 13:08:36.838852 ==
4195 13:08:36.842060 Write leveling (Byte 0): 34 => 34
4196 13:08:36.845371 Write leveling (Byte 1): 30 => 30
4197 13:08:36.845447 DramcWriteLeveling(PI) end<-----
4198 13:08:36.848921
4199 13:08:36.848997 ==
4200 13:08:36.851785 Dram Type= 6, Freq= 0, CH_0, rank 1
4201 13:08:36.855231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 13:08:36.855308 ==
4203 13:08:36.858274 [Gating] SW mode calibration
4204 13:08:36.865386 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4205 13:08:36.868233 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4206 13:08:36.874993 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4207 13:08:36.878221 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4208 13:08:36.881695 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4209 13:08:36.888649 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 1)
4210 13:08:36.891756 0 9 16 | B1->B0 | 2a2a 2525 | 0 0 | (0 0) (0 0)
4211 13:08:36.894791 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 13:08:36.901854 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 13:08:36.904923 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 13:08:36.908413 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 13:08:36.914970 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 13:08:36.918069 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 13:08:36.921727 0 10 12 | B1->B0 | 2e2e 3030 | 0 0 | (0 0) (0 0)
4218 13:08:36.928112 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4219 13:08:36.931774 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 13:08:36.935239 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 13:08:36.941666 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 13:08:36.945390 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 13:08:36.948360 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 13:08:36.955173 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 13:08:36.958419 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 13:08:36.961366 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4227 13:08:36.964860 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 13:08:36.971815 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 13:08:36.974900 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 13:08:36.978450 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 13:08:36.984828 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 13:08:36.988194 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 13:08:36.991359 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 13:08:36.998248 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 13:08:37.001703 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 13:08:37.004999 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 13:08:37.011734 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 13:08:37.014973 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 13:08:37.018150 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 13:08:37.024734 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 13:08:37.028142 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4242 13:08:37.031493 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4243 13:08:37.034724 Total UI for P1: 0, mck2ui 16
4244 13:08:37.038261 best dqsien dly found for B0: ( 0, 13, 12)
4245 13:08:37.045040 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 13:08:37.045179 Total UI for P1: 0, mck2ui 16
4247 13:08:37.051265 best dqsien dly found for B1: ( 0, 13, 14)
4248 13:08:37.054555 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4249 13:08:37.058159 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4250 13:08:37.058236
4251 13:08:37.061182 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4252 13:08:37.065086 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4253 13:08:37.067811 [Gating] SW calibration Done
4254 13:08:37.067887 ==
4255 13:08:37.071183 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 13:08:37.074547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 13:08:37.074624 ==
4258 13:08:37.077920 RX Vref Scan: 0
4259 13:08:37.077996
4260 13:08:37.078055 RX Vref 0 -> 0, step: 1
4261 13:08:37.078109
4262 13:08:37.081575 RX Delay -230 -> 252, step: 16
4263 13:08:37.088022 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4264 13:08:37.091296 iDelay=218, Bit 1, Center 57 (-86 ~ 201) 288
4265 13:08:37.094597 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4266 13:08:37.098122 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4267 13:08:37.101457 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4268 13:08:37.107848 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4269 13:08:37.111203 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4270 13:08:37.114760 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4271 13:08:37.117842 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4272 13:08:37.121154 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4273 13:08:37.127902 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4274 13:08:37.131318 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4275 13:08:37.134999 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4276 13:08:37.138237 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4277 13:08:37.144706 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4278 13:08:37.148271 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4279 13:08:37.148348 ==
4280 13:08:37.151697 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 13:08:37.154597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 13:08:37.154675 ==
4283 13:08:37.158171 DQS Delay:
4284 13:08:37.158247 DQS0 = 0, DQS1 = 0
4285 13:08:37.158309 DQM Delay:
4286 13:08:37.161268 DQM0 = 53, DQM1 = 42
4287 13:08:37.161345 DQ Delay:
4288 13:08:37.164857 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4289 13:08:37.168371 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4290 13:08:37.171296 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4291 13:08:37.174735 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4292 13:08:37.174813
4293 13:08:37.174872
4294 13:08:37.174926 ==
4295 13:08:37.178213 Dram Type= 6, Freq= 0, CH_0, rank 1
4296 13:08:37.181062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4297 13:08:37.184486 ==
4298 13:08:37.184562
4299 13:08:37.184621
4300 13:08:37.184675 TX Vref Scan disable
4301 13:08:37.188405 == TX Byte 0 ==
4302 13:08:37.191189 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4303 13:08:37.194753 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4304 13:08:37.197965 == TX Byte 1 ==
4305 13:08:37.201092 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4306 13:08:37.208080 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4307 13:08:37.208158 ==
4308 13:08:37.211384 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 13:08:37.214558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 13:08:37.214636 ==
4311 13:08:37.214696
4312 13:08:37.214751
4313 13:08:37.217841 TX Vref Scan disable
4314 13:08:37.220963 == TX Byte 0 ==
4315 13:08:37.224781 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4316 13:08:37.227728 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4317 13:08:37.230918 == TX Byte 1 ==
4318 13:08:37.234287 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4319 13:08:37.237581 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4320 13:08:37.237672
4321 13:08:37.237735 [DATLAT]
4322 13:08:37.240905 Freq=600, CH0 RK1
4323 13:08:37.240996
4324 13:08:37.241078 DATLAT Default: 0x9
4325 13:08:37.244478 0, 0xFFFF, sum = 0
4326 13:08:37.247827 1, 0xFFFF, sum = 0
4327 13:08:37.247906 2, 0xFFFF, sum = 0
4328 13:08:37.251163 3, 0xFFFF, sum = 0
4329 13:08:37.251261 4, 0xFFFF, sum = 0
4330 13:08:37.254303 5, 0xFFFF, sum = 0
4331 13:08:37.254382 6, 0xFFFF, sum = 0
4332 13:08:37.257523 7, 0xFFFF, sum = 0
4333 13:08:37.257704 8, 0x0, sum = 1
4334 13:08:37.261373 9, 0x0, sum = 2
4335 13:08:37.261451 10, 0x0, sum = 3
4336 13:08:37.261513 11, 0x0, sum = 4
4337 13:08:37.264671 best_step = 9
4338 13:08:37.264770
4339 13:08:37.264861 ==
4340 13:08:37.267555 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 13:08:37.271200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 13:08:37.271278 ==
4343 13:08:37.274191 RX Vref Scan: 0
4344 13:08:37.274260
4345 13:08:37.274316 RX Vref 0 -> 0, step: 1
4346 13:08:37.274368
4347 13:08:37.277376 RX Delay -179 -> 252, step: 8
4348 13:08:37.284986 iDelay=205, Bit 0, Center 44 (-99 ~ 188) 288
4349 13:08:37.288376 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4350 13:08:37.291804 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4351 13:08:37.294900 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4352 13:08:37.298219 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4353 13:08:37.305241 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4354 13:08:37.308345 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4355 13:08:37.311565 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4356 13:08:37.314952 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4357 13:08:37.318441 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4358 13:08:37.325156 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4359 13:08:37.329268 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4360 13:08:37.332394 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4361 13:08:37.335238 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4362 13:08:37.341619 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4363 13:08:37.345320 iDelay=205, Bit 15, Center 48 (-91 ~ 188) 280
4364 13:08:37.345402 ==
4365 13:08:37.348630 Dram Type= 6, Freq= 0, CH_0, rank 1
4366 13:08:37.351629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 13:08:37.351698 ==
4368 13:08:37.355139 DQS Delay:
4369 13:08:37.355215 DQS0 = 0, DQS1 = 0
4370 13:08:37.355274 DQM Delay:
4371 13:08:37.358562 DQM0 = 47, DQM1 = 41
4372 13:08:37.358637 DQ Delay:
4373 13:08:37.361846 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4374 13:08:37.365102 DQ4 =52, DQ5 =40, DQ6 =56, DQ7 =52
4375 13:08:37.368316 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4376 13:08:37.371669 DQ12 =48, DQ13 =48, DQ14 =52, DQ15 =48
4377 13:08:37.371745
4378 13:08:37.371804
4379 13:08:37.381751 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a36, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
4380 13:08:37.381830 CH0 RK1: MR19=808, MR18=6A36
4381 13:08:37.388306 CH0_RK1: MR19=0x808, MR18=0x6A36, DQSOSC=389, MR23=63, INC=173, DEC=115
4382 13:08:37.391814 [RxdqsGatingPostProcess] freq 600
4383 13:08:37.398734 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4384 13:08:37.401787 Pre-setting of DQS Precalculation
4385 13:08:37.404888 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4386 13:08:37.404964 ==
4387 13:08:37.408652 Dram Type= 6, Freq= 0, CH_1, rank 0
4388 13:08:37.411614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 13:08:37.415245 ==
4390 13:08:37.418664 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4391 13:08:37.425434 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4392 13:08:37.428234 [CA 0] Center 35 (5~66) winsize 62
4393 13:08:37.431912 [CA 1] Center 35 (5~66) winsize 62
4394 13:08:37.434798 [CA 2] Center 34 (4~65) winsize 62
4395 13:08:37.438335 [CA 3] Center 33 (3~64) winsize 62
4396 13:08:37.441726 [CA 4] Center 33 (3~64) winsize 62
4397 13:08:37.444916 [CA 5] Center 33 (3~64) winsize 62
4398 13:08:37.444992
4399 13:08:37.448756 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4400 13:08:37.448833
4401 13:08:37.451730 [CATrainingPosCal] consider 1 rank data
4402 13:08:37.454846 u2DelayCellTimex100 = 270/100 ps
4403 13:08:37.458303 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4404 13:08:37.461649 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4405 13:08:37.465101 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4406 13:08:37.468320 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4407 13:08:37.475104 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4408 13:08:37.478484 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4409 13:08:37.478561
4410 13:08:37.481458 CA PerBit enable=1, Macro0, CA PI delay=33
4411 13:08:37.481535
4412 13:08:37.484937 [CBTSetCACLKResult] CA Dly = 33
4413 13:08:37.485014 CS Dly: 5 (0~36)
4414 13:08:37.485074 ==
4415 13:08:37.488345 Dram Type= 6, Freq= 0, CH_1, rank 1
4416 13:08:37.494958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 13:08:37.495037 ==
4418 13:08:37.498211 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4419 13:08:37.504748 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4420 13:08:37.508340 [CA 0] Center 35 (5~66) winsize 62
4421 13:08:37.511732 [CA 1] Center 35 (5~66) winsize 62
4422 13:08:37.515282 [CA 2] Center 34 (4~65) winsize 62
4423 13:08:37.518450 [CA 3] Center 34 (4~65) winsize 62
4424 13:08:37.521543 [CA 4] Center 34 (4~65) winsize 62
4425 13:08:37.524959 [CA 5] Center 34 (3~65) winsize 63
4426 13:08:37.525058
4427 13:08:37.528571 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4428 13:08:37.528647
4429 13:08:37.531668 [CATrainingPosCal] consider 2 rank data
4430 13:08:37.535280 u2DelayCellTimex100 = 270/100 ps
4431 13:08:37.538372 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4432 13:08:37.541904 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4433 13:08:37.544879 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4434 13:08:37.551814 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4435 13:08:37.554928 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4436 13:08:37.558703 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4437 13:08:37.558780
4438 13:08:37.561785 CA PerBit enable=1, Macro0, CA PI delay=33
4439 13:08:37.561862
4440 13:08:37.565190 [CBTSetCACLKResult] CA Dly = 33
4441 13:08:37.565267 CS Dly: 5 (0~37)
4442 13:08:37.565328
4443 13:08:37.568402 ----->DramcWriteLeveling(PI) begin...
4444 13:08:37.568480 ==
4445 13:08:37.571680 Dram Type= 6, Freq= 0, CH_1, rank 0
4446 13:08:37.578088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4447 13:08:37.578165 ==
4448 13:08:37.581762 Write leveling (Byte 0): 31 => 31
4449 13:08:37.581839 Write leveling (Byte 1): 31 => 31
4450 13:08:37.585325 DramcWriteLeveling(PI) end<-----
4451 13:08:37.585402
4452 13:08:37.585462 ==
4453 13:08:37.588669 Dram Type= 6, Freq= 0, CH_1, rank 0
4454 13:08:37.595197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4455 13:08:37.595274 ==
4456 13:08:37.598707 [Gating] SW mode calibration
4457 13:08:37.604880 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4458 13:08:37.608351 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4459 13:08:37.614660 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4460 13:08:37.618077 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4461 13:08:37.621393 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4462 13:08:37.628337 0 9 12 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
4463 13:08:37.631299 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 13:08:37.634883 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 13:08:37.641595 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 13:08:37.644883 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 13:08:37.648200 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 13:08:37.654729 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 13:08:37.658034 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4470 13:08:37.661474 0 10 12 | B1->B0 | 3838 3b3b | 1 1 | (0 0) (0 0)
4471 13:08:37.664869 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 13:08:37.671328 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 13:08:37.674620 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 13:08:37.678198 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 13:08:37.684473 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 13:08:37.687870 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 13:08:37.691383 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4478 13:08:37.698191 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4479 13:08:37.701649 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 13:08:37.704689 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 13:08:37.711551 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 13:08:37.714614 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 13:08:37.718084 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 13:08:37.725022 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 13:08:37.727943 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 13:08:37.731627 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 13:08:37.737940 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 13:08:37.741325 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 13:08:37.744542 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 13:08:37.751338 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 13:08:37.754956 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 13:08:37.758061 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 13:08:37.764489 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4494 13:08:37.767955 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4495 13:08:37.771845 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 13:08:37.774616 Total UI for P1: 0, mck2ui 16
4497 13:08:37.777733 best dqsien dly found for B0: ( 0, 13, 10)
4498 13:08:37.781580 Total UI for P1: 0, mck2ui 16
4499 13:08:37.784289 best dqsien dly found for B1: ( 0, 13, 12)
4500 13:08:37.787758 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4501 13:08:37.791026 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4502 13:08:37.791102
4503 13:08:37.794168 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4504 13:08:37.800944 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4505 13:08:37.801023 [Gating] SW calibration Done
4506 13:08:37.801083 ==
4507 13:08:37.804729 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 13:08:37.811180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 13:08:37.811258 ==
4510 13:08:37.811318 RX Vref Scan: 0
4511 13:08:37.811374
4512 13:08:37.814492 RX Vref 0 -> 0, step: 1
4513 13:08:37.814569
4514 13:08:37.817840 RX Delay -230 -> 252, step: 16
4515 13:08:37.821158 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4516 13:08:37.824740 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4517 13:08:37.828206 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4518 13:08:37.834662 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4519 13:08:37.837881 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4520 13:08:37.841093 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4521 13:08:37.844553 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4522 13:08:37.847662 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4523 13:08:37.854699 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4524 13:08:37.858065 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4525 13:08:37.861159 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4526 13:08:37.864608 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4527 13:08:37.871498 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4528 13:08:37.874398 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4529 13:08:37.877942 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4530 13:08:37.880869 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4531 13:08:37.880960 ==
4532 13:08:37.884843 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 13:08:37.891286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 13:08:37.891364 ==
4535 13:08:37.891424 DQS Delay:
4536 13:08:37.894567 DQS0 = 0, DQS1 = 0
4537 13:08:37.894651 DQM Delay:
4538 13:08:37.894712 DQM0 = 52, DQM1 = 41
4539 13:08:37.897766 DQ Delay:
4540 13:08:37.901450 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4541 13:08:37.904694 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4542 13:08:37.907965 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4543 13:08:37.911345 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =49
4544 13:08:37.911422
4545 13:08:37.911481
4546 13:08:37.911535 ==
4547 13:08:37.914632 Dram Type= 6, Freq= 0, CH_1, rank 0
4548 13:08:37.918295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4549 13:08:37.918374 ==
4550 13:08:37.918434
4551 13:08:37.918488
4552 13:08:37.921549 TX Vref Scan disable
4553 13:08:37.921625 == TX Byte 0 ==
4554 13:08:37.927758 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4555 13:08:37.931461 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4556 13:08:37.934560 == TX Byte 1 ==
4557 13:08:37.937746 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4558 13:08:37.941107 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4559 13:08:37.941224 ==
4560 13:08:37.944739 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 13:08:37.947621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 13:08:37.947699 ==
4563 13:08:37.947758
4564 13:08:37.950963
4565 13:08:37.951039 TX Vref Scan disable
4566 13:08:37.954673 == TX Byte 0 ==
4567 13:08:37.957737 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4568 13:08:37.961072 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4569 13:08:37.964817 == TX Byte 1 ==
4570 13:08:37.967691 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4571 13:08:37.971000 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4572 13:08:37.974411
4573 13:08:37.974488 [DATLAT]
4574 13:08:37.974547 Freq=600, CH1 RK0
4575 13:08:37.974602
4576 13:08:37.977722 DATLAT Default: 0x9
4577 13:08:37.977800 0, 0xFFFF, sum = 0
4578 13:08:37.981484 1, 0xFFFF, sum = 0
4579 13:08:37.981563 2, 0xFFFF, sum = 0
4580 13:08:37.984541 3, 0xFFFF, sum = 0
4581 13:08:37.984619 4, 0xFFFF, sum = 0
4582 13:08:37.988102 5, 0xFFFF, sum = 0
4583 13:08:37.988181 6, 0xFFFF, sum = 0
4584 13:08:37.991536 7, 0xFFFF, sum = 0
4585 13:08:37.991614 8, 0x0, sum = 1
4586 13:08:37.994834 9, 0x0, sum = 2
4587 13:08:37.994912 10, 0x0, sum = 3
4588 13:08:37.997842 11, 0x0, sum = 4
4589 13:08:37.997919 best_step = 9
4590 13:08:37.997979
4591 13:08:37.998034 ==
4592 13:08:38.001253 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 13:08:38.007962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 13:08:38.008039 ==
4595 13:08:38.008100 RX Vref Scan: 1
4596 13:08:38.008156
4597 13:08:38.011312 RX Vref 0 -> 0, step: 1
4598 13:08:38.011388
4599 13:08:38.014514 RX Delay -179 -> 252, step: 8
4600 13:08:38.014594
4601 13:08:38.018018 Set Vref, RX VrefLevel [Byte0]: 49
4602 13:08:38.020901 [Byte1]: 53
4603 13:08:38.020978
4604 13:08:38.024515 Final RX Vref Byte 0 = 49 to rank0
4605 13:08:38.027863 Final RX Vref Byte 1 = 53 to rank0
4606 13:08:38.031188 Final RX Vref Byte 0 = 49 to rank1
4607 13:08:38.034446 Final RX Vref Byte 1 = 53 to rank1==
4608 13:08:38.038271 Dram Type= 6, Freq= 0, CH_1, rank 0
4609 13:08:38.040901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 13:08:38.040978 ==
4611 13:08:38.044593 DQS Delay:
4612 13:08:38.044668 DQS0 = 0, DQS1 = 0
4613 13:08:38.044728 DQM Delay:
4614 13:08:38.047684 DQM0 = 48, DQM1 = 41
4615 13:08:38.047761 DQ Delay:
4616 13:08:38.051198 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4617 13:08:38.054537 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4618 13:08:38.057748 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4619 13:08:38.061341 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4620 13:08:38.061418
4621 13:08:38.061479
4622 13:08:38.071340 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f75, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
4623 13:08:38.071418 CH1 RK0: MR19=808, MR18=4F75
4624 13:08:38.077571 CH1_RK0: MR19=0x808, MR18=0x4F75, DQSOSC=387, MR23=63, INC=175, DEC=116
4625 13:08:38.077648
4626 13:08:38.080819 ----->DramcWriteLeveling(PI) begin...
4627 13:08:38.084386 ==
4628 13:08:38.084464 Dram Type= 6, Freq= 0, CH_1, rank 1
4629 13:08:38.090971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4630 13:08:38.091048 ==
4631 13:08:38.094149 Write leveling (Byte 0): 30 => 30
4632 13:08:38.097368 Write leveling (Byte 1): 31 => 31
4633 13:08:38.100704 DramcWriteLeveling(PI) end<-----
4634 13:08:38.100784
4635 13:08:38.100845 ==
4636 13:08:38.104103 Dram Type= 6, Freq= 0, CH_1, rank 1
4637 13:08:38.107721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 13:08:38.107798 ==
4639 13:08:38.111001 [Gating] SW mode calibration
4640 13:08:38.117557 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4641 13:08:38.120817 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4642 13:08:38.127298 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4643 13:08:38.130880 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4644 13:08:38.134010 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4645 13:08:38.140709 0 9 12 | B1->B0 | 2727 3030 | 1 1 | (1 0) (0 1)
4646 13:08:38.144175 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 13:08:38.147151 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 13:08:38.153894 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 13:08:38.157047 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 13:08:38.160749 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 13:08:38.166981 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 13:08:38.170904 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4653 13:08:38.174017 0 10 12 | B1->B0 | 4040 2626 | 0 0 | (1 1) (0 0)
4654 13:08:38.180575 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4655 13:08:38.183635 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 13:08:38.187056 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 13:08:38.193602 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 13:08:38.196909 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 13:08:38.200235 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 13:08:38.206727 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4661 13:08:38.210236 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4662 13:08:38.213426 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 13:08:38.220258 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 13:08:38.223661 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 13:08:38.226875 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 13:08:38.233666 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 13:08:38.236908 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 13:08:38.240630 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 13:08:38.247129 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 13:08:38.250215 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 13:08:38.253766 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 13:08:38.260336 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 13:08:38.263375 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 13:08:38.267029 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 13:08:38.270279 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 13:08:38.276749 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 13:08:38.280365 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4678 13:08:38.283765 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 13:08:38.287026 Total UI for P1: 0, mck2ui 16
4680 13:08:38.290466 best dqsien dly found for B0: ( 0, 13, 12)
4681 13:08:38.293602 Total UI for P1: 0, mck2ui 16
4682 13:08:38.297076 best dqsien dly found for B1: ( 0, 13, 12)
4683 13:08:38.300181 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4684 13:08:38.303809 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4685 13:08:38.303986
4686 13:08:38.310338 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4687 13:08:38.313728 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4688 13:08:38.317344 [Gating] SW calibration Done
4689 13:08:38.317421 ==
4690 13:08:38.320359 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 13:08:38.323803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 13:08:38.323884 ==
4693 13:08:38.323944 RX Vref Scan: 0
4694 13:08:38.323999
4695 13:08:38.327007 RX Vref 0 -> 0, step: 1
4696 13:08:38.327086
4697 13:08:38.330728 RX Delay -230 -> 252, step: 16
4698 13:08:38.333558 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4699 13:08:38.336756 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4700 13:08:38.343914 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4701 13:08:38.347164 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4702 13:08:38.350134 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4703 13:08:38.353760 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4704 13:08:38.356933 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4705 13:08:38.363299 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4706 13:08:38.367009 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4707 13:08:38.370292 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4708 13:08:38.373523 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4709 13:08:38.380688 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4710 13:08:38.383484 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4711 13:08:38.387384 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4712 13:08:38.390066 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4713 13:08:38.393946 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4714 13:08:38.397144 ==
4715 13:08:38.400340 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 13:08:38.403430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 13:08:38.403507 ==
4718 13:08:38.403567 DQS Delay:
4719 13:08:38.407086 DQS0 = 0, DQS1 = 0
4720 13:08:38.407162 DQM Delay:
4721 13:08:38.410554 DQM0 = 53, DQM1 = 47
4722 13:08:38.410630 DQ Delay:
4723 13:08:38.413597 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4724 13:08:38.416770 DQ4 =57, DQ5 =65, DQ6 =57, DQ7 =49
4725 13:08:38.420449 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4726 13:08:38.423709 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =65
4727 13:08:38.423786
4728 13:08:38.423845
4729 13:08:38.423904 ==
4730 13:08:38.426832 Dram Type= 6, Freq= 0, CH_1, rank 1
4731 13:08:38.430346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4732 13:08:38.430416 ==
4733 13:08:38.430472
4734 13:08:38.430525
4735 13:08:38.433424 TX Vref Scan disable
4736 13:08:38.437104 == TX Byte 0 ==
4737 13:08:38.440639 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4738 13:08:38.443576 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4739 13:08:38.447011 == TX Byte 1 ==
4740 13:08:38.450424 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4741 13:08:38.453484 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4742 13:08:38.453573 ==
4743 13:08:38.456748 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 13:08:38.460389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 13:08:38.463435 ==
4746 13:08:38.463512
4747 13:08:38.463570
4748 13:08:38.463624 TX Vref Scan disable
4749 13:08:38.467227 == TX Byte 0 ==
4750 13:08:38.470630 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4751 13:08:38.474145 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4752 13:08:38.477252 == TX Byte 1 ==
4753 13:08:38.480788 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4754 13:08:38.484419 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4755 13:08:38.487681
4756 13:08:38.487757 [DATLAT]
4757 13:08:38.487817 Freq=600, CH1 RK1
4758 13:08:38.487873
4759 13:08:38.490687 DATLAT Default: 0x9
4760 13:08:38.490774 0, 0xFFFF, sum = 0
4761 13:08:38.493984 1, 0xFFFF, sum = 0
4762 13:08:38.494061 2, 0xFFFF, sum = 0
4763 13:08:38.497229 3, 0xFFFF, sum = 0
4764 13:08:38.497306 4, 0xFFFF, sum = 0
4765 13:08:38.500892 5, 0xFFFF, sum = 0
4766 13:08:38.503837 6, 0xFFFF, sum = 0
4767 13:08:38.503914 7, 0xFFFF, sum = 0
4768 13:08:38.503975 8, 0x0, sum = 1
4769 13:08:38.507340 9, 0x0, sum = 2
4770 13:08:38.507447 10, 0x0, sum = 3
4771 13:08:38.510505 11, 0x0, sum = 4
4772 13:08:38.510574 best_step = 9
4773 13:08:38.510631
4774 13:08:38.510684 ==
4775 13:08:38.514048 Dram Type= 6, Freq= 0, CH_1, rank 1
4776 13:08:38.520722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4777 13:08:38.520799 ==
4778 13:08:38.520858 RX Vref Scan: 0
4779 13:08:38.520913
4780 13:08:38.524035 RX Vref 0 -> 0, step: 1
4781 13:08:38.524111
4782 13:08:38.527224 RX Delay -163 -> 252, step: 8
4783 13:08:38.530430 iDelay=205, Bit 0, Center 52 (-83 ~ 188) 272
4784 13:08:38.537273 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4785 13:08:38.540803 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4786 13:08:38.543801 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4787 13:08:38.547286 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4788 13:08:38.550869 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4789 13:08:38.554194 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4790 13:08:38.560709 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4791 13:08:38.563899 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4792 13:08:38.567117 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4793 13:08:38.570340 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4794 13:08:38.576930 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4795 13:08:38.580290 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4796 13:08:38.583806 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4797 13:08:38.587035 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4798 13:08:38.593636 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4799 13:08:38.593713 ==
4800 13:08:38.596743 Dram Type= 6, Freq= 0, CH_1, rank 1
4801 13:08:38.600334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4802 13:08:38.600411 ==
4803 13:08:38.600471 DQS Delay:
4804 13:08:38.603716 DQS0 = 0, DQS1 = 0
4805 13:08:38.603793 DQM Delay:
4806 13:08:38.606680 DQM0 = 49, DQM1 = 43
4807 13:08:38.606756 DQ Delay:
4808 13:08:38.610245 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =48
4809 13:08:38.613212 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4810 13:08:38.616907 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4811 13:08:38.619872 DQ12 =48, DQ13 =52, DQ14 =48, DQ15 =52
4812 13:08:38.619964
4813 13:08:38.620048
4814 13:08:38.626967 [DQSOSCAuto] RK1, (LSB)MR18= 0x652b, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 390 ps
4815 13:08:38.629771 CH1 RK1: MR19=808, MR18=652B
4816 13:08:38.636371 CH1_RK1: MR19=0x808, MR18=0x652B, DQSOSC=390, MR23=63, INC=172, DEC=114
4817 13:08:38.639552 [RxdqsGatingPostProcess] freq 600
4818 13:08:38.646460 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4819 13:08:38.649943 Pre-setting of DQS Precalculation
4820 13:08:38.653249 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4821 13:08:38.659628 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4822 13:08:38.666407 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4823 13:08:38.666484
4824 13:08:38.666544
4825 13:08:38.669829 [Calibration Summary] 1200 Mbps
4826 13:08:38.673153 CH 0, Rank 0
4827 13:08:38.673243 SW Impedance : PASS
4828 13:08:38.676490 DUTY Scan : NO K
4829 13:08:38.679488 ZQ Calibration : PASS
4830 13:08:38.679565 Jitter Meter : NO K
4831 13:08:38.683063 CBT Training : PASS
4832 13:08:38.686551 Write leveling : PASS
4833 13:08:38.686628 RX DQS gating : PASS
4834 13:08:38.689443 RX DQ/DQS(RDDQC) : PASS
4835 13:08:38.692976 TX DQ/DQS : PASS
4836 13:08:38.693053 RX DATLAT : PASS
4837 13:08:38.696234 RX DQ/DQS(Engine): PASS
4838 13:08:38.696311 TX OE : NO K
4839 13:08:38.699828 All Pass.
4840 13:08:38.699904
4841 13:08:38.699962 CH 0, Rank 1
4842 13:08:38.703139 SW Impedance : PASS
4843 13:08:38.703216 DUTY Scan : NO K
4844 13:08:38.706046 ZQ Calibration : PASS
4845 13:08:38.709464 Jitter Meter : NO K
4846 13:08:38.709540 CBT Training : PASS
4847 13:08:38.712934 Write leveling : PASS
4848 13:08:38.716688 RX DQS gating : PASS
4849 13:08:38.716764 RX DQ/DQS(RDDQC) : PASS
4850 13:08:38.719453 TX DQ/DQS : PASS
4851 13:08:38.722974 RX DATLAT : PASS
4852 13:08:38.723050 RX DQ/DQS(Engine): PASS
4853 13:08:38.726324 TX OE : NO K
4854 13:08:38.726401 All Pass.
4855 13:08:38.726460
4856 13:08:38.729593 CH 1, Rank 0
4857 13:08:38.729669 SW Impedance : PASS
4858 13:08:38.732708 DUTY Scan : NO K
4859 13:08:38.735887 ZQ Calibration : PASS
4860 13:08:38.735965 Jitter Meter : NO K
4861 13:08:38.739445 CBT Training : PASS
4862 13:08:38.739521 Write leveling : PASS
4863 13:08:38.742662 RX DQS gating : PASS
4864 13:08:38.746498 RX DQ/DQS(RDDQC) : PASS
4865 13:08:38.746568 TX DQ/DQS : PASS
4866 13:08:38.749594 RX DATLAT : PASS
4867 13:08:38.753068 RX DQ/DQS(Engine): PASS
4868 13:08:38.753185 TX OE : NO K
4869 13:08:38.756219 All Pass.
4870 13:08:38.756294
4871 13:08:38.756353 CH 1, Rank 1
4872 13:08:38.759680 SW Impedance : PASS
4873 13:08:38.759757 DUTY Scan : NO K
4874 13:08:38.762921 ZQ Calibration : PASS
4875 13:08:38.766309 Jitter Meter : NO K
4876 13:08:38.766386 CBT Training : PASS
4877 13:08:38.769924 Write leveling : PASS
4878 13:08:38.773132 RX DQS gating : PASS
4879 13:08:38.773224 RX DQ/DQS(RDDQC) : PASS
4880 13:08:38.776228 TX DQ/DQS : PASS
4881 13:08:38.779726 RX DATLAT : PASS
4882 13:08:38.779803 RX DQ/DQS(Engine): PASS
4883 13:08:38.782835 TX OE : NO K
4884 13:08:38.782912 All Pass.
4885 13:08:38.782971
4886 13:08:38.786350 DramC Write-DBI off
4887 13:08:38.789703 PER_BANK_REFRESH: Hybrid Mode
4888 13:08:38.789780 TX_TRACKING: ON
4889 13:08:38.799556 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4890 13:08:38.802659 [FAST_K] Save calibration result to emmc
4891 13:08:38.806126 dramc_set_vcore_voltage set vcore to 662500
4892 13:08:38.806203 Read voltage for 933, 3
4893 13:08:38.809534 Vio18 = 0
4894 13:08:38.809610 Vcore = 662500
4895 13:08:38.809670 Vdram = 0
4896 13:08:38.813010 Vddq = 0
4897 13:08:38.813085 Vmddr = 0
4898 13:08:38.819412 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4899 13:08:38.822922 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4900 13:08:38.826039 MEM_TYPE=3, freq_sel=17
4901 13:08:38.829572 sv_algorithm_assistance_LP4_1600
4902 13:08:38.833003 ============ PULL DRAM RESETB DOWN ============
4903 13:08:38.836488 ========== PULL DRAM RESETB DOWN end =========
4904 13:08:38.842754 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4905 13:08:38.846526 ===================================
4906 13:08:38.846603 LPDDR4 DRAM CONFIGURATION
4907 13:08:38.849748 ===================================
4908 13:08:38.852813 EX_ROW_EN[0] = 0x0
4909 13:08:38.852889 EX_ROW_EN[1] = 0x0
4910 13:08:38.856095 LP4Y_EN = 0x0
4911 13:08:38.856172 WORK_FSP = 0x0
4912 13:08:38.859276 WL = 0x3
4913 13:08:38.859353 RL = 0x3
4914 13:08:38.863074 BL = 0x2
4915 13:08:38.866019 RPST = 0x0
4916 13:08:38.866095 RD_PRE = 0x0
4917 13:08:38.869677 WR_PRE = 0x1
4918 13:08:38.869753 WR_PST = 0x0
4919 13:08:38.872856 DBI_WR = 0x0
4920 13:08:38.872933 DBI_RD = 0x0
4921 13:08:38.875980 OTF = 0x1
4922 13:08:38.879719 ===================================
4923 13:08:38.882695 ===================================
4924 13:08:38.882778 ANA top config
4925 13:08:38.886340 ===================================
4926 13:08:38.889595 DLL_ASYNC_EN = 0
4927 13:08:38.892644 ALL_SLAVE_EN = 1
4928 13:08:38.892716 NEW_RANK_MODE = 1
4929 13:08:38.896318 DLL_IDLE_MODE = 1
4930 13:08:38.899552 LP45_APHY_COMB_EN = 1
4931 13:08:38.903243 TX_ODT_DIS = 1
4932 13:08:38.903320 NEW_8X_MODE = 1
4933 13:08:38.906259 ===================================
4934 13:08:38.909366 ===================================
4935 13:08:38.912768 data_rate = 1866
4936 13:08:38.916358 CKR = 1
4937 13:08:38.919459 DQ_P2S_RATIO = 8
4938 13:08:38.922910 ===================================
4939 13:08:38.926103 CA_P2S_RATIO = 8
4940 13:08:38.929729 DQ_CA_OPEN = 0
4941 13:08:38.929805 DQ_SEMI_OPEN = 0
4942 13:08:38.933117 CA_SEMI_OPEN = 0
4943 13:08:38.936212 CA_FULL_RATE = 0
4944 13:08:38.939752 DQ_CKDIV4_EN = 1
4945 13:08:38.942850 CA_CKDIV4_EN = 1
4946 13:08:38.946449 CA_PREDIV_EN = 0
4947 13:08:38.946526 PH8_DLY = 0
4948 13:08:38.949465 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4949 13:08:38.952799 DQ_AAMCK_DIV = 4
4950 13:08:38.956019 CA_AAMCK_DIV = 4
4951 13:08:38.959509 CA_ADMCK_DIV = 4
4952 13:08:38.962995 DQ_TRACK_CA_EN = 0
4953 13:08:38.963072 CA_PICK = 933
4954 13:08:38.966335 CA_MCKIO = 933
4955 13:08:38.969373 MCKIO_SEMI = 0
4956 13:08:38.973038 PLL_FREQ = 3732
4957 13:08:38.976007 DQ_UI_PI_RATIO = 32
4958 13:08:38.979161 CA_UI_PI_RATIO = 0
4959 13:08:38.982585 ===================================
4960 13:08:38.986170 ===================================
4961 13:08:38.986247 memory_type:LPDDR4
4962 13:08:38.989348 GP_NUM : 10
4963 13:08:38.992944 SRAM_EN : 1
4964 13:08:38.993021 MD32_EN : 0
4965 13:08:38.996132 ===================================
4966 13:08:38.999439 [ANA_INIT] >>>>>>>>>>>>>>
4967 13:08:39.002575 <<<<<< [CONFIGURE PHASE]: ANA_TX
4968 13:08:39.005848 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4969 13:08:39.009692 ===================================
4970 13:08:39.012752 data_rate = 1866,PCW = 0X8f00
4971 13:08:39.016017 ===================================
4972 13:08:39.019323 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4973 13:08:39.022677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4974 13:08:39.029597 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4975 13:08:39.032778 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4976 13:08:39.035804 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4977 13:08:39.038976 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4978 13:08:39.042551 [ANA_INIT] flow start
4979 13:08:39.045642 [ANA_INIT] PLL >>>>>>>>
4980 13:08:39.045718 [ANA_INIT] PLL <<<<<<<<
4981 13:08:39.049260 [ANA_INIT] MIDPI >>>>>>>>
4982 13:08:39.052682 [ANA_INIT] MIDPI <<<<<<<<
4983 13:08:39.055807 [ANA_INIT] DLL >>>>>>>>
4984 13:08:39.055883 [ANA_INIT] flow end
4985 13:08:39.059169 ============ LP4 DIFF to SE enter ============
4986 13:08:39.065849 ============ LP4 DIFF to SE exit ============
4987 13:08:39.065927 [ANA_INIT] <<<<<<<<<<<<<
4988 13:08:39.069045 [Flow] Enable top DCM control >>>>>
4989 13:08:39.072183 [Flow] Enable top DCM control <<<<<
4990 13:08:39.075684 Enable DLL master slave shuffle
4991 13:08:39.082553 ==============================================================
4992 13:08:39.082630 Gating Mode config
4993 13:08:39.088747 ==============================================================
4994 13:08:39.092144 Config description:
4995 13:08:39.102369 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4996 13:08:39.108476 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4997 13:08:39.111914 SELPH_MODE 0: By rank 1: By Phase
4998 13:08:39.118815 ==============================================================
4999 13:08:39.121997 GAT_TRACK_EN = 1
5000 13:08:39.122074 RX_GATING_MODE = 2
5001 13:08:39.125262 RX_GATING_TRACK_MODE = 2
5002 13:08:39.128885 SELPH_MODE = 1
5003 13:08:39.132131 PICG_EARLY_EN = 1
5004 13:08:39.135651 VALID_LAT_VALUE = 1
5005 13:08:39.142067 ==============================================================
5006 13:08:39.145625 Enter into Gating configuration >>>>
5007 13:08:39.148987 Exit from Gating configuration <<<<
5008 13:08:39.151955 Enter into DVFS_PRE_config >>>>>
5009 13:08:39.161932 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5010 13:08:39.165425 Exit from DVFS_PRE_config <<<<<
5011 13:08:39.168917 Enter into PICG configuration >>>>
5012 13:08:39.172390 Exit from PICG configuration <<<<
5013 13:08:39.175235 [RX_INPUT] configuration >>>>>
5014 13:08:39.178864 [RX_INPUT] configuration <<<<<
5015 13:08:39.182487 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5016 13:08:39.188625 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5017 13:08:39.195293 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5018 13:08:39.198599 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5019 13:08:39.205307 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5020 13:08:39.211922 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5021 13:08:39.215441 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5022 13:08:39.218716 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5023 13:08:39.225419 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5024 13:08:39.228691 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5025 13:08:39.231945 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5026 13:08:39.238768 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5027 13:08:39.242016 ===================================
5028 13:08:39.242100 LPDDR4 DRAM CONFIGURATION
5029 13:08:39.245173 ===================================
5030 13:08:39.249068 EX_ROW_EN[0] = 0x0
5031 13:08:39.249183 EX_ROW_EN[1] = 0x0
5032 13:08:39.251815 LP4Y_EN = 0x0
5033 13:08:39.251892 WORK_FSP = 0x0
5034 13:08:39.255297 WL = 0x3
5035 13:08:39.258687 RL = 0x3
5036 13:08:39.258764 BL = 0x2
5037 13:08:39.262373 RPST = 0x0
5038 13:08:39.262456 RD_PRE = 0x0
5039 13:08:39.265372 WR_PRE = 0x1
5040 13:08:39.265473 WR_PST = 0x0
5041 13:08:39.268391 DBI_WR = 0x0
5042 13:08:39.268498 DBI_RD = 0x0
5043 13:08:39.271934 OTF = 0x1
5044 13:08:39.275265 ===================================
5045 13:08:39.278321 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5046 13:08:39.281786 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5047 13:08:39.285383 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5048 13:08:39.288312 ===================================
5049 13:08:39.292120 LPDDR4 DRAM CONFIGURATION
5050 13:08:39.294981 ===================================
5051 13:08:39.298624 EX_ROW_EN[0] = 0x10
5052 13:08:39.298700 EX_ROW_EN[1] = 0x0
5053 13:08:39.302054 LP4Y_EN = 0x0
5054 13:08:39.302155 WORK_FSP = 0x0
5055 13:08:39.305172 WL = 0x3
5056 13:08:39.305249 RL = 0x3
5057 13:08:39.308276 BL = 0x2
5058 13:08:39.308358 RPST = 0x0
5059 13:08:39.311619 RD_PRE = 0x0
5060 13:08:39.314856 WR_PRE = 0x1
5061 13:08:39.314933 WR_PST = 0x0
5062 13:08:39.318130 DBI_WR = 0x0
5063 13:08:39.318208 DBI_RD = 0x0
5064 13:08:39.321729 OTF = 0x1
5065 13:08:39.324962 ===================================
5066 13:08:39.328377 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5067 13:08:39.333596 nWR fixed to 30
5068 13:08:39.337123 [ModeRegInit_LP4] CH0 RK0
5069 13:08:39.337222 [ModeRegInit_LP4] CH0 RK1
5070 13:08:39.340081 [ModeRegInit_LP4] CH1 RK0
5071 13:08:39.343553 [ModeRegInit_LP4] CH1 RK1
5072 13:08:39.343630 match AC timing 9
5073 13:08:39.349982 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5074 13:08:39.353423 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5075 13:08:39.357393 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5076 13:08:39.363442 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5077 13:08:39.366675 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5078 13:08:39.366753 ==
5079 13:08:39.369994 Dram Type= 6, Freq= 0, CH_0, rank 0
5080 13:08:39.373233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5081 13:08:39.373311 ==
5082 13:08:39.379733 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5083 13:08:39.386474 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5084 13:08:39.390155 [CA 0] Center 37 (7~68) winsize 62
5085 13:08:39.393261 [CA 1] Center 38 (8~69) winsize 62
5086 13:08:39.396557 [CA 2] Center 35 (5~66) winsize 62
5087 13:08:39.399925 [CA 3] Center 35 (4~66) winsize 63
5088 13:08:39.403233 [CA 4] Center 34 (4~64) winsize 61
5089 13:08:39.406641 [CA 5] Center 33 (3~64) winsize 62
5090 13:08:39.406718
5091 13:08:39.409585 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5092 13:08:39.409662
5093 13:08:39.413050 [CATrainingPosCal] consider 1 rank data
5094 13:08:39.416366 u2DelayCellTimex100 = 270/100 ps
5095 13:08:39.419548 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5096 13:08:39.423101 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5097 13:08:39.426211 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5098 13:08:39.429620 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5099 13:08:39.433005 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5100 13:08:39.439667 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5101 13:08:39.439745
5102 13:08:39.442867 CA PerBit enable=1, Macro0, CA PI delay=33
5103 13:08:39.442944
5104 13:08:39.446486 [CBTSetCACLKResult] CA Dly = 33
5105 13:08:39.446562 CS Dly: 7 (0~38)
5106 13:08:39.446622 ==
5107 13:08:39.449992 Dram Type= 6, Freq= 0, CH_0, rank 1
5108 13:08:39.453633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 13:08:39.456300 ==
5110 13:08:39.459930 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5111 13:08:39.466461 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5112 13:08:39.469949 [CA 0] Center 38 (8~69) winsize 62
5113 13:08:39.473032 [CA 1] Center 38 (8~69) winsize 62
5114 13:08:39.476220 [CA 2] Center 36 (6~66) winsize 61
5115 13:08:39.479613 [CA 3] Center 35 (5~66) winsize 62
5116 13:08:39.482996 [CA 4] Center 34 (4~65) winsize 62
5117 13:08:39.486417 [CA 5] Center 34 (4~64) winsize 61
5118 13:08:39.486494
5119 13:08:39.489960 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5120 13:08:39.490051
5121 13:08:39.492744 [CATrainingPosCal] consider 2 rank data
5122 13:08:39.496253 u2DelayCellTimex100 = 270/100 ps
5123 13:08:39.499598 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5124 13:08:39.502860 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5125 13:08:39.506168 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5126 13:08:39.509542 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5127 13:08:39.516197 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5128 13:08:39.519441 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5129 13:08:39.519518
5130 13:08:39.522869 CA PerBit enable=1, Macro0, CA PI delay=34
5131 13:08:39.522946
5132 13:08:39.526465 [CBTSetCACLKResult] CA Dly = 34
5133 13:08:39.526542 CS Dly: 7 (0~39)
5134 13:08:39.526602
5135 13:08:39.529246 ----->DramcWriteLeveling(PI) begin...
5136 13:08:39.529324 ==
5137 13:08:39.532699 Dram Type= 6, Freq= 0, CH_0, rank 0
5138 13:08:39.539234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5139 13:08:39.539316 ==
5140 13:08:39.542943 Write leveling (Byte 0): 34 => 34
5141 13:08:39.543019 Write leveling (Byte 1): 28 => 28
5142 13:08:39.546076 DramcWriteLeveling(PI) end<-----
5143 13:08:39.546153
5144 13:08:39.549318 ==
5145 13:08:39.549395 Dram Type= 6, Freq= 0, CH_0, rank 0
5146 13:08:39.556015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5147 13:08:39.556092 ==
5148 13:08:39.559504 [Gating] SW mode calibration
5149 13:08:39.566059 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5150 13:08:39.569390 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5151 13:08:39.576198 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5152 13:08:39.579362 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 13:08:39.582700 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 13:08:39.589487 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 13:08:39.592816 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 13:08:39.595976 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 13:08:39.602778 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
5158 13:08:39.605905 0 14 28 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (1 0)
5159 13:08:39.609164 0 15 0 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5160 13:08:39.612826 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 13:08:39.619533 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 13:08:39.622664 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 13:08:39.626176 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 13:08:39.632754 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 13:08:39.636166 0 15 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5166 13:08:39.639664 0 15 28 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
5167 13:08:39.645875 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5168 13:08:39.649184 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 13:08:39.652751 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 13:08:39.659619 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 13:08:39.662548 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 13:08:39.666227 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 13:08:39.672728 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 13:08:39.675985 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5175 13:08:39.679407 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5176 13:08:39.686051 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 13:08:39.689161 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 13:08:39.692442 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 13:08:39.699464 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 13:08:39.702559 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 13:08:39.706054 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 13:08:39.712542 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 13:08:39.716044 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 13:08:39.719468 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 13:08:39.722846 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 13:08:39.729412 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 13:08:39.732517 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 13:08:39.735805 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 13:08:39.742735 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 13:08:39.746291 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 13:08:39.749525 Total UI for P1: 0, mck2ui 16
5192 13:08:39.752826 best dqsien dly found for B0: ( 1, 2, 26)
5193 13:08:39.756090 Total UI for P1: 0, mck2ui 16
5194 13:08:39.759566 best dqsien dly found for B1: ( 1, 2, 26)
5195 13:08:39.762782 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5196 13:08:39.766024 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5197 13:08:39.766100
5198 13:08:39.769753 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5199 13:08:39.772852 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5200 13:08:39.776630 [Gating] SW calibration Done
5201 13:08:39.776707 ==
5202 13:08:39.779462 Dram Type= 6, Freq= 0, CH_0, rank 0
5203 13:08:39.783237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5204 13:08:39.783314 ==
5205 13:08:39.786171 RX Vref Scan: 0
5206 13:08:39.786258
5207 13:08:39.789281 RX Vref 0 -> 0, step: 1
5208 13:08:39.789358
5209 13:08:39.789419 RX Delay -80 -> 252, step: 8
5210 13:08:39.796487 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5211 13:08:39.799764 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5212 13:08:39.803195 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5213 13:08:39.806502 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5214 13:08:39.809752 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5215 13:08:39.813288 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5216 13:08:39.819885 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5217 13:08:39.823132 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5218 13:08:39.826255 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5219 13:08:39.829754 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5220 13:08:39.833373 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5221 13:08:39.839654 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5222 13:08:39.842750 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5223 13:08:39.846119 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5224 13:08:39.849397 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5225 13:08:39.852802 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5226 13:08:39.852901 ==
5227 13:08:39.856151 Dram Type= 6, Freq= 0, CH_0, rank 0
5228 13:08:39.859664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5229 13:08:39.862739 ==
5230 13:08:39.862847 DQS Delay:
5231 13:08:39.862936 DQS0 = 0, DQS1 = 0
5232 13:08:39.865916 DQM Delay:
5233 13:08:39.866014 DQM0 = 106, DQM1 = 90
5234 13:08:39.869255 DQ Delay:
5235 13:08:39.872929 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5236 13:08:39.875848 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =115
5237 13:08:39.879451 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5238 13:08:39.882683 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5239 13:08:39.882805
5240 13:08:39.882867
5241 13:08:39.882939 ==
5242 13:08:39.886228 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 13:08:39.889684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 13:08:39.889762 ==
5245 13:08:39.889822
5246 13:08:39.889877
5247 13:08:39.892888 TX Vref Scan disable
5248 13:08:39.893005 == TX Byte 0 ==
5249 13:08:39.899430 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5250 13:08:39.902615 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5251 13:08:39.902732 == TX Byte 1 ==
5252 13:08:39.909409 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5253 13:08:39.912632 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5254 13:08:39.912736 ==
5255 13:08:39.916156 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 13:08:39.919457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 13:08:39.919554 ==
5258 13:08:39.919718
5259 13:08:39.922793
5260 13:08:39.922862 TX Vref Scan disable
5261 13:08:39.926121 == TX Byte 0 ==
5262 13:08:39.929191 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5263 13:08:39.933061 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5264 13:08:39.935779 == TX Byte 1 ==
5265 13:08:39.939160 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5266 13:08:39.943027 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5267 13:08:39.945785
5268 13:08:39.945887 [DATLAT]
5269 13:08:39.945977 Freq=933, CH0 RK0
5270 13:08:39.946060
5271 13:08:39.949235 DATLAT Default: 0xd
5272 13:08:39.949347 0, 0xFFFF, sum = 0
5273 13:08:39.952476 1, 0xFFFF, sum = 0
5274 13:08:39.952574 2, 0xFFFF, sum = 0
5275 13:08:39.955768 3, 0xFFFF, sum = 0
5276 13:08:39.955868 4, 0xFFFF, sum = 0
5277 13:08:39.959381 5, 0xFFFF, sum = 0
5278 13:08:39.962641 6, 0xFFFF, sum = 0
5279 13:08:39.962720 7, 0xFFFF, sum = 0
5280 13:08:39.965816 8, 0xFFFF, sum = 0
5281 13:08:39.965895 9, 0xFFFF, sum = 0
5282 13:08:39.969174 10, 0x0, sum = 1
5283 13:08:39.969274 11, 0x0, sum = 2
5284 13:08:39.969337 12, 0x0, sum = 3
5285 13:08:39.972560 13, 0x0, sum = 4
5286 13:08:39.972639 best_step = 11
5287 13:08:39.972700
5288 13:08:39.975778 ==
5289 13:08:39.975880 Dram Type= 6, Freq= 0, CH_0, rank 0
5290 13:08:39.982355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 13:08:39.982435 ==
5292 13:08:39.982497 RX Vref Scan: 1
5293 13:08:39.982554
5294 13:08:39.985956 RX Vref 0 -> 0, step: 1
5295 13:08:39.986034
5296 13:08:39.989163 RX Delay -53 -> 252, step: 4
5297 13:08:39.989242
5298 13:08:39.992626 Set Vref, RX VrefLevel [Byte0]: 54
5299 13:08:39.995891 [Byte1]: 49
5300 13:08:39.995968
5301 13:08:39.999107 Final RX Vref Byte 0 = 54 to rank0
5302 13:08:40.002778 Final RX Vref Byte 1 = 49 to rank0
5303 13:08:40.005814 Final RX Vref Byte 0 = 54 to rank1
5304 13:08:40.009365 Final RX Vref Byte 1 = 49 to rank1==
5305 13:08:40.012779 Dram Type= 6, Freq= 0, CH_0, rank 0
5306 13:08:40.016060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 13:08:40.016162 ==
5308 13:08:40.019433 DQS Delay:
5309 13:08:40.019511 DQS0 = 0, DQS1 = 0
5310 13:08:40.022603 DQM Delay:
5311 13:08:40.022680 DQM0 = 107, DQM1 = 91
5312 13:08:40.022739 DQ Delay:
5313 13:08:40.026302 DQ0 =106, DQ1 =108, DQ2 =104, DQ3 =104
5314 13:08:40.029461 DQ4 =108, DQ5 =98, DQ6 =116, DQ7 =116
5315 13:08:40.032906 DQ8 =84, DQ9 =76, DQ10 =92, DQ11 =90
5316 13:08:40.036387 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =100
5317 13:08:40.039600
5318 13:08:40.039756
5319 13:08:40.046337 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
5320 13:08:40.049870 CH0 RK0: MR19=505, MR18=2521
5321 13:08:40.056378 CH0_RK0: MR19=0x505, MR18=0x2521, DQSOSC=410, MR23=63, INC=64, DEC=42
5322 13:08:40.056590
5323 13:08:40.059211 ----->DramcWriteLeveling(PI) begin...
5324 13:08:40.059307 ==
5325 13:08:40.062666 Dram Type= 6, Freq= 0, CH_0, rank 1
5326 13:08:40.066222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 13:08:40.066303 ==
5328 13:08:40.069199 Write leveling (Byte 0): 32 => 32
5329 13:08:40.072837 Write leveling (Byte 1): 27 => 27
5330 13:08:40.076421 DramcWriteLeveling(PI) end<-----
5331 13:08:40.076497
5332 13:08:40.076557 ==
5333 13:08:40.079370 Dram Type= 6, Freq= 0, CH_0, rank 1
5334 13:08:40.082608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5335 13:08:40.082713 ==
5336 13:08:40.085847 [Gating] SW mode calibration
5337 13:08:40.092643 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5338 13:08:40.099315 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5339 13:08:40.103361 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5340 13:08:40.105966 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 13:08:40.113008 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 13:08:40.116148 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 13:08:40.119422 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 13:08:40.126021 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 13:08:40.129660 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5346 13:08:40.132973 0 14 28 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (1 0)
5347 13:08:40.139623 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5348 13:08:40.142581 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5349 13:08:40.146008 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 13:08:40.153120 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 13:08:40.156191 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 13:08:40.159422 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 13:08:40.166068 0 15 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5354 13:08:40.169521 0 15 28 | B1->B0 | 3c3c 4343 | 1 0 | (0 0) (1 1)
5355 13:08:40.173058 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 13:08:40.179242 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 13:08:40.182203 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 13:08:40.185338 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 13:08:40.192499 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 13:08:40.195519 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 13:08:40.198993 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5362 13:08:40.205411 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5363 13:08:40.208664 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5364 13:08:40.211906 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 13:08:40.215199 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 13:08:40.222014 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 13:08:40.225353 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 13:08:40.228393 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 13:08:40.235382 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 13:08:40.238570 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 13:08:40.242184 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 13:08:40.248428 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 13:08:40.251716 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 13:08:40.255269 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 13:08:40.261618 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 13:08:40.265101 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 13:08:40.268107 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5378 13:08:40.274981 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5379 13:08:40.278175 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5380 13:08:40.281577 Total UI for P1: 0, mck2ui 16
5381 13:08:40.284965 best dqsien dly found for B1: ( 1, 2, 28)
5382 13:08:40.288450 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 13:08:40.291724 Total UI for P1: 0, mck2ui 16
5384 13:08:40.294883 best dqsien dly found for B0: ( 1, 2, 28)
5385 13:08:40.298328 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5386 13:08:40.301858 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5387 13:08:40.301934
5388 13:08:40.308560 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5389 13:08:40.311501 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5390 13:08:40.311605 [Gating] SW calibration Done
5391 13:08:40.315014 ==
5392 13:08:40.318567 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 13:08:40.321474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 13:08:40.321551 ==
5395 13:08:40.321610 RX Vref Scan: 0
5396 13:08:40.321665
5397 13:08:40.324933 RX Vref 0 -> 0, step: 1
5398 13:08:40.325008
5399 13:08:40.328385 RX Delay -80 -> 252, step: 8
5400 13:08:40.331998 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5401 13:08:40.335171 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5402 13:08:40.338753 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5403 13:08:40.341784 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5404 13:08:40.348669 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5405 13:08:40.351695 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5406 13:08:40.355254 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5407 13:08:40.358011 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5408 13:08:40.361572 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5409 13:08:40.368249 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5410 13:08:40.371801 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5411 13:08:40.374768 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5412 13:08:40.378262 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5413 13:08:40.382135 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5414 13:08:40.384926 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5415 13:08:40.391578 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5416 13:08:40.391678 ==
5417 13:08:40.394741 Dram Type= 6, Freq= 0, CH_0, rank 1
5418 13:08:40.398497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5419 13:08:40.398598 ==
5420 13:08:40.398685 DQS Delay:
5421 13:08:40.401381 DQS0 = 0, DQS1 = 0
5422 13:08:40.401462 DQM Delay:
5423 13:08:40.405133 DQM0 = 104, DQM1 = 90
5424 13:08:40.405216 DQ Delay:
5425 13:08:40.408220 DQ0 =99, DQ1 =107, DQ2 =99, DQ3 =99
5426 13:08:40.411343 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5427 13:08:40.414955 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5428 13:08:40.418004 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5429 13:08:40.418108
5430 13:08:40.418192
5431 13:08:40.418307 ==
5432 13:08:40.421423 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 13:08:40.425139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 13:08:40.428018 ==
5435 13:08:40.428143
5436 13:08:40.428239
5437 13:08:40.428328 TX Vref Scan disable
5438 13:08:40.431442 == TX Byte 0 ==
5439 13:08:40.434976 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5440 13:08:40.438789 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5441 13:08:40.441345 == TX Byte 1 ==
5442 13:08:40.445185 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5443 13:08:40.448431 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5444 13:08:40.451521 ==
5445 13:08:40.451798 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 13:08:40.458228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 13:08:40.458592 ==
5448 13:08:40.458873
5449 13:08:40.459128
5450 13:08:40.461813 TX Vref Scan disable
5451 13:08:40.462244 == TX Byte 0 ==
5452 13:08:40.468453 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5453 13:08:40.471611 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5454 13:08:40.472151 == TX Byte 1 ==
5455 13:08:40.478384 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5456 13:08:40.481607 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5457 13:08:40.482042
5458 13:08:40.482380 [DATLAT]
5459 13:08:40.484730 Freq=933, CH0 RK1
5460 13:08:40.485234
5461 13:08:40.485587 DATLAT Default: 0xb
5462 13:08:40.488470 0, 0xFFFF, sum = 0
5463 13:08:40.488909 1, 0xFFFF, sum = 0
5464 13:08:40.491315 2, 0xFFFF, sum = 0
5465 13:08:40.491911 3, 0xFFFF, sum = 0
5466 13:08:40.495077 4, 0xFFFF, sum = 0
5467 13:08:40.495666 5, 0xFFFF, sum = 0
5468 13:08:40.498312 6, 0xFFFF, sum = 0
5469 13:08:40.498758 7, 0xFFFF, sum = 0
5470 13:08:40.501474 8, 0xFFFF, sum = 0
5471 13:08:40.501909 9, 0xFFFF, sum = 0
5472 13:08:40.504810 10, 0x0, sum = 1
5473 13:08:40.505297 11, 0x0, sum = 2
5474 13:08:40.508171 12, 0x0, sum = 3
5475 13:08:40.508607 13, 0x0, sum = 4
5476 13:08:40.511975 best_step = 11
5477 13:08:40.512403
5478 13:08:40.512737 ==
5479 13:08:40.515233 Dram Type= 6, Freq= 0, CH_0, rank 1
5480 13:08:40.518338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5481 13:08:40.518772 ==
5482 13:08:40.521749 RX Vref Scan: 0
5483 13:08:40.522305
5484 13:08:40.522862 RX Vref 0 -> 0, step: 1
5485 13:08:40.523408
5486 13:08:40.524825 RX Delay -53 -> 252, step: 4
5487 13:08:40.531619 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5488 13:08:40.535342 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5489 13:08:40.538552 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5490 13:08:40.542166 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5491 13:08:40.545363 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5492 13:08:40.551982 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5493 13:08:40.554890 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5494 13:08:40.558648 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5495 13:08:40.562060 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5496 13:08:40.564984 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5497 13:08:40.569036 iDelay=199, Bit 10, Center 92 (7 ~ 178) 172
5498 13:08:40.575229 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5499 13:08:40.578626 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5500 13:08:40.581631 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5501 13:08:40.585330 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5502 13:08:40.588573 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5503 13:08:40.591720 ==
5504 13:08:40.592148 Dram Type= 6, Freq= 0, CH_0, rank 1
5505 13:08:40.598467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 13:08:40.598903 ==
5507 13:08:40.599259 DQS Delay:
5508 13:08:40.602377 DQS0 = 0, DQS1 = 0
5509 13:08:40.602936 DQM Delay:
5510 13:08:40.604920 DQM0 = 104, DQM1 = 91
5511 13:08:40.605393 DQ Delay:
5512 13:08:40.608314 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =100
5513 13:08:40.611760 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =112
5514 13:08:40.615331 DQ8 =84, DQ9 =80, DQ10 =92, DQ11 =90
5515 13:08:40.618926 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5516 13:08:40.619358
5517 13:08:40.619692
5518 13:08:40.625186 [DQSOSCAuto] RK1, (LSB)MR18= 0x3111, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 406 ps
5519 13:08:40.628214 CH0 RK1: MR19=505, MR18=3111
5520 13:08:40.635342 CH0_RK1: MR19=0x505, MR18=0x3111, DQSOSC=406, MR23=63, INC=65, DEC=43
5521 13:08:40.638061 [RxdqsGatingPostProcess] freq 933
5522 13:08:40.644926 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5523 13:08:40.648643 best DQS0 dly(2T, 0.5T) = (0, 10)
5524 13:08:40.651617 best DQS1 dly(2T, 0.5T) = (0, 10)
5525 13:08:40.655361 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5526 13:08:40.655804 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5527 13:08:40.658368 best DQS0 dly(2T, 0.5T) = (0, 10)
5528 13:08:40.661487 best DQS1 dly(2T, 0.5T) = (0, 10)
5529 13:08:40.664409 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5530 13:08:40.667785 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5531 13:08:40.671251 Pre-setting of DQS Precalculation
5532 13:08:40.678004 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5533 13:08:40.678085 ==
5534 13:08:40.681323 Dram Type= 6, Freq= 0, CH_1, rank 0
5535 13:08:40.684288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5536 13:08:40.684364 ==
5537 13:08:40.691116 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5538 13:08:40.694450 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5539 13:08:40.698985 [CA 0] Center 37 (7~68) winsize 62
5540 13:08:40.701891 [CA 1] Center 38 (7~69) winsize 63
5541 13:08:40.705534 [CA 2] Center 36 (6~66) winsize 61
5542 13:08:40.708645 [CA 3] Center 35 (5~65) winsize 61
5543 13:08:40.712292 [CA 4] Center 35 (5~66) winsize 62
5544 13:08:40.715403 [CA 5] Center 34 (4~65) winsize 62
5545 13:08:40.715484
5546 13:08:40.719044 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5547 13:08:40.719121
5548 13:08:40.722052 [CATrainingPosCal] consider 1 rank data
5549 13:08:40.725308 u2DelayCellTimex100 = 270/100 ps
5550 13:08:40.728640 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5551 13:08:40.735240 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5552 13:08:40.738342 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5553 13:08:40.742029 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5554 13:08:40.745352 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5555 13:08:40.748400 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5556 13:08:40.748500
5557 13:08:40.751919 CA PerBit enable=1, Macro0, CA PI delay=34
5558 13:08:40.751997
5559 13:08:40.755142 [CBTSetCACLKResult] CA Dly = 34
5560 13:08:40.755220 CS Dly: 6 (0~37)
5561 13:08:40.758239 ==
5562 13:08:40.761612 Dram Type= 6, Freq= 0, CH_1, rank 1
5563 13:08:40.765060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5564 13:08:40.765164 ==
5565 13:08:40.768721 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5566 13:08:40.774878 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5567 13:08:40.778750 [CA 0] Center 37 (7~68) winsize 62
5568 13:08:40.782081 [CA 1] Center 38 (7~69) winsize 63
5569 13:08:40.785495 [CA 2] Center 36 (6~67) winsize 62
5570 13:08:40.788780 [CA 3] Center 35 (5~66) winsize 62
5571 13:08:40.792291 [CA 4] Center 35 (5~66) winsize 62
5572 13:08:40.795272 [CA 5] Center 35 (5~65) winsize 61
5573 13:08:40.795371
5574 13:08:40.798445 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5575 13:08:40.798521
5576 13:08:40.802329 [CATrainingPosCal] consider 2 rank data
5577 13:08:40.805441 u2DelayCellTimex100 = 270/100 ps
5578 13:08:40.808606 CA0 delay=37 (7~68),Diff = 2 PI (12 cell)
5579 13:08:40.812209 CA1 delay=38 (7~69),Diff = 3 PI (18 cell)
5580 13:08:40.818560 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5581 13:08:40.822425 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5582 13:08:40.825857 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
5583 13:08:40.828813 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5584 13:08:40.828906
5585 13:08:40.832028 CA PerBit enable=1, Macro0, CA PI delay=35
5586 13:08:40.832117
5587 13:08:40.835378 [CBTSetCACLKResult] CA Dly = 35
5588 13:08:40.835467 CS Dly: 7 (0~39)
5589 13:08:40.835547
5590 13:08:40.838460 ----->DramcWriteLeveling(PI) begin...
5591 13:08:40.842127 ==
5592 13:08:40.845031 Dram Type= 6, Freq= 0, CH_1, rank 0
5593 13:08:40.848907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5594 13:08:40.849004 ==
5595 13:08:40.851982 Write leveling (Byte 0): 23 => 23
5596 13:08:40.855309 Write leveling (Byte 1): 29 => 29
5597 13:08:40.858474 DramcWriteLeveling(PI) end<-----
5598 13:08:40.858596
5599 13:08:40.858668 ==
5600 13:08:40.862016 Dram Type= 6, Freq= 0, CH_1, rank 0
5601 13:08:40.865122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 13:08:40.865211 ==
5603 13:08:40.868727 [Gating] SW mode calibration
5604 13:08:40.875438 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5605 13:08:40.878571 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5606 13:08:40.885294 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 13:08:40.888444 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 13:08:40.891841 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 13:08:40.898790 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 13:08:40.901916 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 13:08:40.905429 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 13:08:40.911737 0 14 24 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (1 1)
5613 13:08:40.915293 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
5614 13:08:40.918322 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 13:08:40.925240 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 13:08:40.928323 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 13:08:40.931834 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 13:08:40.938195 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 13:08:40.941950 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 13:08:40.945077 0 15 24 | B1->B0 | 2626 2d2d | 0 0 | (0 0) (0 0)
5621 13:08:40.951658 0 15 28 | B1->B0 | 3e3e 3f3f | 0 0 | (0 0) (0 0)
5622 13:08:40.955617 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 13:08:40.958257 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 13:08:40.964982 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 13:08:40.968131 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 13:08:40.971393 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 13:08:40.978531 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 13:08:40.981515 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5629 13:08:40.984680 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 13:08:40.991529 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 13:08:40.994911 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 13:08:40.997962 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 13:08:41.004689 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 13:08:41.008161 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 13:08:41.011408 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 13:08:41.018074 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 13:08:41.021042 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 13:08:41.024478 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 13:08:41.031327 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 13:08:41.034749 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 13:08:41.038154 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 13:08:41.040877 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 13:08:41.047869 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5644 13:08:41.051418 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5645 13:08:41.054509 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 13:08:41.057944 Total UI for P1: 0, mck2ui 16
5647 13:08:41.061012 best dqsien dly found for B0: ( 1, 2, 22)
5648 13:08:41.064547 Total UI for P1: 0, mck2ui 16
5649 13:08:41.067814 best dqsien dly found for B1: ( 1, 2, 26)
5650 13:08:41.071097 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5651 13:08:41.074685 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5652 13:08:41.074775
5653 13:08:41.081181 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5654 13:08:41.084425 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5655 13:08:41.088136 [Gating] SW calibration Done
5656 13:08:41.088234 ==
5657 13:08:41.090992 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 13:08:41.094491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 13:08:41.094569 ==
5660 13:08:41.094629 RX Vref Scan: 0
5661 13:08:41.094684
5662 13:08:41.097903 RX Vref 0 -> 0, step: 1
5663 13:08:41.097990
5664 13:08:41.101308 RX Delay -80 -> 252, step: 8
5665 13:08:41.104585 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5666 13:08:41.107962 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5667 13:08:41.111131 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5668 13:08:41.118211 iDelay=208, Bit 3, Center 107 (24 ~ 191) 168
5669 13:08:41.121156 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5670 13:08:41.125304 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5671 13:08:41.127950 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5672 13:08:41.131417 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5673 13:08:41.134803 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5674 13:08:41.141536 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5675 13:08:41.144871 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5676 13:08:41.148051 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5677 13:08:41.151765 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5678 13:08:41.154962 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5679 13:08:41.158191 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5680 13:08:41.164788 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5681 13:08:41.164865 ==
5682 13:08:41.168504 Dram Type= 6, Freq= 0, CH_1, rank 0
5683 13:08:41.172255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5684 13:08:41.172332 ==
5685 13:08:41.172391 DQS Delay:
5686 13:08:41.174878 DQS0 = 0, DQS1 = 0
5687 13:08:41.174954 DQM Delay:
5688 13:08:41.178195 DQM0 = 103, DQM1 = 95
5689 13:08:41.178271 DQ Delay:
5690 13:08:41.181760 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =107
5691 13:08:41.184853 DQ4 =99, DQ5 =111, DQ6 =115, DQ7 =99
5692 13:08:41.188388 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5693 13:08:41.191297 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =103
5694 13:08:41.191373
5695 13:08:41.191432
5696 13:08:41.191486 ==
5697 13:08:41.194731 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 13:08:41.197923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 13:08:41.201285 ==
5700 13:08:41.201360
5701 13:08:41.201418
5702 13:08:41.201473 TX Vref Scan disable
5703 13:08:41.204699 == TX Byte 0 ==
5704 13:08:41.208382 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5705 13:08:41.211521 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5706 13:08:41.214594 == TX Byte 1 ==
5707 13:08:41.218063 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5708 13:08:41.221241 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5709 13:08:41.224449 ==
5710 13:08:41.228013 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 13:08:41.231314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 13:08:41.231397 ==
5713 13:08:41.231459
5714 13:08:41.231514
5715 13:08:41.234458 TX Vref Scan disable
5716 13:08:41.234535 == TX Byte 0 ==
5717 13:08:41.240926 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5718 13:08:41.244222 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5719 13:08:41.244298 == TX Byte 1 ==
5720 13:08:41.251505 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5721 13:08:41.254539 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5722 13:08:41.254615
5723 13:08:41.254674 [DATLAT]
5724 13:08:41.258019 Freq=933, CH1 RK0
5725 13:08:41.258095
5726 13:08:41.258155 DATLAT Default: 0xd
5727 13:08:41.261039 0, 0xFFFF, sum = 0
5728 13:08:41.261116 1, 0xFFFF, sum = 0
5729 13:08:41.264831 2, 0xFFFF, sum = 0
5730 13:08:41.264908 3, 0xFFFF, sum = 0
5731 13:08:41.268011 4, 0xFFFF, sum = 0
5732 13:08:41.268093 5, 0xFFFF, sum = 0
5733 13:08:41.271214 6, 0xFFFF, sum = 0
5734 13:08:41.271291 7, 0xFFFF, sum = 0
5735 13:08:41.274293 8, 0xFFFF, sum = 0
5736 13:08:41.274370 9, 0xFFFF, sum = 0
5737 13:08:41.277960 10, 0x0, sum = 1
5738 13:08:41.278037 11, 0x0, sum = 2
5739 13:08:41.281019 12, 0x0, sum = 3
5740 13:08:41.281098 13, 0x0, sum = 4
5741 13:08:41.284855 best_step = 11
5742 13:08:41.284930
5743 13:08:41.284990 ==
5744 13:08:41.287862 Dram Type= 6, Freq= 0, CH_1, rank 0
5745 13:08:41.291428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 13:08:41.291498 ==
5747 13:08:41.294914 RX Vref Scan: 1
5748 13:08:41.294977
5749 13:08:41.295031 RX Vref 0 -> 0, step: 1
5750 13:08:41.295084
5751 13:08:41.297724 RX Delay -53 -> 252, step: 4
5752 13:08:41.297800
5753 13:08:41.301110 Set Vref, RX VrefLevel [Byte0]: 49
5754 13:08:41.304131 [Byte1]: 53
5755 13:08:41.308523
5756 13:08:41.308605 Final RX Vref Byte 0 = 49 to rank0
5757 13:08:41.311885 Final RX Vref Byte 1 = 53 to rank0
5758 13:08:41.314886 Final RX Vref Byte 0 = 49 to rank1
5759 13:08:41.318640 Final RX Vref Byte 1 = 53 to rank1==
5760 13:08:41.321722 Dram Type= 6, Freq= 0, CH_1, rank 0
5761 13:08:41.328499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 13:08:41.328576 ==
5763 13:08:41.328636 DQS Delay:
5764 13:08:41.328691 DQS0 = 0, DQS1 = 0
5765 13:08:41.331721 DQM Delay:
5766 13:08:41.331797 DQM0 = 104, DQM1 = 96
5767 13:08:41.334892 DQ Delay:
5768 13:08:41.337985 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5769 13:08:41.341864 DQ4 =102, DQ5 =112, DQ6 =116, DQ7 =100
5770 13:08:41.345001 DQ8 =86, DQ9 =84, DQ10 =98, DQ11 =90
5771 13:08:41.348148 DQ12 =106, DQ13 =104, DQ14 =102, DQ15 =100
5772 13:08:41.348224
5773 13:08:41.348283
5774 13:08:41.355223 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e36, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 412 ps
5775 13:08:41.358276 CH1 RK0: MR19=505, MR18=1E36
5776 13:08:41.364722 CH1_RK0: MR19=0x505, MR18=0x1E36, DQSOSC=404, MR23=63, INC=66, DEC=44
5777 13:08:41.364822
5778 13:08:41.367843 ----->DramcWriteLeveling(PI) begin...
5779 13:08:41.367930 ==
5780 13:08:41.371459 Dram Type= 6, Freq= 0, CH_1, rank 1
5781 13:08:41.374481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 13:08:41.374554 ==
5783 13:08:41.378212 Write leveling (Byte 0): 27 => 27
5784 13:08:41.381493 Write leveling (Byte 1): 29 => 29
5785 13:08:41.384818 DramcWriteLeveling(PI) end<-----
5786 13:08:41.384897
5787 13:08:41.384956 ==
5788 13:08:41.388087 Dram Type= 6, Freq= 0, CH_1, rank 1
5789 13:08:41.391330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5790 13:08:41.394666 ==
5791 13:08:41.394776 [Gating] SW mode calibration
5792 13:08:41.404776 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5793 13:08:41.407711 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5794 13:08:41.411266 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5795 13:08:41.417846 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5796 13:08:41.421067 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 13:08:41.424396 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 13:08:41.431609 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 13:08:41.434592 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 13:08:41.438176 0 14 24 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
5801 13:08:41.444583 0 14 28 | B1->B0 | 2525 2d2d | 0 0 | (0 0) (0 0)
5802 13:08:41.447995 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5803 13:08:41.451544 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 13:08:41.458410 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 13:08:41.461480 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 13:08:41.464639 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 13:08:41.471692 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 13:08:41.474821 0 15 24 | B1->B0 | 2c2c 2929 | 0 0 | (0 0) (0 0)
5809 13:08:41.477912 0 15 28 | B1->B0 | 4040 3838 | 0 1 | (0 0) (0 0)
5810 13:08:41.481549 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5811 13:08:41.487923 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 13:08:41.491137 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 13:08:41.495307 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 13:08:41.501474 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 13:08:41.504885 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 13:08:41.507969 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 13:08:41.515005 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5818 13:08:41.518017 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 13:08:41.521041 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 13:08:41.528086 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 13:08:41.531218 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 13:08:41.534603 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 13:08:41.540906 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 13:08:41.544608 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 13:08:41.547671 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 13:08:41.554546 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 13:08:41.557586 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 13:08:41.561392 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 13:08:41.567990 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 13:08:41.571057 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 13:08:41.574455 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 13:08:41.581047 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 13:08:41.584684 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 13:08:41.587643 Total UI for P1: 0, mck2ui 16
5835 13:08:41.591246 best dqsien dly found for B0: ( 1, 2, 26)
5836 13:08:41.594658 Total UI for P1: 0, mck2ui 16
5837 13:08:41.597764 best dqsien dly found for B1: ( 1, 2, 26)
5838 13:08:41.601015 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5839 13:08:41.604310 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5840 13:08:41.604406
5841 13:08:41.607851 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5842 13:08:41.611106 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5843 13:08:41.614264 [Gating] SW calibration Done
5844 13:08:41.614338 ==
5845 13:08:41.617897 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 13:08:41.621460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 13:08:41.621553 ==
5848 13:08:41.624645 RX Vref Scan: 0
5849 13:08:41.624738
5850 13:08:41.624822 RX Vref 0 -> 0, step: 1
5851 13:08:41.627969
5852 13:08:41.628059 RX Delay -80 -> 252, step: 8
5853 13:08:41.634327 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5854 13:08:41.637518 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5855 13:08:41.640820 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5856 13:08:41.644666 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5857 13:08:41.647832 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5858 13:08:41.651346 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5859 13:08:41.657397 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5860 13:08:41.661050 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5861 13:08:41.664512 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5862 13:08:41.667398 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5863 13:08:41.670704 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5864 13:08:41.674370 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5865 13:08:41.680635 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5866 13:08:41.683904 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5867 13:08:41.687578 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5868 13:08:41.690911 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5869 13:08:41.690988 ==
5870 13:08:41.694081 Dram Type= 6, Freq= 0, CH_1, rank 1
5871 13:08:41.700507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5872 13:08:41.700578 ==
5873 13:08:41.700637 DQS Delay:
5874 13:08:41.700692 DQS0 = 0, DQS1 = 0
5875 13:08:41.704333 DQM Delay:
5876 13:08:41.704394 DQM0 = 101, DQM1 = 95
5877 13:08:41.707405 DQ Delay:
5878 13:08:41.710658 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5879 13:08:41.714018 DQ4 =103, DQ5 =111, DQ6 =107, DQ7 =99
5880 13:08:41.717565 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5881 13:08:41.720907 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5882 13:08:41.721008
5883 13:08:41.721094
5884 13:08:41.721170 ==
5885 13:08:41.724182 Dram Type= 6, Freq= 0, CH_1, rank 1
5886 13:08:41.727431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5887 13:08:41.727521 ==
5888 13:08:41.727602
5889 13:08:41.727679
5890 13:08:41.730483 TX Vref Scan disable
5891 13:08:41.734355 == TX Byte 0 ==
5892 13:08:41.737493 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5893 13:08:41.740475 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5894 13:08:41.744001 == TX Byte 1 ==
5895 13:08:41.747478 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5896 13:08:41.750878 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5897 13:08:41.750976 ==
5898 13:08:41.754238 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 13:08:41.757280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 13:08:41.757361 ==
5901 13:08:41.760874
5902 13:08:41.760949
5903 13:08:41.761007 TX Vref Scan disable
5904 13:08:41.763819 == TX Byte 0 ==
5905 13:08:41.767172 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5906 13:08:41.770578 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5907 13:08:41.773792 == TX Byte 1 ==
5908 13:08:41.777248 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5909 13:08:41.780616 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5910 13:08:41.783882
5911 13:08:41.783979 [DATLAT]
5912 13:08:41.784063 Freq=933, CH1 RK1
5913 13:08:41.784148
5914 13:08:41.787145 DATLAT Default: 0xb
5915 13:08:41.787213 0, 0xFFFF, sum = 0
5916 13:08:41.790665 1, 0xFFFF, sum = 0
5917 13:08:41.790735 2, 0xFFFF, sum = 0
5918 13:08:41.794269 3, 0xFFFF, sum = 0
5919 13:08:41.794334 4, 0xFFFF, sum = 0
5920 13:08:41.797055 5, 0xFFFF, sum = 0
5921 13:08:41.800401 6, 0xFFFF, sum = 0
5922 13:08:41.800494 7, 0xFFFF, sum = 0
5923 13:08:41.803873 8, 0xFFFF, sum = 0
5924 13:08:41.803973 9, 0xFFFF, sum = 0
5925 13:08:41.807032 10, 0x0, sum = 1
5926 13:08:41.807127 11, 0x0, sum = 2
5927 13:08:41.807216 12, 0x0, sum = 3
5928 13:08:41.810354 13, 0x0, sum = 4
5929 13:08:41.810450 best_step = 11
5930 13:08:41.810532
5931 13:08:41.813718 ==
5932 13:08:41.813809 Dram Type= 6, Freq= 0, CH_1, rank 1
5933 13:08:41.820387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5934 13:08:41.820456 ==
5935 13:08:41.820521 RX Vref Scan: 0
5936 13:08:41.820602
5937 13:08:41.824040 RX Vref 0 -> 0, step: 1
5938 13:08:41.824127
5939 13:08:41.826937 RX Delay -53 -> 252, step: 4
5940 13:08:41.830281 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5941 13:08:41.837024 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5942 13:08:41.840436 iDelay=199, Bit 2, Center 96 (19 ~ 174) 156
5943 13:08:41.843601 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5944 13:08:41.846993 iDelay=199, Bit 4, Center 106 (27 ~ 186) 160
5945 13:08:41.850294 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5946 13:08:41.856861 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5947 13:08:41.860385 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5948 13:08:41.863412 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5949 13:08:41.866906 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5950 13:08:41.870484 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5951 13:08:41.873375 iDelay=199, Bit 11, Center 90 (3 ~ 178) 176
5952 13:08:41.880536 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5953 13:08:41.883639 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5954 13:08:41.887009 iDelay=199, Bit 14, Center 104 (15 ~ 194) 180
5955 13:08:41.890513 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5956 13:08:41.890606 ==
5957 13:08:41.893527 Dram Type= 6, Freq= 0, CH_1, rank 1
5958 13:08:41.900023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5959 13:08:41.900099 ==
5960 13:08:41.900184 DQS Delay:
5961 13:08:41.903680 DQS0 = 0, DQS1 = 0
5962 13:08:41.903784 DQM Delay:
5963 13:08:41.903868 DQM0 = 105, DQM1 = 97
5964 13:08:41.906966 DQ Delay:
5965 13:08:41.910014 DQ0 =110, DQ1 =98, DQ2 =96, DQ3 =102
5966 13:08:41.913553 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
5967 13:08:41.916689 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =90
5968 13:08:41.920148 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =106
5969 13:08:41.920217
5970 13:08:41.920274
5971 13:08:41.927223 [DQSOSCAuto] RK1, (LSB)MR18= 0x2906, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5972 13:08:41.929981 CH1 RK1: MR19=505, MR18=2906
5973 13:08:41.936906 CH1_RK1: MR19=0x505, MR18=0x2906, DQSOSC=408, MR23=63, INC=65, DEC=43
5974 13:08:41.940012 [RxdqsGatingPostProcess] freq 933
5975 13:08:41.946963 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5976 13:08:41.949935 best DQS0 dly(2T, 0.5T) = (0, 10)
5977 13:08:41.950012 best DQS1 dly(2T, 0.5T) = (0, 10)
5978 13:08:41.953247 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5979 13:08:41.956540 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5980 13:08:41.959885 best DQS0 dly(2T, 0.5T) = (0, 10)
5981 13:08:41.963147 best DQS1 dly(2T, 0.5T) = (0, 10)
5982 13:08:41.966446 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5983 13:08:41.969723 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5984 13:08:41.973153 Pre-setting of DQS Precalculation
5985 13:08:41.979732 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5986 13:08:41.986459 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5987 13:08:41.992768 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5988 13:08:41.992866
5989 13:08:41.992957
5990 13:08:41.996184 [Calibration Summary] 1866 Mbps
5991 13:08:41.996252 CH 0, Rank 0
5992 13:08:41.999591 SW Impedance : PASS
5993 13:08:42.002819 DUTY Scan : NO K
5994 13:08:42.002911 ZQ Calibration : PASS
5995 13:08:42.006462 Jitter Meter : NO K
5996 13:08:42.009644 CBT Training : PASS
5997 13:08:42.009719 Write leveling : PASS
5998 13:08:42.013095 RX DQS gating : PASS
5999 13:08:42.013184 RX DQ/DQS(RDDQC) : PASS
6000 13:08:42.016231 TX DQ/DQS : PASS
6001 13:08:42.019575 RX DATLAT : PASS
6002 13:08:42.019675 RX DQ/DQS(Engine): PASS
6003 13:08:42.023169 TX OE : NO K
6004 13:08:42.023266 All Pass.
6005 13:08:42.023359
6006 13:08:42.026603 CH 0, Rank 1
6007 13:08:42.026696 SW Impedance : PASS
6008 13:08:42.030166 DUTY Scan : NO K
6009 13:08:42.033468 ZQ Calibration : PASS
6010 13:08:42.033557 Jitter Meter : NO K
6011 13:08:42.036368 CBT Training : PASS
6012 13:08:42.039569 Write leveling : PASS
6013 13:08:42.039665 RX DQS gating : PASS
6014 13:08:42.043034 RX DQ/DQS(RDDQC) : PASS
6015 13:08:42.046168 TX DQ/DQS : PASS
6016 13:08:42.046265 RX DATLAT : PASS
6017 13:08:42.049558 RX DQ/DQS(Engine): PASS
6018 13:08:42.053290 TX OE : NO K
6019 13:08:42.053383 All Pass.
6020 13:08:42.053445
6021 13:08:42.053499 CH 1, Rank 0
6022 13:08:42.056287 SW Impedance : PASS
6023 13:08:42.059622 DUTY Scan : NO K
6024 13:08:42.059721 ZQ Calibration : PASS
6025 13:08:42.062733 Jitter Meter : NO K
6026 13:08:42.062832 CBT Training : PASS
6027 13:08:42.066459 Write leveling : PASS
6028 13:08:42.069298 RX DQS gating : PASS
6029 13:08:42.069378 RX DQ/DQS(RDDQC) : PASS
6030 13:08:42.072769 TX DQ/DQS : PASS
6031 13:08:42.076496 RX DATLAT : PASS
6032 13:08:42.076572 RX DQ/DQS(Engine): PASS
6033 13:08:42.079753 TX OE : NO K
6034 13:08:42.079819 All Pass.
6035 13:08:42.079876
6036 13:08:42.082812 CH 1, Rank 1
6037 13:08:42.082887 SW Impedance : PASS
6038 13:08:42.086066 DUTY Scan : NO K
6039 13:08:42.089561 ZQ Calibration : PASS
6040 13:08:42.089638 Jitter Meter : NO K
6041 13:08:42.092847 CBT Training : PASS
6042 13:08:42.095918 Write leveling : PASS
6043 13:08:42.095994 RX DQS gating : PASS
6044 13:08:42.099314 RX DQ/DQS(RDDQC) : PASS
6045 13:08:42.102644 TX DQ/DQS : PASS
6046 13:08:42.102744 RX DATLAT : PASS
6047 13:08:42.105869 RX DQ/DQS(Engine): PASS
6048 13:08:42.109294 TX OE : NO K
6049 13:08:42.109386 All Pass.
6050 13:08:42.109468
6051 13:08:42.109547 DramC Write-DBI off
6052 13:08:42.112607 PER_BANK_REFRESH: Hybrid Mode
6053 13:08:42.116282 TX_TRACKING: ON
6054 13:08:42.122820 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6055 13:08:42.126224 [FAST_K] Save calibration result to emmc
6056 13:08:42.132470 dramc_set_vcore_voltage set vcore to 650000
6057 13:08:42.132541 Read voltage for 400, 6
6058 13:08:42.135663 Vio18 = 0
6059 13:08:42.135727 Vcore = 650000
6060 13:08:42.135781 Vdram = 0
6061 13:08:42.135835 Vddq = 0
6062 13:08:42.139180 Vmddr = 0
6063 13:08:42.142750 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6064 13:08:42.149372 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6065 13:08:42.152581 MEM_TYPE=3, freq_sel=20
6066 13:08:42.152674 sv_algorithm_assistance_LP4_800
6067 13:08:42.159322 ============ PULL DRAM RESETB DOWN ============
6068 13:08:42.162703 ========== PULL DRAM RESETB DOWN end =========
6069 13:08:42.165874 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6070 13:08:42.169120 ===================================
6071 13:08:42.172592 LPDDR4 DRAM CONFIGURATION
6072 13:08:42.176129 ===================================
6073 13:08:42.179011 EX_ROW_EN[0] = 0x0
6074 13:08:42.179105 EX_ROW_EN[1] = 0x0
6075 13:08:42.182674 LP4Y_EN = 0x0
6076 13:08:42.182764 WORK_FSP = 0x0
6077 13:08:42.185726 WL = 0x2
6078 13:08:42.185819 RL = 0x2
6079 13:08:42.189178 BL = 0x2
6080 13:08:42.189249 RPST = 0x0
6081 13:08:42.192433 RD_PRE = 0x0
6082 13:08:42.192503 WR_PRE = 0x1
6083 13:08:42.196070 WR_PST = 0x0
6084 13:08:42.196157 DBI_WR = 0x0
6085 13:08:42.199254 DBI_RD = 0x0
6086 13:08:42.199347 OTF = 0x1
6087 13:08:42.202326 ===================================
6088 13:08:42.206216 ===================================
6089 13:08:42.209264 ANA top config
6090 13:08:42.212500 ===================================
6091 13:08:42.215867 DLL_ASYNC_EN = 0
6092 13:08:42.215958 ALL_SLAVE_EN = 1
6093 13:08:42.219415 NEW_RANK_MODE = 1
6094 13:08:42.222401 DLL_IDLE_MODE = 1
6095 13:08:42.225893 LP45_APHY_COMB_EN = 1
6096 13:08:42.225985 TX_ODT_DIS = 1
6097 13:08:42.229591 NEW_8X_MODE = 1
6098 13:08:42.232366 ===================================
6099 13:08:42.236080 ===================================
6100 13:08:42.239019 data_rate = 800
6101 13:08:42.242203 CKR = 1
6102 13:08:42.245673 DQ_P2S_RATIO = 4
6103 13:08:42.248908 ===================================
6104 13:08:42.252386 CA_P2S_RATIO = 4
6105 13:08:42.252475 DQ_CA_OPEN = 0
6106 13:08:42.255944 DQ_SEMI_OPEN = 1
6107 13:08:42.259085 CA_SEMI_OPEN = 1
6108 13:08:42.262723 CA_FULL_RATE = 0
6109 13:08:42.265981 DQ_CKDIV4_EN = 0
6110 13:08:42.268980 CA_CKDIV4_EN = 1
6111 13:08:42.269073 CA_PREDIV_EN = 0
6112 13:08:42.272350 PH8_DLY = 0
6113 13:08:42.275815 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6114 13:08:42.278952 DQ_AAMCK_DIV = 0
6115 13:08:42.282448 CA_AAMCK_DIV = 0
6116 13:08:42.285673 CA_ADMCK_DIV = 4
6117 13:08:42.285738 DQ_TRACK_CA_EN = 0
6118 13:08:42.288749 CA_PICK = 800
6119 13:08:42.292225 CA_MCKIO = 400
6120 13:08:42.295678 MCKIO_SEMI = 400
6121 13:08:42.298724 PLL_FREQ = 3016
6122 13:08:42.302161 DQ_UI_PI_RATIO = 32
6123 13:08:42.305834 CA_UI_PI_RATIO = 32
6124 13:08:42.309459 ===================================
6125 13:08:42.312516 ===================================
6126 13:08:42.312615 memory_type:LPDDR4
6127 13:08:42.315454 GP_NUM : 10
6128 13:08:42.319545 SRAM_EN : 1
6129 13:08:42.319641 MD32_EN : 0
6130 13:08:42.322078 ===================================
6131 13:08:42.325234 [ANA_INIT] >>>>>>>>>>>>>>
6132 13:08:42.328985 <<<<<< [CONFIGURE PHASE]: ANA_TX
6133 13:08:42.332070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6134 13:08:42.335527 ===================================
6135 13:08:42.338648 data_rate = 800,PCW = 0X7400
6136 13:08:42.338748 ===================================
6137 13:08:42.345568 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6138 13:08:42.348719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6139 13:08:42.362297 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6140 13:08:42.365853 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6141 13:08:42.368619 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6142 13:08:42.371916 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6143 13:08:42.375712 [ANA_INIT] flow start
6144 13:08:42.375805 [ANA_INIT] PLL >>>>>>>>
6145 13:08:42.378925 [ANA_INIT] PLL <<<<<<<<
6146 13:08:42.382135 [ANA_INIT] MIDPI >>>>>>>>
6147 13:08:42.385161 [ANA_INIT] MIDPI <<<<<<<<
6148 13:08:42.385264 [ANA_INIT] DLL >>>>>>>>
6149 13:08:42.388553 [ANA_INIT] flow end
6150 13:08:42.392220 ============ LP4 DIFF to SE enter ============
6151 13:08:42.395809 ============ LP4 DIFF to SE exit ============
6152 13:08:42.398880 [ANA_INIT] <<<<<<<<<<<<<
6153 13:08:42.402464 [Flow] Enable top DCM control >>>>>
6154 13:08:42.405153 [Flow] Enable top DCM control <<<<<
6155 13:08:42.409302 Enable DLL master slave shuffle
6156 13:08:42.411997 ==============================================================
6157 13:08:42.415449 Gating Mode config
6158 13:08:42.422225 ==============================================================
6159 13:08:42.422303 Config description:
6160 13:08:42.432128 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6161 13:08:42.438707 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6162 13:08:42.445417 SELPH_MODE 0: By rank 1: By Phase
6163 13:08:42.448849 ==============================================================
6164 13:08:42.452258 GAT_TRACK_EN = 0
6165 13:08:42.455228 RX_GATING_MODE = 2
6166 13:08:42.458738 RX_GATING_TRACK_MODE = 2
6167 13:08:42.462142 SELPH_MODE = 1
6168 13:08:42.465088 PICG_EARLY_EN = 1
6169 13:08:42.468485 VALID_LAT_VALUE = 1
6170 13:08:42.471910 ==============================================================
6171 13:08:42.475162 Enter into Gating configuration >>>>
6172 13:08:42.478316 Exit from Gating configuration <<<<
6173 13:08:42.482215 Enter into DVFS_PRE_config >>>>>
6174 13:08:42.495891 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6175 13:08:42.495995 Exit from DVFS_PRE_config <<<<<
6176 13:08:42.498587 Enter into PICG configuration >>>>
6177 13:08:42.502505 Exit from PICG configuration <<<<
6178 13:08:42.505231 [RX_INPUT] configuration >>>>>
6179 13:08:42.508703 [RX_INPUT] configuration <<<<<
6180 13:08:42.515347 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6181 13:08:42.518638 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6182 13:08:42.525383 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6183 13:08:42.531883 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6184 13:08:42.538615 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6185 13:08:42.545360 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6186 13:08:42.548608 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6187 13:08:42.552291 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6188 13:08:42.555264 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6189 13:08:42.562694 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6190 13:08:42.565645 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6191 13:08:42.568916 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6192 13:08:42.572732 ===================================
6193 13:08:42.575978 LPDDR4 DRAM CONFIGURATION
6194 13:08:42.578728 ===================================
6195 13:08:42.578791 EX_ROW_EN[0] = 0x0
6196 13:08:42.582070 EX_ROW_EN[1] = 0x0
6197 13:08:42.582135 LP4Y_EN = 0x0
6198 13:08:42.585246 WORK_FSP = 0x0
6199 13:08:42.585308 WL = 0x2
6200 13:08:42.588937 RL = 0x2
6201 13:08:42.591958 BL = 0x2
6202 13:08:42.592018 RPST = 0x0
6203 13:08:42.595406 RD_PRE = 0x0
6204 13:08:42.595502 WR_PRE = 0x1
6205 13:08:42.598864 WR_PST = 0x0
6206 13:08:42.598934 DBI_WR = 0x0
6207 13:08:42.602028 DBI_RD = 0x0
6208 13:08:42.602095 OTF = 0x1
6209 13:08:42.605494 ===================================
6210 13:08:42.608649 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6211 13:08:42.615482 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6212 13:08:42.618890 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6213 13:08:42.622384 ===================================
6214 13:08:42.625316 LPDDR4 DRAM CONFIGURATION
6215 13:08:42.628645 ===================================
6216 13:08:42.628708 EX_ROW_EN[0] = 0x10
6217 13:08:42.631992 EX_ROW_EN[1] = 0x0
6218 13:08:42.632082 LP4Y_EN = 0x0
6219 13:08:42.635314 WORK_FSP = 0x0
6220 13:08:42.635388 WL = 0x2
6221 13:08:42.638742 RL = 0x2
6222 13:08:42.638834 BL = 0x2
6223 13:08:42.642036 RPST = 0x0
6224 13:08:42.642101 RD_PRE = 0x0
6225 13:08:42.645320 WR_PRE = 0x1
6226 13:08:42.645390 WR_PST = 0x0
6227 13:08:42.649263 DBI_WR = 0x0
6228 13:08:42.649328 DBI_RD = 0x0
6229 13:08:42.652091 OTF = 0x1
6230 13:08:42.655295 ===================================
6231 13:08:42.662248 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6232 13:08:42.665445 nWR fixed to 30
6233 13:08:42.668831 [ModeRegInit_LP4] CH0 RK0
6234 13:08:42.668896 [ModeRegInit_LP4] CH0 RK1
6235 13:08:42.672243 [ModeRegInit_LP4] CH1 RK0
6236 13:08:42.675697 [ModeRegInit_LP4] CH1 RK1
6237 13:08:42.675787 match AC timing 19
6238 13:08:42.682303 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6239 13:08:42.685415 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6240 13:08:42.688475 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6241 13:08:42.695613 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6242 13:08:42.698891 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6243 13:08:42.698972 ==
6244 13:08:42.701878 Dram Type= 6, Freq= 0, CH_0, rank 0
6245 13:08:42.705150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6246 13:08:42.705232 ==
6247 13:08:42.712307 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6248 13:08:42.718575 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6249 13:08:42.722059 [CA 0] Center 36 (8~64) winsize 57
6250 13:08:42.725426 [CA 1] Center 36 (8~64) winsize 57
6251 13:08:42.725511 [CA 2] Center 36 (8~64) winsize 57
6252 13:08:42.729142 [CA 3] Center 36 (8~64) winsize 57
6253 13:08:42.732088 [CA 4] Center 36 (8~64) winsize 57
6254 13:08:42.735438 [CA 5] Center 36 (8~64) winsize 57
6255 13:08:42.735533
6256 13:08:42.739099 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6257 13:08:42.739167
6258 13:08:42.745275 [CATrainingPosCal] consider 1 rank data
6259 13:08:42.745350 u2DelayCellTimex100 = 270/100 ps
6260 13:08:42.752169 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 13:08:42.755182 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 13:08:42.758475 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 13:08:42.762116 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 13:08:42.765268 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 13:08:42.768490 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 13:08:42.768568
6267 13:08:42.771858 CA PerBit enable=1, Macro0, CA PI delay=36
6268 13:08:42.771951
6269 13:08:42.775513 [CBTSetCACLKResult] CA Dly = 36
6270 13:08:42.778973 CS Dly: 1 (0~32)
6271 13:08:42.779041 ==
6272 13:08:42.781721 Dram Type= 6, Freq= 0, CH_0, rank 1
6273 13:08:42.785317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 13:08:42.785388 ==
6275 13:08:42.788798 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6276 13:08:42.795716 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6277 13:08:42.798614 [CA 0] Center 36 (8~64) winsize 57
6278 13:08:42.802235 [CA 1] Center 36 (8~64) winsize 57
6279 13:08:42.805338 [CA 2] Center 36 (8~64) winsize 57
6280 13:08:42.809008 [CA 3] Center 36 (8~64) winsize 57
6281 13:08:42.812176 [CA 4] Center 36 (8~64) winsize 57
6282 13:08:42.815388 [CA 5] Center 36 (8~64) winsize 57
6283 13:08:42.815464
6284 13:08:42.818732 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6285 13:08:42.818809
6286 13:08:42.821745 [CATrainingPosCal] consider 2 rank data
6287 13:08:42.825120 u2DelayCellTimex100 = 270/100 ps
6288 13:08:42.829768 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 13:08:42.831749 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 13:08:42.835304 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 13:08:42.838527 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 13:08:42.845441 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 13:08:42.848883 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 13:08:42.848960
6295 13:08:42.852017 CA PerBit enable=1, Macro0, CA PI delay=36
6296 13:08:42.852094
6297 13:08:42.855505 [CBTSetCACLKResult] CA Dly = 36
6298 13:08:42.855580 CS Dly: 1 (0~32)
6299 13:08:42.855641
6300 13:08:42.858597 ----->DramcWriteLeveling(PI) begin...
6301 13:08:42.858676 ==
6302 13:08:42.861614 Dram Type= 6, Freq= 0, CH_0, rank 0
6303 13:08:42.868304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 13:08:42.868382 ==
6305 13:08:42.871691 Write leveling (Byte 0): 40 => 8
6306 13:08:42.871768 Write leveling (Byte 1): 32 => 0
6307 13:08:42.875018 DramcWriteLeveling(PI) end<-----
6308 13:08:42.875101
6309 13:08:42.875196 ==
6310 13:08:42.878495 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 13:08:42.884970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 13:08:42.885047 ==
6313 13:08:42.888472 [Gating] SW mode calibration
6314 13:08:42.895123 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6315 13:08:42.898744 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6316 13:08:42.905045 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6317 13:08:42.908736 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6318 13:08:42.912394 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6319 13:08:42.915194 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6320 13:08:42.921841 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6321 13:08:42.925033 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6322 13:08:42.928435 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6323 13:08:42.935073 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6324 13:08:42.938232 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6325 13:08:42.941727 Total UI for P1: 0, mck2ui 16
6326 13:08:42.944981 best dqsien dly found for B0: ( 0, 14, 24)
6327 13:08:42.948535 Total UI for P1: 0, mck2ui 16
6328 13:08:42.951441 best dqsien dly found for B1: ( 0, 14, 24)
6329 13:08:42.954848 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6330 13:08:42.958001 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6331 13:08:42.958077
6332 13:08:42.961712 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6333 13:08:42.968508 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6334 13:08:42.968585 [Gating] SW calibration Done
6335 13:08:42.968645 ==
6336 13:08:42.971671 Dram Type= 6, Freq= 0, CH_0, rank 0
6337 13:08:42.978168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6338 13:08:42.978245 ==
6339 13:08:42.978305 RX Vref Scan: 0
6340 13:08:42.978361
6341 13:08:42.981364 RX Vref 0 -> 0, step: 1
6342 13:08:42.981440
6343 13:08:42.984664 RX Delay -410 -> 252, step: 16
6344 13:08:42.988162 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6345 13:08:42.991447 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6346 13:08:42.998011 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6347 13:08:43.001300 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6348 13:08:43.004844 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6349 13:08:43.007879 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6350 13:08:43.014810 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6351 13:08:43.018136 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6352 13:08:43.021731 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6353 13:08:43.024654 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6354 13:08:43.027715 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6355 13:08:43.034694 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6356 13:08:43.037965 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6357 13:08:43.041337 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6358 13:08:43.047923 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6359 13:08:43.051438 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6360 13:08:43.051520 ==
6361 13:08:43.054755 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 13:08:43.058054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 13:08:43.058191 ==
6364 13:08:43.061979 DQS Delay:
6365 13:08:43.062412 DQS0 = 19, DQS1 = 43
6366 13:08:43.062742 DQM Delay:
6367 13:08:43.064830 DQM0 = 5, DQM1 = 14
6368 13:08:43.065287 DQ Delay:
6369 13:08:43.068595 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6370 13:08:43.071624 DQ4 =8, DQ5 =0, DQ6 =8, DQ7 =16
6371 13:08:43.075345 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6372 13:08:43.078676 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6373 13:08:43.079175
6374 13:08:43.079505
6375 13:08:43.079807 ==
6376 13:08:43.081950 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 13:08:43.085188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 13:08:43.085653 ==
6379 13:08:43.085987
6380 13:08:43.088355
6381 13:08:43.088783 TX Vref Scan disable
6382 13:08:43.091367 == TX Byte 0 ==
6383 13:08:43.094887 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6384 13:08:43.098304 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6385 13:08:43.101300 == TX Byte 1 ==
6386 13:08:43.104628 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6387 13:08:43.108120 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6388 13:08:43.108565 ==
6389 13:08:43.111242 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 13:08:43.114677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 13:08:43.118202 ==
6392 13:08:43.118697
6393 13:08:43.119053
6394 13:08:43.119469 TX Vref Scan disable
6395 13:08:43.121371 == TX Byte 0 ==
6396 13:08:43.125118 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6397 13:08:43.128049 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6398 13:08:43.131707 == TX Byte 1 ==
6399 13:08:43.134888 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6400 13:08:43.137866 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6401 13:08:43.138303
6402 13:08:43.141251 [DATLAT]
6403 13:08:43.141682 Freq=400, CH0 RK0
6404 13:08:43.142020
6405 13:08:43.144546 DATLAT Default: 0xf
6406 13:08:43.144623 0, 0xFFFF, sum = 0
6407 13:08:43.147900 1, 0xFFFF, sum = 0
6408 13:08:43.147977 2, 0xFFFF, sum = 0
6409 13:08:43.151071 3, 0xFFFF, sum = 0
6410 13:08:43.151149 4, 0xFFFF, sum = 0
6411 13:08:43.154629 5, 0xFFFF, sum = 0
6412 13:08:43.154707 6, 0xFFFF, sum = 0
6413 13:08:43.157627 7, 0xFFFF, sum = 0
6414 13:08:43.157705 8, 0xFFFF, sum = 0
6415 13:08:43.160985 9, 0xFFFF, sum = 0
6416 13:08:43.161062 10, 0xFFFF, sum = 0
6417 13:08:43.164403 11, 0xFFFF, sum = 0
6418 13:08:43.164481 12, 0xFFFF, sum = 0
6419 13:08:43.167593 13, 0x0, sum = 1
6420 13:08:43.167670 14, 0x0, sum = 2
6421 13:08:43.170883 15, 0x0, sum = 3
6422 13:08:43.170961 16, 0x0, sum = 4
6423 13:08:43.174110 best_step = 14
6424 13:08:43.174186
6425 13:08:43.174245 ==
6426 13:08:43.177860 Dram Type= 6, Freq= 0, CH_0, rank 0
6427 13:08:43.181141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 13:08:43.181225 ==
6429 13:08:43.184669 RX Vref Scan: 1
6430 13:08:43.184812
6431 13:08:43.184882 RX Vref 0 -> 0, step: 1
6432 13:08:43.184944
6433 13:08:43.187626 RX Delay -327 -> 252, step: 8
6434 13:08:43.187768
6435 13:08:43.190807 Set Vref, RX VrefLevel [Byte0]: 54
6436 13:08:43.194406 [Byte1]: 49
6437 13:08:43.199019
6438 13:08:43.199123 Final RX Vref Byte 0 = 54 to rank0
6439 13:08:43.202134 Final RX Vref Byte 1 = 49 to rank0
6440 13:08:43.205573 Final RX Vref Byte 0 = 54 to rank1
6441 13:08:43.209564 Final RX Vref Byte 1 = 49 to rank1==
6442 13:08:43.212243 Dram Type= 6, Freq= 0, CH_0, rank 0
6443 13:08:43.219191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 13:08:43.219353 ==
6445 13:08:43.219479 DQS Delay:
6446 13:08:43.222390 DQS0 = 24, DQS1 = 48
6447 13:08:43.222575 DQM Delay:
6448 13:08:43.222720 DQM0 = 9, DQM1 = 14
6449 13:08:43.225956 DQ Delay:
6450 13:08:43.226251 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6451 13:08:43.229530 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6452 13:08:43.232691 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6453 13:08:43.235526 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6454 13:08:43.235887
6455 13:08:43.236158
6456 13:08:43.246045 [DQSOSCAuto] RK0, (LSB)MR18= 0xb5ac, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6457 13:08:43.249210 CH0 RK0: MR19=C0C, MR18=B5AC
6458 13:08:43.252695 CH0_RK0: MR19=0xC0C, MR18=0xB5AC, DQSOSC=387, MR23=63, INC=394, DEC=262
6459 13:08:43.256555 ==
6460 13:08:43.259333 Dram Type= 6, Freq= 0, CH_0, rank 1
6461 13:08:43.262540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 13:08:43.262981 ==
6463 13:08:43.266454 [Gating] SW mode calibration
6464 13:08:43.272917 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6465 13:08:43.276006 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6466 13:08:43.282852 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6467 13:08:43.286258 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6468 13:08:43.289328 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6469 13:08:43.296348 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6470 13:08:43.299145 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6471 13:08:43.302208 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6472 13:08:43.309256 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6473 13:08:43.312642 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6474 13:08:43.315865 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6475 13:08:43.319177 Total UI for P1: 0, mck2ui 16
6476 13:08:43.322804 best dqsien dly found for B0: ( 0, 14, 24)
6477 13:08:43.325728 Total UI for P1: 0, mck2ui 16
6478 13:08:43.329282 best dqsien dly found for B1: ( 0, 14, 24)
6479 13:08:43.332216 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6480 13:08:43.335959 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6481 13:08:43.336394
6482 13:08:43.339275 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6483 13:08:43.345585 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6484 13:08:43.345663 [Gating] SW calibration Done
6485 13:08:43.348513 ==
6486 13:08:43.348589 Dram Type= 6, Freq= 0, CH_0, rank 1
6487 13:08:43.355157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6488 13:08:43.355235 ==
6489 13:08:43.355295 RX Vref Scan: 0
6490 13:08:43.355351
6491 13:08:43.358806 RX Vref 0 -> 0, step: 1
6492 13:08:43.358881
6493 13:08:43.362324 RX Delay -410 -> 252, step: 16
6494 13:08:43.365299 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6495 13:08:43.368427 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6496 13:08:43.375332 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6497 13:08:43.378393 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6498 13:08:43.381768 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6499 13:08:43.385335 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6500 13:08:43.392168 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6501 13:08:43.395149 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6502 13:08:43.398497 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6503 13:08:43.402451 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6504 13:08:43.408787 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6505 13:08:43.411821 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6506 13:08:43.415166 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6507 13:08:43.418755 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6508 13:08:43.425271 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6509 13:08:43.428446 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6510 13:08:43.428523 ==
6511 13:08:43.431637 Dram Type= 6, Freq= 0, CH_0, rank 1
6512 13:08:43.435119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 13:08:43.435197 ==
6514 13:08:43.438275 DQS Delay:
6515 13:08:43.438351 DQS0 = 27, DQS1 = 43
6516 13:08:43.442197 DQM Delay:
6517 13:08:43.442273 DQM0 = 9, DQM1 = 15
6518 13:08:43.442333 DQ Delay:
6519 13:08:43.445268 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6520 13:08:43.448604 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6521 13:08:43.452066 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6522 13:08:43.455701 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6523 13:08:43.455778
6524 13:08:43.455837
6525 13:08:43.455890 ==
6526 13:08:43.458409 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 13:08:43.461783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 13:08:43.465402 ==
6529 13:08:43.465479
6530 13:08:43.465538
6531 13:08:43.465593 TX Vref Scan disable
6532 13:08:43.468368 == TX Byte 0 ==
6533 13:08:43.472041 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6534 13:08:43.475641 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6535 13:08:43.478860 == TX Byte 1 ==
6536 13:08:43.481847 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6537 13:08:43.485240 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6538 13:08:43.485316 ==
6539 13:08:43.488401 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 13:08:43.492420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 13:08:43.495552 ==
6542 13:08:43.495629
6543 13:08:43.495687
6544 13:08:43.495741 TX Vref Scan disable
6545 13:08:43.498470 == TX Byte 0 ==
6546 13:08:43.501856 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6547 13:08:43.505345 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6548 13:08:43.508590 == TX Byte 1 ==
6549 13:08:43.511661 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6550 13:08:43.515160 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6551 13:08:43.515238
6552 13:08:43.515298 [DATLAT]
6553 13:08:43.518914 Freq=400, CH0 RK1
6554 13:08:43.518992
6555 13:08:43.519052 DATLAT Default: 0xe
6556 13:08:43.522265 0, 0xFFFF, sum = 0
6557 13:08:43.525221 1, 0xFFFF, sum = 0
6558 13:08:43.525299 2, 0xFFFF, sum = 0
6559 13:08:43.528596 3, 0xFFFF, sum = 0
6560 13:08:43.528673 4, 0xFFFF, sum = 0
6561 13:08:43.531851 5, 0xFFFF, sum = 0
6562 13:08:43.531928 6, 0xFFFF, sum = 0
6563 13:08:43.535222 7, 0xFFFF, sum = 0
6564 13:08:43.535300 8, 0xFFFF, sum = 0
6565 13:08:43.538807 9, 0xFFFF, sum = 0
6566 13:08:43.538885 10, 0xFFFF, sum = 0
6567 13:08:43.541825 11, 0xFFFF, sum = 0
6568 13:08:43.541903 12, 0xFFFF, sum = 0
6569 13:08:43.545029 13, 0x0, sum = 1
6570 13:08:43.545157 14, 0x0, sum = 2
6571 13:08:43.548833 15, 0x0, sum = 3
6572 13:08:43.548925 16, 0x0, sum = 4
6573 13:08:43.551820 best_step = 14
6574 13:08:43.551897
6575 13:08:43.551956 ==
6576 13:08:43.555245 Dram Type= 6, Freq= 0, CH_0, rank 1
6577 13:08:43.558396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6578 13:08:43.558473 ==
6579 13:08:43.561861 RX Vref Scan: 0
6580 13:08:43.561938
6581 13:08:43.561997 RX Vref 0 -> 0, step: 1
6582 13:08:43.562053
6583 13:08:43.565068 RX Delay -327 -> 252, step: 8
6584 13:08:43.572431 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6585 13:08:43.575662 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6586 13:08:43.579682 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6587 13:08:43.582525 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6588 13:08:43.589199 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6589 13:08:43.592329 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6590 13:08:43.595820 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6591 13:08:43.599056 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6592 13:08:43.605576 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6593 13:08:43.608919 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6594 13:08:43.612704 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6595 13:08:43.615720 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6596 13:08:43.622342 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6597 13:08:43.625656 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6598 13:08:43.628837 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6599 13:08:43.635299 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6600 13:08:43.635377 ==
6601 13:08:43.638953 Dram Type= 6, Freq= 0, CH_0, rank 1
6602 13:08:43.642519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6603 13:08:43.642597 ==
6604 13:08:43.642657 DQS Delay:
6605 13:08:43.645600 DQS0 = 28, DQS1 = 44
6606 13:08:43.645677 DQM Delay:
6607 13:08:43.648779 DQM0 = 10, DQM1 = 15
6608 13:08:43.648855 DQ Delay:
6609 13:08:43.652333 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6610 13:08:43.655529 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6611 13:08:43.659128 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6612 13:08:43.662343 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6613 13:08:43.662419
6614 13:08:43.662478
6615 13:08:43.668953 [DQSOSCAuto] RK1, (LSB)MR18= 0xc375, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 385 ps
6616 13:08:43.672035 CH0 RK1: MR19=C0C, MR18=C375
6617 13:08:43.679004 CH0_RK1: MR19=0xC0C, MR18=0xC375, DQSOSC=385, MR23=63, INC=398, DEC=265
6618 13:08:43.682141 [RxdqsGatingPostProcess] freq 400
6619 13:08:43.688708 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6620 13:08:43.688785 best DQS0 dly(2T, 0.5T) = (0, 10)
6621 13:08:43.692480 best DQS1 dly(2T, 0.5T) = (0, 10)
6622 13:08:43.695747 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6623 13:08:43.698832 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6624 13:08:43.702246 best DQS0 dly(2T, 0.5T) = (0, 10)
6625 13:08:43.705563 best DQS1 dly(2T, 0.5T) = (0, 10)
6626 13:08:43.708650 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6627 13:08:43.712438 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6628 13:08:43.715403 Pre-setting of DQS Precalculation
6629 13:08:43.722030 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6630 13:08:43.722107 ==
6631 13:08:43.725894 Dram Type= 6, Freq= 0, CH_1, rank 0
6632 13:08:43.728747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6633 13:08:43.728824 ==
6634 13:08:43.732234 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6635 13:08:43.738818 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6636 13:08:43.741910 [CA 0] Center 36 (8~64) winsize 57
6637 13:08:43.745393 [CA 1] Center 36 (8~64) winsize 57
6638 13:08:43.748675 [CA 2] Center 36 (8~64) winsize 57
6639 13:08:43.752224 [CA 3] Center 36 (8~64) winsize 57
6640 13:08:43.755626 [CA 4] Center 36 (8~64) winsize 57
6641 13:08:43.758787 [CA 5] Center 36 (8~64) winsize 57
6642 13:08:43.758864
6643 13:08:43.761790 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6644 13:08:43.761867
6645 13:08:43.765395 [CATrainingPosCal] consider 1 rank data
6646 13:08:43.768490 u2DelayCellTimex100 = 270/100 ps
6647 13:08:43.772030 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 13:08:43.775018 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 13:08:43.778449 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 13:08:43.782413 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 13:08:43.789135 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 13:08:43.791842 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 13:08:43.791918
6654 13:08:43.795581 CA PerBit enable=1, Macro0, CA PI delay=36
6655 13:08:43.795657
6656 13:08:43.798396 [CBTSetCACLKResult] CA Dly = 36
6657 13:08:43.798473 CS Dly: 1 (0~32)
6658 13:08:43.798533 ==
6659 13:08:43.802157 Dram Type= 6, Freq= 0, CH_1, rank 1
6660 13:08:43.805484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 13:08:43.808398 ==
6662 13:08:43.811987 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6663 13:08:43.818480 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6664 13:08:43.822010 [CA 0] Center 36 (8~64) winsize 57
6665 13:08:43.825549 [CA 1] Center 36 (8~64) winsize 57
6666 13:08:43.828511 [CA 2] Center 36 (8~64) winsize 57
6667 13:08:43.831989 [CA 3] Center 36 (8~64) winsize 57
6668 13:08:43.835579 [CA 4] Center 36 (8~64) winsize 57
6669 13:08:43.838614 [CA 5] Center 36 (8~64) winsize 57
6670 13:08:43.838690
6671 13:08:43.841978 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6672 13:08:43.842054
6673 13:08:43.845656 [CATrainingPosCal] consider 2 rank data
6674 13:08:43.848801 u2DelayCellTimex100 = 270/100 ps
6675 13:08:43.852307 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 13:08:43.855255 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 13:08:43.858468 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 13:08:43.861940 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 13:08:43.865062 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 13:08:43.868951 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 13:08:43.869027
6682 13:08:43.872062 CA PerBit enable=1, Macro0, CA PI delay=36
6683 13:08:43.872140
6684 13:08:43.875452 [CBTSetCACLKResult] CA Dly = 36
6685 13:08:43.878765 CS Dly: 1 (0~32)
6686 13:08:43.878841
6687 13:08:43.882106 ----->DramcWriteLeveling(PI) begin...
6688 13:08:43.882184 ==
6689 13:08:43.885365 Dram Type= 6, Freq= 0, CH_1, rank 0
6690 13:08:43.888593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 13:08:43.888675 ==
6692 13:08:43.892250 Write leveling (Byte 0): 40 => 8
6693 13:08:43.895095 Write leveling (Byte 1): 32 => 0
6694 13:08:43.898572 DramcWriteLeveling(PI) end<-----
6695 13:08:43.898648
6696 13:08:43.898708 ==
6697 13:08:43.902102 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 13:08:43.904998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 13:08:43.905116 ==
6700 13:08:43.908500 [Gating] SW mode calibration
6701 13:08:43.915290 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6702 13:08:43.921869 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6703 13:08:43.924879 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6704 13:08:43.931701 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6705 13:08:43.934748 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6706 13:08:43.938389 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6707 13:08:43.944979 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6708 13:08:43.948684 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6709 13:08:43.951523 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6710 13:08:43.955283 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6711 13:08:43.961301 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6712 13:08:43.964808 Total UI for P1: 0, mck2ui 16
6713 13:08:43.968203 best dqsien dly found for B0: ( 0, 14, 24)
6714 13:08:43.971290 Total UI for P1: 0, mck2ui 16
6715 13:08:43.974762 best dqsien dly found for B1: ( 0, 14, 24)
6716 13:08:43.978216 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6717 13:08:43.981461 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6718 13:08:43.981538
6719 13:08:43.984793 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6720 13:08:43.987926 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6721 13:08:43.991477 [Gating] SW calibration Done
6722 13:08:43.991553 ==
6723 13:08:43.994788 Dram Type= 6, Freq= 0, CH_1, rank 0
6724 13:08:43.997828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6725 13:08:43.997906 ==
6726 13:08:44.001093 RX Vref Scan: 0
6727 13:08:44.001217
6728 13:08:44.004469 RX Vref 0 -> 0, step: 1
6729 13:08:44.004546
6730 13:08:44.004606 RX Delay -410 -> 252, step: 16
6731 13:08:44.011288 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6732 13:08:44.014617 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6733 13:08:44.018024 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6734 13:08:44.021537 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6735 13:08:44.027847 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6736 13:08:44.031308 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6737 13:08:44.034643 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6738 13:08:44.037828 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6739 13:08:44.044931 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6740 13:08:44.048112 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6741 13:08:44.051369 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6742 13:08:44.054564 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6743 13:08:44.061081 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6744 13:08:44.064498 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6745 13:08:44.067945 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6746 13:08:44.071690 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6747 13:08:44.074753 ==
6748 13:08:44.077957 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 13:08:44.081082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 13:08:44.081179 ==
6751 13:08:44.081241 DQS Delay:
6752 13:08:44.084665 DQS0 = 27, DQS1 = 43
6753 13:08:44.084741 DQM Delay:
6754 13:08:44.088157 DQM0 = 5, DQM1 = 14
6755 13:08:44.088232 DQ Delay:
6756 13:08:44.091508 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6757 13:08:44.094602 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6758 13:08:44.098348 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6759 13:08:44.101563 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6760 13:08:44.101640
6761 13:08:44.101699
6762 13:08:44.101754 ==
6763 13:08:44.104639 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 13:08:44.107872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 13:08:44.107949 ==
6766 13:08:44.108008
6767 13:08:44.108063
6768 13:08:44.111340 TX Vref Scan disable
6769 13:08:44.111415 == TX Byte 0 ==
6770 13:08:44.117915 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6771 13:08:44.121520 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6772 13:08:44.121598 == TX Byte 1 ==
6773 13:08:44.128118 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6774 13:08:44.131269 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6775 13:08:44.131346 ==
6776 13:08:44.134528 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 13:08:44.138230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 13:08:44.138308 ==
6779 13:08:44.138367
6780 13:08:44.138421
6781 13:08:44.141118 TX Vref Scan disable
6782 13:08:44.141229 == TX Byte 0 ==
6783 13:08:44.147825 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6784 13:08:44.151391 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6785 13:08:44.151468 == TX Byte 1 ==
6786 13:08:44.157882 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6787 13:08:44.161094 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6788 13:08:44.161179
6789 13:08:44.161240 [DATLAT]
6790 13:08:44.164999 Freq=400, CH1 RK0
6791 13:08:44.165099
6792 13:08:44.165209 DATLAT Default: 0xf
6793 13:08:44.167797 0, 0xFFFF, sum = 0
6794 13:08:44.167875 1, 0xFFFF, sum = 0
6795 13:08:44.171043 2, 0xFFFF, sum = 0
6796 13:08:44.171120 3, 0xFFFF, sum = 0
6797 13:08:44.174695 4, 0xFFFF, sum = 0
6798 13:08:44.174773 5, 0xFFFF, sum = 0
6799 13:08:44.177692 6, 0xFFFF, sum = 0
6800 13:08:44.177770 7, 0xFFFF, sum = 0
6801 13:08:44.181338 8, 0xFFFF, sum = 0
6802 13:08:44.181415 9, 0xFFFF, sum = 0
6803 13:08:44.184621 10, 0xFFFF, sum = 0
6804 13:08:44.187630 11, 0xFFFF, sum = 0
6805 13:08:44.187733 12, 0xFFFF, sum = 0
6806 13:08:44.191145 13, 0x0, sum = 1
6807 13:08:44.191222 14, 0x0, sum = 2
6808 13:08:44.194764 15, 0x0, sum = 3
6809 13:08:44.194841 16, 0x0, sum = 4
6810 13:08:44.194902 best_step = 14
6811 13:08:44.194956
6812 13:08:44.197695 ==
6813 13:08:44.200995 Dram Type= 6, Freq= 0, CH_1, rank 0
6814 13:08:44.204400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 13:08:44.204477 ==
6816 13:08:44.204536 RX Vref Scan: 1
6817 13:08:44.204592
6818 13:08:44.207646 RX Vref 0 -> 0, step: 1
6819 13:08:44.207722
6820 13:08:44.210969 RX Delay -327 -> 252, step: 8
6821 13:08:44.211045
6822 13:08:44.214498 Set Vref, RX VrefLevel [Byte0]: 49
6823 13:08:44.217696 [Byte1]: 53
6824 13:08:44.221019
6825 13:08:44.221095 Final RX Vref Byte 0 = 49 to rank0
6826 13:08:44.224378 Final RX Vref Byte 1 = 53 to rank0
6827 13:08:44.227650 Final RX Vref Byte 0 = 49 to rank1
6828 13:08:44.230993 Final RX Vref Byte 1 = 53 to rank1==
6829 13:08:44.234362 Dram Type= 6, Freq= 0, CH_1, rank 0
6830 13:08:44.241077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 13:08:44.241209 ==
6832 13:08:44.241270 DQS Delay:
6833 13:08:44.244499 DQS0 = 32, DQS1 = 40
6834 13:08:44.244575 DQM Delay:
6835 13:08:44.244634 DQM0 = 11, DQM1 = 13
6836 13:08:44.248001 DQ Delay:
6837 13:08:44.250983 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =12
6838 13:08:44.251060 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6839 13:08:44.254245 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6840 13:08:44.257514 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =16
6841 13:08:44.257591
6842 13:08:44.260875
6843 13:08:44.267655 [DQSOSCAuto] RK0, (LSB)MR18= 0x9ad4, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6844 13:08:44.270714 CH1 RK0: MR19=C0C, MR18=9AD4
6845 13:08:44.277372 CH1_RK0: MR19=0xC0C, MR18=0x9AD4, DQSOSC=383, MR23=63, INC=402, DEC=268
6846 13:08:44.277448 ==
6847 13:08:44.280968 Dram Type= 6, Freq= 0, CH_1, rank 1
6848 13:08:44.284485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 13:08:44.284562 ==
6850 13:08:44.287726 [Gating] SW mode calibration
6851 13:08:44.294399 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6852 13:08:44.297839 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6853 13:08:44.304924 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6854 13:08:44.307803 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6855 13:08:44.310990 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6856 13:08:44.317532 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6857 13:08:44.321074 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6858 13:08:44.324554 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6859 13:08:44.330894 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6860 13:08:44.334277 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6861 13:08:44.337435 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6862 13:08:44.340905 Total UI for P1: 0, mck2ui 16
6863 13:08:44.344098 best dqsien dly found for B0: ( 0, 14, 24)
6864 13:08:44.347459 Total UI for P1: 0, mck2ui 16
6865 13:08:44.351313 best dqsien dly found for B1: ( 0, 14, 24)
6866 13:08:44.354203 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6867 13:08:44.357798 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6868 13:08:44.357874
6869 13:08:44.364114 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6870 13:08:44.367952 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6871 13:08:44.370841 [Gating] SW calibration Done
6872 13:08:44.370917 ==
6873 13:08:44.374694 Dram Type= 6, Freq= 0, CH_1, rank 1
6874 13:08:44.377589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6875 13:08:44.377666 ==
6876 13:08:44.377727 RX Vref Scan: 0
6877 13:08:44.377782
6878 13:08:44.381192 RX Vref 0 -> 0, step: 1
6879 13:08:44.381269
6880 13:08:44.384532 RX Delay -410 -> 252, step: 16
6881 13:08:44.387847 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6882 13:08:44.391091 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6883 13:08:44.397737 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6884 13:08:44.401038 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6885 13:08:44.404836 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6886 13:08:44.407693 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6887 13:08:44.414201 iDelay=230, Bit 6, Center -19 (-250 ~ 213) 464
6888 13:08:44.417781 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6889 13:08:44.420930 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6890 13:08:44.424395 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6891 13:08:44.431172 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6892 13:08:44.434410 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6893 13:08:44.437745 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6894 13:08:44.441059 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6895 13:08:44.447568 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6896 13:08:44.451154 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6897 13:08:44.451219 ==
6898 13:08:44.454443 Dram Type= 6, Freq= 0, CH_1, rank 1
6899 13:08:44.458136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 13:08:44.458212 ==
6901 13:08:44.461476 DQS Delay:
6902 13:08:44.461543 DQS0 = 35, DQS1 = 43
6903 13:08:44.464513 DQM Delay:
6904 13:08:44.464575 DQM0 = 16, DQM1 = 19
6905 13:08:44.464627 DQ Delay:
6906 13:08:44.467974 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6907 13:08:44.470984 DQ4 =16, DQ5 =24, DQ6 =16, DQ7 =16
6908 13:08:44.474857 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6909 13:08:44.477776 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6910 13:08:44.477843
6911 13:08:44.477899
6912 13:08:44.477952 ==
6913 13:08:44.481433 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 13:08:44.487630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 13:08:44.487726 ==
6916 13:08:44.487810
6917 13:08:44.487903
6918 13:08:44.487985 TX Vref Scan disable
6919 13:08:44.491194 == TX Byte 0 ==
6920 13:08:44.494320 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6921 13:08:44.497869 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6922 13:08:44.501028 == TX Byte 1 ==
6923 13:08:44.504479 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6924 13:08:44.507655 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6925 13:08:44.507722 ==
6926 13:08:44.510957 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 13:08:44.517927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 13:08:44.518000 ==
6929 13:08:44.518059
6930 13:08:44.518113
6931 13:08:44.518200 TX Vref Scan disable
6932 13:08:44.521276 == TX Byte 0 ==
6933 13:08:44.524361 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6934 13:08:44.528005 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6935 13:08:44.530945 == TX Byte 1 ==
6936 13:08:44.534251 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6937 13:08:44.537569 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6938 13:08:44.537642
6939 13:08:44.541212 [DATLAT]
6940 13:08:44.541287 Freq=400, CH1 RK1
6941 13:08:44.541347
6942 13:08:44.544369 DATLAT Default: 0xe
6943 13:08:44.544445 0, 0xFFFF, sum = 0
6944 13:08:44.548156 1, 0xFFFF, sum = 0
6945 13:08:44.548235 2, 0xFFFF, sum = 0
6946 13:08:44.551390 3, 0xFFFF, sum = 0
6947 13:08:44.551468 4, 0xFFFF, sum = 0
6948 13:08:44.554774 5, 0xFFFF, sum = 0
6949 13:08:44.554852 6, 0xFFFF, sum = 0
6950 13:08:44.557676 7, 0xFFFF, sum = 0
6951 13:08:44.557754 8, 0xFFFF, sum = 0
6952 13:08:44.561087 9, 0xFFFF, sum = 0
6953 13:08:44.561200 10, 0xFFFF, sum = 0
6954 13:08:44.564330 11, 0xFFFF, sum = 0
6955 13:08:44.568005 12, 0xFFFF, sum = 0
6956 13:08:44.568082 13, 0x0, sum = 1
6957 13:08:44.568144 14, 0x0, sum = 2
6958 13:08:44.571139 15, 0x0, sum = 3
6959 13:08:44.571216 16, 0x0, sum = 4
6960 13:08:44.574551 best_step = 14
6961 13:08:44.574627
6962 13:08:44.574685 ==
6963 13:08:44.577640 Dram Type= 6, Freq= 0, CH_1, rank 1
6964 13:08:44.581076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6965 13:08:44.581191 ==
6966 13:08:44.584391 RX Vref Scan: 0
6967 13:08:44.584466
6968 13:08:44.584525 RX Vref 0 -> 0, step: 1
6969 13:08:44.584579
6970 13:08:44.587586 RX Delay -327 -> 252, step: 8
6971 13:08:44.595936 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6972 13:08:44.599344 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6973 13:08:44.602498 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6974 13:08:44.606183 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6975 13:08:44.612873 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6976 13:08:44.615887 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6977 13:08:44.619269 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6978 13:08:44.622718 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6979 13:08:44.629000 iDelay=217, Bit 8, Center -40 (-271 ~ 192) 464
6980 13:08:44.632342 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6981 13:08:44.635516 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6982 13:08:44.642341 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6983 13:08:44.645683 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6984 13:08:44.648783 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6985 13:08:44.651991 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6986 13:08:44.658490 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6987 13:08:44.658567 ==
6988 13:08:44.662109 Dram Type= 6, Freq= 0, CH_1, rank 1
6989 13:08:44.665550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6990 13:08:44.665627 ==
6991 13:08:44.665686 DQS Delay:
6992 13:08:44.668357 DQS0 = 28, DQS1 = 40
6993 13:08:44.668433 DQM Delay:
6994 13:08:44.672212 DQM0 = 8, DQM1 = 14
6995 13:08:44.672287 DQ Delay:
6996 13:08:44.675223 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =8
6997 13:08:44.678463 DQ4 =12, DQ5 =16, DQ6 =16, DQ7 =4
6998 13:08:44.682012 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6999 13:08:44.685285 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
7000 13:08:44.685361
7001 13:08:44.685420
7002 13:08:44.691571 [DQSOSCAuto] RK1, (LSB)MR18= 0xb35b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
7003 13:08:44.695164 CH1 RK1: MR19=C0C, MR18=B35B
7004 13:08:44.701677 CH1_RK1: MR19=0xC0C, MR18=0xB35B, DQSOSC=387, MR23=63, INC=394, DEC=262
7005 13:08:44.705152 [RxdqsGatingPostProcess] freq 400
7006 13:08:44.711799 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7007 13:08:44.714858 best DQS0 dly(2T, 0.5T) = (0, 10)
7008 13:08:44.714934 best DQS1 dly(2T, 0.5T) = (0, 10)
7009 13:08:44.718391 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7010 13:08:44.721679 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7011 13:08:44.724660 best DQS0 dly(2T, 0.5T) = (0, 10)
7012 13:08:44.728555 best DQS1 dly(2T, 0.5T) = (0, 10)
7013 13:08:44.731792 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7014 13:08:44.734705 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7015 13:08:44.738250 Pre-setting of DQS Precalculation
7016 13:08:44.745116 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7017 13:08:44.751644 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7018 13:08:44.758310 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7019 13:08:44.758387
7020 13:08:44.758446
7021 13:08:44.761542 [Calibration Summary] 800 Mbps
7022 13:08:44.761618 CH 0, Rank 0
7023 13:08:44.764831 SW Impedance : PASS
7024 13:08:44.768303 DUTY Scan : NO K
7025 13:08:44.768379 ZQ Calibration : PASS
7026 13:08:44.771884 Jitter Meter : NO K
7027 13:08:44.775000 CBT Training : PASS
7028 13:08:44.775076 Write leveling : PASS
7029 13:08:44.778099 RX DQS gating : PASS
7030 13:08:44.778174 RX DQ/DQS(RDDQC) : PASS
7031 13:08:44.781583 TX DQ/DQS : PASS
7032 13:08:44.784635 RX DATLAT : PASS
7033 13:08:44.784708 RX DQ/DQS(Engine): PASS
7034 13:08:44.788153 TX OE : NO K
7035 13:08:44.788221 All Pass.
7036 13:08:44.788278
7037 13:08:44.791718 CH 0, Rank 1
7038 13:08:44.791794 SW Impedance : PASS
7039 13:08:44.795003 DUTY Scan : NO K
7040 13:08:44.798057 ZQ Calibration : PASS
7041 13:08:44.798150 Jitter Meter : NO K
7042 13:08:44.801392 CBT Training : PASS
7043 13:08:44.804724 Write leveling : NO K
7044 13:08:44.804824 RX DQS gating : PASS
7045 13:08:44.808510 RX DQ/DQS(RDDQC) : PASS
7046 13:08:44.811742 TX DQ/DQS : PASS
7047 13:08:44.811827 RX DATLAT : PASS
7048 13:08:44.815441 RX DQ/DQS(Engine): PASS
7049 13:08:44.815555 TX OE : NO K
7050 13:08:44.818415 All Pass.
7051 13:08:44.818496
7052 13:08:44.818582 CH 1, Rank 0
7053 13:08:44.821661 SW Impedance : PASS
7054 13:08:44.821761 DUTY Scan : NO K
7055 13:08:44.824939 ZQ Calibration : PASS
7056 13:08:44.828271 Jitter Meter : NO K
7057 13:08:44.828351 CBT Training : PASS
7058 13:08:44.831631 Write leveling : PASS
7059 13:08:44.835170 RX DQS gating : PASS
7060 13:08:44.835238 RX DQ/DQS(RDDQC) : PASS
7061 13:08:44.838205 TX DQ/DQS : PASS
7062 13:08:44.841747 RX DATLAT : PASS
7063 13:08:44.841823 RX DQ/DQS(Engine): PASS
7064 13:08:44.844732 TX OE : NO K
7065 13:08:44.844811 All Pass.
7066 13:08:44.844871
7067 13:08:44.848232 CH 1, Rank 1
7068 13:08:44.848320 SW Impedance : PASS
7069 13:08:44.851523 DUTY Scan : NO K
7070 13:08:44.854673 ZQ Calibration : PASS
7071 13:08:44.854747 Jitter Meter : NO K
7072 13:08:44.858180 CBT Training : PASS
7073 13:08:44.858248 Write leveling : NO K
7074 13:08:44.861650 RX DQS gating : PASS
7075 13:08:44.864810 RX DQ/DQS(RDDQC) : PASS
7076 13:08:44.864888 TX DQ/DQS : PASS
7077 13:08:44.868567 RX DATLAT : PASS
7078 13:08:44.871579 RX DQ/DQS(Engine): PASS
7079 13:08:44.871654 TX OE : NO K
7080 13:08:44.874692 All Pass.
7081 13:08:44.874763
7082 13:08:44.874824 DramC Write-DBI off
7083 13:08:44.878042 PER_BANK_REFRESH: Hybrid Mode
7084 13:08:44.881563 TX_TRACKING: ON
7085 13:08:44.888125 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7086 13:08:44.891945 [FAST_K] Save calibration result to emmc
7087 13:08:44.894933 dramc_set_vcore_voltage set vcore to 725000
7088 13:08:44.898178 Read voltage for 1600, 0
7089 13:08:44.898273 Vio18 = 0
7090 13:08:44.901159 Vcore = 725000
7091 13:08:44.901229 Vdram = 0
7092 13:08:44.901290 Vddq = 0
7093 13:08:44.904697 Vmddr = 0
7094 13:08:44.908271 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7095 13:08:44.914981 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7096 13:08:44.915061 MEM_TYPE=3, freq_sel=13
7097 13:08:44.918078 sv_algorithm_assistance_LP4_3733
7098 13:08:44.925112 ============ PULL DRAM RESETB DOWN ============
7099 13:08:44.927860 ========== PULL DRAM RESETB DOWN end =========
7100 13:08:44.931057 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7101 13:08:44.934641 ===================================
7102 13:08:44.937971 LPDDR4 DRAM CONFIGURATION
7103 13:08:44.941977 ===================================
7104 13:08:44.944484 EX_ROW_EN[0] = 0x0
7105 13:08:44.944561 EX_ROW_EN[1] = 0x0
7106 13:08:44.947919 LP4Y_EN = 0x0
7107 13:08:44.948024 WORK_FSP = 0x1
7108 13:08:44.951532 WL = 0x5
7109 13:08:44.951622 RL = 0x5
7110 13:08:44.955003 BL = 0x2
7111 13:08:44.955104 RPST = 0x0
7112 13:08:44.958165 RD_PRE = 0x0
7113 13:08:44.958242 WR_PRE = 0x1
7114 13:08:44.961103 WR_PST = 0x1
7115 13:08:44.961192 DBI_WR = 0x0
7116 13:08:44.964483 DBI_RD = 0x0
7117 13:08:44.964553 OTF = 0x1
7118 13:08:44.968283 ===================================
7119 13:08:44.971348 ===================================
7120 13:08:44.975300 ANA top config
7121 13:08:44.977989 ===================================
7122 13:08:44.978067 DLL_ASYNC_EN = 0
7123 13:08:44.981428 ALL_SLAVE_EN = 0
7124 13:08:44.984814 NEW_RANK_MODE = 1
7125 13:08:44.988278 DLL_IDLE_MODE = 1
7126 13:08:44.991400 LP45_APHY_COMB_EN = 1
7127 13:08:44.991477 TX_ODT_DIS = 0
7128 13:08:44.994680 NEW_8X_MODE = 1
7129 13:08:44.998120 ===================================
7130 13:08:45.001538 ===================================
7131 13:08:45.004806 data_rate = 3200
7132 13:08:45.008294 CKR = 1
7133 13:08:45.011397 DQ_P2S_RATIO = 8
7134 13:08:45.014708 ===================================
7135 13:08:45.014786 CA_P2S_RATIO = 8
7136 13:08:45.017855 DQ_CA_OPEN = 0
7137 13:08:45.021104 DQ_SEMI_OPEN = 0
7138 13:08:45.024903 CA_SEMI_OPEN = 0
7139 13:08:45.027778 CA_FULL_RATE = 0
7140 13:08:45.031428 DQ_CKDIV4_EN = 0
7141 13:08:45.031507 CA_CKDIV4_EN = 0
7142 13:08:45.034581 CA_PREDIV_EN = 0
7143 13:08:45.038072 PH8_DLY = 12
7144 13:08:45.041705 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7145 13:08:45.044525 DQ_AAMCK_DIV = 4
7146 13:08:45.048010 CA_AAMCK_DIV = 4
7147 13:08:45.048110 CA_ADMCK_DIV = 4
7148 13:08:45.051596 DQ_TRACK_CA_EN = 0
7149 13:08:45.054557 CA_PICK = 1600
7150 13:08:45.058035 CA_MCKIO = 1600
7151 13:08:45.061280 MCKIO_SEMI = 0
7152 13:08:45.064674 PLL_FREQ = 3068
7153 13:08:45.067787 DQ_UI_PI_RATIO = 32
7154 13:08:45.067863 CA_UI_PI_RATIO = 0
7155 13:08:45.071523 ===================================
7156 13:08:45.074368 ===================================
7157 13:08:45.077874 memory_type:LPDDR4
7158 13:08:45.081111 GP_NUM : 10
7159 13:08:45.081258 SRAM_EN : 1
7160 13:08:45.084724 MD32_EN : 0
7161 13:08:45.088023 ===================================
7162 13:08:45.091182 [ANA_INIT] >>>>>>>>>>>>>>
7163 13:08:45.094442 <<<<<< [CONFIGURE PHASE]: ANA_TX
7164 13:08:45.097780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7165 13:08:45.101082 ===================================
7166 13:08:45.101207 data_rate = 3200,PCW = 0X7600
7167 13:08:45.104741 ===================================
7168 13:08:45.107942 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7169 13:08:45.114817 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7170 13:08:45.121340 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7171 13:08:45.124288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7172 13:08:45.127810 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7173 13:08:45.131344 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7174 13:08:45.134567 [ANA_INIT] flow start
7175 13:08:45.134644 [ANA_INIT] PLL >>>>>>>>
7176 13:08:45.137949 [ANA_INIT] PLL <<<<<<<<
7177 13:08:45.141345 [ANA_INIT] MIDPI >>>>>>>>
7178 13:08:45.144261 [ANA_INIT] MIDPI <<<<<<<<
7179 13:08:45.144337 [ANA_INIT] DLL >>>>>>>>
7180 13:08:45.147703 [ANA_INIT] DLL <<<<<<<<
7181 13:08:45.147803 [ANA_INIT] flow end
7182 13:08:45.154491 ============ LP4 DIFF to SE enter ============
7183 13:08:45.158047 ============ LP4 DIFF to SE exit ============
7184 13:08:45.161135 [ANA_INIT] <<<<<<<<<<<<<
7185 13:08:45.164792 [Flow] Enable top DCM control >>>>>
7186 13:08:45.168002 [Flow] Enable top DCM control <<<<<
7187 13:08:45.171096 Enable DLL master slave shuffle
7188 13:08:45.174497 ==============================================================
7189 13:08:45.178237 Gating Mode config
7190 13:08:45.181196 ==============================================================
7191 13:08:45.184502 Config description:
7192 13:08:45.194448 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7193 13:08:45.201383 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7194 13:08:45.204255 SELPH_MODE 0: By rank 1: By Phase
7195 13:08:45.211356 ==============================================================
7196 13:08:45.214324 GAT_TRACK_EN = 1
7197 13:08:45.217357 RX_GATING_MODE = 2
7198 13:08:45.220979 RX_GATING_TRACK_MODE = 2
7199 13:08:45.224412 SELPH_MODE = 1
7200 13:08:45.227383 PICG_EARLY_EN = 1
7201 13:08:45.227460 VALID_LAT_VALUE = 1
7202 13:08:45.234368 ==============================================================
7203 13:08:45.237264 Enter into Gating configuration >>>>
7204 13:08:45.241006 Exit from Gating configuration <<<<
7205 13:08:45.244203 Enter into DVFS_PRE_config >>>>>
7206 13:08:45.254173 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7207 13:08:45.257379 Exit from DVFS_PRE_config <<<<<
7208 13:08:45.260513 Enter into PICG configuration >>>>
7209 13:08:45.264040 Exit from PICG configuration <<<<
7210 13:08:45.267589 [RX_INPUT] configuration >>>>>
7211 13:08:45.270478 [RX_INPUT] configuration <<<<<
7212 13:08:45.273895 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7213 13:08:45.280893 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7214 13:08:45.287262 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7215 13:08:45.293843 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7216 13:08:45.300712 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7217 13:08:45.307448 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7218 13:08:45.310631 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7219 13:08:45.314169 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7220 13:08:45.317742 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7221 13:08:45.321230 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7222 13:08:45.327382 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7223 13:08:45.330634 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7224 13:08:45.333786 ===================================
7225 13:08:45.337022 LPDDR4 DRAM CONFIGURATION
7226 13:08:45.340753 ===================================
7227 13:08:45.340830 EX_ROW_EN[0] = 0x0
7228 13:08:45.343746 EX_ROW_EN[1] = 0x0
7229 13:08:45.343821 LP4Y_EN = 0x0
7230 13:08:45.347537 WORK_FSP = 0x1
7231 13:08:45.347613 WL = 0x5
7232 13:08:45.350655 RL = 0x5
7233 13:08:45.350731 BL = 0x2
7234 13:08:45.354631 RPST = 0x0
7235 13:08:45.354707 RD_PRE = 0x0
7236 13:08:45.357333 WR_PRE = 0x1
7237 13:08:45.357411 WR_PST = 0x1
7238 13:08:45.360839 DBI_WR = 0x0
7239 13:08:45.360916 DBI_RD = 0x0
7240 13:08:45.364309 OTF = 0x1
7241 13:08:45.367500 ===================================
7242 13:08:45.370676 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7243 13:08:45.373906 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7244 13:08:45.380930 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7245 13:08:45.383894 ===================================
7246 13:08:45.383972 LPDDR4 DRAM CONFIGURATION
7247 13:08:45.387550 ===================================
7248 13:08:45.390968 EX_ROW_EN[0] = 0x10
7249 13:08:45.394007 EX_ROW_EN[1] = 0x0
7250 13:08:45.394084 LP4Y_EN = 0x0
7251 13:08:45.397956 WORK_FSP = 0x1
7252 13:08:45.398032 WL = 0x5
7253 13:08:45.400995 RL = 0x5
7254 13:08:45.401070 BL = 0x2
7255 13:08:45.404190 RPST = 0x0
7256 13:08:45.404265 RD_PRE = 0x0
7257 13:08:45.407782 WR_PRE = 0x1
7258 13:08:45.407858 WR_PST = 0x1
7259 13:08:45.410752 DBI_WR = 0x0
7260 13:08:45.410828 DBI_RD = 0x0
7261 13:08:45.414153 OTF = 0x1
7262 13:08:45.417474 ===================================
7263 13:08:45.424375 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7264 13:08:45.424452 ==
7265 13:08:45.427987 Dram Type= 6, Freq= 0, CH_0, rank 0
7266 13:08:45.430964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7267 13:08:45.431042 ==
7268 13:08:45.434689 [Duty_Offset_Calibration]
7269 13:08:45.434765 B0:2 B1:0 CA:1
7270 13:08:45.434824
7271 13:08:45.437417 [DutyScan_Calibration_Flow] k_type=0
7272 13:08:45.447052
7273 13:08:45.447127 ==CLK 0==
7274 13:08:45.450423 Final CLK duty delay cell = -4
7275 13:08:45.454100 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7276 13:08:45.457342 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7277 13:08:45.460459 [-4] AVG Duty = 4906%(X100)
7278 13:08:45.460534
7279 13:08:45.463841 CH0 CLK Duty spec in!! Max-Min= 187%
7280 13:08:45.467256 [DutyScan_Calibration_Flow] ====Done====
7281 13:08:45.467332
7282 13:08:45.470374 [DutyScan_Calibration_Flow] k_type=1
7283 13:08:45.486630
7284 13:08:45.486706 ==DQS 0 ==
7285 13:08:45.489724 Final DQS duty delay cell = 0
7286 13:08:45.493419 [0] MAX Duty = 5249%(X100), DQS PI = 32
7287 13:08:45.496941 [0] MIN Duty = 4969%(X100), DQS PI = 0
7288 13:08:45.500425 [0] AVG Duty = 5109%(X100)
7289 13:08:45.500501
7290 13:08:45.500561 ==DQS 1 ==
7291 13:08:45.503592 Final DQS duty delay cell = -4
7292 13:08:45.506640 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7293 13:08:45.509701 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7294 13:08:45.512943 [-4] AVG Duty = 4969%(X100)
7295 13:08:45.513019
7296 13:08:45.516567 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7297 13:08:45.516644
7298 13:08:45.520375 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7299 13:08:45.523679 [DutyScan_Calibration_Flow] ====Done====
7300 13:08:45.523755
7301 13:08:45.526568 [DutyScan_Calibration_Flow] k_type=3
7302 13:08:45.544195
7303 13:08:45.544312 ==DQM 0 ==
7304 13:08:45.547250 Final DQM duty delay cell = 0
7305 13:08:45.550624 [0] MAX Duty = 5062%(X100), DQS PI = 10
7306 13:08:45.553863 [0] MIN Duty = 4813%(X100), DQS PI = 50
7307 13:08:45.557122 [0] AVG Duty = 4937%(X100)
7308 13:08:45.557288
7309 13:08:45.557352 ==DQM 1 ==
7310 13:08:45.560725 Final DQM duty delay cell = 0
7311 13:08:45.563893 [0] MAX Duty = 5249%(X100), DQS PI = 28
7312 13:08:45.567225 [0] MIN Duty = 5000%(X100), DQS PI = 20
7313 13:08:45.570692 [0] AVG Duty = 5124%(X100)
7314 13:08:45.570831
7315 13:08:45.573654 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7316 13:08:45.573793
7317 13:08:45.576967 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7318 13:08:45.580572 [DutyScan_Calibration_Flow] ====Done====
7319 13:08:45.580680
7320 13:08:45.583698 [DutyScan_Calibration_Flow] k_type=2
7321 13:08:45.600960
7322 13:08:45.601069 ==DQ 0 ==
7323 13:08:45.604746 Final DQ duty delay cell = 0
7324 13:08:45.607816 [0] MAX Duty = 5124%(X100), DQS PI = 36
7325 13:08:45.611183 [0] MIN Duty = 5000%(X100), DQS PI = 0
7326 13:08:45.611277 [0] AVG Duty = 5062%(X100)
7327 13:08:45.613975
7328 13:08:45.614056 ==DQ 1 ==
7329 13:08:45.617573 Final DQ duty delay cell = 0
7330 13:08:45.621098 [0] MAX Duty = 4969%(X100), DQS PI = 52
7331 13:08:45.624440 [0] MIN Duty = 4875%(X100), DQS PI = 10
7332 13:08:45.624540 [0] AVG Duty = 4922%(X100)
7333 13:08:45.627865
7334 13:08:45.631047 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7335 13:08:45.631140
7336 13:08:45.634301 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7337 13:08:45.637482 [DutyScan_Calibration_Flow] ====Done====
7338 13:08:45.637550 ==
7339 13:08:45.640923 Dram Type= 6, Freq= 0, CH_1, rank 0
7340 13:08:45.644117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7341 13:08:45.644190 ==
7342 13:08:45.647220 [Duty_Offset_Calibration]
7343 13:08:45.647298 B0:0 B1:-1 CA:2
7344 13:08:45.647356
7345 13:08:45.650731 [DutyScan_Calibration_Flow] k_type=0
7346 13:08:45.661339
7347 13:08:45.661416 ==CLK 0==
7348 13:08:45.664553 Final CLK duty delay cell = 0
7349 13:08:45.668296 [0] MAX Duty = 5156%(X100), DQS PI = 42
7350 13:08:45.671185 [0] MIN Duty = 4906%(X100), DQS PI = 12
7351 13:08:45.671284 [0] AVG Duty = 5031%(X100)
7352 13:08:45.674536
7353 13:08:45.678080 CH1 CLK Duty spec in!! Max-Min= 250%
7354 13:08:45.681104 [DutyScan_Calibration_Flow] ====Done====
7355 13:08:45.681191
7356 13:08:45.684499 [DutyScan_Calibration_Flow] k_type=1
7357 13:08:45.700934
7358 13:08:45.701036 ==DQS 0 ==
7359 13:08:45.704542 Final DQS duty delay cell = 0
7360 13:08:45.707759 [0] MAX Duty = 5062%(X100), DQS PI = 8
7361 13:08:45.711197 [0] MIN Duty = 4969%(X100), DQS PI = 50
7362 13:08:45.711301 [0] AVG Duty = 5015%(X100)
7363 13:08:45.714422
7364 13:08:45.714517 ==DQS 1 ==
7365 13:08:45.717630 Final DQS duty delay cell = 0
7366 13:08:45.721048 [0] MAX Duty = 5187%(X100), DQS PI = 26
7367 13:08:45.724223 [0] MIN Duty = 4844%(X100), DQS PI = 0
7368 13:08:45.724295 [0] AVG Duty = 5015%(X100)
7369 13:08:45.727614
7370 13:08:45.731177 CH1 DQS 0 Duty spec in!! Max-Min= 93%
7371 13:08:45.731269
7372 13:08:45.734148 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7373 13:08:45.737923 [DutyScan_Calibration_Flow] ====Done====
7374 13:08:45.738018
7375 13:08:45.740679 [DutyScan_Calibration_Flow] k_type=3
7376 13:08:45.758851
7377 13:08:45.758948 ==DQM 0 ==
7378 13:08:45.761731 Final DQM duty delay cell = 4
7379 13:08:45.765346 [4] MAX Duty = 5156%(X100), DQS PI = 24
7380 13:08:45.768469 [4] MIN Duty = 4969%(X100), DQS PI = 0
7381 13:08:45.768534 [4] AVG Duty = 5062%(X100)
7382 13:08:45.772452
7383 13:08:45.772518 ==DQM 1 ==
7384 13:08:45.775464 Final DQM duty delay cell = 0
7385 13:08:45.778597 [0] MAX Duty = 5312%(X100), DQS PI = 26
7386 13:08:45.781783 [0] MIN Duty = 4907%(X100), DQS PI = 2
7387 13:08:45.781853 [0] AVG Duty = 5109%(X100)
7388 13:08:45.785014
7389 13:08:45.788512 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7390 13:08:45.788606
7391 13:08:45.791915 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7392 13:08:45.795219 [DutyScan_Calibration_Flow] ====Done====
7393 13:08:45.795322
7394 13:08:45.798511 [DutyScan_Calibration_Flow] k_type=2
7395 13:08:45.815593
7396 13:08:45.815691 ==DQ 0 ==
7397 13:08:45.818551 Final DQ duty delay cell = 0
7398 13:08:45.821958 [0] MAX Duty = 5093%(X100), DQS PI = 24
7399 13:08:45.825276 [0] MIN Duty = 4938%(X100), DQS PI = 0
7400 13:08:45.825348 [0] AVG Duty = 5015%(X100)
7401 13:08:45.825407
7402 13:08:45.828457 ==DQ 1 ==
7403 13:08:45.831793 Final DQ duty delay cell = 0
7404 13:08:45.835124 [0] MAX Duty = 5094%(X100), DQS PI = 34
7405 13:08:45.838634 [0] MIN Duty = 4813%(X100), DQS PI = 0
7406 13:08:45.838699 [0] AVG Duty = 4953%(X100)
7407 13:08:45.838755
7408 13:08:45.842050 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7409 13:08:45.842121
7410 13:08:45.848235 CH1 DQ 1 Duty spec in!! Max-Min= 281%
7411 13:08:45.851889 [DutyScan_Calibration_Flow] ====Done====
7412 13:08:45.854893 nWR fixed to 30
7413 13:08:45.854992 [ModeRegInit_LP4] CH0 RK0
7414 13:08:45.858338 [ModeRegInit_LP4] CH0 RK1
7415 13:08:45.861852 [ModeRegInit_LP4] CH1 RK0
7416 13:08:45.861946 [ModeRegInit_LP4] CH1 RK1
7417 13:08:45.864923 match AC timing 5
7418 13:08:45.868329 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7419 13:08:45.871443 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7420 13:08:45.878340 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7421 13:08:45.881700 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7422 13:08:45.888189 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7423 13:08:45.888270 [MiockJmeterHQA]
7424 13:08:45.888330
7425 13:08:45.891730 [DramcMiockJmeter] u1RxGatingPI = 0
7426 13:08:45.894798 0 : 4252, 4027
7427 13:08:45.894876 4 : 4255, 4030
7428 13:08:45.894937 8 : 4255, 4029
7429 13:08:45.898087 12 : 4257, 4030
7430 13:08:45.898164 16 : 4252, 4027
7431 13:08:45.901942 20 : 4252, 4027
7432 13:08:45.902019 24 : 4252, 4027
7433 13:08:45.905000 28 : 4363, 4138
7434 13:08:45.905077 32 : 4253, 4026
7435 13:08:45.908009 36 : 4252, 4027
7436 13:08:45.908087 40 : 4253, 4026
7437 13:08:45.908147 44 : 4255, 4029
7438 13:08:45.911709 48 : 4255, 4030
7439 13:08:45.911787 52 : 4363, 4137
7440 13:08:45.914814 56 : 4363, 4138
7441 13:08:45.914894 60 : 4366, 4140
7442 13:08:45.918135 64 : 4253, 4029
7443 13:08:45.918212 68 : 4252, 4030
7444 13:08:45.921496 72 : 4250, 4027
7445 13:08:45.921574 76 : 4250, 4027
7446 13:08:45.921634 80 : 4360, 4137
7447 13:08:45.924511 84 : 4250, 4026
7448 13:08:45.924588 88 : 4249, 3730
7449 13:08:45.928030 92 : 4250, 0
7450 13:08:45.928107 96 : 4252, 0
7451 13:08:45.928167 100 : 4253, 0
7452 13:08:45.931527 104 : 4250, 0
7453 13:08:45.931604 108 : 4250, 0
7454 13:08:45.934604 112 : 4251, 0
7455 13:08:45.934681 116 : 4253, 0
7456 13:08:45.934741 120 : 4250, 0
7457 13:08:45.938070 124 : 4250, 0
7458 13:08:45.938147 128 : 4250, 0
7459 13:08:45.941345 132 : 4361, 0
7460 13:08:45.941422 136 : 4365, 0
7461 13:08:45.941481 140 : 4363, 0
7462 13:08:45.944571 144 : 4250, 0
7463 13:08:45.944648 148 : 4361, 0
7464 13:08:45.944708 152 : 4249, 0
7465 13:08:45.947877 156 : 4250, 0
7466 13:08:45.947953 160 : 4250, 0
7467 13:08:45.951272 164 : 4250, 0
7468 13:08:45.951349 168 : 4252, 0
7469 13:08:45.951410 172 : 4250, 0
7470 13:08:45.954605 176 : 4250, 0
7471 13:08:45.954682 180 : 4250, 0
7472 13:08:45.957940 184 : 4361, 0
7473 13:08:45.958016 188 : 4365, 0
7474 13:08:45.958076 192 : 4363, 0
7475 13:08:45.961493 196 : 4250, 0
7476 13:08:45.961570 200 : 4361, 9
7477 13:08:45.964746 204 : 4249, 2386
7478 13:08:45.964823 208 : 4360, 4137
7479 13:08:45.968448 212 : 4360, 4137
7480 13:08:45.968525 216 : 4250, 4027
7481 13:08:45.968586 220 : 4250, 4027
7482 13:08:45.971691 224 : 4251, 4027
7483 13:08:45.971768 228 : 4250, 4026
7484 13:08:45.975105 232 : 4250, 4026
7485 13:08:45.975183 236 : 4361, 4137
7486 13:08:45.978004 240 : 4249, 4027
7487 13:08:45.978081 244 : 4250, 4026
7488 13:08:45.981109 248 : 4250, 4026
7489 13:08:45.981214 252 : 4250, 4027
7490 13:08:45.984454 256 : 4250, 4027
7491 13:08:45.984531 260 : 4361, 4137
7492 13:08:45.987991 264 : 4360, 4137
7493 13:08:45.988095 268 : 4250, 4027
7494 13:08:45.991139 272 : 4250, 4027
7495 13:08:45.991231 276 : 4249, 4027
7496 13:08:45.991318 280 : 4250, 4027
7497 13:08:45.994763 284 : 4250, 4027
7498 13:08:45.994855 288 : 4363, 4140
7499 13:08:45.997989 292 : 4250, 4027
7500 13:08:45.998084 296 : 4250, 4027
7501 13:08:46.001711 300 : 4363, 4140
7502 13:08:46.001814 304 : 4250, 4026
7503 13:08:46.004607 308 : 4250, 4027
7504 13:08:46.004712 312 : 4360, 4074
7505 13:08:46.007957 316 : 4360, 2123
7506 13:08:46.008052
7507 13:08:46.008134 MIOCK jitter meter ch=0
7508 13:08:46.008214
7509 13:08:46.011486 1T = (316-92) = 224 dly cells
7510 13:08:46.017698 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7511 13:08:46.017776 ==
7512 13:08:46.021053 Dram Type= 6, Freq= 0, CH_0, rank 0
7513 13:08:46.024800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7514 13:08:46.024877 ==
7515 13:08:46.031347 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7516 13:08:46.034430 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7517 13:08:46.037907 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7518 13:08:46.044224 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7519 13:08:46.054146 [CA 0] Center 42 (13~72) winsize 60
7520 13:08:46.057335 [CA 1] Center 42 (12~72) winsize 61
7521 13:08:46.060614 [CA 2] Center 37 (8~67) winsize 60
7522 13:08:46.063994 [CA 3] Center 37 (7~67) winsize 61
7523 13:08:46.067323 [CA 4] Center 35 (5~66) winsize 62
7524 13:08:46.071166 [CA 5] Center 35 (5~65) winsize 61
7525 13:08:46.071243
7526 13:08:46.074423 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7527 13:08:46.074499
7528 13:08:46.077307 [CATrainingPosCal] consider 1 rank data
7529 13:08:46.080717 u2DelayCellTimex100 = 290/100 ps
7530 13:08:46.084367 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7531 13:08:46.090892 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7532 13:08:46.094155 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7533 13:08:46.097586 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7534 13:08:46.100821 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7535 13:08:46.104174 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7536 13:08:46.104240
7537 13:08:46.107175 CA PerBit enable=1, Macro0, CA PI delay=35
7538 13:08:46.107243
7539 13:08:46.110868 [CBTSetCACLKResult] CA Dly = 35
7540 13:08:46.110936 CS Dly: 9 (0~40)
7541 13:08:46.117621 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7542 13:08:46.120741 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7543 13:08:46.120811 ==
7544 13:08:46.124167 Dram Type= 6, Freq= 0, CH_0, rank 1
7545 13:08:46.127123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 13:08:46.127188 ==
7547 13:08:46.134043 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7548 13:08:46.137318 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7549 13:08:46.144047 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7550 13:08:46.147230 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7551 13:08:46.157599 [CA 0] Center 43 (13~73) winsize 61
7552 13:08:46.160813 [CA 1] Center 43 (13~73) winsize 61
7553 13:08:46.163790 [CA 2] Center 37 (8~67) winsize 60
7554 13:08:46.167360 [CA 3] Center 38 (8~68) winsize 61
7555 13:08:46.170918 [CA 4] Center 36 (6~66) winsize 61
7556 13:08:46.174109 [CA 5] Center 36 (6~66) winsize 61
7557 13:08:46.174184
7558 13:08:46.177379 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7559 13:08:46.177456
7560 13:08:46.180814 [CATrainingPosCal] consider 2 rank data
7561 13:08:46.183992 u2DelayCellTimex100 = 290/100 ps
7562 13:08:46.187030 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7563 13:08:46.194223 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7564 13:08:46.197305 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7565 13:08:46.200525 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7566 13:08:46.203735 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7567 13:08:46.207119 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7568 13:08:46.207195
7569 13:08:46.210574 CA PerBit enable=1, Macro0, CA PI delay=35
7570 13:08:46.210651
7571 13:08:46.213750 [CBTSetCACLKResult] CA Dly = 35
7572 13:08:46.217291 CS Dly: 10 (0~43)
7573 13:08:46.220665 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7574 13:08:46.223591 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7575 13:08:46.223667
7576 13:08:46.227059 ----->DramcWriteLeveling(PI) begin...
7577 13:08:46.227136 ==
7578 13:08:46.230516 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 13:08:46.233696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 13:08:46.237010 ==
7581 13:08:46.237085 Write leveling (Byte 0): 35 => 35
7582 13:08:46.240608 Write leveling (Byte 1): 32 => 32
7583 13:08:46.244132 DramcWriteLeveling(PI) end<-----
7584 13:08:46.244208
7585 13:08:46.244266 ==
7586 13:08:46.246863 Dram Type= 6, Freq= 0, CH_0, rank 0
7587 13:08:46.253684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7588 13:08:46.253761 ==
7589 13:08:46.253848 [Gating] SW mode calibration
7590 13:08:46.263594 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7591 13:08:46.267095 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7592 13:08:46.270235 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 13:08:46.277497 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 13:08:46.280473 1 4 8 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
7595 13:08:46.283839 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7596 13:08:46.290413 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7597 13:08:46.294090 1 4 20 | B1->B0 | 3231 3434 | 1 1 | (0 0) (1 1)
7598 13:08:46.296822 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7599 13:08:46.303706 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 13:08:46.307084 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7601 13:08:46.310063 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7602 13:08:46.316853 1 5 8 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
7603 13:08:46.320162 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7604 13:08:46.323683 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7605 13:08:46.330336 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
7606 13:08:46.333826 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7607 13:08:46.336807 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 13:08:46.343400 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 13:08:46.347259 1 6 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
7610 13:08:46.350468 1 6 8 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
7611 13:08:46.356895 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7612 13:08:46.360227 1 6 16 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7613 13:08:46.363792 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7614 13:08:46.369902 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 13:08:46.373352 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 13:08:46.376626 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 13:08:46.383780 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7618 13:08:46.386889 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7619 13:08:46.390145 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7620 13:08:46.393333 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7621 13:08:46.400202 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7622 13:08:46.403777 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 13:08:46.406891 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 13:08:46.413463 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 13:08:46.416875 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 13:08:46.420069 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 13:08:46.426835 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 13:08:46.430132 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 13:08:46.433616 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 13:08:46.440101 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 13:08:46.443485 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 13:08:46.447119 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 13:08:46.453337 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 13:08:46.456572 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7635 13:08:46.459807 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7636 13:08:46.466719 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7637 13:08:46.466795 Total UI for P1: 0, mck2ui 16
7638 13:08:46.472974 best dqsien dly found for B0: ( 1, 9, 10)
7639 13:08:46.476608 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7640 13:08:46.479682 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 13:08:46.483515 Total UI for P1: 0, mck2ui 16
7642 13:08:46.486563 best dqsien dly found for B1: ( 1, 9, 20)
7643 13:08:46.490047 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7644 13:08:46.493076 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7645 13:08:46.493177
7646 13:08:46.499672 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7647 13:08:46.503342 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7648 13:08:46.503433 [Gating] SW calibration Done
7649 13:08:46.506162 ==
7650 13:08:46.510002 Dram Type= 6, Freq= 0, CH_0, rank 0
7651 13:08:46.513414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7652 13:08:46.513507 ==
7653 13:08:46.513591 RX Vref Scan: 0
7654 13:08:46.513653
7655 13:08:46.516127 RX Vref 0 -> 0, step: 1
7656 13:08:46.516201
7657 13:08:46.519773 RX Delay 0 -> 252, step: 8
7658 13:08:46.523098 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7659 13:08:46.526186 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7660 13:08:46.530005 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7661 13:08:46.536479 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7662 13:08:46.539700 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7663 13:08:46.543365 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7664 13:08:46.546285 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7665 13:08:46.550044 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7666 13:08:46.553696 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7667 13:08:46.560668 iDelay=200, Bit 9, Center 111 (64 ~ 159) 96
7668 13:08:46.563316 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7669 13:08:46.566925 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7670 13:08:46.569954 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7671 13:08:46.573539 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7672 13:08:46.579991 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7673 13:08:46.583627 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
7674 13:08:46.584190 ==
7675 13:08:46.586559 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 13:08:46.590129 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 13:08:46.590584 ==
7678 13:08:46.593262 DQS Delay:
7679 13:08:46.593926 DQS0 = 0, DQS1 = 0
7680 13:08:46.594566 DQM Delay:
7681 13:08:46.596652 DQM0 = 137, DQM1 = 125
7682 13:08:46.597249 DQ Delay:
7683 13:08:46.599918 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7684 13:08:46.603581 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7685 13:08:46.606812 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
7686 13:08:46.613547 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =131
7687 13:08:46.614007
7688 13:08:46.614402
7689 13:08:46.614913 ==
7690 13:08:46.617200 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 13:08:46.620026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 13:08:46.620597 ==
7693 13:08:46.621092
7694 13:08:46.621545
7695 13:08:46.623567 TX Vref Scan disable
7696 13:08:46.624155 == TX Byte 0 ==
7697 13:08:46.630555 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7698 13:08:46.633516 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7699 13:08:46.633908 == TX Byte 1 ==
7700 13:08:46.640579 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7701 13:08:46.643397 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7702 13:08:46.643804 ==
7703 13:08:46.646672 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 13:08:46.650230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 13:08:46.650652 ==
7706 13:08:46.663765
7707 13:08:46.667130 TX Vref early break, caculate TX vref
7708 13:08:46.670715 TX Vref=16, minBit 8, minWin=22, winSum=376
7709 13:08:46.673805 TX Vref=18, minBit 8, minWin=23, winSum=391
7710 13:08:46.677671 TX Vref=20, minBit 1, minWin=24, winSum=395
7711 13:08:46.680637 TX Vref=22, minBit 12, minWin=24, winSum=409
7712 13:08:46.683579 TX Vref=24, minBit 1, minWin=25, winSum=413
7713 13:08:46.690556 TX Vref=26, minBit 7, minWin=25, winSum=423
7714 13:08:46.693652 TX Vref=28, minBit 2, minWin=26, winSum=428
7715 13:08:46.697362 TX Vref=30, minBit 4, minWin=25, winSum=420
7716 13:08:46.700602 TX Vref=32, minBit 1, minWin=25, winSum=412
7717 13:08:46.703849 TX Vref=34, minBit 8, minWin=24, winSum=403
7718 13:08:46.710574 [TxChooseVref] Worse bit 2, Min win 26, Win sum 428, Final Vref 28
7719 13:08:46.710929
7720 13:08:46.713896 Final TX Range 0 Vref 28
7721 13:08:46.714227
7722 13:08:46.714606 ==
7723 13:08:46.717621 Dram Type= 6, Freq= 0, CH_0, rank 0
7724 13:08:46.720671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7725 13:08:46.721102 ==
7726 13:08:46.721468
7727 13:08:46.721747
7728 13:08:46.724088 TX Vref Scan disable
7729 13:08:46.730346 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7730 13:08:46.730735 == TX Byte 0 ==
7731 13:08:46.733795 u2DelayCellOfst[0]=16 cells (5 PI)
7732 13:08:46.737250 u2DelayCellOfst[1]=20 cells (6 PI)
7733 13:08:46.740420 u2DelayCellOfst[2]=13 cells (4 PI)
7734 13:08:46.743850 u2DelayCellOfst[3]=16 cells (5 PI)
7735 13:08:46.747340 u2DelayCellOfst[4]=13 cells (4 PI)
7736 13:08:46.750539 u2DelayCellOfst[5]=0 cells (0 PI)
7737 13:08:46.753946 u2DelayCellOfst[6]=20 cells (6 PI)
7738 13:08:46.754334 u2DelayCellOfst[7]=16 cells (5 PI)
7739 13:08:46.760286 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7740 13:08:46.763758 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7741 13:08:46.764149 == TX Byte 1 ==
7742 13:08:46.766844 u2DelayCellOfst[8]=0 cells (0 PI)
7743 13:08:46.770634 u2DelayCellOfst[9]=0 cells (0 PI)
7744 13:08:46.773846 u2DelayCellOfst[10]=6 cells (2 PI)
7745 13:08:46.777281 u2DelayCellOfst[11]=3 cells (1 PI)
7746 13:08:46.780560 u2DelayCellOfst[12]=13 cells (4 PI)
7747 13:08:46.783921 u2DelayCellOfst[13]=10 cells (3 PI)
7748 13:08:46.787080 u2DelayCellOfst[14]=13 cells (4 PI)
7749 13:08:46.790454 u2DelayCellOfst[15]=10 cells (3 PI)
7750 13:08:46.793872 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7751 13:08:46.797204 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7752 13:08:46.800208 DramC Write-DBI on
7753 13:08:46.800594 ==
7754 13:08:46.803581 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 13:08:46.806810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 13:08:46.807231 ==
7757 13:08:46.807571
7758 13:08:46.810233
7759 13:08:46.810621 TX Vref Scan disable
7760 13:08:46.813710 == TX Byte 0 ==
7761 13:08:46.816873 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7762 13:08:46.820357 == TX Byte 1 ==
7763 13:08:46.823621 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7764 13:08:46.824056 DramC Write-DBI off
7765 13:08:46.827074
7766 13:08:46.827497 [DATLAT]
7767 13:08:46.827832 Freq=1600, CH0 RK0
7768 13:08:46.828145
7769 13:08:46.830520 DATLAT Default: 0xf
7770 13:08:46.830949 0, 0xFFFF, sum = 0
7771 13:08:46.833600 1, 0xFFFF, sum = 0
7772 13:08:46.834036 2, 0xFFFF, sum = 0
7773 13:08:46.836845 3, 0xFFFF, sum = 0
7774 13:08:46.837321 4, 0xFFFF, sum = 0
7775 13:08:46.840114 5, 0xFFFF, sum = 0
7776 13:08:46.843497 6, 0xFFFF, sum = 0
7777 13:08:46.843933 7, 0xFFFF, sum = 0
7778 13:08:46.846701 8, 0xFFFF, sum = 0
7779 13:08:46.847137 9, 0xFFFF, sum = 0
7780 13:08:46.850614 10, 0xFFFF, sum = 0
7781 13:08:46.851051 11, 0xFFFF, sum = 0
7782 13:08:46.853313 12, 0xFFFF, sum = 0
7783 13:08:46.853710 13, 0xFFFF, sum = 0
7784 13:08:46.856564 14, 0x0, sum = 1
7785 13:08:46.857001 15, 0x0, sum = 2
7786 13:08:46.860269 16, 0x0, sum = 3
7787 13:08:46.860664 17, 0x0, sum = 4
7788 13:08:46.863335 best_step = 15
7789 13:08:46.863721
7790 13:08:46.864035 ==
7791 13:08:46.866826 Dram Type= 6, Freq= 0, CH_0, rank 0
7792 13:08:46.870176 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7793 13:08:46.870567 ==
7794 13:08:46.870870 RX Vref Scan: 1
7795 13:08:46.871151
7796 13:08:46.873387 Set Vref Range= 24 -> 127
7797 13:08:46.873776
7798 13:08:46.876774 RX Vref 24 -> 127, step: 1
7799 13:08:46.877279
7800 13:08:46.880275 RX Delay 19 -> 252, step: 4
7801 13:08:46.880662
7802 13:08:46.883496 Set Vref, RX VrefLevel [Byte0]: 24
7803 13:08:46.886690 [Byte1]: 24
7804 13:08:46.887079
7805 13:08:46.890100 Set Vref, RX VrefLevel [Byte0]: 25
7806 13:08:46.893097 [Byte1]: 25
7807 13:08:46.893517
7808 13:08:46.896665 Set Vref, RX VrefLevel [Byte0]: 26
7809 13:08:46.899823 [Byte1]: 26
7810 13:08:46.903535
7811 13:08:46.903925 Set Vref, RX VrefLevel [Byte0]: 27
7812 13:08:46.906787 [Byte1]: 27
7813 13:08:46.911157
7814 13:08:46.911546 Set Vref, RX VrefLevel [Byte0]: 28
7815 13:08:46.914711 [Byte1]: 28
7816 13:08:46.918638
7817 13:08:46.919025 Set Vref, RX VrefLevel [Byte0]: 29
7818 13:08:46.922352 [Byte1]: 29
7819 13:08:46.926273
7820 13:08:46.926660 Set Vref, RX VrefLevel [Byte0]: 30
7821 13:08:46.929829 [Byte1]: 30
7822 13:08:46.934233
7823 13:08:46.934728 Set Vref, RX VrefLevel [Byte0]: 31
7824 13:08:46.937262 [Byte1]: 31
7825 13:08:46.941553
7826 13:08:46.942031 Set Vref, RX VrefLevel [Byte0]: 32
7827 13:08:46.944985 [Byte1]: 32
7828 13:08:46.949230
7829 13:08:46.949819 Set Vref, RX VrefLevel [Byte0]: 33
7830 13:08:46.952270 [Byte1]: 33
7831 13:08:46.956620
7832 13:08:46.957207 Set Vref, RX VrefLevel [Byte0]: 34
7833 13:08:46.959917 [Byte1]: 34
7834 13:08:46.964274
7835 13:08:46.964663 Set Vref, RX VrefLevel [Byte0]: 35
7836 13:08:46.967551 [Byte1]: 35
7837 13:08:46.971491
7838 13:08:46.971878 Set Vref, RX VrefLevel [Byte0]: 36
7839 13:08:46.975215 [Byte1]: 36
7840 13:08:46.979510
7841 13:08:46.979585 Set Vref, RX VrefLevel [Byte0]: 37
7842 13:08:46.982197 [Byte1]: 37
7843 13:08:46.987107
7844 13:08:46.987182 Set Vref, RX VrefLevel [Byte0]: 38
7845 13:08:46.989970 [Byte1]: 38
7846 13:08:46.994145
7847 13:08:46.994221 Set Vref, RX VrefLevel [Byte0]: 39
7848 13:08:46.997441 [Byte1]: 39
7849 13:08:47.001575
7850 13:08:47.004824 Set Vref, RX VrefLevel [Byte0]: 40
7851 13:08:47.008059 [Byte1]: 40
7852 13:08:47.008135
7853 13:08:47.011676 Set Vref, RX VrefLevel [Byte0]: 41
7854 13:08:47.014745 [Byte1]: 41
7855 13:08:47.014851
7856 13:08:47.018120 Set Vref, RX VrefLevel [Byte0]: 42
7857 13:08:47.021704 [Byte1]: 42
7858 13:08:47.021779
7859 13:08:47.025316 Set Vref, RX VrefLevel [Byte0]: 43
7860 13:08:47.027940 [Byte1]: 43
7861 13:08:47.031749
7862 13:08:47.031824 Set Vref, RX VrefLevel [Byte0]: 44
7863 13:08:47.035243 [Byte1]: 44
7864 13:08:47.039417
7865 13:08:47.039493 Set Vref, RX VrefLevel [Byte0]: 45
7866 13:08:47.042714 [Byte1]: 45
7867 13:08:47.047368
7868 13:08:47.047444 Set Vref, RX VrefLevel [Byte0]: 46
7869 13:08:47.050339 [Byte1]: 46
7870 13:08:47.054606
7871 13:08:47.054682 Set Vref, RX VrefLevel [Byte0]: 47
7872 13:08:47.058359 [Byte1]: 47
7873 13:08:47.062212
7874 13:08:47.062287 Set Vref, RX VrefLevel [Byte0]: 48
7875 13:08:47.065733 [Byte1]: 48
7876 13:08:47.069651
7877 13:08:47.069726 Set Vref, RX VrefLevel [Byte0]: 49
7878 13:08:47.073706 [Byte1]: 49
7879 13:08:47.077167
7880 13:08:47.077243 Set Vref, RX VrefLevel [Byte0]: 50
7881 13:08:47.080569 [Byte1]: 50
7882 13:08:47.084901
7883 13:08:47.084977 Set Vref, RX VrefLevel [Byte0]: 51
7884 13:08:47.088385 [Byte1]: 51
7885 13:08:47.092633
7886 13:08:47.092721 Set Vref, RX VrefLevel [Byte0]: 52
7887 13:08:47.096018 [Byte1]: 52
7888 13:08:47.100066
7889 13:08:47.100150 Set Vref, RX VrefLevel [Byte0]: 53
7890 13:08:47.103212 [Byte1]: 53
7891 13:08:47.107747
7892 13:08:47.107861 Set Vref, RX VrefLevel [Byte0]: 54
7893 13:08:47.110970 [Byte1]: 54
7894 13:08:47.115797
7895 13:08:47.115922 Set Vref, RX VrefLevel [Byte0]: 55
7896 13:08:47.118558 [Byte1]: 55
7897 13:08:47.123193
7898 13:08:47.123353 Set Vref, RX VrefLevel [Byte0]: 56
7899 13:08:47.126155 [Byte1]: 56
7900 13:08:47.130441
7901 13:08:47.130626 Set Vref, RX VrefLevel [Byte0]: 57
7902 13:08:47.133918 [Byte1]: 57
7903 13:08:47.138531
7904 13:08:47.138805 Set Vref, RX VrefLevel [Byte0]: 58
7905 13:08:47.141688 [Byte1]: 58
7906 13:08:47.145779
7907 13:08:47.146132 Set Vref, RX VrefLevel [Byte0]: 59
7908 13:08:47.149030 [Byte1]: 59
7909 13:08:47.153388
7910 13:08:47.153815 Set Vref, RX VrefLevel [Byte0]: 60
7911 13:08:47.156599 [Byte1]: 60
7912 13:08:47.161039
7913 13:08:47.161498 Set Vref, RX VrefLevel [Byte0]: 61
7914 13:08:47.164546 [Byte1]: 61
7915 13:08:47.168525
7916 13:08:47.168951 Set Vref, RX VrefLevel [Byte0]: 62
7917 13:08:47.171884 [Byte1]: 62
7918 13:08:47.176395
7919 13:08:47.176822 Set Vref, RX VrefLevel [Byte0]: 63
7920 13:08:47.179527 [Byte1]: 63
7921 13:08:47.184214
7922 13:08:47.184642 Set Vref, RX VrefLevel [Byte0]: 64
7923 13:08:47.187142 [Byte1]: 64
7924 13:08:47.191573
7925 13:08:47.191999 Set Vref, RX VrefLevel [Byte0]: 65
7926 13:08:47.194514 [Byte1]: 65
7927 13:08:47.199015
7928 13:08:47.199447 Set Vref, RX VrefLevel [Byte0]: 66
7929 13:08:47.202470 [Byte1]: 66
7930 13:08:47.206670
7931 13:08:47.207098 Set Vref, RX VrefLevel [Byte0]: 67
7932 13:08:47.209730 [Byte1]: 67
7933 13:08:47.214101
7934 13:08:47.214538 Set Vref, RX VrefLevel [Byte0]: 68
7935 13:08:47.217762 [Byte1]: 68
7936 13:08:47.221745
7937 13:08:47.222189 Set Vref, RX VrefLevel [Byte0]: 69
7938 13:08:47.224943 [Byte1]: 69
7939 13:08:47.229588
7940 13:08:47.230049 Set Vref, RX VrefLevel [Byte0]: 70
7941 13:08:47.232636 [Byte1]: 70
7942 13:08:47.237054
7943 13:08:47.237571 Set Vref, RX VrefLevel [Byte0]: 71
7944 13:08:47.239953 [Byte1]: 71
7945 13:08:47.244397
7946 13:08:47.244960 Set Vref, RX VrefLevel [Byte0]: 72
7947 13:08:47.247445 [Byte1]: 72
7948 13:08:47.252227
7949 13:08:47.252666 Set Vref, RX VrefLevel [Byte0]: 73
7950 13:08:47.255171 [Byte1]: 73
7951 13:08:47.259376
7952 13:08:47.259847 Set Vref, RX VrefLevel [Byte0]: 74
7953 13:08:47.263214 [Byte1]: 74
7954 13:08:47.266929
7955 13:08:47.267354 Set Vref, RX VrefLevel [Byte0]: 75
7956 13:08:47.270182 [Byte1]: 75
7957 13:08:47.274888
7958 13:08:47.275275 Set Vref, RX VrefLevel [Byte0]: 76
7959 13:08:47.277714 [Byte1]: 76
7960 13:08:47.282225
7961 13:08:47.282572 Set Vref, RX VrefLevel [Byte0]: 77
7962 13:08:47.285271 [Byte1]: 77
7963 13:08:47.289622
7964 13:08:47.289697 Set Vref, RX VrefLevel [Byte0]: 78
7965 13:08:47.293007 [Byte1]: 78
7966 13:08:47.297102
7967 13:08:47.297205 Final RX Vref Byte 0 = 59 to rank0
7968 13:08:47.300426 Final RX Vref Byte 1 = 62 to rank0
7969 13:08:47.303531 Final RX Vref Byte 0 = 59 to rank1
7970 13:08:47.306891 Final RX Vref Byte 1 = 62 to rank1==
7971 13:08:47.310310 Dram Type= 6, Freq= 0, CH_0, rank 0
7972 13:08:47.317016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7973 13:08:47.317117 ==
7974 13:08:47.317203 DQS Delay:
7975 13:08:47.317270 DQS0 = 0, DQS1 = 0
7976 13:08:47.320428 DQM Delay:
7977 13:08:47.320530 DQM0 = 135, DQM1 = 124
7978 13:08:47.323887 DQ Delay:
7979 13:08:47.326802 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
7980 13:08:47.330375 DQ4 =138, DQ5 =124, DQ6 =142, DQ7 =142
7981 13:08:47.333575 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
7982 13:08:47.337033 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =134
7983 13:08:47.337186
7984 13:08:47.337295
7985 13:08:47.337395
7986 13:08:47.340617 [DramC_TX_OE_Calibration] TA2
7987 13:08:47.343608 Original DQ_B0 (3 6) =30, OEN = 27
7988 13:08:47.346769 Original DQ_B1 (3 6) =30, OEN = 27
7989 13:08:47.350386 24, 0x0, End_B0=24 End_B1=24
7990 13:08:47.350611 25, 0x0, End_B0=25 End_B1=25
7991 13:08:47.353707 26, 0x0, End_B0=26 End_B1=26
7992 13:08:47.356926 27, 0x0, End_B0=27 End_B1=27
7993 13:08:47.360521 28, 0x0, End_B0=28 End_B1=28
7994 13:08:47.360891 29, 0x0, End_B0=29 End_B1=29
7995 13:08:47.363842 30, 0x0, End_B0=30 End_B1=30
7996 13:08:47.367122 31, 0x4141, End_B0=30 End_B1=30
7997 13:08:47.370547 Byte0 end_step=30 best_step=27
7998 13:08:47.373618 Byte1 end_step=30 best_step=27
7999 13:08:47.377275 Byte0 TX OE(2T, 0.5T) = (3, 3)
8000 13:08:47.377727 Byte1 TX OE(2T, 0.5T) = (3, 3)
8001 13:08:47.380277
8002 13:08:47.380810
8003 13:08:47.387388 [DQSOSCAuto] RK0, (LSB)MR18= 0x201e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
8004 13:08:47.390418 CH0 RK0: MR19=303, MR18=201E
8005 13:08:47.397168 CH0_RK0: MR19=0x303, MR18=0x201E, DQSOSC=393, MR23=63, INC=23, DEC=15
8006 13:08:47.397610
8007 13:08:47.400313 ----->DramcWriteLeveling(PI) begin...
8008 13:08:47.400760 ==
8009 13:08:47.403702 Dram Type= 6, Freq= 0, CH_0, rank 1
8010 13:08:47.407028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8011 13:08:47.407420 ==
8012 13:08:47.410569 Write leveling (Byte 0): 38 => 38
8013 13:08:47.413483 Write leveling (Byte 1): 29 => 29
8014 13:08:47.417449 DramcWriteLeveling(PI) end<-----
8015 13:08:47.417843
8016 13:08:47.418277 ==
8017 13:08:47.420365 Dram Type= 6, Freq= 0, CH_0, rank 1
8018 13:08:47.423559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8019 13:08:47.423955 ==
8020 13:08:47.427104 [Gating] SW mode calibration
8021 13:08:47.433551 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8022 13:08:47.440356 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8023 13:08:47.443798 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 13:08:47.446946 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 13:08:47.453432 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 13:08:47.456751 1 4 12 | B1->B0 | 2727 3333 | 1 1 | (1 1) (1 1)
8027 13:08:47.460129 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 13:08:47.466932 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8029 13:08:47.470583 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8030 13:08:47.473877 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8031 13:08:47.479974 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8032 13:08:47.483653 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8033 13:08:47.487003 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8034 13:08:47.493389 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
8035 13:08:47.497163 1 5 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8036 13:08:47.500087 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 13:08:47.506980 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 13:08:47.510058 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 13:08:47.513588 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 13:08:47.520130 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 13:08:47.523798 1 6 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8042 13:08:47.526690 1 6 12 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8043 13:08:47.530466 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 13:08:47.536895 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 13:08:47.539987 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 13:08:47.543507 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8047 13:08:47.550571 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 13:08:47.553436 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8049 13:08:47.556823 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8050 13:08:47.563838 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8051 13:08:47.566508 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8052 13:08:47.570389 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 13:08:47.577115 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 13:08:47.580330 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 13:08:47.583473 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 13:08:47.589951 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 13:08:47.593476 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 13:08:47.596696 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 13:08:47.603110 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 13:08:47.606675 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 13:08:47.609651 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 13:08:47.616458 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 13:08:47.619810 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 13:08:47.623457 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 13:08:47.629630 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 13:08:47.633069 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8067 13:08:47.636238 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8068 13:08:47.639646 Total UI for P1: 0, mck2ui 16
8069 13:08:47.642711 best dqsien dly found for B0: ( 1, 9, 12)
8070 13:08:47.646543 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 13:08:47.649566 Total UI for P1: 0, mck2ui 16
8072 13:08:47.652814 best dqsien dly found for B1: ( 1, 9, 14)
8073 13:08:47.656328 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8074 13:08:47.663076 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8075 13:08:47.663308
8076 13:08:47.666330 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8077 13:08:47.669568 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8078 13:08:47.673260 [Gating] SW calibration Done
8079 13:08:47.673519 ==
8080 13:08:47.676541 Dram Type= 6, Freq= 0, CH_0, rank 1
8081 13:08:47.679913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8082 13:08:47.680095 ==
8083 13:08:47.682829 RX Vref Scan: 0
8084 13:08:47.682998
8085 13:08:47.683128 RX Vref 0 -> 0, step: 1
8086 13:08:47.683249
8087 13:08:47.686132 RX Delay 0 -> 252, step: 8
8088 13:08:47.689731 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8089 13:08:47.692666 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8090 13:08:47.699184 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8091 13:08:47.703209 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8092 13:08:47.706300 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8093 13:08:47.709374 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8094 13:08:47.712778 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8095 13:08:47.719523 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8096 13:08:47.723081 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8097 13:08:47.726029 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8098 13:08:47.729519 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8099 13:08:47.732894 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8100 13:08:47.739255 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8101 13:08:47.742605 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8102 13:08:47.745906 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8103 13:08:47.749906 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8104 13:08:47.749974 ==
8105 13:08:47.752668 Dram Type= 6, Freq= 0, CH_0, rank 1
8106 13:08:47.759336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8107 13:08:47.759411 ==
8108 13:08:47.759472 DQS Delay:
8109 13:08:47.759530 DQS0 = 0, DQS1 = 0
8110 13:08:47.762430 DQM Delay:
8111 13:08:47.762495 DQM0 = 136, DQM1 = 124
8112 13:08:47.765759 DQ Delay:
8113 13:08:47.769358 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8114 13:08:47.773271 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8115 13:08:47.775906 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
8116 13:08:47.779471 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8117 13:08:47.779535
8118 13:08:47.779590
8119 13:08:47.779643 ==
8120 13:08:47.782525 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 13:08:47.786202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 13:08:47.789248 ==
8123 13:08:47.789312
8124 13:08:47.789366
8125 13:08:47.789417 TX Vref Scan disable
8126 13:08:47.792912 == TX Byte 0 ==
8127 13:08:47.795948 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8128 13:08:47.799327 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8129 13:08:47.802683 == TX Byte 1 ==
8130 13:08:47.805748 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8131 13:08:47.809091 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8132 13:08:47.809180 ==
8133 13:08:47.812716 Dram Type= 6, Freq= 0, CH_0, rank 1
8134 13:08:47.819047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8135 13:08:47.819146 ==
8136 13:08:47.833068
8137 13:08:47.836970 TX Vref early break, caculate TX vref
8138 13:08:47.840153 TX Vref=16, minBit 0, minWin=23, winSum=388
8139 13:08:47.843166 TX Vref=18, minBit 0, minWin=24, winSum=400
8140 13:08:47.846339 TX Vref=20, minBit 1, minWin=24, winSum=407
8141 13:08:47.849718 TX Vref=22, minBit 0, minWin=25, winSum=418
8142 13:08:47.853250 TX Vref=24, minBit 3, minWin=25, winSum=423
8143 13:08:47.860012 TX Vref=26, minBit 0, minWin=26, winSum=430
8144 13:08:47.863237 TX Vref=28, minBit 0, minWin=26, winSum=431
8145 13:08:47.866523 TX Vref=30, minBit 0, minWin=26, winSum=425
8146 13:08:47.869881 TX Vref=32, minBit 0, minWin=25, winSum=421
8147 13:08:47.873040 TX Vref=34, minBit 4, minWin=24, winSum=410
8148 13:08:47.876631 TX Vref=36, minBit 2, minWin=24, winSum=402
8149 13:08:47.882882 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
8150 13:08:47.882964
8151 13:08:47.886762 Final TX Range 0 Vref 28
8152 13:08:47.886827
8153 13:08:47.886882 ==
8154 13:08:47.889645 Dram Type= 6, Freq= 0, CH_0, rank 1
8155 13:08:47.893364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8156 13:08:47.893429 ==
8157 13:08:47.893483
8158 13:08:47.893532
8159 13:08:47.896761 TX Vref Scan disable
8160 13:08:47.903354 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8161 13:08:47.903418 == TX Byte 0 ==
8162 13:08:47.906241 u2DelayCellOfst[0]=13 cells (4 PI)
8163 13:08:47.909508 u2DelayCellOfst[1]=20 cells (6 PI)
8164 13:08:47.912959 u2DelayCellOfst[2]=13 cells (4 PI)
8165 13:08:47.916191 u2DelayCellOfst[3]=13 cells (4 PI)
8166 13:08:47.919790 u2DelayCellOfst[4]=10 cells (3 PI)
8167 13:08:47.922875 u2DelayCellOfst[5]=0 cells (0 PI)
8168 13:08:47.926235 u2DelayCellOfst[6]=20 cells (6 PI)
8169 13:08:47.929678 u2DelayCellOfst[7]=20 cells (6 PI)
8170 13:08:47.932780 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8171 13:08:47.936054 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8172 13:08:47.940009 == TX Byte 1 ==
8173 13:08:47.942969 u2DelayCellOfst[8]=0 cells (0 PI)
8174 13:08:47.946513 u2DelayCellOfst[9]=3 cells (1 PI)
8175 13:08:47.946597 u2DelayCellOfst[10]=6 cells (2 PI)
8176 13:08:47.949371 u2DelayCellOfst[11]=3 cells (1 PI)
8177 13:08:47.952827 u2DelayCellOfst[12]=13 cells (4 PI)
8178 13:08:47.956347 u2DelayCellOfst[13]=13 cells (4 PI)
8179 13:08:47.959554 u2DelayCellOfst[14]=13 cells (4 PI)
8180 13:08:47.962686 u2DelayCellOfst[15]=10 cells (3 PI)
8181 13:08:47.969447 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8182 13:08:47.972627 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8183 13:08:47.972706 DramC Write-DBI on
8184 13:08:47.972783 ==
8185 13:08:47.976230 Dram Type= 6, Freq= 0, CH_0, rank 1
8186 13:08:47.982565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8187 13:08:47.982642 ==
8188 13:08:47.982703
8189 13:08:47.982758
8190 13:08:47.982810 TX Vref Scan disable
8191 13:08:47.987052 == TX Byte 0 ==
8192 13:08:47.990251 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8193 13:08:47.993584 == TX Byte 1 ==
8194 13:08:47.997032 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8195 13:08:47.997108 DramC Write-DBI off
8196 13:08:48.000020
8197 13:08:48.000094 [DATLAT]
8198 13:08:48.000153 Freq=1600, CH0 RK1
8199 13:08:48.000208
8200 13:08:48.003517 DATLAT Default: 0xf
8201 13:08:48.003592 0, 0xFFFF, sum = 0
8202 13:08:48.007200 1, 0xFFFF, sum = 0
8203 13:08:48.007277 2, 0xFFFF, sum = 0
8204 13:08:48.010231 3, 0xFFFF, sum = 0
8205 13:08:48.013627 4, 0xFFFF, sum = 0
8206 13:08:48.013707 5, 0xFFFF, sum = 0
8207 13:08:48.017049 6, 0xFFFF, sum = 0
8208 13:08:48.017132 7, 0xFFFF, sum = 0
8209 13:08:48.020378 8, 0xFFFF, sum = 0
8210 13:08:48.020454 9, 0xFFFF, sum = 0
8211 13:08:48.023306 10, 0xFFFF, sum = 0
8212 13:08:48.023382 11, 0xFFFF, sum = 0
8213 13:08:48.026794 12, 0xFFFF, sum = 0
8214 13:08:48.026870 13, 0xFFFF, sum = 0
8215 13:08:48.030252 14, 0x0, sum = 1
8216 13:08:48.030329 15, 0x0, sum = 2
8217 13:08:48.033517 16, 0x0, sum = 3
8218 13:08:48.033593 17, 0x0, sum = 4
8219 13:08:48.036816 best_step = 15
8220 13:08:48.036891
8221 13:08:48.036949 ==
8222 13:08:48.040434 Dram Type= 6, Freq= 0, CH_0, rank 1
8223 13:08:48.043388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8224 13:08:48.043465 ==
8225 13:08:48.043524 RX Vref Scan: 0
8226 13:08:48.043578
8227 13:08:48.047129 RX Vref 0 -> 0, step: 1
8228 13:08:48.047204
8229 13:08:48.050876 RX Delay 11 -> 252, step: 4
8230 13:08:48.053759 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8231 13:08:48.060184 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8232 13:08:48.063307 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8233 13:08:48.066846 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8234 13:08:48.070065 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8235 13:08:48.073601 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8236 13:08:48.077031 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8237 13:08:48.083455 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8238 13:08:48.087036 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8239 13:08:48.089945 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8240 13:08:48.093174 iDelay=191, Bit 10, Center 126 (79 ~ 174) 96
8241 13:08:48.096465 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8242 13:08:48.103255 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8243 13:08:48.106505 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8244 13:08:48.110052 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8245 13:08:48.113551 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8246 13:08:48.113617 ==
8247 13:08:48.116708 Dram Type= 6, Freq= 0, CH_0, rank 1
8248 13:08:48.123097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8249 13:08:48.123167 ==
8250 13:08:48.123249 DQS Delay:
8251 13:08:48.126461 DQS0 = 0, DQS1 = 0
8252 13:08:48.126531 DQM Delay:
8253 13:08:48.126587 DQM0 = 132, DQM1 = 123
8254 13:08:48.130080 DQ Delay:
8255 13:08:48.133543 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8256 13:08:48.136703 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8257 13:08:48.139904 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =120
8258 13:08:48.143455 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =128
8259 13:08:48.143521
8260 13:08:48.143586
8261 13:08:48.143639
8262 13:08:48.146746 [DramC_TX_OE_Calibration] TA2
8263 13:08:48.150209 Original DQ_B0 (3 6) =30, OEN = 27
8264 13:08:48.153376 Original DQ_B1 (3 6) =30, OEN = 27
8265 13:08:48.156955 24, 0x0, End_B0=24 End_B1=24
8266 13:08:48.157026 25, 0x0, End_B0=25 End_B1=25
8267 13:08:48.160004 26, 0x0, End_B0=26 End_B1=26
8268 13:08:48.163232 27, 0x0, End_B0=27 End_B1=27
8269 13:08:48.166572 28, 0x0, End_B0=28 End_B1=28
8270 13:08:48.170029 29, 0x0, End_B0=29 End_B1=29
8271 13:08:48.170103 30, 0x0, End_B0=30 End_B1=30
8272 13:08:48.173334 31, 0x4141, End_B0=30 End_B1=30
8273 13:08:48.176599 Byte0 end_step=30 best_step=27
8274 13:08:48.179888 Byte1 end_step=30 best_step=27
8275 13:08:48.183060 Byte0 TX OE(2T, 0.5T) = (3, 3)
8276 13:08:48.183131 Byte1 TX OE(2T, 0.5T) = (3, 3)
8277 13:08:48.186556
8278 13:08:48.186629
8279 13:08:48.193312 [DQSOSCAuto] RK1, (LSB)MR18= 0x210d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8280 13:08:48.196389 CH0 RK1: MR19=303, MR18=210D
8281 13:08:48.203157 CH0_RK1: MR19=0x303, MR18=0x210D, DQSOSC=393, MR23=63, INC=23, DEC=15
8282 13:08:48.206746 [RxdqsGatingPostProcess] freq 1600
8283 13:08:48.210007 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8284 13:08:48.213323 best DQS0 dly(2T, 0.5T) = (1, 1)
8285 13:08:48.216478 best DQS1 dly(2T, 0.5T) = (1, 1)
8286 13:08:48.219951 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8287 13:08:48.223173 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8288 13:08:48.226312 best DQS0 dly(2T, 0.5T) = (1, 1)
8289 13:08:48.229723 best DQS1 dly(2T, 0.5T) = (1, 1)
8290 13:08:48.233013 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8291 13:08:48.236214 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8292 13:08:48.239511 Pre-setting of DQS Precalculation
8293 13:08:48.242937 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8294 13:08:48.243006 ==
8295 13:08:48.246583 Dram Type= 6, Freq= 0, CH_1, rank 0
8296 13:08:48.250191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8297 13:08:48.250257 ==
8298 13:08:48.256558 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8299 13:08:48.260097 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8300 13:08:48.266651 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8301 13:08:48.270203 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8302 13:08:48.279534 [CA 0] Center 40 (11~70) winsize 60
8303 13:08:48.282993 [CA 1] Center 41 (11~71) winsize 61
8304 13:08:48.286113 [CA 2] Center 37 (8~67) winsize 60
8305 13:08:48.289424 [CA 3] Center 36 (7~66) winsize 60
8306 13:08:48.293302 [CA 4] Center 36 (6~67) winsize 62
8307 13:08:48.296084 [CA 5] Center 36 (6~66) winsize 61
8308 13:08:48.296157
8309 13:08:48.299418 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8310 13:08:48.299491
8311 13:08:48.302847 [CATrainingPosCal] consider 1 rank data
8312 13:08:48.306357 u2DelayCellTimex100 = 290/100 ps
8313 13:08:48.309614 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8314 13:08:48.316171 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8315 13:08:48.319580 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8316 13:08:48.322935 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8317 13:08:48.326117 CA4 delay=36 (6~67),Diff = 0 PI (0 cell)
8318 13:08:48.329305 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8319 13:08:48.329377
8320 13:08:48.333004 CA PerBit enable=1, Macro0, CA PI delay=36
8321 13:08:48.333076
8322 13:08:48.336213 [CBTSetCACLKResult] CA Dly = 36
8323 13:08:48.339382 CS Dly: 9 (0~40)
8324 13:08:48.342648 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8325 13:08:48.346082 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8326 13:08:48.346148 ==
8327 13:08:48.349509 Dram Type= 6, Freq= 0, CH_1, rank 1
8328 13:08:48.352691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8329 13:08:48.355556 ==
8330 13:08:48.359105 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8331 13:08:48.362544 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8332 13:08:48.369403 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8333 13:08:48.372374 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8334 13:08:48.382471 [CA 0] Center 42 (13~72) winsize 60
8335 13:08:48.385777 [CA 1] Center 42 (13~72) winsize 60
8336 13:08:48.389268 [CA 2] Center 38 (9~68) winsize 60
8337 13:08:48.392704 [CA 3] Center 37 (8~67) winsize 60
8338 13:08:48.396152 [CA 4] Center 38 (9~68) winsize 60
8339 13:08:48.399215 [CA 5] Center 37 (8~67) winsize 60
8340 13:08:48.399284
8341 13:08:48.402723 [CmdBusTrainingLP45] Vref(ca) range 0: 28
8342 13:08:48.402791
8343 13:08:48.405811 [CATrainingPosCal] consider 2 rank data
8344 13:08:48.409098 u2DelayCellTimex100 = 290/100 ps
8345 13:08:48.412566 CA0 delay=41 (13~70),Diff = 4 PI (13 cell)
8346 13:08:48.419165 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8347 13:08:48.422490 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8348 13:08:48.426193 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8349 13:08:48.429612 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8350 13:08:48.432483 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8351 13:08:48.432562
8352 13:08:48.435758 CA PerBit enable=1, Macro0, CA PI delay=37
8353 13:08:48.435825
8354 13:08:48.439315 [CBTSetCACLKResult] CA Dly = 37
8355 13:08:48.442394 CS Dly: 10 (0~42)
8356 13:08:48.446015 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8357 13:08:48.449045 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8358 13:08:48.449162
8359 13:08:48.452800 ----->DramcWriteLeveling(PI) begin...
8360 13:08:48.452867 ==
8361 13:08:48.456006 Dram Type= 6, Freq= 0, CH_1, rank 0
8362 13:08:48.459205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8363 13:08:48.462526 ==
8364 13:08:48.462604 Write leveling (Byte 0): 25 => 25
8365 13:08:48.466048 Write leveling (Byte 1): 29 => 29
8366 13:08:48.469152 DramcWriteLeveling(PI) end<-----
8367 13:08:48.469240
8368 13:08:48.469297 ==
8369 13:08:48.472723 Dram Type= 6, Freq= 0, CH_1, rank 0
8370 13:08:48.479187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8371 13:08:48.479266 ==
8372 13:08:48.479324 [Gating] SW mode calibration
8373 13:08:48.489288 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8374 13:08:48.492355 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8375 13:08:48.495914 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 13:08:48.502528 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 13:08:48.505976 1 4 8 | B1->B0 | 2b2b 3232 | 0 1 | (0 0) (1 1)
8378 13:08:48.509337 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8379 13:08:48.516004 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 13:08:48.519017 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 13:08:48.522462 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 13:08:48.529196 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 13:08:48.532724 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 13:08:48.535544 1 5 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
8385 13:08:48.542458 1 5 8 | B1->B0 | 3030 2828 | 0 0 | (0 1) (0 1)
8386 13:08:48.545817 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 13:08:48.549024 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 13:08:48.555827 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 13:08:48.559213 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 13:08:48.562229 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 13:08:48.568844 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 13:08:48.572136 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8393 13:08:48.575290 1 6 8 | B1->B0 | 3737 4242 | 0 0 | (0 0) (0 0)
8394 13:08:48.582220 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 13:08:48.585903 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 13:08:48.588821 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 13:08:48.595556 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 13:08:48.599181 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 13:08:48.602214 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 13:08:48.608647 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 13:08:48.612062 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8402 13:08:48.615480 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8403 13:08:48.621876 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 13:08:48.625255 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 13:08:48.628589 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 13:08:48.635453 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 13:08:48.638384 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 13:08:48.641910 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 13:08:48.645241 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 13:08:48.651687 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 13:08:48.655132 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 13:08:48.658478 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 13:08:48.665184 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 13:08:48.668489 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 13:08:48.671811 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 13:08:48.678777 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 13:08:48.681970 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8418 13:08:48.685147 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8419 13:08:48.688643 Total UI for P1: 0, mck2ui 16
8420 13:08:48.692052 best dqsien dly found for B0: ( 1, 9, 8)
8421 13:08:48.698645 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8422 13:08:48.698725 Total UI for P1: 0, mck2ui 16
8423 13:08:48.704982 best dqsien dly found for B1: ( 1, 9, 10)
8424 13:08:48.708224 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8425 13:08:48.711736 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8426 13:08:48.711810
8427 13:08:48.715284 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8428 13:08:48.718294 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8429 13:08:48.721490 [Gating] SW calibration Done
8430 13:08:48.721560 ==
8431 13:08:48.725323 Dram Type= 6, Freq= 0, CH_1, rank 0
8432 13:08:48.728187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8433 13:08:48.728267 ==
8434 13:08:48.731516 RX Vref Scan: 0
8435 13:08:48.731613
8436 13:08:48.731699 RX Vref 0 -> 0, step: 1
8437 13:08:48.731788
8438 13:08:48.734720 RX Delay 0 -> 252, step: 8
8439 13:08:48.738272 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8440 13:08:48.744906 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8441 13:08:48.748233 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8442 13:08:48.751609 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8443 13:08:48.754955 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8444 13:08:48.758307 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8445 13:08:48.761913 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8446 13:08:48.768659 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8447 13:08:48.771772 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8448 13:08:48.774908 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8449 13:08:48.778567 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8450 13:08:48.781600 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8451 13:08:48.788845 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8452 13:08:48.792045 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8453 13:08:48.795256 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8454 13:08:48.798713 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8455 13:08:48.798797 ==
8456 13:08:48.801915 Dram Type= 6, Freq= 0, CH_1, rank 0
8457 13:08:48.805095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8458 13:08:48.809650 ==
8459 13:08:48.809745 DQS Delay:
8460 13:08:48.809805 DQS0 = 0, DQS1 = 0
8461 13:08:48.811971 DQM Delay:
8462 13:08:48.812083 DQM0 = 138, DQM1 = 130
8463 13:08:48.815367 DQ Delay:
8464 13:08:48.818331 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8465 13:08:48.821632 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8466 13:08:48.825225 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8467 13:08:48.828421 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8468 13:08:48.828534
8469 13:08:48.828628
8470 13:08:48.828722 ==
8471 13:08:48.831959 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 13:08:48.835447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 13:08:48.835564 ==
8474 13:08:48.835663
8475 13:08:48.838536
8476 13:08:48.838630 TX Vref Scan disable
8477 13:08:48.842094 == TX Byte 0 ==
8478 13:08:48.845283 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8479 13:08:48.848261 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8480 13:08:48.851945 == TX Byte 1 ==
8481 13:08:48.855190 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8482 13:08:48.858270 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8483 13:08:48.858349 ==
8484 13:08:48.862538 Dram Type= 6, Freq= 0, CH_1, rank 0
8485 13:08:48.868741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8486 13:08:48.868819 ==
8487 13:08:48.879845
8488 13:08:48.883222 TX Vref early break, caculate TX vref
8489 13:08:48.886657 TX Vref=16, minBit 10, minWin=20, winSum=366
8490 13:08:48.890066 TX Vref=18, minBit 10, minWin=21, winSum=376
8491 13:08:48.892942 TX Vref=20, minBit 10, minWin=22, winSum=390
8492 13:08:48.896346 TX Vref=22, minBit 8, minWin=23, winSum=394
8493 13:08:48.903143 TX Vref=24, minBit 10, minWin=24, winSum=407
8494 13:08:48.906433 TX Vref=26, minBit 15, minWin=24, winSum=414
8495 13:08:48.909761 TX Vref=28, minBit 10, minWin=24, winSum=416
8496 13:08:48.912903 TX Vref=30, minBit 8, minWin=24, winSum=411
8497 13:08:48.916189 TX Vref=32, minBit 11, minWin=23, winSum=402
8498 13:08:48.919761 TX Vref=34, minBit 8, minWin=23, winSum=389
8499 13:08:48.926391 [TxChooseVref] Worse bit 10, Min win 24, Win sum 416, Final Vref 28
8500 13:08:48.926468
8501 13:08:48.929532 Final TX Range 0 Vref 28
8502 13:08:48.929608
8503 13:08:48.929667 ==
8504 13:08:48.933108 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 13:08:48.936459 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 13:08:48.936536 ==
8507 13:08:48.936594
8508 13:08:48.939416
8509 13:08:48.939492 TX Vref Scan disable
8510 13:08:48.946357 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8511 13:08:48.946472 == TX Byte 0 ==
8512 13:08:48.949699 u2DelayCellOfst[0]=13 cells (4 PI)
8513 13:08:48.952731 u2DelayCellOfst[1]=10 cells (3 PI)
8514 13:08:48.956246 u2DelayCellOfst[2]=0 cells (0 PI)
8515 13:08:48.959887 u2DelayCellOfst[3]=6 cells (2 PI)
8516 13:08:48.963281 u2DelayCellOfst[4]=6 cells (2 PI)
8517 13:08:48.966353 u2DelayCellOfst[5]=16 cells (5 PI)
8518 13:08:48.969662 u2DelayCellOfst[6]=16 cells (5 PI)
8519 13:08:48.972636 u2DelayCellOfst[7]=3 cells (1 PI)
8520 13:08:48.976170 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8521 13:08:48.979221 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8522 13:08:48.982666 == TX Byte 1 ==
8523 13:08:48.985886 u2DelayCellOfst[8]=0 cells (0 PI)
8524 13:08:48.985982 u2DelayCellOfst[9]=3 cells (1 PI)
8525 13:08:48.989379 u2DelayCellOfst[10]=13 cells (4 PI)
8526 13:08:48.992681 u2DelayCellOfst[11]=6 cells (2 PI)
8527 13:08:48.995957 u2DelayCellOfst[12]=16 cells (5 PI)
8528 13:08:48.999426 u2DelayCellOfst[13]=20 cells (6 PI)
8529 13:08:49.002858 u2DelayCellOfst[14]=20 cells (6 PI)
8530 13:08:49.006357 u2DelayCellOfst[15]=16 cells (5 PI)
8531 13:08:49.009329 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8532 13:08:49.016034 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8533 13:08:49.016102 DramC Write-DBI on
8534 13:08:49.016167 ==
8535 13:08:49.019473 Dram Type= 6, Freq= 0, CH_1, rank 0
8536 13:08:49.026019 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8537 13:08:49.026089 ==
8538 13:08:49.026146
8539 13:08:49.026199
8540 13:08:49.026263 TX Vref Scan disable
8541 13:08:49.029636 == TX Byte 0 ==
8542 13:08:49.033258 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8543 13:08:49.036490 == TX Byte 1 ==
8544 13:08:49.039846 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8545 13:08:49.043011 DramC Write-DBI off
8546 13:08:49.043075
8547 13:08:49.043141 [DATLAT]
8548 13:08:49.043194 Freq=1600, CH1 RK0
8549 13:08:49.043246
8550 13:08:49.046398 DATLAT Default: 0xf
8551 13:08:49.046459 0, 0xFFFF, sum = 0
8552 13:08:49.049739 1, 0xFFFF, sum = 0
8553 13:08:49.053008 2, 0xFFFF, sum = 0
8554 13:08:49.053073 3, 0xFFFF, sum = 0
8555 13:08:49.056609 4, 0xFFFF, sum = 0
8556 13:08:49.056692 5, 0xFFFF, sum = 0
8557 13:08:49.059640 6, 0xFFFF, sum = 0
8558 13:08:49.059719 7, 0xFFFF, sum = 0
8559 13:08:49.062907 8, 0xFFFF, sum = 0
8560 13:08:49.062973 9, 0xFFFF, sum = 0
8561 13:08:49.066437 10, 0xFFFF, sum = 0
8562 13:08:49.066511 11, 0xFFFF, sum = 0
8563 13:08:49.069617 12, 0xFFFF, sum = 0
8564 13:08:49.069682 13, 0xFFFF, sum = 0
8565 13:08:49.073261 14, 0x0, sum = 1
8566 13:08:49.073338 15, 0x0, sum = 2
8567 13:08:49.076371 16, 0x0, sum = 3
8568 13:08:49.076447 17, 0x0, sum = 4
8569 13:08:49.079808 best_step = 15
8570 13:08:49.079880
8571 13:08:49.079936 ==
8572 13:08:49.082933 Dram Type= 6, Freq= 0, CH_1, rank 0
8573 13:08:49.086391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8574 13:08:49.086465 ==
8575 13:08:49.086532 RX Vref Scan: 1
8576 13:08:49.089439
8577 13:08:49.089503 Set Vref Range= 24 -> 127
8578 13:08:49.089559
8579 13:08:49.092937 RX Vref 24 -> 127, step: 1
8580 13:08:49.093023
8581 13:08:49.096202 RX Delay 19 -> 252, step: 4
8582 13:08:49.096266
8583 13:08:49.099633 Set Vref, RX VrefLevel [Byte0]: 24
8584 13:08:49.102667 [Byte1]: 24
8585 13:08:49.102731
8586 13:08:49.106279 Set Vref, RX VrefLevel [Byte0]: 25
8587 13:08:49.109377 [Byte1]: 25
8588 13:08:49.109452
8589 13:08:49.113073 Set Vref, RX VrefLevel [Byte0]: 26
8590 13:08:49.116088 [Byte1]: 26
8591 13:08:49.119907
8592 13:08:49.119983 Set Vref, RX VrefLevel [Byte0]: 27
8593 13:08:49.123430 [Byte1]: 27
8594 13:08:49.127407
8595 13:08:49.127483 Set Vref, RX VrefLevel [Byte0]: 28
8596 13:08:49.130642 [Byte1]: 28
8597 13:08:49.135329
8598 13:08:49.135427 Set Vref, RX VrefLevel [Byte0]: 29
8599 13:08:49.138449 [Byte1]: 29
8600 13:08:49.142769
8601 13:08:49.142845 Set Vref, RX VrefLevel [Byte0]: 30
8602 13:08:49.145878 [Byte1]: 30
8603 13:08:49.150405
8604 13:08:49.150481 Set Vref, RX VrefLevel [Byte0]: 31
8605 13:08:49.153438 [Byte1]: 31
8606 13:08:49.158051
8607 13:08:49.158156 Set Vref, RX VrefLevel [Byte0]: 32
8608 13:08:49.161108 [Byte1]: 32
8609 13:08:49.165142
8610 13:08:49.165233 Set Vref, RX VrefLevel [Byte0]: 33
8611 13:08:49.168846 [Byte1]: 33
8612 13:08:49.173044
8613 13:08:49.173121 Set Vref, RX VrefLevel [Byte0]: 34
8614 13:08:49.176167 [Byte1]: 34
8615 13:08:49.180706
8616 13:08:49.180782 Set Vref, RX VrefLevel [Byte0]: 35
8617 13:08:49.183918 [Byte1]: 35
8618 13:08:49.188085
8619 13:08:49.188161 Set Vref, RX VrefLevel [Byte0]: 36
8620 13:08:49.191251 [Byte1]: 36
8621 13:08:49.195905
8622 13:08:49.195980 Set Vref, RX VrefLevel [Byte0]: 37
8623 13:08:49.199053 [Byte1]: 37
8624 13:08:49.203298
8625 13:08:49.203374 Set Vref, RX VrefLevel [Byte0]: 38
8626 13:08:49.206791 [Byte1]: 38
8627 13:08:49.211281
8628 13:08:49.211358 Set Vref, RX VrefLevel [Byte0]: 39
8629 13:08:49.214312 [Byte1]: 39
8630 13:08:49.218374
8631 13:08:49.218450 Set Vref, RX VrefLevel [Byte0]: 40
8632 13:08:49.221862 [Byte1]: 40
8633 13:08:49.225991
8634 13:08:49.226066 Set Vref, RX VrefLevel [Byte0]: 41
8635 13:08:49.229292 [Byte1]: 41
8636 13:08:49.233878
8637 13:08:49.233954 Set Vref, RX VrefLevel [Byte0]: 42
8638 13:08:49.236796 [Byte1]: 42
8639 13:08:49.241097
8640 13:08:49.241230 Set Vref, RX VrefLevel [Byte0]: 43
8641 13:08:49.244713 [Byte1]: 43
8642 13:08:49.248497
8643 13:08:49.248571 Set Vref, RX VrefLevel [Byte0]: 44
8644 13:08:49.251811 [Byte1]: 44
8645 13:08:49.256432
8646 13:08:49.256500 Set Vref, RX VrefLevel [Byte0]: 45
8647 13:08:49.259898 [Byte1]: 45
8648 13:08:49.263692
8649 13:08:49.263770 Set Vref, RX VrefLevel [Byte0]: 46
8650 13:08:49.267157 [Byte1]: 46
8651 13:08:49.271388
8652 13:08:49.271491 Set Vref, RX VrefLevel [Byte0]: 47
8653 13:08:49.274563 [Byte1]: 47
8654 13:08:49.278981
8655 13:08:49.279050 Set Vref, RX VrefLevel [Byte0]: 48
8656 13:08:49.282155 [Byte1]: 48
8657 13:08:49.286709
8658 13:08:49.286782 Set Vref, RX VrefLevel [Byte0]: 49
8659 13:08:49.289612 [Byte1]: 49
8660 13:08:49.294044
8661 13:08:49.294112 Set Vref, RX VrefLevel [Byte0]: 50
8662 13:08:49.297658 [Byte1]: 50
8663 13:08:49.301770
8664 13:08:49.301837 Set Vref, RX VrefLevel [Byte0]: 51
8665 13:08:49.304909 [Byte1]: 51
8666 13:08:49.309149
8667 13:08:49.309254 Set Vref, RX VrefLevel [Byte0]: 52
8668 13:08:49.312556 [Byte1]: 52
8669 13:08:49.316665
8670 13:08:49.316740 Set Vref, RX VrefLevel [Byte0]: 53
8671 13:08:49.320649 [Byte1]: 53
8672 13:08:49.324158
8673 13:08:49.324224 Set Vref, RX VrefLevel [Byte0]: 54
8674 13:08:49.327656 [Byte1]: 54
8675 13:08:49.331846
8676 13:08:49.331921 Set Vref, RX VrefLevel [Byte0]: 55
8677 13:08:49.335377 [Byte1]: 55
8678 13:08:49.339641
8679 13:08:49.339742 Set Vref, RX VrefLevel [Byte0]: 56
8680 13:08:49.342607 [Byte1]: 56
8681 13:08:49.347164
8682 13:08:49.350870 Set Vref, RX VrefLevel [Byte0]: 57
8683 13:08:49.350942 [Byte1]: 57
8684 13:08:49.354914
8685 13:08:49.354980 Set Vref, RX VrefLevel [Byte0]: 58
8686 13:08:49.357870 [Byte1]: 58
8687 13:08:49.362430
8688 13:08:49.362496 Set Vref, RX VrefLevel [Byte0]: 59
8689 13:08:49.365374 [Byte1]: 59
8690 13:08:49.369717
8691 13:08:49.369793 Set Vref, RX VrefLevel [Byte0]: 60
8692 13:08:49.373024 [Byte1]: 60
8693 13:08:49.377502
8694 13:08:49.377577 Set Vref, RX VrefLevel [Byte0]: 61
8695 13:08:49.381448 [Byte1]: 61
8696 13:08:49.384776
8697 13:08:49.384844 Set Vref, RX VrefLevel [Byte0]: 62
8698 13:08:49.388114 [Byte1]: 62
8699 13:08:49.392800
8700 13:08:49.392868 Set Vref, RX VrefLevel [Byte0]: 63
8701 13:08:49.395745 [Byte1]: 63
8702 13:08:49.399971
8703 13:08:49.400037 Set Vref, RX VrefLevel [Byte0]: 64
8704 13:08:49.403194 [Byte1]: 64
8705 13:08:49.407503
8706 13:08:49.407570 Set Vref, RX VrefLevel [Byte0]: 65
8707 13:08:49.411222 [Byte1]: 65
8708 13:08:49.415641
8709 13:08:49.415713 Set Vref, RX VrefLevel [Byte0]: 66
8710 13:08:49.418660 [Byte1]: 66
8711 13:08:49.423131
8712 13:08:49.423212 Set Vref, RX VrefLevel [Byte0]: 67
8713 13:08:49.426262 [Byte1]: 67
8714 13:08:49.430555
8715 13:08:49.430636 Set Vref, RX VrefLevel [Byte0]: 68
8716 13:08:49.433646 [Byte1]: 68
8717 13:08:49.438450
8718 13:08:49.438523 Set Vref, RX VrefLevel [Byte0]: 69
8719 13:08:49.441392 [Byte1]: 69
8720 13:08:49.445461
8721 13:08:49.445540 Set Vref, RX VrefLevel [Byte0]: 70
8722 13:08:49.449038 [Byte1]: 70
8723 13:08:49.453065
8724 13:08:49.453174 Set Vref, RX VrefLevel [Byte0]: 71
8725 13:08:49.456150 [Byte1]: 71
8726 13:08:49.460954
8727 13:08:49.461032 Set Vref, RX VrefLevel [Byte0]: 72
8728 13:08:49.463798 [Byte1]: 72
8729 13:08:49.468289
8730 13:08:49.468369 Set Vref, RX VrefLevel [Byte0]: 73
8731 13:08:49.471547 [Byte1]: 73
8732 13:08:49.476255
8733 13:08:49.476345 Set Vref, RX VrefLevel [Byte0]: 74
8734 13:08:49.482519 [Byte1]: 74
8735 13:08:49.482589
8736 13:08:49.485741 Set Vref, RX VrefLevel [Byte0]: 75
8737 13:08:49.489092 [Byte1]: 75
8738 13:08:49.489207
8739 13:08:49.492314 Final RX Vref Byte 0 = 53 to rank0
8740 13:08:49.495516 Final RX Vref Byte 1 = 61 to rank0
8741 13:08:49.499114 Final RX Vref Byte 0 = 53 to rank1
8742 13:08:49.502303 Final RX Vref Byte 1 = 61 to rank1==
8743 13:08:49.506148 Dram Type= 6, Freq= 0, CH_1, rank 0
8744 13:08:49.508879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 13:08:49.508951 ==
8746 13:08:49.512083 DQS Delay:
8747 13:08:49.512149 DQS0 = 0, DQS1 = 0
8748 13:08:49.512213 DQM Delay:
8749 13:08:49.515202 DQM0 = 133, DQM1 = 128
8750 13:08:49.515275 DQ Delay:
8751 13:08:49.518974 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8752 13:08:49.521895 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8753 13:08:49.525372 DQ8 =116, DQ9 =116, DQ10 =132, DQ11 =122
8754 13:08:49.532095 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8755 13:08:49.532176
8756 13:08:49.532234
8757 13:08:49.532287
8758 13:08:49.535880 [DramC_TX_OE_Calibration] TA2
8759 13:08:49.538636 Original DQ_B0 (3 6) =30, OEN = 27
8760 13:08:49.538719 Original DQ_B1 (3 6) =30, OEN = 27
8761 13:08:49.542247 24, 0x0, End_B0=24 End_B1=24
8762 13:08:49.545296 25, 0x0, End_B0=25 End_B1=25
8763 13:08:49.548765 26, 0x0, End_B0=26 End_B1=26
8764 13:08:49.551729 27, 0x0, End_B0=27 End_B1=27
8765 13:08:49.551799 28, 0x0, End_B0=28 End_B1=28
8766 13:08:49.555394 29, 0x0, End_B0=29 End_B1=29
8767 13:08:49.558318 30, 0x0, End_B0=30 End_B1=30
8768 13:08:49.561679 31, 0x4141, End_B0=30 End_B1=30
8769 13:08:49.565510 Byte0 end_step=30 best_step=27
8770 13:08:49.565578 Byte1 end_step=30 best_step=27
8771 13:08:49.568822 Byte0 TX OE(2T, 0.5T) = (3, 3)
8772 13:08:49.571899 Byte1 TX OE(2T, 0.5T) = (3, 3)
8773 13:08:49.571965
8774 13:08:49.572019
8775 13:08:49.581984 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8776 13:08:49.585102 CH1 RK0: MR19=303, MR18=1826
8777 13:08:49.588224 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8778 13:08:49.588311
8779 13:08:49.591838 ----->DramcWriteLeveling(PI) begin...
8780 13:08:49.595318 ==
8781 13:08:49.598587 Dram Type= 6, Freq= 0, CH_1, rank 1
8782 13:08:49.601858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 13:08:49.601961 ==
8784 13:08:49.605009 Write leveling (Byte 0): 24 => 24
8785 13:08:49.608274 Write leveling (Byte 1): 28 => 28
8786 13:08:49.611661 DramcWriteLeveling(PI) end<-----
8787 13:08:49.611820
8788 13:08:49.611918 ==
8789 13:08:49.615456 Dram Type= 6, Freq= 0, CH_1, rank 1
8790 13:08:49.618193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8791 13:08:49.618354 ==
8792 13:08:49.621604 [Gating] SW mode calibration
8793 13:08:49.628600 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8794 13:08:49.635301 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8795 13:08:49.638547 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 13:08:49.641853 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 13:08:49.648534 1 4 8 | B1->B0 | 2e2d 2323 | 1 0 | (0 0) (0 0)
8798 13:08:49.651599 1 4 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8799 13:08:49.655001 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 13:08:49.658244 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 13:08:49.665004 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 13:08:49.668430 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 13:08:49.671762 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 13:08:49.678073 1 5 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8805 13:08:49.681858 1 5 8 | B1->B0 | 2323 3434 | 0 1 | (1 0) (1 0)
8806 13:08:49.684985 1 5 12 | B1->B0 | 2323 2828 | 0 0 | (1 0) (1 0)
8807 13:08:49.691358 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 13:08:49.695034 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 13:08:49.698508 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 13:08:49.705241 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 13:08:49.708155 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 13:08:49.711562 1 6 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8813 13:08:49.718114 1 6 8 | B1->B0 | 4242 2323 | 0 0 | (0 0) (0 0)
8814 13:08:49.721711 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 13:08:49.725011 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 13:08:49.731428 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 13:08:49.734723 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 13:08:49.738552 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 13:08:49.745066 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 13:08:49.748415 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 13:08:49.751455 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8822 13:08:49.755052 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 13:08:49.761590 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 13:08:49.764863 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 13:08:49.768489 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 13:08:49.774644 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 13:08:49.778113 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 13:08:49.781918 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 13:08:49.788439 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 13:08:49.791311 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 13:08:49.794680 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 13:08:49.801235 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 13:08:49.804562 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 13:08:49.808142 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 13:08:49.814949 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 13:08:49.817998 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 13:08:49.821627 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8838 13:08:49.828332 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8839 13:08:49.831317 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8840 13:08:49.834805 Total UI for P1: 0, mck2ui 16
8841 13:08:49.838026 best dqsien dly found for B0: ( 1, 9, 10)
8842 13:08:49.841198 Total UI for P1: 0, mck2ui 16
8843 13:08:49.844579 best dqsien dly found for B1: ( 1, 9, 10)
8844 13:08:49.847881 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8845 13:08:49.851236 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8846 13:08:49.851667
8847 13:08:49.854770 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8848 13:08:49.858087 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8849 13:08:49.861454 [Gating] SW calibration Done
8850 13:08:49.861959 ==
8851 13:08:49.864855 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 13:08:49.868097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 13:08:49.868673 ==
8854 13:08:49.871280 RX Vref Scan: 0
8855 13:08:49.871709
8856 13:08:49.874960 RX Vref 0 -> 0, step: 1
8857 13:08:49.875388
8858 13:08:49.875776 RX Delay 0 -> 252, step: 8
8859 13:08:49.881395 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8860 13:08:49.884688 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8861 13:08:49.888087 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8862 13:08:49.891600 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8863 13:08:49.894943 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8864 13:08:49.901330 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8865 13:08:49.904845 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8866 13:08:49.907887 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8867 13:08:49.911358 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8868 13:08:49.914767 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8869 13:08:49.921155 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8870 13:08:49.924474 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8871 13:08:49.927887 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8872 13:08:49.931388 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8873 13:08:49.934776 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8874 13:08:49.941216 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8875 13:08:49.941652 ==
8876 13:08:49.944383 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 13:08:49.947847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 13:08:49.948239 ==
8879 13:08:49.948576 DQS Delay:
8880 13:08:49.951488 DQS0 = 0, DQS1 = 0
8881 13:08:49.952106 DQM Delay:
8882 13:08:49.954199 DQM0 = 137, DQM1 = 132
8883 13:08:49.954760 DQ Delay:
8884 13:08:49.957744 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8885 13:08:49.960998 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =139
8886 13:08:49.964850 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8887 13:08:49.967656 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8888 13:08:49.968250
8889 13:08:49.968669
8890 13:08:49.971297 ==
8891 13:08:49.974781 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 13:08:49.978125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 13:08:49.978715 ==
8894 13:08:49.979087
8895 13:08:49.979378
8896 13:08:49.981578 TX Vref Scan disable
8897 13:08:49.981970 == TX Byte 0 ==
8898 13:08:49.984707 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8899 13:08:49.991052 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8900 13:08:49.991442 == TX Byte 1 ==
8901 13:08:49.994539 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8902 13:08:50.001320 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8903 13:08:50.001732 ==
8904 13:08:50.004626 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 13:08:50.007484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 13:08:50.007876 ==
8907 13:08:50.020799
8908 13:08:50.024092 TX Vref early break, caculate TX vref
8909 13:08:50.027400 TX Vref=16, minBit 9, minWin=22, winSum=381
8910 13:08:50.030651 TX Vref=18, minBit 9, minWin=22, winSum=391
8911 13:08:50.034413 TX Vref=20, minBit 8, minWin=24, winSum=400
8912 13:08:50.037578 TX Vref=22, minBit 8, minWin=24, winSum=409
8913 13:08:50.041171 TX Vref=24, minBit 12, minWin=24, winSum=419
8914 13:08:50.047673 TX Vref=26, minBit 10, minWin=24, winSum=417
8915 13:08:50.050966 TX Vref=28, minBit 10, minWin=24, winSum=419
8916 13:08:50.054127 TX Vref=30, minBit 8, minWin=25, winSum=417
8917 13:08:50.057308 TX Vref=32, minBit 10, minWin=24, winSum=406
8918 13:08:50.060711 TX Vref=34, minBit 9, minWin=23, winSum=397
8919 13:08:50.067257 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 30
8920 13:08:50.067839
8921 13:08:50.070747 Final TX Range 0 Vref 30
8922 13:08:50.071377
8923 13:08:50.071928 ==
8924 13:08:50.074593 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 13:08:50.077294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 13:08:50.077893 ==
8927 13:08:50.078255
8928 13:08:50.078764
8929 13:08:50.080510 TX Vref Scan disable
8930 13:08:50.087223 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8931 13:08:50.087771 == TX Byte 0 ==
8932 13:08:50.090624 u2DelayCellOfst[0]=16 cells (5 PI)
8933 13:08:50.093919 u2DelayCellOfst[1]=13 cells (4 PI)
8934 13:08:50.097103 u2DelayCellOfst[2]=0 cells (0 PI)
8935 13:08:50.100577 u2DelayCellOfst[3]=6 cells (2 PI)
8936 13:08:50.103896 u2DelayCellOfst[4]=10 cells (3 PI)
8937 13:08:50.107053 u2DelayCellOfst[5]=16 cells (5 PI)
8938 13:08:50.110788 u2DelayCellOfst[6]=16 cells (5 PI)
8939 13:08:50.113837 u2DelayCellOfst[7]=6 cells (2 PI)
8940 13:08:50.117316 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8941 13:08:50.120347 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8942 13:08:50.123726 == TX Byte 1 ==
8943 13:08:50.124263 u2DelayCellOfst[8]=0 cells (0 PI)
8944 13:08:50.127179 u2DelayCellOfst[9]=6 cells (2 PI)
8945 13:08:50.130453 u2DelayCellOfst[10]=10 cells (3 PI)
8946 13:08:50.134084 u2DelayCellOfst[11]=6 cells (2 PI)
8947 13:08:50.137113 u2DelayCellOfst[12]=13 cells (4 PI)
8948 13:08:50.140202 u2DelayCellOfst[13]=16 cells (5 PI)
8949 13:08:50.143770 u2DelayCellOfst[14]=20 cells (6 PI)
8950 13:08:50.146902 u2DelayCellOfst[15]=20 cells (6 PI)
8951 13:08:50.150245 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8952 13:08:50.157200 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8953 13:08:50.157665 DramC Write-DBI on
8954 13:08:50.158188 ==
8955 13:08:50.160076 Dram Type= 6, Freq= 0, CH_1, rank 1
8956 13:08:50.166385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8957 13:08:50.166490 ==
8958 13:08:50.166577
8959 13:08:50.166658
8960 13:08:50.166753 TX Vref Scan disable
8961 13:08:50.170163 == TX Byte 0 ==
8962 13:08:50.173752 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8963 13:08:50.176920 == TX Byte 1 ==
8964 13:08:50.180217 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8965 13:08:50.183592 DramC Write-DBI off
8966 13:08:50.183690
8967 13:08:50.183782 [DATLAT]
8968 13:08:50.183867 Freq=1600, CH1 RK1
8969 13:08:50.183954
8970 13:08:50.186659 DATLAT Default: 0xf
8971 13:08:50.186759 0, 0xFFFF, sum = 0
8972 13:08:50.190091 1, 0xFFFF, sum = 0
8973 13:08:50.193295 2, 0xFFFF, sum = 0
8974 13:08:50.193385 3, 0xFFFF, sum = 0
8975 13:08:50.196804 4, 0xFFFF, sum = 0
8976 13:08:50.196912 5, 0xFFFF, sum = 0
8977 13:08:50.199853 6, 0xFFFF, sum = 0
8978 13:08:50.199964 7, 0xFFFF, sum = 0
8979 13:08:50.203298 8, 0xFFFF, sum = 0
8980 13:08:50.203403 9, 0xFFFF, sum = 0
8981 13:08:50.206638 10, 0xFFFF, sum = 0
8982 13:08:50.206749 11, 0xFFFF, sum = 0
8983 13:08:50.210462 12, 0xFFFF, sum = 0
8984 13:08:50.210563 13, 0xFFFF, sum = 0
8985 13:08:50.213235 14, 0x0, sum = 1
8986 13:08:50.213323 15, 0x0, sum = 2
8987 13:08:50.216652 16, 0x0, sum = 3
8988 13:08:50.216754 17, 0x0, sum = 4
8989 13:08:50.220222 best_step = 15
8990 13:08:50.220325
8991 13:08:50.220416 ==
8992 13:08:50.223882 Dram Type= 6, Freq= 0, CH_1, rank 1
8993 13:08:50.226561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8994 13:08:50.226658 ==
8995 13:08:50.226743 RX Vref Scan: 0
8996 13:08:50.229987
8997 13:08:50.230081 RX Vref 0 -> 0, step: 1
8998 13:08:50.230170
8999 13:08:50.233363 RX Delay 19 -> 252, step: 4
9000 13:08:50.236861 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
9001 13:08:50.242915 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9002 13:08:50.247178 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9003 13:08:50.249723 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9004 13:08:50.252908 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9005 13:08:50.256361 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9006 13:08:50.259654 iDelay=195, Bit 6, Center 140 (91 ~ 190) 100
9007 13:08:50.266443 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9008 13:08:50.269988 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9009 13:08:50.272914 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9010 13:08:50.276284 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9011 13:08:50.279825 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9012 13:08:50.286266 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9013 13:08:50.289961 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9014 13:08:50.293158 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9015 13:08:50.296765 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9016 13:08:50.296871 ==
9017 13:08:50.299898 Dram Type= 6, Freq= 0, CH_1, rank 1
9018 13:08:50.306158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9019 13:08:50.306260 ==
9020 13:08:50.306353 DQS Delay:
9021 13:08:50.310093 DQS0 = 0, DQS1 = 0
9022 13:08:50.310199 DQM Delay:
9023 13:08:50.310286 DQM0 = 133, DQM1 = 130
9024 13:08:50.313241 DQ Delay:
9025 13:08:50.316600 DQ0 =138, DQ1 =130, DQ2 =120, DQ3 =130
9026 13:08:50.319717 DQ4 =134, DQ5 =146, DQ6 =140, DQ7 =130
9027 13:08:50.323301 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
9028 13:08:50.326391 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9029 13:08:50.326491
9030 13:08:50.326580
9031 13:08:50.326666
9032 13:08:50.329552 [DramC_TX_OE_Calibration] TA2
9033 13:08:50.333047 Original DQ_B0 (3 6) =30, OEN = 27
9034 13:08:50.336303 Original DQ_B1 (3 6) =30, OEN = 27
9035 13:08:50.339503 24, 0x0, End_B0=24 End_B1=24
9036 13:08:50.339610 25, 0x0, End_B0=25 End_B1=25
9037 13:08:50.342743 26, 0x0, End_B0=26 End_B1=26
9038 13:08:50.346109 27, 0x0, End_B0=27 End_B1=27
9039 13:08:50.349927 28, 0x0, End_B0=28 End_B1=28
9040 13:08:50.352669 29, 0x0, End_B0=29 End_B1=29
9041 13:08:50.352747 30, 0x0, End_B0=30 End_B1=30
9042 13:08:50.356414 31, 0x4141, End_B0=30 End_B1=30
9043 13:08:50.359516 Byte0 end_step=30 best_step=27
9044 13:08:50.362744 Byte1 end_step=30 best_step=27
9045 13:08:50.366203 Byte0 TX OE(2T, 0.5T) = (3, 3)
9046 13:08:50.369434 Byte1 TX OE(2T, 0.5T) = (3, 3)
9047 13:08:50.369510
9048 13:08:50.369569
9049 13:08:50.376018 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 395 ps
9050 13:08:50.379525 CH1 RK1: MR19=303, MR18=1D08
9051 13:08:50.385980 CH1_RK1: MR19=0x303, MR18=0x1D08, DQSOSC=395, MR23=63, INC=23, DEC=15
9052 13:08:50.389437 [RxdqsGatingPostProcess] freq 1600
9053 13:08:50.392608 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9054 13:08:50.396389 best DQS0 dly(2T, 0.5T) = (1, 1)
9055 13:08:50.399528 best DQS1 dly(2T, 0.5T) = (1, 1)
9056 13:08:50.402754 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9057 13:08:50.405899 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9058 13:08:50.409314 best DQS0 dly(2T, 0.5T) = (1, 1)
9059 13:08:50.413163 best DQS1 dly(2T, 0.5T) = (1, 1)
9060 13:08:50.415801 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9061 13:08:50.419189 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9062 13:08:50.423103 Pre-setting of DQS Precalculation
9063 13:08:50.426015 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9064 13:08:50.432775 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9065 13:08:50.439392 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9066 13:08:50.439468
9067 13:08:50.439526
9068 13:08:50.443194 [Calibration Summary] 3200 Mbps
9069 13:08:50.446059 CH 0, Rank 0
9070 13:08:50.446134 SW Impedance : PASS
9071 13:08:50.449656 DUTY Scan : NO K
9072 13:08:50.452933 ZQ Calibration : PASS
9073 13:08:50.453010 Jitter Meter : NO K
9074 13:08:50.455994 CBT Training : PASS
9075 13:08:50.459748 Write leveling : PASS
9076 13:08:50.459824 RX DQS gating : PASS
9077 13:08:50.463020 RX DQ/DQS(RDDQC) : PASS
9078 13:08:50.465828 TX DQ/DQS : PASS
9079 13:08:50.465904 RX DATLAT : PASS
9080 13:08:50.469101 RX DQ/DQS(Engine): PASS
9081 13:08:50.469185 TX OE : PASS
9082 13:08:50.472786 All Pass.
9083 13:08:50.472862
9084 13:08:50.472920 CH 0, Rank 1
9085 13:08:50.475820 SW Impedance : PASS
9086 13:08:50.475884 DUTY Scan : NO K
9087 13:08:50.479209 ZQ Calibration : PASS
9088 13:08:50.482341 Jitter Meter : NO K
9089 13:08:50.482418 CBT Training : PASS
9090 13:08:50.485873 Write leveling : PASS
9091 13:08:50.489236 RX DQS gating : PASS
9092 13:08:50.489312 RX DQ/DQS(RDDQC) : PASS
9093 13:08:50.492640 TX DQ/DQS : PASS
9094 13:08:50.495725 RX DATLAT : PASS
9095 13:08:50.495801 RX DQ/DQS(Engine): PASS
9096 13:08:50.499256 TX OE : PASS
9097 13:08:50.499332 All Pass.
9098 13:08:50.499393
9099 13:08:50.502453 CH 1, Rank 0
9100 13:08:50.502529 SW Impedance : PASS
9101 13:08:50.506022 DUTY Scan : NO K
9102 13:08:50.509554 ZQ Calibration : PASS
9103 13:08:50.509631 Jitter Meter : NO K
9104 13:08:50.512400 CBT Training : PASS
9105 13:08:50.515942 Write leveling : PASS
9106 13:08:50.516018 RX DQS gating : PASS
9107 13:08:50.519588 RX DQ/DQS(RDDQC) : PASS
9108 13:08:50.519664 TX DQ/DQS : PASS
9109 13:08:50.522415 RX DATLAT : PASS
9110 13:08:50.525976 RX DQ/DQS(Engine): PASS
9111 13:08:50.526052 TX OE : PASS
9112 13:08:50.529445 All Pass.
9113 13:08:50.529521
9114 13:08:50.529580 CH 1, Rank 1
9115 13:08:50.532163 SW Impedance : PASS
9116 13:08:50.532238 DUTY Scan : NO K
9117 13:08:50.536002 ZQ Calibration : PASS
9118 13:08:50.538946 Jitter Meter : NO K
9119 13:08:50.539023 CBT Training : PASS
9120 13:08:50.542184 Write leveling : PASS
9121 13:08:50.545722 RX DQS gating : PASS
9122 13:08:50.545798 RX DQ/DQS(RDDQC) : PASS
9123 13:08:50.548990 TX DQ/DQS : PASS
9124 13:08:50.552249 RX DATLAT : PASS
9125 13:08:50.552324 RX DQ/DQS(Engine): PASS
9126 13:08:50.555801 TX OE : PASS
9127 13:08:50.555877 All Pass.
9128 13:08:50.555935
9129 13:08:50.559335 DramC Write-DBI on
9130 13:08:50.562202 PER_BANK_REFRESH: Hybrid Mode
9131 13:08:50.562279 TX_TRACKING: ON
9132 13:08:50.572605 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9133 13:08:50.578971 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9134 13:08:50.585787 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9135 13:08:50.589049 [FAST_K] Save calibration result to emmc
9136 13:08:50.592225 sync common calibartion params.
9137 13:08:50.595645 sync cbt_mode0:1, 1:1
9138 13:08:50.599344 dram_init: ddr_geometry: 2
9139 13:08:50.599419 dram_init: ddr_geometry: 2
9140 13:08:50.602092 dram_init: ddr_geometry: 2
9141 13:08:50.605758 0:dram_rank_size:100000000
9142 13:08:50.605836 1:dram_rank_size:100000000
9143 13:08:50.612235 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9144 13:08:50.615419 DFS_SHUFFLE_HW_MODE: ON
9145 13:08:50.619161 dramc_set_vcore_voltage set vcore to 725000
9146 13:08:50.622329 Read voltage for 1600, 0
9147 13:08:50.622424 Vio18 = 0
9148 13:08:50.622509 Vcore = 725000
9149 13:08:50.625890 Vdram = 0
9150 13:08:50.625980 Vddq = 0
9151 13:08:50.626062 Vmddr = 0
9152 13:08:50.628736 switch to 3200 Mbps bootup
9153 13:08:50.628821 [DramcRunTimeConfig]
9154 13:08:50.632228 PHYPLL
9155 13:08:50.632297 DPM_CONTROL_AFTERK: ON
9156 13:08:50.635377 PER_BANK_REFRESH: ON
9157 13:08:50.638849 REFRESH_OVERHEAD_REDUCTION: ON
9158 13:08:50.638952 CMD_PICG_NEW_MODE: OFF
9159 13:08:50.641844 XRTWTW_NEW_MODE: ON
9160 13:08:50.641942 XRTRTR_NEW_MODE: ON
9161 13:08:50.645272 TX_TRACKING: ON
9162 13:08:50.645363 RDSEL_TRACKING: OFF
9163 13:08:50.648792 DQS Precalculation for DVFS: ON
9164 13:08:50.652069 RX_TRACKING: OFF
9165 13:08:50.652159 HW_GATING DBG: ON
9166 13:08:50.655324 ZQCS_ENABLE_LP4: ON
9167 13:08:50.655412 RX_PICG_NEW_MODE: ON
9168 13:08:50.658807 TX_PICG_NEW_MODE: ON
9169 13:08:50.661825 ENABLE_RX_DCM_DPHY: ON
9170 13:08:50.661928 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9171 13:08:50.665064 DUMMY_READ_FOR_TRACKING: OFF
9172 13:08:50.668826 !!! SPM_CONTROL_AFTERK: OFF
9173 13:08:50.671841 !!! SPM could not control APHY
9174 13:08:50.671941 IMPEDANCE_TRACKING: ON
9175 13:08:50.675060 TEMP_SENSOR: ON
9176 13:08:50.675151 HW_SAVE_FOR_SR: OFF
9177 13:08:50.678562 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9178 13:08:50.681987 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9179 13:08:50.685046 Read ODT Tracking: ON
9180 13:08:50.688753 Refresh Rate DeBounce: ON
9181 13:08:50.688850 DFS_NO_QUEUE_FLUSH: ON
9182 13:08:50.692069 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9183 13:08:50.695192 ENABLE_DFS_RUNTIME_MRW: OFF
9184 13:08:50.698617 DDR_RESERVE_NEW_MODE: ON
9185 13:08:50.698718 MR_CBT_SWITCH_FREQ: ON
9186 13:08:50.702076 =========================
9187 13:08:50.721058 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9188 13:08:50.724176 dram_init: ddr_geometry: 2
9189 13:08:50.742407 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9190 13:08:50.745822 dram_init: dram init end (result: 0)
9191 13:08:50.752183 DRAM-K: Full calibration passed in 24503 msecs
9192 13:08:50.755874 MRC: failed to locate region type 0.
9193 13:08:50.755974 DRAM rank0 size:0x100000000,
9194 13:08:50.759181 DRAM rank1 size=0x100000000
9195 13:08:50.769331 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9196 13:08:50.775806 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9197 13:08:50.782815 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9198 13:08:50.789058 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9199 13:08:50.792407 DRAM rank0 size:0x100000000,
9200 13:08:50.795845 DRAM rank1 size=0x100000000
9201 13:08:50.795947 CBMEM:
9202 13:08:50.799304 IMD: root @ 0xfffff000 254 entries.
9203 13:08:50.802858 IMD: root @ 0xffffec00 62 entries.
9204 13:08:50.806210 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9205 13:08:50.809434 WARNING: RO_VPD is uninitialized or empty.
9206 13:08:50.815855 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9207 13:08:50.822800 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9208 13:08:50.835324 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9209 13:08:50.846654 BS: romstage times (exec / console): total (unknown) / 24015 ms
9210 13:08:50.846817
9211 13:08:50.846992
9212 13:08:50.856993 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9213 13:08:50.860402 ARM64: Exception handlers installed.
9214 13:08:50.863693 ARM64: Testing exception
9215 13:08:50.866857 ARM64: Done test exception
9216 13:08:50.866935 Enumerating buses...
9217 13:08:50.870234 Show all devs... Before device enumeration.
9218 13:08:50.873285 Root Device: enabled 1
9219 13:08:50.876667 CPU_CLUSTER: 0: enabled 1
9220 13:08:50.876744 CPU: 00: enabled 1
9221 13:08:50.880178 Compare with tree...
9222 13:08:50.880255 Root Device: enabled 1
9223 13:08:50.883275 CPU_CLUSTER: 0: enabled 1
9224 13:08:50.886900 CPU: 00: enabled 1
9225 13:08:50.886977 Root Device scanning...
9226 13:08:50.889935 scan_static_bus for Root Device
9227 13:08:50.893028 CPU_CLUSTER: 0 enabled
9228 13:08:50.897039 scan_static_bus for Root Device done
9229 13:08:50.899720 scan_bus: bus Root Device finished in 8 msecs
9230 13:08:50.899809 done
9231 13:08:50.906549 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9232 13:08:50.910233 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9233 13:08:50.916569 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9234 13:08:50.920014 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9235 13:08:50.923802 Allocating resources...
9236 13:08:50.926704 Reading resources...
9237 13:08:50.930011 Root Device read_resources bus 0 link: 0
9238 13:08:50.930173 DRAM rank0 size:0x100000000,
9239 13:08:50.933150 DRAM rank1 size=0x100000000
9240 13:08:50.936916 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9241 13:08:50.939974 CPU: 00 missing read_resources
9242 13:08:50.943487 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9243 13:08:50.950087 Root Device read_resources bus 0 link: 0 done
9244 13:08:50.950450 Done reading resources.
9245 13:08:50.956979 Show resources in subtree (Root Device)...After reading.
9246 13:08:50.960005 Root Device child on link 0 CPU_CLUSTER: 0
9247 13:08:50.963662 CPU_CLUSTER: 0 child on link 0 CPU: 00
9248 13:08:50.973673 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9249 13:08:50.974252 CPU: 00
9250 13:08:50.976838 Root Device assign_resources, bus 0 link: 0
9251 13:08:50.980096 CPU_CLUSTER: 0 missing set_resources
9252 13:08:50.983613 Root Device assign_resources, bus 0 link: 0 done
9253 13:08:50.986977 Done setting resources.
9254 13:08:50.993473 Show resources in subtree (Root Device)...After assigning values.
9255 13:08:50.996618 Root Device child on link 0 CPU_CLUSTER: 0
9256 13:08:51.000105 CPU_CLUSTER: 0 child on link 0 CPU: 00
9257 13:08:51.010255 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9258 13:08:51.010793 CPU: 00
9259 13:08:51.013867 Done allocating resources.
9260 13:08:51.016434 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9261 13:08:51.020098 Enabling resources...
9262 13:08:51.020656 done.
9263 13:08:51.026605 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9264 13:08:51.027181 Initializing devices...
9265 13:08:51.029903 Root Device init
9266 13:08:51.030206 init hardware done!
9267 13:08:51.033386 0x00000018: ctrlr->caps
9268 13:08:51.036460 52.000 MHz: ctrlr->f_max
9269 13:08:51.036767 0.400 MHz: ctrlr->f_min
9270 13:08:51.040084 0x40ff8080: ctrlr->voltages
9271 13:08:51.040393 sclk: 390625
9272 13:08:51.043537 Bus Width = 1
9273 13:08:51.043839 sclk: 390625
9274 13:08:51.044074 Bus Width = 1
9275 13:08:51.046415 Early init status = 3
9276 13:08:51.053320 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9277 13:08:51.056457 in-header: 03 fc 00 00 01 00 00 00
9278 13:08:51.060131 in-data: 00
9279 13:08:51.063108 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9280 13:08:51.068130 in-header: 03 fd 00 00 00 00 00 00
9281 13:08:51.071271 in-data:
9282 13:08:51.074283 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9283 13:08:51.079157 in-header: 03 fc 00 00 01 00 00 00
9284 13:08:51.082844 in-data: 00
9285 13:08:51.085692 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9286 13:08:51.091242 in-header: 03 fd 00 00 00 00 00 00
9287 13:08:51.094468 in-data:
9288 13:08:51.098147 [SSUSB] Setting up USB HOST controller...
9289 13:08:51.101080 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9290 13:08:51.104611 [SSUSB] phy power-on done.
9291 13:08:51.107977 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9292 13:08:51.114596 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9293 13:08:51.117767 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9294 13:08:51.124630 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9295 13:08:51.131399 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9296 13:08:51.138112 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9297 13:08:51.144232 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9298 13:08:51.151386 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9299 13:08:51.154515 SPM: binary array size = 0x9dc
9300 13:08:51.157665 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9301 13:08:51.164345 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9302 13:08:51.171284 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9303 13:08:51.177557 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9304 13:08:51.181027 configure_display: Starting display init
9305 13:08:51.214716 anx7625_power_on_init: Init interface.
9306 13:08:51.217803 anx7625_disable_pd_protocol: Disabled PD feature.
9307 13:08:51.221155 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9308 13:08:51.249107 anx7625_start_dp_work: Secure OCM version=00
9309 13:08:51.252626 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9310 13:08:51.267473 sp_tx_get_edid_block: EDID Block = 1
9311 13:08:51.369423 Extracted contents:
9312 13:08:51.372980 header: 00 ff ff ff ff ff ff 00
9313 13:08:51.376086 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9314 13:08:51.379632 version: 01 04
9315 13:08:51.382787 basic params: 95 1f 11 78 0a
9316 13:08:51.386176 chroma info: 76 90 94 55 54 90 27 21 50 54
9317 13:08:51.389178 established: 00 00 00
9318 13:08:51.395707 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9319 13:08:51.399150 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9320 13:08:51.405527 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9321 13:08:51.412341 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9322 13:08:51.419029 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9323 13:08:51.422512 extensions: 00
9324 13:08:51.422603 checksum: fb
9325 13:08:51.422677
9326 13:08:51.425621 Manufacturer: IVO Model 57d Serial Number 0
9327 13:08:51.429139 Made week 0 of 2020
9328 13:08:51.429228 EDID version: 1.4
9329 13:08:51.432332 Digital display
9330 13:08:51.435905 6 bits per primary color channel
9331 13:08:51.435987 DisplayPort interface
9332 13:08:51.439141 Maximum image size: 31 cm x 17 cm
9333 13:08:51.442981 Gamma: 220%
9334 13:08:51.443046 Check DPMS levels
9335 13:08:51.445760 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9336 13:08:51.449059 First detailed timing is preferred timing
9337 13:08:51.452247 Established timings supported:
9338 13:08:51.455772 Standard timings supported:
9339 13:08:51.455870 Detailed timings
9340 13:08:51.462831 Hex of detail: 383680a07038204018303c0035ae10000019
9341 13:08:51.465607 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9342 13:08:51.472707 0780 0798 07c8 0820 hborder 0
9343 13:08:51.475649 0438 043b 0447 0458 vborder 0
9344 13:08:51.479261 -hsync -vsync
9345 13:08:51.479339 Did detailed timing
9346 13:08:51.482682 Hex of detail: 000000000000000000000000000000000000
9347 13:08:51.485996 Manufacturer-specified data, tag 0
9348 13:08:51.492642 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9349 13:08:51.492713 ASCII string: InfoVision
9350 13:08:51.499327 Hex of detail: 000000fe00523134304e574635205248200a
9351 13:08:51.502245 ASCII string: R140NWF5 RH
9352 13:08:51.502314 Checksum
9353 13:08:51.502372 Checksum: 0xfb (valid)
9354 13:08:51.508860 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9355 13:08:51.512445 DSI data_rate: 832800000 bps
9356 13:08:51.516119 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9357 13:08:51.519126 anx7625_parse_edid: pixelclock(138800).
9358 13:08:51.525606 hactive(1920), hsync(48), hfp(24), hbp(88)
9359 13:08:51.528846 vactive(1080), vsync(12), vfp(3), vbp(17)
9360 13:08:51.532344 anx7625_dsi_config: config dsi.
9361 13:08:51.538697 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9362 13:08:51.551668 anx7625_dsi_config: success to config DSI
9363 13:08:51.554657 anx7625_dp_start: MIPI phy setup OK.
9364 13:08:51.557842 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9365 13:08:51.561568 mtk_ddp_mode_set invalid vrefresh 60
9366 13:08:51.564645 main_disp_path_setup
9367 13:08:51.564721 ovl_layer_smi_id_en
9368 13:08:51.567999 ovl_layer_smi_id_en
9369 13:08:51.568076 ccorr_config
9370 13:08:51.568135 aal_config
9371 13:08:51.571613 gamma_config
9372 13:08:51.571717 postmask_config
9373 13:08:51.574793 dither_config
9374 13:08:51.577954 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9375 13:08:51.584766 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9376 13:08:51.588436 Root Device init finished in 555 msecs
9377 13:08:51.588508 CPU_CLUSTER: 0 init
9378 13:08:51.597847 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9379 13:08:51.601562 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9380 13:08:51.605113 APU_MBOX 0x190000b0 = 0x10001
9381 13:08:51.608159 APU_MBOX 0x190001b0 = 0x10001
9382 13:08:51.611517 APU_MBOX 0x190005b0 = 0x10001
9383 13:08:51.614677 APU_MBOX 0x190006b0 = 0x10001
9384 13:08:51.617886 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9385 13:08:51.630308 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9386 13:08:51.642778 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9387 13:08:51.649443 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9388 13:08:51.661042 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9389 13:08:51.670282 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9390 13:08:51.673698 CPU_CLUSTER: 0 init finished in 81 msecs
9391 13:08:51.676946 Devices initialized
9392 13:08:51.680272 Show all devs... After init.
9393 13:08:51.680342 Root Device: enabled 1
9394 13:08:51.683660 CPU_CLUSTER: 0: enabled 1
9395 13:08:51.687001 CPU: 00: enabled 1
9396 13:08:51.690081 BS: BS_DEV_INIT run times (exec / console): 214 / 447 ms
9397 13:08:51.694010 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9398 13:08:51.696742 ELOG: NV offset 0x57f000 size 0x1000
9399 13:08:51.703425 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9400 13:08:51.710476 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9401 13:08:51.714245 ELOG: Event(17) added with size 13 at 2024-07-18 13:08:41 UTC
9402 13:08:51.717079 out: cmd=0x121: 03 db 21 01 00 00 00 00
9403 13:08:51.720693 in-header: 03 5c 00 00 2c 00 00 00
9404 13:08:51.733664 in-data: e3 70 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9405 13:08:51.740569 ELOG: Event(A1) added with size 10 at 2024-07-18 13:08:41 UTC
9406 13:08:51.747064 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9407 13:08:51.750615 ELOG: Event(A0) added with size 9 at 2024-07-18 13:08:42 UTC
9408 13:08:51.757039 elog_add_boot_reason: Logged dev mode boot
9409 13:08:51.760633 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9410 13:08:51.763847 Finalize devices...
9411 13:08:51.763924 Devices finalized
9412 13:08:51.770466 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9413 13:08:51.774050 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9414 13:08:51.777265 in-header: 03 07 00 00 08 00 00 00
9415 13:08:51.780867 in-data: aa e4 47 04 13 02 00 00
9416 13:08:51.780944 Chrome EC: UHEPI supported
9417 13:08:51.787039 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9418 13:08:51.790886 in-header: 03 a9 00 00 08 00 00 00
9419 13:08:51.794375 in-data: 84 60 60 08 00 00 00 00
9420 13:08:51.800715 ELOG: Event(91) added with size 10 at 2024-07-18 13:08:42 UTC
9421 13:08:51.804193 Chrome EC: clear events_b mask to 0x0000000020004000
9422 13:08:51.810604 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9423 13:08:51.815546 in-header: 03 fd 00 00 00 00 00 00
9424 13:08:51.818833 in-data:
9425 13:08:51.822150 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9426 13:08:51.825521 Writing coreboot table at 0xffe64000
9427 13:08:51.828889 0. 000000000010a000-0000000000113fff: RAMSTAGE
9428 13:08:51.835766 1. 0000000040000000-00000000400fffff: RAM
9429 13:08:51.838884 2. 0000000040100000-000000004032afff: RAMSTAGE
9430 13:08:51.842326 3. 000000004032b000-00000000545fffff: RAM
9431 13:08:51.845571 4. 0000000054600000-000000005465ffff: BL31
9432 13:08:51.848691 5. 0000000054660000-00000000ffe63fff: RAM
9433 13:08:51.855535 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9434 13:08:51.858903 7. 0000000100000000-000000023fffffff: RAM
9435 13:08:51.862229 Passing 5 GPIOs to payload:
9436 13:08:51.865450 NAME | PORT | POLARITY | VALUE
9437 13:08:51.872012 EC in RW | 0x000000aa | low | undefined
9438 13:08:51.875602 EC interrupt | 0x00000005 | low | undefined
9439 13:08:51.878758 TPM interrupt | 0x000000ab | high | undefined
9440 13:08:51.885363 SD card detect | 0x00000011 | high | undefined
9441 13:08:51.888616 speaker enable | 0x00000093 | high | undefined
9442 13:08:51.892161 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9443 13:08:51.895336 in-header: 03 f9 00 00 02 00 00 00
9444 13:08:51.899120 in-data: 02 00
9445 13:08:51.899205 ADC[4]: Raw value=901401 ID=7
9446 13:08:51.902168 ADC[3]: Raw value=212810 ID=1
9447 13:08:51.905801 RAM Code: 0x71
9448 13:08:51.905878 ADC[6]: Raw value=74502 ID=0
9449 13:08:51.908954 ADC[5]: Raw value=211703 ID=1
9450 13:08:51.912218 SKU Code: 0x1
9451 13:08:51.915564 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum fdf0
9452 13:08:51.918860 coreboot table: 964 bytes.
9453 13:08:51.922429 IMD ROOT 0. 0xfffff000 0x00001000
9454 13:08:51.925419 IMD SMALL 1. 0xffffe000 0x00001000
9455 13:08:51.928709 RO MCACHE 2. 0xffffc000 0x00001104
9456 13:08:51.931995 CONSOLE 3. 0xfff7c000 0x00080000
9457 13:08:51.935371 FMAP 4. 0xfff7b000 0x00000452
9458 13:08:51.938722 TIME STAMP 5. 0xfff7a000 0x00000910
9459 13:08:51.942182 VBOOT WORK 6. 0xfff66000 0x00014000
9460 13:08:51.945086 RAMOOPS 7. 0xffe66000 0x00100000
9461 13:08:51.949014 COREBOOT 8. 0xffe64000 0x00002000
9462 13:08:51.949130 IMD small region:
9463 13:08:51.952120 IMD ROOT 0. 0xffffec00 0x00000400
9464 13:08:51.958945 VPD 1. 0xffffeb80 0x0000006c
9465 13:08:51.961861 MMC STATUS 2. 0xffffeb60 0x00000004
9466 13:08:51.965286 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9467 13:08:51.972090 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9468 13:08:52.012206 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9469 13:08:52.015270 Checking segment from ROM address 0x40100000
9470 13:08:52.018714 Checking segment from ROM address 0x4010001c
9471 13:08:52.025462 Loading segment from ROM address 0x40100000
9472 13:08:52.025544 code (compression=0)
9473 13:08:52.035328 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9474 13:08:52.042061 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9475 13:08:52.042141 it's not compressed!
9476 13:08:52.049140 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9477 13:08:52.052292 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9478 13:08:52.072771 Loading segment from ROM address 0x4010001c
9479 13:08:52.072853 Entry Point 0x80000000
9480 13:08:52.075640 Loaded segments
9481 13:08:52.079534 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9482 13:08:52.085710 Jumping to boot code at 0x80000000(0xffe64000)
9483 13:08:52.092245 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9484 13:08:52.098716 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9485 13:08:52.106948 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9486 13:08:52.110439 Checking segment from ROM address 0x40100000
9487 13:08:52.113703 Checking segment from ROM address 0x4010001c
9488 13:08:52.120507 Loading segment from ROM address 0x40100000
9489 13:08:52.120585 code (compression=1)
9490 13:08:52.127276 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9491 13:08:52.137174 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9492 13:08:52.137254 using LZMA
9493 13:08:52.145411 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9494 13:08:52.151957 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9495 13:08:52.155437 Loading segment from ROM address 0x4010001c
9496 13:08:52.155513 Entry Point 0x54601000
9497 13:08:52.158558 Loaded segments
9498 13:08:52.161992 NOTICE: MT8192 bl31_setup
9499 13:08:52.168934 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9500 13:08:52.172297 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9501 13:08:52.175580 WARNING: region 0:
9502 13:08:52.179183 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9503 13:08:52.179258 WARNING: region 1:
9504 13:08:52.185533 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9505 13:08:52.189018 WARNING: region 2:
9506 13:08:52.192238 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9507 13:08:52.195408 WARNING: region 3:
9508 13:08:52.198964 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9509 13:08:52.202259 WARNING: region 4:
9510 13:08:52.208963 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9511 13:08:52.209042 WARNING: region 5:
9512 13:08:52.212492 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9513 13:08:52.215301 WARNING: region 6:
9514 13:08:52.218712 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9515 13:08:52.222450 WARNING: region 7:
9516 13:08:52.225779 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9517 13:08:52.231984 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9518 13:08:52.235494 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9519 13:08:52.238796 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9520 13:08:52.245169 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9521 13:08:52.248684 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9522 13:08:52.252332 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9523 13:08:52.258650 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9524 13:08:52.261912 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9525 13:08:52.268804 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9526 13:08:52.272182 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9527 13:08:52.275751 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9528 13:08:52.282131 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9529 13:08:52.285255 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9530 13:08:52.289147 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9531 13:08:52.295774 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9532 13:08:52.298693 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9533 13:08:52.305625 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9534 13:08:52.308482 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9535 13:08:52.311741 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9536 13:08:52.318301 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9537 13:08:52.321743 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9538 13:08:52.328387 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9539 13:08:52.332134 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9540 13:08:52.334927 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9541 13:08:52.342007 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9542 13:08:52.345134 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9543 13:08:52.351757 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9544 13:08:52.355195 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9545 13:08:52.358373 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9546 13:08:52.365011 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9547 13:08:52.368465 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9548 13:08:52.372175 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9549 13:08:52.378874 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9550 13:08:52.382177 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9551 13:08:52.385255 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9552 13:08:52.388746 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9553 13:08:52.395382 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9554 13:08:52.398408 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9555 13:08:52.401918 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9556 13:08:52.404992 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9557 13:08:52.411988 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9558 13:08:52.415365 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9559 13:08:52.418657 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9560 13:08:52.422008 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9561 13:08:52.428918 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9562 13:08:52.432049 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9563 13:08:52.435392 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9564 13:08:52.442052 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9565 13:08:52.445667 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9566 13:08:52.448635 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9567 13:08:52.455524 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9568 13:08:52.458584 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9569 13:08:52.465121 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9570 13:08:52.468162 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9571 13:08:52.471771 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9572 13:08:52.478281 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9573 13:08:52.482074 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9574 13:08:52.488185 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9575 13:08:52.491558 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9576 13:08:52.498481 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9577 13:08:52.501917 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9578 13:08:52.504940 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9579 13:08:52.511827 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9580 13:08:52.515213 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9581 13:08:52.521674 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9582 13:08:52.525259 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9583 13:08:52.531520 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9584 13:08:52.535207 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9585 13:08:52.541571 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9586 13:08:52.545327 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9587 13:08:52.548345 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9588 13:08:52.554797 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9589 13:08:52.558277 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9590 13:08:52.564874 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9591 13:08:52.568367 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9592 13:08:52.575298 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9593 13:08:52.578307 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9594 13:08:52.581578 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9595 13:08:52.588678 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9596 13:08:52.591835 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9597 13:08:52.598370 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9598 13:08:52.601803 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9599 13:08:52.608492 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9600 13:08:52.611686 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9601 13:08:52.615332 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9602 13:08:52.621888 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9603 13:08:52.625042 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9604 13:08:52.632001 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9605 13:08:52.635015 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9606 13:08:52.641673 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9607 13:08:52.645196 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9608 13:08:52.648561 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9609 13:08:52.654854 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9610 13:08:52.658089 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9611 13:08:52.664775 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9612 13:08:52.668440 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9613 13:08:52.675160 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9614 13:08:52.678222 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9615 13:08:52.681786 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9616 13:08:52.684762 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9617 13:08:52.688449 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9618 13:08:52.694636 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9619 13:08:52.698067 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9620 13:08:52.704677 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9621 13:08:52.708144 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9622 13:08:52.711195 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9623 13:08:52.718048 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9624 13:08:52.721334 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9625 13:08:52.728013 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9626 13:08:52.731571 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9627 13:08:52.734527 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9628 13:08:52.741699 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9629 13:08:52.744676 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9630 13:08:52.751163 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9631 13:08:52.754542 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9632 13:08:52.761135 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9633 13:08:52.764433 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9634 13:08:52.768108 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9635 13:08:52.771247 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9636 13:08:52.778054 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9637 13:08:52.781134 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9638 13:08:52.784590 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9639 13:08:52.788045 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9640 13:08:52.794659 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9641 13:08:52.797491 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9642 13:08:52.800917 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9643 13:08:52.807499 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9644 13:08:52.810811 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9645 13:08:52.817678 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9646 13:08:52.821055 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9647 13:08:52.824130 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9648 13:08:52.830923 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9649 13:08:52.834198 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9650 13:08:52.840981 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9651 13:08:52.844742 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9652 13:08:52.847672 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9653 13:08:52.854037 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9654 13:08:52.857486 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9655 13:08:52.864026 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9656 13:08:52.867387 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9657 13:08:52.870686 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9658 13:08:52.877317 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9659 13:08:52.880702 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9660 13:08:52.887097 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9661 13:08:52.890581 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9662 13:08:52.894373 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9663 13:08:52.900941 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9664 13:08:52.904012 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9665 13:08:52.907277 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9666 13:08:52.913904 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9667 13:08:52.917108 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9668 13:08:52.923782 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9669 13:08:52.927167 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9670 13:08:52.930949 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9671 13:08:52.937400 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9672 13:08:52.940683 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9673 13:08:52.947290 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9674 13:08:52.950906 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9675 13:08:52.954392 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9676 13:08:52.960661 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9677 13:08:52.964166 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9678 13:08:52.967685 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9679 13:08:52.974275 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9680 13:08:52.977328 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9681 13:08:52.984737 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9682 13:08:52.987456 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9683 13:08:52.990797 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9684 13:08:52.997363 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9685 13:08:53.000840 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9686 13:08:53.007113 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9687 13:08:53.010654 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9688 13:08:53.013977 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9689 13:08:53.020824 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9690 13:08:53.023868 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9691 13:08:53.027161 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9692 13:08:53.033952 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9693 13:08:53.037060 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9694 13:08:53.044090 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9695 13:08:53.047616 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9696 13:08:53.050763 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9697 13:08:53.057305 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9698 13:08:53.060907 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9699 13:08:53.067717 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9700 13:08:53.070528 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9701 13:08:53.073936 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9702 13:08:53.080510 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9703 13:08:53.083982 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9704 13:08:53.087617 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9705 13:08:53.094562 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9706 13:08:53.097086 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9707 13:08:53.104163 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9708 13:08:53.107419 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9709 13:08:53.114204 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9710 13:08:53.117409 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9711 13:08:53.120716 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9712 13:08:53.127348 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9713 13:08:53.130743 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9714 13:08:53.137276 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9715 13:08:53.140626 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9716 13:08:53.143929 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9717 13:08:53.150537 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9718 13:08:53.153908 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9719 13:08:53.160838 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9720 13:08:53.163878 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9721 13:08:53.167578 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9722 13:08:53.174265 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9723 13:08:53.177330 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9724 13:08:53.183870 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9725 13:08:53.186990 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9726 13:08:53.194151 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9727 13:08:53.197296 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9728 13:08:53.200475 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9729 13:08:53.206997 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9730 13:08:53.210363 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9731 13:08:53.217356 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9732 13:08:53.220129 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9733 13:08:53.223557 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9734 13:08:53.230249 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9735 13:08:53.233500 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9736 13:08:53.240349 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9737 13:08:53.243581 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9738 13:08:53.250239 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9739 13:08:53.253522 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9740 13:08:53.257287 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9741 13:08:53.263579 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9742 13:08:53.266680 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9743 13:08:53.273524 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9744 13:08:53.276752 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9745 13:08:53.280285 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9746 13:08:53.287019 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9747 13:08:53.289978 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9748 13:08:53.293377 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9749 13:08:53.296860 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9750 13:08:53.303129 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9751 13:08:53.306495 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9752 13:08:53.310038 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9753 13:08:53.316558 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9754 13:08:53.320091 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9755 13:08:53.323155 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9756 13:08:53.329901 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9757 13:08:53.333098 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9758 13:08:53.340012 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9759 13:08:53.343197 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9760 13:08:53.346805 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9761 13:08:53.353074 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9762 13:08:53.356317 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9763 13:08:53.360249 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9764 13:08:53.366915 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9765 13:08:53.370774 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9766 13:08:53.373172 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9767 13:08:53.379999 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9768 13:08:53.383029 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9769 13:08:53.390056 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9770 13:08:53.393454 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9771 13:08:53.396451 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9772 13:08:53.403149 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9773 13:08:53.406931 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9774 13:08:53.409607 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9775 13:08:53.416318 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9776 13:08:53.419829 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9777 13:08:53.423105 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9778 13:08:53.429591 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9779 13:08:53.433097 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9780 13:08:53.436313 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9781 13:08:53.443183 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9782 13:08:53.446755 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9783 13:08:53.453054 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9784 13:08:53.456327 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9785 13:08:53.459795 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9786 13:08:53.463048 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9787 13:08:53.469851 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9788 13:08:53.473474 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9789 13:08:53.476696 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9790 13:08:53.479669 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9791 13:08:53.483086 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9792 13:08:53.490381 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9793 13:08:53.493023 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9794 13:08:53.496310 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9795 13:08:53.500378 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9796 13:08:53.506281 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9797 13:08:53.509737 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9798 13:08:53.512949 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9799 13:08:53.519795 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9800 13:08:53.523199 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9801 13:08:53.529989 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9802 13:08:53.533197 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9803 13:08:53.536362 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9804 13:08:53.543188 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9805 13:08:53.546379 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9806 13:08:53.553202 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9807 13:08:53.556649 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9808 13:08:53.559986 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9809 13:08:53.566918 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9810 13:08:53.569694 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9811 13:08:53.576414 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9812 13:08:53.579922 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9813 13:08:53.583288 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9814 13:08:53.590082 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9815 13:08:53.593026 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9816 13:08:53.599962 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9817 13:08:53.603626 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9818 13:08:53.606299 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9819 13:08:53.613014 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9820 13:08:53.616486 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9821 13:08:53.623469 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9822 13:08:53.626674 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9823 13:08:53.630113 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9824 13:08:53.636511 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9825 13:08:53.639774 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9826 13:08:53.646613 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9827 13:08:53.650377 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9828 13:08:53.653393 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9829 13:08:53.659844 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9830 13:08:53.663155 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9831 13:08:53.669853 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9832 13:08:53.673281 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9833 13:08:53.676558 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9834 13:08:53.683343 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9835 13:08:53.686925 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9836 13:08:53.693297 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9837 13:08:53.696515 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9838 13:08:53.699987 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9839 13:08:53.706767 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9840 13:08:53.709476 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9841 13:08:53.716378 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9842 13:08:53.719604 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9843 13:08:53.726439 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9844 13:08:53.729750 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9845 13:08:53.732877 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9846 13:08:53.739681 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9847 13:08:53.743504 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9848 13:08:53.749539 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9849 13:08:53.753005 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9850 13:08:53.756325 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9851 13:08:53.763117 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9852 13:08:53.766726 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9853 13:08:53.773052 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9854 13:08:53.776203 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9855 13:08:53.779615 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9856 13:08:53.786017 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9857 13:08:53.789536 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9858 13:08:53.796277 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9859 13:08:53.799361 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9860 13:08:53.806001 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9861 13:08:53.809148 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9862 13:08:53.812519 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9863 13:08:53.819320 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9864 13:08:53.822701 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9865 13:08:53.825771 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9866 13:08:53.832648 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9867 13:08:53.835753 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9868 13:08:53.842565 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9869 13:08:53.845784 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9870 13:08:53.848961 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9871 13:08:53.855922 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9872 13:08:53.859246 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9873 13:08:53.866170 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9874 13:08:53.869442 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9875 13:08:53.875706 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9876 13:08:53.879501 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9877 13:08:53.885968 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9878 13:08:53.889361 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9879 13:08:53.892539 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9880 13:08:53.899052 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9881 13:08:53.902748 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9882 13:08:53.909311 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9883 13:08:53.912355 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9884 13:08:53.919140 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9885 13:08:53.922873 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9886 13:08:53.925949 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9887 13:08:53.932405 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9888 13:08:53.935639 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9889 13:08:53.942890 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9890 13:08:53.946021 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9891 13:08:53.952452 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9892 13:08:53.956042 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9893 13:08:53.959452 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9894 13:08:53.966046 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9895 13:08:53.969328 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9896 13:08:53.976323 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9897 13:08:53.979224 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9898 13:08:53.985936 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9899 13:08:53.989933 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9900 13:08:53.992800 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9901 13:08:53.999101 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9902 13:08:54.002814 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9903 13:08:54.009418 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9904 13:08:54.012606 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9905 13:08:54.015873 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9906 13:08:54.022690 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9907 13:08:54.025767 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9908 13:08:54.032633 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9909 13:08:54.036177 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9910 13:08:54.043020 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9911 13:08:54.045964 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9912 13:08:54.049406 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9913 13:08:54.056017 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9914 13:08:54.059707 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9915 13:08:54.065845 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9916 13:08:54.069381 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9917 13:08:54.075802 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9918 13:08:54.079330 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9919 13:08:54.082715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9920 13:08:54.089893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9921 13:08:54.092627 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9922 13:08:54.099667 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9923 13:08:54.102795 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9924 13:08:54.109359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9925 13:08:54.112606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9926 13:08:54.119168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9927 13:08:54.122668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9928 13:08:54.129409 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9929 13:08:54.132853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9930 13:08:54.136141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9931 13:08:54.142624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9932 13:08:54.146246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9933 13:08:54.152687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9934 13:08:54.156262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9935 13:08:54.162969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9936 13:08:54.166116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9937 13:08:54.172994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9938 13:08:54.176216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9939 13:08:54.182636 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9940 13:08:54.186331 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9941 13:08:54.192812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9942 13:08:54.196402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9943 13:08:54.202657 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9944 13:08:54.206175 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9945 13:08:54.212869 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9946 13:08:54.215825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9947 13:08:54.222353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9948 13:08:54.225947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9949 13:08:54.232134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9950 13:08:54.235577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9951 13:08:54.242370 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9952 13:08:54.242447 INFO: [APUAPC] vio 0
9953 13:08:54.248868 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9954 13:08:54.252460 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9955 13:08:54.255757 INFO: [APUAPC] D0_APC_0: 0x400510
9956 13:08:54.258883 INFO: [APUAPC] D0_APC_1: 0x0
9957 13:08:54.262677 INFO: [APUAPC] D0_APC_2: 0x1540
9958 13:08:54.266013 INFO: [APUAPC] D0_APC_3: 0x0
9959 13:08:54.269301 INFO: [APUAPC] D1_APC_0: 0xffffffff
9960 13:08:54.272423 INFO: [APUAPC] D1_APC_1: 0xffffffff
9961 13:08:54.275494 INFO: [APUAPC] D1_APC_2: 0x3fffff
9962 13:08:54.278970 INFO: [APUAPC] D1_APC_3: 0x0
9963 13:08:54.282544 INFO: [APUAPC] D2_APC_0: 0xffffffff
9964 13:08:54.285654 INFO: [APUAPC] D2_APC_1: 0xffffffff
9965 13:08:54.289207 INFO: [APUAPC] D2_APC_2: 0x3fffff
9966 13:08:54.292531 INFO: [APUAPC] D2_APC_3: 0x0
9967 13:08:54.296143 INFO: [APUAPC] D3_APC_0: 0xffffffff
9968 13:08:54.299074 INFO: [APUAPC] D3_APC_1: 0xffffffff
9969 13:08:54.302745 INFO: [APUAPC] D3_APC_2: 0x3fffff
9970 13:08:54.302822 INFO: [APUAPC] D3_APC_3: 0x0
9971 13:08:54.306007 INFO: [APUAPC] D4_APC_0: 0xffffffff
9972 13:08:54.309384 INFO: [APUAPC] D4_APC_1: 0xffffffff
9973 13:08:54.312191 INFO: [APUAPC] D4_APC_2: 0x3fffff
9974 13:08:54.315700 INFO: [APUAPC] D4_APC_3: 0x0
9975 13:08:54.319072 INFO: [APUAPC] D5_APC_0: 0xffffffff
9976 13:08:54.322854 INFO: [APUAPC] D5_APC_1: 0xffffffff
9977 13:08:54.325686 INFO: [APUAPC] D5_APC_2: 0x3fffff
9978 13:08:54.329321 INFO: [APUAPC] D5_APC_3: 0x0
9979 13:08:54.332313 INFO: [APUAPC] D6_APC_0: 0xffffffff
9980 13:08:54.335800 INFO: [APUAPC] D6_APC_1: 0xffffffff
9981 13:08:54.338955 INFO: [APUAPC] D6_APC_2: 0x3fffff
9982 13:08:54.342191 INFO: [APUAPC] D6_APC_3: 0x0
9983 13:08:54.345782 INFO: [APUAPC] D7_APC_0: 0xffffffff
9984 13:08:54.348947 INFO: [APUAPC] D7_APC_1: 0xffffffff
9985 13:08:54.352338 INFO: [APUAPC] D7_APC_2: 0x3fffff
9986 13:08:54.355606 INFO: [APUAPC] D7_APC_3: 0x0
9987 13:08:54.358908 INFO: [APUAPC] D8_APC_0: 0xffffffff
9988 13:08:54.362416 INFO: [APUAPC] D8_APC_1: 0xffffffff
9989 13:08:54.365958 INFO: [APUAPC] D8_APC_2: 0x3fffff
9990 13:08:54.369401 INFO: [APUAPC] D8_APC_3: 0x0
9991 13:08:54.372292 INFO: [APUAPC] D9_APC_0: 0xffffffff
9992 13:08:54.375600 INFO: [APUAPC] D9_APC_1: 0xffffffff
9993 13:08:54.378853 INFO: [APUAPC] D9_APC_2: 0x3fffff
9994 13:08:54.382219 INFO: [APUAPC] D9_APC_3: 0x0
9995 13:08:54.385949 INFO: [APUAPC] D10_APC_0: 0xffffffff
9996 13:08:54.388980 INFO: [APUAPC] D10_APC_1: 0xffffffff
9997 13:08:54.392078 INFO: [APUAPC] D10_APC_2: 0x3fffff
9998 13:08:54.395477 INFO: [APUAPC] D10_APC_3: 0x0
9999 13:08:54.399466 INFO: [APUAPC] D11_APC_0: 0xffffffff
10000 13:08:54.402264 INFO: [APUAPC] D11_APC_1: 0xffffffff
10001 13:08:54.405608 INFO: [APUAPC] D11_APC_2: 0x3fffff
10002 13:08:54.409119 INFO: [APUAPC] D11_APC_3: 0x0
10003 13:08:54.412584 INFO: [APUAPC] D12_APC_0: 0xffffffff
10004 13:08:54.415625 INFO: [APUAPC] D12_APC_1: 0xffffffff
10005 13:08:54.418930 INFO: [APUAPC] D12_APC_2: 0x3fffff
10006 13:08:54.422437 INFO: [APUAPC] D12_APC_3: 0x0
10007 13:08:54.425792 INFO: [APUAPC] D13_APC_0: 0xffffffff
10008 13:08:54.429066 INFO: [APUAPC] D13_APC_1: 0xffffffff
10009 13:08:54.432264 INFO: [APUAPC] D13_APC_2: 0x3fffff
10010 13:08:54.435762 INFO: [APUAPC] D13_APC_3: 0x0
10011 13:08:54.438942 INFO: [APUAPC] D14_APC_0: 0xffffffff
10012 13:08:54.442150 INFO: [APUAPC] D14_APC_1: 0xffffffff
10013 13:08:54.445668 INFO: [APUAPC] D14_APC_2: 0x3fffff
10014 13:08:54.448921 INFO: [APUAPC] D14_APC_3: 0x0
10015 13:08:54.452378 INFO: [APUAPC] D15_APC_0: 0xffffffff
10016 13:08:54.455633 INFO: [APUAPC] D15_APC_1: 0xffffffff
10017 13:08:54.458994 INFO: [APUAPC] D15_APC_2: 0x3fffff
10018 13:08:54.462223 INFO: [APUAPC] D15_APC_3: 0x0
10019 13:08:54.465732 INFO: [APUAPC] APC_CON: 0x4
10020 13:08:54.469246 INFO: [NOCDAPC] D0_APC_0: 0x0
10021 13:08:54.469322 INFO: [NOCDAPC] D0_APC_1: 0x0
10022 13:08:54.472347 INFO: [NOCDAPC] D1_APC_0: 0x0
10023 13:08:54.475851 INFO: [NOCDAPC] D1_APC_1: 0xfff
10024 13:08:54.479134 INFO: [NOCDAPC] D2_APC_0: 0x0
10025 13:08:54.482348 INFO: [NOCDAPC] D2_APC_1: 0xfff
10026 13:08:54.485806 INFO: [NOCDAPC] D3_APC_0: 0x0
10027 13:08:54.489046 INFO: [NOCDAPC] D3_APC_1: 0xfff
10028 13:08:54.492445 INFO: [NOCDAPC] D4_APC_0: 0x0
10029 13:08:54.495625 INFO: [NOCDAPC] D4_APC_1: 0xfff
10030 13:08:54.498730 INFO: [NOCDAPC] D5_APC_0: 0x0
10031 13:08:54.502411 INFO: [NOCDAPC] D5_APC_1: 0xfff
10032 13:08:54.502488 INFO: [NOCDAPC] D6_APC_0: 0x0
10033 13:08:54.505511 INFO: [NOCDAPC] D6_APC_1: 0xfff
10034 13:08:54.509003 INFO: [NOCDAPC] D7_APC_0: 0x0
10035 13:08:54.512446 INFO: [NOCDAPC] D7_APC_1: 0xfff
10036 13:08:54.515332 INFO: [NOCDAPC] D8_APC_0: 0x0
10037 13:08:54.518680 INFO: [NOCDAPC] D8_APC_1: 0xfff
10038 13:08:54.522419 INFO: [NOCDAPC] D9_APC_0: 0x0
10039 13:08:54.525338 INFO: [NOCDAPC] D9_APC_1: 0xfff
10040 13:08:54.528904 INFO: [NOCDAPC] D10_APC_0: 0x0
10041 13:08:54.532187 INFO: [NOCDAPC] D10_APC_1: 0xfff
10042 13:08:54.535425 INFO: [NOCDAPC] D11_APC_0: 0x0
10043 13:08:54.539122 INFO: [NOCDAPC] D11_APC_1: 0xfff
10044 13:08:54.539220 INFO: [NOCDAPC] D12_APC_0: 0x0
10045 13:08:54.542252 INFO: [NOCDAPC] D12_APC_1: 0xfff
10046 13:08:54.545818 INFO: [NOCDAPC] D13_APC_0: 0x0
10047 13:08:54.549167 INFO: [NOCDAPC] D13_APC_1: 0xfff
10048 13:08:54.552295 INFO: [NOCDAPC] D14_APC_0: 0x0
10049 13:08:54.555799 INFO: [NOCDAPC] D14_APC_1: 0xfff
10050 13:08:54.558717 INFO: [NOCDAPC] D15_APC_0: 0x0
10051 13:08:54.562064 INFO: [NOCDAPC] D15_APC_1: 0xfff
10052 13:08:54.565412 INFO: [NOCDAPC] APC_CON: 0x4
10053 13:08:54.568875 INFO: [APUAPC] set_apusys_apc done
10054 13:08:54.572255 INFO: [DEVAPC] devapc_init done
10055 13:08:54.575540 INFO: GICv3 without legacy support detected.
10056 13:08:54.578747 INFO: ARM GICv3 driver initialized in EL3
10057 13:08:54.582112 INFO: Maximum SPI INTID supported: 639
10058 13:08:54.588776 INFO: BL31: Initializing runtime services
10059 13:08:54.592188 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10060 13:08:54.595522 INFO: SPM: enable CPC mode
10061 13:08:54.602074 INFO: mcdi ready for mcusys-off-idle and system suspend
10062 13:08:54.605391 INFO: BL31: Preparing for EL3 exit to normal world
10063 13:08:54.608843 INFO: Entry point address = 0x80000000
10064 13:08:54.612241 INFO: SPSR = 0x8
10065 13:08:54.616893
10066 13:08:54.616968
10067 13:08:54.617058
10068 13:08:54.620422 Starting depthcharge on Spherion...
10069 13:08:54.620498
10070 13:08:54.620556 Wipe memory regions:
10071 13:08:54.620610
10072 13:08:54.621291 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10073 13:08:54.621382 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10074 13:08:54.621455 Setting prompt string to ['asurada:']
10075 13:08:54.621520 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10076 13:08:54.623969 [0x00000040000000, 0x00000054600000)
10077 13:08:54.746200
10078 13:08:54.746330 [0x00000054660000, 0x00000080000000)
10079 13:08:55.006579
10080 13:08:55.006754 [0x000000821a7280, 0x000000ffe64000)
10081 13:08:55.751168
10082 13:08:55.751300 [0x00000100000000, 0x00000240000000)
10083 13:08:57.641242
10084 13:08:57.644908 Initializing XHCI USB controller at 0x11200000.
10085 13:08:58.683084
10086 13:08:58.686127 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10087 13:08:58.686206
10088 13:08:58.686266
10089 13:08:58.686528 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10090 13:08:58.686599 Sending line: 'tftpboot 192.168.201.1 14878975/tftp-deploy-49h2gz7q/kernel/image.itb 14878975/tftp-deploy-49h2gz7q/kernel/cmdline '
10092 13:08:58.787019 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10093 13:08:58.787139 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10094 13:08:58.791115 asurada: tftpboot 192.168.201.1 14878975/tftp-deploy-49h2gz7q/kernel/image.ittp-deploy-49h2gz7q/kernel/cmdline
10095 13:08:58.791201
10096 13:08:58.791261 Waiting for link
10097 13:08:58.949343
10098 13:08:58.949467 R8152: Initializing
10099 13:08:58.949528
10100 13:08:58.952562 Version 9 (ocp_data = 6010)
10101 13:08:58.952628
10102 13:08:58.955950 R8152: Done initializing
10103 13:08:58.956016
10104 13:08:58.956080 Adding net device
10105 13:09:00.904048
10106 13:09:00.904165 done.
10107 13:09:00.904236
10108 13:09:00.904292 MAC: 00:e0:4c:72:2d:d6
10109 13:09:00.904346
10110 13:09:00.907585 Sending DHCP discover... done.
10111 13:09:00.907656
10112 13:09:00.911009 Waiting for reply... done.
10113 13:09:00.911090
10114 13:09:00.913987 Sending DHCP request... done.
10115 13:09:00.914063
10116 13:09:00.914122 Waiting for reply... done.
10117 13:09:00.914176
10118 13:09:00.917401 My ip is 192.168.201.21
10119 13:09:00.917477
10120 13:09:00.920934 The DHCP server ip is 192.168.201.1
10121 13:09:00.921010
10122 13:09:00.924129 TFTP server IP predefined by user: 192.168.201.1
10123 13:09:00.924206
10124 13:09:00.930741 Bootfile predefined by user: 14878975/tftp-deploy-49h2gz7q/kernel/image.itb
10125 13:09:00.930817
10126 13:09:00.934053 Sending tftp read request... done.
10127 13:09:00.934129
10128 13:09:00.937296 Waiting for the transfer...
10129 13:09:00.937403
10130 13:09:01.199488 00000000 ################################################################
10131 13:09:01.199649
10132 13:09:01.446292 00080000 ################################################################
10133 13:09:01.446418
10134 13:09:01.694017 00100000 ################################################################
10135 13:09:01.694153
10136 13:09:01.942641 00180000 ################################################################
10137 13:09:01.942769
10138 13:09:02.188571 00200000 ################################################################
10139 13:09:02.188724
10140 13:09:02.438081 00280000 ################################################################
10141 13:09:02.438224
10142 13:09:02.685704 00300000 ################################################################
10143 13:09:02.685838
10144 13:09:02.931989 00380000 ################################################################
10145 13:09:02.932122
10146 13:09:03.174126 00400000 ################################################################
10147 13:09:03.174288
10148 13:09:03.420078 00480000 ################################################################
10149 13:09:03.420240
10150 13:09:03.665187 00500000 ################################################################
10151 13:09:03.665372
10152 13:09:03.930306 00580000 ################################################################
10153 13:09:03.930448
10154 13:09:04.202818 00600000 ################################################################
10155 13:09:04.202932
10156 13:09:04.488252 00680000 ################################################################
10157 13:09:04.488407
10158 13:09:04.746139 00700000 ################################################################
10159 13:09:04.746291
10160 13:09:05.008535 00780000 ################################################################
10161 13:09:05.008674
10162 13:09:05.268475 00800000 ################################################################
10163 13:09:05.268618
10164 13:09:05.519809 00880000 ################################################################
10165 13:09:05.519953
10166 13:09:05.775750 00900000 ################################################################
10167 13:09:05.775889
10168 13:09:06.034469 00980000 ################################################################
10169 13:09:06.034612
10170 13:09:06.292582 00a00000 ################################################################
10171 13:09:06.292725
10172 13:09:06.542957 00a80000 ################################################################
10173 13:09:06.543108
10174 13:09:06.800961 00b00000 ################################################################
10175 13:09:06.801105
10176 13:09:07.064185 00b80000 ################################################################
10177 13:09:07.064323
10178 13:09:07.329108 00c00000 ################################################################
10179 13:09:07.329274
10180 13:09:07.594418 00c80000 ################################################################
10181 13:09:07.594570
10182 13:09:07.853272 00d00000 ################################################################
10183 13:09:07.853428
10184 13:09:08.105049 00d80000 ################################################################
10185 13:09:08.105228
10186 13:09:08.358607 00e00000 ################################################################
10187 13:09:08.358735
10188 13:09:08.611403 00e80000 ################################################################
10189 13:09:08.611559
10190 13:09:08.866673 00f00000 ################################################################
10191 13:09:08.866806
10192 13:09:09.115328 00f80000 ################################################################
10193 13:09:09.115470
10194 13:09:09.362785 01000000 ################################################################
10195 13:09:09.362914
10196 13:09:09.613374 01080000 ################################################################
10197 13:09:09.613501
10198 13:09:09.866993 01100000 ################################################################
10199 13:09:09.867118
10200 13:09:10.129820 01180000 ################################################################
10201 13:09:10.129940
10202 13:09:10.395913 01200000 ################################################################
10203 13:09:10.396047
10204 13:09:10.666409 01280000 ################################################################
10205 13:09:10.666563
10206 13:09:10.937210 01300000 ################################################################
10207 13:09:10.937335
10208 13:09:11.199484 01380000 ################################################################
10209 13:09:11.199613
10210 13:09:11.472577 01400000 ################################################################
10211 13:09:11.472710
10212 13:09:11.730125 01480000 ################################################################
10213 13:09:11.730259
10214 13:09:11.988239 01500000 ################################################################
10215 13:09:11.988388
10216 13:09:12.261366 01580000 ################################################################
10217 13:09:12.261526
10218 13:09:12.516744 01600000 ################################################################
10219 13:09:12.516858
10220 13:09:12.765207 01680000 ################################################################
10221 13:09:12.765322
10222 13:09:13.012871 01700000 ################################################################
10223 13:09:13.012984
10224 13:09:13.262875 01780000 ################################################################
10225 13:09:13.262989
10226 13:09:13.538075 01800000 ################################################################
10227 13:09:13.538207
10228 13:09:13.795478 01880000 ################################################################
10229 13:09:13.795620
10230 13:09:14.047930 01900000 ################################################################
10231 13:09:14.048050
10232 13:09:14.312092 01980000 ################################################################
10233 13:09:14.312221
10234 13:09:14.562320 01a00000 ################################################################
10235 13:09:14.562447
10236 13:09:14.812899 01a80000 ################################################################
10237 13:09:14.813043
10238 13:09:15.073695 01b00000 ################################################################
10239 13:09:15.073818
10240 13:09:15.326682 01b80000 ################################################################
10241 13:09:15.326793
10242 13:09:15.572728 01c00000 ################################################################
10243 13:09:15.572837
10244 13:09:15.821606 01c80000 ################################################################
10245 13:09:15.821744
10246 13:09:16.068441 01d00000 ################################################################
10247 13:09:16.068583
10248 13:09:16.313810 01d80000 ################################################################
10249 13:09:16.313951
10250 13:09:16.511575 01e00000 ##################################################### done.
10251 13:09:16.511724
10252 13:09:16.514815 The bootfile was 31886626 bytes long.
10253 13:09:16.514884
10254 13:09:16.518294 Sending tftp read request... done.
10255 13:09:16.518380
10256 13:09:16.521717 Waiting for the transfer...
10257 13:09:16.521807
10258 13:09:16.521876 00000000 # done.
10259 13:09:16.521942
10260 13:09:16.531687 Command line loaded dynamically from TFTP file: 14878975/tftp-deploy-49h2gz7q/kernel/cmdline
10261 13:09:16.531795
10262 13:09:16.551753 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14878975/extract-nfsrootfs-uz7mtp0l,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10263 13:09:16.554756
10264 13:09:16.554928 Loading FIT.
10265 13:09:16.555057
10266 13:09:16.558515 Image ramdisk-1 has 18722872 bytes.
10267 13:09:16.558711
10268 13:09:16.561436 Image fdt-1 has 47258 bytes.
10269 13:09:16.561675
10270 13:09:16.564726 Image kernel-1 has 13114469 bytes.
10271 13:09:16.565049
10272 13:09:16.572033 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10273 13:09:16.572427
10274 13:09:16.591655 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10275 13:09:16.592145
10276 13:09:16.595281 Choosing best match conf-1 for compat google,spherion-rev2.
10277 13:09:16.599477
10278 13:09:16.604162 Connected to device vid:did:rid of 1ae0:0028:00
10279 13:09:16.612463
10280 13:09:16.615940 tpm_get_response: command 0x17b, return code 0x0
10281 13:09:16.616499
10282 13:09:16.618954 ec_init: CrosEC protocol v3 supported (256, 248)
10283 13:09:16.623982
10284 13:09:16.627461 tpm_cleanup: add release locality here.
10285 13:09:16.627836
10286 13:09:16.628176 Shutting down all USB controllers.
10287 13:09:16.630857
10288 13:09:16.631123 Removing current net device
10289 13:09:16.631374
10290 13:09:16.637251 Exiting depthcharge with code 4 at timestamp: 51343886
10291 13:09:16.637490
10292 13:09:16.640947 LZMA decompressing kernel-1 to 0x821a6718
10293 13:09:16.641186
10294 13:09:16.643742 LZMA decompressing kernel-1 to 0x40000000
10295 13:09:18.259844
10296 13:09:18.260474 jumping to kernel
10297 13:09:18.262315 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10298 13:09:18.262777 start: 2.2.5 auto-login-action (timeout 00:03:57) [common]
10299 13:09:18.263110 Setting prompt string to ['Linux version [0-9]']
10300 13:09:18.263432 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10301 13:09:18.263747 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10302 13:09:18.340615
10303 13:09:18.343559 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10304 13:09:18.347452 start: 2.2.5.1 login-action (timeout 00:03:57) [common]
10305 13:09:18.348135 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10306 13:09:18.348667 Setting prompt string to []
10307 13:09:18.349269 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10308 13:09:18.349706 Using line separator: #'\n'#
10309 13:09:18.350020 No login prompt set.
10310 13:09:18.350426 Parsing kernel messages
10311 13:09:18.350724 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10312 13:09:18.351285 [login-action] Waiting for messages, (timeout 00:03:57)
10313 13:09:18.351620 Waiting using forced prompt support (timeout 00:01:58)
10314 13:09:18.366954 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j272990-arm64-gcc-12-defconfig-arm64-chromebook-fgzcq) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024
10315 13:09:18.369972 [ 0.000000] random: crng init done
10316 13:09:18.373854 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10317 13:09:18.376648 [ 0.000000] efi: UEFI not found.
10318 13:09:18.386881 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10319 13:09:18.393843 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10320 13:09:18.403612 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10321 13:09:18.413216 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10322 13:09:18.420010 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10323 13:09:18.423501 [ 0.000000] printk: bootconsole [mtk8250] enabled
10324 13:09:18.431291 [ 0.000000] NUMA: No NUMA configuration found
10325 13:09:18.438224 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10326 13:09:18.445246 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10327 13:09:18.445703 [ 0.000000] Zone ranges:
10328 13:09:18.451392 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10329 13:09:18.454424 [ 0.000000] DMA32 empty
10330 13:09:18.460898 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10331 13:09:18.464334 [ 0.000000] Movable zone start for each node
10332 13:09:18.467853 [ 0.000000] Early memory node ranges
10333 13:09:18.474445 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10334 13:09:18.480937 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10335 13:09:18.487792 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10336 13:09:18.494570 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10337 13:09:18.500858 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10338 13:09:18.507682 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10339 13:09:18.564485 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10340 13:09:18.571052 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10341 13:09:18.577621 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10342 13:09:18.581030 [ 0.000000] psci: probing for conduit method from DT.
10343 13:09:18.587913 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10344 13:09:18.591203 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10345 13:09:18.597689 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10346 13:09:18.601166 [ 0.000000] psci: SMC Calling Convention v1.2
10347 13:09:18.607960 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10348 13:09:18.610510 [ 0.000000] Detected VIPT I-cache on CPU0
10349 13:09:18.617522 [ 0.000000] CPU features: detected: GIC system register CPU interface
10350 13:09:18.624176 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10351 13:09:18.630847 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10352 13:09:18.637505 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10353 13:09:18.647145 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10354 13:09:18.653505 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10355 13:09:18.656886 [ 0.000000] alternatives: applying boot alternatives
10356 13:09:18.663571 [ 0.000000] Fallback order for Node 0: 0
10357 13:09:18.669880 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10358 13:09:18.673438 [ 0.000000] Policy zone: Normal
10359 13:09:18.696705 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14878975/extract-nfsrootfs-uz7mtp0l,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10360 13:09:18.706255 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10361 13:09:18.717247 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10362 13:09:18.727120 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10363 13:09:18.733967 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10364 13:09:18.737207 <6>[ 0.000000] software IO TLB: area num 8.
10365 13:09:18.793996 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10366 13:09:18.943704 <6>[ 0.000000] Memory: 7945776K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 406992K reserved, 32768K cma-reserved)
10367 13:09:18.950120 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10368 13:09:18.956726 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10369 13:09:18.960087 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10370 13:09:18.966706 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10371 13:09:18.973334 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10372 13:09:18.976815 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10373 13:09:18.986161 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10374 13:09:18.993060 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10375 13:09:18.999400 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10376 13:09:19.005892 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10377 13:09:19.009238 <6>[ 0.000000] GICv3: 608 SPIs implemented
10378 13:09:19.012708 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10379 13:09:19.019567 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10380 13:09:19.022571 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10381 13:09:19.029259 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10382 13:09:19.042337 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10383 13:09:19.055478 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10384 13:09:19.062376 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10385 13:09:19.070313 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10386 13:09:19.083598 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10387 13:09:19.089306 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10388 13:09:19.096180 <6>[ 0.009183] Console: colour dummy device 80x25
10389 13:09:19.106637 <6>[ 0.013915] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10390 13:09:19.113175 <6>[ 0.024421] pid_max: default: 32768 minimum: 301
10391 13:09:19.116480 <6>[ 0.029323] LSM: Security Framework initializing
10392 13:09:19.123002 <6>[ 0.034292] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10393 13:09:19.132964 <6>[ 0.042104] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10394 13:09:19.139542 <6>[ 0.051520] cblist_init_generic: Setting adjustable number of callback queues.
10395 13:09:19.146516 <6>[ 0.058959] cblist_init_generic: Setting shift to 3 and lim to 1.
10396 13:09:19.155974 <6>[ 0.065298] cblist_init_generic: Setting adjustable number of callback queues.
10397 13:09:19.162709 <6>[ 0.072724] cblist_init_generic: Setting shift to 3 and lim to 1.
10398 13:09:19.165941 <6>[ 0.079154] rcu: Hierarchical SRCU implementation.
10399 13:09:19.172509 <6>[ 0.084170] rcu: Max phase no-delay instances is 1000.
10400 13:09:19.179466 <6>[ 0.091199] EFI services will not be available.
10401 13:09:19.182192 <6>[ 0.096133] smp: Bringing up secondary CPUs ...
10402 13:09:19.190596 <6>[ 0.101184] Detected VIPT I-cache on CPU1
10403 13:09:19.197392 <6>[ 0.101255] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10404 13:09:19.204103 <6>[ 0.101285] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10405 13:09:19.207074 <6>[ 0.101621] Detected VIPT I-cache on CPU2
10406 13:09:19.217246 <6>[ 0.101674] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10407 13:09:19.223407 <6>[ 0.101692] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10408 13:09:19.227293 <6>[ 0.101955] Detected VIPT I-cache on CPU3
10409 13:09:19.233592 <6>[ 0.102003] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10410 13:09:19.239953 <6>[ 0.102017] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10411 13:09:19.243306 <6>[ 0.102323] CPU features: detected: Spectre-v4
10412 13:09:19.250373 <6>[ 0.102330] CPU features: detected: Spectre-BHB
10413 13:09:19.253821 <6>[ 0.102335] Detected PIPT I-cache on CPU4
10414 13:09:19.259799 <6>[ 0.102399] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10415 13:09:19.266604 <6>[ 0.102415] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10416 13:09:19.273278 <6>[ 0.102713] Detected PIPT I-cache on CPU5
10417 13:09:19.280061 <6>[ 0.102776] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10418 13:09:19.286492 <6>[ 0.102792] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10419 13:09:19.289766 <6>[ 0.103077] Detected PIPT I-cache on CPU6
10420 13:09:19.295968 <6>[ 0.103147] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10421 13:09:19.303153 <6>[ 0.103162] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10422 13:09:19.309491 <6>[ 0.103462] Detected PIPT I-cache on CPU7
10423 13:09:19.315948 <6>[ 0.103529] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10424 13:09:19.322589 <6>[ 0.103545] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10425 13:09:19.326131 <6>[ 0.103592] smp: Brought up 1 node, 8 CPUs
10426 13:09:19.332776 <6>[ 0.244978] SMP: Total of 8 processors activated.
10427 13:09:19.335700 <6>[ 0.249900] CPU features: detected: 32-bit EL0 Support
10428 13:09:19.345650 <6>[ 0.255263] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10429 13:09:19.352368 <6>[ 0.264117] CPU features: detected: Common not Private translations
10430 13:09:19.358726 <6>[ 0.270593] CPU features: detected: CRC32 instructions
10431 13:09:19.365699 <6>[ 0.275945] CPU features: detected: RCpc load-acquire (LDAPR)
10432 13:09:19.368902 <6>[ 0.281905] CPU features: detected: LSE atomic instructions
10433 13:09:19.375486 <6>[ 0.287686] CPU features: detected: Privileged Access Never
10434 13:09:19.381969 <6>[ 0.293465] CPU features: detected: RAS Extension Support
10435 13:09:19.388366 <6>[ 0.299074] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10436 13:09:19.391646 <6>[ 0.306293] CPU: All CPU(s) started at EL2
10437 13:09:19.398393 <6>[ 0.310610] alternatives: applying system-wide alternatives
10438 13:09:19.408984 <6>[ 0.321520] devtmpfs: initialized
10439 13:09:19.424339 <6>[ 0.330426] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10440 13:09:19.430654 <6>[ 0.340388] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10441 13:09:19.437500 <6>[ 0.348516] pinctrl core: initialized pinctrl subsystem
10442 13:09:19.440591 <6>[ 0.355413] DMI not present or invalid.
10443 13:09:19.446935 <6>[ 0.359834] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10444 13:09:19.457428 <6>[ 0.366736] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10445 13:09:19.463995 <6>[ 0.374320] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10446 13:09:19.473614 <6>[ 0.382552] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10447 13:09:19.477225 <6>[ 0.390798] audit: initializing netlink subsys (disabled)
10448 13:09:19.486739 <5>[ 0.396494] audit: type=2000 audit(0.284:1): state=initialized audit_enabled=0 res=1
10449 13:09:19.493824 <6>[ 0.397285] thermal_sys: Registered thermal governor 'step_wise'
10450 13:09:19.499882 <6>[ 0.404459] thermal_sys: Registered thermal governor 'power_allocator'
10451 13:09:19.503207 <6>[ 0.410713] cpuidle: using governor menu
10452 13:09:19.510017 <6>[ 0.421676] NET: Registered PF_QIPCRTR protocol family
10453 13:09:19.516953 <6>[ 0.427186] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10454 13:09:19.522988 <6>[ 0.434286] ASID allocator initialised with 32768 entries
10455 13:09:19.526572 <6>[ 0.440948] Serial: AMBA PL011 UART driver
10456 13:09:19.537978 <4>[ 0.451071] Trying to register duplicate clock ID: 134
10457 13:09:19.598609 <6>[ 0.514669] KASLR enabled
10458 13:09:19.612580 <6>[ 0.522323] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10459 13:09:19.619877 <6>[ 0.529337] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10460 13:09:19.626170 <6>[ 0.535827] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10461 13:09:19.632454 <6>[ 0.542832] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10462 13:09:19.639580 <6>[ 0.549318] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10463 13:09:19.645938 <6>[ 0.556320] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10464 13:09:19.652517 <6>[ 0.562807] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10465 13:09:19.659002 <6>[ 0.569812] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10466 13:09:19.662734 <6>[ 0.577295] ACPI: Interpreter disabled.
10467 13:09:19.671104 <6>[ 0.583832] iommu: Default domain type: Translated
10468 13:09:19.677690 <6>[ 0.588945] iommu: DMA domain TLB invalidation policy: strict mode
10469 13:09:19.681238 <5>[ 0.595602] SCSI subsystem initialized
10470 13:09:19.687557 <6>[ 0.599851] usbcore: registered new interface driver usbfs
10471 13:09:19.694025 <6>[ 0.605579] usbcore: registered new interface driver hub
10472 13:09:19.697564 <6>[ 0.611129] usbcore: registered new device driver usb
10473 13:09:19.704353 <6>[ 0.617293] pps_core: LinuxPPS API ver. 1 registered
10474 13:09:19.714437 <6>[ 0.622487] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10475 13:09:19.717365 <6>[ 0.631829] PTP clock support registered
10476 13:09:19.720633 <6>[ 0.636073] EDAC MC: Ver: 3.0.0
10477 13:09:19.728412 <6>[ 0.641320] FPGA manager framework
10478 13:09:19.734861 <6>[ 0.644998] Advanced Linux Sound Architecture Driver Initialized.
10479 13:09:19.738008 <6>[ 0.651800] vgaarb: loaded
10480 13:09:19.744501 <6>[ 0.654975] clocksource: Switched to clocksource arch_sys_counter
10481 13:09:19.747993 <5>[ 0.661417] VFS: Disk quotas dquot_6.6.0
10482 13:09:19.754642 <6>[ 0.665596] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10483 13:09:19.757776 <6>[ 0.672788] pnp: PnP ACPI: disabled
10484 13:09:19.766418 <6>[ 0.679507] NET: Registered PF_INET protocol family
10485 13:09:19.775972 <6>[ 0.685103] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10486 13:09:19.787980 <6>[ 0.697422] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10487 13:09:19.794402 <6>[ 0.706235] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10488 13:09:19.804283 <6>[ 0.714206] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10489 13:09:19.810839 <6>[ 0.722904] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10490 13:09:19.822795 <6>[ 0.732654] TCP: Hash tables configured (established 65536 bind 65536)
10491 13:09:19.829704 <6>[ 0.739522] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10492 13:09:19.835876 <6>[ 0.746722] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10493 13:09:19.842448 <6>[ 0.754430] NET: Registered PF_UNIX/PF_LOCAL protocol family
10494 13:09:19.848822 <6>[ 0.760577] RPC: Registered named UNIX socket transport module.
10495 13:09:19.852398 <6>[ 0.766733] RPC: Registered udp transport module.
10496 13:09:19.858980 <6>[ 0.771665] RPC: Registered tcp transport module.
10497 13:09:19.865465 <6>[ 0.776600] RPC: Registered tcp NFSv4.1 backchannel transport module.
10498 13:09:19.868834 <6>[ 0.783262] PCI: CLS 0 bytes, default 64
10499 13:09:19.871881 <6>[ 0.787602] Unpacking initramfs...
10500 13:09:19.897084 <6>[ 0.807077] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10501 13:09:19.907109 <6>[ 0.815734] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10502 13:09:19.910282 <6>[ 0.824589] kvm [1]: IPA Size Limit: 40 bits
10503 13:09:19.917057 <6>[ 0.829116] kvm [1]: GICv3: no GICV resource entry
10504 13:09:19.920181 <6>[ 0.834136] kvm [1]: disabling GICv2 emulation
10505 13:09:19.927014 <6>[ 0.838824] kvm [1]: GIC system register CPU interface enabled
10506 13:09:19.930315 <6>[ 0.844996] kvm [1]: vgic interrupt IRQ18
10507 13:09:19.937065 <6>[ 0.849343] kvm [1]: VHE mode initialized successfully
10508 13:09:19.943339 <5>[ 0.855817] Initialise system trusted keyrings
10509 13:09:19.949936 <6>[ 0.860632] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10510 13:09:19.957393 <6>[ 0.870608] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10511 13:09:19.963917 <5>[ 0.876991] NFS: Registering the id_resolver key type
10512 13:09:19.966875 <5>[ 0.882292] Key type id_resolver registered
10513 13:09:19.973545 <5>[ 0.886709] Key type id_legacy registered
10514 13:09:19.980455 <6>[ 0.890993] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10515 13:09:19.987156 <6>[ 0.897914] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10516 13:09:19.993389 <6>[ 0.905629] 9p: Installing v9fs 9p2000 file system support
10517 13:09:20.029366 <5>[ 0.942859] Key type asymmetric registered
10518 13:09:20.032647 <5>[ 0.947215] Asymmetric key parser 'x509' registered
10519 13:09:20.043176 <6>[ 0.952354] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10520 13:09:20.046256 <6>[ 0.959973] io scheduler mq-deadline registered
10521 13:09:20.049295 <6>[ 0.964733] io scheduler kyber registered
10522 13:09:20.069080 <6>[ 0.982235] EINJ: ACPI disabled.
10523 13:09:20.102680 <4>[ 1.009201] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10524 13:09:20.112378 <4>[ 1.019847] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10525 13:09:20.128119 <6>[ 1.041282] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10526 13:09:20.136041 <6>[ 1.049432] printk: console [ttyS0] disabled
10527 13:09:20.164000 <6>[ 1.074063] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10528 13:09:20.170844 <6>[ 1.083538] printk: console [ttyS0] enabled
10529 13:09:20.174008 <6>[ 1.083538] printk: console [ttyS0] enabled
10530 13:09:20.180580 <6>[ 1.092432] printk: bootconsole [mtk8250] disabled
10531 13:09:20.183842 <6>[ 1.092432] printk: bootconsole [mtk8250] disabled
10532 13:09:20.190446 <6>[ 1.103749] SuperH (H)SCI(F) driver initialized
10533 13:09:20.193820 <6>[ 1.109030] msm_serial: driver initialized
10534 13:09:20.208297 <6>[ 1.118148] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10535 13:09:20.218102 <6>[ 1.126694] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10536 13:09:20.224820 <6>[ 1.135236] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10537 13:09:20.234942 <6>[ 1.143864] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10538 13:09:20.241426 <6>[ 1.152570] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10539 13:09:20.251177 <6>[ 1.161285] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10540 13:09:20.261225 <6>[ 1.169841] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10541 13:09:20.267925 <6>[ 1.178658] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10542 13:09:20.277638 <6>[ 1.187200] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10543 13:09:20.289387 <6>[ 1.202895] loop: module loaded
10544 13:09:20.296120 <6>[ 1.208903] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10545 13:09:20.319165 <4>[ 1.232567] mtk-pmic-keys: Failed to locate of_node [id: -1]
10546 13:09:20.326269 <6>[ 1.239552] megasas: 07.719.03.00-rc1
10547 13:09:20.336298 <6>[ 1.249329] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10548 13:09:20.349038 <6>[ 1.262386] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10549 13:09:20.365661 <6>[ 1.279045] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10550 13:09:20.422055 <6>[ 1.328848] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10551 13:09:20.665062 <6>[ 1.578673] Freeing initrd memory: 18280K
10552 13:09:20.676903 <6>[ 1.590265] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10553 13:09:20.687818 <6>[ 1.601202] tun: Universal TUN/TAP device driver, 1.6
10554 13:09:20.691139 <6>[ 1.607302] thunder_xcv, ver 1.0
10555 13:09:20.694935 <6>[ 1.610796] thunder_bgx, ver 1.0
10556 13:09:20.697855 <6>[ 1.614293] nicpf, ver 1.0
10557 13:09:20.708638 <6>[ 1.618338] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10558 13:09:20.711454 <6>[ 1.625814] hns3: Copyright (c) 2017 Huawei Corporation.
10559 13:09:20.718000 <6>[ 1.631400] hclge is initializing
10560 13:09:20.721724 <6>[ 1.634982] e1000: Intel(R) PRO/1000 Network Driver
10561 13:09:20.728516 <6>[ 1.640113] e1000: Copyright (c) 1999-2006 Intel Corporation.
10562 13:09:20.731462 <6>[ 1.646127] e1000e: Intel(R) PRO/1000 Network Driver
10563 13:09:20.738106 <6>[ 1.651344] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10564 13:09:20.744810 <6>[ 1.657532] igb: Intel(R) Gigabit Ethernet Network Driver
10565 13:09:20.751668 <6>[ 1.663182] igb: Copyright (c) 2007-2014 Intel Corporation.
10566 13:09:20.758137 <6>[ 1.669019] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10567 13:09:20.764554 <6>[ 1.675539] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10568 13:09:20.768330 <6>[ 1.682004] sky2: driver version 1.30
10569 13:09:20.774682 <6>[ 1.686992] usbcore: registered new device driver r8152-cfgselector
10570 13:09:20.781576 <6>[ 1.693529] usbcore: registered new interface driver r8152
10571 13:09:20.784631 <6>[ 1.699348] VFIO - User Level meta-driver version: 0.3
10572 13:09:20.794446 <6>[ 1.707637] usbcore: registered new interface driver usb-storage
10573 13:09:20.800993 <6>[ 1.714080] usbcore: registered new device driver onboard-usb-hub
10574 13:09:20.809895 <6>[ 1.723292] mt6397-rtc mt6359-rtc: registered as rtc0
10575 13:09:20.820404 <6>[ 1.728756] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-18T13:09:11 UTC (1721308151)
10576 13:09:20.823474 <6>[ 1.738360] i2c_dev: i2c /dev entries driver
10577 13:09:20.837085 <4>[ 1.750594] cpu cpu0: supply cpu not found, using dummy regulator
10578 13:09:20.844403 <4>[ 1.757024] cpu cpu1: supply cpu not found, using dummy regulator
10579 13:09:20.850811 <4>[ 1.763441] cpu cpu2: supply cpu not found, using dummy regulator
10580 13:09:20.857390 <4>[ 1.769865] cpu cpu3: supply cpu not found, using dummy regulator
10581 13:09:20.864016 <4>[ 1.776263] cpu cpu4: supply cpu not found, using dummy regulator
10582 13:09:20.870772 <4>[ 1.782662] cpu cpu5: supply cpu not found, using dummy regulator
10583 13:09:20.877346 <4>[ 1.789062] cpu cpu6: supply cpu not found, using dummy regulator
10584 13:09:20.883931 <4>[ 1.795461] cpu cpu7: supply cpu not found, using dummy regulator
10585 13:09:20.903002 <6>[ 1.816099] cpu cpu0: EM: created perf domain
10586 13:09:20.905797 <6>[ 1.821035] cpu cpu4: EM: created perf domain
10587 13:09:20.913318 <6>[ 1.826624] sdhci: Secure Digital Host Controller Interface driver
10588 13:09:20.919857 <6>[ 1.833057] sdhci: Copyright(c) Pierre Ossman
10589 13:09:20.926835 <6>[ 1.838023] Synopsys Designware Multimedia Card Interface Driver
10590 13:09:20.933156 <6>[ 1.844677] sdhci-pltfm: SDHCI platform and OF driver helper
10591 13:09:20.936545 <6>[ 1.844768] mmc0: CQHCI version 5.10
10592 13:09:20.942960 <6>[ 1.854671] ledtrig-cpu: registered to indicate activity on CPUs
10593 13:09:20.949827 <6>[ 1.861674] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10594 13:09:20.956347 <6>[ 1.868730] usbcore: registered new interface driver usbhid
10595 13:09:20.959858 <6>[ 1.874553] usbhid: USB HID core driver
10596 13:09:20.966585 <6>[ 1.878743] spi_master spi0: will run message pump with realtime priority
10597 13:09:21.013921 <6>[ 1.920502] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10598 13:09:21.033369 <6>[ 1.936585] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10599 13:09:21.036555 <3>[ 1.943915] mtk-msdc 11f60000.mmc: phase error: [map:0]
10600 13:09:21.043794 <3>[ 1.955489] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10601 13:09:21.050485 <3>[ 1.961422] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10602 13:09:21.053484 <3>[ 1.967792] mmc0: error -5 whilst initialising MMC card
10603 13:09:21.060322 <6>[ 1.968001] cros-ec-spi spi0.0: Chrome EC device registered
10604 13:09:21.082111 <6>[ 1.992422] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10605 13:09:21.090065 <6>[ 2.002864] NET: Registered PF_PACKET protocol family
10606 13:09:21.092915 <6>[ 2.008281] 9pnet: Installing 9P2000 support
10607 13:09:21.099505 <5>[ 2.012850] Key type dns_resolver registered
10608 13:09:21.102815 <6>[ 2.018014] registered taskstats version 1
10609 13:09:21.109734 <5>[ 2.022435] Loading compiled-in X.509 certificates
10610 13:09:21.139923 <4>[ 2.046488] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10611 13:09:21.149447 <4>[ 2.057297] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10612 13:09:21.166080 <6>[ 2.079189] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10613 13:09:21.172559 <6>[ 2.079286] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17c14
10614 13:09:21.179058 <6>[ 2.086069] xhci-mtk 11200000.usb: xHCI Host Controller
10615 13:09:21.186140 <6>[ 2.096893] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10616 13:09:21.189088 <6>[ 2.097006] mmc0: Command Queue Engine enabled
10617 13:09:21.199176 <6>[ 2.104767] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10618 13:09:21.206121 <6>[ 2.109249] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10619 13:09:21.212610 <6>[ 2.118669] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10620 13:09:21.218968 <6>[ 2.125796] mmcblk0: mmc0:0001 DA4128 116 GiB
10621 13:09:21.222529 <6>[ 2.131418] xhci-mtk 11200000.usb: xHCI Host Controller
10622 13:09:21.229025 <6>[ 2.141434] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10623 13:09:21.235925 <6>[ 2.144646] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10624 13:09:21.242542 <6>[ 2.149089] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10625 13:09:21.249191 <6>[ 2.156275] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10626 13:09:21.252495 <6>[ 2.162710] hub 1-0:1.0: USB hub found
10627 13:09:21.259628 <6>[ 2.168155] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10628 13:09:21.262452 <6>[ 2.171555] hub 1-0:1.0: 1 port detected
10629 13:09:21.269082 <6>[ 2.177372] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10630 13:09:21.279381 <6>[ 2.181054] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10631 13:09:21.282680 <6>[ 2.196138] hub 2-0:1.0: USB hub found
10632 13:09:21.285981 <6>[ 2.200157] hub 2-0:1.0: 1 port detected
10633 13:09:21.294364 <6>[ 2.207903] mtk-msdc 11f70000.mmc: Got CD GPIO
10634 13:09:21.313387 <6>[ 2.223370] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10635 13:09:21.323296 <6>[ 2.231752] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10636 13:09:21.329857 <6>[ 2.240092] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10637 13:09:21.340063 <6>[ 2.248435] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10638 13:09:21.346764 <6>[ 2.256773] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10639 13:09:21.356898 <6>[ 2.265112] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10640 13:09:21.363338 <6>[ 2.273451] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10641 13:09:21.373317 <6>[ 2.281792] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10642 13:09:21.380062 <6>[ 2.290133] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10643 13:09:21.389841 <6>[ 2.298471] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10644 13:09:21.396872 <6>[ 2.306810] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10645 13:09:21.406871 <6>[ 2.315152] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10646 13:09:21.413244 <6>[ 2.323490] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10647 13:09:21.423879 <6>[ 2.331829] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10648 13:09:21.430143 <6>[ 2.340166] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10649 13:09:21.436676 <6>[ 2.348862] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10650 13:09:21.443362 <6>[ 2.356037] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10651 13:09:21.449985 <6>[ 2.362814] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10652 13:09:21.456462 <6>[ 2.369590] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10653 13:09:21.467024 <6>[ 2.376539] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10654 13:09:21.473273 <6>[ 2.383389] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10655 13:09:21.483429 <6>[ 2.392524] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10656 13:09:21.493558 <6>[ 2.401645] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10657 13:09:21.503319 <6>[ 2.410941] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10658 13:09:21.513541 <6>[ 2.420409] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10659 13:09:21.520110 <6>[ 2.429877] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10660 13:09:21.530034 <6>[ 2.438997] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10661 13:09:21.540189 <6>[ 2.448463] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10662 13:09:21.549765 <6>[ 2.457583] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10663 13:09:21.559890 <6>[ 2.466878] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10664 13:09:21.569830 <6>[ 2.477037] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10665 13:09:21.579565 <6>[ 2.489065] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10666 13:09:21.587539 <6>[ 2.500227] Trying to probe devices needed for running init ...
10667 13:09:21.597855 <3>[ 2.507571] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10668 13:09:21.693533 <6>[ 2.603226] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10669 13:09:21.846160 <6>[ 2.759133] hub 1-1:1.0: USB hub found
10670 13:09:21.849311 <6>[ 2.763501] hub 1-1:1.0: 4 ports detected
10671 13:09:21.859201 <6>[ 2.772155] hub 1-1:1.0: USB hub found
10672 13:09:21.862318 <6>[ 2.776490] hub 1-1:1.0: 4 ports detected
10673 13:09:21.973587 <6>[ 2.883657] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10674 13:09:21.998762 <6>[ 2.912053] hub 2-1:1.0: USB hub found
10675 13:09:22.001928 <6>[ 2.916451] hub 2-1:1.0: 3 ports detected
10676 13:09:22.014094 <6>[ 2.927549] hub 2-1:1.0: USB hub found
10677 13:09:22.017358 <6>[ 2.932096] hub 2-1:1.0: 3 ports detected
10678 13:09:22.181770 <6>[ 3.091131] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10679 13:09:22.314159 <6>[ 3.227161] hub 1-1.4:1.0: USB hub found
10680 13:09:22.317208 <6>[ 3.231830] hub 1-1.4:1.0: 2 ports detected
10681 13:09:22.332674 <6>[ 3.245469] hub 1-1.4:1.0: USB hub found
10682 13:09:22.335692 <6>[ 3.250063] hub 1-1.4:1.0: 2 ports detected
10683 13:09:22.394030 <6>[ 3.303508] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10684 13:09:22.501600 <6>[ 3.411930] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10685 13:09:22.538240 <4>[ 3.447906] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10686 13:09:22.547847 <4>[ 3.456998] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10687 13:09:22.590986 <6>[ 3.504491] r8152 2-1.3:1.0 eth0: v1.12.13
10688 13:09:22.632902 <6>[ 3.543081] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10689 13:09:22.824731 <6>[ 3.735140] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10690 13:09:24.198362 <6>[ 5.111373] r8152 2-1.3:1.0 eth0: carrier on
10691 13:09:25.272739 <5>[ 5.131095] Sending DHCP requests .
10692 13:09:25.279430 <3>[ 6.186558] DHCP/BOOTP: Reply not for us on eth0, op[2] xid[46487fbb]
10693 13:09:25.285871 <3>[ 6.197222] DHCP/BOOTP: Reply not for us on eth0, op[2] xid[46487fbb]
10694 13:09:26.854272 <4>[ 7.739290] ., OK
10695 13:09:26.864502 <6>[ 7.773490] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10696 13:09:26.868021 <6>[ 7.781784] IP-Config: Complete:
10697 13:09:26.877480 <6>[ 7.785275] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10698 13:09:26.887657 <6>[ 7.795986] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10699 13:09:26.894246 <6>[ 7.804600] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10700 13:09:26.897835 <6>[ 7.804609] nameserver0=192.168.201.1
10701 13:09:26.900938 <6>[ 7.816778] clk: Disabling unused clocks
10702 13:09:26.905634 <6>[ 7.822352] ALSA device list:
10703 13:09:26.912182 <6>[ 7.825636] No soundcards found.
10704 13:09:26.919836 <6>[ 7.833277] Freeing unused kernel memory: 8512K
10705 13:09:26.922822 <6>[ 7.838169] Run /init as init process
10706 13:09:26.932964 Loading, please wait...
10707 13:09:26.959135 Starting systemd-udevd version 252.22-1~deb12u1
10708 13:09:27.243261 <6>[ 8.153694] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10709 13:09:27.253030 <6>[ 8.162780] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10710 13:09:27.279972 <6>[ 8.190372] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10711 13:09:27.286613 <6>[ 8.191964] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10712 13:09:27.296354 <6>[ 8.198434] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10713 13:09:27.302838 <4>[ 8.198541] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10714 13:09:27.313157 <6>[ 8.206072] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10715 13:09:27.316402 <6>[ 8.211500] remoteproc remoteproc0: scp is available
10716 13:09:27.322990 <6>[ 8.211554] remoteproc remoteproc0: powering up scp
10717 13:09:27.332985 <6>[ 8.211559] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10718 13:09:27.336512 <6>[ 8.211572] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10719 13:09:27.346288 <6>[ 8.214658] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10720 13:09:27.352781 <6>[ 8.222880] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10721 13:09:27.362632 <4>[ 8.233924] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10722 13:09:27.369564 <6>[ 8.236927] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10723 13:09:27.373058 <6>[ 8.242058] mc: Linux media interface: v0.10
10724 13:09:27.382765 <3>[ 8.252157] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 13:09:27.389323 <6>[ 8.259899] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10726 13:09:27.395780 <4>[ 8.261135] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10727 13:09:27.405600 <3>[ 8.264282] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 13:09:27.412557 <6>[ 8.273024] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10729 13:09:27.422540 <6>[ 8.279209] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10730 13:09:27.429304 <3>[ 8.280199] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 13:09:27.435368 <3>[ 8.280265] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 13:09:27.442111 <6>[ 8.280885] videodev: Linux video capture interface: v2.00
10733 13:09:27.451970 <6>[ 8.288139] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10734 13:09:27.459072 <3>[ 8.292666] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10735 13:09:27.469167 <6>[ 8.300869] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10736 13:09:27.475147 <3>[ 8.308649] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10737 13:09:27.482024 <3>[ 8.309845] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: DATA CRC ERR
10738 13:09:27.488806 <3>[ 8.309859] mtk-msdc 11f60000.mmc: cmd_err = 0, dat_err =-84, intsts = 0x10008000
10739 13:09:27.494909 <4>[ 8.309950] mmc0: running CQE recovery
10740 13:09:27.501771 <3>[ 8.310160] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10741 13:09:27.508441 <3>[ 8.310163] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10742 13:09:27.511531 <4>[ 8.310179] mmc0: running CQE recovery
10743 13:09:27.518277 <3>[ 8.311384] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10744 13:09:27.524955 <3>[ 8.311389] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10745 13:09:27.531768 <4>[ 8.311405] mmc0: running CQE recovery
10746 13:09:27.538230 <3>[ 8.311610] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10747 13:09:27.544873 <3>[ 8.311613] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10748 13:09:27.547862 <4>[ 8.311629] mmc0: running CQE recovery
10749 13:09:27.555095 <3>[ 8.311822] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10750 13:09:27.561248 <3>[ 8.311826] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10751 13:09:27.568236 <4>[ 8.311845] mmc0: running CQE recovery
10752 13:09:27.574781 <3>[ 8.312030] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10753 13:09:27.580932 <3>[ 8.312034] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10754 13:09:27.584637 <4>[ 8.312075] mmc0: running CQE recovery
10755 13:09:27.591261 <3>[ 8.312272] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10756 13:09:27.601340 <3>[ 8.312276] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10757 13:09:27.604667 <4>[ 8.312291] mmc0: running CQE recovery
10758 13:09:27.611187 <3>[ 8.312487] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10759 13:09:27.617362 <3>[ 8.312490] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10760 13:09:27.620685 <4>[ 8.312505] mmc0: running CQE recovery
10761 13:09:27.627366 <3>[ 8.312690] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10762 13:09:27.637348 <3>[ 8.312695] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10763 13:09:27.640623 <4>[ 8.312719] mmc0: running CQE recovery
10764 13:09:27.647167 <3>[ 8.312911] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10765 13:09:27.654107 <3>[ 8.312915] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10766 13:09:27.657757 <4>[ 8.312936] mmc0: running CQE recovery
10767 13:09:27.663715 <3>[ 8.313127] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10768 13:09:27.673543 <3>[ 8.313131] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10769 13:09:27.676999 <4>[ 8.313146] mmc0: running CQE recovery
10770 13:09:27.686991 <3>[ 8.313310] I/O error, dev mmcblk0, sector 205 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 2
10771 13:09:27.693735 <3>[ 8.313365] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10772 13:09:27.700234 <3>[ 8.313372] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10773 13:09:27.703468 <4>[ 8.313421] mmc0: running CQE recovery
10774 13:09:27.710155 <3>[ 8.313535] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10775 13:09:27.716996 <3>[ 8.313538] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10776 13:09:27.723256 <4>[ 8.313553] mmc0: running CQE recovery
10777 13:09:27.729872 <3>[ 8.313747] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10778 13:09:27.736483 <3>[ 8.313750] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10779 13:09:27.740139 <4>[ 8.313765] mmc0: running CQE recovery
10780 13:09:27.750081 <3>[ 8.313923] I/O error, dev mmcblk0, sector 135288 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 2
10781 13:09:27.756340 <3>[ 8.313960] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10782 13:09:27.763199 <3>[ 8.313963] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10783 13:09:27.766272 <4>[ 8.313987] mmc0: running CQE recovery
10784 13:09:27.776445 <3>[ 8.314149] I/O error, dev mmcblk0, sector 168192 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 2
10785 13:09:27.783231 <3>[ 8.314192] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10786 13:09:27.793064 <3>[ 8.314195] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10787 13:09:27.796378 <4>[ 8.314211] mmc0: running CQE recovery
10788 13:09:27.806342 <3>[ 8.314376] I/O error, dev mmcblk0, sector 333 op 0x0:(READ) flags 0x80700 phys_seg 2 prio class 2
10789 13:09:27.809559 <3>[ 8.314412] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10790 13:09:27.819176 <3>[ 8.314415] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10791 13:09:27.823510 <4>[ 8.314451] mmc0: running CQE recovery
10792 13:09:27.832813 <3>[ 8.314611] I/O error, dev mmcblk0, sector 17076480 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 2
10793 13:09:27.839533 <3>[ 8.314661] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10794 13:09:27.846147 <3>[ 8.314664] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10795 13:09:27.849454 <4>[ 8.314680] mmc0: running CQE recovery
10796 13:09:27.859279 <3>[ 8.314849] I/O error, dev mmcblk0, sector 8688136 op 0x0:(READ) flags 0x80700 phys_seg 25 prio class 2
10797 13:09:27.865680 <3>[ 8.314931] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10798 13:09:27.876078 <3>[ 8.314934] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10799 13:09:27.879331 <4>[ 8.314949] mmc0: running CQE recovery
10800 13:09:27.885837 <3>[ 8.315064] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10801 13:09:27.892266 <3>[ 8.315067] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10802 13:09:27.895476 <4>[ 8.315089] mmc0: running CQE recovery
10803 13:09:27.902204 <3>[ 8.315279] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10804 13:09:27.912599 <3>[ 8.315283] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10805 13:09:27.915494 <4>[ 8.315301] mmc0: running CQE recovery
10806 13:09:27.922021 <3>[ 8.315493] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10807 13:09:27.928629 <3>[ 8.315498] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10808 13:09:27.931809 <4>[ 8.315521] mmc0: running CQE recovery
10809 13:09:27.938647 <3>[ 8.315711] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10810 13:09:27.948512 <3>[ 8.315714] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10811 13:09:27.951762 <4>[ 8.315733] mmc0: running CQE recovery
10812 13:09:27.961656 <3>[ 8.315894] I/O error, dev mmcblk0, sector 8687104 op 0x0:(READ) flags 0x80700 phys_seg 3 prio class 2
10813 13:09:27.968104 <3>[ 8.315938] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10814 13:09:27.974849 <3>[ 8.315941] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10815 13:09:27.981548 <3>[ 8.324023] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10816 13:09:27.988389 <4>[ 8.331877] mmc0: running CQE recovery
10817 13:09:27.995422 <3>[ 8.339478] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10818 13:09:28.001534 <3>[ 8.339527] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10819 13:09:28.011716 <3>[ 8.339595] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10820 13:09:28.018073 <6>[ 8.347750] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10821 13:09:28.024843 <6>[ 8.348362] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10822 13:09:28.031696 <6>[ 8.348370] pci_bus 0000:00: root bus resource [bus 00-ff]
10823 13:09:28.037995 <6>[ 8.348377] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10824 13:09:28.047737 <6>[ 8.348382] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10825 13:09:28.054719 <6>[ 8.348418] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10826 13:09:28.061740 <6>[ 8.348437] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10827 13:09:28.064242 <6>[ 8.348513] pci 0000:00:00.0: supports D1 D2
10828 13:09:28.070905 <6>[ 8.348517] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10829 13:09:28.080871 <6>[ 8.350094] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10830 13:09:28.087487 <6>[ 8.350215] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10831 13:09:28.094337 <6>[ 8.350246] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10832 13:09:28.101000 <6>[ 8.350267] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10833 13:09:28.110614 <6>[ 8.350285] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10834 13:09:28.114120 <6>[ 8.350402] pci 0000:01:00.0: supports D1 D2
10835 13:09:28.120854 <6>[ 8.350405] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10836 13:09:28.130697 <3>[ 8.355747] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10837 13:09:28.137317 <3>[ 8.355750] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10838 13:09:28.144093 <3>[ 8.355776] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10839 13:09:28.153704 <6>[ 8.361527] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10840 13:09:28.160734 <6>[ 8.363089] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10841 13:09:28.170803 <6>[ 8.363120] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10842 13:09:28.176770 <6>[ 8.363126] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10843 13:09:28.184257 <6>[ 8.363138] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10844 13:09:28.193629 <6>[ 8.363155] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10845 13:09:28.200208 <6>[ 8.363171] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10846 13:09:28.207519 <6>[ 8.363187] pci 0000:00:00.0: PCI bridge to [bus 01]
10847 13:09:28.213235 <6>[ 8.363195] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10848 13:09:28.220068 <6>[ 8.363349] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10849 13:09:28.226851 <6>[ 8.364286] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10850 13:09:28.233029 <6>[ 8.364543] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10851 13:09:28.239762 <3>[ 8.369319] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10852 13:09:28.249775 <3>[ 8.369324] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10853 13:09:28.256141 <3>[ 8.369326] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10854 13:09:28.266400 <3>[ 8.377583] I/O error, dev mmcblk0, sector 8687360 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 2
10855 13:09:28.272999 <3>[ 8.386521] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10856 13:09:28.283388 <3>[ 8.386532] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10857 13:09:28.292767 <6>[ 8.437274] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10858 13:09:28.299673 <6>[ 8.445054] remoteproc remoteproc0: remote processor scp is now up
10859 13:09:28.309587 <6>[ 8.463272] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10860 13:09:28.312705 <3>[ 8.469327] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: DATA CRC ERR
10861 13:09:28.322551 <6>[ 8.474085] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10862 13:09:28.329163 <3>[ 8.481307] mtk-msdc 11f60000.mmc: cmd_err = 0, dat_err =-84, intsts = 0x10008000
10863 13:09:28.335844 <4>[ 8.481446] mmc0: running CQE recovery
10864 13:09:28.342542 <5>[ 8.504312] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10865 13:09:28.349335 <3>[ 8.505164] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10866 13:09:28.352575 <6>[ 8.511437] Bluetooth: Core ver 2.22
10867 13:09:28.362301 <3>[ 8.518571] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10868 13:09:28.368875 <6>[ 8.518709] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10869 13:09:28.372261 <4>[ 8.518710] mmc0: running CQE recovery
10870 13:09:28.378611 <6>[ 8.522721] NET: Registered PF_BLUETOOTH protocol family
10871 13:09:28.385352 <5>[ 8.524552] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10872 13:09:28.392532 <5>[ 8.525000] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10873 13:09:28.402097 <4>[ 8.525076] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10874 13:09:28.408876 <6>[ 8.525083] cfg80211: failed to load regulatory.db
10875 13:09:28.415237 <3>[ 8.529188] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10876 13:09:28.422006 <6>[ 8.536767] Bluetooth: HCI device and connection manager initialized
10877 13:09:28.428577 <3>[ 8.540762] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10878 13:09:28.432381 <6>[ 8.547125] Bluetooth: HCI socket layer initialized
10879 13:09:28.438513 <4>[ 8.555165] mmc0: running CQE recovery
10880 13:09:28.441880 <6>[ 8.558925] Bluetooth: L2CAP socket layer initialized
10881 13:09:28.448421 <6>[ 8.558936] Bluetooth: SCO socket layer initialized
10882 13:09:28.455370 <3>[ 8.565592] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10883 13:09:28.461764 <3>[ 8.766977] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: rpmsg send timeout
10884 13:09:28.468053 <3>[ 8.767154] cros-ec-spi spi0.0: SPI transfer timed out
10885 13:09:28.474850 <3>[ 8.767163] spi_master spi0: failed to transfer one message from queue
10886 13:09:28.478533 <3>[ 8.767166] spi_master spi0: noqueue transfer failed
10887 13:09:28.484940 <3>[ 8.767174] cros-ec-spi spi0.0: spi transfer failed: -110
10888 13:09:28.491751 <3>[ 8.769226] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10889 13:09:28.501452 <3>[ 8.978977] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: rpmsg send timeout
10890 13:09:28.508049 <3>[ 8.980019] cros-ec-i2c-tunnel 11010000.spi:ec@0:i2c-tunnel: Error transferring EC i2c message -110
10891 13:09:28.514811 <4>[ 8.980171] mmc0: running CQE recovery
10892 13:09:28.521471 <6>[ 8.980172] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10893 13:09:28.528442 <3>[ 8.980388] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10894 13:09:28.535165 <3>[ 8.980392] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10895 13:09:28.538259 <4>[ 8.980418] mmc0: running CQE recovery
10896 13:09:28.551711 <6>[ 8.981724] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10897 13:09:28.557652 <6>[ 8.981998] usbcore: registered new interface driver uvcvideo
10898 13:09:28.564394 <3>[ 8.983746] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10899 13:09:28.570901 <3>[ 8.983755] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10900 13:09:28.574388 <4>[ 8.983783] mmc0: running CQE recovery
10901 13:09:28.580937 <3>[ 8.984193] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10902 13:09:28.587923 <3>[ 8.984201] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10903 13:09:28.593903 <4>[ 8.984229] mmc0: running CQE recovery
10904 13:09:28.600909 <3>[ 8.984380] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10905 13:09:28.607457 <3>[ 8.984388] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10906 13:09:28.610448 <4>[ 8.984414] mmc0: running CQE recovery
10907 13:09:28.620617 <6>[ 8.984503] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10908 13:09:28.627321 <3>[ 8.984578] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10909 13:09:28.633763 <3>[ 8.984586] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10910 13:09:28.637165 <4>[ 8.984630] mmc0: running CQE recovery
10911 13:09:28.643791 <3>[ 8.984792] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10912 13:09:28.650435 <3>[ 8.984800] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10913 13:09:28.656985 <4>[ 8.984837] mmc0: running CQE recovery
10914 13:09:28.663633 <3>[ 8.985007] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10915 13:09:28.670563 <3>[ 8.985015] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10916 13:09:28.673332 <4>[ 8.985955] mmc0: running CQE recovery
10917 13:09:28.680271 <3>[ 8.986152] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
10918 13:09:28.686620 <3>[ 8.986160] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
10919 13:09:28.693316 <4>[ 8.986197] mmc0: running CQE recovery
10920 13:09:28.700185 <3>[ 8.986295] I/O error, dev mmcblk0, sector 65741 op 0x0:(READ) flags 0x80700 phys_seg 4 prio class 2
10921 13:09:28.706512 <6>[ 8.992716] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10922 13:09:28.716567 <4>[ 9.006050] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10923 13:09:28.723547 <4>[ 9.006050] Fallback method does not support PEC.
10924 13:09:28.726173 <6>[ 9.028977] usbcore: registered new interface driver btusb
10925 13:09:28.736215 <4>[ 9.029603] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10926 13:09:28.743190 <3>[ 9.029609] Bluetooth: hci0: Failed to load firmware file (-2)
10927 13:09:28.750121 <3>[ 9.029611] Bluetooth: hci0: Failed to set up firmware (-2)
10928 13:09:28.759722 <4>[ 9.029613] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10929 13:09:28.766000 <6>[ 9.060370] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10930 13:09:28.772660 <6>[ 9.686670] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10931 13:09:28.796991 <6>[ 9.711008] mt7921e 0000:01:00.0: ASIC revision: 79610010
10932 13:09:28.901396 <6>[ 9.811666] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10933 13:09:28.904028 <6>[ 9.811666]
10934 13:09:29.073458 Begin: Loading essential drivers ... done.
10935 13:09:29.076697 Begin: Running /scripts/init-premount ... done.
10936 13:09:29.083719 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10937 13:09:29.093445 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10938 13:09:29.096748 Device /sys/class/net/eth0 found
10939 13:09:29.097216 done.
10940 13:09:29.103717 Begin: Waiting up to 180 secs for any network device to become available ... done.
10941 13:09:29.168606 <6>[ 10.079291] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10942 13:09:29.175083 IP-Config: eth0 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10943 13:09:29.181843 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10944 13:09:29.188780 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10945 13:09:29.195362 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10946 13:09:29.201572 host : mt8192-asurada-spherion-r0-cbg-1
10947 13:09:29.208567 domain : lava-rack
10948 13:09:29.211494 rootserver: 192.168.201.1 rootpath:
10949 13:09:29.214936 filename :
10950 13:09:29.238077 done.
10951 13:09:29.245277 Begin: Running /scripts/nfs-bottom ... done.
10952 13:09:29.256716 Begin: Running /scripts/init-bottom ... done.
10953 13:09:30.576667 <6>[ 11.491139] NET: Registered PF_INET6 protocol family
10954 13:09:30.584545 <6>[ 11.498780] Segment Routing with IPv6
10955 13:09:30.587447 <6>[ 11.502786] In-situ OAM (IOAM) with IPv6
10956 13:09:30.758208 <30>[ 11.645842] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10957 13:09:30.765051 <30>[ 11.678955] systemd[1]: Detected architecture arm64.
10958 13:09:30.772703
10959 13:09:30.775786 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10960 13:09:30.776193
10961 13:09:30.797965 <30>[ 11.712149] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10962 13:09:31.727192 <30>[ 12.638163] systemd[1]: Queued start job for default target graphical.target.
10963 13:09:31.768974 <30>[ 12.679501] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10964 13:09:31.775499 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10965 13:09:31.793843 <30>[ 12.704764] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10966 13:09:31.803660 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10967 13:09:31.821464 <30>[ 12.732768] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10968 13:09:31.831281 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10969 13:09:31.849231 <30>[ 12.760397] systemd[1]: Created slice user.slice - User and Session Slice.
10970 13:09:31.855673 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10971 13:09:31.875611 <30>[ 12.783471] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10972 13:09:31.882264 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10973 13:09:31.903574 <30>[ 12.811428] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10974 13:09:31.909938 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10975 13:09:31.938508 <30>[ 12.839839] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10976 13:09:31.948501 <30>[ 12.859724] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10977 13:09:31.955037 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10978 13:09:31.971985 <30>[ 12.883227] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10979 13:09:31.978559 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10980 13:09:31.995879 <30>[ 12.907249] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10981 13:09:32.005682 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10982 13:09:32.020705 <30>[ 12.935316] systemd[1]: Reached target paths.target - Path Units.
10983 13:09:32.030343 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10984 13:09:32.047886 <30>[ 12.959234] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10985 13:09:32.054678 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10986 13:09:32.068524 <30>[ 12.983209] systemd[1]: Reached target slices.target - Slice Units.
10987 13:09:32.078936 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10988 13:09:32.093321 <30>[ 13.007682] systemd[1]: Reached target swap.target - Swaps.
10989 13:09:32.099922 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10990 13:09:32.120072 <30>[ 13.031295] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10991 13:09:32.130198 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10992 13:09:32.148403 <30>[ 13.059655] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10993 13:09:32.158118 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10994 13:09:32.178785 <30>[ 13.089711] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10995 13:09:32.189215 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10996 13:09:32.206088 <30>[ 13.116517] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10997 13:09:32.215439 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10998 13:09:32.233244 <30>[ 13.144018] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10999 13:09:32.239788 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
11000 13:09:32.257867 <30>[ 13.168857] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
11001 13:09:32.268205 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
11002 13:09:32.288054 <30>[ 13.199068] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
11003 13:09:32.297952 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
11004 13:09:32.312939 <30>[ 13.223774] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
11005 13:09:32.322680 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
11006 13:09:32.372644 <30>[ 13.283804] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
11007 13:09:32.379209 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
11008 13:09:32.398831 <30>[ 13.309710] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
11009 13:09:32.405176 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
11010 13:09:32.428301 <30>[ 13.339044] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
11011 13:09:32.434839 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
11012 13:09:32.459303 <30>[ 13.363855] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
11013 13:09:32.474537 <30>[ 13.385604] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
11014 13:09:32.484443 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
11015 13:09:32.509754 <30>[ 13.420738] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
11016 13:09:32.516446 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
11017 13:09:32.545347 <30>[ 13.456558] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
11018 13:09:32.551632 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
11019 13:09:32.576213 <30>[ 13.487457] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
11020 13:09:32.589656 Starting [0;1;39mmodprobe@drm.service<6>[ 13.498651] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
11021 13:09:32.592450 [0m - Load Kernel Module drm...
11022 13:09:32.621829 <30>[ 13.532921] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
11023 13:09:32.628526 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
11024 13:09:32.657507 <30>[ 13.568766] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
11025 13:09:32.664049 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
11026 13:09:32.689206 <30>[ 13.600661] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
11027 13:09:32.695747 Startin<6>[ 13.609416] fuse: init (API version 7.37)
11028 13:09:32.702606 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
11029 13:09:32.784383 <30>[ 13.695850] systemd[1]: Starting systemd-journald.service - Journal Service...
11030 13:09:32.791071 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
11031 13:09:32.815866 <30>[ 13.727464] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
11032 13:09:32.822656 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
11033 13:09:32.848211 <30>[ 13.756615] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
11034 13:09:32.855085 Starting [0;1;39msystemd-network-g… units from Kernel command line...
11035 13:09:32.881509 <30>[ 13.792979] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
11036 13:09:32.891383 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
11037 13:09:32.916966 <30>[ 13.828536] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
11038 13:09:32.923627 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
11039 13:09:32.952898 <30>[ 13.863978] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
11040 13:09:32.959165 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
11041 13:09:32.976764 <30>[ 13.888056] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
11042 13:09:32.983207 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
11043 13:09:33.008425 <30>[ 13.919636] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
11044 13:09:33.015226 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
11045 13:09:33.033255 <30>[ 13.944266] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
11046 13:09:33.043720 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
11047 13:09:33.061204 <30>[ 13.972080] systemd[1]: Started systemd-journald.service - Journal Service.
11048 13:09:33.067740 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11049 13:09:33.088771 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
11050 13:09:33.106200 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
11051 13:09:33.125715 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
11052 13:09:33.147178 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11053 13:09:33.167263 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11054 13:09:33.187382 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11055 13:09:33.206523 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11056 13:09:33.226243 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11057 13:09:33.246068 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11058 13:09:33.267622 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11059 13:09:33.325573 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11060 13:09:33.348750 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11061 13:09:33.373225 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11062 13:09:33.395959 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11063 13:09:33.445152 <46>[ 14.356465] systemd-journald[312]: Received client request to flush runtime journal.
11064 13:09:33.457441 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11065 13:09:33.484934 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11066 13:09:33.767309 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11067 13:09:33.784675 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11068 13:09:33.803746 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11069 13:09:33.821153 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11070 13:09:34.221590 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11071 13:09:34.558432 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11072 13:09:34.605042 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11073 13:09:34.859481 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11074 13:09:34.955941 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11075 13:09:34.977093 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11076 13:09:34.996695 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11077 13:09:35.051062 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11078 13:09:35.077810 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11079 13:09:35.303515 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11080 13:09:35.369625 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11081 13:09:35.417992 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11082 13:09:35.525974 <3>[ 16.440621] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
11083 13:09:35.533015 <3>[ 16.447110] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: DATA CRC ERR
11084 13:09:35.543003 <3>[ 16.453224] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =-84, intsts = 0x10008300
11085 13:09:35.546062 [[0;32m OK [<4>[ 16.454456] mmc0: running CQE recovery
11086 13:09:35.556299 0m] Finished [0<3>[ 16.467692] mtk-msdc 11f60000.mmc: msdc_cmdq_irq: CMD TIMEOUT ERR
11087 13:09:35.562799 <3>[ 16.474826] mtk-msdc 11f60000.mmc: cmd_err = -110, dat_err =0, intsts = 0x10000200
11088 13:09:35.569383 ;1;39msystemd-tm<4>[ 16.483963] mmc0: running CQE recovery
11089 13:09:35.572531 pfiles-…te Volatile Files and Directories.
11090 13:09:35.722403 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11091 13:09:35.747418 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11092 13:09:35.847248 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11093 13:09:35.854221 <6>[ 16.767469] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11094 13:09:35.867897 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11095 13:09:35.883691 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11096 13:09:35.940248 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11097 13:09:35.975393 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11098 13:09:36.002394 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11099 13:09:36.025901 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11100 13:09:36.048205 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11101 13:09:36.064060 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11102 13:09:36.079942 <46>[ 16.994882] systemd-journald[312]: Time jumped backwards, rotating.
11103 13:09:36.100876 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11104 13:09:36.130576 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11105 13:09:36.151491 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11106 13:09:36.167809 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11107 13:09:36.183380 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11108 13:09:36.895367 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11109 13:09:37.216833 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11110 13:09:37.235937 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11111 13:09:37.592026 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11112 13:09:37.610030 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11113 13:09:37.627598 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11114 13:09:37.651701 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11115 13:09:37.667361 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11116 13:09:37.683847 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11117 13:09:37.734434 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11118 13:09:37.782018 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11119 13:09:37.860231 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11120 13:09:37.888542 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11121 13:09:38.059877 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11122 13:09:38.113342 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11123 13:09:38.135423 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11124 13:09:38.152326 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11125 13:09:38.168834 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11126 13:09:38.202890 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11127 13:09:38.224793 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11128 13:09:38.245966 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11129 13:09:38.264455 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11130 13:09:38.313576 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11131 13:09:38.363057 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11132 13:09:38.452779
11133 13:09:38.456458 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11134 13:09:38.456539
11135 13:09:38.459797 debian-bookworm-arm64 login: root (automatic login)
11136 13:09:38.459866
11137 13:09:38.704087 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024 aarch64
11138 13:09:38.711384
11139 13:09:38.715061 The programs included with the Debian GNU/Linux system are free software;
11140 13:09:38.721581 the exact distribution terms for each program are described in the
11141 13:09:38.728064 individual files in /usr/share/doc/*/copyright.
11142 13:09:38.728184
11143 13:09:38.731451 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11144 13:09:38.734614 permitted by applicable law.
11145 13:09:38.805701 Matched prompt #10: / #
11147 13:09:38.807045 Setting prompt string to ['/ #']
11148 13:09:38.807781 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11150 13:09:38.808911 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11151 13:09:38.809370 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
11152 13:09:38.809686 Setting prompt string to ['/ #']
11153 13:09:38.810232 Forcing a shell prompt, looking for ['/ #']
11154 13:09:38.810725 Sending line: ''
11156 13:09:38.862023 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11157 13:09:38.862426 Waiting using forced prompt support (timeout 00:02:30)
11158 13:09:38.867843 / #
11159 13:09:38.868724 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11160 13:09:38.869258 start: 2.2.7 export-device-env (timeout 00:03:36) [common]
11161 13:09:38.869659 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14878975/extract-nfsrootfs-uz7mtp0l'"
11163 13:09:38.977643 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14878975/extract-nfsrootfs-uz7mtp0l'
11164 13:09:38.978398 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
11166 13:09:39.085783 / # export NFS_SERVER_IP='192.168.201.1'
11167 13:09:39.086647 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11168 13:09:39.087132 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
11169 13:09:39.087586 end: 2 depthcharge-action (duration 00:01:24) [common]
11170 13:09:39.088046 start: 3 lava-test-retry (timeout 00:01:00) [common]
11171 13:09:39.088488 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11172 13:09:39.088871 Using namespace: common
11173 13:09:39.089278 Sending line: '#'
11175 13:09:39.190844 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11176 13:09:39.197008 / # #
11177 13:09:39.198192 Using /lava-14878975
11178 13:09:39.198804 Sending line: 'export SHELL=/bin/sh'
11180 13:09:39.306210 / # export SHELL=/bin/sh
11181 13:09:39.306471 Sending line: '. /lava-14878975/environment'
11183 13:09:39.413306 / # . /lava-14878975/environment
11184 13:09:39.420182 Sending line: '/lava-14878975/bin/lava-test-runner /lava-14878975/0'
11186 13:09:39.521993 Test shell timeout: 10s (minimum of the action and connection timeout)
11187 13:09:39.527770 / # /lava-14878975/bin/lava-test-runner /lava-14878975/0
11188 13:09:39.769736 + export TESTRUN_ID=0_dmesg
11189 13:09:39.772794 + cd /lava-14878975/0/tests/0_dmesg
11190 13:09:39.776117 + cat uuid
11191 13:09:39.790847 + UUID=14878975_<8>[ 20.702796] <LAVA_SIGNAL_STARTRUN 0_dmesg 14878975_1.6.2.3.1>
11192 13:09:39.791246 1.6.2.3.1
11193 13:09:39.791571 + set +x
11194 13:09:39.792149 Received signal: <STARTRUN> 0_dmesg 14878975_1.6.2.3.1
11195 13:09:39.792476 Starting test lava.0_dmesg (14878975_1.6.2.3.1)
11196 13:09:39.792847 Skipping test definition patterns.
11197 13:09:39.797385 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11198 13:09:39.899172 <8>[ 20.810884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11199 13:09:39.899927 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11201 13:09:39.976831 <8>[ 20.888479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11202 13:09:39.977683 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11204 13:09:40.060116 <8>[ 20.971308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11205 13:09:40.060878 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11207 13:09:40.066121 + <8>[ 20.981166] <LAVA_SIGNAL_ENDRUN 0_dmesg 14878975_1.6.2.3.1>
11208 13:09:40.066202 set +x
11209 13:09:40.066462 Received signal: <ENDRUN> 0_dmesg 14878975_1.6.2.3.1
11210 13:09:40.066539 Ending use of test pattern.
11211 13:09:40.066595 Ending test lava.0_dmesg (14878975_1.6.2.3.1), duration 0.27
11213 13:09:40.074216 <LAVA_TEST_RUNNER EXIT>
11214 13:09:40.074464 ok: lava_test_shell seems to have completed
11215 13:09:40.074567 crit: pass
alert: pass
emerg: pass
11216 13:09:40.074652 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11217 13:09:40.074734 end: 3 lava-test-retry (duration 00:00:01) [common]
11218 13:09:40.074820 start: 4 finalize (timeout 00:08:09) [common]
11219 13:09:40.074906 start: 4.1 power-off (timeout 00:00:30) [common]
11220 13:09:40.075035 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=off']
11221 13:09:42.168005 >> Command sent successfully.
11222 13:09:42.175279 Returned 0 in 2 seconds
11223 13:09:42.175435 end: 4.1 power-off (duration 00:00:02) [common]
11225 13:09:42.175632 start: 4.2 read-feedback (timeout 00:08:06) [common]
11226 13:09:42.175761 Listened to connection for namespace 'common' for up to 1s
11227 13:09:43.176996 Finalising connection for namespace 'common'
11228 13:09:43.177598 Disconnecting from shell: Finalise
11229 13:09:43.177951 / #
11230 13:09:43.278937 end: 4.2 read-feedback (duration 00:00:01) [common]
11231 13:09:43.279544 end: 4 finalize (duration 00:00:03) [common]
11232 13:09:43.280100 Cleaning after the job
11233 13:09:43.280586 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14878975/tftp-deploy-49h2gz7q/ramdisk
11234 13:09:43.291300 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14878975/tftp-deploy-49h2gz7q/kernel
11235 13:09:43.325797 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14878975/tftp-deploy-49h2gz7q/dtb
11236 13:09:43.326098 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14878975/tftp-deploy-49h2gz7q/nfsrootfs
11237 13:09:43.385056 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14878975/tftp-deploy-49h2gz7q/modules
11238 13:09:43.390177 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14878975
11239 13:09:43.705022 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14878975
11240 13:09:43.705343 Job finished correctly