Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 45
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 91
1 13:42:51.398530 lava-dispatcher, installed at version: 2024.05
2 13:42:51.398731 start: 0 validate
3 13:42:51.398842 Start time: 2024-07-18 13:42:51.398837+00:00 (UTC)
4 13:42:51.398976 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:42:51.399117 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 13:42:51.898888 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:42:51.899615 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 13:42:52.162308 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:42:52.163141 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 13:42:52.425175 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:42:52.425872 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:42:52.688130 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:42:52.688753 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 13:42:52.949576 validate duration: 1.55
16 13:42:52.950773 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:42:52.951303 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:42:52.951743 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:42:52.952513 Not decompressing ramdisk as can be used compressed.
20 13:42:52.952970 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 13:42:52.953330 saving as /var/lib/lava/dispatcher/tmp/14879038/tftp-deploy-v36e__j0/ramdisk/initrd.cpio.gz
22 13:42:52.953701 total size: 5628169 (5 MB)
23 13:42:52.958376 progress 0 % (0 MB)
24 13:42:52.967987 progress 5 % (0 MB)
25 13:42:52.975101 progress 10 % (0 MB)
26 13:42:52.979361 progress 15 % (0 MB)
27 13:42:52.983260 progress 20 % (1 MB)
28 13:42:52.986360 progress 25 % (1 MB)
29 13:42:52.989220 progress 30 % (1 MB)
30 13:42:52.992011 progress 35 % (1 MB)
31 13:42:52.994181 progress 40 % (2 MB)
32 13:42:52.996711 progress 45 % (2 MB)
33 13:42:52.998627 progress 50 % (2 MB)
34 13:42:53.000731 progress 55 % (2 MB)
35 13:42:53.002708 progress 60 % (3 MB)
36 13:42:53.004369 progress 65 % (3 MB)
37 13:42:53.006237 progress 70 % (3 MB)
38 13:42:53.007767 progress 75 % (4 MB)
39 13:42:53.009527 progress 80 % (4 MB)
40 13:42:53.011014 progress 85 % (4 MB)
41 13:42:53.012595 progress 90 % (4 MB)
42 13:42:53.014104 progress 95 % (5 MB)
43 13:42:53.015461 progress 100 % (5 MB)
44 13:42:53.015666 5 MB downloaded in 0.06 s (86.60 MB/s)
45 13:42:53.015815 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:42:53.016036 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:42:53.016117 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:42:53.016195 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:42:53.016330 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 13:42:53.016393 saving as /var/lib/lava/dispatcher/tmp/14879038/tftp-deploy-v36e__j0/kernel/Image
52 13:42:53.016447 total size: 54813184 (52 MB)
53 13:42:53.016502 No compression specified
54 13:42:53.017547 progress 0 % (0 MB)
55 13:42:53.030494 progress 5 % (2 MB)
56 13:42:53.043631 progress 10 % (5 MB)
57 13:42:53.056556 progress 15 % (7 MB)
58 13:42:53.069668 progress 20 % (10 MB)
59 13:42:53.082930 progress 25 % (13 MB)
60 13:42:53.096085 progress 30 % (15 MB)
61 13:42:53.109333 progress 35 % (18 MB)
62 13:42:53.122553 progress 40 % (20 MB)
63 13:42:53.135437 progress 45 % (23 MB)
64 13:42:53.148505 progress 50 % (26 MB)
65 13:42:53.161697 progress 55 % (28 MB)
66 13:42:53.174722 progress 60 % (31 MB)
67 13:42:53.187845 progress 65 % (34 MB)
68 13:42:53.200915 progress 70 % (36 MB)
69 13:42:53.214222 progress 75 % (39 MB)
70 13:42:53.227521 progress 80 % (41 MB)
71 13:42:53.240698 progress 85 % (44 MB)
72 13:42:53.253700 progress 90 % (47 MB)
73 13:42:53.266701 progress 95 % (49 MB)
74 13:42:53.279676 progress 100 % (52 MB)
75 13:42:53.279883 52 MB downloaded in 0.26 s (198.43 MB/s)
76 13:42:53.280026 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:42:53.280235 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:42:53.280333 start: 1.3 download-retry (timeout 00:10:00) [common]
80 13:42:53.280437 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 13:42:53.280569 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
82 13:42:53.280634 saving as /var/lib/lava/dispatcher/tmp/14879038/tftp-deploy-v36e__j0/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
83 13:42:53.280686 total size: 57695 (0 MB)
84 13:42:53.280737 No compression specified
85 13:42:53.281880 progress 56 % (0 MB)
86 13:42:53.282135 progress 100 % (0 MB)
87 13:42:53.282321 0 MB downloaded in 0.00 s (33.71 MB/s)
88 13:42:53.282430 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:42:53.282627 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:42:53.282700 start: 1.4 download-retry (timeout 00:10:00) [common]
92 13:42:53.282773 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 13:42:53.282873 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 13:42:53.282930 saving as /var/lib/lava/dispatcher/tmp/14879038/tftp-deploy-v36e__j0/nfsrootfs/full.rootfs.tar
95 13:42:53.282981 total size: 120894716 (115 MB)
96 13:42:53.283033 Using unxz to decompress xz
97 13:42:53.284173 progress 0 % (0 MB)
98 13:42:53.616604 progress 5 % (5 MB)
99 13:42:53.946667 progress 10 % (11 MB)
100 13:42:54.278564 progress 15 % (17 MB)
101 13:42:54.596574 progress 20 % (23 MB)
102 13:42:54.896059 progress 25 % (28 MB)
103 13:42:55.228464 progress 30 % (34 MB)
104 13:42:55.539411 progress 35 % (40 MB)
105 13:42:55.708170 progress 40 % (46 MB)
106 13:42:55.888081 progress 45 % (51 MB)
107 13:42:56.179764 progress 50 % (57 MB)
108 13:42:56.522843 progress 55 % (63 MB)
109 13:42:56.852494 progress 60 % (69 MB)
110 13:42:57.184270 progress 65 % (74 MB)
111 13:42:57.514574 progress 70 % (80 MB)
112 13:42:57.851999 progress 75 % (86 MB)
113 13:42:58.182417 progress 80 % (92 MB)
114 13:42:58.510380 progress 85 % (98 MB)
115 13:42:58.836633 progress 90 % (103 MB)
116 13:42:59.147193 progress 95 % (109 MB)
117 13:42:59.494079 progress 100 % (115 MB)
118 13:42:59.499346 115 MB downloaded in 6.22 s (18.55 MB/s)
119 13:42:59.499503 end: 1.4.1 http-download (duration 00:00:06) [common]
121 13:42:59.499711 end: 1.4 download-retry (duration 00:00:06) [common]
122 13:42:59.499789 start: 1.5 download-retry (timeout 00:09:53) [common]
123 13:42:59.499863 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 13:42:59.500003 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 13:42:59.500066 saving as /var/lib/lava/dispatcher/tmp/14879038/tftp-deploy-v36e__j0/modules/modules.tar
126 13:42:59.500120 total size: 8611320 (8 MB)
127 13:42:59.500175 Using unxz to decompress xz
128 13:42:59.501367 progress 0 % (0 MB)
129 13:42:59.521596 progress 5 % (0 MB)
130 13:42:59.545206 progress 10 % (0 MB)
131 13:42:59.568306 progress 15 % (1 MB)
132 13:42:59.591684 progress 20 % (1 MB)
133 13:42:59.614380 progress 25 % (2 MB)
134 13:42:59.637170 progress 30 % (2 MB)
135 13:42:59.658658 progress 35 % (2 MB)
136 13:42:59.683971 progress 40 % (3 MB)
137 13:42:59.707391 progress 45 % (3 MB)
138 13:42:59.730567 progress 50 % (4 MB)
139 13:42:59.754333 progress 55 % (4 MB)
140 13:42:59.777462 progress 60 % (4 MB)
141 13:42:59.799712 progress 65 % (5 MB)
142 13:42:59.824249 progress 70 % (5 MB)
143 13:42:59.850254 progress 75 % (6 MB)
144 13:42:59.876535 progress 80 % (6 MB)
145 13:42:59.899454 progress 85 % (7 MB)
146 13:42:59.921928 progress 90 % (7 MB)
147 13:42:59.944159 progress 95 % (7 MB)
148 13:42:59.966019 progress 100 % (8 MB)
149 13:42:59.971345 8 MB downloaded in 0.47 s (17.43 MB/s)
150 13:42:59.971490 end: 1.5.1 http-download (duration 00:00:00) [common]
152 13:42:59.971696 end: 1.5 download-retry (duration 00:00:00) [common]
153 13:42:59.971772 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 13:42:59.971846 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 13:43:03.426599 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14879038/extract-nfsrootfs-fj34yvmf
156 13:43:03.426777 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 13:43:03.426866 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 13:43:03.427024 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_
159 13:43:03.427141 makedir: /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin
160 13:43:03.427231 makedir: /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/tests
161 13:43:03.427318 makedir: /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/results
162 13:43:03.427397 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-add-keys
163 13:43:03.427520 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-add-sources
164 13:43:03.427634 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-background-process-start
165 13:43:03.427747 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-background-process-stop
166 13:43:03.427864 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-common-functions
167 13:43:03.427977 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-echo-ipv4
168 13:43:03.428088 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-install-packages
169 13:43:03.428198 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-installed-packages
170 13:43:03.428305 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-os-build
171 13:43:03.428414 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-probe-channel
172 13:43:03.428523 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-probe-ip
173 13:43:03.428631 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-target-ip
174 13:43:03.428739 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-target-mac
175 13:43:03.428846 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-target-storage
176 13:43:03.428960 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-test-case
177 13:43:03.429069 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-test-event
178 13:43:03.429176 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-test-feedback
179 13:43:03.429295 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-test-raise
180 13:43:03.429403 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-test-reference
181 13:43:03.429512 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-test-runner
182 13:43:03.429618 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-test-set
183 13:43:03.429726 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-test-shell
184 13:43:03.429835 Updating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-add-keys (debian)
185 13:43:03.429971 Updating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-add-sources (debian)
186 13:43:03.430092 Updating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-install-packages (debian)
187 13:43:03.430213 Updating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-installed-packages (debian)
188 13:43:03.430332 Updating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/bin/lava-os-build (debian)
189 13:43:03.430438 Creating /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/environment
190 13:43:03.430520 LAVA metadata
191 13:43:03.430582 - LAVA_JOB_ID=14879038
192 13:43:03.430637 - LAVA_DISPATCHER_IP=192.168.201.1
193 13:43:03.430725 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
194 13:43:03.430780 skipped lava-vland-overlay
195 13:43:03.430855 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 13:43:03.430925 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
197 13:43:03.430977 skipped lava-multinode-overlay
198 13:43:03.431038 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 13:43:03.431104 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
200 13:43:03.431167 Loading test definitions
201 13:43:03.431239 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
202 13:43:03.431295 Using /lava-14879038 at stage 0
203 13:43:03.431563 uuid=14879038_1.6.2.3.1 testdef=None
204 13:43:03.431641 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 13:43:03.431713 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
206 13:43:03.432094 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 13:43:03.432286 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
209 13:43:03.432779 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 13:43:03.432981 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
212 13:43:03.433467 runner path: /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/0/tests/0_timesync-off test_uuid 14879038_1.6.2.3.1
213 13:43:03.433605 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 13:43:03.433800 start: 1.6.2.3.5 git-repo-action (timeout 00:09:50) [common]
216 13:43:03.433862 Using /lava-14879038 at stage 0
217 13:43:03.433945 Fetching tests from https://github.com/kernelci/test-definitions.git
218 13:43:03.434018 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/0/tests/1_kselftest-alsa'
219 13:43:05.902293 Running '/usr/bin/git checkout kernelci.org
220 13:43:06.049336 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 13:43:06.049698 uuid=14879038_1.6.2.3.5 testdef=None
222 13:43:06.049798 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 13:43:06.049988 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 13:43:06.050616 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 13:43:06.050812 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 13:43:06.051669 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 13:43:06.051876 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 13:43:06.052711 runner path: /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/0/tests/1_kselftest-alsa test_uuid 14879038_1.6.2.3.5
232 13:43:06.052788 BOARD='mt8183-kukui-jacuzzi-juniper-sku16'
233 13:43:06.052845 BRANCH='cip'
234 13:43:06.052896 SKIPFILE='/dev/null'
235 13:43:06.052945 SKIP_INSTALL='True'
236 13:43:06.052994 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz'
237 13:43:06.053043 TST_CASENAME=''
238 13:43:06.053090 TST_CMDFILES='alsa'
239 13:43:06.053216 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 13:43:06.053404 Creating lava-test-runner.conf files
242 13:43:06.053466 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14879038/lava-overlay-s295krc_/lava-14879038/0 for stage 0
243 13:43:06.053547 - 0_timesync-off
244 13:43:06.053605 - 1_kselftest-alsa
245 13:43:06.053689 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 13:43:06.053764 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 13:43:13.113124 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 13:43:13.113297 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:40) [common]
249 13:43:13.113400 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 13:43:13.113481 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 13:43:13.113558 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:40) [common]
252 13:43:13.256310 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 13:43:13.256457 start: 1.6.4 extract-modules (timeout 00:09:40) [common]
254 13:43:13.256529 extracting modules file /var/lib/lava/dispatcher/tmp/14879038/tftp-deploy-v36e__j0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14879038/extract-nfsrootfs-fj34yvmf
255 13:43:13.471760 extracting modules file /var/lib/lava/dispatcher/tmp/14879038/tftp-deploy-v36e__j0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14879038/extract-overlay-ramdisk-kg28slua/ramdisk
256 13:43:13.693971 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 13:43:13.694107 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 13:43:13.694190 [common] Applying overlay to NFS
259 13:43:13.694247 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14879038/compress-overlay-8xfww0ji/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14879038/extract-nfsrootfs-fj34yvmf
260 13:43:14.512414 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 13:43:14.512548 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 13:43:14.512632 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 13:43:14.512708 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 13:43:14.512775 Building ramdisk /var/lib/lava/dispatcher/tmp/14879038/extract-overlay-ramdisk-kg28slua/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14879038/extract-overlay-ramdisk-kg28slua/ramdisk
265 13:43:14.800118 >> 129966 blocks
266 13:43:16.910144 rename /var/lib/lava/dispatcher/tmp/14879038/extract-overlay-ramdisk-kg28slua/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14879038/tftp-deploy-v36e__j0/ramdisk/ramdisk.cpio.gz
267 13:43:16.910311 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 13:43:16.910397 start: 1.6.8 prepare-kernel (timeout 00:09:36) [common]
269 13:43:16.910474 start: 1.6.8.1 prepare-fit (timeout 00:09:36) [common]
270 13:43:16.910553 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14879038/tftp-deploy-v36e__j0/kernel/Image']
271 13:43:30.422024 Returned 0 in 13 seconds
272 13:43:30.422196 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14879038/tftp-deploy-v36e__j0/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14879038/tftp-deploy-v36e__j0/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14879038/tftp-deploy-v36e__j0/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14879038/tftp-deploy-v36e__j0/kernel/image.itb
273 13:43:30.772160 output: FIT description: Kernel Image image with one or more FDT blobs
274 13:43:30.772291 output: Created: Thu Jul 18 14:43:30 2024
275 13:43:30.772352 output: Image 0 (kernel-1)
276 13:43:30.772407 output: Description:
277 13:43:30.772458 output: Created: Thu Jul 18 14:43:30 2024
278 13:43:30.772509 output: Type: Kernel Image
279 13:43:30.772559 output: Compression: lzma compressed
280 13:43:30.772610 output: Data Size: 13114469 Bytes = 12807.10 KiB = 12.51 MiB
281 13:43:30.772659 output: Architecture: AArch64
282 13:43:30.772707 output: OS: Linux
283 13:43:30.772757 output: Load Address: 0x00000000
284 13:43:30.772805 output: Entry Point: 0x00000000
285 13:43:30.772853 output: Hash algo: crc32
286 13:43:30.772900 output: Hash value: a47b020b
287 13:43:30.772947 output: Image 1 (fdt-1)
288 13:43:30.772995 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
289 13:43:30.773043 output: Created: Thu Jul 18 14:43:30 2024
290 13:43:30.773091 output: Type: Flat Device Tree
291 13:43:30.773170 output: Compression: uncompressed
292 13:43:30.773254 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
293 13:43:30.773307 output: Architecture: AArch64
294 13:43:30.773355 output: Hash algo: crc32
295 13:43:30.773402 output: Hash value: a9713552
296 13:43:30.773449 output: Image 2 (ramdisk-1)
297 13:43:30.773497 output: Description: unavailable
298 13:43:30.773545 output: Created: Thu Jul 18 14:43:30 2024
299 13:43:30.773593 output: Type: RAMDisk Image
300 13:43:30.773641 output: Compression: uncompressed
301 13:43:30.773688 output: Data Size: 18720216 Bytes = 18281.46 KiB = 17.85 MiB
302 13:43:30.773735 output: Architecture: AArch64
303 13:43:30.773782 output: OS: Linux
304 13:43:30.773828 output: Load Address: unavailable
305 13:43:30.773875 output: Entry Point: unavailable
306 13:43:30.773922 output: Hash algo: crc32
307 13:43:30.773968 output: Hash value: 70ae63d4
308 13:43:30.774014 output: Default Configuration: 'conf-1'
309 13:43:30.774060 output: Configuration 0 (conf-1)
310 13:43:30.774106 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
311 13:43:30.774153 output: Kernel: kernel-1
312 13:43:30.774200 output: Init Ramdisk: ramdisk-1
313 13:43:30.774247 output: FDT: fdt-1
314 13:43:30.774293 output: Loadables: kernel-1
315 13:43:30.774339 output:
316 13:43:30.774435 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 13:43:30.774509 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 13:43:30.774593 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 13:43:30.774685 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 13:43:30.774749 No LXC device requested
321 13:43:30.774837 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 13:43:30.774925 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 13:43:30.775005 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 13:43:30.775069 Checking files for TFTP limit of 4294967296 bytes.
325 13:43:30.775571 end: 1 tftp-deploy (duration 00:00:38) [common]
326 13:43:30.775690 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 13:43:30.775805 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 13:43:30.775939 substitutions:
329 13:43:30.776026 - {DTB}: 14879038/tftp-deploy-v36e__j0/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
330 13:43:30.776116 - {INITRD}: 14879038/tftp-deploy-v36e__j0/ramdisk/ramdisk.cpio.gz
331 13:43:30.776205 - {KERNEL}: 14879038/tftp-deploy-v36e__j0/kernel/Image
332 13:43:30.776274 - {LAVA_MAC}: None
333 13:43:30.776341 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14879038/extract-nfsrootfs-fj34yvmf
334 13:43:30.776409 - {NFS_SERVER_IP}: 192.168.201.1
335 13:43:30.776492 - {PRESEED_CONFIG}: None
336 13:43:30.776587 - {PRESEED_LOCAL}: None
337 13:43:30.776670 - {RAMDISK}: 14879038/tftp-deploy-v36e__j0/ramdisk/ramdisk.cpio.gz
338 13:43:30.776754 - {ROOT_PART}: None
339 13:43:30.776837 - {ROOT}: None
340 13:43:30.776920 - {SERVER_IP}: 192.168.201.1
341 13:43:30.777003 - {TEE}: None
342 13:43:30.777091 Parsed boot commands:
343 13:43:30.777187 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 13:43:30.777402 Parsed boot commands: tftpboot 192.168.201.1 14879038/tftp-deploy-v36e__j0/kernel/image.itb 14879038/tftp-deploy-v36e__j0/kernel/cmdline
345 13:43:30.777506 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 13:43:30.777608 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 13:43:30.777708 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 13:43:30.777805 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 13:43:30.777887 Not connected, no need to disconnect.
350 13:43:30.777980 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 13:43:30.778074 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 13:43:30.778153 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-5'
353 13:43:30.781181 Setting prompt string to ['lava-test: # ']
354 13:43:30.781510 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 13:43:30.781634 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 13:43:30.781747 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 13:43:30.781852 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 13:43:30.782146 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-5', '--port=1', '--command=reboot']
359 13:43:39.982424 >> Command sent successfully.
360 13:43:39.996795 Returned 0 in 9 seconds
361 13:43:39.997419 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 13:43:39.998440 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 13:43:39.998856 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 13:43:39.999207 Setting prompt string to 'Starting depthcharge on Juniper...'
366 13:43:39.999484 Changing prompt to 'Starting depthcharge on Juniper...'
367 13:43:39.999779 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
368 13:43:40.001373 [Enter `^Ec?' for help]
369 13:43:46.518684 [DL] 00000000 00000000 010701
370 13:43:46.523721
371 13:43:46.524224
372 13:43:46.524566 F0: 102B 0000
373 13:43:46.524900
374 13:43:46.525209 F3: 1006 0033 [0200]
375 13:43:46.526928
376 13:43:46.527363 F3: 4001 00E0 [0200]
377 13:43:46.527712
378 13:43:46.528031 F3: 0000 0000
379 13:43:46.528338
380 13:43:46.530863 V0: 0000 0000 [0001]
381 13:43:46.531361
382 13:43:46.531695 00: 1027 0002
383 13:43:46.532014
384 13:43:46.533702 01: 0000 0000
385 13:43:46.534141
386 13:43:46.534527 BP: 0C00 0251 [0000]
387 13:43:46.534843
388 13:43:46.536773 G0: 1182 0000
389 13:43:46.537194
390 13:43:46.537561 EC: 0004 0000 [0001]
391 13:43:46.537867
392 13:43:46.540300 S7: 0000 0000 [0000]
393 13:43:46.540940
394 13:43:46.541377 CC: 0000 0000 [0001]
395 13:43:46.543804
396 13:43:46.544283 T0: 0000 00DB [000F]
397 13:43:46.544621
398 13:43:46.544925 Jump to BL
399 13:43:46.545219
400 13:43:46.579838
401 13:43:46.580344
402 13:43:46.586167 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
403 13:43:46.589619 ARM64: Exception handlers installed.
404 13:43:46.593171 ARM64: Testing exception
405 13:43:46.596354 ARM64: Done test exception
406 13:43:46.600330 WDT: Last reset was cold boot
407 13:43:46.603231 SPI0(PAD0) initialized at 992727 Hz
408 13:43:46.606599 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
409 13:43:46.607104 Manufacturer: ef
410 13:43:46.614212 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
411 13:43:46.626350 Probing TPM: . done!
412 13:43:46.626847 TPM ready after 0 ms
413 13:43:46.633667 Connected to device vid:did:rid of 1ae0:0028:00
414 13:43:46.640520 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.5.130/cr50_v2.94_mp.110-683b81dc66
415 13:43:46.673369 Initialized TPM device CR50 revision 0
416 13:43:46.685333 tlcl_send_startup: Startup return code is 0
417 13:43:46.685839 TPM: setup succeeded
418 13:43:46.693670 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
419 13:43:46.696546 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
420 13:43:46.700374 in-header: 03 19 00 00 08 00 00 00
421 13:43:46.703764 in-data: a2 e0 47 00 13 00 00 00
422 13:43:46.706693 Chrome EC: UHEPI supported
423 13:43:46.713024 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
424 13:43:46.716667 in-header: 03 a1 00 00 08 00 00 00
425 13:43:46.720044 in-data: 84 60 60 10 00 00 00 00
426 13:43:46.720552 Phase 1
427 13:43:46.723664 FMAP: area GBB found @ 3f5000 (12032 bytes)
428 13:43:46.730171 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
429 13:43:46.733105 VB2:vb2_check_recovery() Recovery was requested manually
430 13:43:46.740331 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
431 13:43:46.745960 Recovery requested (1009000e)
432 13:43:46.754741 tlcl_extend: response is 0
433 13:43:46.759901 tlcl_extend: response is 0
434 13:43:46.784935
435 13:43:46.785488
436 13:43:46.791405 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
437 13:43:46.795450 ARM64: Exception handlers installed.
438 13:43:46.798461 ARM64: Testing exception
439 13:43:46.801295 ARM64: Done test exception
440 13:43:46.817244 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0xaa70, sec=0x201e
441 13:43:46.824058 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
442 13:43:46.827593 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
443 13:43:46.835391 [RTC]rtc_get_frequency_meter,134: input=0xf, output=778
444 13:43:46.842479 [RTC]rtc_get_frequency_meter,134: input=0x17, output=959
445 13:43:46.849923 [RTC]rtc_get_frequency_meter,134: input=0x13, output=867
446 13:43:46.856542 [RTC]rtc_get_frequency_meter,134: input=0x11, output=823
447 13:43:46.863222 [RTC]rtc_get_frequency_meter,134: input=0x10, output=800
448 13:43:46.870414 [RTC]rtc_get_frequency_meter,134: input=0xf, output=778
449 13:43:46.877338 [RTC]rtc_get_frequency_meter,134: input=0x10, output=799
450 13:43:46.883738 [RTC]rtc_osc_init,208: EOSC32 cali val = 0xaa70
451 13:43:46.888020 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
452 13:43:46.890481 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
453 13:43:46.894120 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
454 13:43:46.900666 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
455 13:43:46.901283 in-header: 03 19 00 00 08 00 00 00
456 13:43:46.904163 in-data: a2 e0 47 00 13 00 00 00
457 13:43:46.907650 Chrome EC: UHEPI supported
458 13:43:46.914219 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
459 13:43:46.917398 in-header: 03 a1 00 00 08 00 00 00
460 13:43:46.920961 in-data: 84 60 60 10 00 00 00 00
461 13:43:46.924727 Skip loading cached calibration data
462 13:43:46.931396 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
463 13:43:46.934450 in-header: 03 a1 00 00 08 00 00 00
464 13:43:46.937715 in-data: 84 60 60 10 00 00 00 00
465 13:43:46.944278 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
466 13:43:46.947756 in-header: 03 a1 00 00 08 00 00 00
467 13:43:46.951092 in-data: 84 60 60 10 00 00 00 00
468 13:43:46.954371 ADC[3]: Raw value=1044222 ID=8
469 13:43:46.954873 Manufacturer: ef
470 13:43:46.961375 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
471 13:43:46.964492 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
472 13:43:46.967987 CBFS @ 21000 size 3d4000
473 13:43:46.971470 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
474 13:43:46.978341 CBFS: Locating 'sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB'
475 13:43:46.981323 CBFS: Found @ offset 3c880 size 4b
476 13:43:46.981756 DRAM-K: Full Calibration
477 13:43:46.988055 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
478 13:43:46.988564 CBFS @ 21000 size 3d4000
479 13:43:46.994870 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
480 13:43:46.998093 CBFS: Locating 'fallback/dram'
481 13:43:47.001072 CBFS: Found @ offset 24b00 size 12268
482 13:43:47.028708 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps
483 13:43:47.032376 ddr_geometry: 1, config: 0x0
484 13:43:47.035716 header.status = 0x0
485 13:43:47.039292 header.magic = 0x44524d4b (expected: 0x44524d4b)
486 13:43:47.042566 header.version = 0x5 (expected: 0x5)
487 13:43:47.045781 header.size = 0x8f0 (expected: 0x8f0)
488 13:43:47.046226 header.config = 0x0
489 13:43:47.048952 header.flags = 0x0
490 13:43:47.049420 header.checksum = 0x0
491 13:43:47.055647 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
492 13:43:47.062908 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
493 13:43:47.066211 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
494 13:43:47.069188 ddr_geometry:1
495 13:43:47.069935 [EMI] new MDL number = 1
496 13:43:47.072613 dram_cbt_mode_extern: 0
497 13:43:47.076013 dram_cbt_mode [RK0]: 0, [RK1]: 0
498 13:43:47.082613 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
499 13:43:47.083046
500 13:43:47.083382
501 13:43:47.083688 [Bianco] ETT version 0.0.0.1
502 13:43:47.089621 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
503 13:43:47.090054
504 13:43:47.092754 vSetVcoreByFreq with vcore:762500, freq=1600
505 13:43:47.093179
506 13:43:47.093572 [DramcInit]
507 13:43:47.095963 AutoRefreshCKEOff AutoREF OFF
508 13:43:47.099451 DDRPhyPLLSetting-CKEOFF
509 13:43:47.099954 DDRPhyPLLSetting-CKEON
510 13:43:47.102841
511 13:43:47.103344 Enable WDQS
512 13:43:47.105970 [ModeRegInit_LP4] CH0 RK0
513 13:43:47.109445 Write Rank0 MR13 =0x18
514 13:43:47.109872 Write Rank0 MR12 =0x5d
515 13:43:47.112969 Write Rank0 MR1 =0x56
516 13:43:47.115975 Write Rank0 MR2 =0x1a
517 13:43:47.116402 Write Rank0 MR11 =0x0
518 13:43:47.119360 Write Rank0 MR22 =0x38
519 13:43:47.119791 Write Rank0 MR14 =0x5d
520 13:43:47.123400 Write Rank0 MR3 =0x30
521 13:43:47.126121 Write Rank0 MR13 =0x58
522 13:43:47.126553 Write Rank0 MR12 =0x5d
523 13:43:47.129404 Write Rank0 MR1 =0x56
524 13:43:47.129834 Write Rank0 MR2 =0x2d
525 13:43:47.133147 Write Rank0 MR11 =0x23
526 13:43:47.136225 Write Rank0 MR22 =0x34
527 13:43:47.136724 Write Rank0 MR14 =0x10
528 13:43:47.139928 Write Rank0 MR3 =0x30
529 13:43:47.140429 Write Rank0 MR13 =0xd8
530 13:43:47.142912 [ModeRegInit_LP4] CH0 RK1
531 13:43:47.146624 Write Rank1 MR13 =0x18
532 13:43:47.147126 Write Rank1 MR12 =0x5d
533 13:43:47.149975 Write Rank1 MR1 =0x56
534 13:43:47.152917 Write Rank1 MR2 =0x1a
535 13:43:47.153384 Write Rank1 MR11 =0x0
536 13:43:47.156792 Write Rank1 MR22 =0x38
537 13:43:47.157338 Write Rank1 MR14 =0x5d
538 13:43:47.160191 Write Rank1 MR3 =0x30
539 13:43:47.163554 Write Rank1 MR13 =0x58
540 13:43:47.164058 Write Rank1 MR12 =0x5d
541 13:43:47.166149 Write Rank1 MR1 =0x56
542 13:43:47.166575 Write Rank1 MR2 =0x2d
543 13:43:47.170189 Write Rank1 MR11 =0x23
544 13:43:47.173440 Write Rank1 MR22 =0x34
545 13:43:47.173940 Write Rank1 MR14 =0x10
546 13:43:47.176557 Write Rank1 MR3 =0x30
547 13:43:47.177075 Write Rank1 MR13 =0xd8
548 13:43:47.179735 [ModeRegInit_LP4] CH1 RK0
549 13:43:47.183240 Write Rank0 MR13 =0x18
550 13:43:47.183669 Write Rank0 MR12 =0x5d
551 13:43:47.186616 Write Rank0 MR1 =0x56
552 13:43:47.190058 Write Rank0 MR2 =0x1a
553 13:43:47.190487 Write Rank0 MR11 =0x0
554 13:43:47.193502 Write Rank0 MR22 =0x38
555 13:43:47.194005 Write Rank0 MR14 =0x5d
556 13:43:47.196826 Write Rank0 MR3 =0x30
557 13:43:47.200189 Write Rank0 MR13 =0x58
558 13:43:47.200711 Write Rank0 MR12 =0x5d
559 13:43:47.203893 Write Rank0 MR1 =0x56
560 13:43:47.204346 Write Rank0 MR2 =0x2d
561 13:43:47.206559 Write Rank0 MR11 =0x23
562 13:43:47.209944 Write Rank0 MR22 =0x34
563 13:43:47.210371 Write Rank0 MR14 =0x10
564 13:43:47.213221 Write Rank0 MR3 =0x30
565 13:43:47.213691 Write Rank0 MR13 =0xd8
566 13:43:47.216688 [ModeRegInit_LP4] CH1 RK1
567 13:43:47.220022 Write Rank1 MR13 =0x18
568 13:43:47.220519 Write Rank1 MR12 =0x5d
569 13:43:47.223904 Write Rank1 MR1 =0x56
570 13:43:47.226994 Write Rank1 MR2 =0x1a
571 13:43:47.227475 Write Rank1 MR11 =0x0
572 13:43:47.230202 Write Rank1 MR22 =0x38
573 13:43:47.230639 Write Rank1 MR14 =0x5d
574 13:43:47.233667 Write Rank1 MR3 =0x30
575 13:43:47.236981 Write Rank1 MR13 =0x58
576 13:43:47.237597 Write Rank1 MR12 =0x5d
577 13:43:47.240211 Write Rank1 MR1 =0x56
578 13:43:47.240636 Write Rank1 MR2 =0x2d
579 13:43:47.243679 Write Rank1 MR11 =0x23
580 13:43:47.247144 Write Rank1 MR22 =0x34
581 13:43:47.247643 Write Rank1 MR14 =0x10
582 13:43:47.250281 Write Rank1 MR3 =0x30
583 13:43:47.250785 Write Rank1 MR13 =0xd8
584 13:43:47.253643 match AC timing 3
585 13:43:47.263626 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
586 13:43:47.264015 [MiockJmeterHQA]
587 13:43:47.266939 vSetVcoreByFreq with vcore:762500, freq=1600
588 13:43:47.372218
589 13:43:47.372879 MIOCK jitter meter ch=0
590 13:43:47.373453
591 13:43:47.375310 1T = (100-18) = 82 dly cells
592 13:43:47.382176 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 762/100 ps
593 13:43:47.385087 vSetVcoreByFreq with vcore:725000, freq=1200
594 13:43:47.483537
595 13:43:47.484046 MIOCK jitter meter ch=0
596 13:43:47.484380
597 13:43:47.486802 1T = (95-17) = 78 dly cells
598 13:43:47.493759 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 801/100 ps
599 13:43:47.496865 vSetVcoreByFreq with vcore:725000, freq=800
600 13:43:47.594851
601 13:43:47.595353 MIOCK jitter meter ch=0
602 13:43:47.595689
603 13:43:47.598039 1T = (95-17) = 78 dly cells
604 13:43:47.604924 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 801/100 ps
605 13:43:47.608771 vSetVcoreByFreq with vcore:762500, freq=1600
606 13:43:47.611513 vSetVcoreByFreq with vcore:762500, freq=1600
607 13:43:47.611955
608 13:43:47.612327 K DRVP
609 13:43:47.615246 1. OCD DRVP=0 CALOUT=0
610 13:43:47.618195 1. OCD DRVP=1 CALOUT=0
611 13:43:47.618628 1. OCD DRVP=2 CALOUT=0
612 13:43:47.621692 1. OCD DRVP=3 CALOUT=0
613 13:43:47.622231 1. OCD DRVP=4 CALOUT=0
614 13:43:47.624976 1. OCD DRVP=5 CALOUT=0
615 13:43:47.628124 1. OCD DRVP=6 CALOUT=0
616 13:43:47.628556 1. OCD DRVP=7 CALOUT=0
617 13:43:47.631851 1. OCD DRVP=8 CALOUT=1
618 13:43:47.632382
619 13:43:47.634987 1. OCD DRVP calibration OK! DRVP=8
620 13:43:47.635500
621 13:43:47.635829
622 13:43:47.636131
623 13:43:47.636419 K ODTN
624 13:43:47.638080 3. OCD ODTN=0 ,CALOUT=1
625 13:43:47.641683 3. OCD ODTN=1 ,CALOUT=1
626 13:43:47.642118 3. OCD ODTN=2 ,CALOUT=1
627 13:43:47.645498 3. OCD ODTN=3 ,CALOUT=1
628 13:43:47.646008 3. OCD ODTN=4 ,CALOUT=1
629 13:43:47.648900 3. OCD ODTN=5 ,CALOUT=1
630 13:43:47.652080 3. OCD ODTN=6 ,CALOUT=1
631 13:43:47.652516 3. OCD ODTN=7 ,CALOUT=0
632 13:43:47.652853
633 13:43:47.655477 3. OCD ODTN calibration OK! ODTN=7
634 13:43:47.655913
635 13:43:47.658754 [SwImpedanceCal] DRVP=8, DRVN=9, ODTN=7
636 13:43:47.665821 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15
637 13:43:47.668886 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15 (After Adjust)
638 13:43:47.669432
639 13:43:47.669766 K DRVP
640 13:43:47.672075 1. OCD DRVP=0 CALOUT=0
641 13:43:47.675837 1. OCD DRVP=1 CALOUT=0
642 13:43:47.676351 1. OCD DRVP=2 CALOUT=0
643 13:43:47.679493 1. OCD DRVP=3 CALOUT=0
644 13:43:47.680121 1. OCD DRVP=4 CALOUT=0
645 13:43:47.682110 1. OCD DRVP=5 CALOUT=0
646 13:43:47.686020 1. OCD DRVP=6 CALOUT=0
647 13:43:47.686531 1. OCD DRVP=7 CALOUT=0
648 13:43:47.688892 1. OCD DRVP=8 CALOUT=0
649 13:43:47.692849 1. OCD DRVP=9 CALOUT=1
650 13:43:47.693400
651 13:43:47.693734 1. OCD DRVP calibration OK! DRVP=9
652 13:43:47.695571
653 13:43:47.695989
654 13:43:47.696311
655 13:43:47.696608 K ODTN
656 13:43:47.699328 3. OCD ODTN=0 ,CALOUT=1
657 13:43:47.699836 3. OCD ODTN=1 ,CALOUT=1
658 13:43:47.702705 3. OCD ODTN=2 ,CALOUT=1
659 13:43:47.703228 3. OCD ODTN=3 ,CALOUT=1
660 13:43:47.705540 3. OCD ODTN=4 ,CALOUT=1
661 13:43:47.709362 3. OCD ODTN=5 ,CALOUT=1
662 13:43:47.709871 3. OCD ODTN=6 ,CALOUT=1
663 13:43:47.712367 3. OCD ODTN=7 ,CALOUT=1
664 13:43:47.716186 3. OCD ODTN=8 ,CALOUT=1
665 13:43:47.716692 3. OCD ODTN=9 ,CALOUT=1
666 13:43:47.719461 3. OCD ODTN=10 ,CALOUT=1
667 13:43:47.722853 3. OCD ODTN=11 ,CALOUT=1
668 13:43:47.723361 3. OCD ODTN=12 ,CALOUT=1
669 13:43:47.725954 3. OCD ODTN=13 ,CALOUT=0
670 13:43:47.726464
671 13:43:47.729384 3. OCD ODTN calibration OK! ODTN=13
672 13:43:47.730117
673 13:43:47.733261 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=13
674 13:43:47.736109 term_option=1, Reg: DRVP=9, DRVN=9, ODTN=13
675 13:43:47.742949 term_option=1, Reg: DRVP=9, DRVN=9, ODTN=13 (After Adjust)
676 13:43:47.743397
677 13:43:47.743724 [DramcInit]
678 13:43:47.746099 AutoRefreshCKEOff AutoREF OFF
679 13:43:47.749484 DDRPhyPLLSetting-CKEOFF
680 13:43:47.749905 DDRPhyPLLSetting-CKEON
681 13:43:47.750227
682 13:43:47.752903 Enable WDQS
683 13:43:47.753359 ==
684 13:43:47.756311 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
685 13:43:47.759905 fsp= 1, odt_onoff= 1, Byte mode= 0
686 13:43:47.760376 ==
687 13:43:47.762859 [Duty_Offset_Calibration]
688 13:43:47.763286
689 13:43:47.766029 ===========================
690 13:43:47.766457 B0:1 B1:0 CA:0
691 13:43:47.787640 ==
692 13:43:47.790803 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
693 13:43:47.794104 fsp= 1, odt_onoff= 1, Byte mode= 0
694 13:43:47.794613 ==
695 13:43:47.797966 [Duty_Offset_Calibration]
696 13:43:47.798474
697 13:43:47.800818 ===========================
698 13:43:47.801265 B0:1 B1:0 CA:-1
699 13:43:47.834143 [ModeRegInit_LP4] CH0 RK0
700 13:43:47.837157 Write Rank0 MR13 =0x18
701 13:43:47.837633 Write Rank0 MR12 =0x5d
702 13:43:47.840797 Write Rank0 MR1 =0x56
703 13:43:47.844181 Write Rank0 MR2 =0x1a
704 13:43:47.844610 Write Rank0 MR11 =0x0
705 13:43:47.847638 Write Rank0 MR22 =0x38
706 13:43:47.848148 Write Rank0 MR14 =0x5d
707 13:43:47.850841 Write Rank0 MR3 =0x30
708 13:43:47.854869 Write Rank0 MR13 =0x58
709 13:43:47.855317 Write Rank0 MR12 =0x5d
710 13:43:47.857401 Write Rank0 MR1 =0x56
711 13:43:47.857830 Write Rank0 MR2 =0x2d
712 13:43:47.860625 Write Rank0 MR11 =0x23
713 13:43:47.864286 Write Rank0 MR22 =0x34
714 13:43:47.864787 Write Rank0 MR14 =0x10
715 13:43:47.867325 Write Rank0 MR3 =0x30
716 13:43:47.870995 Write Rank0 MR13 =0xd8
717 13:43:47.871504 [ModeRegInit_LP4] CH0 RK1
718 13:43:47.874224 Write Rank1 MR13 =0x18
719 13:43:47.874759 Write Rank1 MR12 =0x5d
720 13:43:47.877738 Write Rank1 MR1 =0x56
721 13:43:47.880733 Write Rank1 MR2 =0x1a
722 13:43:47.881156 Write Rank1 MR11 =0x0
723 13:43:47.884369 Write Rank1 MR22 =0x38
724 13:43:47.884794 Write Rank1 MR14 =0x5d
725 13:43:47.887501 Write Rank1 MR3 =0x30
726 13:43:47.891033 Write Rank1 MR13 =0x58
727 13:43:47.891456 Write Rank1 MR12 =0x5d
728 13:43:47.894728 Write Rank1 MR1 =0x56
729 13:43:47.895230 Write Rank1 MR2 =0x2d
730 13:43:47.897963 Write Rank1 MR11 =0x23
731 13:43:47.901615 Write Rank1 MR22 =0x34
732 13:43:47.902118 Write Rank1 MR14 =0x10
733 13:43:47.904811 Write Rank1 MR3 =0x30
734 13:43:47.905352 Write Rank1 MR13 =0xd8
735 13:43:47.907985 [ModeRegInit_LP4] CH1 RK0
736 13:43:47.911353 Write Rank0 MR13 =0x18
737 13:43:47.911856 Write Rank0 MR12 =0x5d
738 13:43:47.914588 Write Rank0 MR1 =0x56
739 13:43:47.918382 Write Rank0 MR2 =0x1a
740 13:43:47.918952 Write Rank0 MR11 =0x0
741 13:43:47.921372 Write Rank0 MR22 =0x38
742 13:43:47.921872 Write Rank0 MR14 =0x5d
743 13:43:47.925126 Write Rank0 MR3 =0x30
744 13:43:47.928230 Write Rank0 MR13 =0x58
745 13:43:47.928745 Write Rank0 MR12 =0x5d
746 13:43:47.931150 Write Rank0 MR1 =0x56
747 13:43:47.931578 Write Rank0 MR2 =0x2d
748 13:43:47.934476 Write Rank0 MR11 =0x23
749 13:43:47.938218 Write Rank0 MR22 =0x34
750 13:43:47.938736 Write Rank0 MR14 =0x10
751 13:43:47.941513 Write Rank0 MR3 =0x30
752 13:43:47.941941 Write Rank0 MR13 =0xd8
753 13:43:47.944971 [ModeRegInit_LP4] CH1 RK1
754 13:43:47.948420 Write Rank1 MR13 =0x18
755 13:43:47.949018 Write Rank1 MR12 =0x5d
756 13:43:47.951587 Write Rank1 MR1 =0x56
757 13:43:47.954722 Write Rank1 MR2 =0x1a
758 13:43:47.955153 Write Rank1 MR11 =0x0
759 13:43:47.958234 Write Rank1 MR22 =0x38
760 13:43:47.958658 Write Rank1 MR14 =0x5d
761 13:43:47.961756 Write Rank1 MR3 =0x30
762 13:43:47.965030 Write Rank1 MR13 =0x58
763 13:43:47.965585 Write Rank1 MR12 =0x5d
764 13:43:47.968229 Write Rank1 MR1 =0x56
765 13:43:47.968739 Write Rank1 MR2 =0x2d
766 13:43:47.971545 Write Rank1 MR11 =0x23
767 13:43:47.975452 Write Rank1 MR22 =0x34
768 13:43:47.975989 Write Rank1 MR14 =0x10
769 13:43:47.978530 Write Rank1 MR3 =0x30
770 13:43:47.979035 Write Rank1 MR13 =0xd8
771 13:43:47.981572 match AC timing 3
772 13:43:47.991586 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
773 13:43:47.992083 DramC Write-DBI off
774 13:43:47.995196 DramC Read-DBI off
775 13:43:47.995694 Write Rank0 MR13 =0x59
776 13:43:47.998471 ==
777 13:43:48.001889 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
778 13:43:48.005300 fsp= 1, odt_onoff= 1, Byte mode= 0
779 13:43:48.005824 ==
780 13:43:48.008658 === u2Vref_new: 0x56 --> 0x2d
781 13:43:48.012184 === u2Vref_new: 0x58 --> 0x38
782 13:43:48.015350 === u2Vref_new: 0x5a --> 0x39
783 13:43:48.018521 === u2Vref_new: 0x5c --> 0x3c
784 13:43:48.021841 === u2Vref_new: 0x5e --> 0x3d
785 13:43:48.022360 === u2Vref_new: 0x60 --> 0xa0
786 13:43:48.025693 [CA 0] Center 33 (4~63) winsize 60
787 13:43:48.028857 [CA 1] Center 34 (5~63) winsize 59
788 13:43:48.032211 [CA 2] Center 27 (0~55) winsize 56
789 13:43:48.036150 [CA 3] Center 23 (-4~51) winsize 56
790 13:43:48.038840 [CA 4] Center 24 (-3~52) winsize 56
791 13:43:48.042122 [CA 5] Center 28 (-1~58) winsize 60
792 13:43:48.042554
793 13:43:48.046003 [CATrainingPosCal] consider 1 rank data
794 13:43:48.049093 u2DelayCellTimex100 = 762/100 ps
795 13:43:48.052454 CA0 delay=33 (4~63),Diff = 10 PI (12 cell)
796 13:43:48.055456 CA1 delay=34 (5~63),Diff = 11 PI (14 cell)
797 13:43:48.058994 CA2 delay=27 (0~55),Diff = 4 PI (5 cell)
798 13:43:48.065903 CA3 delay=23 (-4~51),Diff = 0 PI (0 cell)
799 13:43:48.069154 CA4 delay=24 (-3~52),Diff = 1 PI (1 cell)
800 13:43:48.072570 CA5 delay=28 (-1~58),Diff = 5 PI (6 cell)
801 13:43:48.073076
802 13:43:48.075956 CA PerBit enable=1, Macro0, CA PI delay=23
803 13:43:48.079396 === u2Vref_new: 0x58 --> 0x38
804 13:43:48.079903
805 13:43:48.080236 Vref(ca) range 1: 24
806 13:43:48.080543
807 13:43:48.082684 CS Dly= 10 (41-0-32)
808 13:43:48.085914 Write Rank0 MR13 =0xd8
809 13:43:48.086473 Write Rank0 MR13 =0xd8
810 13:43:48.089443 Write Rank0 MR12 =0x58
811 13:43:48.092594 Write Rank1 MR13 =0x59
812 13:43:48.093105 ==
813 13:43:48.096154 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
814 13:43:48.099461 fsp= 1, odt_onoff= 1, Byte mode= 0
815 13:43:48.100063 ==
816 13:43:48.102854 === u2Vref_new: 0x56 --> 0x2d
817 13:43:48.105752 === u2Vref_new: 0x58 --> 0x38
818 13:43:48.109306 === u2Vref_new: 0x5a --> 0x39
819 13:43:48.112627 === u2Vref_new: 0x5c --> 0x3c
820 13:43:48.115920 === u2Vref_new: 0x5e --> 0x3d
821 13:43:48.119221 === u2Vref_new: 0x60 --> 0xa0
822 13:43:48.122732 [CA 0] Center 33 (4~63) winsize 60
823 13:43:48.125706 [CA 1] Center 34 (5~63) winsize 59
824 13:43:48.126217 [CA 2] Center 28 (0~56) winsize 57
825 13:43:48.129538 [CA 3] Center 23 (-4~51) winsize 56
826 13:43:48.132649 [CA 4] Center 24 (-3~52) winsize 56
827 13:43:48.136242 [CA 5] Center 29 (1~58) winsize 58
828 13:43:48.136758
829 13:43:48.139210 [CATrainingPosCal] consider 2 rank data
830 13:43:48.142985 u2DelayCellTimex100 = 762/100 ps
831 13:43:48.146448 CA0 delay=33 (4~63),Diff = 10 PI (12 cell)
832 13:43:48.149645 CA1 delay=34 (5~63),Diff = 11 PI (14 cell)
833 13:43:48.156291 CA2 delay=27 (0~55),Diff = 4 PI (5 cell)
834 13:43:48.159804 CA3 delay=23 (-4~51),Diff = 0 PI (0 cell)
835 13:43:48.163167 CA4 delay=24 (-3~52),Diff = 1 PI (1 cell)
836 13:43:48.166686 CA5 delay=29 (1~58),Diff = 6 PI (7 cell)
837 13:43:48.167193
838 13:43:48.169935 CA PerBit enable=1, Macro0, CA PI delay=23
839 13:43:48.173175 === u2Vref_new: 0x56 --> 0x2d
840 13:43:48.173718
841 13:43:48.174056 Vref(ca) range 1: 22
842 13:43:48.174369
843 13:43:48.176555 CS Dly= 7 (38-0-32)
844 13:43:48.180169 Write Rank1 MR13 =0xd8
845 13:43:48.180679 Write Rank1 MR13 =0xd8
846 13:43:48.183098 Write Rank1 MR12 =0x56
847 13:43:48.186400 [RankSwap] Rank num 2, (Multi 1), Rank 0
848 13:43:48.189987 Write Rank0 MR2 =0xad
849 13:43:48.190498 [Write Leveling]
850 13:43:48.193378 delay byte0 byte1 byte2 byte3
851 13:43:48.193883
852 13:43:48.194221 10 0 0
853 13:43:48.196582 11 0 0
854 13:43:48.197099 12 0 0
855 13:43:48.199950 13 0 0
856 13:43:48.200523 14 0 0
857 13:43:48.200871 15 0 0
858 13:43:48.203331 16 0 0
859 13:43:48.203849 17 0 0
860 13:43:48.206498 18 0 0
861 13:43:48.207017 19 0 0
862 13:43:48.207359 20 0 0
863 13:43:48.210020 21 0 0
864 13:43:48.210537 22 0 0
865 13:43:48.213117 23 0 0
866 13:43:48.213805 24 0 0
867 13:43:48.216737 25 0 0
868 13:43:48.217300 26 0 0
869 13:43:48.217761 27 0 0
870 13:43:48.220032 28 0 ff
871 13:43:48.220549 29 0 ff
872 13:43:48.223340 30 0 ff
873 13:43:48.223858 31 0 ff
874 13:43:48.226764 32 0 ff
875 13:43:48.227277 33 ff ff
876 13:43:48.227614 34 ff ff
877 13:43:48.230142 35 ff ff
878 13:43:48.230660 36 ff ff
879 13:43:48.233465 37 ff ff
880 13:43:48.233978 38 ff ff
881 13:43:48.236647 39 ff ff
882 13:43:48.240130 pass bytecount = 0xff (0xff: all bytes pass)
883 13:43:48.240631
884 13:43:48.240964 DQS0 dly: 33
885 13:43:48.243222 DQS1 dly: 28
886 13:43:48.243647 Write Rank0 MR2 =0x2d
887 13:43:48.246819 [RankSwap] Rank num 2, (Multi 1), Rank 0
888 13:43:48.249857 Write Rank0 MR1 =0xd6
889 13:43:48.250287 [Gating]
890 13:43:48.250620 ==
891 13:43:48.257142 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
892 13:43:48.260386 fsp= 1, odt_onoff= 1, Byte mode= 0
893 13:43:48.260888 ==
894 13:43:48.263627 3 1 0 |3534 3535 |(11 11)(11 11) |(1 1)(1 1)| 0
895 13:43:48.267062 3 1 4 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
896 13:43:48.273749 3 1 8 |3534 1c1c |(11 11)(11 11) |(0 0)(1 1)| 0
897 13:43:48.276998 3 1 12 |3534 3535 |(11 11)(11 11) |(0 0)(0 1)| 0
898 13:43:48.280543 3 1 16 |3534 3434 |(11 11)(11 11) |(0 0)(0 1)| 0
899 13:43:48.287157 3 1 20 |3534 2e2d |(11 11)(11 11) |(0 0)(0 1)| 0
900 13:43:48.290284 3 1 24 |3534 3433 |(11 11)(11 11) |(0 1)(0 1)| 0
901 13:43:48.293975 3 1 28 |3534 202 |(11 11)(11 11) |(0 1)(0 1)| 0
902 13:43:48.300597 3 2 0 |908 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
903 13:43:48.303674 3 2 4 |3d3d 504 |(11 11)(11 11) |(1 1)(1 1)| 0
904 13:43:48.307562 3 2 8 |3d3d 2828 |(11 11)(11 11) |(1 1)(1 1)| 0
905 13:43:48.310523 3 2 12 |3d3d 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0
906 13:43:48.317397 3 2 16 |3d3d 3c3b |(11 11)(11 11) |(1 1)(1 1)| 0
907 13:43:48.320585 3 2 20 |3d3d 2b2b |(11 11)(11 11) |(1 1)(1 1)| 0
908 13:43:48.324361 3 2 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
909 13:43:48.330579 3 2 28 |3d3d 1515 |(11 11)(11 11) |(1 1)(1 1)| 0
910 13:43:48.333595 3 3 0 |3d3d b0a |(11 11)(11 11) |(1 1)(1 1)| 0
911 13:43:48.337186 3 3 4 |3d3d 505 |(11 11)(11 11) |(1 1)(1 1)| 0
912 13:43:48.340516 3 3 8 |504 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
913 13:43:48.346902 [Byte 1] Lead/lag falling Transition (3, 3, 8)
914 13:43:48.350443 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
915 13:43:48.354000 [Byte 0] Lead/lag Transition tap number (1)
916 13:43:48.357325 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
917 13:43:48.363797 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
918 13:43:48.367353 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
919 13:43:48.370658 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
920 13:43:48.377374 3 4 0 |3d3d 504 |(11 11)(11 11) |(1 1)(1 1)| 0
921 13:43:48.380688 3 4 4 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
922 13:43:48.383945 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
923 13:43:48.387435 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
924 13:43:48.394139 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
925 13:43:48.397900 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
926 13:43:48.400924 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
927 13:43:48.407837 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
928 13:43:48.410830 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
929 13:43:48.414065 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
930 13:43:48.421134 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
931 13:43:48.424483 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
932 13:43:48.427715 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
933 13:43:48.431314 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
934 13:43:48.437963 [Byte 1] Lead/lag falling Transition (3, 5, 20)
935 13:43:48.441296 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 0)| 0
936 13:43:48.444573 [Byte 0] Lead/lag falling Transition (3, 5, 24)
937 13:43:48.451425 3 5 28 |202 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
938 13:43:48.454458 [Byte 0] Lead/lag Transition tap number (2)
939 13:43:48.458178 [Byte 1] Lead/lag Transition tap number (3)
940 13:43:48.461690 3 6 0 |4646 202 |(10 10)(11 11) |(0 0)(0 0)| 0
941 13:43:48.465357 3 6 4 |4646 404 |(0 0)(11 11) |(0 0)(0 0)| 0
942 13:43:48.468252 [Byte 0]First pass (3, 6, 4)
943 13:43:48.471812 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
944 13:43:48.474993 [Byte 1]First pass (3, 6, 8)
945 13:43:48.478566 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
946 13:43:48.481552 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
947 13:43:48.488433 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
948 13:43:48.491957 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
949 13:43:48.495179 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
950 13:43:48.498524 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
951 13:43:48.501898 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
952 13:43:48.508851 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
953 13:43:48.512116 All bytes gating window > 1UI, Early break!
954 13:43:48.512620
955 13:43:48.515432 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 28)
956 13:43:48.515950
957 13:43:48.518522 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 26)
958 13:43:48.518945
959 13:43:48.519280
960 13:43:48.519773
961 13:43:48.523002 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 28)
962 13:43:48.523506
963 13:43:48.525693 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 26)
964 13:43:48.528805
965 13:43:48.529366
966 13:43:48.529705 Write Rank0 MR1 =0x56
967 13:43:48.530015
968 13:43:48.532593 best RODT dly(2T, 0.5T) = (2, 2)
969 13:43:48.533092
970 13:43:48.535277 best RODT dly(2T, 0.5T) = (2, 2)
971 13:43:48.535701 ==
972 13:43:48.542006 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
973 13:43:48.545449 fsp= 1, odt_onoff= 1, Byte mode= 0
974 13:43:48.545954 ==
975 13:43:48.549030 Start DQ dly to find pass range UseTestEngine =0
976 13:43:48.552495 x-axis: bit #, y-axis: DQ dly (-127~63)
977 13:43:48.552995 RX Vref Scan = 0
978 13:43:48.555746 -26, [0] xxxxxxxx xxxxxxxx [MSB]
979 13:43:48.558844 -25, [0] xxxxxxxx xxxxxxxx [MSB]
980 13:43:48.561923 -24, [0] xxxxxxxx xxxxxxxx [MSB]
981 13:43:48.565125 -23, [0] xxxxxxxx xxxxxxxx [MSB]
982 13:43:48.568870 -22, [0] xxxxxxxx xxxxxxxx [MSB]
983 13:43:48.572312 -21, [0] xxxxxxxx xxxxxxxx [MSB]
984 13:43:48.575412 -20, [0] xxxxxxxx xxxxxxxx [MSB]
985 13:43:48.575844 -19, [0] xxxxxxxx xxxxxxxx [MSB]
986 13:43:48.578938 -18, [0] xxxxxxxx xxxxxxxx [MSB]
987 13:43:48.582300 -17, [0] xxxxxxxx xxxxxxxx [MSB]
988 13:43:48.585571 -16, [0] xxxxxxxx xxxxxxxx [MSB]
989 13:43:48.589318 -15, [0] xxxxxxxx xxxxxxxx [MSB]
990 13:43:48.592361 -14, [0] xxxxxxxx xxxxxxxx [MSB]
991 13:43:48.595655 -13, [0] xxxxxxxx xxxxxxxx [MSB]
992 13:43:48.598895 -12, [0] xxxxxxxx xxxxxxxx [MSB]
993 13:43:48.599487 -11, [0] xxxxxxxx xxxxxxxx [MSB]
994 13:43:48.602618 -10, [0] xxxxxxxx xxxxxxxx [MSB]
995 13:43:48.605738 -9, [0] xxxxxxxx xxxxxxxx [MSB]
996 13:43:48.608848 -8, [0] xxxxxxxx xxxxxxxx [MSB]
997 13:43:48.612628 -7, [0] xxxxxxxx xxxxxxxx [MSB]
998 13:43:48.615374 -6, [0] xxxxxxxx xxxxxxxx [MSB]
999 13:43:48.618804 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1000 13:43:48.619308 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1001 13:43:48.622378 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1002 13:43:48.625582 -2, [0] xxxoxxxx xxxxxxxx [MSB]
1003 13:43:48.628715 -1, [0] xxxoxoxx xxxxxxxx [MSB]
1004 13:43:48.632260 0, [0] xxxoxoxx xxxxxoxx [MSB]
1005 13:43:48.635366 1, [0] xxxoxooo xxxxxoxx [MSB]
1006 13:43:48.639105 2, [0] xxxoxooo ooxxxoxx [MSB]
1007 13:43:48.639619 3, [0] xxxoxooo ooxoooxx [MSB]
1008 13:43:48.642360 4, [0] xxxoxooo ooxooooo [MSB]
1009 13:43:48.645583 5, [0] xxxoxooo ooxooooo [MSB]
1010 13:43:48.649155 6, [0] xooooooo oooooooo [MSB]
1011 13:43:48.652768 7, [0] xooooooo oooooooo [MSB]
1012 13:43:48.653335 8, [0] xooooooo oooooooo [MSB]
1013 13:43:48.655960 30, [0] oooxoooo oooooooo [MSB]
1014 13:43:48.659398 31, [0] oooxoooo oooooooo [MSB]
1015 13:43:48.662286 32, [0] oooxoxxo oooooooo [MSB]
1016 13:43:48.665925 33, [0] oooxoxxo ooooooxo [MSB]
1017 13:43:48.669321 34, [0] oooxoxxo oooxooxo [MSB]
1018 13:43:48.672859 35, [0] oooxoxxx xooxooxo [MSB]
1019 13:43:48.673422 36, [0] oooxoxxx xooxooxo [MSB]
1020 13:43:48.676144 37, [0] oooxoxxx xooxxxxo [MSB]
1021 13:43:48.679585 38, [0] oooxxxxx xxoxxxxx [MSB]
1022 13:43:48.682399 39, [0] oxoxxxxx xxoxxxxx [MSB]
1023 13:43:48.686053 40, [0] oxxxxxxx xxoxxxxx [MSB]
1024 13:43:48.689378 41, [0] xxxxxxxx xxxxxxxx [MSB]
1025 13:43:48.692748 iDelay=41, Bit 0, Center 24 (9 ~ 40) 32
1026 13:43:48.695726 iDelay=41, Bit 1, Center 22 (6 ~ 38) 33
1027 13:43:48.699316 iDelay=41, Bit 2, Center 22 (6 ~ 39) 34
1028 13:43:48.703026 iDelay=41, Bit 3, Center 13 (-2 ~ 29) 32
1029 13:43:48.706129 iDelay=41, Bit 4, Center 21 (6 ~ 37) 32
1030 13:43:48.709578 iDelay=41, Bit 5, Center 15 (-1 ~ 31) 33
1031 13:43:48.713145 iDelay=41, Bit 6, Center 16 (1 ~ 31) 31
1032 13:43:48.716045 iDelay=41, Bit 7, Center 17 (1 ~ 34) 34
1033 13:43:48.719628 iDelay=41, Bit 8, Center 18 (2 ~ 34) 33
1034 13:43:48.722802 iDelay=41, Bit 9, Center 19 (2 ~ 37) 36
1035 13:43:48.726812 iDelay=41, Bit 10, Center 23 (6 ~ 40) 35
1036 13:43:48.729439 iDelay=41, Bit 11, Center 18 (3 ~ 33) 31
1037 13:43:48.733178 iDelay=41, Bit 12, Center 19 (3 ~ 36) 34
1038 13:43:48.739633 iDelay=41, Bit 13, Center 18 (0 ~ 36) 37
1039 13:43:48.743047 iDelay=41, Bit 14, Center 18 (4 ~ 32) 29
1040 13:43:48.746332 iDelay=41, Bit 15, Center 20 (4 ~ 37) 34
1041 13:43:48.746764 ==
1042 13:43:48.750034 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1043 13:43:48.753131 fsp= 1, odt_onoff= 1, Byte mode= 0
1044 13:43:48.753690 ==
1045 13:43:48.756326 DQS Delay:
1046 13:43:48.756750 DQS0 = 0, DQS1 = 0
1047 13:43:48.757083 DQM Delay:
1048 13:43:48.759803 DQM0 = 18, DQM1 = 19
1049 13:43:48.760311 DQ Delay:
1050 13:43:48.763219 DQ0 =24, DQ1 =22, DQ2 =22, DQ3 =13
1051 13:43:48.766884 DQ4 =21, DQ5 =15, DQ6 =16, DQ7 =17
1052 13:43:48.769810 DQ8 =18, DQ9 =19, DQ10 =23, DQ11 =18
1053 13:43:48.773264 DQ12 =19, DQ13 =18, DQ14 =18, DQ15 =20
1054 13:43:48.773698
1055 13:43:48.774029
1056 13:43:48.776775 DramC Write-DBI off
1057 13:43:48.777329 ==
1058 13:43:48.779852 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1059 13:43:48.783390 fsp= 1, odt_onoff= 1, Byte mode= 0
1060 13:43:48.783818 ==
1061 13:43:48.790228 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1062 13:43:48.790736
1063 13:43:48.791068 Begin, DQ Scan Range 924~1180
1064 13:43:48.791374
1065 13:43:48.793508
1066 13:43:48.793935 TX Vref Scan disable
1067 13:43:48.796778 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1068 13:43:48.800170 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1069 13:43:48.803766 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1070 13:43:48.806591 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1071 13:43:48.810202 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1072 13:43:48.813608 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1073 13:43:48.820217 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1074 13:43:48.824024 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1075 13:43:48.827439 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1076 13:43:48.830894 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1077 13:43:48.833883 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1078 13:43:48.837152 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1079 13:43:48.840253 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1080 13:43:48.843981 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1081 13:43:48.846901 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1082 13:43:48.850947 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1083 13:43:48.854037 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1084 13:43:48.857113 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1085 13:43:48.860714 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1086 13:43:48.863835 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1087 13:43:48.867581 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1088 13:43:48.870854 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1089 13:43:48.873968 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1090 13:43:48.877380 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1091 13:43:48.881010 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1092 13:43:48.883972 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1093 13:43:48.891074 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1094 13:43:48.893880 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1095 13:43:48.897615 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1096 13:43:48.900649 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1097 13:43:48.904165 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1098 13:43:48.907670 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1099 13:43:48.910740 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1100 13:43:48.914243 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1101 13:43:48.917599 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1102 13:43:48.921057 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1103 13:43:48.924281 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1104 13:43:48.927782 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1105 13:43:48.930992 962 |3 6 2|[0] xxxxxxxx oxxoxxxx [MSB]
1106 13:43:48.934785 963 |3 6 3|[0] xxxxxxxx ooxooxox [MSB]
1107 13:43:48.937643 964 |3 6 4|[0] xxxxxxxx ooxoooox [MSB]
1108 13:43:48.941376 965 |3 6 5|[0] xxxxxxxx ooxoooox [MSB]
1109 13:43:48.944647 966 |3 6 6|[0] xxxxxxxx ooxoooox [MSB]
1110 13:43:48.947743 967 |3 6 7|[0] xxxxxxxx ooxooooo [MSB]
1111 13:43:48.951161 968 |3 6 8|[0] xxxxxxxx oooooooo [MSB]
1112 13:43:48.954604 969 |3 6 9|[0] xxxxxxxx oooooooo [MSB]
1113 13:43:48.957975 970 |3 6 10|[0] xxxxxxxx oooooooo [MSB]
1114 13:43:48.961835 971 |3 6 11|[0] xxxoxoxx oooooooo [MSB]
1115 13:43:48.964493 972 |3 6 12|[0] xxxoxooo oooooooo [MSB]
1116 13:43:48.968278 973 |3 6 13|[0] xxxoxooo oooooooo [MSB]
1117 13:43:48.974824 974 |3 6 14|[0] xxxooooo oooooooo [MSB]
1118 13:43:48.977775 975 |3 6 15|[0] xooooooo oooooooo [MSB]
1119 13:43:48.981376 988 |3 6 28|[0] oooooooo xooooooo [MSB]
1120 13:43:48.984903 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1121 13:43:48.988029 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1122 13:43:48.991393 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1123 13:43:48.994765 992 |3 6 32|[0] oooxoooo xxxxxxxx [MSB]
1124 13:43:48.998248 993 |3 6 33|[0] oooxoxoo xxxxxxxx [MSB]
1125 13:43:49.005142 994 |3 6 34|[0] oooxoxxo xxxxxxxx [MSB]
1126 13:43:49.008600 995 |3 6 35|[0] xxxxxxxx xxxxxxxx [MSB]
1127 13:43:49.011584 Byte0, DQ PI dly=983, DQM PI dly= 983
1128 13:43:49.014863 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
1129 13:43:49.015314
1130 13:43:49.018496 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
1131 13:43:49.019025
1132 13:43:49.021864 Byte1, DQ PI dly=976, DQM PI dly= 976
1133 13:43:49.028466 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 16)
1134 13:43:49.028990
1135 13:43:49.031654 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 16)
1136 13:43:49.032177
1137 13:43:49.032509 ==
1138 13:43:49.034863 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1139 13:43:49.038271 fsp= 1, odt_onoff= 1, Byte mode= 0
1140 13:43:49.041990 ==
1141 13:43:49.044946 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1142 13:43:49.045402
1143 13:43:49.048312 Begin, DQ Scan Range 952~1016
1144 13:43:49.048748 Write Rank0 MR14 =0x0
1145 13:43:49.057770
1146 13:43:49.058270 CH=0, VrefRange= 0, VrefLevel = 0
1147 13:43:49.064689 TX Bit0 (977~995) 19 986, Bit8 (965~983) 19 974,
1148 13:43:49.068045 TX Bit1 (977~993) 17 985, Bit9 (966~984) 19 975,
1149 13:43:49.071472 TX Bit2 (977~994) 18 985, Bit10 (969~989) 21 979,
1150 13:43:49.078231 TX Bit3 (970~989) 20 979, Bit11 (966~984) 19 975,
1151 13:43:49.081428 TX Bit4 (976~994) 19 985, Bit12 (966~985) 20 975,
1152 13:43:49.088244 TX Bit5 (974~989) 16 981, Bit13 (967~983) 17 975,
1153 13:43:49.091390 TX Bit6 (975~990) 16 982, Bit14 (966~983) 18 974,
1154 13:43:49.094869 TX Bit7 (975~991) 17 983, Bit15 (969~987) 19 978,
1155 13:43:49.095299
1156 13:43:49.098189 Write Rank0 MR14 =0x2
1157 13:43:49.106802
1158 13:43:49.107302 CH=0, VrefRange= 0, VrefLevel = 2
1159 13:43:49.113343 TX Bit0 (977~995) 19 986, Bit8 (964~984) 21 974,
1160 13:43:49.116691 TX Bit1 (977~993) 17 985, Bit9 (965~984) 20 974,
1161 13:43:49.119944 TX Bit2 (976~994) 19 985, Bit10 (969~989) 21 979,
1162 13:43:49.126912 TX Bit3 (970~989) 20 979, Bit11 (965~985) 21 975,
1163 13:43:49.130153 TX Bit4 (976~995) 20 985, Bit12 (966~986) 21 976,
1164 13:43:49.137609 TX Bit5 (974~990) 17 982, Bit13 (967~983) 17 975,
1165 13:43:49.140307 TX Bit6 (975~990) 16 982, Bit14 (967~984) 18 975,
1166 13:43:49.143824 TX Bit7 (975~992) 18 983, Bit15 (968~988) 21 978,
1167 13:43:49.144329
1168 13:43:49.146809 Write Rank0 MR14 =0x4
1169 13:43:49.155396
1170 13:43:49.155917 CH=0, VrefRange= 0, VrefLevel = 4
1171 13:43:49.162073 TX Bit0 (977~996) 20 986, Bit8 (964~984) 21 974,
1172 13:43:49.165350 TX Bit1 (977~993) 17 985, Bit9 (965~985) 21 975,
1173 13:43:49.169059 TX Bit2 (976~994) 19 985, Bit10 (969~990) 22 979,
1174 13:43:49.175525 TX Bit3 (969~990) 22 979, Bit11 (965~984) 20 974,
1175 13:43:49.179360 TX Bit4 (976~995) 20 985, Bit12 (966~987) 22 976,
1176 13:43:49.185744 TX Bit5 (973~990) 18 981, Bit13 (966~984) 19 975,
1177 13:43:49.189003 TX Bit6 (974~991) 18 982, Bit14 (966~984) 19 975,
1178 13:43:49.192530 TX Bit7 (974~992) 19 983, Bit15 (968~988) 21 978,
1179 13:43:49.193051
1180 13:43:49.195467 Write Rank0 MR14 =0x6
1181 13:43:49.204453
1182 13:43:49.204969 CH=0, VrefRange= 0, VrefLevel = 6
1183 13:43:49.210921 TX Bit0 (977~996) 20 986, Bit8 (964~984) 21 974,
1184 13:43:49.214422 TX Bit1 (976~994) 19 985, Bit9 (965~986) 22 975,
1185 13:43:49.221609 TX Bit2 (976~995) 20 985, Bit10 (969~989) 21 979,
1186 13:43:49.224903 TX Bit3 (969~990) 22 979, Bit11 (964~986) 23 975,
1187 13:43:49.227894 TX Bit4 (976~996) 21 986, Bit12 (965~987) 23 976,
1188 13:43:49.234653 TX Bit5 (973~990) 18 981, Bit13 (966~984) 19 975,
1189 13:43:49.237955 TX Bit6 (974~991) 18 982, Bit14 (965~985) 21 975,
1190 13:43:49.241414 TX Bit7 (974~993) 20 983, Bit15 (968~989) 22 978,
1191 13:43:49.241923
1192 13:43:49.244714 Write Rank0 MR14 =0x8
1193 13:43:49.253493
1194 13:43:49.254007 CH=0, VrefRange= 0, VrefLevel = 8
1195 13:43:49.260225 TX Bit0 (977~997) 21 987, Bit8 (963~985) 23 974,
1196 13:43:49.263113 TX Bit1 (976~994) 19 985, Bit9 (964~986) 23 975,
1197 13:43:49.269998 TX Bit2 (976~996) 21 986, Bit10 (968~990) 23 979,
1198 13:43:49.273488 TX Bit3 (969~990) 22 979, Bit11 (964~987) 24 975,
1199 13:43:49.276994 TX Bit4 (975~997) 23 986, Bit12 (965~988) 24 976,
1200 13:43:49.283384 TX Bit5 (972~991) 20 981, Bit13 (965~985) 21 975,
1201 13:43:49.286518 TX Bit6 (973~991) 19 982, Bit14 (965~986) 22 975,
1202 13:43:49.290527 TX Bit7 (974~994) 21 984, Bit15 (968~989) 22 978,
1203 13:43:49.291031
1204 13:43:49.293205 Write Rank0 MR14 =0xa
1205 13:43:49.302451
1206 13:43:49.305833 CH=0, VrefRange= 0, VrefLevel = 10
1207 13:43:49.309038 TX Bit0 (976~997) 22 986, Bit8 (962~985) 24 973,
1208 13:43:49.360835 TX Bit1 (976~995) 20 985, Bit9 (964~987) 24 975,
1209 13:43:49.361543 TX Bit2 (976~997) 22 986, Bit10 (969~990) 22 979,
1210 13:43:49.361926 TX Bit3 (969~990) 22 979, Bit11 (964~987) 24 975,
1211 13:43:49.362237 TX Bit4 (975~997) 23 986, Bit12 (965~988) 24 976,
1212 13:43:49.362896 TX Bit5 (972~991) 20 981, Bit13 (965~986) 22 975,
1213 13:43:49.363223 TX Bit6 (973~992) 20 982, Bit14 (965~986) 22 975,
1214 13:43:49.363546 TX Bit7 (973~994) 22 983, Bit15 (967~989) 23 978,
1215 13:43:49.363884
1216 13:43:49.364165 Write Rank0 MR14 =0xc
1217 13:43:49.364461
1218 13:43:49.364759 CH=0, VrefRange= 0, VrefLevel = 12
1219 13:43:49.365036 TX Bit0 (976~998) 23 987, Bit8 (962~986) 25 974,
1220 13:43:49.365364 TX Bit1 (976~995) 20 985, Bit9 (963~988) 26 975,
1221 13:43:49.390682 TX Bit2 (975~997) 23 986, Bit10 (968~990) 23 979,
1222 13:43:49.391253 TX Bit3 (968~990) 23 979, Bit11 (963~988) 26 975,
1223 13:43:49.391597 TX Bit4 (975~998) 24 986, Bit12 (965~988) 24 976,
1224 13:43:49.392227 TX Bit5 (971~991) 21 981, Bit13 (965~986) 22 975,
1225 13:43:49.392593 TX Bit6 (972~992) 21 982, Bit14 (964~987) 24 975,
1226 13:43:49.392898 TX Bit7 (973~995) 23 984, Bit15 (967~989) 23 978,
1227 13:43:49.393204
1228 13:43:49.394655 Write Rank0 MR14 =0xe
1229 13:43:49.400855
1230 13:43:49.404120 CH=0, VrefRange= 0, VrefLevel = 14
1231 13:43:49.407383 TX Bit0 (976~998) 23 987, Bit8 (962~987) 26 974,
1232 13:43:49.411022 TX Bit1 (976~996) 21 986, Bit9 (963~988) 26 975,
1233 13:43:49.417548 TX Bit2 (975~997) 23 986, Bit10 (968~991) 24 979,
1234 13:43:49.421038 TX Bit3 (968~991) 24 979, Bit11 (963~988) 26 975,
1235 13:43:49.424706 TX Bit4 (974~998) 25 986, Bit12 (964~989) 26 976,
1236 13:43:49.431449 TX Bit5 (971~991) 21 981, Bit13 (964~987) 24 975,
1237 13:43:49.434532 TX Bit6 (971~992) 22 981, Bit14 (964~988) 25 976,
1238 13:43:49.437629 TX Bit7 (973~995) 23 984, Bit15 (967~990) 24 978,
1239 13:43:49.438070
1240 13:43:49.440883 Write Rank0 MR14 =0x10
1241 13:43:49.450147
1242 13:43:49.450640 CH=0, VrefRange= 0, VrefLevel = 16
1243 13:43:49.457427 TX Bit0 (976~998) 23 987, Bit8 (962~988) 27 975,
1244 13:43:49.461089 TX Bit1 (976~997) 22 986, Bit9 (962~989) 28 975,
1245 13:43:49.463668 TX Bit2 (975~998) 24 986, Bit10 (968~991) 24 979,
1246 13:43:49.470534 TX Bit3 (968~991) 24 979, Bit11 (962~988) 27 975,
1247 13:43:49.473894 TX Bit4 (974~998) 25 986, Bit12 (963~989) 27 976,
1248 13:43:49.480590 TX Bit5 (970~992) 23 981, Bit13 (964~987) 24 975,
1249 13:43:49.483697 TX Bit6 (971~993) 23 982, Bit14 (963~988) 26 975,
1250 13:43:49.487102 TX Bit7 (972~996) 25 984, Bit15 (967~990) 24 978,
1251 13:43:49.487529
1252 13:43:49.490365 Write Rank0 MR14 =0x12
1253 13:43:49.500005
1254 13:43:49.503122 CH=0, VrefRange= 0, VrefLevel = 18
1255 13:43:49.506655 TX Bit0 (975~999) 25 987, Bit8 (961~988) 28 974,
1256 13:43:49.509826 TX Bit1 (975~997) 23 986, Bit9 (962~988) 27 975,
1257 13:43:49.516508 TX Bit2 (975~998) 24 986, Bit10 (968~991) 24 979,
1258 13:43:49.519801 TX Bit3 (968~992) 25 980, Bit11 (962~989) 28 975,
1259 13:43:49.522762 TX Bit4 (974~998) 25 986, Bit12 (963~989) 27 976,
1260 13:43:49.529626 TX Bit5 (970~992) 23 981, Bit13 (963~988) 26 975,
1261 13:43:49.532883 TX Bit6 (971~994) 24 982, Bit14 (963~989) 27 976,
1262 13:43:49.536414 TX Bit7 (971~997) 27 984, Bit15 (967~990) 24 978,
1263 13:43:49.536843
1264 13:43:49.539350 Write Rank0 MR14 =0x14
1265 13:43:49.549608
1266 13:43:49.552691 CH=0, VrefRange= 0, VrefLevel = 20
1267 13:43:49.556465 TX Bit0 (975~999) 25 987, Bit8 (961~988) 28 974,
1268 13:43:49.559197 TX Bit1 (975~997) 23 986, Bit9 (963~989) 27 976,
1269 13:43:49.562695 TX Bit2 (974~998) 25 986, Bit10 (967~991) 25 979,
1270 13:43:49.569493 TX Bit3 (967~992) 26 979, Bit11 (962~988) 27 975,
1271 13:43:49.573093 TX Bit4 (974~998) 25 986, Bit12 (963~989) 27 976,
1272 13:43:49.579595 TX Bit5 (970~992) 23 981, Bit13 (963~988) 26 975,
1273 13:43:49.582791 TX Bit6 (970~994) 25 982, Bit14 (963~989) 27 976,
1274 13:43:49.586041 TX Bit7 (971~997) 27 984, Bit15 (966~990) 25 978,
1275 13:43:49.586475
1276 13:43:49.589221 Write Rank0 MR14 =0x16
1277 13:43:49.598878
1278 13:43:49.602184 CH=0, VrefRange= 0, VrefLevel = 22
1279 13:43:49.605633 TX Bit0 (975~999) 25 987, Bit8 (961~987) 27 974,
1280 13:43:49.608665 TX Bit1 (975~998) 24 986, Bit9 (963~988) 26 975,
1281 13:43:49.615587 TX Bit2 (974~998) 25 986, Bit10 (968~991) 24 979,
1282 13:43:49.619217 TX Bit3 (968~991) 24 979, Bit11 (962~988) 27 975,
1283 13:43:49.622533 TX Bit4 (974~999) 26 986, Bit12 (963~989) 27 976,
1284 13:43:49.629058 TX Bit5 (970~993) 24 981, Bit13 (962~987) 26 974,
1285 13:43:49.632142 TX Bit6 (970~995) 26 982, Bit14 (963~989) 27 976,
1286 13:43:49.635965 TX Bit7 (971~997) 27 984, Bit15 (966~990) 25 978,
1287 13:43:49.636478
1288 13:43:49.639363 Write Rank0 MR14 =0x18
1289 13:43:49.648216
1290 13:43:49.651385 CH=0, VrefRange= 0, VrefLevel = 24
1291 13:43:49.655435 TX Bit0 (975~999) 25 987, Bit8 (961~987) 27 974,
1292 13:43:49.658277 TX Bit1 (975~998) 24 986, Bit9 (963~988) 26 975,
1293 13:43:49.665064 TX Bit2 (974~998) 25 986, Bit10 (968~991) 24 979,
1294 13:43:49.668331 TX Bit3 (968~991) 24 979, Bit11 (962~988) 27 975,
1295 13:43:49.671855 TX Bit4 (974~999) 26 986, Bit12 (963~989) 27 976,
1296 13:43:49.678648 TX Bit5 (970~993) 24 981, Bit13 (962~987) 26 974,
1297 13:43:49.682189 TX Bit6 (970~995) 26 982, Bit14 (963~989) 27 976,
1298 13:43:49.685330 TX Bit7 (971~997) 27 984, Bit15 (966~990) 25 978,
1299 13:43:49.685841
1300 13:43:49.688441 Write Rank0 MR14 =0x1a
1301 13:43:49.698128
1302 13:43:49.698631 CH=0, VrefRange= 0, VrefLevel = 26
1303 13:43:49.704790 TX Bit0 (975~999) 25 987, Bit8 (961~987) 27 974,
1304 13:43:49.707949 TX Bit1 (975~998) 24 986, Bit9 (963~988) 26 975,
1305 13:43:49.714786 TX Bit2 (974~998) 25 986, Bit10 (968~991) 24 979,
1306 13:43:49.718220 TX Bit3 (968~991) 24 979, Bit11 (962~988) 27 975,
1307 13:43:49.721573 TX Bit4 (974~999) 26 986, Bit12 (963~989) 27 976,
1308 13:43:49.728342 TX Bit5 (970~993) 24 981, Bit13 (962~987) 26 974,
1309 13:43:49.731474 TX Bit6 (970~995) 26 982, Bit14 (963~989) 27 976,
1310 13:43:49.734882 TX Bit7 (971~997) 27 984, Bit15 (966~990) 25 978,
1311 13:43:49.735397
1312 13:43:49.737986 Write Rank0 MR14 =0x1c
1313 13:43:49.747648
1314 13:43:49.750510 CH=0, VrefRange= 0, VrefLevel = 28
1315 13:43:49.754217 TX Bit0 (975~999) 25 987, Bit8 (961~987) 27 974,
1316 13:43:49.757629 TX Bit1 (975~998) 24 986, Bit9 (963~988) 26 975,
1317 13:43:49.764239 TX Bit2 (974~998) 25 986, Bit10 (968~991) 24 979,
1318 13:43:49.767428 TX Bit3 (968~991) 24 979, Bit11 (962~988) 27 975,
1319 13:43:49.770637 TX Bit4 (974~999) 26 986, Bit12 (963~989) 27 976,
1320 13:43:49.777581 TX Bit5 (970~993) 24 981, Bit13 (962~987) 26 974,
1321 13:43:49.780893 TX Bit6 (970~995) 26 982, Bit14 (963~989) 27 976,
1322 13:43:49.784643 TX Bit7 (971~997) 27 984, Bit15 (966~990) 25 978,
1323 13:43:49.785170
1324 13:43:49.785554
1325 13:43:49.787636 TX Vref found, early break! 377< 389
1326 13:43:49.794433 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =762/100 ps
1327 13:43:49.797658 u1DelayCellOfst[0]=10 cells (8 PI)
1328 13:43:49.800935 u1DelayCellOfst[1]=8 cells (7 PI)
1329 13:43:49.804370 u1DelayCellOfst[2]=8 cells (7 PI)
1330 13:43:49.804876 u1DelayCellOfst[3]=0 cells (0 PI)
1331 13:43:49.807521 u1DelayCellOfst[4]=8 cells (7 PI)
1332 13:43:49.811361 u1DelayCellOfst[5]=2 cells (2 PI)
1333 13:43:49.814149 u1DelayCellOfst[6]=3 cells (3 PI)
1334 13:43:49.818046 u1DelayCellOfst[7]=6 cells (5 PI)
1335 13:43:49.821430 Byte0, DQ PI dly=979, DQM PI dly= 983
1336 13:43:49.824434 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1337 13:43:49.824863
1338 13:43:49.831752 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1339 13:43:49.832469
1340 13:43:49.834584 u1DelayCellOfst[8]=0 cells (0 PI)
1341 13:43:49.838131 u1DelayCellOfst[9]=1 cells (1 PI)
1342 13:43:49.838636 u1DelayCellOfst[10]=6 cells (5 PI)
1343 13:43:49.841219 u1DelayCellOfst[11]=1 cells (1 PI)
1344 13:43:49.844597 u1DelayCellOfst[12]=2 cells (2 PI)
1345 13:43:49.848234 u1DelayCellOfst[13]=0 cells (0 PI)
1346 13:43:49.851403 u1DelayCellOfst[14]=2 cells (2 PI)
1347 13:43:49.854793 u1DelayCellOfst[15]=5 cells (4 PI)
1348 13:43:49.857950 Byte1, DQ PI dly=974, DQM PI dly= 976
1349 13:43:49.861596 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 14)
1350 13:43:49.862104
1351 13:43:49.868479 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 14)
1352 13:43:49.869005
1353 13:43:49.869391 Write Rank0 MR14 =0x16
1354 13:43:49.869707
1355 13:43:49.871501 Final TX Range 0 Vref 22
1356 13:43:49.872005
1357 13:43:49.878410 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1358 13:43:49.878913
1359 13:43:49.884856 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1360 13:43:49.891975 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1361 13:43:49.898424 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1362 13:43:49.901863 Write Rank0 MR3 =0xb0
1363 13:43:49.902367 DramC Write-DBI on
1364 13:43:49.902796 ==
1365 13:43:49.908285 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1366 13:43:49.912091 fsp= 1, odt_onoff= 1, Byte mode= 0
1367 13:43:49.912611 ==
1368 13:43:49.915283 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1369 13:43:49.915787
1370 13:43:49.918690 Begin, DQ Scan Range 696~760
1371 13:43:49.919110
1372 13:43:49.919431
1373 13:43:49.921737 TX Vref Scan disable
1374 13:43:49.925277 696 |2 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1375 13:43:49.928385 697 |2 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1376 13:43:49.931814 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1377 13:43:49.935375 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1378 13:43:49.938303 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1379 13:43:49.941732 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1380 13:43:49.945177 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1381 13:43:49.948379 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1382 13:43:49.951789 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1383 13:43:49.955190 705 |2 6 1|[0] xxxxxxxx oooooooo [MSB]
1384 13:43:49.958506 706 |2 6 2|[0] xxxxxxxx oooooooo [MSB]
1385 13:43:49.961722 707 |2 6 3|[0] xxxxxxxx oooooooo [MSB]
1386 13:43:49.965330 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB]
1387 13:43:49.968726 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
1388 13:43:49.971817 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
1389 13:43:49.975640 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
1390 13:43:49.978794 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1391 13:43:49.982471 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1392 13:43:49.991860 734 |2 6 30|[0] oooooooo xxxxxxxx [MSB]
1393 13:43:49.994889 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
1394 13:43:49.998676 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
1395 13:43:50.001882 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1396 13:43:50.004968 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1397 13:43:50.008234 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1398 13:43:50.011608 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1399 13:43:50.015473 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1400 13:43:50.018459 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1401 13:43:50.022328 743 |2 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
1402 13:43:50.025283 Byte0, DQ PI dly=728, DQM PI dly= 728
1403 13:43:50.028866 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 24)
1404 13:43:50.029488
1405 13:43:50.035431 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 24)
1406 13:43:50.035937
1407 13:43:50.038759 Byte1, DQ PI dly=719, DQM PI dly= 719
1408 13:43:50.041778 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 15)
1409 13:43:50.042220
1410 13:43:50.045500 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 15)
1411 13:43:50.046005
1412 13:43:50.052779 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1413 13:43:50.058947 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1414 13:43:50.065744 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1415 13:43:50.069113 Write Rank0 MR3 =0x30
1416 13:43:50.072340 DramC Write-DBI off
1417 13:43:50.072862
1418 13:43:50.073190 [DATLAT]
1419 13:43:50.075822 Freq=1600, CH0 RK0, use_rxtx_scan=0
1420 13:43:50.076320
1421 13:43:50.076650 DATLAT Default: 0xf
1422 13:43:50.078842 7, 0xFFFF, sum=0
1423 13:43:50.079271 8, 0xFFFF, sum=0
1424 13:43:50.082434 9, 0xFFFF, sum=0
1425 13:43:50.082944 10, 0xFFFF, sum=0
1426 13:43:50.085821 11, 0xFFFF, sum=0
1427 13:43:50.086324 12, 0xFFFF, sum=0
1428 13:43:50.088959 13, 0xFFFF, sum=0
1429 13:43:50.089528 14, 0x0, sum=1
1430 13:43:50.092357 15, 0x0, sum=2
1431 13:43:50.092785 16, 0x0, sum=3
1432 13:43:50.093115 17, 0x0, sum=4
1433 13:43:50.099441 pattern=2 first_step=14 total pass=5 best_step=16
1434 13:43:50.099944 ==
1435 13:43:50.102385 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1436 13:43:50.106120 fsp= 1, odt_onoff= 1, Byte mode= 0
1437 13:43:50.106625 ==
1438 13:43:50.112521 Start DQ dly to find pass range UseTestEngine =1
1439 13:43:50.115574 x-axis: bit #, y-axis: DQ dly (-127~63)
1440 13:43:50.116001 RX Vref Scan = 1
1441 13:43:50.238811
1442 13:43:50.239333 RX Vref found, early break!
1443 13:43:50.239668
1444 13:43:50.245325 Final RX Vref 13, apply to both rank0 and 1
1445 13:43:50.245832 ==
1446 13:43:50.248953 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1447 13:43:50.251887 fsp= 1, odt_onoff= 1, Byte mode= 0
1448 13:43:50.252392 ==
1449 13:43:50.252722 DQS Delay:
1450 13:43:50.254985 DQS0 = 0, DQS1 = 0
1451 13:43:50.255410 DQM Delay:
1452 13:43:50.258755 DQM0 = 19, DQM1 = 18
1453 13:43:50.259213 DQ Delay:
1454 13:43:50.262107 DQ0 =24, DQ1 =23, DQ2 =23, DQ3 =13
1455 13:43:50.265506 DQ4 =22, DQ5 =15, DQ6 =17, DQ7 =18
1456 13:43:50.268811 DQ8 =17, DQ9 =19, DQ10 =22, DQ11 =17
1457 13:43:50.272150 DQ12 =19, DQ13 =16, DQ14 =17, DQ15 =20
1458 13:43:50.272654
1459 13:43:50.272984
1460 13:43:50.273345
1461 13:43:50.275491 [DramC_TX_OE_Calibration] TA2
1462 13:43:50.278823 Original DQ_B0 (3 6) =30, OEN = 27
1463 13:43:50.282189 Original DQ_B1 (3 6) =30, OEN = 27
1464 13:43:50.285684 23, 0x0, End_B0=23 End_B1=23
1465 13:43:50.286203 24, 0x0, End_B0=24 End_B1=24
1466 13:43:50.288755 25, 0x0, End_B0=25 End_B1=25
1467 13:43:50.291890 26, 0x0, End_B0=26 End_B1=26
1468 13:43:50.295447 27, 0x0, End_B0=27 End_B1=27
1469 13:43:50.295881 28, 0x0, End_B0=28 End_B1=28
1470 13:43:50.298678 29, 0x0, End_B0=29 End_B1=29
1471 13:43:50.302201 30, 0x0, End_B0=30 End_B1=30
1472 13:43:50.305755 31, 0xFFFF, End_B0=30 End_B1=30
1473 13:43:50.309079 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1474 13:43:50.315617 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1475 13:43:50.316111
1476 13:43:50.316437
1477 13:43:50.318572 Write Rank0 MR23 =0x3f
1478 13:43:50.318912 [DQSOSC]
1479 13:43:50.325922 [DQSOSCAuto] RK0, (LSB)MR18= 0x9d, (MSB)MR19= 0x3, tDQSOscB0 = 340 ps tDQSOscB1 = 0 ps
1480 13:43:50.332493 CH0_RK0: MR19=0x3, MR18=0x9D, DQSOSC=340, MR23=63, INC=21, DEC=31
1481 13:43:50.335557 Write Rank0 MR23 =0x3f
1482 13:43:50.335987 [DQSOSC]
1483 13:43:50.342741 [DQSOSCAuto] RK0, (LSB)MR18= 0x9c, (MSB)MR19= 0x3, tDQSOscB0 = 340 ps tDQSOscB1 = 0 ps
1484 13:43:50.345895 CH0 RK0: MR19=3, MR18=9C
1485 13:43:50.348963 [RankSwap] Rank num 2, (Multi 1), Rank 1
1486 13:43:50.352282 Write Rank0 MR2 =0xad
1487 13:43:50.352707 [Write Leveling]
1488 13:43:50.356042 delay byte0 byte1 byte2 byte3
1489 13:43:50.356543
1490 13:43:50.356868 10 0 0
1491 13:43:50.359321 11 0 0
1492 13:43:50.359774 12 0 0
1493 13:43:50.362527 13 0 0
1494 13:43:50.362958 14 0 0
1495 13:43:50.363293 15 0 0
1496 13:43:50.366051 16 0 0
1497 13:43:50.366498 17 0 0
1498 13:43:50.369371 18 0 0
1499 13:43:50.369898 19 0 0
1500 13:43:50.370343 20 0 0
1501 13:43:50.372573 21 0 0
1502 13:43:50.373095 22 0 0
1503 13:43:50.376240 23 0 0
1504 13:43:50.376766 24 0 0
1505 13:43:50.377107 25 0 0
1506 13:43:50.379264 26 0 0
1507 13:43:50.379698 27 0 0
1508 13:43:50.382634 28 0 0
1509 13:43:50.383147 29 0 0
1510 13:43:50.386439 30 0 ff
1511 13:43:50.386951 31 0 ff
1512 13:43:50.387288 32 0 ff
1513 13:43:50.389692 33 0 ff
1514 13:43:50.390213 34 ff ff
1515 13:43:50.393059 35 ff ff
1516 13:43:50.393609 36 ff ff
1517 13:43:50.396558 37 ff ff
1518 13:43:50.397067 38 ff ff
1519 13:43:50.399575 39 ff ff
1520 13:43:50.400006 40 ff ff
1521 13:43:50.402906 pass bytecount = 0xff (0xff: all bytes pass)
1522 13:43:50.403414
1523 13:43:50.405999 DQS0 dly: 34
1524 13:43:50.406423 DQS1 dly: 30
1525 13:43:50.409523 Write Rank0 MR2 =0x2d
1526 13:43:50.413099 [RankSwap] Rank num 2, (Multi 1), Rank 0
1527 13:43:50.413584 Write Rank1 MR1 =0xd6
1528 13:43:50.416416 [Gating]
1529 13:43:50.416933 ==
1530 13:43:50.419537 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1531 13:43:50.422999 fsp= 1, odt_onoff= 1, Byte mode= 0
1532 13:43:50.423509 ==
1533 13:43:50.426449 3 1 0 |3534 3635 |(11 11)(11 11) |(0 0)(0 0)| 0
1534 13:43:50.433185 3 1 4 |3534 3737 |(11 11)(0 0) |(1 1)(0 0)| 0
1535 13:43:50.436173 3 1 8 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1536 13:43:50.439884 3 1 12 |3534 3736 |(11 11)(11 11) |(1 1)(1 1)| 0
1537 13:43:50.446637 3 1 16 |3534 a0a |(11 11)(11 11) |(0 0)(1 1)| 0
1538 13:43:50.449744 3 1 20 |3534 403 |(11 11)(11 11) |(0 0)(1 1)| 0
1539 13:43:50.453133 3 1 24 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1540 13:43:50.456574 [Byte 1] Lead/lag falling Transition (3, 1, 24)
1541 13:43:50.463086 3 1 28 |3534 1413 |(11 11)(11 11) |(0 0)(0 1)| 0
1542 13:43:50.466478 3 2 0 |3534 1515 |(11 11)(11 11) |(0 1)(0 1)| 0
1543 13:43:50.470205 3 2 4 |3534 3434 |(11 11)(0 0) |(0 1)(0 1)| 0
1544 13:43:50.476903 3 2 8 |403 302f |(11 11)(11 11) |(0 1)(0 1)| 0
1545 13:43:50.480221 [Byte 1] Lead/lag Transition tap number (5)
1546 13:43:50.483484 3 2 12 |3d3d 201 |(11 11)(11 11) |(1 1)(0 0)| 0
1547 13:43:50.487080 3 2 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1548 13:43:50.493157 3 2 20 |3d3d 3d3d |(11 11)(0 0) |(1 1)(1 1)| 0
1549 13:43:50.497047 3 2 24 |3d3d 3c3b |(11 11)(11 11) |(1 1)(1 1)| 0
1550 13:43:50.500211 3 2 28 |3d3d 3c3c |(11 11)(0 0) |(1 1)(0 0)| 0
1551 13:43:50.503566 3 3 0 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
1552 13:43:50.510032 3 3 4 |3d3d c0c |(11 11)(11 11) |(1 1)(1 1)| 0
1553 13:43:50.513547 3 3 8 |3d3d 908 |(11 11)(11 11) |(1 1)(1 1)| 0
1554 13:43:50.517198 3 3 12 |3d3d 1b1b |(11 11)(11 11) |(1 1)(1 1)| 0
1555 13:43:50.520406 3 3 16 |2726 1413 |(11 11)(11 11) |(1 1)(1 1)| 0
1556 13:43:50.527084 3 3 20 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1557 13:43:50.530834 [Byte 0] Lead/lag Transition tap number (1)
1558 13:43:50.534176 [Byte 1] Lead/lag falling Transition (3, 3, 20)
1559 13:43:50.537154 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1560 13:43:50.544201 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1561 13:43:50.547665 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1562 13:43:50.550613 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1563 13:43:50.557031 3 4 8 |403 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1564 13:43:50.560979 3 4 12 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
1565 13:43:50.563959 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1566 13:43:50.570662 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1567 13:43:50.574279 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1568 13:43:50.577333 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1569 13:43:50.580622 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1570 13:43:50.587355 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1571 13:43:50.590815 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1572 13:43:50.593991 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1573 13:43:50.600987 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1574 13:43:50.604315 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1575 13:43:50.607656 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1576 13:43:50.614614 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1577 13:43:50.617741 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1578 13:43:50.621473 [Byte 0] Lead/lag falling Transition (3, 6, 0)
1579 13:43:50.624436 [Byte 1] Lead/lag falling Transition (3, 6, 0)
1580 13:43:50.630825 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
1581 13:43:50.634613 [Byte 0] Lead/lag Transition tap number (2)
1582 13:43:50.637842 [Byte 1] Lead/lag Transition tap number (2)
1583 13:43:50.641176 3 6 8 |202 3d3d |(11 11)(11 11) |(0 0)(0 0)| 0
1584 13:43:50.644634 3 6 12 |4646 202 |(10 10)(11 11) |(0 0)(0 0)| 0
1585 13:43:50.651126 3 6 16 |4646 4242 |(0 0)(1 1) |(0 0)(0 0)| 0
1586 13:43:50.651566 [Byte 0]First pass (3, 6, 16)
1587 13:43:50.658062 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1588 13:43:50.658568 [Byte 1]First pass (3, 6, 20)
1589 13:43:50.664164 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1590 13:43:50.667523 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1591 13:43:50.671524 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1592 13:43:50.674445 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1593 13:43:50.677616 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1594 13:43:50.684666 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1595 13:43:50.687904 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1596 13:43:50.690875 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1597 13:43:50.694609 All bytes gating window > 1UI, Early break!
1598 13:43:50.694712
1599 13:43:50.698121 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 4)
1600 13:43:50.698552
1601 13:43:50.701641 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 4)
1602 13:43:50.702196
1603 13:43:50.702630
1604 13:43:50.704921
1605 13:43:50.708697 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 4)
1606 13:43:50.709212
1607 13:43:50.712174 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 4)
1608 13:43:50.712684
1609 13:43:50.713015
1610 13:43:50.715327 Write Rank1 MR1 =0x56
1611 13:43:50.715751
1612 13:43:50.716084 best RODT dly(2T, 0.5T) = (2, 3)
1613 13:43:50.716395
1614 13:43:50.718356 best RODT dly(2T, 0.5T) = (2, 3)
1615 13:43:50.718789 ==
1616 13:43:50.725279 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1617 13:43:50.728872 fsp= 1, odt_onoff= 1, Byte mode= 0
1618 13:43:50.729437 ==
1619 13:43:50.731910 Start DQ dly to find pass range UseTestEngine =0
1620 13:43:50.735349 x-axis: bit #, y-axis: DQ dly (-127~63)
1621 13:43:50.738930 RX Vref Scan = 0
1622 13:43:50.741974 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1623 13:43:50.742494 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1624 13:43:50.745077 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1625 13:43:50.748731 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1626 13:43:50.752152 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1627 13:43:50.755631 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1628 13:43:50.758836 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1629 13:43:50.762070 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1630 13:43:50.765626 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1631 13:43:50.766289 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1632 13:43:50.768962 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1633 13:43:50.772506 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1634 13:43:50.775873 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1635 13:43:50.778996 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1636 13:43:50.782738 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1637 13:43:50.785752 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1638 13:43:50.789392 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1639 13:43:50.789943 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1640 13:43:50.792575 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1641 13:43:50.796157 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1642 13:43:50.798960 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1643 13:43:50.802549 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1644 13:43:50.805993 -4, [0] xxxoxxxx xxxxxxxx [MSB]
1645 13:43:50.806478 -3, [0] xxxoxxxx xxxxxxxx [MSB]
1646 13:43:50.809156 -2, [0] xxxoxxxx xxxxxxxx [MSB]
1647 13:43:50.812975 -1, [0] xxxoxoox oxxxxxxx [MSB]
1648 13:43:50.815961 0, [0] xxxoxooo oxxxxxxx [MSB]
1649 13:43:50.819202 1, [0] xxxoxooo ooxoooox [MSB]
1650 13:43:50.822775 2, [0] xxxoxooo ooxooooo [MSB]
1651 13:43:50.823009 3, [0] xxxoxooo ooxooooo [MSB]
1652 13:43:50.826096 4, [0] xxxooooo ooxooooo [MSB]
1653 13:43:50.829278 5, [0] xooooooo oooooooo [MSB]
1654 13:43:50.832367 6, [0] xooooooo oooooooo [MSB]
1655 13:43:50.836214 33, [0] oooxoooo oooooooo [MSB]
1656 13:43:50.839522 34, [0] oooxoxoo oooooooo [MSB]
1657 13:43:50.839759 35, [0] oooxoxoo oooxooxo [MSB]
1658 13:43:50.842922 36, [0] oooxoxxx xooxooxo [MSB]
1659 13:43:50.846142 37, [0] oooxoxxx xooxoxxo [MSB]
1660 13:43:50.849435 38, [0] oooxoxxx xxoxoxxo [MSB]
1661 13:43:50.852904 39, [0] oooxoxxx xxoxxxxo [MSB]
1662 13:43:50.856406 40, [0] oxoxoxxx xxoxxxxx [MSB]
1663 13:43:50.859663 41, [0] oxxxxxxx xxoxxxxx [MSB]
1664 13:43:50.860154 42, [0] xxxxxxxx xxoxxxxx [MSB]
1665 13:43:50.863098 43, [0] xxxxxxxx xxxxxxxx [MSB]
1666 13:43:50.866643 iDelay=43, Bit 0, Center 24 (7 ~ 41) 35
1667 13:43:50.869892 iDelay=43, Bit 1, Center 22 (5 ~ 39) 35
1668 13:43:50.873118 iDelay=43, Bit 2, Center 22 (5 ~ 40) 36
1669 13:43:50.876753 iDelay=43, Bit 3, Center 14 (-4 ~ 32) 37
1670 13:43:50.883522 iDelay=43, Bit 4, Center 22 (4 ~ 40) 37
1671 13:43:50.886802 iDelay=43, Bit 5, Center 16 (-1 ~ 33) 35
1672 13:43:50.889955 iDelay=43, Bit 6, Center 17 (-1 ~ 35) 37
1673 13:43:50.893309 iDelay=43, Bit 7, Center 17 (0 ~ 35) 36
1674 13:43:50.896555 iDelay=43, Bit 8, Center 17 (-1 ~ 35) 37
1675 13:43:50.899909 iDelay=43, Bit 9, Center 19 (1 ~ 37) 37
1676 13:43:50.903342 iDelay=43, Bit 10, Center 23 (5 ~ 42) 38
1677 13:43:50.906719 iDelay=43, Bit 11, Center 17 (1 ~ 34) 34
1678 13:43:50.910031 iDelay=43, Bit 12, Center 19 (1 ~ 38) 38
1679 13:43:50.914019 iDelay=43, Bit 13, Center 18 (1 ~ 36) 36
1680 13:43:50.917100 iDelay=43, Bit 14, Center 17 (1 ~ 34) 34
1681 13:43:50.920157 iDelay=43, Bit 15, Center 20 (2 ~ 39) 38
1682 13:43:50.920588 ==
1683 13:43:50.927194 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1684 13:43:50.930419 fsp= 1, odt_onoff= 1, Byte mode= 0
1685 13:43:50.930932 ==
1686 13:43:50.931270 DQS Delay:
1687 13:43:50.933826 DQS0 = 0, DQS1 = 0
1688 13:43:50.934334 DQM Delay:
1689 13:43:50.937033 DQM0 = 19, DQM1 = 18
1690 13:43:50.937498 DQ Delay:
1691 13:43:50.940254 DQ0 =24, DQ1 =22, DQ2 =22, DQ3 =14
1692 13:43:50.944361 DQ4 =22, DQ5 =16, DQ6 =17, DQ7 =17
1693 13:43:50.947008 DQ8 =17, DQ9 =19, DQ10 =23, DQ11 =17
1694 13:43:50.950848 DQ12 =19, DQ13 =18, DQ14 =17, DQ15 =20
1695 13:43:50.951359
1696 13:43:50.951694
1697 13:43:50.952001 DramC Write-DBI off
1698 13:43:50.952294 ==
1699 13:43:50.957481 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1700 13:43:50.960607 fsp= 1, odt_onoff= 1, Byte mode= 0
1701 13:43:50.961119 ==
1702 13:43:50.964364 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1703 13:43:50.964873
1704 13:43:50.967148 Begin, DQ Scan Range 926~1182
1705 13:43:50.967813
1706 13:43:50.968210
1707 13:43:50.970740 TX Vref Scan disable
1708 13:43:50.973740 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1709 13:43:50.977755 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1710 13:43:50.980889 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1711 13:43:50.984206 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1712 13:43:50.987391 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1713 13:43:50.990794 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1714 13:43:50.994113 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1715 13:43:50.997560 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1716 13:43:51.000934 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1717 13:43:51.004435 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1718 13:43:51.007322 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1719 13:43:51.010828 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1720 13:43:51.014440 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1721 13:43:51.017648 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1722 13:43:51.020971 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1723 13:43:51.028068 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1724 13:43:51.031879 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1725 13:43:51.034892 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1726 13:43:51.038130 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1727 13:43:51.041393 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1728 13:43:51.044548 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1729 13:43:51.048190 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1730 13:43:51.051358 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1731 13:43:51.054648 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1732 13:43:51.058219 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1733 13:43:51.061783 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1734 13:43:51.064782 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1735 13:43:51.068135 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1736 13:43:51.072007 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1737 13:43:51.074898 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1738 13:43:51.078321 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1739 13:43:51.081760 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1740 13:43:51.085106 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1741 13:43:51.088310 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1742 13:43:51.091693 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1743 13:43:51.095230 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1744 13:43:51.102201 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1745 13:43:51.105422 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1746 13:43:51.108657 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1747 13:43:51.111748 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1748 13:43:51.115548 966 |3 6 6|[0] xxxxxxxx oxxxxxxx [MSB]
1749 13:43:51.118905 967 |3 6 7|[0] xxxxxxxx ooxoxoxx [MSB]
1750 13:43:51.122435 968 |3 6 8|[0] xxxxxxxx ooxooooo [MSB]
1751 13:43:51.125716 969 |3 6 9|[0] xxxxxxxx ooxooooo [MSB]
1752 13:43:51.128951 970 |3 6 10|[0] xxxxxxxx ooxooooo [MSB]
1753 13:43:51.132402 971 |3 6 11|[0] xxxxxxxx ooxooooo [MSB]
1754 13:43:51.135313 972 |3 6 12|[0] xxxoxoox ooxooooo [MSB]
1755 13:43:51.138994 973 |3 6 13|[0] xxxoxoox oooooooo [MSB]
1756 13:43:51.142235 974 |3 6 14|[0] xxxoxoox oooooooo [MSB]
1757 13:43:51.145477 975 |3 6 15|[0] xxxoxooo oooooooo [MSB]
1758 13:43:51.148512 976 |3 6 16|[0] xxoooooo oooooooo [MSB]
1759 13:43:51.156284 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1760 13:43:51.159436 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1761 13:43:51.163168 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1762 13:43:51.166338 993 |3 6 33|[0] oooxoooo xxxxxxxx [MSB]
1763 13:43:51.169693 994 |3 6 34|[0] oooxoxoo xxxxxxxx [MSB]
1764 13:43:51.172999 995 |3 6 35|[0] oooxoxxo xxxxxxxx [MSB]
1765 13:43:51.176478 996 |3 6 36|[0] oooxoxxo xxxxxxxx [MSB]
1766 13:43:51.179747 997 |3 6 37|[0] oooxoxxo xxxxxxxx [MSB]
1767 13:43:51.182955 998 |3 6 38|[0] xxxxxxxx xxxxxxxx [MSB]
1768 13:43:51.186488 Byte0, DQ PI dly=984, DQM PI dly= 984
1769 13:43:51.189872 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
1770 13:43:51.190390
1771 13:43:51.196553 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
1772 13:43:51.197194
1773 13:43:51.199703 Byte1, DQ PI dly=979, DQM PI dly= 979
1774 13:43:51.203494 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1775 13:43:51.204001
1776 13:43:51.206614 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1777 13:43:51.207048
1778 13:43:51.207380 ==
1779 13:43:51.213166 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1780 13:43:51.216492 fsp= 1, odt_onoff= 1, Byte mode= 0
1781 13:43:51.217003 ==
1782 13:43:51.219716 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1783 13:43:51.220141
1784 13:43:51.223763 Begin, DQ Scan Range 955~1019
1785 13:43:51.226812 Write Rank1 MR14 =0x0
1786 13:43:51.234226
1787 13:43:51.234737 CH=0, VrefRange= 0, VrefLevel = 0
1788 13:43:51.240667 TX Bit0 (977~997) 21 987, Bit8 (967~986) 20 976,
1789 13:43:51.243710 TX Bit1 (977~994) 18 985, Bit9 (969~988) 20 978,
1790 13:43:51.250387 TX Bit2 (978~996) 19 987, Bit10 (974~990) 17 982,
1791 13:43:51.253884 TX Bit3 (973~989) 17 981, Bit11 (968~987) 20 977,
1792 13:43:51.256737 TX Bit4 (977~996) 20 986, Bit12 (969~989) 21 979,
1793 13:43:51.263410 TX Bit5 (975~990) 16 982, Bit13 (969~985) 17 977,
1794 13:43:51.266792 TX Bit6 (975~991) 17 983, Bit14 (970~987) 18 978,
1795 13:43:51.270349 TX Bit7 (977~992) 16 984, Bit15 (973~990) 18 981,
1796 13:43:51.270434
1797 13:43:51.273723 Write Rank1 MR14 =0x2
1798 13:43:51.281833
1799 13:43:51.281919 CH=0, VrefRange= 0, VrefLevel = 2
1800 13:43:51.288594 TX Bit0 (978~997) 20 987, Bit8 (967~987) 21 977,
1801 13:43:51.291925 TX Bit1 (977~995) 19 986, Bit9 (969~988) 20 978,
1802 13:43:51.299378 TX Bit2 (978~996) 19 987, Bit10 (974~991) 18 982,
1803 13:43:51.302108 TX Bit3 (973~990) 18 981, Bit11 (968~987) 20 977,
1804 13:43:51.305564 TX Bit4 (977~997) 21 987, Bit12 (969~988) 20 978,
1805 13:43:51.312202 TX Bit5 (975~990) 16 982, Bit13 (969~986) 18 977,
1806 13:43:51.315758 TX Bit6 (975~991) 17 983, Bit14 (969~988) 20 978,
1807 13:43:51.318714 TX Bit7 (977~992) 16 984, Bit15 (972~990) 19 981,
1808 13:43:51.318795
1809 13:43:51.322229 wait MRW command Rank1 MR14 =0x4 fired (1)
1810 13:43:51.325380 Write Rank1 MR14 =0x4
1811 13:43:51.334530
1812 13:43:51.334616 CH=0, VrefRange= 0, VrefLevel = 4
1813 13:43:51.341254 TX Bit0 (977~998) 22 987, Bit8 (967~988) 22 977,
1814 13:43:51.344676 TX Bit1 (977~996) 20 986, Bit9 (969~989) 21 979,
1815 13:43:51.351201 TX Bit2 (977~997) 21 987, Bit10 (974~991) 18 982,
1816 13:43:51.354576 TX Bit3 (973~990) 18 981, Bit11 (968~988) 21 978,
1817 13:43:51.358115 TX Bit4 (977~997) 21 987, Bit12 (969~989) 21 979,
1818 13:43:51.365059 TX Bit5 (974~991) 18 982, Bit13 (969~987) 19 978,
1819 13:43:51.368115 TX Bit6 (974~991) 18 982, Bit14 (969~989) 21 979,
1820 13:43:51.371392 TX Bit7 (977~993) 17 985, Bit15 (972~990) 19 981,
1821 13:43:51.371472
1822 13:43:51.374690 Write Rank1 MR14 =0x6
1823 13:43:51.383567
1824 13:43:51.383659 CH=0, VrefRange= 0, VrefLevel = 6
1825 13:43:51.390256 TX Bit0 (977~998) 22 987, Bit8 (967~988) 22 977,
1826 13:43:51.393450 TX Bit1 (977~996) 20 986, Bit9 (968~989) 22 978,
1827 13:43:51.400170 TX Bit2 (977~997) 21 987, Bit10 (974~991) 18 982,
1828 13:43:51.403434 TX Bit3 (972~990) 19 981, Bit11 (968~989) 22 978,
1829 13:43:51.406721 TX Bit4 (977~997) 21 987, Bit12 (969~989) 21 979,
1830 13:43:51.413475 TX Bit5 (974~991) 18 982, Bit13 (968~988) 21 978,
1831 13:43:51.416720 TX Bit6 (974~992) 19 983, Bit14 (968~989) 22 978,
1832 13:43:51.420330 TX Bit7 (977~993) 17 985, Bit15 (971~991) 21 981,
1833 13:43:51.420417
1834 13:43:51.423997 Write Rank1 MR14 =0x8
1835 13:43:51.432171
1836 13:43:51.432250 CH=0, VrefRange= 0, VrefLevel = 8
1837 13:43:51.439099 TX Bit0 (977~998) 22 987, Bit8 (967~989) 23 978,
1838 13:43:51.441923 TX Bit1 (977~997) 21 987, Bit9 (968~989) 22 978,
1839 13:43:51.445521 TX Bit2 (977~998) 22 987, Bit10 (973~992) 20 982,
1840 13:43:51.452390 TX Bit3 (971~990) 20 980, Bit11 (967~989) 23 978,
1841 13:43:51.455690 TX Bit4 (976~998) 23 987, Bit12 (968~990) 23 979,
1842 13:43:51.462517 TX Bit5 (973~991) 19 982, Bit13 (968~988) 21 978,
1843 13:43:51.465928 TX Bit6 (974~993) 20 983, Bit14 (968~989) 22 978,
1844 13:43:51.469048 TX Bit7 (977~994) 18 985, Bit15 (970~991) 22 980,
1845 13:43:51.469126
1846 13:43:51.472544 wait MRW command Rank1 MR14 =0xa fired (1)
1847 13:43:51.475827 Write Rank1 MR14 =0xa
1848 13:43:51.484771
1849 13:43:51.488459 CH=0, VrefRange= 0, VrefLevel = 10
1850 13:43:51.491507 TX Bit0 (977~999) 23 988, Bit8 (967~989) 23 978,
1851 13:43:51.494897 TX Bit1 (977~997) 21 987, Bit9 (968~989) 22 978,
1852 13:43:51.501608 TX Bit2 (977~998) 22 987, Bit10 (973~992) 20 982,
1853 13:43:51.504868 TX Bit3 (971~991) 21 981, Bit11 (967~989) 23 978,
1854 13:43:51.508414 TX Bit4 (976~998) 23 987, Bit12 (968~990) 23 979,
1855 13:43:51.515024 TX Bit5 (973~992) 20 982, Bit13 (968~988) 21 978,
1856 13:43:51.518486 TX Bit6 (974~993) 20 983, Bit14 (968~989) 22 978,
1857 13:43:51.522080 TX Bit7 (976~994) 19 985, Bit15 (971~991) 21 981,
1858 13:43:51.522213
1859 13:43:51.524971 Write Rank1 MR14 =0xc
1860 13:43:51.533717
1861 13:43:51.536975 CH=0, VrefRange= 0, VrefLevel = 12
1862 13:43:51.540452 TX Bit0 (977~999) 23 988, Bit8 (966~989) 24 977,
1863 13:43:51.543889 TX Bit1 (977~998) 22 987, Bit9 (967~990) 24 978,
1864 13:43:51.550868 TX Bit2 (976~998) 23 987, Bit10 (973~992) 20 982,
1865 13:43:51.553974 TX Bit3 (971~991) 21 981, Bit11 (967~989) 23 978,
1866 13:43:51.557284 TX Bit4 (976~999) 24 987, Bit12 (968~990) 23 979,
1867 13:43:51.563878 TX Bit5 (972~992) 21 982, Bit13 (968~989) 22 978,
1868 13:43:51.567547 TX Bit6 (973~994) 22 983, Bit14 (968~990) 23 979,
1869 13:43:51.570824 TX Bit7 (976~995) 20 985, Bit15 (969~991) 23 980,
1870 13:43:51.570935
1871 13:43:51.574035 Write Rank1 MR14 =0xe
1872 13:43:51.583174
1873 13:43:51.586379 CH=0, VrefRange= 0, VrefLevel = 14
1874 13:43:51.589632 TX Bit0 (977~999) 23 988, Bit8 (966~989) 24 977,
1875 13:43:51.592895 TX Bit1 (977~998) 22 987, Bit9 (968~990) 23 979,
1876 13:43:51.599872 TX Bit2 (977~998) 22 987, Bit10 (973~993) 21 983,
1877 13:43:51.602870 TX Bit3 (970~991) 22 980, Bit11 (967~990) 24 978,
1878 13:43:51.606496 TX Bit4 (976~999) 24 987, Bit12 (968~990) 23 979,
1879 13:43:51.613145 TX Bit5 (972~992) 21 982, Bit13 (968~989) 22 978,
1880 13:43:51.616282 TX Bit6 (972~994) 23 983, Bit14 (968~990) 23 979,
1881 13:43:51.619692 TX Bit7 (976~996) 21 986, Bit15 (970~992) 23 981,
1882 13:43:51.619797
1883 13:43:51.623212 Write Rank1 MR14 =0x10
1884 13:43:51.632500
1885 13:43:51.635691 CH=0, VrefRange= 0, VrefLevel = 16
1886 13:43:51.638883 TX Bit0 (977~1000) 24 988, Bit8 (966~990) 25 978,
1887 13:43:51.642166 TX Bit1 (976~998) 23 987, Bit9 (967~990) 24 978,
1888 13:43:51.648755 TX Bit2 (976~998) 23 987, Bit10 (973~993) 21 983,
1889 13:43:51.652341 TX Bit3 (970~992) 23 981, Bit11 (967~990) 24 978,
1890 13:43:51.655487 TX Bit4 (976~999) 24 987, Bit12 (967~990) 24 978,
1891 13:43:51.662428 TX Bit5 (971~993) 23 982, Bit13 (967~989) 23 978,
1892 13:43:51.665809 TX Bit6 (972~995) 24 983, Bit14 (967~990) 24 978,
1893 13:43:51.669082 TX Bit7 (975~997) 23 986, Bit15 (969~992) 24 980,
1894 13:43:51.669198
1895 13:43:51.672163 Write Rank1 MR14 =0x12
1896 13:43:51.681930
1897 13:43:51.684985 CH=0, VrefRange= 0, VrefLevel = 18
1898 13:43:51.688450 TX Bit0 (976~1000) 25 988, Bit8 (966~990) 25 978,
1899 13:43:51.691837 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
1900 13:43:51.698260 TX Bit2 (976~999) 24 987, Bit10 (973~993) 21 983,
1901 13:43:51.701659 TX Bit3 (970~992) 23 981, Bit11 (966~990) 25 978,
1902 13:43:51.704800 TX Bit4 (975~999) 25 987, Bit12 (967~990) 24 978,
1903 13:43:51.711762 TX Bit5 (971~994) 24 982, Bit13 (967~990) 24 978,
1904 13:43:51.715328 TX Bit6 (972~996) 25 984, Bit14 (967~990) 24 978,
1905 13:43:51.718409 TX Bit7 (975~997) 23 986, Bit15 (969~992) 24 980,
1906 13:43:51.718496
1907 13:43:51.721670 Write Rank1 MR14 =0x14
1908 13:43:51.731050
1909 13:43:51.734405 CH=0, VrefRange= 0, VrefLevel = 20
1910 13:43:51.737670 TX Bit0 (977~1001) 25 989, Bit8 (966~990) 25 978,
1911 13:43:51.741045 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
1912 13:43:51.747826 TX Bit2 (976~999) 24 987, Bit10 (972~994) 23 983,
1913 13:43:51.751089 TX Bit3 (969~993) 25 981, Bit11 (967~990) 24 978,
1914 13:43:51.754686 TX Bit4 (975~1000) 26 987, Bit12 (967~991) 25 979,
1915 13:43:51.761421 TX Bit5 (970~994) 25 982, Bit13 (967~990) 24 978,
1916 13:43:51.764743 TX Bit6 (971~996) 26 983, Bit14 (967~991) 25 979,
1917 13:43:51.767919 TX Bit7 (975~997) 23 986, Bit15 (968~993) 26 980,
1918 13:43:51.768051
1919 13:43:51.771626 Write Rank1 MR14 =0x16
1920 13:43:51.780794
1921 13:43:51.784161 CH=0, VrefRange= 0, VrefLevel = 22
1922 13:43:51.787449 TX Bit0 (976~1001) 26 988, Bit8 (966~990) 25 978,
1923 13:43:51.791064 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
1924 13:43:51.797214 TX Bit2 (976~999) 24 987, Bit10 (972~994) 23 983,
1925 13:43:51.800912 TX Bit3 (969~993) 25 981, Bit11 (966~990) 25 978,
1926 13:43:51.804074 TX Bit4 (976~1000) 25 988, Bit12 (967~991) 25 979,
1927 13:43:51.810774 TX Bit5 (970~994) 25 982, Bit13 (967~990) 24 978,
1928 13:43:51.814249 TX Bit6 (971~996) 26 983, Bit14 (967~991) 25 979,
1929 13:43:51.817571 TX Bit7 (975~998) 24 986, Bit15 (968~992) 25 980,
1930 13:43:51.817657
1931 13:43:51.820694 Write Rank1 MR14 =0x18
1932 13:43:51.830300
1933 13:43:51.833580 CH=0, VrefRange= 0, VrefLevel = 24
1934 13:43:51.836854 TX Bit0 (976~1001) 26 988, Bit8 (966~990) 25 978,
1935 13:43:51.840327 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
1936 13:43:51.847018 TX Bit2 (976~999) 24 987, Bit10 (972~995) 24 983,
1937 13:43:51.850330 TX Bit3 (969~994) 26 981, Bit11 (966~990) 25 978,
1938 13:43:51.853848 TX Bit4 (976~1000) 25 988, Bit12 (967~991) 25 979,
1939 13:43:51.860514 TX Bit5 (970~994) 25 982, Bit13 (967~990) 24 978,
1940 13:43:51.863714 TX Bit6 (971~995) 25 983, Bit14 (967~990) 24 978,
1941 13:43:51.866981 TX Bit7 (974~998) 25 986, Bit15 (969~992) 24 980,
1942 13:43:51.867075
1943 13:43:51.870440 Write Rank1 MR14 =0x1a
1944 13:43:51.880046
1945 13:43:51.880266 CH=0, VrefRange= 0, VrefLevel = 26
1946 13:43:51.886791 TX Bit0 (976~1001) 26 988, Bit8 (966~990) 25 978,
1947 13:43:51.890130 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
1948 13:43:51.896688 TX Bit2 (976~999) 24 987, Bit10 (972~995) 24 983,
1949 13:43:51.899917 TX Bit3 (969~994) 26 981, Bit11 (966~990) 25 978,
1950 13:43:51.903219 TX Bit4 (976~1000) 25 988, Bit12 (967~991) 25 979,
1951 13:43:51.910169 TX Bit5 (970~994) 25 982, Bit13 (967~990) 24 978,
1952 13:43:51.913648 TX Bit6 (971~995) 25 983, Bit14 (967~990) 24 978,
1953 13:43:51.916798 TX Bit7 (974~998) 25 986, Bit15 (969~992) 24 980,
1954 13:43:51.916885
1955 13:43:51.920177 Write Rank1 MR14 =0x1c
1956 13:43:51.929321
1957 13:43:51.929548 CH=0, VrefRange= 0, VrefLevel = 28
1958 13:43:51.935873 TX Bit0 (976~1001) 26 988, Bit8 (966~990) 25 978,
1959 13:43:51.939435 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
1960 13:43:51.946321 TX Bit2 (976~999) 24 987, Bit10 (972~995) 24 983,
1961 13:43:51.949502 TX Bit3 (969~994) 26 981, Bit11 (966~990) 25 978,
1962 13:43:51.952711 TX Bit4 (976~1000) 25 988, Bit12 (967~991) 25 979,
1963 13:43:51.959627 TX Bit5 (970~994) 25 982, Bit13 (967~990) 24 978,
1964 13:43:51.962697 TX Bit6 (971~995) 25 983, Bit14 (967~990) 24 978,
1965 13:43:51.966056 TX Bit7 (974~998) 25 986, Bit15 (969~992) 24 980,
1966 13:43:51.966178
1967 13:43:51.969576 Write Rank1 MR14 =0x1e
1968 13:43:51.978759
1969 13:43:51.982256 CH=0, VrefRange= 0, VrefLevel = 30
1970 13:43:51.985524 TX Bit0 (976~1001) 26 988, Bit8 (966~990) 25 978,
1971 13:43:51.988723 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
1972 13:43:51.995572 TX Bit2 (976~999) 24 987, Bit10 (972~995) 24 983,
1973 13:43:51.999206 TX Bit3 (969~994) 26 981, Bit11 (966~990) 25 978,
1974 13:43:52.002644 TX Bit4 (976~1000) 25 988, Bit12 (967~991) 25 979,
1975 13:43:52.009333 TX Bit5 (970~994) 25 982, Bit13 (967~990) 24 978,
1976 13:43:52.012532 TX Bit6 (971~995) 25 983, Bit14 (967~990) 24 978,
1977 13:43:52.015928 TX Bit7 (974~998) 25 986, Bit15 (969~992) 24 980,
1978 13:43:52.016033
1979 13:43:52.019302 Write Rank1 MR14 =0x20
1980 13:43:52.028523
1981 13:43:52.028660 CH=0, VrefRange= 0, VrefLevel = 32
1982 13:43:52.034868 TX Bit0 (976~1001) 26 988, Bit8 (966~990) 25 978,
1983 13:43:52.038301 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
1984 13:43:52.045309 TX Bit2 (976~999) 24 987, Bit10 (972~995) 24 983,
1985 13:43:52.048254 TX Bit3 (969~994) 26 981, Bit11 (966~990) 25 978,
1986 13:43:52.051647 TX Bit4 (976~1000) 25 988, Bit12 (967~991) 25 979,
1987 13:43:52.058468 TX Bit5 (970~994) 25 982, Bit13 (967~990) 24 978,
1988 13:43:52.061782 TX Bit6 (971~995) 25 983, Bit14 (967~990) 24 978,
1989 13:43:52.065146 TX Bit7 (974~998) 25 986, Bit15 (969~992) 24 980,
1990 13:43:52.065298
1991 13:43:52.065360
1992 13:43:52.068417 TX Vref found, early break! 364< 375
1993 13:43:52.075250 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =762/100 ps
1994 13:43:52.078808 u1DelayCellOfst[0]=8 cells (7 PI)
1995 13:43:52.081869 u1DelayCellOfst[1]=7 cells (6 PI)
1996 13:43:52.085519 u1DelayCellOfst[2]=7 cells (6 PI)
1997 13:43:52.085619 u1DelayCellOfst[3]=0 cells (0 PI)
1998 13:43:52.089018 u1DelayCellOfst[4]=8 cells (7 PI)
1999 13:43:52.092181 u1DelayCellOfst[5]=1 cells (1 PI)
2000 13:43:52.095537 u1DelayCellOfst[6]=2 cells (2 PI)
2001 13:43:52.098775 u1DelayCellOfst[7]=6 cells (5 PI)
2002 13:43:52.102232 Byte0, DQ PI dly=981, DQM PI dly= 984
2003 13:43:52.105548 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
2004 13:43:52.105641
2005 13:43:52.112211 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
2006 13:43:52.112360
2007 13:43:52.115750 u1DelayCellOfst[8]=0 cells (0 PI)
2008 13:43:52.115841 u1DelayCellOfst[9]=0 cells (0 PI)
2009 13:43:52.119104 u1DelayCellOfst[10]=6 cells (5 PI)
2010 13:43:52.122267 u1DelayCellOfst[11]=0 cells (0 PI)
2011 13:43:52.125945 u1DelayCellOfst[12]=1 cells (1 PI)
2012 13:43:52.129198 u1DelayCellOfst[13]=0 cells (0 PI)
2013 13:43:52.132509 u1DelayCellOfst[14]=0 cells (0 PI)
2014 13:43:52.135968 u1DelayCellOfst[15]=2 cells (2 PI)
2015 13:43:52.139282 Byte1, DQ PI dly=978, DQM PI dly= 980
2016 13:43:52.142888 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
2017 13:43:52.143004
2018 13:43:52.149416 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
2019 13:43:52.149519
2020 13:43:52.149580 Write Rank1 MR14 =0x18
2021 13:43:52.149635
2022 13:43:52.152745 Final TX Range 0 Vref 24
2023 13:43:52.152831
2024 13:43:52.159283 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2025 13:43:52.159382
2026 13:43:52.166358 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2027 13:43:52.172742 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2028 13:43:52.179506 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2029 13:43:52.183041 Write Rank1 MR3 =0xb0
2030 13:43:52.183150 DramC Write-DBI on
2031 13:43:52.183224 ==
2032 13:43:52.189674 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2033 13:43:52.193162 fsp= 1, odt_onoff= 1, Byte mode= 0
2034 13:43:52.193318 ==
2035 13:43:52.196442 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2036 13:43:52.196551
2037 13:43:52.200246 Begin, DQ Scan Range 700~764
2038 13:43:52.200339
2039 13:43:52.200421
2040 13:43:52.203060 TX Vref Scan disable
2041 13:43:52.206517 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2042 13:43:52.210240 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2043 13:43:52.213198 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2044 13:43:52.216638 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2045 13:43:52.220131 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2046 13:43:52.223317 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2047 13:43:52.227345 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2048 13:43:52.230324 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2049 13:43:52.233580 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2050 13:43:52.237109 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
2051 13:43:52.240400 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
2052 13:43:52.243148 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
2053 13:43:52.246846 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2054 13:43:52.250256 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2055 13:43:52.253430 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2056 13:43:52.256851 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2057 13:43:52.265581 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
2058 13:43:52.268709 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2059 13:43:52.272313 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2060 13:43:52.275917 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2061 13:43:52.279066 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2062 13:43:52.282565 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2063 13:43:52.285568 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2064 13:43:52.288994 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2065 13:43:52.292283 743 |2 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
2066 13:43:52.295948 Byte0, DQ PI dly=729, DQM PI dly= 729
2067 13:43:52.299137 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 25)
2068 13:43:52.299229
2069 13:43:52.306118 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 25)
2070 13:43:52.306235
2071 13:43:52.309108 Byte1, DQ PI dly=721, DQM PI dly= 721
2072 13:43:52.312810 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 17)
2073 13:43:52.312895
2074 13:43:52.315946 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 17)
2075 13:43:52.316034
2076 13:43:52.322756 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2077 13:43:52.329597 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2078 13:43:52.337597 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2079 13:43:52.337711 Write Rank1 MR3 =0x30
2080 13:43:52.341011 DramC Write-DBI off
2081 13:43:52.341101
2082 13:43:52.341161 [DATLAT]
2083 13:43:52.344225 Freq=1600, CH0 RK1, use_rxtx_scan=0
2084 13:43:52.344311
2085 13:43:52.347741 DATLAT Default: 0x10
2086 13:43:52.347823 7, 0xFFFF, sum=0
2087 13:43:52.351263 8, 0xFFFF, sum=0
2088 13:43:52.351354 9, 0xFFFF, sum=0
2089 13:43:52.355105 10, 0xFFFF, sum=0
2090 13:43:52.355198 11, 0xFFFF, sum=0
2091 13:43:52.357633 12, 0xFFFF, sum=0
2092 13:43:52.357716 13, 0xFFFF, sum=0
2093 13:43:52.361170 14, 0x0, sum=1
2094 13:43:52.361314 15, 0x0, sum=2
2095 13:43:52.361377 16, 0x0, sum=3
2096 13:43:52.364841 17, 0x0, sum=4
2097 13:43:52.367938 pattern=2 first_step=14 total pass=5 best_step=16
2098 13:43:52.368024 ==
2099 13:43:52.374386 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2100 13:43:52.377821 fsp= 1, odt_onoff= 1, Byte mode= 0
2101 13:43:52.377916 ==
2102 13:43:52.381177 Start DQ dly to find pass range UseTestEngine =1
2103 13:43:52.384554 x-axis: bit #, y-axis: DQ dly (-127~63)
2104 13:43:52.387844 RX Vref Scan = 0
2105 13:43:52.387938 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2106 13:43:52.391078 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2107 13:43:52.394616 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2108 13:43:52.398147 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2109 13:43:52.401193 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2110 13:43:52.404755 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2111 13:43:52.408017 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2112 13:43:52.411421 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2113 13:43:52.411511 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2114 13:43:52.414711 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2115 13:43:52.418916 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2116 13:43:52.423954 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2117 13:43:52.424071 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2118 13:43:52.427646 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2119 13:43:52.431733 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2120 13:43:52.431833 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2121 13:43:52.435622 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2122 13:43:52.439408 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2123 13:43:52.442614 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2124 13:43:52.445937 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2125 13:43:52.449719 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2126 13:43:52.449838 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2127 13:43:52.453044 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2128 13:43:52.456007 -3, [0] xxxoxxxx xxxxxxxx [MSB]
2129 13:43:52.459606 -2, [0] xxxoxxxx xxxxxxxx [MSB]
2130 13:43:52.463059 -1, [0] xxxoxoxx xxxxxxxx [MSB]
2131 13:43:52.466328 0, [0] xxxoxoxx oxxoxxxx [MSB]
2132 13:43:52.466418 1, [0] xxxoxoxx oxxoxxxx [MSB]
2133 13:43:52.469710 2, [0] xxxoxoox oxxoxoox [MSB]
2134 13:43:52.472721 3, [0] xxxoxooo ooxooooo [MSB]
2135 13:43:52.476253 4, [0] xxxoxooo ooxooooo [MSB]
2136 13:43:52.479504 5, [0] xxxoxooo ooxooooo [MSB]
2137 13:43:52.482939 6, [0] xoxoxooo oooooooo [MSB]
2138 13:43:52.483108 7, [0] ooxooooo oooooooo [MSB]
2139 13:43:52.488065 32, [0] oooxoooo oooooooo [MSB]
2140 13:43:52.491242 33, [0] oooxoooo oooooooo [MSB]
2141 13:43:52.494360 34, [0] oooxoxoo oooooxoo [MSB]
2142 13:43:52.497622 35, [0] oooxoxxx oooxoxxo [MSB]
2143 13:43:52.501912 36, [0] oooxoxxx xooxoxxo [MSB]
2144 13:43:52.502044 37, [0] oooxoxxx xxoxxxxo [MSB]
2145 13:43:52.505167 38, [0] oooxoxxx xxoxxxxx [MSB]
2146 13:43:52.508609 39, [0] oooxoxxx xxoxxxxx [MSB]
2147 13:43:52.511593 40, [0] ooxxoxxx xxxxxxxx [MSB]
2148 13:43:52.514959 41, [0] oxxxxxxx xxxxxxxx [MSB]
2149 13:43:52.518290 42, [0] xxxxxxxx xxxxxxxx [MSB]
2150 13:43:52.521766 iDelay=42, Bit 0, Center 24 (7 ~ 41) 35
2151 13:43:52.525159 iDelay=42, Bit 1, Center 23 (6 ~ 40) 35
2152 13:43:52.528584 iDelay=42, Bit 2, Center 23 (8 ~ 39) 32
2153 13:43:52.531823 iDelay=42, Bit 3, Center 14 (-3 ~ 31) 35
2154 13:43:52.535245 iDelay=42, Bit 4, Center 23 (7 ~ 40) 34
2155 13:43:52.538434 iDelay=42, Bit 5, Center 16 (-1 ~ 33) 35
2156 13:43:52.541801 iDelay=42, Bit 6, Center 18 (2 ~ 34) 33
2157 13:43:52.545416 iDelay=42, Bit 7, Center 18 (3 ~ 34) 32
2158 13:43:52.548773 iDelay=42, Bit 8, Center 17 (0 ~ 35) 36
2159 13:43:52.551836 iDelay=42, Bit 9, Center 19 (3 ~ 36) 34
2160 13:43:52.555599 iDelay=42, Bit 10, Center 22 (6 ~ 39) 34
2161 13:43:52.559249 iDelay=42, Bit 11, Center 17 (0 ~ 34) 35
2162 13:43:52.562215 iDelay=42, Bit 12, Center 19 (3 ~ 36) 34
2163 13:43:52.565398 iDelay=42, Bit 13, Center 17 (2 ~ 33) 32
2164 13:43:52.572264 iDelay=42, Bit 14, Center 18 (2 ~ 34) 33
2165 13:43:52.575692 iDelay=42, Bit 15, Center 20 (3 ~ 37) 35
2166 13:43:52.575807 ==
2167 13:43:52.578937 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2168 13:43:52.582734 fsp= 1, odt_onoff= 1, Byte mode= 0
2169 13:43:52.582838 ==
2170 13:43:52.585826 DQS Delay:
2171 13:43:52.585909 DQS0 = 0, DQS1 = 0
2172 13:43:52.585978 DQM Delay:
2173 13:43:52.589094 DQM0 = 19, DQM1 = 18
2174 13:43:52.589197 DQ Delay:
2175 13:43:52.592448 DQ0 =24, DQ1 =23, DQ2 =23, DQ3 =14
2176 13:43:52.595786 DQ4 =23, DQ5 =16, DQ6 =18, DQ7 =18
2177 13:43:52.599150 DQ8 =17, DQ9 =19, DQ10 =22, DQ11 =17
2178 13:43:52.602488 DQ12 =19, DQ13 =17, DQ14 =18, DQ15 =20
2179 13:43:52.602594
2180 13:43:52.602683
2181 13:43:52.602767
2182 13:43:52.605815 [DramC_TX_OE_Calibration] TA2
2183 13:43:52.609663 Original DQ_B0 (3 6) =30, OEN = 27
2184 13:43:52.612544 Original DQ_B1 (3 6) =30, OEN = 27
2185 13:43:52.615833 23, 0x0, End_B0=23 End_B1=23
2186 13:43:52.615936 24, 0x0, End_B0=24 End_B1=24
2187 13:43:52.619294 25, 0x0, End_B0=25 End_B1=25
2188 13:43:52.622589 26, 0x0, End_B0=26 End_B1=26
2189 13:43:52.625961 27, 0x0, End_B0=27 End_B1=27
2190 13:43:52.626064 28, 0x0, End_B0=28 End_B1=28
2191 13:43:52.629477 29, 0x0, End_B0=29 End_B1=29
2192 13:43:52.632750 30, 0x0, End_B0=30 End_B1=30
2193 13:43:52.636375 31, 0xFFFF, End_B0=30 End_B1=30
2194 13:43:52.642946 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2195 13:43:52.646300 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2196 13:43:52.646389
2197 13:43:52.646469
2198 13:43:52.649734 Write Rank1 MR23 =0x3f
2199 13:43:52.649816 [DQSOSC]
2200 13:43:52.656190 [DQSOSCAuto] RK1, (LSB)MR18= 0x8d, (MSB)MR19= 0x3, tDQSOscB0 = 346 ps tDQSOscB1 = 0 ps
2201 13:43:52.662898 CH0_RK1: MR19=0x3, MR18=0x8D, DQSOSC=346, MR23=63, INC=20, DEC=30
2202 13:43:52.666057 Write Rank1 MR23 =0x3f
2203 13:43:52.666148 [DQSOSC]
2204 13:43:52.672804 [DQSOSCAuto] RK1, (LSB)MR18= 0x8b, (MSB)MR19= 0x3, tDQSOscB0 = 347 ps tDQSOscB1 = 0 ps
2205 13:43:52.676240 CH0 RK1: MR19=3, MR18=8B
2206 13:43:52.679395 [RxdqsGatingPostProcess] freq 1600
2207 13:43:52.686251 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2208 13:43:52.686356 Rank: 0
2209 13:43:52.689724 best DQS0 dly(2T, 0.5T) = (2, 5)
2210 13:43:52.693117 best DQS1 dly(2T, 0.5T) = (2, 5)
2211 13:43:52.693218 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
2212 13:43:52.696508 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
2213 13:43:52.699555 Rank: 1
2214 13:43:52.702939 best DQS0 dly(2T, 0.5T) = (2, 6)
2215 13:43:52.703024 best DQS1 dly(2T, 0.5T) = (2, 6)
2216 13:43:52.706458 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2217 13:43:52.709774 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2218 13:43:52.716466 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2219 13:43:52.719975 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2220 13:43:52.723604 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2221 13:43:52.726569 Write Rank0 MR13 =0x59
2222 13:43:52.726654 ==
2223 13:43:52.729605 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2224 13:43:52.733219 fsp= 1, odt_onoff= 1, Byte mode= 0
2225 13:43:52.733328 ==
2226 13:43:52.737206 === u2Vref_new: 0x56 --> 0x3a
2227 13:43:52.740053 === u2Vref_new: 0x58 --> 0x58
2228 13:43:52.743117 === u2Vref_new: 0x5a --> 0x5a
2229 13:43:52.746633 === u2Vref_new: 0x5c --> 0x78
2230 13:43:52.749831 === u2Vref_new: 0x5e --> 0x7a
2231 13:43:52.753253 === u2Vref_new: 0x60 --> 0x90
2232 13:43:52.757109 [CA 0] Center 36 (10~63) winsize 54
2233 13:43:52.759826 [CA 1] Center 36 (9~63) winsize 55
2234 13:43:52.763142 [CA 2] Center 33 (4~63) winsize 60
2235 13:43:52.767095 [CA 3] Center 33 (4~63) winsize 60
2236 13:43:52.770145 [CA 4] Center 34 (6~63) winsize 58
2237 13:43:52.770236 [CA 5] Center 28 (0~56) winsize 57
2238 13:43:52.773402
2239 13:43:52.777027 [CATrainingPosCal] consider 1 rank data
2240 13:43:52.777128 u2DelayCellTimex100 = 762/100 ps
2241 13:43:52.783502 CA0 delay=36 (10~63),Diff = 8 PI (10 cell)
2242 13:43:52.786934 CA1 delay=36 (9~63),Diff = 8 PI (10 cell)
2243 13:43:52.790418 CA2 delay=33 (4~63),Diff = 5 PI (6 cell)
2244 13:43:52.793713 CA3 delay=33 (4~63),Diff = 5 PI (6 cell)
2245 13:43:52.797166 CA4 delay=34 (6~63),Diff = 6 PI (7 cell)
2246 13:43:52.800333 CA5 delay=28 (0~56),Diff = 0 PI (0 cell)
2247 13:43:52.800425
2248 13:43:52.803940 CA PerBit enable=1, Macro0, CA PI delay=28
2249 13:43:52.807075 === u2Vref_new: 0x58 --> 0x58
2250 13:43:52.807171
2251 13:43:52.810703 Vref(ca) range 1: 24
2252 13:43:52.810772
2253 13:43:52.810826 CS Dly= 13 (44-0-32)
2254 13:43:52.813929 Write Rank0 MR13 =0xd8
2255 13:43:52.814007 Write Rank0 MR13 =0xd8
2256 13:43:52.817523 Write Rank0 MR12 =0x58
2257 13:43:52.820551 Write Rank1 MR13 =0x59
2258 13:43:52.820630 ==
2259 13:43:52.823949 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2260 13:43:52.827322 fsp= 1, odt_onoff= 1, Byte mode= 0
2261 13:43:52.827420 ==
2262 13:43:52.830570 === u2Vref_new: 0x56 --> 0x3a
2263 13:43:52.834061 === u2Vref_new: 0x58 --> 0x58
2264 13:43:52.837398 === u2Vref_new: 0x5a --> 0x5a
2265 13:43:52.841036 === u2Vref_new: 0x5c --> 0x78
2266 13:43:52.844373 === u2Vref_new: 0x5e --> 0x7a
2267 13:43:52.847488 === u2Vref_new: 0x60 --> 0x90
2268 13:43:52.847600
2269 13:43:52.850831 CBT Vref found, early break!
2270 13:43:52.850982 [CA 0] Center 37 (11~63) winsize 53
2271 13:43:52.854306 [CA 1] Center 35 (8~63) winsize 56
2272 13:43:52.857580 [CA 2] Center 33 (4~63) winsize 60
2273 13:43:52.860899 [CA 3] Center 33 (4~63) winsize 60
2274 13:43:52.864479 [CA 4] Center 35 (7~63) winsize 57
2275 13:43:52.867434 [CA 5] Center 27 (-1~56) winsize 58
2276 13:43:52.867538
2277 13:43:52.870836 [CATrainingPosCal] consider 2 rank data
2278 13:43:52.873969 u2DelayCellTimex100 = 762/100 ps
2279 13:43:52.877363 CA0 delay=37 (11~63),Diff = 9 PI (11 cell)
2280 13:43:52.880675 CA1 delay=36 (9~63),Diff = 8 PI (10 cell)
2281 13:43:52.887532 CA2 delay=33 (4~63),Diff = 5 PI (6 cell)
2282 13:43:52.890799 CA3 delay=33 (4~63),Diff = 5 PI (6 cell)
2283 13:43:52.894136 CA4 delay=35 (7~63),Diff = 7 PI (8 cell)
2284 13:43:52.897562 CA5 delay=28 (0~56),Diff = 0 PI (0 cell)
2285 13:43:52.897678
2286 13:43:52.901087 CA PerBit enable=1, Macro0, CA PI delay=28
2287 13:43:52.904179 === u2Vref_new: 0x56 --> 0x3a
2288 13:43:52.904284
2289 13:43:52.904375 Vref(ca) range 1: 22
2290 13:43:52.904457
2291 13:43:52.907717 CS Dly= 12 (43-0-32)
2292 13:43:52.910840 Write Rank1 MR13 =0xd8
2293 13:43:52.910955 Write Rank1 MR13 =0xd8
2294 13:43:52.914283 Write Rank1 MR12 =0x56
2295 13:43:52.917964 [RankSwap] Rank num 2, (Multi 1), Rank 0
2296 13:43:52.918057 Write Rank0 MR2 =0xad
2297 13:43:52.921052 [Write Leveling]
2298 13:43:52.924509 delay byte0 byte1 byte2 byte3
2299 13:43:52.924597
2300 13:43:52.924657 10 0 0
2301 13:43:52.927879 11 0 0
2302 13:43:52.927984 12 0 0
2303 13:43:52.931207 13 0 0
2304 13:43:52.931318 14 0 0
2305 13:43:52.931427 15 0 0
2306 13:43:52.934556 16 0 0
2307 13:43:52.934671 17 0 0
2308 13:43:52.938067 18 0 0
2309 13:43:52.938196 19 0 0
2310 13:43:52.938289 20 0 0
2311 13:43:52.941513 21 0 0
2312 13:43:52.941745 22 0 0
2313 13:43:52.944879 23 0 0
2314 13:43:52.944990 24 0 0
2315 13:43:52.945079 25 0 0
2316 13:43:52.948055 26 0 0
2317 13:43:52.948165 27 0 0
2318 13:43:52.951473 28 0 0
2319 13:43:52.951606 29 0 0
2320 13:43:52.951730 30 0 0
2321 13:43:52.954848 31 0 0
2322 13:43:52.954947 32 0 0
2323 13:43:52.958128 33 0 ff
2324 13:43:52.958237 34 0 ff
2325 13:43:52.961472 35 0 ff
2326 13:43:52.961570 36 0 ff
2327 13:43:52.961658 37 0 ff
2328 13:43:52.964893 38 ff ff
2329 13:43:52.964994 39 ff ff
2330 13:43:52.968142 40 ff ff
2331 13:43:52.968243 41 ff ff
2332 13:43:52.971728 42 ff ff
2333 13:43:52.971830 43 ff ff
2334 13:43:52.975059 44 ff ff
2335 13:43:52.978100 pass bytecount = 0xff (0xff: all bytes pass)
2336 13:43:52.978202
2337 13:43:52.978298 DQS0 dly: 38
2338 13:43:52.981583 DQS1 dly: 33
2339 13:43:52.981691 Write Rank0 MR2 =0x2d
2340 13:43:52.985711 [RankSwap] Rank num 2, (Multi 1), Rank 0
2341 13:43:52.988287 Write Rank0 MR1 =0xd6
2342 13:43:52.988382 [Gating]
2343 13:43:52.988460 ==
2344 13:43:52.995227 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2345 13:43:52.998606 fsp= 1, odt_onoff= 1, Byte mode= 0
2346 13:43:52.998714 ==
2347 13:43:53.001628 3 1 0 |3534 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
2348 13:43:53.005484 3 1 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2349 13:43:53.011845 3 1 8 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2350 13:43:53.015208 3 1 12 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2351 13:43:53.018656 3 1 16 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2352 13:43:53.025150 3 1 20 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2353 13:43:53.028838 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2354 13:43:53.032220 3 1 28 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2355 13:43:53.035171 3 2 0 |707 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2356 13:43:53.042189 3 2 4 |3d3d 201 |(11 11)(11 11) |(1 1)(0 0)| 0
2357 13:43:53.045630 3 2 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2358 13:43:53.048984 3 2 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2359 13:43:53.055682 3 2 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2360 13:43:53.058930 3 2 20 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2361 13:43:53.062192 3 2 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2362 13:43:53.069050 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2363 13:43:53.072653 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2364 13:43:53.075733 3 3 4 |0 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2365 13:43:53.078988 3 3 8 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2366 13:43:53.082463 [Byte 0] Lead/lag Transition tap number (1)
2367 13:43:53.088999 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2368 13:43:53.092470 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2369 13:43:53.095921 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2370 13:43:53.102997 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2371 13:43:53.106017 3 3 28 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2372 13:43:53.109639 3 4 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2373 13:43:53.112812 3 4 4 |3d3d 505 |(11 11)(11 11) |(1 1)(1 1)| 0
2374 13:43:53.119330 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2375 13:43:53.122719 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2376 13:43:53.126024 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2377 13:43:53.132647 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2378 13:43:53.136094 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2379 13:43:53.139092 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2380 13:43:53.145890 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2381 13:43:53.149476 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2382 13:43:53.152756 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2383 13:43:53.159113 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2384 13:43:53.162446 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2385 13:43:53.165885 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2386 13:43:53.172538 [Byte 0] Lead/lag falling Transition (3, 5, 20)
2387 13:43:53.175974 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2388 13:43:53.179661 [Byte 0] Lead/lag Transition tap number (2)
2389 13:43:53.182850 [Byte 1] Lead/lag falling Transition (3, 5, 24)
2390 13:43:53.189396 3 5 28 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2391 13:43:53.192828 3 6 0 |606 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2392 13:43:53.195963 [Byte 1] Lead/lag Transition tap number (3)
2393 13:43:53.199364 3 6 4 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
2394 13:43:53.202786 [Byte 0]First pass (3, 6, 4)
2395 13:43:53.205726 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2396 13:43:53.209013 [Byte 1]First pass (3, 6, 8)
2397 13:43:53.212624 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2398 13:43:53.216156 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2399 13:43:53.222562 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2400 13:43:53.225903 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2401 13:43:53.229140 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2402 13:43:53.232294 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2403 13:43:53.235713 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2404 13:43:53.242461 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2405 13:43:53.245647 All bytes gating window > 1UI, Early break!
2406 13:43:53.245761
2407 13:43:53.249482 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 24)
2408 13:43:53.249579
2409 13:43:53.252935 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 30)
2410 13:43:53.253053
2411 13:43:53.253138
2412 13:43:53.253211
2413 13:43:53.255719 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 24)
2414 13:43:53.255814
2415 13:43:53.262433 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 30)
2416 13:43:53.262562
2417 13:43:53.262652
2418 13:43:53.262726 Write Rank0 MR1 =0x56
2419 13:43:53.262802
2420 13:43:53.265932 best RODT dly(2T, 0.5T) = (2, 2)
2421 13:43:53.266027
2422 13:43:53.269110 best RODT dly(2T, 0.5T) = (2, 2)
2423 13:43:53.269218 ==
2424 13:43:53.275779 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2425 13:43:53.279163 fsp= 1, odt_onoff= 1, Byte mode= 0
2426 13:43:53.279286 ==
2427 13:43:53.282381 Start DQ dly to find pass range UseTestEngine =0
2428 13:43:53.285937 x-axis: bit #, y-axis: DQ dly (-127~63)
2429 13:43:53.289317 RX Vref Scan = 0
2430 13:43:53.292538 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2431 13:43:53.292644 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2432 13:43:53.296002 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2433 13:43:53.299113 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2434 13:43:53.302438 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2435 13:43:53.305795 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2436 13:43:53.309359 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2437 13:43:53.312829 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2438 13:43:53.315579 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2439 13:43:53.315693 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2440 13:43:53.319136 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2441 13:43:53.322370 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2442 13:43:53.325716 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2443 13:43:53.329152 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2444 13:43:53.332469 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2445 13:43:53.336044 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2446 13:43:53.339178 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2447 13:43:53.339280 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2448 13:43:53.342227 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2449 13:43:53.345577 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2450 13:43:53.349169 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2451 13:43:53.352550 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2452 13:43:53.355653 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2453 13:43:53.359020 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2454 13:43:53.359141 -2, [0] xxxxxxxx xxxxxxxo [MSB]
2455 13:43:53.362361 -1, [0] xxxxxxxx xxxxxxxo [MSB]
2456 13:43:53.365767 0, [0] xxxoxxxx xxxxxxxo [MSB]
2457 13:43:53.369082 1, [0] xxxoxxxx xxxxxxxo [MSB]
2458 13:43:53.372345 2, [0] xxxoxxxx xxxxxxxo [MSB]
2459 13:43:53.375726 3, [0] xxooxxxo oooxxxxo [MSB]
2460 13:43:53.375847 4, [0] xxoooxxo oooxxxxo [MSB]
2461 13:43:53.379091 5, [0] xxoooxxo ooooxooo [MSB]
2462 13:43:53.382851 6, [0] xooooxxo oooooooo [MSB]
2463 13:43:53.385881 31, [0] oooxoooo oooooooo [MSB]
2464 13:43:53.389126 32, [0] ooxxoooo ooooooox [MSB]
2465 13:43:53.392424 33, [0] ooxxoooo oxooooox [MSB]
2466 13:43:53.392540 34, [0] ooxxoooo oxxxooox [MSB]
2467 13:43:53.396051 35, [0] ooxxoooo oxxxooxx [MSB]
2468 13:43:53.399170 36, [0] ooxxxoox xxxxooxx [MSB]
2469 13:43:53.402859 37, [0] ooxxxoox xxxxoxxx [MSB]
2470 13:43:53.405840 38, [0] ooxxxoox xxxxxxxx [MSB]
2471 13:43:53.409446 39, [0] ooxxxoox xxxxxxxx [MSB]
2472 13:43:53.412705 40, [0] ooxxxoox xxxxxxxx [MSB]
2473 13:43:53.412807 41, [0] xxxxxxxx xxxxxxxx [MSB]
2474 13:43:53.416159 iDelay=41, Bit 0, Center 23 (7 ~ 40) 34
2475 13:43:53.422585 iDelay=41, Bit 1, Center 23 (6 ~ 40) 35
2476 13:43:53.426095 iDelay=41, Bit 2, Center 17 (3 ~ 31) 29
2477 13:43:53.429219 iDelay=41, Bit 3, Center 15 (0 ~ 30) 31
2478 13:43:53.432698 iDelay=41, Bit 4, Center 19 (4 ~ 35) 32
2479 13:43:53.435919 iDelay=41, Bit 5, Center 23 (7 ~ 40) 34
2480 13:43:53.439797 iDelay=41, Bit 6, Center 23 (7 ~ 40) 34
2481 13:43:53.442787 iDelay=41, Bit 7, Center 19 (3 ~ 35) 33
2482 13:43:53.446256 iDelay=41, Bit 8, Center 19 (3 ~ 35) 33
2483 13:43:53.449152 iDelay=41, Bit 9, Center 17 (3 ~ 32) 30
2484 13:43:53.452629 iDelay=41, Bit 10, Center 18 (3 ~ 33) 31
2485 13:43:53.456248 iDelay=41, Bit 11, Center 19 (5 ~ 33) 29
2486 13:43:53.459368 iDelay=41, Bit 12, Center 21 (6 ~ 37) 32
2487 13:43:53.462872 iDelay=41, Bit 13, Center 20 (5 ~ 36) 32
2488 13:43:53.466111 iDelay=41, Bit 14, Center 19 (5 ~ 34) 30
2489 13:43:53.469473 iDelay=41, Bit 15, Center 14 (-2 ~ 31) 34
2490 13:43:53.472638 ==
2491 13:43:53.476030 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2492 13:43:53.479549 fsp= 1, odt_onoff= 1, Byte mode= 0
2493 13:43:53.479660 ==
2494 13:43:53.479751 DQS Delay:
2495 13:43:53.482881 DQS0 = 0, DQS1 = 0
2496 13:43:53.482977 DQM Delay:
2497 13:43:53.486073 DQM0 = 20, DQM1 = 18
2498 13:43:53.486179 DQ Delay:
2499 13:43:53.489254 DQ0 =23, DQ1 =23, DQ2 =17, DQ3 =15
2500 13:43:53.492783 DQ4 =19, DQ5 =23, DQ6 =23, DQ7 =19
2501 13:43:53.496065 DQ8 =19, DQ9 =17, DQ10 =18, DQ11 =19
2502 13:43:53.499346 DQ12 =21, DQ13 =20, DQ14 =19, DQ15 =14
2503 13:43:53.499460
2504 13:43:53.499548
2505 13:43:53.502666 DramC Write-DBI off
2506 13:43:53.502763 ==
2507 13:43:53.506618 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2508 13:43:53.509189 fsp= 1, odt_onoff= 1, Byte mode= 0
2509 13:43:53.509320 ==
2510 13:43:53.512788 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2511 13:43:53.516259
2512 13:43:53.516365 Begin, DQ Scan Range 929~1185
2513 13:43:53.516444
2514 13:43:53.516522
2515 13:43:53.519680 TX Vref Scan disable
2516 13:43:53.523011 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2517 13:43:53.525989 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2518 13:43:53.529507 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2519 13:43:53.533019 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2520 13:43:53.536508 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2521 13:43:53.539936 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2522 13:43:53.542754 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2523 13:43:53.546120 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2524 13:43:53.553050 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2525 13:43:53.556004 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2526 13:43:53.559666 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2527 13:43:53.562747 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2528 13:43:53.566265 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2529 13:43:53.569548 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2530 13:43:53.572961 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2531 13:43:53.576415 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2532 13:43:53.579473 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2533 13:43:53.582922 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2534 13:43:53.586376 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2535 13:43:53.590022 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2536 13:43:53.592926 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2537 13:43:53.596221 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2538 13:43:53.599761 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2539 13:43:53.603310 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2540 13:43:53.606581 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2541 13:43:53.609702 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2542 13:43:53.616738 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2543 13:43:53.619835 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2544 13:43:53.623157 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2545 13:43:53.626432 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2546 13:43:53.629960 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2547 13:43:53.633020 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2548 13:43:53.636445 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2549 13:43:53.639757 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2550 13:43:53.643360 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2551 13:43:53.646743 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2552 13:43:53.649780 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2553 13:43:53.653375 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2554 13:43:53.656378 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2555 13:43:53.659869 968 |3 6 8|[0] xxxxxxxx xxxxxxxo [MSB]
2556 13:43:53.663104 969 |3 6 9|[0] xxxxxxxx xxxxxxxo [MSB]
2557 13:43:53.666455 970 |3 6 10|[0] xxxxxxxx oooxxxxo [MSB]
2558 13:43:53.669573 971 |3 6 11|[0] xxxxxxxx ooooxxoo [MSB]
2559 13:43:53.673006 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
2560 13:43:53.676325 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
2561 13:43:53.679882 974 |3 6 14|[0] xxxoxxxx oooooooo [MSB]
2562 13:43:53.686255 975 |3 6 15|[0] xxxoxxxx oooooooo [MSB]
2563 13:43:53.689644 976 |3 6 16|[0] xxoooxxo oooooooo [MSB]
2564 13:43:53.693077 977 |3 6 17|[0] xooooxxo oooooooo [MSB]
2565 13:43:53.696428 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
2566 13:43:53.700076 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
2567 13:43:53.703269 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
2568 13:43:53.709624 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
2569 13:43:53.713130 996 |3 6 36|[0] ooxxoooo xxxxxxxx [MSB]
2570 13:43:53.716523 997 |3 6 37|[0] ooxxoooo xxxxxxxx [MSB]
2571 13:43:53.719833 998 |3 6 38|[0] ooxxoooo xxxxxxxx [MSB]
2572 13:43:53.723003 999 |3 6 39|[0] ooxxxoox xxxxxxxx [MSB]
2573 13:43:53.726325 1000 |3 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
2574 13:43:53.729904 Byte0, DQ PI dly=986, DQM PI dly= 986
2575 13:43:53.733487 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
2576 13:43:53.733582
2577 13:43:53.736522 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
2578 13:43:53.736606
2579 13:43:53.739987 Byte1, DQ PI dly=980, DQM PI dly= 980
2580 13:43:53.746793 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
2581 13:43:53.746912
2582 13:43:53.749799 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
2583 13:43:53.749881
2584 13:43:53.749940 ==
2585 13:43:53.756735 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2586 13:43:53.760578 fsp= 1, odt_onoff= 1, Byte mode= 0
2587 13:43:53.760674 ==
2588 13:43:53.763415 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2589 13:43:53.763520
2590 13:43:53.766732 Begin, DQ Scan Range 956~1020
2591 13:43:53.766818 Write Rank0 MR14 =0x0
2592 13:43:53.776921
2593 13:43:53.777046 CH=1, VrefRange= 0, VrefLevel = 0
2594 13:43:53.783274 TX Bit0 (982~998) 17 990, Bit8 (971~990) 20 980,
2595 13:43:53.786668 TX Bit1 (979~997) 19 988, Bit9 (971~989) 19 980,
2596 13:43:53.793243 TX Bit2 (977~991) 15 984, Bit10 (974~989) 16 981,
2597 13:43:53.796814 TX Bit3 (976~991) 16 983, Bit11 (974~991) 18 982,
2598 13:43:53.800130 TX Bit4 (977~994) 18 985, Bit12 (975~992) 18 983,
2599 13:43:53.806853 TX Bit5 (981~998) 18 989, Bit13 (976~991) 16 983,
2600 13:43:53.810212 TX Bit6 (981~998) 18 989, Bit14 (975~990) 16 982,
2601 13:43:53.813690 TX Bit7 (979~993) 15 986, Bit15 (970~988) 19 979,
2602 13:43:53.813798
2603 13:43:53.816757 Write Rank0 MR14 =0x2
2604 13:43:53.825756
2605 13:43:53.825876 CH=1, VrefRange= 0, VrefLevel = 2
2606 13:43:53.832163 TX Bit0 (982~998) 17 990, Bit8 (971~991) 21 981,
2607 13:43:53.835733 TX Bit1 (979~997) 19 988, Bit9 (971~990) 20 980,
2608 13:43:53.838864 TX Bit2 (977~992) 16 984, Bit10 (973~990) 18 981,
2609 13:43:53.845524 TX Bit3 (976~991) 16 983, Bit11 (974~991) 18 982,
2610 13:43:53.848779 TX Bit4 (977~994) 18 985, Bit12 (975~992) 18 983,
2611 13:43:53.855485 TX Bit5 (980~999) 20 989, Bit13 (975~991) 17 983,
2612 13:43:53.858982 TX Bit6 (981~998) 18 989, Bit14 (974~991) 18 982,
2613 13:43:53.862333 TX Bit7 (979~993) 15 986, Bit15 (970~988) 19 979,
2614 13:43:53.862424
2615 13:43:53.865910 Write Rank0 MR14 =0x4
2616 13:43:53.874451
2617 13:43:53.874567 CH=1, VrefRange= 0, VrefLevel = 4
2618 13:43:53.880764 TX Bit0 (980~999) 20 989, Bit8 (970~991) 22 980,
2619 13:43:53.884275 TX Bit1 (979~998) 20 988, Bit9 (971~991) 21 981,
2620 13:43:53.891085 TX Bit2 (977~992) 16 984, Bit10 (973~991) 19 982,
2621 13:43:53.894240 TX Bit3 (975~991) 17 983, Bit11 (974~991) 18 982,
2622 13:43:53.897505 TX Bit4 (977~995) 19 986, Bit12 (975~992) 18 983,
2623 13:43:53.904254 TX Bit5 (980~999) 20 989, Bit13 (975~992) 18 983,
2624 13:43:53.907689 TX Bit6 (980~999) 20 989, Bit14 (973~991) 19 982,
2625 13:43:53.911237 TX Bit7 (978~994) 17 986, Bit15 (970~988) 19 979,
2626 13:43:53.911344
2627 13:43:53.914202 Write Rank0 MR14 =0x6
2628 13:43:53.922873
2629 13:43:53.923002 CH=1, VrefRange= 0, VrefLevel = 6
2630 13:43:53.930406 TX Bit0 (981~999) 19 990, Bit8 (970~991) 22 980,
2631 13:43:53.932986 TX Bit1 (978~998) 21 988, Bit9 (970~991) 22 980,
2632 13:43:53.939479 TX Bit2 (976~993) 18 984, Bit10 (973~991) 19 982,
2633 13:43:53.942851 TX Bit3 (975~992) 18 983, Bit11 (973~992) 20 982,
2634 13:43:53.946143 TX Bit4 (977~996) 20 986, Bit12 (974~992) 19 983,
2635 13:43:53.953040 TX Bit5 (979~999) 21 989, Bit13 (975~992) 18 983,
2636 13:43:53.956197 TX Bit6 (979~999) 21 989, Bit14 (973~991) 19 982,
2637 13:43:53.959848 TX Bit7 (978~994) 17 986, Bit15 (969~989) 21 979,
2638 13:43:53.959948
2639 13:43:53.962876 Write Rank0 MR14 =0x8
2640 13:43:53.971487
2641 13:43:53.971629 CH=1, VrefRange= 0, VrefLevel = 8
2642 13:43:53.978415 TX Bit0 (980~999) 20 989, Bit8 (970~992) 23 981,
2643 13:43:53.981649 TX Bit1 (977~998) 22 987, Bit9 (970~991) 22 980,
2644 13:43:53.988749 TX Bit2 (976~993) 18 984, Bit10 (971~991) 21 981,
2645 13:43:53.992129 TX Bit3 (975~992) 18 983, Bit11 (972~992) 21 982,
2646 13:43:53.994977 TX Bit4 (977~997) 21 987, Bit12 (973~993) 21 983,
2647 13:43:54.001608 TX Bit5 (979~999) 21 989, Bit13 (974~992) 19 983,
2648 13:43:54.005385 TX Bit6 (979~999) 21 989, Bit14 (972~992) 21 982,
2649 13:43:54.008350 TX Bit7 (977~995) 19 986, Bit15 (969~990) 22 979,
2650 13:43:54.008472
2651 13:43:54.011771 Write Rank0 MR14 =0xa
2652 13:43:54.020652
2653 13:43:54.023890 CH=1, VrefRange= 0, VrefLevel = 10
2654 13:43:54.027181 TX Bit0 (979~999) 21 989, Bit8 (970~992) 23 981,
2655 13:43:54.030392 TX Bit1 (978~998) 21 988, Bit9 (970~991) 22 980,
2656 13:43:54.037192 TX Bit2 (976~994) 19 985, Bit10 (972~992) 21 982,
2657 13:43:54.040736 TX Bit3 (974~993) 20 983, Bit11 (972~992) 21 982,
2658 13:43:54.043867 TX Bit4 (976~997) 22 986, Bit12 (973~993) 21 983,
2659 13:43:54.050730 TX Bit5 (978~999) 22 988, Bit13 (973~992) 20 982,
2660 13:43:54.053758 TX Bit6 (979~999) 21 989, Bit14 (972~992) 21 982,
2661 13:43:54.057652 TX Bit7 (977~996) 20 986, Bit15 (969~990) 22 979,
2662 13:43:54.057817
2663 13:43:54.060666 Write Rank0 MR14 =0xc
2664 13:43:54.069392
2665 13:43:54.072596 CH=1, VrefRange= 0, VrefLevel = 12
2666 13:43:54.075983 TX Bit0 (979~1000) 22 989, Bit8 (970~992) 23 981,
2667 13:43:54.079312 TX Bit1 (977~999) 23 988, Bit9 (970~992) 23 981,
2668 13:43:54.086119 TX Bit2 (976~994) 19 985, Bit10 (971~992) 22 981,
2669 13:43:54.089435 TX Bit3 (974~993) 20 983, Bit11 (971~993) 23 982,
2670 13:43:54.092886 TX Bit4 (976~998) 23 987, Bit12 (972~994) 23 983,
2671 13:43:54.099407 TX Bit5 (978~1000) 23 989, Bit13 (973~992) 20 982,
2672 13:43:54.102984 TX Bit6 (978~1000) 23 989, Bit14 (972~992) 21 982,
2673 13:43:54.106066 TX Bit7 (977~997) 21 987, Bit15 (969~991) 23 980,
2674 13:43:54.106199
2675 13:43:54.109477 Write Rank0 MR14 =0xe
2676 13:43:54.118519
2677 13:43:54.118645 CH=1, VrefRange= 0, VrefLevel = 14
2678 13:43:54.125471 TX Bit0 (979~1000) 22 989, Bit8 (970~992) 23 981,
2679 13:43:54.128613 TX Bit1 (977~999) 23 988, Bit9 (970~992) 23 981,
2680 13:43:54.135277 TX Bit2 (976~995) 20 985, Bit10 (971~992) 22 981,
2681 13:43:54.138607 TX Bit3 (974~994) 21 984, Bit11 (971~993) 23 982,
2682 13:43:54.142072 TX Bit4 (976~998) 23 987, Bit12 (972~994) 23 983,
2683 13:43:54.148794 TX Bit5 (978~1000) 23 989, Bit13 (972~993) 22 982,
2684 13:43:54.151925 TX Bit6 (978~1000) 23 989, Bit14 (971~992) 22 981,
2685 13:43:54.155830 TX Bit7 (977~997) 21 987, Bit15 (968~991) 24 979,
2686 13:43:54.155958
2687 13:43:54.158702 Write Rank0 MR14 =0x10
2688 13:43:54.167952
2689 13:43:54.171422 CH=1, VrefRange= 0, VrefLevel = 16
2690 13:43:54.174778 TX Bit0 (978~1000) 23 989, Bit8 (969~992) 24 980,
2691 13:43:54.177978 TX Bit1 (977~999) 23 988, Bit9 (970~992) 23 981,
2692 13:43:54.184689 TX Bit2 (975~996) 22 985, Bit10 (971~992) 22 981,
2693 13:43:54.187800 TX Bit3 (974~995) 22 984, Bit11 (971~993) 23 982,
2694 13:43:54.191507 TX Bit4 (976~998) 23 987, Bit12 (972~994) 23 983,
2695 13:43:54.197799 TX Bit5 (977~1000) 24 988, Bit13 (971~993) 23 982,
2696 13:43:54.201265 TX Bit6 (978~1000) 23 989, Bit14 (971~992) 22 981,
2697 13:43:54.205077 TX Bit7 (977~998) 22 987, Bit15 (968~991) 24 979,
2698 13:43:54.207979
2699 13:43:54.208068 Write Rank0 MR14 =0x12
2700 13:43:54.217463
2701 13:43:54.220612 CH=1, VrefRange= 0, VrefLevel = 18
2702 13:43:54.224270 TX Bit0 (978~1001) 24 989, Bit8 (969~992) 24 980,
2703 13:43:54.227120 TX Bit1 (977~999) 23 988, Bit9 (970~992) 23 981,
2704 13:43:54.233822 TX Bit2 (975~996) 22 985, Bit10 (970~993) 24 981,
2705 13:43:54.237363 TX Bit3 (973~995) 23 984, Bit11 (971~993) 23 982,
2706 13:43:54.240683 TX Bit4 (976~998) 23 987, Bit12 (971~994) 24 982,
2707 13:43:54.247372 TX Bit5 (977~1000) 24 988, Bit13 (972~993) 22 982,
2708 13:43:54.250661 TX Bit6 (977~1000) 24 988, Bit14 (971~993) 23 982,
2709 13:43:54.257038 TX Bit7 (976~998) 23 987, Bit15 (968~992) 25 980,
2710 13:43:54.257158
2711 13:43:54.257220 Write Rank0 MR14 =0x14
2712 13:43:54.266959
2713 13:43:54.270009 CH=1, VrefRange= 0, VrefLevel = 20
2714 13:43:54.273571 TX Bit0 (977~1001) 25 989, Bit8 (969~992) 24 980,
2715 13:43:54.276939 TX Bit1 (977~999) 23 988, Bit9 (969~992) 24 980,
2716 13:43:54.283907 TX Bit2 (975~997) 23 986, Bit10 (970~993) 24 981,
2717 13:43:54.286713 TX Bit3 (973~996) 24 984, Bit11 (970~994) 25 982,
2718 13:43:54.290360 TX Bit4 (975~999) 25 987, Bit12 (971~995) 25 983,
2719 13:43:54.297044 TX Bit5 (977~1000) 24 988, Bit13 (971~993) 23 982,
2720 13:43:54.300224 TX Bit6 (977~1001) 25 989, Bit14 (970~993) 24 981,
2721 13:43:54.303455 TX Bit7 (976~998) 23 987, Bit15 (968~992) 25 980,
2722 13:43:54.306644
2723 13:43:54.306736 Write Rank0 MR14 =0x16
2724 13:43:54.316560
2725 13:43:54.319517 CH=1, VrefRange= 0, VrefLevel = 22
2726 13:43:54.322885 TX Bit0 (977~1001) 25 989, Bit8 (969~992) 24 980,
2727 13:43:54.326343 TX Bit1 (976~1000) 25 988, Bit9 (969~992) 24 980,
2728 13:43:54.332908 TX Bit2 (975~997) 23 986, Bit10 (970~993) 24 981,
2729 13:43:54.336307 TX Bit3 (973~996) 24 984, Bit11 (970~994) 25 982,
2730 13:43:54.339565 TX Bit4 (976~999) 24 987, Bit12 (971~995) 25 983,
2731 13:43:54.346217 TX Bit5 (977~1000) 24 988, Bit13 (971~994) 24 982,
2732 13:43:54.349985 TX Bit6 (977~1001) 25 989, Bit14 (970~993) 24 981,
2733 13:43:54.352918 TX Bit7 (976~999) 24 987, Bit15 (968~992) 25 980,
2734 13:43:54.356490
2735 13:43:54.356587 Write Rank0 MR14 =0x18
2736 13:43:54.365826
2737 13:43:54.369187 CH=1, VrefRange= 0, VrefLevel = 24
2738 13:43:54.372445 TX Bit0 (977~1001) 25 989, Bit8 (969~992) 24 980,
2739 13:43:54.376012 TX Bit1 (976~1000) 25 988, Bit9 (969~992) 24 980,
2740 13:43:54.382856 TX Bit2 (975~997) 23 986, Bit10 (970~993) 24 981,
2741 13:43:54.385956 TX Bit3 (973~996) 24 984, Bit11 (970~994) 25 982,
2742 13:43:54.389425 TX Bit4 (976~999) 24 987, Bit12 (971~995) 25 983,
2743 13:43:54.396171 TX Bit5 (977~1000) 24 988, Bit13 (971~994) 24 982,
2744 13:43:54.399332 TX Bit6 (977~1001) 25 989, Bit14 (970~993) 24 981,
2745 13:43:54.406255 TX Bit7 (976~999) 24 987, Bit15 (968~992) 25 980,
2746 13:43:54.406391
2747 13:43:54.406488 Write Rank0 MR14 =0x1a
2748 13:43:54.415742
2749 13:43:54.419061 CH=1, VrefRange= 0, VrefLevel = 26
2750 13:43:54.422298 TX Bit0 (977~1001) 25 989, Bit8 (969~992) 24 980,
2751 13:43:54.425741 TX Bit1 (976~1000) 25 988, Bit9 (969~992) 24 980,
2752 13:43:54.432566 TX Bit2 (975~997) 23 986, Bit10 (970~993) 24 981,
2753 13:43:54.435863 TX Bit3 (973~996) 24 984, Bit11 (970~994) 25 982,
2754 13:43:54.439232 TX Bit4 (976~999) 24 987, Bit12 (971~995) 25 983,
2755 13:43:54.445804 TX Bit5 (977~1000) 24 988, Bit13 (971~994) 24 982,
2756 13:43:54.448952 TX Bit6 (977~1001) 25 989, Bit14 (970~993) 24 981,
2757 13:43:54.455568 TX Bit7 (976~999) 24 987, Bit15 (968~992) 25 980,
2758 13:43:54.455674
2759 13:43:54.455736 Write Rank0 MR14 =0x1c
2760 13:43:54.465294
2761 13:43:54.468582 CH=1, VrefRange= 0, VrefLevel = 28
2762 13:43:54.471714 TX Bit0 (977~1001) 25 989, Bit8 (969~992) 24 980,
2763 13:43:54.475215 TX Bit1 (976~1000) 25 988, Bit9 (969~992) 24 980,
2764 13:43:54.481850 TX Bit2 (975~997) 23 986, Bit10 (970~993) 24 981,
2765 13:43:54.485952 TX Bit3 (973~996) 24 984, Bit11 (970~994) 25 982,
2766 13:43:54.488905 TX Bit4 (976~999) 24 987, Bit12 (971~995) 25 983,
2767 13:43:54.495175 TX Bit5 (977~1000) 24 988, Bit13 (971~994) 24 982,
2768 13:43:54.498498 TX Bit6 (977~1001) 25 989, Bit14 (970~993) 24 981,
2769 13:43:54.505055 TX Bit7 (976~999) 24 987, Bit15 (968~992) 25 980,
2770 13:43:54.505162
2771 13:43:54.505222 Write Rank0 MR14 =0x1e
2772 13:43:54.515090
2773 13:43:54.518273 CH=1, VrefRange= 0, VrefLevel = 30
2774 13:43:54.521567 TX Bit0 (977~1001) 25 989, Bit8 (969~992) 24 980,
2775 13:43:54.524682 TX Bit1 (976~1000) 25 988, Bit9 (969~992) 24 980,
2776 13:43:54.531850 TX Bit2 (975~997) 23 986, Bit10 (970~993) 24 981,
2777 13:43:54.534790 TX Bit3 (973~996) 24 984, Bit11 (970~994) 25 982,
2778 13:43:54.538137 TX Bit4 (976~999) 24 987, Bit12 (971~995) 25 983,
2779 13:43:54.544908 TX Bit5 (977~1000) 24 988, Bit13 (971~994) 24 982,
2780 13:43:54.548134 TX Bit6 (977~1001) 25 989, Bit14 (970~993) 24 981,
2781 13:43:54.555308 TX Bit7 (976~999) 24 987, Bit15 (968~992) 25 980,
2782 13:43:54.555444
2783 13:43:54.555507 Write Rank0 MR14 =0x20
2784 13:43:54.564537
2785 13:43:54.567812 CH=1, VrefRange= 0, VrefLevel = 32
2786 13:43:54.571386 TX Bit0 (977~1001) 25 989, Bit8 (969~992) 24 980,
2787 13:43:54.574433 TX Bit1 (976~1000) 25 988, Bit9 (969~992) 24 980,
2788 13:43:54.581447 TX Bit2 (975~997) 23 986, Bit10 (970~993) 24 981,
2789 13:43:54.584505 TX Bit3 (973~996) 24 984, Bit11 (970~994) 25 982,
2790 13:43:54.587856 TX Bit4 (976~999) 24 987, Bit12 (971~995) 25 983,
2791 13:43:54.594570 TX Bit5 (977~1000) 24 988, Bit13 (971~994) 24 982,
2792 13:43:54.598029 TX Bit6 (977~1001) 25 989, Bit14 (970~993) 24 981,
2793 13:43:54.601285 TX Bit7 (976~999) 24 987, Bit15 (968~992) 25 980,
2794 13:43:54.604632
2795 13:43:54.604755
2796 13:43:54.608137 TX Vref found, early break! 356< 369
2797 13:43:54.611165 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =762/100 ps
2798 13:43:54.614388 u1DelayCellOfst[0]=6 cells (5 PI)
2799 13:43:54.617860 u1DelayCellOfst[1]=5 cells (4 PI)
2800 13:43:54.621222 u1DelayCellOfst[2]=2 cells (2 PI)
2801 13:43:54.624649 u1DelayCellOfst[3]=0 cells (0 PI)
2802 13:43:54.627876 u1DelayCellOfst[4]=3 cells (3 PI)
2803 13:43:54.627996 u1DelayCellOfst[5]=5 cells (4 PI)
2804 13:43:54.631464 u1DelayCellOfst[6]=6 cells (5 PI)
2805 13:43:54.634431 u1DelayCellOfst[7]=3 cells (3 PI)
2806 13:43:54.637676 Byte0, DQ PI dly=984, DQM PI dly= 986
2807 13:43:54.644871 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
2808 13:43:54.644999
2809 13:43:54.647872 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
2810 13:43:54.647981
2811 13:43:54.651306 u1DelayCellOfst[8]=0 cells (0 PI)
2812 13:43:54.654395 u1DelayCellOfst[9]=0 cells (0 PI)
2813 13:43:54.658006 u1DelayCellOfst[10]=1 cells (1 PI)
2814 13:43:54.661449 u1DelayCellOfst[11]=2 cells (2 PI)
2815 13:43:54.661568 u1DelayCellOfst[12]=3 cells (3 PI)
2816 13:43:54.664552 u1DelayCellOfst[13]=2 cells (2 PI)
2817 13:43:54.667919 u1DelayCellOfst[14]=1 cells (1 PI)
2818 13:43:54.671357 u1DelayCellOfst[15]=0 cells (0 PI)
2819 13:43:54.674714 Byte1, DQ PI dly=980, DQM PI dly= 981
2820 13:43:54.681460 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
2821 13:43:54.681610
2822 13:43:54.684720 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
2823 13:43:54.684855
2824 13:43:54.687956 Write Rank0 MR14 =0x16
2825 13:43:54.688042
2826 13:43:54.688101 Final TX Range 0 Vref 22
2827 13:43:54.688155
2828 13:43:54.694497 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2829 13:43:54.694611
2830 13:43:54.701407 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2831 13:43:54.707977 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2832 13:43:54.717832 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2833 13:43:54.717948 Write Rank0 MR3 =0xb0
2834 13:43:54.721123 DramC Write-DBI on
2835 13:43:54.721246 ==
2836 13:43:54.724827 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2837 13:43:54.728154 fsp= 1, odt_onoff= 1, Byte mode= 0
2838 13:43:54.728239 ==
2839 13:43:54.734485 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2840 13:43:54.734617
2841 13:43:54.734716 Begin, DQ Scan Range 701~765
2842 13:43:54.734803
2843 13:43:54.734870
2844 13:43:54.737726 TX Vref Scan disable
2845 13:43:54.741421 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2846 13:43:54.744623 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2847 13:43:54.747926 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2848 13:43:54.751334 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2849 13:43:54.754665 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2850 13:43:54.758056 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2851 13:43:54.761522 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2852 13:43:54.764947 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2853 13:43:54.768422 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2854 13:43:54.771240 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2855 13:43:54.774644 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2856 13:43:54.778001 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2857 13:43:54.784761 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2858 13:43:54.788191 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2859 13:43:54.791532 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2860 13:43:54.795090 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2861 13:43:54.798202 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2862 13:43:54.801446 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
2863 13:43:54.808600 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2864 13:43:54.811836 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2865 13:43:54.815400 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2866 13:43:54.818694 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2867 13:43:54.822102 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2868 13:43:54.825488 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2869 13:43:54.828819 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2870 13:43:54.832007 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2871 13:43:54.835525 745 |2 6 41|[0] xxxxxxxx xxxxxxxx [MSB]
2872 13:43:54.838751 Byte0, DQ PI dly=731, DQM PI dly= 731
2873 13:43:54.842697 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 27)
2874 13:43:54.842830
2875 13:43:54.848681 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 27)
2876 13:43:54.848777
2877 13:43:54.852436 Byte1, DQ PI dly=724, DQM PI dly= 724
2878 13:43:54.855550 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 20)
2879 13:43:54.855633
2880 13:43:54.858593 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 20)
2881 13:43:54.858675
2882 13:43:54.865450 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2883 13:43:54.871973 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2884 13:43:54.882313 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2885 13:43:54.882440 Write Rank0 MR3 =0x30
2886 13:43:54.885934 DramC Write-DBI off
2887 13:43:54.886037
2888 13:43:54.886097 [DATLAT]
2889 13:43:54.888925 Freq=1600, CH1 RK0, use_rxtx_scan=0
2890 13:43:54.889021
2891 13:43:54.891893 DATLAT Default: 0xf
2892 13:43:54.891975 7, 0xFFFF, sum=0
2893 13:43:54.892035 8, 0xFFFF, sum=0
2894 13:43:54.895418 9, 0xFFFF, sum=0
2895 13:43:54.895503 10, 0xFFFF, sum=0
2896 13:43:54.898706 11, 0xFFFF, sum=0
2897 13:43:54.898785 12, 0xFFFF, sum=0
2898 13:43:54.902203 13, 0xFFFF, sum=0
2899 13:43:54.902281 14, 0x0, sum=1
2900 13:43:54.905210 15, 0x0, sum=2
2901 13:43:54.905320 16, 0x0, sum=3
2902 13:43:54.908563 17, 0x0, sum=4
2903 13:43:54.912220 pattern=2 first_step=14 total pass=5 best_step=16
2904 13:43:54.912313 ==
2905 13:43:54.915289 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2906 13:43:54.918768 fsp= 1, odt_onoff= 1, Byte mode= 0
2907 13:43:54.918852 ==
2908 13:43:54.925171 Start DQ dly to find pass range UseTestEngine =1
2909 13:43:54.928465 x-axis: bit #, y-axis: DQ dly (-127~63)
2910 13:43:54.928549 RX Vref Scan = 1
2911 13:43:55.052231
2912 13:43:55.052359 RX Vref found, early break!
2913 13:43:55.052419
2914 13:43:55.059215 Final RX Vref 13, apply to both rank0 and 1
2915 13:43:55.059318 ==
2916 13:43:55.062771 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2917 13:43:55.065478 fsp= 1, odt_onoff= 1, Byte mode= 0
2918 13:43:55.065581 ==
2919 13:43:55.065666 DQS Delay:
2920 13:43:55.068942 DQS0 = 0, DQS1 = 0
2921 13:43:55.069023 DQM Delay:
2922 13:43:55.072104 DQM0 = 20, DQM1 = 18
2923 13:43:55.072186 DQ Delay:
2924 13:43:55.075494 DQ0 =24, DQ1 =23, DQ2 =17, DQ3 =15
2925 13:43:55.078844 DQ4 =19, DQ5 =24, DQ6 =25, DQ7 =20
2926 13:43:55.082018 DQ8 =18, DQ9 =18, DQ10 =18, DQ11 =19
2927 13:43:55.085255 DQ12 =21, DQ13 =20, DQ14 =20, DQ15 =15
2928 13:43:55.085355
2929 13:43:55.085414
2930 13:43:55.085467
2931 13:43:55.088977 [DramC_TX_OE_Calibration] TA2
2932 13:43:55.092347 Original DQ_B0 (3 6) =30, OEN = 27
2933 13:43:55.095319 Original DQ_B1 (3 6) =30, OEN = 27
2934 13:43:55.098593 23, 0x0, End_B0=23 End_B1=23
2935 13:43:55.098679 24, 0x0, End_B0=24 End_B1=24
2936 13:43:55.101812 25, 0x0, End_B0=25 End_B1=25
2937 13:43:55.105216 26, 0x0, End_B0=26 End_B1=26
2938 13:43:55.108680 27, 0x0, End_B0=27 End_B1=27
2939 13:43:55.108766 28, 0x0, End_B0=28 End_B1=28
2940 13:43:55.112178 29, 0x0, End_B0=29 End_B1=29
2941 13:43:55.115656 30, 0x0, End_B0=30 End_B1=30
2942 13:43:55.118607 31, 0xFFFF, End_B0=30 End_B1=30
2943 13:43:55.125678 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2944 13:43:55.129002 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2945 13:43:55.129090
2946 13:43:55.129149
2947 13:43:55.132156 Write Rank0 MR23 =0x3f
2948 13:43:55.132234 [DQSOSC]
2949 13:43:55.138890 [DQSOSCAuto] RK0, (LSB)MR18= 0xa4, (MSB)MR19= 0x3, tDQSOscB0 = 337 ps tDQSOscB1 = 0 ps
2950 13:43:55.145260 CH1_RK0: MR19=0x3, MR18=0xA4, DQSOSC=337, MR23=63, INC=21, DEC=32
2951 13:43:55.148964 Write Rank0 MR23 =0x3f
2952 13:43:55.149058 [DQSOSC]
2953 13:43:55.155642 [DQSOSCAuto] RK0, (LSB)MR18= 0xa3, (MSB)MR19= 0x3, tDQSOscB0 = 338 ps tDQSOscB1 = 0 ps
2954 13:43:55.158652 CH1 RK0: MR19=3, MR18=A3
2955 13:43:55.162170 [RankSwap] Rank num 2, (Multi 1), Rank 1
2956 13:43:55.165705 Write Rank0 MR2 =0xad
2957 13:43:55.165816 [Write Leveling]
2958 13:43:55.168948 delay byte0 byte1 byte2 byte3
2959 13:43:55.169032
2960 13:43:55.172015 10 0 0
2961 13:43:55.172097 11 0 0
2962 13:43:55.172157 12 0 0
2963 13:43:55.175761 13 0 0
2964 13:43:55.175844 14 0 0
2965 13:43:55.178909 15 0 0
2966 13:43:55.178993 16 0 0
2967 13:43:55.179077 17 0 0
2968 13:43:55.182688 18 0 0
2969 13:43:55.182843 19 0 0
2970 13:43:55.185479 20 0 0
2971 13:43:55.185562 21 0 0
2972 13:43:55.185621 22 0 0
2973 13:43:55.188892 23 0 0
2974 13:43:55.188999 24 0 0
2975 13:43:55.192267 25 0 0
2976 13:43:55.192348 26 0 0
2977 13:43:55.192408 27 0 0
2978 13:43:55.195784 28 0 0
2979 13:43:55.195866 29 0 0
2980 13:43:55.198867 30 0 0
2981 13:43:55.198951 31 0 ff
2982 13:43:55.202481 32 0 ff
2983 13:43:55.202566 33 0 ff
2984 13:43:55.202626 34 0 ff
2985 13:43:55.205677 35 0 ff
2986 13:43:55.205761 36 0 ff
2987 13:43:55.209246 37 ff ff
2988 13:43:55.209345 38 ff ff
2989 13:43:55.212244 39 ff ff
2990 13:43:55.212374 40 ff ff
2991 13:43:55.215578 41 ff ff
2992 13:43:55.215696 42 ff ff
2993 13:43:55.218950 43 ff ff
2994 13:43:55.222615 pass bytecount = 0xff (0xff: all bytes pass)
2995 13:43:55.222813
2996 13:43:55.222909 DQS0 dly: 37
2997 13:43:55.225705 DQS1 dly: 31
2998 13:43:55.225787 Write Rank0 MR2 =0x2d
2999 13:43:55.229016 [RankSwap] Rank num 2, (Multi 1), Rank 0
3000 13:43:55.232657 Write Rank1 MR1 =0xd6
3001 13:43:55.232750 [Gating]
3002 13:43:55.232809 ==
3003 13:43:55.239181 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3004 13:43:55.242671 fsp= 1, odt_onoff= 1, Byte mode= 0
3005 13:43:55.242766 ==
3006 13:43:55.245953 3 1 0 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3007 13:43:55.249250 3 1 4 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3008 13:43:55.256727 3 1 8 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
3009 13:43:55.259336 3 1 12 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
3010 13:43:55.262771 3 1 16 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
3011 13:43:55.266245 3 1 20 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
3012 13:43:55.272809 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3013 13:43:55.276160 3 1 28 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3014 13:43:55.279344 3 2 0 |505 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3015 13:43:55.286356 3 2 4 |3d3d 303 |(11 11)(11 11) |(1 1)(0 0)| 0
3016 13:43:55.289082 3 2 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3017 13:43:55.292495 3 2 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3018 13:43:55.299206 3 2 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3019 13:43:55.302743 3 2 20 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3020 13:43:55.306076 3 2 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3021 13:43:55.312630 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3022 13:43:55.316005 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3023 13:43:55.319242 3 3 4 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3024 13:43:55.322557 3 3 8 |1414 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3025 13:43:55.329204 [Byte 0] Lead/lag Transition tap number (1)
3026 13:43:55.332559 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
3027 13:43:55.336133 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
3028 13:43:55.342598 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
3029 13:43:55.345946 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3030 13:43:55.349766 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3031 13:43:55.352758 3 4 0 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3032 13:43:55.359307 3 4 4 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
3033 13:43:55.362699 3 4 8 |3d3d 1313 |(11 11)(11 11) |(1 1)(1 1)| 0
3034 13:43:55.365797 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3035 13:43:55.372558 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3036 13:43:55.375740 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3037 13:43:55.379417 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3038 13:43:55.385815 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3039 13:43:55.389108 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3040 13:43:55.392526 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3041 13:43:55.399586 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3042 13:43:55.402451 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3043 13:43:55.406317 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3044 13:43:55.409198 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3045 13:43:55.416034 [Byte 0] Lead/lag falling Transition (3, 5, 20)
3046 13:43:55.419319 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3047 13:43:55.422537 [Byte 0] Lead/lag Transition tap number (2)
3048 13:43:55.425765 [Byte 1] Lead/lag falling Transition (3, 5, 24)
3049 13:43:55.432366 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3050 13:43:55.435639 3 6 0 |403 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3051 13:43:55.439165 [Byte 1] Lead/lag Transition tap number (3)
3052 13:43:55.442386 3 6 4 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
3053 13:43:55.445892 [Byte 0]First pass (3, 6, 4)
3054 13:43:55.449307 3 6 8 |4646 3838 |(0 0)(11 11) |(0 0)(0 0)| 0
3055 13:43:55.455899 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3056 13:43:55.456025 [Byte 1]First pass (3, 6, 12)
3057 13:43:55.462566 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3058 13:43:55.466258 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3059 13:43:55.469325 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3060 13:43:55.472510 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3061 13:43:55.476206 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3062 13:43:55.482880 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3063 13:43:55.486006 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3064 13:43:55.489198 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3065 13:43:55.492563 All bytes gating window > 1UI, Early break!
3066 13:43:55.492653
3067 13:43:55.496004 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 24)
3068 13:43:55.496109
3069 13:43:55.499654 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 30)
3070 13:43:55.502636
3071 13:43:55.502718
3072 13:43:55.502799
3073 13:43:55.506099 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 24)
3074 13:43:55.506185
3075 13:43:55.509738 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 30)
3076 13:43:55.509822
3077 13:43:55.509898
3078 13:43:55.513202 Write Rank1 MR1 =0x56
3079 13:43:55.513311
3080 13:43:55.516235 best RODT dly(2T, 0.5T) = (2, 2)
3081 13:43:55.516318
3082 13:43:55.519318 best RODT dly(2T, 0.5T) = (2, 2)
3083 13:43:55.519399 ==
3084 13:43:55.522982 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3085 13:43:55.526402 fsp= 1, odt_onoff= 1, Byte mode= 0
3086 13:43:55.526503 ==
3087 13:43:55.529637 Start DQ dly to find pass range UseTestEngine =0
3088 13:43:55.533100 x-axis: bit #, y-axis: DQ dly (-127~63)
3089 13:43:55.536361 RX Vref Scan = 0
3090 13:43:55.539630 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3091 13:43:55.542976 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3092 13:43:55.546309 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3093 13:43:55.546402 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3094 13:43:55.549850 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3095 13:43:55.553151 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3096 13:43:55.556414 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3097 13:43:55.559664 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3098 13:43:55.563245 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3099 13:43:55.566414 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3100 13:43:55.570153 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3101 13:43:55.570251 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3102 13:43:55.573428 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3103 13:43:55.576243 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3104 13:43:55.579773 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3105 13:43:55.583037 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3106 13:43:55.586317 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3107 13:43:55.589875 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3108 13:43:55.593239 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3109 13:43:55.593349 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3110 13:43:55.596586 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3111 13:43:55.599790 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3112 13:43:55.603082 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3113 13:43:55.606531 -3, [0] xxxoxxxx xxxxxxxx [MSB]
3114 13:43:55.609780 -2, [0] xxxoxxxx xxxxxxxo [MSB]
3115 13:43:55.609896 -1, [0] xxooxxxx xxxxxxxo [MSB]
3116 13:43:55.613210 0, [0] xxooxxxx xxxxxxxo [MSB]
3117 13:43:55.616692 1, [0] xxooxxxx oxoxxxxo [MSB]
3118 13:43:55.620120 2, [0] xxoooxxo oooxxxxo [MSB]
3119 13:43:55.623266 3, [0] xxoooxxo ooooxxoo [MSB]
3120 13:43:55.626514 4, [0] xxoooxxo ooooxooo [MSB]
3121 13:43:55.626607 5, [0] xooooxxo oooooooo [MSB]
3122 13:43:55.629809 6, [0] xooooxxo oooooooo [MSB]
3123 13:43:55.633234 33, [0] oooxoooo oooooooo [MSB]
3124 13:43:55.636848 34, [0] oooxoooo ooooooox [MSB]
3125 13:43:55.640053 35, [0] ooxxoooo ooooooox [MSB]
3126 13:43:55.643331 36, [0] ooxxoooo oxooooox [MSB]
3127 13:43:55.646567 37, [0] ooxxoooo xxxxooox [MSB]
3128 13:43:55.646665 38, [0] ooxxoooo xxxxooox [MSB]
3129 13:43:55.649871 39, [0] ooxxxoox xxxxooxx [MSB]
3130 13:43:55.653503 40, [0] ooxxxoox xxxxoxxx [MSB]
3131 13:43:55.656745 41, [0] ooxxxoox xxxxxxxx [MSB]
3132 13:43:55.660318 42, [0] ooxxxoox xxxxxxxx [MSB]
3133 13:43:55.663349 43, [0] oxxxxxxx xxxxxxxx [MSB]
3134 13:43:55.666527 44, [0] xxxxxxxx xxxxxxxx [MSB]
3135 13:43:55.669913 iDelay=44, Bit 0, Center 25 (7 ~ 43) 37
3136 13:43:55.673528 iDelay=44, Bit 1, Center 23 (5 ~ 42) 38
3137 13:43:55.676958 iDelay=44, Bit 2, Center 16 (-1 ~ 34) 36
3138 13:43:55.679899 iDelay=44, Bit 3, Center 14 (-3 ~ 32) 36
3139 13:43:55.683420 iDelay=44, Bit 4, Center 20 (2 ~ 38) 37
3140 13:43:55.687017 iDelay=44, Bit 5, Center 24 (7 ~ 42) 36
3141 13:43:55.690287 iDelay=44, Bit 6, Center 24 (7 ~ 42) 36
3142 13:43:55.694036 iDelay=44, Bit 7, Center 20 (2 ~ 38) 37
3143 13:43:55.697088 iDelay=44, Bit 8, Center 18 (1 ~ 36) 36
3144 13:43:55.700172 iDelay=44, Bit 9, Center 18 (2 ~ 35) 34
3145 13:43:55.703604 iDelay=44, Bit 10, Center 18 (1 ~ 36) 36
3146 13:43:55.707125 iDelay=44, Bit 11, Center 19 (3 ~ 36) 34
3147 13:43:55.710208 iDelay=44, Bit 12, Center 22 (5 ~ 40) 36
3148 13:43:55.714126 iDelay=44, Bit 13, Center 21 (4 ~ 39) 36
3149 13:43:55.720317 iDelay=44, Bit 14, Center 20 (3 ~ 38) 36
3150 13:43:55.723610 iDelay=44, Bit 15, Center 15 (-2 ~ 33) 36
3151 13:43:55.723700 ==
3152 13:43:55.726987 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3153 13:43:55.730239 fsp= 1, odt_onoff= 1, Byte mode= 0
3154 13:43:55.730371 ==
3155 13:43:55.733481 DQS Delay:
3156 13:43:55.733561 DQS0 = 0, DQS1 = 0
3157 13:43:55.733622 DQM Delay:
3158 13:43:55.736958 DQM0 = 20, DQM1 = 18
3159 13:43:55.737059 DQ Delay:
3160 13:43:55.740147 DQ0 =25, DQ1 =23, DQ2 =16, DQ3 =14
3161 13:43:55.743493 DQ4 =20, DQ5 =24, DQ6 =24, DQ7 =20
3162 13:43:55.746788 DQ8 =18, DQ9 =18, DQ10 =18, DQ11 =19
3163 13:43:55.750406 DQ12 =22, DQ13 =21, DQ14 =20, DQ15 =15
3164 13:43:55.750490
3165 13:43:55.750548
3166 13:43:55.753677 DramC Write-DBI off
3167 13:43:55.753757 ==
3168 13:43:55.757051 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3169 13:43:55.760476 fsp= 1, odt_onoff= 1, Byte mode= 0
3170 13:43:55.760576 ==
3171 13:43:55.766879 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3172 13:43:55.767001
3173 13:43:55.767063 Begin, DQ Scan Range 927~1183
3174 13:43:55.770146
3175 13:43:55.770228
3176 13:43:55.770290 TX Vref Scan disable
3177 13:43:55.773404 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
3178 13:43:55.777001 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3179 13:43:55.780431 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3180 13:43:55.783465 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3181 13:43:55.790011 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3182 13:43:55.793431 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3183 13:43:55.796969 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3184 13:43:55.800201 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3185 13:43:55.803502 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3186 13:43:55.806947 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3187 13:43:55.810164 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3188 13:43:55.813250 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3189 13:43:55.816727 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3190 13:43:55.820029 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3191 13:43:55.823274 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3192 13:43:55.826607 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3193 13:43:55.829863 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3194 13:43:55.833553 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3195 13:43:55.836917 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3196 13:43:55.840538 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3197 13:43:55.846434 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3198 13:43:55.850153 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3199 13:43:55.853451 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3200 13:43:55.856905 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3201 13:43:55.859843 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3202 13:43:55.863340 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3203 13:43:55.866674 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3204 13:43:55.870004 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3205 13:43:55.873296 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3206 13:43:55.876610 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3207 13:43:55.879981 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3208 13:43:55.883325 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3209 13:43:55.886702 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3210 13:43:55.889823 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3211 13:43:55.892990 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3212 13:43:55.896690 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3213 13:43:55.900258 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3214 13:43:55.903026 964 |3 6 4|[0] xxxxxxxx xxxxxxxo [MSB]
3215 13:43:55.909651 965 |3 6 5|[0] xxxxxxxx xxxxxxxo [MSB]
3216 13:43:55.913031 966 |3 6 6|[0] xxxxxxxx xxxxxxxo [MSB]
3217 13:43:55.916562 967 |3 6 7|[0] xxxxxxxx ooxxxxxo [MSB]
3218 13:43:55.919854 968 |3 6 8|[0] xxxxxxxx oooxxxxo [MSB]
3219 13:43:55.923201 969 |3 6 9|[0] xxxxxxxx ooooxooo [MSB]
3220 13:43:55.926751 970 |3 6 10|[0] xxxxxxxx oooooooo [MSB]
3221 13:43:55.930002 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB]
3222 13:43:55.933438 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
3223 13:43:55.936464 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
3224 13:43:55.939934 974 |3 6 14|[0] xxoooxxx oooooooo [MSB]
3225 13:43:55.943183 975 |3 6 15|[0] xxoooxxo oooooooo [MSB]
3226 13:43:55.946421 976 |3 6 16|[0] xooooooo oooooooo [MSB]
3227 13:43:55.953549 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
3228 13:43:55.956931 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
3229 13:43:55.960516 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
3230 13:43:55.963497 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
3231 13:43:55.966790 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
3232 13:43:55.970151 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
3233 13:43:55.973924 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
3234 13:43:55.976767 997 |3 6 37|[0] oooxoooo xxxxxxxx [MSB]
3235 13:43:55.980160 998 |3 6 38|[0] ooxxoooo xxxxxxxx [MSB]
3236 13:43:55.983520 999 |3 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
3237 13:43:55.987188 Byte0, DQ PI dly=986, DQM PI dly= 986
3238 13:43:55.990313 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
3239 13:43:55.990406
3240 13:43:55.996819 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
3241 13:43:55.996925
3242 13:43:56.000211 Byte1, DQ PI dly=977, DQM PI dly= 977
3243 13:43:56.003739 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
3244 13:43:56.003835
3245 13:43:56.006698 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
3246 13:43:56.010241
3247 13:43:56.010323 ==
3248 13:43:56.013777 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3249 13:43:56.017055 fsp= 1, odt_onoff= 1, Byte mode= 0
3250 13:43:56.017140 ==
3251 13:43:56.020284 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3252 13:43:56.020378
3253 13:43:56.023668 Begin, DQ Scan Range 953~1017
3254 13:43:56.027061 Write Rank1 MR14 =0x0
3255 13:43:56.035693
3256 13:43:56.035805 CH=1, VrefRange= 0, VrefLevel = 0
3257 13:43:56.042070 TX Bit0 (978~998) 21 988, Bit8 (969~986) 18 977,
3258 13:43:56.045203 TX Bit1 (977~997) 21 987, Bit9 (969~986) 18 977,
3259 13:43:56.051849 TX Bit2 (975~992) 18 983, Bit10 (970~985) 16 977,
3260 13:43:56.055159 TX Bit3 (975~991) 17 983, Bit11 (971~989) 19 980,
3261 13:43:56.058395 TX Bit4 (976~994) 19 985, Bit12 (971~990) 20 980,
3262 13:43:56.065014 TX Bit5 (978~998) 21 988, Bit13 (970~986) 17 978,
3263 13:43:56.068859 TX Bit6 (978~998) 21 988, Bit14 (970~987) 18 978,
3264 13:43:56.072090 TX Bit7 (977~994) 18 985, Bit15 (966~985) 20 975,
3265 13:43:56.072180
3266 13:43:56.075259 Write Rank1 MR14 =0x2
3267 13:43:56.084613
3268 13:43:56.084735 CH=1, VrefRange= 0, VrefLevel = 2
3269 13:43:56.091595 TX Bit0 (977~998) 22 987, Bit8 (969~987) 19 978,
3270 13:43:56.095012 TX Bit1 (977~997) 21 987, Bit9 (969~986) 18 977,
3271 13:43:56.101142 TX Bit2 (975~992) 18 983, Bit10 (970~986) 17 978,
3272 13:43:56.104835 TX Bit3 (974~991) 18 982, Bit11 (970~989) 20 979,
3273 13:43:56.108022 TX Bit4 (976~994) 19 985, Bit12 (971~990) 20 980,
3274 13:43:56.114939 TX Bit5 (977~998) 22 987, Bit13 (970~987) 18 978,
3275 13:43:56.117979 TX Bit6 (977~998) 22 987, Bit14 (970~987) 18 978,
3276 13:43:56.121717 TX Bit7 (977~995) 19 986, Bit15 (966~985) 20 975,
3277 13:43:56.121813
3278 13:43:56.124694 Write Rank1 MR14 =0x4
3279 13:43:56.133888
3280 13:43:56.134014 CH=1, VrefRange= 0, VrefLevel = 4
3281 13:43:56.140295 TX Bit0 (977~999) 23 988, Bit8 (969~988) 20 978,
3282 13:43:56.143730 TX Bit1 (977~998) 22 987, Bit9 (969~987) 19 978,
3283 13:43:56.150176 TX Bit2 (975~993) 19 984, Bit10 (970~986) 17 978,
3284 13:43:56.153819 TX Bit3 (974~992) 19 983, Bit11 (970~990) 21 980,
3285 13:43:56.157032 TX Bit4 (976~995) 20 985, Bit12 (971~991) 21 981,
3286 13:43:56.163586 TX Bit5 (977~998) 22 987, Bit13 (970~988) 19 979,
3287 13:43:56.167267 TX Bit6 (977~999) 23 988, Bit14 (970~988) 19 979,
3288 13:43:56.170473 TX Bit7 (977~996) 20 986, Bit15 (966~985) 20 975,
3289 13:43:56.170575
3290 13:43:56.173620 Write Rank1 MR14 =0x6
3291 13:43:56.183194
3292 13:43:56.183317 CH=1, VrefRange= 0, VrefLevel = 6
3293 13:43:56.189467 TX Bit0 (977~999) 23 988, Bit8 (968~988) 21 978,
3294 13:43:56.192889 TX Bit1 (976~998) 23 987, Bit9 (969~987) 19 978,
3295 13:43:56.199567 TX Bit2 (974~993) 20 983, Bit10 (969~986) 18 977,
3296 13:43:56.202813 TX Bit3 (973~992) 20 982, Bit11 (970~990) 21 980,
3297 13:43:56.206568 TX Bit4 (976~996) 21 986, Bit12 (971~991) 21 981,
3298 13:43:56.213081 TX Bit5 (977~998) 22 987, Bit13 (970~989) 20 979,
3299 13:43:56.216281 TX Bit6 (977~999) 23 988, Bit14 (970~989) 20 979,
3300 13:43:56.219583 TX Bit7 (977~996) 20 986, Bit15 (965~986) 22 975,
3301 13:43:56.219700
3302 13:43:56.222852 Write Rank1 MR14 =0x8
3303 13:43:56.232432
3304 13:43:56.232547 CH=1, VrefRange= 0, VrefLevel = 8
3305 13:43:56.238774 TX Bit0 (977~999) 23 988, Bit8 (968~989) 22 978,
3306 13:43:56.242153 TX Bit1 (976~998) 23 987, Bit9 (968~988) 21 978,
3307 13:43:56.248946 TX Bit2 (974~994) 21 984, Bit10 (969~988) 20 978,
3308 13:43:56.252211 TX Bit3 (973~993) 21 983, Bit11 (970~991) 22 980,
3309 13:43:56.255543 TX Bit4 (976~996) 21 986, Bit12 (970~991) 22 980,
3310 13:43:56.262386 TX Bit5 (977~999) 23 988, Bit13 (970~989) 20 979,
3311 13:43:56.265380 TX Bit6 (977~999) 23 988, Bit14 (969~990) 22 979,
3312 13:43:56.269451 TX Bit7 (976~997) 22 986, Bit15 (964~987) 24 975,
3313 13:43:56.269581
3314 13:43:56.272038 Write Rank1 MR14 =0xa
3315 13:43:56.281844
3316 13:43:56.285249 CH=1, VrefRange= 0, VrefLevel = 10
3317 13:43:56.288039 TX Bit0 (977~999) 23 988, Bit8 (968~990) 23 979,
3318 13:43:56.291639 TX Bit1 (976~998) 23 987, Bit9 (968~988) 21 978,
3319 13:43:56.298228 TX Bit2 (974~994) 21 984, Bit10 (969~988) 20 978,
3320 13:43:56.301406 TX Bit3 (973~994) 22 983, Bit11 (969~991) 23 980,
3321 13:43:56.304898 TX Bit4 (975~997) 23 986, Bit12 (970~991) 22 980,
3322 13:43:56.311616 TX Bit5 (977~999) 23 988, Bit13 (969~990) 22 979,
3323 13:43:56.315155 TX Bit6 (977~999) 23 988, Bit14 (969~990) 22 979,
3324 13:43:56.318499 TX Bit7 (976~997) 22 986, Bit15 (964~987) 24 975,
3325 13:43:56.318579
3326 13:43:56.321608 Write Rank1 MR14 =0xc
3327 13:43:56.331186
3328 13:43:56.334735 CH=1, VrefRange= 0, VrefLevel = 12
3329 13:43:56.337813 TX Bit0 (977~1000) 24 988, Bit8 (967~990) 24 978,
3330 13:43:56.341499 TX Bit1 (976~998) 23 987, Bit9 (968~990) 23 979,
3331 13:43:56.347714 TX Bit2 (974~996) 23 985, Bit10 (969~989) 21 979,
3332 13:43:56.351162 TX Bit3 (972~994) 23 983, Bit11 (970~991) 22 980,
3333 13:43:56.354330 TX Bit4 (975~997) 23 986, Bit12 (970~992) 23 981,
3334 13:43:56.360990 TX Bit5 (977~999) 23 988, Bit13 (969~990) 22 979,
3335 13:43:56.364440 TX Bit6 (977~1000) 24 988, Bit14 (969~991) 23 980,
3336 13:43:56.367685 TX Bit7 (976~997) 22 986, Bit15 (964~988) 25 976,
3337 13:43:56.371012
3338 13:43:56.371095 Write Rank1 MR14 =0xe
3339 13:43:56.380668
3340 13:43:56.383866 CH=1, VrefRange= 0, VrefLevel = 14
3341 13:43:56.387634 TX Bit0 (977~1000) 24 988, Bit8 (967~991) 25 979,
3342 13:43:56.390646 TX Bit1 (976~998) 23 987, Bit9 (967~990) 24 978,
3343 13:43:56.397954 TX Bit2 (973~996) 24 984, Bit10 (968~990) 23 979,
3344 13:43:56.400874 TX Bit3 (972~995) 24 983, Bit11 (969~992) 24 980,
3345 13:43:56.404082 TX Bit4 (975~997) 23 986, Bit12 (970~992) 23 981,
3346 13:43:56.410725 TX Bit5 (976~999) 24 987, Bit13 (969~991) 23 980,
3347 13:43:56.414121 TX Bit6 (977~1000) 24 988, Bit14 (969~991) 23 980,
3348 13:43:56.417609 TX Bit7 (976~997) 22 986, Bit15 (964~989) 26 976,
3349 13:43:56.417694
3350 13:43:56.420756 Write Rank1 MR14 =0x10
3351 13:43:56.430550
3352 13:43:56.433968 CH=1, VrefRange= 0, VrefLevel = 16
3353 13:43:56.437178 TX Bit0 (976~1000) 25 988, Bit8 (967~991) 25 979,
3354 13:43:56.440492 TX Bit1 (976~998) 23 987, Bit9 (967~990) 24 978,
3355 13:43:56.447383 TX Bit2 (972~997) 26 984, Bit10 (968~990) 23 979,
3356 13:43:56.450517 TX Bit3 (972~996) 25 984, Bit11 (969~992) 24 980,
3357 13:43:56.454222 TX Bit4 (974~997) 24 985, Bit12 (969~992) 24 980,
3358 13:43:56.460976 TX Bit5 (976~1000) 25 988, Bit13 (969~991) 23 980,
3359 13:43:56.464163 TX Bit6 (976~1000) 25 988, Bit14 (969~991) 23 980,
3360 13:43:56.467102 TX Bit7 (975~997) 23 986, Bit15 (963~989) 27 976,
3361 13:43:56.470622
3362 13:43:56.470741 Write Rank1 MR14 =0x12
3363 13:43:56.480538
3364 13:43:56.483901 CH=1, VrefRange= 0, VrefLevel = 18
3365 13:43:56.487341 TX Bit0 (976~1001) 26 988, Bit8 (966~991) 26 978,
3366 13:43:56.490585 TX Bit1 (976~999) 24 987, Bit9 (966~990) 25 978,
3367 13:43:56.497088 TX Bit2 (972~997) 26 984, Bit10 (967~991) 25 979,
3368 13:43:56.500459 TX Bit3 (971~996) 26 983, Bit11 (968~992) 25 980,
3369 13:43:56.503861 TX Bit4 (974~997) 24 985, Bit12 (970~992) 23 981,
3370 13:43:56.510610 TX Bit5 (976~1000) 25 988, Bit13 (968~991) 24 979,
3371 13:43:56.513971 TX Bit6 (976~1000) 25 988, Bit14 (968~991) 24 979,
3372 13:43:56.517197 TX Bit7 (975~998) 24 986, Bit15 (963~989) 27 976,
3373 13:43:56.520503
3374 13:43:56.520578 Write Rank1 MR14 =0x14
3375 13:43:56.530800
3376 13:43:56.533896 CH=1, VrefRange= 0, VrefLevel = 20
3377 13:43:56.537568 TX Bit0 (976~1001) 26 988, Bit8 (966~991) 26 978,
3378 13:43:56.540618 TX Bit1 (976~999) 24 987, Bit9 (966~991) 26 978,
3379 13:43:56.547307 TX Bit2 (971~997) 27 984, Bit10 (968~991) 24 979,
3380 13:43:56.551004 TX Bit3 (970~996) 27 983, Bit11 (968~992) 25 980,
3381 13:43:56.554221 TX Bit4 (974~998) 25 986, Bit12 (969~992) 24 980,
3382 13:43:56.560715 TX Bit5 (976~1000) 25 988, Bit13 (969~991) 23 980,
3383 13:43:56.564213 TX Bit6 (976~1001) 26 988, Bit14 (968~991) 24 979,
3384 13:43:56.567679 TX Bit7 (975~998) 24 986, Bit15 (963~990) 28 976,
3385 13:43:56.567753
3386 13:43:56.571032 Write Rank1 MR14 =0x16
3387 13:43:56.580401
3388 13:43:56.583975 CH=1, VrefRange= 0, VrefLevel = 22
3389 13:43:56.587314 TX Bit0 (976~1001) 26 988, Bit8 (965~991) 27 978,
3390 13:43:56.591219 TX Bit1 (975~999) 25 987, Bit9 (965~991) 27 978,
3391 13:43:56.597248 TX Bit2 (971~997) 27 984, Bit10 (967~991) 25 979,
3392 13:43:56.600712 TX Bit3 (970~997) 28 983, Bit11 (968~992) 25 980,
3393 13:43:56.604250 TX Bit4 (974~998) 25 986, Bit12 (969~992) 24 980,
3394 13:43:56.610781 TX Bit5 (976~1000) 25 988, Bit13 (968~992) 25 980,
3395 13:43:56.614287 TX Bit6 (976~1001) 26 988, Bit14 (968~992) 25 980,
3396 13:43:56.617697 TX Bit7 (975~998) 24 986, Bit15 (963~990) 28 976,
3397 13:43:56.620636
3398 13:43:56.620709 Write Rank1 MR14 =0x18
3399 13:43:56.630776
3400 13:43:56.634181 CH=1, VrefRange= 0, VrefLevel = 24
3401 13:43:56.637623 TX Bit0 (976~1001) 26 988, Bit8 (965~991) 27 978,
3402 13:43:56.641003 TX Bit1 (975~999) 25 987, Bit9 (965~991) 27 978,
3403 13:43:56.647491 TX Bit2 (971~997) 27 984, Bit10 (967~991) 25 979,
3404 13:43:56.650766 TX Bit3 (970~997) 28 983, Bit11 (968~992) 25 980,
3405 13:43:56.654063 TX Bit4 (974~998) 25 986, Bit12 (969~992) 24 980,
3406 13:43:56.660847 TX Bit5 (976~1000) 25 988, Bit13 (968~992) 25 980,
3407 13:43:56.664512 TX Bit6 (976~1001) 26 988, Bit14 (968~992) 25 980,
3408 13:43:56.667993 TX Bit7 (975~998) 24 986, Bit15 (963~990) 28 976,
3409 13:43:56.668068
3410 13:43:56.671305 Write Rank1 MR14 =0x1a
3411 13:43:56.680942
3412 13:43:56.684157 CH=1, VrefRange= 0, VrefLevel = 26
3413 13:43:56.687352 TX Bit0 (976~1001) 26 988, Bit8 (965~991) 27 978,
3414 13:43:56.690834 TX Bit1 (975~999) 25 987, Bit9 (965~991) 27 978,
3415 13:43:56.697548 TX Bit2 (971~997) 27 984, Bit10 (967~991) 25 979,
3416 13:43:56.701030 TX Bit3 (970~997) 28 983, Bit11 (968~992) 25 980,
3417 13:43:56.704261 TX Bit4 (974~998) 25 986, Bit12 (969~992) 24 980,
3418 13:43:56.711209 TX Bit5 (976~1000) 25 988, Bit13 (968~992) 25 980,
3419 13:43:56.714211 TX Bit6 (976~1001) 26 988, Bit14 (968~992) 25 980,
3420 13:43:56.718116 TX Bit7 (975~998) 24 986, Bit15 (963~990) 28 976,
3421 13:43:56.718191
3422 13:43:56.720918 Write Rank1 MR14 =0x1c
3423 13:43:56.730817
3424 13:43:56.734363 CH=1, VrefRange= 0, VrefLevel = 28
3425 13:43:56.737478 TX Bit0 (976~1001) 26 988, Bit8 (965~991) 27 978,
3426 13:43:56.741024 TX Bit1 (975~999) 25 987, Bit9 (965~991) 27 978,
3427 13:43:56.747425 TX Bit2 (971~997) 27 984, Bit10 (967~991) 25 979,
3428 13:43:56.750936 TX Bit3 (970~997) 28 983, Bit11 (968~992) 25 980,
3429 13:43:56.754085 TX Bit4 (974~998) 25 986, Bit12 (969~992) 24 980,
3430 13:43:56.760699 TX Bit5 (976~1000) 25 988, Bit13 (968~992) 25 980,
3431 13:43:56.764233 TX Bit6 (976~1001) 26 988, Bit14 (968~992) 25 980,
3432 13:43:56.770799 TX Bit7 (975~998) 24 986, Bit15 (963~990) 28 976,
3433 13:43:56.770875
3434 13:43:56.770933 Write Rank1 MR14 =0x1e
3435 13:43:56.780819
3436 13:43:56.780895 CH=1, VrefRange= 0, VrefLevel = 30
3437 13:43:56.787310 TX Bit0 (976~1001) 26 988, Bit8 (965~991) 27 978,
3438 13:43:56.791031 TX Bit1 (975~999) 25 987, Bit9 (965~991) 27 978,
3439 13:43:56.797790 TX Bit2 (971~997) 27 984, Bit10 (967~991) 25 979,
3440 13:43:56.800867 TX Bit3 (970~997) 28 983, Bit11 (968~992) 25 980,
3441 13:43:56.804106 TX Bit4 (974~998) 25 986, Bit12 (969~992) 24 980,
3442 13:43:56.810720 TX Bit5 (976~1000) 25 988, Bit13 (968~992) 25 980,
3443 13:43:56.814361 TX Bit6 (976~1001) 26 988, Bit14 (968~992) 25 980,
3444 13:43:56.817817 TX Bit7 (975~998) 24 986, Bit15 (963~990) 28 976,
3445 13:43:56.820854
3446 13:43:56.820979
3447 13:43:56.824264 TX Vref found, early break! 388< 391
3448 13:43:56.827477 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =762/100 ps
3449 13:43:56.831023 u1DelayCellOfst[0]=6 cells (5 PI)
3450 13:43:56.834379 u1DelayCellOfst[1]=5 cells (4 PI)
3451 13:43:56.837490 u1DelayCellOfst[2]=1 cells (1 PI)
3452 13:43:56.840846 u1DelayCellOfst[3]=0 cells (0 PI)
3453 13:43:56.840922 u1DelayCellOfst[4]=3 cells (3 PI)
3454 13:43:56.844141 u1DelayCellOfst[5]=6 cells (5 PI)
3455 13:43:56.847389 u1DelayCellOfst[6]=6 cells (5 PI)
3456 13:43:56.850726 u1DelayCellOfst[7]=3 cells (3 PI)
3457 13:43:56.854155 Byte0, DQ PI dly=983, DQM PI dly= 985
3458 13:43:56.860663 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
3459 13:43:56.860739
3460 13:43:56.864240 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
3461 13:43:56.864316
3462 13:43:56.867242 u1DelayCellOfst[8]=2 cells (2 PI)
3463 13:43:56.870486 u1DelayCellOfst[9]=2 cells (2 PI)
3464 13:43:56.873868 u1DelayCellOfst[10]=3 cells (3 PI)
3465 13:43:56.877330 u1DelayCellOfst[11]=5 cells (4 PI)
3466 13:43:56.880684 u1DelayCellOfst[12]=5 cells (4 PI)
3467 13:43:56.880759 u1DelayCellOfst[13]=5 cells (4 PI)
3468 13:43:56.883934 u1DelayCellOfst[14]=5 cells (4 PI)
3469 13:43:56.887421 u1DelayCellOfst[15]=0 cells (0 PI)
3470 13:43:56.890692 Byte1, DQ PI dly=976, DQM PI dly= 978
3471 13:43:56.897217 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 16)
3472 13:43:56.897326
3473 13:43:56.900637 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 16)
3474 13:43:56.900712
3475 13:43:56.904170 Write Rank1 MR14 =0x16
3476 13:43:56.904244
3477 13:43:56.904302 Final TX Range 0 Vref 22
3478 13:43:56.904355
3479 13:43:56.910589 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3480 13:43:56.910664
3481 13:43:56.917518 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3482 13:43:56.923932 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3483 13:43:56.934017 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3484 13:43:56.934098 Write Rank1 MR3 =0xb0
3485 13:43:56.937180 DramC Write-DBI on
3486 13:43:56.937261 ==
3487 13:43:56.940718 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3488 13:43:56.943981 fsp= 1, odt_onoff= 1, Byte mode= 0
3489 13:43:56.944056 ==
3490 13:43:56.950680 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3491 13:43:56.950754
3492 13:43:56.950812 Begin, DQ Scan Range 698~762
3493 13:43:56.950865
3494 13:43:56.950915
3495 13:43:56.954038 TX Vref Scan disable
3496 13:43:56.957158 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3497 13:43:56.960667 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3498 13:43:56.964090 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3499 13:43:56.967173 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3500 13:43:56.970740 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3501 13:43:56.974055 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3502 13:43:56.977509 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3503 13:43:56.983991 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3504 13:43:56.987260 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3505 13:43:56.990654 707 |2 6 3|[0] xxxxxxxx oooooooo [MSB]
3506 13:43:56.994201 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB]
3507 13:43:56.997442 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
3508 13:43:57.000887 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
3509 13:43:57.004504 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
3510 13:43:57.007150 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
3511 13:43:57.011237 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
3512 13:43:57.014119 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
3513 13:43:57.017236 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3514 13:43:57.020671 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3515 13:43:57.023907 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3516 13:43:57.031988 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
3517 13:43:57.035116 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
3518 13:43:57.038523 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
3519 13:43:57.042123 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
3520 13:43:57.045265 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
3521 13:43:57.048639 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
3522 13:43:57.051933 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3523 13:43:57.055305 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3524 13:43:57.058806 744 |2 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
3525 13:43:57.061869 Byte0, DQ PI dly=730, DQM PI dly= 730
3526 13:43:57.065197 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 26)
3527 13:43:57.065287
3528 13:43:57.072295 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 26)
3529 13:43:57.072374
3530 13:43:57.075332 Byte1, DQ PI dly=721, DQM PI dly= 721
3531 13:43:57.078634 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 17)
3532 13:43:57.078708
3533 13:43:57.082225 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 17)
3534 13:43:57.082300
3535 13:43:57.088568 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3536 13:43:57.095473 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3537 13:43:57.105190 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3538 13:43:57.105283 Write Rank1 MR3 =0x30
3539 13:43:57.109012 DramC Write-DBI off
3540 13:43:57.109086
3541 13:43:57.109143 [DATLAT]
3542 13:43:57.112060 Freq=1600, CH1 RK1, use_rxtx_scan=0
3543 13:43:57.112134
3544 13:43:57.115132 DATLAT Default: 0x10
3545 13:43:57.115207 7, 0xFFFF, sum=0
3546 13:43:57.118671 8, 0xFFFF, sum=0
3547 13:43:57.118746 9, 0xFFFF, sum=0
3548 13:43:57.121911 10, 0xFFFF, sum=0
3549 13:43:57.121987 11, 0xFFFF, sum=0
3550 13:43:57.122048 12, 0xFFFF, sum=0
3551 13:43:57.125294 13, 0xFFFF, sum=0
3552 13:43:57.125370 14, 0x0, sum=1
3553 13:43:57.128752 15, 0x0, sum=2
3554 13:43:57.128828 16, 0x0, sum=3
3555 13:43:57.131921 17, 0x0, sum=4
3556 13:43:57.135459 pattern=2 first_step=14 total pass=5 best_step=16
3557 13:43:57.135534 ==
3558 13:43:57.142105 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3559 13:43:57.142180 fsp= 1, odt_onoff= 1, Byte mode= 0
3560 13:43:57.145537 ==
3561 13:43:57.149006 Start DQ dly to find pass range UseTestEngine =1
3562 13:43:57.152505 x-axis: bit #, y-axis: DQ dly (-127~63)
3563 13:43:57.152580 RX Vref Scan = 0
3564 13:43:57.155937 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3565 13:43:57.158754 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3566 13:43:57.162039 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3567 13:43:57.165374 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3568 13:43:57.168609 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3569 13:43:57.172041 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3570 13:43:57.172116 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3571 13:43:57.175553 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3572 13:43:57.178815 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3573 13:43:57.181853 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3574 13:43:57.185366 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3575 13:43:57.188675 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3576 13:43:57.191978 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3577 13:43:57.195517 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3578 13:43:57.198639 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3579 13:43:57.198716 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3580 13:43:57.202261 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3581 13:43:57.205395 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3582 13:43:57.208756 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3583 13:43:57.211910 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3584 13:43:57.215456 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3585 13:43:57.219176 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3586 13:43:57.219252 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3587 13:43:57.222683 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3588 13:43:57.225388 -2, [0] xxxoxxxx xxxxxxxx [MSB]
3589 13:43:57.228736 -1, [0] xxxoxxxx xxxxxxxo [MSB]
3590 13:43:57.232221 0, [0] xxooxxxx xxxxxxxo [MSB]
3591 13:43:57.235551 1, [0] xxooxxxx oooxxxxo [MSB]
3592 13:43:57.235627 2, [0] xxooxxxx oooxxxxo [MSB]
3593 13:43:57.238930 3, [0] xxooxxxx ooooxxoo [MSB]
3594 13:43:57.242190 4, [0] xxoooxxo ooooxxoo [MSB]
3595 13:43:57.245391 5, [0] xxoooxxo ooooxooo [MSB]
3596 13:43:57.248632 6, [0] xxoooxxo oooooooo [MSB]
3597 13:43:57.252140 7, [0] xoooooxo oooooooo [MSB]
3598 13:43:57.252216 8, [0] ooooooxo oooooooo [MSB]
3599 13:43:57.256998 33, [0] oooxoooo ooooooox [MSB]
3600 13:43:57.260266 34, [0] oooxoooo ooooooox [MSB]
3601 13:43:57.263744 35, [0] oooxoooo ooooooox [MSB]
3602 13:43:57.266889 36, [0] ooxxoooo ooxoooox [MSB]
3603 13:43:57.270491 37, [0] ooxxoooo xxxxooox [MSB]
3604 13:43:57.273705 38, [0] ooxxxoox xxxxooxx [MSB]
3605 13:43:57.273781 39, [0] ooxxxoox xxxxoxxx [MSB]
3606 13:43:57.277314 40, [0] ooxxxoox xxxxxxxx [MSB]
3607 13:43:57.280625 41, [0] ooxxxxox xxxxxxxx [MSB]
3608 13:43:57.283778 42, [0] xxxxxxxx xxxxxxxx [MSB]
3609 13:43:57.287079 iDelay=42, Bit 0, Center 24 (8 ~ 41) 34
3610 13:43:57.290580 iDelay=42, Bit 1, Center 24 (7 ~ 41) 35
3611 13:43:57.293928 iDelay=42, Bit 2, Center 17 (0 ~ 35) 36
3612 13:43:57.297112 iDelay=42, Bit 3, Center 15 (-2 ~ 32) 35
3613 13:43:57.300603 iDelay=42, Bit 4, Center 20 (4 ~ 37) 34
3614 13:43:57.303821 iDelay=42, Bit 5, Center 23 (7 ~ 40) 34
3615 13:43:57.307074 iDelay=42, Bit 6, Center 25 (9 ~ 41) 33
3616 13:43:57.310594 iDelay=42, Bit 7, Center 20 (4 ~ 37) 34
3617 13:43:57.317556 iDelay=42, Bit 8, Center 18 (1 ~ 36) 36
3618 13:43:57.320709 iDelay=42, Bit 9, Center 18 (1 ~ 36) 36
3619 13:43:57.324010 iDelay=42, Bit 10, Center 18 (1 ~ 35) 35
3620 13:43:57.327351 iDelay=42, Bit 11, Center 19 (3 ~ 36) 34
3621 13:43:57.330618 iDelay=42, Bit 12, Center 22 (6 ~ 39) 34
3622 13:43:57.333903 iDelay=42, Bit 13, Center 21 (5 ~ 38) 34
3623 13:43:57.337589 iDelay=42, Bit 14, Center 20 (3 ~ 37) 35
3624 13:43:57.340788 iDelay=42, Bit 15, Center 15 (-1 ~ 32) 34
3625 13:43:57.340862 ==
3626 13:43:57.347746 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3627 13:43:57.350587 fsp= 1, odt_onoff= 1, Byte mode= 0
3628 13:43:57.350662 ==
3629 13:43:57.350719 DQS Delay:
3630 13:43:57.354184 DQS0 = 0, DQS1 = 0
3631 13:43:57.354259 DQM Delay:
3632 13:43:57.354315 DQM0 = 21, DQM1 = 18
3633 13:43:57.357196 DQ Delay:
3634 13:43:57.360775 DQ0 =24, DQ1 =24, DQ2 =17, DQ3 =15
3635 13:43:57.364269 DQ4 =20, DQ5 =23, DQ6 =25, DQ7 =20
3636 13:43:57.367403 DQ8 =18, DQ9 =18, DQ10 =18, DQ11 =19
3637 13:43:57.370604 DQ12 =22, DQ13 =21, DQ14 =20, DQ15 =15
3638 13:43:57.370679
3639 13:43:57.370736
3640 13:43:57.370789
3641 13:43:57.374184 [DramC_TX_OE_Calibration] TA2
3642 13:43:57.374259 Original DQ_B0 (3 6) =30, OEN = 27
3643 13:43:57.377423 Original DQ_B1 (3 6) =30, OEN = 27
3644 13:43:57.381134 23, 0x0, End_B0=23 End_B1=23
3645 13:43:57.384253 24, 0x0, End_B0=24 End_B1=24
3646 13:43:57.387791 25, 0x0, End_B0=25 End_B1=25
3647 13:43:57.387867 26, 0x0, End_B0=26 End_B1=26
3648 13:43:57.390826 27, 0x0, End_B0=27 End_B1=27
3649 13:43:57.394419 28, 0x0, End_B0=28 End_B1=28
3650 13:43:57.397608 29, 0x0, End_B0=29 End_B1=29
3651 13:43:57.400890 30, 0x0, End_B0=30 End_B1=30
3652 13:43:57.400966 31, 0xFFFF, End_B0=30 End_B1=30
3653 13:43:57.407647 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3654 13:43:57.414216 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3655 13:43:57.414290
3656 13:43:57.414347
3657 13:43:57.414399 Write Rank1 MR23 =0x3f
3658 13:43:57.417410 [DQSOSC]
3659 13:43:57.424177 [DQSOSCAuto] RK1, (LSB)MR18= 0xa4, (MSB)MR19= 0x3, tDQSOscB0 = 337 ps tDQSOscB1 = 0 ps
3660 13:43:57.430771 CH1_RK1: MR19=0x3, MR18=0xA4, DQSOSC=337, MR23=63, INC=21, DEC=32
3661 13:43:57.430872 Write Rank1 MR23 =0x3f
3662 13:43:57.434654 [DQSOSC]
3663 13:43:57.441023 [DQSOSCAuto] RK1, (LSB)MR18= 0xa3, (MSB)MR19= 0x3, tDQSOscB0 = 338 ps tDQSOscB1 = 0 ps
3664 13:43:57.441097 CH1 RK1: MR19=3, MR18=A3
3665 13:43:57.444523 [RxdqsGatingPostProcess] freq 1600
3666 13:43:57.450854 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3667 13:43:57.450927 Rank: 0
3668 13:43:57.454081 best DQS0 dly(2T, 0.5T) = (2, 5)
3669 13:43:57.457820 best DQS1 dly(2T, 0.5T) = (2, 5)
3670 13:43:57.461154 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3671 13:43:57.464175 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
3672 13:43:57.464249 Rank: 1
3673 13:43:57.467565 best DQS0 dly(2T, 0.5T) = (2, 5)
3674 13:43:57.470904 best DQS1 dly(2T, 0.5T) = (2, 5)
3675 13:43:57.474092 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3676 13:43:57.477204 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
3677 13:43:57.480809 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3678 13:43:57.484273 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3679 13:43:57.490684 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3680 13:43:57.490778
3681 13:43:57.490911
3682 13:43:57.494400 [Calibration Summary] Freqency 1600
3683 13:43:57.494476 CH 0, Rank 0
3684 13:43:57.497241 All Pass.
3685 13:43:57.497334
3686 13:43:57.497392 CH 0, Rank 1
3687 13:43:57.497446 All Pass.
3688 13:43:57.497496
3689 13:43:57.500892 CH 1, Rank 0
3690 13:43:57.500990 All Pass.
3691 13:43:57.501073
3692 13:43:57.501153 CH 1, Rank 1
3693 13:43:57.504201 All Pass.
3694 13:43:57.504274
3695 13:43:57.510790 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3696 13:43:57.517389 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3697 13:43:57.524149 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3698 13:43:57.524225 Write Rank0 MR3 =0xb0
3699 13:43:57.531098 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3700 13:43:57.537625 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3701 13:43:57.544414 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3702 13:43:57.547546 Write Rank1 MR3 =0xb0
3703 13:43:57.554216 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3704 13:43:57.561133 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3705 13:43:57.567842 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3706 13:43:57.570893 Write Rank0 MR3 =0xb0
3707 13:43:57.577748 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3708 13:43:57.584440 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3709 13:43:57.590998 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3710 13:43:57.594349 Write Rank1 MR3 =0xb0
3711 13:43:57.594426 DramC Write-DBI on
3712 13:43:57.598001 [GetDramInforAfterCalByMRR] Vendor 1.
3713 13:43:57.601300 [GetDramInforAfterCalByMRR] Revision 7.
3714 13:43:57.601375 MR8 12
3715 13:43:57.608412 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3716 13:43:57.608488 MR8 12
3717 13:43:57.611159 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3718 13:43:57.614647 MR8 12
3719 13:43:57.618303 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3720 13:43:57.618378 MR8 12
3721 13:43:57.624694 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3722 13:43:57.631419 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3723 13:43:57.634501 Write Rank0 MR13 =0xd0
3724 13:43:57.638026 Write Rank1 MR13 =0xd0
3725 13:43:57.638100 Write Rank0 MR13 =0xd0
3726 13:43:57.641371 Write Rank1 MR13 =0xd0
3727 13:43:57.644416 Save calibration result to emmc
3728 13:43:57.644490
3729 13:43:57.644548
3730 13:43:57.647801 [DramcModeReg_Check] Freq_1600, FSP_1
3731 13:43:57.647876 FSP_1, CH_0, RK0
3732 13:43:57.651117 Write Rank0 MR13 =0xd8
3733 13:43:57.654462 MR12 = 0x58 (global = 0x58) match
3734 13:43:57.657760 MR14 = 0x16 (global = 0x16) match
3735 13:43:57.657835 FSP_1, CH_0, RK1
3736 13:43:57.661120 Write Rank1 MR13 =0xd8
3737 13:43:57.664395 MR12 = 0x56 (global = 0x56) match
3738 13:43:57.667875 MR14 = 0x18 (global = 0x18) match
3739 13:43:57.667950 FSP_1, CH_1, RK0
3740 13:43:57.671364 Write Rank0 MR13 =0xd8
3741 13:43:57.674868 MR12 = 0x58 (global = 0x58) match
3742 13:43:57.678224 MR14 = 0x16 (global = 0x16) match
3743 13:43:57.678301 FSP_1, CH_1, RK1
3744 13:43:57.681445 Write Rank1 MR13 =0xd8
3745 13:43:57.685058 MR12 = 0x56 (global = 0x56) match
3746 13:43:57.688187 MR14 = 0x16 (global = 0x16) match
3747 13:43:57.688263
3748 13:43:57.691583 [MEM_TEST] 02: After DFS, before run time config
3749 13:43:57.702880 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3750 13:43:57.702957
3751 13:43:57.703016 [TA2_TEST]
3752 13:43:57.703069 === TA2 HW
3753 13:43:57.706213 TA2 PAT: XTALK
3754 13:43:57.709174 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3755 13:43:57.716104 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3756 13:43:57.719743 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3757 13:43:57.725850 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3758 13:43:57.725927
3759 13:43:57.725986
3760 13:43:57.726039 Settings after calibration
3761 13:43:57.726091
3762 13:43:57.729123 [DramcRunTimeConfig]
3763 13:43:57.732531 TransferPLLToSPMControl - MODE SW PHYPLL
3764 13:43:57.732607 TX_TRACKING: ON
3765 13:43:57.735968 RX_TRACKING: ON
3766 13:43:57.736043 HW_GATING: ON
3767 13:43:57.739399 HW_GATING DBG: OFF
3768 13:43:57.739475 ddr_geometry:1
3769 13:43:57.742572 ddr_geometry:1
3770 13:43:57.742647 ddr_geometry:1
3771 13:43:57.742706 ddr_geometry:1
3772 13:43:57.746097 ddr_geometry:1
3773 13:43:57.746172 ddr_geometry:1
3774 13:43:57.749117 ddr_geometry:1
3775 13:43:57.749198 ddr_geometry:1
3776 13:43:57.752682 High Freq DUMMY_READ_FOR_TRACKING: ON
3777 13:43:57.755966 ZQCS_ENABLE_LP4: OFF
3778 13:43:57.759362 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
3779 13:43:57.762767 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
3780 13:43:57.762843 SPM_CONTROL_AFTERK: ON
3781 13:43:57.765973 IMPEDANCE_TRACKING: ON
3782 13:43:57.766048 TEMP_SENSOR: ON
3783 13:43:57.769349 PER_BANK_REFRESH: ON
3784 13:43:57.769424 HW_SAVE_FOR_SR: ON
3785 13:43:57.772714 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3786 13:43:57.775936 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
3787 13:43:57.779036 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
3788 13:43:57.782455 Read ODT Tracking: ON
3789 13:43:57.785822 =========================
3790 13:43:57.785898
3791 13:43:57.785957 [TA2_TEST]
3792 13:43:57.786011 === TA2 HW
3793 13:43:57.792945 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
3794 13:43:57.796113 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
3795 13:43:57.802733 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
3796 13:43:57.805967 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
3797 13:43:57.806044
3798 13:43:57.809195 [MEM_TEST] 03: After run time config
3799 13:43:57.820471 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3800 13:43:57.823882 [complex_mem_test] start addr:0x40024000, len:131072
3801 13:43:58.028446 1st complex R/W mem test pass
3802 13:43:58.034477 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
3803 13:43:58.037864 sync preloader write leveling
3804 13:43:58.041579 sync preloader cbt_mr12
3805 13:43:58.041683 sync preloader cbt_clk_dly
3806 13:43:58.044611 sync preloader cbt_cmd_dly
3807 13:43:58.047987 sync preloader cbt_cs
3808 13:43:58.051409 sync preloader cbt_ca_perbit_delay
3809 13:43:58.051484 sync preloader clk_delay
3810 13:43:58.054751 sync preloader dqs_delay
3811 13:43:58.058218 sync preloader u1Gating2T_Save
3812 13:43:58.061165 sync preloader u1Gating05T_Save
3813 13:43:58.064802 sync preloader u1Gatingfine_tune_Save
3814 13:43:58.068187 sync preloader u1Gatingucpass_count_Save
3815 13:43:58.071298 sync preloader u1TxWindowPerbitVref_Save
3816 13:43:58.074850 sync preloader u1TxCenter_min_Save
3817 13:43:58.078057 sync preloader u1TxCenter_max_Save
3818 13:43:58.081232 sync preloader u1Txwin_center_Save
3819 13:43:58.084790 sync preloader u1Txfirst_pass_Save
3820 13:43:58.088217 sync preloader u1Txlast_pass_Save
3821 13:43:58.088292 sync preloader u1RxDatlat_Save
3822 13:43:58.091588 sync preloader u1RxWinPerbitVref_Save
3823 13:43:58.098166 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3824 13:43:58.101446 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3825 13:43:58.104702 sync preloader delay_cell_unit
3826 13:43:58.111484 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
3827 13:43:58.114708 sync preloader write leveling
3828 13:43:58.114783 sync preloader cbt_mr12
3829 13:43:58.118186 sync preloader cbt_clk_dly
3830 13:43:58.121315 sync preloader cbt_cmd_dly
3831 13:43:58.121390 sync preloader cbt_cs
3832 13:43:58.124614 sync preloader cbt_ca_perbit_delay
3833 13:43:58.128142 sync preloader clk_delay
3834 13:43:58.131498 sync preloader dqs_delay
3835 13:43:58.131574 sync preloader u1Gating2T_Save
3836 13:43:58.134508 sync preloader u1Gating05T_Save
3837 13:43:58.137939 sync preloader u1Gatingfine_tune_Save
3838 13:43:58.141475 sync preloader u1Gatingucpass_count_Save
3839 13:43:58.145056 sync preloader u1TxWindowPerbitVref_Save
3840 13:43:58.148089 sync preloader u1TxCenter_min_Save
3841 13:43:58.151448 sync preloader u1TxCenter_max_Save
3842 13:43:58.155062 sync preloader u1Txwin_center_Save
3843 13:43:58.158236 sync preloader u1Txfirst_pass_Save
3844 13:43:58.161801 sync preloader u1Txlast_pass_Save
3845 13:43:58.165126 sync preloader u1RxDatlat_Save
3846 13:43:58.168196 sync preloader u1RxWinPerbitVref_Save
3847 13:43:58.171504 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3848 13:43:58.174903 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3849 13:43:58.178422 sync preloader delay_cell_unit
3850 13:43:58.184737 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
3851 13:43:58.188362 sync preloader write leveling
3852 13:43:58.191741 sync preloader cbt_mr12
3853 13:43:58.191816 sync preloader cbt_clk_dly
3854 13:43:58.195082 sync preloader cbt_cmd_dly
3855 13:43:58.198518 sync preloader cbt_cs
3856 13:43:58.198594 sync preloader cbt_ca_perbit_delay
3857 13:43:58.201892 sync preloader clk_delay
3858 13:43:58.205060 sync preloader dqs_delay
3859 13:43:58.208186 sync preloader u1Gating2T_Save
3860 13:43:58.211528 sync preloader u1Gating05T_Save
3861 13:43:58.215213 sync preloader u1Gatingfine_tune_Save
3862 13:43:58.218289 sync preloader u1Gatingucpass_count_Save
3863 13:43:58.221682 sync preloader u1TxWindowPerbitVref_Save
3864 13:43:58.225207 sync preloader u1TxCenter_min_Save
3865 13:43:58.228436 sync preloader u1TxCenter_max_Save
3866 13:43:58.228510 sync preloader u1Txwin_center_Save
3867 13:43:58.231757 sync preloader u1Txfirst_pass_Save
3868 13:43:58.234975 sync preloader u1Txlast_pass_Save
3869 13:43:58.238852 sync preloader u1RxDatlat_Save
3870 13:43:58.241738 sync preloader u1RxWinPerbitVref_Save
3871 13:43:58.245247 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3872 13:43:58.251624 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3873 13:43:58.251699 sync preloader delay_cell_unit
3874 13:43:58.258472 just_for_test_dump_coreboot_params dump all params
3875 13:43:58.258547 dump source = 0x0
3876 13:43:58.261716 dump params frequency:1600
3877 13:43:58.265233 dump params rank number:2
3878 13:43:58.265355
3879 13:43:58.265414 dump params write leveling
3880 13:43:58.268311 write leveling[0][0][0] = 0x21
3881 13:43:58.271977 write leveling[0][0][1] = 0x1c
3882 13:43:58.275305 write leveling[0][1][0] = 0x22
3883 13:43:58.278354 write leveling[0][1][1] = 0x1e
3884 13:43:58.281789 write leveling[1][0][0] = 0x26
3885 13:43:58.281921 write leveling[1][0][1] = 0x21
3886 13:43:58.285095 write leveling[1][1][0] = 0x25
3887 13:43:58.288366 write leveling[1][1][1] = 0x1f
3888 13:43:58.291845 dump params cbt_cs
3889 13:43:58.292018 cbt_cs[0][0] = 0x8
3890 13:43:58.295113 cbt_cs[0][1] = 0x8
3891 13:43:58.295187 cbt_cs[1][0] = 0xc
3892 13:43:58.298422 cbt_cs[1][1] = 0xc
3893 13:43:58.298536 dump params cbt_mr12
3894 13:43:58.301679 cbt_mr12[0][0] = 0x18
3895 13:43:58.301772 cbt_mr12[0][1] = 0x16
3896 13:43:58.305144 cbt_mr12[1][0] = 0x18
3897 13:43:58.308231 cbt_mr12[1][1] = 0x16
3898 13:43:58.308307 dump params tx window
3899 13:43:58.311636 tx_center_min[0][0][0] = 979
3900 13:43:58.314991 tx_center_max[0][0][0] = 987
3901 13:43:58.318575 tx_center_min[0][0][1] = 974
3902 13:43:58.318651 tx_center_max[0][0][1] = 979
3903 13:43:58.321620 tx_center_min[0][1][0] = 981
3904 13:43:58.325431 tx_center_max[0][1][0] = 988
3905 13:43:58.328261 tx_center_min[0][1][1] = 978
3906 13:43:58.331702 tx_center_max[0][1][1] = 983
3907 13:43:58.331778 tx_center_min[1][0][0] = 984
3908 13:43:58.335368 tx_center_max[1][0][0] = 989
3909 13:43:58.338308 tx_center_min[1][0][1] = 980
3910 13:43:58.341884 tx_center_max[1][0][1] = 983
3911 13:43:58.341959 tx_center_min[1][1][0] = 983
3912 13:43:58.345086 tx_center_max[1][1][0] = 988
3913 13:43:58.348366 tx_center_min[1][1][1] = 976
3914 13:43:58.351674 tx_center_max[1][1][1] = 980
3915 13:43:58.351750 dump params tx window
3916 13:43:58.354748 tx_win_center[0][0][0] = 987
3917 13:43:58.358326 tx_first_pass[0][0][0] = 975
3918 13:43:58.361950 tx_last_pass[0][0][0] = 999
3919 13:43:58.365616 tx_win_center[0][0][1] = 986
3920 13:43:58.365691 tx_first_pass[0][0][1] = 975
3921 13:43:58.368230 tx_last_pass[0][0][1] = 998
3922 13:43:58.371818 tx_win_center[0][0][2] = 986
3923 13:43:58.374879 tx_first_pass[0][0][2] = 974
3924 13:43:58.374955 tx_last_pass[0][0][2] = 998
3925 13:43:58.378331 tx_win_center[0][0][3] = 979
3926 13:43:58.381580 tx_first_pass[0][0][3] = 968
3927 13:43:58.385181 tx_last_pass[0][0][3] = 991
3928 13:43:58.388449 tx_win_center[0][0][4] = 986
3929 13:43:58.388525 tx_first_pass[0][0][4] = 974
3930 13:43:58.391787 tx_last_pass[0][0][4] = 999
3931 13:43:58.395053 tx_win_center[0][0][5] = 981
3932 13:43:58.398202 tx_first_pass[0][0][5] = 970
3933 13:43:58.398277 tx_last_pass[0][0][5] = 993
3934 13:43:58.401835 tx_win_center[0][0][6] = 982
3935 13:43:58.405016 tx_first_pass[0][0][6] = 970
3936 13:43:58.408319 tx_last_pass[0][0][6] = 995
3937 13:43:58.411455 tx_win_center[0][0][7] = 984
3938 13:43:58.411530 tx_first_pass[0][0][7] = 971
3939 13:43:58.414828 tx_last_pass[0][0][7] = 997
3940 13:43:58.418309 tx_win_center[0][0][8] = 974
3941 13:43:58.421949 tx_first_pass[0][0][8] = 961
3942 13:43:58.422074 tx_last_pass[0][0][8] = 987
3943 13:43:58.424929 tx_win_center[0][0][9] = 975
3944 13:43:58.428205 tx_first_pass[0][0][9] = 963
3945 13:43:58.431595 tx_last_pass[0][0][9] = 988
3946 13:43:58.435172 tx_win_center[0][0][10] = 979
3947 13:43:58.435247 tx_first_pass[0][0][10] = 968
3948 13:43:58.438641 tx_last_pass[0][0][10] = 991
3949 13:43:58.441934 tx_win_center[0][0][11] = 975
3950 13:43:58.445046 tx_first_pass[0][0][11] = 962
3951 13:43:58.448298 tx_last_pass[0][0][11] = 988
3952 13:43:58.448385 tx_win_center[0][0][12] = 976
3953 13:43:58.451744 tx_first_pass[0][0][12] = 963
3954 13:43:58.455296 tx_last_pass[0][0][12] = 989
3955 13:43:58.458390 tx_win_center[0][0][13] = 974
3956 13:43:58.461669 tx_first_pass[0][0][13] = 962
3957 13:43:58.461777 tx_last_pass[0][0][13] = 987
3958 13:43:58.465178 tx_win_center[0][0][14] = 976
3959 13:43:58.468664 tx_first_pass[0][0][14] = 963
3960 13:43:58.471754 tx_last_pass[0][0][14] = 989
3961 13:43:58.475362 tx_win_center[0][0][15] = 978
3962 13:43:58.475436 tx_first_pass[0][0][15] = 966
3963 13:43:58.478494 tx_last_pass[0][0][15] = 990
3964 13:43:58.481675 tx_win_center[0][1][0] = 988
3965 13:43:58.485352 tx_first_pass[0][1][0] = 976
3966 13:43:58.485442 tx_last_pass[0][1][0] = 1001
3967 13:43:58.488914 tx_win_center[0][1][1] = 987
3968 13:43:58.491898 tx_first_pass[0][1][1] = 976
3969 13:43:58.494990 tx_last_pass[0][1][1] = 999
3970 13:43:58.498407 tx_win_center[0][1][2] = 987
3971 13:43:58.498482 tx_first_pass[0][1][2] = 976
3972 13:43:58.501839 tx_last_pass[0][1][2] = 999
3973 13:43:58.505143 tx_win_center[0][1][3] = 981
3974 13:43:58.508471 tx_first_pass[0][1][3] = 969
3975 13:43:58.508546 tx_last_pass[0][1][3] = 994
3976 13:43:58.511902 tx_win_center[0][1][4] = 988
3977 13:43:58.515207 tx_first_pass[0][1][4] = 976
3978 13:43:58.518483 tx_last_pass[0][1][4] = 1000
3979 13:43:58.521808 tx_win_center[0][1][5] = 982
3980 13:43:58.521884 tx_first_pass[0][1][5] = 970
3981 13:43:58.525193 tx_last_pass[0][1][5] = 994
3982 13:43:58.528472 tx_win_center[0][1][6] = 983
3983 13:43:58.531662 tx_first_pass[0][1][6] = 971
3984 13:43:58.531738 tx_last_pass[0][1][6] = 995
3985 13:43:58.535242 tx_win_center[0][1][7] = 986
3986 13:43:58.538434 tx_first_pass[0][1][7] = 974
3987 13:43:58.541722 tx_last_pass[0][1][7] = 998
3988 13:43:58.545041 tx_win_center[0][1][8] = 978
3989 13:43:58.545116 tx_first_pass[0][1][8] = 966
3990 13:43:58.548432 tx_last_pass[0][1][8] = 990
3991 13:43:58.551727 tx_win_center[0][1][9] = 978
3992 13:43:58.555343 tx_first_pass[0][1][9] = 967
3993 13:43:58.555419 tx_last_pass[0][1][9] = 990
3994 13:43:58.558429 tx_win_center[0][1][10] = 983
3995 13:43:58.561884 tx_first_pass[0][1][10] = 972
3996 13:43:58.565114 tx_last_pass[0][1][10] = 995
3997 13:43:58.568203 tx_win_center[0][1][11] = 978
3998 13:43:58.568279 tx_first_pass[0][1][11] = 966
3999 13:43:58.571739 tx_last_pass[0][1][11] = 990
4000 13:43:58.575447 tx_win_center[0][1][12] = 979
4001 13:43:58.578613 tx_first_pass[0][1][12] = 967
4002 13:43:58.581744 tx_last_pass[0][1][12] = 991
4003 13:43:58.581820 tx_win_center[0][1][13] = 978
4004 13:43:58.585515 tx_first_pass[0][1][13] = 967
4005 13:43:58.588338 tx_last_pass[0][1][13] = 990
4006 13:43:58.591681 tx_win_center[0][1][14] = 978
4007 13:43:58.595338 tx_first_pass[0][1][14] = 967
4008 13:43:58.595413 tx_last_pass[0][1][14] = 990
4009 13:43:58.598385 tx_win_center[0][1][15] = 980
4010 13:43:58.601728 tx_first_pass[0][1][15] = 969
4011 13:43:58.605122 tx_last_pass[0][1][15] = 992
4012 13:43:58.608487 tx_win_center[1][0][0] = 989
4013 13:43:58.608563 tx_first_pass[1][0][0] = 977
4014 13:43:58.611882 tx_last_pass[1][0][0] = 1001
4015 13:43:58.615252 tx_win_center[1][0][1] = 988
4016 13:43:58.618374 tx_first_pass[1][0][1] = 976
4017 13:43:58.621794 tx_last_pass[1][0][1] = 1000
4018 13:43:58.621873 tx_win_center[1][0][2] = 986
4019 13:43:58.625031 tx_first_pass[1][0][2] = 975
4020 13:43:58.628392 tx_last_pass[1][0][2] = 997
4021 13:43:58.631556 tx_win_center[1][0][3] = 984
4022 13:43:58.631634 tx_first_pass[1][0][3] = 973
4023 13:43:58.634932 tx_last_pass[1][0][3] = 996
4024 13:43:58.638325 tx_win_center[1][0][4] = 987
4025 13:43:58.642097 tx_first_pass[1][0][4] = 976
4026 13:43:58.645046 tx_last_pass[1][0][4] = 999
4027 13:43:58.645123 tx_win_center[1][0][5] = 988
4028 13:43:58.648338 tx_first_pass[1][0][5] = 977
4029 13:43:58.651806 tx_last_pass[1][0][5] = 1000
4030 13:43:58.655033 tx_win_center[1][0][6] = 989
4031 13:43:58.655107 tx_first_pass[1][0][6] = 977
4032 13:43:58.658499 tx_last_pass[1][0][6] = 1001
4033 13:43:58.661830 tx_win_center[1][0][7] = 987
4034 13:43:58.665146 tx_first_pass[1][0][7] = 976
4035 13:43:58.668374 tx_last_pass[1][0][7] = 999
4036 13:43:58.668450 tx_win_center[1][0][8] = 980
4037 13:43:58.671715 tx_first_pass[1][0][8] = 969
4038 13:43:58.675105 tx_last_pass[1][0][8] = 992
4039 13:43:58.678507 tx_win_center[1][0][9] = 980
4040 13:43:58.678584 tx_first_pass[1][0][9] = 969
4041 13:43:58.682050 tx_last_pass[1][0][9] = 992
4042 13:43:58.685647 tx_win_center[1][0][10] = 981
4043 13:43:58.688539 tx_first_pass[1][0][10] = 970
4044 13:43:58.692087 tx_last_pass[1][0][10] = 993
4045 13:43:58.692164 tx_win_center[1][0][11] = 982
4046 13:43:58.695112 tx_first_pass[1][0][11] = 970
4047 13:43:58.698512 tx_last_pass[1][0][11] = 994
4048 13:43:58.701981 tx_win_center[1][0][12] = 983
4049 13:43:58.705306 tx_first_pass[1][0][12] = 971
4050 13:43:58.705383 tx_last_pass[1][0][12] = 995
4051 13:43:58.708635 tx_win_center[1][0][13] = 982
4052 13:43:58.711805 tx_first_pass[1][0][13] = 971
4053 13:43:58.715039 tx_last_pass[1][0][13] = 994
4054 13:43:58.718802 tx_win_center[1][0][14] = 981
4055 13:43:58.718878 tx_first_pass[1][0][14] = 970
4056 13:43:58.722089 tx_last_pass[1][0][14] = 993
4057 13:43:58.725344 tx_win_center[1][0][15] = 980
4058 13:43:58.728782 tx_first_pass[1][0][15] = 968
4059 13:43:58.731733 tx_last_pass[1][0][15] = 992
4060 13:43:58.731810 tx_win_center[1][1][0] = 988
4061 13:43:58.735068 tx_first_pass[1][1][0] = 976
4062 13:43:58.738841 tx_last_pass[1][1][0] = 1001
4063 13:43:58.741996 tx_win_center[1][1][1] = 987
4064 13:43:58.745190 tx_first_pass[1][1][1] = 975
4065 13:43:58.745306 tx_last_pass[1][1][1] = 999
4066 13:43:58.748427 tx_win_center[1][1][2] = 984
4067 13:43:58.751795 tx_first_pass[1][1][2] = 971
4068 13:43:58.755693 tx_last_pass[1][1][2] = 997
4069 13:43:58.755769 tx_win_center[1][1][3] = 983
4070 13:43:58.758745 tx_first_pass[1][1][3] = 970
4071 13:43:58.762004 tx_last_pass[1][1][3] = 997
4072 13:43:58.765534 tx_win_center[1][1][4] = 986
4073 13:43:58.765609 tx_first_pass[1][1][4] = 974
4074 13:43:58.768881 tx_last_pass[1][1][4] = 998
4075 13:43:58.772404 tx_win_center[1][1][5] = 988
4076 13:43:58.775279 tx_first_pass[1][1][5] = 976
4077 13:43:58.778854 tx_last_pass[1][1][5] = 1000
4078 13:43:58.778931 tx_win_center[1][1][6] = 988
4079 13:43:58.782297 tx_first_pass[1][1][6] = 976
4080 13:43:58.785438 tx_last_pass[1][1][6] = 1001
4081 13:43:58.788739 tx_win_center[1][1][7] = 986
4082 13:43:58.791868 tx_first_pass[1][1][7] = 975
4083 13:43:58.791945 tx_last_pass[1][1][7] = 998
4084 13:43:58.795566 tx_win_center[1][1][8] = 978
4085 13:43:58.798587 tx_first_pass[1][1][8] = 965
4086 13:43:58.802085 tx_last_pass[1][1][8] = 991
4087 13:43:58.802160 tx_win_center[1][1][9] = 978
4088 13:43:58.805472 tx_first_pass[1][1][9] = 965
4089 13:43:58.808596 tx_last_pass[1][1][9] = 991
4090 13:43:58.812463 tx_win_center[1][1][10] = 979
4091 13:43:58.815309 tx_first_pass[1][1][10] = 967
4092 13:43:58.815386 tx_last_pass[1][1][10] = 991
4093 13:43:58.818869 tx_win_center[1][1][11] = 980
4094 13:43:58.822319 tx_first_pass[1][1][11] = 968
4095 13:43:58.825522 tx_last_pass[1][1][11] = 992
4096 13:43:58.825598 tx_win_center[1][1][12] = 980
4097 13:43:58.828924 tx_first_pass[1][1][12] = 969
4098 13:43:58.832312 tx_last_pass[1][1][12] = 992
4099 13:43:58.835750 tx_win_center[1][1][13] = 980
4100 13:43:58.838636 tx_first_pass[1][1][13] = 968
4101 13:43:58.842013 tx_last_pass[1][1][13] = 992
4102 13:43:58.842088 tx_win_center[1][1][14] = 980
4103 13:43:58.845450 tx_first_pass[1][1][14] = 968
4104 13:43:58.848758 tx_last_pass[1][1][14] = 992
4105 13:43:58.852362 tx_win_center[1][1][15] = 976
4106 13:43:58.852438 tx_first_pass[1][1][15] = 963
4107 13:43:58.855469 tx_last_pass[1][1][15] = 990
4108 13:43:58.859025 dump params rx window
4109 13:43:58.862122 rx_firspass[0][0][0] = 8
4110 13:43:58.862197 rx_lastpass[0][0][0] = 40
4111 13:43:58.865554 rx_firspass[0][0][1] = 7
4112 13:43:58.868909 rx_lastpass[0][0][1] = 39
4113 13:43:58.868985 rx_firspass[0][0][2] = 9
4114 13:43:58.872115 rx_lastpass[0][0][2] = 38
4115 13:43:58.875726 rx_firspass[0][0][3] = -3
4116 13:43:58.875801 rx_lastpass[0][0][3] = 29
4117 13:43:58.878749 rx_firspass[0][0][4] = 7
4118 13:43:58.882149 rx_lastpass[0][0][4] = 38
4119 13:43:58.885606 rx_firspass[0][0][5] = 0
4120 13:43:58.885682 rx_lastpass[0][0][5] = 30
4121 13:43:58.888812 rx_firspass[0][0][6] = 2
4122 13:43:58.892233 rx_lastpass[0][0][6] = 32
4123 13:43:58.892310 rx_firspass[0][0][7] = 4
4124 13:43:58.895807 rx_lastpass[0][0][7] = 32
4125 13:43:58.898869 rx_firspass[0][0][8] = 0
4126 13:43:58.898976 rx_lastpass[0][0][8] = 34
4127 13:43:58.902108 rx_firspass[0][0][9] = 5
4128 13:43:58.905476 rx_lastpass[0][0][9] = 34
4129 13:43:58.908689 rx_firspass[0][0][10] = 7
4130 13:43:58.908764 rx_lastpass[0][0][10] = 38
4131 13:43:58.912043 rx_firspass[0][0][11] = 1
4132 13:43:58.915713 rx_lastpass[0][0][11] = 34
4133 13:43:58.915790 rx_firspass[0][0][12] = 2
4134 13:43:58.918897 rx_lastpass[0][0][12] = 36
4135 13:43:58.922122 rx_firspass[0][0][13] = 3
4136 13:43:58.925492 rx_lastpass[0][0][13] = 30
4137 13:43:58.925568 rx_firspass[0][0][14] = 0
4138 13:43:58.928643 rx_lastpass[0][0][14] = 35
4139 13:43:58.932522 rx_firspass[0][0][15] = 3
4140 13:43:58.935359 rx_lastpass[0][0][15] = 36
4141 13:43:58.935435 rx_firspass[0][1][0] = 7
4142 13:43:58.939312 rx_lastpass[0][1][0] = 41
4143 13:43:58.942451 rx_firspass[0][1][1] = 6
4144 13:43:58.942526 rx_lastpass[0][1][1] = 40
4145 13:43:58.945326 rx_firspass[0][1][2] = 8
4146 13:43:58.948618 rx_lastpass[0][1][2] = 39
4147 13:43:58.948693 rx_firspass[0][1][3] = -3
4148 13:43:58.952091 rx_lastpass[0][1][3] = 31
4149 13:43:58.955353 rx_firspass[0][1][4] = 7
4150 13:43:58.958745 rx_lastpass[0][1][4] = 40
4151 13:43:58.958820 rx_firspass[0][1][5] = -1
4152 13:43:58.962175 rx_lastpass[0][1][5] = 33
4153 13:43:58.965646 rx_firspass[0][1][6] = 2
4154 13:43:58.965722 rx_lastpass[0][1][6] = 34
4155 13:43:58.968715 rx_firspass[0][1][7] = 3
4156 13:43:58.972055 rx_lastpass[0][1][7] = 34
4157 13:43:58.972130 rx_firspass[0][1][8] = 0
4158 13:43:58.975358 rx_lastpass[0][1][8] = 35
4159 13:43:58.978768 rx_firspass[0][1][9] = 3
4160 13:43:58.982217 rx_lastpass[0][1][9] = 36
4161 13:43:58.982292 rx_firspass[0][1][10] = 6
4162 13:43:58.985965 rx_lastpass[0][1][10] = 39
4163 13:43:58.988691 rx_firspass[0][1][11] = 0
4164 13:43:58.988790 rx_lastpass[0][1][11] = 34
4165 13:43:58.992125 rx_firspass[0][1][12] = 3
4166 13:43:58.995558 rx_lastpass[0][1][12] = 36
4167 13:43:58.998845 rx_firspass[0][1][13] = 2
4168 13:43:58.998945 rx_lastpass[0][1][13] = 33
4169 13:43:59.002322 rx_firspass[0][1][14] = 2
4170 13:43:59.005508 rx_lastpass[0][1][14] = 34
4171 13:43:59.005582 rx_firspass[0][1][15] = 3
4172 13:43:59.009074 rx_lastpass[0][1][15] = 37
4173 13:43:59.012652 rx_firspass[1][0][0] = 8
4174 13:43:59.015684 rx_lastpass[1][0][0] = 40
4175 13:43:59.015758 rx_firspass[1][0][1] = 7
4176 13:43:59.018874 rx_lastpass[1][0][1] = 39
4177 13:43:59.022197 rx_firspass[1][0][2] = 1
4178 13:43:59.022271 rx_lastpass[1][0][2] = 34
4179 13:43:59.025380 rx_firspass[1][0][3] = -2
4180 13:43:59.028922 rx_lastpass[1][0][3] = 32
4181 13:43:59.032171 rx_firspass[1][0][4] = 4
4182 13:43:59.032246 rx_lastpass[1][0][4] = 34
4183 13:43:59.035626 rx_firspass[1][0][5] = 8
4184 13:43:59.039010 rx_lastpass[1][0][5] = 40
4185 13:43:59.039084 rx_firspass[1][0][6] = 9
4186 13:43:59.042154 rx_lastpass[1][0][6] = 40
4187 13:43:59.045504 rx_firspass[1][0][7] = 4
4188 13:43:59.045578 rx_lastpass[1][0][7] = 35
4189 13:43:59.048942 rx_firspass[1][0][8] = 1
4190 13:43:59.052445 rx_lastpass[1][0][8] = 35
4191 13:43:59.052519 rx_firspass[1][0][9] = 1
4192 13:43:59.055492 rx_lastpass[1][0][9] = 35
4193 13:43:59.059023 rx_firspass[1][0][10] = 2
4194 13:43:59.062702 rx_lastpass[1][0][10] = 33
4195 13:43:59.062808 rx_firspass[1][0][11] = 2
4196 13:43:59.065871 rx_lastpass[1][0][11] = 36
4197 13:43:59.069159 rx_firspass[1][0][12] = 5
4198 13:43:59.072417 rx_lastpass[1][0][12] = 37
4199 13:43:59.072491 rx_firspass[1][0][13] = 3
4200 13:43:59.075946 rx_lastpass[1][0][13] = 35
4201 13:43:59.078870 rx_firspass[1][0][14] = 4
4202 13:43:59.078944 rx_lastpass[1][0][14] = 35
4203 13:43:59.082271 rx_firspass[1][0][15] = -1
4204 13:43:59.085610 rx_lastpass[1][0][15] = 31
4205 13:43:59.088965 rx_firspass[1][1][0] = 8
4206 13:43:59.089040 rx_lastpass[1][1][0] = 41
4207 13:43:59.092362 rx_firspass[1][1][1] = 7
4208 13:43:59.095876 rx_lastpass[1][1][1] = 41
4209 13:43:59.095950 rx_firspass[1][1][2] = 0
4210 13:43:59.099024 rx_lastpass[1][1][2] = 35
4211 13:43:59.102399 rx_firspass[1][1][3] = -2
4212 13:43:59.102473 rx_lastpass[1][1][3] = 32
4213 13:43:59.105704 rx_firspass[1][1][4] = 4
4214 13:43:59.109219 rx_lastpass[1][1][4] = 37
4215 13:43:59.112475 rx_firspass[1][1][5] = 7
4216 13:43:59.112551 rx_lastpass[1][1][5] = 40
4217 13:43:59.115631 rx_firspass[1][1][6] = 9
4218 13:43:59.118949 rx_lastpass[1][1][6] = 41
4219 13:43:59.119025 rx_firspass[1][1][7] = 4
4220 13:43:59.122309 rx_lastpass[1][1][7] = 37
4221 13:43:59.125825 rx_firspass[1][1][8] = 1
4222 13:43:59.125900 rx_lastpass[1][1][8] = 36
4223 13:43:59.129122 rx_firspass[1][1][9] = 1
4224 13:43:59.132678 rx_lastpass[1][1][9] = 36
4225 13:43:59.135969 rx_firspass[1][1][10] = 1
4226 13:43:59.136045 rx_lastpass[1][1][10] = 35
4227 13:43:59.138965 rx_firspass[1][1][11] = 3
4228 13:43:59.142545 rx_lastpass[1][1][11] = 36
4229 13:43:59.142620 rx_firspass[1][1][12] = 6
4230 13:43:59.145948 rx_lastpass[1][1][12] = 39
4231 13:43:59.149340 rx_firspass[1][1][13] = 5
4232 13:43:59.152505 rx_lastpass[1][1][13] = 38
4233 13:43:59.152581 rx_firspass[1][1][14] = 3
4234 13:43:59.155648 rx_lastpass[1][1][14] = 37
4235 13:43:59.159503 rx_firspass[1][1][15] = -1
4236 13:43:59.162486 rx_lastpass[1][1][15] = 32
4237 13:43:59.162562 dump params clk_delay
4238 13:43:59.166117 clk_delay[0] = 0
4239 13:43:59.166192 clk_delay[1] = 0
4240 13:43:59.169332 dump params dqs_delay
4241 13:43:59.169408 dqs_delay[0][0] = -1
4242 13:43:59.172670 dqs_delay[0][1] = 0
4243 13:43:59.172745 dqs_delay[1][0] = 0
4244 13:43:59.176008 dqs_delay[1][1] = 0
4245 13:43:59.179805 dump params delay_cell_unit = 762
4246 13:43:59.179880 dump source = 0x0
4247 13:43:59.182810 dump params frequency:1200
4248 13:43:59.186088 dump params rank number:2
4249 13:43:59.186164
4250 13:43:59.186222 dump params write leveling
4251 13:43:59.189207 write leveling[0][0][0] = 0x0
4252 13:43:59.192713 write leveling[0][0][1] = 0x0
4253 13:43:59.195837 write leveling[0][1][0] = 0x0
4254 13:43:59.199575 write leveling[0][1][1] = 0x0
4255 13:43:59.199650 write leveling[1][0][0] = 0x0
4256 13:43:59.202609 write leveling[1][0][1] = 0x0
4257 13:43:59.206054 write leveling[1][1][0] = 0x0
4258 13:43:59.209431 write leveling[1][1][1] = 0x0
4259 13:43:59.209506 dump params cbt_cs
4260 13:43:59.212955 cbt_cs[0][0] = 0x0
4261 13:43:59.213031 cbt_cs[0][1] = 0x0
4262 13:43:59.216160 cbt_cs[1][0] = 0x0
4263 13:43:59.216235 cbt_cs[1][1] = 0x0
4264 13:43:59.219399 dump params cbt_mr12
4265 13:43:59.222817 cbt_mr12[0][0] = 0x0
4266 13:43:59.222893 cbt_mr12[0][1] = 0x0
4267 13:43:59.226126 cbt_mr12[1][0] = 0x0
4268 13:43:59.226201 cbt_mr12[1][1] = 0x0
4269 13:43:59.229669 dump params tx window
4270 13:43:59.232655 tx_center_min[0][0][0] = 0
4271 13:43:59.232730 tx_center_max[0][0][0] = 0
4272 13:43:59.236333 tx_center_min[0][0][1] = 0
4273 13:43:59.239556 tx_center_max[0][0][1] = 0
4274 13:43:59.239632 tx_center_min[0][1][0] = 0
4275 13:43:59.242991 tx_center_max[0][1][0] = 0
4276 13:43:59.246058 tx_center_min[0][1][1] = 0
4277 13:43:59.249719 tx_center_max[0][1][1] = 0
4278 13:43:59.249794 tx_center_min[1][0][0] = 0
4279 13:43:59.252848 tx_center_max[1][0][0] = 0
4280 13:43:59.256428 tx_center_min[1][0][1] = 0
4281 13:43:59.260043 tx_center_max[1][0][1] = 0
4282 13:43:59.260119 tx_center_min[1][1][0] = 0
4283 13:43:59.262952 tx_center_max[1][1][0] = 0
4284 13:43:59.266435 tx_center_min[1][1][1] = 0
4285 13:43:59.270096 tx_center_max[1][1][1] = 0
4286 13:43:59.270172 dump params tx window
4287 13:43:59.273123 tx_win_center[0][0][0] = 0
4288 13:43:59.276387 tx_first_pass[0][0][0] = 0
4289 13:43:59.276463 tx_last_pass[0][0][0] = 0
4290 13:43:59.279842 tx_win_center[0][0][1] = 0
4291 13:43:59.283207 tx_first_pass[0][0][1] = 0
4292 13:43:59.283283 tx_last_pass[0][0][1] = 0
4293 13:43:59.286503 tx_win_center[0][0][2] = 0
4294 13:43:59.289871 tx_first_pass[0][0][2] = 0
4295 13:43:59.293110 tx_last_pass[0][0][2] = 0
4296 13:43:59.293184 tx_win_center[0][0][3] = 0
4297 13:43:59.296743 tx_first_pass[0][0][3] = 0
4298 13:43:59.300019 tx_last_pass[0][0][3] = 0
4299 13:43:59.303116 tx_win_center[0][0][4] = 0
4300 13:43:59.303192 tx_first_pass[0][0][4] = 0
4301 13:43:59.306546 tx_last_pass[0][0][4] = 0
4302 13:43:59.309671 tx_win_center[0][0][5] = 0
4303 13:43:59.309747 tx_first_pass[0][0][5] = 0
4304 13:43:59.313473 tx_last_pass[0][0][5] = 0
4305 13:43:59.316505 tx_win_center[0][0][6] = 0
4306 13:43:59.319887 tx_first_pass[0][0][6] = 0
4307 13:43:59.319962 tx_last_pass[0][0][6] = 0
4308 13:43:59.323309 tx_win_center[0][0][7] = 0
4309 13:43:59.326543 tx_first_pass[0][0][7] = 0
4310 13:43:59.326619 tx_last_pass[0][0][7] = 0
4311 13:43:59.330157 tx_win_center[0][0][8] = 0
4312 13:43:59.333265 tx_first_pass[0][0][8] = 0
4313 13:43:59.336390 tx_last_pass[0][0][8] = 0
4314 13:43:59.336466 tx_win_center[0][0][9] = 0
4315 13:43:59.339762 tx_first_pass[0][0][9] = 0
4316 13:43:59.342937 tx_last_pass[0][0][9] = 0
4317 13:43:59.346383 tx_win_center[0][0][10] = 0
4318 13:43:59.346459 tx_first_pass[0][0][10] = 0
4319 13:43:59.349589 tx_last_pass[0][0][10] = 0
4320 13:43:59.353170 tx_win_center[0][0][11] = 0
4321 13:43:59.356550 tx_first_pass[0][0][11] = 0
4322 13:43:59.356626 tx_last_pass[0][0][11] = 0
4323 13:43:59.359857 tx_win_center[0][0][12] = 0
4324 13:43:59.363602 tx_first_pass[0][0][12] = 0
4325 13:43:59.366963 tx_last_pass[0][0][12] = 0
4326 13:43:59.367039 tx_win_center[0][0][13] = 0
4327 13:43:59.369960 tx_first_pass[0][0][13] = 0
4328 13:43:59.373326 tx_last_pass[0][0][13] = 0
4329 13:43:59.376517 tx_win_center[0][0][14] = 0
4330 13:43:59.376592 tx_first_pass[0][0][14] = 0
4331 13:43:59.379750 tx_last_pass[0][0][14] = 0
4332 13:43:59.383491 tx_win_center[0][0][15] = 0
4333 13:43:59.386684 tx_first_pass[0][0][15] = 0
4334 13:43:59.386760 tx_last_pass[0][0][15] = 0
4335 13:43:59.389756 tx_win_center[0][1][0] = 0
4336 13:43:59.393133 tx_first_pass[0][1][0] = 0
4337 13:43:59.393208 tx_last_pass[0][1][0] = 0
4338 13:43:59.396460 tx_win_center[0][1][1] = 0
4339 13:43:59.399913 tx_first_pass[0][1][1] = 0
4340 13:43:59.403076 tx_last_pass[0][1][1] = 0
4341 13:43:59.403154 tx_win_center[0][1][2] = 0
4342 13:43:59.406426 tx_first_pass[0][1][2] = 0
4343 13:43:59.409877 tx_last_pass[0][1][2] = 0
4344 13:43:59.409952 tx_win_center[0][1][3] = 0
4345 13:43:59.413489 tx_first_pass[0][1][3] = 0
4346 13:43:59.416648 tx_last_pass[0][1][3] = 0
4347 13:43:59.420009 tx_win_center[0][1][4] = 0
4348 13:43:59.420084 tx_first_pass[0][1][4] = 0
4349 13:43:59.423120 tx_last_pass[0][1][4] = 0
4350 13:43:59.426756 tx_win_center[0][1][5] = 0
4351 13:43:59.429940 tx_first_pass[0][1][5] = 0
4352 13:43:59.430015 tx_last_pass[0][1][5] = 0
4353 13:43:59.433196 tx_win_center[0][1][6] = 0
4354 13:43:59.436757 tx_first_pass[0][1][6] = 0
4355 13:43:59.436832 tx_last_pass[0][1][6] = 0
4356 13:43:59.439810 tx_win_center[0][1][7] = 0
4357 13:43:59.443036 tx_first_pass[0][1][7] = 0
4358 13:43:59.446420 tx_last_pass[0][1][7] = 0
4359 13:43:59.446495 tx_win_center[0][1][8] = 0
4360 13:43:59.449773 tx_first_pass[0][1][8] = 0
4361 13:43:59.453430 tx_last_pass[0][1][8] = 0
4362 13:43:59.456650 tx_win_center[0][1][9] = 0
4363 13:43:59.456725 tx_first_pass[0][1][9] = 0
4364 13:43:59.460017 tx_last_pass[0][1][9] = 0
4365 13:43:59.463235 tx_win_center[0][1][10] = 0
4366 13:43:59.466898 tx_first_pass[0][1][10] = 0
4367 13:43:59.466974 tx_last_pass[0][1][10] = 0
4368 13:43:59.470216 tx_win_center[0][1][11] = 0
4369 13:43:59.473121 tx_first_pass[0][1][11] = 0
4370 13:43:59.473294 tx_last_pass[0][1][11] = 0
4371 13:43:59.476782 tx_win_center[0][1][12] = 0
4372 13:43:59.480031 tx_first_pass[0][1][12] = 0
4373 13:43:59.483111 tx_last_pass[0][1][12] = 0
4374 13:43:59.483186 tx_win_center[0][1][13] = 0
4375 13:43:59.486460 tx_first_pass[0][1][13] = 0
4376 13:43:59.489713 tx_last_pass[0][1][13] = 0
4377 13:43:59.493243 tx_win_center[0][1][14] = 0
4378 13:43:59.496601 tx_first_pass[0][1][14] = 0
4379 13:43:59.496676 tx_last_pass[0][1][14] = 0
4380 13:43:59.499655 tx_win_center[0][1][15] = 0
4381 13:43:59.503090 tx_first_pass[0][1][15] = 0
4382 13:43:59.503165 tx_last_pass[0][1][15] = 0
4383 13:43:59.506643 tx_win_center[1][0][0] = 0
4384 13:43:59.510056 tx_first_pass[1][0][0] = 0
4385 13:43:59.513211 tx_last_pass[1][0][0] = 0
4386 13:43:59.513295 tx_win_center[1][0][1] = 0
4387 13:43:59.516477 tx_first_pass[1][0][1] = 0
4388 13:43:59.520107 tx_last_pass[1][0][1] = 0
4389 13:43:59.523221 tx_win_center[1][0][2] = 0
4390 13:43:59.523296 tx_first_pass[1][0][2] = 0
4391 13:43:59.526699 tx_last_pass[1][0][2] = 0
4392 13:43:59.529922 tx_win_center[1][0][3] = 0
4393 13:43:59.529997 tx_first_pass[1][0][3] = 0
4394 13:43:59.533103 tx_last_pass[1][0][3] = 0
4395 13:43:59.536923 tx_win_center[1][0][4] = 0
4396 13:43:59.539979 tx_first_pass[1][0][4] = 0
4397 13:43:59.540054 tx_last_pass[1][0][4] = 0
4398 13:43:59.543375 tx_win_center[1][0][5] = 0
4399 13:43:59.546591 tx_first_pass[1][0][5] = 0
4400 13:43:59.546667 tx_last_pass[1][0][5] = 0
4401 13:43:59.550257 tx_win_center[1][0][6] = 0
4402 13:43:59.553515 tx_first_pass[1][0][6] = 0
4403 13:43:59.556792 tx_last_pass[1][0][6] = 0
4404 13:43:59.556867 tx_win_center[1][0][7] = 0
4405 13:43:59.560490 tx_first_pass[1][0][7] = 0
4406 13:43:59.563315 tx_last_pass[1][0][7] = 0
4407 13:43:59.567158 tx_win_center[1][0][8] = 0
4408 13:43:59.567233 tx_first_pass[1][0][8] = 0
4409 13:43:59.570261 tx_last_pass[1][0][8] = 0
4410 13:43:59.573414 tx_win_center[1][0][9] = 0
4411 13:43:59.573491 tx_first_pass[1][0][9] = 0
4412 13:43:59.576675 tx_last_pass[1][0][9] = 0
4413 13:43:59.580052 tx_win_center[1][0][10] = 0
4414 13:43:59.583498 tx_first_pass[1][0][10] = 0
4415 13:43:59.583574 tx_last_pass[1][0][10] = 0
4416 13:43:59.586934 tx_win_center[1][0][11] = 0
4417 13:43:59.590164 tx_first_pass[1][0][11] = 0
4418 13:43:59.593275 tx_last_pass[1][0][11] = 0
4419 13:43:59.593350 tx_win_center[1][0][12] = 0
4420 13:43:59.596621 tx_first_pass[1][0][12] = 0
4421 13:43:59.599860 tx_last_pass[1][0][12] = 0
4422 13:43:59.603397 tx_win_center[1][0][13] = 0
4423 13:43:59.603472 tx_first_pass[1][0][13] = 0
4424 13:43:59.606648 tx_last_pass[1][0][13] = 0
4425 13:43:59.609815 tx_win_center[1][0][14] = 0
4426 13:43:59.613459 tx_first_pass[1][0][14] = 0
4427 13:43:59.613534 tx_last_pass[1][0][14] = 0
4428 13:43:59.616669 tx_win_center[1][0][15] = 0
4429 13:43:59.620319 tx_first_pass[1][0][15] = 0
4430 13:43:59.623278 tx_last_pass[1][0][15] = 0
4431 13:43:59.623357 tx_win_center[1][1][0] = 0
4432 13:43:59.627062 tx_first_pass[1][1][0] = 0
4433 13:43:59.630124 tx_last_pass[1][1][0] = 0
4434 13:43:59.633367 tx_win_center[1][1][1] = 0
4435 13:43:59.633442 tx_first_pass[1][1][1] = 0
4436 13:43:59.636782 tx_last_pass[1][1][1] = 0
4437 13:43:59.640173 tx_win_center[1][1][2] = 0
4438 13:43:59.640248 tx_first_pass[1][1][2] = 0
4439 13:43:59.643616 tx_last_pass[1][1][2] = 0
4440 13:43:59.646888 tx_win_center[1][1][3] = 0
4441 13:43:59.650268 tx_first_pass[1][1][3] = 0
4442 13:43:59.650344 tx_last_pass[1][1][3] = 0
4443 13:43:59.653498 tx_win_center[1][1][4] = 0
4444 13:43:59.656919 tx_first_pass[1][1][4] = 0
4445 13:43:59.656994 tx_last_pass[1][1][4] = 0
4446 13:43:59.660055 tx_win_center[1][1][5] = 0
4447 13:43:59.663426 tx_first_pass[1][1][5] = 0
4448 13:43:59.667346 tx_last_pass[1][1][5] = 0
4449 13:43:59.667421 tx_win_center[1][1][6] = 0
4450 13:43:59.670107 tx_first_pass[1][1][6] = 0
4451 13:43:59.673851 tx_last_pass[1][1][6] = 0
4452 13:43:59.673927 tx_win_center[1][1][7] = 0
4453 13:43:59.676757 tx_first_pass[1][1][7] = 0
4454 13:43:59.680027 tx_last_pass[1][1][7] = 0
4455 13:43:59.683692 tx_win_center[1][1][8] = 0
4456 13:43:59.683768 tx_first_pass[1][1][8] = 0
4457 13:43:59.686730 tx_last_pass[1][1][8] = 0
4458 13:43:59.690345 tx_win_center[1][1][9] = 0
4459 13:43:59.693992 tx_first_pass[1][1][9] = 0
4460 13:43:59.694068 tx_last_pass[1][1][9] = 0
4461 13:43:59.696914 tx_win_center[1][1][10] = 0
4462 13:43:59.700073 tx_first_pass[1][1][10] = 0
4463 13:43:59.703421 tx_last_pass[1][1][10] = 0
4464 13:43:59.703497 tx_win_center[1][1][11] = 0
4465 13:43:59.707037 tx_first_pass[1][1][11] = 0
4466 13:43:59.710158 tx_last_pass[1][1][11] = 0
4467 13:43:59.713643 tx_win_center[1][1][12] = 0
4468 13:43:59.713719 tx_first_pass[1][1][12] = 0
4469 13:43:59.716984 tx_last_pass[1][1][12] = 0
4470 13:43:59.720138 tx_win_center[1][1][13] = 0
4471 13:43:59.723521 tx_first_pass[1][1][13] = 0
4472 13:43:59.723597 tx_last_pass[1][1][13] = 0
4473 13:43:59.726969 tx_win_center[1][1][14] = 0
4474 13:43:59.730580 tx_first_pass[1][1][14] = 0
4475 13:43:59.730656 tx_last_pass[1][1][14] = 0
4476 13:43:59.733770 tx_win_center[1][1][15] = 0
4477 13:43:59.737245 tx_first_pass[1][1][15] = 0
4478 13:43:59.740619 tx_last_pass[1][1][15] = 0
4479 13:43:59.740694 dump params rx window
4480 13:43:59.743855 rx_firspass[0][0][0] = 0
4481 13:43:59.747122 rx_lastpass[0][0][0] = 0
4482 13:43:59.747197 rx_firspass[0][0][1] = 0
4483 13:43:59.750612 rx_lastpass[0][0][1] = 0
4484 13:43:59.754248 rx_firspass[0][0][2] = 0
4485 13:43:59.754323 rx_lastpass[0][0][2] = 0
4486 13:43:59.757190 rx_firspass[0][0][3] = 0
4487 13:43:59.760607 rx_lastpass[0][0][3] = 0
4488 13:43:59.760682 rx_firspass[0][0][4] = 0
4489 13:43:59.763755 rx_lastpass[0][0][4] = 0
4490 13:43:59.767241 rx_firspass[0][0][5] = 0
4491 13:43:59.770680 rx_lastpass[0][0][5] = 0
4492 13:43:59.770756 rx_firspass[0][0][6] = 0
4493 13:43:59.773897 rx_lastpass[0][0][6] = 0
4494 13:43:59.777183 rx_firspass[0][0][7] = 0
4495 13:43:59.777297 rx_lastpass[0][0][7] = 0
4496 13:43:59.780506 rx_firspass[0][0][8] = 0
4497 13:43:59.783864 rx_lastpass[0][0][8] = 0
4498 13:43:59.783952 rx_firspass[0][0][9] = 0
4499 13:43:59.787539 rx_lastpass[0][0][9] = 0
4500 13:43:59.790443 rx_firspass[0][0][10] = 0
4501 13:43:59.790518 rx_lastpass[0][0][10] = 0
4502 13:43:59.793717 rx_firspass[0][0][11] = 0
4503 13:43:59.796975 rx_lastpass[0][0][11] = 0
4504 13:43:59.800119 rx_firspass[0][0][12] = 0
4505 13:43:59.800194 rx_lastpass[0][0][12] = 0
4506 13:43:59.803719 rx_firspass[0][0][13] = 0
4507 13:43:59.807394 rx_lastpass[0][0][13] = 0
4508 13:43:59.807470 rx_firspass[0][0][14] = 0
4509 13:43:59.810379 rx_lastpass[0][0][14] = 0
4510 13:43:59.813953 rx_firspass[0][0][15] = 0
4511 13:43:59.817217 rx_lastpass[0][0][15] = 0
4512 13:43:59.817332 rx_firspass[0][1][0] = 0
4513 13:43:59.820442 rx_lastpass[0][1][0] = 0
4514 13:43:59.824177 rx_firspass[0][1][1] = 0
4515 13:43:59.824252 rx_lastpass[0][1][1] = 0
4516 13:43:59.826908 rx_firspass[0][1][2] = 0
4517 13:43:59.830412 rx_lastpass[0][1][2] = 0
4518 13:43:59.830488 rx_firspass[0][1][3] = 0
4519 13:43:59.833751 rx_lastpass[0][1][3] = 0
4520 13:43:59.837096 rx_firspass[0][1][4] = 0
4521 13:43:59.837171 rx_lastpass[0][1][4] = 0
4522 13:43:59.840472 rx_firspass[0][1][5] = 0
4523 13:43:59.843818 rx_lastpass[0][1][5] = 0
4524 13:43:59.843894 rx_firspass[0][1][6] = 0
4525 13:43:59.847111 rx_lastpass[0][1][6] = 0
4526 13:43:59.850520 rx_firspass[0][1][7] = 0
4527 13:43:59.850595 rx_lastpass[0][1][7] = 0
4528 13:43:59.853780 rx_firspass[0][1][8] = 0
4529 13:43:59.857014 rx_lastpass[0][1][8] = 0
4530 13:43:59.860382 rx_firspass[0][1][9] = 0
4531 13:43:59.860458 rx_lastpass[0][1][9] = 0
4532 13:43:59.863729 rx_firspass[0][1][10] = 0
4533 13:43:59.867324 rx_lastpass[0][1][10] = 0
4534 13:43:59.867401 rx_firspass[0][1][11] = 0
4535 13:43:59.870912 rx_lastpass[0][1][11] = 0
4536 13:43:59.873876 rx_firspass[0][1][12] = 0
4537 13:43:59.873951 rx_lastpass[0][1][12] = 0
4538 13:43:59.877354 rx_firspass[0][1][13] = 0
4539 13:43:59.880510 rx_lastpass[0][1][13] = 0
4540 13:43:59.883795 rx_firspass[0][1][14] = 0
4541 13:43:59.883871 rx_lastpass[0][1][14] = 0
4542 13:43:59.887258 rx_firspass[0][1][15] = 0
4543 13:43:59.890674 rx_lastpass[0][1][15] = 0
4544 13:43:59.890750 rx_firspass[1][0][0] = 0
4545 13:43:59.894114 rx_lastpass[1][0][0] = 0
4546 13:43:59.897262 rx_firspass[1][0][1] = 0
4547 13:43:59.897352 rx_lastpass[1][0][1] = 0
4548 13:43:59.900879 rx_firspass[1][0][2] = 0
4549 13:43:59.903891 rx_lastpass[1][0][2] = 0
4550 13:43:59.903967 rx_firspass[1][0][3] = 0
4551 13:43:59.907643 rx_lastpass[1][0][3] = 0
4552 13:43:59.910973 rx_firspass[1][0][4] = 0
4553 13:43:59.914210 rx_lastpass[1][0][4] = 0
4554 13:43:59.914285 rx_firspass[1][0][5] = 0
4555 13:43:59.917825 rx_lastpass[1][0][5] = 0
4556 13:43:59.920771 rx_firspass[1][0][6] = 0
4557 13:43:59.920847 rx_lastpass[1][0][6] = 0
4558 13:43:59.924252 rx_firspass[1][0][7] = 0
4559 13:43:59.927400 rx_lastpass[1][0][7] = 0
4560 13:43:59.927476 rx_firspass[1][0][8] = 0
4561 13:43:59.930948 rx_lastpass[1][0][8] = 0
4562 13:43:59.934042 rx_firspass[1][0][9] = 0
4563 13:43:59.934116 rx_lastpass[1][0][9] = 0
4564 13:43:59.937512 rx_firspass[1][0][10] = 0
4565 13:43:59.940923 rx_lastpass[1][0][10] = 0
4566 13:43:59.940998 rx_firspass[1][0][11] = 0
4567 13:43:59.944204 rx_lastpass[1][0][11] = 0
4568 13:43:59.947545 rx_firspass[1][0][12] = 0
4569 13:43:59.950874 rx_lastpass[1][0][12] = 0
4570 13:43:59.950950 rx_firspass[1][0][13] = 0
4571 13:43:59.954094 rx_lastpass[1][0][13] = 0
4572 13:43:59.957480 rx_firspass[1][0][14] = 0
4573 13:43:59.957556 rx_lastpass[1][0][14] = 0
4574 13:43:59.960948 rx_firspass[1][0][15] = 0
4575 13:43:59.964170 rx_lastpass[1][0][15] = 0
4576 13:43:59.967523 rx_firspass[1][1][0] = 0
4577 13:43:59.967599 rx_lastpass[1][1][0] = 0
4578 13:43:59.970681 rx_firspass[1][1][1] = 0
4579 13:43:59.974190 rx_lastpass[1][1][1] = 0
4580 13:43:59.974276 rx_firspass[1][1][2] = 0
4581 13:43:59.977676 rx_lastpass[1][1][2] = 0
4582 13:43:59.981401 rx_firspass[1][1][3] = 0
4583 13:43:59.981476 rx_lastpass[1][1][3] = 0
4584 13:43:59.984202 rx_firspass[1][1][4] = 0
4585 13:43:59.987392 rx_lastpass[1][1][4] = 0
4586 13:43:59.987467 rx_firspass[1][1][5] = 0
4587 13:43:59.991072 rx_lastpass[1][1][5] = 0
4588 13:43:59.994219 rx_firspass[1][1][6] = 0
4589 13:43:59.994293 rx_lastpass[1][1][6] = 0
4590 13:43:59.997594 rx_firspass[1][1][7] = 0
4591 13:44:00.001106 rx_lastpass[1][1][7] = 0
4592 13:44:00.001180 rx_firspass[1][1][8] = 0
4593 13:44:00.004273 rx_lastpass[1][1][8] = 0
4594 13:44:00.007583 rx_firspass[1][1][9] = 0
4595 13:44:00.010912 rx_lastpass[1][1][9] = 0
4596 13:44:00.010987 rx_firspass[1][1][10] = 0
4597 13:44:00.014467 rx_lastpass[1][1][10] = 0
4598 13:44:00.017476 rx_firspass[1][1][11] = 0
4599 13:44:00.017551 rx_lastpass[1][1][11] = 0
4600 13:44:00.020843 rx_firspass[1][1][12] = 0
4601 13:44:00.024402 rx_lastpass[1][1][12] = 0
4602 13:44:00.027544 rx_firspass[1][1][13] = 0
4603 13:44:00.027620 rx_lastpass[1][1][13] = 0
4604 13:44:00.031044 rx_firspass[1][1][14] = 0
4605 13:44:00.034388 rx_lastpass[1][1][14] = 0
4606 13:44:00.034463 rx_firspass[1][1][15] = 0
4607 13:44:00.037790 rx_lastpass[1][1][15] = 0
4608 13:44:00.040799 dump params clk_delay
4609 13:44:00.040873 clk_delay[0] = 0
4610 13:44:00.044435 clk_delay[1] = 0
4611 13:44:00.044510 dump params dqs_delay
4612 13:44:00.047990 dqs_delay[0][0] = 0
4613 13:44:00.048065 dqs_delay[0][1] = 0
4614 13:44:00.051219 dqs_delay[1][0] = 0
4615 13:44:00.051295 dqs_delay[1][1] = 0
4616 13:44:00.054456 dump params delay_cell_unit = 762
4617 13:44:00.057844 dump source = 0x0
4618 13:44:00.057919 dump params frequency:800
4619 13:44:00.061037 dump params rank number:2
4620 13:44:00.061111
4621 13:44:00.064326 dump params write leveling
4622 13:44:00.067964 write leveling[0][0][0] = 0x0
4623 13:44:00.071132 write leveling[0][0][1] = 0x0
4624 13:44:00.071206 write leveling[0][1][0] = 0x0
4625 13:44:00.074472 write leveling[0][1][1] = 0x0
4626 13:44:00.077887 write leveling[1][0][0] = 0x0
4627 13:44:00.081205 write leveling[1][0][1] = 0x0
4628 13:44:00.084418 write leveling[1][1][0] = 0x0
4629 13:44:00.084493 write leveling[1][1][1] = 0x0
4630 13:44:00.087795 dump params cbt_cs
4631 13:44:00.087868 cbt_cs[0][0] = 0x0
4632 13:44:00.091133 cbt_cs[0][1] = 0x0
4633 13:44:00.091208 cbt_cs[1][0] = 0x0
4634 13:44:00.094451 cbt_cs[1][1] = 0x0
4635 13:44:00.094525 dump params cbt_mr12
4636 13:44:00.097827 cbt_mr12[0][0] = 0x0
4637 13:44:00.101191 cbt_mr12[0][1] = 0x0
4638 13:44:00.101284 cbt_mr12[1][0] = 0x0
4639 13:44:00.104477 cbt_mr12[1][1] = 0x0
4640 13:44:00.104553 dump params tx window
4641 13:44:00.107797 tx_center_min[0][0][0] = 0
4642 13:44:00.111241 tx_center_max[0][0][0] = 0
4643 13:44:00.114681 tx_center_min[0][0][1] = 0
4644 13:44:00.114756 tx_center_max[0][0][1] = 0
4645 13:44:00.118031 tx_center_min[0][1][0] = 0
4646 13:44:00.121701 tx_center_max[0][1][0] = 0
4647 13:44:00.121777 tx_center_min[0][1][1] = 0
4648 13:44:00.124350 tx_center_max[0][1][1] = 0
4649 13:44:00.127820 tx_center_min[1][0][0] = 0
4650 13:44:00.131056 tx_center_max[1][0][0] = 0
4651 13:44:00.131132 tx_center_min[1][0][1] = 0
4652 13:44:00.134658 tx_center_max[1][0][1] = 0
4653 13:44:00.138062 tx_center_min[1][1][0] = 0
4654 13:44:00.141335 tx_center_max[1][1][0] = 0
4655 13:44:00.141411 tx_center_min[1][1][1] = 0
4656 13:44:00.144612 tx_center_max[1][1][1] = 0
4657 13:44:00.147916 dump params tx window
4658 13:44:00.147991 tx_win_center[0][0][0] = 0
4659 13:44:00.151367 tx_first_pass[0][0][0] = 0
4660 13:44:00.155079 tx_last_pass[0][0][0] = 0
4661 13:44:00.158297 tx_win_center[0][0][1] = 0
4662 13:44:00.158372 tx_first_pass[0][0][1] = 0
4663 13:44:00.161398 tx_last_pass[0][0][1] = 0
4664 13:44:00.164822 tx_win_center[0][0][2] = 0
4665 13:44:00.164898 tx_first_pass[0][0][2] = 0
4666 13:44:00.168163 tx_last_pass[0][0][2] = 0
4667 13:44:00.171546 tx_win_center[0][0][3] = 0
4668 13:44:00.174556 tx_first_pass[0][0][3] = 0
4669 13:44:00.174631 tx_last_pass[0][0][3] = 0
4670 13:44:00.178139 tx_win_center[0][0][4] = 0
4671 13:44:00.181543 tx_first_pass[0][0][4] = 0
4672 13:44:00.181618 tx_last_pass[0][0][4] = 0
4673 13:44:00.184730 tx_win_center[0][0][5] = 0
4674 13:44:00.188035 tx_first_pass[0][0][5] = 0
4675 13:44:00.191761 tx_last_pass[0][0][5] = 0
4676 13:44:00.191835 tx_win_center[0][0][6] = 0
4677 13:44:00.194880 tx_first_pass[0][0][6] = 0
4678 13:44:00.198116 tx_last_pass[0][0][6] = 0
4679 13:44:00.201540 tx_win_center[0][0][7] = 0
4680 13:44:00.201614 tx_first_pass[0][0][7] = 0
4681 13:44:00.204655 tx_last_pass[0][0][7] = 0
4682 13:44:00.208209 tx_win_center[0][0][8] = 0
4683 13:44:00.208283 tx_first_pass[0][0][8] = 0
4684 13:44:00.211414 tx_last_pass[0][0][8] = 0
4685 13:44:00.215051 tx_win_center[0][0][9] = 0
4686 13:44:00.218288 tx_first_pass[0][0][9] = 0
4687 13:44:00.218361 tx_last_pass[0][0][9] = 0
4688 13:44:00.221621 tx_win_center[0][0][10] = 0
4689 13:44:00.225075 tx_first_pass[0][0][10] = 0
4690 13:44:00.228207 tx_last_pass[0][0][10] = 0
4691 13:44:00.228280 tx_win_center[0][0][11] = 0
4692 13:44:00.231500 tx_first_pass[0][0][11] = 0
4693 13:44:00.234737 tx_last_pass[0][0][11] = 0
4694 13:44:00.238382 tx_win_center[0][0][12] = 0
4695 13:44:00.238456 tx_first_pass[0][0][12] = 0
4696 13:44:00.241584 tx_last_pass[0][0][12] = 0
4697 13:44:00.244855 tx_win_center[0][0][13] = 0
4698 13:44:00.248362 tx_first_pass[0][0][13] = 0
4699 13:44:00.248436 tx_last_pass[0][0][13] = 0
4700 13:44:00.251377 tx_win_center[0][0][14] = 0
4701 13:44:00.255003 tx_first_pass[0][0][14] = 0
4702 13:44:00.258204 tx_last_pass[0][0][14] = 0
4703 13:44:00.258278 tx_win_center[0][0][15] = 0
4704 13:44:00.262075 tx_first_pass[0][0][15] = 0
4705 13:44:00.264813 tx_last_pass[0][0][15] = 0
4706 13:44:00.264888 tx_win_center[0][1][0] = 0
4707 13:44:00.268512 tx_first_pass[0][1][0] = 0
4708 13:44:00.271509 tx_last_pass[0][1][0] = 0
4709 13:44:00.274823 tx_win_center[0][1][1] = 0
4710 13:44:00.274896 tx_first_pass[0][1][1] = 0
4711 13:44:00.278255 tx_last_pass[0][1][1] = 0
4712 13:44:00.281831 tx_win_center[0][1][2] = 0
4713 13:44:00.285001 tx_first_pass[0][1][2] = 0
4714 13:44:00.285074 tx_last_pass[0][1][2] = 0
4715 13:44:00.288377 tx_win_center[0][1][3] = 0
4716 13:44:00.291816 tx_first_pass[0][1][3] = 0
4717 13:44:00.291889 tx_last_pass[0][1][3] = 0
4718 13:44:00.295571 tx_win_center[0][1][4] = 0
4719 13:44:00.298214 tx_first_pass[0][1][4] = 0
4720 13:44:00.301910 tx_last_pass[0][1][4] = 0
4721 13:44:00.301983 tx_win_center[0][1][5] = 0
4722 13:44:00.304969 tx_first_pass[0][1][5] = 0
4723 13:44:00.308406 tx_last_pass[0][1][5] = 0
4724 13:44:00.308479 tx_win_center[0][1][6] = 0
4725 13:44:00.311832 tx_first_pass[0][1][6] = 0
4726 13:44:00.315126 tx_last_pass[0][1][6] = 0
4727 13:44:00.318603 tx_win_center[0][1][7] = 0
4728 13:44:00.318694 tx_first_pass[0][1][7] = 0
4729 13:44:00.321722 tx_last_pass[0][1][7] = 0
4730 13:44:00.325144 tx_win_center[0][1][8] = 0
4731 13:44:00.328483 tx_first_pass[0][1][8] = 0
4732 13:44:00.328557 tx_last_pass[0][1][8] = 0
4733 13:44:00.331682 tx_win_center[0][1][9] = 0
4734 13:44:00.335142 tx_first_pass[0][1][9] = 0
4735 13:44:00.335215 tx_last_pass[0][1][9] = 0
4736 13:44:00.338497 tx_win_center[0][1][10] = 0
4737 13:44:00.341898 tx_first_pass[0][1][10] = 0
4738 13:44:00.345547 tx_last_pass[0][1][10] = 0
4739 13:44:00.345621 tx_win_center[0][1][11] = 0
4740 13:44:00.348666 tx_first_pass[0][1][11] = 0
4741 13:44:00.352180 tx_last_pass[0][1][11] = 0
4742 13:44:00.355044 tx_win_center[0][1][12] = 0
4743 13:44:00.355118 tx_first_pass[0][1][12] = 0
4744 13:44:00.358524 tx_last_pass[0][1][12] = 0
4745 13:44:00.361878 tx_win_center[0][1][13] = 0
4746 13:44:00.365172 tx_first_pass[0][1][13] = 0
4747 13:44:00.365314 tx_last_pass[0][1][13] = 0
4748 13:44:00.368620 tx_win_center[0][1][14] = 0
4749 13:44:00.371879 tx_first_pass[0][1][14] = 0
4750 13:44:00.375249 tx_last_pass[0][1][14] = 0
4751 13:44:00.375324 tx_win_center[0][1][15] = 0
4752 13:44:00.378783 tx_first_pass[0][1][15] = 0
4753 13:44:00.381784 tx_last_pass[0][1][15] = 0
4754 13:44:00.385047 tx_win_center[1][0][0] = 0
4755 13:44:00.385121 tx_first_pass[1][0][0] = 0
4756 13:44:00.388458 tx_last_pass[1][0][0] = 0
4757 13:44:00.391993 tx_win_center[1][0][1] = 0
4758 13:44:00.395195 tx_first_pass[1][0][1] = 0
4759 13:44:00.395269 tx_last_pass[1][0][1] = 0
4760 13:44:00.398557 tx_win_center[1][0][2] = 0
4761 13:44:00.402240 tx_first_pass[1][0][2] = 0
4762 13:44:00.402315 tx_last_pass[1][0][2] = 0
4763 13:44:00.405469 tx_win_center[1][0][3] = 0
4764 13:44:00.408615 tx_first_pass[1][0][3] = 0
4765 13:44:00.412073 tx_last_pass[1][0][3] = 0
4766 13:44:00.412147 tx_win_center[1][0][4] = 0
4767 13:44:00.415265 tx_first_pass[1][0][4] = 0
4768 13:44:00.418589 tx_last_pass[1][0][4] = 0
4769 13:44:00.418664 tx_win_center[1][0][5] = 0
4770 13:44:00.421960 tx_first_pass[1][0][5] = 0
4771 13:44:00.425353 tx_last_pass[1][0][5] = 0
4772 13:44:00.428633 tx_win_center[1][0][6] = 0
4773 13:44:00.428707 tx_first_pass[1][0][6] = 0
4774 13:44:00.432060 tx_last_pass[1][0][6] = 0
4775 13:44:00.435395 tx_win_center[1][0][7] = 0
4776 13:44:00.438482 tx_first_pass[1][0][7] = 0
4777 13:44:00.438580 tx_last_pass[1][0][7] = 0
4778 13:44:00.442438 tx_win_center[1][0][8] = 0
4779 13:44:00.445195 tx_first_pass[1][0][8] = 0
4780 13:44:00.445298 tx_last_pass[1][0][8] = 0
4781 13:44:00.448770 tx_win_center[1][0][9] = 0
4782 13:44:00.451951 tx_first_pass[1][0][9] = 0
4783 13:44:00.455523 tx_last_pass[1][0][9] = 0
4784 13:44:00.455598 tx_win_center[1][0][10] = 0
4785 13:44:00.458476 tx_first_pass[1][0][10] = 0
4786 13:44:00.461883 tx_last_pass[1][0][10] = 0
4787 13:44:00.465423 tx_win_center[1][0][11] = 0
4788 13:44:00.465498 tx_first_pass[1][0][11] = 0
4789 13:44:00.468570 tx_last_pass[1][0][11] = 0
4790 13:44:00.471955 tx_win_center[1][0][12] = 0
4791 13:44:00.475477 tx_first_pass[1][0][12] = 0
4792 13:44:00.475551 tx_last_pass[1][0][12] = 0
4793 13:44:00.478871 tx_win_center[1][0][13] = 0
4794 13:44:00.481922 tx_first_pass[1][0][13] = 0
4795 13:44:00.485472 tx_last_pass[1][0][13] = 0
4796 13:44:00.485546 tx_win_center[1][0][14] = 0
4797 13:44:00.488760 tx_first_pass[1][0][14] = 0
4798 13:44:00.492144 tx_last_pass[1][0][14] = 0
4799 13:44:00.495307 tx_win_center[1][0][15] = 0
4800 13:44:00.495381 tx_first_pass[1][0][15] = 0
4801 13:44:00.498861 tx_last_pass[1][0][15] = 0
4802 13:44:00.501958 tx_win_center[1][1][0] = 0
4803 13:44:00.505665 tx_first_pass[1][1][0] = 0
4804 13:44:00.505740 tx_last_pass[1][1][0] = 0
4805 13:44:00.508699 tx_win_center[1][1][1] = 0
4806 13:44:00.512179 tx_first_pass[1][1][1] = 0
4807 13:44:00.512253 tx_last_pass[1][1][1] = 0
4808 13:44:00.515628 tx_win_center[1][1][2] = 0
4809 13:44:00.518856 tx_first_pass[1][1][2] = 0
4810 13:44:00.522133 tx_last_pass[1][1][2] = 0
4811 13:44:00.522209 tx_win_center[1][1][3] = 0
4812 13:44:00.525609 tx_first_pass[1][1][3] = 0
4813 13:44:00.528966 tx_last_pass[1][1][3] = 0
4814 13:44:00.529041 tx_win_center[1][1][4] = 0
4815 13:44:00.532083 tx_first_pass[1][1][4] = 0
4816 13:44:00.535363 tx_last_pass[1][1][4] = 0
4817 13:44:00.538865 tx_win_center[1][1][5] = 0
4818 13:44:00.538941 tx_first_pass[1][1][5] = 0
4819 13:44:00.542323 tx_last_pass[1][1][5] = 0
4820 13:44:00.545585 tx_win_center[1][1][6] = 0
4821 13:44:00.545661 tx_first_pass[1][1][6] = 0
4822 13:44:00.548756 tx_last_pass[1][1][6] = 0
4823 13:44:00.552141 tx_win_center[1][1][7] = 0
4824 13:44:00.555279 tx_first_pass[1][1][7] = 0
4825 13:44:00.555355 tx_last_pass[1][1][7] = 0
4826 13:44:00.559038 tx_win_center[1][1][8] = 0
4827 13:44:00.562141 tx_first_pass[1][1][8] = 0
4828 13:44:00.565347 tx_last_pass[1][1][8] = 0
4829 13:44:00.565460 tx_win_center[1][1][9] = 0
4830 13:44:00.568838 tx_first_pass[1][1][9] = 0
4831 13:44:00.572298 tx_last_pass[1][1][9] = 0
4832 13:44:00.572374 tx_win_center[1][1][10] = 0
4833 13:44:00.575623 tx_first_pass[1][1][10] = 0
4834 13:44:00.578745 tx_last_pass[1][1][10] = 0
4835 13:44:00.582092 tx_win_center[1][1][11] = 0
4836 13:44:00.585623 tx_first_pass[1][1][11] = 0
4837 13:44:00.585698 tx_last_pass[1][1][11] = 0
4838 13:44:00.588795 tx_win_center[1][1][12] = 0
4839 13:44:00.592027 tx_first_pass[1][1][12] = 0
4840 13:44:00.595392 tx_last_pass[1][1][12] = 0
4841 13:44:00.595468 tx_win_center[1][1][13] = 0
4842 13:44:00.598961 tx_first_pass[1][1][13] = 0
4843 13:44:00.602033 tx_last_pass[1][1][13] = 0
4844 13:44:00.602108 tx_win_center[1][1][14] = 0
4845 13:44:00.605737 tx_first_pass[1][1][14] = 0
4846 13:44:00.608760 tx_last_pass[1][1][14] = 0
4847 13:44:00.612020 tx_win_center[1][1][15] = 0
4848 13:44:00.615318 tx_first_pass[1][1][15] = 0
4849 13:44:00.615393 tx_last_pass[1][1][15] = 0
4850 13:44:00.618678 dump params rx window
4851 13:44:00.618754 rx_firspass[0][0][0] = 0
4852 13:44:00.622352 rx_lastpass[0][0][0] = 0
4853 13:44:00.625646 rx_firspass[0][0][1] = 0
4854 13:44:00.628801 rx_lastpass[0][0][1] = 0
4855 13:44:00.628876 rx_firspass[0][0][2] = 0
4856 13:44:00.632144 rx_lastpass[0][0][2] = 0
4857 13:44:00.635794 rx_firspass[0][0][3] = 0
4858 13:44:00.635869 rx_lastpass[0][0][3] = 0
4859 13:44:00.638799 rx_firspass[0][0][4] = 0
4860 13:44:00.642174 rx_lastpass[0][0][4] = 0
4861 13:44:00.642249 rx_firspass[0][0][5] = 0
4862 13:44:00.645579 rx_lastpass[0][0][5] = 0
4863 13:44:00.648808 rx_firspass[0][0][6] = 0
4864 13:44:00.648883 rx_lastpass[0][0][6] = 0
4865 13:44:00.652155 rx_firspass[0][0][7] = 0
4866 13:44:00.655492 rx_lastpass[0][0][7] = 0
4867 13:44:00.655567 rx_firspass[0][0][8] = 0
4868 13:44:00.659114 rx_lastpass[0][0][8] = 0
4869 13:44:00.662564 rx_firspass[0][0][9] = 0
4870 13:44:00.662640 rx_lastpass[0][0][9] = 0
4871 13:44:00.665451 rx_firspass[0][0][10] = 0
4872 13:44:00.669051 rx_lastpass[0][0][10] = 0
4873 13:44:00.672434 rx_firspass[0][0][11] = 0
4874 13:44:00.672510 rx_lastpass[0][0][11] = 0
4875 13:44:00.675977 rx_firspass[0][0][12] = 0
4876 13:44:00.679327 rx_lastpass[0][0][12] = 0
4877 13:44:00.679402 rx_firspass[0][0][13] = 0
4878 13:44:00.682705 rx_lastpass[0][0][13] = 0
4879 13:44:00.685773 rx_firspass[0][0][14] = 0
4880 13:44:00.689201 rx_lastpass[0][0][14] = 0
4881 13:44:00.689318 rx_firspass[0][0][15] = 0
4882 13:44:00.692417 rx_lastpass[0][0][15] = 0
4883 13:44:00.695738 rx_firspass[0][1][0] = 0
4884 13:44:00.695813 rx_lastpass[0][1][0] = 0
4885 13:44:00.699419 rx_firspass[0][1][1] = 0
4886 13:44:00.702642 rx_lastpass[0][1][1] = 0
4887 13:44:00.702717 rx_firspass[0][1][2] = 0
4888 13:44:00.706029 rx_lastpass[0][1][2] = 0
4889 13:44:00.709119 rx_firspass[0][1][3] = 0
4890 13:44:00.709194 rx_lastpass[0][1][3] = 0
4891 13:44:00.713069 rx_firspass[0][1][4] = 0
4892 13:44:00.715911 rx_lastpass[0][1][4] = 0
4893 13:44:00.715987 rx_firspass[0][1][5] = 0
4894 13:44:00.719176 rx_lastpass[0][1][5] = 0
4895 13:44:00.722934 rx_firspass[0][1][6] = 0
4896 13:44:00.723010 rx_lastpass[0][1][6] = 0
4897 13:44:00.726176 rx_firspass[0][1][7] = 0
4898 13:44:00.729348 rx_lastpass[0][1][7] = 0
4899 13:44:00.729423 rx_firspass[0][1][8] = 0
4900 13:44:00.733058 rx_lastpass[0][1][8] = 0
4901 13:44:00.736117 rx_firspass[0][1][9] = 0
4902 13:44:00.739356 rx_lastpass[0][1][9] = 0
4903 13:44:00.739432 rx_firspass[0][1][10] = 0
4904 13:44:00.742719 rx_lastpass[0][1][10] = 0
4905 13:44:00.746238 rx_firspass[0][1][11] = 0
4906 13:44:00.746317 rx_lastpass[0][1][11] = 0
4907 13:44:00.749603 rx_firspass[0][1][12] = 0
4908 13:44:00.753173 rx_lastpass[0][1][12] = 0
4909 13:44:00.756071 rx_firspass[0][1][13] = 0
4910 13:44:00.756147 rx_lastpass[0][1][13] = 0
4911 13:44:00.759274 rx_firspass[0][1][14] = 0
4912 13:44:00.763017 rx_lastpass[0][1][14] = 0
4913 13:44:00.763092 rx_firspass[0][1][15] = 0
4914 13:44:00.766293 rx_lastpass[0][1][15] = 0
4915 13:44:00.769545 rx_firspass[1][0][0] = 0
4916 13:44:00.769620 rx_lastpass[1][0][0] = 0
4917 13:44:00.772816 rx_firspass[1][0][1] = 0
4918 13:44:00.776418 rx_lastpass[1][0][1] = 0
4919 13:44:00.776494 rx_firspass[1][0][2] = 0
4920 13:44:00.779573 rx_lastpass[1][0][2] = 0
4921 13:44:00.783080 rx_firspass[1][0][3] = 0
4922 13:44:00.786634 rx_lastpass[1][0][3] = 0
4923 13:44:00.786710 rx_firspass[1][0][4] = 0
4924 13:44:00.789516 rx_lastpass[1][0][4] = 0
4925 13:44:00.792895 rx_firspass[1][0][5] = 0
4926 13:44:00.792970 rx_lastpass[1][0][5] = 0
4927 13:44:00.796242 rx_firspass[1][0][6] = 0
4928 13:44:00.799744 rx_lastpass[1][0][6] = 0
4929 13:44:00.799820 rx_firspass[1][0][7] = 0
4930 13:44:00.802961 rx_lastpass[1][0][7] = 0
4931 13:44:00.806487 rx_firspass[1][0][8] = 0
4932 13:44:00.806563 rx_lastpass[1][0][8] = 0
4933 13:44:00.809434 rx_firspass[1][0][9] = 0
4934 13:44:00.812949 rx_lastpass[1][0][9] = 0
4935 13:44:00.813024 rx_firspass[1][0][10] = 0
4936 13:44:00.816258 rx_lastpass[1][0][10] = 0
4937 13:44:00.819784 rx_firspass[1][0][11] = 0
4938 13:44:00.823225 rx_lastpass[1][0][11] = 0
4939 13:44:00.823300 rx_firspass[1][0][12] = 0
4940 13:44:00.826363 rx_lastpass[1][0][12] = 0
4941 13:44:00.829805 rx_firspass[1][0][13] = 0
4942 13:44:00.829880 rx_lastpass[1][0][13] = 0
4943 13:44:00.832884 rx_firspass[1][0][14] = 0
4944 13:44:00.836050 rx_lastpass[1][0][14] = 0
4945 13:44:00.839650 rx_firspass[1][0][15] = 0
4946 13:44:00.839726 rx_lastpass[1][0][15] = 0
4947 13:44:00.842850 rx_firspass[1][1][0] = 0
4948 13:44:00.846771 rx_lastpass[1][1][0] = 0
4949 13:44:00.846846 rx_firspass[1][1][1] = 0
4950 13:44:00.849694 rx_lastpass[1][1][1] = 0
4951 13:44:00.853139 rx_firspass[1][1][2] = 0
4952 13:44:00.853272 rx_lastpass[1][1][2] = 0
4953 13:44:00.856230 rx_firspass[1][1][3] = 0
4954 13:44:00.859841 rx_lastpass[1][1][3] = 0
4955 13:44:00.859917 rx_firspass[1][1][4] = 0
4956 13:44:00.863019 rx_lastpass[1][1][4] = 0
4957 13:44:00.866435 rx_firspass[1][1][5] = 0
4958 13:44:00.866511 rx_lastpass[1][1][5] = 0
4959 13:44:00.869843 rx_firspass[1][1][6] = 0
4960 13:44:00.873259 rx_lastpass[1][1][6] = 0
4961 13:44:00.873349 rx_firspass[1][1][7] = 0
4962 13:44:00.876638 rx_lastpass[1][1][7] = 0
4963 13:44:00.879834 rx_firspass[1][1][8] = 0
4964 13:44:00.883245 rx_lastpass[1][1][8] = 0
4965 13:44:00.883321 rx_firspass[1][1][9] = 0
4966 13:44:00.886699 rx_lastpass[1][1][9] = 0
4967 13:44:00.889994 rx_firspass[1][1][10] = 0
4968 13:44:00.890070 rx_lastpass[1][1][10] = 0
4969 13:44:00.893580 rx_firspass[1][1][11] = 0
4970 13:44:00.896609 rx_lastpass[1][1][11] = 0
4971 13:44:00.896685 rx_firspass[1][1][12] = 0
4972 13:44:00.899882 rx_lastpass[1][1][12] = 0
4973 13:44:00.903192 rx_firspass[1][1][13] = 0
4974 13:44:00.907009 rx_lastpass[1][1][13] = 0
4975 13:44:00.907086 rx_firspass[1][1][14] = 0
4976 13:44:00.910092 rx_lastpass[1][1][14] = 0
4977 13:44:00.913293 rx_firspass[1][1][15] = 0
4978 13:44:00.913393 rx_lastpass[1][1][15] = 0
4979 13:44:00.916731 dump params clk_delay
4980 13:44:00.916820 clk_delay[0] = 0
4981 13:44:00.919909 clk_delay[1] = 0
4982 13:44:00.919985 dump params dqs_delay
4983 13:44:00.923026 dqs_delay[0][0] = 0
4984 13:44:00.926544 dqs_delay[0][1] = 0
4985 13:44:00.926622 dqs_delay[1][0] = 0
4986 13:44:00.929786 dqs_delay[1][1] = 0
4987 13:44:00.933406 dump params delay_cell_unit = 762
4988 13:44:00.933482 mt_set_emi_preloader end
4989 13:44:00.939902 [mt_mem_init] dram size: 0x100000000, rank number: 2
4990 13:44:00.943090 [complex_mem_test] start addr:0x40000000, len:20480
4991 13:44:00.980064 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
4992 13:44:00.986718 [complex_mem_test] start addr:0x80000000, len:20480
4993 13:44:01.022490 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
4994 13:44:01.029034 [complex_mem_test] start addr:0xc0000000, len:20480
4995 13:44:01.064822 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
4996 13:44:01.071561 [complex_mem_test] start addr:0x56000000, len:8192
4997 13:44:01.088112 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
4998 13:44:01.088192 ddr_geometry:1
4999 13:44:01.094516 [complex_mem_test] start addr:0x80000000, len:8192
5000 13:44:01.111607 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5001 13:44:01.115084 dram_init: dram init end (result: 0)
5002 13:44:01.121479 Successfully loaded DRAM blobs and ran DRAM calibration
5003 13:44:01.131747 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5004 13:44:01.131825 CBMEM:
5005 13:44:01.135383 IMD: root @ 00000000fffff000 254 entries.
5006 13:44:01.138498 IMD: root @ 00000000ffffec00 62 entries.
5007 13:44:01.145091 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5008 13:44:01.151535 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5009 13:44:01.154651 in-header: 03 a1 00 00 08 00 00 00
5010 13:44:01.157901 in-data: 84 60 60 10 00 00 00 00
5011 13:44:01.161432 Chrome EC: clear events_b mask to 0x0000000020004000
5012 13:44:01.168906 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5013 13:44:01.172159 in-header: 03 fd 00 00 00 00 00 00
5014 13:44:01.172236 in-data:
5015 13:44:01.178695 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5016 13:44:01.178773 CBFS @ 21000 size 3d4000
5017 13:44:01.185134 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5018 13:44:01.188855 CBFS: Locating 'fallback/ramstage'
5019 13:44:01.191845 CBFS: Found @ offset 10d40 size d563
5020 13:44:01.213482 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5021 13:44:01.225742 Accumulated console time in romstage 12761 ms
5022 13:44:01.225819
5023 13:44:01.225877
5024 13:44:01.235572 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5025 13:44:01.239122 ARM64: Exception handlers installed.
5026 13:44:01.239197 ARM64: Testing exception
5027 13:44:01.242244 ARM64: Done test exception
5028 13:44:01.245512 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5029 13:44:01.248783 Manufacturer: ef
5030 13:44:01.252550 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5031 13:44:01.259218 WARNING: RO_VPD is uninitialized or empty.
5032 13:44:01.262216 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5033 13:44:01.265406 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5034 13:44:01.275754 read SPI 0x550600 0x3a00: 4533 us, 3275 KB/s, 26.200 Mbps
5035 13:44:01.278650 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5036 13:44:01.285426 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5037 13:44:01.285502 Enumerating buses...
5038 13:44:01.292093 Show all devs... Before device enumeration.
5039 13:44:01.292170 Root Device: enabled 1
5040 13:44:01.295369 CPU_CLUSTER: 0: enabled 1
5041 13:44:01.295444 CPU: 00: enabled 1
5042 13:44:01.298842 Compare with tree...
5043 13:44:01.301886 Root Device: enabled 1
5044 13:44:01.301962 CPU_CLUSTER: 0: enabled 1
5045 13:44:01.305240 CPU: 00: enabled 1
5046 13:44:01.308697 Root Device scanning...
5047 13:44:01.308772 root_dev_scan_bus for Root Device
5048 13:44:01.312129 CPU_CLUSTER: 0 enabled
5049 13:44:01.315424 root_dev_scan_bus for Root Device done
5050 13:44:01.318885 scan_bus: scanning of bus Root Device took 10690 usecs
5051 13:44:01.322254 done
5052 13:44:01.325515 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5053 13:44:01.328863 Allocating resources...
5054 13:44:01.328939 Reading resources...
5055 13:44:01.332040 Root Device read_resources bus 0 link: 0
5056 13:44:01.338832 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5057 13:44:01.338908 CPU: 00 missing read_resources
5058 13:44:01.345570 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5059 13:44:01.348848 Root Device read_resources bus 0 link: 0 done
5060 13:44:01.352390 Done reading resources.
5061 13:44:01.355363 Show resources in subtree (Root Device)...After reading.
5062 13:44:01.358767 Root Device child on link 0 CPU_CLUSTER: 0
5063 13:44:01.361984 CPU_CLUSTER: 0 child on link 0 CPU: 00
5064 13:44:01.372464 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5065 13:44:01.372542 CPU: 00
5066 13:44:01.375758 Setting resources...
5067 13:44:01.378777 Root Device assign_resources, bus 0 link: 0
5068 13:44:01.382209 CPU_CLUSTER: 0 missing set_resources
5069 13:44:01.385417 Root Device assign_resources, bus 0 link: 0
5070 13:44:01.388818 Done setting resources.
5071 13:44:01.392078 Show resources in subtree (Root Device)...After assigning values.
5072 13:44:01.398952 Root Device child on link 0 CPU_CLUSTER: 0
5073 13:44:01.402349 CPU_CLUSTER: 0 child on link 0 CPU: 00
5074 13:44:01.409114 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5075 13:44:01.412027 CPU: 00
5076 13:44:01.412102 Done allocating resources.
5077 13:44:01.418976 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5078 13:44:01.419052 Enabling resources...
5079 13:44:01.422247 done.
5080 13:44:01.425409 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5081 13:44:01.428882 Initializing devices...
5082 13:44:01.428957 Root Device init ...
5083 13:44:01.432230 mainboard_init: Starting display init.
5084 13:44:01.435389 ADC[4]: Raw value=77032 ID=0
5085 13:44:01.458375 anx7625_power_on_init: Init interface.
5086 13:44:01.461356 anx7625_disable_pd_protocol: Disabled PD feature.
5087 13:44:01.468054 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5088 13:44:01.525159 anx7625_start_dp_work: Secure OCM version=00
5089 13:44:01.528638 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5090 13:44:01.545681 sp_tx_get_edid_block: EDID Block = 1
5091 13:44:01.662942 Extracted contents:
5092 13:44:01.666030 header: 00 ff ff ff ff ff ff 00
5093 13:44:01.669446 serial number: 06 af 5c 14 00 00 00 00 00 1a
5094 13:44:01.673072 version: 01 04
5095 13:44:01.676109 basic params: 95 1a 0e 78 02
5096 13:44:01.679332 chroma info: 99 85 95 55 56 92 28 22 50 54
5097 13:44:01.682765 established: 00 00 00
5098 13:44:01.689364 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5099 13:44:01.692855 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5100 13:44:01.699334 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5101 13:44:01.705982 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5102 13:44:01.712755 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5103 13:44:01.715792 extensions: 00
5104 13:44:01.715866 checksum: ae
5105 13:44:01.715924
5106 13:44:01.719310 Manufacturer: AUO Model 145c Serial Number 0
5107 13:44:01.722577 Made week 0 of 2016
5108 13:44:01.722651 EDID version: 1.4
5109 13:44:01.726012 Digital display
5110 13:44:01.729153 6 bits per primary color channel
5111 13:44:01.729240 DisplayPort interface
5112 13:44:01.732647 Maximum image size: 26 cm x 14 cm
5113 13:44:01.735803 Gamma: 220%
5114 13:44:01.735878 Check DPMS levels
5115 13:44:01.739380 Supported color formats: RGB 4:4:4
5116 13:44:01.742638 First detailed timing is preferred timing
5117 13:44:01.746063 Established timings supported:
5118 13:44:01.749444 Standard timings supported:
5119 13:44:01.749521 Detailed timings
5120 13:44:01.752732 Hex of detail: ce1d56ea50001a3030204600009010000018
5121 13:44:01.759578 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5122 13:44:01.762757 0556 0586 05a6 0640 hborder 0
5123 13:44:01.766039 0300 0304 030a 031a vborder 0
5124 13:44:01.769257 -hsync -vsync
5125 13:44:01.772556 Did detailed timing
5126 13:44:01.776056 Hex of detail: 0000000f0000000000000000000000000020
5127 13:44:01.779576 Manufacturer-specified data, tag 15
5128 13:44:01.782818 Hex of detail: 000000fe0041554f0a202020202020202020
5129 13:44:01.786369 ASCII string: AUO
5130 13:44:01.789234 Hex of detail: 000000fe004231313658414230312e34200a
5131 13:44:01.792685 ASCII string: B116XAB01.4
5132 13:44:01.792782 Checksum
5133 13:44:01.795887 Checksum: 0xae (valid)
5134 13:44:01.799380 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5135 13:44:01.802797 DSI data_rate: 457800000 bps
5136 13:44:01.809966 anx7625_parse_edid: set default k value to 0x3d for panel
5137 13:44:01.813084 anx7625_parse_edid: pixelclock(76300).
5138 13:44:01.816537 hactive(1366), hsync(32), hfp(48), hbp(154)
5139 13:44:01.819795 vactive(768), vsync(6), vfp(4), vbp(16)
5140 13:44:01.823215 anx7625_dsi_config: config dsi.
5141 13:44:01.830934 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5142 13:44:01.852162 anx7625_dsi_config: success to config DSI
5143 13:44:01.855174 anx7625_dp_start: MIPI phy setup OK.
5144 13:44:01.858620 [SSUSB] Setting up USB HOST controller...
5145 13:44:01.862097 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5146 13:44:01.865328 [SSUSB] phy power-on done.
5147 13:44:01.869020 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5148 13:44:01.872480 in-header: 03 fc 01 00 00 00 00 00
5149 13:44:01.872556 in-data:
5150 13:44:01.875876 handle_proto3_response: EC response with error code: 1
5151 13:44:01.879121 SPM: pcm index = 1
5152 13:44:01.882411 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5153 13:44:01.885888 CBFS @ 21000 size 3d4000
5154 13:44:01.892556 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5155 13:44:01.895862 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5156 13:44:01.898951 CBFS: Found @ offset 1e7c0 size 1026
5157 13:44:01.905808 read SPI 0x3f808 0x1026: 1271 us, 3252 KB/s, 26.016 Mbps
5158 13:44:01.908992 SPM: binary array size = 2988
5159 13:44:01.912307 SPM: version = pcm_allinone_v1.17.2_20180829
5160 13:44:01.915644 SPM binary loaded in 32 msecs
5161 13:44:01.923136 spm_kick_im_to_fetch: ptr = 000000004021eec2
5162 13:44:01.926339 spm_kick_im_to_fetch: len = 2988
5163 13:44:01.926415 SPM: spm_kick_pcm_to_run
5164 13:44:01.929758 SPM: spm_kick_pcm_to_run done
5165 13:44:01.933130 SPM: spm_init done in 52 msecs
5166 13:44:01.936544 Root Device init finished in 505262 usecs
5167 13:44:01.939740 CPU_CLUSTER: 0 init ...
5168 13:44:01.946530 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5169 13:44:01.953160 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5170 13:44:01.953263 CBFS @ 21000 size 3d4000
5171 13:44:01.960332 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5172 13:44:01.963354 CBFS: Locating 'sspm.bin'
5173 13:44:01.966959 CBFS: Found @ offset 208c0 size 41cb
5174 13:44:01.976728 read SPI 0x418f8 0x41cb: 5142 us, 3275 KB/s, 26.200 Mbps
5175 13:44:01.984633 CPU_CLUSTER: 0 init finished in 42801 usecs
5176 13:44:01.984715 Devices initialized
5177 13:44:01.987613 Show all devs... After init.
5178 13:44:01.990919 Root Device: enabled 1
5179 13:44:01.991075 CPU_CLUSTER: 0: enabled 1
5180 13:44:01.994471 CPU: 00: enabled 1
5181 13:44:01.997573 BS: BS_DEV_INIT times (ms): entry 0 run 234 exit 0
5182 13:44:02.000769 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5183 13:44:02.004277 ELOG: NV offset 0x558000 size 0x1000
5184 13:44:02.011802 read SPI 0x558000 0x1000: 1259 us, 3253 KB/s, 26.024 Mbps
5185 13:44:02.018554 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5186 13:44:02.021757 ELOG: Event(17) added with size 13 at 2024-07-18 13:44:01 UTC
5187 13:44:02.025160 out: cmd=0x121: 03 db 21 01 00 00 00 00
5188 13:44:02.028632 in-header: 03 87 00 00 2c 00 00 00
5189 13:44:02.041979 in-data: 43 49 00 00 00 00 00 00 02 10 00 00 06 80 00 00 a4 77 01 00 06 80 00 00 9f 81 02 00 06 80 00 00 35 37 01 00 06 80 00 00 b8 2f 02 00
5190 13:44:02.045370 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5191 13:44:02.048666 in-header: 03 19 00 00 08 00 00 00
5192 13:44:02.051866 in-data: a2 e0 47 00 13 00 00 00
5193 13:44:02.055094 Chrome EC: UHEPI supported
5194 13:44:02.062115 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5195 13:44:02.065108 in-header: 03 e1 00 00 08 00 00 00
5196 13:44:02.068425 in-data: 84 20 60 10 00 00 00 00
5197 13:44:02.072042 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5198 13:44:02.078542 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5199 13:44:02.081925 in-header: 03 e1 00 00 08 00 00 00
5200 13:44:02.085259 in-data: 84 20 60 10 00 00 00 00
5201 13:44:02.091985 ELOG: Event(A1) added with size 10 at 2024-07-18 13:44:01 UTC
5202 13:44:02.098631 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5203 13:44:02.101855 ELOG: Event(A0) added with size 9 at 2024-07-18 13:44:01 UTC
5204 13:44:02.105463 elog_add_boot_reason: Logged dev mode boot
5205 13:44:02.108499 Finalize devices...
5206 13:44:02.108576 Devices finalized
5207 13:44:02.115288 BS: BS_POST_DEVICE times (ms): entry 3 run 0 exit 0
5208 13:44:02.118637 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5209 13:44:02.125415 ELOG: Event(91) added with size 10 at 2024-07-18 13:44:01 UTC
5210 13:44:02.128622 Writing coreboot table at 0xffeda000
5211 13:44:02.131933 0. 0000000000114000-000000000011efff: RAMSTAGE
5212 13:44:02.135192 1. 0000000040000000-000000004023cfff: RAMSTAGE
5213 13:44:02.142173 2. 000000004023d000-00000000545fffff: RAM
5214 13:44:02.145278 3. 0000000054600000-000000005465ffff: BL31
5215 13:44:02.148811 4. 0000000054660000-00000000ffed9fff: RAM
5216 13:44:02.152031 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5217 13:44:02.158687 6. 0000000100000000-000000013fffffff: RAM
5218 13:44:02.158766 Passing 5 GPIOs to payload:
5219 13:44:02.165385 NAME | PORT | POLARITY | VALUE
5220 13:44:02.169049 write protect | 0x00000096 | low | high
5221 13:44:02.175437 EC in RW | 0x000000b1 | high | undefined
5222 13:44:02.178737 EC interrupt | 0x00000097 | low | undefined
5223 13:44:02.181829 TPM interrupt | 0x00000099 | high | undefined
5224 13:44:02.188544 speaker enable | 0x000000af | high | undefined
5225 13:44:02.192043 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5226 13:44:02.195128 in-header: 03 f7 00 00 02 00 00 00
5227 13:44:02.195219 in-data: 04 00
5228 13:44:02.198415 Board ID: 4
5229 13:44:02.198491 ADC[3]: Raw value=1040656 ID=8
5230 13:44:02.201860 RAM code: 8
5231 13:44:02.201935 SKU ID: 16
5232 13:44:02.205282 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5233 13:44:02.208572 CBFS @ 21000 size 3d4000
5234 13:44:02.215307 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5235 13:44:02.221957 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum 4619
5236 13:44:02.222034 coreboot table: 940 bytes.
5237 13:44:02.225283 IMD ROOT 0. 00000000fffff000 00001000
5238 13:44:02.228582 IMD SMALL 1. 00000000ffffe000 00001000
5239 13:44:02.231984 CONSOLE 2. 00000000fffde000 00020000
5240 13:44:02.238505 FMAP 3. 00000000fffdd000 0000047c
5241 13:44:02.242017 TIME STAMP 4. 00000000fffdc000 00000910
5242 13:44:02.245365 RAMOOPS 5. 00000000ffedc000 00100000
5243 13:44:02.248616 COREBOOT 6. 00000000ffeda000 00002000
5244 13:44:02.248691 IMD small region:
5245 13:44:02.251963 IMD ROOT 0. 00000000ffffec00 00000400
5246 13:44:02.258669 VBOOT WORK 1. 00000000ffffeb00 00000100
5247 13:44:02.262037 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5248 13:44:02.265590 VPD 3. 00000000ffffea60 0000006c
5249 13:44:02.268501 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5250 13:44:02.275369 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5251 13:44:02.278640 in-header: 03 e1 00 00 08 00 00 00
5252 13:44:02.282059 in-data: 84 20 60 10 00 00 00 00
5253 13:44:02.285558 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5254 13:44:02.288774 CBFS @ 21000 size 3d4000
5255 13:44:02.295470 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5256 13:44:02.298865 CBFS: Locating 'fallback/payload'
5257 13:44:02.305654 CBFS: Found @ offset dc040 size 439a0
5258 13:44:02.393656 read SPI 0xfd078 0x439a0: 84378 us, 3281 KB/s, 26.248 Mbps
5259 13:44:02.397017 Checking segment from ROM address 0x0000000040003a00
5260 13:44:02.403736 Checking segment from ROM address 0x0000000040003a1c
5261 13:44:02.407472 Loading segment from ROM address 0x0000000040003a00
5262 13:44:02.410472 code (compression=0)
5263 13:44:02.417124 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5264 13:44:02.427191 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5265 13:44:02.430481 it's not compressed!
5266 13:44:02.434275 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5267 13:44:02.440851 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5268 13:44:02.448136 Loading segment from ROM address 0x0000000040003a1c
5269 13:44:02.451784 Entry Point 0x0000000080000000
5270 13:44:02.451860 Loaded segments
5271 13:44:02.458187 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5272 13:44:02.461398 Jumping to boot code at 0000000080000000(00000000ffeda000)
5273 13:44:02.471388 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5274 13:44:02.474723 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5275 13:44:02.478222 CBFS @ 21000 size 3d4000
5276 13:44:02.484848 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5277 13:44:02.484926 CBFS: Locating 'fallback/bl31'
5278 13:44:02.488448 CBFS: Found @ offset 36dc0 size 5820
5279 13:44:02.501850 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5280 13:44:02.505261 Checking segment from ROM address 0x0000000040003a00
5281 13:44:02.512204 Checking segment from ROM address 0x0000000040003a1c
5282 13:44:02.515243 Loading segment from ROM address 0x0000000040003a00
5283 13:44:02.518805 code (compression=1)
5284 13:44:02.525146 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5285 13:44:02.535252 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5286 13:44:02.535330 using LZMA
5287 13:44:02.543838 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5288 13:44:02.550535 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5289 13:44:02.554008 Loading segment from ROM address 0x0000000040003a1c
5290 13:44:02.557504 Entry Point 0x0000000054601000
5291 13:44:02.557607 Loaded segments
5292 13:44:02.560360 NOTICE: MT8183 bl31_setup
5293 13:44:02.567694 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5294 13:44:02.571109 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5295 13:44:02.574093 INFO: [DEVAPC] dump DEVAPC registers:
5296 13:44:02.584181 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5297 13:44:02.590746 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5298 13:44:02.600930 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5299 13:44:02.607664 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5300 13:44:02.617745 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5301 13:44:02.624087 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5302 13:44:02.634163 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5303 13:44:02.640785 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5304 13:44:02.647754 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5305 13:44:02.657347 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5306 13:44:02.664065 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5307 13:44:02.674281 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5308 13:44:02.680919 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5309 13:44:02.687502 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5310 13:44:02.697677 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5311 13:44:02.704095 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5312 13:44:02.710901 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5313 13:44:02.717873 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5314 13:44:02.724397 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5315 13:44:02.734191 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5316 13:44:02.740823 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5317 13:44:02.747555 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5318 13:44:02.750745 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5319 13:44:02.754112 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5320 13:44:02.757505 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5321 13:44:02.760754 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5322 13:44:02.764123 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5323 13:44:02.771059 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5324 13:44:02.774253 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5325 13:44:02.777568 WARNING: region 0:
5326 13:44:02.781119 WARNING: apc:0x168, sa:0x0, ea:0xfff
5327 13:44:02.781219 WARNING: region 1:
5328 13:44:02.784422 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5329 13:44:02.787787 WARNING: region 2:
5330 13:44:02.791027 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5331 13:44:02.794304 WARNING: region 3:
5332 13:44:02.797602 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5333 13:44:02.797679 WARNING: region 4:
5334 13:44:02.800946 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5335 13:44:02.804812 WARNING: region 5:
5336 13:44:02.807763 WARNING: apc:0x0, sa:0x0, ea:0x0
5337 13:44:02.807840 WARNING: region 6:
5338 13:44:02.811476 WARNING: apc:0x0, sa:0x0, ea:0x0
5339 13:44:02.814436 WARNING: region 7:
5340 13:44:02.817676 WARNING: apc:0x0, sa:0x0, ea:0x0
5341 13:44:02.824431 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5342 13:44:02.827618 INFO: SPM: enable SPMC mode
5343 13:44:02.827694 NOTICE: spm_boot_init() start
5344 13:44:02.831187 NOTICE: spm_boot_init() end
5345 13:44:02.834463 INFO: BL31: Initializing runtime services
5346 13:44:02.841001 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5347 13:44:02.847737 INFO: BL31: Preparing for EL3 exit to normal world
5348 13:44:02.851142 INFO: Entry point address = 0x80000000
5349 13:44:02.851218 INFO: SPSR = 0x8
5350 13:44:02.874077
5351 13:44:02.874160
5352 13:44:02.874219
5353 13:44:02.874686 end: 2.2.3 depthcharge-start (duration 00:00:23) [common]
5354 13:44:02.874781 start: 2.2.4 bootloader-commands (timeout 00:04:28) [common]
5355 13:44:02.874857 Setting prompt string to ['jacuzzi:']
5356 13:44:02.874921 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:28)
5357 13:44:02.877616 Starting depthcharge on Juniper...
5358 13:44:02.877693
5359 13:44:02.880688 vboot_handoff: creating legacy vboot_handoff structure
5360 13:44:02.880765
5361 13:44:02.884133 ec_init(0): CrosEC protocol v3 supported (544, 544)
5362 13:44:02.884209
5363 13:44:02.887367 Wipe memory regions:
5364 13:44:02.887444
5365 13:44:02.890727 [0x00000040000000, 0x00000054600000)
5366 13:44:02.933636
5367 13:44:02.933746 [0x00000054660000, 0x00000080000000)
5368 13:44:03.025281
5369 13:44:03.025415 [0x000000811994a0, 0x000000ffeda000)
5370 13:44:03.285156
5371 13:44:03.285340 [0x00000100000000, 0x00000140000000)
5372 13:44:03.418124
5373 13:44:03.421315 Initializing XHCI USB controller at 0x11200000.
5374 13:44:03.444079
5375 13:44:03.447416 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5376 13:44:03.447493
5377 13:44:03.447555
5378 13:44:03.447813 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5379 13:44:03.447885 Sending line: 'tftpboot 192.168.201.1 14879038/tftp-deploy-v36e__j0/kernel/image.itb 14879038/tftp-deploy-v36e__j0/kernel/cmdline '
5381 13:44:03.548385 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5382 13:44:03.548483 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:27)
5383 13:44:03.552851 jacuzzi: tftpboot 192.168.201.1 14879038/tftp-deploy-v36e__j0/kernel/image.ittp-deploy-v36e__j0/kernel/cmdline
5384 13:44:03.552928
5385 13:44:03.552987 Waiting for link
5386 13:44:04.104625
5387 13:44:04.104749 R8152: Initializing
5388 13:44:04.104808
5389 13:44:04.107984 Version 9 (ocp_data = 6010)
5390 13:44:04.108060
5391 13:44:04.110917 R8152: Done initializing
5392 13:44:04.110992
5393 13:44:04.111050 Adding net device
5394 13:44:04.289920
5395 13:44:04.290049 R8152: Initializing
5396 13:44:04.290107
5397 13:44:04.293261 Version 9 (ocp_data = 6010)
5398 13:44:04.293338
5399 13:44:04.296805 R8152: Done initializing
5400 13:44:04.296888
5401 13:44:04.300224 net_add_device: Attemp to include the same device
5402 13:44:04.686098
5403 13:44:04.686229 done.
5404 13:44:04.686290
5405 13:44:04.686345 MAC: 00:e0:4c:68:03:2b
5406 13:44:04.686398
5407 13:44:04.689427 Sending DHCP discover... done.
5408 13:44:04.689504
5409 13:44:04.692677 Waiting for reply... done.
5410 13:44:04.692754
5411 13:44:04.695780 Sending DHCP request... done.
5412 13:44:04.695856
5413 13:44:04.723200 Waiting for reply... done.
5414 13:44:04.723325
5415 13:44:04.723386 My ip is 192.168.201.17
5416 13:44:04.723440
5417 13:44:04.726418 The DHCP server ip is 192.168.201.1
5418 13:44:04.726498
5419 13:44:04.732789 TFTP server IP predefined by user: 192.168.201.1
5420 13:44:04.732896
5421 13:44:04.739835 Bootfile predefined by user: 14879038/tftp-deploy-v36e__j0/kernel/image.itb
5422 13:44:04.739947
5423 13:44:04.740007 Sending tftp read request... done.
5424 13:44:04.740062
5425 13:44:04.746471 Waiting for the transfer...
5426 13:44:04.746587
5427 13:44:05.003883 00000000 ################################################################
5428 13:44:05.004012
5429 13:44:05.278668 00080000 ################################################################
5430 13:44:05.278800
5431 13:44:05.535157 00100000 ################################################################
5432 13:44:05.535287
5433 13:44:05.792313 00180000 ################################################################
5434 13:44:05.792517
5435 13:44:06.045505 00200000 ################################################################
5436 13:44:06.045644
5437 13:44:06.293236 00280000 ################################################################
5438 13:44:06.293398
5439 13:44:06.545247 00300000 ################################################################
5440 13:44:06.545381
5441 13:44:06.800548 00380000 ################################################################
5442 13:44:06.800684
5443 13:44:07.039130 00400000 ################################################################
5444 13:44:07.039265
5445 13:44:07.283957 00480000 ################################################################
5446 13:44:07.284081
5447 13:44:07.524732 00500000 ################################################################
5448 13:44:07.524861
5449 13:44:07.769935 00580000 ################################################################
5450 13:44:07.770063
5451 13:44:08.036547 00600000 ################################################################
5452 13:44:08.036670
5453 13:44:08.295710 00680000 ################################################################
5454 13:44:08.295833
5455 13:44:08.546953 00700000 ################################################################
5456 13:44:08.547077
5457 13:44:08.835484 00780000 ################################################################
5458 13:44:08.835668
5459 13:44:09.118921 00800000 ################################################################
5460 13:44:09.119081
5461 13:44:09.400799 00880000 ################################################################
5462 13:44:09.401061
5463 13:44:09.647811 00900000 ################################################################
5464 13:44:09.647939
5465 13:44:09.891367 00980000 ################################################################
5466 13:44:09.891496
5467 13:44:10.133361 00a00000 ################################################################
5468 13:44:10.133487
5469 13:44:10.404692 00a80000 ################################################################
5470 13:44:10.404819
5471 13:44:10.672579 00b00000 ################################################################
5472 13:44:10.672701
5473 13:44:10.964906 00b80000 ################################################################
5474 13:44:10.965027
5475 13:44:11.254359 00c00000 ################################################################
5476 13:44:11.254478
5477 13:44:11.535912 00c80000 ################################################################
5478 13:44:11.536034
5479 13:44:11.819358 00d00000 ################################################################
5480 13:44:11.819499
5481 13:44:12.097695 00d80000 ################################################################
5482 13:44:12.097839
5483 13:44:12.397251 00e00000 ################################################################
5484 13:44:12.397383
5485 13:44:12.687753 00e80000 ################################################################
5486 13:44:12.687877
5487 13:44:12.978332 00f00000 ################################################################
5488 13:44:12.978452
5489 13:44:13.274465 00f80000 ################################################################
5490 13:44:13.274587
5491 13:44:13.563548 01000000 ################################################################
5492 13:44:13.563667
5493 13:44:13.837779 01080000 ################################################################
5494 13:44:13.837902
5495 13:44:14.106886 01100000 ################################################################
5496 13:44:14.107004
5497 13:44:14.374830 01180000 ################################################################
5498 13:44:14.374952
5499 13:44:14.673439 01200000 ################################################################
5500 13:44:14.673607
5501 13:44:14.956243 01280000 ################################################################
5502 13:44:14.956392
5503 13:44:15.245597 01300000 ################################################################
5504 13:44:15.245723
5505 13:44:15.526856 01380000 ################################################################
5506 13:44:15.526980
5507 13:44:15.806934 01400000 ################################################################
5508 13:44:15.807082
5509 13:44:16.086135 01480000 ################################################################
5510 13:44:16.086263
5511 13:44:16.380140 01500000 ################################################################
5512 13:44:16.380261
5513 13:44:16.651617 01580000 ################################################################
5514 13:44:16.651738
5515 13:44:16.936434 01600000 ################################################################
5516 13:44:16.936560
5517 13:44:17.226915 01680000 ################################################################
5518 13:44:17.227042
5519 13:44:17.527177 01700000 ################################################################
5520 13:44:17.527292
5521 13:44:17.821202 01780000 ################################################################
5522 13:44:17.821334
5523 13:44:18.107758 01800000 ################################################################
5524 13:44:18.107882
5525 13:44:18.398078 01880000 ################################################################
5526 13:44:18.398202
5527 13:44:18.680538 01900000 ################################################################
5528 13:44:18.680655
5529 13:44:18.954973 01980000 ################################################################
5530 13:44:18.955086
5531 13:44:19.210741 01a00000 ################################################################
5532 13:44:19.210850
5533 13:44:19.497179 01a80000 ################################################################
5534 13:44:19.497309
5535 13:44:19.768453 01b00000 ################################################################
5536 13:44:19.768560
5537 13:44:20.028971 01b80000 ################################################################
5538 13:44:20.029083
5539 13:44:20.287434 01c00000 ################################################################
5540 13:44:20.287545
5541 13:44:20.573467 01c80000 ################################################################
5542 13:44:20.573586
5543 13:44:20.873219 01d00000 ################################################################
5544 13:44:20.873347
5545 13:44:21.173335 01d80000 ################################################################
5546 13:44:21.173444
5547 13:44:21.423177 01e00000 ###################################################### done.
5548 13:44:21.423285
5549 13:44:21.426516 The bootfile was 31894422 bytes long.
5550 13:44:21.426597
5551 13:44:21.430201 Sending tftp read request... done.
5552 13:44:21.430306
5553 13:44:21.433409 Waiting for the transfer...
5554 13:44:21.433496
5555 13:44:21.433562 00000000 # done.
5556 13:44:21.433626
5557 13:44:21.444036 Command line loaded dynamically from TFTP file: 14879038/tftp-deploy-v36e__j0/kernel/cmdline
5558 13:44:21.444569
5559 13:44:21.467023 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14879038/extract-nfsrootfs-fj34yvmf,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5560 13:44:21.467526
5561 13:44:21.470313 Loading FIT.
5562 13:44:21.470737
5563 13:44:21.473504 Image ramdisk-1 has 18720216 bytes.
5564 13:44:21.473932
5565 13:44:21.474259 Image fdt-1 has 57695 bytes.
5566 13:44:21.477161
5567 13:44:21.477650 Image kernel-1 has 13114469 bytes.
5568 13:44:21.477988
5569 13:44:21.486983 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5570 13:44:21.487469
5571 13:44:21.500388 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5572 13:44:21.501016
5573 13:44:21.503441 Choosing best match conf-1 for compat google,juniper-sku16.
5574 13:44:21.508779
5575 13:44:21.513214 Connected to device vid:did:rid of 1ae0:0028:00
5576 13:44:21.520198
5577 13:44:21.523916 tpm_get_response: command 0x17b, return code 0x0
5578 13:44:21.524519
5579 13:44:21.526911 tpm_cleanup: add release locality here.
5580 13:44:21.527297
5581 13:44:21.530457 Shutting down all USB controllers.
5582 13:44:21.530963
5583 13:44:21.533505 Removing current net device
5584 13:44:21.533926
5585 13:44:21.536840 Exiting depthcharge with code 4 at timestamp: 34980677
5586 13:44:21.537456
5587 13:44:21.540543 LZMA decompressing kernel-1 to 0x80193568
5588 13:44:21.540943
5589 13:44:21.547071 LZMA decompressing kernel-1 to 0x40000000
5590 13:44:23.409355
5591 13:44:23.409986 jumping to kernel
5592 13:44:23.413104 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
5593 13:44:23.413846 start: 2.2.5 auto-login-action (timeout 00:04:07) [common]
5594 13:44:23.414415 Setting prompt string to ['Linux version [0-9]']
5595 13:44:23.414962 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5596 13:44:23.415522 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5597 13:44:23.484261
5598 13:44:23.487695 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5599 13:44:23.491339 start: 2.2.5.1 login-action (timeout 00:04:07) [common]
5600 13:44:23.492070 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5601 13:44:23.492589 Setting prompt string to []
5602 13:44:23.492990 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5603 13:44:23.493381 Using line separator: #'\n'#
5604 13:44:23.493689 No login prompt set.
5605 13:44:23.493997 Parsing kernel messages
5606 13:44:23.494280 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5607 13:44:23.494894 [login-action] Waiting for messages, (timeout 00:04:07)
5608 13:44:23.495239 Waiting using forced prompt support (timeout 00:02:04)
5609 13:44:23.510892 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j272990-arm64-gcc-12-defconfig-arm64-chromebook-fgzcq) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024
5610 13:44:23.514632 [ 0.000000] random: crng init done
5611 13:44:23.517659 [ 0.000000] Machine model: Google juniper sku16 board
5612 13:44:23.520555 [ 0.000000] efi: UEFI not found.
5613 13:44:23.530868 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5614 13:44:23.537402 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5615 13:44:23.544370 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5616 13:44:23.551119 [ 0.000000] printk: bootconsole [mtk8250] enabled
5617 13:44:23.558289 [ 0.000000] NUMA: No NUMA configuration found
5618 13:44:23.564954 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5619 13:44:23.571711 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5620 13:44:23.572223 [ 0.000000] Zone ranges:
5621 13:44:23.578155 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5622 13:44:23.581946 [ 0.000000] DMA32 empty
5623 13:44:23.588104 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5624 13:44:23.591432 [ 0.000000] Movable zone start for each node
5625 13:44:23.595118 [ 0.000000] Early memory node ranges
5626 13:44:23.601376 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5627 13:44:23.608064 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5628 13:44:23.615082 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5629 13:44:23.621337 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5630 13:44:23.629044 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5631 13:44:23.634858 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5632 13:44:23.654609 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5633 13:44:23.661463 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5634 13:44:23.668194 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5635 13:44:23.671605 [ 0.000000] psci: probing for conduit method from DT.
5636 13:44:23.678259 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5637 13:44:23.681403 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5638 13:44:23.688179 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5639 13:44:23.691543 [ 0.000000] psci: SMC Calling Convention v1.1
5640 13:44:23.697897 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5641 13:44:23.701680 [ 0.000000] Detected VIPT I-cache on CPU0
5642 13:44:23.707918 [ 0.000000] CPU features: detected: GIC system register CPU interface
5643 13:44:23.714832 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5644 13:44:23.721273 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5645 13:44:23.724561 [ 0.000000] CPU features: detected: ARM erratum 845719
5646 13:44:23.731475 [ 0.000000] alternatives: applying boot alternatives
5647 13:44:23.734893 [ 0.000000] Fallback order for Node 0: 0
5648 13:44:23.741322 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5649 13:44:23.744961 [ 0.000000] Policy zone: Normal
5650 13:44:23.771502 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14879038/extract-nfsrootfs-fj34yvmf,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5651 13:44:23.784884 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5652 13:44:23.794717 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5653 13:44:23.802097 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5654 13:44:23.808120 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
5655 13:44:23.811340 <6>[ 0.000000] software IO TLB: area num 8.
5656 13:44:23.839026 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5657 13:44:23.896866 <6>[ 0.000000] Memory: 3896792K/4191232K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 261672K reserved, 32768K cma-reserved)
5658 13:44:23.903637 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5659 13:44:23.910329 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5660 13:44:23.913347 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5661 13:44:23.919939 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5662 13:44:23.926940 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5663 13:44:23.930027 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5664 13:44:23.939923 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5665 13:44:23.946839 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5666 13:44:23.949988 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5667 13:44:23.961855 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5668 13:44:23.969115 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5669 13:44:23.972315 <6>[ 0.000000] GICv3: 640 SPIs implemented
5670 13:44:23.975491 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5671 13:44:23.978684 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5672 13:44:23.985573 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5673 13:44:23.992433 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5674 13:44:24.001982 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5675 13:44:24.015818 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5676 13:44:24.022479 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5677 13:44:24.033782 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5678 13:44:24.047058 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5679 13:44:24.054019 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5680 13:44:24.060603 <6>[ 0.009463] Console: colour dummy device 80x25
5681 13:44:24.063868 <6>[ 0.014497] printk: console [tty1] enabled
5682 13:44:24.073933 <6>[ 0.018886] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5683 13:44:24.080997 <6>[ 0.029351] pid_max: default: 32768 minimum: 301
5684 13:44:24.083978 <6>[ 0.034232] LSM: Security Framework initializing
5685 13:44:24.093579 <6>[ 0.039146] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5686 13:44:24.100434 <6>[ 0.046768] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5687 13:44:24.107124 <4>[ 0.055651] cacheinfo: Unable to detect cache hierarchy for CPU 0
5688 13:44:24.117530 <6>[ 0.062278] cblist_init_generic: Setting adjustable number of callback queues.
5689 13:44:24.120320 <6>[ 0.069723] cblist_init_generic: Setting shift to 3 and lim to 1.
5690 13:44:24.130487 <6>[ 0.076076] cblist_init_generic: Setting adjustable number of callback queues.
5691 13:44:24.137482 <6>[ 0.083521] cblist_init_generic: Setting shift to 3 and lim to 1.
5692 13:44:24.140688 <6>[ 0.089920] rcu: Hierarchical SRCU implementation.
5693 13:44:24.147370 <6>[ 0.094946] rcu: Max phase no-delay instances is 1000.
5694 13:44:24.153947 <6>[ 0.102851] EFI services will not be available.
5695 13:44:24.157567 <6>[ 0.107798] smp: Bringing up secondary CPUs ...
5696 13:44:24.167565 <6>[ 0.113061] Detected VIPT I-cache on CPU1
5697 13:44:24.174190 <4>[ 0.113109] cacheinfo: Unable to detect cache hierarchy for CPU 1
5698 13:44:24.181111 <6>[ 0.113117] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5699 13:44:24.187879 <6>[ 0.113150] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5700 13:44:24.191026 <6>[ 0.113629] Detected VIPT I-cache on CPU2
5701 13:44:24.197635 <4>[ 0.113663] cacheinfo: Unable to detect cache hierarchy for CPU 2
5702 13:44:24.204133 <6>[ 0.113668] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5703 13:44:24.210862 <6>[ 0.113680] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5704 13:44:24.214546 <6>[ 0.114125] Detected VIPT I-cache on CPU3
5705 13:44:24.220880 <4>[ 0.114156] cacheinfo: Unable to detect cache hierarchy for CPU 3
5706 13:44:24.227366 <6>[ 0.114160] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5707 13:44:24.234152 <6>[ 0.114172] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5708 13:44:24.240545 <6>[ 0.114747] CPU features: detected: Spectre-v2
5709 13:44:24.244073 <6>[ 0.114757] CPU features: detected: Spectre-BHB
5710 13:44:24.250835 <6>[ 0.114760] CPU features: detected: ARM erratum 858921
5711 13:44:24.254226 <6>[ 0.114766] Detected VIPT I-cache on CPU4
5712 13:44:24.260898 <4>[ 0.114816] cacheinfo: Unable to detect cache hierarchy for CPU 4
5713 13:44:24.267532 <6>[ 0.114824] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5714 13:44:24.274047 <6>[ 0.114832] arch_timer: Enabling local workaround for ARM erratum 858921
5715 13:44:24.281215 <6>[ 0.114843] arch_timer: CPU4: Trapping CNTVCT access
5716 13:44:24.287148 <6>[ 0.114851] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5717 13:44:24.291055 <6>[ 0.115333] Detected VIPT I-cache on CPU5
5718 13:44:24.297529 <4>[ 0.115374] cacheinfo: Unable to detect cache hierarchy for CPU 5
5719 13:44:24.304084 <6>[ 0.115380] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5720 13:44:24.310452 <6>[ 0.115387] arch_timer: Enabling local workaround for ARM erratum 858921
5721 13:44:24.317158 <6>[ 0.115393] arch_timer: CPU5: Trapping CNTVCT access
5722 13:44:24.323861 <6>[ 0.115398] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5723 13:44:24.327213 <6>[ 0.115934] Detected VIPT I-cache on CPU6
5724 13:44:24.334091 <4>[ 0.115980] cacheinfo: Unable to detect cache hierarchy for CPU 6
5725 13:44:24.341106 <6>[ 0.115986] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5726 13:44:24.347047 <6>[ 0.115993] arch_timer: Enabling local workaround for ARM erratum 858921
5727 13:44:24.353852 <6>[ 0.115999] arch_timer: CPU6: Trapping CNTVCT access
5728 13:44:24.360633 <6>[ 0.116004] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5729 13:44:24.364253 <6>[ 0.116534] Detected VIPT I-cache on CPU7
5730 13:44:24.370759 <4>[ 0.116577] cacheinfo: Unable to detect cache hierarchy for CPU 7
5731 13:44:24.377344 <6>[ 0.116583] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5732 13:44:24.384229 <6>[ 0.116590] arch_timer: Enabling local workaround for ARM erratum 858921
5733 13:44:24.391294 <6>[ 0.116596] arch_timer: CPU7: Trapping CNTVCT access
5734 13:44:24.397540 <6>[ 0.116602] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5735 13:44:24.400614 <6>[ 0.116650] smp: Brought up 1 node, 8 CPUs
5736 13:44:24.407822 <6>[ 0.355524] SMP: Total of 8 processors activated.
5737 13:44:24.411028 <6>[ 0.360460] CPU features: detected: 32-bit EL0 Support
5738 13:44:24.417740 <6>[ 0.365831] CPU features: detected: 32-bit EL1 Support
5739 13:44:24.424247 <6>[ 0.371198] CPU features: detected: CRC32 instructions
5740 13:44:24.427236 <6>[ 0.376625] CPU: All CPU(s) started at EL2
5741 13:44:24.434564 <6>[ 0.380964] alternatives: applying system-wide alternatives
5742 13:44:24.437568 <6>[ 0.389015] devtmpfs: initialized
5743 13:44:24.452580 <6>[ 0.397954] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5744 13:44:24.462364 <6>[ 0.407901] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5745 13:44:24.465867 <6>[ 0.415625] pinctrl core: initialized pinctrl subsystem
5746 13:44:24.474025 <6>[ 0.422743] DMI not present or invalid.
5747 13:44:24.480828 <6>[ 0.427108] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5748 13:44:24.487179 <6>[ 0.434014] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5749 13:44:24.496931 <6>[ 0.441544] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5750 13:44:24.503411 <6>[ 0.449794] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5751 13:44:24.510331 <6>[ 0.457970] audit: initializing netlink subsys (disabled)
5752 13:44:24.517519 <5>[ 0.463676] audit: type=2000 audit(0.332:1): state=initialized audit_enabled=0 res=1
5753 13:44:24.523462 <6>[ 0.464651] thermal_sys: Registered thermal governor 'step_wise'
5754 13:44:24.530482 <6>[ 0.471643] thermal_sys: Registered thermal governor 'power_allocator'
5755 13:44:24.533792 <6>[ 0.477942] cpuidle: using governor menu
5756 13:44:24.540526 <6>[ 0.488905] NET: Registered PF_QIPCRTR protocol family
5757 13:44:24.547143 <6>[ 0.494402] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5758 13:44:24.553541 <6>[ 0.501501] ASID allocator initialised with 32768 entries
5759 13:44:24.557193 <6>[ 0.508269] Serial: AMBA PL011 UART driver
5760 13:44:24.570690 <4>[ 0.519599] Trying to register duplicate clock ID: 113
5761 13:44:24.630630 <6>[ 0.576045] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5762 13:44:24.644679 <6>[ 0.590431] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5763 13:44:24.647742 <6>[ 0.600206] KASLR enabled
5764 13:44:24.662746 <6>[ 0.608182] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
5765 13:44:24.669209 <6>[ 0.615184] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
5766 13:44:24.676358 <6>[ 0.621661] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
5767 13:44:24.682778 <6>[ 0.628651] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
5768 13:44:24.689379 <6>[ 0.635125] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
5769 13:44:24.695640 <6>[ 0.642114] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
5770 13:44:24.702727 <6>[ 0.648587] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
5771 13:44:24.709287 <6>[ 0.655577] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
5772 13:44:24.712322 <6>[ 0.663135] ACPI: Interpreter disabled.
5773 13:44:24.721902 <6>[ 0.671109] iommu: Default domain type: Translated
5774 13:44:24.729061 <6>[ 0.676217] iommu: DMA domain TLB invalidation policy: strict mode
5775 13:44:24.732212 <5>[ 0.682848] SCSI subsystem initialized
5776 13:44:24.738526 <6>[ 0.687260] usbcore: registered new interface driver usbfs
5777 13:44:24.745557 <6>[ 0.692986] usbcore: registered new interface driver hub
5778 13:44:24.748987 <6>[ 0.698527] usbcore: registered new device driver usb
5779 13:44:24.755706 <6>[ 0.704830] pps_core: LinuxPPS API ver. 1 registered
5780 13:44:24.765875 <6>[ 0.710015] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
5781 13:44:24.769884 <6>[ 0.719340] PTP clock support registered
5782 13:44:24.772298 <6>[ 0.723593] EDAC MC: Ver: 3.0.0
5783 13:44:24.780176 <6>[ 0.729220] FPGA manager framework
5784 13:44:24.784189 <6>[ 0.732907] Advanced Linux Sound Architecture Driver Initialized.
5785 13:44:24.787572 <6>[ 0.739665] vgaarb: loaded
5786 13:44:24.793913 <6>[ 0.742793] clocksource: Switched to clocksource arch_sys_counter
5787 13:44:24.800457 <5>[ 0.749225] VFS: Disk quotas dquot_6.6.0
5788 13:44:24.807249 <6>[ 0.753399] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
5789 13:44:24.810694 <6>[ 0.760572] pnp: PnP ACPI: disabled
5790 13:44:24.818456 <6>[ 0.767467] NET: Registered PF_INET protocol family
5791 13:44:24.825105 <6>[ 0.772700] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
5792 13:44:24.837079 <6>[ 0.782613] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
5793 13:44:24.843911 <6>[ 0.791367] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
5794 13:44:24.853832 <6>[ 0.799318] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
5795 13:44:24.860342 <6>[ 0.807551] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
5796 13:44:24.867450 <6>[ 0.815646] TCP: Hash tables configured (established 32768 bind 32768)
5797 13:44:24.877151 <6>[ 0.822475] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
5798 13:44:24.883531 <6>[ 0.829447] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
5799 13:44:24.890097 <6>[ 0.836929] NET: Registered PF_UNIX/PF_LOCAL protocol family
5800 13:44:24.893294 <6>[ 0.843030] RPC: Registered named UNIX socket transport module.
5801 13:44:24.900086 <6>[ 0.849173] RPC: Registered udp transport module.
5802 13:44:24.903365 <6>[ 0.854098] RPC: Registered tcp transport module.
5803 13:44:24.910409 <6>[ 0.859022] RPC: Registered tcp NFSv4.1 backchannel transport module.
5804 13:44:24.916996 <6>[ 0.865674] PCI: CLS 0 bytes, default 64
5805 13:44:24.920263 <6>[ 0.869964] Unpacking initramfs...
5806 13:44:24.933875 <6>[ 0.879403] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
5807 13:44:24.943503 <6>[ 0.888025] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
5808 13:44:24.947221 <6>[ 0.896876] kvm [1]: IPA Size Limit: 40 bits
5809 13:44:24.954053 <6>[ 0.903203] kvm [1]: vgic-v2@c420000
5810 13:44:24.957628 <6>[ 0.907020] kvm [1]: GIC system register CPU interface enabled
5811 13:44:24.964434 <6>[ 0.913185] kvm [1]: vgic interrupt IRQ18
5812 13:44:24.967353 <6>[ 0.917535] kvm [1]: Hyp mode initialized successfully
5813 13:44:24.974825 <5>[ 0.923831] Initialise system trusted keyrings
5814 13:44:24.981312 <6>[ 0.928659] workingset: timestamp_bits=42 max_order=20 bucket_order=0
5815 13:44:24.989319 <6>[ 0.938554] squashfs: version 4.0 (2009/01/31) Phillip Lougher
5816 13:44:24.996201 <5>[ 0.945031] NFS: Registering the id_resolver key type
5817 13:44:24.999464 <5>[ 0.950343] Key type id_resolver registered
5818 13:44:25.006047 <5>[ 0.954759] Key type id_legacy registered
5819 13:44:25.012823 <6>[ 0.959068] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
5820 13:44:25.019474 <6>[ 0.965987] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
5821 13:44:25.026021 <6>[ 0.973748] 9p: Installing v9fs 9p2000 file system support
5822 13:44:25.052978 <5>[ 1.002226] Key type asymmetric registered
5823 13:44:25.056876 <5>[ 1.006571] Asymmetric key parser 'x509' registered
5824 13:44:25.066618 <6>[ 1.011732] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
5825 13:44:25.070045 <6>[ 1.019350] io scheduler mq-deadline registered
5826 13:44:25.073118 <6>[ 1.024106] io scheduler kyber registered
5827 13:44:25.095512 <6>[ 1.044880] EINJ: ACPI disabled.
5828 13:44:25.102164 <4>[ 1.048648] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
5829 13:44:25.140645 <6>[ 1.089525] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
5830 13:44:25.148917 <6>[ 1.098025] printk: console [ttyS0] disabled
5831 13:44:25.177393 <6>[ 1.122678] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
5832 13:44:25.183684 <6>[ 1.132152] printk: console [ttyS0] enabled
5833 13:44:25.186913 <6>[ 1.132152] printk: console [ttyS0] enabled
5834 13:44:25.193556 <6>[ 1.141076] printk: bootconsole [mtk8250] disabled
5835 13:44:25.197102 <6>[ 1.141076] printk: bootconsole [mtk8250] disabled
5836 13:44:25.207084 <3>[ 1.151609] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
5837 13:44:25.213835 <3>[ 1.159991] mt6577-uart 11003000.serial: Error applying setting, reverse things back
5838 13:44:25.242982 <6>[ 1.188400] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
5839 13:44:25.249522 <6>[ 1.198053] serial serial0: tty port ttyS1 registered
5840 13:44:25.256095 <6>[ 1.204622] SuperH (H)SCI(F) driver initialized
5841 13:44:25.259246 <6>[ 1.210117] msm_serial: driver initialized
5842 13:44:25.275283 <6>[ 1.220467] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
5843 13:44:25.284781 <6>[ 1.229058] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
5844 13:44:25.291343 <6>[ 1.237633] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
5845 13:44:25.301381 <6>[ 1.246205] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
5846 13:44:25.307872 <6>[ 1.254861] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
5847 13:44:25.317741 <6>[ 1.263519] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
5848 13:44:25.328129 <6>[ 1.272255] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
5849 13:44:25.334567 <6>[ 1.280996] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
5850 13:44:25.344471 <6>[ 1.289561] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
5851 13:44:25.351076 <6>[ 1.298366] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
5852 13:44:25.361757 <4>[ 1.310773] cacheinfo: Unable to detect cache hierarchy for CPU 0
5853 13:44:25.370873 <6>[ 1.320090] loop: module loaded
5854 13:44:25.383075 <6>[ 1.332046] vsim1: Bringing 1800000uV into 2700000-2700000uV
5855 13:44:25.401184 <6>[ 1.350088] megasas: 07.719.03.00-rc1
5856 13:44:25.409983 <6>[ 1.358911] spi-nor spi1.0: w25q64dw (8192 Kbytes)
5857 13:44:25.417126 <6>[ 1.366183] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
5858 13:44:25.434194 <6>[ 1.383011] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
5859 13:44:25.490679 <6>[ 1.433175] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.5.130/cr50_v2.94_mp.110-683b8
5860 13:44:25.538858 <6>[ 1.487716] Freeing initrd memory: 18276K
5861 13:44:25.553666 <4>[ 1.499588] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
5862 13:44:25.560259 <4>[ 1.508820] CPU: 6 PID: 1 Comm: swapper/0 Not tainted 6.1.96-cip24 #1
5863 13:44:25.567109 <4>[ 1.515518] Hardware name: Google juniper sku16 board (DT)
5864 13:44:25.570988 <4>[ 1.521258] Call trace:
5865 13:44:25.574047 <4>[ 1.523958] dump_backtrace.part.0+0xe0/0xf0
5866 13:44:25.577075 <4>[ 1.528497] show_stack+0x18/0x30
5867 13:44:25.580621 <4>[ 1.532070] dump_stack_lvl+0x64/0x80
5868 13:44:25.583993 <4>[ 1.535990] dump_stack+0x18/0x34
5869 13:44:25.590795 <4>[ 1.539559] sysfs_warn_dup+0x64/0x80
5870 13:44:25.593823 <4>[ 1.543481] sysfs_do_create_link_sd+0xf0/0x100
5871 13:44:25.597750 <4>[ 1.548269] sysfs_create_link+0x20/0x40
5872 13:44:25.604146 <4>[ 1.552448] bus_add_device+0x64/0x120
5873 13:44:25.607443 <4>[ 1.556453] device_add+0x354/0x7ec
5874 13:44:25.610831 <4>[ 1.560199] of_device_add+0x44/0x60
5875 13:44:25.614165 <4>[ 1.564033] of_platform_device_create_pdata+0x90/0x124
5876 13:44:25.620678 <4>[ 1.569514] of_platform_bus_create+0x154/0x380
5877 13:44:25.624141 <4>[ 1.574300] of_platform_populate+0x50/0xfc
5878 13:44:25.630407 <4>[ 1.578739] parse_mtd_partitions+0x1d8/0x4e0
5879 13:44:25.634027 <4>[ 1.583356] mtd_device_parse_register+0xec/0x2e0
5880 13:44:25.637481 <4>[ 1.588318] spi_nor_probe+0x280/0x2f4
5881 13:44:25.640941 <4>[ 1.592322] spi_mem_probe+0x6c/0xc0
5882 13:44:25.643998 <4>[ 1.596155] spi_probe+0x84/0xe4
5883 13:44:25.650678 <4>[ 1.599641] really_probe+0xbc/0x2dc
5884 13:44:25.653872 <4>[ 1.603471] __driver_probe_device+0x78/0x114
5885 13:44:25.657361 <4>[ 1.608083] driver_probe_device+0xd8/0x15c
5886 13:44:25.664147 <4>[ 1.612520] __device_attach_driver+0xb8/0x134
5887 13:44:25.667482 <4>[ 1.617219] bus_for_each_drv+0x7c/0xd4
5888 13:44:25.671442 <4>[ 1.621311] __device_attach+0x9c/0x1a0
5889 13:44:25.677466 <4>[ 1.625401] device_initial_probe+0x14/0x20
5890 13:44:25.680786 <4>[ 1.629839] bus_probe_device+0x98/0xa0
5891 13:44:25.684274 <4>[ 1.633928] device_add+0x3c0/0x7ec
5892 13:44:25.687388 <4>[ 1.637674] __spi_add_device+0x78/0x120
5893 13:44:25.690630 <4>[ 1.641851] spi_add_device+0x44/0x80
5894 13:44:25.698179 <4>[ 1.645769] spi_register_controller+0x704/0xb20
5895 13:44:25.701521 <4>[ 1.650642] devm_spi_register_controller+0x4c/0xac
5896 13:44:25.704241 <4>[ 1.655775] mtk_spi_probe+0x4f4/0x684
5897 13:44:25.710822 <4>[ 1.659780] platform_probe+0x68/0xc0
5898 13:44:25.714116 <4>[ 1.663699] really_probe+0xbc/0x2dc
5899 13:44:25.717483 <4>[ 1.667529] __driver_probe_device+0x78/0x114
5900 13:44:25.724196 <4>[ 1.672140] driver_probe_device+0xd8/0x15c
5901 13:44:25.727969 <4>[ 1.676578] __driver_attach+0x94/0x19c
5902 13:44:25.730703 <4>[ 1.680668] bus_for_each_dev+0x74/0xd0
5903 13:44:25.734281 <4>[ 1.684760] driver_attach+0x24/0x30
5904 13:44:25.737478 <4>[ 1.688591] bus_add_driver+0x154/0x20c
5905 13:44:25.743995 <4>[ 1.692680] driver_register+0x78/0x130
5906 13:44:25.747521 <4>[ 1.696771] __platform_driver_register+0x28/0x34
5907 13:44:25.750623 <4>[ 1.701731] mtk_spi_driver_init+0x1c/0x28
5908 13:44:25.757321 <4>[ 1.706087] do_one_initcall+0x64/0x1dc
5909 13:44:25.760597 <4>[ 1.710178] kernel_init_freeable+0x218/0x284
5910 13:44:25.763968 <4>[ 1.714792] kernel_init+0x24/0x12c
5911 13:44:25.767591 <4>[ 1.718538] ret_from_fork+0x10/0x20
5912 13:44:25.778607 <6>[ 1.727463] tun: Universal TUN/TAP device driver, 1.6
5913 13:44:25.782035 <6>[ 1.733745] thunder_xcv, ver 1.0
5914 13:44:25.785039 <6>[ 1.737261] thunder_bgx, ver 1.0
5915 13:44:25.788528 <6>[ 1.740764] nicpf, ver 1.0
5916 13:44:25.799775 <6>[ 1.745138] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
5917 13:44:25.803196 <6>[ 1.752622] hns3: Copyright (c) 2017 Huawei Corporation.
5918 13:44:25.806361 <6>[ 1.758219] hclge is initializing
5919 13:44:25.813046 <6>[ 1.761804] e1000: Intel(R) PRO/1000 Network Driver
5920 13:44:25.819479 <6>[ 1.766938] e1000: Copyright (c) 1999-2006 Intel Corporation.
5921 13:44:25.823207 <6>[ 1.772959] e1000e: Intel(R) PRO/1000 Network Driver
5922 13:44:25.829848 <6>[ 1.778180] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
5923 13:44:25.836423 <6>[ 1.784375] igb: Intel(R) Gigabit Ethernet Network Driver
5924 13:44:25.843160 <6>[ 1.790031] igb: Copyright (c) 2007-2014 Intel Corporation.
5925 13:44:25.850006 <6>[ 1.795875] igbvf: Intel(R) Gigabit Virtual Function Network Driver
5926 13:44:25.853122 <6>[ 1.802398] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
5927 13:44:25.860236 <6>[ 1.808957] sky2: driver version 1.30
5928 13:44:25.866696 <6>[ 1.814218] usbcore: registered new device driver r8152-cfgselector
5929 13:44:25.873436 <6>[ 1.820760] usbcore: registered new interface driver r8152
5930 13:44:25.876922 <6>[ 1.826591] VFIO - User Level meta-driver version: 0.3
5931 13:44:25.885178 <6>[ 1.834370] mtu3 11201000.usb: uwk - reg:0x420, version:101
5932 13:44:25.892519 <4>[ 1.840244] mtu3 11201000.usb: supply vbus not found, using dummy regulator
5933 13:44:25.898970 <6>[ 1.847520] mtu3 11201000.usb: dr_mode: 1, drd: auto
5934 13:44:25.905772 <6>[ 1.852746] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
5935 13:44:25.908638 <6>[ 1.858935] mtu3 11201000.usb: usb3-drd: 0
5936 13:44:25.919033 <6>[ 1.864500] mtu3 11201000.usb: xHCI platform device register success...
5937 13:44:25.925811 <4>[ 1.873139] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
5938 13:44:25.932233 <6>[ 1.881101] xhci-mtk 11200000.usb: xHCI Host Controller
5939 13:44:25.939093 <6>[ 1.886606] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
5940 13:44:25.945874 <6>[ 1.894322] xhci-mtk 11200000.usb: USB3 root hub has no ports
5941 13:44:25.955655 <6>[ 1.900349] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
5942 13:44:25.962167 <6>[ 1.909776] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
5943 13:44:25.965358 <6>[ 1.915851] xhci-mtk 11200000.usb: xHCI Host Controller
5944 13:44:25.976160 <6>[ 1.921340] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
5945 13:44:25.982250 <6>[ 1.929001] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
5946 13:44:25.985975 <6>[ 1.935819] hub 1-0:1.0: USB hub found
5947 13:44:25.988961 <6>[ 1.939865] hub 1-0:1.0: 1 port detected
5948 13:44:25.999842 <6>[ 1.945233] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
5949 13:44:26.003148 <6>[ 1.953848] hub 2-0:1.0: USB hub found
5950 13:44:26.009633 <3>[ 1.957874] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
5951 13:44:26.016768 <6>[ 1.965758] usbcore: registered new interface driver usb-storage
5952 13:44:26.023137 <6>[ 1.972372] usbcore: registered new device driver onboard-usb-hub
5953 13:44:26.041054 <4>[ 1.986914] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
5954 13:44:26.050521 <6>[ 1.999193] mt6397-rtc mt6358-rtc: registered as rtc0
5955 13:44:26.060213 <6>[ 2.004674] mt6397-rtc mt6358-rtc: setting system clock to 2024-07-18T13:44:25 UTC (1721310265)
5956 13:44:26.063444 <6>[ 2.014556] i2c_dev: i2c /dev entries driver
5957 13:44:26.075329 <6>[ 2.020970] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5958 13:44:26.085581 <6>[ 2.029287] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5959 13:44:26.088602 <6>[ 2.038192] i2c 4-0058: Fixed dependency cycle(s) with /panel
5960 13:44:26.098384 <6>[ 2.044232] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
5961 13:44:26.114717 <6>[ 2.063691] cpu cpu0: EM: created perf domain
5962 13:44:26.124582 <6>[ 2.069218] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
5963 13:44:26.131493 <6>[ 2.080507] cpu cpu4: EM: created perf domain
5964 13:44:26.138409 <6>[ 2.087576] sdhci: Secure Digital Host Controller Interface driver
5965 13:44:26.145181 <6>[ 2.094031] sdhci: Copyright(c) Pierre Ossman
5966 13:44:26.152050 <6>[ 2.099440] Synopsys Designware Multimedia Card Interface Driver
5967 13:44:26.159074 <6>[ 2.099992] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
5968 13:44:26.161968 <6>[ 2.106486] sdhci-pltfm: SDHCI platform and OF driver helper
5969 13:44:26.170542 <6>[ 2.119211] ledtrig-cpu: registered to indicate activity on CPUs
5970 13:44:26.177758 <6>[ 2.126948] usbcore: registered new interface driver usbhid
5971 13:44:26.181696 <6>[ 2.132786] usbhid: USB HID core driver
5972 13:44:26.192388 <6>[ 2.137113] spi_master spi2: will run message pump with realtime priority
5973 13:44:26.195921 <4>[ 2.137411] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
5974 13:44:26.202901 <4>[ 2.151484] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
5975 13:44:26.216611 <6>[ 2.156593] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
5976 13:44:26.235347 <6>[ 2.174199] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
5977 13:44:26.241682 <4>[ 2.187088] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
5978 13:44:26.245304 <6>[ 2.188634] cros-ec-spi spi2.0: Chrome EC device registered
5979 13:44:26.260133 <4>[ 2.205474] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
5980 13:44:26.266913 <6>[ 2.215783] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x11c14
5981 13:44:26.276478 <4>[ 2.217184] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
5982 13:44:26.280018 <6>[ 2.222280] mmc0: new HS400 MMC card at address 0001
5983 13:44:26.287232 <4>[ 2.230433] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
5984 13:44:26.293776 <6>[ 2.242119] mmcblk0: mmc0:0001 TB2932 29.2 GiB
5985 13:44:26.301171 <6>[ 2.250120] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
5986 13:44:26.307837 <6>[ 2.250200] mmc1: new ultra high speed SDR104 SDIO card at address 0001
5987 13:44:26.314630 <6>[ 2.257090] mmcblk0boot0: mmc0:0001 TB2932 4.00 MiB
5988 13:44:26.321212 <6>[ 2.258773] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
5989 13:44:26.334559 <6>[ 2.265869] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
5990 13:44:26.338037 <6>[ 2.269509] mmcblk0boot1: mmc0:0001 TB2932 4.00 MiB
5991 13:44:26.344460 <6>[ 2.277916] NET: Registered PF_PACKET protocol family
5992 13:44:26.351196 <6>[ 2.288671] mmcblk0rpmb: mmc0:0001 TB2932 4.00 MiB, chardev (507:0)
5993 13:44:26.354867 <6>[ 2.292989] 9pnet: Installing 9P2000 support
5994 13:44:26.368359 <6>[ 2.299356] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
5995 13:44:26.371494 <5>[ 2.304778] Key type dns_resolver registered
5996 13:44:26.381433 <6>[ 2.309883] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
5997 13:44:26.385031 <6>[ 2.321779] registered taskstats version 1
5998 13:44:26.392034 <5>[ 2.340210] Loading compiled-in X.509 certificates
5999 13:44:26.417287 <6>[ 2.362947] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6000 13:44:26.442985 <3>[ 2.388451] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6001 13:44:26.473024 <6>[ 2.415521] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6002 13:44:26.483668 <6>[ 2.428973] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6003 13:44:26.493167 <6>[ 2.437642] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6004 13:44:26.500359 <6>[ 2.446237] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6005 13:44:26.509907 <6>[ 2.454838] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6006 13:44:26.516512 <6>[ 2.463387] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6007 13:44:26.526715 <6>[ 2.471926] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6008 13:44:26.533539 <6>[ 2.480498] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6009 13:44:26.540746 <6>[ 2.489764] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6010 13:44:26.548631 <6>[ 2.497273] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6011 13:44:26.555496 <6>[ 2.504543] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6012 13:44:26.565791 <6>[ 2.511771] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6013 13:44:26.569477 <6>[ 2.517661] hub 1-1:1.0: USB hub found
6014 13:44:26.575971 <6>[ 2.519242] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6015 13:44:26.579079 <6>[ 2.522920] hub 1-1:1.0: 3 ports detected
6016 13:44:26.586150 <6>[ 2.530780] panfrost 13040000.gpu: clock rate = 511999970
6017 13:44:26.596186 <6>[ 2.539102] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6018 13:44:26.603041 <6>[ 2.549145] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6019 13:44:26.612877 <6>[ 2.557158] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6020 13:44:26.622729 <6>[ 2.565591] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6021 13:44:26.629593 <6>[ 2.577671] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6022 13:44:26.641851 <6>[ 2.587723] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6023 13:44:26.652091 <6>[ 2.596445] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6024 13:44:26.662387 <6>[ 2.605607] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6025 13:44:26.668754 <6>[ 2.614742] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6026 13:44:26.678718 <6>[ 2.623871] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6027 13:44:26.688845 <6>[ 2.633174] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6028 13:44:26.698609 <6>[ 2.642473] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6029 13:44:26.708460 <6>[ 2.651949] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6030 13:44:26.715396 <6>[ 2.661423] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6031 13:44:26.724983 <6>[ 2.670550] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6032 13:44:26.796256 <6>[ 2.742080] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6033 13:44:26.806126 <6>[ 2.750960] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6034 13:44:26.817271 <6>[ 2.762746] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6035 13:44:26.877142 <6>[ 2.822833] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
6036 13:44:26.979534 <6>[ 2.928030] hub 1-1.1:1.0: USB hub found
6037 13:44:26.982423 <6>[ 2.932317] hub 1-1.1:1.0: 4 ports detected
6038 13:44:27.543245 <6>[ 3.475673] Console: switching to colour frame buffer device 170x48
6039 13:44:27.553490 <6>[ 3.498904] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6040 13:44:27.573462 <6>[ 3.515295] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6041 13:44:27.589671 <6>[ 3.531883] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6042 13:44:27.596352 <6>[ 3.544267] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6043 13:44:27.606961 <6>[ 3.552409] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6044 13:44:27.616630 <6>[ 3.557702] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6045 13:44:27.634568 <6>[ 3.576637] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6046 13:44:27.640960 <6>[ 3.586834] usb 1-1.2: new high-speed USB device number 4 using xhci-mtk
6047 13:44:27.647541 <6>[ 3.587986] Trying to probe devices needed for running init ...
6048 13:44:27.659071 <3>[ 3.604549] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: could not get audiosys reset:-517
6049 13:44:27.673360 <6>[ 3.615557] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6050 13:44:27.833398 <6>[ 3.779007] r8152-cfgselector 1-1.2: reset high-speed USB device number 4 using xhci-mtk
6051 13:44:27.945343 <4>[ 3.890565] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6052 13:44:27.954855 <4>[ 3.899958] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6053 13:44:27.995735 <6>[ 3.944281] r8152 1-1.2:1.0 eth0: v1.12.13
6054 13:44:28.014673 <6>[ 3.956738] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6055 13:44:28.021090 <6>[ 3.967799] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
6056 13:44:28.209632 <6>[ 4.155176] usb 1-1.3: new high-speed USB device number 6 using xhci-mtk
6057 13:44:28.348883 <6>[ 4.291345] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6058 13:44:28.401634 <6>[ 4.347302] r8152-cfgselector 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
6059 13:44:28.519206 <4>[ 4.464733] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6060 13:44:28.531499 <4>[ 4.477246] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6061 13:44:28.575908 <6>[ 4.525030] r8152 1-1.1.1:1.0 eth1: v1.12.13
6062 13:44:28.604535 <6>[ 4.547029] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6063 13:44:29.625290 <6>[ 5.574253] r8152 1-1.2:1.0 eth0: carrier on
6064 13:44:31.989512 <5>[ 5.594827] Sending DHCP requests .., OK
6065 13:44:32.002007 <6>[ 7.948273] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.17
6066 13:44:32.012100 <6>[ 7.961689] IP-Config: Complete:
6067 13:44:32.027520 <6>[ 7.970219] device=eth0, hwaddr=00:e0:4c:68:03:2b, ipaddr=192.168.201.17, mask=255.255.255.0, gw=192.168.201.1
6068 13:44:32.040282 <6>[ 7.986128] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-5, domain=lava-rack, nis-domain=(none)
6069 13:44:32.053383 <6>[ 7.999527] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6070 13:44:32.061144 <6>[ 7.999536] nameserver0=192.168.201.1
6071 13:44:32.090310 <6>[ 8.039942] clk: Disabling unused clocks
6072 13:44:32.097348 <6>[ 8.050082] ALSA device list:
6073 13:44:32.105804 <6>[ 8.055296] No soundcards found.
6074 13:44:32.113801 <6>[ 8.063236] Freeing unused kernel memory: 8512K
6075 13:44:32.120556 <6>[ 8.070137] Run /init as init process
6076 13:44:32.130820 Loading, please wait...
6077 13:44:32.157728 Starting systemd-udevd version 252.22-1~deb12u1
6078 13:44:32.457802 <3>[ 8.406994] thermal_sys: Failed to find 'trips' node
6079 13:44:32.467602 <3>[ 8.413041] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6080 13:44:32.474127 <3>[ 8.421126] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6081 13:44:32.484210 <3>[ 8.421477] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6082 13:44:32.493868 <4>[ 8.429562] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6083 13:44:32.497357 <3>[ 8.430915] thermal_sys: Failed to find 'trips' node
6084 13:44:32.507872 <3>[ 8.439563] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6085 13:44:32.517940 <3>[ 8.439570] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6086 13:44:32.524568 <3>[ 8.439575] elan_i2c 2-0015: Error applying setting, reverse things back
6087 13:44:32.531133 <4>[ 8.462958] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6088 13:44:32.541152 <5>[ 8.465518] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6089 13:44:32.547587 <6>[ 8.470263] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6090 13:44:32.554280 <3>[ 8.472460] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6091 13:44:32.564774 <3>[ 8.472473] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6092 13:44:32.571650 <5>[ 8.480726] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6093 13:44:32.578073 <4>[ 8.482933] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6094 13:44:32.588091 <4>[ 8.486724] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6095 13:44:32.598532 <4>[ 8.491766] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6096 13:44:32.608301 <5>[ 8.495216] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6097 13:44:32.617969 <6>[ 8.510303] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6098 13:44:32.625669 <4>[ 8.510958] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6099 13:44:32.632989 <6>[ 8.512657] mc: Linux media interface: v0.10
6100 13:44:32.646446 <6>[ 8.521871] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6101 13:44:32.653021 <6>[ 8.526260] cfg80211: failed to load regulatory.db
6102 13:44:32.662708 <3>[ 8.532087] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6103 13:44:32.672520 <3>[ 8.532109] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6104 13:44:32.679463 <3>[ 8.532118] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6105 13:44:32.686133 <6>[ 8.532990] videodev: Linux video capture interface: v2.00
6106 13:44:32.695807 <3>[ 8.534397] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6107 13:44:32.702544 <6>[ 8.539254] cs_system_cfg: CoreSight Configuration manager initialised
6108 13:44:32.715830 <3>[ 8.555616] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6109 13:44:32.722529 <6>[ 8.556056] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6110 13:44:32.732409 <3>[ 8.561518] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6111 13:44:32.736020 <6>[ 8.562097] r8152 1-1.1.1:1.0 enx88541f0f7aca: renamed from eth1
6112 13:44:32.745723 <6>[ 8.615057] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6113 13:44:32.755733 <3>[ 8.617423] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6114 13:44:32.762601 <6>[ 8.636107] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6115 13:44:32.768822 <6>[ 8.636585] Bluetooth: Core ver 2.22
6116 13:44:32.772216 <6>[ 8.636916] NET: Registered PF_BLUETOOTH protocol family
6117 13:44:32.778713 <6>[ 8.636923] Bluetooth: HCI device and connection manager initialized
6118 13:44:32.785324 <6>[ 8.636941] Bluetooth: HCI socket layer initialized
6119 13:44:32.788737 <6>[ 8.636948] Bluetooth: L2CAP socket layer initialized
6120 13:44:32.795159 <6>[ 8.636983] Bluetooth: SCO socket layer initialized
6121 13:44:32.801859 <3>[ 8.637469] mtk-scp 10500000.scp: invalid resource
6122 13:44:32.808955 <6>[ 8.637524] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6123 13:44:32.815349 <6>[ 8.638499] remoteproc remoteproc0: scp is available
6124 13:44:32.821668 <4>[ 8.638575] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6125 13:44:32.828530 <6>[ 8.638580] remoteproc remoteproc0: powering up scp
6126 13:44:32.835198 <4>[ 8.638599] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6127 13:44:32.842076 <3>[ 8.638603] remoteproc remoteproc0: request_firmware failed: -2
6128 13:44:32.852105 Begin: Loading e<3>[ 8.641112] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6129 13:44:32.862460 ssential drivers<6>[ 8.650267] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6130 13:44:32.862535 ... done.
6131 13:44:32.871879 Begi<3>[ 8.656568] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6132 13:44:32.881901 n: Running /scri<6>[ 8.670450] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6133 13:44:32.892011 pts/init-premoun<3>[ 8.677050] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6134 13:44:32.892084 t ... done.
6135 13:44:32.901957 Beg<6>[ 8.685429] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6136 13:44:32.908590 in: Mounting roo<6>[ 8.686057] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6137 13:44:32.918370 t file system ..<6>[ 8.686562] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6138 13:44:32.925037 . Begin: Running<6>[ 8.687005] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6139 13:44:32.935349 /scripts/nfs-to<6>[ 8.687018] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video0 (81,0)
6140 13:44:32.935426 p ... done.
6141 13:44:32.945087 Beg<6>[ 8.687690] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video1
6142 13:44:32.951925 in: Running /scr<6>[ 8.701917] Bluetooth: HCI UART driver ver 2.3
6143 13:44:32.965319 ipts/nfs-premoun<6>[ 8.705294] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6144 13:44:32.971724 t ... Waiting up<6>[ 8.705447] usbcore: registered new interface driver uvcvideo
6145 13:44:32.981719 to 60 secs for <6>[ 8.710619] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6146 13:44:32.988232 any ethernet to <6>[ 8.718191] Bluetooth: HCI UART protocol H4 registered
6147 13:44:32.994832 become available<6>[ 8.722221] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6148 13:44:32.998274
6149 13:44:33.004877 Device /sys/cl<6>[ 8.727790] Bluetooth: HCI UART protocol LL registered
6150 13:44:33.011384 ass/net/enx88541<6>[ 8.734220] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6151 13:44:33.014944 f0f7aca found
6152 13:44:33.021539 d<6>[ 8.739333] Bluetooth: HCI UART protocol Three-wire (H5) registered
6153 13:44:33.021608 one.
6154 13:44:33.031715 Begin: Wai<6>[ 8.749735] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6155 13:44:33.035216 <6>[ 8.750904] Bluetooth: HCI UART protocol Broadcom registered
6156 13:44:33.048561 <3>[ 8.750968] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6157 13:44:33.055566 ting up to 180 s<3>[ 8.751881] debugfs: File 'Playback' in directory 'dapm' already present!
6158 13:44:33.065317 ecs for any netw<3>[ 8.751889] debugfs: File 'Capture' in directory 'dapm' already present!
6159 13:44:33.078704 ork device to be<6>[ 8.753564] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input6
6160 13:44:33.088679 come available .<6>[ 8.763933] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6161 13:44:33.088753 .. done.
6162 13:44:33.095565 <6>[ 8.763991] Bluetooth: HCI UART protocol QCA registered
6163 13:44:33.101773 <6>[ 8.765094] Bluetooth: hci0: setting up ROME/QCA6390
6164 13:44:33.108461 <6>[ 8.769165] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6165 13:44:33.116260 <6>[ 8.777613] Bluetooth: HCI UART protocol Marvell registered
6166 13:44:33.129611 IP-Config: enx88541f0f7aca hardw<6>[ 8.782855] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6167 13:44:33.139591 are address 88:5<4>[ 8.904891] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6168 13:44:33.146101 <4>[ 8.904891] Fallback method does not support PEC.
6169 13:44:33.152609 4:1f:0f:7a:ca mt<3>[ 8.982376] Bluetooth: hci0: Frame reassembly failed (-84)
6170 13:44:33.152689 u 1500 DHCP
6171 13:44:33.162302 <3>[ 8.987940] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6172 13:44:33.169013 <6>[ 9.057301] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6173 13:44:33.179458 <3>[ 9.070517] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6174 13:44:33.241366 IP-Config: eth0 hardware address 00:e0:4c:68:03:2b mtu 1500 DHCP
6175 13:44:33.247962 IP-Config: eth0 complete (dhcp from 192.168.201.1):
6176 13:44:33.254774 address: 192.168.201.17 broadcast: 192.168.201.255 netmask: 255.255.255.0
6177 13:44:33.261659 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
6178 13:44:33.268152 host : mt8183-kukui-jacuzzi-juniper-sku16-cbg-5
6179 13:44:33.274673 domain : lava-rack
6180 13:44:33.277824 rootserver: 192.168.201.1 rootpath:
6181 13:44:33.277896 filename :
6182 13:44:33.306017 <6>[ 9.255690] Bluetooth: hci0: QCA Product ID :0x00000008
6183 13:44:33.315933 <6>[ 9.265443] Bluetooth: hci0: QCA SOC Version :0x00000044
6184 13:44:33.325438 <6>[ 9.275031] Bluetooth: hci0: QCA ROM Version :0x00000302
6185 13:44:33.334521 <6>[ 9.283558] Bluetooth: hci0: QCA Patch Version:0x00000111
6186 13:44:33.342948 <6>[ 9.292170] Bluetooth: hci0: QCA controller version 0x00440302
6187 13:44:33.356488 <6>[ 9.302678] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6188 13:44:33.367331 <4>[ 9.313269] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6189 13:44:33.367408 done.
6190 13:44:33.380235 <3>[ 9.326019] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6191 13:44:33.387519 <3>[ 9.336893] Bluetooth: hci0: QCA Failed to download patch (-2)
6192 13:44:33.398555 Begin: Running /scripts/nfs-bottom ... done.
6193 13:44:33.423047 Begin: Running /scripts/init-bottom ... done.
6194 13:44:33.557424 <6>[ 9.503459] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6195 13:44:33.636313 <4>[ 9.585735] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6196 13:44:33.659157 <4>[ 9.605433] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6197 13:44:33.675159 <4>[ 9.621393] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6198 13:44:33.685541 <4>[ 9.635074] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6199 13:44:34.754406 <6>[ 10.704001] NET: Registered PF_INET6 protocol family
6200 13:44:34.766745 <6>[ 10.716032] Segment Routing with IPv6
6201 13:44:34.773698 <6>[ 10.723321] In-situ OAM (IOAM) with IPv6
6202 13:44:34.945353 <30>[ 10.868229] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6203 13:44:34.966718 <30>[ 10.916193] systemd[1]: Detected architecture arm64.
6204 13:44:34.978045
6205 13:44:34.981144 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6206 13:44:34.981271
6207 13:44:35.010180 <30>[ 10.959655] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6208 13:44:35.959782 <30>[ 11.905818] systemd[1]: Queued start job for default target graphical.target.
6209 13:44:36.010600 <30>[ 11.956215] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6210 13:44:36.022927 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6211 13:44:36.043616 <30>[ 11.989327] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6212 13:44:36.057183 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6213 13:44:36.075644 <30>[ 12.021345] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6214 13:44:36.090008 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6215 13:44:36.110564 <30>[ 12.056436] systemd[1]: Created slice user.slice - User and Session Slice.
6216 13:44:36.122968 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6217 13:44:36.145435 <30>[ 12.087404] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6218 13:44:36.157807 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6219 13:44:36.176605 <30>[ 12.119238] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6220 13:44:36.189332 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6221 13:44:36.215157 <30>[ 12.151181] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6222 13:44:36.234669 <30>[ 12.180709] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6223 13:44:36.242824 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6224 13:44:36.261220 <30>[ 12.206994] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6225 13:44:36.274098 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6226 13:44:36.293002 <30>[ 12.239042] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6227 13:44:36.307495 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6228 13:44:36.321834 <30>[ 12.271097] systemd[1]: Reached target paths.target - Path Units.
6229 13:44:36.337130 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6230 13:44:36.353065 <30>[ 12.299014] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6231 13:44:36.365570 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6232 13:44:36.377954 <30>[ 12.326962] systemd[1]: Reached target slices.target - Slice Units.
6233 13:44:36.392278 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6234 13:44:36.405791 <30>[ 12.355021] systemd[1]: Reached target swap.target - Swaps.
6235 13:44:36.416691 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6236 13:44:36.437337 <30>[ 12.383033] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6237 13:44:36.449392 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6238 13:44:36.465468 <30>[ 12.411506] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6239 13:44:36.479351 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6240 13:44:36.500201 <30>[ 12.445963] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6241 13:44:36.513464 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6242 13:44:36.531084 <30>[ 12.476752] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6243 13:44:36.544945 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6244 13:44:36.561758 <30>[ 12.507767] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6245 13:44:36.574076 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6246 13:44:36.595301 <30>[ 12.540844] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6247 13:44:36.608860 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6248 13:44:36.628880 <30>[ 12.574401] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6249 13:44:36.642854 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6250 13:44:36.662399 <30>[ 12.607618] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6251 13:44:36.675511 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6252 13:44:36.717714 <30>[ 12.663151] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6253 13:44:36.730127 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6254 13:44:36.751229 <30>[ 12.696922] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6255 13:44:36.764336 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6256 13:44:36.784914 <30>[ 12.730374] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6257 13:44:36.796434 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6258 13:44:36.820760 <30>[ 12.759784] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6259 13:44:36.862204 <30>[ 12.807554] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6260 13:44:36.874750 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6261 13:44:36.900082 <30>[ 12.845564] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6262 13:44:36.914385 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6263 13:44:36.933751 <30>[ 12.879337] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6264 13:44:36.945479 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6265 13:44:36.967033 <30>[ 12.912530] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6266 13:44:36.978913 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
6267 13:44:37.005296 <6>[ 12.950758] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6268 13:44:37.025956 <30>[ 12.971492] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6269 13:44:37.037995 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6270 13:44:37.058144 <30>[ 13.003721] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
6271 13:44:37.071586 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
6272 13:44:37.094836 <30>[ 13.040428] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6273 13:44:37.102848 Startin<6>[ 13.052044] fuse: init (API version 7.37)
6274 13:44:37.109343 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6275 13:44:37.154505 <30>[ 13.099991] systemd[1]: Starting systemd-journald.service - Journal Service...
6276 13:44:37.167718 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6277 13:44:37.189952 <30>[ 13.135189] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6278 13:44:37.200005 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6279 13:44:37.224491 <30>[ 13.167007] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6280 13:44:37.236113 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6281 13:44:37.258713 <30>[ 13.204138] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6282 13:44:37.271493 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6283 13:44:37.293545 <30>[ 13.239300] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6284 13:44:37.305668 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6285 13:44:37.327373 <30>[ 13.273043] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
6286 13:44:37.337676 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
6287 13:44:37.354391 <30>[ 13.299410] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
6288 13:44:37.363836 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
6289 13:44:37.374974 <3>[ 13.320023] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6290 13:44:37.382216 <30>[ 13.329130] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
6291 13:44:37.392028 <3>[ 13.335239] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6292 13:44:37.403540 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
6293 13:44:37.409915 <3>[ 13.355253] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6294 13:44:37.421041 <30>[ 13.365508] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
6295 13:44:37.427893 <3>[ 13.372182] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6296 13:44:37.447662 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static D<3>[ 13.391237] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6297 13:44:37.448071 evice Nodes.
6298 13:44:37.462693 <3>[ 13.408361] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6299 13:44:37.470373 <30>[ 13.418398] systemd[1]: modprobe@configfs.service: Deactivated successfully.
6300 13:44:37.480617 <3>[ 13.424192] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6301 13:44:37.488363 <30>[ 13.426458] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
6302 13:44:37.498183 <3>[ 13.440158] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6303 13:44:37.514523 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6304 13:44:37.530054 <30>[ 13.475719] systemd[1]: Started systemd-journald.service - Journal Service.
6305 13:44:37.543875 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6306 13:44:37.566986 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6307 13:44:37.588754 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6308 13:44:37.607873 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6309 13:44:37.628203 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
6310 13:44:37.652626 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6311 13:44:37.675867 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6312 13:44:37.699345 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6313 13:44:37.718878 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
6314 13:44:37.744824 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6315 13:44:37.798533 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
6316 13:44:37.822614 <4>[ 13.760881] synth uevent: /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:i2c-tunnel/i2c-12/12-000b/power_supply/sbs-12-000b: failed to send uevent
6317 13:44:37.833392 <3>[ 13.778698] power_supply sbs-12-000b: uevent: failed to send synthetic uevent: -5
6318 13:44:37.840317 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6319 13:44:37.869762 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
6320 13:44:37.890684 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6321 13:44:37.917177 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
6322 13:44:37.946683 <46>[ 13.892189] systemd-journald[324]: Received client request to flush runtime journal.
6323 13:44:37.958733 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6324 13:44:37.992829 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6325 13:44:38.011273 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
6326 13:44:38.035370 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6327 13:44:38.060178 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6328 13:44:38.080125 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6329 13:44:39.076190 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6330 13:44:39.126650 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6331 13:44:39.440810 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6332 13:44:39.557009 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6333 13:44:39.574419 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6334 13:44:39.593912 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6335 13:44:39.638676 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6336 13:44:39.661560 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6337 13:44:39.959565 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6338 13:44:40.025942 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6339 13:44:40.066639 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6340 13:44:40.268473 <4>[ 16.216654] power_supply_show_property: 4 callbacks suppressed
6341 13:44:40.278918 <3>[ 16.216672] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6342 13:44:40.295125 <3>[ 16.240532] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6343 13:44:40.309374 <3>[ 16.254917] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6344 13:44:40.327091 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/system<3>[ 16.271313] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6345 13:44:40.327178 d-backlight.
6346 13:44:40.342759 <3>[ 16.288562] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6347 13:44:40.354272 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6348 13:44:40.360963 <3>[ 16.306995] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6349 13:44:40.376528 <3>[ 16.321854] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6350 13:44:40.391057 <3>[ 16.336406] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6351 13:44:40.405923 <3>[ 16.350937] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6352 13:44:40.420031 Starting [0;1;39msystemd-backlight…ess of backlight:<3>[ 16.365491] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6353 13:44:40.423446 backlight_lcd0...
6354 13:44:40.468040 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6355 13:44:40.488981 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6356 13:44:40.577586 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6357 13:44:40.604469 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6358 13:44:40.625732 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6359 13:44:40.718545 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6360 13:44:40.841680 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6361 13:44:40.861271 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6362 13:44:40.884661 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6363 13:44:40.917077 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6364 13:44:40.936711 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6365 13:44:40.958430 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6366 13:44:40.981333 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6367 13:44:41.004523 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6368 13:44:41.024305 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6369 13:44:41.041124 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6370 13:44:41.063585 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6371 13:44:41.085708 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6372 13:44:41.108669 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6373 13:44:41.135381 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
6374 13:44:41.157290 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
6375 13:44:41.175067 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
6376 13:44:41.197892 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
6377 13:44:41.218685 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6378 13:44:41.238161 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6379 13:44:41.254459 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6380 13:44:41.273052 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6381 13:44:41.290704 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6382 13:44:41.309801 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6383 13:44:41.362981 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
6384 13:44:41.383479 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6385 13:44:41.436312 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
6386 13:44:41.505285 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6387 13:44:41.530794 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6388 13:44:41.553536 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
6389 13:44:41.570679 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6390 13:44:41.643268 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6391 13:44:41.682254 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6392 13:44:41.729114 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6393 13:44:41.748012 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6394 13:44:41.811659 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6395 13:44:41.855960 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
6396 13:44:41.881421 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6397 13:44:41.899442 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6398 13:44:41.921294 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6399 13:44:41.971405 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6400 13:44:42.029136 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6401 13:44:42.132393
6402 13:44:42.135890 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6403 13:44:42.135964
6404 13:44:42.139512 debian-bookworm-arm64 login: root (automatic login)
6405 13:44:42.139588
6406 13:44:42.412961 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024 aarch64
6407 13:44:42.413188
6408 13:44:42.419114 The programs included with the Debian GNU/Linux system are free software;
6409 13:44:42.425938 the exact distribution terms for each program are described in the
6410 13:44:42.429134 individual files in /usr/share/doc/*/copyright.
6411 13:44:42.429256
6412 13:44:42.435989 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6413 13:44:42.439183 permitted by applicable law.
6414 13:44:43.665801 Matched prompt #10: / #
6416 13:44:43.666812 Setting prompt string to ['/ #']
6417 13:44:43.667219 end: 2.2.5.1 login-action (duration 00:00:20) [common]
6419 13:44:43.668089 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
6420 13:44:43.668503 start: 2.2.6 expect-shell-connection (timeout 00:03:47) [common]
6421 13:44:43.668805 Setting prompt string to ['/ #']
6422 13:44:43.669078 Forcing a shell prompt, looking for ['/ #']
6423 13:44:43.669403 Sending line: ''
6425 13:44:43.720590 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6426 13:44:43.721027 Waiting using forced prompt support (timeout 00:02:30)
6427 13:44:43.727048 / #
6428 13:44:43.727951 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6429 13:44:43.728478 start: 2.2.7 export-device-env (timeout 00:03:47) [common]
6430 13:44:43.728899 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14879038/extract-nfsrootfs-fj34yvmf'"
6432 13:44:43.836146 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14879038/extract-nfsrootfs-fj34yvmf'
6433 13:44:43.836889 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
6435 13:44:43.942869 / # export NFS_SERVER_IP='192.168.201.1'
6436 13:44:43.943154 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6437 13:44:43.943261 end: 2.2 depthcharge-retry (duration 00:01:13) [common]
6438 13:44:43.943375 end: 2 depthcharge-action (duration 00:01:13) [common]
6439 13:44:43.943486 start: 3 lava-test-retry (timeout 00:08:09) [common]
6440 13:44:43.943592 start: 3.1 lava-test-shell (timeout 00:08:09) [common]
6441 13:44:43.943692 Using namespace: common
6442 13:44:43.943783 Sending line: '#'
6444 13:44:44.045030 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6445 13:44:44.051017 / # #
6446 13:44:44.051829 Using /lava-14879038
6447 13:44:44.052177 Sending line: 'export SHELL=/bin/bash'
6449 13:44:44.159202 / # export SHELL=/bin/bash
6450 13:44:44.159458 Sending line: '. /lava-14879038/environment'
6452 13:44:44.266017 / # . /lava-14879038/environment
6453 13:44:44.273090 Sending line: '/lava-14879038/bin/lava-test-runner /lava-14879038/0'
6455 13:44:44.374840 Test shell timeout: 10s (minimum of the action and connection timeout)
6456 13:44:44.380493 / # /lava-14879038/bin/lava-test-runner /lava-14879038/0
6457 13:44:44.657304 + export TESTRUN_ID=0_timesync-off
6458 13:44:44.660523 + TESTRUN_ID=0_timesync-off
6459 13:44:44.663594 + cd /lava-14879038/0/tests/0_timesync-off
6460 13:44:44.666862 ++ cat uuid
6461 13:44:44.673585 + UUID=14879038_1.6.2.3.1
6462 13:44:44.673949 + set +x
6463 13:44:44.680172 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14879038_1.6.2.3.1>
6464 13:44:44.680795 Received signal: <STARTRUN> 0_timesync-off 14879038_1.6.2.3.1
6465 13:44:44.681112 Starting test lava.0_timesync-off (14879038_1.6.2.3.1)
6466 13:44:44.681577 Skipping test definition patterns.
6467 13:44:44.683254 + systemctl stop systemd-timesyncd
6468 13:44:44.759195 + set +x
6469 13:44:44.762059 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14879038_1.6.2.3.1>
6470 13:44:44.762467 Received signal: <ENDRUN> 0_timesync-off 14879038_1.6.2.3.1
6471 13:44:44.762668 Ending use of test pattern.
6472 13:44:44.762821 Ending test lava.0_timesync-off (14879038_1.6.2.3.1), duration 0.08
6474 13:44:44.841449 + export TESTRUN_ID=1_kselftest-alsa
6475 13:44:44.841617 + TESTRUN_ID=1_kselftest-alsa
6476 13:44:44.847430 + cd /lava-14879038/0/tests/1_kselftest-alsa
6477 13:44:44.847597 ++ cat uuid
6478 13:44:44.850795 + UUID=14879038_1.6.2.3.5
6479 13:44:44.850986 + set +x
6480 13:44:44.857623 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14879038_1.6.2.3.5>
6481 13:44:44.858059 Received signal: <STARTRUN> 1_kselftest-alsa 14879038_1.6.2.3.5
6482 13:44:44.858263 Starting test lava.1_kselftest-alsa (14879038_1.6.2.3.5)
6483 13:44:44.858526 Skipping test definition patterns.
6484 13:44:44.860909 + cd ./automated/linux/kselftest/
6485 13:44:44.887707 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b mt8183-kukui-jacuzzi-juniper-sku16 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
6486 13:44:44.927078 INFO: install_deps skipped
6487 13:44:45.462140 --2024-07-18 13:44:44-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz
6488 13:44:45.478694 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
6489 13:44:45.610028 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
6490 13:44:45.738518 HTTP request sent, awaiting response... 200 OK
6491 13:44:45.741696 Length: 1919140 (1.8M) [application/octet-stream]
6492 13:44:45.745350 Saving to: 'kselftest_armhf.tar.gz'
6493 13:44:45.745852
6494 13:44:45.746186
6495 13:44:45.996350 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
6496 13:44:46.253992 kselftest_armhf.tar 2%[ ] 44.98K 175KB/s
6497 13:44:46.559307 kselftest_armhf.tar 11%[=> ] 214.67K 417KB/s
6498 13:44:46.694042 kselftest_armhf.tar 44%[=======> ] 831.20K 1013KB/s
6499 13:44:46.700400 kselftest_armhf.tar 100%[===================>] 1.83M 1.91MB/s in 1.0s
6500 13:44:46.700487
6501 13:44:46.869151 2024-07-18 13:44:46 (1.91 MB/s) - 'kselftest_armhf.tar.gz' saved [1919140/1919140]
6502 13:44:46.869302
6503 13:44:54.006676 skiplist:
6504 13:44:54.009762 ========================================
6505 13:44:54.012932 ========================================
6506 13:44:54.064235 alsa:mixer-test
6507 13:44:54.087932 ============== Tests to run ===============
6508 13:44:54.090841 alsa:mixer-test
6509 13:44:54.094225 ===========End Tests to run ===============
6510 13:44:54.098254 shardfile-alsa pass
6511 13:44:54.215487 <12>[ 30.164107] kselftest: Running tests in alsa
6512 13:44:54.226972 TAP version 13
6513 13:44:54.243525 1..1
6514 13:44:54.261981 # selftests: alsa: mixer-test
6515 13:44:54.365215 <6>[ 30.306895] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6516 13:44:54.378177 <6>[ 30.319232] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6517 13:44:54.391709 <6>[ 30.331486] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 1
6518 13:44:54.401871 <6>[ 30.343720] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6519 13:44:54.414688 <6>[ 30.355995] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6520 13:44:54.424863 <6>[ 30.368360] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6521 13:44:54.438229 <6>[ 30.379724] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6522 13:44:54.447958 <6>[ 30.391067] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 1
6523 13:44:54.461041 <6>[ 30.402410] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6524 13:44:54.471105 <6>[ 30.413746] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6525 13:44:54.481443 <6>[ 30.425085] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6526 13:44:54.494612 <6>[ 30.436416] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6527 13:44:54.504405 <6>[ 30.447743] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 1
6528 13:44:54.517577 <6>[ 30.459082] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6529 13:44:54.527721 <6>[ 30.470434] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6530 13:44:54.541408 <6>[ 30.481795] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6531 13:44:54.551327 <6>[ 30.493142] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6532 13:44:54.560663 <6>[ 30.504483] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 1
6533 13:44:54.574079 <6>[ 30.515827] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6534 13:44:54.583998 <6>[ 30.527182] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6535 13:44:54.597317 <6>[ 30.538556] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6536 13:44:54.607331 <6>[ 30.549916] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6537 13:44:54.620533 <6>[ 30.561279] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 1
6538 13:44:54.630552 <6>[ 30.572668] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6539 13:44:54.640562 <6>[ 30.584045] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6540 13:44:54.653796 <6>[ 30.595439] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6541 13:44:54.667595 # TAP version 13<6>[ 30.606860] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6542 13:44:54.677122 <6>[ 30.619457] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 1
6543 13:44:54.690298 <6>[ 30.630794] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6544 13:44:54.700811 <6>[ 30.642129] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6545 13:44:54.701358
6546 13:44:54.701695 # 1..658
6547 13:44:54.703715 # ok 1 get_value.0.93
6548 13:44:54.704215 # ok 2 name.0.93
6549 13:44:54.707238 # ok 3 write_default.0.93
6550 13:44:54.710282 # ok 4 write_valid.0.93
6551 13:44:54.713502 # ok 5 write_invalid.0.93
6552 13:44:54.714015 # ok 6 event_missing.0.93
6553 13:44:54.716659 # ok 7 event_spurious.0.93
6554 13:44:54.720462 # ok 8 get_value.0.92
6555 13:44:54.720970 # ok 9 name.0.92
6556 13:44:54.723451 # ok 10 write_default.0.92
6557 13:44:54.726882 # ok 11 write_valid.0.92
6558 13:44:54.727396 # ok 12 write_invalid.0.92
6559 13:44:54.730005 # ok 13 event_missing.0.92
6560 13:44:54.733707 # ok 14 event_spurious.0.92
6561 13:44:54.736755 # ok 15 get_value.0.91
6562 13:44:54.737180 # ok 16 name.0.91
6563 13:44:54.740093 # ok 17 write_default.0.91
6564 13:44:54.743404 # ok 18 write_valid.0.91
6565 13:44:54.746630 # ok 19 write_invalid.0.91
6566 13:44:54.747054 # ok 20 event_missing.0.91
6567 13:44:54.749966 # ok 21 event_spurious.0.91
6568 13:44:54.753131 # ok 22 get_value.0.90
6569 13:44:54.753585 # ok 23 name.0.90
6570 13:44:54.756537 # ok 24 write_default.0.90
6571 13:44:54.760032 # ok 25 write_valid.0.90
6572 13:44:54.763190 # ok 26 write_invalid.0.90
6573 13:44:54.763615 # ok 27 event_missing.0.90
6574 13:44:54.766775 # ok 28 event_spurious.0.90
6575 13:44:54.770032 # ok 29 get_value.0.89
6576 13:44:54.773143 # ok 30 name.0.89
6577 13:44:54.773605 # ok 31 write_default.0.89
6578 13:44:54.776581 # ok 32 write_valid.0.89
6579 13:44:54.779614 # ok 33 write_invalid.0.89
6580 13:44:54.783166 # ok 34 event_missing.0.89
6581 13:44:54.786950 # ok 35 event_spurious.0.89
6582 13:44:54.787448 # ok 36 get_value.0.88
6583 13:44:54.789941 # ok 37 name.0.88
6584 13:44:54.793350 # ok 38 write_default.0.88
6585 13:44:54.796886 # # Spurious event generated for AIF Out Mux
6586 13:44:54.800497 # # AIF Out Mux.0 expected 1 but read 0, is_volatile 0
6587 13:44:54.806893 # # Spurious event generated for AIF Out Mux
6588 13:44:54.810222 # not ok 39 write_valid.0.88
6589 13:44:54.810726 # ok 40 write_invalid.0.88
6590 13:44:54.813944 # ok 41 event_missing.0.88
6591 13:44:54.816860 # not ok 42 event_spurious.0.88
6592 13:44:54.820139 # ok 43 get_value.0.87
6593 13:44:54.820596 # ok 44 name.0.87
6594 13:44:54.823198 # ok 45 write_default.0.87
6595 13:44:54.823620 # ok 46 write_valid.0.87
6596 13:44:54.826870 # ok 47 write_invalid.0.87
6597 13:44:54.830259 # ok 48 event_missing.0.87
6598 13:44:54.833322 # ok 49 event_spurious.0.87
6599 13:44:54.833750 # ok 50 get_value.0.86
6600 13:44:54.837084 # ok 51 name.0.86
6601 13:44:54.839950 # ok 52 write_default.0.86
6602 13:44:54.843129 # # HPR Mux.0 expected 5 but read 0, is_volatile 0
6603 13:44:54.846900 # # HPR Mux.0 expected 6 but read 0, is_volatile 0
6604 13:44:54.853498 # # HPR Mux.0 expected 7 but read 0, is_volatile 0
6605 13:44:54.856764 # not ok 53 write_valid.0.86
6606 13:44:54.857357 # ok 54 write_invalid.0.86
6607 13:44:54.860022 # ok 55 event_missing.0.86
6608 13:44:54.863399 # ok 56 event_spurious.0.86
6609 13:44:54.866820 # ok 57 get_value.0.85
6610 13:44:54.867245 # ok 58 name.0.85
6611 13:44:54.870041 # ok 59 write_default.0.85
6612 13:44:54.873144 # # HPL Mux.0 expected 5 but read 0, is_volatile 0
6613 13:44:54.879940 # # HPL Mux.0 expected 6 but read 0, is_volatile 0
6614 13:44:54.883121 # # HPL Mux.0 expected 7 but read 0, is_volatile 0
6615 13:44:54.886488 # not ok 60 write_valid.0.85
6616 13:44:54.889593 # ok 61 write_invalid.0.85
6617 13:44:54.890021 # ok 62 event_missing.0.85
6618 13:44:54.893350 # ok 63 event_spurious.0.85
6619 13:44:54.896797 # ok 64 get_value.0.84
6620 13:44:54.897345 # ok 65 name.0.84
6621 13:44:54.900377 # ok 66 write_default.0.84
6622 13:44:54.903535 # ok 67 write_valid.0.84
6623 13:44:54.906544 # ok 68 write_invalid.0.84
6624 13:44:54.907054 # ok 69 event_missing.0.84
6625 13:44:54.909898 # ok 70 event_spurious.0.84
6626 13:44:54.913382 # ok 71 get_value.0.83
6627 13:44:54.913881 # ok 72 name.0.83
6628 13:44:54.916173 # ok 73 write_default.0.83
6629 13:44:54.919681 # ok 74 write_valid.0.83
6630 13:44:54.923436 # ok 75 write_invalid.0.83
6631 13:44:54.923940 # ok 76 event_missing.0.83
6632 13:44:54.926347 # ok 77 event_spurious.0.83
6633 13:44:54.929534 # ok 78 get_value.0.82
6634 13:44:54.929962 # ok 79 name.0.82
6635 13:44:54.933033 # # Headset Jack is not writeable
6636 13:44:54.936359 # ok 80 # SKIP write_default.0.82
6637 13:44:54.939205 # # Headset Jack is not writeable
6638 13:44:54.942494 # ok 81 # SKIP write_valid.0.82
6639 13:44:54.946046 # # Headset Jack is not writeable
6640 13:44:54.949435 # ok 82 # SKIP write_invalid.0.82
6641 13:44:54.953001 # ok 83 event_missing.0.82
6642 13:44:54.953172 # ok 84 event_spurious.0.82
6643 13:44:54.955998 # ok 85 get_value.0.81
6644 13:44:54.956132 # ok 86 name.0.81
6645 13:44:54.959629 # ok 87 write_default.0.81
6646 13:44:54.965944 # # No event generated for Wake-on-Voice Phase2 Switch
6647 13:44:54.969333 # # No event generated for Wake-on-Voice Phase2 Switch
6648 13:44:54.972550 # ok 88 write_valid.0.81
6649 13:44:54.979598 # # Wake-on-Voice Phase2 Switch.0 Invalid boolean value 2
6650 13:44:54.982889 # # No event generated for Wake-on-Voice Phase2 Switch
6651 13:44:54.986131 # not ok 89 write_invalid.0.81
6652 13:44:54.989683 # not ok 90 event_missing.0.81
6653 13:44:54.992835 # ok 91 event_spurious.0.81
6654 13:44:54.993068 # ok 92 get_value.0.80
6655 13:44:54.996091 # ok 93 name.0.80
6656 13:44:54.999463 # ok 94 write_default.0.80
6657 13:44:54.999753 # ok 95 write_valid.0.80
6658 13:44:55.002925 # ok 96 write_invalid.0.80
6659 13:44:55.006606 # ok 97 event_missing.0.80
6660 13:44:55.009752 # ok 98 event_spurious.0.80
6661 13:44:55.013678 # # Handset Volume.0 value -13 less than minimum 0
6662 13:44:55.015992 # not ok 99 get_value.0.79
6663 13:44:55.016535 # ok 100 name.0.79
6664 13:44:55.023265 # # snd_ctl_elem_write() failed: Invalid argument
6665 13:44:55.026532 # not ok 101 write_default.0.79
6666 13:44:55.029606 # # snd_ctl_elem_write() failed: Invalid argument
6667 13:44:55.033110 # not ok 102 write_valid.0.79
6668 13:44:55.036549 # # snd_ctl_elem_write() failed: Invalid argument
6669 13:44:55.040104 # not ok 103 write_invalid.0.79
6670 13:44:55.042956 # ok 104 event_missing.0.79
6671 13:44:55.046516 # ok 105 event_spurious.0.79
6672 13:44:55.049946 # # Lineout Volume.0 value -13 less than minimum 0
6673 13:44:55.053892 # # Lineout Volume.1 value -13 less than minimum 0
6674 13:44:55.056697 # not ok 106 get_value.0.78
6675 13:44:55.059638 # ok 107 name.0.78
6676 13:44:55.063334 # # snd_ctl_elem_write() failed: Invalid argument
6677 13:44:55.066053 # not ok 108 write_default.0.78
6678 13:44:55.069667 # # snd_ctl_elem_write() failed: Invalid argument
6679 13:44:55.072945 # not ok 109 write_valid.0.78
6680 13:44:55.076428 # # snd_ctl_elem_write() failed: Invalid argument
6681 13:44:55.079450 # not ok 110 write_invalid.0.78
6682 13:44:55.082684 # ok 111 event_missing.0.78
6683 13:44:55.086200 # ok 112 event_spurious.0.78
6684 13:44:55.089404 # # Headphone Volume.0 value -13 less than minimum 0
6685 13:44:55.095962 # # Headphone Volume.1 value -13 less than minimum 0
6686 13:44:55.096392 # not ok 113 get_value.0.77
6687 13:44:55.099482 # ok 114 name.0.77
6688 13:44:55.102807 # # snd_ctl_elem_write() failed: Invalid argument
6689 13:44:55.106621 # not ok 115 write_default.0.77
6690 13:44:55.109515 # # snd_ctl_elem_write() failed: Invalid argument
6691 13:44:55.112748 # not ok 116 write_valid.0.77
6692 13:44:55.116179 # # snd_ctl_elem_write() failed: Invalid argument
6693 13:44:55.119185 # not ok 117 write_invalid.0.77
6694 13:44:55.122919 # ok 118 event_missing.0.77
6695 13:44:55.125930 # ok 119 event_spurious.0.77
6696 13:44:55.129655 # ok 120 get_value.0.76
6697 13:44:55.136234 # # 0.76 ADDA_DL_CH2 PCM_2_CAP_CH2 is a writeable boolean but not a Switch
6698 13:44:55.136742 # not ok 121 name.0.76
6699 13:44:55.139118 # ok 122 write_default.0.76
6700 13:44:55.142492 # ok 123 write_valid.0.76
6701 13:44:55.145986 # ok 124 write_invalid.0.76
6702 13:44:55.146489 # ok 125 event_missing.0.76
6703 13:44:55.149501 # ok 126 event_spurious.0.76
6704 13:44:55.152971 # ok 127 get_value.0.75
6705 13:44:55.159394 # # 0.75 ADDA_DL_CH2 PCM_1_CAP_CH2 is a writeable boolean but not a Switch
6706 13:44:55.162546 # not ok 128 name.0.75
6707 13:44:55.163044 # ok 129 write_default.0.75
6708 13:44:55.165611 # ok 130 write_valid.0.75
6709 13:44:55.169691 # ok 131 write_invalid.0.75
6710 13:44:55.172172 # ok 132 event_missing.0.75
6711 13:44:55.172598 # ok 133 event_spurious.0.75
6712 13:44:55.176028 # ok 134 get_value.0.74
6713 13:44:55.182423 # # 0.74 ADDA_DL_CH2 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
6714 13:44:55.185905 # not ok 135 name.0.74
6715 13:44:55.189020 # ok 136 write_default.0.74
6716 13:44:55.189583 # ok 137 write_valid.0.74
6717 13:44:55.192412 # ok 138 write_invalid.0.74
6718 13:44:55.195245 # ok 139 event_missing.0.74
6719 13:44:55.199188 # ok 140 event_spurious.0.74
6720 13:44:55.199692 # ok 141 get_value.0.73
6721 13:44:55.209102 # # 0.73 ADDA_DL_CH2 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
6722 13:44:55.209650 # not ok 142 name.0.73
6723 13:44:55.212428 # ok 143 write_default.0.73
6724 13:44:55.215507 # ok 144 write_valid.0.73
6725 13:44:55.216013 # ok 145 write_invalid.0.73
6726 13:44:55.218750 # ok 146 event_missing.0.73
6727 13:44:55.221858 # ok 147 event_spurious.0.73
6728 13:44:55.225838 # ok 148 get_value.0.72
6729 13:44:55.231998 # # 0.72 ADDA_DL_CH2 ADDA_UL_CH1 is a writeable boolean but not a Switch
6730 13:44:55.232509 # not ok 149 name.0.72
6731 13:44:55.235791 # ok 150 write_default.0.72
6732 13:44:55.238406 # ok 151 write_valid.0.72
6733 13:44:55.241727 # ok 152 write_invalid.0.72
6734 13:44:55.245612 # ok 153 event_missing.0.72
6735 13:44:55.246116 # ok 154 event_spurious.0.72
6736 13:44:55.248374 # ok 155 get_value.0.71
6737 13:44:55.255184 # # 0.71 ADDA_DL_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
6738 13:44:55.258650 # not ok 156 name.0.71
6739 13:44:55.259153 # ok 157 write_default.0.71
6740 13:44:55.261750 # ok 158 write_valid.0.71
6741 13:44:55.265183 # ok 159 write_invalid.0.71
6742 13:44:55.268939 # ok 160 event_missing.0.71
6743 13:44:55.272162 # ok 161 event_spurious.0.71
6744 13:44:55.272667 # ok 162 get_value.0.70
6745 13:44:55.278741 # # 0.70 ADDA_DL_CH2 DL3_CH2 is a writeable boolean but not a Switch
6746 13:44:55.281770 # not ok 163 name.0.70
6747 13:44:55.285386 # ok 164 write_default.0.70
6748 13:44:55.285893 # ok 165 write_valid.0.70
6749 13:44:55.288613 # ok 166 write_invalid.0.70
6750 13:44:55.291981 # ok 167 event_missing.0.70
6751 13:44:55.295346 # ok 168 event_spurious.0.70
6752 13:44:55.295777 # ok 169 get_value.0.69
6753 13:44:55.301648 # # 0.69 ADDA_DL_CH2 DL3_CH1 is a writeable boolean but not a Switch
6754 13:44:55.305156 # not ok 170 name.0.69
6755 13:44:55.308478 # ok 171 write_default.0.69
6756 13:44:55.308974 # ok 172 write_valid.0.69
6757 13:44:55.312063 # ok 173 write_invalid.0.69
6758 13:44:55.315193 # ok 174 event_missing.0.69
6759 13:44:55.318318 # ok 175 event_spurious.0.69
6760 13:44:55.318753 # ok 176 get_value.0.68
6761 13:44:55.324838 # # 0.68 ADDA_DL_CH2 DL2_CH2 is a writeable boolean but not a Switch
6762 13:44:55.328143 # not ok 177 name.0.68
6763 13:44:55.331357 # ok 178 write_default.0.68
6764 13:44:55.335033 # ok 179 write_valid.0.68
6765 13:44:55.335652 # ok 180 write_invalid.0.68
6766 13:44:55.337860 # ok 181 event_missing.0.68
6767 13:44:55.341483 # ok 182 event_spurious.0.68
6768 13:44:55.344914 # ok 183 get_value.0.67
6769 13:44:55.351624 # # 0.67 ADDA_DL_CH2 DL2_CH1 is a writeable boolean but not a Switch
6770 13:44:55.352132 # not ok 184 name.0.67
6771 13:44:55.355054 # ok 185 write_default.0.67
6772 13:44:55.358015 # ok 186 write_valid.0.67
6773 13:44:55.358440 # ok 187 write_invalid.0.67
6774 13:44:55.361874 # ok 188 event_missing.0.67
6775 13:44:55.364410 # ok 189 event_spurious.0.67
6776 13:44:55.367985 # ok 190 get_value.0.66
6777 13:44:55.374746 # # 0.66 ADDA_DL_CH2 DL1_CH2 is a writeable boolean but not a Switch
6778 13:44:55.375253 # not ok 191 name.0.66
6779 13:44:55.378129 # ok 192 write_default.0.66
6780 13:44:55.380990 # ok 193 write_valid.0.66
6781 13:44:55.384369 # ok 194 write_invalid.0.66
6782 13:44:55.384795 # ok 195 event_missing.0.66
6783 13:44:55.387946 # ok 196 event_spurious.0.66
6784 13:44:55.390893 # ok 197 get_value.0.65
6785 13:44:55.397567 # # 0.65 ADDA_DL_CH2 DL1_CH1 is a writeable boolean but not a Switch
6786 13:44:55.398078 # not ok 198 name.0.65
6787 13:44:55.401448 # ok 199 write_default.0.65
6788 13:44:55.404529 # ok 200 write_valid.0.65
6789 13:44:55.407789 # ok 201 write_invalid.0.65
6790 13:44:55.408312 # ok 202 event_missing.0.65
6791 13:44:55.411206 # ok 203 event_spurious.0.65
6792 13:44:55.414229 # ok 204 get_value.0.64
6793 13:44:55.421301 # # 0.64 ADDA_DL_CH1 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
6794 13:44:55.421840 # not ok 205 name.0.64
6795 13:44:55.424482 # ok 206 write_default.0.64
6796 13:44:55.427760 # ok 207 write_valid.0.64
6797 13:44:55.430791 # ok 208 write_invalid.0.64
6798 13:44:55.431214 # ok 209 event_missing.0.64
6799 13:44:55.434173 # ok 210 event_spurious.0.64
6800 13:44:55.438189 # ok 211 get_value.0.63
6801 13:44:55.444101 # # 0.63 ADDA_DL_CH1 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
6802 13:44:55.444614 # not ok 212 name.0.63
6803 13:44:55.447084 # ok 213 write_default.0.63
6804 13:44:55.450887 # ok 214 write_valid.0.63
6805 13:44:55.453733 # ok 215 write_invalid.0.63
6806 13:44:55.454208 # ok 216 event_missing.0.63
6807 13:44:55.457322 # ok 217 event_spurious.0.63
6808 13:44:55.461207 # ok 218 get_value.0.62
6809 13:44:55.467466 # # 0.62 ADDA_DL_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
6810 13:44:55.467977 # not ok 219 name.0.62
6811 13:44:55.470598 # ok 220 write_default.0.62
6812 13:44:55.473931 # ok 221 write_valid.0.62
6813 13:44:55.477468 # ok 222 write_invalid.0.62
6814 13:44:55.477977 # ok 223 event_missing.0.62
6815 13:44:55.480868 # ok 224 event_spurious.0.62
6816 13:44:55.483714 # ok 225 get_value.0.61
6817 13:44:55.490332 # # 0.61 ADDA_DL_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
6818 13:44:55.493614 # not ok 226 name.0.61
6819 13:44:55.494106 # ok 227 write_default.0.61
6820 13:44:55.496885 # ok 228 write_valid.0.61
6821 13:44:55.500307 # ok 229 write_invalid.0.61
6822 13:44:55.504033 # ok 230 event_missing.0.61
6823 13:44:55.504542 # ok 231 event_spurious.0.61
6824 13:44:55.507088 # ok 232 get_value.0.60
6825 13:44:55.513580 # # 0.60 ADDA_DL_CH1 DL3_CH1 is a writeable boolean but not a Switch
6826 13:44:55.516633 # not ok 233 name.0.60
6827 13:44:55.517130 # ok 234 write_default.0.60
6828 13:44:55.520141 # ok 235 write_valid.0.60
6829 13:44:55.523533 # ok 236 write_invalid.0.60
6830 13:44:55.527055 # ok 237 event_missing.0.60
6831 13:44:55.530105 # ok 238 event_spurious.0.60
6832 13:44:55.530554 # ok 239 get_value.0.59
6833 13:44:55.536944 # # 0.59 ADDA_DL_CH1 DL2_CH1 is a writeable boolean but not a Switch
6834 13:44:55.540046 # not ok 240 name.0.59
6835 13:44:55.543156 # ok 241 write_default.0.59
6836 13:44:55.543583 # ok 242 write_valid.0.59
6837 13:44:55.546841 # ok 243 write_invalid.0.59
6838 13:44:55.550187 # ok 244 event_missing.0.59
6839 13:44:55.553291 # ok 245 event_spurious.0.59
6840 13:44:55.553719 # ok 246 get_value.0.58
6841 13:44:55.560049 # # 0.58 ADDA_DL_CH1 DL1_CH1 is a writeable boolean but not a Switch
6842 13:44:55.563464 # not ok 247 name.0.58
6843 13:44:55.566517 # ok 248 write_default.0.58
6844 13:44:55.569793 # ok 249 write_valid.0.58
6845 13:44:55.570236 # ok 250 write_invalid.0.58
6846 13:44:55.573461 # ok 251 event_missing.0.58
6847 13:44:55.576513 # ok 252 event_spurious.0.58
6848 13:44:55.580057 # ok 253 get_value.0.57
6849 13:44:55.583279 # # 0.57 I2S5_CH2 DL3_CH2 is a writeable boolean but not a Switch
6850 13:44:55.586487 # not ok 254 name.0.57
6851 13:44:55.589709 # ok 255 write_default.0.57
6852 13:44:55.593214 # ok 256 write_valid.0.57
6853 13:44:55.593803 # ok 257 write_invalid.0.57
6854 13:44:55.596506 # ok 258 event_missing.0.57
6855 13:44:55.599945 # ok 259 event_spurious.0.57
6856 13:44:55.603453 # ok 260 get_value.0.56
6857 13:44:55.606493 # # 0.56 I2S5_CH2 DL2_CH2 is a writeable boolean but not a Switch
6858 13:44:55.609502 # not ok 261 name.0.56
6859 13:44:55.613465 # ok 262 write_default.0.56
6860 13:44:55.616656 # ok 263 write_valid.0.56
6861 13:44:55.617106 # ok 264 write_invalid.0.56
6862 13:44:55.619780 # ok 265 event_missing.0.56
6863 13:44:55.622897 # ok 266 event_spurious.0.56
6864 13:44:55.626094 # ok 267 get_value.0.55
6865 13:44:55.633067 # # 0.55 I2S5_CH2 DL1_CH2 is a writeable boolean but not a Switch
6866 13:44:55.633597 # not ok 268 name.0.55
6867 13:44:55.636371 # ok 269 write_default.0.55
6868 13:44:55.639571 # ok 270 write_valid.0.55
6869 13:44:55.639997 # ok 271 write_invalid.0.55
6870 13:44:55.643085 # ok 272 event_missing.0.55
6871 13:44:55.646310 # ok 273 event_spurious.0.55
6872 13:44:55.649547 # ok 274 get_value.0.54
6873 13:44:55.656388 # # 0.54 I2S5_CH1 DL3_CH1 is a writeable boolean but not a Switch
6874 13:44:55.656816 # not ok 275 name.0.54
6875 13:44:55.659701 # ok 276 write_default.0.54
6876 13:44:55.663368 # ok 277 write_valid.0.54
6877 13:44:55.666332 # ok 278 write_invalid.0.54
6878 13:44:55.666782 # ok 279 event_missing.0.54
6879 13:44:55.669905 # ok 280 event_spurious.0.54
6880 13:44:55.673023 # ok 281 get_value.0.53
6881 13:44:55.679673 # # 0.53 I2S5_CH1 DL2_CH1 is a writeable boolean but not a Switch
6882 13:44:55.680203 # not ok 282 name.0.53
6883 13:44:55.682883 # ok 283 write_default.0.53
6884 13:44:55.685996 # ok 284 write_valid.0.53
6885 13:44:55.689395 # ok 285 write_invalid.0.53
6886 13:44:55.689823 # ok 286 event_missing.0.53
6887 13:44:55.692648 # ok 287 event_spurious.0.53
6888 13:44:55.696325 # ok 288 get_value.0.52
6889 13:44:55.703141 # # 0.52 I2S5_CH1 DL1_CH1 is a writeable boolean but not a Switch
6890 13:44:55.703680 # not ok 289 name.0.52
6891 13:44:55.706197 # ok 290 write_default.0.52
6892 13:44:55.709719 # ok 291 write_valid.0.52
6893 13:44:55.713039 # ok 292 write_invalid.0.52
6894 13:44:55.713584 # ok 293 event_missing.0.52
6895 13:44:55.716203 # ok 294 event_spurious.0.52
6896 13:44:55.719155 # ok 295 get_value.0.51
6897 13:44:55.725988 # # 0.51 I2S3_CH2 DL3_CH2 is a writeable boolean but not a Switch
6898 13:44:55.726418 # not ok 296 name.0.51
6899 13:44:55.729329 # ok 297 write_default.0.51
6900 13:44:55.732676 # ok 298 write_valid.0.51
6901 13:44:55.736237 # ok 299 write_invalid.0.51
6902 13:44:55.736756 # ok 300 event_missing.0.51
6903 13:44:55.739740 # ok 301 event_spurious.0.51
6904 13:44:55.742323 # ok 302 get_value.0.50
6905 13:44:55.749442 # # 0.50 I2S3_CH2 DL2_CH2 is a writeable boolean but not a Switch
6906 13:44:55.750086 # not ok 303 name.0.50
6907 13:44:55.752636 # ok 304 write_default.0.50
6908 13:44:55.755915 # ok 305 write_valid.0.50
6909 13:44:55.760012 # ok 306 write_invalid.0.50
6910 13:44:55.760520 # ok 307 event_missing.0.50
6911 13:44:55.763434 # ok 308 event_spurious.0.50
6912 13:44:55.765890 # ok 309 get_value.0.49
6913 13:44:55.772812 # # 0.49 I2S3_CH2 DL1_CH2 is a writeable boolean but not a Switch
6914 13:44:55.773385 # not ok 310 name.0.49
6915 13:44:55.776297 # ok 311 write_default.0.49
6916 13:44:55.779109 # ok 312 write_valid.0.49
6917 13:44:55.782499 # ok 313 write_invalid.0.49
6918 13:44:55.782925 # ok 314 event_missing.0.49
6919 13:44:55.785780 # ok 315 event_spurious.0.49
6920 13:44:55.789366 # ok 316 get_value.0.48
6921 13:44:55.796018 # # 0.48 I2S3_CH1 DL3_CH1 is a writeable boolean but not a Switch
6922 13:44:55.796528 # not ok 317 name.0.48
6923 13:44:55.799063 # ok 318 write_default.0.48
6924 13:44:55.802632 # ok 319 write_valid.0.48
6925 13:44:55.805934 # ok 320 write_invalid.0.48
6926 13:44:55.806437 # ok 321 event_missing.0.48
6927 13:44:55.809074 # ok 322 event_spurious.0.48
6928 13:44:55.812862 # ok 323 get_value.0.47
6929 13:44:55.819316 # # 0.47 I2S3_CH1 DL2_CH1 is a writeable boolean but not a Switch
6930 13:44:55.819855 # not ok 324 name.0.47
6931 13:44:55.822684 # ok 325 write_default.0.47
6932 13:44:55.825953 # ok 326 write_valid.0.47
6933 13:44:55.829298 # ok 327 write_invalid.0.47
6934 13:44:55.829819 # ok 328 event_missing.0.47
6935 13:44:55.832471 # ok 329 event_spurious.0.47
6936 13:44:55.835706 # ok 330 get_value.0.46
6937 13:44:55.842620 # # 0.46 I2S3_CH1 DL1_CH1 is a writeable boolean but not a Switch
6938 13:44:55.843144 # not ok 331 name.0.46
6939 13:44:55.845769 # ok 332 write_default.0.46
6940 13:44:55.848817 # ok 333 write_valid.0.46
6941 13:44:55.852216 # ok 334 write_invalid.0.46
6942 13:44:55.855595 # ok 335 event_missing.0.46
6943 13:44:55.856018 # ok 336 event_spurious.0.46
6944 13:44:55.859320 # ok 337 get_value.0.45
6945 13:44:55.865849 # # 0.45 I2S1_CH2 DL3_CH2 is a writeable boolean but not a Switch
6946 13:44:55.866344 # not ok 338 name.0.45
6947 13:44:55.868691 # ok 339 write_default.0.45
6948 13:44:55.872050 # ok 340 write_valid.0.45
6949 13:44:55.875514 # ok 341 write_invalid.0.45
6950 13:44:55.879349 # ok 342 event_missing.0.45
6951 13:44:55.879850 # ok 343 event_spurious.0.45
6952 13:44:55.882318 # ok 344 get_value.0.44
6953 13:44:55.889466 # # 0.44 I2S1_CH2 DL2_CH2 is a writeable boolean but not a Switch
6954 13:44:55.892071 # not ok 345 name.0.44
6955 13:44:55.892496 # ok 346 write_default.0.44
6956 13:44:55.895659 # ok 347 write_valid.0.44
6957 13:44:55.898936 # ok 348 write_invalid.0.44
6958 13:44:55.902026 # ok 349 event_missing.0.44
6959 13:44:55.902453 # ok 350 event_spurious.0.44
6960 13:44:55.905751 # ok 351 get_value.0.43
6961 13:44:55.912160 # # 0.43 I2S1_CH2 DL1_CH2 is a writeable boolean but not a Switch
6962 13:44:55.912663 # not ok 352 name.0.43
6963 13:44:55.915398 # ok 353 write_default.0.43
6964 13:44:55.918873 # ok 354 write_valid.0.43
6965 13:44:55.922110 # ok 355 write_invalid.0.43
6966 13:44:55.922537 # ok 356 event_missing.0.43
6967 13:44:55.925418 # ok 357 event_spurious.0.43
6968 13:44:55.929302 # ok 358 get_value.0.42
6969 13:44:55.935791 # # 0.42 I2S1_CH1 DL3_CH1 is a writeable boolean but not a Switch
6970 13:44:55.936306 # not ok 359 name.0.42
6971 13:44:55.939237 # ok 360 write_default.0.42
6972 13:44:55.942352 # ok 361 write_valid.0.42
6973 13:44:55.942788 # ok 362 write_invalid.0.42
6974 13:44:55.945726 # ok 363 event_missing.0.42
6975 13:44:55.949281 # ok 364 event_spurious.0.42
6976 13:44:55.952413 # ok 365 get_value.0.41
6977 13:44:55.955543 # # 0.41 I2S1_CH1 DL2_CH1 is a writeable boolean but not a Switch
6978 13:44:55.958770 # not ok 366 name.0.41
6979 13:44:55.962261 # ok 367 write_default.0.41
6980 13:44:55.965691 # ok 368 write_valid.0.41
6981 13:44:55.966124 # ok 369 write_invalid.0.41
6982 13:44:55.968665 # ok 370 event_missing.0.41
6983 13:44:55.972400 # ok 371 event_spurious.0.41
6984 13:44:55.975680 # ok 372 get_value.0.40
6985 13:44:55.978875 # # 0.40 I2S1_CH1 DL1_CH1 is a writeable boolean but not a Switch
6986 13:44:55.981955 # not ok 373 name.0.40
6987 13:44:55.985635 # ok 374 write_default.0.40
6988 13:44:55.988802 # ok 375 write_valid.0.40
6989 13:44:55.989362 # ok 376 write_invalid.0.40
6990 13:44:55.992456 # ok 377 event_missing.0.40
6991 13:44:55.995214 # ok 378 event_spurious.0.40
6992 13:44:55.999221 # ok 379 get_value.0.39
6993 13:44:56.005602 # # 0.39 PCM_2_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
6994 13:44:56.006168 # not ok 380 name.0.39
6995 13:44:56.008540 # ok 381 write_default.0.39
6996 13:44:56.012130 # ok 382 write_valid.0.39
6997 13:44:56.015191 # ok 383 write_invalid.0.39
6998 13:44:56.015619 # ok 384 event_missing.0.39
6999 13:44:56.018844 # ok 385 event_spurious.0.39
7000 13:44:56.021613 # ok 386 get_value.0.38
7001 13:44:56.028649 # # 0.38 PCM_2_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
7002 13:44:56.029172 # not ok 387 name.0.38
7003 13:44:56.032365 # ok 388 write_default.0.38
7004 13:44:56.035412 # ok 389 write_valid.0.38
7005 13:44:56.038659 # ok 390 write_invalid.0.38
7006 13:44:56.039166 # ok 391 event_missing.0.38
7007 13:44:56.042126 # ok 392 event_spurious.0.38
7008 13:44:56.045345 # ok 393 get_value.0.37
7009 13:44:56.052054 # # 0.37 PCM_2_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7010 13:44:56.055108 # not ok 394 name.0.37
7011 13:44:56.055556 # ok 395 write_default.0.37
7012 13:44:56.058786 # ok 396 write_valid.0.37
7013 13:44:56.061983 # ok 397 write_invalid.0.37
7014 13:44:56.065408 # ok 398 event_missing.0.37
7015 13:44:56.065913 # ok 399 event_spurious.0.37
7016 13:44:56.069168 # ok 400 get_value.0.36
7017 13:44:56.075558 # # 0.36 PCM_2_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7018 13:44:56.078806 # not ok 401 name.0.36
7019 13:44:56.079309 # ok 402 write_default.0.36
7020 13:44:56.081632 # ok 403 write_valid.0.36
7021 13:44:56.084994 # ok 404 write_invalid.0.36
7022 13:44:56.088742 # ok 405 event_missing.0.36
7023 13:44:56.089289 # ok 406 event_spurious.0.36
7024 13:44:56.091830 # ok 407 get_value.0.35
7025 13:44:56.098544 # # 0.35 PCM_2_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7026 13:44:56.101875 # not ok 408 name.0.35
7027 13:44:56.102385 # ok 409 write_default.0.35
7028 13:44:56.105202 # ok 410 write_valid.0.35
7029 13:44:56.108346 # ok 411 write_invalid.0.35
7030 13:44:56.112182 # ok 412 event_missing.0.35
7031 13:44:56.112684 # ok 413 event_spurious.0.35
7032 13:44:56.114926 # ok 414 get_value.0.34
7033 13:44:56.121505 # # 0.34 PCM_1_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
7034 13:44:56.121987 # not ok 415 name.0.34
7035 13:44:56.124748 # ok 416 write_default.0.34
7036 13:44:56.128509 # ok 417 write_valid.0.34
7037 13:44:56.131791 # ok 418 write_invalid.0.34
7038 13:44:56.132298 # ok 419 event_missing.0.34
7039 13:44:56.134784 # ok 420 event_spurious.0.34
7040 13:44:56.138167 # ok 421 get_value.0.33
7041 13:44:56.144745 # # 0.33 PCM_1_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
7042 13:44:56.145177 # not ok 422 name.0.33
7043 13:44:56.148396 # ok 423 write_default.0.33
7044 13:44:56.151645 # ok 424 write_valid.0.33
7045 13:44:56.154592 # ok 425 write_invalid.0.33
7046 13:44:56.155021 # ok 426 event_missing.0.33
7047 13:44:56.158083 # ok 427 event_spurious.0.33
7048 13:44:56.161916 # ok 428 get_value.0.32
7049 13:44:56.168317 # # 0.32 PCM_1_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7050 13:44:56.171704 # not ok 429 name.0.32
7051 13:44:56.172208 # ok 430 write_default.0.32
7052 13:44:56.175519 # ok 431 write_valid.0.32
7053 13:44:56.178447 # ok 432 write_invalid.0.32
7054 13:44:56.181484 # ok 433 event_missing.0.32
7055 13:44:56.181994 # ok 434 event_spurious.0.32
7056 13:44:56.184621 # ok 435 get_value.0.31
7057 13:44:56.191124 # # 0.31 PCM_1_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7058 13:44:56.194339 # not ok 436 name.0.31
7059 13:44:56.197914 # ok 437 write_default.0.31
7060 13:44:56.198426 # ok 438 write_valid.0.31
7061 13:44:56.201450 # ok 439 write_invalid.0.31
7062 13:44:56.204912 # ok 440 event_missing.0.31
7063 13:44:56.207929 # ok 441 event_spurious.0.31
7064 13:44:56.208433 # ok 442 get_value.0.30
7065 13:44:56.214222 # # 0.30 PCM_1_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7066 13:44:56.217450 # not ok 443 name.0.30
7067 13:44:56.220908 # ok 444 write_default.0.30
7068 13:44:56.224072 # ok 445 write_valid.0.30
7069 13:44:56.224509 # ok 446 write_invalid.0.30
7070 13:44:56.227908 # ok 447 event_missing.0.30
7071 13:44:56.230654 # ok 448 event_spurious.0.30
7072 13:44:56.234202 # ok 449 get_value.0.29
7073 13:44:56.234713 # ok 450 name.0.29
7074 13:44:56.237653 # ok 451 write_default.0.29
7075 13:44:56.241162 # ok 452 write_valid.0.29
7076 13:44:56.241709 # ok 453 write_invalid.0.29
7077 13:44:56.244889 # ok 454 event_missing.0.29
7078 13:44:56.247435 # ok 455 event_spurious.0.29
7079 13:44:56.251609 # ok 456 get_value.0.28
7080 13:44:56.252117 # ok 457 name.0.28
7081 13:44:56.254200 # ok 458 write_default.0.28
7082 13:44:56.257846 # ok 459 write_valid.0.28
7083 13:44:56.260958 # ok 460 write_invalid.0.28
7084 13:44:56.261577 # ok 461 event_missing.0.28
7085 13:44:56.264709 # ok 462 event_spurious.0.28
7086 13:44:56.267729 # ok 463 get_value.0.27
7087 13:44:56.268242 # ok 464 name.0.27
7088 13:44:56.270675 # ok 465 write_default.0.27
7089 13:44:56.273813 # ok 466 write_valid.0.27
7090 13:44:56.277999 # ok 467 write_invalid.0.27
7091 13:44:56.278509 # ok 468 event_missing.0.27
7092 13:44:56.280705 # ok 469 event_spurious.0.27
7093 13:44:56.284130 # ok 470 get_value.0.26
7094 13:44:56.287485 # ok 471 name.0.26
7095 13:44:56.287994 # ok 472 write_default.0.26
7096 13:44:56.290594 # ok 473 write_valid.0.26
7097 13:44:56.293941 # ok 474 write_invalid.0.26
7098 13:44:56.297356 # ok 475 event_missing.0.26
7099 13:44:56.297784 # ok 476 event_spurious.0.26
7100 13:44:56.300575 # ok 477 get_value.0.25
7101 13:44:56.303799 # ok 478 name.0.25
7102 13:44:56.304225 # ok 479 write_default.0.25
7103 13:44:56.307638 # ok 480 write_valid.0.25
7104 13:44:56.310482 # ok 481 write_invalid.0.25
7105 13:44:56.314138 # ok 482 event_missing.0.25
7106 13:44:56.317475 # ok 483 event_spurious.0.25
7107 13:44:56.317980 # ok 484 get_value.0.24
7108 13:44:56.320305 # ok 485 name.0.24
7109 13:44:56.320732 # ok 486 write_default.0.24
7110 13:44:56.323642 # ok 487 write_valid.0.24
7111 13:44:56.327147 # ok 488 write_invalid.0.24
7112 13:44:56.330795 # ok 489 event_missing.0.24
7113 13:44:56.331300 # ok 490 event_spurious.0.24
7114 13:44:56.333926 # ok 491 get_value.0.23
7115 13:44:56.337172 # ok 492 name.0.23
7116 13:44:56.337726 # ok 493 write_default.0.23
7117 13:44:56.340334 # ok 494 write_valid.0.23
7118 13:44:56.343809 # ok 495 write_invalid.0.23
7119 13:44:56.347472 # ok 496 event_missing.0.23
7120 13:44:56.347980 # ok 497 event_spurious.0.23
7121 13:44:56.350418 # ok 498 get_value.0.22
7122 13:44:56.354231 # ok 499 name.0.22
7123 13:44:56.354735 # ok 500 write_default.0.22
7124 13:44:56.357102 # ok 501 write_valid.0.22
7125 13:44:56.360549 # ok 502 write_invalid.0.22
7126 13:44:56.363773 # ok 503 event_missing.0.22
7127 13:44:56.367346 # ok 504 event_spurious.0.22
7128 13:44:56.367859 # ok 505 get_value.0.21
7129 13:44:56.374006 # # 0.21 UL_MONO_1_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
7130 13:44:56.377151 # not ok 506 name.0.21
7131 13:44:56.380536 # ok 507 write_default.0.21
7132 13:44:56.383915 # ok 508 write_valid.0.21
7133 13:44:56.384493 # ok 509 write_invalid.0.21
7134 13:44:56.387827 # ok 510 event_missing.0.21
7135 13:44:56.390344 # ok 511 event_spurious.0.21
7136 13:44:56.393299 # ok 512 get_value.0.20
7137 13:44:56.400221 # # 0.20 UL_MONO_1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7138 13:44:56.400364 # not ok 513 name.0.20
7139 13:44:56.403403 # ok 514 write_default.0.20
7140 13:44:56.406688 # ok 515 write_valid.0.20
7141 13:44:56.410380 # ok 516 write_invalid.0.20
7142 13:44:56.410543 # ok 517 event_missing.0.20
7143 13:44:56.413723 # ok 518 event_spurious.0.20
7144 13:44:56.417425 # ok 519 get_value.0.19
7145 13:44:56.423295 # # 0.19 UL4_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7146 13:44:56.423513 # not ok 520 name.0.19
7147 13:44:56.427135 # ok 521 write_default.0.19
7148 13:44:56.430130 # ok 522 write_valid.0.19
7149 13:44:56.433185 # ok 523 write_invalid.0.19
7150 13:44:56.436598 # ok 524 event_missing.0.19
7151 13:44:56.436799 # ok 525 event_spurious.0.19
7152 13:44:56.439852 # ok 526 get_value.0.18
7153 13:44:56.446642 # # 0.18 UL4_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7154 13:44:56.449822 # not ok 527 name.0.18
7155 13:44:56.450056 # ok 528 write_default.0.18
7156 13:44:56.453264 # ok 529 write_valid.0.18
7157 13:44:56.456693 # ok 530 write_invalid.0.18
7158 13:44:56.460253 # ok 531 event_missing.0.18
7159 13:44:56.460642 # ok 532 event_spurious.0.18
7160 13:44:56.463388 # ok 533 get_value.0.17
7161 13:44:56.469972 # # 0.17 UL3_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7162 13:44:56.473660 # not ok 534 name.0.17
7163 13:44:56.474255 # ok 535 write_default.0.17
7164 13:44:56.477059 # ok 536 write_valid.0.17
7165 13:44:56.480046 # ok 537 write_invalid.0.17
7166 13:44:56.483110 # ok 538 event_missing.0.17
7167 13:44:56.486419 # ok 539 event_spurious.0.17
7168 13:44:56.486948 # ok 540 get_value.0.16
7169 13:44:56.493339 # # 0.16 UL3_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7170 13:44:56.496414 # not ok 541 name.0.16
7171 13:44:56.499726 # ok 542 write_default.0.16
7172 13:44:56.500235 # ok 543 write_valid.0.16
7173 13:44:56.503656 # ok 544 write_invalid.0.16
7174 13:44:56.506286 # ok 545 event_missing.0.16
7175 13:44:56.509959 # ok 546 event_spurious.0.16
7176 13:44:56.510467 # ok 547 get_value.0.15
7177 13:44:56.516340 # # 0.15 UL3_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7178 13:44:56.519476 # not ok 548 name.0.15
7179 13:44:56.522759 # ok 549 write_default.0.15
7180 13:44:56.523256 # ok 550 write_valid.0.15
7181 13:44:56.526733 # ok 551 write_invalid.0.15
7182 13:44:56.529870 # ok 552 event_missing.0.15
7183 13:44:56.533370 # ok 553 event_spurious.0.15
7184 13:44:56.533878 # ok 554 get_value.0.14
7185 13:44:56.539608 # # 0.14 UL3_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7186 13:44:56.543093 # not ok 555 name.0.14
7187 13:44:56.546100 # ok 556 write_default.0.14
7188 13:44:56.546527 # ok 557 write_valid.0.14
7189 13:44:56.550079 # ok 558 write_invalid.0.14
7190 13:44:56.553122 # ok 559 event_missing.0.14
7191 13:44:56.556115 # ok 560 event_spurious.0.14
7192 13:44:56.559538 # ok 561 get_value.0.13
7193 13:44:56.562598 # # 0.13 UL2_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7194 13:44:56.565981 # not ok 562 name.0.13
7195 13:44:56.569276 # ok 563 write_default.0.13
7196 13:44:56.573267 # ok 564 write_valid.0.13
7197 13:44:56.573784 # ok 565 write_invalid.0.13
7198 13:44:56.576378 # ok 566 event_missing.0.13
7199 13:44:56.579777 # ok 567 event_spurious.0.13
7200 13:44:56.582550 # ok 568 get_value.0.12
7201 13:44:56.586053 # # 0.12 UL2_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7202 13:44:56.589422 # not ok 569 name.0.12
7203 13:44:56.592824 # ok 570 write_default.0.12
7204 13:44:56.595852 # ok 571 write_valid.0.12
7205 13:44:56.596300 # ok 572 write_invalid.0.12
7206 13:44:56.599197 # ok 573 event_missing.0.12
7207 13:44:56.602586 # ok 574 event_spurious.0.12
7208 13:44:56.605752 # ok 575 get_value.0.11
7209 13:44:56.609349 # # 0.11 UL2_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7210 13:44:56.612352 # not ok 576 name.0.11
7211 13:44:56.615974 # ok 577 write_default.0.11
7212 13:44:56.619287 # ok 578 write_valid.0.11
7213 13:44:56.619713 # ok 579 write_invalid.0.11
7214 13:44:56.622341 # ok 580 event_missing.0.11
7215 13:44:56.625691 # ok 581 event_spurious.0.11
7216 13:44:56.629023 # ok 582 get_value.0.10
7217 13:44:56.635709 # # 0.10 UL2_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7218 13:44:56.636275 # not ok 583 name.0.10
7219 13:44:56.639241 # ok 584 write_default.0.10
7220 13:44:56.642333 # ok 585 write_valid.0.10
7221 13:44:56.645515 # ok 586 write_invalid.0.10
7222 13:44:56.645946 # ok 587 event_missing.0.10
7223 13:44:56.648700 # ok 588 event_spurious.0.10
7224 13:44:56.652132 # ok 589 get_value.0.9
7225 13:44:56.659165 # # 0.9 UL1_CH2 I2S0_CH2 is a writeable boolean but not a Switch
7226 13:44:56.659673 # not ok 590 name.0.9
7227 13:44:56.662293 # ok 591 write_default.0.9
7228 13:44:56.665562 # ok 592 write_valid.0.9
7229 13:44:56.668546 # ok 593 write_invalid.0.9
7230 13:44:56.669047 # ok 594 event_missing.0.9
7231 13:44:56.672047 # ok 595 event_spurious.0.9
7232 13:44:56.675041 # ok 596 get_value.0.8
7233 13:44:56.682164 # # 0.8 UL1_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7234 13:44:56.682598 # not ok 597 name.0.8
7235 13:44:56.685301 # ok 598 write_default.0.8
7236 13:44:56.688403 # ok 599 write_valid.0.8
7237 13:44:56.688832 # ok 600 write_invalid.0.8
7238 13:44:56.691823 # ok 601 event_missing.0.8
7239 13:44:56.695228 # ok 602 event_spurious.0.8
7240 13:44:56.698551 # ok 603 get_value.0.7
7241 13:44:56.701552 # # 0.7 UL1_CH1 I2S0_CH1 is a writeable boolean but not a Switch
7242 13:44:56.705583 # not ok 604 name.0.7
7243 13:44:56.708871 # ok 605 write_default.0.7
7244 13:44:56.712060 # ok 606 write_valid.0.7
7245 13:44:56.712493 # ok 607 write_invalid.0.7
7246 13:44:56.715212 # ok 608 event_missing.0.7
7247 13:44:56.718080 # ok 609 event_spurious.0.7
7248 13:44:56.721376 # ok 610 get_value.0.6
7249 13:44:56.725125 # # 0.6 UL1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7250 13:44:56.728042 # not ok 611 name.0.6
7251 13:44:56.731589 # ok 612 write_default.0.6
7252 13:44:56.732020 # ok 613 write_valid.0.6
7253 13:44:56.734889 # ok 614 write_invalid.0.6
7254 13:44:56.738314 # ok 615 event_missing.0.6
7255 13:44:56.741606 # ok 616 event_spurious.0.6
7256 13:44:56.742072 # ok 617 get_value.0.5
7257 13:44:56.744953 # ok 618 name.0.5
7258 13:44:56.748302 # ok 619 write_default.0.5
7259 13:44:56.751573 # # No event generated for MTKAIF_DMIC
7260 13:44:56.754663 # # No event generated for MTKAIF_DMIC
7261 13:44:56.758040 # ok 620 write_valid.0.5
7262 13:44:56.758473 # ok 621 write_invalid.0.5
7263 13:44:56.761473 # not ok 622 event_missing.0.5
7264 13:44:56.765281 # ok 623 event_spurious.0.5
7265 13:44:56.768339 # ok 624 get_value.0.4
7266 13:44:56.768771 # ok 625 name.0.4
7267 13:44:56.771577 # ok 626 write_default.0.4
7268 13:44:56.774481 # # No event generated for I2S5_HD_Mux
7269 13:44:56.778221 # # No event generated for I2S5_HD_Mux
7270 13:44:56.781181 # ok 627 write_valid.0.4
7271 13:44:56.781649 # ok 628 write_invalid.0.4
7272 13:44:56.784694 # not ok 629 event_missing.0.4
7273 13:44:56.787928 # ok 630 event_spurious.0.4
7274 13:44:56.791016 # ok 631 get_value.0.3
7275 13:44:56.791407 # ok 632 name.0.3
7276 13:44:56.794594 # ok 633 write_default.0.3
7277 13:44:56.797762 # # No event generated for I2S3_HD_Mux
7278 13:44:56.801416 # # No event generated for I2S3_HD_Mux
7279 13:44:56.804402 # ok 634 write_valid.0.3
7280 13:44:56.804789 # ok 635 write_invalid.0.3
7281 13:44:56.807674 # not ok 636 event_missing.0.3
7282 13:44:56.811035 # ok 637 event_spurious.0.3
7283 13:44:56.814641 # ok 638 get_value.0.2
7284 13:44:56.815030 # ok 639 name.0.2
7285 13:44:56.817847 # ok 640 write_default.0.2
7286 13:44:56.820932 # # No event generated for I2S2_HD_Mux
7287 13:44:56.824290 # # No event generated for I2S2_HD_Mux
7288 13:44:56.827670 # ok 641 write_valid.0.2
7289 13:44:56.828060 # ok 642 write_invalid.0.2
7290 13:44:56.831104 # not ok 643 event_missing.0.2
7291 13:44:56.834308 # ok 644 event_spurious.0.2
7292 13:44:56.834697 # ok 645 get_value.0.1
7293 13:44:56.837187 # ok 646 name.0.1
7294 13:44:56.840807 # ok 647 write_default.0.1
7295 13:44:56.844142 # # No event generated for I2S1_HD_Mux
7296 13:44:56.847338 # # No event generated for I2S1_HD_Mux
7297 13:44:56.847727 # ok 648 write_valid.0.1
7298 13:44:56.850857 # ok 649 write_invalid.0.1
7299 13:44:56.854285 # not ok 650 event_missing.0.1
7300 13:44:56.857727 # ok 651 event_spurious.0.1
7301 13:44:56.858113 # ok 652 get_value.0.0
7302 13:44:56.860804 # ok 653 name.0.0
7303 13:44:56.864275 # ok 654 write_default.0.0
7304 13:44:56.867767 # # No event generated for I2S0_HD_Mux
7305 13:44:56.871387 # # No event generated for I2S0_HD_Mux
7306 13:44:56.871778 # ok 655 write_valid.0.0
7307 13:44:56.874554 # ok 656 write_invalid.0.0
7308 13:44:56.877764 # not ok 657 event_missing.0.0
7309 13:44:56.881126 # ok 658 event_spurious.0.0
7310 13:44:56.884104 # # Totals: pass:568 fail:87 xfail:0 xpass:0 skip:3 error:0
7311 13:44:56.887417 ok 1 selftests: alsa: mixer-test
7312 13:44:58.732420 alsa_mixer-test_get_value_0_93 pass
7313 13:44:58.735401 alsa_mixer-test_name_0_93 pass
7314 13:44:58.738744 alsa_mixer-test_write_default_0_93 pass
7315 13:44:58.741949 alsa_mixer-test_write_valid_0_93 pass
7316 13:44:58.745517 alsa_mixer-test_write_invalid_0_93 pass
7317 13:44:58.752007 alsa_mixer-test_event_missing_0_93 pass
7318 13:44:58.755380 alsa_mixer-test_event_spurious_0_93 pass
7319 13:44:58.758572 alsa_mixer-test_get_value_0_92 pass
7320 13:44:58.758648 alsa_mixer-test_name_0_92 pass
7321 13:44:58.765431 alsa_mixer-test_write_default_0_92 pass
7322 13:44:58.768849 alsa_mixer-test_write_valid_0_92 pass
7323 13:44:58.771898 alsa_mixer-test_write_invalid_0_92 pass
7324 13:44:58.775615 alsa_mixer-test_event_missing_0_92 pass
7325 13:44:58.778420 alsa_mixer-test_event_spurious_0_92 pass
7326 13:44:58.782617 alsa_mixer-test_get_value_0_91 pass
7327 13:44:58.785271 alsa_mixer-test_name_0_91 pass
7328 13:44:58.788537 alsa_mixer-test_write_default_0_91 pass
7329 13:44:58.792000 alsa_mixer-test_write_valid_0_91 pass
7330 13:44:58.795439 alsa_mixer-test_write_invalid_0_91 pass
7331 13:44:58.798426 alsa_mixer-test_event_missing_0_91 pass
7332 13:44:58.801960 alsa_mixer-test_event_spurious_0_91 pass
7333 13:44:58.805451 alsa_mixer-test_get_value_0_90 pass
7334 13:44:58.808958 alsa_mixer-test_name_0_90 pass
7335 13:44:58.812050 alsa_mixer-test_write_default_0_90 pass
7336 13:44:58.815014 alsa_mixer-test_write_valid_0_90 pass
7337 13:44:58.818812 alsa_mixer-test_write_invalid_0_90 pass
7338 13:44:58.821862 alsa_mixer-test_event_missing_0_90 pass
7339 13:44:58.828601 alsa_mixer-test_event_spurious_0_90 pass
7340 13:44:58.831596 alsa_mixer-test_get_value_0_89 pass
7341 13:44:58.831672 alsa_mixer-test_name_0_89 pass
7342 13:44:58.838350 alsa_mixer-test_write_default_0_89 pass
7343 13:44:58.841716 alsa_mixer-test_write_valid_0_89 pass
7344 13:44:58.845006 alsa_mixer-test_write_invalid_0_89 pass
7345 13:44:58.848633 alsa_mixer-test_event_missing_0_89 pass
7346 13:44:58.851823 alsa_mixer-test_event_spurious_0_89 pass
7347 13:44:58.855141 alsa_mixer-test_get_value_0_88 pass
7348 13:44:58.858378 alsa_mixer-test_name_0_88 pass
7349 13:44:58.861843 alsa_mixer-test_write_default_0_88 pass
7350 13:44:58.865349 alsa_mixer-test_write_valid_0_88 fail
7351 13:44:58.868616 alsa_mixer-test_write_invalid_0_88 pass
7352 13:44:58.875131 alsa_mixer-test_event_missing_0_88 pass
7353 13:44:58.878487 alsa_mixer-test_event_spurious_0_88 fail
7354 13:44:58.881825 alsa_mixer-test_get_value_0_87 pass
7355 13:44:58.885160 alsa_mixer-test_name_0_87 pass
7356 13:44:58.888491 alsa_mixer-test_write_default_0_87 pass
7357 13:44:58.891988 alsa_mixer-test_write_valid_0_87 pass
7358 13:44:58.895059 alsa_mixer-test_write_invalid_0_87 pass
7359 13:44:58.898273 alsa_mixer-test_event_missing_0_87 pass
7360 13:44:58.905376 alsa_mixer-test_event_spurious_0_87 pass
7361 13:44:58.908431 alsa_mixer-test_get_value_0_86 pass
7362 13:44:58.908506 alsa_mixer-test_name_0_86 pass
7363 13:44:58.915009 alsa_mixer-test_write_default_0_86 pass
7364 13:44:58.918474 alsa_mixer-test_write_valid_0_86 fail
7365 13:44:58.921646 alsa_mixer-test_write_invalid_0_86 pass
7366 13:44:58.925075 alsa_mixer-test_event_missing_0_86 pass
7367 13:44:58.928233 alsa_mixer-test_event_spurious_0_86 pass
7368 13:44:58.931599 alsa_mixer-test_get_value_0_85 pass
7369 13:44:58.934903 alsa_mixer-test_name_0_85 pass
7370 13:44:58.938516 alsa_mixer-test_write_default_0_85 pass
7371 13:44:58.941976 alsa_mixer-test_write_valid_0_85 fail
7372 13:44:58.945300 alsa_mixer-test_write_invalid_0_85 pass
7373 13:44:58.948949 alsa_mixer-test_event_missing_0_85 pass
7374 13:44:58.951587 alsa_mixer-test_event_spurious_0_85 pass
7375 13:44:58.954898 alsa_mixer-test_get_value_0_84 pass
7376 13:44:58.958483 alsa_mixer-test_name_0_84 pass
7377 13:44:58.961483 alsa_mixer-test_write_default_0_84 pass
7378 13:44:58.965149 alsa_mixer-test_write_valid_0_84 pass
7379 13:44:58.968182 alsa_mixer-test_write_invalid_0_84 pass
7380 13:44:58.975002 alsa_mixer-test_event_missing_0_84 pass
7381 13:44:58.978424 alsa_mixer-test_event_spurious_0_84 pass
7382 13:44:58.981911 alsa_mixer-test_get_value_0_83 pass
7383 13:44:58.985287 alsa_mixer-test_name_0_83 pass
7384 13:44:58.988672 alsa_mixer-test_write_default_0_83 pass
7385 13:44:58.991544 alsa_mixer-test_write_valid_0_83 pass
7386 13:44:58.995232 alsa_mixer-test_write_invalid_0_83 pass
7387 13:44:58.998755 alsa_mixer-test_event_missing_0_83 pass
7388 13:44:59.001646 alsa_mixer-test_event_spurious_0_83 pass
7389 13:44:59.004972 alsa_mixer-test_get_value_0_82 pass
7390 13:44:59.008531 alsa_mixer-test_name_0_82 pass
7391 13:44:59.011777 alsa_mixer-test_write_default_0_82 skip
7392 13:44:59.015113 alsa_mixer-test_write_valid_0_82 skip
7393 13:44:59.018309 alsa_mixer-test_write_invalid_0_82 skip
7394 13:44:59.021920 alsa_mixer-test_event_missing_0_82 pass
7395 13:44:59.025428 alsa_mixer-test_event_spurious_0_82 pass
7396 13:44:59.028480 alsa_mixer-test_get_value_0_81 pass
7397 13:44:59.031998 alsa_mixer-test_name_0_81 pass
7398 13:44:59.035324 alsa_mixer-test_write_default_0_81 pass
7399 13:44:59.038762 alsa_mixer-test_write_valid_0_81 pass
7400 13:44:59.045309 alsa_mixer-test_write_invalid_0_81 fail
7401 13:44:59.048411 alsa_mixer-test_event_missing_0_81 fail
7402 13:44:59.051805 alsa_mixer-test_event_spurious_0_81 pass
7403 13:44:59.055084 alsa_mixer-test_get_value_0_80 pass
7404 13:44:59.058824 alsa_mixer-test_name_0_80 pass
7405 13:44:59.061915 alsa_mixer-test_write_default_0_80 pass
7406 13:44:59.065258 alsa_mixer-test_write_valid_0_80 pass
7407 13:44:59.068314 alsa_mixer-test_write_invalid_0_80 pass
7408 13:44:59.071957 alsa_mixer-test_event_missing_0_80 pass
7409 13:44:59.075730 alsa_mixer-test_event_spurious_0_80 pass
7410 13:44:59.078281 alsa_mixer-test_get_value_0_79 fail
7411 13:44:59.081914 alsa_mixer-test_name_0_79 pass
7412 13:44:59.084828 alsa_mixer-test_write_default_0_79 fail
7413 13:44:59.088731 alsa_mixer-test_write_valid_0_79 fail
7414 13:44:59.091997 alsa_mixer-test_write_invalid_0_79 fail
7415 13:44:59.095359 alsa_mixer-test_event_missing_0_79 pass
7416 13:44:59.098851 alsa_mixer-test_event_spurious_0_79 pass
7417 13:44:59.101805 alsa_mixer-test_get_value_0_78 fail
7418 13:44:59.105424 alsa_mixer-test_name_0_78 pass
7419 13:44:59.108473 alsa_mixer-test_write_default_0_78 fail
7420 13:44:59.111710 alsa_mixer-test_write_valid_0_78 fail
7421 13:44:59.114953 alsa_mixer-test_write_invalid_0_78 fail
7422 13:44:59.118503 alsa_mixer-test_event_missing_0_78 pass
7423 13:44:59.121949 alsa_mixer-test_event_spurious_0_78 pass
7424 13:44:59.124882 alsa_mixer-test_get_value_0_77 fail
7425 13:44:59.128670 alsa_mixer-test_name_0_77 pass
7426 13:44:59.131843 alsa_mixer-test_write_default_0_77 fail
7427 13:44:59.134920 alsa_mixer-test_write_valid_0_77 fail
7428 13:44:59.138663 alsa_mixer-test_write_invalid_0_77 fail
7429 13:44:59.142116 alsa_mixer-test_event_missing_0_77 pass
7430 13:44:59.148612 alsa_mixer-test_event_spurious_0_77 pass
7431 13:44:59.151892 alsa_mixer-test_get_value_0_76 pass
7432 13:44:59.152449 alsa_mixer-test_name_0_76 fail
7433 13:44:59.155120 alsa_mixer-test_write_default_0_76 pass
7434 13:44:59.161359 alsa_mixer-test_write_valid_0_76 pass
7435 13:44:59.164842 alsa_mixer-test_write_invalid_0_76 pass
7436 13:44:59.168241 alsa_mixer-test_event_missing_0_76 pass
7437 13:44:59.172094 alsa_mixer-test_event_spurious_0_76 pass
7438 13:44:59.175189 alsa_mixer-test_get_value_0_75 pass
7439 13:44:59.178563 alsa_mixer-test_name_0_75 fail
7440 13:44:59.181592 alsa_mixer-test_write_default_0_75 pass
7441 13:44:59.184891 alsa_mixer-test_write_valid_0_75 pass
7442 13:44:59.188257 alsa_mixer-test_write_invalid_0_75 pass
7443 13:44:59.191403 alsa_mixer-test_event_missing_0_75 pass
7444 13:44:59.194717 alsa_mixer-test_event_spurious_0_75 pass
7445 13:44:59.197974 alsa_mixer-test_get_value_0_74 pass
7446 13:44:59.201608 alsa_mixer-test_name_0_74 fail
7447 13:44:59.204940 alsa_mixer-test_write_default_0_74 pass
7448 13:44:59.208243 alsa_mixer-test_write_valid_0_74 pass
7449 13:44:59.211407 alsa_mixer-test_write_invalid_0_74 pass
7450 13:44:59.214703 alsa_mixer-test_event_missing_0_74 pass
7451 13:44:59.217928 alsa_mixer-test_event_spurious_0_74 pass
7452 13:44:59.221414 alsa_mixer-test_get_value_0_73 pass
7453 13:44:59.224490 alsa_mixer-test_name_0_73 fail
7454 13:44:59.227946 alsa_mixer-test_write_default_0_73 pass
7455 13:44:59.231387 alsa_mixer-test_write_valid_0_73 pass
7456 13:44:59.234425 alsa_mixer-test_write_invalid_0_73 pass
7457 13:44:59.237797 alsa_mixer-test_event_missing_0_73 pass
7458 13:44:59.241476 alsa_mixer-test_event_spurious_0_73 pass
7459 13:44:59.244942 alsa_mixer-test_get_value_0_72 pass
7460 13:44:59.248098 alsa_mixer-test_name_0_72 fail
7461 13:44:59.251388 alsa_mixer-test_write_default_0_72 pass
7462 13:44:59.255027 alsa_mixer-test_write_valid_0_72 pass
7463 13:44:59.258027 alsa_mixer-test_write_invalid_0_72 pass
7464 13:44:59.261166 alsa_mixer-test_event_missing_0_72 pass
7465 13:44:59.264759 alsa_mixer-test_event_spurious_0_72 pass
7466 13:44:59.268106 alsa_mixer-test_get_value_0_71 pass
7467 13:44:59.270927 alsa_mixer-test_name_0_71 fail
7468 13:44:59.274382 alsa_mixer-test_write_default_0_71 pass
7469 13:44:59.277446 alsa_mixer-test_write_valid_0_71 pass
7470 13:44:59.280602 alsa_mixer-test_write_invalid_0_71 pass
7471 13:44:59.287490 alsa_mixer-test_event_missing_0_71 pass
7472 13:44:59.290805 alsa_mixer-test_event_spurious_0_71 pass
7473 13:44:59.294212 alsa_mixer-test_get_value_0_70 pass
7474 13:44:59.294645 alsa_mixer-test_name_0_70 fail
7475 13:44:59.300426 alsa_mixer-test_write_default_0_70 pass
7476 13:44:59.303738 alsa_mixer-test_write_valid_0_70 pass
7477 13:44:59.307038 alsa_mixer-test_write_invalid_0_70 pass
7478 13:44:59.310695 alsa_mixer-test_event_missing_0_70 pass
7479 13:44:59.313688 alsa_mixer-test_event_spurious_0_70 pass
7480 13:44:59.317525 alsa_mixer-test_get_value_0_69 pass
7481 13:44:59.320276 alsa_mixer-test_name_0_69 fail
7482 13:44:59.323770 alsa_mixer-test_write_default_0_69 pass
7483 13:44:59.327677 alsa_mixer-test_write_valid_0_69 pass
7484 13:44:59.330382 alsa_mixer-test_write_invalid_0_69 pass
7485 13:44:59.333729 alsa_mixer-test_event_missing_0_69 pass
7486 13:44:59.337074 alsa_mixer-test_event_spurious_0_69 pass
7487 13:44:59.340361 alsa_mixer-test_get_value_0_68 pass
7488 13:44:59.343530 alsa_mixer-test_name_0_68 fail
7489 13:44:59.346877 alsa_mixer-test_write_default_0_68 pass
7490 13:44:59.350429 alsa_mixer-test_write_valid_0_68 pass
7491 13:44:59.353232 alsa_mixer-test_write_invalid_0_68 pass
7492 13:44:59.356239 alsa_mixer-test_event_missing_0_68 pass
7493 13:44:59.363192 alsa_mixer-test_event_spurious_0_68 pass
7494 13:44:59.366336 alsa_mixer-test_get_value_0_67 pass
7495 13:44:59.366412 alsa_mixer-test_name_0_67 fail
7496 13:44:59.373166 alsa_mixer-test_write_default_0_67 pass
7497 13:44:59.376058 alsa_mixer-test_write_valid_0_67 pass
7498 13:44:59.379479 alsa_mixer-test_write_invalid_0_67 pass
7499 13:44:59.383018 alsa_mixer-test_event_missing_0_67 pass
7500 13:44:59.386509 alsa_mixer-test_event_spurious_0_67 pass
7501 13:44:59.389793 alsa_mixer-test_get_value_0_66 pass
7502 13:44:59.393027 alsa_mixer-test_name_0_66 fail
7503 13:44:59.396128 alsa_mixer-test_write_default_0_66 pass
7504 13:44:59.399518 alsa_mixer-test_write_valid_0_66 pass
7505 13:44:59.402720 alsa_mixer-test_write_invalid_0_66 pass
7506 13:44:59.406220 alsa_mixer-test_event_missing_0_66 pass
7507 13:44:59.409409 alsa_mixer-test_event_spurious_0_66 pass
7508 13:44:59.413125 alsa_mixer-test_get_value_0_65 pass
7509 13:44:59.416084 alsa_mixer-test_name_0_65 fail
7510 13:44:59.419742 alsa_mixer-test_write_default_0_65 pass
7511 13:44:59.422740 alsa_mixer-test_write_valid_0_65 pass
7512 13:44:59.426292 alsa_mixer-test_write_invalid_0_65 pass
7513 13:44:59.429558 alsa_mixer-test_event_missing_0_65 pass
7514 13:44:59.432963 alsa_mixer-test_event_spurious_0_65 pass
7515 13:44:59.436525 alsa_mixer-test_get_value_0_64 pass
7516 13:44:59.440099 alsa_mixer-test_name_0_64 fail
7517 13:44:59.443378 alsa_mixer-test_write_default_0_64 pass
7518 13:44:59.446258 alsa_mixer-test_write_valid_0_64 pass
7519 13:44:59.449533 alsa_mixer-test_write_invalid_0_64 pass
7520 13:44:59.456206 alsa_mixer-test_event_missing_0_64 pass
7521 13:44:59.459471 alsa_mixer-test_event_spurious_0_64 pass
7522 13:44:59.462858 alsa_mixer-test_get_value_0_63 pass
7523 13:44:59.463291 alsa_mixer-test_name_0_63 fail
7524 13:44:59.466221 alsa_mixer-test_write_default_0_63 pass
7525 13:44:59.469823 alsa_mixer-test_write_valid_0_63 pass
7526 13:44:59.476660 alsa_mixer-test_write_invalid_0_63 pass
7527 13:44:59.479630 alsa_mixer-test_event_missing_0_63 pass
7528 13:44:59.483617 alsa_mixer-test_event_spurious_0_63 pass
7529 13:44:59.486348 alsa_mixer-test_get_value_0_62 pass
7530 13:44:59.489815 alsa_mixer-test_name_0_62 fail
7531 13:44:59.493033 alsa_mixer-test_write_default_0_62 pass
7532 13:44:59.496942 alsa_mixer-test_write_valid_0_62 pass
7533 13:44:59.500054 alsa_mixer-test_write_invalid_0_62 pass
7534 13:44:59.503146 alsa_mixer-test_event_missing_0_62 pass
7535 13:44:59.507019 alsa_mixer-test_event_spurious_0_62 pass
7536 13:44:59.509844 alsa_mixer-test_get_value_0_61 pass
7537 13:44:59.513557 alsa_mixer-test_name_0_61 fail
7538 13:44:59.516872 alsa_mixer-test_write_default_0_61 pass
7539 13:44:59.519627 alsa_mixer-test_write_valid_0_61 pass
7540 13:44:59.523389 alsa_mixer-test_write_invalid_0_61 pass
7541 13:44:59.526340 alsa_mixer-test_event_missing_0_61 pass
7542 13:44:59.532876 alsa_mixer-test_event_spurious_0_61 pass
7543 13:44:59.536231 alsa_mixer-test_get_value_0_60 pass
7544 13:44:59.536678 alsa_mixer-test_name_0_60 fail
7545 13:44:59.542866 alsa_mixer-test_write_default_0_60 pass
7546 13:44:59.546438 alsa_mixer-test_write_valid_0_60 pass
7547 13:44:59.549908 alsa_mixer-test_write_invalid_0_60 pass
7548 13:44:59.552974 alsa_mixer-test_event_missing_0_60 pass
7549 13:44:59.556211 alsa_mixer-test_event_spurious_0_60 pass
7550 13:44:59.559471 alsa_mixer-test_get_value_0_59 pass
7551 13:44:59.562803 alsa_mixer-test_name_0_59 fail
7552 13:44:59.566074 alsa_mixer-test_write_default_0_59 pass
7553 13:44:59.569525 alsa_mixer-test_write_valid_0_59 pass
7554 13:44:59.572655 alsa_mixer-test_write_invalid_0_59 pass
7555 13:44:59.576038 alsa_mixer-test_event_missing_0_59 pass
7556 13:44:59.579659 alsa_mixer-test_event_spurious_0_59 pass
7557 13:44:59.582430 alsa_mixer-test_get_value_0_58 pass
7558 13:44:59.586102 alsa_mixer-test_name_0_58 fail
7559 13:44:59.589155 alsa_mixer-test_write_default_0_58 pass
7560 13:44:59.592479 alsa_mixer-test_write_valid_0_58 pass
7561 13:44:59.599284 alsa_mixer-test_write_invalid_0_58 pass
7562 13:44:59.602435 alsa_mixer-test_event_missing_0_58 pass
7563 13:44:59.605811 alsa_mixer-test_event_spurious_0_58 pass
7564 13:44:59.609341 alsa_mixer-test_get_value_0_57 pass
7565 13:44:59.612727 alsa_mixer-test_name_0_57 fail
7566 13:44:59.615822 alsa_mixer-test_write_default_0_57 pass
7567 13:44:59.619205 alsa_mixer-test_write_valid_0_57 pass
7568 13:44:59.622517 alsa_mixer-test_write_invalid_0_57 pass
7569 13:44:59.625862 alsa_mixer-test_event_missing_0_57 pass
7570 13:44:59.629007 alsa_mixer-test_event_spurious_0_57 pass
7571 13:44:59.632384 alsa_mixer-test_get_value_0_56 pass
7572 13:44:59.635787 alsa_mixer-test_name_0_56 fail
7573 13:44:59.639256 alsa_mixer-test_write_default_0_56 pass
7574 13:44:59.642616 alsa_mixer-test_write_valid_0_56 pass
7575 13:44:59.645430 alsa_mixer-test_write_invalid_0_56 pass
7576 13:44:59.652205 alsa_mixer-test_event_missing_0_56 pass
7577 13:44:59.656107 alsa_mixer-test_event_spurious_0_56 pass
7578 13:44:59.658801 alsa_mixer-test_get_value_0_55 pass
7579 13:44:59.661892 alsa_mixer-test_name_0_55 fail
7580 13:44:59.665663 alsa_mixer-test_write_default_0_55 pass
7581 13:44:59.668839 alsa_mixer-test_write_valid_0_55 pass
7582 13:44:59.672489 alsa_mixer-test_write_invalid_0_55 pass
7583 13:44:59.675423 alsa_mixer-test_event_missing_0_55 pass
7584 13:44:59.678888 alsa_mixer-test_event_spurious_0_55 pass
7585 13:44:59.682273 alsa_mixer-test_get_value_0_54 pass
7586 13:44:59.685302 alsa_mixer-test_name_0_54 fail
7587 13:44:59.689171 alsa_mixer-test_write_default_0_54 pass
7588 13:44:59.692112 alsa_mixer-test_write_valid_0_54 pass
7589 13:44:59.696030 alsa_mixer-test_write_invalid_0_54 pass
7590 13:44:59.698939 alsa_mixer-test_event_missing_0_54 pass
7591 13:44:59.701907 alsa_mixer-test_event_spurious_0_54 pass
7592 13:44:59.705289 alsa_mixer-test_get_value_0_53 pass
7593 13:44:59.708702 alsa_mixer-test_name_0_53 fail
7594 13:44:59.712507 alsa_mixer-test_write_default_0_53 pass
7595 13:44:59.715409 alsa_mixer-test_write_valid_0_53 pass
7596 13:44:59.722116 alsa_mixer-test_write_invalid_0_53 pass
7597 13:44:59.725622 alsa_mixer-test_event_missing_0_53 pass
7598 13:44:59.728658 alsa_mixer-test_event_spurious_0_53 pass
7599 13:44:59.731639 alsa_mixer-test_get_value_0_52 pass
7600 13:44:59.735212 alsa_mixer-test_name_0_52 fail
7601 13:44:59.738813 alsa_mixer-test_write_default_0_52 pass
7602 13:44:59.741505 alsa_mixer-test_write_valid_0_52 pass
7603 13:44:59.745749 alsa_mixer-test_write_invalid_0_52 pass
7604 13:44:59.748631 alsa_mixer-test_event_missing_0_52 pass
7605 13:44:59.751722 alsa_mixer-test_event_spurious_0_52 pass
7606 13:44:59.755291 alsa_mixer-test_get_value_0_51 pass
7607 13:44:59.758455 alsa_mixer-test_name_0_51 fail
7608 13:44:59.761808 alsa_mixer-test_write_default_0_51 pass
7609 13:44:59.765182 alsa_mixer-test_write_valid_0_51 pass
7610 13:44:59.768704 alsa_mixer-test_write_invalid_0_51 pass
7611 13:44:59.775440 alsa_mixer-test_event_missing_0_51 pass
7612 13:44:59.778652 alsa_mixer-test_event_spurious_0_51 pass
7613 13:44:59.782059 alsa_mixer-test_get_value_0_50 pass
7614 13:44:59.784816 alsa_mixer-test_name_0_50 fail
7615 13:44:59.788108 alsa_mixer-test_write_default_0_50 pass
7616 13:44:59.791512 alsa_mixer-test_write_valid_0_50 pass
7617 13:44:59.794798 alsa_mixer-test_write_invalid_0_50 pass
7618 13:44:59.798459 alsa_mixer-test_event_missing_0_50 pass
7619 13:44:59.801504 alsa_mixer-test_event_spurious_0_50 pass
7620 13:44:59.805067 alsa_mixer-test_get_value_0_49 pass
7621 13:44:59.808048 alsa_mixer-test_name_0_49 fail
7622 13:44:59.811516 alsa_mixer-test_write_default_0_49 pass
7623 13:44:59.814780 alsa_mixer-test_write_valid_0_49 pass
7624 13:44:59.818015 alsa_mixer-test_write_invalid_0_49 pass
7625 13:44:59.821488 alsa_mixer-test_event_missing_0_49 pass
7626 13:44:59.825003 alsa_mixer-test_event_spurious_0_49 pass
7627 13:44:59.827938 alsa_mixer-test_get_value_0_48 pass
7628 13:44:59.831406 alsa_mixer-test_name_0_48 fail
7629 13:44:59.834530 alsa_mixer-test_write_default_0_48 pass
7630 13:44:59.838247 alsa_mixer-test_write_valid_0_48 pass
7631 13:44:59.845045 alsa_mixer-test_write_invalid_0_48 pass
7632 13:44:59.848309 alsa_mixer-test_event_missing_0_48 pass
7633 13:44:59.851470 alsa_mixer-test_event_spurious_0_48 pass
7634 13:44:59.855044 alsa_mixer-test_get_value_0_47 pass
7635 13:44:59.858359 alsa_mixer-test_name_0_47 fail
7636 13:44:59.861817 alsa_mixer-test_write_default_0_47 pass
7637 13:44:59.865061 alsa_mixer-test_write_valid_0_47 pass
7638 13:44:59.867985 alsa_mixer-test_write_invalid_0_47 pass
7639 13:44:59.871568 alsa_mixer-test_event_missing_0_47 pass
7640 13:44:59.875023 alsa_mixer-test_event_spurious_0_47 pass
7641 13:44:59.877854 alsa_mixer-test_get_value_0_46 pass
7642 13:44:59.881464 alsa_mixer-test_name_0_46 fail
7643 13:44:59.884992 alsa_mixer-test_write_default_0_46 pass
7644 13:44:59.888068 alsa_mixer-test_write_valid_0_46 pass
7645 13:44:59.891057 alsa_mixer-test_write_invalid_0_46 pass
7646 13:44:59.894693 alsa_mixer-test_event_missing_0_46 pass
7647 13:44:59.901516 alsa_mixer-test_event_spurious_0_46 pass
7648 13:44:59.904912 alsa_mixer-test_get_value_0_45 pass
7649 13:44:59.905474 alsa_mixer-test_name_0_45 fail
7650 13:44:59.911637 alsa_mixer-test_write_default_0_45 pass
7651 13:44:59.914911 alsa_mixer-test_write_valid_0_45 pass
7652 13:44:59.918682 alsa_mixer-test_write_invalid_0_45 pass
7653 13:44:59.921527 alsa_mixer-test_event_missing_0_45 pass
7654 13:44:59.924415 alsa_mixer-test_event_spurious_0_45 pass
7655 13:44:59.928006 alsa_mixer-test_get_value_0_44 pass
7656 13:44:59.931035 alsa_mixer-test_name_0_44 fail
7657 13:44:59.934595 alsa_mixer-test_write_default_0_44 pass
7658 13:44:59.937706 alsa_mixer-test_write_valid_0_44 pass
7659 13:44:59.941090 alsa_mixer-test_write_invalid_0_44 pass
7660 13:44:59.944562 alsa_mixer-test_event_missing_0_44 pass
7661 13:44:59.947915 alsa_mixer-test_event_spurious_0_44 pass
7662 13:44:59.951192 alsa_mixer-test_get_value_0_43 pass
7663 13:44:59.954677 alsa_mixer-test_name_0_43 fail
7664 13:44:59.957675 alsa_mixer-test_write_default_0_43 pass
7665 13:44:59.961385 alsa_mixer-test_write_valid_0_43 pass
7666 13:44:59.964474 alsa_mixer-test_write_invalid_0_43 pass
7667 13:44:59.971004 alsa_mixer-test_event_missing_0_43 pass
7668 13:44:59.974080 alsa_mixer-test_event_spurious_0_43 pass
7669 13:44:59.977969 alsa_mixer-test_get_value_0_42 pass
7670 13:44:59.981281 alsa_mixer-test_name_0_42 fail
7671 13:44:59.984577 alsa_mixer-test_write_default_0_42 pass
7672 13:44:59.987999 alsa_mixer-test_write_valid_0_42 pass
7673 13:44:59.990926 alsa_mixer-test_write_invalid_0_42 pass
7674 13:44:59.994116 alsa_mixer-test_event_missing_0_42 pass
7675 13:44:59.997680 alsa_mixer-test_event_spurious_0_42 pass
7676 13:45:00.000749 alsa_mixer-test_get_value_0_41 pass
7677 13:45:00.004227 alsa_mixer-test_name_0_41 fail
7678 13:45:00.007477 alsa_mixer-test_write_default_0_41 pass
7679 13:45:00.010695 alsa_mixer-test_write_valid_0_41 pass
7680 13:45:00.014241 alsa_mixer-test_write_invalid_0_41 pass
7681 13:45:00.017322 alsa_mixer-test_event_missing_0_41 pass
7682 13:45:00.024085 alsa_mixer-test_event_spurious_0_41 pass
7683 13:45:00.027630 alsa_mixer-test_get_value_0_40 pass
7684 13:45:00.028058 alsa_mixer-test_name_0_40 fail
7685 13:45:00.030721 alsa_mixer-test_write_default_0_40 pass
7686 13:45:00.037530 alsa_mixer-test_write_valid_0_40 pass
7687 13:45:00.040805 alsa_mixer-test_write_invalid_0_40 pass
7688 13:45:00.044151 alsa_mixer-test_event_missing_0_40 pass
7689 13:45:00.047278 alsa_mixer-test_event_spurious_0_40 pass
7690 13:45:00.050766 alsa_mixer-test_get_value_0_39 pass
7691 13:45:00.054139 alsa_mixer-test_name_0_39 fail
7692 13:45:00.057561 alsa_mixer-test_write_default_0_39 pass
7693 13:45:00.060924 alsa_mixer-test_write_valid_0_39 pass
7694 13:45:00.064460 alsa_mixer-test_write_invalid_0_39 pass
7695 13:45:00.067361 alsa_mixer-test_event_missing_0_39 pass
7696 13:45:00.070723 alsa_mixer-test_event_spurious_0_39 pass
7697 13:45:00.074562 alsa_mixer-test_get_value_0_38 pass
7698 13:45:00.077302 alsa_mixer-test_name_0_38 fail
7699 13:45:00.080509 alsa_mixer-test_write_default_0_38 pass
7700 13:45:00.084278 alsa_mixer-test_write_valid_0_38 pass
7701 13:45:00.087879 alsa_mixer-test_write_invalid_0_38 pass
7702 13:45:00.094059 alsa_mixer-test_event_missing_0_38 pass
7703 13:45:00.097113 alsa_mixer-test_event_spurious_0_38 pass
7704 13:45:00.100854 alsa_mixer-test_get_value_0_37 pass
7705 13:45:00.104056 alsa_mixer-test_name_0_37 fail
7706 13:45:00.107030 alsa_mixer-test_write_default_0_37 pass
7707 13:45:00.110459 alsa_mixer-test_write_valid_0_37 pass
7708 13:45:00.113727 alsa_mixer-test_write_invalid_0_37 pass
7709 13:45:00.117016 alsa_mixer-test_event_missing_0_37 pass
7710 13:45:00.120518 alsa_mixer-test_event_spurious_0_37 pass
7711 13:45:00.123789 alsa_mixer-test_get_value_0_36 pass
7712 13:45:00.127454 alsa_mixer-test_name_0_36 fail
7713 13:45:00.130319 alsa_mixer-test_write_default_0_36 pass
7714 13:45:00.133916 alsa_mixer-test_write_valid_0_36 pass
7715 13:45:00.136678 alsa_mixer-test_write_invalid_0_36 pass
7716 13:45:00.140487 alsa_mixer-test_event_missing_0_36 pass
7717 13:45:00.143394 alsa_mixer-test_event_spurious_0_36 pass
7718 13:45:00.146840 alsa_mixer-test_get_value_0_35 pass
7719 13:45:00.150127 alsa_mixer-test_name_0_35 fail
7720 13:45:00.153420 alsa_mixer-test_write_default_0_35 pass
7721 13:45:00.160451 alsa_mixer-test_write_valid_0_35 pass
7722 13:45:00.163613 alsa_mixer-test_write_invalid_0_35 pass
7723 13:45:00.166945 alsa_mixer-test_event_missing_0_35 pass
7724 13:45:00.170404 alsa_mixer-test_event_spurious_0_35 pass
7725 13:45:00.173794 alsa_mixer-test_get_value_0_34 pass
7726 13:45:00.177141 alsa_mixer-test_name_0_34 fail
7727 13:45:00.179889 alsa_mixer-test_write_default_0_34 pass
7728 13:45:00.183518 alsa_mixer-test_write_valid_0_34 pass
7729 13:45:00.186826 alsa_mixer-test_write_invalid_0_34 pass
7730 13:45:00.190531 alsa_mixer-test_event_missing_0_34 pass
7731 13:45:00.193518 alsa_mixer-test_event_spurious_0_34 pass
7732 13:45:00.197035 alsa_mixer-test_get_value_0_33 pass
7733 13:45:00.199977 alsa_mixer-test_name_0_33 fail
7734 13:45:00.203496 alsa_mixer-test_write_default_0_33 pass
7735 13:45:00.207046 alsa_mixer-test_write_valid_0_33 pass
7736 13:45:00.210067 alsa_mixer-test_write_invalid_0_33 pass
7737 13:45:00.213570 alsa_mixer-test_event_missing_0_33 pass
7738 13:45:00.220026 alsa_mixer-test_event_spurious_0_33 pass
7739 13:45:00.223487 alsa_mixer-test_get_value_0_32 pass
7740 13:45:00.223890 alsa_mixer-test_name_0_32 fail
7741 13:45:00.230358 alsa_mixer-test_write_default_0_32 pass
7742 13:45:00.233527 alsa_mixer-test_write_valid_0_32 pass
7743 13:45:00.236862 alsa_mixer-test_write_invalid_0_32 pass
7744 13:45:00.240019 alsa_mixer-test_event_missing_0_32 pass
7745 13:45:00.243192 alsa_mixer-test_event_spurious_0_32 pass
7746 13:45:00.246484 alsa_mixer-test_get_value_0_31 pass
7747 13:45:00.249959 alsa_mixer-test_name_0_31 fail
7748 13:45:00.253392 alsa_mixer-test_write_default_0_31 pass
7749 13:45:00.256533 alsa_mixer-test_write_valid_0_31 pass
7750 13:45:00.259993 alsa_mixer-test_write_invalid_0_31 pass
7751 13:45:00.263101 alsa_mixer-test_event_missing_0_31 pass
7752 13:45:00.266446 alsa_mixer-test_event_spurious_0_31 pass
7753 13:45:00.269663 alsa_mixer-test_get_value_0_30 pass
7754 13:45:00.273116 alsa_mixer-test_name_0_30 fail
7755 13:45:00.276191 alsa_mixer-test_write_default_0_30 pass
7756 13:45:00.280144 alsa_mixer-test_write_valid_0_30 pass
7757 13:45:00.286632 alsa_mixer-test_write_invalid_0_30 pass
7758 13:45:00.289846 alsa_mixer-test_event_missing_0_30 pass
7759 13:45:00.292999 alsa_mixer-test_event_spurious_0_30 pass
7760 13:45:00.296304 alsa_mixer-test_get_value_0_29 pass
7761 13:45:00.299913 alsa_mixer-test_name_0_29 pass
7762 13:45:00.303056 alsa_mixer-test_write_default_0_29 pass
7763 13:45:00.306585 alsa_mixer-test_write_valid_0_29 pass
7764 13:45:00.309676 alsa_mixer-test_write_invalid_0_29 pass
7765 13:45:00.313094 alsa_mixer-test_event_missing_0_29 pass
7766 13:45:00.316093 alsa_mixer-test_event_spurious_0_29 pass
7767 13:45:00.319402 alsa_mixer-test_get_value_0_28 pass
7768 13:45:00.322805 alsa_mixer-test_name_0_28 pass
7769 13:45:00.326292 alsa_mixer-test_write_default_0_28 pass
7770 13:45:00.329654 alsa_mixer-test_write_valid_0_28 pass
7771 13:45:00.333200 alsa_mixer-test_write_invalid_0_28 pass
7772 13:45:00.336185 alsa_mixer-test_event_missing_0_28 pass
7773 13:45:00.342967 alsa_mixer-test_event_spurious_0_28 pass
7774 13:45:00.346058 alsa_mixer-test_get_value_0_27 pass
7775 13:45:00.346443 alsa_mixer-test_name_0_27 pass
7776 13:45:00.352925 alsa_mixer-test_write_default_0_27 pass
7777 13:45:00.356093 alsa_mixer-test_write_valid_0_27 pass
7778 13:45:00.359405 alsa_mixer-test_write_invalid_0_27 pass
7779 13:45:00.362457 alsa_mixer-test_event_missing_0_27 pass
7780 13:45:00.366094 alsa_mixer-test_event_spurious_0_27 pass
7781 13:45:00.369216 alsa_mixer-test_get_value_0_26 pass
7782 13:45:00.372657 alsa_mixer-test_name_0_26 pass
7783 13:45:00.375643 alsa_mixer-test_write_default_0_26 pass
7784 13:45:00.378835 alsa_mixer-test_write_valid_0_26 pass
7785 13:45:00.382021 alsa_mixer-test_write_invalid_0_26 pass
7786 13:45:00.385873 alsa_mixer-test_event_missing_0_26 pass
7787 13:45:00.389007 alsa_mixer-test_event_spurious_0_26 pass
7788 13:45:00.391970 alsa_mixer-test_get_value_0_25 pass
7789 13:45:00.395404 alsa_mixer-test_name_0_25 pass
7790 13:45:00.399026 alsa_mixer-test_write_default_0_25 pass
7791 13:45:00.401986 alsa_mixer-test_write_valid_0_25 pass
7792 13:45:00.408663 alsa_mixer-test_write_invalid_0_25 pass
7793 13:45:00.412341 alsa_mixer-test_event_missing_0_25 pass
7794 13:45:00.415635 alsa_mixer-test_event_spurious_0_25 pass
7795 13:45:00.418713 alsa_mixer-test_get_value_0_24 pass
7796 13:45:00.422178 alsa_mixer-test_name_0_24 pass
7797 13:45:00.425358 alsa_mixer-test_write_default_0_24 pass
7798 13:45:00.428599 alsa_mixer-test_write_valid_0_24 pass
7799 13:45:00.432272 alsa_mixer-test_write_invalid_0_24 pass
7800 13:45:00.435183 alsa_mixer-test_event_missing_0_24 pass
7801 13:45:00.438715 alsa_mixer-test_event_spurious_0_24 pass
7802 13:45:00.441823 alsa_mixer-test_get_value_0_23 pass
7803 13:45:00.445448 alsa_mixer-test_name_0_23 pass
7804 13:45:00.448792 alsa_mixer-test_write_default_0_23 pass
7805 13:45:00.452164 alsa_mixer-test_write_valid_0_23 pass
7806 13:45:00.455591 alsa_mixer-test_write_invalid_0_23 pass
7807 13:45:00.458632 alsa_mixer-test_event_missing_0_23 pass
7808 13:45:00.465423 alsa_mixer-test_event_spurious_0_23 pass
7809 13:45:00.468627 alsa_mixer-test_get_value_0_22 pass
7810 13:45:00.468701 alsa_mixer-test_name_0_22 pass
7811 13:45:00.475062 alsa_mixer-test_write_default_0_22 pass
7812 13:45:00.478476 alsa_mixer-test_write_valid_0_22 pass
7813 13:45:00.481661 alsa_mixer-test_write_invalid_0_22 pass
7814 13:45:00.485083 alsa_mixer-test_event_missing_0_22 pass
7815 13:45:00.488626 alsa_mixer-test_event_spurious_0_22 pass
7816 13:45:00.492018 alsa_mixer-test_get_value_0_21 pass
7817 13:45:00.495166 alsa_mixer-test_name_0_21 fail
7818 13:45:00.498600 alsa_mixer-test_write_default_0_21 pass
7819 13:45:00.501688 alsa_mixer-test_write_valid_0_21 pass
7820 13:45:00.505214 alsa_mixer-test_write_invalid_0_21 pass
7821 13:45:00.508570 alsa_mixer-test_event_missing_0_21 pass
7822 13:45:00.511796 alsa_mixer-test_event_spurious_0_21 pass
7823 13:45:00.514919 alsa_mixer-test_get_value_0_20 pass
7824 13:45:00.518549 alsa_mixer-test_name_0_20 fail
7825 13:45:00.522016 alsa_mixer-test_write_default_0_20 pass
7826 13:45:00.525075 alsa_mixer-test_write_valid_0_20 pass
7827 13:45:00.528683 alsa_mixer-test_write_invalid_0_20 pass
7828 13:45:00.535712 alsa_mixer-test_event_missing_0_20 pass
7829 13:45:00.538408 alsa_mixer-test_event_spurious_0_20 pass
7830 13:45:00.541975 alsa_mixer-test_get_value_0_19 pass
7831 13:45:00.545081 alsa_mixer-test_name_0_19 fail
7832 13:45:00.548513 alsa_mixer-test_write_default_0_19 pass
7833 13:45:00.552173 alsa_mixer-test_write_valid_0_19 pass
7834 13:45:00.555601 alsa_mixer-test_write_invalid_0_19 pass
7835 13:45:00.558628 alsa_mixer-test_event_missing_0_19 pass
7836 13:45:00.562046 alsa_mixer-test_event_spurious_0_19 pass
7837 13:45:00.565136 alsa_mixer-test_get_value_0_18 pass
7838 13:45:00.568881 alsa_mixer-test_name_0_18 fail
7839 13:45:00.572251 alsa_mixer-test_write_default_0_18 pass
7840 13:45:00.575467 alsa_mixer-test_write_valid_0_18 pass
7841 13:45:00.578856 alsa_mixer-test_write_invalid_0_18 pass
7842 13:45:00.582213 alsa_mixer-test_event_missing_0_18 pass
7843 13:45:00.585597 alsa_mixer-test_event_spurious_0_18 pass
7844 13:45:00.588988 alsa_mixer-test_get_value_0_17 pass
7845 13:45:00.592124 alsa_mixer-test_name_0_17 fail
7846 13:45:00.595819 alsa_mixer-test_write_default_0_17 pass
7847 13:45:00.599143 alsa_mixer-test_write_valid_0_17 pass
7848 13:45:00.605417 alsa_mixer-test_write_invalid_0_17 pass
7849 13:45:00.608690 alsa_mixer-test_event_missing_0_17 pass
7850 13:45:00.611931 alsa_mixer-test_event_spurious_0_17 pass
7851 13:45:00.615832 alsa_mixer-test_get_value_0_16 pass
7852 13:45:00.618643 alsa_mixer-test_name_0_16 fail
7853 13:45:00.621765 alsa_mixer-test_write_default_0_16 pass
7854 13:45:00.625561 alsa_mixer-test_write_valid_0_16 pass
7855 13:45:00.628665 alsa_mixer-test_write_invalid_0_16 pass
7856 13:45:00.632387 alsa_mixer-test_event_missing_0_16 pass
7857 13:45:00.635610 alsa_mixer-test_event_spurious_0_16 pass
7858 13:45:00.638703 alsa_mixer-test_get_value_0_15 pass
7859 13:45:00.642085 alsa_mixer-test_name_0_15 fail
7860 13:45:00.645291 alsa_mixer-test_write_default_0_15 pass
7861 13:45:00.648611 alsa_mixer-test_write_valid_0_15 pass
7862 13:45:00.652007 alsa_mixer-test_write_invalid_0_15 pass
7863 13:45:00.655645 alsa_mixer-test_event_missing_0_15 pass
7864 13:45:00.661897 alsa_mixer-test_event_spurious_0_15 pass
7865 13:45:00.665144 alsa_mixer-test_get_value_0_14 pass
7866 13:45:00.665562 alsa_mixer-test_name_0_14 fail
7867 13:45:00.671793 alsa_mixer-test_write_default_0_14 pass
7868 13:45:00.675350 alsa_mixer-test_write_valid_0_14 pass
7869 13:45:00.678388 alsa_mixer-test_write_invalid_0_14 pass
7870 13:45:00.681721 alsa_mixer-test_event_missing_0_14 pass
7871 13:45:00.685021 alsa_mixer-test_event_spurious_0_14 pass
7872 13:45:00.688474 alsa_mixer-test_get_value_0_13 pass
7873 13:45:00.691683 alsa_mixer-test_name_0_13 fail
7874 13:45:00.695027 alsa_mixer-test_write_default_0_13 pass
7875 13:45:00.698443 alsa_mixer-test_write_valid_0_13 pass
7876 13:45:00.701916 alsa_mixer-test_write_invalid_0_13 pass
7877 13:45:00.705320 alsa_mixer-test_event_missing_0_13 pass
7878 13:45:00.708571 alsa_mixer-test_event_spurious_0_13 pass
7879 13:45:00.711691 alsa_mixer-test_get_value_0_12 pass
7880 13:45:00.715236 alsa_mixer-test_name_0_12 fail
7881 13:45:00.718538 alsa_mixer-test_write_default_0_12 pass
7882 13:45:00.721791 alsa_mixer-test_write_valid_0_12 pass
7883 13:45:00.725149 alsa_mixer-test_write_invalid_0_12 pass
7884 13:45:00.731611 alsa_mixer-test_event_missing_0_12 pass
7885 13:45:00.734886 alsa_mixer-test_event_spurious_0_12 pass
7886 13:45:00.738574 alsa_mixer-test_get_value_0_11 pass
7887 13:45:00.742116 alsa_mixer-test_name_0_11 fail
7888 13:45:00.745558 alsa_mixer-test_write_default_0_11 pass
7889 13:45:00.748585 alsa_mixer-test_write_valid_0_11 pass
7890 13:45:00.751756 alsa_mixer-test_write_invalid_0_11 pass
7891 13:45:00.755183 alsa_mixer-test_event_missing_0_11 pass
7892 13:45:00.758195 alsa_mixer-test_event_spurious_0_11 pass
7893 13:45:00.762036 alsa_mixer-test_get_value_0_10 pass
7894 13:45:00.764912 alsa_mixer-test_name_0_10 fail
7895 13:45:00.768251 alsa_mixer-test_write_default_0_10 pass
7896 13:45:00.771792 alsa_mixer-test_write_valid_0_10 pass
7897 13:45:00.775016 alsa_mixer-test_write_invalid_0_10 pass
7898 13:45:00.778562 alsa_mixer-test_event_missing_0_10 pass
7899 13:45:00.781791 alsa_mixer-test_event_spurious_0_10 pass
7900 13:45:00.784989 alsa_mixer-test_get_value_0_9 pass
7901 13:45:00.788602 alsa_mixer-test_name_0_9 fail
7902 13:45:00.791520 alsa_mixer-test_write_default_0_9 pass
7903 13:45:00.794999 alsa_mixer-test_write_valid_0_9 pass
7904 13:45:00.798143 alsa_mixer-test_write_invalid_0_9 pass
7905 13:45:00.801604 alsa_mixer-test_event_missing_0_9 pass
7906 13:45:00.808056 alsa_mixer-test_event_spurious_0_9 pass
7907 13:45:00.811925 alsa_mixer-test_get_value_0_8 pass
7908 13:45:00.812553 alsa_mixer-test_name_0_8 fail
7909 13:45:00.814804 alsa_mixer-test_write_default_0_8 pass
7910 13:45:00.818251 alsa_mixer-test_write_valid_0_8 pass
7911 13:45:00.821461 alsa_mixer-test_write_invalid_0_8 pass
7912 13:45:00.824652 alsa_mixer-test_event_missing_0_8 pass
7913 13:45:00.831690 alsa_mixer-test_event_spurious_0_8 pass
7914 13:45:00.832347 alsa_mixer-test_get_value_0_7 pass
7915 13:45:00.834889 alsa_mixer-test_name_0_7 fail
7916 13:45:00.837720 alsa_mixer-test_write_default_0_7 pass
7917 13:45:00.841368 alsa_mixer-test_write_valid_0_7 pass
7918 13:45:00.845254 alsa_mixer-test_write_invalid_0_7 pass
7919 13:45:00.847768 alsa_mixer-test_event_missing_0_7 pass
7920 13:45:00.851250 alsa_mixer-test_event_spurious_0_7 pass
7921 13:45:00.854947 alsa_mixer-test_get_value_0_6 pass
7922 13:45:00.858392 alsa_mixer-test_name_0_6 fail
7923 13:45:00.861375 alsa_mixer-test_write_default_0_6 pass
7924 13:45:00.864842 alsa_mixer-test_write_valid_0_6 pass
7925 13:45:00.867797 alsa_mixer-test_write_invalid_0_6 pass
7926 13:45:00.871213 alsa_mixer-test_event_missing_0_6 pass
7927 13:45:00.878118 alsa_mixer-test_event_spurious_0_6 pass
7928 13:45:00.878508 alsa_mixer-test_get_value_0_5 pass
7929 13:45:00.881105 alsa_mixer-test_name_0_5 pass
7930 13:45:00.884369 alsa_mixer-test_write_default_0_5 pass
7931 13:45:00.888087 alsa_mixer-test_write_valid_0_5 pass
7932 13:45:00.891009 alsa_mixer-test_write_invalid_0_5 pass
7933 13:45:00.895137 alsa_mixer-test_event_missing_0_5 fail
7934 13:45:00.898218 alsa_mixer-test_event_spurious_0_5 pass
7935 13:45:00.901026 alsa_mixer-test_get_value_0_4 pass
7936 13:45:00.904558 alsa_mixer-test_name_0_4 pass
7937 13:45:00.908047 alsa_mixer-test_write_default_0_4 pass
7938 13:45:00.911158 alsa_mixer-test_write_valid_0_4 pass
7939 13:45:00.914720 alsa_mixer-test_write_invalid_0_4 pass
7940 13:45:00.917647 alsa_mixer-test_event_missing_0_4 fail
7941 13:45:00.924359 alsa_mixer-test_event_spurious_0_4 pass
7942 13:45:00.927813 alsa_mixer-test_get_value_0_3 pass
7943 13:45:00.928321 alsa_mixer-test_name_0_3 pass
7944 13:45:00.931041 alsa_mixer-test_write_default_0_3 pass
7945 13:45:00.934225 alsa_mixer-test_write_valid_0_3 pass
7946 13:45:00.937682 alsa_mixer-test_write_invalid_0_3 pass
7947 13:45:00.940874 alsa_mixer-test_event_missing_0_3 fail
7948 13:45:00.947536 alsa_mixer-test_event_spurious_0_3 pass
7949 13:45:00.947932 alsa_mixer-test_get_value_0_2 pass
7950 13:45:00.950973 alsa_mixer-test_name_0_2 pass
7951 13:45:00.954238 alsa_mixer-test_write_default_0_2 pass
7952 13:45:00.957602 alsa_mixer-test_write_valid_0_2 pass
7953 13:45:00.960956 alsa_mixer-test_write_invalid_0_2 pass
7954 13:45:00.964294 alsa_mixer-test_event_missing_0_2 fail
7955 13:45:00.970720 alsa_mixer-test_event_spurious_0_2 pass
7956 13:45:00.974174 alsa_mixer-test_get_value_0_1 pass
7957 13:45:00.974560 alsa_mixer-test_name_0_1 pass
7958 13:45:00.977335 alsa_mixer-test_write_default_0_1 pass
7959 13:45:00.981002 alsa_mixer-test_write_valid_0_1 pass
7960 13:45:00.984342 alsa_mixer-test_write_invalid_0_1 pass
7961 13:45:00.990722 alsa_mixer-test_event_missing_0_1 fail
7962 13:45:00.994301 alsa_mixer-test_event_spurious_0_1 pass
7963 13:45:00.997567 alsa_mixer-test_get_value_0_0 pass
7964 13:45:00.997954 alsa_mixer-test_name_0_0 pass
7965 13:45:01.000621 alsa_mixer-test_write_default_0_0 pass
7966 13:45:01.003689 alsa_mixer-test_write_valid_0_0 pass
7967 13:45:01.010655 alsa_mixer-test_write_invalid_0_0 pass
7968 13:45:01.014188 alsa_mixer-test_event_missing_0_0 fail
7969 13:45:01.017179 alsa_mixer-test_event_spurious_0_0 pass
7970 13:45:01.017774 alsa_mixer-test pass
7971 13:45:01.024069 + ../../utils/send-to-lava.sh ./output/result.txt
7972 13:45:01.027251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
7973 13:45:01.028331 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
7975 13:45:01.033715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass>
7976 13:45:01.034355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass
7978 13:45:01.040328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass>
7979 13:45:01.041042 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass
7981 13:45:01.046926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass>
7982 13:45:01.047564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass
7984 13:45:01.093344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass>
7985 13:45:01.094006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass
7987 13:45:01.146433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass>
7988 13:45:01.146696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass
7990 13:45:01.192035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass>
7991 13:45:01.192296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass
7993 13:45:01.230449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass>
7994 13:45:01.230735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass
7996 13:45:01.275794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass>
7997 13:45:01.276065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass
7999 13:45:01.309159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass>
8000 13:45:01.309488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass
8002 13:45:01.349856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass>
8003 13:45:01.350111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass
8005 13:45:01.387873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass>
8006 13:45:01.388128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass
8008 13:45:01.431335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass>
8009 13:45:01.431590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass
8011 13:45:01.473163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass>
8012 13:45:01.473462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass
8014 13:45:01.516278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass>
8015 13:45:01.516533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass
8017 13:45:01.560775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass>
8018 13:45:01.561059 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass
8020 13:45:01.595241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass>
8021 13:45:01.595488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass
8023 13:45:01.639601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass>
8024 13:45:01.639884 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass
8026 13:45:01.686333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass>
8027 13:45:01.686627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass
8029 13:45:01.729488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass>
8030 13:45:01.729762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass
8032 13:45:01.767327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass>
8033 13:45:01.767596 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass
8035 13:45:01.805992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass>
8036 13:45:01.806247 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass
8038 13:45:01.846445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass>
8039 13:45:01.846708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass
8041 13:45:01.881391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass>
8042 13:45:01.881637 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass
8044 13:45:01.924188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass>
8045 13:45:01.924455 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass
8047 13:45:01.966769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass>
8048 13:45:01.967023 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass
8050 13:45:02.005177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass>
8051 13:45:02.005457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass
8053 13:45:02.044280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass>
8054 13:45:02.044543 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass
8056 13:45:02.087834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass>
8057 13:45:02.088494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass
8059 13:45:02.138596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass>
8060 13:45:02.139249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass
8062 13:45:02.188083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass>
8063 13:45:02.188705 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass
8065 13:45:02.244308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass>
8066 13:45:02.245047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass
8068 13:45:02.297164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass>
8069 13:45:02.297996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass
8071 13:45:02.349496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass>
8072 13:45:02.350125 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass
8074 13:45:02.397379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass>
8075 13:45:02.398029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass
8077 13:45:02.451787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass>
8078 13:45:02.452490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass
8080 13:45:02.502329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass>
8081 13:45:02.503001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass
8083 13:45:02.554472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass>
8084 13:45:02.555128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass
8086 13:45:02.617291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass>
8087 13:45:02.617983 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass
8089 13:45:02.669339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail>
8090 13:45:02.670011 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail
8092 13:45:02.725536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass>
8093 13:45:02.726158 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass
8095 13:45:02.779771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass>
8096 13:45:02.780392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass
8098 13:45:02.829953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail>
8099 13:45:02.830643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail
8101 13:45:02.879474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass>
8102 13:45:02.880130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass
8104 13:45:02.926328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass>
8105 13:45:02.926945 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass
8107 13:45:02.980691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass>
8108 13:45:02.981356 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass
8110 13:45:03.037462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass>
8111 13:45:03.038092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass
8113 13:45:03.091265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass>
8114 13:45:03.092007 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass
8116 13:45:03.143866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass>
8117 13:45:03.144615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass
8119 13:45:03.199122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass>
8120 13:45:03.199881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass
8122 13:45:03.252061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass>
8123 13:45:03.252845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass
8125 13:45:03.302259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass>
8126 13:45:03.302950 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass
8128 13:45:03.360961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass>
8129 13:45:03.361629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass
8131 13:45:03.416591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail>
8132 13:45:03.417277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail
8134 13:45:03.474766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass>
8135 13:45:03.475434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass
8137 13:45:03.531540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass>
8138 13:45:03.532166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass
8140 13:45:03.584734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass>
8141 13:45:03.585392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass
8143 13:45:03.637265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass>
8144 13:45:03.637928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass
8146 13:45:03.687979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass>
8147 13:45:03.688750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass
8149 13:45:03.740957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass>
8150 13:45:03.741249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass
8152 13:45:03.787899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail>
8153 13:45:03.788163 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail
8155 13:45:03.841142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass>
8156 13:45:03.841819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass
8158 13:45:03.893004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass>
8159 13:45:03.893691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass
8161 13:45:03.941577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass>
8162 13:45:03.941872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass
8164 13:45:03.986409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass>
8165 13:45:03.986738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass
8167 13:45:04.030022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass>
8168 13:45:04.030319 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass
8170 13:45:04.074337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass>
8171 13:45:04.074639 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass
8173 13:45:04.087456 <6>[ 40.039429] vaux18: disabling
8174 13:45:04.091051 <6>[ 40.043248] vio28: disabling
8175 13:45:04.126262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass>
8176 13:45:04.126513 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass
8178 13:45:04.173096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass>
8179 13:45:04.173433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass
8181 13:45:04.221154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass>
8182 13:45:04.221461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass
8184 13:45:04.269921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass>
8185 13:45:04.270231 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass
8187 13:45:04.317677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass>
8188 13:45:04.317987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass
8190 13:45:04.364177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass>
8191 13:45:04.364814 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass
8193 13:45:04.422051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass>
8194 13:45:04.422797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass
8196 13:45:04.482319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass>
8197 13:45:04.482956 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass
8199 13:45:04.537075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass>
8200 13:45:04.537734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass
8202 13:45:04.589776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass>
8203 13:45:04.590414 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass
8205 13:45:04.642970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass>
8206 13:45:04.643608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass
8208 13:45:04.694456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass>
8209 13:45:04.695229 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass
8211 13:45:04.742642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass>
8212 13:45:04.742939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass
8214 13:45:04.787309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip>
8215 13:45:04.787562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip
8217 13:45:04.833459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip>
8218 13:45:04.833764 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip
8220 13:45:04.887632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip>
8221 13:45:04.888311 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip
8223 13:45:04.942304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass>
8224 13:45:04.942788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass
8226 13:45:04.992373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass>
8227 13:45:04.992644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass
8229 13:45:05.033580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass>
8230 13:45:05.033828 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass
8232 13:45:05.079631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass>
8233 13:45:05.079884 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass
8235 13:45:05.124312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass>
8236 13:45:05.124568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass
8238 13:45:05.171876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass>
8239 13:45:05.172153 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass
8241 13:45:05.216948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail>
8242 13:45:05.217217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail
8244 13:45:05.261192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail>
8245 13:45:05.261466 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail
8247 13:45:05.313801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass>
8248 13:45:05.314095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass
8250 13:45:05.366465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass
8252 13:45:05.369119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass>
8253 13:45:05.423536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass>
8254 13:45:05.424227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass
8256 13:45:05.485032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass>
8257 13:45:05.485703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass
8259 13:45:05.538357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass>
8260 13:45:05.538622 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass
8262 13:45:05.594088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass>
8263 13:45:05.594421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass
8265 13:45:05.641445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass>
8266 13:45:05.641748 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass
8268 13:45:05.692522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass>
8269 13:45:05.692779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass
8271 13:45:05.742731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail>
8272 13:45:05.743222 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail
8274 13:45:05.792380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass>
8275 13:45:05.793254 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass
8277 13:45:05.859332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail>
8278 13:45:05.860048 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail
8280 13:45:05.909238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail>
8281 13:45:05.909508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail
8283 13:45:05.960523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail>
8284 13:45:05.960805 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail
8286 13:45:06.014314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass>
8287 13:45:06.014954 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass
8289 13:45:06.072216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass>
8290 13:45:06.072854 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass
8292 13:45:06.126241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail>
8293 13:45:06.126583 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail
8295 13:45:06.176372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass>
8296 13:45:06.177052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass
8298 13:45:06.236772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail>
8299 13:45:06.237558 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail
8301 13:45:06.293820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail>
8302 13:45:06.294527 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail
8304 13:45:06.353957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail>
8305 13:45:06.354600 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail
8307 13:45:06.415161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass>
8308 13:45:06.415846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass
8310 13:45:06.463764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass>
8311 13:45:06.464078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass
8313 13:45:06.511211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail>
8314 13:45:06.511843 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail
8316 13:45:06.563605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass>
8317 13:45:06.564241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass
8319 13:45:06.624567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail>
8320 13:45:06.625193 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail
8322 13:45:06.683421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail>
8323 13:45:06.684233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail
8325 13:45:06.732787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail>
8326 13:45:06.733444 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail
8328 13:45:06.784389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass>
8329 13:45:06.785173 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass
8331 13:45:06.837550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass>
8332 13:45:06.838206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass
8334 13:45:06.887726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass>
8335 13:45:06.888574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass
8337 13:45:06.936451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail>
8338 13:45:06.937120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail
8340 13:45:06.991819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass>
8341 13:45:06.992471 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass
8343 13:45:07.041958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass>
8344 13:45:07.042606 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass
8346 13:45:07.090449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass>
8347 13:45:07.091096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass
8349 13:45:07.137830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass>
8350 13:45:07.138467 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass
8352 13:45:07.190048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass>
8353 13:45:07.190701 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass
8355 13:45:07.242449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass>
8356 13:45:07.243092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass
8358 13:45:07.287017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail>
8359 13:45:07.287841 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail
8361 13:45:07.338923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass>
8362 13:45:07.339610 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass
8364 13:45:07.387489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass>
8365 13:45:07.388137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass
8367 13:45:07.434493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass>
8368 13:45:07.435239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass
8370 13:45:07.480147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass>
8371 13:45:07.480524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass
8373 13:45:07.524148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass>
8374 13:45:07.524788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass
8376 13:45:07.570010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass>
8377 13:45:07.570689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass
8379 13:45:07.615394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail>
8380 13:45:07.616025 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail
8382 13:45:07.669796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass>
8383 13:45:07.670504 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass
8385 13:45:07.716798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass>
8386 13:45:07.717064 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass
8388 13:45:07.756939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass>
8389 13:45:07.757270 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass
8391 13:45:07.798120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass>
8392 13:45:07.798764 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass
8394 13:45:07.848315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass>
8395 13:45:07.848958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass
8397 13:45:07.899104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass>
8398 13:45:07.899759 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass
8400 13:45:07.944228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail>
8401 13:45:07.944864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail
8403 13:45:07.994247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass>
8404 13:45:07.994917 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass
8406 13:45:08.038690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass>
8407 13:45:08.039080 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass
8409 13:45:08.080377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass>
8410 13:45:08.080991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass
8412 13:45:08.124262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass>
8413 13:45:08.124919 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass
8415 13:45:08.174657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass>
8416 13:45:08.175442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass
8418 13:45:08.224800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass>
8419 13:45:08.225453 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass
8421 13:45:08.271113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail>
8422 13:45:08.271751 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail
8424 13:45:08.324000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass>
8425 13:45:08.324265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass
8427 13:45:08.367483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass>
8428 13:45:08.367774 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass
8430 13:45:08.408170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass>
8431 13:45:08.408431 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass
8433 13:45:08.450279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass>
8434 13:45:08.450540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass
8436 13:45:08.490835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass>
8437 13:45:08.491095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass
8439 13:45:08.534502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass>
8440 13:45:08.534753 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass
8442 13:45:08.570145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail>
8443 13:45:08.570406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail
8445 13:45:08.609914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass>
8446 13:45:08.610200 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass
8448 13:45:08.648750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass>
8449 13:45:08.649001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass
8451 13:45:08.687823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass>
8452 13:45:08.688078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass
8454 13:45:08.727589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass>
8455 13:45:08.727846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass
8457 13:45:08.765012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass>
8458 13:45:08.765264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass
8460 13:45:08.801908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass>
8461 13:45:08.802169 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass
8463 13:45:08.837678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail>
8464 13:45:08.837935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail
8466 13:45:08.880526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass>
8467 13:45:08.880785 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass
8469 13:45:08.921564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass>
8470 13:45:08.921823 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass
8472 13:45:08.959601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass>
8473 13:45:08.960276 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass
8475 13:45:09.009667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass>
8476 13:45:09.010317 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass
8478 13:45:09.061326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass>
8479 13:45:09.061974 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass
8481 13:45:09.108342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass>
8482 13:45:09.109008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass
8484 13:45:09.152226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail>
8485 13:45:09.152894 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail
8487 13:45:09.201953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass>
8488 13:45:09.202621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass
8490 13:45:09.247536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass>
8491 13:45:09.248195 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass
8493 13:45:09.294003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass>
8494 13:45:09.294698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass
8496 13:45:09.345407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass>
8497 13:45:09.346058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass
8499 13:45:09.394275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass>
8500 13:45:09.395043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass
8502 13:45:09.445646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass>
8503 13:45:09.446352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass
8505 13:45:09.494614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail>
8506 13:45:09.495295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail
8508 13:45:09.544868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass>
8509 13:45:09.545244 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass
8511 13:45:09.597107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass>
8512 13:45:09.597867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass
8514 13:45:09.652760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass>
8515 13:45:09.653569 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass
8517 13:45:09.711615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass>
8518 13:45:09.712247 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass
8520 13:45:09.768023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass>
8521 13:45:09.768706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass
8523 13:45:09.821597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass>
8524 13:45:09.821865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass
8526 13:45:09.861137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail>
8527 13:45:09.861451 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail
8529 13:45:09.915910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass>
8530 13:45:09.916547 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass
8532 13:45:09.964834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass>
8533 13:45:09.965503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass
8535 13:45:10.010958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass>
8536 13:45:10.011602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass
8538 13:45:10.058128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass>
8539 13:45:10.058779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass
8541 13:45:10.104561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass>
8542 13:45:10.105206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass
8544 13:45:10.156074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass>
8545 13:45:10.156725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass
8547 13:45:10.201127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail>
8548 13:45:10.201815 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail
8550 13:45:10.254337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass>
8551 13:45:10.255121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass
8553 13:45:10.301693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass>
8554 13:45:10.302350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass
8556 13:45:10.355812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass>
8557 13:45:10.356472 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass
8559 13:45:10.405257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass>
8560 13:45:10.405923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass
8562 13:45:10.448077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass>
8563 13:45:10.448718 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass
8565 13:45:10.494557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass>
8566 13:45:10.495238 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass
8568 13:45:10.540774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail>
8569 13:45:10.541424 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail
8571 13:45:10.592377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass>
8572 13:45:10.593095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass
8574 13:45:10.638594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass>
8575 13:45:10.639234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass
8577 13:45:10.687298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass>
8578 13:45:10.687952 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass
8580 13:45:10.733485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass>
8581 13:45:10.734128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass
8583 13:45:10.779563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass>
8584 13:45:10.780215 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass
8586 13:45:10.822800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass>
8587 13:45:10.823446 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass
8589 13:45:10.867328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail>
8590 13:45:10.867975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail
8592 13:45:10.916478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass>
8593 13:45:10.916742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass
8595 13:45:10.953773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass>
8596 13:45:10.954031 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass
8598 13:45:10.994288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass>
8599 13:45:10.994538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass
8601 13:45:11.037274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass>
8602 13:45:11.037544 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass
8604 13:45:11.080599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass>
8605 13:45:11.080860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass
8607 13:45:11.119519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass>
8608 13:45:11.119769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass
8610 13:45:11.154990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail>
8611 13:45:11.155246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail
8613 13:45:11.199552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass>
8614 13:45:11.199815 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass
8616 13:45:11.238795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass>
8617 13:45:11.239049 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass
8619 13:45:11.279580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass>
8620 13:45:11.279836 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass
8622 13:45:11.320381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass>
8623 13:45:11.320649 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass
8625 13:45:11.362388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass>
8626 13:45:11.362671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass
8628 13:45:11.412731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass>
8629 13:45:11.413325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass
8631 13:45:11.460599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail>
8632 13:45:11.461564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail
8634 13:45:11.512737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass>
8635 13:45:11.513370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass
8637 13:45:11.562747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass>
8638 13:45:11.563392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass
8640 13:45:11.613348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass>
8641 13:45:11.613986 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass
8643 13:45:11.664574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass>
8644 13:45:11.665286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass
8646 13:45:11.721681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass>
8647 13:45:11.722320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass
8649 13:45:11.774027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass>
8650 13:45:11.774745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass
8652 13:45:11.819310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail>
8653 13:45:11.819734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail
8655 13:45:11.867858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass>
8656 13:45:11.868123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass
8658 13:45:11.920875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass>
8659 13:45:11.921558 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass
8661 13:45:11.973395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass>
8662 13:45:11.974057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass
8664 13:45:12.026139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass>
8665 13:45:12.026847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass
8667 13:45:12.076500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass>
8668 13:45:12.077216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass
8670 13:45:12.128061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass>
8671 13:45:12.128740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass
8673 13:45:12.179007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail>
8674 13:45:12.179637 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail
8676 13:45:12.235246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass>
8677 13:45:12.236118 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass
8679 13:45:12.290928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass>
8680 13:45:12.291752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass
8682 13:45:12.344857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass>
8683 13:45:12.345742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass
8685 13:45:12.395504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass>
8686 13:45:12.396273 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass
8688 13:45:12.454275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass>
8689 13:45:12.454988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass
8691 13:45:12.504296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass>
8692 13:45:12.504822 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass
8694 13:45:12.555981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail>
8695 13:45:12.556665 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail
8697 13:45:12.609687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass>
8698 13:45:12.610452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass
8700 13:45:12.662828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass>
8701 13:45:12.663652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass
8703 13:45:12.711515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass>
8704 13:45:12.712169 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass
8706 13:45:12.767491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass>
8707 13:45:12.768106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass
8709 13:45:12.819803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass>
8710 13:45:12.820492 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass
8712 13:45:12.868478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass>
8713 13:45:12.868736 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass
8715 13:45:12.917779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail>
8716 13:45:12.918753 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail
8718 13:45:12.977858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass>
8719 13:45:12.978573 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass
8721 13:45:13.026757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass>
8722 13:45:13.027047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass
8724 13:45:13.065126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass>
8725 13:45:13.065415 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass
8727 13:45:13.103392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass>
8728 13:45:13.103677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass
8730 13:45:13.145062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass>
8731 13:45:13.145332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass
8733 13:45:13.186188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass>
8734 13:45:13.186445 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass
8736 13:45:13.222057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail>
8737 13:45:13.222308 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail
8739 13:45:13.264240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass>
8740 13:45:13.264510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass
8742 13:45:13.310321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass>
8743 13:45:13.310588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass
8745 13:45:13.352979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass>
8746 13:45:13.353264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass
8748 13:45:13.395479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass>
8749 13:45:13.395786 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass
8751 13:45:13.433916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass>
8752 13:45:13.434175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass
8754 13:45:13.471259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass>
8755 13:45:13.471513 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass
8757 13:45:13.513934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail>
8758 13:45:13.514189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail
8760 13:45:13.556925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass>
8761 13:45:13.557179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass
8763 13:45:13.594467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass>
8764 13:45:13.594724 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass
8766 13:45:13.633482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass>
8767 13:45:13.633759 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass
8769 13:45:13.670844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass>
8770 13:45:13.671108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass
8772 13:45:13.708260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass>
8773 13:45:13.708523 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass
8775 13:45:13.748210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass>
8776 13:45:13.748502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass
8778 13:45:13.785329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail>
8779 13:45:13.785617 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail
8781 13:45:13.829170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass>
8782 13:45:13.829478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass
8784 13:45:13.868917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass>
8785 13:45:13.869184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass
8787 13:45:13.910484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass>
8788 13:45:13.910744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass
8790 13:45:13.950811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass>
8791 13:45:13.951088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass
8793 13:45:13.986910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass>
8794 13:45:13.987166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass
8796 13:45:14.027761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass>
8797 13:45:14.028025 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass
8799 13:45:14.064831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail>
8800 13:45:14.065085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail
8802 13:45:14.108103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass>
8803 13:45:14.108389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass
8805 13:45:14.147915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass>
8806 13:45:14.148192 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass
8808 13:45:14.187848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass>
8809 13:45:14.188124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass
8811 13:45:14.227785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass>
8812 13:45:14.228065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass
8814 13:45:14.265168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass>
8815 13:45:14.265441 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass
8817 13:45:14.299929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass>
8818 13:45:14.300207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass
8820 13:45:14.334848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail>
8821 13:45:14.335103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail
8823 13:45:14.376723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass>
8824 13:45:14.376975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass
8826 13:45:14.416482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass>
8827 13:45:14.416750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass
8829 13:45:14.455427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass>
8830 13:45:14.455682 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass
8832 13:45:14.497839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass>
8833 13:45:14.498094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass
8835 13:45:14.538106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass>
8836 13:45:14.538363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass
8838 13:45:14.578929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass>
8839 13:45:14.579199 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass
8841 13:45:14.616540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail>
8842 13:45:14.616807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail
8844 13:45:14.660942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass>
8845 13:45:14.661329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass
8847 13:45:14.710081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass>
8848 13:45:14.710359 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass
8850 13:45:14.756422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass>
8851 13:45:14.756725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass
8853 13:45:14.803089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass>
8854 13:45:14.803620 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass
8856 13:45:14.855339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass>
8857 13:45:14.856036 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass
8859 13:45:14.909165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass>
8860 13:45:14.909447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass
8862 13:45:14.954615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail>
8863 13:45:14.954903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail
8865 13:45:14.998509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass>
8866 13:45:14.998767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass
8868 13:45:15.042500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass>
8869 13:45:15.042762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass
8871 13:45:15.085211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass>
8872 13:45:15.085474 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass
8874 13:45:15.129098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass>
8875 13:45:15.129379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass
8877 13:45:15.176694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass>
8878 13:45:15.177384 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass
8880 13:45:15.225427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass>
8881 13:45:15.225781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass
8883 13:45:15.273199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail>
8884 13:45:15.273468 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail
8886 13:45:15.324979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass>
8887 13:45:15.325237 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass
8889 13:45:15.374644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass>
8890 13:45:15.375068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass
8892 13:45:15.426740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass>
8893 13:45:15.427518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass
8895 13:45:15.479637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass>
8896 13:45:15.480304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass
8898 13:45:15.539544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass>
8899 13:45:15.540191 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass
8901 13:45:15.592314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass>
8902 13:45:15.593005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass
8904 13:45:15.644098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail>
8905 13:45:15.644747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail
8907 13:45:15.709350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass>
8908 13:45:15.710062 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass
8910 13:45:15.766791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass>
8911 13:45:15.767524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass
8913 13:45:15.822579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass>
8914 13:45:15.823282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass
8916 13:45:15.874400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass>
8917 13:45:15.875089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass
8919 13:45:15.925529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass>
8920 13:45:15.926252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass
8922 13:45:15.982432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass>
8923 13:45:15.983105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass
8925 13:45:16.034430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail>
8926 13:45:16.035210 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail
8928 13:45:16.092174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass>
8929 13:45:16.092967 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass
8931 13:45:16.146058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass>
8932 13:45:16.146745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass
8934 13:45:16.202059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass>
8935 13:45:16.202771 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass
8937 13:45:16.257809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass>
8938 13:45:16.258566 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass
8940 13:45:16.312699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass>
8941 13:45:16.313528 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass
8943 13:45:16.363621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass>
8944 13:45:16.363927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass
8946 13:45:16.408223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail>
8947 13:45:16.408486 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail
8949 13:45:16.456169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass>
8950 13:45:16.456815 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass
8952 13:45:16.511170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass>
8953 13:45:16.511853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass
8955 13:45:16.565505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass>
8956 13:45:16.566169 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass
8958 13:45:16.618000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass>
8959 13:45:16.618735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass
8961 13:45:16.671831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass>
8962 13:45:16.672512 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass
8964 13:45:16.724025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass>
8965 13:45:16.724793 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass
8967 13:45:16.776105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail>
8968 13:45:16.776964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail
8970 13:45:16.835731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass>
8971 13:45:16.836606 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass
8973 13:45:16.891112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass>
8974 13:45:16.891852 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass
8976 13:45:16.947872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass>
8977 13:45:16.948608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass
8979 13:45:16.992373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass>
8980 13:45:16.993202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass
8982 13:45:17.048555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass>
8983 13:45:17.049332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass
8985 13:45:17.101966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass>
8986 13:45:17.102874 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass
8988 13:45:17.154733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail>
8989 13:45:17.155362 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail
8991 13:45:17.216571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass>
8992 13:45:17.217288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass
8994 13:45:17.265775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass>
8995 13:45:17.266032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass
8997 13:45:17.310952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass>
8998 13:45:17.311582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass
9000 13:45:17.365179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass>
9001 13:45:17.365898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass
9003 13:45:17.412958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass>
9004 13:45:17.413232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass
9006 13:45:17.458382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass>
9007 13:45:17.458641 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass
9009 13:45:17.498471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail>
9010 13:45:17.498720 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail
9012 13:45:17.546147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass>
9013 13:45:17.546498 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass
9015 13:45:17.593905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass>
9016 13:45:17.594154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass
9018 13:45:17.639704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass>
9019 13:45:17.639959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass
9021 13:45:17.681181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass>
9022 13:45:17.681454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass
9024 13:45:17.726548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass>
9025 13:45:17.727172 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass
9027 13:45:17.781163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass>
9028 13:45:17.781876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass
9030 13:45:17.834827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail>
9031 13:45:17.835661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail
9033 13:45:17.881865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass>
9034 13:45:17.882124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass
9036 13:45:17.930352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass>
9037 13:45:17.930622 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass
9039 13:45:17.973659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass>
9040 13:45:17.973923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass
9042 13:45:18.012055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass>
9043 13:45:18.012320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass
9045 13:45:18.062417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass>
9046 13:45:18.062752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass
9048 13:45:18.112058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass>
9049 13:45:18.112415 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass
9051 13:45:18.160116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail>
9052 13:45:18.160851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail
9054 13:45:18.215034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass>
9055 13:45:18.215698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass
9057 13:45:18.274611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass>
9058 13:45:18.275279 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass
9060 13:45:18.334909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass>
9061 13:45:18.335646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass
9063 13:45:18.390720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass>
9064 13:45:18.391369 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass
9066 13:45:18.451501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass>
9067 13:45:18.452133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass
9069 13:45:18.510382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass>
9070 13:45:18.511034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass
9072 13:45:18.559403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail>
9073 13:45:18.560118 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail
9075 13:45:18.615305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass>
9076 13:45:18.616233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass
9078 13:45:18.665827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass>
9079 13:45:18.666462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass
9081 13:45:18.717159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass>
9082 13:45:18.717917 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass
9084 13:45:18.769189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass>
9085 13:45:18.769888 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass
9087 13:45:18.812257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass>
9088 13:45:18.812516 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass
9090 13:45:18.853698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass>
9091 13:45:18.853958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass
9093 13:45:18.889852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail>
9094 13:45:18.890135 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail
9096 13:45:18.932461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass>
9097 13:45:18.932747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass
9099 13:45:18.972796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass>
9100 13:45:18.973048 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass
9102 13:45:19.013115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass>
9103 13:45:19.013438 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass
9105 13:45:19.050542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass>
9106 13:45:19.050854 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass
9108 13:45:19.088489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass>
9109 13:45:19.088741 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass
9111 13:45:19.129507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass>
9112 13:45:19.129771 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass
9114 13:45:19.163640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail>
9115 13:45:19.163892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail
9117 13:45:19.210189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass>
9118 13:45:19.210442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass
9120 13:45:19.246822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass>
9121 13:45:19.247075 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass
9123 13:45:19.285708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass>
9124 13:45:19.285961 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass
9126 13:45:19.328574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass>
9127 13:45:19.328868 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass
9129 13:45:19.368385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass>
9130 13:45:19.368673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass
9132 13:45:19.406302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass>
9133 13:45:19.406585 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass
9135 13:45:19.441830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail>
9136 13:45:19.442114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail
9138 13:45:19.481209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass>
9139 13:45:19.481513 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass
9141 13:45:19.520825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass>
9142 13:45:19.521105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass
9144 13:45:19.562770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass>
9145 13:45:19.563027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass
9147 13:45:19.604443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass>
9148 13:45:19.604708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass
9150 13:45:19.646142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass>
9151 13:45:19.646431 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass
9153 13:45:19.686912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass>
9154 13:45:19.687166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass
9156 13:45:19.724701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail>
9157 13:45:19.724981 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail
9159 13:45:19.766775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass>
9160 13:45:19.767032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass
9162 13:45:19.805508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass>
9163 13:45:19.805765 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass
9165 13:45:19.842536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass>
9166 13:45:19.842796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass
9168 13:45:19.879119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass>
9169 13:45:19.879371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass
9171 13:45:19.921246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass>
9172 13:45:19.921509 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass
9174 13:45:19.961262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass>
9175 13:45:19.961520 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass
9177 13:45:19.998134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail>
9178 13:45:19.998389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail
9180 13:45:20.041370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass>
9181 13:45:20.041634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass
9183 13:45:20.081318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass>
9184 13:45:20.081572 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass
9186 13:45:20.120781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass>
9187 13:45:20.121034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass
9189 13:45:20.160310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass>
9190 13:45:20.160565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass
9192 13:45:20.196402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass>
9193 13:45:20.196648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass
9195 13:45:20.233880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass>
9196 13:45:20.234136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass
9198 13:45:20.268510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail>
9199 13:45:20.268762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail
9201 13:45:20.310173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass>
9202 13:45:20.310424 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass
9204 13:45:20.346564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass>
9205 13:45:20.346825 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass
9207 13:45:20.385723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass>
9208 13:45:20.385979 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass
9210 13:45:20.423147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass>
9211 13:45:20.423430 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass
9213 13:45:20.460748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass>
9214 13:45:20.461034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass
9216 13:45:20.499217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass>
9217 13:45:20.499475 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass
9219 13:45:20.537640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail>
9220 13:45:20.537900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail
9222 13:45:20.587826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass>
9223 13:45:20.588086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass
9225 13:45:20.629499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass>
9226 13:45:20.629753 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass
9228 13:45:20.665653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass>
9229 13:45:20.665930 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass
9231 13:45:20.704457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass>
9232 13:45:20.704707 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass
9234 13:45:20.743044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass>
9235 13:45:20.743302 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass
9237 13:45:20.782423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass>
9238 13:45:20.782673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass
9240 13:45:20.823689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail>
9241 13:45:20.823942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail
9243 13:45:20.863223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass>
9244 13:45:20.863477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass
9246 13:45:20.905152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass>
9247 13:45:20.905462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass
9249 13:45:20.945735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass>
9250 13:45:20.945997 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass
9252 13:45:20.984547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass>
9253 13:45:20.984816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass
9255 13:45:21.026445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass>
9256 13:45:21.026703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass
9258 13:45:21.068964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass>
9259 13:45:21.069233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass
9261 13:45:21.105562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail>
9262 13:45:21.105819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail
9264 13:45:21.149174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass>
9265 13:45:21.149453 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass
9267 13:45:21.187961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass>
9268 13:45:21.188238 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass
9270 13:45:21.228710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass>
9271 13:45:21.228962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass
9273 13:45:21.267931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass>
9274 13:45:21.268212 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass
9276 13:45:21.306017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass>
9277 13:45:21.306273 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass
9279 13:45:21.344857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass>
9280 13:45:21.345138 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass
9282 13:45:21.384913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail>
9283 13:45:21.385168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail
9285 13:45:21.430150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass>
9286 13:45:21.430407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass
9288 13:45:21.468862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass>
9289 13:45:21.469142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass
9291 13:45:21.508572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass>
9292 13:45:21.508830 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass
9294 13:45:21.552385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass>
9295 13:45:21.552673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass
9297 13:45:21.592746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass>
9298 13:45:21.593019 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass
9300 13:45:21.627122 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass
9302 13:45:21.630230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass>
9303 13:45:21.666787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail>
9304 13:45:21.667055 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail
9306 13:45:21.708746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass>
9307 13:45:21.709030 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass
9309 13:45:21.748390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass>
9310 13:45:21.748653 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass
9312 13:45:21.788524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass>
9313 13:45:21.788779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass
9315 13:45:21.832988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass>
9316 13:45:21.833282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass
9318 13:45:21.873697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass>
9319 13:45:21.873948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass
9321 13:45:21.916993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass>
9322 13:45:21.917266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass
9324 13:45:21.954112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass>
9325 13:45:21.954400 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass
9327 13:45:21.995815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass>
9328 13:45:21.996064 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass
9330 13:45:22.038259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass>
9331 13:45:22.038534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass
9333 13:45:22.074595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass>
9334 13:45:22.074872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass
9336 13:45:22.112866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass>
9337 13:45:22.113114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass
9339 13:45:22.152653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass>
9340 13:45:22.152945 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass
9342 13:45:22.191425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass>
9343 13:45:22.191700 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass
9345 13:45:22.225811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass>
9346 13:45:22.226068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass
9348 13:45:22.266591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass>
9349 13:45:22.266851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass
9351 13:45:22.303624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass>
9352 13:45:22.303901 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass
9354 13:45:22.339317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass>
9355 13:45:22.339590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass
9357 13:45:22.375163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass>
9358 13:45:22.375412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass
9360 13:45:22.410417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass>
9361 13:45:22.410667 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass
9363 13:45:22.445743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass>
9364 13:45:22.446016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass
9366 13:45:22.479288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass>
9367 13:45:22.479566 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass
9369 13:45:22.518272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass>
9370 13:45:22.518552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass
9372 13:45:22.558817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass>
9373 13:45:22.559090 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass
9375 13:45:22.596084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass>
9376 13:45:22.596330 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass
9378 13:45:22.634569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass>
9379 13:45:22.634844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass
9381 13:45:22.676580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass>
9382 13:45:22.676834 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass
9384 13:45:22.720265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass>
9385 13:45:22.720535 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass
9387 13:45:22.755639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass>
9388 13:45:22.755925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass
9390 13:45:22.797470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass>
9391 13:45:22.797752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass
9393 13:45:22.838229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass>
9394 13:45:22.838491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass
9396 13:45:22.875734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass>
9397 13:45:22.876010 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass
9399 13:45:22.916114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass>
9400 13:45:22.916370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass
9402 13:45:22.955003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass>
9403 13:45:22.955260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass
9405 13:45:22.994493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass>
9406 13:45:22.994746 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass
9408 13:45:23.029202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass>
9409 13:45:23.029464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass
9411 13:45:23.072002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass>
9412 13:45:23.072296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass
9414 13:45:23.113163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass>
9415 13:45:23.113482 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass
9417 13:45:23.151408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass>
9418 13:45:23.151664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass
9420 13:45:23.192771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass>
9421 13:45:23.193029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass
9423 13:45:23.235548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass>
9424 13:45:23.235807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass
9426 13:45:23.274357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass>
9427 13:45:23.274612 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass
9429 13:45:23.312965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass>
9430 13:45:23.313222 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass
9432 13:45:23.354437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass>
9433 13:45:23.354686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass
9435 13:45:23.392360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass>
9436 13:45:23.392614 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass
9438 13:45:23.429601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass>
9439 13:45:23.429859 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass
9441 13:45:23.468613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass>
9442 13:45:23.468867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass
9444 13:45:23.510028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass>
9445 13:45:23.510297 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass
9447 13:45:23.554122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass>
9448 13:45:23.554391 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass
9450 13:45:23.590200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass>
9451 13:45:23.590455 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass
9453 13:45:23.632051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass>
9454 13:45:23.632313 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass
9456 13:45:23.673084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass>
9457 13:45:23.673359 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass
9459 13:45:23.713614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass>
9460 13:45:23.713872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass
9462 13:45:23.752529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass>
9463 13:45:23.752782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass
9465 13:45:23.791232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass>
9466 13:45:23.791490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass
9468 13:45:23.829832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass>
9469 13:45:23.830103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass
9471 13:45:23.865808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass>
9472 13:45:23.866151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass
9474 13:45:23.906735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass>
9475 13:45:23.906995 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass
9477 13:45:23.944959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass>
9478 13:45:23.945220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass
9480 13:45:23.983358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass>
9481 13:45:23.983619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass
9483 13:45:24.022236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass>
9484 13:45:24.022494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass
9486 13:45:24.064188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass>
9487 13:45:24.064453 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass
9489 13:45:24.112684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass>
9490 13:45:24.112960 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass
9492 13:45:24.148040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail>
9493 13:45:24.148308 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail
9495 13:45:24.189528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass>
9496 13:45:24.189792 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass
9498 13:45:24.230153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass>
9499 13:45:24.230411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass
9501 13:45:24.270169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass>
9502 13:45:24.270423 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass
9504 13:45:24.308892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass>
9505 13:45:24.309147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass
9507 13:45:24.346319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass>
9508 13:45:24.346577 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass
9510 13:45:24.385542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass>
9511 13:45:24.385797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass
9513 13:45:24.417675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail>
9514 13:45:24.417953 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail
9516 13:45:24.466811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass>
9517 13:45:24.467069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass
9519 13:45:24.508287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass>
9520 13:45:24.508543 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass
9522 13:45:24.552955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass>
9523 13:45:24.553216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass
9525 13:45:24.593782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass>
9526 13:45:24.594042 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass
9528 13:45:24.635958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass>
9529 13:45:24.636222 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass
9531 13:45:24.676760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass>
9532 13:45:24.677021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass
9534 13:45:24.716611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail>
9535 13:45:24.716873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail
9537 13:45:24.760695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass>
9538 13:45:24.760952 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass
9540 13:45:24.803818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass>
9541 13:45:24.804075 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass
9543 13:45:24.844869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass>
9544 13:45:24.845138 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass
9546 13:45:24.884006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass>
9547 13:45:24.884298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass
9549 13:45:24.923413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass>
9550 13:45:24.923713 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass
9552 13:45:24.962220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass>
9553 13:45:24.962485 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass
9555 13:45:24.996030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail>
9556 13:45:24.996285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail
9558 13:45:25.037415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass>
9559 13:45:25.037712 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass
9561 13:45:25.077972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass>
9562 13:45:25.078239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass
9564 13:45:25.114723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass>
9565 13:45:25.115001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass
9567 13:45:25.155862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass>
9568 13:45:25.156163 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass
9570 13:45:25.195766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass>
9571 13:45:25.196057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass
9573 13:45:25.237385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass>
9574 13:45:25.237666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass
9576 13:45:25.271256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail>
9577 13:45:25.271505 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail
9579 13:45:25.314995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass>
9580 13:45:25.315293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass
9582 13:45:25.360883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass>
9583 13:45:25.361690 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass
9585 13:45:25.410101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass>
9586 13:45:25.410806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass
9588 13:45:25.457035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass>
9589 13:45:25.457804 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass
9591 13:45:25.507146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass>
9592 13:45:25.507787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass
9594 13:45:25.555908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass>
9595 13:45:25.556573 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass
9597 13:45:25.599923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail>
9598 13:45:25.600694 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail
9600 13:45:25.647520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass>
9601 13:45:25.648328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass
9603 13:45:25.694408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass>
9604 13:45:25.695114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass
9606 13:45:25.745147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass>
9607 13:45:25.745857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass
9609 13:45:25.793576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass>
9610 13:45:25.794228 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass
9612 13:45:25.842536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass>
9613 13:45:25.843225 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass
9615 13:45:25.889508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass>
9616 13:45:25.890162 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass
9618 13:45:25.933969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail>
9619 13:45:25.934624 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail
9621 13:45:25.988437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass>
9622 13:45:25.989096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass
9624 13:45:26.038878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass>
9625 13:45:26.039526 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass
9627 13:45:26.090427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass>
9628 13:45:26.091073 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass
9630 13:45:26.144234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass>
9631 13:45:26.144909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass
9633 13:45:26.195182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass>
9634 13:45:26.195990 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass
9636 13:45:26.246412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass>
9637 13:45:26.247399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass
9639 13:45:26.289731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail>
9640 13:45:26.290362 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail
9642 13:45:26.341142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass>
9643 13:45:26.341838 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass
9645 13:45:26.386987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass>
9646 13:45:26.387618 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass
9648 13:45:26.436112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass>
9649 13:45:26.436942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass
9651 13:45:26.489844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass>
9652 13:45:26.490490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass
9654 13:45:26.535173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass>
9655 13:45:26.536069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass
9657 13:45:26.580326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass>
9658 13:45:26.581016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass
9660 13:45:26.621368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail>
9661 13:45:26.622022 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail
9663 13:45:26.671464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass>
9664 13:45:26.672146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass
9666 13:45:26.718946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass>
9667 13:45:26.719812 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass
9669 13:45:26.768049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass>
9670 13:45:26.768696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass
9672 13:45:26.818863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass>
9673 13:45:26.819754 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass
9675 13:45:26.868180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass>
9676 13:45:26.868823 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass
9678 13:45:26.916576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass>
9679 13:45:26.917326 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass
9681 13:45:26.961188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail>
9682 13:45:26.961935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail
9684 13:45:27.015774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass>
9685 13:45:27.016679 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass
9687 13:45:27.064445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass>
9688 13:45:27.065090 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass
9690 13:45:27.116531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass>
9691 13:45:27.117207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass
9693 13:45:27.165866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass>
9694 13:45:27.166523 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass
9696 13:45:27.214670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass>
9697 13:45:27.214927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass
9699 13:45:27.255363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass>
9700 13:45:27.255630 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass
9702 13:45:27.289287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail>
9703 13:45:27.289560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail
9705 13:45:27.329751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass>
9706 13:45:27.330008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass
9708 13:45:27.369801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass>
9709 13:45:27.370088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass
9711 13:45:27.411257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass>
9712 13:45:27.411537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass
9714 13:45:27.453198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass>
9715 13:45:27.453479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass
9717 13:45:27.496576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass>
9718 13:45:27.496831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass
9720 13:45:27.533061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass>
9721 13:45:27.533321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass
9723 13:45:27.569042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail>
9724 13:45:27.569297 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail
9726 13:45:27.614905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass>
9727 13:45:27.615167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass
9729 13:45:27.655108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass>
9730 13:45:27.655369 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass
9732 13:45:27.693046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass>
9733 13:45:27.693298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass
9735 13:45:27.734138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass>
9736 13:45:27.734396 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass
9738 13:45:27.777087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass>
9739 13:45:27.777345 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass
9741 13:45:27.821444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass>
9742 13:45:27.821697 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass
9744 13:45:27.861190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail>
9745 13:45:27.861500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail
9747 13:45:27.904088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass>
9748 13:45:27.904337 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass
9750 13:45:27.945060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass>
9751 13:45:27.945353 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass
9753 13:45:27.985889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass>
9754 13:45:27.986142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass
9756 13:45:28.026077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass>
9757 13:45:28.026332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass
9759 13:45:28.063895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass>
9760 13:45:28.064149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass
9762 13:45:28.105806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass>
9763 13:45:28.106059 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass
9765 13:45:28.143140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail>
9766 13:45:28.143398 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail
9768 13:45:28.185472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass>
9769 13:45:28.185742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass
9771 13:45:28.225693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass>
9772 13:45:28.225944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass
9774 13:45:28.264850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass>
9775 13:45:28.265131 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass
9777 13:45:28.304427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass>
9778 13:45:28.304703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass
9780 13:45:28.344957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass>
9781 13:45:28.345260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass
9783 13:45:28.385738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass>
9784 13:45:28.386005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass
9786 13:45:28.418808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail>
9787 13:45:28.419065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail
9789 13:45:28.466290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass>
9790 13:45:28.466564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass
9792 13:45:28.506233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass>
9793 13:45:28.506553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass
9795 13:45:28.552192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass>
9796 13:45:28.552900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass
9798 13:45:28.599493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass>
9799 13:45:28.600145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass
9801 13:45:28.649491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass>
9802 13:45:28.650158 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass
9804 13:45:28.689994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass
9806 13:45:28.693418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass>
9807 13:45:28.736102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail>
9808 13:45:28.736547 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail
9810 13:45:28.786766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass>
9811 13:45:28.787028 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass
9813 13:45:28.824734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass>
9814 13:45:28.824990 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass
9816 13:45:28.864281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass>
9817 13:45:28.864544 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass
9819 13:45:28.902770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass>
9820 13:45:28.903024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass
9822 13:45:28.945867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass>
9823 13:45:28.946133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass
9825 13:45:28.986738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass>
9826 13:45:28.986991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass
9828 13:45:29.027884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass>
9829 13:45:29.028160 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass
9831 13:45:29.076315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass>
9832 13:45:29.076579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass
9834 13:45:29.114433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass>
9835 13:45:29.114686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass
9837 13:45:29.153021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass>
9838 13:45:29.153306 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass
9840 13:45:29.195797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail>
9841 13:45:29.196078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail
9843 13:45:29.237640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass>
9844 13:45:29.237897 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass
9846 13:45:29.274162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass>
9847 13:45:29.274416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass
9849 13:45:29.312340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass>
9850 13:45:29.312595 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass
9852 13:45:29.354253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass>
9853 13:45:29.354527 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass
9855 13:45:29.392957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass>
9856 13:45:29.393213 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass
9858 13:45:29.432734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass>
9859 13:45:29.432992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass
9861 13:45:29.471685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail>
9862 13:45:29.471939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail
9864 13:45:29.512215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass>
9865 13:45:29.512491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass
9867 13:45:29.553464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass>
9868 13:45:29.553740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass
9870 13:45:29.588241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass>
9871 13:45:29.588501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass
9873 13:45:29.627782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass>
9874 13:45:29.628041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass
9876 13:45:29.668606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass>
9877 13:45:29.668865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass
9879 13:45:29.701067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass>
9880 13:45:29.701351 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass
9882 13:45:29.738093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail>
9883 13:45:29.738350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail
9885 13:45:29.777923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass>
9886 13:45:29.778180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass
9888 13:45:29.818609 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass
9890 13:45:29.821548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass>
9891 13:45:29.856630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass>
9892 13:45:29.856887 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass
9894 13:45:29.898219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass>
9895 13:45:29.898472 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass
9897 13:45:29.942173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass>
9898 13:45:29.942433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass
9900 13:45:29.980019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass>
9901 13:45:29.980272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass
9903 13:45:30.014398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail>
9904 13:45:30.014654 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail
9906 13:45:30.050732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass>
9907 13:45:30.050991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass
9909 13:45:30.084461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass
9911 13:45:30.087854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass>
9912 13:45:30.122678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass>
9913 13:45:30.122956 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass
9915 13:45:30.167122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass>
9916 13:45:30.167409 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass
9918 13:45:30.206583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass>
9919 13:45:30.206840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass
9921 13:45:30.243870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass>
9922 13:45:30.244121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass
9924 13:45:30.280495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail>
9925 13:45:30.280750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail
9927 13:45:30.316676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass>
9928 13:45:30.316926 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass
9930 13:45:30.356217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass>
9931 13:45:30.356477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass
9933 13:45:30.395343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass>
9934 13:45:30.395611 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass
9936 13:45:30.435272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass>
9937 13:45:30.435532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass
9939 13:45:30.472698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass>
9940 13:45:30.472953 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass
9942 13:45:30.511129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass>
9943 13:45:30.511409 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass
9945 13:45:30.551216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail>
9946 13:45:30.551472 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail
9948 13:45:30.592246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass>
9949 13:45:30.592510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass
9951 13:45:30.628046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
9952 13:45:30.628136 + set +x
9953 13:45:30.628364 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
9955 13:45:30.634887 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14879038_1.6.2.3.5>
9956 13:45:30.635131 Received signal: <ENDRUN> 1_kselftest-alsa 14879038_1.6.2.3.5
9957 13:45:30.635202 Ending use of test pattern.
9958 13:45:30.635258 Ending test lava.1_kselftest-alsa (14879038_1.6.2.3.5), duration 45.78
9960 13:45:30.637695 <LAVA_TEST_RUNNER EXIT>
9961 13:45:30.637936 ok: lava_test_shell seems to have completed
9962 13:45:30.640853 shardfile-alsa: pass
alsa_mixer-test_get_value_0_93: pass
alsa_mixer-test_name_0_93: pass
alsa_mixer-test_write_default_0_93: pass
alsa_mixer-test_write_valid_0_93: pass
alsa_mixer-test_write_invalid_0_93: pass
alsa_mixer-test_event_missing_0_93: pass
alsa_mixer-test_event_spurious_0_93: pass
alsa_mixer-test_get_value_0_92: pass
alsa_mixer-test_name_0_92: pass
alsa_mixer-test_write_default_0_92: pass
alsa_mixer-test_write_valid_0_92: pass
alsa_mixer-test_write_invalid_0_92: pass
alsa_mixer-test_event_missing_0_92: pass
alsa_mixer-test_event_spurious_0_92: pass
alsa_mixer-test_get_value_0_91: pass
alsa_mixer-test_name_0_91: pass
alsa_mixer-test_write_default_0_91: pass
alsa_mixer-test_write_valid_0_91: pass
alsa_mixer-test_write_invalid_0_91: pass
alsa_mixer-test_event_missing_0_91: pass
alsa_mixer-test_event_spurious_0_91: pass
alsa_mixer-test_get_value_0_90: pass
alsa_mixer-test_name_0_90: pass
alsa_mixer-test_write_default_0_90: pass
alsa_mixer-test_write_valid_0_90: pass
alsa_mixer-test_write_invalid_0_90: pass
alsa_mixer-test_event_missing_0_90: pass
alsa_mixer-test_event_spurious_0_90: pass
alsa_mixer-test_get_value_0_89: pass
alsa_mixer-test_name_0_89: pass
alsa_mixer-test_write_default_0_89: pass
alsa_mixer-test_write_valid_0_89: pass
alsa_mixer-test_write_invalid_0_89: pass
alsa_mixer-test_event_missing_0_89: pass
alsa_mixer-test_event_spurious_0_89: pass
alsa_mixer-test_get_value_0_88: pass
alsa_mixer-test_name_0_88: pass
alsa_mixer-test_write_default_0_88: pass
alsa_mixer-test_write_valid_0_88: fail
alsa_mixer-test_write_invalid_0_88: pass
alsa_mixer-test_event_missing_0_88: pass
alsa_mixer-test_event_spurious_0_88: fail
alsa_mixer-test_get_value_0_87: pass
alsa_mixer-test_name_0_87: pass
alsa_mixer-test_write_default_0_87: pass
alsa_mixer-test_write_valid_0_87: pass
alsa_mixer-test_write_invalid_0_87: pass
alsa_mixer-test_event_missing_0_87: pass
alsa_mixer-test_event_spurious_0_87: pass
alsa_mixer-test_get_value_0_86: pass
alsa_mixer-test_name_0_86: pass
alsa_mixer-test_write_default_0_86: pass
alsa_mixer-test_write_valid_0_86: fail
alsa_mixer-test_write_invalid_0_86: pass
alsa_mixer-test_event_missing_0_86: pass
alsa_mixer-test_event_spurious_0_86: pass
alsa_mixer-test_get_value_0_85: pass
alsa_mixer-test_name_0_85: pass
alsa_mixer-test_write_default_0_85: pass
alsa_mixer-test_write_valid_0_85: fail
alsa_mixer-test_write_invalid_0_85: pass
alsa_mixer-test_event_missing_0_85: pass
alsa_mixer-test_event_spurious_0_85: pass
alsa_mixer-test_get_value_0_84: pass
alsa_mixer-test_name_0_84: pass
alsa_mixer-test_write_default_0_84: pass
alsa_mixer-test_write_valid_0_84: pass
alsa_mixer-test_write_invalid_0_84: pass
alsa_mixer-test_event_missing_0_84: pass
alsa_mixer-test_event_spurious_0_84: pass
alsa_mixer-test_get_value_0_83: pass
alsa_mixer-test_name_0_83: pass
alsa_mixer-test_write_default_0_83: pass
alsa_mixer-test_write_valid_0_83: pass
alsa_mixer-test_write_invalid_0_83: pass
alsa_mixer-test_event_missing_0_83: pass
alsa_mixer-test_event_spurious_0_83: pass
alsa_mixer-test_get_value_0_82: pass
alsa_mixer-test_name_0_82: pass
alsa_mixer-test_write_default_0_82: skip
alsa_mixer-test_write_valid_0_82: skip
alsa_mixer-test_write_invalid_0_82: skip
alsa_mixer-test_event_missing_0_82: pass
alsa_mixer-test_event_spurious_0_82: pass
alsa_mixer-test_get_value_0_81: pass
alsa_mixer-test_name_0_81: pass
alsa_mixer-test_write_default_0_81: pass
alsa_mixer-test_write_valid_0_81: pass
alsa_mixer-test_write_invalid_0_81: fail
alsa_mixer-test_event_missing_0_81: fail
alsa_mixer-test_event_spurious_0_81: pass
alsa_mixer-test_get_value_0_80: pass
alsa_mixer-test_name_0_80: pass
alsa_mixer-test_write_default_0_80: pass
alsa_mixer-test_write_valid_0_80: pass
alsa_mixer-test_write_invalid_0_80: pass
alsa_mixer-test_event_missing_0_80: pass
alsa_mixer-test_event_spurious_0_80: pass
alsa_mixer-test_get_value_0_79: fail
alsa_mixer-test_name_0_79: pass
alsa_mixer-test_write_default_0_79: fail
alsa_mixer-test_write_valid_0_79: fail
alsa_mixer-test_write_invalid_0_79: fail
alsa_mixer-test_event_missing_0_79: pass
alsa_mixer-test_event_spurious_0_79: pass
alsa_mixer-test_get_value_0_78: fail
alsa_mixer-test_name_0_78: pass
alsa_mixer-test_write_default_0_78: fail
alsa_mixer-test_write_valid_0_78: fail
alsa_mixer-test_write_invalid_0_78: fail
alsa_mixer-test_event_missing_0_78: pass
alsa_mixer-test_event_spurious_0_78: pass
alsa_mixer-test_get_value_0_77: fail
alsa_mixer-test_name_0_77: pass
alsa_mixer-test_write_default_0_77: fail
alsa_mixer-test_write_valid_0_77: fail
alsa_mixer-test_write_invalid_0_77: fail
alsa_mixer-test_event_missing_0_77: pass
alsa_mixer-test_event_spurious_0_77: pass
alsa_mixer-test_get_value_0_76: pass
alsa_mixer-test_name_0_76: fail
alsa_mixer-test_write_default_0_76: pass
alsa_mixer-test_write_valid_0_76: pass
alsa_mixer-test_write_invalid_0_76: pass
alsa_mixer-test_event_missing_0_76: pass
alsa_mixer-test_event_spurious_0_76: pass
alsa_mixer-test_get_value_0_75: pass
alsa_mixer-test_name_0_75: fail
alsa_mixer-test_write_default_0_75: pass
alsa_mixer-test_write_valid_0_75: pass
alsa_mixer-test_write_invalid_0_75: pass
alsa_mixer-test_event_missing_0_75: pass
alsa_mixer-test_event_spurious_0_75: pass
alsa_mixer-test_get_value_0_74: pass
alsa_mixer-test_name_0_74: fail
alsa_mixer-test_write_default_0_74: pass
alsa_mixer-test_write_valid_0_74: pass
alsa_mixer-test_write_invalid_0_74: pass
alsa_mixer-test_event_missing_0_74: pass
alsa_mixer-test_event_spurious_0_74: pass
alsa_mixer-test_get_value_0_73: pass
alsa_mixer-test_name_0_73: fail
alsa_mixer-test_write_default_0_73: pass
alsa_mixer-test_write_valid_0_73: pass
alsa_mixer-test_write_invalid_0_73: pass
alsa_mixer-test_event_missing_0_73: pass
alsa_mixer-test_event_spurious_0_73: pass
alsa_mixer-test_get_value_0_72: pass
alsa_mixer-test_name_0_72: fail
alsa_mixer-test_write_default_0_72: pass
alsa_mixer-test_write_valid_0_72: pass
alsa_mixer-test_write_invalid_0_72: pass
alsa_mixer-test_event_missing_0_72: pass
alsa_mixer-test_event_spurious_0_72: pass
alsa_mixer-test_get_value_0_71: pass
alsa_mixer-test_name_0_71: fail
alsa_mixer-test_write_default_0_71: pass
alsa_mixer-test_write_valid_0_71: pass
alsa_mixer-test_write_invalid_0_71: pass
alsa_mixer-test_event_missing_0_71: pass
alsa_mixer-test_event_spurious_0_71: pass
alsa_mixer-test_get_value_0_70: pass
alsa_mixer-test_name_0_70: fail
alsa_mixer-test_write_default_0_70: pass
alsa_mixer-test_write_valid_0_70: pass
alsa_mixer-test_write_invalid_0_70: pass
alsa_mixer-test_event_missing_0_70: pass
alsa_mixer-test_event_spurious_0_70: pass
alsa_mixer-test_get_value_0_69: pass
alsa_mixer-test_name_0_69: fail
alsa_mixer-test_write_default_0_69: pass
alsa_mixer-test_write_valid_0_69: pass
alsa_mixer-test_write_invalid_0_69: pass
alsa_mixer-test_event_missing_0_69: pass
alsa_mixer-test_event_spurious_0_69: pass
alsa_mixer-test_get_value_0_68: pass
alsa_mixer-test_name_0_68: fail
alsa_mixer-test_write_default_0_68: pass
alsa_mixer-test_write_valid_0_68: pass
alsa_mixer-test_write_invalid_0_68: pass
alsa_mixer-test_event_missing_0_68: pass
alsa_mixer-test_event_spurious_0_68: pass
alsa_mixer-test_get_value_0_67: pass
alsa_mixer-test_name_0_67: fail
alsa_mixer-test_write_default_0_67: pass
alsa_mixer-test_write_valid_0_67: pass
alsa_mixer-test_write_invalid_0_67: pass
alsa_mixer-test_event_missing_0_67: pass
alsa_mixer-test_event_spurious_0_67: pass
alsa_mixer-test_get_value_0_66: pass
alsa_mixer-test_name_0_66: fail
alsa_mixer-test_write_default_0_66: pass
alsa_mixer-test_write_valid_0_66: pass
alsa_mixer-test_write_invalid_0_66: pass
alsa_mixer-test_event_missing_0_66: pass
alsa_mixer-test_event_spurious_0_66: pass
alsa_mixer-test_get_value_0_65: pass
alsa_mixer-test_name_0_65: fail
alsa_mixer-test_write_default_0_65: pass
alsa_mixer-test_write_valid_0_65: pass
alsa_mixer-test_write_invalid_0_65: pass
alsa_mixer-test_event_missing_0_65: pass
alsa_mixer-test_event_spurious_0_65: pass
alsa_mixer-test_get_value_0_64: pass
alsa_mixer-test_name_0_64: fail
alsa_mixer-test_write_default_0_64: pass
alsa_mixer-test_write_valid_0_64: pass
alsa_mixer-test_write_invalid_0_64: pass
alsa_mixer-test_event_missing_0_64: pass
alsa_mixer-test_event_spurious_0_64: pass
alsa_mixer-test_get_value_0_63: pass
alsa_mixer-test_name_0_63: fail
alsa_mixer-test_write_default_0_63: pass
alsa_mixer-test_write_valid_0_63: pass
alsa_mixer-test_write_invalid_0_63: pass
alsa_mixer-test_event_missing_0_63: pass
alsa_mixer-test_event_spurious_0_63: pass
alsa_mixer-test_get_value_0_62: pass
alsa_mixer-test_name_0_62: fail
alsa_mixer-test_write_default_0_62: pass
alsa_mixer-test_write_valid_0_62: pass
alsa_mixer-test_write_invalid_0_62: pass
alsa_mixer-test_event_missing_0_62: pass
alsa_mixer-test_event_spurious_0_62: pass
alsa_mixer-test_get_value_0_61: pass
alsa_mixer-test_name_0_61: fail
alsa_mixer-test_write_default_0_61: pass
alsa_mixer-test_write_valid_0_61: pass
alsa_mixer-test_write_invalid_0_61: pass
alsa_mixer-test_event_missing_0_61: pass
alsa_mixer-test_event_spurious_0_61: pass
alsa_mixer-test_get_value_0_60: pass
alsa_mixer-test_name_0_60: fail
alsa_mixer-test_write_default_0_60: pass
alsa_mixer-test_write_valid_0_60: pass
alsa_mixer-test_write_invalid_0_60: pass
alsa_mixer-test_event_missing_0_60: pass
alsa_mixer-test_event_spurious_0_60: pass
alsa_mixer-test_get_value_0_59: pass
alsa_mixer-test_name_0_59: fail
alsa_mixer-test_write_default_0_59: pass
alsa_mixer-test_write_valid_0_59: pass
alsa_mixer-test_write_invalid_0_59: pass
alsa_mixer-test_event_missing_0_59: pass
alsa_mixer-test_event_spurious_0_59: pass
alsa_mixer-test_get_value_0_58: pass
alsa_mixer-test_name_0_58: fail
alsa_mixer-test_write_default_0_58: pass
alsa_mixer-test_write_valid_0_58: pass
alsa_mixer-test_write_invalid_0_58: pass
alsa_mixer-test_event_missing_0_58: pass
alsa_mixer-test_event_spurious_0_58: pass
alsa_mixer-test_get_value_0_57: pass
alsa_mixer-test_name_0_57: fail
alsa_mixer-test_write_default_0_57: pass
alsa_mixer-test_write_valid_0_57: pass
alsa_mixer-test_write_invalid_0_57: pass
alsa_mixer-test_event_missing_0_57: pass
alsa_mixer-test_event_spurious_0_57: pass
alsa_mixer-test_get_value_0_56: pass
alsa_mixer-test_name_0_56: fail
alsa_mixer-test_write_default_0_56: pass
alsa_mixer-test_write_valid_0_56: pass
alsa_mixer-test_write_invalid_0_56: pass
alsa_mixer-test_event_missing_0_56: pass
alsa_mixer-test_event_spurious_0_56: pass
alsa_mixer-test_get_value_0_55: pass
alsa_mixer-test_name_0_55: fail
alsa_mixer-test_write_default_0_55: pass
alsa_mixer-test_write_valid_0_55: pass
alsa_mixer-test_write_invalid_0_55: pass
alsa_mixer-test_event_missing_0_55: pass
alsa_mixer-test_event_spurious_0_55: pass
alsa_mixer-test_get_value_0_54: pass
alsa_mixer-test_name_0_54: fail
alsa_mixer-test_write_default_0_54: pass
alsa_mixer-test_write_valid_0_54: pass
alsa_mixer-test_write_invalid_0_54: pass
alsa_mixer-test_event_missing_0_54: pass
alsa_mixer-test_event_spurious_0_54: pass
alsa_mixer-test_get_value_0_53: pass
alsa_mixer-test_name_0_53: fail
alsa_mixer-test_write_default_0_53: pass
alsa_mixer-test_write_valid_0_53: pass
alsa_mixer-test_write_invalid_0_53: pass
alsa_mixer-test_event_missing_0_53: pass
alsa_mixer-test_event_spurious_0_53: pass
alsa_mixer-test_get_value_0_52: pass
alsa_mixer-test_name_0_52: fail
alsa_mixer-test_write_default_0_52: pass
alsa_mixer-test_write_valid_0_52: pass
alsa_mixer-test_write_invalid_0_52: pass
alsa_mixer-test_event_missing_0_52: pass
alsa_mixer-test_event_spurious_0_52: pass
alsa_mixer-test_get_value_0_51: pass
alsa_mixer-test_name_0_51: fail
alsa_mixer-test_write_default_0_51: pass
alsa_mixer-test_write_valid_0_51: pass
alsa_mixer-test_write_invalid_0_51: pass
alsa_mixer-test_event_missing_0_51: pass
alsa_mixer-test_event_spurious_0_51: pass
alsa_mixer-test_get_value_0_50: pass
alsa_mixer-test_name_0_50: fail
alsa_mixer-test_write_default_0_50: pass
alsa_mixer-test_write_valid_0_50: pass
alsa_mixer-test_write_invalid_0_50: pass
alsa_mixer-test_event_missing_0_50: pass
alsa_mixer-test_event_spurious_0_50: pass
alsa_mixer-test_get_value_0_49: pass
alsa_mixer-test_name_0_49: fail
alsa_mixer-test_write_default_0_49: pass
alsa_mixer-test_write_valid_0_49: pass
alsa_mixer-test_write_invalid_0_49: pass
alsa_mixer-test_event_missing_0_49: pass
alsa_mixer-test_event_spurious_0_49: pass
alsa_mixer-test_get_value_0_48: pass
alsa_mixer-test_name_0_48: fail
alsa_mixer-test_write_default_0_48: pass
alsa_mixer-test_write_valid_0_48: pass
alsa_mixer-test_write_invalid_0_48: pass
alsa_mixer-test_event_missing_0_48: pass
alsa_mixer-test_event_spurious_0_48: pass
alsa_mixer-test_get_value_0_47: pass
alsa_mixer-test_name_0_47: fail
alsa_mixer-test_write_default_0_47: pass
alsa_mixer-test_write_valid_0_47: pass
alsa_mixer-test_write_invalid_0_47: pass
alsa_mixer-test_event_missing_0_47: pass
alsa_mixer-test_event_spurious_0_47: pass
alsa_mixer-test_get_value_0_46: pass
alsa_mixer-test_name_0_46: fail
alsa_mixer-test_write_default_0_46: pass
alsa_mixer-test_write_valid_0_46: pass
alsa_mixer-test_write_invalid_0_46: pass
alsa_mixer-test_event_missing_0_46: pass
alsa_mixer-test_event_spurious_0_46: pass
alsa_mixer-test_get_value_0_45: pass
alsa_mixer-test_name_0_45: fail
alsa_mixer-test_write_default_0_45: pass
alsa_mixer-test_write_valid_0_45: pass
alsa_mixer-test_write_invalid_0_45: pass
alsa_mixer-test_event_missing_0_45: pass
alsa_mixer-test_event_spurious_0_45: pass
alsa_mixer-test_get_value_0_44: pass
alsa_mixer-test_name_0_44: fail
alsa_mixer-test_write_default_0_44: pass
alsa_mixer-test_write_valid_0_44: pass
alsa_mixer-test_write_invalid_0_44: pass
alsa_mixer-test_event_missing_0_44: pass
alsa_mixer-test_event_spurious_0_44: pass
alsa_mixer-test_get_value_0_43: pass
alsa_mixer-test_name_0_43: fail
alsa_mixer-test_write_default_0_43: pass
alsa_mixer-test_write_valid_0_43: pass
alsa_mixer-test_write_invalid_0_43: pass
alsa_mixer-test_event_missing_0_43: pass
alsa_mixer-test_event_spurious_0_43: pass
alsa_mixer-test_get_value_0_42: pass
alsa_mixer-test_name_0_42: fail
alsa_mixer-test_write_default_0_42: pass
alsa_mixer-test_write_valid_0_42: pass
alsa_mixer-test_write_invalid_0_42: pass
alsa_mixer-test_event_missing_0_42: pass
alsa_mixer-test_event_spurious_0_42: pass
alsa_mixer-test_get_value_0_41: pass
alsa_mixer-test_name_0_41: fail
alsa_mixer-test_write_default_0_41: pass
alsa_mixer-test_write_valid_0_41: pass
alsa_mixer-test_write_invalid_0_41: pass
alsa_mixer-test_event_missing_0_41: pass
alsa_mixer-test_event_spurious_0_41: pass
alsa_mixer-test_get_value_0_40: pass
alsa_mixer-test_name_0_40: fail
alsa_mixer-test_write_default_0_40: pass
alsa_mixer-test_write_valid_0_40: pass
alsa_mixer-test_write_invalid_0_40: pass
alsa_mixer-test_event_missing_0_40: pass
alsa_mixer-test_event_spurious_0_40: pass
alsa_mixer-test_get_value_0_39: pass
alsa_mixer-test_name_0_39: fail
alsa_mixer-test_write_default_0_39: pass
alsa_mixer-test_write_valid_0_39: pass
alsa_mixer-test_write_invalid_0_39: pass
alsa_mixer-test_event_missing_0_39: pass
alsa_mixer-test_event_spurious_0_39: pass
alsa_mixer-test_get_value_0_38: pass
alsa_mixer-test_name_0_38: fail
alsa_mixer-test_write_default_0_38: pass
alsa_mixer-test_write_valid_0_38: pass
alsa_mixer-test_write_invalid_0_38: pass
alsa_mixer-test_event_missing_0_38: pass
alsa_mixer-test_event_spurious_0_38: pass
alsa_mixer-test_get_value_0_37: pass
alsa_mixer-test_name_0_37: fail
alsa_mixer-test_write_default_0_37: pass
alsa_mixer-test_write_valid_0_37: pass
alsa_mixer-test_write_invalid_0_37: pass
alsa_mixer-test_event_missing_0_37: pass
alsa_mixer-test_event_spurious_0_37: pass
alsa_mixer-test_get_value_0_36: pass
alsa_mixer-test_name_0_36: fail
alsa_mixer-test_write_default_0_36: pass
alsa_mixer-test_write_valid_0_36: pass
alsa_mixer-test_write_invalid_0_36: pass
alsa_mixer-test_event_missing_0_36: pass
alsa_mixer-test_event_spurious_0_36: pass
alsa_mixer-test_get_value_0_35: pass
alsa_mixer-test_name_0_35: fail
alsa_mixer-test_write_default_0_35: pass
alsa_mixer-test_write_valid_0_35: pass
alsa_mixer-test_write_invalid_0_35: pass
alsa_mixer-test_event_missing_0_35: pass
alsa_mixer-test_event_spurious_0_35: pass
alsa_mixer-test_get_value_0_34: pass
alsa_mixer-test_name_0_34: fail
alsa_mixer-test_write_default_0_34: pass
alsa_mixer-test_write_valid_0_34: pass
alsa_mixer-test_write_invalid_0_34: pass
alsa_mixer-test_event_missing_0_34: pass
alsa_mixer-test_event_spurious_0_34: pass
alsa_mixer-test_get_value_0_33: pass
alsa_mixer-test_name_0_33: fail
alsa_mixer-test_write_default_0_33: pass
alsa_mixer-test_write_valid_0_33: pass
alsa_mixer-test_write_invalid_0_33: pass
alsa_mixer-test_event_missing_0_33: pass
alsa_mixer-test_event_spurious_0_33: pass
alsa_mixer-test_get_value_0_32: pass
alsa_mixer-test_name_0_32: fail
alsa_mixer-test_write_default_0_32: pass
alsa_mixer-test_write_valid_0_32: pass
alsa_mixer-test_write_invalid_0_32: pass
alsa_mixer-test_event_missing_0_32: pass
alsa_mixer-test_event_spurious_0_32: pass
alsa_mixer-test_get_value_0_31: pass
alsa_mixer-test_name_0_31: fail
alsa_mixer-test_write_default_0_31: pass
alsa_mixer-test_write_valid_0_31: pass
alsa_mixer-test_write_invalid_0_31: pass
alsa_mixer-test_event_missing_0_31: pass
alsa_mixer-test_event_spurious_0_31: pass
alsa_mixer-test_get_value_0_30: pass
alsa_mixer-test_name_0_30: fail
alsa_mixer-test_write_default_0_30: pass
alsa_mixer-test_write_valid_0_30: pass
alsa_mixer-test_write_invalid_0_30: pass
alsa_mixer-test_event_missing_0_30: pass
alsa_mixer-test_event_spurious_0_30: pass
alsa_mixer-test_get_value_0_29: pass
alsa_mixer-test_name_0_29: pass
alsa_mixer-test_write_default_0_29: pass
alsa_mixer-test_write_valid_0_29: pass
alsa_mixer-test_write_invalid_0_29: pass
alsa_mixer-test_event_missing_0_29: pass
alsa_mixer-test_event_spurious_0_29: pass
alsa_mixer-test_get_value_0_28: pass
alsa_mixer-test_name_0_28: pass
alsa_mixer-test_write_default_0_28: pass
alsa_mixer-test_write_valid_0_28: pass
alsa_mixer-test_write_invalid_0_28: pass
alsa_mixer-test_event_missing_0_28: pass
alsa_mixer-test_event_spurious_0_28: pass
alsa_mixer-test_get_value_0_27: pass
alsa_mixer-test_name_0_27: pass
alsa_mixer-test_write_default_0_27: pass
alsa_mixer-test_write_valid_0_27: pass
alsa_mixer-test_write_invalid_0_27: pass
alsa_mixer-test_event_missing_0_27: pass
alsa_mixer-test_event_spurious_0_27: pass
alsa_mixer-test_get_value_0_26: pass
alsa_mixer-test_name_0_26: pass
alsa_mixer-test_write_default_0_26: pass
alsa_mixer-test_write_valid_0_26: pass
alsa_mixer-test_write_invalid_0_26: pass
alsa_mixer-test_event_missing_0_26: pass
alsa_mixer-test_event_spurious_0_26: pass
alsa_mixer-test_get_value_0_25: pass
alsa_mixer-test_name_0_25: pass
alsa_mixer-test_write_default_0_25: pass
alsa_mixer-test_write_valid_0_25: pass
alsa_mixer-test_write_invalid_0_25: pass
alsa_mixer-test_event_missing_0_25: pass
alsa_mixer-test_event_spurious_0_25: pass
alsa_mixer-test_get_value_0_24: pass
alsa_mixer-test_name_0_24: pass
alsa_mixer-test_write_default_0_24: pass
alsa_mixer-test_write_valid_0_24: pass
alsa_mixer-test_write_invalid_0_24: pass
alsa_mixer-test_event_missing_0_24: pass
alsa_mixer-test_event_spurious_0_24: pass
alsa_mixer-test_get_value_0_23: pass
alsa_mixer-test_name_0_23: pass
alsa_mixer-test_write_default_0_23: pass
alsa_mixer-test_write_valid_0_23: pass
alsa_mixer-test_write_invalid_0_23: pass
alsa_mixer-test_event_missing_0_23: pass
alsa_mixer-test_event_spurious_0_23: pass
alsa_mixer-test_get_value_0_22: pass
alsa_mixer-test_name_0_22: pass
alsa_mixer-test_write_default_0_22: pass
alsa_mixer-test_write_valid_0_22: pass
alsa_mixer-test_write_invalid_0_22: pass
alsa_mixer-test_event_missing_0_22: pass
alsa_mixer-test_event_spurious_0_22: pass
alsa_mixer-test_get_value_0_21: pass
alsa_mixer-test_name_0_21: fail
alsa_mixer-test_write_default_0_21: pass
alsa_mixer-test_write_valid_0_21: pass
alsa_mixer-test_write_invalid_0_21: pass
alsa_mixer-test_event_missing_0_21: pass
alsa_mixer-test_event_spurious_0_21: pass
alsa_mixer-test_get_value_0_20: pass
alsa_mixer-test_name_0_20: fail
alsa_mixer-test_write_default_0_20: pass
alsa_mixer-test_write_valid_0_20: pass
alsa_mixer-test_write_invalid_0_20: pass
alsa_mixer-test_event_missing_0_20: pass
alsa_mixer-test_event_spurious_0_20: pass
alsa_mixer-test_get_value_0_19: pass
alsa_mixer-test_name_0_19: fail
alsa_mixer-test_write_default_0_19: pass
alsa_mixer-test_write_valid_0_19: pass
alsa_mixer-test_write_invalid_0_19: pass
alsa_mixer-test_event_missing_0_19: pass
alsa_mixer-test_event_spurious_0_19: pass
alsa_mixer-test_get_value_0_18: pass
alsa_mixer-test_name_0_18: fail
alsa_mixer-test_write_default_0_18: pass
alsa_mixer-test_write_valid_0_18: pass
alsa_mixer-test_write_invalid_0_18: pass
alsa_mixer-test_event_missing_0_18: pass
alsa_mixer-test_event_spurious_0_18: pass
alsa_mixer-test_get_value_0_17: pass
alsa_mixer-test_name_0_17: fail
alsa_mixer-test_write_default_0_17: pass
alsa_mixer-test_write_valid_0_17: pass
alsa_mixer-test_write_invalid_0_17: pass
alsa_mixer-test_event_missing_0_17: pass
alsa_mixer-test_event_spurious_0_17: pass
alsa_mixer-test_get_value_0_16: pass
alsa_mixer-test_name_0_16: fail
alsa_mixer-test_write_default_0_16: pass
alsa_mixer-test_write_valid_0_16: pass
alsa_mixer-test_write_invalid_0_16: pass
alsa_mixer-test_event_missing_0_16: pass
alsa_mixer-test_event_spurious_0_16: pass
alsa_mixer-test_get_value_0_15: pass
alsa_mixer-test_name_0_15: fail
alsa_mixer-test_write_default_0_15: pass
alsa_mixer-test_write_valid_0_15: pass
alsa_mixer-test_write_invalid_0_15: pass
alsa_mixer-test_event_missing_0_15: pass
alsa_mixer-test_event_spurious_0_15: pass
alsa_mixer-test_get_value_0_14: pass
alsa_mixer-test_name_0_14: fail
alsa_mixer-test_write_default_0_14: pass
alsa_mixer-test_write_valid_0_14: pass
alsa_mixer-test_write_invalid_0_14: pass
alsa_mixer-test_event_missing_0_14: pass
alsa_mixer-test_event_spurious_0_14: pass
alsa_mixer-test_get_value_0_13: pass
alsa_mixer-test_name_0_13: fail
alsa_mixer-test_write_default_0_13: pass
alsa_mixer-test_write_valid_0_13: pass
alsa_mixer-test_write_invalid_0_13: pass
alsa_mixer-test_event_missing_0_13: pass
alsa_mixer-test_event_spurious_0_13: pass
alsa_mixer-test_get_value_0_12: pass
alsa_mixer-test_name_0_12: fail
alsa_mixer-test_write_default_0_12: pass
alsa_mixer-test_write_valid_0_12: pass
alsa_mixer-test_write_invalid_0_12: pass
alsa_mixer-test_event_missing_0_12: pass
alsa_mixer-test_event_spurious_0_12: pass
alsa_mixer-test_get_value_0_11: pass
alsa_mixer-test_name_0_11: fail
alsa_mixer-test_write_default_0_11: pass
alsa_mixer-test_write_valid_0_11: pass
alsa_mixer-test_write_invalid_0_11: pass
alsa_mixer-test_event_missing_0_11: pass
alsa_mixer-test_event_spurious_0_11: pass
alsa_mixer-test_get_value_0_10: pass
alsa_mixer-test_name_0_10: fail
alsa_mixer-test_write_default_0_10: pass
alsa_mixer-test_write_valid_0_10: pass
alsa_mixer-test_write_invalid_0_10: pass
alsa_mixer-test_event_missing_0_10: pass
alsa_mixer-test_event_spurious_0_10: pass
alsa_mixer-test_get_value_0_9: pass
alsa_mixer-test_name_0_9: fail
alsa_mixer-test_write_default_0_9: pass
alsa_mixer-test_write_valid_0_9: pass
alsa_mixer-test_write_invalid_0_9: pass
alsa_mixer-test_event_missing_0_9: pass
alsa_mixer-test_event_spurious_0_9: pass
alsa_mixer-test_get_value_0_8: pass
alsa_mixer-test_name_0_8: fail
alsa_mixer-test_write_default_0_8: pass
alsa_mixer-test_write_valid_0_8: pass
alsa_mixer-test_write_invalid_0_8: pass
alsa_mixer-test_event_missing_0_8: pass
alsa_mixer-test_event_spurious_0_8: pass
alsa_mixer-test_get_value_0_7: pass
alsa_mixer-test_name_0_7: fail
alsa_mixer-test_write_default_0_7: pass
alsa_mixer-test_write_valid_0_7: pass
alsa_mixer-test_write_invalid_0_7: pass
alsa_mixer-test_event_missing_0_7: pass
alsa_mixer-test_event_spurious_0_7: pass
alsa_mixer-test_get_value_0_6: pass
alsa_mixer-test_name_0_6: fail
alsa_mixer-test_write_default_0_6: pass
alsa_mixer-test_write_valid_0_6: pass
alsa_mixer-test_write_invalid_0_6: pass
alsa_mixer-test_event_missing_0_6: pass
alsa_mixer-test_event_spurious_0_6: pass
alsa_mixer-test_get_value_0_5: pass
alsa_mixer-test_name_0_5: pass
alsa_mixer-test_write_default_0_5: pass
alsa_mixer-test_write_valid_0_5: pass
alsa_mixer-test_write_invalid_0_5: pass
alsa_mixer-test_event_missing_0_5: fail
alsa_mixer-test_event_spurious_0_5: pass
alsa_mixer-test_get_value_0_4: pass
alsa_mixer-test_name_0_4: pass
alsa_mixer-test_write_default_0_4: pass
alsa_mixer-test_write_valid_0_4: pass
alsa_mixer-test_write_invalid_0_4: pass
alsa_mixer-test_event_missing_0_4: fail
alsa_mixer-test_event_spurious_0_4: pass
alsa_mixer-test_get_value_0_3: pass
alsa_mixer-test_name_0_3: pass
alsa_mixer-test_write_default_0_3: pass
alsa_mixer-test_write_valid_0_3: pass
alsa_mixer-test_write_invalid_0_3: pass
alsa_mixer-test_event_missing_0_3: fail
alsa_mixer-test_event_spurious_0_3: pass
alsa_mixer-test_get_value_0_2: pass
alsa_mixer-test_name_0_2: pass
alsa_mixer-test_write_default_0_2: pass
alsa_mixer-test_write_valid_0_2: pass
alsa_mixer-test_write_invalid_0_2: pass
alsa_mixer-test_event_missing_0_2: fail
alsa_mixer-test_event_spurious_0_2: pass
alsa_mixer-test_get_value_0_1: pass
alsa_mixer-test_name_0_1: pass
alsa_mixer-test_write_default_0_1: pass
alsa_mixer-test_write_valid_0_1: pass
alsa_mixer-test_write_invalid_0_1: pass
alsa_mixer-test_event_missing_0_1: fail
alsa_mixer-test_event_spurious_0_1: pass
alsa_mixer-test_get_value_0_0: pass
alsa_mixer-test_name_0_0: pass
alsa_mixer-test_write_default_0_0: pass
alsa_mixer-test_write_valid_0_0: pass
alsa_mixer-test_write_invalid_0_0: pass
alsa_mixer-test_event_missing_0_0: fail
alsa_mixer-test_event_spurious_0_0: pass
alsa_mixer-test: pass
9963 13:45:30.641234 end: 3.1 lava-test-shell (duration 00:00:47) [common]
9964 13:45:30.641358 end: 3 lava-test-retry (duration 00:00:47) [common]
9965 13:45:30.641442 start: 4 finalize (timeout 00:07:22) [common]
9966 13:45:30.641523 start: 4.1 power-off (timeout 00:00:30) [common]
9967 13:45:30.641648 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-5', '--port=1', '--command=off']
9968 13:45:32.736890 >> Command sent successfully.
9969 13:45:32.743719 Returned 0 in 2 seconds
9970 13:45:32.743847 end: 4.1 power-off (duration 00:00:02) [common]
9972 13:45:32.744033 start: 4.2 read-feedback (timeout 00:07:20) [common]
9973 13:45:32.744171 Listened to connection for namespace 'common' for up to 1s
9974 13:45:33.745550 Finalising connection for namespace 'common'
9975 13:45:33.746120 Disconnecting from shell: Finalise
9976 13:45:33.746490 / #
9977 13:45:33.847397 end: 4.2 read-feedback (duration 00:00:01) [common]
9978 13:45:33.847988 end: 4 finalize (duration 00:00:03) [common]
9979 13:45:33.848527 Cleaning after the job
9980 13:45:33.849038 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879038/tftp-deploy-v36e__j0/ramdisk
9981 13:45:33.858962 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879038/tftp-deploy-v36e__j0/kernel
9982 13:45:33.869895 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879038/tftp-deploy-v36e__j0/dtb
9983 13:45:33.870067 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879038/tftp-deploy-v36e__j0/nfsrootfs
9984 13:45:33.936941 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879038/tftp-deploy-v36e__j0/modules
9985 13:45:33.943036 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14879038
9986 13:45:34.544619 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14879038
9987 13:45:34.544786 Job finished correctly