Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 36
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 13:28:48.873665 lava-dispatcher, installed at version: 2024.05
2 13:28:48.873916 start: 0 validate
3 13:28:48.874095 Start time: 2024-07-18 13:28:48.874081+00:00 (UTC)
4 13:28:48.874280 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:28:48.874488 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 13:28:49.135056 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:28:49.135302 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 13:28:49.395896 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:28:49.396148 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:28:49.656018 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:28:49.656213 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:28:49.914640 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:28:49.914845 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 13:28:50.174901 validate duration: 1.30
16 13:28:50.175295 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:28:50.175436 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:28:50.175551 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:28:50.175738 Not decompressing ramdisk as can be used compressed.
20 13:28:50.175857 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 13:28:50.175959 saving as /var/lib/lava/dispatcher/tmp/14879064/tftp-deploy-6ha59yvu/ramdisk/initrd.cpio.gz
22 13:28:50.176051 total size: 5628169 (5 MB)
23 13:28:50.177508 progress 0 % (0 MB)
24 13:28:50.179340 progress 5 % (0 MB)
25 13:28:50.181116 progress 10 % (0 MB)
26 13:28:50.182848 progress 15 % (0 MB)
27 13:28:50.184595 progress 20 % (1 MB)
28 13:28:50.186110 progress 25 % (1 MB)
29 13:28:50.187984 progress 30 % (1 MB)
30 13:28:50.189756 progress 35 % (1 MB)
31 13:28:50.191438 progress 40 % (2 MB)
32 13:28:50.193242 progress 45 % (2 MB)
33 13:28:50.194712 progress 50 % (2 MB)
34 13:28:50.196461 progress 55 % (2 MB)
35 13:28:50.198322 progress 60 % (3 MB)
36 13:28:50.199845 progress 65 % (3 MB)
37 13:28:50.201694 progress 70 % (3 MB)
38 13:28:50.203282 progress 75 % (4 MB)
39 13:28:50.205025 progress 80 % (4 MB)
40 13:28:50.206550 progress 85 % (4 MB)
41 13:28:50.208248 progress 90 % (4 MB)
42 13:28:50.210000 progress 95 % (5 MB)
43 13:28:50.211495 progress 100 % (5 MB)
44 13:28:50.211744 5 MB downloaded in 0.04 s (150.39 MB/s)
45 13:28:50.211940 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:28:50.212283 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:28:50.212406 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:28:50.212549 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:28:50.212727 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 13:28:50.212820 saving as /var/lib/lava/dispatcher/tmp/14879064/tftp-deploy-6ha59yvu/kernel/Image
52 13:28:50.212903 total size: 54813184 (52 MB)
53 13:28:50.212994 No compression specified
54 13:28:50.214484 progress 0 % (0 MB)
55 13:28:50.230205 progress 5 % (2 MB)
56 13:28:50.247159 progress 10 % (5 MB)
57 13:28:50.263776 progress 15 % (7 MB)
58 13:28:50.279945 progress 20 % (10 MB)
59 13:28:50.295949 progress 25 % (13 MB)
60 13:28:50.310811 progress 30 % (15 MB)
61 13:28:50.325876 progress 35 % (18 MB)
62 13:28:50.341275 progress 40 % (20 MB)
63 13:28:50.357482 progress 45 % (23 MB)
64 13:28:50.373911 progress 50 % (26 MB)
65 13:28:50.390382 progress 55 % (28 MB)
66 13:28:50.406271 progress 60 % (31 MB)
67 13:28:50.421249 progress 65 % (34 MB)
68 13:28:50.435882 progress 70 % (36 MB)
69 13:28:50.451508 progress 75 % (39 MB)
70 13:28:50.466815 progress 80 % (41 MB)
71 13:28:50.482554 progress 85 % (44 MB)
72 13:28:50.498392 progress 90 % (47 MB)
73 13:28:50.514086 progress 95 % (49 MB)
74 13:28:50.529476 progress 100 % (52 MB)
75 13:28:50.529752 52 MB downloaded in 0.32 s (164.98 MB/s)
76 13:28:50.529955 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:28:50.530323 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:28:50.530440 start: 1.3 download-retry (timeout 00:10:00) [common]
80 13:28:50.530559 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 13:28:50.530724 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:28:50.530815 saving as /var/lib/lava/dispatcher/tmp/14879064/tftp-deploy-6ha59yvu/dtb/mt8192-asurada-spherion-r0.dtb
83 13:28:50.530910 total size: 47258 (0 MB)
84 13:28:50.530993 No compression specified
85 13:28:50.532678 progress 69 % (0 MB)
86 13:28:50.533009 progress 100 % (0 MB)
87 13:28:50.533207 0 MB downloaded in 0.00 s (19.64 MB/s)
88 13:28:50.533371 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:28:50.533714 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:28:50.533821 start: 1.4 download-retry (timeout 00:10:00) [common]
92 13:28:50.533931 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 13:28:50.534068 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 13:28:50.534154 saving as /var/lib/lava/dispatcher/tmp/14879064/tftp-deploy-6ha59yvu/nfsrootfs/full.rootfs.tar
95 13:28:50.534235 total size: 120894716 (115 MB)
96 13:28:50.534323 Using unxz to decompress xz
97 13:28:50.535912 progress 0 % (0 MB)
98 13:28:50.889759 progress 5 % (5 MB)
99 13:28:51.257595 progress 10 % (11 MB)
100 13:28:51.620228 progress 15 % (17 MB)
101 13:28:51.975602 progress 20 % (23 MB)
102 13:28:52.305032 progress 25 % (28 MB)
103 13:28:52.706964 progress 30 % (34 MB)
104 13:28:53.087642 progress 35 % (40 MB)
105 13:28:53.267163 progress 40 % (46 MB)
106 13:28:53.459791 progress 45 % (51 MB)
107 13:28:53.781546 progress 50 % (57 MB)
108 13:28:54.161655 progress 55 % (63 MB)
109 13:28:54.526322 progress 60 % (69 MB)
110 13:28:54.888305 progress 65 % (74 MB)
111 13:28:55.267601 progress 70 % (80 MB)
112 13:28:55.657668 progress 75 % (86 MB)
113 13:28:56.020085 progress 80 % (92 MB)
114 13:28:56.391403 progress 85 % (98 MB)
115 13:28:56.750317 progress 90 % (103 MB)
116 13:28:57.087626 progress 95 % (109 MB)
117 13:28:57.447346 progress 100 % (115 MB)
118 13:28:57.452828 115 MB downloaded in 6.92 s (16.66 MB/s)
119 13:28:57.453030 end: 1.4.1 http-download (duration 00:00:07) [common]
121 13:28:57.453396 end: 1.4 download-retry (duration 00:00:07) [common]
122 13:28:57.453506 start: 1.5 download-retry (timeout 00:09:53) [common]
123 13:28:57.453612 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 13:28:57.453774 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 13:28:57.453867 saving as /var/lib/lava/dispatcher/tmp/14879064/tftp-deploy-6ha59yvu/modules/modules.tar
126 13:28:57.453950 total size: 8611320 (8 MB)
127 13:28:57.454034 Using unxz to decompress xz
128 13:28:57.455713 progress 0 % (0 MB)
129 13:28:57.476277 progress 5 % (0 MB)
130 13:28:57.500506 progress 10 % (0 MB)
131 13:28:57.525119 progress 15 % (1 MB)
132 13:28:57.551043 progress 20 % (1 MB)
133 13:28:57.574905 progress 25 % (2 MB)
134 13:28:57.598276 progress 30 % (2 MB)
135 13:28:57.620535 progress 35 % (2 MB)
136 13:28:57.646654 progress 40 % (3 MB)
137 13:28:57.670962 progress 45 % (3 MB)
138 13:28:57.694839 progress 50 % (4 MB)
139 13:28:57.719360 progress 55 % (4 MB)
140 13:28:57.743118 progress 60 % (4 MB)
141 13:28:57.766106 progress 65 % (5 MB)
142 13:28:57.791673 progress 70 % (5 MB)
143 13:28:57.819154 progress 75 % (6 MB)
144 13:28:57.847204 progress 80 % (6 MB)
145 13:28:57.870774 progress 85 % (7 MB)
146 13:28:57.894385 progress 90 % (7 MB)
147 13:28:57.918207 progress 95 % (7 MB)
148 13:28:57.942149 progress 100 % (8 MB)
149 13:28:57.947796 8 MB downloaded in 0.49 s (16.63 MB/s)
150 13:28:57.947992 end: 1.5.1 http-download (duration 00:00:00) [common]
152 13:28:57.948325 end: 1.5 download-retry (duration 00:00:00) [common]
153 13:28:57.948405 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 13:28:57.948489 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 13:29:02.951103 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14879064/extract-nfsrootfs-qesymwcp
156 13:29:02.951287 end: 1.6.1 extract-nfsrootfs (duration 00:00:05) [common]
157 13:29:02.951382 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 13:29:02.951557 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z
159 13:29:02.951693 makedir: /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin
160 13:29:02.951787 makedir: /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/tests
161 13:29:02.951895 makedir: /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/results
162 13:29:02.951979 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-add-keys
163 13:29:02.952120 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-add-sources
164 13:29:02.952249 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-background-process-start
165 13:29:02.952376 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-background-process-stop
166 13:29:02.952502 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-common-functions
167 13:29:02.952629 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-echo-ipv4
168 13:29:02.952744 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-install-packages
169 13:29:02.952872 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-installed-packages
170 13:29:02.952994 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-os-build
171 13:29:02.953109 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-probe-channel
172 13:29:02.953243 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-probe-ip
173 13:29:02.953367 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-target-ip
174 13:29:02.953481 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-target-mac
175 13:29:02.953618 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-target-storage
176 13:29:02.953737 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-test-case
177 13:29:02.953868 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-test-event
178 13:29:02.953981 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-test-feedback
179 13:29:02.954106 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-test-raise
180 13:29:02.954227 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-test-reference
181 13:29:02.954340 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-test-runner
182 13:29:02.954468 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-test-set
183 13:29:02.954591 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-test-shell
184 13:29:02.954707 Updating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-add-keys (debian)
185 13:29:02.954862 Updating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-add-sources (debian)
186 13:29:02.955003 Updating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-install-packages (debian)
187 13:29:02.955160 Updating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-installed-packages (debian)
188 13:29:02.955289 Updating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/bin/lava-os-build (debian)
189 13:29:02.955414 Creating /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/environment
190 13:29:02.955510 LAVA metadata
191 13:29:02.955575 - LAVA_JOB_ID=14879064
192 13:29:02.955632 - LAVA_DISPATCHER_IP=192.168.201.1
193 13:29:02.955736 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 13:29:02.955793 skipped lava-vland-overlay
195 13:29:02.955861 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 13:29:02.955946 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 13:29:02.956000 skipped lava-multinode-overlay
198 13:29:02.956064 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 13:29:02.956144 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 13:29:02.956206 Loading test definitions
201 13:29:02.956292 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 13:29:02.956361 Using /lava-14879064 at stage 0
203 13:29:02.956644 uuid=14879064_1.6.2.3.1 testdef=None
204 13:29:02.956732 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 13:29:02.956808 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 13:29:02.957245 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 13:29:02.957457 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 13:29:02.958012 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 13:29:02.958233 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 13:29:02.958758 runner path: /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/0/tests/0_timesync-off test_uuid 14879064_1.6.2.3.1
213 13:29:02.958911 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 13:29:02.959125 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 13:29:02.959193 Using /lava-14879064 at stage 0
217 13:29:02.959280 Fetching tests from https://github.com/kernelci/test-definitions.git
218 13:29:02.959370 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/0/tests/1_kselftest-alsa'
219 13:29:05.914131 Running '/usr/bin/git checkout kernelci.org
220 13:29:06.065902 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 13:29:06.066480 uuid=14879064_1.6.2.3.5 testdef=None
222 13:29:06.066614 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 13:29:06.066929 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 13:29:06.068043 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 13:29:06.068379 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 13:29:06.069928 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 13:29:06.070289 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 13:29:06.071818 runner path: /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/0/tests/1_kselftest-alsa test_uuid 14879064_1.6.2.3.5
232 13:29:06.071928 BOARD='mt8192-asurada-spherion-r0'
233 13:29:06.072014 BRANCH='cip'
234 13:29:06.072095 SKIPFILE='/dev/null'
235 13:29:06.072173 SKIP_INSTALL='True'
236 13:29:06.072242 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz'
237 13:29:06.072310 TST_CASENAME=''
238 13:29:06.072389 TST_CMDFILES='alsa'
239 13:29:06.072560 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 13:29:06.072884 Creating lava-test-runner.conf files
242 13:29:06.072971 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14879064/lava-overlay-r8jfbi3z/lava-14879064/0 for stage 0
243 13:29:06.073089 - 0_timesync-off
244 13:29:06.073183 - 1_kselftest-alsa
245 13:29:06.073305 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 13:29:06.073411 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 13:29:13.553317 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 13:29:13.553504 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 13:29:13.553626 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 13:29:13.553745 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 13:29:13.553863 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 13:29:13.719791 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 13:29:13.719960 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 13:29:13.720072 extracting modules file /var/lib/lava/dispatcher/tmp/14879064/tftp-deploy-6ha59yvu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14879064/extract-nfsrootfs-qesymwcp
255 13:29:14.030249 extracting modules file /var/lib/lava/dispatcher/tmp/14879064/tftp-deploy-6ha59yvu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14879064/extract-overlay-ramdisk-kryjde9q/ramdisk
256 13:29:14.278705 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 13:29:14.278883 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 13:29:14.279021 [common] Applying overlay to NFS
259 13:29:14.279116 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14879064/compress-overlay-u_h9kp17/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14879064/extract-nfsrootfs-qesymwcp
260 13:29:15.310830 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 13:29:15.310988 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 13:29:15.311089 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 13:29:15.311173 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 13:29:15.311243 Building ramdisk /var/lib/lava/dispatcher/tmp/14879064/extract-overlay-ramdisk-kryjde9q/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14879064/extract-overlay-ramdisk-kryjde9q/ramdisk
265 13:29:15.623225 >> 129966 blocks
266 13:29:17.860192 rename /var/lib/lava/dispatcher/tmp/14879064/extract-overlay-ramdisk-kryjde9q/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14879064/tftp-deploy-6ha59yvu/ramdisk/ramdisk.cpio.gz
267 13:29:17.860376 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 13:29:17.860470 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 13:29:17.860569 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 13:29:17.860647 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14879064/tftp-deploy-6ha59yvu/kernel/Image']
271 13:29:32.089106 Returned 0 in 14 seconds
272 13:29:32.089319 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14879064/tftp-deploy-6ha59yvu/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14879064/tftp-deploy-6ha59yvu/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14879064/tftp-deploy-6ha59yvu/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14879064/tftp-deploy-6ha59yvu/kernel/image.itb
273 13:29:32.623125 output: FIT description: Kernel Image image with one or more FDT blobs
274 13:29:32.623256 output: Created: Thu Jul 18 14:29:32 2024
275 13:29:32.623318 output: Image 0 (kernel-1)
276 13:29:32.623374 output: Description:
277 13:29:32.623427 output: Created: Thu Jul 18 14:29:32 2024
278 13:29:32.623480 output: Type: Kernel Image
279 13:29:32.623531 output: Compression: lzma compressed
280 13:29:32.623585 output: Data Size: 13114469 Bytes = 12807.10 KiB = 12.51 MiB
281 13:29:32.623636 output: Architecture: AArch64
282 13:29:32.623685 output: OS: Linux
283 13:29:32.623734 output: Load Address: 0x00000000
284 13:29:32.623783 output: Entry Point: 0x00000000
285 13:29:32.623832 output: Hash algo: crc32
286 13:29:32.623881 output: Hash value: a47b020b
287 13:29:32.623930 output: Image 1 (fdt-1)
288 13:29:32.623979 output: Description: mt8192-asurada-spherion-r0
289 13:29:32.624028 output: Created: Thu Jul 18 14:29:32 2024
290 13:29:32.624077 output: Type: Flat Device Tree
291 13:29:32.624125 output: Compression: uncompressed
292 13:29:32.624173 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 13:29:32.624222 output: Architecture: AArch64
294 13:29:32.624270 output: Hash algo: crc32
295 13:29:32.624318 output: Hash value: 0f8e4d2e
296 13:29:32.624366 output: Image 2 (ramdisk-1)
297 13:29:32.624414 output: Description: unavailable
298 13:29:32.624462 output: Created: Thu Jul 18 14:29:32 2024
299 13:29:32.624511 output: Type: RAMDisk Image
300 13:29:32.624560 output: Compression: uncompressed
301 13:29:32.624608 output: Data Size: 18722854 Bytes = 18284.04 KiB = 17.86 MiB
302 13:29:32.624656 output: Architecture: AArch64
303 13:29:32.624703 output: OS: Linux
304 13:29:32.624751 output: Load Address: unavailable
305 13:29:32.624799 output: Entry Point: unavailable
306 13:29:32.624847 output: Hash algo: crc32
307 13:29:32.624895 output: Hash value: f1a949e7
308 13:29:32.624943 output: Default Configuration: 'conf-1'
309 13:29:32.624990 output: Configuration 0 (conf-1)
310 13:29:32.625036 output: Description: mt8192-asurada-spherion-r0
311 13:29:32.625084 output: Kernel: kernel-1
312 13:29:32.625145 output: Init Ramdisk: ramdisk-1
313 13:29:32.625268 output: FDT: fdt-1
314 13:29:32.625317 output: Loadables: kernel-1
315 13:29:32.625365 output:
316 13:29:32.625464 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 13:29:32.625538 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 13:29:32.625610 end: 1.6 prepare-tftp-overlay (duration 00:00:35) [common]
319 13:29:32.625684 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 13:29:32.625740 No LXC device requested
321 13:29:32.625806 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 13:29:32.625876 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 13:29:32.625942 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 13:29:32.625996 Checking files for TFTP limit of 4294967296 bytes.
325 13:29:32.626356 end: 1 tftp-deploy (duration 00:00:42) [common]
326 13:29:32.626443 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 13:29:32.626521 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 13:29:32.626608 substitutions:
329 13:29:32.626666 - {DTB}: 14879064/tftp-deploy-6ha59yvu/dtb/mt8192-asurada-spherion-r0.dtb
330 13:29:32.626721 - {INITRD}: 14879064/tftp-deploy-6ha59yvu/ramdisk/ramdisk.cpio.gz
331 13:29:32.626774 - {KERNEL}: 14879064/tftp-deploy-6ha59yvu/kernel/Image
332 13:29:32.626830 - {LAVA_MAC}: None
333 13:29:32.626881 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14879064/extract-nfsrootfs-qesymwcp
334 13:29:32.626931 - {NFS_SERVER_IP}: 192.168.201.1
335 13:29:32.626980 - {PRESEED_CONFIG}: None
336 13:29:32.627037 - {PRESEED_LOCAL}: None
337 13:29:32.627095 - {RAMDISK}: 14879064/tftp-deploy-6ha59yvu/ramdisk/ramdisk.cpio.gz
338 13:29:32.627165 - {ROOT_PART}: None
339 13:29:32.627231 - {ROOT}: None
340 13:29:32.627289 - {SERVER_IP}: 192.168.201.1
341 13:29:32.627339 - {TEE}: None
342 13:29:32.627388 Parsed boot commands:
343 13:29:32.627540 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 13:29:32.627811 Parsed boot commands: tftpboot 192.168.201.1 14879064/tftp-deploy-6ha59yvu/kernel/image.itb 14879064/tftp-deploy-6ha59yvu/kernel/cmdline
345 13:29:32.627929 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 13:29:32.628033 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 13:29:32.628133 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 13:29:32.628231 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 13:29:32.628311 Not connected, no need to disconnect.
350 13:29:32.628404 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 13:29:32.628499 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 13:29:32.628579 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 13:29:32.631453 Setting prompt string to ['lava-test: # ']
354 13:29:32.631776 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 13:29:32.631866 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 13:29:32.631957 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 13:29:32.632054 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 13:29:32.632244 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=reboot']
359 13:29:41.759373 >> Command sent successfully.
360 13:29:41.762840 Returned 0 in 9 seconds
361 13:29:41.762981 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 13:29:41.763184 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 13:29:41.763266 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 13:29:41.763341 Setting prompt string to 'Starting depthcharge on Spherion...'
366 13:29:41.763396 Changing prompt to 'Starting depthcharge on Spherion...'
367 13:29:41.763455 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 13:29:41.763789 [Enter `^Ec?' for help]
369 13:29:43.388806
370 13:29:43.388942
371 13:29:43.389003 F0: 102B 0000
372 13:29:43.389060
373 13:29:43.389111 F3: 1001 0000 [0200]
374 13:29:43.393096
375 13:29:43.393205 F3: 1001 0000
376 13:29:43.393295
377 13:29:43.393429 F7: 102D 0000
378 13:29:43.393542
379 13:29:43.393619 F1: 0000 0000
380 13:29:43.396829
381 13:29:43.396925 V0: 0000 0000 [0001]
382 13:29:43.397002
383 13:29:43.397078 00: 0007 8000
384 13:29:43.397191
385 13:29:43.400155 01: 0000 0000
386 13:29:43.400230
387 13:29:43.400287 BP: 0C00 0209 [0000]
388 13:29:43.400340
389 13:29:43.404042 G0: 1182 0000
390 13:29:43.404114
391 13:29:43.404171 EC: 0000 0021 [4000]
392 13:29:43.404225
393 13:29:43.407688 S7: 0000 0000 [0000]
394 13:29:43.407761
395 13:29:43.407818 CC: 0000 0000 [0001]
396 13:29:43.407871
397 13:29:43.410869 T0: 0000 0040 [010F]
398 13:29:43.410942
399 13:29:43.410999 Jump to BL
400 13:29:43.411051
401 13:29:43.436431
402 13:29:43.436525
403 13:29:43.442683 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 13:29:43.446238 ARM64: Exception handlers installed.
405 13:29:43.449447 ARM64: Testing exception
406 13:29:43.452546 ARM64: Done test exception
407 13:29:43.459517 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 13:29:43.469262 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 13:29:43.476202 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 13:29:43.486707 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 13:29:43.493014 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 13:29:43.503361 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 13:29:43.513432 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 13:29:43.520317 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 13:29:43.538821 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 13:29:43.541897 WDT: Last reset was cold boot
417 13:29:43.545485 SPI1(PAD0) initialized at 2873684 Hz
418 13:29:43.548595 SPI5(PAD0) initialized at 992727 Hz
419 13:29:43.552116 VBOOT: Loading verstage.
420 13:29:43.558747 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 13:29:43.561775 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 13:29:43.565569 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 13:29:43.568704 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 13:29:43.576184 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 13:29:43.582857 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 13:29:43.593658 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
427 13:29:43.593734
428 13:29:43.593791
429 13:29:43.603943 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 13:29:43.607076 ARM64: Exception handlers installed.
431 13:29:43.610233 ARM64: Testing exception
432 13:29:43.613499 ARM64: Done test exception
433 13:29:43.616575 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 13:29:43.620359 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 13:29:43.634995 Probing TPM: . done!
436 13:29:43.635073 TPM ready after 0 ms
437 13:29:43.641353 Connected to device vid:did:rid of 1ae0:0028:00
438 13:29:43.648352 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
439 13:29:43.687201 Initialized TPM device CR50 revision 0
440 13:29:43.699354 tlcl_send_startup: Startup return code is 0
441 13:29:43.699442 TPM: setup succeeded
442 13:29:43.710883 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 13:29:43.719367 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 13:29:43.729409 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 13:29:43.738407 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 13:29:43.741543 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 13:29:43.745314 in-header: 03 07 00 00 08 00 00 00
448 13:29:43.748494 in-data: aa e4 47 04 13 02 00 00
449 13:29:43.751581 Chrome EC: UHEPI supported
450 13:29:43.758237 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 13:29:43.761459 in-header: 03 a9 00 00 08 00 00 00
452 13:29:43.765311 in-data: 84 60 60 08 00 00 00 00
453 13:29:43.765456 Phase 1
454 13:29:43.768505 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 13:29:43.774650 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 13:29:43.781587 VB2:vb2_check_recovery() Recovery was requested manually
457 13:29:43.784704 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
458 13:29:43.788277 Recovery requested (1009000e)
459 13:29:43.796705 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 13:29:43.801994 tlcl_extend: response is 0
461 13:29:43.810225 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 13:29:43.815298 tlcl_extend: response is 0
463 13:29:43.822153 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 13:29:43.842992 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 13:29:43.849407 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 13:29:43.849485
467 13:29:43.849544
468 13:29:43.859949 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 13:29:43.863815 ARM64: Exception handlers installed.
470 13:29:43.863891 ARM64: Testing exception
471 13:29:43.867106 ARM64: Done test exception
472 13:29:43.888524 pmic_efuse_setting: Set efuses in 11 msecs
473 13:29:43.891775 pmwrap_interface_init: Select PMIF_VLD_RDY
474 13:29:43.898611 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 13:29:43.901460 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 13:29:43.908222 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 13:29:43.911482 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 13:29:43.915166 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 13:29:43.921738 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 13:29:43.924744 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 13:29:43.931773 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 13:29:43.935176 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 13:29:43.941435 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 13:29:43.945035 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 13:29:43.948211 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 13:29:43.954548 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 13:29:43.961443 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 13:29:43.964919 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 13:29:43.971220 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 13:29:43.978210 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 13:29:43.984597 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 13:29:43.988049 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 13:29:43.994499 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 13:29:44.001446 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 13:29:44.004512 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 13:29:44.011434 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 13:29:44.017455 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 13:29:44.021108 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 13:29:44.027591 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 13:29:44.031185 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 13:29:44.037749 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 13:29:44.041467 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 13:29:44.047576 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 13:29:44.051034 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 13:29:44.057711 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 13:29:44.060809 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 13:29:44.067683 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 13:29:44.070764 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 13:29:44.077642 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 13:29:44.080684 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 13:29:44.087539 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 13:29:44.090651 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 13:29:44.094937 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 13:29:44.101385 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 13:29:44.104564 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 13:29:44.107793 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 13:29:44.114683 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 13:29:44.117699 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 13:29:44.121424 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 13:29:44.124553 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 13:29:44.130954 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 13:29:44.134689 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 13:29:44.137659 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 13:29:44.144353 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 13:29:44.150738 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
526 13:29:44.161005 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 13:29:44.164561 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 13:29:44.170889 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 13:29:44.180775 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 13:29:44.184079 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 13:29:44.190986 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 13:29:44.194146 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 13:29:44.201015 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
534 13:29:44.207318 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 13:29:44.210995 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
536 13:29:44.217387 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 13:29:44.225492 [RTC]rtc_get_frequency_meter,154: input=15, output=852
538 13:29:44.234903 [RTC]rtc_get_frequency_meter,154: input=7, output=725
539 13:29:44.244389 [RTC]rtc_get_frequency_meter,154: input=11, output=788
540 13:29:44.253467 [RTC]rtc_get_frequency_meter,154: input=13, output=820
541 13:29:44.263037 [RTC]rtc_get_frequency_meter,154: input=12, output=804
542 13:29:44.272927 [RTC]rtc_get_frequency_meter,154: input=11, output=788
543 13:29:44.282055 [RTC]rtc_get_frequency_meter,154: input=12, output=804
544 13:29:44.285775 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
545 13:29:44.292661 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
546 13:29:44.295829 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 13:29:44.299648 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 13:29:44.306047 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 13:29:44.309237 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 13:29:44.312749 ADC[4]: Raw value=904802 ID=7
551 13:29:44.312813 ADC[3]: Raw value=213916 ID=1
552 13:29:44.316019 RAM Code: 0x71
553 13:29:44.319248 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 13:29:44.326109 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 13:29:44.332467 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 13:29:44.339174 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 13:29:44.342425 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 13:29:44.345656 in-header: 03 07 00 00 08 00 00 00
559 13:29:44.348801 in-data: aa e4 47 04 13 02 00 00
560 13:29:44.352528 Chrome EC: UHEPI supported
561 13:29:44.358990 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 13:29:44.362145 in-header: 03 a9 00 00 08 00 00 00
563 13:29:44.365348 in-data: 84 60 60 08 00 00 00 00
564 13:29:44.368899 MRC: failed to locate region type 0.
565 13:29:44.375244 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 13:29:44.378615 DRAM-K: Running full calibration
567 13:29:44.385256 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 13:29:44.385332 header.status = 0x0
569 13:29:44.388940 header.version = 0x6 (expected: 0x6)
570 13:29:44.392010 header.size = 0xd00 (expected: 0xd00)
571 13:29:44.395384 header.flags = 0x0
572 13:29:44.402044 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 13:29:44.419145 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 13:29:44.425429 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 13:29:44.429036 dram_init: ddr_geometry: 2
576 13:29:44.432161 [EMI] MDL number = 2
577 13:29:44.432237 [EMI] Get MDL freq = 0
578 13:29:44.435423 dram_init: ddr_type: 0
579 13:29:44.435517 is_discrete_lpddr4: 1
580 13:29:44.439141 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 13:29:44.439216
582 13:29:44.439274
583 13:29:44.442213 [Bian_co] ETT version 0.0.0.1
584 13:29:44.449174 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 13:29:44.449249
586 13:29:44.452410 dramc_set_vcore_voltage set vcore to 650000
587 13:29:44.455514 Read voltage for 800, 4
588 13:29:44.455588 Vio18 = 0
589 13:29:44.455647 Vcore = 650000
590 13:29:44.458713 Vdram = 0
591 13:29:44.458788 Vddq = 0
592 13:29:44.458847 Vmddr = 0
593 13:29:44.462537 dram_init: config_dvfs: 1
594 13:29:44.465743 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 13:29:44.472199 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 13:29:44.475362 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 13:29:44.478861 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 13:29:44.482006 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 13:29:44.485723 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 13:29:44.488744 MEM_TYPE=3, freq_sel=18
601 13:29:44.492119 sv_algorithm_assistance_LP4_1600
602 13:29:44.495604 ============ PULL DRAM RESETB DOWN ============
603 13:29:44.501888 ========== PULL DRAM RESETB DOWN end =========
604 13:29:44.505367 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 13:29:44.508963 ===================================
606 13:29:44.511857 LPDDR4 DRAM CONFIGURATION
607 13:29:44.515525 ===================================
608 13:29:44.515601 EX_ROW_EN[0] = 0x0
609 13:29:44.519143 EX_ROW_EN[1] = 0x0
610 13:29:44.519217 LP4Y_EN = 0x0
611 13:29:44.522518 WORK_FSP = 0x0
612 13:29:44.522593 WL = 0x2
613 13:29:44.526272 RL = 0x2
614 13:29:44.526347 BL = 0x2
615 13:29:44.530020 RPST = 0x0
616 13:29:44.530095 RD_PRE = 0x0
617 13:29:44.533961 WR_PRE = 0x1
618 13:29:44.534036 WR_PST = 0x0
619 13:29:44.534094 DBI_WR = 0x0
620 13:29:44.537348 DBI_RD = 0x0
621 13:29:44.537424 OTF = 0x1
622 13:29:44.540838 ===================================
623 13:29:44.544053 ===================================
624 13:29:44.547709 ANA top config
625 13:29:44.551531 ===================================
626 13:29:44.551607 DLL_ASYNC_EN = 0
627 13:29:44.555467 ALL_SLAVE_EN = 1
628 13:29:44.558529 NEW_RANK_MODE = 1
629 13:29:44.561729 DLL_IDLE_MODE = 1
630 13:29:44.561804 LP45_APHY_COMB_EN = 1
631 13:29:44.564904 TX_ODT_DIS = 1
632 13:29:44.568619 NEW_8X_MODE = 1
633 13:29:44.571878 ===================================
634 13:29:44.575045 ===================================
635 13:29:44.578122 data_rate = 1600
636 13:29:44.581791 CKR = 1
637 13:29:44.581866 DQ_P2S_RATIO = 8
638 13:29:44.585034 ===================================
639 13:29:44.588258 CA_P2S_RATIO = 8
640 13:29:44.591469 DQ_CA_OPEN = 0
641 13:29:44.595145 DQ_SEMI_OPEN = 0
642 13:29:44.598241 CA_SEMI_OPEN = 0
643 13:29:44.601938 CA_FULL_RATE = 0
644 13:29:44.602012 DQ_CKDIV4_EN = 1
645 13:29:44.604912 CA_CKDIV4_EN = 1
646 13:29:44.608530 CA_PREDIV_EN = 0
647 13:29:44.611810 PH8_DLY = 0
648 13:29:44.615259 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 13:29:44.618035 DQ_AAMCK_DIV = 4
650 13:29:44.618109 CA_AAMCK_DIV = 4
651 13:29:44.621803 CA_ADMCK_DIV = 4
652 13:29:44.624906 DQ_TRACK_CA_EN = 0
653 13:29:44.628051 CA_PICK = 800
654 13:29:44.631632 CA_MCKIO = 800
655 13:29:44.634960 MCKIO_SEMI = 0
656 13:29:44.638425 PLL_FREQ = 3068
657 13:29:44.638500 DQ_UI_PI_RATIO = 32
658 13:29:44.641481 CA_UI_PI_RATIO = 0
659 13:29:44.644960 ===================================
660 13:29:44.648284 ===================================
661 13:29:44.651649 memory_type:LPDDR4
662 13:29:44.654649 GP_NUM : 10
663 13:29:44.654723 SRAM_EN : 1
664 13:29:44.658418 MD32_EN : 0
665 13:29:44.661505 ===================================
666 13:29:44.661580 [ANA_INIT] >>>>>>>>>>>>>>
667 13:29:44.664797 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 13:29:44.667904 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 13:29:44.671027 ===================================
670 13:29:44.674927 data_rate = 1600,PCW = 0X7600
671 13:29:44.678061 ===================================
672 13:29:44.681175 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 13:29:44.688098 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 13:29:44.691802 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 13:29:44.698044 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 13:29:44.701576 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 13:29:44.704677 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 13:29:44.707813 [ANA_INIT] flow start
679 13:29:44.707888 [ANA_INIT] PLL >>>>>>>>
680 13:29:44.710895 [ANA_INIT] PLL <<<<<<<<
681 13:29:44.714806 [ANA_INIT] MIDPI >>>>>>>>
682 13:29:44.714925 [ANA_INIT] MIDPI <<<<<<<<
683 13:29:44.717816 [ANA_INIT] DLL >>>>>>>>
684 13:29:44.721480 [ANA_INIT] flow end
685 13:29:44.724426 ============ LP4 DIFF to SE enter ============
686 13:29:44.727801 ============ LP4 DIFF to SE exit ============
687 13:29:44.731273 [ANA_INIT] <<<<<<<<<<<<<
688 13:29:44.734351 [Flow] Enable top DCM control >>>>>
689 13:29:44.738087 [Flow] Enable top DCM control <<<<<
690 13:29:44.741077 Enable DLL master slave shuffle
691 13:29:44.744193 ==============================================================
692 13:29:44.747706 Gating Mode config
693 13:29:44.754575 ==============================================================
694 13:29:44.754651 Config description:
695 13:29:44.764459 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 13:29:44.770779 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 13:29:44.773939 SELPH_MODE 0: By rank 1: By Phase
698 13:29:44.780866 ==============================================================
699 13:29:44.783944 GAT_TRACK_EN = 1
700 13:29:44.787694 RX_GATING_MODE = 2
701 13:29:44.790656 RX_GATING_TRACK_MODE = 2
702 13:29:44.794480 SELPH_MODE = 1
703 13:29:44.797492 PICG_EARLY_EN = 1
704 13:29:44.800621 VALID_LAT_VALUE = 1
705 13:29:44.804311 ==============================================================
706 13:29:44.807405 Enter into Gating configuration >>>>
707 13:29:44.810549 Exit from Gating configuration <<<<
708 13:29:44.814378 Enter into DVFS_PRE_config >>>>>
709 13:29:44.827498 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 13:29:44.827576 Exit from DVFS_PRE_config <<<<<
711 13:29:44.830562 Enter into PICG configuration >>>>
712 13:29:44.834157 Exit from PICG configuration <<<<
713 13:29:44.837056 [RX_INPUT] configuration >>>>>
714 13:29:44.840597 [RX_INPUT] configuration <<<<<
715 13:29:44.847162 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 13:29:44.850767 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 13:29:44.857336 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 13:29:44.864120 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 13:29:44.870472 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 13:29:44.877411 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 13:29:44.880566 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 13:29:44.883580 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 13:29:44.886799 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 13:29:44.893707 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 13:29:44.896807 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 13:29:44.900044 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 13:29:44.903321 ===================================
728 13:29:44.906914 LPDDR4 DRAM CONFIGURATION
729 13:29:44.910020 ===================================
730 13:29:44.913757 EX_ROW_EN[0] = 0x0
731 13:29:44.913832 EX_ROW_EN[1] = 0x0
732 13:29:44.916879 LP4Y_EN = 0x0
733 13:29:44.916955 WORK_FSP = 0x0
734 13:29:44.920082 WL = 0x2
735 13:29:44.920157 RL = 0x2
736 13:29:44.923423 BL = 0x2
737 13:29:44.923498 RPST = 0x0
738 13:29:44.926581 RD_PRE = 0x0
739 13:29:44.926656 WR_PRE = 0x1
740 13:29:44.929746 WR_PST = 0x0
741 13:29:44.929821 DBI_WR = 0x0
742 13:29:44.933513 DBI_RD = 0x0
743 13:29:44.933588 OTF = 0x1
744 13:29:44.936534 ===================================
745 13:29:44.943615 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 13:29:44.946662 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 13:29:44.949846 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 13:29:44.952860 ===================================
749 13:29:44.956379 LPDDR4 DRAM CONFIGURATION
750 13:29:44.959652 ===================================
751 13:29:44.959744 EX_ROW_EN[0] = 0x10
752 13:29:44.962913 EX_ROW_EN[1] = 0x0
753 13:29:44.966483 LP4Y_EN = 0x0
754 13:29:44.966558 WORK_FSP = 0x0
755 13:29:44.969969 WL = 0x2
756 13:29:44.970044 RL = 0x2
757 13:29:44.972785 BL = 0x2
758 13:29:44.972883 RPST = 0x0
759 13:29:44.976165 RD_PRE = 0x0
760 13:29:44.976239 WR_PRE = 0x1
761 13:29:44.979652 WR_PST = 0x0
762 13:29:44.979809 DBI_WR = 0x0
763 13:29:44.983246 DBI_RD = 0x0
764 13:29:44.983338 OTF = 0x1
765 13:29:44.986167 ===================================
766 13:29:44.993017 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 13:29:44.997293 nWR fixed to 40
768 13:29:45.000932 [ModeRegInit_LP4] CH0 RK0
769 13:29:45.001007 [ModeRegInit_LP4] CH0 RK1
770 13:29:45.004050 [ModeRegInit_LP4] CH1 RK0
771 13:29:45.007138 [ModeRegInit_LP4] CH1 RK1
772 13:29:45.007214 match AC timing 13
773 13:29:45.013890 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 13:29:45.017083 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 13:29:45.020830 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 13:29:45.027137 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 13:29:45.030332 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 13:29:45.033470 [EMI DOE] emi_dcm 0
779 13:29:45.037051 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 13:29:45.037172 ==
781 13:29:45.040219 Dram Type= 6, Freq= 0, CH_0, rank 0
782 13:29:45.043463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 13:29:45.043539 ==
784 13:29:45.050236 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 13:29:45.057090 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 13:29:45.064692 [CA 0] Center 38 (7~69) winsize 63
787 13:29:45.068788 [CA 1] Center 37 (6~68) winsize 63
788 13:29:45.071704 [CA 2] Center 34 (4~65) winsize 62
789 13:29:45.074994 [CA 3] Center 35 (4~66) winsize 63
790 13:29:45.078339 [CA 4] Center 33 (3~64) winsize 62
791 13:29:45.081366 [CA 5] Center 33 (3~64) winsize 62
792 13:29:45.081442
793 13:29:45.084978 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 13:29:45.085076
795 13:29:45.088215 [CATrainingPosCal] consider 1 rank data
796 13:29:45.091891 u2DelayCellTimex100 = 270/100 ps
797 13:29:45.095384 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
798 13:29:45.098671 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 13:29:45.102631 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 13:29:45.105822 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 13:29:45.112167 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 13:29:45.115354 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 13:29:45.115430
804 13:29:45.118798 CA PerBit enable=1, Macro0, CA PI delay=33
805 13:29:45.118873
806 13:29:45.122047 [CBTSetCACLKResult] CA Dly = 33
807 13:29:45.122122 CS Dly: 6 (0~37)
808 13:29:45.122181 ==
809 13:29:45.125770 Dram Type= 6, Freq= 0, CH_0, rank 1
810 13:29:45.132118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 13:29:45.132195 ==
812 13:29:45.135364 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 13:29:45.142122 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 13:29:45.151583 [CA 0] Center 38 (7~69) winsize 63
815 13:29:45.154545 [CA 1] Center 37 (7~68) winsize 62
816 13:29:45.157758 [CA 2] Center 35 (4~66) winsize 63
817 13:29:45.161015 [CA 3] Center 35 (4~66) winsize 63
818 13:29:45.164167 [CA 4] Center 34 (3~65) winsize 63
819 13:29:45.168039 [CA 5] Center 33 (3~64) winsize 62
820 13:29:45.168115
821 13:29:45.171154 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 13:29:45.171229
823 13:29:45.174324 [CATrainingPosCal] consider 2 rank data
824 13:29:45.177470 u2DelayCellTimex100 = 270/100 ps
825 13:29:45.181290 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
826 13:29:45.187565 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 13:29:45.191126 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 13:29:45.194209 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
829 13:29:45.197831 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 13:29:45.200922 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 13:29:45.200996
832 13:29:45.204032 CA PerBit enable=1, Macro0, CA PI delay=33
833 13:29:45.204107
834 13:29:45.207462 [CBTSetCACLKResult] CA Dly = 33
835 13:29:45.211005 CS Dly: 6 (0~38)
836 13:29:45.211079
837 13:29:45.213954 ----->DramcWriteLeveling(PI) begin...
838 13:29:45.214030 ==
839 13:29:45.217349 Dram Type= 6, Freq= 0, CH_0, rank 0
840 13:29:45.220555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 13:29:45.220630 ==
842 13:29:45.223775 Write leveling (Byte 0): 29 => 29
843 13:29:45.227538 Write leveling (Byte 1): 28 => 28
844 13:29:45.230759 DramcWriteLeveling(PI) end<-----
845 13:29:45.230834
846 13:29:45.230891 ==
847 13:29:45.233983 Dram Type= 6, Freq= 0, CH_0, rank 0
848 13:29:45.237132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 13:29:45.237246 ==
850 13:29:45.240381 [Gating] SW mode calibration
851 13:29:45.247294 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 13:29:45.253704 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 13:29:45.257457 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 13:29:45.260490 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 13:29:45.266852 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
856 13:29:45.270732 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 13:29:45.273856 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 13:29:45.280197 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 13:29:45.283297 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 13:29:45.286905 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 13:29:45.293556 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 13:29:45.296961 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 13:29:45.300372 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 13:29:45.306897 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 13:29:45.310100 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 13:29:45.313457 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 13:29:45.319853 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 13:29:45.323487 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 13:29:45.326665 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 13:29:45.333286 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
871 13:29:45.336711 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 13:29:45.339985 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 13:29:45.346402 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 13:29:45.350071 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 13:29:45.353330 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 13:29:45.359608 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 13:29:45.363322 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 13:29:45.366429 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 13:29:45.369665 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
880 13:29:45.376697 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
881 13:29:45.379780 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 13:29:45.382952 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 13:29:45.389964 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 13:29:45.393015 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 13:29:45.396316 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 13:29:45.403022 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
887 13:29:45.406165 0 10 8 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
888 13:29:45.409781 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
889 13:29:45.416575 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 13:29:45.419645 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 13:29:45.423114 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 13:29:45.429484 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 13:29:45.433381 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 13:29:45.436478 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
895 13:29:45.442756 0 11 8 | B1->B0 | 2929 4545 | 0 0 | (0 0) (0 0)
896 13:29:45.446463 0 11 12 | B1->B0 | 3a39 4646 | 1 0 | (0 0) (0 0)
897 13:29:45.449337 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 13:29:45.456086 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 13:29:45.459668 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 13:29:45.463058 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 13:29:45.469408 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 13:29:45.473070 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
903 13:29:45.476338 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 13:29:45.482594 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 13:29:45.486383 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 13:29:45.489551 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 13:29:45.495846 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 13:29:45.498976 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 13:29:45.502665 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 13:29:45.509528 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 13:29:45.512785 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 13:29:45.515844 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 13:29:45.522360 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 13:29:45.526010 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 13:29:45.529059 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 13:29:45.532399 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 13:29:45.538787 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 13:29:45.542526 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 13:29:45.545630 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 13:29:45.548790 Total UI for P1: 0, mck2ui 16
921 13:29:45.552042 best dqsien dly found for B0: ( 0, 14, 4)
922 13:29:45.558916 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 13:29:45.562058 Total UI for P1: 0, mck2ui 16
924 13:29:45.565739 best dqsien dly found for B1: ( 0, 14, 8)
925 13:29:45.568798 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 13:29:45.572050 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 13:29:45.572143
928 13:29:45.575866 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 13:29:45.578660 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 13:29:45.582291 [Gating] SW calibration Done
931 13:29:45.582367 ==
932 13:29:45.585371 Dram Type= 6, Freq= 0, CH_0, rank 0
933 13:29:45.589054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 13:29:45.589131 ==
935 13:29:45.592168 RX Vref Scan: 0
936 13:29:45.592242
937 13:29:45.592301 RX Vref 0 -> 0, step: 1
938 13:29:45.592355
939 13:29:45.595394 RX Delay -130 -> 252, step: 16
940 13:29:45.602278 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
941 13:29:45.605387 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 13:29:45.609085 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 13:29:45.612071 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 13:29:45.615229 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 13:29:45.619065 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 13:29:45.625178 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 13:29:45.628806 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
948 13:29:45.632022 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 13:29:45.635761 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
950 13:29:45.638888 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 13:29:45.645127 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 13:29:45.648572 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 13:29:45.652089 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 13:29:45.655845 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 13:29:45.662217 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 13:29:45.662293 ==
957 13:29:45.665471 Dram Type= 6, Freq= 0, CH_0, rank 0
958 13:29:45.668589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 13:29:45.668686 ==
960 13:29:45.668780 DQS Delay:
961 13:29:45.671726 DQS0 = 0, DQS1 = 0
962 13:29:45.671834 DQM Delay:
963 13:29:45.674926 DQM0 = 89, DQM1 = 75
964 13:29:45.675022 DQ Delay:
965 13:29:45.678772 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85
966 13:29:45.682021 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
967 13:29:45.685089 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
968 13:29:45.688155 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
969 13:29:45.688231
970 13:29:45.688288
971 13:29:45.688342 ==
972 13:29:45.691833 Dram Type= 6, Freq= 0, CH_0, rank 0
973 13:29:45.695031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 13:29:45.695107 ==
975 13:29:45.698260
976 13:29:45.698335
977 13:29:45.698393 TX Vref Scan disable
978 13:29:45.701978 == TX Byte 0 ==
979 13:29:45.705067 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
980 13:29:45.708576 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
981 13:29:45.711800 == TX Byte 1 ==
982 13:29:45.714829 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
983 13:29:45.718441 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
984 13:29:45.718517 ==
985 13:29:45.721610 Dram Type= 6, Freq= 0, CH_0, rank 0
986 13:29:45.728343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 13:29:45.728421 ==
988 13:29:45.740069 TX Vref=22, minBit 1, minWin=26, winSum=437
989 13:29:45.743315 TX Vref=24, minBit 0, minWin=27, winSum=440
990 13:29:45.746593 TX Vref=26, minBit 1, minWin=27, winSum=449
991 13:29:45.750138 TX Vref=28, minBit 2, minWin=27, winSum=450
992 13:29:45.753129 TX Vref=30, minBit 1, minWin=27, winSum=446
993 13:29:45.756684 TX Vref=32, minBit 1, minWin=27, winSum=447
994 13:29:45.763733 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 28
995 13:29:45.763811
996 13:29:45.766887 Final TX Range 1 Vref 28
997 13:29:45.766953
998 13:29:45.767010 ==
999 13:29:45.770074 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 13:29:45.773249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 13:29:45.773317 ==
1002 13:29:45.773376
1003 13:29:45.773429
1004 13:29:45.776857 TX Vref Scan disable
1005 13:29:45.780189 == TX Byte 0 ==
1006 13:29:45.783361 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1007 13:29:45.787080 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1008 13:29:45.790307 == TX Byte 1 ==
1009 13:29:45.793394 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1010 13:29:45.796533 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1011 13:29:45.796600
1012 13:29:45.800230 [DATLAT]
1013 13:29:45.800294 Freq=800, CH0 RK0
1014 13:29:45.800347
1015 13:29:45.803452 DATLAT Default: 0xa
1016 13:29:45.803515 0, 0xFFFF, sum = 0
1017 13:29:45.806491 1, 0xFFFF, sum = 0
1018 13:29:45.806554 2, 0xFFFF, sum = 0
1019 13:29:45.810178 3, 0xFFFF, sum = 0
1020 13:29:45.810244 4, 0xFFFF, sum = 0
1021 13:29:45.813126 5, 0xFFFF, sum = 0
1022 13:29:45.813233 6, 0xFFFF, sum = 0
1023 13:29:45.816632 7, 0xFFFF, sum = 0
1024 13:29:45.816697 8, 0xFFFF, sum = 0
1025 13:29:45.820105 9, 0x0, sum = 1
1026 13:29:45.820176 10, 0x0, sum = 2
1027 13:29:45.823503 11, 0x0, sum = 3
1028 13:29:45.823568 12, 0x0, sum = 4
1029 13:29:45.826815 best_step = 10
1030 13:29:45.826882
1031 13:29:45.826937 ==
1032 13:29:45.830297 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 13:29:45.833459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 13:29:45.833527 ==
1035 13:29:45.836558 RX Vref Scan: 1
1036 13:29:45.836622
1037 13:29:45.836675 Set Vref Range= 32 -> 127
1038 13:29:45.836726
1039 13:29:45.839708 RX Vref 32 -> 127, step: 1
1040 13:29:45.839772
1041 13:29:45.843054 RX Delay -111 -> 252, step: 8
1042 13:29:45.843153
1043 13:29:45.846353 Set Vref, RX VrefLevel [Byte0]: 32
1044 13:29:45.849607 [Byte1]: 32
1045 13:29:45.849676
1046 13:29:45.853431 Set Vref, RX VrefLevel [Byte0]: 33
1047 13:29:45.856488 [Byte1]: 33
1048 13:29:45.860138
1049 13:29:45.860204 Set Vref, RX VrefLevel [Byte0]: 34
1050 13:29:45.863815 [Byte1]: 34
1051 13:29:45.868113
1052 13:29:45.868180 Set Vref, RX VrefLevel [Byte0]: 35
1053 13:29:45.871545 [Byte1]: 35
1054 13:29:45.875870
1055 13:29:45.875935 Set Vref, RX VrefLevel [Byte0]: 36
1056 13:29:45.879128 [Byte1]: 36
1057 13:29:45.883554
1058 13:29:45.883618 Set Vref, RX VrefLevel [Byte0]: 37
1059 13:29:45.886615 [Byte1]: 37
1060 13:29:45.890973
1061 13:29:45.891040 Set Vref, RX VrefLevel [Byte0]: 38
1062 13:29:45.894134 [Byte1]: 38
1063 13:29:45.898573
1064 13:29:45.898639 Set Vref, RX VrefLevel [Byte0]: 39
1065 13:29:45.901626 [Byte1]: 39
1066 13:29:45.906149
1067 13:29:45.906217 Set Vref, RX VrefLevel [Byte0]: 40
1068 13:29:45.909338 [Byte1]: 40
1069 13:29:45.913672
1070 13:29:45.913762 Set Vref, RX VrefLevel [Byte0]: 41
1071 13:29:45.916954 [Byte1]: 41
1072 13:29:45.921298
1073 13:29:45.921365 Set Vref, RX VrefLevel [Byte0]: 42
1074 13:29:45.928237 [Byte1]: 42
1075 13:29:45.928305
1076 13:29:45.931539 Set Vref, RX VrefLevel [Byte0]: 43
1077 13:29:45.934694 [Byte1]: 43
1078 13:29:45.934774
1079 13:29:45.937726 Set Vref, RX VrefLevel [Byte0]: 44
1080 13:29:45.941083 [Byte1]: 44
1081 13:29:45.944639
1082 13:29:45.944703 Set Vref, RX VrefLevel [Byte0]: 45
1083 13:29:45.948094 [Byte1]: 45
1084 13:29:45.952371
1085 13:29:45.952444 Set Vref, RX VrefLevel [Byte0]: 46
1086 13:29:45.955284 [Byte1]: 46
1087 13:29:45.959726
1088 13:29:45.959823 Set Vref, RX VrefLevel [Byte0]: 47
1089 13:29:45.962941 [Byte1]: 47
1090 13:29:45.967540
1091 13:29:45.967608 Set Vref, RX VrefLevel [Byte0]: 48
1092 13:29:45.970552 [Byte1]: 48
1093 13:29:45.974835
1094 13:29:45.974899 Set Vref, RX VrefLevel [Byte0]: 49
1095 13:29:45.978306 [Byte1]: 49
1096 13:29:45.982627
1097 13:29:45.982727 Set Vref, RX VrefLevel [Byte0]: 50
1098 13:29:45.985895 [Byte1]: 50
1099 13:29:45.990579
1100 13:29:45.990654 Set Vref, RX VrefLevel [Byte0]: 51
1101 13:29:45.993869 [Byte1]: 51
1102 13:29:45.998063
1103 13:29:45.998139 Set Vref, RX VrefLevel [Byte0]: 52
1104 13:29:46.001190 [Byte1]: 52
1105 13:29:46.005663
1106 13:29:46.005738 Set Vref, RX VrefLevel [Byte0]: 53
1107 13:29:46.008863 [Byte1]: 53
1108 13:29:46.013144
1109 13:29:46.013226 Set Vref, RX VrefLevel [Byte0]: 54
1110 13:29:46.016545 [Byte1]: 54
1111 13:29:46.020903
1112 13:29:46.020977 Set Vref, RX VrefLevel [Byte0]: 55
1113 13:29:46.024110 [Byte1]: 55
1114 13:29:46.028563
1115 13:29:46.028638 Set Vref, RX VrefLevel [Byte0]: 56
1116 13:29:46.031727 [Byte1]: 56
1117 13:29:46.036134
1118 13:29:46.036208 Set Vref, RX VrefLevel [Byte0]: 57
1119 13:29:46.039367 [Byte1]: 57
1120 13:29:46.044169
1121 13:29:46.044244 Set Vref, RX VrefLevel [Byte0]: 58
1122 13:29:46.047252 [Byte1]: 58
1123 13:29:46.051363
1124 13:29:46.051437 Set Vref, RX VrefLevel [Byte0]: 59
1125 13:29:46.055106 [Byte1]: 59
1126 13:29:46.058880
1127 13:29:46.058955 Set Vref, RX VrefLevel [Byte0]: 60
1128 13:29:46.062618 [Byte1]: 60
1129 13:29:46.066922
1130 13:29:46.066996 Set Vref, RX VrefLevel [Byte0]: 61
1131 13:29:46.070118 [Byte1]: 61
1132 13:29:46.074374
1133 13:29:46.074472 Set Vref, RX VrefLevel [Byte0]: 62
1134 13:29:46.077512 [Byte1]: 62
1135 13:29:46.081943
1136 13:29:46.082018 Set Vref, RX VrefLevel [Byte0]: 63
1137 13:29:46.085454 [Byte1]: 63
1138 13:29:46.090006
1139 13:29:46.090081 Set Vref, RX VrefLevel [Byte0]: 64
1140 13:29:46.093055 [Byte1]: 64
1141 13:29:46.097076
1142 13:29:46.097193 Set Vref, RX VrefLevel [Byte0]: 65
1143 13:29:46.100401 [Byte1]: 65
1144 13:29:46.104849
1145 13:29:46.104938 Set Vref, RX VrefLevel [Byte0]: 66
1146 13:29:46.108286 [Byte1]: 66
1147 13:29:46.112817
1148 13:29:46.112929 Set Vref, RX VrefLevel [Byte0]: 67
1149 13:29:46.115742 [Byte1]: 67
1150 13:29:46.120336
1151 13:29:46.120413 Set Vref, RX VrefLevel [Byte0]: 68
1152 13:29:46.123953 [Byte1]: 68
1153 13:29:46.127678
1154 13:29:46.127762 Set Vref, RX VrefLevel [Byte0]: 69
1155 13:29:46.131402 [Byte1]: 69
1156 13:29:46.135824
1157 13:29:46.135893 Set Vref, RX VrefLevel [Byte0]: 70
1158 13:29:46.138959 [Byte1]: 70
1159 13:29:46.143327
1160 13:29:46.143396 Set Vref, RX VrefLevel [Byte0]: 71
1161 13:29:46.146480 [Byte1]: 71
1162 13:29:46.151140
1163 13:29:46.151214 Final RX Vref Byte 0 = 57 to rank0
1164 13:29:46.154147 Final RX Vref Byte 1 = 60 to rank0
1165 13:29:46.157315 Final RX Vref Byte 0 = 57 to rank1
1166 13:29:46.161054 Final RX Vref Byte 1 = 60 to rank1==
1167 13:29:46.164239 Dram Type= 6, Freq= 0, CH_0, rank 0
1168 13:29:46.170502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1169 13:29:46.170578 ==
1170 13:29:46.170636 DQS Delay:
1171 13:29:46.170691 DQS0 = 0, DQS1 = 0
1172 13:29:46.174071 DQM Delay:
1173 13:29:46.174146 DQM0 = 88, DQM1 = 76
1174 13:29:46.177164 DQ Delay:
1175 13:29:46.180937 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1176 13:29:46.184036 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1177 13:29:46.187112 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =72
1178 13:29:46.190854 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1179 13:29:46.190929
1180 13:29:46.190987
1181 13:29:46.197390 [DQSOSCAuto] RK0, (LSB)MR18= 0x322b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1182 13:29:46.201004 CH0 RK0: MR19=606, MR18=322B
1183 13:29:46.207146 CH0_RK0: MR19=0x606, MR18=0x322B, DQSOSC=397, MR23=63, INC=93, DEC=62
1184 13:29:46.207222
1185 13:29:46.210625 ----->DramcWriteLeveling(PI) begin...
1186 13:29:46.210702 ==
1187 13:29:46.214101 Dram Type= 6, Freq= 0, CH_0, rank 1
1188 13:29:46.216913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1189 13:29:46.217012 ==
1190 13:29:46.220776 Write leveling (Byte 0): 33 => 33
1191 13:29:46.223792 Write leveling (Byte 1): 29 => 29
1192 13:29:46.227492 DramcWriteLeveling(PI) end<-----
1193 13:29:46.227567
1194 13:29:46.227624 ==
1195 13:29:46.230726 Dram Type= 6, Freq= 0, CH_0, rank 1
1196 13:29:46.234167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1197 13:29:46.234245 ==
1198 13:29:46.237117 [Gating] SW mode calibration
1199 13:29:46.243792 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1200 13:29:46.250589 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1201 13:29:46.254214 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1202 13:29:46.257415 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1203 13:29:46.264189 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 13:29:46.267332 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 13:29:46.270379 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 13:29:46.277418 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 13:29:46.280413 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 13:29:46.283540 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 13:29:46.290516 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 13:29:46.293719 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 13:29:46.337922 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 13:29:46.338234 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 13:29:46.338319 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 13:29:46.338387 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 13:29:46.338463 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 13:29:46.338540 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 13:29:46.339177 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 13:29:46.339472 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1219 13:29:46.339559 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1220 13:29:46.339814 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 13:29:46.382502 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 13:29:46.382911 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 13:29:46.383211 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 13:29:46.383483 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 13:29:46.384072 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 13:29:46.384399 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
1227 13:29:46.384778 0 9 8 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
1228 13:29:46.385162 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1229 13:29:46.385495 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1230 13:29:46.385800 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1231 13:29:46.399820 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1232 13:29:46.400586 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1233 13:29:46.401029 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 13:29:46.401633 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
1235 13:29:46.403758 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
1236 13:29:46.406991 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
1237 13:29:46.413781 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 13:29:46.416927 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 13:29:46.420385 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 13:29:46.426740 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 13:29:46.429921 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 13:29:46.433233 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1243 13:29:46.440082 0 11 8 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
1244 13:29:46.443559 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1245 13:29:46.446559 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1246 13:29:46.453381 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1247 13:29:46.456587 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1248 13:29:46.460329 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1249 13:29:46.466761 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 13:29:46.470458 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1251 13:29:46.473484 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1252 13:29:46.480170 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 13:29:46.483635 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 13:29:46.486923 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 13:29:46.493524 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 13:29:46.496563 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 13:29:46.499778 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 13:29:46.503258 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 13:29:46.510408 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 13:29:46.513433 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 13:29:46.516521 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 13:29:46.523315 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 13:29:46.526470 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 13:29:46.529636 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 13:29:46.536508 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 13:29:46.539665 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1267 13:29:46.543409 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1268 13:29:46.546587 Total UI for P1: 0, mck2ui 16
1269 13:29:46.550195 best dqsien dly found for B0: ( 0, 14, 4)
1270 13:29:46.556438 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 13:29:46.556987 Total UI for P1: 0, mck2ui 16
1272 13:29:46.563097 best dqsien dly found for B1: ( 0, 14, 10)
1273 13:29:46.566197 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1274 13:29:46.569760 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1275 13:29:46.570131
1276 13:29:46.573314 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1277 13:29:46.576207 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1278 13:29:46.579879 [Gating] SW calibration Done
1279 13:29:46.580362 ==
1280 13:29:46.583175 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 13:29:46.586330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 13:29:46.586850 ==
1283 13:29:46.589869 RX Vref Scan: 0
1284 13:29:46.590374
1285 13:29:46.590823 RX Vref 0 -> 0, step: 1
1286 13:29:46.591250
1287 13:29:46.592851 RX Delay -130 -> 252, step: 16
1288 13:29:46.599719 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1289 13:29:46.602649 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1290 13:29:46.606117 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1291 13:29:46.609396 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1292 13:29:46.612674 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1293 13:29:46.619417 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1294 13:29:46.622865 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1295 13:29:46.625688 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1296 13:29:46.629479 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1297 13:29:46.632612 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1298 13:29:46.639581 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1299 13:29:46.642723 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1300 13:29:46.645918 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1301 13:29:46.649058 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1302 13:29:46.652225 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1303 13:29:46.659012 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1304 13:29:46.659503 ==
1305 13:29:46.662687 Dram Type= 6, Freq= 0, CH_0, rank 1
1306 13:29:46.665533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1307 13:29:46.666206 ==
1308 13:29:46.666769 DQS Delay:
1309 13:29:46.669231 DQS0 = 0, DQS1 = 0
1310 13:29:46.669802 DQM Delay:
1311 13:29:46.672350 DQM0 = 85, DQM1 = 76
1312 13:29:46.672938 DQ Delay:
1313 13:29:46.675415 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1314 13:29:46.678855 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =93
1315 13:29:46.682359 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1316 13:29:46.685402 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1317 13:29:46.686035
1318 13:29:46.686593
1319 13:29:46.687118 ==
1320 13:29:46.688732 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 13:29:46.692315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 13:29:46.692724 ==
1323 13:29:46.695211
1324 13:29:46.695491
1325 13:29:46.695763 TX Vref Scan disable
1326 13:29:46.699067 == TX Byte 0 ==
1327 13:29:46.702272 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1328 13:29:46.705554 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1329 13:29:46.708680 == TX Byte 1 ==
1330 13:29:46.711867 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1331 13:29:46.715422 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1332 13:29:46.718421 ==
1333 13:29:46.718723 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 13:29:46.725123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 13:29:46.725460 ==
1336 13:29:46.737362 TX Vref=22, minBit 0, minWin=27, winSum=440
1337 13:29:46.741053 TX Vref=24, minBit 1, minWin=27, winSum=444
1338 13:29:46.743855 TX Vref=26, minBit 2, minWin=27, winSum=446
1339 13:29:46.747585 TX Vref=28, minBit 2, minWin=27, winSum=449
1340 13:29:46.750785 TX Vref=30, minBit 4, minWin=27, winSum=448
1341 13:29:46.757644 TX Vref=32, minBit 4, minWin=27, winSum=448
1342 13:29:46.760865 [TxChooseVref] Worse bit 2, Min win 27, Win sum 449, Final Vref 28
1343 13:29:46.760958
1344 13:29:46.763893 Final TX Range 1 Vref 28
1345 13:29:46.764021
1346 13:29:46.764152 ==
1347 13:29:46.767568 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 13:29:46.770704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 13:29:46.770800 ==
1350 13:29:46.774129
1351 13:29:46.774219
1352 13:29:46.774300 TX Vref Scan disable
1353 13:29:46.777514 == TX Byte 0 ==
1354 13:29:46.781130 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1355 13:29:46.787580 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1356 13:29:46.787663 == TX Byte 1 ==
1357 13:29:46.790697 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1358 13:29:46.796945 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1359 13:29:46.797038
1360 13:29:46.797123 [DATLAT]
1361 13:29:46.797245 Freq=800, CH0 RK1
1362 13:29:46.797318
1363 13:29:46.800638 DATLAT Default: 0xa
1364 13:29:46.800729 0, 0xFFFF, sum = 0
1365 13:29:46.803765 1, 0xFFFF, sum = 0
1366 13:29:46.806991 2, 0xFFFF, sum = 0
1367 13:29:46.807082 3, 0xFFFF, sum = 0
1368 13:29:46.810924 4, 0xFFFF, sum = 0
1369 13:29:46.811020 5, 0xFFFF, sum = 0
1370 13:29:46.814135 6, 0xFFFF, sum = 0
1371 13:29:46.814230 7, 0xFFFF, sum = 0
1372 13:29:46.817283 8, 0xFFFF, sum = 0
1373 13:29:46.817375 9, 0x0, sum = 1
1374 13:29:46.820389 10, 0x0, sum = 2
1375 13:29:46.820481 11, 0x0, sum = 3
1376 13:29:46.820564 12, 0x0, sum = 4
1377 13:29:46.823907 best_step = 10
1378 13:29:46.823995
1379 13:29:46.824077 ==
1380 13:29:46.827081 Dram Type= 6, Freq= 0, CH_0, rank 1
1381 13:29:46.830317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 13:29:46.830408 ==
1383 13:29:46.834057 RX Vref Scan: 0
1384 13:29:46.834151
1385 13:29:46.837115 RX Vref 0 -> 0, step: 1
1386 13:29:46.837233
1387 13:29:46.837320 RX Delay -95 -> 252, step: 8
1388 13:29:46.843940 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1389 13:29:46.847521 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1390 13:29:46.850994 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1391 13:29:46.853945 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1392 13:29:46.857150 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1393 13:29:46.864043 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1394 13:29:46.867104 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1395 13:29:46.870964 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1396 13:29:46.874104 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1397 13:29:46.877370 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1398 13:29:46.884138 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1399 13:29:46.887519 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1400 13:29:46.890757 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1401 13:29:46.893915 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1402 13:29:46.900527 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1403 13:29:46.903800 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1404 13:29:46.903934 ==
1405 13:29:46.907065 Dram Type= 6, Freq= 0, CH_0, rank 1
1406 13:29:46.910902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1407 13:29:46.910993 ==
1408 13:29:46.911074 DQS Delay:
1409 13:29:46.914096 DQS0 = 0, DQS1 = 0
1410 13:29:46.914162 DQM Delay:
1411 13:29:46.917252 DQM0 = 86, DQM1 = 76
1412 13:29:46.917340 DQ Delay:
1413 13:29:46.920436 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1414 13:29:46.924179 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1415 13:29:46.927181 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1416 13:29:46.930325 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1417 13:29:46.930417
1418 13:29:46.930500
1419 13:29:46.940311 [DQSOSCAuto] RK1, (LSB)MR18= 0x2623, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1420 13:29:46.940406 CH0 RK1: MR19=606, MR18=2623
1421 13:29:46.947249 CH0_RK1: MR19=0x606, MR18=0x2623, DQSOSC=400, MR23=63, INC=92, DEC=61
1422 13:29:46.950530 [RxdqsGatingPostProcess] freq 800
1423 13:29:46.957122 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1424 13:29:46.960387 Pre-setting of DQS Precalculation
1425 13:29:46.963364 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1426 13:29:46.963430 ==
1427 13:29:46.966968 Dram Type= 6, Freq= 0, CH_1, rank 0
1428 13:29:46.970383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1429 13:29:46.973455 ==
1430 13:29:46.976690 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1431 13:29:46.983565 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1432 13:29:46.992396 [CA 0] Center 37 (6~68) winsize 63
1433 13:29:46.996018 [CA 1] Center 37 (6~68) winsize 63
1434 13:29:46.999037 [CA 2] Center 35 (5~65) winsize 61
1435 13:29:47.002498 [CA 3] Center 34 (4~65) winsize 62
1436 13:29:47.006009 [CA 4] Center 34 (4~65) winsize 62
1437 13:29:47.008857 [CA 5] Center 34 (3~65) winsize 63
1438 13:29:47.008945
1439 13:29:47.012385 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1440 13:29:47.012472
1441 13:29:47.015716 [CATrainingPosCal] consider 1 rank data
1442 13:29:47.018996 u2DelayCellTimex100 = 270/100 ps
1443 13:29:47.022477 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1444 13:29:47.028780 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1445 13:29:47.032428 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1446 13:29:47.035447 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1447 13:29:47.038656 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1448 13:29:47.042384 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1449 13:29:47.042450
1450 13:29:47.045523 CA PerBit enable=1, Macro0, CA PI delay=34
1451 13:29:47.045612
1452 13:29:47.049219 [CBTSetCACLKResult] CA Dly = 34
1453 13:29:47.049284 CS Dly: 4 (0~35)
1454 13:29:47.052310 ==
1455 13:29:47.055458 Dram Type= 6, Freq= 0, CH_1, rank 1
1456 13:29:47.059068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1457 13:29:47.059132 ==
1458 13:29:47.061963 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1459 13:29:47.068837 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1460 13:29:47.078573 [CA 0] Center 36 (6~67) winsize 62
1461 13:29:47.082044 [CA 1] Center 36 (6~67) winsize 62
1462 13:29:47.085119 [CA 2] Center 34 (4~65) winsize 62
1463 13:29:47.088351 [CA 3] Center 33 (3~64) winsize 62
1464 13:29:47.092109 [CA 4] Center 34 (3~65) winsize 63
1465 13:29:47.095353 [CA 5] Center 34 (3~65) winsize 63
1466 13:29:47.095417
1467 13:29:47.098465 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1468 13:29:47.098551
1469 13:29:47.101597 [CATrainingPosCal] consider 2 rank data
1470 13:29:47.105475 u2DelayCellTimex100 = 270/100 ps
1471 13:29:47.108461 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1472 13:29:47.111565 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1473 13:29:47.118449 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1474 13:29:47.122050 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1475 13:29:47.125061 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1476 13:29:47.128592 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1477 13:29:47.128656
1478 13:29:47.131943 CA PerBit enable=1, Macro0, CA PI delay=34
1479 13:29:47.132035
1480 13:29:47.135109 [CBTSetCACLKResult] CA Dly = 34
1481 13:29:47.135245 CS Dly: 5 (0~37)
1482 13:29:47.135336
1483 13:29:47.141469 ----->DramcWriteLeveling(PI) begin...
1484 13:29:47.141539 ==
1485 13:29:47.145084 Dram Type= 6, Freq= 0, CH_1, rank 0
1486 13:29:47.148122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1487 13:29:47.148186 ==
1488 13:29:47.151900 Write leveling (Byte 0): 25 => 25
1489 13:29:47.155065 Write leveling (Byte 1): 25 => 25
1490 13:29:47.158408 DramcWriteLeveling(PI) end<-----
1491 13:29:47.158499
1492 13:29:47.158588 ==
1493 13:29:47.161467 Dram Type= 6, Freq= 0, CH_1, rank 0
1494 13:29:47.164537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1495 13:29:47.164623 ==
1496 13:29:47.168398 [Gating] SW mode calibration
1497 13:29:47.174765 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1498 13:29:47.181051 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1499 13:29:47.184823 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1500 13:29:47.187861 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1501 13:29:47.194690 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1502 13:29:47.197933 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 13:29:47.201072 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 13:29:47.207377 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 13:29:47.211100 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 13:29:47.214187 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 13:29:47.221061 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 13:29:47.224765 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 13:29:47.228002 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 13:29:47.234210 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 13:29:47.237936 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 13:29:47.240912 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 13:29:47.247513 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 13:29:47.251076 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 13:29:47.254218 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 13:29:47.257789 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1517 13:29:47.263952 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 13:29:47.267735 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 13:29:47.270692 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 13:29:47.277752 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 13:29:47.280950 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 13:29:47.284205 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 13:29:47.290487 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 13:29:47.293695 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 13:29:47.297411 0 9 8 | B1->B0 | 2f2f 3434 | 1 0 | (1 1) (0 0)
1526 13:29:47.304032 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1527 13:29:47.307404 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1528 13:29:47.310336 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1529 13:29:47.317058 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1530 13:29:47.320764 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1531 13:29:47.323986 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1532 13:29:47.330571 0 10 4 | B1->B0 | 3030 2f2f | 1 1 | (1 1) (0 1)
1533 13:29:47.333812 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
1534 13:29:47.337540 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 13:29:47.343850 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 13:29:47.346930 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 13:29:47.350672 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 13:29:47.356737 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 13:29:47.360261 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 13:29:47.363610 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1541 13:29:47.370594 0 11 8 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
1542 13:29:47.373364 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1543 13:29:47.377024 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1544 13:29:47.383287 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1545 13:29:47.386437 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1546 13:29:47.389670 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 13:29:47.396673 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1548 13:29:47.399740 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1549 13:29:47.403003 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1550 13:29:47.409389 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 13:29:47.412974 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 13:29:47.415907 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 13:29:47.423252 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 13:29:47.426092 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 13:29:47.429654 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 13:29:47.436322 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 13:29:47.439288 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 13:29:47.443008 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 13:29:47.449298 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 13:29:47.452470 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 13:29:47.456169 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 13:29:47.462357 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 13:29:47.466127 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 13:29:47.469356 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1565 13:29:47.472315 Total UI for P1: 0, mck2ui 16
1566 13:29:47.475717 best dqsien dly found for B0: ( 0, 14, 2)
1567 13:29:47.482461 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1568 13:29:47.485907 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 13:29:47.489315 Total UI for P1: 0, mck2ui 16
1570 13:29:47.492378 best dqsien dly found for B1: ( 0, 14, 6)
1571 13:29:47.495836 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1572 13:29:47.499016 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1573 13:29:47.499107
1574 13:29:47.502125 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1575 13:29:47.505433 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1576 13:29:47.509333 [Gating] SW calibration Done
1577 13:29:47.509424 ==
1578 13:29:47.512478 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 13:29:47.515646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 13:29:47.515736 ==
1581 13:29:47.518929 RX Vref Scan: 0
1582 13:29:47.519019
1583 13:29:47.522035 RX Vref 0 -> 0, step: 1
1584 13:29:47.522122
1585 13:29:47.522201 RX Delay -130 -> 252, step: 16
1586 13:29:47.529109 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1587 13:29:47.532135 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1588 13:29:47.535853 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1589 13:29:47.538843 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1590 13:29:47.542431 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1591 13:29:47.549065 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1592 13:29:47.551997 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1593 13:29:47.555488 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1594 13:29:47.558778 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1595 13:29:47.561810 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1596 13:29:47.568791 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1597 13:29:47.571886 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1598 13:29:47.575063 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1599 13:29:47.578824 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1600 13:29:47.585399 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1601 13:29:47.588857 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1602 13:29:47.588978 ==
1603 13:29:47.592077 Dram Type= 6, Freq= 0, CH_1, rank 0
1604 13:29:47.595150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1605 13:29:47.595242 ==
1606 13:29:47.595325 DQS Delay:
1607 13:29:47.598680 DQS0 = 0, DQS1 = 0
1608 13:29:47.598767 DQM Delay:
1609 13:29:47.601468 DQM0 = 86, DQM1 = 79
1610 13:29:47.601557 DQ Delay:
1611 13:29:47.604820 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1612 13:29:47.608601 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1613 13:29:47.611696 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1614 13:29:47.614931 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1615 13:29:47.614999
1616 13:29:47.615055
1617 13:29:47.615107 ==
1618 13:29:47.618611 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 13:29:47.625020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 13:29:47.625130 ==
1621 13:29:47.625286
1622 13:29:47.625392
1623 13:29:47.625496 TX Vref Scan disable
1624 13:29:47.628163 == TX Byte 0 ==
1625 13:29:47.631933 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1626 13:29:47.638349 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1627 13:29:47.638416 == TX Byte 1 ==
1628 13:29:47.641415 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1629 13:29:47.648291 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1630 13:29:47.648375 ==
1631 13:29:47.651500 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 13:29:47.654635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 13:29:47.654726 ==
1634 13:29:47.667439 TX Vref=22, minBit 2, minWin=26, winSum=443
1635 13:29:47.670515 TX Vref=24, minBit 4, minWin=27, winSum=445
1636 13:29:47.674027 TX Vref=26, minBit 4, minWin=27, winSum=449
1637 13:29:47.677572 TX Vref=28, minBit 0, minWin=27, winSum=450
1638 13:29:47.680830 TX Vref=30, minBit 2, minWin=27, winSum=455
1639 13:29:47.684034 TX Vref=32, minBit 0, minWin=27, winSum=454
1640 13:29:47.690630 [TxChooseVref] Worse bit 2, Min win 27, Win sum 455, Final Vref 30
1641 13:29:47.690721
1642 13:29:47.693608 Final TX Range 1 Vref 30
1643 13:29:47.693693
1644 13:29:47.693751 ==
1645 13:29:47.697387 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 13:29:47.700534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 13:29:47.700622 ==
1648 13:29:47.703643
1649 13:29:47.703730
1650 13:29:47.703814 TX Vref Scan disable
1651 13:29:47.707610 == TX Byte 0 ==
1652 13:29:47.710640 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1653 13:29:47.717027 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1654 13:29:47.717130 == TX Byte 1 ==
1655 13:29:47.720482 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1656 13:29:47.727329 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1657 13:29:47.727425
1658 13:29:47.727515 [DATLAT]
1659 13:29:47.727597 Freq=800, CH1 RK0
1660 13:29:47.727678
1661 13:29:47.730423 DATLAT Default: 0xa
1662 13:29:47.730511 0, 0xFFFF, sum = 0
1663 13:29:47.733507 1, 0xFFFF, sum = 0
1664 13:29:47.733572 2, 0xFFFF, sum = 0
1665 13:29:47.737315 3, 0xFFFF, sum = 0
1666 13:29:47.740458 4, 0xFFFF, sum = 0
1667 13:29:47.740546 5, 0xFFFF, sum = 0
1668 13:29:47.743561 6, 0xFFFF, sum = 0
1669 13:29:47.743652 7, 0xFFFF, sum = 0
1670 13:29:47.747335 8, 0xFFFF, sum = 0
1671 13:29:47.747433 9, 0x0, sum = 1
1672 13:29:47.750051 10, 0x0, sum = 2
1673 13:29:47.750146 11, 0x0, sum = 3
1674 13:29:47.750231 12, 0x0, sum = 4
1675 13:29:47.753618 best_step = 10
1676 13:29:47.753705
1677 13:29:47.753783 ==
1678 13:29:47.756885 Dram Type= 6, Freq= 0, CH_1, rank 0
1679 13:29:47.760069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1680 13:29:47.760156 ==
1681 13:29:47.763368 RX Vref Scan: 1
1682 13:29:47.763453
1683 13:29:47.767119 Set Vref Range= 32 -> 127
1684 13:29:47.767208
1685 13:29:47.767288 RX Vref 32 -> 127, step: 1
1686 13:29:47.767367
1687 13:29:47.770154 RX Delay -95 -> 252, step: 8
1688 13:29:47.770239
1689 13:29:47.773719 Set Vref, RX VrefLevel [Byte0]: 32
1690 13:29:47.776644 [Byte1]: 32
1691 13:29:47.780062
1692 13:29:47.780153 Set Vref, RX VrefLevel [Byte0]: 33
1693 13:29:47.783496 [Byte1]: 33
1694 13:29:47.787383
1695 13:29:47.787471 Set Vref, RX VrefLevel [Byte0]: 34
1696 13:29:47.791049 [Byte1]: 34
1697 13:29:47.795447
1698 13:29:47.795535 Set Vref, RX VrefLevel [Byte0]: 35
1699 13:29:47.798415 [Byte1]: 35
1700 13:29:47.802508
1701 13:29:47.802599 Set Vref, RX VrefLevel [Byte0]: 36
1702 13:29:47.806198 [Byte1]: 36
1703 13:29:47.810228
1704 13:29:47.810292 Set Vref, RX VrefLevel [Byte0]: 37
1705 13:29:47.813996 [Byte1]: 37
1706 13:29:47.817772
1707 13:29:47.817835 Set Vref, RX VrefLevel [Byte0]: 38
1708 13:29:47.820944 [Byte1]: 38
1709 13:29:47.825385
1710 13:29:47.825449 Set Vref, RX VrefLevel [Byte0]: 39
1711 13:29:47.828525 [Byte1]: 39
1712 13:29:47.833036
1713 13:29:47.833107 Set Vref, RX VrefLevel [Byte0]: 40
1714 13:29:47.836491 [Byte1]: 40
1715 13:29:47.840677
1716 13:29:47.840750 Set Vref, RX VrefLevel [Byte0]: 41
1717 13:29:47.843907 [Byte1]: 41
1718 13:29:47.848300
1719 13:29:47.848392 Set Vref, RX VrefLevel [Byte0]: 42
1720 13:29:47.851404 [Byte1]: 42
1721 13:29:47.856216
1722 13:29:47.856287 Set Vref, RX VrefLevel [Byte0]: 43
1723 13:29:47.859162 [Byte1]: 43
1724 13:29:47.863416
1725 13:29:47.863500 Set Vref, RX VrefLevel [Byte0]: 44
1726 13:29:47.866547 [Byte1]: 44
1727 13:29:47.870940
1728 13:29:47.871025 Set Vref, RX VrefLevel [Byte0]: 45
1729 13:29:47.874119 [Byte1]: 45
1730 13:29:47.878709
1731 13:29:47.878795 Set Vref, RX VrefLevel [Byte0]: 46
1732 13:29:47.882194 [Byte1]: 46
1733 13:29:47.886043
1734 13:29:47.886159 Set Vref, RX VrefLevel [Byte0]: 47
1735 13:29:47.889893 [Byte1]: 47
1736 13:29:47.894062
1737 13:29:47.894125 Set Vref, RX VrefLevel [Byte0]: 48
1738 13:29:47.896904 [Byte1]: 48
1739 13:29:47.901542
1740 13:29:47.901602 Set Vref, RX VrefLevel [Byte0]: 49
1741 13:29:47.904985 [Byte1]: 49
1742 13:29:47.908994
1743 13:29:47.909053 Set Vref, RX VrefLevel [Byte0]: 50
1744 13:29:47.912800 [Byte1]: 50
1745 13:29:47.916968
1746 13:29:47.917077 Set Vref, RX VrefLevel [Byte0]: 51
1747 13:29:47.920082 [Byte1]: 51
1748 13:29:47.924505
1749 13:29:47.924564 Set Vref, RX VrefLevel [Byte0]: 52
1750 13:29:47.927671 [Byte1]: 52
1751 13:29:47.932041
1752 13:29:47.932130 Set Vref, RX VrefLevel [Byte0]: 53
1753 13:29:47.935163 [Byte1]: 53
1754 13:29:47.939643
1755 13:29:47.939726 Set Vref, RX VrefLevel [Byte0]: 54
1756 13:29:47.942945 [Byte1]: 54
1757 13:29:47.947117
1758 13:29:47.947199 Set Vref, RX VrefLevel [Byte0]: 55
1759 13:29:47.950638 [Byte1]: 55
1760 13:29:47.954514
1761 13:29:47.954579 Set Vref, RX VrefLevel [Byte0]: 56
1762 13:29:47.958106 [Byte1]: 56
1763 13:29:47.962043
1764 13:29:47.962145 Set Vref, RX VrefLevel [Byte0]: 57
1765 13:29:47.965601 [Byte1]: 57
1766 13:29:47.969677
1767 13:29:47.969764 Set Vref, RX VrefLevel [Byte0]: 58
1768 13:29:47.973368 [Byte1]: 58
1769 13:29:47.977684
1770 13:29:47.977772 Set Vref, RX VrefLevel [Byte0]: 59
1771 13:29:47.980790 [Byte1]: 59
1772 13:29:47.985025
1773 13:29:47.985115 Set Vref, RX VrefLevel [Byte0]: 60
1774 13:29:47.988155 [Byte1]: 60
1775 13:29:47.992599
1776 13:29:47.992689 Set Vref, RX VrefLevel [Byte0]: 61
1777 13:29:47.995818 [Byte1]: 61
1778 13:29:48.000056
1779 13:29:48.000147 Set Vref, RX VrefLevel [Byte0]: 62
1780 13:29:48.003739 [Byte1]: 62
1781 13:29:48.008044
1782 13:29:48.008131 Set Vref, RX VrefLevel [Byte0]: 63
1783 13:29:48.010942 [Byte1]: 63
1784 13:29:48.015378
1785 13:29:48.015440 Set Vref, RX VrefLevel [Byte0]: 64
1786 13:29:48.018738 [Byte1]: 64
1787 13:29:48.023304
1788 13:29:48.023371 Set Vref, RX VrefLevel [Byte0]: 65
1789 13:29:48.026150 [Byte1]: 65
1790 13:29:48.030498
1791 13:29:48.030586 Set Vref, RX VrefLevel [Byte0]: 66
1792 13:29:48.033719 [Byte1]: 66
1793 13:29:48.038154
1794 13:29:48.038216 Set Vref, RX VrefLevel [Byte0]: 67
1795 13:29:48.041411 [Byte1]: 67
1796 13:29:48.045788
1797 13:29:48.045871 Set Vref, RX VrefLevel [Byte0]: 68
1798 13:29:48.048996 [Byte1]: 68
1799 13:29:48.053514
1800 13:29:48.053573 Set Vref, RX VrefLevel [Byte0]: 69
1801 13:29:48.056605 [Byte1]: 69
1802 13:29:48.061028
1803 13:29:48.061111 Set Vref, RX VrefLevel [Byte0]: 70
1804 13:29:48.064191 [Byte1]: 70
1805 13:29:48.068833
1806 13:29:48.068916 Set Vref, RX VrefLevel [Byte0]: 71
1807 13:29:48.072028 [Byte1]: 71
1808 13:29:48.076278
1809 13:29:48.076360 Set Vref, RX VrefLevel [Byte0]: 72
1810 13:29:48.079398 [Byte1]: 72
1811 13:29:48.083532
1812 13:29:48.083594 Set Vref, RX VrefLevel [Byte0]: 73
1813 13:29:48.086984 [Byte1]: 73
1814 13:29:48.091548
1815 13:29:48.091633 Set Vref, RX VrefLevel [Byte0]: 74
1816 13:29:48.094482 [Byte1]: 74
1817 13:29:48.098942
1818 13:29:48.099013 Set Vref, RX VrefLevel [Byte0]: 75
1819 13:29:48.102179 [Byte1]: 75
1820 13:29:48.106531
1821 13:29:48.106616 Final RX Vref Byte 0 = 55 to rank0
1822 13:29:48.110233 Final RX Vref Byte 1 = 59 to rank0
1823 13:29:48.113299 Final RX Vref Byte 0 = 55 to rank1
1824 13:29:48.116498 Final RX Vref Byte 1 = 59 to rank1==
1825 13:29:48.120336 Dram Type= 6, Freq= 0, CH_1, rank 0
1826 13:29:48.126501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1827 13:29:48.126617 ==
1828 13:29:48.126728 DQS Delay:
1829 13:29:48.126836 DQS0 = 0, DQS1 = 0
1830 13:29:48.130084 DQM Delay:
1831 13:29:48.130168 DQM0 = 84, DQM1 = 79
1832 13:29:48.133023 DQ Delay:
1833 13:29:48.136292 DQ0 =92, DQ1 =80, DQ2 =72, DQ3 =84
1834 13:29:48.139649 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =76
1835 13:29:48.142794 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1836 13:29:48.146514 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =84
1837 13:29:48.146583
1838 13:29:48.146663
1839 13:29:48.152892 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a2d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1840 13:29:48.156025 CH1 RK0: MR19=606, MR18=1A2D
1841 13:29:48.162902 CH1_RK0: MR19=0x606, MR18=0x1A2D, DQSOSC=398, MR23=63, INC=93, DEC=62
1842 13:29:48.162970
1843 13:29:48.166135 ----->DramcWriteLeveling(PI) begin...
1844 13:29:48.166199 ==
1845 13:29:48.169432 Dram Type= 6, Freq= 0, CH_1, rank 1
1846 13:29:48.172517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1847 13:29:48.172580 ==
1848 13:29:48.175666 Write leveling (Byte 0): 26 => 26
1849 13:29:48.179241 Write leveling (Byte 1): 31 => 31
1850 13:29:48.182424 DramcWriteLeveling(PI) end<-----
1851 13:29:48.182513
1852 13:29:48.182592 ==
1853 13:29:48.185932 Dram Type= 6, Freq= 0, CH_1, rank 1
1854 13:29:48.189471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1855 13:29:48.189537 ==
1856 13:29:48.192340 [Gating] SW mode calibration
1857 13:29:48.199313 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1858 13:29:48.205818 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1859 13:29:48.209080 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1860 13:29:48.215648 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1861 13:29:48.218675 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 13:29:48.222363 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 13:29:48.228848 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 13:29:48.232050 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 13:29:48.235767 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 13:29:48.242556 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 13:29:48.245470 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 13:29:48.248804 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 13:29:48.255590 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 13:29:48.258774 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 13:29:48.261939 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 13:29:48.265652 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 13:29:48.271995 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 13:29:48.275176 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 13:29:48.278819 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1876 13:29:48.285575 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1877 13:29:48.288713 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1878 13:29:48.291925 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 13:29:48.298749 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 13:29:48.301839 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 13:29:48.304894 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 13:29:48.311852 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 13:29:48.315080 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 13:29:48.318583 0 9 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1885 13:29:48.325009 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1886 13:29:48.328412 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1887 13:29:48.331670 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 13:29:48.338171 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 13:29:48.341366 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 13:29:48.345115 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 13:29:48.351425 0 10 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1892 13:29:48.354942 0 10 4 | B1->B0 | 3030 2727 | 0 0 | (0 0) (0 0)
1893 13:29:48.358172 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1894 13:29:48.365018 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 13:29:48.368094 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 13:29:48.371723 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 13:29:48.378091 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 13:29:48.381243 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 13:29:48.385047 0 11 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1900 13:29:48.391185 0 11 4 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
1901 13:29:48.395057 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
1902 13:29:48.398209 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 13:29:48.404495 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 13:29:48.408353 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 13:29:48.411429 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 13:29:48.418293 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 13:29:48.421289 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 13:29:48.424400 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1909 13:29:48.431068 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1910 13:29:48.434513 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 13:29:48.437882 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 13:29:48.441345 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 13:29:48.447774 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 13:29:48.451458 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 13:29:48.454383 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 13:29:48.461170 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 13:29:48.464638 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 13:29:48.467480 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 13:29:48.474514 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 13:29:48.477708 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 13:29:48.480927 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 13:29:48.487772 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 13:29:48.490966 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1924 13:29:48.494727 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1925 13:29:48.497848 Total UI for P1: 0, mck2ui 16
1926 13:29:48.500869 best dqsien dly found for B0: ( 0, 14, 0)
1927 13:29:48.507847 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 13:29:48.507952 Total UI for P1: 0, mck2ui 16
1929 13:29:48.514176 best dqsien dly found for B1: ( 0, 14, 4)
1930 13:29:48.517783 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1931 13:29:48.520906 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1932 13:29:48.521002
1933 13:29:48.524084 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1934 13:29:48.527903 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1935 13:29:48.530966 [Gating] SW calibration Done
1936 13:29:48.531041 ==
1937 13:29:48.534049 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 13:29:48.537445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 13:29:48.537542 ==
1940 13:29:48.540830 RX Vref Scan: 0
1941 13:29:48.540931
1942 13:29:48.541019 RX Vref 0 -> 0, step: 1
1943 13:29:48.541127
1944 13:29:48.544134 RX Delay -130 -> 252, step: 16
1945 13:29:48.547332 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1946 13:29:48.554223 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1947 13:29:48.557062 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1948 13:29:48.560312 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1949 13:29:48.564132 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1950 13:29:48.567083 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1951 13:29:48.573719 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1952 13:29:48.577327 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1953 13:29:48.580119 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1954 13:29:48.583712 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1955 13:29:48.586905 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1956 13:29:48.593954 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1957 13:29:48.597133 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1958 13:29:48.600115 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1959 13:29:48.603971 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1960 13:29:48.610405 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1961 13:29:48.610500 ==
1962 13:29:48.613528 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 13:29:48.617351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 13:29:48.617442 ==
1965 13:29:48.617524 DQS Delay:
1966 13:29:48.620427 DQS0 = 0, DQS1 = 0
1967 13:29:48.620513 DQM Delay:
1968 13:29:48.623563 DQM0 = 83, DQM1 = 80
1969 13:29:48.623647 DQ Delay:
1970 13:29:48.626728 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1971 13:29:48.630552 DQ4 =85, DQ5 =85, DQ6 =85, DQ7 =85
1972 13:29:48.633739 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1973 13:29:48.636850 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1974 13:29:48.636919
1975 13:29:48.636977
1976 13:29:48.637037 ==
1977 13:29:48.640024 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 13:29:48.643542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 13:29:48.643634 ==
1980 13:29:48.643716
1981 13:29:48.643798
1982 13:29:48.647036 TX Vref Scan disable
1983 13:29:48.650356 == TX Byte 0 ==
1984 13:29:48.653810 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1985 13:29:48.656593 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1986 13:29:48.660425 == TX Byte 1 ==
1987 13:29:48.663554 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1988 13:29:48.667151 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1989 13:29:48.667245 ==
1990 13:29:48.670117 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 13:29:48.676805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 13:29:48.676898 ==
1993 13:29:48.688802 TX Vref=22, minBit 1, minWin=27, winSum=444
1994 13:29:48.692119 TX Vref=24, minBit 4, minWin=27, winSum=449
1995 13:29:48.695580 TX Vref=26, minBit 1, minWin=27, winSum=450
1996 13:29:48.698791 TX Vref=28, minBit 6, minWin=27, winSum=455
1997 13:29:48.701857 TX Vref=30, minBit 5, minWin=27, winSum=456
1998 13:29:48.708699 TX Vref=32, minBit 6, minWin=27, winSum=455
1999 13:29:48.711962 [TxChooseVref] Worse bit 5, Min win 27, Win sum 456, Final Vref 30
2000 13:29:48.712060
2001 13:29:48.715095 Final TX Range 1 Vref 30
2002 13:29:48.715187
2003 13:29:48.715273 ==
2004 13:29:48.718299 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 13:29:48.722100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 13:29:48.725120 ==
2007 13:29:48.725255
2008 13:29:48.725344
2009 13:29:48.725429 TX Vref Scan disable
2010 13:29:48.728896 == TX Byte 0 ==
2011 13:29:48.731987 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2012 13:29:48.735782 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2013 13:29:48.738777 == TX Byte 1 ==
2014 13:29:48.741969 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2015 13:29:48.745709 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2016 13:29:48.748817
2017 13:29:48.748985 [DATLAT]
2018 13:29:48.749088 Freq=800, CH1 RK1
2019 13:29:48.749240
2020 13:29:48.751926 DATLAT Default: 0xa
2021 13:29:48.752031 0, 0xFFFF, sum = 0
2022 13:29:48.755467 1, 0xFFFF, sum = 0
2023 13:29:48.755549 2, 0xFFFF, sum = 0
2024 13:29:48.758945 3, 0xFFFF, sum = 0
2025 13:29:48.762299 4, 0xFFFF, sum = 0
2026 13:29:48.762362 5, 0xFFFF, sum = 0
2027 13:29:48.765582 6, 0xFFFF, sum = 0
2028 13:29:48.765648 7, 0xFFFF, sum = 0
2029 13:29:48.768719 8, 0xFFFF, sum = 0
2030 13:29:48.768787 9, 0x0, sum = 1
2031 13:29:48.768845 10, 0x0, sum = 2
2032 13:29:48.771913 11, 0x0, sum = 3
2033 13:29:48.771976 12, 0x0, sum = 4
2034 13:29:48.775104 best_step = 10
2035 13:29:48.775189
2036 13:29:48.775245 ==
2037 13:29:48.778857 Dram Type= 6, Freq= 0, CH_1, rank 1
2038 13:29:48.781845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2039 13:29:48.781952 ==
2040 13:29:48.785335 RX Vref Scan: 0
2041 13:29:48.785398
2042 13:29:48.785451 RX Vref 0 -> 0, step: 1
2043 13:29:48.785510
2044 13:29:48.788313 RX Delay -95 -> 252, step: 8
2045 13:29:48.795462 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2046 13:29:48.798944 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
2047 13:29:48.802179 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2048 13:29:48.805714 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2049 13:29:48.808587 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2050 13:29:48.815294 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2051 13:29:48.818516 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2052 13:29:48.822183 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2053 13:29:48.825451 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2054 13:29:48.828479 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2055 13:29:48.835413 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2056 13:29:48.838580 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2057 13:29:48.841771 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2058 13:29:48.845500 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2059 13:29:48.851838 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2060 13:29:48.855023 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2061 13:29:48.855117 ==
2062 13:29:48.858762 Dram Type= 6, Freq= 0, CH_1, rank 1
2063 13:29:48.861861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2064 13:29:48.861954 ==
2065 13:29:48.862039 DQS Delay:
2066 13:29:48.865441 DQS0 = 0, DQS1 = 0
2067 13:29:48.865535 DQM Delay:
2068 13:29:48.868771 DQM0 = 86, DQM1 = 81
2069 13:29:48.868867 DQ Delay:
2070 13:29:48.871738 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2071 13:29:48.875063 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2072 13:29:48.878510 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
2073 13:29:48.882324 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =84
2074 13:29:48.882414
2075 13:29:48.882475
2076 13:29:48.892014 [DQSOSCAuto] RK1, (LSB)MR18= 0x203c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2077 13:29:48.892116 CH1 RK1: MR19=606, MR18=203C
2078 13:29:48.898670 CH1_RK1: MR19=0x606, MR18=0x203C, DQSOSC=394, MR23=63, INC=95, DEC=63
2079 13:29:48.901759 [RxdqsGatingPostProcess] freq 800
2080 13:29:48.908599 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2081 13:29:48.912019 Pre-setting of DQS Precalculation
2082 13:29:48.914883 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2083 13:29:48.921808 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2084 13:29:48.928698 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2085 13:29:48.931850
2086 13:29:48.931947
2087 13:29:48.932032 [Calibration Summary] 1600 Mbps
2088 13:29:48.935007 CH 0, Rank 0
2089 13:29:48.935112 SW Impedance : PASS
2090 13:29:48.938089 DUTY Scan : NO K
2091 13:29:48.941326 ZQ Calibration : PASS
2092 13:29:48.941400 Jitter Meter : NO K
2093 13:29:48.944584 CBT Training : PASS
2094 13:29:48.948289 Write leveling : PASS
2095 13:29:48.948358 RX DQS gating : PASS
2096 13:29:49.035644 RX DQ/DQS(RDDQC) : PASS
2097 13:29:49.035897 TX DQ/DQS : PASS
2098 13:29:49.036076 RX DATLAT : PASS
2099 13:29:49.036275 RX DQ/DQS(Engine): PASS
2100 13:29:49.036443 TX OE : NO K
2101 13:29:49.036599 All Pass.
2102 13:29:49.036753
2103 13:29:49.036916 CH 0, Rank 1
2104 13:29:49.037059 SW Impedance : PASS
2105 13:29:49.037221 DUTY Scan : NO K
2106 13:29:49.037359 ZQ Calibration : PASS
2107 13:29:49.037493 Jitter Meter : NO K
2108 13:29:49.037621 CBT Training : PASS
2109 13:29:49.037753 Write leveling : PASS
2110 13:29:49.037878 RX DQS gating : PASS
2111 13:29:49.038009 RX DQ/DQS(RDDQC) : PASS
2112 13:29:49.038141 TX DQ/DQS : PASS
2113 13:29:49.038274 RX DATLAT : PASS
2114 13:29:49.038408 RX DQ/DQS(Engine): PASS
2115 13:29:49.038541 TX OE : NO K
2116 13:29:49.038677 All Pass.
2117 13:29:49.038788
2118 13:29:49.038886 CH 1, Rank 0
2119 13:29:49.039010 SW Impedance : PASS
2120 13:29:49.039143 DUTY Scan : NO K
2121 13:29:49.039291 ZQ Calibration : PASS
2122 13:29:49.039436 Jitter Meter : NO K
2123 13:29:49.039578 CBT Training : PASS
2124 13:29:49.039716 Write leveling : PASS
2125 13:29:49.039859 RX DQS gating : PASS
2126 13:29:49.040003 RX DQ/DQS(RDDQC) : PASS
2127 13:29:49.040145 TX DQ/DQS : PASS
2128 13:29:49.040283 RX DATLAT : PASS
2129 13:29:49.040419 RX DQ/DQS(Engine): PASS
2130 13:29:49.040562 TX OE : NO K
2131 13:29:49.040704 All Pass.
2132 13:29:49.040857
2133 13:29:49.040993 CH 1, Rank 1
2134 13:29:49.041151 SW Impedance : PASS
2135 13:29:49.041291 DUTY Scan : NO K
2136 13:29:49.041433 ZQ Calibration : PASS
2137 13:29:49.041564 Jitter Meter : NO K
2138 13:29:49.041701 CBT Training : PASS
2139 13:29:49.041836 Write leveling : PASS
2140 13:29:49.041971 RX DQS gating : PASS
2141 13:29:49.042321 RX DQ/DQS(RDDQC) : PASS
2142 13:29:49.042455 TX DQ/DQS : PASS
2143 13:29:49.042593 RX DATLAT : PASS
2144 13:29:49.044227 RX DQ/DQS(Engine): PASS
2145 13:29:49.044382 TX OE : NO K
2146 13:29:49.047380 All Pass.
2147 13:29:49.047520
2148 13:29:49.047659 DramC Write-DBI off
2149 13:29:49.050582 PER_BANK_REFRESH: Hybrid Mode
2150 13:29:49.050753 TX_TRACKING: ON
2151 13:29:49.053884 [GetDramInforAfterCalByMRR] Vendor 6.
2152 13:29:49.060627 [GetDramInforAfterCalByMRR] Revision 606.
2153 13:29:49.063841 [GetDramInforAfterCalByMRR] Revision 2 0.
2154 13:29:49.064128 MR0 0x3b3b
2155 13:29:49.064467 MR8 0x5151
2156 13:29:49.067124 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2157 13:29:49.067527
2158 13:29:49.070847 MR0 0x3b3b
2159 13:29:49.071305 MR8 0x5151
2160 13:29:49.074010 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2161 13:29:49.074366
2162 13:29:49.083779 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2163 13:29:49.087625 [FAST_K] Save calibration result to emmc
2164 13:29:49.090556 [FAST_K] Save calibration result to emmc
2165 13:29:49.093953 dram_init: config_dvfs: 1
2166 13:29:49.097727 dramc_set_vcore_voltage set vcore to 662500
2167 13:29:49.100660 Read voltage for 1200, 2
2168 13:29:49.101209 Vio18 = 0
2169 13:29:49.101591 Vcore = 662500
2170 13:29:49.104265 Vdram = 0
2171 13:29:49.104744 Vddq = 0
2172 13:29:49.105314 Vmddr = 0
2173 13:29:49.110505 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2174 13:29:49.113668 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2175 13:29:49.116949 MEM_TYPE=3, freq_sel=15
2176 13:29:49.120247 sv_algorithm_assistance_LP4_1600
2177 13:29:49.123923 ============ PULL DRAM RESETB DOWN ============
2178 13:29:49.126982 ========== PULL DRAM RESETB DOWN end =========
2179 13:29:49.133295 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2180 13:29:49.137079 ===================================
2181 13:29:49.139998 LPDDR4 DRAM CONFIGURATION
2182 13:29:49.143741 ===================================
2183 13:29:49.144172 EX_ROW_EN[0] = 0x0
2184 13:29:49.147002 EX_ROW_EN[1] = 0x0
2185 13:29:49.147455 LP4Y_EN = 0x0
2186 13:29:49.150087 WORK_FSP = 0x0
2187 13:29:49.150597 WL = 0x4
2188 13:29:49.153306 RL = 0x4
2189 13:29:49.153799 BL = 0x2
2190 13:29:49.156923 RPST = 0x0
2191 13:29:49.157400 RD_PRE = 0x0
2192 13:29:49.160010 WR_PRE = 0x1
2193 13:29:49.160326 WR_PST = 0x0
2194 13:29:49.163400 DBI_WR = 0x0
2195 13:29:49.163780 DBI_RD = 0x0
2196 13:29:49.166601 OTF = 0x1
2197 13:29:49.170348 ===================================
2198 13:29:49.173357 ===================================
2199 13:29:49.173872 ANA top config
2200 13:29:49.176501 ===================================
2201 13:29:49.180076 DLL_ASYNC_EN = 0
2202 13:29:49.183123 ALL_SLAVE_EN = 0
2203 13:29:49.187046 NEW_RANK_MODE = 1
2204 13:29:49.187481 DLL_IDLE_MODE = 1
2205 13:29:49.190131 LP45_APHY_COMB_EN = 1
2206 13:29:49.193327 TX_ODT_DIS = 1
2207 13:29:49.196366 NEW_8X_MODE = 1
2208 13:29:49.200057 ===================================
2209 13:29:49.203388 ===================================
2210 13:29:49.206440 data_rate = 2400
2211 13:29:49.206896 CKR = 1
2212 13:29:49.210027 DQ_P2S_RATIO = 8
2213 13:29:49.213040 ===================================
2214 13:29:49.216553 CA_P2S_RATIO = 8
2215 13:29:49.220102 DQ_CA_OPEN = 0
2216 13:29:49.223216 DQ_SEMI_OPEN = 0
2217 13:29:49.226674 CA_SEMI_OPEN = 0
2218 13:29:49.227282 CA_FULL_RATE = 0
2219 13:29:49.229689 DQ_CKDIV4_EN = 0
2220 13:29:49.233228 CA_CKDIV4_EN = 0
2221 13:29:49.236621 CA_PREDIV_EN = 0
2222 13:29:49.239713 PH8_DLY = 17
2223 13:29:49.243225 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2224 13:29:49.243651 DQ_AAMCK_DIV = 4
2225 13:29:49.246228 CA_AAMCK_DIV = 4
2226 13:29:49.249936 CA_ADMCK_DIV = 4
2227 13:29:49.252932 DQ_TRACK_CA_EN = 0
2228 13:29:49.256239 CA_PICK = 1200
2229 13:29:49.259979 CA_MCKIO = 1200
2230 13:29:49.263163 MCKIO_SEMI = 0
2231 13:29:49.266331 PLL_FREQ = 2366
2232 13:29:49.266877 DQ_UI_PI_RATIO = 32
2233 13:29:49.269438 CA_UI_PI_RATIO = 0
2234 13:29:49.273302 ===================================
2235 13:29:49.276404 ===================================
2236 13:29:49.279619 memory_type:LPDDR4
2237 13:29:49.282870 GP_NUM : 10
2238 13:29:49.283251 SRAM_EN : 1
2239 13:29:49.286428 MD32_EN : 0
2240 13:29:49.289511 ===================================
2241 13:29:49.290017 [ANA_INIT] >>>>>>>>>>>>>>
2242 13:29:49.293172 <<<<<< [CONFIGURE PHASE]: ANA_TX
2243 13:29:49.296254 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2244 13:29:49.299398 ===================================
2245 13:29:49.303296 data_rate = 2400,PCW = 0X5b00
2246 13:29:49.306449 ===================================
2247 13:29:49.309440 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2248 13:29:49.315894 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2249 13:29:49.322681 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2250 13:29:49.326036 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2251 13:29:49.329694 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2252 13:29:49.332542 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2253 13:29:49.335951 [ANA_INIT] flow start
2254 13:29:49.336394 [ANA_INIT] PLL >>>>>>>>
2255 13:29:49.339350 [ANA_INIT] PLL <<<<<<<<
2256 13:29:49.342857 [ANA_INIT] MIDPI >>>>>>>>
2257 13:29:49.343408 [ANA_INIT] MIDPI <<<<<<<<
2258 13:29:49.345907 [ANA_INIT] DLL >>>>>>>>
2259 13:29:49.349257 [ANA_INIT] DLL <<<<<<<<
2260 13:29:49.349753 [ANA_INIT] flow end
2261 13:29:49.355958 ============ LP4 DIFF to SE enter ============
2262 13:29:49.359541 ============ LP4 DIFF to SE exit ============
2263 13:29:49.362604 [ANA_INIT] <<<<<<<<<<<<<
2264 13:29:49.363121 [Flow] Enable top DCM control >>>>>
2265 13:29:49.365835 [Flow] Enable top DCM control <<<<<
2266 13:29:49.369455 Enable DLL master slave shuffle
2267 13:29:49.375823 ==============================================================
2268 13:29:49.379538 Gating Mode config
2269 13:29:49.382703 ==============================================================
2270 13:29:49.385728 Config description:
2271 13:29:49.395555 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2272 13:29:49.402788 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2273 13:29:49.405864 SELPH_MODE 0: By rank 1: By Phase
2274 13:29:49.412580 ==============================================================
2275 13:29:49.415570 GAT_TRACK_EN = 1
2276 13:29:49.419047 RX_GATING_MODE = 2
2277 13:29:49.422223 RX_GATING_TRACK_MODE = 2
2278 13:29:49.422793 SELPH_MODE = 1
2279 13:29:49.425900 PICG_EARLY_EN = 1
2280 13:29:49.429120 VALID_LAT_VALUE = 1
2281 13:29:49.435797 ==============================================================
2282 13:29:49.438849 Enter into Gating configuration >>>>
2283 13:29:49.442397 Exit from Gating configuration <<<<
2284 13:29:49.445856 Enter into DVFS_PRE_config >>>>>
2285 13:29:49.455415 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2286 13:29:49.459128 Exit from DVFS_PRE_config <<<<<
2287 13:29:49.462255 Enter into PICG configuration >>>>
2288 13:29:49.465385 Exit from PICG configuration <<<<
2289 13:29:49.468932 [RX_INPUT] configuration >>>>>
2290 13:29:49.472099 [RX_INPUT] configuration <<<<<
2291 13:29:49.475384 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2292 13:29:49.482418 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2293 13:29:49.488541 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2294 13:29:49.495455 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2295 13:29:49.502035 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2296 13:29:49.505209 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2297 13:29:49.512185 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2298 13:29:49.515307 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2299 13:29:49.518583 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2300 13:29:49.522115 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2301 13:29:49.525411 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2302 13:29:49.532013 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2303 13:29:49.535322 ===================================
2304 13:29:49.538455 LPDDR4 DRAM CONFIGURATION
2305 13:29:49.542104 ===================================
2306 13:29:49.542650 EX_ROW_EN[0] = 0x0
2307 13:29:49.545022 EX_ROW_EN[1] = 0x0
2308 13:29:49.545776 LP4Y_EN = 0x0
2309 13:29:49.548365 WORK_FSP = 0x0
2310 13:29:49.549020 WL = 0x4
2311 13:29:49.552042 RL = 0x4
2312 13:29:49.552423 BL = 0x2
2313 13:29:49.555336 RPST = 0x0
2314 13:29:49.555978 RD_PRE = 0x0
2315 13:29:49.558342 WR_PRE = 0x1
2316 13:29:49.558740 WR_PST = 0x0
2317 13:29:49.561658 DBI_WR = 0x0
2318 13:29:49.562140 DBI_RD = 0x0
2319 13:29:49.565000 OTF = 0x1
2320 13:29:49.568113 ===================================
2321 13:29:49.571652 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2322 13:29:49.575140 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2323 13:29:49.581544 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2324 13:29:49.585067 ===================================
2325 13:29:49.585620 LPDDR4 DRAM CONFIGURATION
2326 13:29:49.588226 ===================================
2327 13:29:49.591487 EX_ROW_EN[0] = 0x10
2328 13:29:49.595265 EX_ROW_EN[1] = 0x0
2329 13:29:49.595781 LP4Y_EN = 0x0
2330 13:29:49.598361 WORK_FSP = 0x0
2331 13:29:49.598891 WL = 0x4
2332 13:29:49.601484 RL = 0x4
2333 13:29:49.602054 BL = 0x2
2334 13:29:49.605301 RPST = 0x0
2335 13:29:49.605821 RD_PRE = 0x0
2336 13:29:49.608355 WR_PRE = 0x1
2337 13:29:49.608774 WR_PST = 0x0
2338 13:29:49.611388 DBI_WR = 0x0
2339 13:29:49.611926 DBI_RD = 0x0
2340 13:29:49.615012 OTF = 0x1
2341 13:29:49.618321 ===================================
2342 13:29:49.624845 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2343 13:29:49.625374 ==
2344 13:29:49.628291 Dram Type= 6, Freq= 0, CH_0, rank 0
2345 13:29:49.631693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2346 13:29:49.632141 ==
2347 13:29:49.634569 [Duty_Offset_Calibration]
2348 13:29:49.634967 B0:2 B1:0 CA:4
2349 13:29:49.635287
2350 13:29:49.638372 [DutyScan_Calibration_Flow] k_type=0
2351 13:29:49.648853
2352 13:29:49.649486 ==CLK 0==
2353 13:29:49.651717 Final CLK duty delay cell = 0
2354 13:29:49.655257 [0] MAX Duty = 5156%(X100), DQS PI = 14
2355 13:29:49.658315 [0] MIN Duty = 4969%(X100), DQS PI = 8
2356 13:29:49.658702 [0] AVG Duty = 5062%(X100)
2357 13:29:49.661479
2358 13:29:49.664783 CH0 CLK Duty spec in!! Max-Min= 187%
2359 13:29:49.668583 [DutyScan_Calibration_Flow] ====Done====
2360 13:29:49.669727
2361 13:29:49.671551 [DutyScan_Calibration_Flow] k_type=1
2362 13:29:49.686939
2363 13:29:49.687484 ==DQS 0 ==
2364 13:29:49.690288 Final DQS duty delay cell = -4
2365 13:29:49.693776 [-4] MAX Duty = 4938%(X100), DQS PI = 6
2366 13:29:49.696915 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2367 13:29:49.699968 [-4] AVG Duty = 4907%(X100)
2368 13:29:49.700530
2369 13:29:49.701080 ==DQS 1 ==
2370 13:29:49.703619 Final DQS duty delay cell = 0
2371 13:29:49.706618 [0] MAX Duty = 5125%(X100), DQS PI = 50
2372 13:29:49.710325 [0] MIN Duty = 5000%(X100), DQS PI = 0
2373 13:29:49.713627 [0] AVG Duty = 5062%(X100)
2374 13:29:49.714160
2375 13:29:49.716861 CH0 DQS 0 Duty spec in!! Max-Min= 62%
2376 13:29:49.717448
2377 13:29:49.719955 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2378 13:29:49.723242 [DutyScan_Calibration_Flow] ====Done====
2379 13:29:49.723769
2380 13:29:49.726992 [DutyScan_Calibration_Flow] k_type=3
2381 13:29:49.743227
2382 13:29:49.743621 ==DQM 0 ==
2383 13:29:49.746907 Final DQM duty delay cell = 0
2384 13:29:49.750063 [0] MAX Duty = 5094%(X100), DQS PI = 20
2385 13:29:49.753724 [0] MIN Duty = 4844%(X100), DQS PI = 50
2386 13:29:49.754017 [0] AVG Duty = 4969%(X100)
2387 13:29:49.756547
2388 13:29:49.756811 ==DQM 1 ==
2389 13:29:49.760005 Final DQM duty delay cell = 0
2390 13:29:49.763101 [0] MAX Duty = 4969%(X100), DQS PI = 2
2391 13:29:49.766768 [0] MIN Duty = 4875%(X100), DQS PI = 20
2392 13:29:49.766843 [0] AVG Duty = 4922%(X100)
2393 13:29:49.769865
2394 13:29:49.773025 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2395 13:29:49.773121
2396 13:29:49.776819 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2397 13:29:49.779964 [DutyScan_Calibration_Flow] ====Done====
2398 13:29:49.780073
2399 13:29:49.782979 [DutyScan_Calibration_Flow] k_type=2
2400 13:29:49.799760
2401 13:29:49.799937 ==DQ 0 ==
2402 13:29:49.803222 Final DQ duty delay cell = 0
2403 13:29:49.806636 [0] MAX Duty = 5156%(X100), DQS PI = 18
2404 13:29:49.809598 [0] MIN Duty = 4938%(X100), DQS PI = 58
2405 13:29:49.809779 [0] AVG Duty = 5047%(X100)
2406 13:29:49.813064
2407 13:29:49.813330 ==DQ 1 ==
2408 13:29:49.816673 Final DQ duty delay cell = 0
2409 13:29:49.819978 [0] MAX Duty = 5125%(X100), DQS PI = 4
2410 13:29:49.823012 [0] MIN Duty = 4938%(X100), DQS PI = 16
2411 13:29:49.823283 [0] AVG Duty = 5031%(X100)
2412 13:29:49.823491
2413 13:29:49.826353 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2414 13:29:49.830267
2415 13:29:49.833375 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2416 13:29:49.836458 [DutyScan_Calibration_Flow] ====Done====
2417 13:29:49.836836 ==
2418 13:29:49.839934 Dram Type= 6, Freq= 0, CH_1, rank 0
2419 13:29:49.843150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2420 13:29:49.843624 ==
2421 13:29:49.846696 [Duty_Offset_Calibration]
2422 13:29:49.847203 B0:0 B1:-1 CA:3
2423 13:29:49.847659
2424 13:29:49.849736 [DutyScan_Calibration_Flow] k_type=0
2425 13:29:49.859158
2426 13:29:49.859534 ==CLK 0==
2427 13:29:49.862780 Final CLK duty delay cell = -4
2428 13:29:49.865856 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2429 13:29:49.869074 [-4] MIN Duty = 4876%(X100), DQS PI = 10
2430 13:29:49.872279 [-4] AVG Duty = 4938%(X100)
2431 13:29:49.872655
2432 13:29:49.876091 CH1 CLK Duty spec in!! Max-Min= 124%
2433 13:29:49.879328 [DutyScan_Calibration_Flow] ====Done====
2434 13:29:49.879717
2435 13:29:49.882498 [DutyScan_Calibration_Flow] k_type=1
2436 13:29:49.898957
2437 13:29:49.899333 ==DQS 0 ==
2438 13:29:49.902095 Final DQS duty delay cell = 0
2439 13:29:49.905230 [0] MAX Duty = 5187%(X100), DQS PI = 18
2440 13:29:49.908921 [0] MIN Duty = 4907%(X100), DQS PI = 38
2441 13:29:49.911926 [0] AVG Duty = 5047%(X100)
2442 13:29:49.912302
2443 13:29:49.912595 ==DQS 1 ==
2444 13:29:49.915294 Final DQS duty delay cell = 0
2445 13:29:49.918806 [0] MAX Duty = 5156%(X100), DQS PI = 8
2446 13:29:49.922141 [0] MIN Duty = 5031%(X100), DQS PI = 18
2447 13:29:49.922538 [0] AVG Duty = 5093%(X100)
2448 13:29:49.925316
2449 13:29:49.929077 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2450 13:29:49.929605
2451 13:29:49.931940 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2452 13:29:49.935195 [DutyScan_Calibration_Flow] ====Done====
2453 13:29:49.935669
2454 13:29:49.938293 [DutyScan_Calibration_Flow] k_type=3
2455 13:29:49.955324
2456 13:29:49.955836 ==DQM 0 ==
2457 13:29:49.958817 Final DQM duty delay cell = 0
2458 13:29:49.961817 [0] MAX Duty = 5031%(X100), DQS PI = 28
2459 13:29:49.964857 [0] MIN Duty = 4782%(X100), DQS PI = 38
2460 13:29:49.968611 [0] AVG Duty = 4906%(X100)
2461 13:29:49.969202
2462 13:29:49.969607 ==DQM 1 ==
2463 13:29:49.971564 Final DQM duty delay cell = 0
2464 13:29:49.975258 [0] MAX Duty = 5000%(X100), DQS PI = 34
2465 13:29:49.978319 [0] MIN Duty = 4844%(X100), DQS PI = 0
2466 13:29:49.982105 [0] AVG Duty = 4922%(X100)
2467 13:29:49.982689
2468 13:29:49.985106 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2469 13:29:49.985672
2470 13:29:49.988230 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2471 13:29:49.991944 [DutyScan_Calibration_Flow] ====Done====
2472 13:29:49.992327
2473 13:29:49.995021 [DutyScan_Calibration_Flow] k_type=2
2474 13:29:50.011777
2475 13:29:50.012155 ==DQ 0 ==
2476 13:29:50.014835 Final DQ duty delay cell = -4
2477 13:29:50.018508 [-4] MAX Duty = 5000%(X100), DQS PI = 14
2478 13:29:50.021646 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2479 13:29:50.024826 [-4] AVG Duty = 4922%(X100)
2480 13:29:50.025249
2481 13:29:50.025554 ==DQ 1 ==
2482 13:29:50.028558 Final DQ duty delay cell = 4
2483 13:29:50.031746 [4] MAX Duty = 5156%(X100), DQS PI = 10
2484 13:29:50.035232 [4] MIN Duty = 5031%(X100), DQS PI = 60
2485 13:29:50.038230 [4] AVG Duty = 5093%(X100)
2486 13:29:50.038716
2487 13:29:50.041959 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2488 13:29:50.042419
2489 13:29:50.045055 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2490 13:29:50.048387 [DutyScan_Calibration_Flow] ====Done====
2491 13:29:50.051449 nWR fixed to 30
2492 13:29:50.054707 [ModeRegInit_LP4] CH0 RK0
2493 13:29:50.055172 [ModeRegInit_LP4] CH0 RK1
2494 13:29:50.058374 [ModeRegInit_LP4] CH1 RK0
2495 13:29:50.061514 [ModeRegInit_LP4] CH1 RK1
2496 13:29:50.061974 match AC timing 7
2497 13:29:50.068069 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2498 13:29:50.071785 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2499 13:29:50.074964 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2500 13:29:50.081367 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2501 13:29:50.084540 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2502 13:29:50.084916 ==
2503 13:29:50.087734 Dram Type= 6, Freq= 0, CH_0, rank 0
2504 13:29:50.091690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2505 13:29:50.092144 ==
2506 13:29:50.097658 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2507 13:29:50.104412 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2508 13:29:50.112029 [CA 0] Center 39 (9~70) winsize 62
2509 13:29:50.115710 [CA 1] Center 39 (9~69) winsize 61
2510 13:29:50.118993 [CA 2] Center 35 (5~66) winsize 62
2511 13:29:50.122101 [CA 3] Center 35 (5~66) winsize 62
2512 13:29:50.125338 [CA 4] Center 33 (3~64) winsize 62
2513 13:29:50.128299 [CA 5] Center 33 (3~64) winsize 62
2514 13:29:50.128645
2515 13:29:50.132194 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2516 13:29:50.132597
2517 13:29:50.135416 [CATrainingPosCal] consider 1 rank data
2518 13:29:50.138501 u2DelayCellTimex100 = 270/100 ps
2519 13:29:50.142397 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2520 13:29:50.145398 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2521 13:29:50.152351 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2522 13:29:50.155212 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2523 13:29:50.158463 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2524 13:29:50.161924 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2525 13:29:50.162427
2526 13:29:50.165132 CA PerBit enable=1, Macro0, CA PI delay=33
2527 13:29:50.165549
2528 13:29:50.168493 [CBTSetCACLKResult] CA Dly = 33
2529 13:29:50.168950 CS Dly: 7 (0~38)
2530 13:29:50.169479 ==
2531 13:29:50.171923 Dram Type= 6, Freq= 0, CH_0, rank 1
2532 13:29:50.178599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 13:29:50.179125 ==
2534 13:29:50.181451 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2535 13:29:50.188451 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2536 13:29:50.197785 [CA 0] Center 39 (9~70) winsize 62
2537 13:29:50.200803 [CA 1] Center 39 (9~70) winsize 62
2538 13:29:50.204560 [CA 2] Center 35 (5~66) winsize 62
2539 13:29:50.207597 [CA 3] Center 35 (5~66) winsize 62
2540 13:29:50.211303 [CA 4] Center 34 (4~65) winsize 62
2541 13:29:50.214462 [CA 5] Center 33 (3~64) winsize 62
2542 13:29:50.214819
2543 13:29:50.217544 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2544 13:29:50.218115
2545 13:29:50.221236 [CATrainingPosCal] consider 2 rank data
2546 13:29:50.224303 u2DelayCellTimex100 = 270/100 ps
2547 13:29:50.227535 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2548 13:29:50.231286 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2549 13:29:50.237709 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2550 13:29:50.240828 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2551 13:29:50.244022 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2552 13:29:50.247622 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2553 13:29:50.248119
2554 13:29:50.250854 CA PerBit enable=1, Macro0, CA PI delay=33
2555 13:29:50.251330
2556 13:29:50.254037 [CBTSetCACLKResult] CA Dly = 33
2557 13:29:50.254466 CS Dly: 8 (0~41)
2558 13:29:50.254909
2559 13:29:50.260876 ----->DramcWriteLeveling(PI) begin...
2560 13:29:50.261403 ==
2561 13:29:50.264475 Dram Type= 6, Freq= 0, CH_0, rank 0
2562 13:29:50.267652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2563 13:29:50.268138 ==
2564 13:29:50.270789 Write leveling (Byte 0): 30 => 30
2565 13:29:50.273806 Write leveling (Byte 1): 27 => 27
2566 13:29:50.277115 DramcWriteLeveling(PI) end<-----
2567 13:29:50.277583
2568 13:29:50.277901 ==
2569 13:29:50.280579 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 13:29:50.283965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 13:29:50.284420 ==
2572 13:29:50.287243 [Gating] SW mode calibration
2573 13:29:50.293915 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2574 13:29:50.300511 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2575 13:29:50.303804 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2576 13:29:50.307039 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2577 13:29:50.313975 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2578 13:29:50.317045 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2579 13:29:50.320448 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 13:29:50.327222 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 13:29:50.330188 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2582 13:29:50.333885 0 15 28 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
2583 13:29:50.340254 1 0 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
2584 13:29:50.344137 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 13:29:50.347147 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2586 13:29:50.350396 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 13:29:50.356994 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 13:29:50.360192 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 13:29:50.363375 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2590 13:29:50.370596 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2591 13:29:50.373795 1 1 0 | B1->B0 | 2e2e 4646 | 1 0 | (0 0) (0 0)
2592 13:29:50.376993 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2593 13:29:50.383588 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 13:29:50.386997 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 13:29:50.390187 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 13:29:50.396639 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 13:29:50.400253 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 13:29:50.403230 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2599 13:29:50.410313 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2600 13:29:50.413755 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2601 13:29:50.416706 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 13:29:50.423399 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 13:29:50.426752 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 13:29:50.430011 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 13:29:50.436150 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 13:29:50.439801 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 13:29:50.443036 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 13:29:50.449747 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 13:29:50.453130 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 13:29:50.456238 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 13:29:50.463053 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 13:29:50.466264 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 13:29:50.469407 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2614 13:29:50.476032 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2615 13:29:50.476451 Total UI for P1: 0, mck2ui 16
2616 13:29:50.483014 best dqsien dly found for B0: ( 1, 3, 24)
2617 13:29:50.485963 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2618 13:29:50.489619 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2619 13:29:50.496018 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 13:29:50.496382 Total UI for P1: 0, mck2ui 16
2621 13:29:50.499174 best dqsien dly found for B1: ( 1, 4, 0)
2622 13:29:50.506062 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2623 13:29:50.509752 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2624 13:29:50.510149
2625 13:29:50.512731 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2626 13:29:50.516194 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2627 13:29:50.519127 [Gating] SW calibration Done
2628 13:29:50.519630 ==
2629 13:29:50.522996 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 13:29:50.526199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 13:29:50.526591 ==
2632 13:29:50.529236 RX Vref Scan: 0
2633 13:29:50.529624
2634 13:29:50.529930 RX Vref 0 -> 0, step: 1
2635 13:29:50.530212
2636 13:29:50.532740 RX Delay -40 -> 252, step: 8
2637 13:29:50.536167 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2638 13:29:50.542708 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2639 13:29:50.546195 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2640 13:29:50.549421 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2641 13:29:50.552805 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2642 13:29:50.556029 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2643 13:29:50.559136 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2644 13:29:50.565855 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2645 13:29:50.569105 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2646 13:29:50.572251 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2647 13:29:50.576001 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2648 13:29:50.579081 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2649 13:29:50.585502 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2650 13:29:50.589046 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2651 13:29:50.592156 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2652 13:29:50.595445 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2653 13:29:50.595789 ==
2654 13:29:50.599281 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 13:29:50.605553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 13:29:50.605898 ==
2657 13:29:50.606203 DQS Delay:
2658 13:29:50.609037 DQS0 = 0, DQS1 = 0
2659 13:29:50.609532 DQM Delay:
2660 13:29:50.611844 DQM0 = 120, DQM1 = 107
2661 13:29:50.612357 DQ Delay:
2662 13:29:50.615787 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2663 13:29:50.618902 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2664 13:29:50.622012 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2665 13:29:50.625456 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2666 13:29:50.625887
2667 13:29:50.626195
2668 13:29:50.626490 ==
2669 13:29:50.629245 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 13:29:50.632450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 13:29:50.635444 ==
2672 13:29:50.635826
2673 13:29:50.636124
2674 13:29:50.636424 TX Vref Scan disable
2675 13:29:50.638788 == TX Byte 0 ==
2676 13:29:50.641966 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2677 13:29:50.645718 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2678 13:29:50.649103 == TX Byte 1 ==
2679 13:29:50.652569 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2680 13:29:50.655601 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2681 13:29:50.658555 ==
2682 13:29:50.659039 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 13:29:50.665299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 13:29:50.665753 ==
2685 13:29:50.676689 TX Vref=22, minBit 1, minWin=25, winSum=411
2686 13:29:50.679793 TX Vref=24, minBit 8, minWin=25, winSum=417
2687 13:29:50.683109 TX Vref=26, minBit 10, minWin=25, winSum=421
2688 13:29:50.686616 TX Vref=28, minBit 1, minWin=26, winSum=428
2689 13:29:50.690161 TX Vref=30, minBit 5, minWin=26, winSum=429
2690 13:29:50.696817 TX Vref=32, minBit 4, minWin=26, winSum=427
2691 13:29:50.699897 [TxChooseVref] Worse bit 5, Min win 26, Win sum 429, Final Vref 30
2692 13:29:50.700282
2693 13:29:50.702966 Final TX Range 1 Vref 30
2694 13:29:50.703353
2695 13:29:50.703652 ==
2696 13:29:50.706894 Dram Type= 6, Freq= 0, CH_0, rank 0
2697 13:29:50.709967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2698 13:29:50.710365 ==
2699 13:29:50.712995
2700 13:29:50.713422
2701 13:29:50.713726 TX Vref Scan disable
2702 13:29:50.716457 == TX Byte 0 ==
2703 13:29:50.719691 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2704 13:29:50.723445 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2705 13:29:50.726457 == TX Byte 1 ==
2706 13:29:50.729704 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2707 13:29:50.736132 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2708 13:29:50.736664
2709 13:29:50.737214 [DATLAT]
2710 13:29:50.737635 Freq=1200, CH0 RK0
2711 13:29:50.738132
2712 13:29:50.739824 DATLAT Default: 0xd
2713 13:29:50.742906 0, 0xFFFF, sum = 0
2714 13:29:50.743457 1, 0xFFFF, sum = 0
2715 13:29:50.746065 2, 0xFFFF, sum = 0
2716 13:29:50.746636 3, 0xFFFF, sum = 0
2717 13:29:50.749069 4, 0xFFFF, sum = 0
2718 13:29:50.749668 5, 0xFFFF, sum = 0
2719 13:29:50.752849 6, 0xFFFF, sum = 0
2720 13:29:50.753426 7, 0xFFFF, sum = 0
2721 13:29:50.756102 8, 0xFFFF, sum = 0
2722 13:29:50.756521 9, 0xFFFF, sum = 0
2723 13:29:50.759723 10, 0xFFFF, sum = 0
2724 13:29:50.760268 11, 0xFFFF, sum = 0
2725 13:29:50.763094 12, 0x0, sum = 1
2726 13:29:50.763523 13, 0x0, sum = 2
2727 13:29:50.766370 14, 0x0, sum = 3
2728 13:29:50.766759 15, 0x0, sum = 4
2729 13:29:50.769551 best_step = 13
2730 13:29:50.770124
2731 13:29:50.770663 ==
2732 13:29:50.772680 Dram Type= 6, Freq= 0, CH_0, rank 0
2733 13:29:50.776034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2734 13:29:50.776421 ==
2735 13:29:50.776724 RX Vref Scan: 1
2736 13:29:50.776999
2737 13:29:50.779540 Set Vref Range= 32 -> 127
2738 13:29:50.779925
2739 13:29:50.783104 RX Vref 32 -> 127, step: 1
2740 13:29:50.783487
2741 13:29:50.785953 RX Delay -21 -> 252, step: 4
2742 13:29:50.786336
2743 13:29:50.789405 Set Vref, RX VrefLevel [Byte0]: 32
2744 13:29:50.792817 [Byte1]: 32
2745 13:29:50.793414
2746 13:29:50.796007 Set Vref, RX VrefLevel [Byte0]: 33
2747 13:29:50.799292 [Byte1]: 33
2748 13:29:50.803160
2749 13:29:50.803720 Set Vref, RX VrefLevel [Byte0]: 34
2750 13:29:50.806519 [Byte1]: 34
2751 13:29:50.811034
2752 13:29:50.811474 Set Vref, RX VrefLevel [Byte0]: 35
2753 13:29:50.814189 [Byte1]: 35
2754 13:29:50.818447
2755 13:29:50.818975 Set Vref, RX VrefLevel [Byte0]: 36
2756 13:29:50.822230 [Byte1]: 36
2757 13:29:50.826856
2758 13:29:50.827390 Set Vref, RX VrefLevel [Byte0]: 37
2759 13:29:50.829944 [Byte1]: 37
2760 13:29:50.834793
2761 13:29:50.835327 Set Vref, RX VrefLevel [Byte0]: 38
2762 13:29:50.837891 [Byte1]: 38
2763 13:29:50.842494
2764 13:29:50.845636 Set Vref, RX VrefLevel [Byte0]: 39
2765 13:29:50.848646 [Byte1]: 39
2766 13:29:50.849214
2767 13:29:50.852545 Set Vref, RX VrefLevel [Byte0]: 40
2768 13:29:50.855705 [Byte1]: 40
2769 13:29:50.856234
2770 13:29:50.858872 Set Vref, RX VrefLevel [Byte0]: 41
2771 13:29:50.861965 [Byte1]: 41
2772 13:29:50.866416
2773 13:29:50.867010 Set Vref, RX VrefLevel [Byte0]: 42
2774 13:29:50.869483 [Byte1]: 42
2775 13:29:50.874730
2776 13:29:50.875273 Set Vref, RX VrefLevel [Byte0]: 43
2777 13:29:50.877642 [Byte1]: 43
2778 13:29:50.881908
2779 13:29:50.882292 Set Vref, RX VrefLevel [Byte0]: 44
2780 13:29:50.885455 [Byte1]: 44
2781 13:29:50.890293
2782 13:29:50.890890 Set Vref, RX VrefLevel [Byte0]: 45
2783 13:29:50.893407 [Byte1]: 45
2784 13:29:50.898424
2785 13:29:50.898960 Set Vref, RX VrefLevel [Byte0]: 46
2786 13:29:50.901373 [Byte1]: 46
2787 13:29:50.906136
2788 13:29:50.906716 Set Vref, RX VrefLevel [Byte0]: 47
2789 13:29:50.909174 [Byte1]: 47
2790 13:29:50.914142
2791 13:29:50.914729 Set Vref, RX VrefLevel [Byte0]: 48
2792 13:29:50.917276 [Byte1]: 48
2793 13:29:50.921699
2794 13:29:50.922108 Set Vref, RX VrefLevel [Byte0]: 49
2795 13:29:50.925211 [Byte1]: 49
2796 13:29:50.929897
2797 13:29:50.930238 Set Vref, RX VrefLevel [Byte0]: 50
2798 13:29:50.932802 [Byte1]: 50
2799 13:29:50.937899
2800 13:29:50.938300 Set Vref, RX VrefLevel [Byte0]: 51
2801 13:29:50.941085 [Byte1]: 51
2802 13:29:50.945972
2803 13:29:50.946519 Set Vref, RX VrefLevel [Byte0]: 52
2804 13:29:50.948974 [Byte1]: 52
2805 13:29:50.953809
2806 13:29:50.954307 Set Vref, RX VrefLevel [Byte0]: 53
2807 13:29:50.956815 [Byte1]: 53
2808 13:29:50.961567
2809 13:29:50.961990 Set Vref, RX VrefLevel [Byte0]: 54
2810 13:29:50.964866 [Byte1]: 54
2811 13:29:50.969081
2812 13:29:50.969595 Set Vref, RX VrefLevel [Byte0]: 55
2813 13:29:50.972881 [Byte1]: 55
2814 13:29:50.977048
2815 13:29:50.977701 Set Vref, RX VrefLevel [Byte0]: 56
2816 13:29:50.980735 [Byte1]: 56
2817 13:29:50.985500
2818 13:29:50.986042 Set Vref, RX VrefLevel [Byte0]: 57
2819 13:29:50.988701 [Byte1]: 57
2820 13:29:50.993213
2821 13:29:50.993640 Set Vref, RX VrefLevel [Byte0]: 58
2822 13:29:50.996405 [Byte1]: 58
2823 13:29:51.000777
2824 13:29:51.004179 Set Vref, RX VrefLevel [Byte0]: 59
2825 13:29:51.007378 [Byte1]: 59
2826 13:29:51.007921
2827 13:29:51.011229 Set Vref, RX VrefLevel [Byte0]: 60
2828 13:29:51.014389 [Byte1]: 60
2829 13:29:51.014940
2830 13:29:51.017354 Set Vref, RX VrefLevel [Byte0]: 61
2831 13:29:51.020491 [Byte1]: 61
2832 13:29:51.024840
2833 13:29:51.025455 Set Vref, RX VrefLevel [Byte0]: 62
2834 13:29:51.028173 [Byte1]: 62
2835 13:29:51.032941
2836 13:29:51.033463 Set Vref, RX VrefLevel [Byte0]: 63
2837 13:29:51.036423 [Byte1]: 63
2838 13:29:51.041008
2839 13:29:51.041569 Set Vref, RX VrefLevel [Byte0]: 64
2840 13:29:51.044041 [Byte1]: 64
2841 13:29:51.048458
2842 13:29:51.049008 Set Vref, RX VrefLevel [Byte0]: 65
2843 13:29:51.051723 [Byte1]: 65
2844 13:29:51.056633
2845 13:29:51.057200 Set Vref, RX VrefLevel [Byte0]: 66
2846 13:29:51.059966 [Byte1]: 66
2847 13:29:51.064402
2848 13:29:51.064888 Set Vref, RX VrefLevel [Byte0]: 67
2849 13:29:51.067674 [Byte1]: 67
2850 13:29:51.072055
2851 13:29:51.072561 Final RX Vref Byte 0 = 56 to rank0
2852 13:29:51.075946 Final RX Vref Byte 1 = 49 to rank0
2853 13:29:51.079018 Final RX Vref Byte 0 = 56 to rank1
2854 13:29:51.082575 Final RX Vref Byte 1 = 49 to rank1==
2855 13:29:51.085800 Dram Type= 6, Freq= 0, CH_0, rank 0
2856 13:29:51.092419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2857 13:29:51.093020 ==
2858 13:29:51.093527 DQS Delay:
2859 13:29:51.093968 DQS0 = 0, DQS1 = 0
2860 13:29:51.095822 DQM Delay:
2861 13:29:51.096298 DQM0 = 119, DQM1 = 105
2862 13:29:51.098954 DQ Delay:
2863 13:29:51.102157 DQ0 =118, DQ1 =118, DQ2 =116, DQ3 =116
2864 13:29:51.106018 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =122
2865 13:29:51.108939 DQ8 =96, DQ9 =92, DQ10 =106, DQ11 =100
2866 13:29:51.112452 DQ12 =114, DQ13 =108, DQ14 =116, DQ15 =114
2867 13:29:51.112889
2868 13:29:51.113329
2869 13:29:51.118925 [DQSOSCAuto] RK0, (LSB)MR18= 0x3ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2870 13:29:51.121916 CH0 RK0: MR19=403, MR18=3FF
2871 13:29:51.128925 CH0_RK0: MR19=0x403, MR18=0x3FF, DQSOSC=408, MR23=63, INC=39, DEC=26
2872 13:29:51.129527
2873 13:29:51.132684 ----->DramcWriteLeveling(PI) begin...
2874 13:29:51.133256 ==
2875 13:29:51.135804 Dram Type= 6, Freq= 0, CH_0, rank 1
2876 13:29:51.138886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2877 13:29:51.141938 ==
2878 13:29:51.142483 Write leveling (Byte 0): 34 => 34
2879 13:29:51.145502 Write leveling (Byte 1): 26 => 26
2880 13:29:51.148554 DramcWriteLeveling(PI) end<-----
2881 13:29:51.149048
2882 13:29:51.149435 ==
2883 13:29:51.151618 Dram Type= 6, Freq= 0, CH_0, rank 1
2884 13:29:51.158647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2885 13:29:51.159081 ==
2886 13:29:51.159591 [Gating] SW mode calibration
2887 13:29:51.168501 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2888 13:29:51.171615 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2889 13:29:51.178179 0 15 0 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
2890 13:29:51.181930 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2891 13:29:51.185004 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2892 13:29:51.191298 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 13:29:51.195111 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 13:29:51.198142 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2895 13:29:51.204407 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2896 13:29:51.208079 0 15 28 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
2897 13:29:51.211094 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
2898 13:29:51.217972 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2899 13:29:51.221189 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2900 13:29:51.224248 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 13:29:51.231230 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 13:29:51.234310 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 13:29:51.237417 1 0 24 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2904 13:29:51.244326 1 0 28 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
2905 13:29:51.247400 1 1 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2906 13:29:51.250900 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 13:29:51.257816 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 13:29:51.260890 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 13:29:51.264130 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 13:29:51.270662 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 13:29:51.274397 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2912 13:29:51.277712 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2913 13:29:51.284185 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2914 13:29:51.287380 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 13:29:51.290398 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 13:29:51.294270 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 13:29:51.300576 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 13:29:51.303511 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 13:29:51.307256 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 13:29:51.313858 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 13:29:51.317235 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 13:29:51.320585 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 13:29:51.326840 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 13:29:51.330568 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 13:29:51.333715 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 13:29:51.340504 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 13:29:51.343630 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2928 13:29:51.346909 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2929 13:29:51.350485 Total UI for P1: 0, mck2ui 16
2930 13:29:51.354141 best dqsien dly found for B0: ( 1, 3, 24)
2931 13:29:51.360684 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 13:29:51.361118 Total UI for P1: 0, mck2ui 16
2933 13:29:51.366970 best dqsien dly found for B1: ( 1, 3, 30)
2934 13:29:51.370720 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2935 13:29:51.373829 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2936 13:29:51.374256
2937 13:29:51.376997 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2938 13:29:51.380662 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2939 13:29:51.383608 [Gating] SW calibration Done
2940 13:29:51.383991 ==
2941 13:29:51.387116 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 13:29:51.390376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 13:29:51.390915 ==
2944 13:29:51.393777 RX Vref Scan: 0
2945 13:29:51.394200
2946 13:29:51.394503 RX Vref 0 -> 0, step: 1
2947 13:29:51.394782
2948 13:29:51.397045 RX Delay -40 -> 252, step: 8
2949 13:29:51.400166 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2950 13:29:51.407066 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2951 13:29:51.410312 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2952 13:29:51.413360 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2953 13:29:51.416999 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2954 13:29:51.419884 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2955 13:29:51.426479 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2956 13:29:51.429996 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2957 13:29:51.433587 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2958 13:29:51.436797 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2959 13:29:51.439876 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2960 13:29:51.446671 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2961 13:29:51.449789 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2962 13:29:51.452824 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2963 13:29:51.455938 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2964 13:29:51.462618 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2965 13:29:51.463218 ==
2966 13:29:51.466121 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 13:29:51.469197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 13:29:51.469552 ==
2969 13:29:51.469868 DQS Delay:
2970 13:29:51.472392 DQS0 = 0, DQS1 = 0
2971 13:29:51.472914 DQM Delay:
2972 13:29:51.476104 DQM0 = 119, DQM1 = 107
2973 13:29:51.476613 DQ Delay:
2974 13:29:51.479310 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2975 13:29:51.482530 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2976 13:29:51.485587 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2977 13:29:51.488740 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =115
2978 13:29:51.492549
2979 13:29:51.492930
2980 13:29:51.493337 ==
2981 13:29:51.495626 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 13:29:51.498890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 13:29:51.499309 ==
2984 13:29:51.499766
2985 13:29:51.500199
2986 13:29:51.501995 TX Vref Scan disable
2987 13:29:51.502510 == TX Byte 0 ==
2988 13:29:51.508554 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2989 13:29:51.511858 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2990 13:29:51.512364 == TX Byte 1 ==
2991 13:29:51.518260 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2992 13:29:51.521575 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2993 13:29:51.521977 ==
2994 13:29:51.524927 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 13:29:51.528022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 13:29:51.528459 ==
2997 13:29:51.541803 TX Vref=22, minBit 13, minWin=25, winSum=416
2998 13:29:51.545465 TX Vref=24, minBit 12, minWin=25, winSum=419
2999 13:29:51.548315 TX Vref=26, minBit 1, minWin=26, winSum=426
3000 13:29:51.551547 TX Vref=28, minBit 10, minWin=26, winSum=428
3001 13:29:51.555334 TX Vref=30, minBit 4, minWin=26, winSum=426
3002 13:29:51.561532 TX Vref=32, minBit 5, minWin=26, winSum=427
3003 13:29:51.565196 [TxChooseVref] Worse bit 10, Min win 26, Win sum 428, Final Vref 28
3004 13:29:51.565605
3005 13:29:51.568367 Final TX Range 1 Vref 28
3006 13:29:51.568750
3007 13:29:51.569197 ==
3008 13:29:51.571728 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 13:29:51.577859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 13:29:51.578456 ==
3011 13:29:51.578993
3012 13:29:51.579431
3013 13:29:51.579849 TX Vref Scan disable
3014 13:29:51.582196 == TX Byte 0 ==
3015 13:29:51.585389 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3016 13:29:51.591616 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3017 13:29:51.592123 == TX Byte 1 ==
3018 13:29:51.594883 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3019 13:29:51.601875 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3020 13:29:51.602374
3021 13:29:51.602814 [DATLAT]
3022 13:29:51.603252 Freq=1200, CH0 RK1
3023 13:29:51.603676
3024 13:29:51.604923 DATLAT Default: 0xd
3025 13:29:51.608206 0, 0xFFFF, sum = 0
3026 13:29:51.608726 1, 0xFFFF, sum = 0
3027 13:29:51.611873 2, 0xFFFF, sum = 0
3028 13:29:51.612399 3, 0xFFFF, sum = 0
3029 13:29:51.615108 4, 0xFFFF, sum = 0
3030 13:29:51.615646 5, 0xFFFF, sum = 0
3031 13:29:51.618365 6, 0xFFFF, sum = 0
3032 13:29:51.618761 7, 0xFFFF, sum = 0
3033 13:29:51.621236 8, 0xFFFF, sum = 0
3034 13:29:51.621652 9, 0xFFFF, sum = 0
3035 13:29:51.624702 10, 0xFFFF, sum = 0
3036 13:29:51.625268 11, 0xFFFF, sum = 0
3037 13:29:51.628202 12, 0x0, sum = 1
3038 13:29:51.628681 13, 0x0, sum = 2
3039 13:29:51.631193 14, 0x0, sum = 3
3040 13:29:51.631718 15, 0x0, sum = 4
3041 13:29:51.634666 best_step = 13
3042 13:29:51.635077
3043 13:29:51.635540 ==
3044 13:29:51.637919 Dram Type= 6, Freq= 0, CH_0, rank 1
3045 13:29:51.641367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 13:29:51.641754 ==
3047 13:29:51.644495 RX Vref Scan: 0
3048 13:29:51.644879
3049 13:29:51.645222 RX Vref 0 -> 0, step: 1
3050 13:29:51.645539
3051 13:29:51.647688 RX Delay -21 -> 252, step: 4
3052 13:29:51.654281 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3053 13:29:51.657761 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
3054 13:29:51.661257 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
3055 13:29:51.664371 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3056 13:29:51.667505 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3057 13:29:51.673907 iDelay=195, Bit 5, Center 112 (51 ~ 174) 124
3058 13:29:51.677506 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3059 13:29:51.680365 iDelay=195, Bit 7, Center 124 (59 ~ 190) 132
3060 13:29:51.684236 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3061 13:29:51.687417 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3062 13:29:51.693697 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3063 13:29:51.697333 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3064 13:29:51.700651 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3065 13:29:51.703840 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3066 13:29:51.710042 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3067 13:29:51.713845 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3068 13:29:51.714235 ==
3069 13:29:51.716798 Dram Type= 6, Freq= 0, CH_0, rank 1
3070 13:29:51.719953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 13:29:51.720458 ==
3072 13:29:51.723767 DQS Delay:
3073 13:29:51.724289 DQS0 = 0, DQS1 = 0
3074 13:29:51.724682 DQM Delay:
3075 13:29:51.726951 DQM0 = 118, DQM1 = 106
3076 13:29:51.727481 DQ Delay:
3077 13:29:51.730396 DQ0 =114, DQ1 =118, DQ2 =114, DQ3 =114
3078 13:29:51.733705 DQ4 =120, DQ5 =112, DQ6 =128, DQ7 =124
3079 13:29:51.736687 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =98
3080 13:29:51.743130 DQ12 =112, DQ13 =112, DQ14 =120, DQ15 =114
3081 13:29:51.743637
3082 13:29:51.744098
3083 13:29:51.750184 [DQSOSCAuto] RK1, (LSB)MR18= 0xfdfb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
3084 13:29:51.753238 CH0 RK1: MR19=303, MR18=FDFB
3085 13:29:51.759948 CH0_RK1: MR19=0x303, MR18=0xFDFB, DQSOSC=411, MR23=63, INC=38, DEC=25
3086 13:29:51.763059 [RxdqsGatingPostProcess] freq 1200
3087 13:29:51.766372 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3088 13:29:51.769791 best DQS0 dly(2T, 0.5T) = (0, 11)
3089 13:29:51.773511 best DQS1 dly(2T, 0.5T) = (0, 12)
3090 13:29:51.776576 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3091 13:29:51.779506 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3092 13:29:51.782846 best DQS0 dly(2T, 0.5T) = (0, 11)
3093 13:29:51.786268 best DQS1 dly(2T, 0.5T) = (0, 11)
3094 13:29:51.789436 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3095 13:29:51.792967 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3096 13:29:51.796130 Pre-setting of DQS Precalculation
3097 13:29:51.799212 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3098 13:29:51.802825 ==
3099 13:29:51.803209 Dram Type= 6, Freq= 0, CH_1, rank 0
3100 13:29:51.809448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 13:29:51.809981 ==
3102 13:29:51.812430 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3103 13:29:51.818875 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3104 13:29:51.828239 [CA 0] Center 38 (8~68) winsize 61
3105 13:29:51.831541 [CA 1] Center 38 (8~68) winsize 61
3106 13:29:51.834879 [CA 2] Center 35 (5~65) winsize 61
3107 13:29:51.838141 [CA 3] Center 34 (4~64) winsize 61
3108 13:29:51.841379 [CA 4] Center 35 (5~65) winsize 61
3109 13:29:51.844442 [CA 5] Center 34 (4~64) winsize 61
3110 13:29:51.844828
3111 13:29:51.848085 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3112 13:29:51.848610
3113 13:29:51.851118 [CATrainingPosCal] consider 1 rank data
3114 13:29:51.854340 u2DelayCellTimex100 = 270/100 ps
3115 13:29:51.858069 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3116 13:29:51.864208 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3117 13:29:51.868030 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3118 13:29:51.871249 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3119 13:29:51.874539 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3120 13:29:51.877704 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3121 13:29:51.878593
3122 13:29:51.880592 CA PerBit enable=1, Macro0, CA PI delay=34
3123 13:29:51.881326
3124 13:29:51.884350 [CBTSetCACLKResult] CA Dly = 34
3125 13:29:51.887572 CS Dly: 5 (0~36)
3126 13:29:51.888033 ==
3127 13:29:51.890609 Dram Type= 6, Freq= 0, CH_1, rank 1
3128 13:29:51.894060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 13:29:51.894581 ==
3130 13:29:51.900425 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3131 13:29:51.903933 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3132 13:29:51.913797 [CA 0] Center 37 (7~68) winsize 62
3133 13:29:51.917342 [CA 1] Center 38 (8~68) winsize 61
3134 13:29:51.920517 [CA 2] Center 35 (5~65) winsize 61
3135 13:29:51.923739 [CA 3] Center 33 (3~64) winsize 62
3136 13:29:51.926767 [CA 4] Center 34 (4~64) winsize 61
3137 13:29:51.930057 [CA 5] Center 33 (3~64) winsize 62
3138 13:29:51.930442
3139 13:29:51.933909 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3140 13:29:51.934339
3141 13:29:51.936825 [CATrainingPosCal] consider 2 rank data
3142 13:29:51.940409 u2DelayCellTimex100 = 270/100 ps
3143 13:29:51.943489 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3144 13:29:51.949812 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3145 13:29:51.953550 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3146 13:29:51.956559 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3147 13:29:51.960169 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3148 13:29:51.963210 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3149 13:29:51.963640
3150 13:29:51.966281 CA PerBit enable=1, Macro0, CA PI delay=34
3151 13:29:51.966664
3152 13:29:51.969422 [CBTSetCACLKResult] CA Dly = 34
3153 13:29:51.972669 CS Dly: 6 (0~39)
3154 13:29:51.973020
3155 13:29:51.976512 ----->DramcWriteLeveling(PI) begin...
3156 13:29:51.976910 ==
3157 13:29:51.979823 Dram Type= 6, Freq= 0, CH_1, rank 0
3158 13:29:51.982912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3159 13:29:51.983309 ==
3160 13:29:51.985948 Write leveling (Byte 0): 26 => 26
3161 13:29:51.989171 Write leveling (Byte 1): 27 => 27
3162 13:29:51.992884 DramcWriteLeveling(PI) end<-----
3163 13:29:51.993396
3164 13:29:51.993700 ==
3165 13:29:51.996032 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 13:29:51.999116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 13:29:51.999504 ==
3168 13:29:52.002669 [Gating] SW mode calibration
3169 13:29:52.009035 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3170 13:29:52.015441 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3171 13:29:52.019353 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3172 13:29:52.022470 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3173 13:29:52.029230 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3174 13:29:52.032744 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3175 13:29:52.035861 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 13:29:52.042302 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 13:29:52.045599 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
3178 13:29:52.048979 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (1 0)
3179 13:29:52.055828 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 13:29:52.058847 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3181 13:29:52.065454 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3182 13:29:52.068184 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 13:29:52.071753 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 13:29:52.078210 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 13:29:52.081985 1 0 24 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
3186 13:29:52.085095 1 0 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
3187 13:29:52.091860 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 13:29:52.095059 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 13:29:52.098322 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 13:29:52.101521 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 13:29:52.108382 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 13:29:52.111361 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 13:29:52.117679 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 13:29:52.121605 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3195 13:29:52.124733 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3196 13:29:52.131454 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 13:29:52.134688 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 13:29:52.137909 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 13:29:52.144639 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 13:29:52.147794 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 13:29:52.150728 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 13:29:52.154204 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 13:29:52.160645 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 13:29:52.164050 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 13:29:52.167684 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 13:29:52.173906 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 13:29:52.177713 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 13:29:52.183785 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 13:29:52.187331 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3210 13:29:52.190515 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3211 13:29:52.196771 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 13:29:52.197290 Total UI for P1: 0, mck2ui 16
3213 13:29:52.203684 best dqsien dly found for B0: ( 1, 3, 26)
3214 13:29:52.204165 Total UI for P1: 0, mck2ui 16
3215 13:29:52.206867 best dqsien dly found for B1: ( 1, 3, 26)
3216 13:29:52.213285 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3217 13:29:52.217080 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3218 13:29:52.217517
3219 13:29:52.220001 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3220 13:29:52.223030 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3221 13:29:52.226427 [Gating] SW calibration Done
3222 13:29:52.226945 ==
3223 13:29:52.229698 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 13:29:52.233302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 13:29:52.233689 ==
3226 13:29:52.236418 RX Vref Scan: 0
3227 13:29:52.236795
3228 13:29:52.237091 RX Vref 0 -> 0, step: 1
3229 13:29:52.237420
3230 13:29:52.239528 RX Delay -40 -> 252, step: 8
3231 13:29:52.242873 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3232 13:29:52.249372 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3233 13:29:52.252551 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3234 13:29:52.255768 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3235 13:29:52.259454 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3236 13:29:52.265664 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3237 13:29:52.268794 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3238 13:29:52.272330 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3239 13:29:52.275415 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3240 13:29:52.279037 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3241 13:29:52.285599 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3242 13:29:52.288759 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3243 13:29:52.291925 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3244 13:29:52.295153 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3245 13:29:52.302052 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3246 13:29:52.305399 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3247 13:29:52.305737 ==
3248 13:29:52.308700 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 13:29:52.311949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 13:29:52.312222 ==
3251 13:29:52.312444 DQS Delay:
3252 13:29:52.315106 DQS0 = 0, DQS1 = 0
3253 13:29:52.315534 DQM Delay:
3254 13:29:52.318251 DQM0 = 116, DQM1 = 112
3255 13:29:52.318564 DQ Delay:
3256 13:29:52.321574 DQ0 =119, DQ1 =115, DQ2 =107, DQ3 =119
3257 13:29:52.324699 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3258 13:29:52.327791 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3259 13:29:52.334203 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3260 13:29:52.334277
3261 13:29:52.334335
3262 13:29:52.334388 ==
3263 13:29:52.337843 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 13:29:52.341159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 13:29:52.341246 ==
3266 13:29:52.341305
3267 13:29:52.341359
3268 13:29:52.344235 TX Vref Scan disable
3269 13:29:52.344308 == TX Byte 0 ==
3270 13:29:52.351175 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3271 13:29:52.354340 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3272 13:29:52.354416 == TX Byte 1 ==
3273 13:29:52.360736 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3274 13:29:52.363839 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3275 13:29:52.363915 ==
3276 13:29:52.367548 Dram Type= 6, Freq= 0, CH_1, rank 0
3277 13:29:52.370618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3278 13:29:52.370695 ==
3279 13:29:52.383956 TX Vref=22, minBit 0, minWin=25, winSum=414
3280 13:29:52.387112 TX Vref=24, minBit 11, minWin=25, winSum=421
3281 13:29:52.390068 TX Vref=26, minBit 9, minWin=25, winSum=425
3282 13:29:52.393429 TX Vref=28, minBit 6, minWin=26, winSum=430
3283 13:29:52.397079 TX Vref=30, minBit 2, minWin=26, winSum=430
3284 13:29:52.403578 TX Vref=32, minBit 2, minWin=26, winSum=427
3285 13:29:52.406655 [TxChooseVref] Worse bit 6, Min win 26, Win sum 430, Final Vref 28
3286 13:29:52.406731
3287 13:29:52.410159 Final TX Range 1 Vref 28
3288 13:29:52.410235
3289 13:29:52.410294 ==
3290 13:29:52.413181 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 13:29:52.416601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 13:29:52.420036 ==
3293 13:29:52.420112
3294 13:29:52.420170
3295 13:29:52.420224 TX Vref Scan disable
3296 13:29:52.423131 == TX Byte 0 ==
3297 13:29:52.426763 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3298 13:29:52.432969 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3299 13:29:52.433046 == TX Byte 1 ==
3300 13:29:52.436778 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3301 13:29:52.443391 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3302 13:29:52.443467
3303 13:29:52.443526 [DATLAT]
3304 13:29:52.443581 Freq=1200, CH1 RK0
3305 13:29:52.443634
3306 13:29:52.446178 DATLAT Default: 0xd
3307 13:29:52.449877 0, 0xFFFF, sum = 0
3308 13:29:52.449955 1, 0xFFFF, sum = 0
3309 13:29:52.452847 2, 0xFFFF, sum = 0
3310 13:29:52.452923 3, 0xFFFF, sum = 0
3311 13:29:52.455943 4, 0xFFFF, sum = 0
3312 13:29:52.456021 5, 0xFFFF, sum = 0
3313 13:29:52.459489 6, 0xFFFF, sum = 0
3314 13:29:52.459566 7, 0xFFFF, sum = 0
3315 13:29:52.462633 8, 0xFFFF, sum = 0
3316 13:29:52.462710 9, 0xFFFF, sum = 0
3317 13:29:52.465865 10, 0xFFFF, sum = 0
3318 13:29:52.465940 11, 0xFFFF, sum = 0
3319 13:29:52.469079 12, 0x0, sum = 1
3320 13:29:52.469177 13, 0x0, sum = 2
3321 13:29:52.472636 14, 0x0, sum = 3
3322 13:29:52.472726 15, 0x0, sum = 4
3323 13:29:52.475728 best_step = 13
3324 13:29:52.475801
3325 13:29:52.475858 ==
3326 13:29:52.478982 Dram Type= 6, Freq= 0, CH_1, rank 0
3327 13:29:52.482804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3328 13:29:52.482879 ==
3329 13:29:52.486054 RX Vref Scan: 1
3330 13:29:52.486128
3331 13:29:52.486185 Set Vref Range= 32 -> 127
3332 13:29:52.486239
3333 13:29:52.489149 RX Vref 32 -> 127, step: 1
3334 13:29:52.489236
3335 13:29:52.492503 RX Delay -13 -> 252, step: 4
3336 13:29:52.492577
3337 13:29:52.495629 Set Vref, RX VrefLevel [Byte0]: 32
3338 13:29:52.499155 [Byte1]: 32
3339 13:29:52.499229
3340 13:29:52.501995 Set Vref, RX VrefLevel [Byte0]: 33
3341 13:29:52.505811 [Byte1]: 33
3342 13:29:52.509781
3343 13:29:52.509855 Set Vref, RX VrefLevel [Byte0]: 34
3344 13:29:52.512904 [Byte1]: 34
3345 13:29:52.517817
3346 13:29:52.517891 Set Vref, RX VrefLevel [Byte0]: 35
3347 13:29:52.521030 [Byte1]: 35
3348 13:29:52.525481
3349 13:29:52.525555 Set Vref, RX VrefLevel [Byte0]: 36
3350 13:29:52.528554 [Byte1]: 36
3351 13:29:52.533050
3352 13:29:52.533124 Set Vref, RX VrefLevel [Byte0]: 37
3353 13:29:52.536533 [Byte1]: 37
3354 13:29:52.541328
3355 13:29:52.541402 Set Vref, RX VrefLevel [Byte0]: 38
3356 13:29:52.544520 [Byte1]: 38
3357 13:29:52.548888
3358 13:29:52.548987 Set Vref, RX VrefLevel [Byte0]: 39
3359 13:29:52.552473 [Byte1]: 39
3360 13:29:52.557115
3361 13:29:52.557229 Set Vref, RX VrefLevel [Byte0]: 40
3362 13:29:52.560050 [Byte1]: 40
3363 13:29:52.564642
3364 13:29:52.564716 Set Vref, RX VrefLevel [Byte0]: 41
3365 13:29:52.568356 [Byte1]: 41
3366 13:29:52.572582
3367 13:29:52.572678 Set Vref, RX VrefLevel [Byte0]: 42
3368 13:29:52.576182 [Byte1]: 42
3369 13:29:52.580468
3370 13:29:52.580562 Set Vref, RX VrefLevel [Byte0]: 43
3371 13:29:52.583645 [Byte1]: 43
3372 13:29:52.588659
3373 13:29:52.588750 Set Vref, RX VrefLevel [Byte0]: 44
3374 13:29:52.591839 [Byte1]: 44
3375 13:29:52.596446
3376 13:29:52.596515 Set Vref, RX VrefLevel [Byte0]: 45
3377 13:29:52.599566 [Byte1]: 45
3378 13:29:52.604040
3379 13:29:52.604141 Set Vref, RX VrefLevel [Byte0]: 46
3380 13:29:52.607703 [Byte1]: 46
3381 13:29:52.612261
3382 13:29:52.612376 Set Vref, RX VrefLevel [Byte0]: 47
3383 13:29:52.615519 [Byte1]: 47
3384 13:29:52.619896
3385 13:29:52.619969 Set Vref, RX VrefLevel [Byte0]: 48
3386 13:29:52.623077 [Byte1]: 48
3387 13:29:52.628140
3388 13:29:52.628237 Set Vref, RX VrefLevel [Byte0]: 49
3389 13:29:52.631299 [Byte1]: 49
3390 13:29:52.635763
3391 13:29:52.635836 Set Vref, RX VrefLevel [Byte0]: 50
3392 13:29:52.638840 [Byte1]: 50
3393 13:29:52.643818
3394 13:29:52.643891 Set Vref, RX VrefLevel [Byte0]: 51
3395 13:29:52.646838 [Byte1]: 51
3396 13:29:52.651680
3397 13:29:52.651753 Set Vref, RX VrefLevel [Byte0]: 52
3398 13:29:52.654975 [Byte1]: 52
3399 13:29:52.659130
3400 13:29:52.659203 Set Vref, RX VrefLevel [Byte0]: 53
3401 13:29:52.662505 [Byte1]: 53
3402 13:29:52.667168
3403 13:29:52.667242 Set Vref, RX VrefLevel [Byte0]: 54
3404 13:29:52.670612 [Byte1]: 54
3405 13:29:52.675059
3406 13:29:52.675132 Set Vref, RX VrefLevel [Byte0]: 55
3407 13:29:52.678601 [Byte1]: 55
3408 13:29:52.683231
3409 13:29:52.683304 Set Vref, RX VrefLevel [Byte0]: 56
3410 13:29:52.686171 [Byte1]: 56
3411 13:29:52.690713
3412 13:29:52.690787 Set Vref, RX VrefLevel [Byte0]: 57
3413 13:29:52.693911 [Byte1]: 57
3414 13:29:52.698968
3415 13:29:52.699041 Set Vref, RX VrefLevel [Byte0]: 58
3416 13:29:52.702080 [Byte1]: 58
3417 13:29:52.706548
3418 13:29:52.706645 Set Vref, RX VrefLevel [Byte0]: 59
3419 13:29:52.709832 [Byte1]: 59
3420 13:29:52.714755
3421 13:29:52.714827 Set Vref, RX VrefLevel [Byte0]: 60
3422 13:29:52.717848 [Byte1]: 60
3423 13:29:52.722664
3424 13:29:52.722736 Set Vref, RX VrefLevel [Byte0]: 61
3425 13:29:52.725448 [Byte1]: 61
3426 13:29:52.730391
3427 13:29:52.730482 Set Vref, RX VrefLevel [Byte0]: 62
3428 13:29:52.733846 [Byte1]: 62
3429 13:29:52.738194
3430 13:29:52.738267 Set Vref, RX VrefLevel [Byte0]: 63
3431 13:29:52.741310 [Byte1]: 63
3432 13:29:52.746147
3433 13:29:52.746221 Set Vref, RX VrefLevel [Byte0]: 64
3434 13:29:52.749318 [Byte1]: 64
3435 13:29:52.753894
3436 13:29:52.753999 Final RX Vref Byte 0 = 52 to rank0
3437 13:29:52.757005 Final RX Vref Byte 1 = 51 to rank0
3438 13:29:52.760855 Final RX Vref Byte 0 = 52 to rank1
3439 13:29:52.763931 Final RX Vref Byte 1 = 51 to rank1==
3440 13:29:52.766905 Dram Type= 6, Freq= 0, CH_1, rank 0
3441 13:29:52.773522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3442 13:29:52.773598 ==
3443 13:29:52.773656 DQS Delay:
3444 13:29:52.776709 DQS0 = 0, DQS1 = 0
3445 13:29:52.776847 DQM Delay:
3446 13:29:52.776933 DQM0 = 114, DQM1 = 112
3447 13:29:52.780325 DQ Delay:
3448 13:29:52.783805 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3449 13:29:52.786572 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3450 13:29:52.790055 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3451 13:29:52.793357 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =120
3452 13:29:52.793423
3453 13:29:52.793479
3454 13:29:52.803489 [DQSOSCAuto] RK0, (LSB)MR18= 0xf703, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 413 ps
3455 13:29:52.803588 CH1 RK0: MR19=304, MR18=F703
3456 13:29:52.810022 CH1_RK0: MR19=0x304, MR18=0xF703, DQSOSC=408, MR23=63, INC=39, DEC=26
3457 13:29:52.810098
3458 13:29:52.813110 ----->DramcWriteLeveling(PI) begin...
3459 13:29:52.813226 ==
3460 13:29:52.816282 Dram Type= 6, Freq= 0, CH_1, rank 1
3461 13:29:52.823138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3462 13:29:52.823293 ==
3463 13:29:52.826209 Write leveling (Byte 0): 25 => 25
3464 13:29:52.829342 Write leveling (Byte 1): 27 => 27
3465 13:29:52.832829 DramcWriteLeveling(PI) end<-----
3466 13:29:52.832903
3467 13:29:52.832961 ==
3468 13:29:52.836410 Dram Type= 6, Freq= 0, CH_1, rank 1
3469 13:29:52.839226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3470 13:29:52.839301 ==
3471 13:29:52.842555 [Gating] SW mode calibration
3472 13:29:52.849391 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3473 13:29:52.855619 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3474 13:29:52.858753 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3475 13:29:52.862501 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3476 13:29:52.868863 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3477 13:29:52.871981 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 13:29:52.875119 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3479 13:29:52.881783 0 15 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3480 13:29:52.885177 0 15 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
3481 13:29:52.888524 0 15 28 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
3482 13:29:52.895167 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3483 13:29:52.898374 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3484 13:29:52.901419 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3485 13:29:52.908244 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 13:29:52.911521 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3487 13:29:52.914847 1 0 20 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
3488 13:29:52.921015 1 0 24 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
3489 13:29:52.924861 1 0 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
3490 13:29:52.927966 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 13:29:52.934390 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 13:29:52.937441 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 13:29:52.941175 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 13:29:52.947716 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 13:29:52.950683 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 13:29:52.954056 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3497 13:29:52.960720 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3498 13:29:52.963847 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 13:29:52.967068 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 13:29:52.973977 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 13:29:52.977128 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 13:29:52.980355 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 13:29:52.987165 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 13:29:52.990204 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 13:29:52.993680 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 13:29:53.000139 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 13:29:53.003648 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 13:29:53.006726 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 13:29:53.013017 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 13:29:53.016612 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 13:29:53.020158 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3512 13:29:53.026478 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3513 13:29:53.029665 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3514 13:29:53.033337 Total UI for P1: 0, mck2ui 16
3515 13:29:53.036404 best dqsien dly found for B0: ( 1, 3, 22)
3516 13:29:53.039454 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 13:29:53.043170 Total UI for P1: 0, mck2ui 16
3518 13:29:53.046433 best dqsien dly found for B1: ( 1, 3, 26)
3519 13:29:53.049511 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3520 13:29:53.056446 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3521 13:29:53.056550
3522 13:29:53.059485 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3523 13:29:53.062926 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3524 13:29:53.065763 [Gating] SW calibration Done
3525 13:29:53.065861 ==
3526 13:29:53.069479 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 13:29:53.072635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 13:29:53.072730 ==
3529 13:29:53.075801 RX Vref Scan: 0
3530 13:29:53.075893
3531 13:29:53.075979 RX Vref 0 -> 0, step: 1
3532 13:29:53.076059
3533 13:29:53.078948 RX Delay -40 -> 252, step: 8
3534 13:29:53.082233 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3535 13:29:53.089050 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3536 13:29:53.092321 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3537 13:29:53.095948 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3538 13:29:53.099064 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3539 13:29:53.102064 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3540 13:29:53.108902 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3541 13:29:53.111820 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3542 13:29:53.115589 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3543 13:29:53.118719 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3544 13:29:53.121770 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3545 13:29:53.128618 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3546 13:29:53.131723 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3547 13:29:53.134815 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3548 13:29:53.138374 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3549 13:29:53.144633 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3550 13:29:53.144735 ==
3551 13:29:53.148345 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 13:29:53.151439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 13:29:53.151542 ==
3554 13:29:53.151602 DQS Delay:
3555 13:29:53.155277 DQS0 = 0, DQS1 = 0
3556 13:29:53.155372 DQM Delay:
3557 13:29:53.158407 DQM0 = 114, DQM1 = 111
3558 13:29:53.158507 DQ Delay:
3559 13:29:53.161492 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3560 13:29:53.164635 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =111
3561 13:29:53.168293 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3562 13:29:53.171193 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3563 13:29:53.171287
3564 13:29:53.171371
3565 13:29:53.174697 ==
3566 13:29:53.174789 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 13:29:53.180890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 13:29:53.180988 ==
3569 13:29:53.181071
3570 13:29:53.181175
3571 13:29:53.184792 TX Vref Scan disable
3572 13:29:53.184888 == TX Byte 0 ==
3573 13:29:53.188038 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3574 13:29:53.194278 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3575 13:29:53.194349 == TX Byte 1 ==
3576 13:29:53.197450 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3577 13:29:53.204072 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3578 13:29:53.204166 ==
3579 13:29:53.207707 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 13:29:53.210803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 13:29:53.210904 ==
3582 13:29:53.223128 TX Vref=22, minBit 9, minWin=25, winSum=421
3583 13:29:53.226061 TX Vref=24, minBit 3, minWin=25, winSum=425
3584 13:29:53.229315 TX Vref=26, minBit 1, minWin=26, winSum=427
3585 13:29:53.232810 TX Vref=28, minBit 2, minWin=26, winSum=429
3586 13:29:53.235922 TX Vref=30, minBit 1, minWin=26, winSum=432
3587 13:29:53.242253 TX Vref=32, minBit 9, minWin=26, winSum=434
3588 13:29:53.246083 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 32
3589 13:29:53.246178
3590 13:29:53.249052 Final TX Range 1 Vref 32
3591 13:29:53.249183
3592 13:29:53.249269 ==
3593 13:29:53.252272 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 13:29:53.258889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 13:29:53.258985 ==
3596 13:29:53.259070
3597 13:29:53.259150
3598 13:29:53.259249 TX Vref Scan disable
3599 13:29:53.262440 == TX Byte 0 ==
3600 13:29:53.265512 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3601 13:29:53.272191 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3602 13:29:53.272288 == TX Byte 1 ==
3603 13:29:53.275935 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3604 13:29:53.281974 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3605 13:29:53.282068
3606 13:29:53.282155 [DATLAT]
3607 13:29:53.282240 Freq=1200, CH1 RK1
3608 13:29:53.282326
3609 13:29:53.285537 DATLAT Default: 0xd
3610 13:29:53.288764 0, 0xFFFF, sum = 0
3611 13:29:53.288861 1, 0xFFFF, sum = 0
3612 13:29:53.291956 2, 0xFFFF, sum = 0
3613 13:29:53.292057 3, 0xFFFF, sum = 0
3614 13:29:53.295083 4, 0xFFFF, sum = 0
3615 13:29:53.295191 5, 0xFFFF, sum = 0
3616 13:29:53.298829 6, 0xFFFF, sum = 0
3617 13:29:53.298929 7, 0xFFFF, sum = 0
3618 13:29:53.301954 8, 0xFFFF, sum = 0
3619 13:29:53.302063 9, 0xFFFF, sum = 0
3620 13:29:53.305143 10, 0xFFFF, sum = 0
3621 13:29:53.305284 11, 0xFFFF, sum = 0
3622 13:29:53.308569 12, 0x0, sum = 1
3623 13:29:53.308672 13, 0x0, sum = 2
3624 13:29:53.311680 14, 0x0, sum = 3
3625 13:29:53.311783 15, 0x0, sum = 4
3626 13:29:53.315531 best_step = 13
3627 13:29:53.315606
3628 13:29:53.315664 ==
3629 13:29:53.318831 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 13:29:53.321982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 13:29:53.322059 ==
3632 13:29:53.325006 RX Vref Scan: 0
3633 13:29:53.325153
3634 13:29:53.325231 RX Vref 0 -> 0, step: 1
3635 13:29:53.325287
3636 13:29:53.328563 RX Delay -13 -> 252, step: 4
3637 13:29:53.334960 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3638 13:29:53.338597 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3639 13:29:53.341849 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3640 13:29:53.344916 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3641 13:29:53.348074 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3642 13:29:53.355114 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3643 13:29:53.358251 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3644 13:29:53.361385 iDelay=195, Bit 7, Center 114 (47 ~ 182) 136
3645 13:29:53.364811 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3646 13:29:53.368265 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3647 13:29:53.375010 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3648 13:29:53.377745 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3649 13:29:53.381336 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3650 13:29:53.384439 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3651 13:29:53.391059 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3652 13:29:53.394181 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3653 13:29:53.394255 ==
3654 13:29:53.397964 Dram Type= 6, Freq= 0, CH_1, rank 1
3655 13:29:53.400993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3656 13:29:53.401091 ==
3657 13:29:53.404190 DQS Delay:
3658 13:29:53.404264 DQS0 = 0, DQS1 = 0
3659 13:29:53.404322 DQM Delay:
3660 13:29:53.407844 DQM0 = 115, DQM1 = 112
3661 13:29:53.407918 DQ Delay:
3662 13:29:53.411069 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =112
3663 13:29:53.413978 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3664 13:29:53.417634 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3665 13:29:53.423987 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =120
3666 13:29:53.424081
3667 13:29:53.424163
3668 13:29:53.430985 [DQSOSCAuto] RK1, (LSB)MR18= 0xf507, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
3669 13:29:53.434004 CH1 RK1: MR19=304, MR18=F507
3670 13:29:53.440539 CH1_RK1: MR19=0x304, MR18=0xF507, DQSOSC=407, MR23=63, INC=39, DEC=26
3671 13:29:53.444035 [RxdqsGatingPostProcess] freq 1200
3672 13:29:53.447051 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3673 13:29:53.450336 best DQS0 dly(2T, 0.5T) = (0, 11)
3674 13:29:53.453589 best DQS1 dly(2T, 0.5T) = (0, 11)
3675 13:29:53.457414 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3676 13:29:53.460504 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3677 13:29:53.463684 best DQS0 dly(2T, 0.5T) = (0, 11)
3678 13:29:53.466851 best DQS1 dly(2T, 0.5T) = (0, 11)
3679 13:29:53.469959 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3680 13:29:53.473693 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3681 13:29:53.476611 Pre-setting of DQS Precalculation
3682 13:29:53.483085 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3683 13:29:53.489802 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3684 13:29:53.496176 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3685 13:29:53.496276
3686 13:29:53.496403
3687 13:29:53.499580 [Calibration Summary] 2400 Mbps
3688 13:29:53.499672 CH 0, Rank 0
3689 13:29:53.502610 SW Impedance : PASS
3690 13:29:53.505810 DUTY Scan : NO K
3691 13:29:53.505902 ZQ Calibration : PASS
3692 13:29:53.509599 Jitter Meter : NO K
3693 13:29:53.512473 CBT Training : PASS
3694 13:29:53.512565 Write leveling : PASS
3695 13:29:53.516180 RX DQS gating : PASS
3696 13:29:53.519192 RX DQ/DQS(RDDQC) : PASS
3697 13:29:53.519289 TX DQ/DQS : PASS
3698 13:29:53.522297 RX DATLAT : PASS
3699 13:29:53.525963 RX DQ/DQS(Engine): PASS
3700 13:29:53.526056 TX OE : NO K
3701 13:29:53.529025 All Pass.
3702 13:29:53.529116
3703 13:29:53.529223 CH 0, Rank 1
3704 13:29:53.532242 SW Impedance : PASS
3705 13:29:53.532339 DUTY Scan : NO K
3706 13:29:53.535365 ZQ Calibration : PASS
3707 13:29:53.539232 Jitter Meter : NO K
3708 13:29:53.539328 CBT Training : PASS
3709 13:29:53.542261 Write leveling : PASS
3710 13:29:53.545689 RX DQS gating : PASS
3711 13:29:53.545764 RX DQ/DQS(RDDQC) : PASS
3712 13:29:53.548891 TX DQ/DQS : PASS
3713 13:29:53.551805 RX DATLAT : PASS
3714 13:29:53.551898 RX DQ/DQS(Engine): PASS
3715 13:29:53.555389 TX OE : NO K
3716 13:29:53.555482 All Pass.
3717 13:29:53.555572
3718 13:29:53.558539 CH 1, Rank 0
3719 13:29:53.558615 SW Impedance : PASS
3720 13:29:53.561716 DUTY Scan : NO K
3721 13:29:53.561791 ZQ Calibration : PASS
3722 13:29:53.564947 Jitter Meter : NO K
3723 13:29:53.568634 CBT Training : PASS
3724 13:29:53.568709 Write leveling : PASS
3725 13:29:53.571863 RX DQS gating : PASS
3726 13:29:53.575021 RX DQ/DQS(RDDQC) : PASS
3727 13:29:53.575097 TX DQ/DQS : PASS
3728 13:29:53.578226 RX DATLAT : PASS
3729 13:29:53.582004 RX DQ/DQS(Engine): PASS
3730 13:29:53.582079 TX OE : NO K
3731 13:29:53.585051 All Pass.
3732 13:29:53.585196
3733 13:29:53.585342 CH 1, Rank 1
3734 13:29:53.588205 SW Impedance : PASS
3735 13:29:53.588293 DUTY Scan : NO K
3736 13:29:53.591719 ZQ Calibration : PASS
3737 13:29:53.595156 Jitter Meter : NO K
3738 13:29:53.595236 CBT Training : PASS
3739 13:29:53.598227 Write leveling : PASS
3740 13:29:53.601757 RX DQS gating : PASS
3741 13:29:53.601850 RX DQ/DQS(RDDQC) : PASS
3742 13:29:53.604724 TX DQ/DQS : PASS
3743 13:29:53.608260 RX DATLAT : PASS
3744 13:29:53.608365 RX DQ/DQS(Engine): PASS
3745 13:29:53.611450 TX OE : NO K
3746 13:29:53.611526 All Pass.
3747 13:29:53.611584
3748 13:29:53.614807 DramC Write-DBI off
3749 13:29:53.617819 PER_BANK_REFRESH: Hybrid Mode
3750 13:29:53.617894 TX_TRACKING: ON
3751 13:29:53.627627 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3752 13:29:53.630734 [FAST_K] Save calibration result to emmc
3753 13:29:53.634658 dramc_set_vcore_voltage set vcore to 650000
3754 13:29:53.637801 Read voltage for 600, 5
3755 13:29:53.637876 Vio18 = 0
3756 13:29:53.637935 Vcore = 650000
3757 13:29:53.640957 Vdram = 0
3758 13:29:53.641048 Vddq = 0
3759 13:29:53.641109 Vmddr = 0
3760 13:29:53.647197 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3761 13:29:53.650915 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3762 13:29:53.654029 MEM_TYPE=3, freq_sel=19
3763 13:29:53.657375 sv_algorithm_assistance_LP4_1600
3764 13:29:53.660226 ============ PULL DRAM RESETB DOWN ============
3765 13:29:53.667060 ========== PULL DRAM RESETB DOWN end =========
3766 13:29:53.670736 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3767 13:29:53.673938 ===================================
3768 13:29:53.677073 LPDDR4 DRAM CONFIGURATION
3769 13:29:53.680209 ===================================
3770 13:29:53.680304 EX_ROW_EN[0] = 0x0
3771 13:29:53.683492 EX_ROW_EN[1] = 0x0
3772 13:29:53.683598 LP4Y_EN = 0x0
3773 13:29:53.687188 WORK_FSP = 0x0
3774 13:29:53.687282 WL = 0x2
3775 13:29:53.690301 RL = 0x2
3776 13:29:53.690406 BL = 0x2
3777 13:29:53.693421 RPST = 0x0
3778 13:29:53.696918 RD_PRE = 0x0
3779 13:29:53.697021 WR_PRE = 0x1
3780 13:29:53.700075 WR_PST = 0x0
3781 13:29:53.700261 DBI_WR = 0x0
3782 13:29:53.703599 DBI_RD = 0x0
3783 13:29:53.703708 OTF = 0x1
3784 13:29:53.706602 ===================================
3785 13:29:53.710382 ===================================
3786 13:29:53.713501 ANA top config
3787 13:29:53.716594 ===================================
3788 13:29:53.716687 DLL_ASYNC_EN = 0
3789 13:29:53.720094 ALL_SLAVE_EN = 1
3790 13:29:53.723349 NEW_RANK_MODE = 1
3791 13:29:53.726500 DLL_IDLE_MODE = 1
3792 13:29:53.726591 LP45_APHY_COMB_EN = 1
3793 13:29:53.729703 TX_ODT_DIS = 1
3794 13:29:53.733293 NEW_8X_MODE = 1
3795 13:29:53.736669 ===================================
3796 13:29:53.739735 ===================================
3797 13:29:53.742701 data_rate = 1200
3798 13:29:53.746452 CKR = 1
3799 13:29:53.749565 DQ_P2S_RATIO = 8
3800 13:29:53.752669 ===================================
3801 13:29:53.752738 CA_P2S_RATIO = 8
3802 13:29:53.756439 DQ_CA_OPEN = 0
3803 13:29:53.759702 DQ_SEMI_OPEN = 0
3804 13:29:53.762645 CA_SEMI_OPEN = 0
3805 13:29:53.766117 CA_FULL_RATE = 0
3806 13:29:53.769488 DQ_CKDIV4_EN = 1
3807 13:29:53.769589 CA_CKDIV4_EN = 1
3808 13:29:53.772667 CA_PREDIV_EN = 0
3809 13:29:53.775895 PH8_DLY = 0
3810 13:29:53.779085 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3811 13:29:53.782319 DQ_AAMCK_DIV = 4
3812 13:29:53.785418 CA_AAMCK_DIV = 4
3813 13:29:53.789324 CA_ADMCK_DIV = 4
3814 13:29:53.789391 DQ_TRACK_CA_EN = 0
3815 13:29:53.792404 CA_PICK = 600
3816 13:29:53.795481 CA_MCKIO = 600
3817 13:29:53.799128 MCKIO_SEMI = 0
3818 13:29:53.802358 PLL_FREQ = 2288
3819 13:29:53.805417 DQ_UI_PI_RATIO = 32
3820 13:29:53.808980 CA_UI_PI_RATIO = 0
3821 13:29:53.812035 ===================================
3822 13:29:53.815290 ===================================
3823 13:29:53.815385 memory_type:LPDDR4
3824 13:29:53.818374 GP_NUM : 10
3825 13:29:53.821575 SRAM_EN : 1
3826 13:29:53.821642 MD32_EN : 0
3827 13:29:53.824812 ===================================
3828 13:29:53.828525 [ANA_INIT] >>>>>>>>>>>>>>
3829 13:29:53.831536 <<<<<< [CONFIGURE PHASE]: ANA_TX
3830 13:29:53.835105 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3831 13:29:53.838347 ===================================
3832 13:29:53.841314 data_rate = 1200,PCW = 0X5800
3833 13:29:53.844932 ===================================
3834 13:29:53.848495 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3835 13:29:53.851273 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3836 13:29:53.857968 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3837 13:29:53.861481 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3838 13:29:53.864509 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3839 13:29:53.871377 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3840 13:29:53.871470 [ANA_INIT] flow start
3841 13:29:53.874271 [ANA_INIT] PLL >>>>>>>>
3842 13:29:53.877681 [ANA_INIT] PLL <<<<<<<<
3843 13:29:53.877750 [ANA_INIT] MIDPI >>>>>>>>
3844 13:29:53.880766 [ANA_INIT] MIDPI <<<<<<<<
3845 13:29:53.884491 [ANA_INIT] DLL >>>>>>>>
3846 13:29:53.884688 [ANA_INIT] flow end
3847 13:29:53.891018 ============ LP4 DIFF to SE enter ============
3848 13:29:53.894147 ============ LP4 DIFF to SE exit ============
3849 13:29:53.894242 [ANA_INIT] <<<<<<<<<<<<<
3850 13:29:53.897491 [Flow] Enable top DCM control >>>>>
3851 13:29:53.900552 [Flow] Enable top DCM control <<<<<
3852 13:29:53.904116 Enable DLL master slave shuffle
3853 13:29:53.910489 ==============================================================
3854 13:29:53.914063 Gating Mode config
3855 13:29:53.917100 ==============================================================
3856 13:29:53.920297 Config description:
3857 13:29:53.930375 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3858 13:29:53.937216 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3859 13:29:53.940194 SELPH_MODE 0: By rank 1: By Phase
3860 13:29:53.947139 ==============================================================
3861 13:29:53.950446 GAT_TRACK_EN = 1
3862 13:29:53.953641 RX_GATING_MODE = 2
3863 13:29:53.956699 RX_GATING_TRACK_MODE = 2
3864 13:29:53.959803 SELPH_MODE = 1
3865 13:29:53.959897 PICG_EARLY_EN = 1
3866 13:29:53.963380 VALID_LAT_VALUE = 1
3867 13:29:53.969805 ==============================================================
3868 13:29:53.973079 Enter into Gating configuration >>>>
3869 13:29:53.976472 Exit from Gating configuration <<<<
3870 13:29:53.979984 Enter into DVFS_PRE_config >>>>>
3871 13:29:53.989725 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3872 13:29:53.993358 Exit from DVFS_PRE_config <<<<<
3873 13:29:53.996427 Enter into PICG configuration >>>>
3874 13:29:53.999542 Exit from PICG configuration <<<<
3875 13:29:54.002694 [RX_INPUT] configuration >>>>>
3876 13:29:54.006465 [RX_INPUT] configuration <<<<<
3877 13:29:54.012565 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3878 13:29:54.016115 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3879 13:29:54.022421 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3880 13:29:54.029107 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3881 13:29:54.035514 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3882 13:29:54.042311 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3883 13:29:54.045316 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3884 13:29:54.048722 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3885 13:29:54.052513 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3886 13:29:54.058767 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3887 13:29:54.062031 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3888 13:29:54.065705 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3889 13:29:54.068763 ===================================
3890 13:29:54.071887 LPDDR4 DRAM CONFIGURATION
3891 13:29:54.075646 ===================================
3892 13:29:54.078740 EX_ROW_EN[0] = 0x0
3893 13:29:54.078816 EX_ROW_EN[1] = 0x0
3894 13:29:54.081776 LP4Y_EN = 0x0
3895 13:29:54.081851 WORK_FSP = 0x0
3896 13:29:54.085370 WL = 0x2
3897 13:29:54.085446 RL = 0x2
3898 13:29:54.088455 BL = 0x2
3899 13:29:54.088530 RPST = 0x0
3900 13:29:54.091954 RD_PRE = 0x0
3901 13:29:54.092030 WR_PRE = 0x1
3902 13:29:54.095298 WR_PST = 0x0
3903 13:29:54.095396 DBI_WR = 0x0
3904 13:29:54.098264 DBI_RD = 0x0
3905 13:29:54.098339 OTF = 0x1
3906 13:29:54.101527 ===================================
3907 13:29:54.108103 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3908 13:29:54.111568 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3909 13:29:54.114714 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3910 13:29:54.118487 ===================================
3911 13:29:54.121433 LPDDR4 DRAM CONFIGURATION
3912 13:29:54.124572 ===================================
3913 13:29:54.128343 EX_ROW_EN[0] = 0x10
3914 13:29:54.128418 EX_ROW_EN[1] = 0x0
3915 13:29:54.131489 LP4Y_EN = 0x0
3916 13:29:54.131565 WORK_FSP = 0x0
3917 13:29:54.134578 WL = 0x2
3918 13:29:54.134653 RL = 0x2
3919 13:29:54.137713 BL = 0x2
3920 13:29:54.137788 RPST = 0x0
3921 13:29:54.141437 RD_PRE = 0x0
3922 13:29:54.141512 WR_PRE = 0x1
3923 13:29:54.144504 WR_PST = 0x0
3924 13:29:54.144579 DBI_WR = 0x0
3925 13:29:54.147759 DBI_RD = 0x0
3926 13:29:54.147834 OTF = 0x1
3927 13:29:54.151415 ===================================
3928 13:29:54.157868 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3929 13:29:54.162731 nWR fixed to 30
3930 13:29:54.165907 [ModeRegInit_LP4] CH0 RK0
3931 13:29:54.165982 [ModeRegInit_LP4] CH0 RK1
3932 13:29:54.169096 [ModeRegInit_LP4] CH1 RK0
3933 13:29:54.172637 [ModeRegInit_LP4] CH1 RK1
3934 13:29:54.172712 match AC timing 17
3935 13:29:54.179010 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3936 13:29:54.182556 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3937 13:29:54.185689 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3938 13:29:54.192210 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3939 13:29:54.195408 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3940 13:29:54.195483 ==
3941 13:29:54.198517 Dram Type= 6, Freq= 0, CH_0, rank 0
3942 13:29:54.201721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3943 13:29:54.205480 ==
3944 13:29:54.208529 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3945 13:29:54.215008 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3946 13:29:54.218339 [CA 0] Center 36 (6~67) winsize 62
3947 13:29:54.221592 [CA 1] Center 36 (6~67) winsize 62
3948 13:29:54.224901 [CA 2] Center 34 (4~65) winsize 62
3949 13:29:54.228299 [CA 3] Center 34 (4~65) winsize 62
3950 13:29:54.231505 [CA 4] Center 33 (3~64) winsize 62
3951 13:29:54.234488 [CA 5] Center 33 (3~64) winsize 62
3952 13:29:54.234564
3953 13:29:54.238245 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3954 13:29:54.238321
3955 13:29:54.241509 [CATrainingPosCal] consider 1 rank data
3956 13:29:54.244686 u2DelayCellTimex100 = 270/100 ps
3957 13:29:54.247878 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3958 13:29:54.251050 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3959 13:29:54.257765 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3960 13:29:54.261374 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3961 13:29:54.264611 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3962 13:29:54.267720 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3963 13:29:54.267795
3964 13:29:54.270969 CA PerBit enable=1, Macro0, CA PI delay=33
3965 13:29:54.271044
3966 13:29:54.274140 [CBTSetCACLKResult] CA Dly = 33
3967 13:29:54.274215 CS Dly: 6 (0~37)
3968 13:29:54.277760 ==
3969 13:29:54.280947 Dram Type= 6, Freq= 0, CH_0, rank 1
3970 13:29:54.284045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 13:29:54.284134 ==
3972 13:29:54.290825 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3973 13:29:54.293806 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3974 13:29:54.298165 [CA 0] Center 36 (6~67) winsize 62
3975 13:29:54.301069 [CA 1] Center 36 (6~67) winsize 62
3976 13:29:54.304704 [CA 2] Center 34 (4~65) winsize 62
3977 13:29:54.307840 [CA 3] Center 34 (4~65) winsize 62
3978 13:29:54.311038 [CA 4] Center 34 (3~65) winsize 63
3979 13:29:54.314150 [CA 5] Center 33 (3~64) winsize 62
3980 13:29:54.314225
3981 13:29:54.317402 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3982 13:29:54.317477
3983 13:29:54.324090 [CATrainingPosCal] consider 2 rank data
3984 13:29:54.324200 u2DelayCellTimex100 = 270/100 ps
3985 13:29:54.330448 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3986 13:29:54.333816 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3987 13:29:54.337203 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3988 13:29:54.340473 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3989 13:29:54.343754 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3990 13:29:54.347237 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3991 13:29:54.347345
3992 13:29:54.350294 CA PerBit enable=1, Macro0, CA PI delay=33
3993 13:29:54.350386
3994 13:29:54.353451 [CBTSetCACLKResult] CA Dly = 33
3995 13:29:54.357127 CS Dly: 6 (0~37)
3996 13:29:54.357210
3997 13:29:54.360222 ----->DramcWriteLeveling(PI) begin...
3998 13:29:54.360338 ==
3999 13:29:54.363744 Dram Type= 6, Freq= 0, CH_0, rank 0
4000 13:29:54.366901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4001 13:29:54.366993 ==
4002 13:29:54.370039 Write leveling (Byte 0): 32 => 32
4003 13:29:54.373364 Write leveling (Byte 1): 27 => 27
4004 13:29:54.376511 DramcWriteLeveling(PI) end<-----
4005 13:29:54.376601
4006 13:29:54.376688 ==
4007 13:29:54.380223 Dram Type= 6, Freq= 0, CH_0, rank 0
4008 13:29:54.383436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4009 13:29:54.383526 ==
4010 13:29:54.386582 [Gating] SW mode calibration
4011 13:29:54.393342 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4012 13:29:54.399698 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4013 13:29:54.402890 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4014 13:29:54.409708 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4015 13:29:54.413218 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4016 13:29:54.416132 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4017 13:29:54.423161 0 9 16 | B1->B0 | 2c2c 2a2a | 1 1 | (1 0) (0 0)
4018 13:29:54.426375 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 13:29:54.429550 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 13:29:54.435888 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 13:29:54.439081 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 13:29:54.442690 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 13:29:54.448978 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 13:29:54.452509 0 10 12 | B1->B0 | 2c2c 2f2f | 0 1 | (0 0) (0 0)
4025 13:29:54.455451 0 10 16 | B1->B0 | 3939 4242 | 0 0 | (0 0) (0 0)
4026 13:29:54.462321 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 13:29:54.465417 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 13:29:54.469006 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 13:29:54.475185 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 13:29:54.478927 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 13:29:54.482073 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 13:29:54.488797 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4033 13:29:54.492038 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 13:29:54.495069 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 13:29:54.501410 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 13:29:54.505119 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 13:29:54.508316 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 13:29:54.515127 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 13:29:54.518226 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 13:29:54.521414 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 13:29:54.527720 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 13:29:54.531541 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 13:29:54.534653 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 13:29:54.541133 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 13:29:54.544164 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 13:29:54.547932 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 13:29:54.554628 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 13:29:54.557484 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 13:29:54.560671 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 13:29:54.564429 Total UI for P1: 0, mck2ui 16
4051 13:29:54.567321 best dqsien dly found for B0: ( 0, 13, 14)
4052 13:29:54.570670 Total UI for P1: 0, mck2ui 16
4053 13:29:54.574087 best dqsien dly found for B1: ( 0, 13, 14)
4054 13:29:54.577399 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4055 13:29:54.580761 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4056 13:29:54.583860
4057 13:29:54.587093 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4058 13:29:54.590808 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4059 13:29:54.593933 [Gating] SW calibration Done
4060 13:29:54.594026 ==
4061 13:29:54.597017 Dram Type= 6, Freq= 0, CH_0, rank 0
4062 13:29:54.600091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4063 13:29:54.600167 ==
4064 13:29:54.603747 RX Vref Scan: 0
4065 13:29:54.603845
4066 13:29:54.603930 RX Vref 0 -> 0, step: 1
4067 13:29:54.604012
4068 13:29:54.607002 RX Delay -230 -> 252, step: 16
4069 13:29:54.610328 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4070 13:29:54.616520 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4071 13:29:54.620362 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4072 13:29:54.623594 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4073 13:29:54.626683 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4074 13:29:54.633260 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4075 13:29:54.636636 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4076 13:29:54.639830 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4077 13:29:54.642930 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4078 13:29:54.646443 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4079 13:29:54.653166 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4080 13:29:54.656283 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4081 13:29:54.659277 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4082 13:29:54.662635 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4083 13:29:54.669333 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4084 13:29:54.672588 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4085 13:29:54.672663 ==
4086 13:29:54.676390 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 13:29:54.679562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 13:29:54.679639 ==
4089 13:29:54.682585 DQS Delay:
4090 13:29:54.682660 DQS0 = 0, DQS1 = 0
4091 13:29:54.686234 DQM Delay:
4092 13:29:54.686311 DQM0 = 50, DQM1 = 39
4093 13:29:54.686371 DQ Delay:
4094 13:29:54.689159 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4095 13:29:54.692313 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4096 13:29:54.696041 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4097 13:29:54.699053 DQ12 =49, DQ13 =41, DQ14 =49, DQ15 =49
4098 13:29:54.699128
4099 13:29:54.699187
4100 13:29:54.702625 ==
4101 13:29:54.705746 Dram Type= 6, Freq= 0, CH_0, rank 0
4102 13:29:54.708905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4103 13:29:54.708980 ==
4104 13:29:54.709039
4105 13:29:54.709093
4106 13:29:54.712054 TX Vref Scan disable
4107 13:29:54.712130 == TX Byte 0 ==
4108 13:29:54.718891 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4109 13:29:54.722049 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4110 13:29:54.722125 == TX Byte 1 ==
4111 13:29:54.729084 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4112 13:29:54.732326 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4113 13:29:54.732400 ==
4114 13:29:54.735431 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 13:29:54.739077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 13:29:54.739153 ==
4117 13:29:54.739211
4118 13:29:54.739266
4119 13:29:54.742095 TX Vref Scan disable
4120 13:29:54.745387 == TX Byte 0 ==
4121 13:29:54.748946 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4122 13:29:54.751946 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4123 13:29:54.755066 == TX Byte 1 ==
4124 13:29:54.758824 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4125 13:29:54.762126 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4126 13:29:54.765368
4127 13:29:54.765443 [DATLAT]
4128 13:29:54.765501 Freq=600, CH0 RK0
4129 13:29:54.765556
4130 13:29:54.768203 DATLAT Default: 0x9
4131 13:29:54.768278 0, 0xFFFF, sum = 0
4132 13:29:54.771624 1, 0xFFFF, sum = 0
4133 13:29:54.771701 2, 0xFFFF, sum = 0
4134 13:29:54.775198 3, 0xFFFF, sum = 0
4135 13:29:54.778418 4, 0xFFFF, sum = 0
4136 13:29:54.778494 5, 0xFFFF, sum = 0
4137 13:29:54.781543 6, 0xFFFF, sum = 0
4138 13:29:54.781620 7, 0xFFFF, sum = 0
4139 13:29:54.784789 8, 0x0, sum = 1
4140 13:29:54.784866 9, 0x0, sum = 2
4141 13:29:54.784926 10, 0x0, sum = 3
4142 13:29:54.787884 11, 0x0, sum = 4
4143 13:29:54.787961 best_step = 9
4144 13:29:54.788020
4145 13:29:54.788105 ==
4146 13:29:54.791724 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 13:29:54.798118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 13:29:54.798194 ==
4149 13:29:54.798253 RX Vref Scan: 1
4150 13:29:54.798307
4151 13:29:54.801172 RX Vref 0 -> 0, step: 1
4152 13:29:54.801261
4153 13:29:54.804824 RX Delay -179 -> 252, step: 8
4154 13:29:54.804899
4155 13:29:54.807708 Set Vref, RX VrefLevel [Byte0]: 56
4156 13:29:54.811127 [Byte1]: 49
4157 13:29:54.811201
4158 13:29:54.814634 Final RX Vref Byte 0 = 56 to rank0
4159 13:29:54.817816 Final RX Vref Byte 1 = 49 to rank0
4160 13:29:54.820805 Final RX Vref Byte 0 = 56 to rank1
4161 13:29:54.824263 Final RX Vref Byte 1 = 49 to rank1==
4162 13:29:54.827758 Dram Type= 6, Freq= 0, CH_0, rank 0
4163 13:29:54.831029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 13:29:54.834149 ==
4165 13:29:54.834224 DQS Delay:
4166 13:29:54.834283 DQS0 = 0, DQS1 = 0
4167 13:29:54.837399 DQM Delay:
4168 13:29:54.837474 DQM0 = 45, DQM1 = 37
4169 13:29:54.840512 DQ Delay:
4170 13:29:54.840587 DQ0 =48, DQ1 =44, DQ2 =40, DQ3 =40
4171 13:29:54.844448 DQ4 =48, DQ5 =36, DQ6 =56, DQ7 =48
4172 13:29:54.847575 DQ8 =28, DQ9 =28, DQ10 =36, DQ11 =32
4173 13:29:54.850509 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4174 13:29:54.854050
4175 13:29:54.854148
4176 13:29:54.860290 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f46, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
4177 13:29:54.863625 CH0 RK0: MR19=808, MR18=4F46
4178 13:29:54.870352 CH0_RK0: MR19=0x808, MR18=0x4F46, DQSOSC=394, MR23=63, INC=168, DEC=112
4179 13:29:54.870428
4180 13:29:54.873446 ----->DramcWriteLeveling(PI) begin...
4181 13:29:54.873523 ==
4182 13:29:54.876999 Dram Type= 6, Freq= 0, CH_0, rank 1
4183 13:29:54.879859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4184 13:29:54.879957 ==
4185 13:29:54.883160 Write leveling (Byte 0): 31 => 31
4186 13:29:54.886446 Write leveling (Byte 1): 30 => 30
4187 13:29:54.890321 DramcWriteLeveling(PI) end<-----
4188 13:29:54.890396
4189 13:29:54.890454 ==
4190 13:29:54.893461 Dram Type= 6, Freq= 0, CH_0, rank 1
4191 13:29:54.896601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 13:29:54.899798 ==
4193 13:29:54.899873 [Gating] SW mode calibration
4194 13:29:54.909394 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4195 13:29:54.913099 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4196 13:29:54.916405 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4197 13:29:54.922734 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4198 13:29:54.925922 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4199 13:29:54.929574 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
4200 13:29:54.936035 0 9 16 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
4201 13:29:54.939394 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 13:29:54.942607 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 13:29:54.949104 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 13:29:54.952548 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 13:29:54.955620 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 13:29:54.962317 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 13:29:54.965278 0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
4208 13:29:54.968630 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4209 13:29:54.975398 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 13:29:54.978480 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 13:29:54.982102 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 13:29:54.988717 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 13:29:54.992125 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 13:29:54.995246 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 13:29:55.001622 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4216 13:29:55.004769 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 13:29:55.008528 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 13:29:55.014883 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 13:29:55.018053 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 13:29:55.021710 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 13:29:55.027906 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 13:29:55.031112 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 13:29:55.034360 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 13:29:55.041347 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 13:29:55.044529 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 13:29:55.047667 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 13:29:55.054061 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 13:29:55.057477 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 13:29:55.060470 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 13:29:55.067374 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 13:29:55.070750 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4232 13:29:55.077373 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 13:29:55.077449 Total UI for P1: 0, mck2ui 16
4234 13:29:55.080211 best dqsien dly found for B0: ( 0, 13, 12)
4235 13:29:55.083725 Total UI for P1: 0, mck2ui 16
4236 13:29:55.086755 best dqsien dly found for B1: ( 0, 13, 12)
4237 13:29:55.093483 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4238 13:29:55.096857 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4239 13:29:55.096949
4240 13:29:55.100272 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4241 13:29:55.103342 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4242 13:29:55.106583 [Gating] SW calibration Done
4243 13:29:55.106675 ==
4244 13:29:55.109798 Dram Type= 6, Freq= 0, CH_0, rank 1
4245 13:29:55.113395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4246 13:29:55.113483 ==
4247 13:29:55.116562 RX Vref Scan: 0
4248 13:29:55.116654
4249 13:29:55.116744 RX Vref 0 -> 0, step: 1
4250 13:29:55.116826
4251 13:29:55.119737 RX Delay -230 -> 252, step: 16
4252 13:29:55.126056 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4253 13:29:55.129729 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4254 13:29:55.132839 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4255 13:29:55.136599 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4256 13:29:55.139864 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4257 13:29:55.146150 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4258 13:29:55.149362 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4259 13:29:55.153194 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4260 13:29:55.156285 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4261 13:29:55.163148 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4262 13:29:55.166130 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4263 13:29:55.169100 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4264 13:29:55.172694 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4265 13:29:55.179023 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4266 13:29:55.182483 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4267 13:29:55.186132 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4268 13:29:55.186207 ==
4269 13:29:55.189169 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 13:29:55.192099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 13:29:55.195734 ==
4272 13:29:55.195808 DQS Delay:
4273 13:29:55.195869 DQS0 = 0, DQS1 = 0
4274 13:29:55.198623 DQM Delay:
4275 13:29:55.198710 DQM0 = 44, DQM1 = 36
4276 13:29:55.202103 DQ Delay:
4277 13:29:55.205121 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4278 13:29:55.208875 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =49
4279 13:29:55.209011 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4280 13:29:55.215224 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4281 13:29:55.215325
4282 13:29:55.215410
4283 13:29:55.215490 ==
4284 13:29:55.218950 Dram Type= 6, Freq= 0, CH_0, rank 1
4285 13:29:55.222063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4286 13:29:55.222131 ==
4287 13:29:55.222187
4288 13:29:55.222264
4289 13:29:55.225152 TX Vref Scan disable
4290 13:29:55.225277 == TX Byte 0 ==
4291 13:29:55.231520 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4292 13:29:55.234760 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4293 13:29:55.238412 == TX Byte 1 ==
4294 13:29:55.241504 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4295 13:29:55.244682 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4296 13:29:55.244772 ==
4297 13:29:55.248414 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 13:29:55.251563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 13:29:55.254781 ==
4300 13:29:55.254872
4301 13:29:55.254954
4302 13:29:55.255037 TX Vref Scan disable
4303 13:29:55.258534 == TX Byte 0 ==
4304 13:29:55.261646 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4305 13:29:55.268354 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4306 13:29:55.268449 == TX Byte 1 ==
4307 13:29:55.271435 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4308 13:29:55.278557 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4309 13:29:55.278652
4310 13:29:55.278742 [DATLAT]
4311 13:29:55.278824 Freq=600, CH0 RK1
4312 13:29:55.278907
4313 13:29:55.281698 DATLAT Default: 0x9
4314 13:29:55.284822 0, 0xFFFF, sum = 0
4315 13:29:55.284897 1, 0xFFFF, sum = 0
4316 13:29:55.287866 2, 0xFFFF, sum = 0
4317 13:29:55.287941 3, 0xFFFF, sum = 0
4318 13:29:55.291421 4, 0xFFFF, sum = 0
4319 13:29:55.291496 5, 0xFFFF, sum = 0
4320 13:29:55.294839 6, 0xFFFF, sum = 0
4321 13:29:55.294948 7, 0xFFFF, sum = 0
4322 13:29:55.298103 8, 0x0, sum = 1
4323 13:29:55.298229 9, 0x0, sum = 2
4324 13:29:55.301102 10, 0x0, sum = 3
4325 13:29:55.301208 11, 0x0, sum = 4
4326 13:29:55.301270 best_step = 9
4327 13:29:55.301326
4328 13:29:55.304370 ==
4329 13:29:55.308157 Dram Type= 6, Freq= 0, CH_0, rank 1
4330 13:29:55.311459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 13:29:55.311553 ==
4332 13:29:55.311636 RX Vref Scan: 0
4333 13:29:55.311716
4334 13:29:55.314387 RX Vref 0 -> 0, step: 1
4335 13:29:55.314451
4336 13:29:55.317829 RX Delay -179 -> 252, step: 8
4337 13:29:55.324508 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4338 13:29:55.327350 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4339 13:29:55.331204 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4340 13:29:55.334478 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4341 13:29:55.337531 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4342 13:29:55.343806 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4343 13:29:55.347655 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4344 13:29:55.350852 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4345 13:29:55.354056 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4346 13:29:55.360376 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4347 13:29:55.363469 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4348 13:29:55.367463 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4349 13:29:55.370333 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4350 13:29:55.377108 iDelay=205, Bit 13, Center 40 (-107 ~ 188) 296
4351 13:29:55.380191 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4352 13:29:55.383838 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4353 13:29:55.383930 ==
4354 13:29:55.386980 Dram Type= 6, Freq= 0, CH_0, rank 1
4355 13:29:55.390300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4356 13:29:55.390393 ==
4357 13:29:55.393453 DQS Delay:
4358 13:29:55.393526 DQS0 = 0, DQS1 = 0
4359 13:29:55.396595 DQM Delay:
4360 13:29:55.396686 DQM0 = 43, DQM1 = 36
4361 13:29:55.400300 DQ Delay:
4362 13:29:55.400370 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4363 13:29:55.403362 DQ4 =48, DQ5 =32, DQ6 =56, DQ7 =48
4364 13:29:55.406355 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =32
4365 13:29:55.409708 DQ12 =36, DQ13 =40, DQ14 =48, DQ15 =44
4366 13:29:55.413794
4367 13:29:55.413863
4368 13:29:55.419575 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d39, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
4369 13:29:55.423168 CH0 RK1: MR19=808, MR18=3D39
4370 13:29:55.430025 CH0_RK1: MR19=0x808, MR18=0x3D39, DQSOSC=398, MR23=63, INC=165, DEC=110
4371 13:29:55.433002 [RxdqsGatingPostProcess] freq 600
4372 13:29:55.436379 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4373 13:29:55.439538 Pre-setting of DQS Precalculation
4374 13:29:55.446171 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4375 13:29:55.446247 ==
4376 13:29:55.449663 Dram Type= 6, Freq= 0, CH_1, rank 0
4377 13:29:55.452824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 13:29:55.452916 ==
4379 13:29:55.459152 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4380 13:29:55.462374 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4381 13:29:55.467302 [CA 0] Center 36 (6~66) winsize 61
4382 13:29:55.470440 [CA 1] Center 35 (5~66) winsize 62
4383 13:29:55.473573 [CA 2] Center 35 (5~65) winsize 61
4384 13:29:55.477416 [CA 3] Center 34 (4~65) winsize 62
4385 13:29:55.480486 [CA 4] Center 34 (4~65) winsize 62
4386 13:29:55.483569 [CA 5] Center 34 (3~65) winsize 63
4387 13:29:55.483667
4388 13:29:55.487115 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4389 13:29:55.487206
4390 13:29:55.490108 [CATrainingPosCal] consider 1 rank data
4391 13:29:55.493462 u2DelayCellTimex100 = 270/100 ps
4392 13:29:55.497127 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4393 13:29:55.503529 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4394 13:29:55.506717 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4395 13:29:55.509887 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4396 13:29:55.513669 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4397 13:29:55.516700 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4398 13:29:55.516801
4399 13:29:55.519723 CA PerBit enable=1, Macro0, CA PI delay=34
4400 13:29:55.519816
4401 13:29:55.523384 [CBTSetCACLKResult] CA Dly = 34
4402 13:29:55.526337 CS Dly: 4 (0~35)
4403 13:29:55.526408 ==
4404 13:29:55.529855 Dram Type= 6, Freq= 0, CH_1, rank 1
4405 13:29:55.533053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 13:29:55.533190 ==
4407 13:29:55.539625 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4408 13:29:55.542955 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4409 13:29:55.546823 [CA 0] Center 36 (6~66) winsize 61
4410 13:29:55.550101 [CA 1] Center 36 (6~66) winsize 61
4411 13:29:55.553494 [CA 2] Center 35 (5~65) winsize 61
4412 13:29:55.557152 [CA 3] Center 34 (4~64) winsize 61
4413 13:29:55.560275 [CA 4] Center 34 (4~64) winsize 61
4414 13:29:55.563945 [CA 5] Center 34 (4~64) winsize 61
4415 13:29:55.564039
4416 13:29:55.567114 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4417 13:29:55.567212
4418 13:29:55.570305 [CATrainingPosCal] consider 2 rank data
4419 13:29:55.573456 u2DelayCellTimex100 = 270/100 ps
4420 13:29:55.577037 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4421 13:29:55.583313 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4422 13:29:55.586397 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4423 13:29:55.589967 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
4424 13:29:55.593010 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4425 13:29:55.596567 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4426 13:29:55.596662
4427 13:29:55.599762 CA PerBit enable=1, Macro0, CA PI delay=34
4428 13:29:55.599858
4429 13:29:55.602878 [CBTSetCACLKResult] CA Dly = 34
4430 13:29:55.606546 CS Dly: 4 (0~36)
4431 13:29:55.606636
4432 13:29:55.609668 ----->DramcWriteLeveling(PI) begin...
4433 13:29:55.609762 ==
4434 13:29:55.612729 Dram Type= 6, Freq= 0, CH_1, rank 0
4435 13:29:55.616080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4436 13:29:55.616175 ==
4437 13:29:55.619127 Write leveling (Byte 0): 28 => 28
4438 13:29:55.622913 Write leveling (Byte 1): 27 => 27
4439 13:29:55.626025 DramcWriteLeveling(PI) end<-----
4440 13:29:55.626103
4441 13:29:55.626166 ==
4442 13:29:55.629699 Dram Type= 6, Freq= 0, CH_1, rank 0
4443 13:29:55.632915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 13:29:55.633010 ==
4445 13:29:55.636053 [Gating] SW mode calibration
4446 13:29:55.642188 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4447 13:29:55.649629 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4448 13:29:55.652241 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4449 13:29:55.655980 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4450 13:29:55.662002 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4451 13:29:55.665832 0 9 12 | B1->B0 | 3030 2e2e | 0 0 | (0 0) (0 0)
4452 13:29:55.668862 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 13:29:55.675754 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 13:29:55.678790 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 13:29:55.682068 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 13:29:55.688907 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 13:29:55.691979 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 13:29:55.698551 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4459 13:29:55.701996 0 10 12 | B1->B0 | 3030 3a3a | 0 1 | (0 0) (0 0)
4460 13:29:55.705010 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 13:29:55.711350 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 13:29:55.715095 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 13:29:55.718323 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 13:29:55.725403 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 13:29:55.728838 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 13:29:55.731912 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4467 13:29:55.738830 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 13:29:55.741834 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 13:29:55.745032 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 13:29:55.748594 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 13:29:55.754898 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 13:29:55.757998 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 13:29:55.764615 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 13:29:55.767721 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 13:29:55.771510 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 13:29:55.774611 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 13:29:55.781427 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 13:29:55.784268 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 13:29:55.790840 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 13:29:55.794375 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 13:29:55.797895 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 13:29:55.804038 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 13:29:55.807718 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4484 13:29:55.810538 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 13:29:55.814240 Total UI for P1: 0, mck2ui 16
4486 13:29:55.817465 best dqsien dly found for B0: ( 0, 13, 12)
4487 13:29:55.820623 Total UI for P1: 0, mck2ui 16
4488 13:29:55.823689 best dqsien dly found for B1: ( 0, 13, 12)
4489 13:29:55.827858 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4490 13:29:55.831111 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4491 13:29:55.831740
4492 13:29:55.837269 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4493 13:29:55.840713 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4494 13:29:55.841219 [Gating] SW calibration Done
4495 13:29:55.843607 ==
4496 13:29:55.846854 Dram Type= 6, Freq= 0, CH_1, rank 0
4497 13:29:55.850845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4498 13:29:55.851323 ==
4499 13:29:55.851719 RX Vref Scan: 0
4500 13:29:55.852088
4501 13:29:55.853601 RX Vref 0 -> 0, step: 1
4502 13:29:55.853993
4503 13:29:55.856859 RX Delay -230 -> 252, step: 16
4504 13:29:55.859967 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4505 13:29:55.864021 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4506 13:29:55.870099 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4507 13:29:55.873349 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4508 13:29:55.876646 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4509 13:29:55.880161 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4510 13:29:55.886349 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4511 13:29:55.890044 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4512 13:29:55.893196 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4513 13:29:55.896319 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4514 13:29:55.903043 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4515 13:29:55.906456 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4516 13:29:55.909328 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4517 13:29:55.912980 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4518 13:29:55.919330 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4519 13:29:55.922829 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4520 13:29:55.923211 ==
4521 13:29:55.926125 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 13:29:55.929114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 13:29:55.929603 ==
4524 13:29:55.932143 DQS Delay:
4525 13:29:55.932478 DQS0 = 0, DQS1 = 0
4526 13:29:55.932800 DQM Delay:
4527 13:29:55.935878 DQM0 = 45, DQM1 = 39
4528 13:29:55.936202 DQ Delay:
4529 13:29:55.939030 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4530 13:29:55.942126 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4531 13:29:55.946246 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4532 13:29:55.948755 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4533 13:29:55.949133
4534 13:29:55.949481
4535 13:29:55.949754 ==
4536 13:29:55.951972 Dram Type= 6, Freq= 0, CH_1, rank 0
4537 13:29:55.958717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4538 13:29:55.959102 ==
4539 13:29:55.959445
4540 13:29:55.959755
4541 13:29:55.961896 TX Vref Scan disable
4542 13:29:55.962290 == TX Byte 0 ==
4543 13:29:55.965225 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4544 13:29:55.971987 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4545 13:29:55.972371 == TX Byte 1 ==
4546 13:29:55.978648 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4547 13:29:55.981849 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4548 13:29:55.982251 ==
4549 13:29:55.984974 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 13:29:55.988105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 13:29:55.988489 ==
4552 13:29:55.988787
4553 13:29:55.989066
4554 13:29:55.992128 TX Vref Scan disable
4555 13:29:55.994839 == TX Byte 0 ==
4556 13:29:55.998065 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4557 13:29:56.001200 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4558 13:29:56.004980 == TX Byte 1 ==
4559 13:29:56.007733 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4560 13:29:56.011626 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4561 13:29:56.012025
4562 13:29:56.014699 [DATLAT]
4563 13:29:56.015094 Freq=600, CH1 RK0
4564 13:29:56.015493
4565 13:29:56.017680 DATLAT Default: 0x9
4566 13:29:56.018081 0, 0xFFFF, sum = 0
4567 13:29:56.021282 1, 0xFFFF, sum = 0
4568 13:29:56.021689 2, 0xFFFF, sum = 0
4569 13:29:56.024360 3, 0xFFFF, sum = 0
4570 13:29:56.024767 4, 0xFFFF, sum = 0
4571 13:29:56.028086 5, 0xFFFF, sum = 0
4572 13:29:56.030912 6, 0xFFFF, sum = 0
4573 13:29:56.031316 7, 0xFFFF, sum = 0
4574 13:29:56.031716 8, 0x0, sum = 1
4575 13:29:56.034255 9, 0x0, sum = 2
4576 13:29:56.034659 10, 0x0, sum = 3
4577 13:29:56.037485 11, 0x0, sum = 4
4578 13:29:56.037890 best_step = 9
4579 13:29:56.038284
4580 13:29:56.038656 ==
4581 13:29:56.040601 Dram Type= 6, Freq= 0, CH_1, rank 0
4582 13:29:56.047449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 13:29:56.047975 ==
4584 13:29:56.048412 RX Vref Scan: 1
4585 13:29:56.048826
4586 13:29:56.050703 RX Vref 0 -> 0, step: 1
4587 13:29:56.051162
4588 13:29:56.053815 RX Delay -179 -> 252, step: 8
4589 13:29:56.054335
4590 13:29:56.057198 Set Vref, RX VrefLevel [Byte0]: 52
4591 13:29:56.060553 [Byte1]: 51
4592 13:29:56.060939
4593 13:29:56.064359 Final RX Vref Byte 0 = 52 to rank0
4594 13:29:56.067673 Final RX Vref Byte 1 = 51 to rank0
4595 13:29:56.071099 Final RX Vref Byte 0 = 52 to rank1
4596 13:29:56.074003 Final RX Vref Byte 1 = 51 to rank1==
4597 13:29:56.077549 Dram Type= 6, Freq= 0, CH_1, rank 0
4598 13:29:56.080214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 13:29:56.080605 ==
4600 13:29:56.083998 DQS Delay:
4601 13:29:56.084391 DQS0 = 0, DQS1 = 0
4602 13:29:56.087170 DQM Delay:
4603 13:29:56.087700 DQM0 = 40, DQM1 = 33
4604 13:29:56.088029 DQ Delay:
4605 13:29:56.090072 DQ0 =48, DQ1 =36, DQ2 =28, DQ3 =40
4606 13:29:56.093934 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =32
4607 13:29:56.097228 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4608 13:29:56.100909 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4609 13:29:56.101463
4610 13:29:56.101777
4611 13:29:56.110278 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d46, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4612 13:29:56.113658 CH1 RK0: MR19=808, MR18=2D46
4613 13:29:56.119771 CH1_RK0: MR19=0x808, MR18=0x2D46, DQSOSC=396, MR23=63, INC=167, DEC=111
4614 13:29:56.120281
4615 13:29:56.123281 ----->DramcWriteLeveling(PI) begin...
4616 13:29:56.123817 ==
4617 13:29:56.126401 Dram Type= 6, Freq= 0, CH_1, rank 1
4618 13:29:56.129690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4619 13:29:56.130082 ==
4620 13:29:56.133465 Write leveling (Byte 0): 30 => 30
4621 13:29:56.136509 Write leveling (Byte 1): 30 => 30
4622 13:29:56.139568 DramcWriteLeveling(PI) end<-----
4623 13:29:56.139986
4624 13:29:56.140290 ==
4625 13:29:56.142809 Dram Type= 6, Freq= 0, CH_1, rank 1
4626 13:29:56.146498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 13:29:56.146887 ==
4628 13:29:56.149396 [Gating] SW mode calibration
4629 13:29:56.156311 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4630 13:29:56.162720 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4631 13:29:56.166074 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4632 13:29:56.172567 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4633 13:29:56.175759 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4634 13:29:56.179445 0 9 12 | B1->B0 | 3030 2e2e | 0 0 | (0 0) (0 0)
4635 13:29:56.185693 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4636 13:29:56.189537 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4637 13:29:56.192434 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4638 13:29:56.198929 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4639 13:29:56.202046 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 13:29:56.205827 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 13:29:56.212019 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4642 13:29:56.215225 0 10 12 | B1->B0 | 2f2f 3838 | 0 0 | (1 1) (0 0)
4643 13:29:56.218963 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 13:29:56.225246 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 13:29:56.228901 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 13:29:56.231840 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 13:29:56.238771 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 13:29:56.241752 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 13:29:56.244890 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4650 13:29:56.251440 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4651 13:29:56.255033 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 13:29:56.258119 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 13:29:56.264518 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 13:29:56.267983 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 13:29:56.270975 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 13:29:56.277340 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 13:29:56.280772 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 13:29:56.284281 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 13:29:56.290851 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 13:29:56.294076 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 13:29:56.297544 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 13:29:56.303761 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 13:29:56.307553 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 13:29:56.310686 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 13:29:56.317022 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 13:29:56.320607 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4667 13:29:56.323828 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 13:29:56.326755 Total UI for P1: 0, mck2ui 16
4669 13:29:56.330284 best dqsien dly found for B0: ( 0, 13, 12)
4670 13:29:56.333259 Total UI for P1: 0, mck2ui 16
4671 13:29:56.336998 best dqsien dly found for B1: ( 0, 13, 14)
4672 13:29:56.339931 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4673 13:29:56.343781 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4674 13:29:56.346881
4675 13:29:56.350096 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4676 13:29:56.353262 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4677 13:29:56.356264 [Gating] SW calibration Done
4678 13:29:56.356865 ==
4679 13:29:56.359549 Dram Type= 6, Freq= 0, CH_1, rank 1
4680 13:29:56.363350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4681 13:29:56.363731 ==
4682 13:29:56.364025 RX Vref Scan: 0
4683 13:29:56.366539
4684 13:29:56.366898 RX Vref 0 -> 0, step: 1
4685 13:29:56.367279
4686 13:29:56.369724 RX Delay -230 -> 252, step: 16
4687 13:29:56.373236 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4688 13:29:56.379766 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4689 13:29:56.382766 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4690 13:29:56.386406 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4691 13:29:56.389616 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4692 13:29:56.396273 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4693 13:29:56.399225 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4694 13:29:56.402609 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4695 13:29:56.405932 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4696 13:29:56.409129 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4697 13:29:56.415512 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4698 13:29:56.418970 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4699 13:29:56.422651 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4700 13:29:56.425825 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4701 13:29:56.432176 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4702 13:29:56.435145 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4703 13:29:56.435651 ==
4704 13:29:56.438640 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 13:29:56.442099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 13:29:56.442490 ==
4707 13:29:56.445227 DQS Delay:
4708 13:29:56.445612 DQS0 = 0, DQS1 = 0
4709 13:29:56.448849 DQM Delay:
4710 13:29:56.449462 DQM0 = 44, DQM1 = 39
4711 13:29:56.449784 DQ Delay:
4712 13:29:56.451921 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4713 13:29:56.455157 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4714 13:29:56.458327 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4715 13:29:56.462083 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4716 13:29:56.462469
4717 13:29:56.462766
4718 13:29:56.465185 ==
4719 13:29:56.468343 Dram Type= 6, Freq= 0, CH_1, rank 1
4720 13:29:56.471483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4721 13:29:56.472003 ==
4722 13:29:56.472442
4723 13:29:56.472854
4724 13:29:56.475183 TX Vref Scan disable
4725 13:29:56.475569 == TX Byte 0 ==
4726 13:29:56.481686 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4727 13:29:56.484849 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4728 13:29:56.485297 == TX Byte 1 ==
4729 13:29:56.491396 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4730 13:29:56.494392 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4731 13:29:56.494859 ==
4732 13:29:56.497640 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 13:29:56.501489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 13:29:56.501949 ==
4735 13:29:56.502257
4736 13:29:56.502531
4737 13:29:56.504674 TX Vref Scan disable
4738 13:29:56.507797 == TX Byte 0 ==
4739 13:29:56.510785 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4740 13:29:56.517337 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4741 13:29:56.517724 == TX Byte 1 ==
4742 13:29:56.520886 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4743 13:29:56.527558 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4744 13:29:56.527957
4745 13:29:56.528255 [DATLAT]
4746 13:29:56.528533 Freq=600, CH1 RK1
4747 13:29:56.528806
4748 13:29:56.530442 DATLAT Default: 0x9
4749 13:29:56.534036 0, 0xFFFF, sum = 0
4750 13:29:56.534427 1, 0xFFFF, sum = 0
4751 13:29:56.537132 2, 0xFFFF, sum = 0
4752 13:29:56.537567 3, 0xFFFF, sum = 0
4753 13:29:56.540939 4, 0xFFFF, sum = 0
4754 13:29:56.541789 5, 0xFFFF, sum = 0
4755 13:29:56.543754 6, 0xFFFF, sum = 0
4756 13:29:56.544263 7, 0xFFFF, sum = 0
4757 13:29:56.546969 8, 0x0, sum = 1
4758 13:29:56.547610 9, 0x0, sum = 2
4759 13:29:56.550182 10, 0x0, sum = 3
4760 13:29:56.550491 11, 0x0, sum = 4
4761 13:29:56.550712 best_step = 9
4762 13:29:56.550917
4763 13:29:56.553772 ==
4764 13:29:56.556564 Dram Type= 6, Freq= 0, CH_1, rank 1
4765 13:29:56.559735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4766 13:29:56.559936 ==
4767 13:29:56.560075 RX Vref Scan: 0
4768 13:29:56.560214
4769 13:29:56.563505 RX Vref 0 -> 0, step: 1
4770 13:29:56.563709
4771 13:29:56.566737 RX Delay -179 -> 252, step: 8
4772 13:29:56.573036 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4773 13:29:56.576200 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4774 13:29:56.579936 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4775 13:29:56.583212 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4776 13:29:56.589741 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4777 13:29:56.592581 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4778 13:29:56.596021 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4779 13:29:56.599121 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4780 13:29:56.602822 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4781 13:29:56.609109 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4782 13:29:56.612232 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4783 13:29:56.616023 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4784 13:29:56.619113 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4785 13:29:56.625985 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4786 13:29:56.628949 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4787 13:29:56.632120 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4788 13:29:56.632196 ==
4789 13:29:56.635327 Dram Type= 6, Freq= 0, CH_1, rank 1
4790 13:29:56.642335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4791 13:29:56.642413 ==
4792 13:29:56.642472 DQS Delay:
4793 13:29:56.642527 DQS0 = 0, DQS1 = 0
4794 13:29:56.645746 DQM Delay:
4795 13:29:56.645822 DQM0 = 37, DQM1 = 32
4796 13:29:56.649175 DQ Delay:
4797 13:29:56.651904 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4798 13:29:56.655108 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =32
4799 13:29:56.658441 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4800 13:29:56.661892 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4801 13:29:56.661970
4802 13:29:56.662030
4803 13:29:56.668602 [DQSOSCAuto] RK1, (LSB)MR18= 0x365b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4804 13:29:56.671489 CH1 RK1: MR19=808, MR18=365B
4805 13:29:56.678427 CH1_RK1: MR19=0x808, MR18=0x365B, DQSOSC=392, MR23=63, INC=170, DEC=113
4806 13:29:56.681590 [RxdqsGatingPostProcess] freq 600
4807 13:29:56.684779 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4808 13:29:56.687960 Pre-setting of DQS Precalculation
4809 13:29:56.694947 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4810 13:29:56.701027 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4811 13:29:56.707969 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4812 13:29:56.708045
4813 13:29:56.708102
4814 13:29:56.711127 [Calibration Summary] 1200 Mbps
4815 13:29:56.714290 CH 0, Rank 0
4816 13:29:56.714365 SW Impedance : PASS
4817 13:29:56.718034 DUTY Scan : NO K
4818 13:29:56.721109 ZQ Calibration : PASS
4819 13:29:56.721222 Jitter Meter : NO K
4820 13:29:56.724368 CBT Training : PASS
4821 13:29:56.724444 Write leveling : PASS
4822 13:29:56.727592 RX DQS gating : PASS
4823 13:29:56.730796 RX DQ/DQS(RDDQC) : PASS
4824 13:29:56.730871 TX DQ/DQS : PASS
4825 13:29:56.733782 RX DATLAT : PASS
4826 13:29:56.737716 RX DQ/DQS(Engine): PASS
4827 13:29:56.737815 TX OE : NO K
4828 13:29:56.740755 All Pass.
4829 13:29:56.740830
4830 13:29:56.740888 CH 0, Rank 1
4831 13:29:56.743806 SW Impedance : PASS
4832 13:29:56.743895 DUTY Scan : NO K
4833 13:29:56.747040 ZQ Calibration : PASS
4834 13:29:56.750662 Jitter Meter : NO K
4835 13:29:56.750739 CBT Training : PASS
4836 13:29:56.753714 Write leveling : PASS
4837 13:29:56.756936 RX DQS gating : PASS
4838 13:29:56.757049 RX DQ/DQS(RDDQC) : PASS
4839 13:29:56.760703 TX DQ/DQS : PASS
4840 13:29:56.764127 RX DATLAT : PASS
4841 13:29:56.764204 RX DQ/DQS(Engine): PASS
4842 13:29:56.767397 TX OE : NO K
4843 13:29:56.767462 All Pass.
4844 13:29:56.767517
4845 13:29:56.770274 CH 1, Rank 0
4846 13:29:56.770340 SW Impedance : PASS
4847 13:29:56.774007 DUTY Scan : NO K
4848 13:29:56.776844 ZQ Calibration : PASS
4849 13:29:56.776904 Jitter Meter : NO K
4850 13:29:56.780172 CBT Training : PASS
4851 13:29:56.783949 Write leveling : PASS
4852 13:29:56.784029 RX DQS gating : PASS
4853 13:29:56.786766 RX DQ/DQS(RDDQC) : PASS
4854 13:29:56.790475 TX DQ/DQS : PASS
4855 13:29:56.790551 RX DATLAT : PASS
4856 13:29:56.793615 RX DQ/DQS(Engine): PASS
4857 13:29:56.793690 TX OE : NO K
4858 13:29:56.796725 All Pass.
4859 13:29:56.796799
4860 13:29:56.796857 CH 1, Rank 1
4861 13:29:56.799928 SW Impedance : PASS
4862 13:29:56.800003 DUTY Scan : NO K
4863 13:29:56.803752 ZQ Calibration : PASS
4864 13:29:56.806818 Jitter Meter : NO K
4865 13:29:56.806893 CBT Training : PASS
4866 13:29:56.810293 Write leveling : PASS
4867 13:29:56.813214 RX DQS gating : PASS
4868 13:29:56.813289 RX DQ/DQS(RDDQC) : PASS
4869 13:29:56.816629 TX DQ/DQS : PASS
4870 13:29:56.819737 RX DATLAT : PASS
4871 13:29:56.819812 RX DQ/DQS(Engine): PASS
4872 13:29:56.823343 TX OE : NO K
4873 13:29:56.823434 All Pass.
4874 13:29:56.823508
4875 13:29:56.826547 DramC Write-DBI off
4876 13:29:56.829677 PER_BANK_REFRESH: Hybrid Mode
4877 13:29:56.829763 TX_TRACKING: ON
4878 13:29:56.839499 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4879 13:29:56.843205 [FAST_K] Save calibration result to emmc
4880 13:29:56.846460 dramc_set_vcore_voltage set vcore to 662500
4881 13:29:56.849607 Read voltage for 933, 3
4882 13:29:56.849682 Vio18 = 0
4883 13:29:56.849741 Vcore = 662500
4884 13:29:56.852746 Vdram = 0
4885 13:29:56.852821 Vddq = 0
4886 13:29:56.852879 Vmddr = 0
4887 13:29:56.859412 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4888 13:29:56.862636 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4889 13:29:56.865918 MEM_TYPE=3, freq_sel=17
4890 13:29:56.869807 sv_algorithm_assistance_LP4_1600
4891 13:29:56.872362 ============ PULL DRAM RESETB DOWN ============
4892 13:29:56.879342 ========== PULL DRAM RESETB DOWN end =========
4893 13:29:56.882495 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4894 13:29:56.885783 ===================================
4895 13:29:56.889286 LPDDR4 DRAM CONFIGURATION
4896 13:29:56.892311 ===================================
4897 13:29:56.892403 EX_ROW_EN[0] = 0x0
4898 13:29:56.895690 EX_ROW_EN[1] = 0x0
4899 13:29:56.895803 LP4Y_EN = 0x0
4900 13:29:56.898981 WORK_FSP = 0x0
4901 13:29:56.899074 WL = 0x3
4902 13:29:56.902176 RL = 0x3
4903 13:29:56.905854 BL = 0x2
4904 13:29:56.905951 RPST = 0x0
4905 13:29:56.909033 RD_PRE = 0x0
4906 13:29:56.909131 WR_PRE = 0x1
4907 13:29:56.912289 WR_PST = 0x0
4908 13:29:56.912382 DBI_WR = 0x0
4909 13:29:56.915386 DBI_RD = 0x0
4910 13:29:56.915479 OTF = 0x1
4911 13:29:56.918465 ===================================
4912 13:29:56.921887 ===================================
4913 13:29:56.925053 ANA top config
4914 13:29:56.928399 ===================================
4915 13:29:56.928493 DLL_ASYNC_EN = 0
4916 13:29:56.931740 ALL_SLAVE_EN = 1
4917 13:29:56.935389 NEW_RANK_MODE = 1
4918 13:29:56.938455 DLL_IDLE_MODE = 1
4919 13:29:56.941912 LP45_APHY_COMB_EN = 1
4920 13:29:56.941978 TX_ODT_DIS = 1
4921 13:29:56.944981 NEW_8X_MODE = 1
4922 13:29:56.948174 ===================================
4923 13:29:56.952023 ===================================
4924 13:29:56.955150 data_rate = 1866
4925 13:29:56.958329 CKR = 1
4926 13:29:56.961388 DQ_P2S_RATIO = 8
4927 13:29:56.964457 ===================================
4928 13:29:56.968169 CA_P2S_RATIO = 8
4929 13:29:56.968243 DQ_CA_OPEN = 0
4930 13:29:56.971336 DQ_SEMI_OPEN = 0
4931 13:29:56.974563 CA_SEMI_OPEN = 0
4932 13:29:56.978250 CA_FULL_RATE = 0
4933 13:29:56.980948 DQ_CKDIV4_EN = 1
4934 13:29:56.984606 CA_CKDIV4_EN = 1
4935 13:29:56.984674 CA_PREDIV_EN = 0
4936 13:29:56.987769 PH8_DLY = 0
4937 13:29:56.990913 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4938 13:29:56.994107 DQ_AAMCK_DIV = 4
4939 13:29:56.997824 CA_AAMCK_DIV = 4
4940 13:29:57.000782 CA_ADMCK_DIV = 4
4941 13:29:57.000845 DQ_TRACK_CA_EN = 0
4942 13:29:57.004533 CA_PICK = 933
4943 13:29:57.007653 CA_MCKIO = 933
4944 13:29:57.011024 MCKIO_SEMI = 0
4945 13:29:57.013985 PLL_FREQ = 3732
4946 13:29:57.017445 DQ_UI_PI_RATIO = 32
4947 13:29:57.020643 CA_UI_PI_RATIO = 0
4948 13:29:57.023684 ===================================
4949 13:29:57.027405 ===================================
4950 13:29:57.027471 memory_type:LPDDR4
4951 13:29:57.030442 GP_NUM : 10
4952 13:29:57.033446 SRAM_EN : 1
4953 13:29:57.033510 MD32_EN : 0
4954 13:29:57.037106 ===================================
4955 13:29:57.040011 [ANA_INIT] >>>>>>>>>>>>>>
4956 13:29:57.043407 <<<<<< [CONFIGURE PHASE]: ANA_TX
4957 13:29:57.046688 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4958 13:29:57.050411 ===================================
4959 13:29:57.053552 data_rate = 1866,PCW = 0X8f00
4960 13:29:57.056662 ===================================
4961 13:29:57.059904 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4962 13:29:57.063053 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4963 13:29:57.070034 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4964 13:29:57.076509 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4965 13:29:57.079599 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4966 13:29:57.082720 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4967 13:29:57.082788 [ANA_INIT] flow start
4968 13:29:57.086504 [ANA_INIT] PLL >>>>>>>>
4969 13:29:57.089399 [ANA_INIT] PLL <<<<<<<<
4970 13:29:57.089462 [ANA_INIT] MIDPI >>>>>>>>
4971 13:29:57.092487 [ANA_INIT] MIDPI <<<<<<<<
4972 13:29:57.096292 [ANA_INIT] DLL >>>>>>>>
4973 13:29:57.096354 [ANA_INIT] flow end
4974 13:29:57.102670 ============ LP4 DIFF to SE enter ============
4975 13:29:57.105637 ============ LP4 DIFF to SE exit ============
4976 13:29:57.109313 [ANA_INIT] <<<<<<<<<<<<<
4977 13:29:57.112575 [Flow] Enable top DCM control >>>>>
4978 13:29:57.115751 [Flow] Enable top DCM control <<<<<
4979 13:29:57.118849 Enable DLL master slave shuffle
4980 13:29:57.122328 ==============================================================
4981 13:29:57.125928 Gating Mode config
4982 13:29:57.128637 ==============================================================
4983 13:29:57.132336 Config description:
4984 13:29:57.142295 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4985 13:29:57.149118 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4986 13:29:57.151994 SELPH_MODE 0: By rank 1: By Phase
4987 13:29:57.158550 ==============================================================
4988 13:29:57.161798 GAT_TRACK_EN = 1
4989 13:29:57.164962 RX_GATING_MODE = 2
4990 13:29:57.168819 RX_GATING_TRACK_MODE = 2
4991 13:29:57.171951 SELPH_MODE = 1
4992 13:29:57.175062 PICG_EARLY_EN = 1
4993 13:29:57.178401 VALID_LAT_VALUE = 1
4994 13:29:57.181893 ==============================================================
4995 13:29:57.184999 Enter into Gating configuration >>>>
4996 13:29:57.188227 Exit from Gating configuration <<<<
4997 13:29:57.191419 Enter into DVFS_PRE_config >>>>>
4998 13:29:57.204824 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4999 13:29:57.204913 Exit from DVFS_PRE_config <<<<<
5000 13:29:57.207935 Enter into PICG configuration >>>>
5001 13:29:57.211530 Exit from PICG configuration <<<<
5002 13:29:57.214676 [RX_INPUT] configuration >>>>>
5003 13:29:57.217947 [RX_INPUT] configuration <<<<<
5004 13:29:57.224289 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5005 13:29:57.227930 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5006 13:29:57.234725 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5007 13:29:57.240992 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5008 13:29:57.247259 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5009 13:29:57.254225 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5010 13:29:57.257329 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5011 13:29:57.260317 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5012 13:29:57.267114 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5013 13:29:57.270517 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5014 13:29:57.274028 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5015 13:29:57.277113 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5016 13:29:57.280343 ===================================
5017 13:29:57.283492 LPDDR4 DRAM CONFIGURATION
5018 13:29:57.287002 ===================================
5019 13:29:57.290372 EX_ROW_EN[0] = 0x0
5020 13:29:57.290465 EX_ROW_EN[1] = 0x0
5021 13:29:57.293484 LP4Y_EN = 0x0
5022 13:29:57.293551 WORK_FSP = 0x0
5023 13:29:57.296704 WL = 0x3
5024 13:29:57.296765 RL = 0x3
5025 13:29:57.299977 BL = 0x2
5026 13:29:57.300051 RPST = 0x0
5027 13:29:57.303760 RD_PRE = 0x0
5028 13:29:57.303835 WR_PRE = 0x1
5029 13:29:57.306593 WR_PST = 0x0
5030 13:29:57.309863 DBI_WR = 0x0
5031 13:29:57.309938 DBI_RD = 0x0
5032 13:29:57.313520 OTF = 0x1
5033 13:29:57.316681 ===================================
5034 13:29:57.319856 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5035 13:29:57.322939 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5036 13:29:57.326129 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5037 13:29:57.329856 ===================================
5038 13:29:57.333054 LPDDR4 DRAM CONFIGURATION
5039 13:29:57.336302 ===================================
5040 13:29:57.339379 EX_ROW_EN[0] = 0x10
5041 13:29:57.339453 EX_ROW_EN[1] = 0x0
5042 13:29:57.343053 LP4Y_EN = 0x0
5043 13:29:57.343127 WORK_FSP = 0x0
5044 13:29:57.346071 WL = 0x3
5045 13:29:57.346145 RL = 0x3
5046 13:29:57.349579 BL = 0x2
5047 13:29:57.349653 RPST = 0x0
5048 13:29:57.352686 RD_PRE = 0x0
5049 13:29:57.356087 WR_PRE = 0x1
5050 13:29:57.356161 WR_PST = 0x0
5051 13:29:57.359119 DBI_WR = 0x0
5052 13:29:57.359194 DBI_RD = 0x0
5053 13:29:57.362359 OTF = 0x1
5054 13:29:57.365979 ===================================
5055 13:29:57.369077 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5056 13:29:57.374958 nWR fixed to 30
5057 13:29:57.377929 [ModeRegInit_LP4] CH0 RK0
5058 13:29:57.378003 [ModeRegInit_LP4] CH0 RK1
5059 13:29:57.381586 [ModeRegInit_LP4] CH1 RK0
5060 13:29:57.384477 [ModeRegInit_LP4] CH1 RK1
5061 13:29:57.384547 match AC timing 9
5062 13:29:57.391379 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5063 13:29:57.394397 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5064 13:29:57.398141 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5065 13:29:57.404284 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5066 13:29:57.407918 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5067 13:29:57.407993 ==
5068 13:29:57.410979 Dram Type= 6, Freq= 0, CH_0, rank 0
5069 13:29:57.414400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5070 13:29:57.414489 ==
5071 13:29:57.421106 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5072 13:29:57.427374 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5073 13:29:57.431020 [CA 0] Center 38 (7~69) winsize 63
5074 13:29:57.434232 [CA 1] Center 37 (7~68) winsize 62
5075 13:29:57.437399 [CA 2] Center 34 (4~65) winsize 62
5076 13:29:57.440573 [CA 3] Center 34 (4~65) winsize 62
5077 13:29:57.443628 [CA 4] Center 33 (3~64) winsize 62
5078 13:29:57.447399 [CA 5] Center 32 (2~63) winsize 62
5079 13:29:57.447468
5080 13:29:57.450662 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5081 13:29:57.450736
5082 13:29:57.453716 [CATrainingPosCal] consider 1 rank data
5083 13:29:57.456937 u2DelayCellTimex100 = 270/100 ps
5084 13:29:57.460468 CA0 delay=38 (7~69),Diff = 6 PI (37 cell)
5085 13:29:57.463406 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5086 13:29:57.466812 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5087 13:29:57.473627 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5088 13:29:57.476708 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5089 13:29:57.479884 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5090 13:29:57.479958
5091 13:29:57.482832 CA PerBit enable=1, Macro0, CA PI delay=32
5092 13:29:57.482914
5093 13:29:57.486398 [CBTSetCACLKResult] CA Dly = 32
5094 13:29:57.486487 CS Dly: 6 (0~37)
5095 13:29:57.489871 ==
5096 13:29:57.493162 Dram Type= 6, Freq= 0, CH_0, rank 1
5097 13:29:57.496480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5098 13:29:57.496556 ==
5099 13:29:57.499723 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5100 13:29:57.506093 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5101 13:29:57.510158 [CA 0] Center 38 (8~69) winsize 62
5102 13:29:57.513345 [CA 1] Center 37 (7~68) winsize 62
5103 13:29:57.516709 [CA 2] Center 35 (5~65) winsize 61
5104 13:29:57.519717 [CA 3] Center 34 (4~65) winsize 62
5105 13:29:57.523092 [CA 4] Center 33 (3~64) winsize 62
5106 13:29:57.526501 [CA 5] Center 33 (3~63) winsize 61
5107 13:29:57.526576
5108 13:29:57.529674 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5109 13:29:57.529750
5110 13:29:57.532972 [CATrainingPosCal] consider 2 rank data
5111 13:29:57.536621 u2DelayCellTimex100 = 270/100 ps
5112 13:29:57.539711 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5113 13:29:57.546104 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5114 13:29:57.549363 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5115 13:29:57.553061 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5116 13:29:57.556303 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5117 13:29:57.559436 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5118 13:29:57.559511
5119 13:29:57.562535 CA PerBit enable=1, Macro0, CA PI delay=33
5120 13:29:57.562610
5121 13:29:57.566316 [CBTSetCACLKResult] CA Dly = 33
5122 13:29:57.569424 CS Dly: 7 (0~39)
5123 13:29:57.569514
5124 13:29:57.572547 ----->DramcWriteLeveling(PI) begin...
5125 13:29:57.572624 ==
5126 13:29:57.576149 Dram Type= 6, Freq= 0, CH_0, rank 0
5127 13:29:57.579640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5128 13:29:57.579716 ==
5129 13:29:57.582515 Write leveling (Byte 0): 31 => 31
5130 13:29:57.585852 Write leveling (Byte 1): 28 => 28
5131 13:29:57.589485 DramcWriteLeveling(PI) end<-----
5132 13:29:57.589561
5133 13:29:57.589619 ==
5134 13:29:57.592668 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 13:29:57.595818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 13:29:57.595894 ==
5137 13:29:57.599433 [Gating] SW mode calibration
5138 13:29:57.605562 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5139 13:29:57.612325 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5140 13:29:57.615396 0 14 0 | B1->B0 | 2525 3333 | 1 0 | (1 1) (0 0)
5141 13:29:57.618924 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5142 13:29:57.625287 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 13:29:57.628945 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5144 13:29:57.631773 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5145 13:29:57.638153 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 13:29:57.641974 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5147 13:29:57.648187 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5148 13:29:57.651394 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5149 13:29:57.654574 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5150 13:29:57.661493 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 13:29:57.664792 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 13:29:57.668046 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 13:29:57.674896 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 13:29:57.678101 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5155 13:29:57.681132 0 15 28 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
5156 13:29:57.687962 1 0 0 | B1->B0 | 3232 4646 | 0 0 | (1 1) (0 0)
5157 13:29:57.691016 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 13:29:57.694614 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 13:29:57.700806 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 13:29:57.704250 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 13:29:57.707318 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 13:29:57.714679 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5163 13:29:57.717391 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5164 13:29:57.720610 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5165 13:29:57.727158 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 13:29:57.730937 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 13:29:57.734120 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 13:29:57.737292 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 13:29:57.744373 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 13:29:57.747120 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 13:29:57.753674 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 13:29:57.756849 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 13:29:57.760677 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 13:29:57.766995 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 13:29:57.770198 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 13:29:57.773331 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 13:29:57.780179 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 13:29:57.783438 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 13:29:57.786935 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5180 13:29:57.790145 Total UI for P1: 0, mck2ui 16
5181 13:29:57.793145 best dqsien dly found for B0: ( 1, 2, 26)
5182 13:29:57.800118 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5183 13:29:57.803261 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 13:29:57.806188 Total UI for P1: 0, mck2ui 16
5185 13:29:57.809689 best dqsien dly found for B1: ( 1, 2, 30)
5186 13:29:57.813262 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5187 13:29:57.816015 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5188 13:29:57.816090
5189 13:29:57.819500 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5190 13:29:57.822743 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5191 13:29:57.826234 [Gating] SW calibration Done
5192 13:29:57.826310 ==
5193 13:29:57.829255 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 13:29:57.832779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 13:29:57.836202 ==
5196 13:29:57.836278 RX Vref Scan: 0
5197 13:29:57.836373
5198 13:29:57.838995 RX Vref 0 -> 0, step: 1
5199 13:29:57.839084
5200 13:29:57.842653 RX Delay -80 -> 252, step: 8
5201 13:29:57.845650 iDelay=200, Bit 0, Center 107 (16 ~ 199) 184
5202 13:29:57.849429 iDelay=200, Bit 1, Center 107 (16 ~ 199) 184
5203 13:29:57.852584 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5204 13:29:57.855545 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5205 13:29:57.862073 iDelay=200, Bit 4, Center 107 (16 ~ 199) 184
5206 13:29:57.865854 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5207 13:29:57.868948 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5208 13:29:57.872243 iDelay=200, Bit 7, Center 111 (24 ~ 199) 176
5209 13:29:57.875317 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5210 13:29:57.878543 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5211 13:29:57.885413 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5212 13:29:57.888564 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5213 13:29:57.892169 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5214 13:29:57.895292 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5215 13:29:57.898484 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5216 13:29:57.904778 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5217 13:29:57.904853 ==
5218 13:29:57.908562 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 13:29:57.911569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 13:29:57.911645 ==
5221 13:29:57.911703 DQS Delay:
5222 13:29:57.915171 DQS0 = 0, DQS1 = 0
5223 13:29:57.915246 DQM Delay:
5224 13:29:57.918385 DQM0 = 103, DQM1 = 87
5225 13:29:57.918460 DQ Delay:
5226 13:29:57.921450 DQ0 =107, DQ1 =107, DQ2 =95, DQ3 =99
5227 13:29:57.925054 DQ4 =107, DQ5 =91, DQ6 =107, DQ7 =111
5228 13:29:57.927910 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =83
5229 13:29:57.931402 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5230 13:29:57.931476
5231 13:29:57.931535
5232 13:29:57.931588 ==
5233 13:29:57.934533 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 13:29:57.941057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 13:29:57.941133 ==
5236 13:29:57.941257
5237 13:29:57.941343
5238 13:29:57.941482 TX Vref Scan disable
5239 13:29:57.944789 == TX Byte 0 ==
5240 13:29:57.948103 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5241 13:29:57.951376 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5242 13:29:57.954763 == TX Byte 1 ==
5243 13:29:57.958329 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5244 13:29:57.964816 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5245 13:29:57.964893 ==
5246 13:29:57.967877 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 13:29:57.971209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 13:29:57.971285 ==
5249 13:29:57.971344
5250 13:29:57.971397
5251 13:29:57.974819 TX Vref Scan disable
5252 13:29:57.974895 == TX Byte 0 ==
5253 13:29:57.980970 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5254 13:29:57.984733 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5255 13:29:57.987842 == TX Byte 1 ==
5256 13:29:57.991029 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5257 13:29:57.994518 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5258 13:29:57.994594
5259 13:29:57.994653 [DATLAT]
5260 13:29:57.997546 Freq=933, CH0 RK0
5261 13:29:57.997621
5262 13:29:57.997679 DATLAT Default: 0xd
5263 13:29:58.001189 0, 0xFFFF, sum = 0
5264 13:29:58.004502 1, 0xFFFF, sum = 0
5265 13:29:58.004579 2, 0xFFFF, sum = 0
5266 13:29:58.007684 3, 0xFFFF, sum = 0
5267 13:29:58.007761 4, 0xFFFF, sum = 0
5268 13:29:58.010880 5, 0xFFFF, sum = 0
5269 13:29:58.010956 6, 0xFFFF, sum = 0
5270 13:29:58.013883 7, 0xFFFF, sum = 0
5271 13:29:58.013963 8, 0xFFFF, sum = 0
5272 13:29:58.017481 9, 0xFFFF, sum = 0
5273 13:29:58.017557 10, 0x0, sum = 1
5274 13:29:58.020467 11, 0x0, sum = 2
5275 13:29:58.020543 12, 0x0, sum = 3
5276 13:29:58.023747 13, 0x0, sum = 4
5277 13:29:58.023824 best_step = 11
5278 13:29:58.023882
5279 13:29:58.023937 ==
5280 13:29:58.026890 Dram Type= 6, Freq= 0, CH_0, rank 0
5281 13:29:58.030609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 13:29:58.033842 ==
5283 13:29:58.033918 RX Vref Scan: 1
5284 13:29:58.033977
5285 13:29:58.036791 RX Vref 0 -> 0, step: 1
5286 13:29:58.036854
5287 13:29:58.040238 RX Delay -69 -> 252, step: 4
5288 13:29:58.040301
5289 13:29:58.043895 Set Vref, RX VrefLevel [Byte0]: 56
5290 13:29:58.046904 [Byte1]: 49
5291 13:29:58.047015
5292 13:29:58.049925 Final RX Vref Byte 0 = 56 to rank0
5293 13:29:58.053671 Final RX Vref Byte 1 = 49 to rank0
5294 13:29:58.056849 Final RX Vref Byte 0 = 56 to rank1
5295 13:29:58.059881 Final RX Vref Byte 1 = 49 to rank1==
5296 13:29:58.063453 Dram Type= 6, Freq= 0, CH_0, rank 0
5297 13:29:58.066813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 13:29:58.066889 ==
5299 13:29:58.070199 DQS Delay:
5300 13:29:58.070277 DQS0 = 0, DQS1 = 0
5301 13:29:58.070337 DQM Delay:
5302 13:29:58.073051 DQM0 = 103, DQM1 = 90
5303 13:29:58.073125 DQ Delay:
5304 13:29:58.076430 DQ0 =104, DQ1 =102, DQ2 =100, DQ3 =100
5305 13:29:58.079939 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =108
5306 13:29:58.082876 DQ8 =82, DQ9 =76, DQ10 =90, DQ11 =84
5307 13:29:58.086400 DQ12 =98, DQ13 =94, DQ14 =98, DQ15 =98
5308 13:29:58.086494
5309 13:29:58.089612
5310 13:29:58.096551 [DQSOSCAuto] RK0, (LSB)MR18= 0x1711, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
5311 13:29:58.099576 CH0 RK0: MR19=505, MR18=1711
5312 13:29:58.106005 CH0_RK0: MR19=0x505, MR18=0x1711, DQSOSC=414, MR23=63, INC=63, DEC=42
5313 13:29:58.106080
5314 13:29:58.109848 ----->DramcWriteLeveling(PI) begin...
5315 13:29:58.109925 ==
5316 13:29:58.112943 Dram Type= 6, Freq= 0, CH_0, rank 1
5317 13:29:58.116171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 13:29:58.116303 ==
5319 13:29:58.119117 Write leveling (Byte 0): 31 => 31
5320 13:29:58.122601 Write leveling (Byte 1): 27 => 27
5321 13:29:58.125854 DramcWriteLeveling(PI) end<-----
5322 13:29:58.125930
5323 13:29:58.125989 ==
5324 13:29:58.128946 Dram Type= 6, Freq= 0, CH_0, rank 1
5325 13:29:58.132720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 13:29:58.132820 ==
5327 13:29:58.135818 [Gating] SW mode calibration
5328 13:29:58.142282 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5329 13:29:58.149010 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5330 13:29:58.152177 0 14 0 | B1->B0 | 2b2b 3434 | 1 0 | (1 1) (0 0)
5331 13:29:58.158850 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 13:29:58.162255 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 13:29:58.165162 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 13:29:58.172072 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 13:29:58.175165 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 13:29:58.178834 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5337 13:29:58.185367 0 14 28 | B1->B0 | 3333 2c2c | 1 0 | (1 0) (1 0)
5338 13:29:58.188195 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5339 13:29:58.191740 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5340 13:29:58.198408 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 13:29:58.201493 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 13:29:58.204553 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 13:29:58.211459 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 13:29:58.214586 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5345 13:29:58.217725 0 15 28 | B1->B0 | 2929 3838 | 0 1 | (0 0) (0 0)
5346 13:29:58.224551 1 0 0 | B1->B0 | 4040 4545 | 0 0 | (0 0) (0 0)
5347 13:29:58.227596 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 13:29:58.231357 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 13:29:58.237797 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 13:29:58.240945 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 13:29:58.244128 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 13:29:58.251091 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5353 13:29:58.254146 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5354 13:29:58.257452 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5355 13:29:58.264017 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 13:29:58.267049 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 13:29:58.270807 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 13:29:58.276934 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 13:29:58.280222 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 13:29:58.283508 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 13:29:58.290071 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 13:29:58.293509 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 13:29:58.297046 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 13:29:58.303621 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 13:29:58.306870 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 13:29:58.310184 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 13:29:58.316575 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 13:29:58.319740 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5369 13:29:58.322949 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5370 13:29:58.326713 Total UI for P1: 0, mck2ui 16
5371 13:29:58.329913 best dqsien dly found for B0: ( 1, 2, 24)
5372 13:29:58.336715 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5373 13:29:58.339760 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 13:29:58.342927 Total UI for P1: 0, mck2ui 16
5375 13:29:58.346054 best dqsien dly found for B1: ( 1, 3, 2)
5376 13:29:58.349719 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5377 13:29:58.352955 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5378 13:29:58.353030
5379 13:29:58.356221 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5380 13:29:58.359314 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5381 13:29:58.363069 [Gating] SW calibration Done
5382 13:29:58.363170 ==
5383 13:29:58.366111 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 13:29:58.369299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 13:29:58.372382 ==
5386 13:29:58.372451 RX Vref Scan: 0
5387 13:29:58.372512
5388 13:29:58.376210 RX Vref 0 -> 0, step: 1
5389 13:29:58.376295
5390 13:29:58.379377 RX Delay -80 -> 252, step: 8
5391 13:29:58.382554 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5392 13:29:58.385683 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5393 13:29:58.389508 iDelay=200, Bit 2, Center 95 (8 ~ 183) 176
5394 13:29:58.392411 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5395 13:29:58.395635 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5396 13:29:58.402437 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5397 13:29:58.405725 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5398 13:29:58.408998 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5399 13:29:58.411985 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5400 13:29:58.415743 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5401 13:29:58.421939 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5402 13:29:58.425146 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5403 13:29:58.428644 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5404 13:29:58.432190 iDelay=200, Bit 13, Center 91 (0 ~ 183) 184
5405 13:29:58.435222 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5406 13:29:58.441622 iDelay=200, Bit 15, Center 95 (8 ~ 183) 176
5407 13:29:58.441694 ==
5408 13:29:58.444823 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 13:29:58.448108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 13:29:58.448208 ==
5411 13:29:58.448293 DQS Delay:
5412 13:29:58.451715 DQS0 = 0, DQS1 = 0
5413 13:29:58.451789 DQM Delay:
5414 13:29:58.454928 DQM0 = 100, DQM1 = 88
5415 13:29:58.455022 DQ Delay:
5416 13:29:58.458147 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5417 13:29:58.461282 DQ4 =103, DQ5 =91, DQ6 =107, DQ7 =107
5418 13:29:58.465017 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5419 13:29:58.468100 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =95
5420 13:29:58.468197
5421 13:29:58.468280
5422 13:29:58.468360 ==
5423 13:29:58.471103 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 13:29:58.478010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 13:29:58.478077 ==
5426 13:29:58.478133
5427 13:29:58.478186
5428 13:29:58.478236 TX Vref Scan disable
5429 13:29:58.481078 == TX Byte 0 ==
5430 13:29:58.484817 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5431 13:29:58.491145 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5432 13:29:58.491240 == TX Byte 1 ==
5433 13:29:58.494393 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5434 13:29:58.500588 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5435 13:29:58.500679 ==
5436 13:29:58.504395 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 13:29:58.507591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 13:29:58.507661 ==
5439 13:29:58.507718
5440 13:29:58.507771
5441 13:29:58.510684 TX Vref Scan disable
5442 13:29:58.510778 == TX Byte 0 ==
5443 13:29:58.517556 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5444 13:29:58.520783 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5445 13:29:58.523809 == TX Byte 1 ==
5446 13:29:58.527352 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5447 13:29:58.530435 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5448 13:29:58.530527
5449 13:29:58.530609 [DATLAT]
5450 13:29:58.534067 Freq=933, CH0 RK1
5451 13:29:58.534130
5452 13:29:58.537128 DATLAT Default: 0xb
5453 13:29:58.537254 0, 0xFFFF, sum = 0
5454 13:29:58.540519 1, 0xFFFF, sum = 0
5455 13:29:58.540621 2, 0xFFFF, sum = 0
5456 13:29:58.543547 3, 0xFFFF, sum = 0
5457 13:29:58.543656 4, 0xFFFF, sum = 0
5458 13:29:58.547304 5, 0xFFFF, sum = 0
5459 13:29:58.547397 6, 0xFFFF, sum = 0
5460 13:29:58.550298 7, 0xFFFF, sum = 0
5461 13:29:58.550364 8, 0xFFFF, sum = 0
5462 13:29:58.553905 9, 0xFFFF, sum = 0
5463 13:29:58.553974 10, 0x0, sum = 1
5464 13:29:58.557245 11, 0x0, sum = 2
5465 13:29:58.557334 12, 0x0, sum = 3
5466 13:29:58.560323 13, 0x0, sum = 4
5467 13:29:58.560411 best_step = 11
5468 13:29:58.560491
5469 13:29:58.560572 ==
5470 13:29:58.563723 Dram Type= 6, Freq= 0, CH_0, rank 1
5471 13:29:58.566679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 13:29:58.566745 ==
5473 13:29:58.570037 RX Vref Scan: 0
5474 13:29:58.570109
5475 13:29:58.573739 RX Vref 0 -> 0, step: 1
5476 13:29:58.573833
5477 13:29:58.573917 RX Delay -61 -> 252, step: 4
5478 13:29:58.581736 iDelay=195, Bit 0, Center 98 (15 ~ 182) 168
5479 13:29:58.584945 iDelay=195, Bit 1, Center 102 (15 ~ 190) 176
5480 13:29:58.588127 iDelay=195, Bit 2, Center 96 (11 ~ 182) 172
5481 13:29:58.591255 iDelay=195, Bit 3, Center 98 (11 ~ 186) 176
5482 13:29:58.594533 iDelay=195, Bit 4, Center 102 (15 ~ 190) 176
5483 13:29:58.601270 iDelay=195, Bit 5, Center 92 (7 ~ 178) 172
5484 13:29:58.604394 iDelay=195, Bit 6, Center 110 (27 ~ 194) 168
5485 13:29:58.607673 iDelay=195, Bit 7, Center 108 (23 ~ 194) 172
5486 13:29:58.611379 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5487 13:29:58.614580 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5488 13:29:58.620789 iDelay=195, Bit 10, Center 92 (7 ~ 178) 172
5489 13:29:58.623954 iDelay=195, Bit 11, Center 80 (-5 ~ 166) 172
5490 13:29:58.627634 iDelay=195, Bit 12, Center 94 (11 ~ 178) 168
5491 13:29:58.630767 iDelay=195, Bit 13, Center 94 (11 ~ 178) 168
5492 13:29:58.634256 iDelay=195, Bit 14, Center 100 (15 ~ 186) 172
5493 13:29:58.640466 iDelay=195, Bit 15, Center 96 (11 ~ 182) 172
5494 13:29:58.640539 ==
5495 13:29:58.644025 Dram Type= 6, Freq= 0, CH_0, rank 1
5496 13:29:58.647171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 13:29:58.647267 ==
5498 13:29:58.647353 DQS Delay:
5499 13:29:58.650361 DQS0 = 0, DQS1 = 0
5500 13:29:58.650451 DQM Delay:
5501 13:29:58.654010 DQM0 = 100, DQM1 = 89
5502 13:29:58.654102 DQ Delay:
5503 13:29:58.657084 DQ0 =98, DQ1 =102, DQ2 =96, DQ3 =98
5504 13:29:58.660334 DQ4 =102, DQ5 =92, DQ6 =110, DQ7 =108
5505 13:29:58.663522 DQ8 =80, DQ9 =76, DQ10 =92, DQ11 =80
5506 13:29:58.666727 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =96
5507 13:29:58.666821
5508 13:29:58.666904
5509 13:29:58.676821 [DQSOSCAuto] RK1, (LSB)MR18= 0x110f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 416 ps
5510 13:29:58.680168 CH0 RK1: MR19=505, MR18=110F
5511 13:29:58.683354 CH0_RK1: MR19=0x505, MR18=0x110F, DQSOSC=416, MR23=63, INC=62, DEC=41
5512 13:29:58.686363 [RxdqsGatingPostProcess] freq 933
5513 13:29:58.693042 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5514 13:29:58.696570 best DQS0 dly(2T, 0.5T) = (0, 10)
5515 13:29:58.699683 best DQS1 dly(2T, 0.5T) = (0, 10)
5516 13:29:58.702752 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5517 13:29:58.706460 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5518 13:29:58.709670 best DQS0 dly(2T, 0.5T) = (0, 10)
5519 13:29:58.712756 best DQS1 dly(2T, 0.5T) = (0, 11)
5520 13:29:58.715864 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5521 13:29:58.719645 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5522 13:29:58.722687 Pre-setting of DQS Precalculation
5523 13:29:58.725741 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5524 13:29:58.725809 ==
5525 13:29:58.729428 Dram Type= 6, Freq= 0, CH_1, rank 0
5526 13:29:58.732682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5527 13:29:58.735799 ==
5528 13:29:58.739371 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5529 13:29:58.745714 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5530 13:29:58.748838 [CA 0] Center 36 (6~67) winsize 62
5531 13:29:58.752572 [CA 1] Center 36 (6~67) winsize 62
5532 13:29:58.755674 [CA 2] Center 34 (4~64) winsize 61
5533 13:29:58.758841 [CA 3] Center 34 (4~64) winsize 61
5534 13:29:58.762031 [CA 4] Center 34 (4~64) winsize 61
5535 13:29:58.765797 [CA 5] Center 33 (3~64) winsize 62
5536 13:29:58.765898
5537 13:29:58.768925 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5538 13:29:58.769018
5539 13:29:58.772236 [CATrainingPosCal] consider 1 rank data
5540 13:29:58.775281 u2DelayCellTimex100 = 270/100 ps
5541 13:29:58.778375 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5542 13:29:58.782265 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5543 13:29:58.785446 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5544 13:29:58.791784 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5545 13:29:58.794860 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5546 13:29:58.798354 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5547 13:29:58.798419
5548 13:29:58.801745 CA PerBit enable=1, Macro0, CA PI delay=33
5549 13:29:58.801838
5550 13:29:58.805222 [CBTSetCACLKResult] CA Dly = 33
5551 13:29:58.805287 CS Dly: 4 (0~35)
5552 13:29:58.805342 ==
5553 13:29:58.808430 Dram Type= 6, Freq= 0, CH_1, rank 1
5554 13:29:58.815200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 13:29:58.815299 ==
5556 13:29:58.818406 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5557 13:29:58.824711 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5558 13:29:58.828368 [CA 0] Center 36 (6~67) winsize 62
5559 13:29:58.831504 [CA 1] Center 36 (6~67) winsize 62
5560 13:29:58.834614 [CA 2] Center 34 (4~65) winsize 62
5561 13:29:58.838325 [CA 3] Center 33 (3~64) winsize 62
5562 13:29:58.841298 [CA 4] Center 33 (3~64) winsize 62
5563 13:29:58.845010 [CA 5] Center 33 (3~64) winsize 62
5564 13:29:58.845108
5565 13:29:58.848144 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5566 13:29:58.848224
5567 13:29:58.851132 [CATrainingPosCal] consider 2 rank data
5568 13:29:58.854366 u2DelayCellTimex100 = 270/100 ps
5569 13:29:58.857855 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5570 13:29:58.864386 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5571 13:29:58.867471 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5572 13:29:58.871285 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5573 13:29:58.874402 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5574 13:29:58.877625 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5575 13:29:58.877715
5576 13:29:58.880717 CA PerBit enable=1, Macro0, CA PI delay=33
5577 13:29:58.880806
5578 13:29:58.883947 [CBTSetCACLKResult] CA Dly = 33
5579 13:29:58.887759 CS Dly: 5 (0~38)
5580 13:29:58.887854
5581 13:29:58.890892 ----->DramcWriteLeveling(PI) begin...
5582 13:29:58.890986 ==
5583 13:29:58.894036 Dram Type= 6, Freq= 0, CH_1, rank 0
5584 13:29:58.897290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5585 13:29:58.897360 ==
5586 13:29:58.900417 Write leveling (Byte 0): 26 => 26
5587 13:29:58.903513 Write leveling (Byte 1): 29 => 29
5588 13:29:58.907468 DramcWriteLeveling(PI) end<-----
5589 13:29:58.907555
5590 13:29:58.907640 ==
5591 13:29:58.910667 Dram Type= 6, Freq= 0, CH_1, rank 0
5592 13:29:58.913751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 13:29:58.913830 ==
5594 13:29:58.916970 [Gating] SW mode calibration
5595 13:29:58.923531 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5596 13:29:58.930283 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5597 13:29:58.933451 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 13:29:58.939988 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 13:29:58.943078 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 13:29:58.946432 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 13:29:58.953108 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 13:29:58.956576 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5603 13:29:58.959908 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 1)
5604 13:29:58.966098 0 14 28 | B1->B0 | 2b2b 2626 | 1 1 | (1 0) (1 1)
5605 13:29:58.969681 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 13:29:58.973056 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 13:29:58.979681 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 13:29:58.982827 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 13:29:58.985889 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 13:29:58.992834 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 13:29:58.995930 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5612 13:29:58.999047 0 15 28 | B1->B0 | 3434 3d3d | 0 1 | (1 1) (0 0)
5613 13:29:59.006012 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 13:29:59.009121 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 13:29:59.012261 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 13:29:59.019178 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 13:29:59.022175 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 13:29:59.025420 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 13:29:59.031704 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5620 13:29:59.034942 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5621 13:29:59.038705 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5622 13:29:59.045332 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 13:29:59.048304 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 13:29:59.051866 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 13:29:59.058144 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 13:29:59.061664 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 13:29:59.065055 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 13:29:59.071563 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 13:29:59.074695 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 13:29:59.077741 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 13:29:59.084562 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 13:29:59.088122 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 13:29:59.090999 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 13:29:59.097517 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 13:29:59.100721 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5636 13:29:59.104488 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 13:29:59.107674 Total UI for P1: 0, mck2ui 16
5638 13:29:59.110853 best dqsien dly found for B0: ( 1, 2, 24)
5639 13:29:59.114058 Total UI for P1: 0, mck2ui 16
5640 13:29:59.117246 best dqsien dly found for B1: ( 1, 2, 24)
5641 13:29:59.121233 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5642 13:29:59.124223 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5643 13:29:59.127295
5644 13:29:59.130486 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5645 13:29:59.133699 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5646 13:29:59.137436 [Gating] SW calibration Done
5647 13:29:59.137523 ==
5648 13:29:59.140424 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 13:29:59.143648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 13:29:59.143741 ==
5651 13:29:59.143830 RX Vref Scan: 0
5652 13:29:59.147322
5653 13:29:59.147407 RX Vref 0 -> 0, step: 1
5654 13:29:59.147489
5655 13:29:59.150459 RX Delay -80 -> 252, step: 8
5656 13:29:59.153577 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5657 13:29:59.156863 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5658 13:29:59.163693 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5659 13:29:59.166660 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5660 13:29:59.170169 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5661 13:29:59.173325 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5662 13:29:59.176414 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5663 13:29:59.179982 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5664 13:29:59.186715 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5665 13:29:59.190075 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5666 13:29:59.193322 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5667 13:29:59.196356 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5668 13:29:59.199610 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5669 13:29:59.206414 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5670 13:29:59.209101 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5671 13:29:59.212583 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5672 13:29:59.212677 ==
5673 13:29:59.216030 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 13:29:59.219166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 13:29:59.219303 ==
5676 13:29:59.222417 DQS Delay:
5677 13:29:59.222510 DQS0 = 0, DQS1 = 0
5678 13:29:59.226202 DQM Delay:
5679 13:29:59.226292 DQM0 = 99, DQM1 = 96
5680 13:29:59.226382 DQ Delay:
5681 13:29:59.229145 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5682 13:29:59.232310 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5683 13:29:59.235988 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5684 13:29:59.242255 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5685 13:29:59.242327
5686 13:29:59.242386
5687 13:29:59.242440 ==
5688 13:29:59.245492 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 13:29:59.249144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 13:29:59.249238 ==
5691 13:29:59.249294
5692 13:29:59.249353
5693 13:29:59.252047 TX Vref Scan disable
5694 13:29:59.252106 == TX Byte 0 ==
5695 13:29:59.258956 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5696 13:29:59.262217 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5697 13:29:59.262306 == TX Byte 1 ==
5698 13:29:59.268508 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5699 13:29:59.272148 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5700 13:29:59.272239 ==
5701 13:29:59.275149 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 13:29:59.278747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 13:29:59.278812 ==
5704 13:29:59.278869
5705 13:29:59.281851
5706 13:29:59.281938 TX Vref Scan disable
5707 13:29:59.285072 == TX Byte 0 ==
5708 13:29:59.288732 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5709 13:29:59.295024 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5710 13:29:59.295113 == TX Byte 1 ==
5711 13:29:59.298109 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5712 13:29:59.304902 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5713 13:29:59.304994
5714 13:29:59.305093 [DATLAT]
5715 13:29:59.305208 Freq=933, CH1 RK0
5716 13:29:59.305268
5717 13:29:59.307972 DATLAT Default: 0xd
5718 13:29:59.311486 0, 0xFFFF, sum = 0
5719 13:29:59.311582 1, 0xFFFF, sum = 0
5720 13:29:59.314494 2, 0xFFFF, sum = 0
5721 13:29:59.314589 3, 0xFFFF, sum = 0
5722 13:29:59.317902 4, 0xFFFF, sum = 0
5723 13:29:59.317996 5, 0xFFFF, sum = 0
5724 13:29:59.321517 6, 0xFFFF, sum = 0
5725 13:29:59.321607 7, 0xFFFF, sum = 0
5726 13:29:59.324311 8, 0xFFFF, sum = 0
5727 13:29:59.324399 9, 0xFFFF, sum = 0
5728 13:29:59.327799 10, 0x0, sum = 1
5729 13:29:59.327892 11, 0x0, sum = 2
5730 13:29:59.331188 12, 0x0, sum = 3
5731 13:29:59.331285 13, 0x0, sum = 4
5732 13:29:59.334628 best_step = 11
5733 13:29:59.334722
5734 13:29:59.334805 ==
5735 13:29:59.337693 Dram Type= 6, Freq= 0, CH_1, rank 0
5736 13:29:59.340844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 13:29:59.340931 ==
5738 13:29:59.341012 RX Vref Scan: 1
5739 13:29:59.344115
5740 13:29:59.344203 RX Vref 0 -> 0, step: 1
5741 13:29:59.344283
5742 13:29:59.347319 RX Delay -53 -> 252, step: 4
5743 13:29:59.347421
5744 13:29:59.351004 Set Vref, RX VrefLevel [Byte0]: 52
5745 13:29:59.354122 [Byte1]: 51
5746 13:29:59.357785
5747 13:29:59.357850 Final RX Vref Byte 0 = 52 to rank0
5748 13:29:59.360918 Final RX Vref Byte 1 = 51 to rank0
5749 13:29:59.364130 Final RX Vref Byte 0 = 52 to rank1
5750 13:29:59.367838 Final RX Vref Byte 1 = 51 to rank1==
5751 13:29:59.371007 Dram Type= 6, Freq= 0, CH_1, rank 0
5752 13:29:59.377257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 13:29:59.377348 ==
5754 13:29:59.377434 DQS Delay:
5755 13:29:59.380828 DQS0 = 0, DQS1 = 0
5756 13:29:59.380919 DQM Delay:
5757 13:29:59.381003 DQM0 = 98, DQM1 = 94
5758 13:29:59.383731 DQ Delay:
5759 13:29:59.386863 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =98
5760 13:29:59.390157 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5761 13:29:59.393709 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5762 13:29:59.396849 DQ12 =100, DQ13 =102, DQ14 =100, DQ15 =104
5763 13:29:59.396941
5764 13:29:59.397024
5765 13:29:59.403601 [DQSOSCAuto] RK0, (LSB)MR18= 0x918, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5766 13:29:59.406675 CH1 RK0: MR19=505, MR18=918
5767 13:29:59.413120 CH1_RK0: MR19=0x505, MR18=0x918, DQSOSC=414, MR23=63, INC=63, DEC=42
5768 13:29:59.413252
5769 13:29:59.416274 ----->DramcWriteLeveling(PI) begin...
5770 13:29:59.416341 ==
5771 13:29:59.419855 Dram Type= 6, Freq= 0, CH_1, rank 1
5772 13:29:59.422801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5773 13:29:59.426543 ==
5774 13:29:59.426610 Write leveling (Byte 0): 24 => 24
5775 13:29:59.429742 Write leveling (Byte 1): 24 => 24
5776 13:29:59.432894 DramcWriteLeveling(PI) end<-----
5777 13:29:59.432989
5778 13:29:59.433071 ==
5779 13:29:59.436467 Dram Type= 6, Freq= 0, CH_1, rank 1
5780 13:29:59.442685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5781 13:29:59.442774 ==
5782 13:29:59.446302 [Gating] SW mode calibration
5783 13:29:59.452553 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5784 13:29:59.455761 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5785 13:29:59.462630 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 13:29:59.465831 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 13:29:59.468984 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 13:29:59.475335 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 13:29:59.479059 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 13:29:59.482222 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5791 13:29:59.488743 0 14 24 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 0)
5792 13:29:59.491928 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
5793 13:29:59.495087 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 13:29:59.501979 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 13:29:59.505044 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 13:29:59.508244 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 13:29:59.515197 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 13:29:59.518535 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5799 13:29:59.521518 0 15 24 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (1 1)
5800 13:29:59.528369 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5801 13:29:59.531719 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 13:29:59.534730 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 13:29:59.540931 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 13:29:59.544286 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 13:29:59.547798 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 13:29:59.554127 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 13:29:59.557530 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5808 13:29:59.561052 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5809 13:29:59.567869 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 13:29:59.571020 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 13:29:59.574209 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 13:29:59.580958 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 13:29:59.584103 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 13:29:59.587446 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 13:29:59.593947 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 13:29:59.597454 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 13:29:59.600688 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 13:29:59.607572 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 13:29:59.610828 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 13:29:59.614016 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 13:29:59.620272 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 13:29:59.623903 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 13:29:59.627397 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5824 13:29:59.633560 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5825 13:29:59.637243 Total UI for P1: 0, mck2ui 16
5826 13:29:59.640193 best dqsien dly found for B0: ( 1, 2, 24)
5827 13:29:59.643542 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5828 13:29:59.647001 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 13:29:59.650243 Total UI for P1: 0, mck2ui 16
5830 13:29:59.653360 best dqsien dly found for B1: ( 1, 2, 28)
5831 13:29:59.657179 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5832 13:29:59.663131 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5833 13:29:59.663666
5834 13:29:59.666833 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5835 13:29:59.670255 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5836 13:29:59.673053 [Gating] SW calibration Done
5837 13:29:59.673528 ==
5838 13:29:59.676296 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 13:29:59.679791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 13:29:59.680364 ==
5841 13:29:59.683004 RX Vref Scan: 0
5842 13:29:59.683413
5843 13:29:59.683749 RX Vref 0 -> 0, step: 1
5844 13:29:59.684184
5845 13:29:59.686775 RX Delay -80 -> 252, step: 8
5846 13:29:59.689898 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5847 13:29:59.693080 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5848 13:29:59.699953 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5849 13:29:59.702882 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5850 13:29:59.706324 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5851 13:29:59.710018 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5852 13:29:59.713022 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5853 13:29:59.716141 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5854 13:29:59.722719 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5855 13:29:59.725820 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5856 13:29:59.729485 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5857 13:29:59.732942 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5858 13:29:59.735872 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5859 13:29:59.742721 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5860 13:29:59.746006 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5861 13:29:59.749014 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5862 13:29:59.749461 ==
5863 13:29:59.752335 Dram Type= 6, Freq= 0, CH_1, rank 1
5864 13:29:59.755686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5865 13:29:59.756179 ==
5866 13:29:59.759375 DQS Delay:
5867 13:29:59.759929 DQS0 = 0, DQS1 = 0
5868 13:29:59.762445 DQM Delay:
5869 13:29:59.762843 DQM0 = 97, DQM1 = 94
5870 13:29:59.763234 DQ Delay:
5871 13:29:59.765651 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5872 13:29:59.768754 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5873 13:29:59.772307 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5874 13:29:59.778779 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =103
5875 13:29:59.779200
5876 13:29:59.779587
5877 13:29:59.779952 ==
5878 13:29:59.782277 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 13:29:59.785680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 13:29:59.786155 ==
5881 13:29:59.786548
5882 13:29:59.786913
5883 13:29:59.788690 TX Vref Scan disable
5884 13:29:59.789085 == TX Byte 0 ==
5885 13:29:59.795544 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5886 13:29:59.798662 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5887 13:29:59.799152 == TX Byte 1 ==
5888 13:29:59.805619 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5889 13:29:59.808597 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5890 13:29:59.808982 ==
5891 13:29:59.811572 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 13:29:59.815025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 13:29:59.815425 ==
5894 13:29:59.815819
5895 13:29:59.816183
5896 13:29:59.818527 TX Vref Scan disable
5897 13:29:59.821624 == TX Byte 0 ==
5898 13:29:59.824867 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5899 13:29:59.828711 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5900 13:29:59.831764 == TX Byte 1 ==
5901 13:29:59.834961 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5902 13:29:59.837993 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5903 13:29:59.841513
5904 13:29:59.841943 [DATLAT]
5905 13:29:59.842402 Freq=933, CH1 RK1
5906 13:29:59.843270
5907 13:29:59.844913 DATLAT Default: 0xb
5908 13:29:59.845518 0, 0xFFFF, sum = 0
5909 13:29:59.847985 1, 0xFFFF, sum = 0
5910 13:29:59.848707 2, 0xFFFF, sum = 0
5911 13:29:59.851012 3, 0xFFFF, sum = 0
5912 13:29:59.854659 4, 0xFFFF, sum = 0
5913 13:29:59.855210 5, 0xFFFF, sum = 0
5914 13:29:59.857944 6, 0xFFFF, sum = 0
5915 13:29:59.858525 7, 0xFFFF, sum = 0
5916 13:29:59.860985 8, 0xFFFF, sum = 0
5917 13:29:59.861618 9, 0xFFFF, sum = 0
5918 13:29:59.864358 10, 0x0, sum = 1
5919 13:29:59.864863 11, 0x0, sum = 2
5920 13:29:59.867910 12, 0x0, sum = 3
5921 13:29:59.868362 13, 0x0, sum = 4
5922 13:29:59.868827 best_step = 11
5923 13:29:59.869451
5924 13:29:59.871365 ==
5925 13:29:59.874248 Dram Type= 6, Freq= 0, CH_1, rank 1
5926 13:29:59.877655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5927 13:29:59.878213 ==
5928 13:29:59.878705 RX Vref Scan: 0
5929 13:29:59.879210
5930 13:29:59.880740 RX Vref 0 -> 0, step: 1
5931 13:29:59.881281
5932 13:29:59.884415 RX Delay -53 -> 252, step: 4
5933 13:29:59.891033 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5934 13:29:59.894221 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5935 13:29:59.897348 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5936 13:29:59.900390 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5937 13:29:59.903931 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5938 13:29:59.907208 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5939 13:29:59.913618 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5940 13:29:59.917376 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5941 13:29:59.920149 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5942 13:29:59.923664 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5943 13:29:59.927147 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5944 13:29:59.933423 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5945 13:29:59.936522 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5946 13:29:59.939650 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5947 13:29:59.943448 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5948 13:29:59.946583 iDelay=199, Bit 15, Center 100 (7 ~ 194) 188
5949 13:29:59.950201 ==
5950 13:29:59.952927 Dram Type= 6, Freq= 0, CH_1, rank 1
5951 13:29:59.956756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5952 13:29:59.957322 ==
5953 13:29:59.957702 DQS Delay:
5954 13:29:59.959882 DQS0 = 0, DQS1 = 0
5955 13:29:59.960421 DQM Delay:
5956 13:29:59.962974 DQM0 = 96, DQM1 = 92
5957 13:29:59.963539 DQ Delay:
5958 13:29:59.966201 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =92
5959 13:29:59.969933 DQ4 =96, DQ5 =106, DQ6 =106, DQ7 =92
5960 13:29:59.972907 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =86
5961 13:29:59.976697 DQ12 =100, DQ13 =100, DQ14 =96, DQ15 =100
5962 13:29:59.977286
5963 13:29:59.977821
5964 13:29:59.982979 [DQSOSCAuto] RK1, (LSB)MR18= 0xc24, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 418 ps
5965 13:29:59.986389 CH1 RK1: MR19=505, MR18=C24
5966 13:29:59.993036 CH1_RK1: MR19=0x505, MR18=0xC24, DQSOSC=410, MR23=63, INC=64, DEC=42
5967 13:29:59.996046 [RxdqsGatingPostProcess] freq 933
5968 13:30:00.002598 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5969 13:30:00.006489 best DQS0 dly(2T, 0.5T) = (0, 10)
5970 13:30:00.009433 best DQS1 dly(2T, 0.5T) = (0, 10)
5971 13:30:00.013250 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5972 13:30:00.013790 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5973 13:30:00.015895 best DQS0 dly(2T, 0.5T) = (0, 10)
5974 13:30:00.019308 best DQS1 dly(2T, 0.5T) = (0, 10)
5975 13:30:00.022379 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5976 13:30:00.025920 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5977 13:30:00.028837 Pre-setting of DQS Precalculation
5978 13:30:00.035797 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5979 13:30:00.042080 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5980 13:30:00.049046 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5981 13:30:00.049487
5982 13:30:00.049801
5983 13:30:00.052078 [Calibration Summary] 1866 Mbps
5984 13:30:00.052463 CH 0, Rank 0
5985 13:30:00.055254 SW Impedance : PASS
5986 13:30:00.058708 DUTY Scan : NO K
5987 13:30:00.059094 ZQ Calibration : PASS
5988 13:30:00.061972 Jitter Meter : NO K
5989 13:30:00.065117 CBT Training : PASS
5990 13:30:00.065563 Write leveling : PASS
5991 13:30:00.068378 RX DQS gating : PASS
5992 13:30:00.071639 RX DQ/DQS(RDDQC) : PASS
5993 13:30:00.072054 TX DQ/DQS : PASS
5994 13:30:00.075298 RX DATLAT : PASS
5995 13:30:00.078408 RX DQ/DQS(Engine): PASS
5996 13:30:00.078793 TX OE : NO K
5997 13:30:00.082057 All Pass.
5998 13:30:00.082594
5999 13:30:00.083062 CH 0, Rank 1
6000 13:30:00.085015 SW Impedance : PASS
6001 13:30:00.085578 DUTY Scan : NO K
6002 13:30:00.088360 ZQ Calibration : PASS
6003 13:30:00.091848 Jitter Meter : NO K
6004 13:30:00.092432 CBT Training : PASS
6005 13:30:00.095371 Write leveling : PASS
6006 13:30:00.098169 RX DQS gating : PASS
6007 13:30:00.098637 RX DQ/DQS(RDDQC) : PASS
6008 13:30:00.101791 TX DQ/DQS : PASS
6009 13:30:00.104926 RX DATLAT : PASS
6010 13:30:00.105499 RX DQ/DQS(Engine): PASS
6011 13:30:00.108098 TX OE : NO K
6012 13:30:00.108568 All Pass.
6013 13:30:00.108926
6014 13:30:00.111372 CH 1, Rank 0
6015 13:30:00.111889 SW Impedance : PASS
6016 13:30:00.115337 DUTY Scan : NO K
6017 13:30:00.118054 ZQ Calibration : PASS
6018 13:30:00.118731 Jitter Meter : NO K
6019 13:30:00.121585 CBT Training : PASS
6020 13:30:00.122045 Write leveling : PASS
6021 13:30:00.124658 RX DQS gating : PASS
6022 13:30:00.127734 RX DQ/DQS(RDDQC) : PASS
6023 13:30:00.128201 TX DQ/DQS : PASS
6024 13:30:00.131202 RX DATLAT : PASS
6025 13:30:00.134449 RX DQ/DQS(Engine): PASS
6026 13:30:00.134835 TX OE : NO K
6027 13:30:00.137720 All Pass.
6028 13:30:00.138113
6029 13:30:00.138413 CH 1, Rank 1
6030 13:30:00.141195 SW Impedance : PASS
6031 13:30:00.141698 DUTY Scan : NO K
6032 13:30:00.144391 ZQ Calibration : PASS
6033 13:30:00.147437 Jitter Meter : NO K
6034 13:30:00.147893 CBT Training : PASS
6035 13:30:00.150657 Write leveling : PASS
6036 13:30:00.154419 RX DQS gating : PASS
6037 13:30:00.154921 RX DQ/DQS(RDDQC) : PASS
6038 13:30:00.157689 TX DQ/DQS : PASS
6039 13:30:00.160939 RX DATLAT : PASS
6040 13:30:00.161509 RX DQ/DQS(Engine): PASS
6041 13:30:00.163901 TX OE : NO K
6042 13:30:00.164357 All Pass.
6043 13:30:00.164818
6044 13:30:00.167449 DramC Write-DBI off
6045 13:30:00.170998 PER_BANK_REFRESH: Hybrid Mode
6046 13:30:00.171507 TX_TRACKING: ON
6047 13:30:00.180459 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6048 13:30:00.183556 [FAST_K] Save calibration result to emmc
6049 13:30:00.187278 dramc_set_vcore_voltage set vcore to 650000
6050 13:30:00.190315 Read voltage for 400, 6
6051 13:30:00.190731 Vio18 = 0
6052 13:30:00.191053 Vcore = 650000
6053 13:30:00.193557 Vdram = 0
6054 13:30:00.193953 Vddq = 0
6055 13:30:00.194289 Vmddr = 0
6056 13:30:00.200346 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6057 13:30:00.204159 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6058 13:30:00.207040 MEM_TYPE=3, freq_sel=20
6059 13:30:00.210357 sv_algorithm_assistance_LP4_800
6060 13:30:00.213817 ============ PULL DRAM RESETB DOWN ============
6061 13:30:00.220488 ========== PULL DRAM RESETB DOWN end =========
6062 13:30:00.223643 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6063 13:30:00.226952 ===================================
6064 13:30:00.230102 LPDDR4 DRAM CONFIGURATION
6065 13:30:00.233950 ===================================
6066 13:30:00.234689 EX_ROW_EN[0] = 0x0
6067 13:30:00.237047 EX_ROW_EN[1] = 0x0
6068 13:30:00.237732 LP4Y_EN = 0x0
6069 13:30:00.239748 WORK_FSP = 0x0
6070 13:30:00.240277 WL = 0x2
6071 13:30:00.243398 RL = 0x2
6072 13:30:00.243943 BL = 0x2
6073 13:30:00.246836 RPST = 0x0
6074 13:30:00.247261 RD_PRE = 0x0
6075 13:30:00.249602 WR_PRE = 0x1
6076 13:30:00.253402 WR_PST = 0x0
6077 13:30:00.254012 DBI_WR = 0x0
6078 13:30:00.256636 DBI_RD = 0x0
6079 13:30:00.257322 OTF = 0x1
6080 13:30:00.259866 ===================================
6081 13:30:00.263137 ===================================
6082 13:30:00.266268 ANA top config
6083 13:30:00.266659 ===================================
6084 13:30:00.270087 DLL_ASYNC_EN = 0
6085 13:30:00.273181 ALL_SLAVE_EN = 1
6086 13:30:00.276413 NEW_RANK_MODE = 1
6087 13:30:00.279304 DLL_IDLE_MODE = 1
6088 13:30:00.279772 LP45_APHY_COMB_EN = 1
6089 13:30:00.282930 TX_ODT_DIS = 1
6090 13:30:00.286173 NEW_8X_MODE = 1
6091 13:30:00.289620 ===================================
6092 13:30:00.292682 ===================================
6093 13:30:00.296405 data_rate = 800
6094 13:30:00.299655 CKR = 1
6095 13:30:00.302863 DQ_P2S_RATIO = 4
6096 13:30:00.306000 ===================================
6097 13:30:00.306454 CA_P2S_RATIO = 4
6098 13:30:00.308992 DQ_CA_OPEN = 0
6099 13:30:00.312737 DQ_SEMI_OPEN = 1
6100 13:30:00.315822 CA_SEMI_OPEN = 1
6101 13:30:00.319369 CA_FULL_RATE = 0
6102 13:30:00.322630 DQ_CKDIV4_EN = 0
6103 13:30:00.323012 CA_CKDIV4_EN = 1
6104 13:30:00.325916 CA_PREDIV_EN = 0
6105 13:30:00.328732 PH8_DLY = 0
6106 13:30:00.332547 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6107 13:30:00.335734 DQ_AAMCK_DIV = 0
6108 13:30:00.338911 CA_AAMCK_DIV = 0
6109 13:30:00.339335 CA_ADMCK_DIV = 4
6110 13:30:00.342127 DQ_TRACK_CA_EN = 0
6111 13:30:00.345765 CA_PICK = 800
6112 13:30:00.348655 CA_MCKIO = 400
6113 13:30:00.351958 MCKIO_SEMI = 400
6114 13:30:00.355625 PLL_FREQ = 3016
6115 13:30:00.358895 DQ_UI_PI_RATIO = 32
6116 13:30:00.361571 CA_UI_PI_RATIO = 32
6117 13:30:00.364903 ===================================
6118 13:30:00.368627 ===================================
6119 13:30:00.369130 memory_type:LPDDR4
6120 13:30:00.371802 GP_NUM : 10
6121 13:30:00.374980 SRAM_EN : 1
6122 13:30:00.375360 MD32_EN : 0
6123 13:30:00.378785 ===================================
6124 13:30:00.382071 [ANA_INIT] >>>>>>>>>>>>>>
6125 13:30:00.385047 <<<<<< [CONFIGURE PHASE]: ANA_TX
6126 13:30:00.388479 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6127 13:30:00.391403 ===================================
6128 13:30:00.395159 data_rate = 800,PCW = 0X7400
6129 13:30:00.398365 ===================================
6130 13:30:00.401500 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6131 13:30:00.404716 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6132 13:30:00.417959 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6133 13:30:00.421266 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6134 13:30:00.424350 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6135 13:30:00.427618 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6136 13:30:00.431117 [ANA_INIT] flow start
6137 13:30:00.434462 [ANA_INIT] PLL >>>>>>>>
6138 13:30:00.434844 [ANA_INIT] PLL <<<<<<<<
6139 13:30:00.437809 [ANA_INIT] MIDPI >>>>>>>>
6140 13:30:00.440582 [ANA_INIT] MIDPI <<<<<<<<
6141 13:30:00.440991 [ANA_INIT] DLL >>>>>>>>
6142 13:30:00.444358 [ANA_INIT] flow end
6143 13:30:00.447622 ============ LP4 DIFF to SE enter ============
6144 13:30:00.450859 ============ LP4 DIFF to SE exit ============
6145 13:30:00.453922 [ANA_INIT] <<<<<<<<<<<<<
6146 13:30:00.457691 [Flow] Enable top DCM control >>>>>
6147 13:30:00.460692 [Flow] Enable top DCM control <<<<<
6148 13:30:00.463940 Enable DLL master slave shuffle
6149 13:30:00.470924 ==============================================================
6150 13:30:00.471327 Gating Mode config
6151 13:30:00.477288 ==============================================================
6152 13:30:00.480556 Config description:
6153 13:30:00.486971 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6154 13:30:00.493827 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6155 13:30:00.500328 SELPH_MODE 0: By rank 1: By Phase
6156 13:30:00.506936 ==============================================================
6157 13:30:00.510211 GAT_TRACK_EN = 0
6158 13:30:00.510598 RX_GATING_MODE = 2
6159 13:30:00.513370 RX_GATING_TRACK_MODE = 2
6160 13:30:00.516319 SELPH_MODE = 1
6161 13:30:00.520313 PICG_EARLY_EN = 1
6162 13:30:00.523322 VALID_LAT_VALUE = 1
6163 13:30:00.529823 ==============================================================
6164 13:30:00.532933 Enter into Gating configuration >>>>
6165 13:30:00.536083 Exit from Gating configuration <<<<
6166 13:30:00.539773 Enter into DVFS_PRE_config >>>>>
6167 13:30:00.549658 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6168 13:30:00.552677 Exit from DVFS_PRE_config <<<<<
6169 13:30:00.555857 Enter into PICG configuration >>>>
6170 13:30:00.559436 Exit from PICG configuration <<<<
6171 13:30:00.562637 [RX_INPUT] configuration >>>>>
6172 13:30:00.565933 [RX_INPUT] configuration <<<<<
6173 13:30:00.569099 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6174 13:30:00.575883 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6175 13:30:00.582160 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6176 13:30:00.588801 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6177 13:30:00.595639 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6178 13:30:00.598634 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6179 13:30:00.605353 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6180 13:30:00.608798 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6181 13:30:00.612050 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6182 13:30:00.618404 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6183 13:30:00.622113 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6184 13:30:00.625194 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6185 13:30:00.628370 ===================================
6186 13:30:00.631608 LPDDR4 DRAM CONFIGURATION
6187 13:30:00.634812 ===================================
6188 13:30:00.635201 EX_ROW_EN[0] = 0x0
6189 13:30:00.638573 EX_ROW_EN[1] = 0x0
6190 13:30:00.638961 LP4Y_EN = 0x0
6191 13:30:00.641739 WORK_FSP = 0x0
6192 13:30:00.644810 WL = 0x2
6193 13:30:00.645244 RL = 0x2
6194 13:30:00.648463 BL = 0x2
6195 13:30:00.648851 RPST = 0x0
6196 13:30:00.651417 RD_PRE = 0x0
6197 13:30:00.651832 WR_PRE = 0x1
6198 13:30:00.654908 WR_PST = 0x0
6199 13:30:00.655296 DBI_WR = 0x0
6200 13:30:00.658380 DBI_RD = 0x0
6201 13:30:00.658763 OTF = 0x1
6202 13:30:00.661171 ===================================
6203 13:30:00.664547 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6204 13:30:00.671220 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6205 13:30:00.674409 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6206 13:30:00.678232 ===================================
6207 13:30:00.681230 LPDDR4 DRAM CONFIGURATION
6208 13:30:00.684307 ===================================
6209 13:30:00.684696 EX_ROW_EN[0] = 0x10
6210 13:30:00.687426 EX_ROW_EN[1] = 0x0
6211 13:30:00.690681 LP4Y_EN = 0x0
6212 13:30:00.691217 WORK_FSP = 0x0
6213 13:30:00.694359 WL = 0x2
6214 13:30:00.694747 RL = 0x2
6215 13:30:00.697691 BL = 0x2
6216 13:30:00.698078 RPST = 0x0
6217 13:30:00.700786 RD_PRE = 0x0
6218 13:30:00.701444 WR_PRE = 0x1
6219 13:30:00.703754 WR_PST = 0x0
6220 13:30:00.704208 DBI_WR = 0x0
6221 13:30:00.707295 DBI_RD = 0x0
6222 13:30:00.707749 OTF = 0x1
6223 13:30:00.710820 ===================================
6224 13:30:00.717581 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6225 13:30:00.721780 nWR fixed to 30
6226 13:30:00.725011 [ModeRegInit_LP4] CH0 RK0
6227 13:30:00.725556 [ModeRegInit_LP4] CH0 RK1
6228 13:30:00.728156 [ModeRegInit_LP4] CH1 RK0
6229 13:30:00.731398 [ModeRegInit_LP4] CH1 RK1
6230 13:30:00.731790 match AC timing 19
6231 13:30:00.738384 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6232 13:30:00.741982 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6233 13:30:00.744984 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6234 13:30:00.751397 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6235 13:30:00.754696 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6236 13:30:00.755095 ==
6237 13:30:00.757772 Dram Type= 6, Freq= 0, CH_0, rank 0
6238 13:30:00.761344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6239 13:30:00.761731 ==
6240 13:30:00.767948 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6241 13:30:00.774607 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6242 13:30:00.777674 [CA 0] Center 36 (8~64) winsize 57
6243 13:30:00.780888 [CA 1] Center 36 (8~64) winsize 57
6244 13:30:00.784737 [CA 2] Center 36 (8~64) winsize 57
6245 13:30:00.787733 [CA 3] Center 36 (8~64) winsize 57
6246 13:30:00.790866 [CA 4] Center 36 (8~64) winsize 57
6247 13:30:00.793998 [CA 5] Center 36 (8~64) winsize 57
6248 13:30:00.794383
6249 13:30:00.797234 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6250 13:30:00.797622
6251 13:30:00.800972 [CATrainingPosCal] consider 1 rank data
6252 13:30:00.804238 u2DelayCellTimex100 = 270/100 ps
6253 13:30:00.807459 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 13:30:00.810669 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 13:30:00.813888 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 13:30:00.817035 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 13:30:00.820694 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 13:30:00.823504 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 13:30:00.823925
6260 13:30:00.830258 CA PerBit enable=1, Macro0, CA PI delay=36
6261 13:30:00.830661
6262 13:30:00.830962 [CBTSetCACLKResult] CA Dly = 36
6263 13:30:00.833867 CS Dly: 1 (0~32)
6264 13:30:00.834252 ==
6265 13:30:00.836696 Dram Type= 6, Freq= 0, CH_0, rank 1
6266 13:30:00.840190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6267 13:30:00.840596 ==
6268 13:30:00.846698 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6269 13:30:00.853472 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6270 13:30:00.856578 [CA 0] Center 36 (8~64) winsize 57
6271 13:30:00.860133 [CA 1] Center 36 (8~64) winsize 57
6272 13:30:00.863333 [CA 2] Center 36 (8~64) winsize 57
6273 13:30:00.866804 [CA 3] Center 36 (8~64) winsize 57
6274 13:30:00.867192 [CA 4] Center 36 (8~64) winsize 57
6275 13:30:00.869685 [CA 5] Center 36 (8~64) winsize 57
6276 13:30:00.870074
6277 13:30:00.876782 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6278 13:30:00.877335
6279 13:30:00.879779 [CATrainingPosCal] consider 2 rank data
6280 13:30:00.883482 u2DelayCellTimex100 = 270/100 ps
6281 13:30:00.886704 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 13:30:00.889741 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 13:30:00.892893 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 13:30:00.896695 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 13:30:00.899852 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 13:30:00.903072 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 13:30:00.903459
6288 13:30:00.906234 CA PerBit enable=1, Macro0, CA PI delay=36
6289 13:30:00.906620
6290 13:30:00.910010 [CBTSetCACLKResult] CA Dly = 36
6291 13:30:00.913203 CS Dly: 1 (0~32)
6292 13:30:00.913593
6293 13:30:00.916293 ----->DramcWriteLeveling(PI) begin...
6294 13:30:00.916685 ==
6295 13:30:00.919547 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 13:30:00.922805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 13:30:00.923195 ==
6298 13:30:00.925948 Write leveling (Byte 0): 40 => 8
6299 13:30:00.929566 Write leveling (Byte 1): 40 => 8
6300 13:30:00.932474 DramcWriteLeveling(PI) end<-----
6301 13:30:00.932861
6302 13:30:00.933191 ==
6303 13:30:00.935782 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 13:30:00.938964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 13:30:00.939354 ==
6306 13:30:00.942628 [Gating] SW mode calibration
6307 13:30:00.948910 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6308 13:30:00.955741 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6309 13:30:00.958877 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6310 13:30:00.965497 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6311 13:30:00.969094 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6312 13:30:00.971878 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6313 13:30:00.979027 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6314 13:30:00.982071 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6315 13:30:00.985099 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6316 13:30:00.991880 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6317 13:30:00.995130 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6318 13:30:00.998349 Total UI for P1: 0, mck2ui 16
6319 13:30:01.001445 best dqsien dly found for B0: ( 0, 14, 24)
6320 13:30:01.004617 Total UI for P1: 0, mck2ui 16
6321 13:30:01.008365 best dqsien dly found for B1: ( 0, 14, 24)
6322 13:30:01.011473 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6323 13:30:01.014705 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6324 13:30:01.015093
6325 13:30:01.017873 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6326 13:30:01.021556 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6327 13:30:01.024769 [Gating] SW calibration Done
6328 13:30:01.025194 ==
6329 13:30:01.027977 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 13:30:01.034542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 13:30:01.034933 ==
6332 13:30:01.035235 RX Vref Scan: 0
6333 13:30:01.035515
6334 13:30:01.037626 RX Vref 0 -> 0, step: 1
6335 13:30:01.038012
6336 13:30:01.040680 RX Delay -410 -> 252, step: 16
6337 13:30:01.044411 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6338 13:30:01.047749 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6339 13:30:01.054270 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6340 13:30:01.057238 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6341 13:30:01.060906 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6342 13:30:01.064098 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6343 13:30:01.070327 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6344 13:30:01.073582 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6345 13:30:01.077185 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6346 13:30:01.080214 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6347 13:30:01.087006 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6348 13:30:01.089922 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6349 13:30:01.093694 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6350 13:30:01.100050 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6351 13:30:01.103434 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6352 13:30:01.106907 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6353 13:30:01.107434 ==
6354 13:30:01.109954 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 13:30:01.113074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 13:30:01.116451 ==
6357 13:30:01.116945 DQS Delay:
6358 13:30:01.117373 DQS0 = 35, DQS1 = 51
6359 13:30:01.120108 DQM Delay:
6360 13:30:01.120580 DQM0 = 4, DQM1 = 9
6361 13:30:01.123368 DQ Delay:
6362 13:30:01.123755 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6363 13:30:01.126459 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6364 13:30:01.129646 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6365 13:30:01.132785 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6366 13:30:01.133209
6367 13:30:01.133519
6368 13:30:01.133795 ==
6369 13:30:01.136555 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 13:30:01.143203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 13:30:01.143711 ==
6372 13:30:01.144149
6373 13:30:01.144561
6374 13:30:01.144965 TX Vref Scan disable
6375 13:30:01.146164 == TX Byte 0 ==
6376 13:30:01.149405 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6377 13:30:01.153068 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6378 13:30:01.156148 == TX Byte 1 ==
6379 13:30:01.159724 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6380 13:30:01.162625 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6381 13:30:01.166028 ==
6382 13:30:01.169199 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 13:30:01.172433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 13:30:01.172600 ==
6385 13:30:01.172730
6386 13:30:01.172851
6387 13:30:01.175535 TX Vref Scan disable
6388 13:30:01.175701 == TX Byte 0 ==
6389 13:30:01.179237 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6390 13:30:01.185323 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6391 13:30:01.185398 == TX Byte 1 ==
6392 13:30:01.188922 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6393 13:30:01.195177 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6394 13:30:01.195252
6395 13:30:01.195310 [DATLAT]
6396 13:30:01.195364 Freq=400, CH0 RK0
6397 13:30:01.195416
6398 13:30:01.198243 DATLAT Default: 0xf
6399 13:30:01.202123 0, 0xFFFF, sum = 0
6400 13:30:01.202201 1, 0xFFFF, sum = 0
6401 13:30:01.205261 2, 0xFFFF, sum = 0
6402 13:30:01.205338 3, 0xFFFF, sum = 0
6403 13:30:01.208422 4, 0xFFFF, sum = 0
6404 13:30:01.208498 5, 0xFFFF, sum = 0
6405 13:30:01.212082 6, 0xFFFF, sum = 0
6406 13:30:01.212159 7, 0xFFFF, sum = 0
6407 13:30:01.215163 8, 0xFFFF, sum = 0
6408 13:30:01.215240 9, 0xFFFF, sum = 0
6409 13:30:01.218212 10, 0xFFFF, sum = 0
6410 13:30:01.218288 11, 0xFFFF, sum = 0
6411 13:30:01.221668 12, 0xFFFF, sum = 0
6412 13:30:01.221743 13, 0x0, sum = 1
6413 13:30:01.224602 14, 0x0, sum = 2
6414 13:30:01.224708 15, 0x0, sum = 3
6415 13:30:01.228260 16, 0x0, sum = 4
6416 13:30:01.228336 best_step = 14
6417 13:30:01.228394
6418 13:30:01.228446 ==
6419 13:30:01.231658 Dram Type= 6, Freq= 0, CH_0, rank 0
6420 13:30:01.238497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 13:30:01.238572 ==
6422 13:30:01.238631 RX Vref Scan: 1
6423 13:30:01.238686
6424 13:30:01.241630 RX Vref 0 -> 0, step: 1
6425 13:30:01.241704
6426 13:30:01.244750 RX Delay -343 -> 252, step: 8
6427 13:30:01.244825
6428 13:30:01.248177 Set Vref, RX VrefLevel [Byte0]: 56
6429 13:30:01.251691 [Byte1]: 49
6430 13:30:01.251767
6431 13:30:01.254769 Final RX Vref Byte 0 = 56 to rank0
6432 13:30:01.258060 Final RX Vref Byte 1 = 49 to rank0
6433 13:30:01.261018 Final RX Vref Byte 0 = 56 to rank1
6434 13:30:01.264828 Final RX Vref Byte 1 = 49 to rank1==
6435 13:30:01.267860 Dram Type= 6, Freq= 0, CH_0, rank 0
6436 13:30:01.274449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 13:30:01.274524 ==
6438 13:30:01.274582 DQS Delay:
6439 13:30:01.277432 DQS0 = 44, DQS1 = 56
6440 13:30:01.277506 DQM Delay:
6441 13:30:01.277564 DQM0 = 11, DQM1 = 13
6442 13:30:01.281348 DQ Delay:
6443 13:30:01.284442 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6444 13:30:01.287408 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6445 13:30:01.287483 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6446 13:30:01.291085 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6447 13:30:01.294174
6448 13:30:01.294248
6449 13:30:01.300985 [DQSOSCAuto] RK0, (LSB)MR18= 0x9085, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
6450 13:30:01.304200 CH0 RK0: MR19=C0C, MR18=9085
6451 13:30:01.310545 CH0_RK0: MR19=0xC0C, MR18=0x9085, DQSOSC=391, MR23=63, INC=386, DEC=257
6452 13:30:01.310620 ==
6453 13:30:01.314096 Dram Type= 6, Freq= 0, CH_0, rank 1
6454 13:30:01.317373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 13:30:01.317474 ==
6456 13:30:01.320634 [Gating] SW mode calibration
6457 13:30:01.326936 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6458 13:30:01.333440 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6459 13:30:01.336962 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6460 13:30:01.340489 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6461 13:30:01.346743 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6462 13:30:01.350178 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6463 13:30:01.353103 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6464 13:30:01.359944 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6465 13:30:01.363215 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6466 13:30:01.366732 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6467 13:30:01.373060 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6468 13:30:01.376616 Total UI for P1: 0, mck2ui 16
6469 13:30:01.379777 best dqsien dly found for B0: ( 0, 14, 24)
6470 13:30:01.382899 Total UI for P1: 0, mck2ui 16
6471 13:30:01.386839 best dqsien dly found for B1: ( 0, 14, 24)
6472 13:30:01.390014 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6473 13:30:01.393079 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6474 13:30:01.393487
6475 13:30:01.396148 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6476 13:30:01.399693 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6477 13:30:01.402857 [Gating] SW calibration Done
6478 13:30:01.403235 ==
6479 13:30:01.406592 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 13:30:01.409799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 13:30:01.410179 ==
6482 13:30:01.412883 RX Vref Scan: 0
6483 13:30:01.413297
6484 13:30:01.416074 RX Vref 0 -> 0, step: 1
6485 13:30:01.416452
6486 13:30:01.416745 RX Delay -410 -> 252, step: 16
6487 13:30:01.423100 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6488 13:30:01.426211 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6489 13:30:01.429892 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6490 13:30:01.433205 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6491 13:30:01.439341 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6492 13:30:01.442682 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6493 13:30:01.446518 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6494 13:30:01.452913 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6495 13:30:01.455786 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6496 13:30:01.458916 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6497 13:30:01.462629 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6498 13:30:01.469295 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6499 13:30:01.472633 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6500 13:30:01.475490 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6501 13:30:01.478923 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6502 13:30:01.485608 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6503 13:30:01.486020 ==
6504 13:30:01.489186 Dram Type= 6, Freq= 0, CH_0, rank 1
6505 13:30:01.491997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6506 13:30:01.492462 ==
6507 13:30:01.495713 DQS Delay:
6508 13:30:01.496136 DQS0 = 35, DQS1 = 59
6509 13:30:01.496714 DQM Delay:
6510 13:30:01.498801 DQM0 = 5, DQM1 = 17
6511 13:30:01.499249 DQ Delay:
6512 13:30:01.501878 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6513 13:30:01.505667 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6514 13:30:01.508808 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6515 13:30:01.512045 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6516 13:30:01.512655
6517 13:30:01.513169
6518 13:30:01.513599 ==
6519 13:30:01.515149 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 13:30:01.518320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 13:30:01.518702 ==
6522 13:30:01.521580
6523 13:30:01.521975
6524 13:30:01.522270 TX Vref Scan disable
6525 13:30:01.524732 == TX Byte 0 ==
6526 13:30:01.528386 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6527 13:30:01.531610 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6528 13:30:01.534722 == TX Byte 1 ==
6529 13:30:01.537848 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6530 13:30:01.541622 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6531 13:30:01.542136 ==
6532 13:30:01.544494 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 13:30:01.550863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 13:30:01.551212 ==
6535 13:30:01.551525
6536 13:30:01.551799
6537 13:30:01.552069 TX Vref Scan disable
6538 13:30:01.554671 == TX Byte 0 ==
6539 13:30:01.557419 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6540 13:30:01.561058 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6541 13:30:01.564078 == TX Byte 1 ==
6542 13:30:01.567677 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6543 13:30:01.570395 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6544 13:30:01.570815
6545 13:30:01.574097 [DATLAT]
6546 13:30:01.574521 Freq=400, CH0 RK1
6547 13:30:01.574827
6548 13:30:01.577436 DATLAT Default: 0xe
6549 13:30:01.577820 0, 0xFFFF, sum = 0
6550 13:30:01.580411 1, 0xFFFF, sum = 0
6551 13:30:01.580774 2, 0xFFFF, sum = 0
6552 13:30:01.584273 3, 0xFFFF, sum = 0
6553 13:30:01.584852 4, 0xFFFF, sum = 0
6554 13:30:01.587089 5, 0xFFFF, sum = 0
6555 13:30:01.587533 6, 0xFFFF, sum = 0
6556 13:30:01.590571 7, 0xFFFF, sum = 0
6557 13:30:01.593940 8, 0xFFFF, sum = 0
6558 13:30:01.594370 9, 0xFFFF, sum = 0
6559 13:30:01.596840 10, 0xFFFF, sum = 0
6560 13:30:01.597311 11, 0xFFFF, sum = 0
6561 13:30:01.600009 12, 0xFFFF, sum = 0
6562 13:30:01.600435 13, 0x0, sum = 1
6563 13:30:01.603629 14, 0x0, sum = 2
6564 13:30:01.604077 15, 0x0, sum = 3
6565 13:30:01.606922 16, 0x0, sum = 4
6566 13:30:01.607359 best_step = 14
6567 13:30:01.607754
6568 13:30:01.608136 ==
6569 13:30:01.610235 Dram Type= 6, Freq= 0, CH_0, rank 1
6570 13:30:01.613277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 13:30:01.613707 ==
6572 13:30:01.616923 RX Vref Scan: 0
6573 13:30:01.617443
6574 13:30:01.619999 RX Vref 0 -> 0, step: 1
6575 13:30:01.620410
6576 13:30:01.620825 RX Delay -359 -> 252, step: 8
6577 13:30:01.629230 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6578 13:30:01.632497 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6579 13:30:01.635608 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6580 13:30:01.642516 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6581 13:30:01.645882 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6582 13:30:01.648733 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6583 13:30:01.651831 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6584 13:30:01.658331 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6585 13:30:01.661994 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6586 13:30:01.664904 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6587 13:30:01.668483 iDelay=217, Bit 10, Center -40 (-279 ~ 200) 480
6588 13:30:01.674698 iDelay=217, Bit 11, Center -52 (-287 ~ 184) 472
6589 13:30:01.678110 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6590 13:30:01.681832 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6591 13:30:01.684930 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6592 13:30:01.691402 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6593 13:30:01.691783 ==
6594 13:30:01.694986 Dram Type= 6, Freq= 0, CH_0, rank 1
6595 13:30:01.698111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6596 13:30:01.698684 ==
6597 13:30:01.701213 DQS Delay:
6598 13:30:01.701670 DQS0 = 48, DQS1 = 60
6599 13:30:01.702084 DQM Delay:
6600 13:30:01.704397 DQM0 = 13, DQM1 = 15
6601 13:30:01.704996 DQ Delay:
6602 13:30:01.708097 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6603 13:30:01.711491 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =20
6604 13:30:01.714549 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6605 13:30:01.718042 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =20
6606 13:30:01.718538
6607 13:30:01.718966
6608 13:30:01.727337 [DQSOSCAuto] RK1, (LSB)MR18= 0x8a83, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6609 13:30:01.727846 CH0 RK1: MR19=C0C, MR18=8A83
6610 13:30:01.734122 CH0_RK1: MR19=0xC0C, MR18=0x8A83, DQSOSC=392, MR23=63, INC=384, DEC=256
6611 13:30:01.737467 [RxdqsGatingPostProcess] freq 400
6612 13:30:01.743857 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6613 13:30:01.747084 best DQS0 dly(2T, 0.5T) = (0, 10)
6614 13:30:01.750825 best DQS1 dly(2T, 0.5T) = (0, 10)
6615 13:30:01.753779 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6616 13:30:01.757017 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6617 13:30:01.760349 best DQS0 dly(2T, 0.5T) = (0, 10)
6618 13:30:01.764025 best DQS1 dly(2T, 0.5T) = (0, 10)
6619 13:30:01.767193 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6620 13:30:01.770181 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6621 13:30:01.773819 Pre-setting of DQS Precalculation
6622 13:30:01.776767 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6623 13:30:01.777189 ==
6624 13:30:01.780733 Dram Type= 6, Freq= 0, CH_1, rank 0
6625 13:30:01.783669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6626 13:30:01.784050 ==
6627 13:30:01.790297 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6628 13:30:01.797063 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6629 13:30:01.800294 [CA 0] Center 36 (8~64) winsize 57
6630 13:30:01.803351 [CA 1] Center 36 (8~64) winsize 57
6631 13:30:01.807065 [CA 2] Center 36 (8~64) winsize 57
6632 13:30:01.810076 [CA 3] Center 36 (8~64) winsize 57
6633 13:30:01.813126 [CA 4] Center 36 (8~64) winsize 57
6634 13:30:01.813545 [CA 5] Center 36 (8~64) winsize 57
6635 13:30:01.816907
6636 13:30:01.819723 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6637 13:30:01.820104
6638 13:30:01.823493 [CATrainingPosCal] consider 1 rank data
6639 13:30:01.826753 u2DelayCellTimex100 = 270/100 ps
6640 13:30:01.829721 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 13:30:01.832983 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 13:30:01.836374 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 13:30:01.839758 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 13:30:01.843148 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 13:30:01.846259 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 13:30:01.846641
6647 13:30:01.849385 CA PerBit enable=1, Macro0, CA PI delay=36
6648 13:30:01.852856
6649 13:30:01.853284 [CBTSetCACLKResult] CA Dly = 36
6650 13:30:01.856309 CS Dly: 1 (0~32)
6651 13:30:01.856691 ==
6652 13:30:01.859435 Dram Type= 6, Freq= 0, CH_1, rank 1
6653 13:30:01.862706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6654 13:30:01.863093 ==
6655 13:30:01.869548 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6656 13:30:01.875639 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6657 13:30:01.879233 [CA 0] Center 36 (8~64) winsize 57
6658 13:30:01.882382 [CA 1] Center 36 (8~64) winsize 57
6659 13:30:01.886026 [CA 2] Center 36 (8~64) winsize 57
6660 13:30:01.889243 [CA 3] Center 36 (8~64) winsize 57
6661 13:30:01.889670 [CA 4] Center 36 (8~64) winsize 57
6662 13:30:01.892269 [CA 5] Center 36 (8~64) winsize 57
6663 13:30:01.892755
6664 13:30:01.899336 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6665 13:30:01.899719
6666 13:30:01.902394 [CATrainingPosCal] consider 2 rank data
6667 13:30:01.905397 u2DelayCellTimex100 = 270/100 ps
6668 13:30:01.908991 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 13:30:01.912199 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 13:30:01.915394 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 13:30:01.918651 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 13:30:01.921801 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 13:30:01.925213 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 13:30:01.925600
6675 13:30:01.928590 CA PerBit enable=1, Macro0, CA PI delay=36
6676 13:30:01.928972
6677 13:30:01.931800 [CBTSetCACLKResult] CA Dly = 36
6678 13:30:01.934938 CS Dly: 1 (0~32)
6679 13:30:01.935573
6680 13:30:01.938161 ----->DramcWriteLeveling(PI) begin...
6681 13:30:01.938549 ==
6682 13:30:01.941387 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 13:30:01.944922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 13:30:01.945360 ==
6685 13:30:01.947896 Write leveling (Byte 0): 40 => 8
6686 13:30:01.951679 Write leveling (Byte 1): 40 => 8
6687 13:30:01.954669 DramcWriteLeveling(PI) end<-----
6688 13:30:01.955098
6689 13:30:01.955424 ==
6690 13:30:01.958084 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 13:30:01.961026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 13:30:01.964445 ==
6693 13:30:01.964884 [Gating] SW mode calibration
6694 13:30:01.974061 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6695 13:30:01.977386 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6696 13:30:01.981090 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6697 13:30:01.987917 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6698 13:30:01.991110 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6699 13:30:01.994344 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6700 13:30:02.000516 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6701 13:30:02.004106 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6702 13:30:02.007601 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6703 13:30:02.013679 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6704 13:30:02.017450 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6705 13:30:02.020746 Total UI for P1: 0, mck2ui 16
6706 13:30:02.023840 best dqsien dly found for B0: ( 0, 14, 24)
6707 13:30:02.027038 Total UI for P1: 0, mck2ui 16
6708 13:30:02.030146 best dqsien dly found for B1: ( 0, 14, 24)
6709 13:30:02.033788 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6710 13:30:02.036643 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6711 13:30:02.037026
6712 13:30:02.040389 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6713 13:30:02.046688 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6714 13:30:02.047112 [Gating] SW calibration Done
6715 13:30:02.047485 ==
6716 13:30:02.050255 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 13:30:02.056496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 13:30:02.056931 ==
6719 13:30:02.057398 RX Vref Scan: 0
6720 13:30:02.057693
6721 13:30:02.060159 RX Vref 0 -> 0, step: 1
6722 13:30:02.060547
6723 13:30:02.063299 RX Delay -410 -> 252, step: 16
6724 13:30:02.066532 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6725 13:30:02.070264 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6726 13:30:02.076967 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6727 13:30:02.080134 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6728 13:30:02.083195 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6729 13:30:02.086480 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6730 13:30:02.093079 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6731 13:30:02.095916 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6732 13:30:02.099368 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6733 13:30:02.102560 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6734 13:30:02.109276 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6735 13:30:02.112684 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6736 13:30:02.115704 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6737 13:30:02.122605 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6738 13:30:02.125830 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6739 13:30:02.129106 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6740 13:30:02.129527 ==
6741 13:30:02.132122 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 13:30:02.138595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 13:30:02.138978 ==
6744 13:30:02.139287 DQS Delay:
6745 13:30:02.142075 DQS0 = 35, DQS1 = 51
6746 13:30:02.142456 DQM Delay:
6747 13:30:02.142754 DQM0 = 6, DQM1 = 13
6748 13:30:02.145505 DQ Delay:
6749 13:30:02.148599 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6750 13:30:02.148982 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6751 13:30:02.151671 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6752 13:30:02.155240 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6753 13:30:02.155620
6754 13:30:02.158394
6755 13:30:02.158773 ==
6756 13:30:02.161641 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 13:30:02.165204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 13:30:02.165588 ==
6759 13:30:02.165888
6760 13:30:02.166159
6761 13:30:02.168436 TX Vref Scan disable
6762 13:30:02.168819 == TX Byte 0 ==
6763 13:30:02.171611 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6764 13:30:02.178087 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6765 13:30:02.178470 == TX Byte 1 ==
6766 13:30:02.181870 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6767 13:30:02.188130 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6768 13:30:02.188539 ==
6769 13:30:02.191191 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 13:30:02.194715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 13:30:02.195128 ==
6772 13:30:02.195431
6773 13:30:02.195705
6774 13:30:02.197848 TX Vref Scan disable
6775 13:30:02.198227 == TX Byte 0 ==
6776 13:30:02.204576 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6777 13:30:02.207770 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6778 13:30:02.208272 == TX Byte 1 ==
6779 13:30:02.214722 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6780 13:30:02.217665 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6781 13:30:02.218056
6782 13:30:02.218351 [DATLAT]
6783 13:30:02.221078 Freq=400, CH1 RK0
6784 13:30:02.221501
6785 13:30:02.221800 DATLAT Default: 0xf
6786 13:30:02.224414 0, 0xFFFF, sum = 0
6787 13:30:02.224805 1, 0xFFFF, sum = 0
6788 13:30:02.227413 2, 0xFFFF, sum = 0
6789 13:30:02.227800 3, 0xFFFF, sum = 0
6790 13:30:02.231318 4, 0xFFFF, sum = 0
6791 13:30:02.231706 5, 0xFFFF, sum = 0
6792 13:30:02.234382 6, 0xFFFF, sum = 0
6793 13:30:02.234766 7, 0xFFFF, sum = 0
6794 13:30:02.237419 8, 0xFFFF, sum = 0
6795 13:30:02.237896 9, 0xFFFF, sum = 0
6796 13:30:02.240697 10, 0xFFFF, sum = 0
6797 13:30:02.243789 11, 0xFFFF, sum = 0
6798 13:30:02.244176 12, 0xFFFF, sum = 0
6799 13:30:02.247790 13, 0x0, sum = 1
6800 13:30:02.248181 14, 0x0, sum = 2
6801 13:30:02.250496 15, 0x0, sum = 3
6802 13:30:02.250885 16, 0x0, sum = 4
6803 13:30:02.251189 best_step = 14
6804 13:30:02.251462
6805 13:30:02.253940 ==
6806 13:30:02.257506 Dram Type= 6, Freq= 0, CH_1, rank 0
6807 13:30:02.260376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 13:30:02.260776 ==
6809 13:30:02.261077 RX Vref Scan: 1
6810 13:30:02.261413
6811 13:30:02.264033 RX Vref 0 -> 0, step: 1
6812 13:30:02.264416
6813 13:30:02.267195 RX Delay -343 -> 252, step: 8
6814 13:30:02.267579
6815 13:30:02.270107 Set Vref, RX VrefLevel [Byte0]: 52
6816 13:30:02.273215 [Byte1]: 51
6817 13:30:02.277649
6818 13:30:02.278031 Final RX Vref Byte 0 = 52 to rank0
6819 13:30:02.280727 Final RX Vref Byte 1 = 51 to rank0
6820 13:30:02.283925 Final RX Vref Byte 0 = 52 to rank1
6821 13:30:02.287035 Final RX Vref Byte 1 = 51 to rank1==
6822 13:30:02.290809 Dram Type= 6, Freq= 0, CH_1, rank 0
6823 13:30:02.296978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 13:30:02.297442 ==
6825 13:30:02.297745 DQS Delay:
6826 13:30:02.300599 DQS0 = 44, DQS1 = 56
6827 13:30:02.300976 DQM Delay:
6828 13:30:02.301323 DQM0 = 10, DQM1 = 13
6829 13:30:02.303794 DQ Delay:
6830 13:30:02.306957 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6831 13:30:02.310209 DQ4 =4, DQ5 =20, DQ6 =20, DQ7 =4
6832 13:30:02.310598 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6833 13:30:02.316888 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6834 13:30:02.317316
6835 13:30:02.317626
6836 13:30:02.323251 [DQSOSCAuto] RK0, (LSB)MR18= 0x6b92, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6837 13:30:02.326970 CH1 RK0: MR19=C0C, MR18=6B92
6838 13:30:02.333243 CH1_RK0: MR19=0xC0C, MR18=0x6B92, DQSOSC=391, MR23=63, INC=386, DEC=257
6839 13:30:02.333637 ==
6840 13:30:02.336612 Dram Type= 6, Freq= 0, CH_1, rank 1
6841 13:30:02.339805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 13:30:02.340200 ==
6843 13:30:02.343281 [Gating] SW mode calibration
6844 13:30:02.349935 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6845 13:30:02.356184 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6846 13:30:02.359645 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6847 13:30:02.363033 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6848 13:30:02.369460 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6849 13:30:02.373134 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6850 13:30:02.376173 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6851 13:30:02.383141 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6852 13:30:02.386391 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6853 13:30:02.389490 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6854 13:30:02.395822 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6855 13:30:02.396206 Total UI for P1: 0, mck2ui 16
6856 13:30:02.402906 best dqsien dly found for B0: ( 0, 14, 24)
6857 13:30:02.403291 Total UI for P1: 0, mck2ui 16
6858 13:30:02.409199 best dqsien dly found for B1: ( 0, 14, 24)
6859 13:30:02.412257 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6860 13:30:02.416217 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6861 13:30:02.416378
6862 13:30:02.418904 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6863 13:30:02.422053 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6864 13:30:02.425273 [Gating] SW calibration Done
6865 13:30:02.425348 ==
6866 13:30:02.428438 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 13:30:02.431991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 13:30:02.432065 ==
6869 13:30:02.435125 RX Vref Scan: 0
6870 13:30:02.435199
6871 13:30:02.438756 RX Vref 0 -> 0, step: 1
6872 13:30:02.438830
6873 13:30:02.438888 RX Delay -410 -> 252, step: 16
6874 13:30:02.445412 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6875 13:30:02.448379 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6876 13:30:02.451947 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6877 13:30:02.458514 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6878 13:30:02.461828 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6879 13:30:02.464874 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6880 13:30:02.468047 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6881 13:30:02.474900 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6882 13:30:02.478269 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6883 13:30:02.481081 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6884 13:30:02.484644 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6885 13:30:02.491595 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6886 13:30:02.494767 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6887 13:30:02.497887 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6888 13:30:02.501020 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6889 13:30:02.507811 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6890 13:30:02.507887 ==
6891 13:30:02.510978 Dram Type= 6, Freq= 0, CH_1, rank 1
6892 13:30:02.514035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6893 13:30:02.514114 ==
6894 13:30:02.514209 DQS Delay:
6895 13:30:02.517814 DQS0 = 43, DQS1 = 51
6896 13:30:02.517888 DQM Delay:
6897 13:30:02.520982 DQM0 = 10, DQM1 = 13
6898 13:30:02.521081 DQ Delay:
6899 13:30:02.524090 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6900 13:30:02.527431 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6901 13:30:02.530588 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6902 13:30:02.534230 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6903 13:30:02.534305
6904 13:30:02.534364
6905 13:30:02.534417 ==
6906 13:30:02.537146 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 13:30:02.540484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 13:30:02.543617 ==
6909 13:30:02.543692
6910 13:30:02.543750
6911 13:30:02.543803 TX Vref Scan disable
6912 13:30:02.547216 == TX Byte 0 ==
6913 13:30:02.550076 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6914 13:30:02.553874 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6915 13:30:02.556922 == TX Byte 1 ==
6916 13:30:02.560180 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6917 13:30:02.563292 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6918 13:30:02.563368 ==
6919 13:30:02.566861 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 13:30:02.573413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 13:30:02.573490 ==
6922 13:30:02.573548
6923 13:30:02.573602
6924 13:30:02.573654 TX Vref Scan disable
6925 13:30:02.576754 == TX Byte 0 ==
6926 13:30:02.580113 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6927 13:30:02.582966 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6928 13:30:02.586203 == TX Byte 1 ==
6929 13:30:02.589507 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6930 13:30:02.593400 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6931 13:30:02.593475
6932 13:30:02.596013 [DATLAT]
6933 13:30:02.596089 Freq=400, CH1 RK1
6934 13:30:02.596147
6935 13:30:02.599424 DATLAT Default: 0xe
6936 13:30:02.599499 0, 0xFFFF, sum = 0
6937 13:30:02.602962 1, 0xFFFF, sum = 0
6938 13:30:02.603038 2, 0xFFFF, sum = 0
6939 13:30:02.605922 3, 0xFFFF, sum = 0
6940 13:30:02.605998 4, 0xFFFF, sum = 0
6941 13:30:02.609638 5, 0xFFFF, sum = 0
6942 13:30:02.609714 6, 0xFFFF, sum = 0
6943 13:30:02.612754 7, 0xFFFF, sum = 0
6944 13:30:02.615946 8, 0xFFFF, sum = 0
6945 13:30:02.616022 9, 0xFFFF, sum = 0
6946 13:30:02.619086 10, 0xFFFF, sum = 0
6947 13:30:02.619177 11, 0xFFFF, sum = 0
6948 13:30:02.622363 12, 0xFFFF, sum = 0
6949 13:30:02.622473 13, 0x0, sum = 1
6950 13:30:02.625980 14, 0x0, sum = 2
6951 13:30:02.626056 15, 0x0, sum = 3
6952 13:30:02.629275 16, 0x0, sum = 4
6953 13:30:02.629351 best_step = 14
6954 13:30:02.629410
6955 13:30:02.629463 ==
6956 13:30:02.632401 Dram Type= 6, Freq= 0, CH_1, rank 1
6957 13:30:02.635741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6958 13:30:02.635816 ==
6959 13:30:02.638806 RX Vref Scan: 0
6960 13:30:02.638880
6961 13:30:02.642475 RX Vref 0 -> 0, step: 1
6962 13:30:02.642550
6963 13:30:02.642608 RX Delay -343 -> 252, step: 8
6964 13:30:02.651353 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6965 13:30:02.654539 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6966 13:30:02.657953 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6967 13:30:02.664667 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6968 13:30:02.667928 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6969 13:30:02.670994 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6970 13:30:02.674155 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6971 13:30:02.680829 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6972 13:30:02.684354 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6973 13:30:02.687276 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6974 13:30:02.690970 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6975 13:30:02.697204 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6976 13:30:02.700805 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6977 13:30:02.704247 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6978 13:30:02.707116 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6979 13:30:02.713700 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6980 13:30:02.713776 ==
6981 13:30:02.716938 Dram Type= 6, Freq= 0, CH_1, rank 1
6982 13:30:02.720133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6983 13:30:02.720245 ==
6984 13:30:02.720329 DQS Delay:
6985 13:30:02.723869 DQS0 = 48, DQS1 = 52
6986 13:30:02.723942 DQM Delay:
6987 13:30:02.726969 DQM0 = 12, DQM1 = 11
6988 13:30:02.727044 DQ Delay:
6989 13:30:02.730693 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6990 13:30:02.733764 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6991 13:30:02.736891 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6992 13:30:02.740060 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6993 13:30:02.740135
6994 13:30:02.740192
6995 13:30:02.750120 [DQSOSCAuto] RK1, (LSB)MR18= 0x79b1, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
6996 13:30:02.750226 CH1 RK1: MR19=C0C, MR18=79B1
6997 13:30:02.756444 CH1_RK1: MR19=0xC0C, MR18=0x79B1, DQSOSC=387, MR23=63, INC=394, DEC=262
6998 13:30:02.759756 [RxdqsGatingPostProcess] freq 400
6999 13:30:02.766410 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7000 13:30:02.769960 best DQS0 dly(2T, 0.5T) = (0, 10)
7001 13:30:02.773065 best DQS1 dly(2T, 0.5T) = (0, 10)
7002 13:30:02.776311 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7003 13:30:02.779455 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7004 13:30:02.783106 best DQS0 dly(2T, 0.5T) = (0, 10)
7005 13:30:02.786255 best DQS1 dly(2T, 0.5T) = (0, 10)
7006 13:30:02.789685 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7007 13:30:02.792554 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7008 13:30:02.792629 Pre-setting of DQS Precalculation
7009 13:30:02.799357 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7010 13:30:02.805581 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7011 13:30:02.812579 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7012 13:30:02.812653
7013 13:30:02.812711
7014 13:30:02.815670 [Calibration Summary] 800 Mbps
7015 13:30:02.819328 CH 0, Rank 0
7016 13:30:02.819402 SW Impedance : PASS
7017 13:30:02.822390 DUTY Scan : NO K
7018 13:30:02.825845 ZQ Calibration : PASS
7019 13:30:02.825920 Jitter Meter : NO K
7020 13:30:02.828887 CBT Training : PASS
7021 13:30:02.832213 Write leveling : PASS
7022 13:30:02.832288 RX DQS gating : PASS
7023 13:30:02.835315 RX DQ/DQS(RDDQC) : PASS
7024 13:30:02.838983 TX DQ/DQS : PASS
7025 13:30:02.839058 RX DATLAT : PASS
7026 13:30:02.842085 RX DQ/DQS(Engine): PASS
7027 13:30:02.845229 TX OE : NO K
7028 13:30:02.845304 All Pass.
7029 13:30:02.845362
7030 13:30:02.845416 CH 0, Rank 1
7031 13:30:02.848718 SW Impedance : PASS
7032 13:30:02.851899 DUTY Scan : NO K
7033 13:30:02.851974 ZQ Calibration : PASS
7034 13:30:02.855140 Jitter Meter : NO K
7035 13:30:02.858334 CBT Training : PASS
7036 13:30:02.858408 Write leveling : NO K
7037 13:30:02.861414 RX DQS gating : PASS
7038 13:30:02.861489 RX DQ/DQS(RDDQC) : PASS
7039 13:30:02.865270 TX DQ/DQS : PASS
7040 13:30:02.868408 RX DATLAT : PASS
7041 13:30:02.868482 RX DQ/DQS(Engine): PASS
7042 13:30:02.871309 TX OE : NO K
7043 13:30:02.871385 All Pass.
7044 13:30:02.871443
7045 13:30:02.874909 CH 1, Rank 0
7046 13:30:02.874983 SW Impedance : PASS
7047 13:30:02.878526 DUTY Scan : NO K
7048 13:30:02.881748 ZQ Calibration : PASS
7049 13:30:02.881823 Jitter Meter : NO K
7050 13:30:02.884910 CBT Training : PASS
7051 13:30:02.888107 Write leveling : PASS
7052 13:30:02.888182 RX DQS gating : PASS
7053 13:30:02.891257 RX DQ/DQS(RDDQC) : PASS
7054 13:30:02.894426 TX DQ/DQS : PASS
7055 13:30:02.894501 RX DATLAT : PASS
7056 13:30:02.898173 RX DQ/DQS(Engine): PASS
7057 13:30:02.901050 TX OE : NO K
7058 13:30:02.901187 All Pass.
7059 13:30:02.901248
7060 13:30:02.901303 CH 1, Rank 1
7061 13:30:02.904595 SW Impedance : PASS
7062 13:30:02.907698 DUTY Scan : NO K
7063 13:30:02.907790 ZQ Calibration : PASS
7064 13:30:02.911069 Jitter Meter : NO K
7065 13:30:02.914752 CBT Training : PASS
7066 13:30:02.914827 Write leveling : NO K
7067 13:30:02.917883 RX DQS gating : PASS
7068 13:30:02.921021 RX DQ/DQS(RDDQC) : PASS
7069 13:30:02.921142 TX DQ/DQS : PASS
7070 13:30:02.924139 RX DATLAT : PASS
7071 13:30:02.927887 RX DQ/DQS(Engine): PASS
7072 13:30:02.927963 TX OE : NO K
7073 13:30:02.930966 All Pass.
7074 13:30:02.931041
7075 13:30:02.931099 DramC Write-DBI off
7076 13:30:02.934057 PER_BANK_REFRESH: Hybrid Mode
7077 13:30:02.934132 TX_TRACKING: ON
7078 13:30:02.944294 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7079 13:30:02.947115 [FAST_K] Save calibration result to emmc
7080 13:30:02.950511 dramc_set_vcore_voltage set vcore to 725000
7081 13:30:02.953935 Read voltage for 1600, 0
7082 13:30:02.954046 Vio18 = 0
7083 13:30:02.957054 Vcore = 725000
7084 13:30:02.957186 Vdram = 0
7085 13:30:02.957247 Vddq = 0
7086 13:30:02.960295 Vmddr = 0
7087 13:30:02.963495 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7088 13:30:02.970387 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7089 13:30:02.970463 MEM_TYPE=3, freq_sel=13
7090 13:30:02.973526 sv_algorithm_assistance_LP4_3733
7091 13:30:02.980257 ============ PULL DRAM RESETB DOWN ============
7092 13:30:02.983273 ========== PULL DRAM RESETB DOWN end =========
7093 13:30:02.986902 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7094 13:30:02.990096 ===================================
7095 13:30:02.993275 LPDDR4 DRAM CONFIGURATION
7096 13:30:02.996491 ===================================
7097 13:30:03.000276 EX_ROW_EN[0] = 0x0
7098 13:30:03.000351 EX_ROW_EN[1] = 0x0
7099 13:30:03.003438 LP4Y_EN = 0x0
7100 13:30:03.003513 WORK_FSP = 0x1
7101 13:30:03.006593 WL = 0x5
7102 13:30:03.006668 RL = 0x5
7103 13:30:03.009581 BL = 0x2
7104 13:30:03.009656 RPST = 0x0
7105 13:30:03.013099 RD_PRE = 0x0
7106 13:30:03.013205 WR_PRE = 0x1
7107 13:30:03.016706 WR_PST = 0x1
7108 13:30:03.016780 DBI_WR = 0x0
7109 13:30:03.019555 DBI_RD = 0x0
7110 13:30:03.019630 OTF = 0x1
7111 13:30:03.022890 ===================================
7112 13:30:03.026343 ===================================
7113 13:30:03.029580 ANA top config
7114 13:30:03.033423 ===================================
7115 13:30:03.036494 DLL_ASYNC_EN = 0
7116 13:30:03.036572 ALL_SLAVE_EN = 0
7117 13:30:03.039631 NEW_RANK_MODE = 1
7118 13:30:03.042742 DLL_IDLE_MODE = 1
7119 13:30:03.046453 LP45_APHY_COMB_EN = 1
7120 13:30:03.049530 TX_ODT_DIS = 0
7121 13:30:03.049609 NEW_8X_MODE = 1
7122 13:30:03.053260 ===================================
7123 13:30:03.056138 ===================================
7124 13:30:03.059548 data_rate = 3200
7125 13:30:03.062863 CKR = 1
7126 13:30:03.066285 DQ_P2S_RATIO = 8
7127 13:30:03.069362 ===================================
7128 13:30:03.072454 CA_P2S_RATIO = 8
7129 13:30:03.075674 DQ_CA_OPEN = 0
7130 13:30:03.075749 DQ_SEMI_OPEN = 0
7131 13:30:03.079409 CA_SEMI_OPEN = 0
7132 13:30:03.082628 CA_FULL_RATE = 0
7133 13:30:03.085689 DQ_CKDIV4_EN = 0
7134 13:30:03.089337 CA_CKDIV4_EN = 0
7135 13:30:03.092285 CA_PREDIV_EN = 0
7136 13:30:03.092384 PH8_DLY = 12
7137 13:30:03.095483 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7138 13:30:03.099148 DQ_AAMCK_DIV = 4
7139 13:30:03.102272 CA_AAMCK_DIV = 4
7140 13:30:03.105454 CA_ADMCK_DIV = 4
7141 13:30:03.108612 DQ_TRACK_CA_EN = 0
7142 13:30:03.111844 CA_PICK = 1600
7143 13:30:03.111920 CA_MCKIO = 1600
7144 13:30:03.115007 MCKIO_SEMI = 0
7145 13:30:03.118652 PLL_FREQ = 3068
7146 13:30:03.121812 DQ_UI_PI_RATIO = 32
7147 13:30:03.124990 CA_UI_PI_RATIO = 0
7148 13:30:03.128542 ===================================
7149 13:30:03.132506 ===================================
7150 13:30:03.135327 memory_type:LPDDR4
7151 13:30:03.135402 GP_NUM : 10
7152 13:30:03.138515 SRAM_EN : 1
7153 13:30:03.138590 MD32_EN : 0
7154 13:30:03.141759 ===================================
7155 13:30:03.145114 [ANA_INIT] >>>>>>>>>>>>>>
7156 13:30:03.148315 <<<<<< [CONFIGURE PHASE]: ANA_TX
7157 13:30:03.151496 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7158 13:30:03.155012 ===================================
7159 13:30:03.158224 data_rate = 3200,PCW = 0X7600
7160 13:30:03.161341 ===================================
7161 13:30:03.165088 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7162 13:30:03.171616 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7163 13:30:03.174902 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7164 13:30:03.181426 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7165 13:30:03.184597 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7166 13:30:03.187768 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7167 13:30:03.187862 [ANA_INIT] flow start
7168 13:30:03.191437 [ANA_INIT] PLL >>>>>>>>
7169 13:30:03.194494 [ANA_INIT] PLL <<<<<<<<
7170 13:30:03.198025 [ANA_INIT] MIDPI >>>>>>>>
7171 13:30:03.198122 [ANA_INIT] MIDPI <<<<<<<<
7172 13:30:03.201245 [ANA_INIT] DLL >>>>>>>>
7173 13:30:03.204389 [ANA_INIT] DLL <<<<<<<<
7174 13:30:03.204455 [ANA_INIT] flow end
7175 13:30:03.207526 ============ LP4 DIFF to SE enter ============
7176 13:30:03.214476 ============ LP4 DIFF to SE exit ============
7177 13:30:03.214575 [ANA_INIT] <<<<<<<<<<<<<
7178 13:30:03.217693 [Flow] Enable top DCM control >>>>>
7179 13:30:03.220704 [Flow] Enable top DCM control <<<<<
7180 13:30:03.223872 Enable DLL master slave shuffle
7181 13:30:03.230491 ==============================================================
7182 13:30:03.230587 Gating Mode config
7183 13:30:03.237521 ==============================================================
7184 13:30:03.240685 Config description:
7185 13:30:03.250532 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7186 13:30:03.257246 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7187 13:30:03.260507 SELPH_MODE 0: By rank 1: By Phase
7188 13:30:03.267063 ==============================================================
7189 13:30:03.270348 GAT_TRACK_EN = 1
7190 13:30:03.273441 RX_GATING_MODE = 2
7191 13:30:03.276647 RX_GATING_TRACK_MODE = 2
7192 13:30:03.276720 SELPH_MODE = 1
7193 13:30:03.280193 PICG_EARLY_EN = 1
7194 13:30:03.283807 VALID_LAT_VALUE = 1
7195 13:30:03.290144 ==============================================================
7196 13:30:03.293383 Enter into Gating configuration >>>>
7197 13:30:03.296543 Exit from Gating configuration <<<<
7198 13:30:03.299626 Enter into DVFS_PRE_config >>>>>
7199 13:30:03.309492 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7200 13:30:03.313321 Exit from DVFS_PRE_config <<<<<
7201 13:30:03.316477 Enter into PICG configuration >>>>
7202 13:30:03.319668 Exit from PICG configuration <<<<
7203 13:30:03.322873 [RX_INPUT] configuration >>>>>
7204 13:30:03.326088 [RX_INPUT] configuration <<<<<
7205 13:30:03.329376 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7206 13:30:03.336293 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7207 13:30:03.342501 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7208 13:30:03.349495 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7209 13:30:03.356084 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7210 13:30:03.362667 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7211 13:30:03.365449 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7212 13:30:03.368945 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7213 13:30:03.372413 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7214 13:30:03.378843 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7215 13:30:03.381985 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7216 13:30:03.385803 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7217 13:30:03.388803 ===================================
7218 13:30:03.391997 LPDDR4 DRAM CONFIGURATION
7219 13:30:03.395345 ===================================
7220 13:30:03.395439 EX_ROW_EN[0] = 0x0
7221 13:30:03.398803 EX_ROW_EN[1] = 0x0
7222 13:30:03.401868 LP4Y_EN = 0x0
7223 13:30:03.401936 WORK_FSP = 0x1
7224 13:30:03.405186 WL = 0x5
7225 13:30:03.405269 RL = 0x5
7226 13:30:03.408425 BL = 0x2
7227 13:30:03.408512 RPST = 0x0
7228 13:30:03.411908 RD_PRE = 0x0
7229 13:30:03.412001 WR_PRE = 0x1
7230 13:30:03.415385 WR_PST = 0x1
7231 13:30:03.415474 DBI_WR = 0x0
7232 13:30:03.418553 DBI_RD = 0x0
7233 13:30:03.418619 OTF = 0x1
7234 13:30:03.421711 ===================================
7235 13:30:03.424895 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7236 13:30:03.431787 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7237 13:30:03.434855 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7238 13:30:03.438205 ===================================
7239 13:30:03.441402 LPDDR4 DRAM CONFIGURATION
7240 13:30:03.445256 ===================================
7241 13:30:03.445328 EX_ROW_EN[0] = 0x10
7242 13:30:03.448308 EX_ROW_EN[1] = 0x0
7243 13:30:03.451375 LP4Y_EN = 0x0
7244 13:30:03.451471 WORK_FSP = 0x1
7245 13:30:03.454624 WL = 0x5
7246 13:30:03.454717 RL = 0x5
7247 13:30:03.457895 BL = 0x2
7248 13:30:03.457961 RPST = 0x0
7249 13:30:03.461481 RD_PRE = 0x0
7250 13:30:03.461550 WR_PRE = 0x1
7251 13:30:03.464454 WR_PST = 0x1
7252 13:30:03.464520 DBI_WR = 0x0
7253 13:30:03.468307 DBI_RD = 0x0
7254 13:30:03.468398 OTF = 0x1
7255 13:30:03.471477 ===================================
7256 13:30:03.477876 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7257 13:30:03.477972 ==
7258 13:30:03.480832 Dram Type= 6, Freq= 0, CH_0, rank 0
7259 13:30:03.487613 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7260 13:30:03.487709 ==
7261 13:30:03.487803 [Duty_Offset_Calibration]
7262 13:30:03.490816 B0:2 B1:0 CA:4
7263 13:30:03.490908
7264 13:30:03.493993 [DutyScan_Calibration_Flow] k_type=0
7265 13:30:03.502681
7266 13:30:03.502776 ==CLK 0==
7267 13:30:03.505807 Final CLK duty delay cell = -4
7268 13:30:03.509645 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7269 13:30:03.512592 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7270 13:30:03.515776 [-4] AVG Duty = 4922%(X100)
7271 13:30:03.515868
7272 13:30:03.519097 CH0 CLK Duty spec in!! Max-Min= 218%
7273 13:30:03.522417 [DutyScan_Calibration_Flow] ====Done====
7274 13:30:03.522510
7275 13:30:03.525561 [DutyScan_Calibration_Flow] k_type=1
7276 13:30:03.542904
7277 13:30:03.543001 ==DQS 0 ==
7278 13:30:03.546136 Final DQS duty delay cell = 0
7279 13:30:03.549229 [0] MAX Duty = 5218%(X100), DQS PI = 38
7280 13:30:03.553027 [0] MIN Duty = 5093%(X100), DQS PI = 12
7281 13:30:03.556358 [0] AVG Duty = 5155%(X100)
7282 13:30:03.556423
7283 13:30:03.556478 ==DQS 1 ==
7284 13:30:03.559432 Final DQS duty delay cell = 0
7285 13:30:03.562612 [0] MAX Duty = 5156%(X100), DQS PI = 0
7286 13:30:03.565783 [0] MIN Duty = 4969%(X100), DQS PI = 10
7287 13:30:03.569500 [0] AVG Duty = 5062%(X100)
7288 13:30:03.569586
7289 13:30:03.572609 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7290 13:30:03.572702
7291 13:30:03.575712 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7292 13:30:03.578775 [DutyScan_Calibration_Flow] ====Done====
7293 13:30:03.578866
7294 13:30:03.582496 [DutyScan_Calibration_Flow] k_type=3
7295 13:30:03.600013
7296 13:30:03.600110 ==DQM 0 ==
7297 13:30:03.603125 Final DQM duty delay cell = 0
7298 13:30:03.606780 [0] MAX Duty = 5124%(X100), DQS PI = 22
7299 13:30:03.609925 [0] MIN Duty = 4844%(X100), DQS PI = 56
7300 13:30:03.612949 [0] AVG Duty = 4984%(X100)
7301 13:30:03.613044
7302 13:30:03.613127 ==DQM 1 ==
7303 13:30:03.616282 Final DQM duty delay cell = 0
7304 13:30:03.619431 [0] MAX Duty = 4969%(X100), DQS PI = 0
7305 13:30:03.623216 [0] MIN Duty = 4844%(X100), DQS PI = 10
7306 13:30:03.626349 [0] AVG Duty = 4906%(X100)
7307 13:30:03.626445
7308 13:30:03.629424 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7309 13:30:03.629523
7310 13:30:03.632897 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7311 13:30:03.636371 [DutyScan_Calibration_Flow] ====Done====
7312 13:30:03.636465
7313 13:30:03.639660 [DutyScan_Calibration_Flow] k_type=2
7314 13:30:03.656870
7315 13:30:03.656973 ==DQ 0 ==
7316 13:30:03.660661 Final DQ duty delay cell = 0
7317 13:30:03.663805 [0] MAX Duty = 5124%(X100), DQS PI = 20
7318 13:30:03.666959 [0] MIN Duty = 4969%(X100), DQS PI = 12
7319 13:30:03.670606 [0] AVG Duty = 5046%(X100)
7320 13:30:03.670708
7321 13:30:03.670801 ==DQ 1 ==
7322 13:30:03.673682 Final DQ duty delay cell = 0
7323 13:30:03.676909 [0] MAX Duty = 5187%(X100), DQS PI = 2
7324 13:30:03.680537 [0] MIN Duty = 4907%(X100), DQS PI = 32
7325 13:30:03.680635 [0] AVG Duty = 5047%(X100)
7326 13:30:03.683500
7327 13:30:03.686979 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7328 13:30:03.687073
7329 13:30:03.690081 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7330 13:30:03.693703 [DutyScan_Calibration_Flow] ====Done====
7331 13:30:03.693799 ==
7332 13:30:03.696757 Dram Type= 6, Freq= 0, CH_1, rank 0
7333 13:30:03.699837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7334 13:30:03.699936 ==
7335 13:30:03.703086 [Duty_Offset_Calibration]
7336 13:30:03.703176 B0:0 B1:-1 CA:3
7337 13:30:03.703260
7338 13:30:03.706816 [DutyScan_Calibration_Flow] k_type=0
7339 13:30:03.716500
7340 13:30:03.716572 ==CLK 0==
7341 13:30:03.719731 Final CLK duty delay cell = -4
7342 13:30:03.722993 [-4] MAX Duty = 5062%(X100), DQS PI = 36
7343 13:30:03.726765 [-4] MIN Duty = 4813%(X100), DQS PI = 4
7344 13:30:03.729799 [-4] AVG Duty = 4937%(X100)
7345 13:30:03.729903
7346 13:30:03.732878 CH1 CLK Duty spec in!! Max-Min= 249%
7347 13:30:03.736680 [DutyScan_Calibration_Flow] ====Done====
7348 13:30:03.736754
7349 13:30:03.739837 [DutyScan_Calibration_Flow] k_type=1
7350 13:30:03.755875
7351 13:30:03.755975 ==DQS 0 ==
7352 13:30:03.759035 Final DQS duty delay cell = 0
7353 13:30:03.762310 [0] MAX Duty = 5187%(X100), DQS PI = 60
7354 13:30:03.765603 [0] MIN Duty = 4938%(X100), DQS PI = 8
7355 13:30:03.768839 [0] AVG Duty = 5062%(X100)
7356 13:30:03.768929
7357 13:30:03.769010 ==DQS 1 ==
7358 13:30:03.772631 Final DQS duty delay cell = -4
7359 13:30:03.775487 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7360 13:30:03.779004 [-4] MIN Duty = 4813%(X100), DQS PI = 52
7361 13:30:03.782099 [-4] AVG Duty = 4906%(X100)
7362 13:30:03.782214
7363 13:30:03.785058 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7364 13:30:03.785189
7365 13:30:03.788904 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7366 13:30:03.791686 [DutyScan_Calibration_Flow] ====Done====
7367 13:30:03.791829
7368 13:30:03.795269 [DutyScan_Calibration_Flow] k_type=3
7369 13:30:03.813401
7370 13:30:03.813605 ==DQM 0 ==
7371 13:30:03.816328 Final DQM duty delay cell = 0
7372 13:30:03.819531 [0] MAX Duty = 5000%(X100), DQS PI = 16
7373 13:30:03.823163 [0] MIN Duty = 4782%(X100), DQS PI = 8
7374 13:30:03.826318 [0] AVG Duty = 4891%(X100)
7375 13:30:03.826677
7376 13:30:03.826995 ==DQM 1 ==
7377 13:30:03.829508 Final DQM duty delay cell = 0
7378 13:30:03.833310 [0] MAX Duty = 4969%(X100), DQS PI = 0
7379 13:30:03.836439 [0] MIN Duty = 4813%(X100), DQS PI = 28
7380 13:30:03.839666 [0] AVG Duty = 4891%(X100)
7381 13:30:03.840026
7382 13:30:03.842907 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7383 13:30:03.843273
7384 13:30:03.846004 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7385 13:30:03.849918 [DutyScan_Calibration_Flow] ====Done====
7386 13:30:03.850217
7387 13:30:03.853051 [DutyScan_Calibration_Flow] k_type=2
7388 13:30:03.870087
7389 13:30:03.870508 ==DQ 0 ==
7390 13:30:03.873544 Final DQ duty delay cell = 0
7391 13:30:03.877019 [0] MAX Duty = 5187%(X100), DQS PI = 0
7392 13:30:03.879867 [0] MIN Duty = 5000%(X100), DQS PI = 8
7393 13:30:03.880256 [0] AVG Duty = 5093%(X100)
7394 13:30:03.880570
7395 13:30:03.883313 ==DQ 1 ==
7396 13:30:03.886614 Final DQ duty delay cell = 0
7397 13:30:03.889804 [0] MAX Duty = 5031%(X100), DQS PI = 0
7398 13:30:03.893003 [0] MIN Duty = 4875%(X100), DQS PI = 26
7399 13:30:03.893311 [0] AVG Duty = 4953%(X100)
7400 13:30:03.893528
7401 13:30:03.896429 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7402 13:30:03.899863
7403 13:30:03.902962 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7404 13:30:03.906416 [DutyScan_Calibration_Flow] ====Done====
7405 13:30:03.909494 nWR fixed to 30
7406 13:30:03.909885 [ModeRegInit_LP4] CH0 RK0
7407 13:30:03.912697 [ModeRegInit_LP4] CH0 RK1
7408 13:30:03.916553 [ModeRegInit_LP4] CH1 RK0
7409 13:30:03.919527 [ModeRegInit_LP4] CH1 RK1
7410 13:30:03.919913 match AC timing 5
7411 13:30:03.926186 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7412 13:30:03.929165 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7413 13:30:03.933117 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7414 13:30:03.939298 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7415 13:30:03.942501 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7416 13:30:03.942891 [MiockJmeterHQA]
7417 13:30:03.943187
7418 13:30:03.945886 [DramcMiockJmeter] u1RxGatingPI = 0
7419 13:30:03.949031 0 : 4255, 4026
7420 13:30:03.949473 4 : 4252, 4027
7421 13:30:03.952280 8 : 4252, 4027
7422 13:30:03.952669 12 : 4258, 4026
7423 13:30:03.955472 16 : 4367, 4140
7424 13:30:03.955860 20 : 4252, 4027
7425 13:30:03.956166 24 : 4252, 4027
7426 13:30:03.958548 28 : 4252, 4027
7427 13:30:03.958940 32 : 4252, 4027
7428 13:30:03.962452 36 : 4363, 4137
7429 13:30:03.962844 40 : 4250, 4027
7430 13:30:03.965631 44 : 4253, 4026
7431 13:30:03.966021 48 : 4252, 4027
7432 13:30:03.968831 52 : 4249, 4027
7433 13:30:03.969259 56 : 4250, 4026
7434 13:30:03.969570 60 : 4360, 4138
7435 13:30:03.971831 64 : 4360, 4138
7436 13:30:03.972360 68 : 4252, 4027
7437 13:30:03.974988 72 : 4250, 4027
7438 13:30:03.975379 76 : 4250, 4026
7439 13:30:03.978773 80 : 4250, 4027
7440 13:30:03.979289 84 : 4250, 4027
7441 13:30:03.981965 88 : 4361, 4137
7442 13:30:03.982354 92 : 4250, 4027
7443 13:30:03.982657 96 : 4250, 2483
7444 13:30:03.985092 100 : 4250, 0
7445 13:30:03.985530 104 : 4250, 0
7446 13:30:03.988685 108 : 4250, 0
7447 13:30:03.989073 112 : 4250, 0
7448 13:30:03.989458 116 : 4250, 0
7449 13:30:03.991849 120 : 4249, 0
7450 13:30:03.992438 124 : 4360, 0
7451 13:30:03.995442 128 : 4250, 0
7452 13:30:03.996001 132 : 4250, 0
7453 13:30:03.996528 136 : 4250, 0
7454 13:30:03.998252 140 : 4360, 0
7455 13:30:03.998748 144 : 4361, 0
7456 13:30:04.001872 148 : 4250, 0
7457 13:30:04.002420 152 : 4249, 0
7458 13:30:04.002918 156 : 4250, 0
7459 13:30:04.004989 160 : 4253, 0
7460 13:30:04.005486 164 : 4249, 0
7461 13:30:04.008710 168 : 4250, 0
7462 13:30:04.009273 172 : 4253, 0
7463 13:30:04.009627 176 : 4360, 0
7464 13:30:04.011431 180 : 4250, 0
7465 13:30:04.012003 184 : 4250, 0
7466 13:30:04.012492 188 : 4250, 0
7467 13:30:04.015042 192 : 4360, 0
7468 13:30:04.015580 196 : 4361, 0
7469 13:30:04.018076 200 : 4250, 0
7470 13:30:04.018656 204 : 4249, 0
7471 13:30:04.019160 208 : 4250, 0
7472 13:30:04.021231 212 : 4253, 0
7473 13:30:04.021775 216 : 4249, 0
7474 13:30:04.024710 220 : 4250, 546
7475 13:30:04.025340 224 : 4360, 4121
7476 13:30:04.027936 228 : 4250, 4027
7477 13:30:04.028553 232 : 4361, 4138
7478 13:30:04.031419 236 : 4360, 4137
7479 13:30:04.031947 240 : 4250, 4027
7480 13:30:04.034511 244 : 4250, 4027
7481 13:30:04.035053 248 : 4360, 4137
7482 13:30:04.035542 252 : 4250, 4026
7483 13:30:04.037773 256 : 4250, 4027
7484 13:30:04.038321 260 : 4250, 4027
7485 13:30:04.040926 264 : 4249, 4027
7486 13:30:04.041466 268 : 4250, 4026
7487 13:30:04.044579 272 : 4250, 4027
7488 13:30:04.045079 276 : 4360, 4138
7489 13:30:04.047925 280 : 4250, 4027
7490 13:30:04.048447 284 : 4250, 4026
7491 13:30:04.051080 288 : 4361, 4137
7492 13:30:04.051624 292 : 4250, 4027
7493 13:30:04.054169 296 : 4250, 4027
7494 13:30:04.054707 300 : 4360, 4137
7495 13:30:04.057394 304 : 4250, 4026
7496 13:30:04.057967 308 : 4250, 4027
7497 13:30:04.060551 312 : 4250, 4027
7498 13:30:04.061097 316 : 4250, 4027
7499 13:30:04.063798 320 : 4250, 4026
7500 13:30:04.064289 324 : 4250, 4027
7501 13:30:04.064627 328 : 4361, 4137
7502 13:30:04.067445 332 : 4249, 3978
7503 13:30:04.067979 336 : 4250, 1629
7504 13:30:04.068444
7505 13:30:04.070750 MIOCK jitter meter ch=0
7506 13:30:04.071326
7507 13:30:04.073772 1T = (336-100) = 236 dly cells
7508 13:30:04.080313 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7509 13:30:04.080832 ==
7510 13:30:04.083890 Dram Type= 6, Freq= 0, CH_0, rank 0
7511 13:30:04.087044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7512 13:30:04.087583 ==
7513 13:30:04.093993 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7514 13:30:04.097094 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7515 13:30:04.100072 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7516 13:30:04.106978 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7517 13:30:04.116347 [CA 0] Center 44 (14~74) winsize 61
7518 13:30:04.119713 [CA 1] Center 43 (13~74) winsize 62
7519 13:30:04.122696 [CA 2] Center 39 (10~68) winsize 59
7520 13:30:04.126038 [CA 3] Center 38 (9~68) winsize 60
7521 13:30:04.129425 [CA 4] Center 36 (7~66) winsize 60
7522 13:30:04.132841 [CA 5] Center 36 (6~66) winsize 61
7523 13:30:04.133380
7524 13:30:04.135958 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7525 13:30:04.136346
7526 13:30:04.139236 [CATrainingPosCal] consider 1 rank data
7527 13:30:04.142525 u2DelayCellTimex100 = 275/100 ps
7528 13:30:04.149360 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7529 13:30:04.152346 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7530 13:30:04.155564 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7531 13:30:04.158704 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7532 13:30:04.162435 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7533 13:30:04.165875 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7534 13:30:04.166258
7535 13:30:04.168895 CA PerBit enable=1, Macro0, CA PI delay=36
7536 13:30:04.169319
7537 13:30:04.172069 [CBTSetCACLKResult] CA Dly = 36
7538 13:30:04.175107 CS Dly: 11 (0~42)
7539 13:30:04.178964 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7540 13:30:04.182040 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7541 13:30:04.182425 ==
7542 13:30:04.185170 Dram Type= 6, Freq= 0, CH_0, rank 1
7543 13:30:04.192063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7544 13:30:04.192571 ==
7545 13:30:04.195016 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7546 13:30:04.202051 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7547 13:30:04.204966 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7548 13:30:04.211383 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7549 13:30:04.219931 [CA 0] Center 44 (14~74) winsize 61
7550 13:30:04.223020 [CA 1] Center 43 (13~74) winsize 62
7551 13:30:04.226263 [CA 2] Center 38 (9~68) winsize 60
7552 13:30:04.229893 [CA 3] Center 39 (10~68) winsize 59
7553 13:30:04.233057 [CA 4] Center 37 (7~67) winsize 61
7554 13:30:04.236180 [CA 5] Center 36 (7~66) winsize 60
7555 13:30:04.236588
7556 13:30:04.239796 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7557 13:30:04.240180
7558 13:30:04.243001 [CATrainingPosCal] consider 2 rank data
7559 13:30:04.246667 u2DelayCellTimex100 = 275/100 ps
7560 13:30:04.252758 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7561 13:30:04.256597 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7562 13:30:04.259793 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7563 13:30:04.262992 CA3 delay=39 (10~68),Diff = 3 PI (10 cell)
7564 13:30:04.266061 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7565 13:30:04.269754 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7566 13:30:04.270140
7567 13:30:04.272799 CA PerBit enable=1, Macro0, CA PI delay=36
7568 13:30:04.273321
7569 13:30:04.276022 [CBTSetCACLKResult] CA Dly = 36
7570 13:30:04.279073 CS Dly: 11 (0~43)
7571 13:30:04.282317 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7572 13:30:04.286042 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7573 13:30:04.286427
7574 13:30:04.289164 ----->DramcWriteLeveling(PI) begin...
7575 13:30:04.292130 ==
7576 13:30:04.295824 Dram Type= 6, Freq= 0, CH_0, rank 0
7577 13:30:04.298827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7578 13:30:04.299207 ==
7579 13:30:04.302152 Write leveling (Byte 0): 33 => 33
7580 13:30:04.305429 Write leveling (Byte 1): 26 => 26
7581 13:30:04.308473 DramcWriteLeveling(PI) end<-----
7582 13:30:04.308857
7583 13:30:04.309204 ==
7584 13:30:04.312196 Dram Type= 6, Freq= 0, CH_0, rank 0
7585 13:30:04.315379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7586 13:30:04.315764 ==
7587 13:30:04.318590 [Gating] SW mode calibration
7588 13:30:04.325275 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7589 13:30:04.331664 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7590 13:30:04.335371 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 13:30:04.338626 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 13:30:04.344897 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 13:30:04.348517 1 4 12 | B1->B0 | 2323 3130 | 0 1 | (0 0) (0 0)
7594 13:30:04.351882 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7595 13:30:04.358086 1 4 20 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
7596 13:30:04.361454 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 13:30:04.365234 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7598 13:30:04.371199 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7599 13:30:04.375037 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7600 13:30:04.378147 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7601 13:30:04.384432 1 5 12 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
7602 13:30:04.387797 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7603 13:30:04.391383 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
7604 13:30:04.397764 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7605 13:30:04.401271 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 13:30:04.404461 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 13:30:04.410811 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 13:30:04.414419 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7609 13:30:04.417702 1 6 12 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7610 13:30:04.424112 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7611 13:30:04.427334 1 6 20 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
7612 13:30:04.431000 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 13:30:04.437358 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 13:30:04.440607 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 13:30:04.443661 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 13:30:04.450877 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 13:30:04.453958 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7618 13:30:04.456932 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7619 13:30:04.463946 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7620 13:30:04.467231 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7621 13:30:04.470593 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 13:30:04.476802 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 13:30:04.480598 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 13:30:04.483732 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 13:30:04.490319 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 13:30:04.493882 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 13:30:04.496697 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 13:30:04.503115 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 13:30:04.506822 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 13:30:04.510386 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 13:30:04.516360 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 13:30:04.519712 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7633 13:30:04.523557 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7634 13:30:04.529766 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7635 13:30:04.530156 Total UI for P1: 0, mck2ui 16
7636 13:30:04.536107 best dqsien dly found for B0: ( 1, 9, 10)
7637 13:30:04.539266 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7638 13:30:04.542812 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 13:30:04.546549 Total UI for P1: 0, mck2ui 16
7640 13:30:04.549832 best dqsien dly found for B1: ( 1, 9, 18)
7641 13:30:04.552894 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7642 13:30:04.555808 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7643 13:30:04.556263
7644 13:30:04.562782 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7645 13:30:04.565667 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7646 13:30:04.569212 [Gating] SW calibration Done
7647 13:30:04.569721 ==
7648 13:30:04.572164 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 13:30:04.575949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 13:30:04.576723 ==
7651 13:30:04.577519 RX Vref Scan: 0
7652 13:30:04.578051
7653 13:30:04.578983 RX Vref 0 -> 0, step: 1
7654 13:30:04.579566
7655 13:30:04.582112 RX Delay 0 -> 252, step: 8
7656 13:30:04.586000 iDelay=192, Bit 0, Center 135 (80 ~ 191) 112
7657 13:30:04.589117 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7658 13:30:04.595370 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7659 13:30:04.598491 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7660 13:30:04.602092 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7661 13:30:04.605406 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7662 13:30:04.608387 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7663 13:30:04.615366 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7664 13:30:04.618974 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7665 13:30:04.622043 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7666 13:30:04.625332 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7667 13:30:04.628382 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7668 13:30:04.635329 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7669 13:30:04.638185 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7670 13:30:04.641468 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7671 13:30:04.645180 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7672 13:30:04.645697 ==
7673 13:30:04.648345 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 13:30:04.655012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 13:30:04.655461 ==
7676 13:30:04.655799 DQS Delay:
7677 13:30:04.657940 DQS0 = 0, DQS1 = 0
7678 13:30:04.658386 DQM Delay:
7679 13:30:04.661186 DQM0 = 131, DQM1 = 126
7680 13:30:04.661850 DQ Delay:
7681 13:30:04.664752 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
7682 13:30:04.667773 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7683 13:30:04.670961 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
7684 13:30:04.674509 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7685 13:30:04.674956
7686 13:30:04.675365
7687 13:30:04.675762 ==
7688 13:30:04.677786 Dram Type= 6, Freq= 0, CH_0, rank 0
7689 13:30:04.684104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7690 13:30:04.684609 ==
7691 13:30:04.685039
7692 13:30:04.685401
7693 13:30:04.685673 TX Vref Scan disable
7694 13:30:04.687720 == TX Byte 0 ==
7695 13:30:04.691057 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7696 13:30:04.697859 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7697 13:30:04.698238 == TX Byte 1 ==
7698 13:30:04.700950 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7699 13:30:04.707711 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7700 13:30:04.708091 ==
7701 13:30:04.710855 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 13:30:04.714146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 13:30:04.714530 ==
7704 13:30:04.728693
7705 13:30:04.731550 TX Vref early break, caculate TX vref
7706 13:30:04.735199 TX Vref=16, minBit 1, minWin=22, winSum=370
7707 13:30:04.738209 TX Vref=18, minBit 8, minWin=22, winSum=383
7708 13:30:04.741480 TX Vref=20, minBit 1, minWin=24, winSum=391
7709 13:30:04.744740 TX Vref=22, minBit 1, minWin=24, winSum=399
7710 13:30:04.751493 TX Vref=24, minBit 8, minWin=24, winSum=412
7711 13:30:04.754653 TX Vref=26, minBit 1, minWin=25, winSum=418
7712 13:30:04.757888 TX Vref=28, minBit 2, minWin=25, winSum=421
7713 13:30:04.761103 TX Vref=30, minBit 4, minWin=25, winSum=418
7714 13:30:04.764694 TX Vref=32, minBit 1, minWin=24, winSum=406
7715 13:30:04.767808 TX Vref=34, minBit 0, minWin=24, winSum=400
7716 13:30:04.774414 TX Vref=36, minBit 2, minWin=23, winSum=389
7717 13:30:04.777593 [TxChooseVref] Worse bit 2, Min win 25, Win sum 421, Final Vref 28
7718 13:30:04.777973
7719 13:30:04.780653 Final TX Range 0 Vref 28
7720 13:30:04.781032
7721 13:30:04.781356 ==
7722 13:30:04.784181 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 13:30:04.790742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 13:30:04.791138 ==
7725 13:30:04.791638
7726 13:30:04.791939
7727 13:30:04.792211 TX Vref Scan disable
7728 13:30:04.797634 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7729 13:30:04.798017 == TX Byte 0 ==
7730 13:30:04.801248 u2DelayCellOfst[0]=10 cells (3 PI)
7731 13:30:04.804397 u2DelayCellOfst[1]=14 cells (4 PI)
7732 13:30:04.807892 u2DelayCellOfst[2]=7 cells (2 PI)
7733 13:30:04.810977 u2DelayCellOfst[3]=10 cells (3 PI)
7734 13:30:04.814832 u2DelayCellOfst[4]=7 cells (2 PI)
7735 13:30:04.817804 u2DelayCellOfst[5]=0 cells (0 PI)
7736 13:30:04.820993 u2DelayCellOfst[6]=14 cells (4 PI)
7737 13:30:04.824172 u2DelayCellOfst[7]=14 cells (4 PI)
7738 13:30:04.827365 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7739 13:30:04.831025 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7740 13:30:04.834062 == TX Byte 1 ==
7741 13:30:04.837208 u2DelayCellOfst[8]=0 cells (0 PI)
7742 13:30:04.840419 u2DelayCellOfst[9]=0 cells (0 PI)
7743 13:30:04.844260 u2DelayCellOfst[10]=3 cells (1 PI)
7744 13:30:04.847472 u2DelayCellOfst[11]=0 cells (0 PI)
7745 13:30:04.850573 u2DelayCellOfst[12]=10 cells (3 PI)
7746 13:30:04.853591 u2DelayCellOfst[13]=10 cells (3 PI)
7747 13:30:04.856989 u2DelayCellOfst[14]=14 cells (4 PI)
7748 13:30:04.860384 u2DelayCellOfst[15]=10 cells (3 PI)
7749 13:30:04.863469 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7750 13:30:04.866665 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7751 13:30:04.870406 DramC Write-DBI on
7752 13:30:04.870887 ==
7753 13:30:04.873196 Dram Type= 6, Freq= 0, CH_0, rank 0
7754 13:30:04.876815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7755 13:30:04.877411 ==
7756 13:30:04.877751
7757 13:30:04.878032
7758 13:30:04.879828 TX Vref Scan disable
7759 13:30:04.880232 == TX Byte 0 ==
7760 13:30:04.886741 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
7761 13:30:04.887151 == TX Byte 1 ==
7762 13:30:04.893117 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7763 13:30:04.893541 DramC Write-DBI off
7764 13:30:04.893834
7765 13:30:04.894149 [DATLAT]
7766 13:30:04.896642 Freq=1600, CH0 RK0
7767 13:30:04.896974
7768 13:30:04.897337 DATLAT Default: 0xf
7769 13:30:04.899900 0, 0xFFFF, sum = 0
7770 13:30:04.902966 1, 0xFFFF, sum = 0
7771 13:30:04.903353 2, 0xFFFF, sum = 0
7772 13:30:04.906949 3, 0xFFFF, sum = 0
7773 13:30:04.907335 4, 0xFFFF, sum = 0
7774 13:30:04.910022 5, 0xFFFF, sum = 0
7775 13:30:04.910465 6, 0xFFFF, sum = 0
7776 13:30:04.913075 7, 0xFFFF, sum = 0
7777 13:30:04.913740 8, 0xFFFF, sum = 0
7778 13:30:04.916021 9, 0xFFFF, sum = 0
7779 13:30:04.916464 10, 0xFFFF, sum = 0
7780 13:30:04.919837 11, 0xFFFF, sum = 0
7781 13:30:04.920314 12, 0xFFFF, sum = 0
7782 13:30:04.923170 13, 0xFFFF, sum = 0
7783 13:30:04.923587 14, 0x0, sum = 1
7784 13:30:04.926408 15, 0x0, sum = 2
7785 13:30:04.926806 16, 0x0, sum = 3
7786 13:30:04.929473 17, 0x0, sum = 4
7787 13:30:04.929940 best_step = 15
7788 13:30:04.930236
7789 13:30:04.930507 ==
7790 13:30:04.933064 Dram Type= 6, Freq= 0, CH_0, rank 0
7791 13:30:04.939469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7792 13:30:04.939847 ==
7793 13:30:04.940144 RX Vref Scan: 1
7794 13:30:04.940411
7795 13:30:04.942742 Set Vref Range= 24 -> 127
7796 13:30:04.943143
7797 13:30:04.946314 RX Vref 24 -> 127, step: 1
7798 13:30:04.946690
7799 13:30:04.946981 RX Delay 11 -> 252, step: 4
7800 13:30:04.949389
7801 13:30:04.949766 Set Vref, RX VrefLevel [Byte0]: 24
7802 13:30:04.952616 [Byte1]: 24
7803 13:30:04.956846
7804 13:30:04.957264 Set Vref, RX VrefLevel [Byte0]: 25
7805 13:30:04.960188 [Byte1]: 25
7806 13:30:04.964688
7807 13:30:04.965228 Set Vref, RX VrefLevel [Byte0]: 26
7808 13:30:04.967679 [Byte1]: 26
7809 13:30:04.972129
7810 13:30:04.972595 Set Vref, RX VrefLevel [Byte0]: 27
7811 13:30:04.975469 [Byte1]: 27
7812 13:30:04.979864
7813 13:30:04.980240 Set Vref, RX VrefLevel [Byte0]: 28
7814 13:30:04.983548 [Byte1]: 28
7815 13:30:04.987463
7816 13:30:04.987840 Set Vref, RX VrefLevel [Byte0]: 29
7817 13:30:04.990557 [Byte1]: 29
7818 13:30:04.994793
7819 13:30:04.995168 Set Vref, RX VrefLevel [Byte0]: 30
7820 13:30:04.998301 [Byte1]: 30
7821 13:30:05.002859
7822 13:30:05.003236 Set Vref, RX VrefLevel [Byte0]: 31
7823 13:30:05.006166 [Byte1]: 31
7824 13:30:05.010215
7825 13:30:05.010755 Set Vref, RX VrefLevel [Byte0]: 32
7826 13:30:05.013622 [Byte1]: 32
7827 13:30:05.017894
7828 13:30:05.018339 Set Vref, RX VrefLevel [Byte0]: 33
7829 13:30:05.021167 [Byte1]: 33
7830 13:30:05.025700
7831 13:30:05.026076 Set Vref, RX VrefLevel [Byte0]: 34
7832 13:30:05.028510 [Byte1]: 34
7833 13:30:05.032985
7834 13:30:05.033423 Set Vref, RX VrefLevel [Byte0]: 35
7835 13:30:05.036166 [Byte1]: 35
7836 13:30:05.041028
7837 13:30:05.041438 Set Vref, RX VrefLevel [Byte0]: 36
7838 13:30:05.044127 [Byte1]: 36
7839 13:30:05.048616
7840 13:30:05.048992 Set Vref, RX VrefLevel [Byte0]: 37
7841 13:30:05.051735 [Byte1]: 37
7842 13:30:05.056063
7843 13:30:05.056441 Set Vref, RX VrefLevel [Byte0]: 38
7844 13:30:05.059226 [Byte1]: 38
7845 13:30:05.063756
7846 13:30:05.064130 Set Vref, RX VrefLevel [Byte0]: 39
7847 13:30:05.066875 [Byte1]: 39
7848 13:30:05.071329
7849 13:30:05.071704 Set Vref, RX VrefLevel [Byte0]: 40
7850 13:30:05.074583 [Byte1]: 40
7851 13:30:05.078885
7852 13:30:05.079260 Set Vref, RX VrefLevel [Byte0]: 41
7853 13:30:05.082167 [Byte1]: 41
7854 13:30:05.086698
7855 13:30:05.087074 Set Vref, RX VrefLevel [Byte0]: 42
7856 13:30:05.089654 [Byte1]: 42
7857 13:30:05.094052
7858 13:30:05.094586 Set Vref, RX VrefLevel [Byte0]: 43
7859 13:30:05.097478 [Byte1]: 43
7860 13:30:05.101630
7861 13:30:05.102018 Set Vref, RX VrefLevel [Byte0]: 44
7862 13:30:05.104931 [Byte1]: 44
7863 13:30:05.109538
7864 13:30:05.109991 Set Vref, RX VrefLevel [Byte0]: 45
7865 13:30:05.112660 [Byte1]: 45
7866 13:30:05.116951
7867 13:30:05.117485 Set Vref, RX VrefLevel [Byte0]: 46
7868 13:30:05.120133 [Byte1]: 46
7869 13:30:05.124655
7870 13:30:05.125223 Set Vref, RX VrefLevel [Byte0]: 47
7871 13:30:05.127753 [Byte1]: 47
7872 13:30:05.131830
7873 13:30:05.132340 Set Vref, RX VrefLevel [Byte0]: 48
7874 13:30:05.135248 [Byte1]: 48
7875 13:30:05.139435
7876 13:30:05.139991 Set Vref, RX VrefLevel [Byte0]: 49
7877 13:30:05.143223 [Byte1]: 49
7878 13:30:05.147119
7879 13:30:05.147494 Set Vref, RX VrefLevel [Byte0]: 50
7880 13:30:05.150770 [Byte1]: 50
7881 13:30:05.155039
7882 13:30:05.155573 Set Vref, RX VrefLevel [Byte0]: 51
7883 13:30:05.158356 [Byte1]: 51
7884 13:30:05.162431
7885 13:30:05.162927 Set Vref, RX VrefLevel [Byte0]: 52
7886 13:30:05.165747 [Byte1]: 52
7887 13:30:05.170180
7888 13:30:05.170608 Set Vref, RX VrefLevel [Byte0]: 53
7889 13:30:05.173374 [Byte1]: 53
7890 13:30:05.177782
7891 13:30:05.178317 Set Vref, RX VrefLevel [Byte0]: 54
7892 13:30:05.180855 [Byte1]: 54
7893 13:30:05.185509
7894 13:30:05.185916 Set Vref, RX VrefLevel [Byte0]: 55
7895 13:30:05.188593 [Byte1]: 55
7896 13:30:05.193014
7897 13:30:05.193487 Set Vref, RX VrefLevel [Byte0]: 56
7898 13:30:05.196226 [Byte1]: 56
7899 13:30:05.200770
7900 13:30:05.201308 Set Vref, RX VrefLevel [Byte0]: 57
7901 13:30:05.203859 [Byte1]: 57
7902 13:30:05.208148
7903 13:30:05.208617 Set Vref, RX VrefLevel [Byte0]: 58
7904 13:30:05.211680 [Byte1]: 58
7905 13:30:05.215839
7906 13:30:05.216389 Set Vref, RX VrefLevel [Byte0]: 59
7907 13:30:05.218860 [Byte1]: 59
7908 13:30:05.223370
7909 13:30:05.223902 Set Vref, RX VrefLevel [Byte0]: 60
7910 13:30:05.226473 [Byte1]: 60
7911 13:30:05.231001
7912 13:30:05.231432 Set Vref, RX VrefLevel [Byte0]: 61
7913 13:30:05.234224 [Byte1]: 61
7914 13:30:05.238525
7915 13:30:05.238909 Set Vref, RX VrefLevel [Byte0]: 62
7916 13:30:05.242135 [Byte1]: 62
7917 13:30:05.246585
7918 13:30:05.247064 Set Vref, RX VrefLevel [Byte0]: 63
7919 13:30:05.249466 [Byte1]: 63
7920 13:30:05.254237
7921 13:30:05.254696 Set Vref, RX VrefLevel [Byte0]: 64
7922 13:30:05.257325 [Byte1]: 64
7923 13:30:05.261763
7924 13:30:05.262202 Set Vref, RX VrefLevel [Byte0]: 65
7925 13:30:05.264766 [Byte1]: 65
7926 13:30:05.269562
7927 13:30:05.270036 Set Vref, RX VrefLevel [Byte0]: 66
7928 13:30:05.272779 [Byte1]: 66
7929 13:30:05.276595
7930 13:30:05.276973 Set Vref, RX VrefLevel [Byte0]: 67
7931 13:30:05.280006 [Byte1]: 67
7932 13:30:05.284349
7933 13:30:05.284871 Set Vref, RX VrefLevel [Byte0]: 68
7934 13:30:05.287420 [Byte1]: 68
7935 13:30:05.291858
7936 13:30:05.292228 Set Vref, RX VrefLevel [Byte0]: 69
7937 13:30:05.295197 [Byte1]: 69
7938 13:30:05.299629
7939 13:30:05.299979 Set Vref, RX VrefLevel [Byte0]: 70
7940 13:30:05.302923 [Byte1]: 70
7941 13:30:05.307302
7942 13:30:05.307743 Set Vref, RX VrefLevel [Byte0]: 71
7943 13:30:05.310566 [Byte1]: 71
7944 13:30:05.314906
7945 13:30:05.315353 Set Vref, RX VrefLevel [Byte0]: 72
7946 13:30:05.317813 [Byte1]: 72
7947 13:30:05.322315
7948 13:30:05.322913 Final RX Vref Byte 0 = 55 to rank0
7949 13:30:05.325247 Final RX Vref Byte 1 = 57 to rank0
7950 13:30:05.329081 Final RX Vref Byte 0 = 55 to rank1
7951 13:30:05.332142 Final RX Vref Byte 1 = 57 to rank1==
7952 13:30:05.335374 Dram Type= 6, Freq= 0, CH_0, rank 0
7953 13:30:05.342322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7954 13:30:05.342708 ==
7955 13:30:05.343230 DQS Delay:
7956 13:30:05.345391 DQS0 = 0, DQS1 = 0
7957 13:30:05.345768 DQM Delay:
7958 13:30:05.346063 DQM0 = 128, DQM1 = 124
7959 13:30:05.348663 DQ Delay:
7960 13:30:05.351824 DQ0 =130, DQ1 =130, DQ2 =128, DQ3 =124
7961 13:30:05.355543 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =132
7962 13:30:05.358487 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7963 13:30:05.362091 DQ12 =132, DQ13 =130, DQ14 =134, DQ15 =130
7964 13:30:05.362470
7965 13:30:05.362760
7966 13:30:05.363028
7967 13:30:05.365050 [DramC_TX_OE_Calibration] TA2
7968 13:30:05.368274 Original DQ_B0 (3 6) =30, OEN = 27
7969 13:30:05.371561 Original DQ_B1 (3 6) =30, OEN = 27
7970 13:30:05.374679 24, 0x0, End_B0=24 End_B1=24
7971 13:30:05.378504 25, 0x0, End_B0=25 End_B1=25
7972 13:30:05.378889 26, 0x0, End_B0=26 End_B1=26
7973 13:30:05.381696 27, 0x0, End_B0=27 End_B1=27
7974 13:30:05.384860 28, 0x0, End_B0=28 End_B1=28
7975 13:30:05.387814 29, 0x0, End_B0=29 End_B1=29
7976 13:30:05.391719 30, 0x0, End_B0=30 End_B1=30
7977 13:30:05.392136 31, 0x5151, End_B0=30 End_B1=30
7978 13:30:05.394534 Byte0 end_step=30 best_step=27
7979 13:30:05.397767 Byte1 end_step=30 best_step=27
7980 13:30:05.400990 Byte0 TX OE(2T, 0.5T) = (3, 3)
7981 13:30:05.404334 Byte1 TX OE(2T, 0.5T) = (3, 3)
7982 13:30:05.404409
7983 13:30:05.404467
7984 13:30:05.410676 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7985 13:30:05.413681 CH0 RK0: MR19=303, MR18=1A17
7986 13:30:05.420525 CH0_RK0: MR19=0x303, MR18=0x1A17, DQSOSC=396, MR23=63, INC=23, DEC=15
7987 13:30:05.420613
7988 13:30:05.423715 ----->DramcWriteLeveling(PI) begin...
7989 13:30:05.423791 ==
7990 13:30:05.427245 Dram Type= 6, Freq= 0, CH_0, rank 1
7991 13:30:05.430281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7992 13:30:05.433920 ==
7993 13:30:05.434000 Write leveling (Byte 0): 34 => 34
7994 13:30:05.436799 Write leveling (Byte 1): 28 => 28
7995 13:30:05.440547 DramcWriteLeveling(PI) end<-----
7996 13:30:05.440640
7997 13:30:05.440711 ==
7998 13:30:05.443606 Dram Type= 6, Freq= 0, CH_0, rank 1
7999 13:30:05.450484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8000 13:30:05.450590 ==
8001 13:30:05.453708 [Gating] SW mode calibration
8002 13:30:05.459940 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8003 13:30:05.463514 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8004 13:30:05.469561 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 13:30:05.473566 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 13:30:05.476569 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8007 13:30:05.482982 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8008 13:30:05.486173 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8009 13:30:05.490023 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8010 13:30:05.496449 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8011 13:30:05.499638 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8012 13:30:05.502748 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8013 13:30:05.509868 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 13:30:05.512817 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8015 13:30:05.516379 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8016 13:30:05.523015 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8017 13:30:05.526054 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
8018 13:30:05.529176 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 13:30:05.536207 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 13:30:05.539812 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 13:30:05.542654 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 13:30:05.549666 1 6 8 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
8023 13:30:12.904016 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8024 13:30:12.904132 1 6 16 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
8025 13:30:12.904193 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 13:30:12.904248 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 13:30:12.904302 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 13:30:12.904353 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 13:30:12.904407 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 13:30:12.904462 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8031 13:30:12.904512 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8032 13:30:12.904560 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8033 13:30:12.904608 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8034 13:30:12.904656 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 13:30:12.904705 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 13:30:12.904753 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 13:30:12.904802 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 13:30:12.904850 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 13:30:12.904899 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 13:30:12.904948 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 13:30:12.904996 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 13:30:12.905043 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 13:30:12.905090 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 13:30:12.905164 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 13:30:12.905231 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8046 13:30:12.905280 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8047 13:30:12.905328 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8048 13:30:12.905375 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8049 13:30:12.905424 Total UI for P1: 0, mck2ui 16
8050 13:30:12.905474 best dqsien dly found for B0: ( 1, 9, 8)
8051 13:30:12.905522 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8052 13:30:12.905570 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 13:30:12.905618 Total UI for P1: 0, mck2ui 16
8054 13:30:12.905666 best dqsien dly found for B1: ( 1, 9, 20)
8055 13:30:12.905780 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8056 13:30:12.905844 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8057 13:30:12.905915
8058 13:30:12.905978 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8059 13:30:12.906026 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8060 13:30:12.906074 [Gating] SW calibration Done
8061 13:30:12.906122 ==
8062 13:30:12.906170 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 13:30:12.906219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 13:30:12.906267 ==
8065 13:30:12.906315 RX Vref Scan: 0
8066 13:30:12.906362
8067 13:30:12.906410 RX Vref 0 -> 0, step: 1
8068 13:30:12.906483
8069 13:30:12.906544 RX Delay 0 -> 252, step: 8
8070 13:30:12.906592 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8071 13:30:12.906640 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8072 13:30:12.906688 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8073 13:30:12.906737 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8074 13:30:12.906819 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8075 13:30:12.906872 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8076 13:30:12.906922 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8077 13:30:12.906971 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8078 13:30:12.907020 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8079 13:30:12.907075 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8080 13:30:12.907186 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8081 13:30:12.907299 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8082 13:30:12.907348 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8083 13:30:12.907396 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8084 13:30:12.907445 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8085 13:30:12.907493 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8086 13:30:12.907554 ==
8087 13:30:12.907631 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 13:30:12.907741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 13:30:12.907826 ==
8090 13:30:12.907878 DQS Delay:
8091 13:30:12.907927 DQS0 = 0, DQS1 = 0
8092 13:30:12.907975 DQM Delay:
8093 13:30:12.908041 DQM0 = 132, DQM1 = 126
8094 13:30:12.908144 DQ Delay:
8095 13:30:12.908208 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8096 13:30:12.908258 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8097 13:30:12.908322 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
8098 13:30:12.908370 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8099 13:30:12.908434
8100 13:30:12.908497
8101 13:30:12.908544 ==
8102 13:30:12.908592 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 13:30:12.908657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 13:30:12.908721 ==
8105 13:30:12.908784
8106 13:30:12.908849
8107 13:30:12.908898 TX Vref Scan disable
8108 13:30:12.908949 == TX Byte 0 ==
8109 13:30:12.908999 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8110 13:30:12.909049 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8111 13:30:12.909099 == TX Byte 1 ==
8112 13:30:12.909156 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8113 13:30:12.909251 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8114 13:30:12.909300 ==
8115 13:30:12.909349 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 13:30:12.909398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 13:30:12.909447 ==
8118 13:30:12.909495
8119 13:30:12.909542 TX Vref early break, caculate TX vref
8120 13:30:12.909591 TX Vref=16, minBit 1, minWin=23, winSum=383
8121 13:30:12.909640 TX Vref=18, minBit 2, minWin=23, winSum=390
8122 13:30:12.909690 TX Vref=20, minBit 2, minWin=24, winSum=397
8123 13:30:12.909739 TX Vref=22, minBit 0, minWin=25, winSum=407
8124 13:30:12.909787 TX Vref=24, minBit 1, minWin=25, winSum=413
8125 13:30:12.909836 TX Vref=26, minBit 0, minWin=26, winSum=421
8126 13:30:12.909885 TX Vref=28, minBit 2, minWin=25, winSum=420
8127 13:30:12.909963 TX Vref=30, minBit 1, minWin=25, winSum=416
8128 13:30:12.910012 TX Vref=32, minBit 1, minWin=25, winSum=413
8129 13:30:12.910092 TX Vref=34, minBit 0, minWin=24, winSum=400
8130 13:30:12.910141 TX Vref=36, minBit 2, minWin=23, winSum=395
8131 13:30:12.910190 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 26
8132 13:30:12.910239
8133 13:30:12.910287 Final TX Range 0 Vref 26
8134 13:30:12.910335
8135 13:30:12.910399 ==
8136 13:30:12.910666 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 13:30:12.910721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 13:30:12.910771 ==
8139 13:30:12.910825
8140 13:30:12.910939
8141 13:30:12.911007 TX Vref Scan disable
8142 13:30:12.911086 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8143 13:30:12.911152 == TX Byte 0 ==
8144 13:30:12.911202 u2DelayCellOfst[0]=10 cells (3 PI)
8145 13:30:12.911290 u2DelayCellOfst[1]=14 cells (4 PI)
8146 13:30:12.911353 u2DelayCellOfst[2]=7 cells (2 PI)
8147 13:30:12.911403 u2DelayCellOfst[3]=7 cells (2 PI)
8148 13:30:12.911482 u2DelayCellOfst[4]=7 cells (2 PI)
8149 13:30:12.911560 u2DelayCellOfst[5]=0 cells (0 PI)
8150 13:30:12.911624 u2DelayCellOfst[6]=14 cells (4 PI)
8151 13:30:12.911728 u2DelayCellOfst[7]=14 cells (4 PI)
8152 13:30:12.911794 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8153 13:30:12.911850 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8154 13:30:12.911901 == TX Byte 1 ==
8155 13:30:12.911952 u2DelayCellOfst[8]=0 cells (0 PI)
8156 13:30:12.912002 u2DelayCellOfst[9]=0 cells (0 PI)
8157 13:30:12.912052 u2DelayCellOfst[10]=3 cells (1 PI)
8158 13:30:12.912102 u2DelayCellOfst[11]=3 cells (1 PI)
8159 13:30:12.912152 u2DelayCellOfst[12]=10 cells (3 PI)
8160 13:30:12.912202 u2DelayCellOfst[13]=10 cells (3 PI)
8161 13:30:12.912257 u2DelayCellOfst[14]=17 cells (5 PI)
8162 13:30:12.912307 u2DelayCellOfst[15]=10 cells (3 PI)
8163 13:30:12.912356 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8164 13:30:12.912406 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8165 13:30:12.912485 DramC Write-DBI on
8166 13:30:12.912550 ==
8167 13:30:12.912602 Dram Type= 6, Freq= 0, CH_0, rank 1
8168 13:30:12.912668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8169 13:30:12.912718 ==
8170 13:30:12.912774
8171 13:30:12.912825
8172 13:30:12.912874 TX Vref Scan disable
8173 13:30:12.912924 == TX Byte 0 ==
8174 13:30:12.912974 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8175 13:30:12.913046 == TX Byte 1 ==
8176 13:30:12.913125 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8177 13:30:12.913206 DramC Write-DBI off
8178 13:30:12.913256
8179 13:30:12.913304 [DATLAT]
8180 13:30:12.913352 Freq=1600, CH0 RK1
8181 13:30:12.913406
8182 13:30:12.913456 DATLAT Default: 0xf
8183 13:30:12.913504 0, 0xFFFF, sum = 0
8184 13:30:12.913585 1, 0xFFFF, sum = 0
8185 13:30:12.913641 2, 0xFFFF, sum = 0
8186 13:30:12.913691 3, 0xFFFF, sum = 0
8187 13:30:12.913744 4, 0xFFFF, sum = 0
8188 13:30:12.913793 5, 0xFFFF, sum = 0
8189 13:30:12.913843 6, 0xFFFF, sum = 0
8190 13:30:12.913892 7, 0xFFFF, sum = 0
8191 13:30:12.913941 8, 0xFFFF, sum = 0
8192 13:30:12.914025 9, 0xFFFF, sum = 0
8193 13:30:12.914076 10, 0xFFFF, sum = 0
8194 13:30:12.914126 11, 0xFFFF, sum = 0
8195 13:30:12.914175 12, 0xFFFF, sum = 0
8196 13:30:12.914225 13, 0xFFFF, sum = 0
8197 13:30:12.914274 14, 0x0, sum = 1
8198 13:30:12.914323 15, 0x0, sum = 2
8199 13:30:12.914388 16, 0x0, sum = 3
8200 13:30:12.914455 17, 0x0, sum = 4
8201 13:30:12.914534 best_step = 15
8202 13:30:12.914656
8203 13:30:12.914763 ==
8204 13:30:12.914817 Dram Type= 6, Freq= 0, CH_0, rank 1
8205 13:30:12.914868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8206 13:30:12.914919 ==
8207 13:30:12.914985 RX Vref Scan: 0
8208 13:30:12.915032
8209 13:30:12.915088 RX Vref 0 -> 0, step: 1
8210 13:30:12.915153
8211 13:30:12.915217 RX Delay 11 -> 252, step: 4
8212 13:30:12.915266 iDelay=191, Bit 0, Center 126 (79 ~ 174) 96
8213 13:30:12.915315 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8214 13:30:12.915410 iDelay=191, Bit 2, Center 126 (75 ~ 178) 104
8215 13:30:12.915482 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8216 13:30:12.915551 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8217 13:30:12.915627 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8218 13:30:12.915677 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8219 13:30:12.915742 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8220 13:30:12.915805 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8221 13:30:12.915883 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8222 13:30:12.915976 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8223 13:30:12.916054 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8224 13:30:12.916133 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8225 13:30:12.916210 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8226 13:30:12.916293 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8227 13:30:12.916372 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8228 13:30:12.916422 ==
8229 13:30:12.916479 Dram Type= 6, Freq= 0, CH_0, rank 1
8230 13:30:12.916530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 13:30:12.916580 ==
8232 13:30:12.916643 DQS Delay:
8233 13:30:12.916729 DQS0 = 0, DQS1 = 0
8234 13:30:12.916820 DQM Delay:
8235 13:30:12.916916 DQM0 = 129, DQM1 = 124
8236 13:30:12.916994 DQ Delay:
8237 13:30:12.917071 DQ0 =126, DQ1 =130, DQ2 =126, DQ3 =126
8238 13:30:12.917156 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
8239 13:30:12.917239 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8240 13:30:12.917294 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8241 13:30:12.917346
8242 13:30:12.917395
8243 13:30:12.917458
8244 13:30:12.917506 [DramC_TX_OE_Calibration] TA2
8245 13:30:12.917593 Original DQ_B0 (3 6) =30, OEN = 27
8246 13:30:12.917644 Original DQ_B1 (3 6) =30, OEN = 27
8247 13:30:12.917701 24, 0x0, End_B0=24 End_B1=24
8248 13:30:12.917782 25, 0x0, End_B0=25 End_B1=25
8249 13:30:12.917862 26, 0x0, End_B0=26 End_B1=26
8250 13:30:12.917927 27, 0x0, End_B0=27 End_B1=27
8251 13:30:12.917991 28, 0x0, End_B0=28 End_B1=28
8252 13:30:12.918064 29, 0x0, End_B0=29 End_B1=29
8253 13:30:12.918115 30, 0x0, End_B0=30 End_B1=30
8254 13:30:12.918167 31, 0x4141, End_B0=30 End_B1=30
8255 13:30:12.918218 Byte0 end_step=30 best_step=27
8256 13:30:12.918268 Byte1 end_step=30 best_step=27
8257 13:30:12.918318 Byte0 TX OE(2T, 0.5T) = (3, 3)
8258 13:30:12.918368 Byte1 TX OE(2T, 0.5T) = (3, 3)
8259 13:30:12.918425
8260 13:30:12.918475
8261 13:30:12.918525 [DQSOSCAuto] RK1, (LSB)MR18= 0x1412, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8262 13:30:12.918591 CH0 RK1: MR19=303, MR18=1412
8263 13:30:12.918640 CH0_RK1: MR19=0x303, MR18=0x1412, DQSOSC=399, MR23=63, INC=23, DEC=15
8264 13:30:12.918690 [RxdqsGatingPostProcess] freq 1600
8265 13:30:12.918769 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8266 13:30:12.918825 best DQS0 dly(2T, 0.5T) = (1, 1)
8267 13:30:12.918874 best DQS1 dly(2T, 0.5T) = (1, 1)
8268 13:30:12.918923 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8269 13:30:12.918972 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8270 13:30:12.919021 best DQS0 dly(2T, 0.5T) = (1, 1)
8271 13:30:12.919070 best DQS1 dly(2T, 0.5T) = (1, 1)
8272 13:30:12.919118 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8273 13:30:12.919196 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8274 13:30:12.919252 Pre-setting of DQS Precalculation
8275 13:30:12.919523 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8276 13:30:12.919636 ==
8277 13:30:12.919714 Dram Type= 6, Freq= 0, CH_1, rank 0
8278 13:30:12.919791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8279 13:30:12.919872 ==
8280 13:30:12.919948 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8281 13:30:12.920041 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8282 13:30:12.920119 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8283 13:30:12.920217 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8284 13:30:12.920270 [CA 0] Center 42 (12~72) winsize 61
8285 13:30:12.920319 [CA 1] Center 42 (12~72) winsize 61
8286 13:30:12.920368 [CA 2] Center 38 (9~67) winsize 59
8287 13:30:12.920432 [CA 3] Center 37 (8~66) winsize 59
8288 13:30:12.920494 [CA 4] Center 37 (8~67) winsize 60
8289 13:30:12.920543 [CA 5] Center 36 (7~66) winsize 60
8290 13:30:12.920592
8291 13:30:12.920645 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8292 13:30:12.920695
8293 13:30:12.920743 [CATrainingPosCal] consider 1 rank data
8294 13:30:12.920792 u2DelayCellTimex100 = 275/100 ps
8295 13:30:12.920857 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8296 13:30:12.920920 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8297 13:30:12.920969 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8298 13:30:12.921022 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8299 13:30:12.921099 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8300 13:30:12.921205 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8301 13:30:12.921256
8302 13:30:12.921305 CA PerBit enable=1, Macro0, CA PI delay=36
8303 13:30:12.921354
8304 13:30:12.921403 [CBTSetCACLKResult] CA Dly = 36
8305 13:30:12.921459 CS Dly: 8 (0~39)
8306 13:30:12.921508 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8307 13:30:12.921556 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8308 13:30:12.921605 ==
8309 13:30:12.921660 Dram Type= 6, Freq= 0, CH_1, rank 1
8310 13:30:12.921709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 13:30:12.921759 ==
8312 13:30:12.921826 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8313 13:30:12.921880 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8314 13:30:12.921945 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8315 13:30:12.921994 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8316 13:30:12.922042 [CA 0] Center 42 (13~72) winsize 60
8317 13:30:12.922091 [CA 1] Center 42 (13~72) winsize 60
8318 13:30:12.922140 [CA 2] Center 38 (9~68) winsize 60
8319 13:30:12.922189 [CA 3] Center 37 (8~66) winsize 59
8320 13:30:12.922236 [CA 4] Center 37 (7~68) winsize 62
8321 13:30:12.922289 [CA 5] Center 37 (8~67) winsize 60
8322 13:30:12.922338
8323 13:30:12.922387 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8324 13:30:12.922435
8325 13:30:12.922483 [CATrainingPosCal] consider 2 rank data
8326 13:30:12.922531 u2DelayCellTimex100 = 275/100 ps
8327 13:30:12.922580 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8328 13:30:12.922628 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8329 13:30:12.922712 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8330 13:30:12.922762 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8331 13:30:12.922811 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8332 13:30:12.922860 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8333 13:30:12.922908
8334 13:30:12.922956 CA PerBit enable=1, Macro0, CA PI delay=37
8335 13:30:12.923005
8336 13:30:12.923071 [CBTSetCACLKResult] CA Dly = 37
8337 13:30:12.923136 CS Dly: 9 (0~42)
8338 13:30:12.923185 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8339 13:30:12.923234 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8340 13:30:12.923283
8341 13:30:12.923331 ----->DramcWriteLeveling(PI) begin...
8342 13:30:12.923380 ==
8343 13:30:12.923428 Dram Type= 6, Freq= 0, CH_1, rank 0
8344 13:30:12.923477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8345 13:30:12.923573 ==
8346 13:30:12.923651 Write leveling (Byte 0): 24 => 24
8347 13:30:12.923742 Write leveling (Byte 1): 26 => 26
8348 13:30:12.923818 DramcWriteLeveling(PI) end<-----
8349 13:30:12.923897
8350 13:30:12.924002 ==
8351 13:30:12.924078 Dram Type= 6, Freq= 0, CH_1, rank 0
8352 13:30:12.924154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8353 13:30:12.924230 ==
8354 13:30:12.924286 [Gating] SW mode calibration
8355 13:30:12.924336 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8356 13:30:12.924386 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8357 13:30:12.924435 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 13:30:12.924484 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 13:30:12.924533 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 13:30:12.924588 1 4 12 | B1->B0 | 2525 3333 | 0 1 | (0 0) (0 0)
8361 13:30:12.924683 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 13:30:12.924747 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 13:30:12.924796 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 13:30:12.924845 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 13:30:12.924908 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 13:30:12.924988 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 13:30:12.925066 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8368 13:30:12.925149 1 5 12 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (1 0)
8369 13:30:12.925217 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8370 13:30:12.925265 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 13:30:12.925313 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 13:30:12.925396 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 13:30:12.925445 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 13:30:12.925510 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 13:30:12.925573 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8376 13:30:12.925621 1 6 12 | B1->B0 | 3030 4444 | 0 0 | (0 0) (0 0)
8377 13:30:12.925669 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 13:30:12.925748 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 13:30:12.925812 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 13:30:12.925860 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 13:30:12.925908 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 13:30:12.925955 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 13:30:12.926193 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 13:30:12.926250 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8385 13:30:12.926299 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8386 13:30:12.926352 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 13:30:12.926402 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 13:30:12.926501 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 13:30:12.926577 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 13:30:12.926684 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 13:30:12.926778 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 13:30:12.926870 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 13:30:12.926945 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 13:30:12.927021 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 13:30:12.927100 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 13:30:12.927208 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 13:30:12.927334 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 13:30:12.927459 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 13:30:12.927535 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8400 13:30:12.927610 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8401 13:30:12.927686 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8402 13:30:12.927765 Total UI for P1: 0, mck2ui 16
8403 13:30:12.927858 best dqsien dly found for B0: ( 1, 9, 10)
8404 13:30:12.927936 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 13:30:12.928013 Total UI for P1: 0, mck2ui 16
8406 13:30:12.928174 best dqsien dly found for B1: ( 1, 9, 14)
8407 13:30:12.928251 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8408 13:30:12.928327 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8409 13:30:12.928402
8410 13:30:12.928478 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8411 13:30:12.928553 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8412 13:30:12.928605 [Gating] SW calibration Done
8413 13:30:12.928668 ==
8414 13:30:12.928718 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 13:30:12.928768 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 13:30:12.928832 ==
8417 13:30:12.928881 RX Vref Scan: 0
8418 13:30:12.928945
8419 13:30:12.929024 RX Vref 0 -> 0, step: 1
8420 13:30:12.929101
8421 13:30:12.929191 RX Delay 0 -> 252, step: 8
8422 13:30:12.929241 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8423 13:30:12.929290 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8424 13:30:12.929339 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8425 13:30:12.929394 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8426 13:30:12.929443 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8427 13:30:12.929491 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8428 13:30:12.929539 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8429 13:30:12.929587 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8430 13:30:12.929634 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8431 13:30:12.929682 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8432 13:30:12.929730 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8433 13:30:12.929784 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8434 13:30:12.929832 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8435 13:30:12.929883 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8436 13:30:12.929931 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8437 13:30:12.929979 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8438 13:30:12.930027 ==
8439 13:30:12.930074 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 13:30:12.930145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 13:30:12.930209 ==
8442 13:30:12.930257 DQS Delay:
8443 13:30:12.930305 DQS0 = 0, DQS1 = 0
8444 13:30:12.930353 DQM Delay:
8445 13:30:12.930406 DQM0 = 135, DQM1 = 131
8446 13:30:12.930457 DQ Delay:
8447 13:30:12.930505 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8448 13:30:12.930553 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8449 13:30:12.930600 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8450 13:30:12.930648 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8451 13:30:12.930696
8452 13:30:12.930744
8453 13:30:12.930795 ==
8454 13:30:12.930844 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 13:30:12.930893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 13:30:12.930941 ==
8457 13:30:12.930988
8458 13:30:12.931035
8459 13:30:12.931113 TX Vref Scan disable
8460 13:30:12.931188 == TX Byte 0 ==
8461 13:30:12.931264 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8462 13:30:12.931343 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8463 13:30:12.931419 == TX Byte 1 ==
8464 13:30:12.931525 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8465 13:30:12.931601 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8466 13:30:12.931675 ==
8467 13:30:12.931751 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 13:30:12.931830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 13:30:12.931905 ==
8470 13:30:12.932009
8471 13:30:12.932084 TX Vref early break, caculate TX vref
8472 13:30:12.932159 TX Vref=16, minBit 8, minWin=21, winSum=371
8473 13:30:12.932211 TX Vref=18, minBit 8, minWin=21, winSum=379
8474 13:30:12.932260 TX Vref=20, minBit 6, minWin=23, winSum=390
8475 13:30:12.932308 TX Vref=22, minBit 8, minWin=23, winSum=396
8476 13:30:12.932357 TX Vref=24, minBit 6, minWin=24, winSum=405
8477 13:30:12.932405 TX Vref=26, minBit 9, minWin=24, winSum=416
8478 13:30:12.932453 TX Vref=28, minBit 8, minWin=25, winSum=417
8479 13:30:12.932501 TX Vref=30, minBit 9, minWin=24, winSum=416
8480 13:30:12.932576 TX Vref=32, minBit 0, minWin=24, winSum=406
8481 13:30:12.932643 TX Vref=34, minBit 1, minWin=23, winSum=393
8482 13:30:12.932692 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 28
8483 13:30:12.932769
8484 13:30:12.932816 Final TX Range 0 Vref 28
8485 13:30:12.932865
8486 13:30:12.932913 ==
8487 13:30:12.932960 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 13:30:12.933029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 13:30:12.933107 ==
8490 13:30:12.933193
8491 13:30:12.933242
8492 13:30:12.933290 TX Vref Scan disable
8493 13:30:12.933339 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8494 13:30:12.933391 == TX Byte 0 ==
8495 13:30:12.933442 u2DelayCellOfst[0]=21 cells (6 PI)
8496 13:30:12.933490 u2DelayCellOfst[1]=14 cells (4 PI)
8497 13:30:12.933539 u2DelayCellOfst[2]=0 cells (0 PI)
8498 13:30:12.933593 u2DelayCellOfst[3]=7 cells (2 PI)
8499 13:30:12.933643 u2DelayCellOfst[4]=10 cells (3 PI)
8500 13:30:12.933692 u2DelayCellOfst[5]=17 cells (5 PI)
8501 13:30:12.933741 u2DelayCellOfst[6]=17 cells (5 PI)
8502 13:30:12.933981 u2DelayCellOfst[7]=7 cells (2 PI)
8503 13:30:12.934035 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8504 13:30:12.934084 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8505 13:30:12.934132 == TX Byte 1 ==
8506 13:30:12.934180 u2DelayCellOfst[8]=0 cells (0 PI)
8507 13:30:12.934227 u2DelayCellOfst[9]=3 cells (1 PI)
8508 13:30:12.934276 u2DelayCellOfst[10]=10 cells (3 PI)
8509 13:30:12.934324 u2DelayCellOfst[11]=3 cells (1 PI)
8510 13:30:12.934371 u2DelayCellOfst[12]=14 cells (4 PI)
8511 13:30:12.934439 u2DelayCellOfst[13]=14 cells (4 PI)
8512 13:30:12.934504 u2DelayCellOfst[14]=17 cells (5 PI)
8513 13:30:12.934552 u2DelayCellOfst[15]=17 cells (5 PI)
8514 13:30:12.934600 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8515 13:30:12.934648 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8516 13:30:12.934695 DramC Write-DBI on
8517 13:30:12.934743 ==
8518 13:30:12.934791 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 13:30:12.934847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 13:30:12.934896 ==
8521 13:30:12.934944
8522 13:30:12.934992
8523 13:30:12.935045 TX Vref Scan disable
8524 13:30:12.935093 == TX Byte 0 ==
8525 13:30:12.935141 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8526 13:30:12.935189 == TX Byte 1 ==
8527 13:30:12.935238 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8528 13:30:12.935286 DramC Write-DBI off
8529 13:30:12.935334
8530 13:30:12.935385 [DATLAT]
8531 13:30:12.935461 Freq=1600, CH1 RK0
8532 13:30:12.935567
8533 13:30:12.935642 DATLAT Default: 0xf
8534 13:30:12.935717 0, 0xFFFF, sum = 0
8535 13:30:12.935798 1, 0xFFFF, sum = 0
8536 13:30:12.935876 2, 0xFFFF, sum = 0
8537 13:30:12.935968 3, 0xFFFF, sum = 0
8538 13:30:12.936046 4, 0xFFFF, sum = 0
8539 13:30:12.936143 5, 0xFFFF, sum = 0
8540 13:30:12.936220 6, 0xFFFF, sum = 0
8541 13:30:12.936327 7, 0xFFFF, sum = 0
8542 13:30:12.936404 8, 0xFFFF, sum = 0
8543 13:30:12.936483 9, 0xFFFF, sum = 0
8544 13:30:12.936551 10, 0xFFFF, sum = 0
8545 13:30:12.936602 11, 0xFFFF, sum = 0
8546 13:30:12.936650 12, 0xFFFF, sum = 0
8547 13:30:12.936700 13, 0xFFFF, sum = 0
8548 13:30:12.936748 14, 0x0, sum = 1
8549 13:30:12.936797 15, 0x0, sum = 2
8550 13:30:12.936846 16, 0x0, sum = 3
8551 13:30:12.936894 17, 0x0, sum = 4
8552 13:30:12.936942 best_step = 15
8553 13:30:12.937001
8554 13:30:12.937096 ==
8555 13:30:12.937189 Dram Type= 6, Freq= 0, CH_1, rank 0
8556 13:30:12.937240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8557 13:30:12.937289 ==
8558 13:30:12.937338 RX Vref Scan: 1
8559 13:30:12.937392
8560 13:30:12.937440 Set Vref Range= 24 -> 127
8561 13:30:12.937488
8562 13:30:12.937536 RX Vref 24 -> 127, step: 1
8563 13:30:12.937585
8564 13:30:12.937633 RX Delay 19 -> 252, step: 4
8565 13:30:12.937681
8566 13:30:12.937728 Set Vref, RX VrefLevel [Byte0]: 24
8567 13:30:12.937822 [Byte1]: 24
8568 13:30:12.937871
8569 13:30:12.937956 Set Vref, RX VrefLevel [Byte0]: 25
8570 13:30:12.938005 [Byte1]: 25
8571 13:30:12.938054
8572 13:30:12.938123 Set Vref, RX VrefLevel [Byte0]: 26
8573 13:30:12.938186 [Byte1]: 26
8574 13:30:12.938234
8575 13:30:12.938304 Set Vref, RX VrefLevel [Byte0]: 27
8576 13:30:12.938395 [Byte1]: 27
8577 13:30:12.938445
8578 13:30:12.938523 Set Vref, RX VrefLevel [Byte0]: 28
8579 13:30:12.938611 [Byte1]: 28
8580 13:30:12.938675
8581 13:30:12.938768 Set Vref, RX VrefLevel [Byte0]: 29
8582 13:30:12.938847 [Byte1]: 29
8583 13:30:12.938959
8584 13:30:12.939035 Set Vref, RX VrefLevel [Byte0]: 30
8585 13:30:12.939111 [Byte1]: 30
8586 13:30:12.939226
8587 13:30:12.939337 Set Vref, RX VrefLevel [Byte0]: 31
8588 13:30:12.939431 [Byte1]: 31
8589 13:30:12.939508
8590 13:30:12.939588 Set Vref, RX VrefLevel [Byte0]: 32
8591 13:30:12.939666 [Byte1]: 32
8592 13:30:12.939742
8593 13:30:12.939822 Set Vref, RX VrefLevel [Byte0]: 33
8594 13:30:12.939900 [Byte1]: 33
8595 13:30:12.939976
8596 13:30:12.940053 Set Vref, RX VrefLevel [Byte0]: 34
8597 13:30:12.940130 [Byte1]: 34
8598 13:30:12.940206
8599 13:30:12.940270 Set Vref, RX VrefLevel [Byte0]: 35
8600 13:30:12.940318 [Byte1]: 35
8601 13:30:12.940383
8602 13:30:12.940475 Set Vref, RX VrefLevel [Byte0]: 36
8603 13:30:12.940550 [Byte1]: 36
8604 13:30:12.940654
8605 13:30:12.940729 Set Vref, RX VrefLevel [Byte0]: 37
8606 13:30:12.940821 [Byte1]: 37
8607 13:30:12.940899
8608 13:30:12.940975 Set Vref, RX VrefLevel [Byte0]: 38
8609 13:30:12.941052 [Byte1]: 38
8610 13:30:12.941128
8611 13:30:12.941227 Set Vref, RX VrefLevel [Byte0]: 39
8612 13:30:12.941338 [Byte1]: 39
8613 13:30:12.941415
8614 13:30:12.941519 Set Vref, RX VrefLevel [Byte0]: 40
8615 13:30:12.941594 [Byte1]: 40
8616 13:30:12.941703
8617 13:30:12.941779 Set Vref, RX VrefLevel [Byte0]: 41
8618 13:30:12.941854 [Byte1]: 41
8619 13:30:12.941928
8620 13:30:12.942003 Set Vref, RX VrefLevel [Byte0]: 42
8621 13:30:12.942097 [Byte1]: 42
8622 13:30:12.942162
8623 13:30:12.942210 Set Vref, RX VrefLevel [Byte0]: 43
8624 13:30:12.942287 [Byte1]: 43
8625 13:30:12.942335
8626 13:30:12.942383 Set Vref, RX VrefLevel [Byte0]: 44
8627 13:30:12.942447 [Byte1]: 44
8628 13:30:12.942540
8629 13:30:12.942615 Set Vref, RX VrefLevel [Byte0]: 45
8630 13:30:12.942705 [Byte1]: 45
8631 13:30:12.942801
8632 13:30:12.942881 Set Vref, RX VrefLevel [Byte0]: 46
8633 13:30:12.942956 [Byte1]: 46
8634 13:30:12.943031
8635 13:30:12.943139 Set Vref, RX VrefLevel [Byte0]: 47
8636 13:30:12.943215 [Byte1]: 47
8637 13:30:12.943319
8638 13:30:12.943394 Set Vref, RX VrefLevel [Byte0]: 48
8639 13:30:12.943485 [Byte1]: 48
8640 13:30:12.943552
8641 13:30:12.943615 Set Vref, RX VrefLevel [Byte0]: 49
8642 13:30:12.943664 [Byte1]: 49
8643 13:30:12.943713
8644 13:30:12.943768 Set Vref, RX VrefLevel [Byte0]: 50
8645 13:30:12.943818 [Byte1]: 50
8646 13:30:12.943867
8647 13:30:12.943916 Set Vref, RX VrefLevel [Byte0]: 51
8648 13:30:12.943966 [Byte1]: 51
8649 13:30:12.944015
8650 13:30:12.944063 Set Vref, RX VrefLevel [Byte0]: 52
8651 13:30:12.944119 [Byte1]: 52
8652 13:30:12.944196
8653 13:30:12.944273 Set Vref, RX VrefLevel [Byte0]: 53
8654 13:30:12.944365 [Byte1]: 53
8655 13:30:12.944440
8656 13:30:12.944533 Set Vref, RX VrefLevel [Byte0]: 54
8657 13:30:12.944599 [Byte1]: 54
8658 13:30:12.944647
8659 13:30:12.944708 Set Vref, RX VrefLevel [Byte0]: 55
8660 13:30:12.944770 [Byte1]: 55
8661 13:30:12.944818
8662 13:30:12.944866 Set Vref, RX VrefLevel [Byte0]: 56
8663 13:30:12.944929 [Byte1]: 56
8664 13:30:12.944978
8665 13:30:12.945026 Set Vref, RX VrefLevel [Byte0]: 57
8666 13:30:12.945075 [Byte1]: 57
8667 13:30:12.945124
8668 13:30:12.945199 Set Vref, RX VrefLevel [Byte0]: 58
8669 13:30:12.945439 [Byte1]: 58
8670 13:30:12.945534
8671 13:30:12.945583 Set Vref, RX VrefLevel [Byte0]: 59
8672 13:30:12.945631 [Byte1]: 59
8673 13:30:12.945678
8674 13:30:12.945755 Set Vref, RX VrefLevel [Byte0]: 60
8675 13:30:12.945804 [Byte1]: 60
8676 13:30:12.945867
8677 13:30:12.945915 Set Vref, RX VrefLevel [Byte0]: 61
8678 13:30:12.945963 [Byte1]: 61
8679 13:30:12.946012
8680 13:30:12.946060 Set Vref, RX VrefLevel [Byte0]: 62
8681 13:30:12.946110 [Byte1]: 62
8682 13:30:12.946159
8683 13:30:12.946207 Set Vref, RX VrefLevel [Byte0]: 63
8684 13:30:12.946270 [Byte1]: 63
8685 13:30:12.946318
8686 13:30:12.946365 Set Vref, RX VrefLevel [Byte0]: 64
8687 13:30:12.946411 [Byte1]: 64
8688 13:30:12.946488
8689 13:30:12.946535 Set Vref, RX VrefLevel [Byte0]: 65
8690 13:30:12.946583 [Byte1]: 65
8691 13:30:12.946646
8692 13:30:12.946708 Set Vref, RX VrefLevel [Byte0]: 66
8693 13:30:12.946756 [Byte1]: 66
8694 13:30:12.946818
8695 13:30:12.946881 Set Vref, RX VrefLevel [Byte0]: 67
8696 13:30:12.946929 [Byte1]: 67
8697 13:30:12.946977
8698 13:30:12.947056 Set Vref, RX VrefLevel [Byte0]: 68
8699 13:30:12.947104 [Byte1]: 68
8700 13:30:12.947167
8701 13:30:12.947281 Set Vref, RX VrefLevel [Byte0]: 69
8702 13:30:12.947398 [Byte1]: 69
8703 13:30:12.947463
8704 13:30:12.947511 Set Vref, RX VrefLevel [Byte0]: 70
8705 13:30:12.947579 [Byte1]: 70
8706 13:30:12.947658
8707 13:30:12.947706 Set Vref, RX VrefLevel [Byte0]: 71
8708 13:30:12.947786 [Byte1]: 71
8709 13:30:12.947834
8710 13:30:12.947883 Set Vref, RX VrefLevel [Byte0]: 72
8711 13:30:12.947932 [Byte1]: 72
8712 13:30:12.947980
8713 13:30:12.948028 Set Vref, RX VrefLevel [Byte0]: 73
8714 13:30:12.948077 [Byte1]: 73
8715 13:30:12.948126
8716 13:30:12.948173 Final RX Vref Byte 0 = 57 to rank0
8717 13:30:12.948236 Final RX Vref Byte 1 = 61 to rank0
8718 13:30:12.948312 Final RX Vref Byte 0 = 57 to rank1
8719 13:30:12.948360 Final RX Vref Byte 1 = 61 to rank1==
8720 13:30:12.948408 Dram Type= 6, Freq= 0, CH_1, rank 0
8721 13:30:12.948456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8722 13:30:12.948504 ==
8723 13:30:12.948552 DQS Delay:
8724 13:30:12.948599 DQS0 = 0, DQS1 = 0
8725 13:30:12.948647 DQM Delay:
8726 13:30:12.948709 DQM0 = 132, DQM1 = 130
8727 13:30:12.948758 DQ Delay:
8728 13:30:12.948806 DQ0 =140, DQ1 =130, DQ2 =118, DQ3 =130
8729 13:30:12.948854 DQ4 =128, DQ5 =142, DQ6 =146, DQ7 =126
8730 13:30:12.948917 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =122
8731 13:30:12.948965 DQ12 =140, DQ13 =140, DQ14 =138, DQ15 =140
8732 13:30:12.949013
8733 13:30:12.949060
8734 13:30:12.949122
8735 13:30:12.949195 [DramC_TX_OE_Calibration] TA2
8736 13:30:12.949244 Original DQ_B0 (3 6) =30, OEN = 27
8737 13:30:12.949293 Original DQ_B1 (3 6) =30, OEN = 27
8738 13:30:12.949340 24, 0x0, End_B0=24 End_B1=24
8739 13:30:12.949390 25, 0x0, End_B0=25 End_B1=25
8740 13:30:12.949440 26, 0x0, End_B0=26 End_B1=26
8741 13:30:12.949489 27, 0x0, End_B0=27 End_B1=27
8742 13:30:12.949552 28, 0x0, End_B0=28 End_B1=28
8743 13:30:12.949616 29, 0x0, End_B0=29 End_B1=29
8744 13:30:12.949664 30, 0x0, End_B0=30 End_B1=30
8745 13:30:12.949712 31, 0x4141, End_B0=30 End_B1=30
8746 13:30:12.949761 Byte0 end_step=30 best_step=27
8747 13:30:12.949810 Byte1 end_step=30 best_step=27
8748 13:30:12.949857 Byte0 TX OE(2T, 0.5T) = (3, 3)
8749 13:30:12.949905 Byte1 TX OE(2T, 0.5T) = (3, 3)
8750 13:30:12.949952
8751 13:30:12.950016
8752 13:30:12.950078 [DQSOSCAuto] RK0, (LSB)MR18= 0xa14, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
8753 13:30:12.950128 CH1 RK0: MR19=303, MR18=A14
8754 13:30:12.950175 CH1_RK0: MR19=0x303, MR18=0xA14, DQSOSC=399, MR23=63, INC=23, DEC=15
8755 13:30:12.950223
8756 13:30:12.950271 ----->DramcWriteLeveling(PI) begin...
8757 13:30:12.950320 ==
8758 13:30:12.950368 Dram Type= 6, Freq= 0, CH_1, rank 1
8759 13:30:12.950434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8760 13:30:12.950513 ==
8761 13:30:12.950562 Write leveling (Byte 0): 25 => 25
8762 13:30:12.950611 Write leveling (Byte 1): 26 => 26
8763 13:30:12.950701 DramcWriteLeveling(PI) end<-----
8764 13:30:12.950748
8765 13:30:12.950795 ==
8766 13:30:12.950843 Dram Type= 6, Freq= 0, CH_1, rank 1
8767 13:30:12.950907 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8768 13:30:12.950969 ==
8769 13:30:12.951017 [Gating] SW mode calibration
8770 13:30:12.951065 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8771 13:30:12.951114 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8772 13:30:12.951162 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 13:30:12.951210 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 13:30:12.951258 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8775 13:30:12.951306 1 4 12 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8776 13:30:12.951353 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 13:30:12.951401 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 13:30:12.951449 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 13:30:12.951498 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 13:30:12.951546 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 13:30:12.951594 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8782 13:30:12.951641 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8783 13:30:12.951690 1 5 12 | B1->B0 | 3434 2323 | 0 0 | (0 1) (1 0)
8784 13:30:12.951737 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8785 13:30:12.951785 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 13:30:12.951833 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 13:30:12.951880 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 13:30:12.951928 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 13:30:12.951976 1 6 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8790 13:30:12.952023 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8791 13:30:12.952069 1 6 12 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
8792 13:30:12.952116 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 13:30:12.952180 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 13:30:12.952229 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 13:30:12.952279 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 13:30:12.952517 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 13:30:12.952623 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 13:30:12.952735 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8799 13:30:12.952785 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8800 13:30:12.952834 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8801 13:30:12.952882 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 13:30:12.952967 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 13:30:12.953042 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 13:30:12.953118 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 13:30:12.953221 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 13:30:12.953271 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 13:30:12.953320 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 13:30:12.953368 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 13:30:12.953416 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 13:30:12.953470 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 13:30:12.953520 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 13:30:12.953569 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 13:30:12.953617 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 13:30:12.953665 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8815 13:30:12.953714 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8816 13:30:12.953762 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8817 13:30:12.953810 Total UI for P1: 0, mck2ui 16
8818 13:30:12.953863 best dqsien dly found for B0: ( 1, 9, 10)
8819 13:30:12.953913 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 13:30:12.953961 Total UI for P1: 0, mck2ui 16
8821 13:30:12.954009 best dqsien dly found for B1: ( 1, 9, 12)
8822 13:30:12.954056 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8823 13:30:12.954104 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8824 13:30:12.954152
8825 13:30:12.954203 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8826 13:30:12.954253 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8827 13:30:12.954302 [Gating] SW calibration Done
8828 13:30:12.954350 ==
8829 13:30:12.954398 Dram Type= 6, Freq= 0, CH_1, rank 1
8830 13:30:12.954447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8831 13:30:12.954495 ==
8832 13:30:12.954542 RX Vref Scan: 0
8833 13:30:12.954590
8834 13:30:12.954638 RX Vref 0 -> 0, step: 1
8835 13:30:12.954691
8836 13:30:12.954739 RX Delay 0 -> 252, step: 8
8837 13:30:12.954788 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8838 13:30:12.954836 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8839 13:30:12.954884 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8840 13:30:12.954932 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8841 13:30:12.954979 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8842 13:30:12.955031 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8843 13:30:12.955090 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8844 13:30:12.955140 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8845 13:30:12.955188 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8846 13:30:12.955235 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8847 13:30:12.955283 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8848 13:30:12.955331 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8849 13:30:12.955379 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8850 13:30:12.955432 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8851 13:30:12.955482 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8852 13:30:12.955529 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8853 13:30:12.955577 ==
8854 13:30:12.955641 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 13:30:12.955717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 13:30:12.955810 ==
8857 13:30:12.955965 DQS Delay:
8858 13:30:12.956040 DQS0 = 0, DQS1 = 0
8859 13:30:12.956114 DQM Delay:
8860 13:30:12.956191 DQM0 = 136, DQM1 = 130
8861 13:30:12.956242 DQ Delay:
8862 13:30:12.956291 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =135
8863 13:30:12.956340 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =135
8864 13:30:12.956392 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8865 13:30:12.956442 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8866 13:30:12.956490
8867 13:30:12.956537
8868 13:30:12.956584 ==
8869 13:30:12.956632 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 13:30:12.956679 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 13:30:12.956727 ==
8872 13:30:12.956780
8873 13:30:12.956855
8874 13:30:12.956929 TX Vref Scan disable
8875 13:30:12.957004 == TX Byte 0 ==
8876 13:30:12.957080 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8877 13:30:12.957161 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8878 13:30:12.957218 == TX Byte 1 ==
8879 13:30:12.957268 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8880 13:30:12.957316 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8881 13:30:12.957364 ==
8882 13:30:12.957412 Dram Type= 6, Freq= 0, CH_1, rank 1
8883 13:30:12.957460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8884 13:30:12.957509 ==
8885 13:30:12.957582
8886 13:30:12.957651 TX Vref early break, caculate TX vref
8887 13:30:12.957700 TX Vref=16, minBit 9, minWin=22, winSum=381
8888 13:30:12.957766 TX Vref=18, minBit 9, minWin=22, winSum=385
8889 13:30:12.957837 TX Vref=20, minBit 9, minWin=22, winSum=397
8890 13:30:12.957887 TX Vref=22, minBit 1, minWin=24, winSum=404
8891 13:30:12.957935 TX Vref=24, minBit 9, minWin=23, winSum=410
8892 13:30:12.957984 TX Vref=26, minBit 9, minWin=24, winSum=421
8893 13:30:12.958032 TX Vref=28, minBit 5, minWin=25, winSum=420
8894 13:30:12.958081 TX Vref=30, minBit 8, minWin=25, winSum=417
8895 13:30:12.958130 TX Vref=32, minBit 0, minWin=24, winSum=410
8896 13:30:12.958178 TX Vref=34, minBit 9, minWin=23, winSum=399
8897 13:30:12.958234 TX Vref=36, minBit 9, minWin=22, winSum=390
8898 13:30:12.958283 [TxChooseVref] Worse bit 5, Min win 25, Win sum 420, Final Vref 28
8899 13:30:12.958332
8900 13:30:12.958379 Final TX Range 0 Vref 28
8901 13:30:12.958427
8902 13:30:12.958475 ==
8903 13:30:12.958522 Dram Type= 6, Freq= 0, CH_1, rank 1
8904 13:30:12.958574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8905 13:30:12.958625 ==
8906 13:30:12.958673
8907 13:30:12.958720
8908 13:30:12.958767 TX Vref Scan disable
8909 13:30:12.958815 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8910 13:30:12.958863 == TX Byte 0 ==
8911 13:30:12.958911 u2DelayCellOfst[0]=17 cells (5 PI)
8912 13:30:12.958989 u2DelayCellOfst[1]=10 cells (3 PI)
8913 13:30:12.959065 u2DelayCellOfst[2]=0 cells (0 PI)
8914 13:30:12.959141 u2DelayCellOfst[3]=7 cells (2 PI)
8915 13:30:12.959405 u2DelayCellOfst[4]=7 cells (2 PI)
8916 13:30:12.959485 u2DelayCellOfst[5]=17 cells (5 PI)
8917 13:30:12.959561 u2DelayCellOfst[6]=17 cells (5 PI)
8918 13:30:12.959636 u2DelayCellOfst[7]=7 cells (2 PI)
8919 13:30:12.959711 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8920 13:30:12.959763 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8921 13:30:12.959812 == TX Byte 1 ==
8922 13:30:12.959860 u2DelayCellOfst[8]=0 cells (0 PI)
8923 13:30:12.959908 u2DelayCellOfst[9]=3 cells (1 PI)
8924 13:30:12.959962 u2DelayCellOfst[10]=10 cells (3 PI)
8925 13:30:12.960012 u2DelayCellOfst[11]=3 cells (1 PI)
8926 13:30:12.960061 u2DelayCellOfst[12]=14 cells (4 PI)
8927 13:30:12.960109 u2DelayCellOfst[13]=17 cells (5 PI)
8928 13:30:12.960157 u2DelayCellOfst[14]=17 cells (5 PI)
8929 13:30:12.960206 u2DelayCellOfst[15]=14 cells (4 PI)
8930 13:30:12.960255 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8931 13:30:12.960303 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8932 13:30:12.960351 DramC Write-DBI on
8933 13:30:12.960398 ==
8934 13:30:12.960476 Dram Type= 6, Freq= 0, CH_1, rank 1
8935 13:30:12.960556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8936 13:30:12.960632 ==
8937 13:30:12.960697
8938 13:30:12.960772
8939 13:30:12.960847 TX Vref Scan disable
8940 13:30:12.960922 == TX Byte 0 ==
8941 13:30:12.960997 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8942 13:30:12.961073 == TX Byte 1 ==
8943 13:30:12.961185 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8944 13:30:12.961237 DramC Write-DBI off
8945 13:30:12.961286
8946 13:30:12.961333 [DATLAT]
8947 13:30:12.961381 Freq=1600, CH1 RK1
8948 13:30:12.961428
8949 13:30:12.961477 DATLAT Default: 0xf
8950 13:30:12.961525 0, 0xFFFF, sum = 0
8951 13:30:12.961583 1, 0xFFFF, sum = 0
8952 13:30:12.961632 2, 0xFFFF, sum = 0
8953 13:30:12.961682 3, 0xFFFF, sum = 0
8954 13:30:12.961731 4, 0xFFFF, sum = 0
8955 13:30:12.961780 5, 0xFFFF, sum = 0
8956 13:30:12.961829 6, 0xFFFF, sum = 0
8957 13:30:12.961878 7, 0xFFFF, sum = 0
8958 13:30:12.961930 8, 0xFFFF, sum = 0
8959 13:30:12.961981 9, 0xFFFF, sum = 0
8960 13:30:12.962030 10, 0xFFFF, sum = 0
8961 13:30:12.962079 11, 0xFFFF, sum = 0
8962 13:30:12.962131 12, 0xFFFF, sum = 0
8963 13:30:12.962182 13, 0xFFFF, sum = 0
8964 13:30:12.962231 14, 0x0, sum = 1
8965 13:30:12.962279 15, 0x0, sum = 2
8966 13:30:12.962328 16, 0x0, sum = 3
8967 13:30:12.962377 17, 0x0, sum = 4
8968 13:30:12.962425 best_step = 15
8969 13:30:12.962473
8970 13:30:12.962524 ==
8971 13:30:12.962572 Dram Type= 6, Freq= 0, CH_1, rank 1
8972 13:30:12.962620 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8973 13:30:12.962669 ==
8974 13:30:12.962717 RX Vref Scan: 0
8975 13:30:12.962765
8976 13:30:12.962812 RX Vref 0 -> 0, step: 1
8977 13:30:12.962860
8978 13:30:12.962907 RX Delay 11 -> 252, step: 4
8979 13:30:12.962956 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8980 13:30:12.963011 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8981 13:30:12.963059 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8982 13:30:12.963107 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8983 13:30:12.963154 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8984 13:30:12.963202 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8985 13:30:12.963264 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8986 13:30:12.963313 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8987 13:30:12.963365 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8988 13:30:12.963416 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8989 13:30:12.963465 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8990 13:30:12.963514 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8991 13:30:12.963586 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8992 13:30:12.963664 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8993 13:30:12.963742 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8994 13:30:12.963819 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8995 13:30:12.963895 ==
8996 13:30:12.963976 Dram Type= 6, Freq= 0, CH_1, rank 1
8997 13:30:12.964055 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8998 13:30:12.964137 ==
8999 13:30:12.964214 DQS Delay:
9000 13:30:12.964290 DQS0 = 0, DQS1 = 0
9001 13:30:12.964366 DQM Delay:
9002 13:30:12.964423 DQM0 = 132, DQM1 = 127
9003 13:30:12.964473 DQ Delay:
9004 13:30:12.964522 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
9005 13:30:12.964572 DQ4 =130, DQ5 =144, DQ6 =142, DQ7 =130
9006 13:30:12.964628 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
9007 13:30:12.964710 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
9008 13:30:12.964791
9009 13:30:12.964868
9010 13:30:12.964944
9011 13:30:12.965024 [DramC_TX_OE_Calibration] TA2
9012 13:30:12.965102 Original DQ_B0 (3 6) =30, OEN = 27
9013 13:30:14.072765 Original DQ_B1 (3 6) =30, OEN = 27
9014 13:30:14.072886 24, 0x0, End_B0=24 End_B1=24
9015 13:30:14.072947 25, 0x0, End_B0=25 End_B1=25
9016 13:30:14.073003 26, 0x0, End_B0=26 End_B1=26
9017 13:30:14.073056 27, 0x0, End_B0=27 End_B1=27
9018 13:30:14.073108 28, 0x0, End_B0=28 End_B1=28
9019 13:30:14.073196 29, 0x0, End_B0=29 End_B1=29
9020 13:30:14.073247 30, 0x0, End_B0=30 End_B1=30
9021 13:30:14.073297 31, 0x4545, End_B0=30 End_B1=30
9022 13:30:14.073348 Byte0 end_step=30 best_step=27
9023 13:30:14.073396 Byte1 end_step=30 best_step=27
9024 13:30:14.073445 Byte0 TX OE(2T, 0.5T) = (3, 3)
9025 13:30:14.073494 Byte1 TX OE(2T, 0.5T) = (3, 3)
9026 13:30:14.073543
9027 13:30:14.073591
9028 13:30:14.073640 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 402 ps
9029 13:30:14.073690 CH1 RK1: MR19=303, MR18=F1E
9030 13:30:14.073772 CH1_RK1: MR19=0x303, MR18=0xF1E, DQSOSC=394, MR23=63, INC=23, DEC=15
9031 13:30:14.073852 [RxdqsGatingPostProcess] freq 1600
9032 13:30:14.073902 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9033 13:30:14.073951 best DQS0 dly(2T, 0.5T) = (1, 1)
9034 13:30:14.074000 best DQS1 dly(2T, 0.5T) = (1, 1)
9035 13:30:14.074049 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9036 13:30:14.074097 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9037 13:30:14.074144 best DQS0 dly(2T, 0.5T) = (1, 1)
9038 13:30:14.074192 best DQS1 dly(2T, 0.5T) = (1, 1)
9039 13:30:14.074240 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9040 13:30:14.074319 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9041 13:30:14.074366 Pre-setting of DQS Precalculation
9042 13:30:14.074414 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9043 13:30:14.074463 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9044 13:30:14.074511 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9045 13:30:14.074560
9046 13:30:14.074607
9047 13:30:14.074654 [Calibration Summary] 3200 Mbps
9048 13:30:14.074702 CH 0, Rank 0
9049 13:30:14.074750 SW Impedance : PASS
9050 13:30:14.074798 DUTY Scan : NO K
9051 13:30:14.074876 ZQ Calibration : PASS
9052 13:30:14.075125 Jitter Meter : NO K
9053 13:30:14.075179 CBT Training : PASS
9054 13:30:14.075228 Write leveling : PASS
9055 13:30:14.075276 RX DQS gating : PASS
9056 13:30:14.075323 RX DQ/DQS(RDDQC) : PASS
9057 13:30:14.075406 TX DQ/DQS : PASS
9058 13:30:14.075521 RX DATLAT : PASS
9059 13:30:14.075569 RX DQ/DQS(Engine): PASS
9060 13:30:14.075617 TX OE : PASS
9061 13:30:14.075664 All Pass.
9062 13:30:14.075712
9063 13:30:14.075760 CH 0, Rank 1
9064 13:30:14.075825 SW Impedance : PASS
9065 13:30:14.075888 DUTY Scan : NO K
9066 13:30:14.075934 ZQ Calibration : PASS
9067 13:30:14.075983 Jitter Meter : NO K
9068 13:30:14.076031 CBT Training : PASS
9069 13:30:14.076079 Write leveling : PASS
9070 13:30:14.076126 RX DQS gating : PASS
9071 13:30:14.076173 RX DQ/DQS(RDDQC) : PASS
9072 13:30:14.076220 TX DQ/DQS : PASS
9073 13:30:14.076268 RX DATLAT : PASS
9074 13:30:14.076316 RX DQ/DQS(Engine): PASS
9075 13:30:14.076363 TX OE : PASS
9076 13:30:14.076410 All Pass.
9077 13:30:14.076458
9078 13:30:14.076505 CH 1, Rank 0
9079 13:30:14.076553 SW Impedance : PASS
9080 13:30:14.076600 DUTY Scan : NO K
9081 13:30:14.076647 ZQ Calibration : PASS
9082 13:30:14.076694 Jitter Meter : NO K
9083 13:30:14.076742 CBT Training : PASS
9084 13:30:14.076790 Write leveling : PASS
9085 13:30:14.076837 RX DQS gating : PASS
9086 13:30:14.076884 RX DQ/DQS(RDDQC) : PASS
9087 13:30:14.076932 TX DQ/DQS : PASS
9088 13:30:14.076979 RX DATLAT : PASS
9089 13:30:14.077027 RX DQ/DQS(Engine): PASS
9090 13:30:14.077074 TX OE : PASS
9091 13:30:14.077122 All Pass.
9092 13:30:14.077206
9093 13:30:14.077254 CH 1, Rank 1
9094 13:30:14.077301 SW Impedance : PASS
9095 13:30:14.077348 DUTY Scan : NO K
9096 13:30:14.077396 ZQ Calibration : PASS
9097 13:30:14.077444 Jitter Meter : NO K
9098 13:30:14.077492 CBT Training : PASS
9099 13:30:14.077540 Write leveling : PASS
9100 13:30:14.077589 RX DQS gating : PASS
9101 13:30:14.077637 RX DQ/DQS(RDDQC) : PASS
9102 13:30:14.077685 TX DQ/DQS : PASS
9103 13:30:14.077734 RX DATLAT : PASS
9104 13:30:14.077781 RX DQ/DQS(Engine): PASS
9105 13:30:14.077829 TX OE : PASS
9106 13:30:14.077877 All Pass.
9107 13:30:14.077924
9108 13:30:14.077972 DramC Write-DBI on
9109 13:30:14.078021 PER_BANK_REFRESH: Hybrid Mode
9110 13:30:14.078069 TX_TRACKING: ON
9111 13:30:14.078117 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9112 13:30:14.078167 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9113 13:30:14.078217 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9114 13:30:14.078265 [FAST_K] Save calibration result to emmc
9115 13:30:14.078313 sync common calibartion params.
9116 13:30:14.078362 sync cbt_mode0:1, 1:1
9117 13:30:14.078410 dram_init: ddr_geometry: 2
9118 13:30:14.078458 dram_init: ddr_geometry: 2
9119 13:30:14.078507 dram_init: ddr_geometry: 2
9120 13:30:14.078554 0:dram_rank_size:100000000
9121 13:30:14.078603 1:dram_rank_size:100000000
9122 13:30:14.078653 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9123 13:30:14.078702 DFS_SHUFFLE_HW_MODE: ON
9124 13:30:14.078750 dramc_set_vcore_voltage set vcore to 725000
9125 13:30:14.078798 Read voltage for 1600, 0
9126 13:30:14.078847 Vio18 = 0
9127 13:30:14.078894 Vcore = 725000
9128 13:30:14.078942 Vdram = 0
9129 13:30:14.078990 Vddq = 0
9130 13:30:14.079037 Vmddr = 0
9131 13:30:14.079085 switch to 3200 Mbps bootup
9132 13:30:14.079133 [DramcRunTimeConfig]
9133 13:30:14.079181 PHYPLL
9134 13:30:14.079229 DPM_CONTROL_AFTERK: ON
9135 13:30:14.079276 PER_BANK_REFRESH: ON
9136 13:30:14.079324 REFRESH_OVERHEAD_REDUCTION: ON
9137 13:30:14.079372 CMD_PICG_NEW_MODE: OFF
9138 13:30:14.079421 XRTWTW_NEW_MODE: ON
9139 13:30:14.079468 XRTRTR_NEW_MODE: ON
9140 13:30:14.079516 TX_TRACKING: ON
9141 13:30:14.079563 RDSEL_TRACKING: OFF
9142 13:30:14.079611 DQS Precalculation for DVFS: ON
9143 13:30:14.079660 RX_TRACKING: OFF
9144 13:30:14.079707 HW_GATING DBG: ON
9145 13:30:14.079755 ZQCS_ENABLE_LP4: ON
9146 13:30:14.079803 RX_PICG_NEW_MODE: ON
9147 13:30:14.079851 TX_PICG_NEW_MODE: ON
9148 13:30:14.079900 ENABLE_RX_DCM_DPHY: ON
9149 13:30:14.079948 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9150 13:30:14.079995 DUMMY_READ_FOR_TRACKING: OFF
9151 13:30:14.080044 !!! SPM_CONTROL_AFTERK: OFF
9152 13:30:14.080097 !!! SPM could not control APHY
9153 13:30:14.080146 IMPEDANCE_TRACKING: ON
9154 13:30:14.080194 TEMP_SENSOR: ON
9155 13:30:14.080241 HW_SAVE_FOR_SR: OFF
9156 13:30:14.080289 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9157 13:30:14.080338 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9158 13:30:14.080386 Read ODT Tracking: ON
9159 13:30:14.080434 Refresh Rate DeBounce: ON
9160 13:30:14.080482 DFS_NO_QUEUE_FLUSH: ON
9161 13:30:14.080530 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9162 13:30:14.080579 ENABLE_DFS_RUNTIME_MRW: OFF
9163 13:30:14.080627 DDR_RESERVE_NEW_MODE: ON
9164 13:30:14.080675 MR_CBT_SWITCH_FREQ: ON
9165 13:30:14.080722 =========================
9166 13:30:14.080772 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9167 13:30:14.080820 dram_init: ddr_geometry: 2
9168 13:30:14.080868 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9169 13:30:14.080918 dram_init: dram init end (result: 0)
9170 13:30:14.080966 DRAM-K: Full calibration passed in 24388 msecs
9171 13:30:14.081015 MRC: failed to locate region type 0.
9172 13:30:14.081063 DRAM rank0 size:0x100000000,
9173 13:30:14.081112 DRAM rank1 size=0x100000000
9174 13:30:14.081198 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9175 13:30:14.081249 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9176 13:30:14.081298 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9177 13:30:14.081347 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9178 13:30:14.081396 DRAM rank0 size:0x100000000,
9179 13:30:14.081445 DRAM rank1 size=0x100000000
9180 13:30:14.081493 CBMEM:
9181 13:30:14.081541 IMD: root @ 0xfffff000 254 entries.
9182 13:30:14.081589 IMD: root @ 0xffffec00 62 entries.
9183 13:30:14.081638 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9184 13:30:14.081687 WARNING: RO_VPD is uninitialized or empty.
9185 13:30:14.081736 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9186 13:30:14.081784 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9187 13:30:14.081834 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9188 13:30:14.081882 BS: romstage times (exec / console): total (unknown) / 23923 ms
9189 13:30:14.081931
9190 13:30:14.081978
9191 13:30:14.082252 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9192 13:30:14.082307 ARM64: Exception handlers installed.
9193 13:30:14.082356 ARM64: Testing exception
9194 13:30:14.082434 ARM64: Done test exception
9195 13:30:14.082482 Enumerating buses...
9196 13:30:14.082530 Show all devs... Before device enumeration.
9197 13:30:14.082593 Root Device: enabled 1
9198 13:30:14.082655 CPU_CLUSTER: 0: enabled 1
9199 13:30:14.082703 CPU: 00: enabled 1
9200 13:30:14.082751 Compare with tree...
9201 13:30:14.082838 Root Device: enabled 1
9202 13:30:14.082886 CPU_CLUSTER: 0: enabled 1
9203 13:30:14.082934 CPU: 00: enabled 1
9204 13:30:14.082983 Root Device scanning...
9205 13:30:14.083031 scan_static_bus for Root Device
9206 13:30:14.083079 CPU_CLUSTER: 0 enabled
9207 13:30:14.083127 scan_static_bus for Root Device done
9208 13:30:14.083175 scan_bus: bus Root Device finished in 8 msecs
9209 13:30:14.083222 done
9210 13:30:14.083269 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9211 13:30:14.083318 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9212 13:30:14.083367 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9213 13:30:14.083415 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9214 13:30:14.083463 Allocating resources...
9215 13:30:14.083511 Reading resources...
9216 13:30:14.083558 Root Device read_resources bus 0 link: 0
9217 13:30:14.083606 DRAM rank0 size:0x100000000,
9218 13:30:14.083653 DRAM rank1 size=0x100000000
9219 13:30:14.083701 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9220 13:30:14.083750 CPU: 00 missing read_resources
9221 13:30:14.083798 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9222 13:30:14.083847 Root Device read_resources bus 0 link: 0 done
9223 13:30:14.083895 Done reading resources.
9224 13:30:14.083943 Show resources in subtree (Root Device)...After reading.
9225 13:30:14.083992 Root Device child on link 0 CPU_CLUSTER: 0
9226 13:30:14.084041 CPU_CLUSTER: 0 child on link 0 CPU: 00
9227 13:30:14.084089 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9228 13:30:14.084138 CPU: 00
9229 13:30:14.084187 Root Device assign_resources, bus 0 link: 0
9230 13:30:14.084235 CPU_CLUSTER: 0 missing set_resources
9231 13:30:14.084283 Root Device assign_resources, bus 0 link: 0 done
9232 13:30:14.084331 Done setting resources.
9233 13:30:14.084379 Show resources in subtree (Root Device)...After assigning values.
9234 13:30:14.084428 Root Device child on link 0 CPU_CLUSTER: 0
9235 13:30:14.084476 CPU_CLUSTER: 0 child on link 0 CPU: 00
9236 13:30:14.084525 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9237 13:30:14.084575 CPU: 00
9238 13:30:14.084623 Done allocating resources.
9239 13:30:14.084671 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9240 13:30:14.084720 Enabling resources...
9241 13:30:14.084768 done.
9242 13:30:14.084817 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9243 13:30:14.084866 Initializing devices...
9244 13:30:14.084914 Root Device init
9245 13:30:14.084961 init hardware done!
9246 13:30:14.085009 0x00000018: ctrlr->caps
9247 13:30:14.085058 52.000 MHz: ctrlr->f_max
9248 13:30:14.085108 0.400 MHz: ctrlr->f_min
9249 13:30:14.085178 0x40ff8080: ctrlr->voltages
9250 13:30:14.085243 sclk: 390625
9251 13:30:14.085291 Bus Width = 1
9252 13:30:14.085339 sclk: 390625
9253 13:30:14.085386 Bus Width = 1
9254 13:30:14.085434 Early init status = 3
9255 13:30:14.085482 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9256 13:30:14.085532 in-header: 03 fc 00 00 01 00 00 00
9257 13:30:14.085580 in-data: 00
9258 13:30:14.085628 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9259 13:30:14.085677 in-header: 03 fd 00 00 00 00 00 00
9260 13:30:14.085725 in-data:
9261 13:30:14.085773 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9262 13:30:14.085822 in-header: 03 fc 00 00 01 00 00 00
9263 13:30:14.085870 in-data: 00
9264 13:30:14.085919 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9265 13:30:14.085968 in-header: 03 fd 00 00 00 00 00 00
9266 13:30:14.086017 in-data:
9267 13:30:14.086064 [SSUSB] Setting up USB HOST controller...
9268 13:30:14.086113 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9269 13:30:14.086161 [SSUSB] phy power-on done.
9270 13:30:14.086210 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9271 13:30:14.086259 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9272 13:30:14.086307 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9273 13:30:14.086356 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9274 13:30:14.086405 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9275 13:30:14.086454 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9276 13:30:14.086503 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9277 13:30:14.086551 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9278 13:30:14.086600 SPM: binary array size = 0x9dc
9279 13:30:14.086648 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9280 13:30:14.086696 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9281 13:30:14.086744 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9282 13:30:14.086793 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9283 13:30:14.086842 configure_display: Starting display init
9284 13:30:14.086890 anx7625_power_on_init: Init interface.
9285 13:30:14.086939 anx7625_disable_pd_protocol: Disabled PD feature.
9286 13:30:14.086987 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9287 13:30:14.087036 anx7625_start_dp_work: Secure OCM version=00
9288 13:30:14.087084 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9289 13:30:14.087132 sp_tx_get_edid_block: EDID Block = 1
9290 13:30:14.087180 Extracted contents:
9291 13:30:14.087228 header: 00 ff ff ff ff ff ff 00
9292 13:30:14.087276 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9293 13:30:14.087324 version: 01 04
9294 13:30:14.087573 basic params: 95 1f 11 78 0a
9295 13:30:14.087627 chroma info: 76 90 94 55 54 90 27 21 50 54
9296 13:30:14.087677 established: 00 00 00
9297 13:30:14.087726 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9298 13:30:14.087776 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9299 13:30:14.087826 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9300 13:30:14.087874 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9301 13:30:14.087940 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9302 13:30:14.088003 extensions: 00
9303 13:30:14.088051 checksum: fb
9304 13:30:14.088099
9305 13:30:14.088147 Manufacturer: IVO Model 57d Serial Number 0
9306 13:30:14.088196 Made week 0 of 2020
9307 13:30:14.088244 EDID version: 1.4
9308 13:30:14.088292 Digital display
9309 13:30:14.088340 6 bits per primary color channel
9310 13:30:14.088389 DisplayPort interface
9311 13:30:14.088438 Maximum image size: 31 cm x 17 cm
9312 13:30:14.088486 Gamma: 220%
9313 13:30:14.088534 Check DPMS levels
9314 13:30:14.088581 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9315 13:30:14.088629 First detailed timing is preferred timing
9316 13:30:14.088678 Established timings supported:
9317 13:30:14.088725 Standard timings supported:
9318 13:30:14.088773 Detailed timings
9319 13:30:14.088821 Hex of detail: 383680a07038204018303c0035ae10000019
9320 13:30:14.088870 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9321 13:30:14.088918 0780 0798 07c8 0820 hborder 0
9322 13:30:14.088967 0438 043b 0447 0458 vborder 0
9323 13:30:14.089015 -hsync -vsync
9324 13:30:14.089062 Did detailed timing
9325 13:30:14.089111 Hex of detail: 000000000000000000000000000000000000
9326 13:30:14.089185 Manufacturer-specified data, tag 0
9327 13:30:14.089249 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9328 13:30:14.089298 ASCII string: InfoVision
9329 13:30:14.089346 Hex of detail: 000000fe00523134304e574635205248200a
9330 13:30:14.089394 ASCII string: R140NWF5 RH
9331 13:30:14.089442 Checksum
9332 13:30:14.089490 Checksum: 0xfb (valid)
9333 13:30:14.089538 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9334 13:30:14.089586 DSI data_rate: 832800000 bps
9335 13:30:14.089634 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9336 13:30:14.089682 anx7625_parse_edid: pixelclock(138800).
9337 13:30:14.089730 hactive(1920), hsync(48), hfp(24), hbp(88)
9338 13:30:14.089778 vactive(1080), vsync(12), vfp(3), vbp(17)
9339 13:30:14.089827 anx7625_dsi_config: config dsi.
9340 13:30:14.089876 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9341 13:30:14.089926 anx7625_dsi_config: success to config DSI
9342 13:30:14.089974 anx7625_dp_start: MIPI phy setup OK.
9343 13:30:14.090021 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9344 13:30:14.090069 mtk_ddp_mode_set invalid vrefresh 60
9345 13:30:14.090117 main_disp_path_setup
9346 13:30:14.090165 ovl_layer_smi_id_en
9347 13:30:14.090213 ovl_layer_smi_id_en
9348 13:30:14.090261 ccorr_config
9349 13:30:14.090308 aal_config
9350 13:30:14.090356 gamma_config
9351 13:30:14.090403 postmask_config
9352 13:30:14.090450 dither_config
9353 13:30:14.090498 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9354 13:30:14.090548 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9355 13:30:14.090597 Root Device init finished in 552 msecs
9356 13:30:14.090645 CPU_CLUSTER: 0 init
9357 13:30:14.090693 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9358 13:30:14.090743 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9359 13:30:14.090791 APU_MBOX 0x190000b0 = 0x10001
9360 13:30:14.090839 APU_MBOX 0x190001b0 = 0x10001
9361 13:30:14.090887 APU_MBOX 0x190005b0 = 0x10001
9362 13:30:14.090935 APU_MBOX 0x190006b0 = 0x10001
9363 13:30:14.090983 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9364 13:30:14.091033 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9365 13:30:14.091081 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9366 13:30:14.091130 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9367 13:30:14.091179 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9368 13:30:14.091228 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9369 13:30:14.091279 CPU_CLUSTER: 0 init finished in 81 msecs
9370 13:30:14.091326 Devices initialized
9371 13:30:14.091374 Show all devs... After init.
9372 13:30:14.091422 Root Device: enabled 1
9373 13:30:14.091470 CPU_CLUSTER: 0: enabled 1
9374 13:30:14.091517 CPU: 00: enabled 1
9375 13:30:14.091565 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9376 13:30:14.091613 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9377 13:30:14.091660 ELOG: NV offset 0x57f000 size 0x1000
9378 13:30:14.091708 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9379 13:30:14.091755 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9380 13:30:14.091802 ELOG: Event(17) added with size 13 at 2024-07-18 13:30:09 UTC
9381 13:30:14.091850 out: cmd=0x121: 03 db 21 01 00 00 00 00
9382 13:30:14.091898 in-header: 03 ff 00 00 2c 00 00 00
9383 13:30:14.091947 in-data: 3e 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9384 13:30:14.091995 ELOG: Event(A1) added with size 10 at 2024-07-18 13:30:09 UTC
9385 13:30:14.092043 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9386 13:30:14.092091 ELOG: Event(A0) added with size 9 at 2024-07-18 13:30:09 UTC
9387 13:30:14.092139 elog_add_boot_reason: Logged dev mode boot
9388 13:30:14.092186 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9389 13:30:14.092234 Finalize devices...
9390 13:30:14.092282 Devices finalized
9391 13:30:14.092330 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9392 13:30:14.092569 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9393 13:30:14.092623 in-header: 03 07 00 00 08 00 00 00
9394 13:30:14.092672 in-data: aa e4 47 04 13 02 00 00
9395 13:30:14.092720 Chrome EC: UHEPI supported
9396 13:30:14.092768 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9397 13:30:14.092817 in-header: 03 a9 00 00 08 00 00 00
9398 13:30:14.092864 in-data: 84 60 60 08 00 00 00 00
9399 13:30:14.092912 ELOG: Event(91) added with size 10 at 2024-07-18 13:30:09 UTC
9400 13:30:14.092961 Chrome EC: clear events_b mask to 0x0000000020004000
9401 13:30:14.093009 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9402 13:30:14.093057 in-header: 03 fd 00 00 00 00 00 00
9403 13:30:14.093106 in-data:
9404 13:30:14.093179 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9405 13:30:14.093243 Writing coreboot table at 0xffe64000
9406 13:30:14.093292 0. 000000000010a000-0000000000113fff: RAMSTAGE
9407 13:30:14.093341 1. 0000000040000000-00000000400fffff: RAM
9408 13:30:14.093389 2. 0000000040100000-000000004032afff: RAMSTAGE
9409 13:30:14.093437 3. 000000004032b000-00000000545fffff: RAM
9410 13:30:14.093485 4. 0000000054600000-000000005465ffff: BL31
9411 13:30:14.093533 5. 0000000054660000-00000000ffe63fff: RAM
9412 13:30:14.093581 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9413 13:30:14.093629 7. 0000000100000000-000000023fffffff: RAM
9414 13:30:14.093677 Passing 5 GPIOs to payload:
9415 13:30:14.093725 NAME | PORT | POLARITY | VALUE
9416 13:30:14.093773 EC in RW | 0x000000aa | low | undefined
9417 13:30:14.093822 EC interrupt | 0x00000005 | low | undefined
9418 13:30:14.093870 TPM interrupt | 0x000000ab | high | undefined
9419 13:30:14.093918 SD card detect | 0x00000011 | high | undefined
9420 13:30:14.093966 speaker enable | 0x00000093 | high | undefined
9421 13:30:14.094014 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9422 13:30:14.094061 in-header: 03 f9 00 00 02 00 00 00
9423 13:30:14.094109 in-data: 02 00
9424 13:30:14.094157 ADC[4]: Raw value=901477 ID=7
9425 13:30:14.094206 ADC[3]: Raw value=213546 ID=1
9426 13:30:14.094254 RAM Code: 0x71
9427 13:30:14.094302 ADC[6]: Raw value=75000 ID=0
9428 13:30:14.094349 ADC[5]: Raw value=213546 ID=1
9429 13:30:14.094397 SKU Code: 0x1
9430 13:30:14.094445 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 37eb
9431 13:30:14.094494 coreboot table: 964 bytes.
9432 13:30:14.094542 IMD ROOT 0. 0xfffff000 0x00001000
9433 13:30:14.094590 IMD SMALL 1. 0xffffe000 0x00001000
9434 13:30:14.094638 RO MCACHE 2. 0xffffc000 0x00001104
9435 13:30:14.094686 CONSOLE 3. 0xfff7c000 0x00080000
9436 13:30:14.094733 FMAP 4. 0xfff7b000 0x00000452
9437 13:30:14.094782 TIME STAMP 5. 0xfff7a000 0x00000910
9438 13:30:14.094830 VBOOT WORK 6. 0xfff66000 0x00014000
9439 13:30:14.094878 RAMOOPS 7. 0xffe66000 0x00100000
9440 13:30:14.094926 COREBOOT 8. 0xffe64000 0x00002000
9441 13:30:14.094973 IMD small region:
9442 13:30:14.095021 IMD ROOT 0. 0xffffec00 0x00000400
9443 13:30:14.095070 VPD 1. 0xffffeb80 0x0000006c
9444 13:30:14.095118 MMC STATUS 2. 0xffffeb60 0x00000004
9445 13:30:14.095166 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9446 13:30:14.095214 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9447 13:30:14.095263 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9448 13:30:14.095311 Checking segment from ROM address 0x40100000
9449 13:30:14.095359 Checking segment from ROM address 0x4010001c
9450 13:30:14.095406 Loading segment from ROM address 0x40100000
9451 13:30:14.095454 code (compression=0)
9452 13:30:14.095501 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9453 13:30:14.095550 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9454 13:30:14.095599 it's not compressed!
9455 13:30:14.095647 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9456 13:30:14.095695 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9457 13:30:14.095743 Loading segment from ROM address 0x4010001c
9458 13:30:14.095791 Entry Point 0x80000000
9459 13:30:14.095838 Loaded segments
9460 13:30:14.095885 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9461 13:30:14.095956 Jumping to boot code at 0x80000000(0xffe64000)
9462 13:30:14.096019 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9463 13:30:14.096067 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9464 13:30:14.096116 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9465 13:30:14.096164 Checking segment from ROM address 0x40100000
9466 13:30:14.096213 Checking segment from ROM address 0x4010001c
9467 13:30:14.096261 Loading segment from ROM address 0x40100000
9468 13:30:14.096309 code (compression=1)
9469 13:30:14.096357 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9470 13:30:14.096406 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9471 13:30:14.096455 using LZMA
9472 13:30:14.096502 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9473 13:30:14.096551 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9474 13:30:14.096600 Loading segment from ROM address 0x4010001c
9475 13:30:14.096648 Entry Point 0x54601000
9476 13:30:14.096696 Loaded segments
9477 13:30:14.096744 NOTICE: MT8192 bl31_setup
9478 13:30:14.096792 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9479 13:30:14.096841 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9480 13:30:14.096890 WARNING: region 0:
9481 13:30:14.096938 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 13:30:14.096986 WARNING: region 1:
9483 13:30:14.097212 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9484 13:30:14.097266 WARNING: region 2:
9485 13:30:14.097315 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9486 13:30:14.097364 WARNING: region 3:
9487 13:30:14.097413 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9488 13:30:14.097462 WARNING: region 4:
9489 13:30:14.097510 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9490 13:30:14.097558 WARNING: region 5:
9491 13:30:14.097606 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9492 13:30:14.097654 WARNING: region 6:
9493 13:30:14.097702 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9494 13:30:14.097750 WARNING: region 7:
9495 13:30:14.097797 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 13:30:14.097846 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9497 13:30:14.097894 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9498 13:30:14.097942 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9499 13:30:14.097990 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9500 13:30:14.098038 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9501 13:30:14.098086 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9502 13:30:14.098134 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9503 13:30:14.098181 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9504 13:30:14.098229 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9505 13:30:14.098277 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9506 13:30:14.098324 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9507 13:30:14.098372 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9508 13:30:14.098420 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9509 13:30:14.098468 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9510 13:30:14.098516 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9511 13:30:14.098565 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9512 13:30:14.098613 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9513 13:30:14.098660 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9514 13:30:14.098708 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9515 13:30:14.098755 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9516 13:30:14.098803 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9517 13:30:14.098851 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9518 13:30:14.098899 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9519 13:30:14.098947 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9520 13:30:14.098994 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9521 13:30:14.099043 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9522 13:30:14.099091 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9523 13:30:14.099139 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9524 13:30:14.099187 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9525 13:30:14.099235 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9526 13:30:14.099282 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9527 13:30:14.099330 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9528 13:30:14.099377 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9529 13:30:14.099425 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9530 13:30:14.099472 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9531 13:30:14.099520 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9532 13:30:14.099567 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9533 13:30:14.099614 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9534 13:30:14.099662 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9535 13:30:14.099709 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9536 13:30:14.099757 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9537 13:30:14.099804 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9538 13:30:14.099851 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9539 13:30:14.099899 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9540 13:30:14.099947 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9541 13:30:14.099994 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9542 13:30:14.100042 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9543 13:30:14.100090 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9544 13:30:14.100138 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9545 13:30:14.100186 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9546 13:30:14.100233 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9547 13:30:14.100280 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9548 13:30:14.100328 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9549 13:30:14.100376 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9550 13:30:14.100423 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9551 13:30:14.100470 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9552 13:30:14.100518 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9553 13:30:14.100566 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9554 13:30:14.100613 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9555 13:30:14.100660 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9556 13:30:14.100708 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9557 13:30:14.100756 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9558 13:30:14.100804 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9559 13:30:14.100851 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9560 13:30:14.100898 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9561 13:30:14.100946 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9562 13:30:14.100993 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9563 13:30:14.101041 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9564 13:30:14.101279 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9565 13:30:14.101333 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9566 13:30:14.101381 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9567 13:30:14.101430 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9568 13:30:14.101479 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9569 13:30:14.101527 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9570 13:30:14.101574 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9571 13:30:14.101623 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9572 13:30:14.101672 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9573 13:30:14.101720 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9574 13:30:14.101768 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9575 13:30:14.101816 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9576 13:30:14.101864 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9577 13:30:14.101913 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9578 13:30:14.101960 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9579 13:30:14.102008 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9580 13:30:14.102056 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9581 13:30:14.102105 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9582 13:30:14.102153 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9583 13:30:14.102201 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9584 13:30:14.102249 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9585 13:30:14.102297 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9586 13:30:14.102345 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9587 13:30:14.102393 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9588 13:30:14.102441 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9589 13:30:14.102489 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9590 13:30:14.102538 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9591 13:30:14.102586 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9592 13:30:14.102636 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9593 13:30:14.102685 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9594 13:30:14.102733 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9595 13:30:14.102781 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9596 13:30:14.102829 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9597 13:30:14.102876 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9598 13:30:14.102925 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9599 13:30:14.102973 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9600 13:30:14.103021 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9601 13:30:14.103069 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9602 13:30:14.103117 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9603 13:30:14.103165 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9604 13:30:14.103213 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9605 13:30:14.103261 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9606 13:30:14.103309 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9607 13:30:14.103357 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9608 13:30:14.103405 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9609 13:30:14.103454 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9610 13:30:14.103502 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9611 13:30:14.103550 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9612 13:30:14.103598 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9613 13:30:14.103645 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9614 13:30:14.103693 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9615 13:30:14.103742 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9616 13:30:14.103790 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9617 13:30:14.103838 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9618 13:30:14.103885 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9619 13:30:14.103933 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9620 13:30:14.103981 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9621 13:30:14.104028 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9622 13:30:14.104076 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9623 13:30:14.104124 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9624 13:30:14.104172 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9625 13:30:14.104220 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9626 13:30:14.104268 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9627 13:30:14.104332 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9628 13:30:14.104383 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9629 13:30:14.104430 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9630 13:30:14.104478 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9631 13:30:14.104526 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9632 13:30:14.104574 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9633 13:30:14.104640 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9634 13:30:14.104692 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9635 13:30:14.104741 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9636 13:30:14.104789 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9637 13:30:14.104837 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9638 13:30:14.104885 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9639 13:30:14.104933 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9640 13:30:14.104981 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9641 13:30:14.105213 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9642 13:30:14.105272 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9643 13:30:14.105321 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9644 13:30:14.105369 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9645 13:30:14.105417 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9646 13:30:14.105465 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9647 13:30:14.105513 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9648 13:30:14.105562 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9649 13:30:14.105610 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9650 13:30:14.105658 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9651 13:30:14.105706 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9652 13:30:14.105755 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9653 13:30:14.105803 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9654 13:30:14.105851 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9655 13:30:14.105900 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9656 13:30:14.105949 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9657 13:30:14.105997 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9658 13:30:14.106045 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9659 13:30:14.106093 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9660 13:30:14.106141 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9661 13:30:14.106188 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9662 13:30:14.106236 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9663 13:30:14.106284 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9664 13:30:14.106332 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9665 13:30:14.106380 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9666 13:30:14.106429 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9667 13:30:14.106476 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9668 13:30:14.106524 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9669 13:30:14.106572 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9670 13:30:14.106619 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9671 13:30:14.106666 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9672 13:30:14.106714 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9673 13:30:14.106762 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9674 13:30:14.106809 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9675 13:30:14.106858 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9676 13:30:14.106906 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9677 13:30:14.106954 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9678 13:30:14.107002 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9679 13:30:14.107050 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9680 13:30:14.107098 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9681 13:30:14.107146 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9682 13:30:14.107194 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9683 13:30:14.107242 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9684 13:30:14.107290 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9685 13:30:14.107338 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9686 13:30:14.107387 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9687 13:30:14.107435 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9688 13:30:14.107482 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9689 13:30:14.107530 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9690 13:30:14.107579 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9691 13:30:14.107627 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9692 13:30:14.107675 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9693 13:30:14.107723 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9694 13:30:14.107771 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9695 13:30:14.107818 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9696 13:30:14.107866 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9697 13:30:14.107917 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9698 13:30:14.107996 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9699 13:30:14.108073 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9700 13:30:14.108121 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9701 13:30:14.108169 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9702 13:30:14.108217 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9703 13:30:14.108264 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9704 13:30:14.108312 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9705 13:30:14.108360 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9706 13:30:14.108407 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9707 13:30:14.108456 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9708 13:30:14.108522 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9709 13:30:14.108573 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9710 13:30:14.108621 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9711 13:30:14.108670 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9712 13:30:14.108717 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9713 13:30:14.108765 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9714 13:30:14.108813 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9715 13:30:14.108875 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9716 13:30:14.108953 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9717 13:30:14.109207 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9718 13:30:14.109264 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9719 13:30:14.109314 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9720 13:30:14.109363 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9721 13:30:14.109412 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9722 13:30:14.109461 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9723 13:30:14.109509 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9724 13:30:14.109557 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9725 13:30:14.109606 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9726 13:30:14.109674 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9727 13:30:14.109792 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9728 13:30:14.109870 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9729 13:30:14.109946 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9730 13:30:14.110014 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9731 13:30:14.110064 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9732 13:30:14.110113 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9733 13:30:14.110161 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9734 13:30:14.110210 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9735 13:30:14.110259 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9736 13:30:14.110307 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9737 13:30:14.110355 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9738 13:30:14.110403 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9739 13:30:14.110452 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9740 13:30:14.110501 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9741 13:30:14.110549 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9742 13:30:14.110597 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9743 13:30:14.110644 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9744 13:30:14.110692 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9745 13:30:14.110739 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9746 13:30:14.110787 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9747 13:30:14.110836 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9748 13:30:14.110884 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9749 13:30:14.110932 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9750 13:30:14.110980 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9751 13:30:14.111028 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9752 13:30:14.111076 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9753 13:30:14.111124 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9754 13:30:14.111172 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9755 13:30:14.111220 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9756 13:30:14.111269 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9757 13:30:14.111317 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9758 13:30:14.111364 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9759 13:30:14.111412 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9760 13:30:14.111461 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9761 13:30:14.111510 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9762 13:30:14.111558 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9763 13:30:14.111605 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9764 13:30:14.111654 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9765 13:30:14.111701 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9766 13:30:14.111749 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9767 13:30:14.111800 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9768 13:30:14.111855 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9769 13:30:14.111904 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9770 13:30:14.111952 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9771 13:30:14.112001 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9772 13:30:14.112049 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9773 13:30:14.112097 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9774 13:30:14.112145 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9775 13:30:14.112193 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9776 13:30:14.112241 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9777 13:30:14.112290 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9778 13:30:14.112338 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9779 13:30:14.112386 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9780 13:30:14.112434 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9781 13:30:14.112483 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9782 13:30:14.112530 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9783 13:30:14.112578 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9784 13:30:14.112626 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9785 13:30:14.112675 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9786 13:30:14.112723 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9787 13:30:14.112771 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9788 13:30:14.112820 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9789 13:30:14.112869 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9790 13:30:14.112917 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9791 13:30:14.112964 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9792 13:30:14.113012 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9793 13:30:14.113060 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9794 13:30:14.113109 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9795 13:30:14.113377 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9796 13:30:14.113431 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9797 13:30:14.113481 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9798 13:30:14.113529 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9799 13:30:14.113577 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9800 13:30:14.113626 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9801 13:30:14.113675 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9802 13:30:14.113723 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9803 13:30:14.113771 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9804 13:30:14.113819 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9805 13:30:14.113867 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9806 13:30:14.113916 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9807 13:30:14.113964 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9808 13:30:14.114012 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9809 13:30:14.114060 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9810 13:30:14.114109 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9811 13:30:14.114156 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9812 13:30:14.114204 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9813 13:30:14.114252 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9814 13:30:14.114300 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9815 13:30:14.114347 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9816 13:30:14.114395 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9817 13:30:14.114442 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9818 13:30:14.114490 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9819 13:30:14.114538 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9820 13:30:14.114586 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9821 13:30:14.114634 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9822 13:30:14.114682 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9823 13:30:14.114730 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9824 13:30:14.114778 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9825 13:30:14.114826 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9826 13:30:14.114874 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9827 13:30:14.114922 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9828 13:30:14.114970 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9829 13:30:14.115018 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9830 13:30:14.115066 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9831 13:30:14.115114 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9832 13:30:14.115162 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9833 13:30:14.115210 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9834 13:30:14.115258 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9835 13:30:14.115306 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9836 13:30:14.115353 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9837 13:30:14.115401 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9838 13:30:14.115450 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9839 13:30:14.115498 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9840 13:30:14.115545 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9841 13:30:14.115592 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9842 13:30:14.115640 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9843 13:30:14.115688 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9844 13:30:14.115736 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9845 13:30:14.115784 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9846 13:30:14.115832 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9847 13:30:14.115880 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9848 13:30:14.115960 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9849 13:30:14.116024 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9850 13:30:14.116072 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9851 13:30:14.116121 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9852 13:30:14.116169 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9853 13:30:14.116218 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9854 13:30:14.116266 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9855 13:30:14.116314 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9856 13:30:14.116362 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9857 13:30:14.116410 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9858 13:30:14.116458 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9859 13:30:14.116525 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9860 13:30:14.116576 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9861 13:30:14.116624 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9862 13:30:14.116673 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9863 13:30:14.116721 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9864 13:30:14.116770 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9865 13:30:14.116818 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9866 13:30:14.116866 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9867 13:30:14.116914 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9868 13:30:14.116963 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9869 13:30:14.117011 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9870 13:30:14.117247 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9871 13:30:14.117302 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9872 13:30:14.117352 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9873 13:30:14.117401 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9874 13:30:14.117450 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9875 13:30:14.117499 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9876 13:30:14.117547 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9877 13:30:14.117595 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9878 13:30:14.117643 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9879 13:30:14.117691 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9880 13:30:14.117739 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9881 13:30:14.117787 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9882 13:30:14.117834 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9883 13:30:14.117883 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9884 13:30:14.117930 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9885 13:30:14.117978 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9886 13:30:14.118026 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9887 13:30:14.118075 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9888 13:30:14.118122 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9889 13:30:14.118170 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9890 13:30:14.118217 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9891 13:30:14.118266 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9892 13:30:14.118314 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9893 13:30:14.118362 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9894 13:30:14.118410 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9895 13:30:14.118458 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9896 13:30:14.118506 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9897 13:30:14.118554 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9898 13:30:14.118601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9899 13:30:14.118649 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9900 13:30:14.118697 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9901 13:30:14.118745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9902 13:30:14.249782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9903 13:30:14.249900 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9904 13:30:14.249961 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9905 13:30:14.250036 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9906 13:30:14.250111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9907 13:30:14.250164 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9908 13:30:14.250215 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9909 13:30:14.250266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9910 13:30:14.250316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9911 13:30:14.250365 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9912 13:30:14.250414 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9913 13:30:14.250463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9914 13:30:14.250512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9915 13:30:14.250560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9916 13:30:14.250609 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9917 13:30:14.250657 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9918 13:30:14.250706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9919 13:30:14.250755 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9920 13:30:14.250804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9921 13:30:14.250853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9922 13:30:14.250902 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9923 13:30:14.250951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9924 13:30:14.250999 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9925 13:30:14.251048 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9926 13:30:14.251096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9927 13:30:14.251145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9928 13:30:14.251194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9929 13:30:14.251242 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9930 13:30:14.251291 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9931 13:30:14.251338 INFO: [APUAPC] vio 0
9932 13:30:14.251386 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9933 13:30:14.251434 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9934 13:30:14.251482 INFO: [APUAPC] D0_APC_0: 0x400510
9935 13:30:14.251530 INFO: [APUAPC] D0_APC_1: 0x0
9936 13:30:14.251577 INFO: [APUAPC] D0_APC_2: 0x1540
9937 13:30:14.251625 INFO: [APUAPC] D0_APC_3: 0x0
9938 13:30:14.251674 INFO: [APUAPC] D1_APC_0: 0xffffffff
9939 13:30:14.251722 INFO: [APUAPC] D1_APC_1: 0xffffffff
9940 13:30:14.251770 INFO: [APUAPC] D1_APC_2: 0x3fffff
9941 13:30:14.251818 INFO: [APUAPC] D1_APC_3: 0x0
9942 13:30:14.251866 INFO: [APUAPC] D2_APC_0: 0xffffffff
9943 13:30:14.251914 INFO: [APUAPC] D2_APC_1: 0xffffffff
9944 13:30:14.251961 INFO: [APUAPC] D2_APC_2: 0x3fffff
9945 13:30:14.252009 INFO: [APUAPC] D2_APC_3: 0x0
9946 13:30:14.252056 INFO: [APUAPC] D3_APC_0: 0xffffffff
9947 13:30:14.252103 INFO: [APUAPC] D3_APC_1: 0xffffffff
9948 13:30:14.252151 INFO: [APUAPC] D3_APC_2: 0x3fffff
9949 13:30:14.252198 INFO: [APUAPC] D3_APC_3: 0x0
9950 13:30:14.252444 INFO: [APUAPC] D4_APC_0: 0xffffffff
9951 13:30:14.252498 INFO: [APUAPC] D4_APC_1: 0xffffffff
9952 13:30:14.252546 INFO: [APUAPC] D4_APC_2: 0x3fffff
9953 13:30:14.252594 INFO: [APUAPC] D4_APC_3: 0x0
9954 13:30:14.252642 INFO: [APUAPC] D5_APC_0: 0xffffffff
9955 13:30:14.252690 INFO: [APUAPC] D5_APC_1: 0xffffffff
9956 13:30:14.252739 INFO: [APUAPC] D5_APC_2: 0x3fffff
9957 13:30:14.252786 INFO: [APUAPC] D5_APC_3: 0x0
9958 13:30:14.252834 INFO: [APUAPC] D6_APC_0: 0xffffffff
9959 13:30:14.252882 INFO: [APUAPC] D6_APC_1: 0xffffffff
9960 13:30:14.252930 INFO: [APUAPC] D6_APC_2: 0x3fffff
9961 13:30:14.252978 INFO: [APUAPC] D6_APC_3: 0x0
9962 13:30:14.253025 INFO: [APUAPC] D7_APC_0: 0xffffffff
9963 13:30:14.253073 INFO: [APUAPC] D7_APC_1: 0xffffffff
9964 13:30:14.253120 INFO: [APUAPC] D7_APC_2: 0x3fffff
9965 13:30:14.253212 INFO: [APUAPC] D7_APC_3: 0x0
9966 13:30:14.253260 INFO: [APUAPC] D8_APC_0: 0xffffffff
9967 13:30:14.253308 INFO: [APUAPC] D8_APC_1: 0xffffffff
9968 13:30:14.253355 INFO: [APUAPC] D8_APC_2: 0x3fffff
9969 13:30:14.253404 INFO: [APUAPC] D8_APC_3: 0x0
9970 13:30:14.253452 INFO: [APUAPC] D9_APC_0: 0xffffffff
9971 13:30:14.253501 INFO: [APUAPC] D9_APC_1: 0xffffffff
9972 13:30:14.253547 INFO: [APUAPC] D9_APC_2: 0x3fffff
9973 13:30:14.253595 INFO: [APUAPC] D9_APC_3: 0x0
9974 13:30:14.253642 INFO: [APUAPC] D10_APC_0: 0xffffffff
9975 13:30:14.253690 INFO: [APUAPC] D10_APC_1: 0xffffffff
9976 13:30:14.253737 INFO: [APUAPC] D10_APC_2: 0x3fffff
9977 13:30:14.253784 INFO: [APUAPC] D10_APC_3: 0x0
9978 13:30:14.253832 INFO: [APUAPC] D11_APC_0: 0xffffffff
9979 13:30:14.253880 INFO: [APUAPC] D11_APC_1: 0xffffffff
9980 13:30:14.253928 INFO: [APUAPC] D11_APC_2: 0x3fffff
9981 13:30:14.253975 INFO: [APUAPC] D11_APC_3: 0x0
9982 13:30:14.254023 INFO: [APUAPC] D12_APC_0: 0xffffffff
9983 13:30:14.254071 INFO: [APUAPC] D12_APC_1: 0xffffffff
9984 13:30:14.254119 INFO: [APUAPC] D12_APC_2: 0x3fffff
9985 13:30:14.254167 INFO: [APUAPC] D12_APC_3: 0x0
9986 13:30:14.254214 INFO: [APUAPC] D13_APC_0: 0xffffffff
9987 13:30:14.254261 INFO: [APUAPC] D13_APC_1: 0xffffffff
9988 13:30:14.254308 INFO: [APUAPC] D13_APC_2: 0x3fffff
9989 13:30:14.254356 INFO: [APUAPC] D13_APC_3: 0x0
9990 13:30:14.254404 INFO: [APUAPC] D14_APC_0: 0xffffffff
9991 13:30:14.254452 INFO: [APUAPC] D14_APC_1: 0xffffffff
9992 13:30:14.254500 INFO: [APUAPC] D14_APC_2: 0x3fffff
9993 13:30:14.254548 INFO: [APUAPC] D14_APC_3: 0x0
9994 13:30:14.254595 INFO: [APUAPC] D15_APC_0: 0xffffffff
9995 13:30:14.254642 INFO: [APUAPC] D15_APC_1: 0xffffffff
9996 13:30:14.254689 INFO: [APUAPC] D15_APC_2: 0x3fffff
9997 13:30:14.254737 INFO: [APUAPC] D15_APC_3: 0x0
9998 13:30:14.254785 INFO: [APUAPC] APC_CON: 0x4
9999 13:30:14.254833 INFO: [NOCDAPC] D0_APC_0: 0x0
10000 13:30:14.254880 INFO: [NOCDAPC] D0_APC_1: 0x0
10001 13:30:14.254927 INFO: [NOCDAPC] D1_APC_0: 0x0
10002 13:30:14.254975 INFO: [NOCDAPC] D1_APC_1: 0xfff
10003 13:30:14.255023 INFO: [NOCDAPC] D2_APC_0: 0x0
10004 13:30:14.255071 INFO: [NOCDAPC] D2_APC_1: 0xfff
10005 13:30:14.255118 INFO: [NOCDAPC] D3_APC_0: 0x0
10006 13:30:14.255166 INFO: [NOCDAPC] D3_APC_1: 0xfff
10007 13:30:14.255214 INFO: [NOCDAPC] D4_APC_0: 0x0
10008 13:30:14.255262 INFO: [NOCDAPC] D4_APC_1: 0xfff
10009 13:30:14.255310 INFO: [NOCDAPC] D5_APC_0: 0x0
10010 13:30:14.255358 INFO: [NOCDAPC] D5_APC_1: 0xfff
10011 13:30:14.255406 INFO: [NOCDAPC] D6_APC_0: 0x0
10012 13:30:14.255454 INFO: [NOCDAPC] D6_APC_1: 0xfff
10013 13:30:14.255502 INFO: [NOCDAPC] D7_APC_0: 0x0
10014 13:30:14.255550 INFO: [NOCDAPC] D7_APC_1: 0xfff
10015 13:30:14.255597 INFO: [NOCDAPC] D8_APC_0: 0x0
10016 13:30:14.255645 INFO: [NOCDAPC] D8_APC_1: 0xfff
10017 13:30:14.255693 INFO: [NOCDAPC] D9_APC_0: 0x0
10018 13:30:14.255741 INFO: [NOCDAPC] D9_APC_1: 0xfff
10019 13:30:14.255788 INFO: [NOCDAPC] D10_APC_0: 0x0
10020 13:30:14.255836 INFO: [NOCDAPC] D10_APC_1: 0xfff
10021 13:30:14.255884 INFO: [NOCDAPC] D11_APC_0: 0x0
10022 13:30:14.255932 INFO: [NOCDAPC] D11_APC_1: 0xfff
10023 13:30:14.255980 INFO: [NOCDAPC] D12_APC_0: 0x0
10024 13:30:14.256057 INFO: [NOCDAPC] D12_APC_1: 0xfff
10025 13:30:14.256179 INFO: [NOCDAPC] D13_APC_0: 0x0
10026 13:30:14.256247 INFO: [NOCDAPC] D13_APC_1: 0xfff
10027 13:30:14.256297 INFO: [NOCDAPC] D14_APC_0: 0x0
10028 13:30:14.256345 INFO: [NOCDAPC] D14_APC_1: 0xfff
10029 13:30:14.256393 INFO: [NOCDAPC] D15_APC_0: 0x0
10030 13:30:14.256441 INFO: [NOCDAPC] D15_APC_1: 0xfff
10031 13:30:14.256488 INFO: [NOCDAPC] APC_CON: 0x4
10032 13:30:14.256537 INFO: [APUAPC] set_apusys_apc done
10033 13:30:14.256584 INFO: [DEVAPC] devapc_init done
10034 13:30:14.256632 INFO: GICv3 without legacy support detected.
10035 13:30:14.256680 INFO: ARM GICv3 driver initialized in EL3
10036 13:30:14.256728 INFO: Maximum SPI INTID supported: 639
10037 13:30:14.256776 INFO: BL31: Initializing runtime services
10038 13:30:14.256824 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10039 13:30:14.256872 INFO: SPM: enable CPC mode
10040 13:30:14.256921 INFO: mcdi ready for mcusys-off-idle and system suspend
10041 13:30:14.256969 INFO: BL31: Preparing for EL3 exit to normal world
10042 13:30:14.257017 INFO: Entry point address = 0x80000000
10043 13:30:14.257065 INFO: SPSR = 0x8
10044 13:30:14.257113
10045 13:30:14.257201
10046 13:30:14.257250
10047 13:30:14.257297 Starting depthcharge on Spherion...
10048 13:30:14.257345
10049 13:30:14.257392 Wipe memory regions:
10050 13:30:14.257439
10051 13:30:14.257487 [0x00000040000000, 0x00000054600000)
10052 13:30:14.257535
10053 13:30:14.257583 [0x00000054660000, 0x00000080000000)
10054 13:30:14.257631
10055 13:30:14.257679 [0x000000821a7280, 0x000000ffe64000)
10056 13:30:14.257726
10057 13:30:14.257774 [0x00000100000000, 0x00000240000000)
10058 13:30:14.258490 end: 2.2.3 depthcharge-start (duration 00:00:32) [common]
10059 13:30:14.258580 start: 2.2.4 bootloader-commands (timeout 00:04:18) [common]
10060 13:30:14.258654 Setting prompt string to ['asurada:']
10061 13:30:14.258718 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:18)
10062 13:30:15.664131
10063 13:30:15.667293 Initializing XHCI USB controller at 0x11200000.
10064 13:30:16.706152
10065 13:30:16.709331 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10066 13:30:16.709431
10067 13:30:16.709494
10068 13:30:16.709765 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10069 13:30:16.709859 Sending line: 'tftpboot 192.168.201.1 14879064/tftp-deploy-6ha59yvu/kernel/image.itb 14879064/tftp-deploy-6ha59yvu/kernel/cmdline '
10071 13:30:16.810400 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10072 13:30:16.810500 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10073 13:30:16.814661 asurada: tftpboot 192.168.201.1 14879064/tftp-deploy-6ha59yvu/kernel/image.ittp-deploy-6ha59yvu/kernel/cmdline
10074 13:30:16.814770
10075 13:30:16.814834 Waiting for link
10076 13:30:16.972931
10077 13:30:16.973071 R8152: Initializing
10078 13:30:16.973134
10079 13:30:16.976380 Version 6 (ocp_data = 5c30)
10080 13:30:16.976464
10081 13:30:16.979284 R8152: Done initializing
10082 13:30:16.979368
10083 13:30:16.979428 Adding net device
10084 13:30:18.853699
10085 13:30:18.853834 done.
10086 13:30:18.853897
10087 13:30:18.853952 MAC: 00:24:32:30:7c:7b
10088 13:30:18.854006
10089 13:30:18.856720 Sending DHCP discover... done.
10090 13:30:18.856798
10091 13:30:18.859687 Waiting for reply... done.
10092 13:30:18.859764
10093 13:30:18.863108 Sending DHCP request... done.
10094 13:30:18.863189
10095 13:30:18.901017 Waiting for reply... done.
10096 13:30:18.901197
10097 13:30:18.901300 My ip is 192.168.201.14
10098 13:30:18.901435
10099 13:30:18.904043 The DHCP server ip is 192.168.201.1
10100 13:30:18.904214
10101 13:30:18.910948 TFTP server IP predefined by user: 192.168.201.1
10102 13:30:18.911077
10103 13:30:18.917521 Bootfile predefined by user: 14879064/tftp-deploy-6ha59yvu/kernel/image.itb
10104 13:30:18.917654
10105 13:30:18.920661 Sending tftp read request... done.
10106 13:30:18.920810
10107 13:30:18.924428 Waiting for the transfer...
10108 13:30:18.924570
10109 13:30:19.549337 00000000 ################################################################
10110 13:30:19.549488
10111 13:30:20.194507 00080000 ################################################################
10112 13:30:20.194648
10113 13:30:20.831495 00100000 ################################################################
10114 13:30:20.832091
10115 13:30:21.471791 00180000 ################################################################
10116 13:30:21.472270
10117 13:30:22.133298 00200000 ################################################################
10118 13:30:22.133803
10119 13:30:22.775677 00280000 ################################################################
10120 13:30:22.776133
10121 13:30:23.460651 00300000 ################################################################
10122 13:30:23.461111
10123 13:30:24.141295 00380000 ################################################################
10124 13:30:24.141796
10125 13:30:24.794815 00400000 ################################################################
10126 13:30:24.795285
10127 13:30:25.477616 00480000 ################################################################
10128 13:30:25.477731
10129 13:30:26.118370 00500000 ################################################################
10130 13:30:26.118503
10131 13:30:26.759934 00580000 ################################################################
10132 13:30:26.760088
10133 13:30:27.398353 00600000 ################################################################
10134 13:30:27.398810
10135 13:30:28.038972 00680000 ################################################################
10136 13:30:28.039094
10137 13:30:28.690716 00700000 ################################################################
10138 13:30:28.691180
10139 13:30:29.336690 00780000 ################################################################
10140 13:30:29.336828
10141 13:30:29.961937 00800000 ################################################################
10142 13:30:29.962066
10143 13:30:30.562211 00880000 ################################################################
10144 13:30:30.562359
10145 13:30:31.174332 00900000 ################################################################
10146 13:30:31.174454
10147 13:30:31.757008 00980000 ################################################################
10148 13:30:31.757191
10149 13:30:32.321304 00a00000 ################################################################
10150 13:30:32.321429
10151 13:30:32.903850 00a80000 ################################################################
10152 13:30:32.903975
10153 13:30:33.469274 00b00000 ################################################################
10154 13:30:33.469403
10155 13:30:34.019287 00b80000 ################################################################
10156 13:30:34.019437
10157 13:30:34.565819 00c00000 ################################################################
10158 13:30:34.565933
10159 13:30:35.137577 00c80000 ################################################################
10160 13:30:35.137686
10161 13:30:35.687747 00d00000 ################################################################
10162 13:30:35.687859
10163 13:30:36.231338 00d80000 ################################################################
10164 13:30:36.231450
10165 13:30:36.792161 00e00000 ################################################################
10166 13:30:36.792287
10167 13:30:37.364308 00e80000 ################################################################
10168 13:30:37.364442
10169 13:30:37.929767 00f00000 ################################################################
10170 13:30:37.929888
10171 13:30:38.496238 00f80000 ################################################################
10172 13:30:38.496351
10173 13:30:39.069910 01000000 ################################################################
10174 13:30:39.070039
10175 13:30:39.655767 01080000 ################################################################
10176 13:30:39.655969
10177 13:30:40.257917 01100000 ################################################################
10178 13:30:40.258063
10179 13:30:40.903391 01180000 ################################################################
10180 13:30:40.903557
10181 13:30:41.529780 01200000 ################################################################
10182 13:30:41.529908
10183 13:30:42.135330 01280000 ################################################################
10184 13:30:42.135481
10185 13:30:42.684324 01300000 ################################################################
10186 13:30:42.684454
10187 13:30:43.234519 01380000 ################################################################
10188 13:30:43.234676
10189 13:30:43.774505 01400000 ################################################################
10190 13:30:43.774628
10191 13:30:44.295731 01480000 ################################################################
10192 13:30:44.295851
10193 13:30:44.819958 01500000 ################################################################
10194 13:30:44.820080
10195 13:30:45.362488 01580000 ################################################################
10196 13:30:45.362610
10197 13:30:45.947266 01600000 ################################################################
10198 13:30:45.947414
10199 13:30:46.511303 01680000 ################################################################
10200 13:30:46.511428
10201 13:30:47.059494 01700000 ################################################################
10202 13:30:47.059623
10203 13:30:47.659243 01780000 ################################################################
10204 13:30:47.659379
10205 13:30:48.132280 01800000 ################################################################
10206 13:30:48.132410
10207 13:30:48.674039 01880000 ################################################################
10208 13:30:48.674214
10209 13:30:49.193805 01900000 ################################################################
10210 13:30:49.193956
10211 13:30:49.742817 01980000 ################################################################
10212 13:30:49.742941
10213 13:30:50.336820 01a00000 ################################################################
10214 13:30:50.336947
10215 13:30:50.918801 01a80000 ################################################################
10216 13:30:50.918928
10217 13:30:51.532983 01b00000 ################################################################
10218 13:30:51.533164
10219 13:30:52.077241 01b80000 ################################################################
10220 13:30:52.077365
10221 13:30:52.616713 01c00000 ################################################################
10222 13:30:52.616842
10223 13:30:53.218437 01c80000 ################################################################
10224 13:30:53.218559
10225 13:30:53.777571 01d00000 ################################################################
10226 13:30:53.777697
10227 13:30:54.330986 01d80000 ################################################################
10228 13:30:54.331112
10229 13:30:54.778545 01e00000 ##################################################### done.
10230 13:30:54.778670
10231 13:30:54.781993 The bootfile was 31886610 bytes long.
10232 13:30:54.782072
10233 13:30:54.785128 Sending tftp read request... done.
10234 13:30:54.785248
10235 13:30:54.785323 Waiting for the transfer...
10236 13:30:54.785410
10237 13:30:54.788412 00000000 # done.
10238 13:30:54.788490
10239 13:30:54.795420 Command line loaded dynamically from TFTP file: 14879064/tftp-deploy-6ha59yvu/kernel/cmdline
10240 13:30:54.795499
10241 13:30:54.818459 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14879064/extract-nfsrootfs-qesymwcp,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10242 13:30:54.818550
10243 13:30:54.818612 Loading FIT.
10244 13:30:54.818667
10245 13:30:54.822211 Image ramdisk-1 has 18722854 bytes.
10246 13:30:54.822288
10247 13:30:54.825464 Image fdt-1 has 47258 bytes.
10248 13:30:54.825540
10249 13:30:54.828727 Image kernel-1 has 13114469 bytes.
10250 13:30:54.828803
10251 13:30:54.838205 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10252 13:30:54.838282
10253 13:30:54.855298 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10254 13:30:54.855379
10255 13:30:54.861774 Choosing best match conf-1 for compat google,spherion-rev2.
10256 13:30:54.861875
10257 13:30:54.883950 Connected to device vid:did:rid of 1ae0:0028:00
10258 13:30:54.884091
10259 13:30:54.884181 tpm_get_response: command 0x17b, return code 0x0
10260 13:30:54.884262
10261 13:30:54.884318 ec_init: CrosEC protocol v3 supported (256, 248)
10262 13:30:54.887828
10263 13:30:54.891158 tpm_cleanup: add release locality here.
10264 13:30:54.891237
10265 13:30:54.891326 Shutting down all USB controllers.
10266 13:30:54.894491
10267 13:30:54.894573 Removing current net device
10268 13:30:54.894634
10269 13:30:54.900980 Exiting depthcharge with code 4 at timestamp: 71461476
10270 13:30:54.901079
10271 13:30:54.904867 LZMA decompressing kernel-1 to 0x821a6718
10272 13:30:54.904943
10273 13:30:54.907882 LZMA decompressing kernel-1 to 0x40000000
10274 13:30:56.522976
10275 13:30:56.523134 jumping to kernel
10276 13:30:56.523914 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10277 13:30:56.524015 start: 2.2.5 auto-login-action (timeout 00:03:36) [common]
10278 13:30:56.524091 Setting prompt string to ['Linux version [0-9]']
10279 13:30:56.524161 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10280 13:30:56.524232 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10281 13:30:56.604295
10282 13:30:56.607699 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10283 13:30:56.611418 start: 2.2.5.1 login-action (timeout 00:03:36) [common]
10284 13:30:56.611829 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10285 13:30:56.612150 Setting prompt string to []
10286 13:30:56.612482 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10287 13:30:56.612774 Using line separator: #'\n'#
10288 13:30:56.613026 No login prompt set.
10289 13:30:56.613354 Parsing kernel messages
10290 13:30:56.613605 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10291 13:30:56.614052 [login-action] Waiting for messages, (timeout 00:03:36)
10292 13:30:56.614346 Waiting using forced prompt support (timeout 00:01:48)
10293 13:30:56.630882 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j272990-arm64-gcc-12-defconfig-arm64-chromebook-fgzcq) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024
10294 13:30:56.634042 [ 0.000000] random: crng init done
10295 13:30:56.637305 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10296 13:30:56.640613 [ 0.000000] efi: UEFI not found.
10297 13:30:56.650877 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10298 13:30:56.657635 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10299 13:30:56.667427 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10300 13:30:56.677393 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10301 13:30:56.683498 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10302 13:30:56.687007 [ 0.000000] printk: bootconsole [mtk8250] enabled
10303 13:30:56.695309 [ 0.000000] NUMA: No NUMA configuration found
10304 13:30:56.702507 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10305 13:30:56.708641 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10306 13:30:56.709002 [ 0.000000] Zone ranges:
10307 13:30:56.715312 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10308 13:30:56.718542 [ 0.000000] DMA32 empty
10309 13:30:56.725234 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10310 13:30:56.728601 [ 0.000000] Movable zone start for each node
10311 13:30:56.731845 [ 0.000000] Early memory node ranges
10312 13:30:56.738301 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10313 13:30:56.745046 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10314 13:30:56.751532 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10315 13:30:56.758102 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10316 13:30:56.764751 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10317 13:30:56.771875 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10318 13:30:56.828828 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10319 13:30:56.835556 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10320 13:30:56.842116 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10321 13:30:56.845399 [ 0.000000] psci: probing for conduit method from DT.
10322 13:30:56.852037 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10323 13:30:56.855200 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10324 13:30:56.861728 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10325 13:30:56.865229 [ 0.000000] psci: SMC Calling Convention v1.2
10326 13:30:56.871978 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10327 13:30:56.874641 [ 0.000000] Detected VIPT I-cache on CPU0
10328 13:30:56.881820 [ 0.000000] CPU features: detected: GIC system register CPU interface
10329 13:30:56.888186 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10330 13:30:56.894841 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10331 13:30:56.901230 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10332 13:30:56.907914 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10333 13:30:56.918226 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10334 13:30:56.921576 [ 0.000000] alternatives: applying boot alternatives
10335 13:30:56.928152 [ 0.000000] Fallback order for Node 0: 0
10336 13:30:56.934535 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10337 13:30:56.938040 [ 0.000000] Policy zone: Normal
10338 13:30:56.960771 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14879064/extract-nfsrootfs-qesymwcp,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10339 13:30:56.970490 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10340 13:30:56.981671 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10341 13:30:56.991578 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10342 13:30:56.998226 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10343 13:30:57.001389 <6>[ 0.000000] software IO TLB: area num 8.
10344 13:30:57.058665 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10345 13:30:57.208100 <6>[ 0.000000] Memory: 7945776K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 406992K reserved, 32768K cma-reserved)
10346 13:30:57.214808 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10347 13:30:57.220734 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10348 13:30:57.223949 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10349 13:30:57.230937 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10350 13:30:57.237632 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10351 13:30:57.240817 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10352 13:30:57.250405 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10353 13:30:57.257612 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10354 13:30:57.264016 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10355 13:30:57.270586 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10356 13:30:57.273938 <6>[ 0.000000] GICv3: 608 SPIs implemented
10357 13:30:57.277187 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10358 13:30:57.283774 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10359 13:30:57.286924 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10360 13:30:57.293442 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10361 13:30:57.306619 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10362 13:30:57.320070 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10363 13:30:57.326543 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10364 13:30:57.334647 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10365 13:30:57.347255 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10366 13:30:57.354026 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10367 13:30:57.361005 <6>[ 0.009181] Console: colour dummy device 80x25
10368 13:30:57.370649 <6>[ 0.013913] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10369 13:30:57.377518 <6>[ 0.024355] pid_max: default: 32768 minimum: 301
10370 13:30:57.380796 <6>[ 0.029228] LSM: Security Framework initializing
10371 13:30:57.387274 <6>[ 0.034195] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10372 13:30:57.397380 <6>[ 0.042055] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10373 13:30:57.403803 <6>[ 0.051532] cblist_init_generic: Setting adjustable number of callback queues.
10374 13:30:57.410415 <6>[ 0.058973] cblist_init_generic: Setting shift to 3 and lim to 1.
10375 13:30:57.420394 <6>[ 0.065313] cblist_init_generic: Setting adjustable number of callback queues.
10376 13:30:57.427116 <6>[ 0.072740] cblist_init_generic: Setting shift to 3 and lim to 1.
10377 13:30:57.430580 <6>[ 0.079141] rcu: Hierarchical SRCU implementation.
10378 13:30:57.437249 <6>[ 0.084187] rcu: Max phase no-delay instances is 1000.
10379 13:30:57.443415 <6>[ 0.091214] EFI services will not be available.
10380 13:30:57.447178 <6>[ 0.096174] smp: Bringing up secondary CPUs ...
10381 13:30:57.455118 <6>[ 0.101223] Detected VIPT I-cache on CPU1
10382 13:30:57.461430 <6>[ 0.101296] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10383 13:30:57.467985 <6>[ 0.101331] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10384 13:30:57.471680 <6>[ 0.101674] Detected VIPT I-cache on CPU2
10385 13:30:57.481589 <6>[ 0.101727] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10386 13:30:57.487884 <6>[ 0.101745] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10387 13:30:57.491051 <6>[ 0.102008] Detected VIPT I-cache on CPU3
10388 13:30:57.497676 <6>[ 0.102057] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10389 13:30:57.504545 <6>[ 0.102072] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10390 13:30:57.511021 <6>[ 0.102381] CPU features: detected: Spectre-v4
10391 13:30:57.514480 <6>[ 0.102387] CPU features: detected: Spectre-BHB
10392 13:30:57.517902 <6>[ 0.102392] Detected PIPT I-cache on CPU4
10393 13:30:57.524004 <6>[ 0.102453] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10394 13:30:57.534016 <6>[ 0.102470] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10395 13:30:57.537569 <6>[ 0.102763] Detected PIPT I-cache on CPU5
10396 13:30:57.544466 <6>[ 0.102828] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10397 13:30:57.550726 <6>[ 0.102844] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10398 13:30:57.554076 <6>[ 0.103125] Detected PIPT I-cache on CPU6
10399 13:30:57.560798 <6>[ 0.103192] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10400 13:30:57.567326 <6>[ 0.103207] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10401 13:30:57.573566 <6>[ 0.103507] Detected PIPT I-cache on CPU7
10402 13:30:57.580195 <6>[ 0.103573] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10403 13:30:57.586756 <6>[ 0.103589] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10404 13:30:57.590001 <6>[ 0.103637] smp: Brought up 1 node, 8 CPUs
10405 13:30:57.596729 <6>[ 0.244951] SMP: Total of 8 processors activated.
10406 13:30:57.603131 <6>[ 0.249872] CPU features: detected: 32-bit EL0 Support
10407 13:30:57.609760 <6>[ 0.255235] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10408 13:30:57.616266 <6>[ 0.264090] CPU features: detected: Common not Private translations
10409 13:30:57.623007 <6>[ 0.270567] CPU features: detected: CRC32 instructions
10410 13:30:57.629670 <6>[ 0.275951] CPU features: detected: RCpc load-acquire (LDAPR)
10411 13:30:57.633037 <6>[ 0.281948] CPU features: detected: LSE atomic instructions
10412 13:30:57.639514 <6>[ 0.287730] CPU features: detected: Privileged Access Never
10413 13:30:57.646344 <6>[ 0.293545] CPU features: detected: RAS Extension Support
10414 13:30:57.652718 <6>[ 0.299154] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10415 13:30:57.656347 <6>[ 0.306376] CPU: All CPU(s) started at EL2
10416 13:30:57.662967 <6>[ 0.310693] alternatives: applying system-wide alternatives
10417 13:30:57.672921 <6>[ 0.321562] devtmpfs: initialized
10418 13:30:57.688282 <6>[ 0.330493] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10419 13:30:57.695031 <6>[ 0.340458] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10420 13:30:57.701684 <6>[ 0.348302] pinctrl core: initialized pinctrl subsystem
10421 13:30:57.704748 <6>[ 0.354978] DMI not present or invalid.
10422 13:30:57.711634 <6>[ 0.359391] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10423 13:30:57.721507 <6>[ 0.366287] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10424 13:30:57.728191 <6>[ 0.373874] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10425 13:30:57.738048 <6>[ 0.382086] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10426 13:30:57.741186 <6>[ 0.390325] audit: initializing netlink subsys (disabled)
10427 13:30:57.750900 <5>[ 0.396022] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10428 13:30:57.757868 <6>[ 0.396730] thermal_sys: Registered thermal governor 'step_wise'
10429 13:30:57.764401 <6>[ 0.403985] thermal_sys: Registered thermal governor 'power_allocator'
10430 13:30:57.767421 <6>[ 0.410239] cpuidle: using governor menu
10431 13:30:57.774151 <6>[ 0.421198] NET: Registered PF_QIPCRTR protocol family
10432 13:30:57.781068 <6>[ 0.426696] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10433 13:30:57.787169 <6>[ 0.433801] ASID allocator initialised with 32768 entries
10434 13:30:57.790428 <6>[ 0.440377] Serial: AMBA PL011 UART driver
10435 13:30:57.800931 <4>[ 0.449721] Trying to register duplicate clock ID: 134
10436 13:30:57.858981 <6>[ 0.511223] KASLR enabled
10437 13:30:57.873678 <6>[ 0.518913] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10438 13:30:57.880241 <6>[ 0.525929] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10439 13:30:57.886803 <6>[ 0.532418] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10440 13:30:57.892769 <6>[ 0.539424] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10441 13:30:57.899353 <6>[ 0.545911] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10442 13:30:57.905951 <6>[ 0.552915] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10443 13:30:57.912922 <6>[ 0.559401] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10444 13:30:57.919140 <6>[ 0.566408] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10445 13:30:57.922409 <6>[ 0.573939] ACPI: Interpreter disabled.
10446 13:30:57.931677 <6>[ 0.580381] iommu: Default domain type: Translated
10447 13:30:57.937859 <6>[ 0.585495] iommu: DMA domain TLB invalidation policy: strict mode
10448 13:30:57.941159 <5>[ 0.592146] SCSI subsystem initialized
10449 13:30:57.947808 <6>[ 0.596311] usbcore: registered new interface driver usbfs
10450 13:30:57.954916 <6>[ 0.602042] usbcore: registered new interface driver hub
10451 13:30:57.957683 <6>[ 0.607594] usbcore: registered new device driver usb
10452 13:30:57.964763 <6>[ 0.613706] pps_core: LinuxPPS API ver. 1 registered
10453 13:30:57.974690 <6>[ 0.618897] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10454 13:30:57.977948 <6>[ 0.628244] PTP clock support registered
10455 13:30:57.981187 <6>[ 0.632488] EDAC MC: Ver: 3.0.0
10456 13:30:57.988498 <6>[ 0.637653] FPGA manager framework
10457 13:30:57.995596 <6>[ 0.641340] Advanced Linux Sound Architecture Driver Initialized.
10458 13:30:57.998915 <6>[ 0.648136] vgaarb: loaded
10459 13:30:58.005396 <6>[ 0.651316] clocksource: Switched to clocksource arch_sys_counter
10460 13:30:58.008081 <5>[ 0.657756] VFS: Disk quotas dquot_6.6.0
10461 13:30:58.014772 <6>[ 0.661941] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10462 13:30:58.018066 <6>[ 0.669134] pnp: PnP ACPI: disabled
10463 13:30:58.026888 <6>[ 0.675905] NET: Registered PF_INET protocol family
10464 13:30:58.036722 <6>[ 0.681521] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10465 13:30:58.048402 <6>[ 0.693885] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10466 13:30:58.058487 <6>[ 0.702701] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10467 13:30:58.064496 <6>[ 0.710672] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10468 13:30:58.074807 <6>[ 0.719372] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10469 13:30:58.081286 <6>[ 0.729122] TCP: Hash tables configured (established 65536 bind 65536)
10470 13:30:58.087690 <6>[ 0.735986] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10471 13:30:58.097451 <6>[ 0.743183] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10472 13:30:58.103938 <6>[ 0.750886] NET: Registered PF_UNIX/PF_LOCAL protocol family
10473 13:30:58.110613 <6>[ 0.757048] RPC: Registered named UNIX socket transport module.
10474 13:30:58.113827 <6>[ 0.763202] RPC: Registered udp transport module.
10475 13:30:58.120892 <6>[ 0.768135] RPC: Registered tcp transport module.
10476 13:30:58.126928 <6>[ 0.773065] RPC: Registered tcp NFSv4.1 backchannel transport module.
10477 13:30:58.130944 <6>[ 0.779731] PCI: CLS 0 bytes, default 64
10478 13:30:58.133912 <6>[ 0.784005] Unpacking initramfs...
10479 13:30:58.158086 <6>[ 0.803425] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10480 13:30:58.167642 <6>[ 0.812069] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10481 13:30:58.170932 <6>[ 0.820909] kvm [1]: IPA Size Limit: 40 bits
10482 13:30:58.177764 <6>[ 0.825434] kvm [1]: GICv3: no GICV resource entry
10483 13:30:58.181053 <6>[ 0.830454] kvm [1]: disabling GICv2 emulation
10484 13:30:58.187739 <6>[ 0.835143] kvm [1]: GIC system register CPU interface enabled
10485 13:30:58.191062 <6>[ 0.841301] kvm [1]: vgic interrupt IRQ18
10486 13:30:58.197046 <6>[ 0.845656] kvm [1]: VHE mode initialized successfully
10487 13:30:58.203752 <5>[ 0.851978] Initialise system trusted keyrings
10488 13:30:58.210293 <6>[ 0.856780] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10489 13:30:58.217625 <6>[ 0.866756] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10490 13:30:58.224426 <5>[ 0.873149] NFS: Registering the id_resolver key type
10491 13:30:58.227925 <5>[ 0.878452] Key type id_resolver registered
10492 13:30:58.234609 <5>[ 0.882867] Key type id_legacy registered
10493 13:30:58.240831 <6>[ 0.887148] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10494 13:30:58.247819 <6>[ 0.894069] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10495 13:30:58.253926 <6>[ 0.901796] 9p: Installing v9fs 9p2000 file system support
10496 13:30:58.290371 <5>[ 0.939469] Key type asymmetric registered
10497 13:30:58.293721 <5>[ 0.943802] Asymmetric key parser 'x509' registered
10498 13:30:58.303825 <6>[ 0.948957] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10499 13:30:58.307183 <6>[ 0.956568] io scheduler mq-deadline registered
10500 13:30:58.310631 <6>[ 0.961349] io scheduler kyber registered
10501 13:30:58.329723 <6>[ 0.978533] EINJ: ACPI disabled.
10502 13:30:58.362511 <4>[ 1.004961] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10503 13:30:58.372457 <4>[ 1.015594] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10504 13:30:58.387683 <6>[ 1.036909] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10505 13:30:58.395699 <6>[ 1.044942] printk: console [ttyS0] disabled
10506 13:30:58.424185 <6>[ 1.069570] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10507 13:30:58.430851 <6>[ 1.079049] printk: console [ttyS0] enabled
10508 13:30:58.433556 <6>[ 1.079049] printk: console [ttyS0] enabled
10509 13:30:58.440303 <6>[ 1.087944] printk: bootconsole [mtk8250] disabled
10510 13:30:58.443475 <6>[ 1.087944] printk: bootconsole [mtk8250] disabled
10511 13:30:58.450426 <6>[ 1.099152] SuperH (H)SCI(F) driver initialized
10512 13:30:58.453123 <6>[ 1.104426] msm_serial: driver initialized
10513 13:30:58.467501 <6>[ 1.113420] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10514 13:30:58.477770 <6>[ 1.121967] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10515 13:30:58.484242 <6>[ 1.130509] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10516 13:30:58.493871 <6>[ 1.139136] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10517 13:30:58.504112 <6>[ 1.147842] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10518 13:30:58.510376 <6>[ 1.156556] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10519 13:30:58.520215 <6>[ 1.165103] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10520 13:30:58.526862 <6>[ 1.173910] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10521 13:30:58.537021 <6>[ 1.182455] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10522 13:30:58.549544 <6>[ 1.198230] loop: module loaded
10523 13:30:58.555939 <6>[ 1.204170] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10524 13:30:58.579089 <4>[ 1.227910] mtk-pmic-keys: Failed to locate of_node [id: -1]
10525 13:30:58.586318 <6>[ 1.235060] megasas: 07.719.03.00-rc1
10526 13:30:58.595962 <6>[ 1.244873] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10527 13:30:58.605867 <6>[ 1.254697] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10528 13:30:58.622925 <6>[ 1.271479] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10529 13:30:58.679703 <6>[ 1.321784] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10530 13:30:58.933913 <6>[ 1.582306] Freeing initrd memory: 18280K
10531 13:30:58.944932 <6>[ 1.593670] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10532 13:30:58.956036 <6>[ 1.604622] tun: Universal TUN/TAP device driver, 1.6
10533 13:30:58.959017 <6>[ 1.610689] thunder_xcv, ver 1.0
10534 13:30:58.962764 <6>[ 1.614197] thunder_bgx, ver 1.0
10535 13:30:58.965674 <6>[ 1.617693] nicpf, ver 1.0
10536 13:30:58.976360 <6>[ 1.621729] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10537 13:30:58.979548 <6>[ 1.629205] hns3: Copyright (c) 2017 Huawei Corporation.
10538 13:30:58.986412 <6>[ 1.634792] hclge is initializing
10539 13:30:58.989973 <6>[ 1.638366] e1000: Intel(R) PRO/1000 Network Driver
10540 13:30:58.996146 <6>[ 1.643496] e1000: Copyright (c) 1999-2006 Intel Corporation.
10541 13:30:58.999660 <6>[ 1.649507] e1000e: Intel(R) PRO/1000 Network Driver
10542 13:30:59.006300 <6>[ 1.654723] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10543 13:30:59.012637 <6>[ 1.660908] igb: Intel(R) Gigabit Ethernet Network Driver
10544 13:30:59.019855 <6>[ 1.666558] igb: Copyright (c) 2007-2014 Intel Corporation.
10545 13:30:59.025897 <6>[ 1.672395] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10546 13:30:59.032659 <6>[ 1.678913] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10547 13:30:59.036348 <6>[ 1.685375] sky2: driver version 1.30
10548 13:30:59.042917 <6>[ 1.690313] usbcore: registered new device driver r8152-cfgselector
10549 13:30:59.049469 <6>[ 1.696848] usbcore: registered new interface driver r8152
10550 13:30:59.055647 <6>[ 1.702666] VFIO - User Level meta-driver version: 0.3
10551 13:30:59.062175 <6>[ 1.710921] usbcore: registered new interface driver usb-storage
10552 13:30:59.068697 <6>[ 1.717370] usbcore: registered new device driver onboard-usb-hub
10553 13:30:59.077425 <6>[ 1.726575] mt6397-rtc mt6359-rtc: registered as rtc0
10554 13:30:59.087389 <6>[ 1.732043] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-18T13:30:58 UTC (1721309458)
10555 13:30:59.090781 <6>[ 1.741617] i2c_dev: i2c /dev entries driver
10556 13:30:59.104852 <4>[ 1.753763] cpu cpu0: supply cpu not found, using dummy regulator
10557 13:30:59.111647 <4>[ 1.760208] cpu cpu1: supply cpu not found, using dummy regulator
10558 13:30:59.118131 <4>[ 1.766609] cpu cpu2: supply cpu not found, using dummy regulator
10559 13:30:59.124740 <4>[ 1.773011] cpu cpu3: supply cpu not found, using dummy regulator
10560 13:30:59.131270 <4>[ 1.779408] cpu cpu4: supply cpu not found, using dummy regulator
10561 13:30:59.137804 <4>[ 1.785805] cpu cpu5: supply cpu not found, using dummy regulator
10562 13:30:59.144404 <4>[ 1.792225] cpu cpu6: supply cpu not found, using dummy regulator
10563 13:30:59.151075 <4>[ 1.798622] cpu cpu7: supply cpu not found, using dummy regulator
10564 13:30:59.171495 <6>[ 1.820270] cpu cpu0: EM: created perf domain
10565 13:30:59.174744 <6>[ 1.825216] cpu cpu4: EM: created perf domain
10566 13:30:59.182002 <6>[ 1.830841] sdhci: Secure Digital Host Controller Interface driver
10567 13:30:59.188337 <6>[ 1.837274] sdhci: Copyright(c) Pierre Ossman
10568 13:30:59.194847 <6>[ 1.842240] Synopsys Designware Multimedia Card Interface Driver
10569 13:30:59.201470 <6>[ 1.848881] sdhci-pltfm: SDHCI platform and OF driver helper
10570 13:30:59.204704 <6>[ 1.848932] mmc0: CQHCI version 5.10
10571 13:30:59.211543 <6>[ 1.858835] ledtrig-cpu: registered to indicate activity on CPUs
10572 13:30:59.218612 <6>[ 1.865841] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10573 13:30:59.224699 <6>[ 1.872904] usbcore: registered new interface driver usbhid
10574 13:30:59.228062 <6>[ 1.878727] usbhid: USB HID core driver
10575 13:30:59.234771 <6>[ 1.882922] spi_master spi0: will run message pump with realtime priority
10576 13:30:59.284013 <6>[ 1.926321] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10577 13:30:59.304133 <6>[ 1.942937] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10578 13:30:59.306819 <6>[ 1.952836] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17814
10579 13:30:59.316002 <6>[ 1.964448] cros-ec-spi spi0.0: Chrome EC device registered
10580 13:30:59.322310 <6>[ 1.970525] mmc0: Command Queue Engine enabled
10581 13:30:59.328895 <6>[ 1.975292] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10582 13:30:59.332120 <6>[ 1.982746] mmcblk0: mmc0:0001 DA4128 116 GiB
10583 13:30:59.343349 <6>[ 1.988933] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10584 13:30:59.349967 <6>[ 1.992121] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10585 13:30:59.356566 <6>[ 1.999539] NET: Registered PF_PACKET protocol family
10586 13:30:59.359926 <6>[ 2.005084] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10587 13:30:59.366479 <6>[ 2.009561] 9pnet: Installing 9P2000 support
10588 13:30:59.369790 <6>[ 2.015388] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10589 13:30:59.376450 <5>[ 2.019257] Key type dns_resolver registered
10590 13:30:59.383393 <6>[ 2.025021] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10591 13:30:59.386677 <6>[ 2.029451] registered taskstats version 1
10592 13:30:59.389428 <5>[ 2.039859] Loading compiled-in X.509 certificates
10593 13:30:59.418809 <4>[ 2.061121] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10594 13:30:59.428265 <4>[ 2.071874] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10595 13:30:59.443104 <6>[ 2.091988] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10596 13:30:59.449963 <6>[ 2.099007] xhci-mtk 11200000.usb: xHCI Host Controller
10597 13:30:59.456622 <6>[ 2.104508] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10598 13:30:59.466768 <6>[ 2.112365] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10599 13:30:59.473385 <6>[ 2.121795] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10600 13:30:59.479996 <6>[ 2.127861] xhci-mtk 11200000.usb: xHCI Host Controller
10601 13:30:59.486213 <6>[ 2.133342] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10602 13:30:59.493091 <6>[ 2.140989] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10603 13:30:59.499691 <6>[ 2.148821] hub 1-0:1.0: USB hub found
10604 13:30:59.502999 <6>[ 2.152849] hub 1-0:1.0: 1 port detected
10605 13:30:59.513026 <6>[ 2.157130] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10606 13:30:59.516600 <6>[ 2.165864] hub 2-0:1.0: USB hub found
10607 13:30:59.519831 <6>[ 2.169887] hub 2-0:1.0: 1 port detected
10608 13:30:59.527564 <6>[ 2.176627] mtk-msdc 11f70000.mmc: Got CD GPIO
10609 13:30:59.541089 <6>[ 2.186870] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10610 13:30:59.548144 <6>[ 2.195247] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10611 13:30:59.557633 <6>[ 2.203587] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10612 13:30:59.567613 <6>[ 2.211929] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10613 13:30:59.574282 <6>[ 2.220280] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10614 13:30:59.584262 <6>[ 2.228623] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10615 13:30:59.591234 <6>[ 2.236962] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10616 13:30:59.601039 <6>[ 2.245301] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10617 13:30:59.607442 <6>[ 2.253640] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10618 13:30:59.617515 <6>[ 2.261978] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10619 13:30:59.623968 <6>[ 2.270317] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10620 13:30:59.634216 <6>[ 2.278662] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10621 13:30:59.640500 <6>[ 2.287001] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10622 13:30:59.650589 <6>[ 2.295341] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10623 13:30:59.656953 <6>[ 2.303680] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10624 13:30:59.663726 <6>[ 2.312372] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10625 13:30:59.670785 <6>[ 2.319551] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10626 13:30:59.677522 <6>[ 2.326310] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10627 13:30:59.687478 <6>[ 2.333115] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10628 13:30:59.694095 <6>[ 2.340051] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10629 13:30:59.700620 <6>[ 2.346925] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10630 13:30:59.710262 <6>[ 2.356061] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10631 13:30:59.720347 <6>[ 2.365184] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10632 13:30:59.730269 <6>[ 2.374479] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10633 13:30:59.740381 <6>[ 2.383947] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10634 13:30:59.750220 <6>[ 2.393414] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10635 13:30:59.756831 <6>[ 2.402534] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10636 13:30:59.766737 <6>[ 2.412002] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10637 13:30:59.776655 <6>[ 2.421121] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10638 13:30:59.786110 <6>[ 2.430417] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10639 13:30:59.796089 <6>[ 2.440578] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10640 13:30:59.806000 <6>[ 2.451789] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10641 13:30:59.813617 <6>[ 2.462765] Trying to probe devices needed for running init ...
10642 13:30:59.824193 <3>[ 2.470070] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10643 13:30:59.933684 <6>[ 2.579458] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10644 13:31:00.088559 <6>[ 2.737454] hub 1-1:1.0: USB hub found
10645 13:31:00.091839 <6>[ 2.742013] hub 1-1:1.0: 4 ports detected
10646 13:31:00.103181 <6>[ 2.751949] hub 1-1:1.0: USB hub found
10647 13:31:00.106240 <6>[ 2.756321] hub 1-1:1.0: 4 ports detected
10648 13:31:00.213816 <6>[ 2.859923] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10649 13:31:00.240432 <6>[ 2.889615] hub 2-1:1.0: USB hub found
10650 13:31:00.243865 <6>[ 2.894109] hub 2-1:1.0: 3 ports detected
10651 13:31:00.255277 <6>[ 2.904158] hub 2-1:1.0: USB hub found
10652 13:31:00.258599 <6>[ 2.908551] hub 2-1:1.0: 3 ports detected
10653 13:31:00.426354 <6>[ 3.071634] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10654 13:31:00.558673 <6>[ 3.207442] hub 1-1.4:1.0: USB hub found
10655 13:31:00.561891 <6>[ 3.212098] hub 1-1.4:1.0: 2 ports detected
10656 13:31:00.576439 <6>[ 3.225303] hub 1-1.4:1.0: USB hub found
10657 13:31:00.579608 <6>[ 3.229903] hub 1-1.4:1.0: 2 ports detected
10658 13:31:00.637999 <6>[ 3.283846] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10659 13:31:00.747008 <6>[ 3.392262] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10660 13:31:00.782982 <4>[ 3.429062] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10661 13:31:00.793009 <4>[ 3.438197] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10662 13:31:00.828067 <6>[ 3.477077] r8152 2-1.3:1.0 eth0: v1.12.13
10663 13:31:00.882236 <6>[ 3.527454] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10664 13:31:01.077588 <6>[ 3.723629] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10665 13:31:02.430518 <6>[ 5.079331] r8152 2-1.3:1.0 eth0: carrier on
10666 13:31:02.470396 <5>[ 5.103387] Sending DHCP requests ., OK
10667 13:31:02.476734 <6>[ 5.123665] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10668 13:31:02.480010 <6>[ 5.131955] IP-Config: Complete:
10669 13:31:02.493622 <6>[ 5.135456] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10670 13:31:02.499978 <6>[ 5.146175] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10671 13:31:02.506624 <6>[ 5.154792] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10672 13:31:02.513456 <6>[ 5.154802] nameserver0=192.168.201.1
10673 13:31:02.516466 <6>[ 5.166916] clk: Disabling unused clocks
10674 13:31:02.519817 <6>[ 5.172436] ALSA device list:
10675 13:31:02.526875 <6>[ 5.175709] No soundcards found.
10676 13:31:02.534846 <6>[ 5.183491] Freeing unused kernel memory: 8512K
10677 13:31:02.537583 <6>[ 5.188400] Run /init as init process
10678 13:31:02.547409 Loading, please wait...
10679 13:31:02.580506 Starting systemd-udevd version 252.22-1~deb12u1
10680 13:31:02.866548 <6>[ 5.512547] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10681 13:31:02.887213 <6>[ 5.533145] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10682 13:31:02.893670 <6>[ 5.540246] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10683 13:31:02.903515 <6>[ 5.541261] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10684 13:31:02.910111 <4>[ 5.556585] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10685 13:31:02.916756 <6>[ 5.558977] remoteproc remoteproc0: scp is available
10686 13:31:02.923095 <6>[ 5.566318] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10687 13:31:02.929716 <6>[ 5.570963] remoteproc remoteproc0: powering up scp
10688 13:31:02.936572 <3>[ 5.572595] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 13:31:02.946486 <3>[ 5.572614] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 13:31:02.953221 <3>[ 5.572622] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 13:31:02.962586 <6>[ 5.573725] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10692 13:31:02.969370 <6>[ 5.573750] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10693 13:31:02.979471 <6>[ 5.573756] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10694 13:31:02.986385 <6>[ 5.578998] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10695 13:31:02.996732 <6>[ 5.584203] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10696 13:31:03.000114 <6>[ 5.584231] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10697 13:31:03.010042 <3>[ 5.584332] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10698 13:31:03.016870 <3>[ 5.584384] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 13:31:03.026616 <3>[ 5.584400] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10700 13:31:03.033402 <3>[ 5.584420] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10701 13:31:03.040882 <3>[ 5.584429] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10702 13:31:03.050262 <3>[ 5.584675] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10703 13:31:03.057545 <3>[ 5.587886] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 13:31:03.067631 <3>[ 5.587936] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10705 13:31:03.073596 <3>[ 5.587949] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10706 13:31:03.083678 <3>[ 5.588090] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10707 13:31:03.090025 <3>[ 5.588104] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10708 13:31:03.100001 <3>[ 5.588114] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10709 13:31:03.106965 <3>[ 5.588133] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10710 13:31:03.113273 <3>[ 5.588142] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10711 13:31:03.123476 <4>[ 5.588220] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10712 13:31:03.129986 <6>[ 5.588229] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10713 13:31:03.136772 <4>[ 5.588340] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10714 13:31:03.146260 <3>[ 5.588610] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10715 13:31:03.153185 <6>[ 5.596884] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10716 13:31:03.162941 <4>[ 5.615176] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10717 13:31:03.166257 <4>[ 5.615176] Fallback method does not support PEC.
10718 13:31:03.176229 <6>[ 5.616287] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10719 13:31:03.182325 <3>[ 5.652593] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10720 13:31:03.192245 <6>[ 5.655595] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10721 13:31:03.195589 <6>[ 5.668085] mc: Linux media interface: v0.10
10722 13:31:03.205884 <6>[ 5.671686] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10723 13:31:03.212140 <3>[ 5.691354] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10724 13:31:03.218936 <6>[ 5.692984] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10725 13:31:03.225356 <6>[ 5.692994] pci_bus 0000:00: root bus resource [bus 00-ff]
10726 13:31:03.232096 <6>[ 5.693002] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10727 13:31:03.241861 <6>[ 5.693008] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10728 13:31:03.248399 <6>[ 5.693059] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10729 13:31:03.255203 <6>[ 5.693094] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10730 13:31:03.261633 <6>[ 5.693193] pci 0000:00:00.0: supports D1 D2
10731 13:31:03.268167 <6>[ 5.693197] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10732 13:31:03.274792 <6>[ 5.695005] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10733 13:31:03.281464 <6>[ 5.695168] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10734 13:31:03.291385 <6>[ 5.695200] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10735 13:31:03.297987 <6>[ 5.695221] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10736 13:31:03.304853 <6>[ 5.695239] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10737 13:31:03.308230 <6>[ 5.695383] pci 0000:01:00.0: supports D1 D2
10738 13:31:03.317892 <6>[ 5.695386] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10739 13:31:03.328026 <6>[ 5.704651] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10740 13:31:03.334249 <6>[ 5.712518] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10741 13:31:03.340897 <6>[ 5.721159] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10742 13:31:03.350664 <6>[ 5.728672] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10743 13:31:03.357167 <6>[ 5.736745] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10744 13:31:03.367209 <6>[ 5.736788] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10745 13:31:03.374032 <6>[ 5.736797] remoteproc remoteproc0: remote processor scp is now up
10746 13:31:03.380699 <6>[ 5.744774] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10747 13:31:03.387250 <6>[ 5.744785] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10748 13:31:03.397118 <6>[ 5.744798] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10749 13:31:03.407072 <6>[ 5.754981] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10750 13:31:03.413689 <6>[ 5.761139] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10751 13:31:03.420407 <6>[ 5.784564] videodev: Linux video capture interface: v2.00
10752 13:31:03.426796 <6>[ 5.785799] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10753 13:31:03.436717 <6>[ 5.787028] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10754 13:31:03.439972 <6>[ 5.791425] pci 0000:00:00.0: PCI bridge to [bus 01]
10755 13:31:03.446815 <6>[ 5.807887] Bluetooth: Core ver 2.22
10756 13:31:03.452948 <6>[ 5.821046] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10757 13:31:03.459708 <6>[ 5.828932] NET: Registered PF_BLUETOOTH protocol family
10758 13:31:03.466237 <6>[ 5.837841] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10759 13:31:03.472905 <6>[ 5.845414] Bluetooth: HCI device and connection manager initialized
10760 13:31:03.476104 <6>[ 5.845427] Bluetooth: HCI socket layer initialized
10761 13:31:03.483154 <6>[ 5.850665] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10762 13:31:03.489308 <6>[ 5.859060] Bluetooth: L2CAP socket layer initialized
10763 13:31:03.492547 <6>[ 5.859070] Bluetooth: SCO socket layer initialized
10764 13:31:03.499133 <6>[ 5.860818] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10765 13:31:03.512885 <6>[ 5.862354] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10766 13:31:03.518920 <6>[ 5.862475] usbcore: registered new interface driver uvcvideo
10767 13:31:03.525731 <6>[ 5.868273] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10768 13:31:03.532313 <6>[ 5.905028] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10769 13:31:03.535395 <6>[ 5.923273] usbcore: registered new interface driver btusb
10770 13:31:03.549100 <4>[ 5.924397] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10771 13:31:03.552468 <3>[ 5.924404] Bluetooth: hci0: Failed to load firmware file (-2)
10772 13:31:03.558719 <3>[ 5.924406] Bluetooth: hci0: Failed to set up firmware (-2)
10773 13:31:03.568984 <4>[ 5.924408] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10774 13:31:03.578229 <5>[ 5.933332] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10775 13:31:03.603254 <5>[ 6.249271] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10776 13:31:03.609891 <5>[ 6.256593] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10777 13:31:03.619139 <4>[ 6.265012] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10778 13:31:03.625959 <6>[ 6.273893] cfg80211: failed to load regulatory.db
10779 13:31:03.665133 <6>[ 6.311614] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10780 13:31:03.672228 <6>[ 6.319107] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10781 13:31:03.696246 <6>[ 6.345828] mt7921e 0000:01:00.0: ASIC revision: 79610010
10782 13:31:03.800686 <6>[ 6.447035] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10783 13:31:03.803816 <6>[ 6.447035]
10784 13:31:03.819285 Begin: Loading essential drivers ... done.
10785 13:31:03.822545 Begin: Running /scripts/init-premount ... done.
10786 13:31:03.829378 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10787 13:31:03.838599 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10788 13:31:03.842001 Device /sys/class/net/eth0 found
10789 13:31:03.842076 done.
10790 13:31:03.848699 Begin: Waiting up to 180 secs for any network device to become available ... done.
10791 13:31:03.878232 IP-Config: eth0 hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10792 13:31:03.929512 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10793 13:31:03.936270 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10794 13:31:03.942537 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10795 13:31:03.949114 host : mt8192-asurada-spherion-r0-cbg-2
10796 13:31:03.955966 domain : lava-rack
10797 13:31:03.959155 rootserver: 192.168.201.1 rootpath:
10798 13:31:03.962541 filename :
10799 13:31:03.962620 done.
10800 13:31:03.965616 Begin: Running /scripts/nfs-bottom ... done.
10801 13:31:03.988823 Begin: Running /scripts/init-bottom ... done.
10802 13:31:04.071025 <6>[ 6.717308] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10803 13:31:05.292941 <6>[ 7.942633] NET: Registered PF_INET6 protocol family
10804 13:31:05.300210 <6>[ 7.949633] Segment Routing with IPv6
10805 13:31:05.303465 <6>[ 7.953634] In-situ OAM (IOAM) with IPv6
10806 13:31:05.472623 <30>[ 8.095508] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10807 13:31:05.478508 <30>[ 8.128598] systemd[1]: Detected architecture arm64.
10808 13:31:05.487322
10809 13:31:05.490508 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10810 13:31:05.490590
10811 13:31:05.515225 <30>[ 8.165199] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10812 13:31:06.547402 <30>[ 9.194215] systemd[1]: Queued start job for default target graphical.target.
10813 13:31:06.582363 <30>[ 9.228812] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10814 13:31:06.589044 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10815 13:31:06.610778 <30>[ 9.257468] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10816 13:31:06.620664 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10817 13:31:06.639067 <30>[ 9.285368] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10818 13:31:06.648749 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10819 13:31:06.667480 <30>[ 9.313867] systemd[1]: Created slice user.slice - User and Session Slice.
10820 13:31:06.674134 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10821 13:31:06.697328 <30>[ 9.340497] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10822 13:31:06.707110 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10823 13:31:06.724742 <30>[ 9.367843] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10824 13:31:06.730976 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10825 13:31:06.760018 <30>[ 9.396254] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10826 13:31:06.769634 <30>[ 9.416145] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10827 13:31:06.776165 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10828 13:31:06.792875 <30>[ 9.439613] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10829 13:31:06.799613 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10830 13:31:06.817450 <30>[ 9.463675] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10831 13:31:06.827290 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10832 13:31:06.841643 <30>[ 9.491725] systemd[1]: Reached target paths.target - Path Units.
10833 13:31:06.851457 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10834 13:31:06.870009 <30>[ 9.516041] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10835 13:31:06.876191 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10836 13:31:06.889878 <30>[ 9.539591] systemd[1]: Reached target slices.target - Slice Units.
10837 13:31:06.899982 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10838 13:31:06.914541 <30>[ 9.564097] systemd[1]: Reached target swap.target - Swaps.
10839 13:31:06.921101 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10840 13:31:06.941414 <30>[ 9.588130] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10841 13:31:06.951742 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10842 13:31:06.969413 <30>[ 9.616112] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10843 13:31:06.979474 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10844 13:31:07.000213 <30>[ 9.646482] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10845 13:31:07.009653 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10846 13:31:07.027341 <30>[ 9.673802] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10847 13:31:07.036983 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10848 13:31:07.053958 <30>[ 9.700312] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10849 13:31:07.060381 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10850 13:31:07.078728 <30>[ 9.725153] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10851 13:31:07.088231 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10852 13:31:07.108313 <30>[ 9.754815] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10853 13:31:07.118261 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10854 13:31:07.133857 <30>[ 9.780124] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10855 13:31:07.143736 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10856 13:31:07.201108 <30>[ 9.847848] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10857 13:31:07.207740 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10858 13:31:07.229610 <30>[ 9.876181] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10859 13:31:07.236055 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10860 13:31:07.262009 <30>[ 9.908334] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10861 13:31:07.268384 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10862 13:31:07.295782 <30>[ 9.936040] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10863 13:31:07.345346 <30>[ 9.992204] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10864 13:31:07.355547 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10865 13:31:07.378772 <30>[ 10.025127] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10866 13:31:07.385431 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10867 13:31:07.410205 <30>[ 10.056953] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10868 13:31:07.417144 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10869 13:31:07.442283 <30>[ 10.088999] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10870 13:31:07.452208 Starting [0;1;39mmodpr<6>[ 10.098750] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10871 13:31:07.458728 obe@drm.service[0m - Load Kernel Module drm...
10872 13:31:07.482600 <30>[ 10.129163] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10873 13:31:07.492657 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10874 13:31:07.514586 <30>[ 10.161054] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10875 13:31:07.521624 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10876 13:31:07.545973 <30>[ 10.191844] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10877 13:31:07.552211 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10878 13:31:07.559353 <6>[ 10.208962] fuse: init (API version 7.37)
10879 13:31:07.579192 <30>[ 10.225073] systemd[1]: Starting systemd-journald.service - Journal Service...
10880 13:31:07.585536 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10881 13:31:07.610736 <30>[ 10.256614] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10882 13:31:07.616686 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10883 13:31:07.645402 <30>[ 10.288408] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10884 13:31:07.651685 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10885 13:31:07.714044 <30>[ 10.360498] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10886 13:31:07.723996 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10887 13:31:07.745580 <30>[ 10.391449] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10888 13:31:07.751578 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10889 13:31:07.778825 <30>[ 10.425159] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10890 13:31:07.785609 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10891 13:31:07.806303 <30>[ 10.452179] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10892 13:31:07.816338 [[0;32m OK [0m] Mounted [0;<3>[ 10.462052] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 13:31:07.822924 1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10894 13:31:07.842258 <30>[ 10.487865] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10895 13:31:07.849048 <3>[ 10.492472] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 13:31:07.858770 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10897 13:31:07.881691 <30>[ 10.528518] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10898 13:31:07.898743 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static D<3>[ 10.544814] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 13:31:07.898830 evice Nodes.
10900 13:31:07.918694 <30>[ 10.564651] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10901 13:31:07.925015 <30>[ 10.572652] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10902 13:31:07.935188 <3>[ 10.576442] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 13:31:07.945232 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10904 13:31:07.962654 <30>[ 10.608911] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10905 13:31:07.969220 <3>[ 10.611883] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 13:31:07.979217 <30>[ 10.617256] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10907 13:31:07.985825 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10908 13:31:08.001282 <3>[ 10.647803] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 13:31:08.011906 <30>[ 10.658764] systemd[1]: modprobe@drm.service: Deactivated successfully.
10910 13:31:08.019225 <30>[ 10.666565] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10911 13:31:08.033001 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 10.678003] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 13:31:08.036558 rm.service[0m - Load Kernel Module drm.
10913 13:31:08.055793 <30>[ 10.701578] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10914 13:31:08.065279 <30>[ 10.710331] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10915 13:31:08.071974 <3>[ 10.711012] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 13:31:08.082280 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10917 13:31:08.102795 <3>[ 10.749199] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 13:31:08.109055 <30>[ 10.749569] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10919 13:31:08.119994 <30>[ 10.766248] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10920 13:31:08.133405 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Mo<3>[ 10.780806] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 13:31:08.136621 dule fuse.
10922 13:31:08.155498 <30>[ 10.802242] systemd[1]: modprobe@loop.service: Deactivated successfully.
10923 13:31:08.162253 <30>[ 10.810272] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10924 13:31:08.172828 <3>[ 10.812130] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 13:31:08.179638 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10926 13:31:08.189409 <3>[ 10.835233] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 13:31:08.196153 <3>[ 10.835969] power_supply sbs-5-000b: driver failed to report `status' property: -6
10928 13:31:08.213364 <4>[ 10.844132] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10929 13:31:08.220106 <30>[ 10.845237] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10930 13:31:08.230082 <3>[ 10.872624] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 13:31:08.236267 <3>[ 10.875648] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10932 13:31:08.246329 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10933 13:31:08.266132 <3>[ 10.912905] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 13:31:08.276088 <30>[ 10.913022] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10935 13:31:08.287198 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10936 13:31:08.297551 <3>[ 10.942503] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 13:31:08.306867 <30>[ 10.953136] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10938 13:31:08.316954 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10939 13:31:08.334305 <30>[ 10.980960] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
10940 13:31:08.344829 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10941 13:31:08.362740 <30>[ 11.009077] systemd[1]: Reached target network-pre.target - Preparation for Network.
10942 13:31:08.369606 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10943 13:31:08.429367 <30>[ 11.075797] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
10944 13:31:08.435721 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10945 13:31:08.462182 <30>[ 11.108457] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
10946 13:31:08.468763 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10947 13:31:08.493210 <30>[ 11.135754] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
10948 13:31:08.509625 <30>[ 11.149385] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
10949 13:31:08.524056 <30>[ 11.170592] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
10950 13:31:08.530816 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10951 13:31:08.556533 <30>[ 11.199777] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
10952 13:31:08.598268 <30>[ 11.244530] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
10953 13:31:08.605026 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10954 13:31:08.629286 <30>[ 11.275863] systemd[1]: Starting systemd-sysusers.service - Create System Users...
10955 13:31:08.635897 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10956 13:31:08.667567 <30>[ 11.313701] systemd[1]: Started systemd-journald.service - Journal Service.
10957 13:31:08.674190 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10958 13:31:08.702924 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10959 13:31:08.722740 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10960 13:31:08.746976 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10961 13:31:08.767590 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10962 13:31:08.787456 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10963 13:31:08.825918 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10964 13:31:08.854078 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10965 13:31:08.899861 <46>[ 11.546724] systemd-journald[310]: Received client request to flush runtime journal.
10966 13:31:09.682262 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10967 13:31:09.701911 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10968 13:31:09.721095 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10969 13:31:10.037696 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10970 13:31:10.325752 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10971 13:31:10.375704 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10972 13:31:10.510879 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10973 13:31:10.571638 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10974 13:31:10.628616 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10975 13:31:10.923719 <6>[ 13.574008] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10976 13:31:10.933913 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10977 13:31:11.002723 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10978 13:31:11.102072 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10979 13:31:11.121789 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10980 13:31:11.141922 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10981 13:31:11.207295 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10982 13:31:11.213105 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10983 13:31:11.240388 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10984 13:31:11.258844 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10985 13:31:11.321701 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10986 13:31:11.351005 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10987 13:31:11.374321 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10988 13:31:11.414026 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10989 13:31:11.479601 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10990 13:31:11.497348 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10991 13:31:11.516723 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10992 13:31:11.532402 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10993 13:31:11.556930 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10994 13:31:11.575795 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10995 13:31:11.593198 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10996 13:31:11.612310 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10997 13:31:11.632660 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10998 13:31:11.648660 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10999 13:31:11.666641 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11000 13:31:11.684338 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11001 13:31:11.700622 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11002 13:31:11.741946 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11003 13:31:11.779082 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11004 13:31:11.885641 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11005 13:31:11.914480 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11006 13:31:11.959720 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11007 13:31:12.018031 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11008 13:31:12.061340 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11009 13:31:12.080534 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11010 13:31:12.185351 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11011 13:31:12.223513 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11012 13:31:12.243996 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11013 13:31:12.262861 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11014 13:31:12.285705 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11015 13:31:12.331071 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11016 13:31:12.385590 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11017 13:31:12.465302
11018 13:31:12.468633 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11019 13:31:12.468753
11020 13:31:12.471884 debian-bookworm-arm64 login: root (automatic login)
11021 13:31:12.471987
11022 13:31:12.813832 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024 aarch64
11023 13:31:12.813965
11024 13:31:12.820268 The programs included with the Debian GNU/Linux system are free software;
11025 13:31:12.827130 the exact distribution terms for each program are described in the
11026 13:31:12.830522 individual files in /usr/share/doc/*/copyright.
11027 13:31:12.830620
11028 13:31:12.836923 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11029 13:31:12.840029 permitted by applicable law.
11030 13:31:13.890249 Matched prompt #10: / #
11032 13:31:13.890493 Setting prompt string to ['/ #']
11033 13:31:13.890612 end: 2.2.5.1 login-action (duration 00:00:17) [common]
11035 13:31:13.890896 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
11036 13:31:13.891014 start: 2.2.6 expect-shell-connection (timeout 00:03:19) [common]
11037 13:31:13.891108 Setting prompt string to ['/ #']
11038 13:31:13.891192 Forcing a shell prompt, looking for ['/ #']
11039 13:31:13.891275 Sending line: ''
11041 13:31:13.941625 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11042 13:31:13.941728 Waiting using forced prompt support (timeout 00:02:30)
11043 13:31:13.946372 / #
11044 13:31:13.946663 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11045 13:31:13.946779 start: 2.2.7 export-device-env (timeout 00:03:19) [common]
11046 13:31:13.946878 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14879064/extract-nfsrootfs-qesymwcp'"
11048 13:31:14.052101 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14879064/extract-nfsrootfs-qesymwcp'
11049 13:31:14.052377 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
11051 13:31:14.157617 / # export NFS_SERVER_IP='192.168.201.1'
11052 13:31:14.157926 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11053 13:31:14.158044 end: 2.2 depthcharge-retry (duration 00:01:42) [common]
11054 13:31:14.158158 end: 2 depthcharge-action (duration 00:01:42) [common]
11055 13:31:14.158268 start: 3 lava-test-retry (timeout 00:07:36) [common]
11056 13:31:14.158382 start: 3.1 lava-test-shell (timeout 00:07:36) [common]
11057 13:31:14.158489 Using namespace: common
11058 13:31:14.158592 Sending line: '#'
11060 13:31:14.259070 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11061 13:31:14.263301 / # #
11062 13:31:14.263598 Using /lava-14879064
11063 13:31:14.263702 Sending line: 'export SHELL=/bin/bash'
11065 13:31:14.369053 / # export SHELL=/bin/bash
11066 13:31:14.369355 Sending line: '. /lava-14879064/environment'
11068 13:31:14.474556 / # . /lava-14879064/environment
11069 13:31:14.479760 Sending line: '/lava-14879064/bin/lava-test-runner /lava-14879064/0'
11071 13:31:14.580196 Test shell timeout: 10s (minimum of the action and connection timeout)
11072 13:31:14.584907 / # /lava-14879064/bin/lava-test-runner /lava-14879064/0
11073 13:31:14.867467 + export TESTRUN_ID=0_timesync-off
11074 13:31:14.870831 + TESTRUN_ID=0_timesync-off
11075 13:31:14.874133 + cd /lava-14879064/0/tests/0_timesync-off
11076 13:31:14.877181 ++ cat uuid
11077 13:31:14.881348 + UUID=14879064_1.6.2.3.1
11078 13:31:14.881432 + set +x
11079 13:31:14.887636 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14879064_1.6.2.3.1>
11080 13:31:14.887936 Received signal: <STARTRUN> 0_timesync-off 14879064_1.6.2.3.1
11081 13:31:14.888035 Starting test lava.0_timesync-off (14879064_1.6.2.3.1)
11082 13:31:14.888157 Skipping test definition patterns.
11083 13:31:14.891132 + systemctl stop systemd-timesyncd
11084 13:31:14.970792 + set +x
11085 13:31:14.974074 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14879064_1.6.2.3.1>
11086 13:31:14.974353 Received signal: <ENDRUN> 0_timesync-off 14879064_1.6.2.3.1
11087 13:31:14.974459 Ending use of test pattern.
11088 13:31:14.974544 Ending test lava.0_timesync-off (14879064_1.6.2.3.1), duration 0.09
11090 13:31:15.051557 + export TESTRUN_ID=1_kselftest-alsa
11091 13:31:15.054941 + TESTRUN_ID=1_kselftest-alsa
11092 13:31:15.061415 + cd /lava-14879064/0/tests/1_kselftest-alsa
11093 13:31:15.061520 ++ cat uuid
11094 13:31:15.068365 + UUID=14879064_1.6.2.3.5
11095 13:31:15.068462 + set +x
11096 13:31:15.074843 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14879064_1.6.2.3.5>
11097 13:31:15.075118 Received signal: <STARTRUN> 1_kselftest-alsa 14879064_1.6.2.3.5
11098 13:31:15.075208 Starting test lava.1_kselftest-alsa (14879064_1.6.2.3.5)
11099 13:31:15.075322 Skipping test definition patterns.
11100 13:31:15.077918 + cd ./automated/linux/kselftest/
11101 13:31:15.104654 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
11102 13:31:15.149322 INFO: install_deps skipped
11103 13:31:15.688213 --2024-07-18 13:31:15-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz
11104 13:31:15.708781 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11105 13:31:15.838027 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11106 13:31:15.967956 HTTP request sent, awaiting response... 200 OK
11107 13:31:15.971083 Length: 1919140 (1.8M) [application/octet-stream]
11108 13:31:15.974524 Saving to: 'kselftest_armhf.tar.gz'
11109 13:31:15.974911
11110 13:31:15.975245
11111 13:31:16.227312 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11112 13:31:16.486358 kselftest_armhf.tar 2%[ ] 47.81K 185KB/s
11113 13:31:16.925452 kselftest_armhf.tar 11%[=> ] 217.50K 420KB/s
11114 13:31:17.012301 kselftest_armhf.tar 44%[=======> ] 834.03K 871KB/s
11115 13:31:17.018880 kselftest_armhf.tar 100%[===================>] 1.83M 1.75MB/s in 1.0s
11116 13:31:17.019456
11117 13:31:17.186898 2024-07-18 13:31:17 (1.75 MB/s) - 'kselftest_armhf.tar.gz' saved [1919140/1919140]
11118 13:31:17.187031
11119 13:31:24.633804 skiplist:
11120 13:31:24.637562 ========================================
11121 13:31:24.640862 ========================================
11122 13:31:24.691895 alsa:mixer-test
11123 13:31:24.714647 ============== Tests to run ===============
11124 13:31:24.717927 alsa:mixer-test
11125 13:31:24.721001 ===========End Tests to run ===============
11126 13:31:24.725376 shardfile-alsa pass
11127 13:31:24.839691 <12>[ 27.491477] kselftest: Running tests in alsa
11128 13:31:24.849424 TAP version 13
11129 13:31:24.865063 1..1
11130 13:31:24.882809 # selftests: alsa: mixer-test
11131 13:31:25.393769 # TAP version 13
11132 13:31:25.393914 # 1..0
11133 13:31:25.400488 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11134 13:31:25.403425 ok 1 selftests: alsa: mixer-test
11135 13:31:26.903851 alsa_mixer-test pass
11136 13:31:26.981882 + ../../utils/send-to-lava.sh ./output/result.txt
11137 13:31:27.065629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11138 13:31:27.065919 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11140 13:31:27.121690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11141 13:31:27.121798 + set +x
11142 13:31:27.122083 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11144 13:31:27.128295 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14879064_1.6.2.3.5>
11145 13:31:27.128557 Received signal: <ENDRUN> 1_kselftest-alsa 14879064_1.6.2.3.5
11146 13:31:27.128652 Ending use of test pattern.
11147 13:31:27.128733 Ending test lava.1_kselftest-alsa (14879064_1.6.2.3.5), duration 12.05
11149 13:31:27.130973 <LAVA_TEST_RUNNER EXIT>
11150 13:31:27.131233 ok: lava_test_shell seems to have completed
11151 13:31:27.131324 shardfile-alsa: pass
alsa_mixer-test: pass
11152 13:31:27.131404 end: 3.1 lava-test-shell (duration 00:00:13) [common]
11153 13:31:27.131479 end: 3 lava-test-retry (duration 00:00:13) [common]
11154 13:31:27.131557 start: 4 finalize (timeout 00:07:23) [common]
11155 13:31:27.131635 start: 4.1 power-off (timeout 00:00:30) [common]
11156 13:31:27.131865 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
11157 13:31:29.205881 >> Command sent successfully.
11158 13:31:29.208931 Returned 0 in 2 seconds
11159 13:31:29.209066 end: 4.1 power-off (duration 00:00:02) [common]
11161 13:31:29.209294 start: 4.2 read-feedback (timeout 00:07:21) [common]
11162 13:31:29.209429 Listened to connection for namespace 'common' for up to 1s
11163 13:31:30.210569 Finalising connection for namespace 'common'
11164 13:31:30.210721 Disconnecting from shell: Finalise
11165 13:31:30.210805 / #
11166 13:31:30.311032 end: 4.2 read-feedback (duration 00:00:01) [common]
11167 13:31:30.311176 end: 4 finalize (duration 00:00:03) [common]
11168 13:31:30.311303 Cleaning after the job
11169 13:31:30.311410 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879064/tftp-deploy-6ha59yvu/ramdisk
11170 13:31:30.313550 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879064/tftp-deploy-6ha59yvu/kernel
11171 13:31:30.323716 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879064/tftp-deploy-6ha59yvu/dtb
11172 13:31:30.323896 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879064/tftp-deploy-6ha59yvu/nfsrootfs
11173 13:31:30.383471 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879064/tftp-deploy-6ha59yvu/modules
11174 13:31:30.388789 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14879064
11175 13:31:30.935832 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14879064
11176 13:31:30.935996 Job finished correctly