Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 43
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 89
1 13:41:46.572693 lava-dispatcher, installed at version: 2024.05
2 13:41:46.572919 start: 0 validate
3 13:41:46.573057 Start time: 2024-07-18 13:41:46.573051+00:00 (UTC)
4 13:41:46.573201 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:41:46.573359 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 13:41:46.834649 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:41:46.835389 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 13:41:47.098887 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:41:47.099698 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 13:41:47.352583 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:41:47.353162 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:41:47.604177 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:41:47.604355 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 13:41:47.869003 validate duration: 1.30
16 13:41:47.870040 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:41:47.870479 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:41:47.870844 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:41:47.871485 Not decompressing ramdisk as can be used compressed.
20 13:41:47.871878 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 13:41:47.872149 saving as /var/lib/lava/dispatcher/tmp/14879035/tftp-deploy-nycbem4k/ramdisk/initrd.cpio.gz
22 13:41:47.872430 total size: 5628169 (5 MB)
23 13:41:47.876284 progress 0 % (0 MB)
24 13:41:47.883764 progress 5 % (0 MB)
25 13:41:47.891413 progress 10 % (0 MB)
26 13:41:47.896908 progress 15 % (0 MB)
27 13:41:47.901362 progress 20 % (1 MB)
28 13:41:47.904792 progress 25 % (1 MB)
29 13:41:47.908036 progress 30 % (1 MB)
30 13:41:47.910863 progress 35 % (1 MB)
31 13:41:47.913328 progress 40 % (2 MB)
32 13:41:47.915739 progress 45 % (2 MB)
33 13:41:47.917827 progress 50 % (2 MB)
34 13:41:47.920027 progress 55 % (2 MB)
35 13:41:47.922061 progress 60 % (3 MB)
36 13:41:47.923862 progress 65 % (3 MB)
37 13:41:47.925773 progress 70 % (3 MB)
38 13:41:47.927362 progress 75 % (4 MB)
39 13:41:47.929126 progress 80 % (4 MB)
40 13:41:47.930615 progress 85 % (4 MB)
41 13:41:47.932344 progress 90 % (4 MB)
42 13:41:47.933985 progress 95 % (5 MB)
43 13:41:47.935450 progress 100 % (5 MB)
44 13:41:47.935682 5 MB downloaded in 0.06 s (84.85 MB/s)
45 13:41:47.935840 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:41:47.936082 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:41:47.936169 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:41:47.936251 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:41:47.936397 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 13:41:47.936474 saving as /var/lib/lava/dispatcher/tmp/14879035/tftp-deploy-nycbem4k/kernel/Image
52 13:41:47.936534 total size: 54813184 (52 MB)
53 13:41:47.936593 No compression specified
54 13:41:47.937718 progress 0 % (0 MB)
55 13:41:47.952628 progress 5 % (2 MB)
56 13:41:47.967939 progress 10 % (5 MB)
57 13:41:47.983382 progress 15 % (7 MB)
58 13:41:47.998459 progress 20 % (10 MB)
59 13:41:48.013754 progress 25 % (13 MB)
60 13:41:48.028704 progress 30 % (15 MB)
61 13:41:48.043827 progress 35 % (18 MB)
62 13:41:48.059217 progress 40 % (20 MB)
63 13:41:48.074248 progress 45 % (23 MB)
64 13:41:48.089453 progress 50 % (26 MB)
65 13:41:48.104785 progress 55 % (28 MB)
66 13:41:48.120584 progress 60 % (31 MB)
67 13:41:48.135437 progress 65 % (34 MB)
68 13:41:48.150463 progress 70 % (36 MB)
69 13:41:48.166117 progress 75 % (39 MB)
70 13:41:48.181621 progress 80 % (41 MB)
71 13:41:48.196400 progress 85 % (44 MB)
72 13:41:48.211173 progress 90 % (47 MB)
73 13:41:48.226360 progress 95 % (49 MB)
74 13:41:48.241578 progress 100 % (52 MB)
75 13:41:48.241842 52 MB downloaded in 0.31 s (171.22 MB/s)
76 13:41:48.241999 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:41:48.242231 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:41:48.242319 start: 1.3 download-retry (timeout 00:10:00) [common]
80 13:41:48.242404 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 13:41:48.242534 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
82 13:41:48.242602 saving as /var/lib/lava/dispatcher/tmp/14879035/tftp-deploy-nycbem4k/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
83 13:41:48.242660 total size: 57695 (0 MB)
84 13:41:48.242718 No compression specified
85 13:41:48.243940 progress 56 % (0 MB)
86 13:41:48.244262 progress 100 % (0 MB)
87 13:41:48.244472 0 MB downloaded in 0.00 s (30.41 MB/s)
88 13:41:48.244594 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:41:48.244817 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:41:48.244900 start: 1.4 download-retry (timeout 00:10:00) [common]
92 13:41:48.244989 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 13:41:48.245105 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 13:41:48.245171 saving as /var/lib/lava/dispatcher/tmp/14879035/tftp-deploy-nycbem4k/nfsrootfs/full.rootfs.tar
95 13:41:48.245230 total size: 120894716 (115 MB)
96 13:41:48.245289 Using unxz to decompress xz
97 13:41:48.246601 progress 0 % (0 MB)
98 13:41:48.611670 progress 5 % (5 MB)
99 13:41:48.981075 progress 10 % (11 MB)
100 13:41:49.352461 progress 15 % (17 MB)
101 13:41:49.702127 progress 20 % (23 MB)
102 13:41:50.034727 progress 25 % (28 MB)
103 13:41:50.405768 progress 30 % (34 MB)
104 13:41:50.753760 progress 35 % (40 MB)
105 13:41:50.939940 progress 40 % (46 MB)
106 13:41:51.138630 progress 45 % (51 MB)
107 13:41:51.462779 progress 50 % (57 MB)
108 13:41:51.848045 progress 55 % (63 MB)
109 13:41:52.215740 progress 60 % (69 MB)
110 13:41:52.587773 progress 65 % (74 MB)
111 13:41:52.957924 progress 70 % (80 MB)
112 13:41:53.333513 progress 75 % (86 MB)
113 13:41:53.691248 progress 80 % (92 MB)
114 13:41:54.057155 progress 85 % (98 MB)
115 13:41:54.418531 progress 90 % (103 MB)
116 13:41:54.789560 progress 95 % (109 MB)
117 13:41:55.175189 progress 100 % (115 MB)
118 13:41:55.181066 115 MB downloaded in 6.94 s (16.62 MB/s)
119 13:41:55.181289 end: 1.4.1 http-download (duration 00:00:07) [common]
121 13:41:55.181528 end: 1.4 download-retry (duration 00:00:07) [common]
122 13:41:55.181615 start: 1.5 download-retry (timeout 00:09:53) [common]
123 13:41:55.181697 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 13:41:55.181847 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 13:41:55.181921 saving as /var/lib/lava/dispatcher/tmp/14879035/tftp-deploy-nycbem4k/modules/modules.tar
126 13:41:55.181980 total size: 8611320 (8 MB)
127 13:41:55.182041 Using unxz to decompress xz
128 13:41:55.183389 progress 0 % (0 MB)
129 13:41:55.206269 progress 5 % (0 MB)
130 13:41:55.232941 progress 10 % (0 MB)
131 13:41:55.259075 progress 15 % (1 MB)
132 13:41:55.285921 progress 20 % (1 MB)
133 13:41:55.312112 progress 25 % (2 MB)
134 13:41:55.337776 progress 30 % (2 MB)
135 13:41:55.362611 progress 35 % (2 MB)
136 13:41:55.392186 progress 40 % (3 MB)
137 13:41:55.419367 progress 45 % (3 MB)
138 13:41:55.445871 progress 50 % (4 MB)
139 13:41:55.472821 progress 55 % (4 MB)
140 13:41:55.499274 progress 60 % (4 MB)
141 13:41:55.524849 progress 65 % (5 MB)
142 13:41:55.552966 progress 70 % (5 MB)
143 13:41:55.582421 progress 75 % (6 MB)
144 13:41:55.612305 progress 80 % (6 MB)
145 13:41:55.638903 progress 85 % (7 MB)
146 13:41:55.666300 progress 90 % (7 MB)
147 13:41:55.694367 progress 95 % (7 MB)
148 13:41:55.722005 progress 100 % (8 MB)
149 13:41:55.728636 8 MB downloaded in 0.55 s (15.02 MB/s)
150 13:41:55.728837 end: 1.5.1 http-download (duration 00:00:01) [common]
152 13:41:55.729110 end: 1.5 download-retry (duration 00:00:01) [common]
153 13:41:55.729210 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 13:41:55.729327 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 13:41:59.810101 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14879035/extract-nfsrootfs-6fdsh4oj
156 13:41:59.810290 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 13:41:59.810435 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 13:41:59.810689 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz
159 13:41:59.810901 makedir: /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin
160 13:41:59.811059 makedir: /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/tests
161 13:41:59.811215 makedir: /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/results
162 13:41:59.811354 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-add-keys
163 13:41:59.811577 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-add-sources
164 13:41:59.811781 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-background-process-start
165 13:41:59.811971 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-background-process-stop
166 13:41:59.812127 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-common-functions
167 13:41:59.812258 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-echo-ipv4
168 13:41:59.812386 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-install-packages
169 13:41:59.812527 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-installed-packages
170 13:41:59.812659 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-os-build
171 13:41:59.812788 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-probe-channel
172 13:41:59.812930 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-probe-ip
173 13:41:59.813055 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-target-ip
174 13:41:59.813178 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-target-mac
175 13:41:59.813309 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-target-storage
176 13:41:59.813445 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-test-case
177 13:41:59.813570 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-test-event
178 13:41:59.813690 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-test-feedback
179 13:41:59.813822 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-test-raise
180 13:41:59.813945 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-test-reference
181 13:41:59.814067 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-test-runner
182 13:41:59.814196 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-test-set
183 13:41:59.814317 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-test-shell
184 13:41:59.814445 Updating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-add-keys (debian)
185 13:41:59.814614 Updating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-add-sources (debian)
186 13:41:59.814755 Updating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-install-packages (debian)
187 13:41:59.814894 Updating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-installed-packages (debian)
188 13:41:59.815031 Updating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/bin/lava-os-build (debian)
189 13:41:59.815160 Creating /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/environment
190 13:41:59.815255 LAVA metadata
191 13:41:59.815330 - LAVA_JOB_ID=14879035
192 13:41:59.815391 - LAVA_DISPATCHER_IP=192.168.201.1
193 13:41:59.815507 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 13:41:59.815571 skipped lava-vland-overlay
195 13:41:59.815653 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 13:41:59.815737 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 13:41:59.815797 skipped lava-multinode-overlay
198 13:41:59.815867 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 13:41:59.815955 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 13:41:59.816032 Loading test definitions
201 13:41:59.816115 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 13:41:59.816181 Using /lava-14879035 at stage 0
203 13:41:59.816494 uuid=14879035_1.6.2.3.1 testdef=None
204 13:41:59.816582 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 13:41:59.816662 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 13:41:59.817096 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 13:41:59.817317 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 13:41:59.817893 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 13:41:59.818129 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 13:41:59.818678 runner path: /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/0/tests/0_timesync-off test_uuid 14879035_1.6.2.3.1
213 13:41:59.818848 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 13:41:59.819068 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 13:41:59.819135 Using /lava-14879035 at stage 0
217 13:41:59.819228 Fetching tests from https://github.com/kernelci/test-definitions.git
218 13:41:59.819307 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/0/tests/1_kselftest-arm64'
219 13:42:01.962079 Running '/usr/bin/git checkout kernelci.org
220 13:42:02.124550 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 13:42:02.124988 uuid=14879035_1.6.2.3.5 testdef=None
222 13:42:02.125115 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 13:42:02.125372 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 13:42:02.126122 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 13:42:02.126377 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 13:42:02.127388 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 13:42:02.127786 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 13:42:02.128767 runner path: /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/0/tests/1_kselftest-arm64 test_uuid 14879035_1.6.2.3.5
232 13:42:02.128863 BOARD='mt8183-kukui-jacuzzi-juniper-sku16'
233 13:42:02.128939 BRANCH='cip'
234 13:42:02.129018 SKIPFILE='/dev/null'
235 13:42:02.129095 SKIP_INSTALL='True'
236 13:42:02.129170 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz'
237 13:42:02.129267 TST_CASENAME=''
238 13:42:02.129360 TST_CMDFILES='arm64'
239 13:42:02.129571 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 13:42:02.129937 Creating lava-test-runner.conf files
242 13:42:02.130037 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14879035/lava-overlay-o_ru9rkz/lava-14879035/0 for stage 0
243 13:42:02.130174 - 0_timesync-off
244 13:42:02.130282 - 1_kselftest-arm64
245 13:42:02.130431 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 13:42:02.130554 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 13:42:10.153032 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 13:42:10.153173 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 13:42:10.153266 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 13:42:10.153367 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 13:42:10.153454 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 13:42:10.310481 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 13:42:10.310638 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 13:42:10.310723 extracting modules file /var/lib/lava/dispatcher/tmp/14879035/tftp-deploy-nycbem4k/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14879035/extract-nfsrootfs-6fdsh4oj
255 13:42:10.553561 extracting modules file /var/lib/lava/dispatcher/tmp/14879035/tftp-deploy-nycbem4k/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14879035/extract-overlay-ramdisk-le7bhvde/ramdisk
256 13:42:10.838325 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 13:42:10.838471 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 13:42:10.838556 [common] Applying overlay to NFS
259 13:42:10.838621 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14879035/compress-overlay-uk7smwju/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14879035/extract-nfsrootfs-6fdsh4oj
260 13:42:11.830534 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 13:42:11.830687 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 13:42:11.830777 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 13:42:11.830871 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 13:42:11.830946 Building ramdisk /var/lib/lava/dispatcher/tmp/14879035/extract-overlay-ramdisk-le7bhvde/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14879035/extract-overlay-ramdisk-le7bhvde/ramdisk
265 13:42:12.139545 >> 129966 blocks
266 13:42:14.463859 rename /var/lib/lava/dispatcher/tmp/14879035/extract-overlay-ramdisk-le7bhvde/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14879035/tftp-deploy-nycbem4k/ramdisk/ramdisk.cpio.gz
267 13:42:14.464043 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 13:42:14.464181 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 13:42:14.464285 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 13:42:14.464401 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14879035/tftp-deploy-nycbem4k/kernel/Image']
271 13:42:29.327615 Returned 0 in 14 seconds
272 13:42:29.327814 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14879035/tftp-deploy-nycbem4k/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14879035/tftp-deploy-nycbem4k/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14879035/tftp-deploy-nycbem4k/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14879035/tftp-deploy-nycbem4k/kernel/image.itb
273 13:42:30.017924 output: FIT description: Kernel Image image with one or more FDT blobs
274 13:42:30.018064 output: Created: Thu Jul 18 14:42:29 2024
275 13:42:30.018131 output: Image 0 (kernel-1)
276 13:42:30.018190 output: Description:
277 13:42:30.018248 output: Created: Thu Jul 18 14:42:29 2024
278 13:42:30.018303 output: Type: Kernel Image
279 13:42:30.018359 output: Compression: lzma compressed
280 13:42:30.018416 output: Data Size: 13114469 Bytes = 12807.10 KiB = 12.51 MiB
281 13:42:30.018472 output: Architecture: AArch64
282 13:42:30.018526 output: OS: Linux
283 13:42:30.018578 output: Load Address: 0x00000000
284 13:42:30.018631 output: Entry Point: 0x00000000
285 13:42:30.018684 output: Hash algo: crc32
286 13:42:30.018737 output: Hash value: a47b020b
287 13:42:30.018790 output: Image 1 (fdt-1)
288 13:42:30.018842 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
289 13:42:30.018894 output: Created: Thu Jul 18 14:42:29 2024
290 13:42:30.018946 output: Type: Flat Device Tree
291 13:42:30.019003 output: Compression: uncompressed
292 13:42:30.019063 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
293 13:42:30.019118 output: Architecture: AArch64
294 13:42:30.019170 output: Hash algo: crc32
295 13:42:30.019222 output: Hash value: a9713552
296 13:42:30.019274 output: Image 2 (ramdisk-1)
297 13:42:30.019325 output: Description: unavailable
298 13:42:30.019377 output: Created: Thu Jul 18 14:42:29 2024
299 13:42:30.019430 output: Type: RAMDisk Image
300 13:42:30.019501 output: Compression: uncompressed
301 13:42:30.019555 output: Data Size: 18723980 Bytes = 18285.14 KiB = 17.86 MiB
302 13:42:30.019608 output: Architecture: AArch64
303 13:42:30.019660 output: OS: Linux
304 13:42:30.019712 output: Load Address: unavailable
305 13:42:30.019763 output: Entry Point: unavailable
306 13:42:30.019815 output: Hash algo: crc32
307 13:42:30.019867 output: Hash value: 134a8019
308 13:42:30.019918 output: Default Configuration: 'conf-1'
309 13:42:30.019970 output: Configuration 0 (conf-1)
310 13:42:30.020021 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
311 13:42:30.020072 output: Kernel: kernel-1
312 13:42:30.020123 output: Init Ramdisk: ramdisk-1
313 13:42:30.020174 output: FDT: fdt-1
314 13:42:30.020226 output: Loadables: kernel-1
315 13:42:30.020277 output:
316 13:42:30.020383 end: 1.6.8.1 prepare-fit (duration 00:00:16) [common]
317 13:42:30.020464 end: 1.6.8 prepare-kernel (duration 00:00:16) [common]
318 13:42:30.020552 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 13:42:30.020631 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 13:42:30.020693 No LXC device requested
321 13:42:30.020763 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 13:42:30.020838 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 13:42:30.020910 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 13:42:30.020968 Checking files for TFTP limit of 4294967296 bytes.
325 13:42:30.021400 end: 1 tftp-deploy (duration 00:00:42) [common]
326 13:42:30.021496 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 13:42:30.021581 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 13:42:30.021678 substitutions:
329 13:42:30.021742 - {DTB}: 14879035/tftp-deploy-nycbem4k/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
330 13:42:30.021802 - {INITRD}: 14879035/tftp-deploy-nycbem4k/ramdisk/ramdisk.cpio.gz
331 13:42:30.021860 - {KERNEL}: 14879035/tftp-deploy-nycbem4k/kernel/Image
332 13:42:30.021916 - {LAVA_MAC}: None
333 13:42:30.021971 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14879035/extract-nfsrootfs-6fdsh4oj
334 13:42:30.022025 - {NFS_SERVER_IP}: 192.168.201.1
335 13:42:30.022079 - {PRESEED_CONFIG}: None
336 13:42:30.022137 - {PRESEED_LOCAL}: None
337 13:42:30.022191 - {RAMDISK}: 14879035/tftp-deploy-nycbem4k/ramdisk/ramdisk.cpio.gz
338 13:42:30.022243 - {ROOT_PART}: None
339 13:42:30.022296 - {ROOT}: None
340 13:42:30.022349 - {SERVER_IP}: 192.168.201.1
341 13:42:30.022401 - {TEE}: None
342 13:42:30.022453 Parsed boot commands:
343 13:42:30.022505 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 13:42:30.022651 Parsed boot commands: tftpboot 192.168.201.1 14879035/tftp-deploy-nycbem4k/kernel/image.itb 14879035/tftp-deploy-nycbem4k/kernel/cmdline
345 13:42:30.022738 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 13:42:30.022818 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 13:42:30.022897 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 13:42:30.022973 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 13:42:30.023044 Not connected, no need to disconnect.
350 13:42:30.023116 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 13:42:30.023196 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 13:42:30.023256 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-2'
353 13:42:30.026475 Setting prompt string to ['lava-test: # ']
354 13:42:30.026816 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 13:42:30.026918 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 13:42:30.027020 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 13:42:30.027136 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 13:42:30.027488 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-2', '--port=1', '--command=reboot']
359 13:42:39.228831 >> Command sent successfully.
360 13:42:39.246419 Returned 0 in 9 seconds
361 13:42:39.247289 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 13:42:39.248565 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 13:42:39.248988 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 13:42:39.249344 Setting prompt string to 'Starting depthcharge on Juniper...'
366 13:42:39.249625 Changing prompt to 'Starting depthcharge on Juniper...'
367 13:42:39.249913 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
368 13:42:39.251446 [Enter `^Ec?' for help]
369 13:42:45.900599 [DL] 00000000 00000000 010701
370 13:42:45.905449
371 13:42:45.905610
372 13:42:45.905734 F0: 102B 0000
373 13:42:45.905857
374 13:42:45.908734 F3: 1006 0033 [0200]
375 13:42:45.908894
376 13:42:45.909040 F3: 4001 00E0 [0200]
377 13:42:45.909165
378 13:42:45.909302 F3: 0000 0000
379 13:42:45.912213
380 13:42:45.912396 V0: 0000 0000 [0001]
381 13:42:45.912545
382 13:42:45.912673 00: 1027 0002
383 13:42:45.915398
384 13:42:45.915669 01: 0000 0000
385 13:42:45.915862
386 13:42:45.916016 BP: 0C00 0251 [0000]
387 13:42:45.916185
388 13:42:45.918693 G0: 1182 0000
389 13:42:45.918900
390 13:42:45.919128 EC: 0004 0000 [0001]
391 13:42:45.919313
392 13:42:45.921935 S7: 0000 0000 [0000]
393 13:42:45.922291
394 13:42:45.925544 CC: 0000 0000 [0001]
395 13:42:45.925985
396 13:42:45.926366 T0: 0000 00DB [000F]
397 13:42:45.926738
398 13:42:45.927057 Jump to BL
399 13:42:45.928699
400 13:42:45.961161
401 13:42:45.961248
402 13:42:45.971145 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
403 13:42:45.974827 ARM64: Exception handlers installed.
404 13:42:45.974912 ARM64: Testing exception
405 13:42:45.977710 ARM64: Done test exception
406 13:42:45.981331 WDT: Last reset was cold boot
407 13:42:45.984894 SPI0(PAD0) initialized at 992727 Hz
408 13:42:45.988018 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
409 13:42:45.988105 Manufacturer: ef
410 13:42:45.994639 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
411 13:42:46.007933 Probing TPM: . done!
412 13:42:46.008018 TPM ready after 0 ms
413 13:42:46.014667 Connected to device vid:did:rid of 1ae0:0028:00
414 13:42:46.024457 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.3.25/cr50_v1.9308_87_mp.398-afa1dd1
415 13:42:46.055310 Initialized TPM device CR50 revision 0
416 13:42:46.067359 tlcl_send_startup: Startup return code is 0
417 13:42:46.067781 TPM: setup succeeded
418 13:42:46.075231 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
419 13:42:46.078476 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
420 13:42:46.081778 in-header: 03 19 00 00 08 00 00 00
421 13:42:46.085216 in-data: a2 e0 47 00 13 00 00 00
422 13:42:46.088329 Chrome EC: UHEPI supported
423 13:42:46.095054 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
424 13:42:46.098326 in-header: 03 a1 00 00 08 00 00 00
425 13:42:46.101625 in-data: 84 60 60 10 00 00 00 00
426 13:42:46.101986 Phase 1
427 13:42:46.104745 FMAP: area GBB found @ 3f5000 (12032 bytes)
428 13:42:46.111168 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
429 13:42:46.117812 VB2:vb2_check_recovery() Recovery was requested manually
430 13:42:46.121381 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
431 13:42:46.125418 Recovery requested (1009000e)
432 13:42:46.133715 tlcl_extend: response is 0
433 13:42:46.142080 tlcl_extend: response is 0
434 13:42:46.166840
435 13:42:46.167402
436 13:42:46.176793 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
437 13:42:46.180143 ARM64: Exception handlers installed.
438 13:42:46.180498 ARM64: Testing exception
439 13:42:46.183258 ARM64: Done test exception
440 13:42:46.199618 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0x926b, sec=0x2000
441 13:42:46.206451 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
442 13:42:46.209478 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
443 13:42:46.217217 [RTC]rtc_get_frequency_meter,134: input=0xf, output=863
444 13:42:46.224323 [RTC]rtc_get_frequency_meter,134: input=0x7, output=734
445 13:42:46.231345 [RTC]rtc_get_frequency_meter,134: input=0xb, output=799
446 13:42:46.238131 [RTC]rtc_get_frequency_meter,134: input=0x9, output=767
447 13:42:46.245157 [RTC]rtc_get_frequency_meter,134: input=0xa, output=784
448 13:42:46.252147 [RTC]rtc_get_frequency_meter,134: input=0xa, output=781
449 13:42:46.259088 [RTC]rtc_get_frequency_meter,134: input=0xb, output=798
450 13:42:46.265553 [RTC]rtc_osc_init,208: EOSC32 cali val = 0x926b
451 13:42:46.268563 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
452 13:42:46.272022 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
453 13:42:46.278627 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
454 13:42:46.282248 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
455 13:42:46.285272 in-header: 03 19 00 00 08 00 00 00
456 13:42:46.288389 in-data: a2 e0 47 00 13 00 00 00
457 13:42:46.288778 Chrome EC: UHEPI supported
458 13:42:46.295747 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
459 13:42:46.298272 in-header: 03 a1 00 00 08 00 00 00
460 13:42:46.301299 in-data: 84 60 60 10 00 00 00 00
461 13:42:46.304642 Skip loading cached calibration data
462 13:42:46.311228 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
463 13:42:46.314644 in-header: 03 a1 00 00 08 00 00 00
464 13:42:46.317824 in-data: 84 60 60 10 00 00 00 00
465 13:42:46.324502 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
466 13:42:46.327615 in-header: 03 a1 00 00 08 00 00 00
467 13:42:46.331163 in-data: 84 60 60 10 00 00 00 00
468 13:42:46.334387 ADC[3]: Raw value=215404 ID=1
469 13:42:46.337494 Manufacturer: ef
470 13:42:46.340987 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
471 13:42:46.347428 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
472 13:42:46.347880 CBFS @ 21000 size 3d4000
473 13:42:46.353917 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
474 13:42:46.357277 CBFS: Locating 'sdram-lpddr4x-H9HCNNNCPMALHR-4GB'
475 13:42:46.360422 CBFS: Found @ offset 3c700 size 44
476 13:42:46.363720 DRAM-K: Full Calibration
477 13:42:46.366860 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
478 13:42:46.370356 CBFS @ 21000 size 3d4000
479 13:42:46.377075 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
480 13:42:46.377436 CBFS: Locating 'fallback/dram'
481 13:42:46.383848 CBFS: Found @ offset 24b00 size 12268
482 13:42:46.409860 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps
483 13:42:46.413407 ddr_geometry: 1, config: 0x0
484 13:42:46.416372 header.status = 0x0
485 13:42:46.419962 header.magic = 0x44524d4b (expected: 0x44524d4b)
486 13:42:46.423227 header.version = 0x5 (expected: 0x5)
487 13:42:46.426099 header.size = 0x8f0 (expected: 0x8f0)
488 13:42:46.429420 header.config = 0x0
489 13:42:46.429510 header.flags = 0x0
490 13:42:46.432521 header.checksum = 0x0
491 13:42:46.439058 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
492 13:42:46.442624 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
493 13:42:46.448765 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
494 13:42:46.448865 ddr_geometry:1
495 13:42:46.452394 [EMI] new MDL number = 1
496 13:42:46.452485 dram_cbt_mode_extern: 0
497 13:42:46.455580 dram_cbt_mode [RK0]: 0, [RK1]: 0
498 13:42:46.462513 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
499 13:42:46.462641
500 13:42:46.462743
501 13:42:46.465767 [Bianco] ETT version 0.0.0.1
502 13:42:46.469035 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
503 13:42:46.469124
504 13:42:46.472391 vSetVcoreByFreq with vcore:762500, freq=1600
505 13:42:46.472480
506 13:42:46.475596 [DramcInit]
507 13:42:46.478829 AutoRefreshCKEOff AutoREF OFF
508 13:42:46.478916 DDRPhyPLLSetting-CKEOFF
509 13:42:46.481983 DDRPhyPLLSetting-CKEON
510 13:42:46.482070
511 13:42:46.482157 Enable WDQS
512 13:42:46.486920 [ModeRegInit_LP4] CH0 RK0
513 13:42:46.490393 Write Rank0 MR13 =0x18
514 13:42:46.490489 Write Rank0 MR12 =0x5d
515 13:42:46.493708 Write Rank0 MR1 =0x56
516 13:42:46.496696 Write Rank0 MR2 =0x1a
517 13:42:46.496786 Write Rank0 MR11 =0x0
518 13:42:46.500165 Write Rank0 MR22 =0x38
519 13:42:46.503385 Write Rank0 MR14 =0x5d
520 13:42:46.503481 Write Rank0 MR3 =0x30
521 13:42:46.506717 Write Rank0 MR13 =0x58
522 13:42:46.506806 Write Rank0 MR12 =0x5d
523 13:42:46.509979 Write Rank0 MR1 =0x56
524 13:42:46.513219 Write Rank0 MR2 =0x2d
525 13:42:46.513307 Write Rank0 MR11 =0x23
526 13:42:46.516440 Write Rank0 MR22 =0x34
527 13:42:46.519681 Write Rank0 MR14 =0x10
528 13:42:46.519769 Write Rank0 MR3 =0x30
529 13:42:46.522897 Write Rank0 MR13 =0xd8
530 13:42:46.522986 [ModeRegInit_LP4] CH0 RK1
531 13:42:46.526106 Write Rank1 MR13 =0x18
532 13:42:46.529787 Write Rank1 MR12 =0x5d
533 13:42:46.529881 Write Rank1 MR1 =0x56
534 13:42:46.532905 Write Rank1 MR2 =0x1a
535 13:42:46.536208 Write Rank1 MR11 =0x0
536 13:42:46.536298 Write Rank1 MR22 =0x38
537 13:42:46.539296 Write Rank1 MR14 =0x5d
538 13:42:46.539385 Write Rank1 MR3 =0x30
539 13:42:46.542897 Write Rank1 MR13 =0x58
540 13:42:46.546026 Write Rank1 MR12 =0x5d
541 13:42:46.546114 Write Rank1 MR1 =0x56
542 13:42:46.549104 Write Rank1 MR2 =0x2d
543 13:42:46.552634 Write Rank1 MR11 =0x23
544 13:42:46.552722 Write Rank1 MR22 =0x34
545 13:42:46.555821 Write Rank1 MR14 =0x10
546 13:42:46.555908 Write Rank1 MR3 =0x30
547 13:42:46.559023 Write Rank1 MR13 =0xd8
548 13:42:46.562250 [ModeRegInit_LP4] CH1 RK0
549 13:42:46.562337 Write Rank0 MR13 =0x18
550 13:42:46.565691 Write Rank0 MR12 =0x5d
551 13:42:46.568866 Write Rank0 MR1 =0x56
552 13:42:46.568955 Write Rank0 MR2 =0x1a
553 13:42:46.571993 Write Rank0 MR11 =0x0
554 13:42:46.572081 Write Rank0 MR22 =0x38
555 13:42:46.575580 Write Rank0 MR14 =0x5d
556 13:42:46.578626 Write Rank0 MR3 =0x30
557 13:42:46.578714 Write Rank0 MR13 =0x58
558 13:42:46.582079 Write Rank0 MR12 =0x5d
559 13:42:46.585212 Write Rank0 MR1 =0x56
560 13:42:46.585299 Write Rank0 MR2 =0x2d
561 13:42:46.588627 Write Rank0 MR11 =0x23
562 13:42:46.588719 Write Rank0 MR22 =0x34
563 13:42:46.591747 Write Rank0 MR14 =0x10
564 13:42:46.595230 Write Rank0 MR3 =0x30
565 13:42:46.595320 Write Rank0 MR13 =0xd8
566 13:42:46.598343 [ModeRegInit_LP4] CH1 RK1
567 13:42:46.601669 Write Rank1 MR13 =0x18
568 13:42:46.601756 Write Rank1 MR12 =0x5d
569 13:42:46.604933 Write Rank1 MR1 =0x56
570 13:42:46.605021 Write Rank1 MR2 =0x1a
571 13:42:46.608316 Write Rank1 MR11 =0x0
572 13:42:46.611446 Write Rank1 MR22 =0x38
573 13:42:46.611565 Write Rank1 MR14 =0x5d
574 13:42:46.614560 Write Rank1 MR3 =0x30
575 13:42:46.618209 Write Rank1 MR13 =0x58
576 13:42:46.618295 Write Rank1 MR12 =0x5d
577 13:42:46.621268 Write Rank1 MR1 =0x56
578 13:42:46.621351 Write Rank1 MR2 =0x2d
579 13:42:46.624645 Write Rank1 MR11 =0x23
580 13:42:46.627754 Write Rank1 MR22 =0x34
581 13:42:46.627839 Write Rank1 MR14 =0x10
582 13:42:46.631039 Write Rank1 MR3 =0x30
583 13:42:46.634555 Write Rank1 MR13 =0xd8
584 13:42:46.634639 match AC timing 3
585 13:42:46.644328 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
586 13:42:46.644416 [MiockJmeterHQA]
587 13:42:46.650922 vSetVcoreByFreq with vcore:762500, freq=1600
588 13:42:46.755094
589 13:42:46.755232 MIOCK jitter meter ch=0
590 13:42:46.755299
591 13:42:46.758342 1T = (102-18) = 84 dly cells
592 13:42:46.764699 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 744/100 ps
593 13:42:46.768176 vSetVcoreByFreq with vcore:725000, freq=1200
594 13:42:46.868434
595 13:42:46.868567 MIOCK jitter meter ch=0
596 13:42:46.868636
597 13:42:46.871555 1T = (97-17) = 80 dly cells
598 13:42:46.878325 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
599 13:42:46.881802 vSetVcoreByFreq with vcore:725000, freq=800
600 13:42:46.981937
601 13:42:46.982066 MIOCK jitter meter ch=0
602 13:42:46.982134
603 13:42:46.985089 1T = (97-17) = 80 dly cells
604 13:42:46.991737 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
605 13:42:46.994726 vSetVcoreByFreq with vcore:762500, freq=1600
606 13:42:46.998324 vSetVcoreByFreq with vcore:762500, freq=1600
607 13:42:46.998436
608 13:42:46.998504 K DRVP
609 13:42:47.001309 1. OCD DRVP=0 CALOUT=0
610 13:42:47.004673 1. OCD DRVP=1 CALOUT=0
611 13:42:47.004775 1. OCD DRVP=2 CALOUT=0
612 13:42:47.007922 1. OCD DRVP=3 CALOUT=0
613 13:42:47.011285 1. OCD DRVP=4 CALOUT=0
614 13:42:47.011413 1. OCD DRVP=5 CALOUT=0
615 13:42:47.014416 1. OCD DRVP=6 CALOUT=0
616 13:42:47.017815 1. OCD DRVP=7 CALOUT=0
617 13:42:47.017925 1. OCD DRVP=8 CALOUT=1
618 13:42:47.018017
619 13:42:47.021191 1. OCD DRVP calibration OK! DRVP=8
620 13:42:47.021311
621 13:42:47.021378
622 13:42:47.021439
623 13:42:47.024469 K ODTN
624 13:42:47.024570 3. OCD ODTN=0 ,CALOUT=1
625 13:42:47.027397 3. OCD ODTN=1 ,CALOUT=1
626 13:42:47.030876 3. OCD ODTN=2 ,CALOUT=1
627 13:42:47.031003 3. OCD ODTN=3 ,CALOUT=1
628 13:42:47.033959 3. OCD ODTN=4 ,CALOUT=1
629 13:42:47.034064 3. OCD ODTN=5 ,CALOUT=1
630 13:42:47.037317 3. OCD ODTN=6 ,CALOUT=1
631 13:42:47.040610 3. OCD ODTN=7 ,CALOUT=0
632 13:42:47.040783
633 13:42:47.043923 3. OCD ODTN calibration OK! ODTN=7
634 13:42:47.044054
635 13:42:47.047426 [SwImpedanceCal] DRVP=8, DRVN=9, ODTN=7
636 13:42:47.050624 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15
637 13:42:47.057042 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15 (After Adjust)
638 13:42:47.057198
639 13:42:47.057295 K DRVP
640 13:42:47.060210 1. OCD DRVP=0 CALOUT=0
641 13:42:47.060327 1. OCD DRVP=1 CALOUT=0
642 13:42:47.063788 1. OCD DRVP=2 CALOUT=0
643 13:42:47.066954 1. OCD DRVP=3 CALOUT=0
644 13:42:47.067049 1. OCD DRVP=4 CALOUT=0
645 13:42:47.070274 1. OCD DRVP=5 CALOUT=0
646 13:42:47.070401 1. OCD DRVP=6 CALOUT=0
647 13:42:47.073546 1. OCD DRVP=7 CALOUT=0
648 13:42:47.076785 1. OCD DRVP=8 CALOUT=0
649 13:42:47.076879 1. OCD DRVP=9 CALOUT=0
650 13:42:47.079907 1. OCD DRVP=10 CALOUT=1
651 13:42:47.079998
652 13:42:47.083074 1. OCD DRVP calibration OK! DRVP=10
653 13:42:47.083165
654 13:42:47.083236
655 13:42:47.083364
656 13:42:47.083465 K ODTN
657 13:42:47.086630 3. OCD ODTN=0 ,CALOUT=1
658 13:42:47.089833 3. OCD ODTN=1 ,CALOUT=1
659 13:42:47.089936 3. OCD ODTN=2 ,CALOUT=1
660 13:42:47.093000 3. OCD ODTN=3 ,CALOUT=1
661 13:42:47.096385 3. OCD ODTN=4 ,CALOUT=1
662 13:42:47.096511 3. OCD ODTN=5 ,CALOUT=1
663 13:42:47.099566 3. OCD ODTN=6 ,CALOUT=1
664 13:42:47.103073 3. OCD ODTN=7 ,CALOUT=1
665 13:42:47.103197 3. OCD ODTN=8 ,CALOUT=1
666 13:42:47.106193 3. OCD ODTN=9 ,CALOUT=1
667 13:42:47.109419 3. OCD ODTN=10 ,CALOUT=1
668 13:42:47.109529 3. OCD ODTN=11 ,CALOUT=1
669 13:42:47.112733 3. OCD ODTN=12 ,CALOUT=1
670 13:42:47.116114 3. OCD ODTN=13 ,CALOUT=1
671 13:42:47.116207 3. OCD ODTN=14 ,CALOUT=1
672 13:42:47.119303 3. OCD ODTN=15 ,CALOUT=0
673 13:42:47.119416
674 13:42:47.122645 3. OCD ODTN calibration OK! ODTN=15
675 13:42:47.122782
676 13:42:47.125877 [SwImpedanceCal] DRVP=10, DRVN=9, ODTN=15
677 13:42:47.128983 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15
678 13:42:47.135612 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15 (After Adjust)
679 13:42:47.135746
680 13:42:47.135842 [DramcInit]
681 13:42:47.138973 AutoRefreshCKEOff AutoREF OFF
682 13:42:47.142037 DDRPhyPLLSetting-CKEOFF
683 13:42:47.145410 DDRPhyPLLSetting-CKEON
684 13:42:47.145496
685 13:42:47.145558 Enable WDQS
686 13:42:47.145617 ==
687 13:42:47.152114 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
688 13:42:47.155442 fsp= 1, odt_onoff= 1, Byte mode= 0
689 13:42:47.155574 ==
690 13:42:47.155648 [Duty_Offset_Calibration]
691 13:42:47.155710
692 13:42:47.158627 ===========================
693 13:42:47.161788 B0:1 B1:-1 CA:0
694 13:42:47.181368 ==
695 13:42:47.184784 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
696 13:42:47.187841 fsp= 1, odt_onoff= 1, Byte mode= 0
697 13:42:47.187943 ==
698 13:42:47.191328 [Duty_Offset_Calibration]
699 13:42:47.191433
700 13:42:47.194499 ===========================
701 13:42:47.194596 B0:0 B1:0 CA:0
702 13:42:47.226735 [ModeRegInit_LP4] CH0 RK0
703 13:42:47.230256 Write Rank0 MR13 =0x18
704 13:42:47.230376 Write Rank0 MR12 =0x5d
705 13:42:47.233370 Write Rank0 MR1 =0x56
706 13:42:47.236539 Write Rank0 MR2 =0x1a
707 13:42:47.236642 Write Rank0 MR11 =0x0
708 13:42:47.240080 Write Rank0 MR22 =0x38
709 13:42:47.243015 Write Rank0 MR14 =0x5d
710 13:42:47.243105 Write Rank0 MR3 =0x30
711 13:42:47.246370 Write Rank0 MR13 =0x58
712 13:42:47.246460 Write Rank0 MR12 =0x5d
713 13:42:47.249873 Write Rank0 MR1 =0x56
714 13:42:47.252874 Write Rank0 MR2 =0x2d
715 13:42:47.252970 Write Rank0 MR11 =0x23
716 13:42:47.256418 Write Rank0 MR22 =0x34
717 13:42:47.259348 Write Rank0 MR14 =0x10
718 13:42:47.259476 Write Rank0 MR3 =0x30
719 13:42:47.262901 Write Rank0 MR13 =0xd8
720 13:42:47.263010 [ModeRegInit_LP4] CH0 RK1
721 13:42:47.266109 Write Rank1 MR13 =0x18
722 13:42:47.269192 Write Rank1 MR12 =0x5d
723 13:42:47.269282 Write Rank1 MR1 =0x56
724 13:42:47.272744 Write Rank1 MR2 =0x1a
725 13:42:47.275885 Write Rank1 MR11 =0x0
726 13:42:47.275979 Write Rank1 MR22 =0x38
727 13:42:47.279230 Write Rank1 MR14 =0x5d
728 13:42:47.279320 Write Rank1 MR3 =0x30
729 13:42:47.282182 Write Rank1 MR13 =0x58
730 13:42:47.285773 Write Rank1 MR12 =0x5d
731 13:42:47.285870 Write Rank1 MR1 =0x56
732 13:42:47.288872 Write Rank1 MR2 =0x2d
733 13:42:47.292072 Write Rank1 MR11 =0x23
734 13:42:47.292177 Write Rank1 MR22 =0x34
735 13:42:47.295209 Write Rank1 MR14 =0x10
736 13:42:47.295304 Write Rank1 MR3 =0x30
737 13:42:47.298820 Write Rank1 MR13 =0xd8
738 13:42:47.302190 [ModeRegInit_LP4] CH1 RK0
739 13:42:47.302286 Write Rank0 MR13 =0x18
740 13:42:47.305321 Write Rank0 MR12 =0x5d
741 13:42:47.308561 Write Rank0 MR1 =0x56
742 13:42:47.308656 Write Rank0 MR2 =0x1a
743 13:42:47.311790 Write Rank0 MR11 =0x0
744 13:42:47.311883 Write Rank0 MR22 =0x38
745 13:42:47.314815 Write Rank0 MR14 =0x5d
746 13:42:47.318374 Write Rank0 MR3 =0x30
747 13:42:47.318478 Write Rank0 MR13 =0x58
748 13:42:47.321673 Write Rank0 MR12 =0x5d
749 13:42:47.324948 Write Rank0 MR1 =0x56
750 13:42:47.325052 Write Rank0 MR2 =0x2d
751 13:42:47.328085 Write Rank0 MR11 =0x23
752 13:42:47.328195 Write Rank0 MR22 =0x34
753 13:42:47.331565 Write Rank0 MR14 =0x10
754 13:42:47.334704 Write Rank0 MR3 =0x30
755 13:42:47.334805 Write Rank0 MR13 =0xd8
756 13:42:47.337953 [ModeRegInit_LP4] CH1 RK1
757 13:42:47.341441 Write Rank1 MR13 =0x18
758 13:42:47.341541 Write Rank1 MR12 =0x5d
759 13:42:47.344513 Write Rank1 MR1 =0x56
760 13:42:47.347881 Write Rank1 MR2 =0x1a
761 13:42:47.347981 Write Rank1 MR11 =0x0
762 13:42:47.351065 Write Rank1 MR22 =0x38
763 13:42:47.351166 Write Rank1 MR14 =0x5d
764 13:42:47.354401 Write Rank1 MR3 =0x30
765 13:42:47.357816 Write Rank1 MR13 =0x58
766 13:42:47.357918 Write Rank1 MR12 =0x5d
767 13:42:47.360876 Write Rank1 MR1 =0x56
768 13:42:47.360973 Write Rank1 MR2 =0x2d
769 13:42:47.363986 Write Rank1 MR11 =0x23
770 13:42:47.367443 Write Rank1 MR22 =0x34
771 13:42:47.367554 Write Rank1 MR14 =0x10
772 13:42:47.370686 Write Rank1 MR3 =0x30
773 13:42:47.373907 Write Rank1 MR13 =0xd8
774 13:42:47.374031 match AC timing 3
775 13:42:47.383866 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
776 13:42:47.386974 DramC Write-DBI off
777 13:42:47.387103 DramC Read-DBI off
778 13:42:47.390653 Write Rank0 MR13 =0x59
779 13:42:47.390751 ==
780 13:42:47.393792 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
781 13:42:47.396908 fsp= 1, odt_onoff= 1, Byte mode= 0
782 13:42:47.396999 ==
783 13:42:47.400089 === u2Vref_new: 0x56 --> 0x2d
784 13:42:47.403288 === u2Vref_new: 0x58 --> 0x38
785 13:42:47.406796 === u2Vref_new: 0x5a --> 0x39
786 13:42:47.409866 === u2Vref_new: 0x5c --> 0x3c
787 13:42:47.413445 === u2Vref_new: 0x5e --> 0x3d
788 13:42:47.416728 === u2Vref_new: 0x60 --> 0xa0
789 13:42:47.419889 [CA 0] Center 34 (5~63) winsize 59
790 13:42:47.423129 [CA 1] Center 35 (7~63) winsize 57
791 13:42:47.426315 [CA 2] Center 28 (-1~58) winsize 60
792 13:42:47.429493 [CA 3] Center 23 (-4~51) winsize 56
793 13:42:47.432748 [CA 4] Center 24 (-4~53) winsize 58
794 13:42:47.436259 [CA 5] Center 29 (0~59) winsize 60
795 13:42:47.436355
796 13:42:47.439291 [CATrainingPosCal] consider 1 rank data
797 13:42:47.442645 u2DelayCellTimex100 = 744/100 ps
798 13:42:47.445778 CA0 delay=34 (5~63),Diff = 11 PI (14 cell)
799 13:42:47.449258 CA1 delay=35 (7~63),Diff = 12 PI (15 cell)
800 13:42:47.452722 CA2 delay=28 (-1~58),Diff = 5 PI (6 cell)
801 13:42:47.455768 CA3 delay=23 (-4~51),Diff = 0 PI (0 cell)
802 13:42:47.462360 CA4 delay=24 (-4~53),Diff = 1 PI (1 cell)
803 13:42:47.465459 CA5 delay=29 (0~59),Diff = 6 PI (7 cell)
804 13:42:47.465591
805 13:42:47.468778 CA PerBit enable=1, Macro0, CA PI delay=23
806 13:42:47.472291 === u2Vref_new: 0x5c --> 0x3c
807 13:42:47.472412
808 13:42:47.472507 Vref(ca) range 1: 28
809 13:42:47.472603
810 13:42:47.475269 CS Dly= 7 (38-0-32)
811 13:42:47.478795 Write Rank0 MR13 =0xd8
812 13:42:47.478886 Write Rank0 MR13 =0xd8
813 13:42:47.482249 Write Rank0 MR12 =0x5c
814 13:42:47.482359 Write Rank1 MR13 =0x59
815 13:42:47.485175 ==
816 13:42:47.488666 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
817 13:42:47.491752 fsp= 1, odt_onoff= 1, Byte mode= 0
818 13:42:47.491863 ==
819 13:42:47.494922 === u2Vref_new: 0x56 --> 0x2d
820 13:42:47.498448 === u2Vref_new: 0x58 --> 0x38
821 13:42:47.501688 === u2Vref_new: 0x5a --> 0x39
822 13:42:47.504977 === u2Vref_new: 0x5c --> 0x3c
823 13:42:47.508275 === u2Vref_new: 0x5e --> 0x3d
824 13:42:47.511152 === u2Vref_new: 0x60 --> 0xa0
825 13:42:47.514448 [CA 0] Center 34 (6~63) winsize 58
826 13:42:47.517915 [CA 1] Center 34 (6~63) winsize 58
827 13:42:47.521043 [CA 2] Center 28 (-1~58) winsize 60
828 13:42:47.524475 [CA 3] Center 23 (-5~51) winsize 57
829 13:42:47.527686 [CA 4] Center 24 (-4~52) winsize 57
830 13:42:47.530853 [CA 5] Center 29 (0~58) winsize 59
831 13:42:47.530944
832 13:42:47.534051 [CATrainingPosCal] consider 2 rank data
833 13:42:47.537668 u2DelayCellTimex100 = 744/100 ps
834 13:42:47.540796 CA0 delay=34 (6~63),Diff = 11 PI (14 cell)
835 13:42:47.544028 CA1 delay=35 (7~63),Diff = 12 PI (15 cell)
836 13:42:47.547347 CA2 delay=28 (-1~58),Diff = 5 PI (6 cell)
837 13:42:47.550447 CA3 delay=23 (-4~51),Diff = 0 PI (0 cell)
838 13:42:47.553996 CA4 delay=24 (-4~52),Diff = 1 PI (1 cell)
839 13:42:47.557366 CA5 delay=29 (0~58),Diff = 6 PI (7 cell)
840 13:42:47.557491
841 13:42:47.563946 CA PerBit enable=1, Macro0, CA PI delay=23
842 13:42:47.564052 === u2Vref_new: 0x60 --> 0xa0
843 13:42:47.564142
844 13:42:47.567006 Vref(ca) range 1: 32
845 13:42:47.567127
846 13:42:47.570265 CS Dly= 5 (36-0-32)
847 13:42:47.570355 Write Rank1 MR13 =0xd8
848 13:42:47.573541 Write Rank1 MR13 =0xd8
849 13:42:47.576631 Write Rank1 MR12 =0x60
850 13:42:47.580253 [RankSwap] Rank num 2, (Multi 1), Rank 0
851 13:42:47.580351 Write Rank0 MR2 =0xad
852 13:42:47.583450 [Write Leveling]
853 13:42:47.586706 delay byte0 byte1 byte2 byte3
854 13:42:47.586797
855 13:42:47.586888 10 0 0
856 13:42:47.589885 11 0 0
857 13:42:47.589976 12 0 0
858 13:42:47.590044 13 0 0
859 13:42:47.593096 14 0 0
860 13:42:47.593194 15 0 0
861 13:42:47.596293 16 0 0
862 13:42:47.596386 17 0 0
863 13:42:47.599796 18 0 0
864 13:42:47.599897 19 0 0
865 13:42:47.599967 20 0 0
866 13:42:47.603037 21 0 0
867 13:42:47.603122 22 0 0
868 13:42:47.606514 23 0 0
869 13:42:47.606614 24 0 0
870 13:42:47.606682 25 0 0
871 13:42:47.609858 26 0 ff
872 13:42:47.609951 27 0 ff
873 13:42:47.612849 28 0 ff
874 13:42:47.612967 29 0 ff
875 13:42:47.616119 30 0 ff
876 13:42:47.616239 31 ff ff
877 13:42:47.619273 32 ff ff
878 13:42:47.619381 33 ff ff
879 13:42:47.622822 34 ff ff
880 13:42:47.622932 35 ff ff
881 13:42:47.626024 36 ff ff
882 13:42:47.626116 37 ff ff
883 13:42:47.629272 pass bytecount = 0xff (0xff: all bytes pass)
884 13:42:47.629362
885 13:42:47.632450 DQS0 dly: 31
886 13:42:47.632537 DQS1 dly: 26
887 13:42:47.635612 Write Rank0 MR2 =0x2d
888 13:42:47.639111 [RankSwap] Rank num 2, (Multi 1), Rank 0
889 13:42:47.639202 Write Rank0 MR1 =0xd6
890 13:42:47.642248 [Gating]
891 13:42:47.642366 ==
892 13:42:47.645433 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
893 13:42:47.648985 fsp= 1, odt_onoff= 1, Byte mode= 0
894 13:42:47.649095 ==
895 13:42:47.655643 3 1 0 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
896 13:42:47.658617 3 1 4 |2c2b 2c2b |(11 11)(11 11) |(0 0)(0 0)| 0
897 13:42:47.662040 3 1 8 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
898 13:42:47.668536 3 1 12 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
899 13:42:47.671612 3 1 16 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
900 13:42:47.675039 3 1 20 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
901 13:42:47.681717 3 1 24 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
902 13:42:47.684985 3 1 28 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
903 13:42:47.688098 3 2 0 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
904 13:42:47.694850 3 2 4 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
905 13:42:47.698084 3 2 8 |2c2c 2c2b |(11 0)(11 11) |(0 0)(1 0)| 0
906 13:42:47.701273 3 2 12 |3534 2c2b |(11 11)(11 11) |(0 0)(0 0)| 0
907 13:42:47.707832 3 2 16 |3534 201 |(11 11)(11 11) |(0 0)(0 0)| 0
908 13:42:47.711038 3 2 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
909 13:42:47.714617 3 2 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
910 13:42:47.720895 3 2 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
911 13:42:47.724179 3 3 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
912 13:42:47.727445 3 3 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
913 13:42:47.733871 3 3 8 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
914 13:42:47.737384 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
915 13:42:47.740489 3 3 16 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
916 13:42:47.743742 [Byte 0] Lead/lag Transition tap number (1)
917 13:42:47.750445 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
918 13:42:47.753627 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
919 13:42:47.756994 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
920 13:42:47.763246 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
921 13:42:47.766770 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
922 13:42:47.769756 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
923 13:42:47.776377 3 4 12 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
924 13:42:47.779882 3 4 16 |403 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
925 13:42:47.783156 3 4 20 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
926 13:42:47.789764 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
927 13:42:47.792752 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
928 13:42:47.796335 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
929 13:42:47.802635 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
930 13:42:47.806005 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
931 13:42:47.809392 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
932 13:42:47.815892 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
933 13:42:47.819281 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
934 13:42:47.822280 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
935 13:42:47.829075 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
936 13:42:47.832249 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
937 13:42:47.835602 [Byte 0] Lead/lag falling Transition (3, 6, 0)
938 13:42:47.842321 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
939 13:42:47.845358 [Byte 1] Lead/lag falling Transition (3, 6, 4)
940 13:42:47.848448 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
941 13:42:47.851852 [Byte 0] Lead/lag Transition tap number (3)
942 13:42:47.858222 [Byte 1] Lead/lag Transition tap number (2)
943 13:42:47.861890 3 6 12 |202 3d3d |(11 11)(11 11) |(0 0)(0 0)| 0
944 13:42:47.865050 3 6 16 |4646 404 |(0 0)(11 11) |(0 0)(0 0)| 0
945 13:42:47.868157 [Byte 0]First pass (3, 6, 16)
946 13:42:47.871397 3 6 20 |4646 1616 |(0 0)(1 1) |(0 0)(0 0)| 0
947 13:42:47.874603 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
948 13:42:47.877963 [Byte 1]First pass (3, 6, 24)
949 13:42:47.881356 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
950 13:42:47.887986 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
951 13:42:47.891230 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
952 13:42:47.894257 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
953 13:42:47.897837 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
954 13:42:47.904029 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
955 13:42:47.907582 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
956 13:42:47.910871 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
957 13:42:47.913961 All bytes gating window > 1UI, Early break!
958 13:42:47.914075
959 13:42:47.917036 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 6)
960 13:42:47.917144
961 13:42:47.920453 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 8)
962 13:42:47.923777
963 13:42:47.923869
964 13:42:47.923937
965 13:42:47.927272 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 6)
966 13:42:47.927352
967 13:42:47.930440 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 8)
968 13:42:47.930521
969 13:42:47.930585
970 13:42:47.933604 Write Rank0 MR1 =0x56
971 13:42:47.933691
972 13:42:47.937068 best RODT dly(2T, 0.5T) = (2, 3)
973 13:42:47.937149
974 13:42:47.940431 best RODT dly(2T, 0.5T) = (2, 3)
975 13:42:47.940513 ==
976 13:42:47.943407 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
977 13:42:47.946604 fsp= 1, odt_onoff= 1, Byte mode= 0
978 13:42:47.946692 ==
979 13:42:47.953307 Start DQ dly to find pass range UseTestEngine =0
980 13:42:47.956875 x-axis: bit #, y-axis: DQ dly (-127~63)
981 13:42:47.956959 RX Vref Scan = 0
982 13:42:47.960029 -26, [0] xxxxxxxx xxxxxxxx [MSB]
983 13:42:47.963154 -25, [0] xxxxxxxx xxxxxxxx [MSB]
984 13:42:47.966290 -24, [0] xxxxxxxx xxxxxxxx [MSB]
985 13:42:47.969861 -23, [0] xxxxxxxx xxxxxxxx [MSB]
986 13:42:47.973071 -22, [0] xxxxxxxx xxxxxxxx [MSB]
987 13:42:47.973164 -21, [0] xxxxxxxx xxxxxxxx [MSB]
988 13:42:47.976254 -20, [0] xxxxxxxx xxxxxxxx [MSB]
989 13:42:47.979368 -19, [0] xxxxxxxx xxxxxxxx [MSB]
990 13:42:47.982819 -18, [0] xxxxxxxx xxxxxxxx [MSB]
991 13:42:47.985893 -17, [0] xxxxxxxx xxxxxxxx [MSB]
992 13:42:47.989223 -16, [0] xxxxxxxx xxxxxxxx [MSB]
993 13:42:47.992661 -15, [0] xxxxxxxx xxxxxxxx [MSB]
994 13:42:47.995733 -14, [0] xxxxxxxx xxxxxxxx [MSB]
995 13:42:47.999262 -13, [0] xxxxxxxx xxxxxxxx [MSB]
996 13:42:48.002635 -12, [0] xxxxxxxx xxxxxxxx [MSB]
997 13:42:48.002727 -11, [0] xxxxxxxx xxxxxxxx [MSB]
998 13:42:48.005589 -10, [0] xxxxxxxx xxxxxxxx [MSB]
999 13:42:48.009105 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1000 13:42:48.012270 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1001 13:42:48.015448 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1002 13:42:48.018705 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1003 13:42:48.022214 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1004 13:42:48.025246 -4, [0] xxxxxxxx oxxxxxxx [MSB]
1005 13:42:48.025341 -3, [0] xxxoxxxx oxxxxxxx [MSB]
1006 13:42:48.028568 -2, [0] xxxoxxxx oxxoxxxx [MSB]
1007 13:42:48.032099 -1, [0] xxxoxxxx oxxoxxxx [MSB]
1008 13:42:48.035317 0, [0] xxxoxxxx oxxoooxx [MSB]
1009 13:42:48.038494 1, [0] xxxoxoox ooxoooox [MSB]
1010 13:42:48.041615 2, [0] xxxoxoox ooxoooox [MSB]
1011 13:42:48.044824 3, [0] xxxoxoox ooxoooox [MSB]
1012 13:42:48.044906 4, [0] xxxoxoox ooxooooo [MSB]
1013 13:42:48.048154 5, [0] xxxooooo ooxooooo [MSB]
1014 13:42:48.051405 6, [0] oxoooooo ooxooooo [MSB]
1015 13:42:48.054626 32, [0] oooxoooo oooooooo [MSB]
1016 13:42:48.058112 33, [0] oooxoooo xooooooo [MSB]
1017 13:42:48.061359 34, [0] oooxoooo xooxoooo [MSB]
1018 13:42:48.064818 35, [0] oooxoooo xxoxoooo [MSB]
1019 13:42:48.064915 36, [0] oooxoxoo xxoxxoxo [MSB]
1020 13:42:48.068072 37, [0] oooxoxxo xxoxxxxo [MSB]
1021 13:42:48.071215 38, [0] oooxoxxx xxoxxxxo [MSB]
1022 13:42:48.074317 39, [0] oooxoxxx xxoxxxxx [MSB]
1023 13:42:48.077523 40, [0] ooxxxxxx xxoxxxxx [MSB]
1024 13:42:48.080859 41, [0] xxxxxxxx xxoxxxxx [MSB]
1025 13:42:48.084371 42, [0] xxxxxxxx xxxxxxxx [MSB]
1026 13:42:48.087382 iDelay=42, Bit 0, Center 23 (6 ~ 40) 35
1027 13:42:48.090907 iDelay=42, Bit 1, Center 23 (7 ~ 40) 34
1028 13:42:48.093986 iDelay=42, Bit 2, Center 22 (6 ~ 39) 34
1029 13:42:48.097180 iDelay=42, Bit 3, Center 14 (-3 ~ 31) 35
1030 13:42:48.100546 iDelay=42, Bit 4, Center 22 (5 ~ 39) 35
1031 13:42:48.104134 iDelay=42, Bit 5, Center 18 (1 ~ 35) 35
1032 13:42:48.107139 iDelay=42, Bit 6, Center 18 (1 ~ 36) 36
1033 13:42:48.110692 iDelay=42, Bit 7, Center 21 (5 ~ 37) 33
1034 13:42:48.113686 iDelay=42, Bit 8, Center 14 (-4 ~ 32) 37
1035 13:42:48.116916 iDelay=42, Bit 9, Center 17 (1 ~ 34) 34
1036 13:42:48.123729 iDelay=42, Bit 10, Center 24 (7 ~ 41) 35
1037 13:42:48.126686 iDelay=42, Bit 11, Center 15 (-2 ~ 33) 36
1038 13:42:48.130206 iDelay=42, Bit 12, Center 17 (0 ~ 35) 36
1039 13:42:48.133559 iDelay=42, Bit 13, Center 18 (0 ~ 36) 37
1040 13:42:48.136639 iDelay=42, Bit 14, Center 18 (1 ~ 35) 35
1041 13:42:48.139785 iDelay=42, Bit 15, Center 21 (4 ~ 38) 35
1042 13:42:48.139873 ==
1043 13:42:48.146568 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1044 13:42:48.149775 fsp= 1, odt_onoff= 1, Byte mode= 0
1045 13:42:48.149865 ==
1046 13:42:48.149931 DQS Delay:
1047 13:42:48.152933 DQS0 = 0, DQS1 = 0
1048 13:42:48.153020 DQM Delay:
1049 13:42:48.156180 DQM0 = 20, DQM1 = 18
1050 13:42:48.156266 DQ Delay:
1051 13:42:48.159610 DQ0 =23, DQ1 =23, DQ2 =22, DQ3 =14
1052 13:42:48.162963 DQ4 =22, DQ5 =18, DQ6 =18, DQ7 =21
1053 13:42:48.166256 DQ8 =14, DQ9 =17, DQ10 =24, DQ11 =15
1054 13:42:48.169486 DQ12 =17, DQ13 =18, DQ14 =18, DQ15 =21
1055 13:42:48.169576
1056 13:42:48.169642
1057 13:42:48.169703 DramC Write-DBI off
1058 13:42:48.172656 ==
1059 13:42:48.175953 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1060 13:42:48.179239 fsp= 1, odt_onoff= 1, Byte mode= 0
1061 13:42:48.179329 ==
1062 13:42:48.182491 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1063 13:42:48.182580
1064 13:42:48.185841 Begin, DQ Scan Range 922~1178
1065 13:42:48.185930
1066 13:42:48.185997
1067 13:42:48.189041 TX Vref Scan disable
1068 13:42:48.192461 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1069 13:42:48.195633 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1070 13:42:48.198788 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1071 13:42:48.202134 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1072 13:42:48.205341 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1073 13:42:48.208722 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1074 13:42:48.215118 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1075 13:42:48.218501 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1076 13:42:48.221842 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1077 13:42:48.225075 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1078 13:42:48.228312 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1079 13:42:48.231669 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1080 13:42:48.234886 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1081 13:42:48.237961 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1082 13:42:48.241276 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1083 13:42:48.244676 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1084 13:42:48.248009 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1085 13:42:48.251099 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1086 13:42:48.254248 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1087 13:42:48.260958 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1088 13:42:48.264298 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1089 13:42:48.267827 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1090 13:42:48.270893 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1091 13:42:48.274046 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1092 13:42:48.277360 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1093 13:42:48.280824 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1094 13:42:48.283873 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1095 13:42:48.287167 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1096 13:42:48.290422 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1097 13:42:48.293868 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1098 13:42:48.297225 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1099 13:42:48.300311 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1100 13:42:48.306774 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1101 13:42:48.309931 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1102 13:42:48.313402 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1103 13:42:48.316724 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1104 13:42:48.320194 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1105 13:42:48.323296 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1106 13:42:48.326331 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1107 13:42:48.329742 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1108 13:42:48.332971 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1109 13:42:48.336461 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1110 13:42:48.339577 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1111 13:42:48.342729 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1112 13:42:48.346071 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1113 13:42:48.349339 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1114 13:42:48.352508 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
1115 13:42:48.356103 969 |3 6 9|[0] xxxxxxxx oxxoxxxx [MSB]
1116 13:42:48.362438 970 |3 6 10|[0] xxxxxxxx ooxoxxxx [MSB]
1117 13:42:48.365761 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1118 13:42:48.369224 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1119 13:42:48.372327 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1120 13:42:48.375447 974 |3 6 14|[0] xxxxxxxx ooxoooox [MSB]
1121 13:42:48.379035 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
1122 13:42:48.382223 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1123 13:42:48.385428 977 |3 6 17|[0] xxxoxooo oooooooo [MSB]
1124 13:42:48.388554 978 |3 6 18|[0] xoxooooo oooooooo [MSB]
1125 13:42:48.396259 990 |3 6 30|[0] oooooooo oooxoxoo [MSB]
1126 13:42:48.399250 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1127 13:42:48.402471 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1128 13:42:48.405913 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1129 13:42:48.409169 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB]
1130 13:42:48.412353 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
1131 13:42:48.415776 996 |3 6 36|[0] oooxoxoo xxxxxxxx [MSB]
1132 13:42:48.419163 997 |3 6 37|[0] oooxoxoo xxxxxxxx [MSB]
1133 13:42:48.422360 998 |3 6 38|[0] xxoxxxxx xxxxxxxx [MSB]
1134 13:42:48.425338 999 |3 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
1135 13:42:48.428625 Byte0, DQ PI dly=986, DQM PI dly= 986
1136 13:42:48.435150 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
1137 13:42:48.435262
1138 13:42:48.438608 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
1139 13:42:48.438702
1140 13:42:48.441828 Byte1, DQ PI dly=980, DQM PI dly= 980
1141 13:42:48.445060 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
1142 13:42:48.445156
1143 13:42:48.451726 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
1144 13:42:48.451836
1145 13:42:48.451904 ==
1146 13:42:48.455020 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1147 13:42:48.458176 fsp= 1, odt_onoff= 1, Byte mode= 0
1148 13:42:48.458272 ==
1149 13:42:48.464975 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1150 13:42:48.465089
1151 13:42:48.468028 Begin, DQ Scan Range 956~1020
1152 13:42:48.468121 Write Rank0 MR14 =0x0
1153 13:42:48.476714
1154 13:42:48.476833 CH=0, VrefRange= 0, VrefLevel = 0
1155 13:42:48.483056 TX Bit0 (983~993) 11 988, Bit8 (970~984) 15 977,
1156 13:42:48.486668 TX Bit1 (980~993) 14 986, Bit9 (972~986) 15 979,
1157 13:42:48.492953 TX Bit2 (981~994) 14 987, Bit10 (977~991) 15 984,
1158 13:42:48.496398 TX Bit3 (976~990) 15 983, Bit11 (971~983) 13 977,
1159 13:42:48.499419 TX Bit4 (979~992) 14 985, Bit12 (975~984) 10 979,
1160 13:42:48.506161 TX Bit5 (978~991) 14 984, Bit13 (975~984) 10 979,
1161 13:42:48.509259 TX Bit6 (979~991) 13 985, Bit14 (975~989) 15 982,
1162 13:42:48.515837 TX Bit7 (980~993) 14 986, Bit15 (976~991) 16 983,
1163 13:42:48.515957
1164 13:42:48.516025 Write Rank0 MR14 =0x2
1165 13:42:48.524840
1166 13:42:48.528021 CH=0, VrefRange= 0, VrefLevel = 2
1167 13:42:48.531210 TX Bit0 (982~994) 13 988, Bit8 (970~985) 16 977,
1168 13:42:48.534345 TX Bit1 (980~994) 15 987, Bit9 (971~987) 17 979,
1169 13:42:48.541130 TX Bit2 (981~995) 15 988, Bit10 (977~991) 15 984,
1170 13:42:48.544051 TX Bit3 (976~991) 16 983, Bit11 (970~984) 15 977,
1171 13:42:48.547372 TX Bit4 (979~993) 15 986, Bit12 (974~985) 12 979,
1172 13:42:48.554121 TX Bit5 (977~992) 16 984, Bit13 (974~985) 12 979,
1173 13:42:48.557511 TX Bit6 (978~992) 15 985, Bit14 (974~989) 16 981,
1174 13:42:48.563744 TX Bit7 (979~993) 15 986, Bit15 (976~991) 16 983,
1175 13:42:48.563866
1176 13:42:48.563932 Write Rank0 MR14 =0x4
1177 13:42:48.572878
1178 13:42:48.573023 CH=0, VrefRange= 0, VrefLevel = 4
1179 13:42:48.579356 TX Bit0 (982~995) 14 988, Bit8 (969~986) 18 977,
1180 13:42:48.582563 TX Bit1 (979~995) 17 987, Bit9 (971~988) 18 979,
1181 13:42:48.589296 TX Bit2 (980~995) 16 987, Bit10 (977~992) 16 984,
1182 13:42:48.592476 TX Bit3 (976~991) 16 983, Bit11 (970~985) 16 977,
1183 13:42:48.595715 TX Bit4 (979~994) 16 986, Bit12 (973~986) 14 979,
1184 13:42:48.602090 TX Bit5 (977~992) 16 984, Bit13 (974~986) 13 980,
1185 13:42:48.605748 TX Bit6 (978~992) 15 985, Bit14 (974~990) 17 982,
1186 13:42:48.612029 TX Bit7 (979~994) 16 986, Bit15 (976~992) 17 984,
1187 13:42:48.612146
1188 13:42:48.612212 Write Rank0 MR14 =0x6
1189 13:42:48.621331
1190 13:42:48.621458 CH=0, VrefRange= 0, VrefLevel = 6
1191 13:42:48.627620 TX Bit0 (982~996) 15 989, Bit8 (969~987) 19 978,
1192 13:42:48.630861 TX Bit1 (979~996) 18 987, Bit9 (970~988) 19 979,
1193 13:42:48.637783 TX Bit2 (981~997) 17 989, Bit10 (976~993) 18 984,
1194 13:42:48.640775 TX Bit3 (975~991) 17 983, Bit11 (970~985) 16 977,
1195 13:42:48.644056 TX Bit4 (979~994) 16 986, Bit12 (973~987) 15 980,
1196 13:42:48.650693 TX Bit5 (977~993) 17 985, Bit13 (973~987) 15 980,
1197 13:42:48.653978 TX Bit6 (977~993) 17 985, Bit14 (974~990) 17 982,
1198 13:42:48.707934 TX Bit7 (979~995) 17 987, Bit15 (976~993) 18 984,
1199 13:42:48.708069
1200 13:42:48.708138 Write Rank0 MR14 =0x8
1201 13:42:48.708212
1202 13:42:48.708487 CH=0, VrefRange= 0, VrefLevel = 8
1203 13:42:48.708559 TX Bit0 (980~997) 18 988, Bit8 (969~988) 20 978,
1204 13:42:48.708620 TX Bit1 (978~997) 20 987, Bit9 (971~989) 19 980,
1205 13:42:48.708678 TX Bit2 (980~998) 19 989, Bit10 (976~993) 18 984,
1206 13:42:48.708747 TX Bit3 (975~992) 18 983, Bit11 (969~987) 19 978,
1207 13:42:48.709253 TX Bit4 (978~995) 18 986, Bit12 (973~988) 16 980,
1208 13:42:48.709361 TX Bit5 (977~993) 17 985, Bit13 (973~988) 16 980,
1209 13:42:48.709635 TX Bit6 (977~994) 18 985, Bit14 (973~991) 19 982,
1210 13:42:48.709915 TX Bit7 (979~996) 18 987, Bit15 (975~993) 19 984,
1211 13:42:48.710008
1212 13:42:48.713335 Write Rank0 MR14 =0xa
1213 13:42:48.718040
1214 13:42:48.721490 CH=0, VrefRange= 0, VrefLevel = 10
1215 13:42:48.724628 TX Bit0 (980~997) 18 988, Bit8 (969~989) 21 979,
1216 13:42:48.728149 TX Bit1 (978~997) 20 987, Bit9 (970~989) 20 979,
1217 13:42:48.734775 TX Bit2 (979~998) 20 988, Bit10 (976~994) 19 985,
1218 13:42:48.737941 TX Bit3 (975~992) 18 983, Bit11 (969~988) 20 978,
1219 13:42:48.741111 TX Bit4 (978~996) 19 987, Bit12 (972~989) 18 980,
1220 13:42:48.747581 TX Bit5 (977~993) 17 985, Bit13 (972~988) 17 980,
1221 13:42:48.750916 TX Bit6 (977~994) 18 985, Bit14 (973~991) 19 982,
1222 13:42:48.757302 TX Bit7 (979~997) 19 988, Bit15 (976~995) 20 985,
1223 13:42:48.757422
1224 13:42:48.757488 Write Rank0 MR14 =0xc
1225 13:42:48.766780
1226 13:42:48.770060 CH=0, VrefRange= 0, VrefLevel = 12
1227 13:42:48.773250 TX Bit0 (979~998) 20 988, Bit8 (969~989) 21 979,
1228 13:42:48.776735 TX Bit1 (978~998) 21 988, Bit9 (970~990) 21 980,
1229 13:42:48.783199 TX Bit2 (979~998) 20 988, Bit10 (976~996) 21 986,
1230 13:42:48.786600 TX Bit3 (975~992) 18 983, Bit11 (969~989) 21 979,
1231 13:42:48.789849 TX Bit4 (978~997) 20 987, Bit12 (971~989) 19 980,
1232 13:42:48.796306 TX Bit5 (976~994) 19 985, Bit13 (972~989) 18 980,
1233 13:42:48.799367 TX Bit6 (977~995) 19 986, Bit14 (972~991) 20 981,
1234 13:42:48.806123 TX Bit7 (978~998) 21 988, Bit15 (975~996) 22 985,
1235 13:42:48.806241
1236 13:42:48.806308 Write Rank0 MR14 =0xe
1237 13:42:48.815741
1238 13:42:48.818782 CH=0, VrefRange= 0, VrefLevel = 14
1239 13:42:48.822101 TX Bit0 (979~998) 20 988, Bit8 (968~989) 22 978,
1240 13:42:48.825398 TX Bit1 (978~998) 21 988, Bit9 (970~990) 21 980,
1241 13:42:48.831952 TX Bit2 (979~999) 21 989, Bit10 (975~996) 22 985,
1242 13:42:48.835414 TX Bit3 (975~993) 19 984, Bit11 (969~988) 20 978,
1243 13:42:48.838629 TX Bit4 (978~998) 21 988, Bit12 (971~989) 19 980,
1244 13:42:48.845165 TX Bit5 (976~994) 19 985, Bit13 (971~990) 20 980,
1245 13:42:48.848266 TX Bit6 (977~996) 20 986, Bit14 (972~992) 21 982,
1246 13:42:48.854935 TX Bit7 (978~998) 21 988, Bit15 (975~996) 22 985,
1247 13:42:48.855057
1248 13:42:48.855126 Write Rank0 MR14 =0x10
1249 13:42:48.864702
1250 13:42:48.868052 CH=0, VrefRange= 0, VrefLevel = 16
1251 13:42:48.871080 TX Bit0 (979~999) 21 989, Bit8 (968~990) 23 979,
1252 13:42:48.874368 TX Bit1 (978~999) 22 988, Bit9 (969~990) 22 979,
1253 13:42:48.880911 TX Bit2 (979~999) 21 989, Bit10 (975~997) 23 986,
1254 13:42:48.884163 TX Bit3 (974~993) 20 983, Bit11 (969~989) 21 979,
1255 13:42:48.887273 TX Bit4 (977~998) 22 987, Bit12 (970~990) 21 980,
1256 13:42:48.894051 TX Bit5 (976~995) 20 985, Bit13 (971~989) 19 980,
1257 13:42:48.897200 TX Bit6 (977~997) 21 987, Bit14 (971~992) 22 981,
1258 13:42:48.903973 TX Bit7 (978~999) 22 988, Bit15 (975~996) 22 985,
1259 13:42:48.904099
1260 13:42:48.904168 Write Rank0 MR14 =0x12
1261 13:42:48.913623
1262 13:42:48.916760 CH=0, VrefRange= 0, VrefLevel = 18
1263 13:42:48.919927 TX Bit0 (979~999) 21 989, Bit8 (968~990) 23 979,
1264 13:42:48.923409 TX Bit1 (978~999) 22 988, Bit9 (969~991) 23 980,
1265 13:42:48.929906 TX Bit2 (978~1000) 23 989, Bit10 (975~997) 23 986,
1266 13:42:48.933193 TX Bit3 (974~993) 20 983, Bit11 (969~989) 21 979,
1267 13:42:48.936490 TX Bit4 (977~998) 22 987, Bit12 (970~990) 21 980,
1268 13:42:48.943145 TX Bit5 (976~996) 21 986, Bit13 (971~990) 20 980,
1269 13:42:48.946344 TX Bit6 (976~997) 22 986, Bit14 (971~993) 23 982,
1270 13:42:48.952716 TX Bit7 (978~999) 22 988, Bit15 (974~997) 24 985,
1271 13:42:48.952847
1272 13:42:48.952917 Write Rank0 MR14 =0x14
1273 13:42:48.962651
1274 13:42:48.965919 CH=0, VrefRange= 0, VrefLevel = 20
1275 13:42:48.969078 TX Bit0 (979~1000) 22 989, Bit8 (968~990) 23 979,
1276 13:42:48.972491 TX Bit1 (977~999) 23 988, Bit9 (969~991) 23 980,
1277 13:42:48.978902 TX Bit2 (978~1000) 23 989, Bit10 (974~997) 24 985,
1278 13:42:48.982504 TX Bit3 (974~994) 21 984, Bit11 (969~990) 22 979,
1279 13:42:48.985606 TX Bit4 (977~999) 23 988, Bit12 (970~991) 22 980,
1280 13:42:48.992300 TX Bit5 (976~997) 22 986, Bit13 (970~990) 21 980,
1281 13:42:48.995578 TX Bit6 (976~998) 23 987, Bit14 (970~993) 24 981,
1282 13:42:49.001721 TX Bit7 (978~1000) 23 989, Bit15 (974~997) 24 985,
1283 13:42:49.001838
1284 13:42:49.001905 Write Rank0 MR14 =0x16
1285 13:42:49.012163
1286 13:42:49.015270 CH=0, VrefRange= 0, VrefLevel = 22
1287 13:42:49.018438 TX Bit0 (978~1000) 23 989, Bit8 (967~990) 24 978,
1288 13:42:49.022079 TX Bit1 (977~1000) 24 988, Bit9 (969~992) 24 980,
1289 13:42:49.028458 TX Bit2 (978~1000) 23 989, Bit10 (974~998) 25 986,
1290 13:42:49.031551 TX Bit3 (973~994) 22 983, Bit11 (968~990) 23 979,
1291 13:42:49.038322 TX Bit4 (977~999) 23 988, Bit12 (970~991) 22 980,
1292 13:42:49.041247 TX Bit5 (975~997) 23 986, Bit13 (970~991) 22 980,
1293 13:42:49.044538 TX Bit6 (976~999) 24 987, Bit14 (970~994) 25 982,
1294 13:42:49.051098 TX Bit7 (977~1000) 24 988, Bit15 (974~997) 24 985,
1295 13:42:49.051220
1296 13:42:49.051287 Write Rank0 MR14 =0x18
1297 13:42:49.061229
1298 13:42:49.064772 CH=0, VrefRange= 0, VrefLevel = 24
1299 13:42:49.067980 TX Bit0 (978~1000) 23 989, Bit8 (967~991) 25 979,
1300 13:42:49.071129 TX Bit1 (977~1000) 24 988, Bit9 (969~992) 24 980,
1301 13:42:49.077807 TX Bit2 (978~1000) 23 989, Bit10 (974~998) 25 986,
1302 13:42:49.081176 TX Bit3 (973~995) 23 984, Bit11 (968~991) 24 979,
1303 13:42:49.087441 TX Bit4 (977~999) 23 988, Bit12 (969~991) 23 980,
1304 13:42:49.090928 TX Bit5 (975~998) 24 986, Bit13 (970~991) 22 980,
1305 13:42:49.093991 TX Bit6 (976~999) 24 987, Bit14 (970~994) 25 982,
1306 13:42:49.100682 TX Bit7 (977~1000) 24 988, Bit15 (974~998) 25 986,
1307 13:42:49.100804
1308 13:42:49.100873 Write Rank0 MR14 =0x1a
1309 13:42:49.110928
1310 13:42:49.114147 CH=0, VrefRange= 0, VrefLevel = 26
1311 13:42:49.117387 TX Bit0 (978~1001) 24 989, Bit8 (967~991) 25 979,
1312 13:42:49.120927 TX Bit1 (977~1000) 24 988, Bit9 (969~992) 24 980,
1313 13:42:49.127294 TX Bit2 (978~1001) 24 989, Bit10 (974~998) 25 986,
1314 13:42:49.130422 TX Bit3 (973~995) 23 984, Bit11 (968~991) 24 979,
1315 13:42:49.137127 TX Bit4 (977~1000) 24 988, Bit12 (969~992) 24 980,
1316 13:42:49.140313 TX Bit5 (975~998) 24 986, Bit13 (969~992) 24 980,
1317 13:42:49.143925 TX Bit6 (976~999) 24 987, Bit14 (970~996) 27 983,
1318 13:42:49.149970 TX Bit7 (977~1001) 25 989, Bit15 (973~997) 25 985,
1319 13:42:49.150083
1320 13:42:49.150150 Write Rank0 MR14 =0x1c
1321 13:42:49.160434
1322 13:42:49.164070 CH=0, VrefRange= 0, VrefLevel = 28
1323 13:42:49.167273 TX Bit0 (978~1001) 24 989, Bit8 (967~990) 24 978,
1324 13:42:49.170448 TX Bit1 (977~1001) 25 989, Bit9 (969~993) 25 981,
1325 13:42:49.176704 TX Bit2 (977~1001) 25 989, Bit10 (973~998) 26 985,
1326 13:42:49.180311 TX Bit3 (972~995) 24 983, Bit11 (968~991) 24 979,
1327 13:42:49.186549 TX Bit4 (977~1000) 24 988, Bit12 (969~993) 25 981,
1328 13:42:49.189953 TX Bit5 (975~998) 24 986, Bit13 (969~992) 24 980,
1329 13:42:49.193236 TX Bit6 (976~999) 24 987, Bit14 (969~996) 28 982,
1330 13:42:49.199563 TX Bit7 (977~1001) 25 989, Bit15 (972~998) 27 985,
1331 13:42:49.199708
1332 13:42:49.199809 Write Rank0 MR14 =0x1e
1333 13:42:49.210267
1334 13:42:49.213666 CH=0, VrefRange= 0, VrefLevel = 30
1335 13:42:49.216809 TX Bit0 (978~1002) 25 990, Bit8 (967~990) 24 978,
1336 13:42:49.219965 TX Bit1 (977~1001) 25 989, Bit9 (968~992) 25 980,
1337 13:42:49.226546 TX Bit2 (978~1002) 25 990, Bit10 (973~997) 25 985,
1338 13:42:49.229867 TX Bit3 (972~995) 24 983, Bit11 (967~991) 25 979,
1339 13:42:49.236593 TX Bit4 (977~1000) 24 988, Bit12 (969~993) 25 981,
1340 13:42:49.239767 TX Bit5 (975~998) 24 986, Bit13 (969~993) 25 981,
1341 13:42:49.243010 TX Bit6 (976~999) 24 987, Bit14 (969~996) 28 982,
1342 13:42:49.249696 TX Bit7 (977~1001) 25 989, Bit15 (972~998) 27 985,
1343 13:42:49.249810
1344 13:42:49.249879 Write Rank0 MR14 =0x20
1345 13:42:49.260290
1346 13:42:49.263277 CH=0, VrefRange= 0, VrefLevel = 32
1347 13:42:49.266515 TX Bit0 (978~1002) 25 990, Bit8 (967~990) 24 978,
1348 13:42:49.269843 TX Bit1 (977~1001) 25 989, Bit9 (968~992) 25 980,
1349 13:42:49.276684 TX Bit2 (978~1002) 25 990, Bit10 (973~997) 25 985,
1350 13:42:49.279758 TX Bit3 (972~995) 24 983, Bit11 (967~991) 25 979,
1351 13:42:49.286439 TX Bit4 (977~1000) 24 988, Bit12 (969~993) 25 981,
1352 13:42:49.289639 TX Bit5 (975~998) 24 986, Bit13 (969~993) 25 981,
1353 13:42:49.292724 TX Bit6 (976~999) 24 987, Bit14 (969~996) 28 982,
1354 13:42:49.299212 TX Bit7 (977~1001) 25 989, Bit15 (972~998) 27 985,
1355 13:42:49.299333
1356 13:42:49.299400 Write Rank0 MR14 =0x22
1357 13:42:49.310106
1358 13:42:49.313196 CH=0, VrefRange= 0, VrefLevel = 34
1359 13:42:49.316369 TX Bit0 (978~1002) 25 990, Bit8 (967~990) 24 978,
1360 13:42:49.319659 TX Bit1 (977~1001) 25 989, Bit9 (968~992) 25 980,
1361 13:42:49.326295 TX Bit2 (978~1002) 25 990, Bit10 (973~997) 25 985,
1362 13:42:49.329612 TX Bit3 (972~995) 24 983, Bit11 (967~991) 25 979,
1363 13:42:49.336244 TX Bit4 (977~1000) 24 988, Bit12 (969~993) 25 981,
1364 13:42:49.339482 TX Bit5 (975~998) 24 986, Bit13 (969~993) 25 981,
1365 13:42:49.342645 TX Bit6 (976~999) 24 987, Bit14 (969~996) 28 982,
1366 13:42:49.349232 TX Bit7 (977~1001) 25 989, Bit15 (972~998) 27 985,
1367 13:42:49.349344
1368 13:42:49.349411 Write Rank0 MR14 =0x24
1369 13:42:49.359692
1370 13:42:49.362785 CH=0, VrefRange= 0, VrefLevel = 36
1371 13:42:49.366329 TX Bit0 (978~1002) 25 990, Bit8 (967~990) 24 978,
1372 13:42:49.369601 TX Bit1 (977~1001) 25 989, Bit9 (968~992) 25 980,
1373 13:42:49.375962 TX Bit2 (978~1002) 25 990, Bit10 (973~997) 25 985,
1374 13:42:49.379406 TX Bit3 (972~995) 24 983, Bit11 (967~991) 25 979,
1375 13:42:49.385776 TX Bit4 (977~1000) 24 988, Bit12 (969~993) 25 981,
1376 13:42:49.389307 TX Bit5 (975~998) 24 986, Bit13 (969~993) 25 981,
1377 13:42:49.392435 TX Bit6 (976~999) 24 987, Bit14 (969~996) 28 982,
1378 13:42:49.398967 TX Bit7 (977~1001) 25 989, Bit15 (972~998) 27 985,
1379 13:42:49.399105
1380 13:42:49.399200
1381 13:42:49.402148 TX Vref found, early break! 379< 380
1382 13:42:49.405599 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
1383 13:42:49.408725 u1DelayCellOfst[0]=9 cells (7 PI)
1384 13:42:49.412028 u1DelayCellOfst[1]=7 cells (6 PI)
1385 13:42:49.415247 u1DelayCellOfst[2]=9 cells (7 PI)
1386 13:42:49.418411 u1DelayCellOfst[3]=0 cells (0 PI)
1387 13:42:49.421851 u1DelayCellOfst[4]=6 cells (5 PI)
1388 13:42:49.425028 u1DelayCellOfst[5]=3 cells (3 PI)
1389 13:42:49.428417 u1DelayCellOfst[6]=5 cells (4 PI)
1390 13:42:49.431579 u1DelayCellOfst[7]=7 cells (6 PI)
1391 13:42:49.435013 Byte0, DQ PI dly=983, DQM PI dly= 986
1392 13:42:49.438350 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
1393 13:42:49.438447
1394 13:42:49.441442 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
1395 13:42:49.441557
1396 13:42:49.444748 u1DelayCellOfst[8]=0 cells (0 PI)
1397 13:42:49.448176 u1DelayCellOfst[9]=2 cells (2 PI)
1398 13:42:49.451342 u1DelayCellOfst[10]=9 cells (7 PI)
1399 13:42:49.454829 u1DelayCellOfst[11]=1 cells (1 PI)
1400 13:42:49.457764 u1DelayCellOfst[12]=3 cells (3 PI)
1401 13:42:49.461256 u1DelayCellOfst[13]=3 cells (3 PI)
1402 13:42:49.464466 u1DelayCellOfst[14]=5 cells (4 PI)
1403 13:42:49.467803 u1DelayCellOfst[15]=9 cells (7 PI)
1404 13:42:49.470950 Byte1, DQ PI dly=978, DQM PI dly= 981
1405 13:42:49.474096 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
1406 13:42:49.474214
1407 13:42:49.480724 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
1408 13:42:49.480858
1409 13:42:49.480956 Write Rank0 MR14 =0x1e
1410 13:42:49.481050
1411 13:42:49.483958 Final TX Range 0 Vref 30
1412 13:42:49.484063
1413 13:42:49.490607 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1414 13:42:49.490739
1415 13:42:49.496985 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1416 13:42:49.503676 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1417 13:42:49.510189 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1418 13:42:49.513358 Write Rank0 MR3 =0xb0
1419 13:42:49.516912 DramC Write-DBI on
1420 13:42:49.517009 ==
1421 13:42:49.520112 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1422 13:42:49.523420 fsp= 1, odt_onoff= 1, Byte mode= 0
1423 13:42:49.523508 ==
1424 13:42:49.529704 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1425 13:42:49.529832
1426 13:42:49.529901 Begin, DQ Scan Range 701~765
1427 13:42:49.529963
1428 13:42:49.530021
1429 13:42:49.533169 TX Vref Scan disable
1430 13:42:49.536389 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1431 13:42:49.539669 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1432 13:42:49.542825 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1433 13:42:49.546314 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1434 13:42:49.549415 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1435 13:42:49.552587 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1436 13:42:49.559211 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1437 13:42:49.562399 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1438 13:42:49.565641 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1439 13:42:49.569018 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1440 13:42:49.572319 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1441 13:42:49.575732 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1442 13:42:49.578886 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1443 13:42:49.582391 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1444 13:42:49.585644 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
1445 13:42:49.588863 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
1446 13:42:49.592063 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
1447 13:42:49.595135 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
1448 13:42:49.598664 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
1449 13:42:49.607574 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1450 13:42:49.610969 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1451 13:42:49.613937 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1452 13:42:49.617635 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1453 13:42:49.620743 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
1454 13:42:49.623981 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
1455 13:42:49.627109 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
1456 13:42:49.630389 746 |2 6 42|[0] xxxxxxxx xxxxxxxx [MSB]
1457 13:42:49.633917 Byte0, DQ PI dly=732, DQM PI dly= 732
1458 13:42:49.637224 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 28)
1459 13:42:49.640453
1460 13:42:49.643660 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 28)
1461 13:42:49.643758
1462 13:42:49.646885 Byte1, DQ PI dly=725, DQM PI dly= 725
1463 13:42:49.650355 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 21)
1464 13:42:49.650451
1465 13:42:49.656826 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 21)
1466 13:42:49.656954
1467 13:42:49.663422 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1468 13:42:49.669779 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1469 13:42:49.676382 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1470 13:42:49.679652 Write Rank0 MR3 =0x30
1471 13:42:49.679804 DramC Write-DBI off
1472 13:42:49.679875
1473 13:42:49.679947 [DATLAT]
1474 13:42:49.682943 Freq=1600, CH0 RK0, use_rxtx_scan=0
1475 13:42:49.683098
1476 13:42:49.686157 DATLAT Default: 0xf
1477 13:42:49.686245 7, 0xFFFF, sum=0
1478 13:42:49.689497 8, 0xFFFF, sum=0
1479 13:42:49.689591 9, 0xFFFF, sum=0
1480 13:42:49.692755 10, 0xFFFF, sum=0
1481 13:42:49.692880 11, 0xFFFF, sum=0
1482 13:42:49.695952 12, 0xFFFF, sum=0
1483 13:42:49.696121 13, 0xFFFF, sum=0
1484 13:42:49.699371 14, 0x0, sum=1
1485 13:42:49.699536 15, 0x0, sum=2
1486 13:42:49.702485 16, 0x0, sum=3
1487 13:42:49.702579 17, 0x0, sum=4
1488 13:42:49.706005 pattern=2 first_step=14 total pass=5 best_step=16
1489 13:42:49.709104 ==
1490 13:42:49.712495 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1491 13:42:49.715643 fsp= 1, odt_onoff= 1, Byte mode= 0
1492 13:42:49.715763 ==
1493 13:42:49.719079 Start DQ dly to find pass range UseTestEngine =1
1494 13:42:49.722399 x-axis: bit #, y-axis: DQ dly (-127~63)
1495 13:42:49.725249 RX Vref Scan = 1
1496 13:42:49.832485
1497 13:42:49.832618 RX Vref found, early break!
1498 13:42:49.832685
1499 13:42:49.839102 Final RX Vref 11, apply to both rank0 and 1
1500 13:42:49.839228 ==
1501 13:42:49.842206 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1502 13:42:49.845635 fsp= 1, odt_onoff= 1, Byte mode= 0
1503 13:42:49.845750 ==
1504 13:42:49.848819 DQS Delay:
1505 13:42:49.848929 DQS0 = 0, DQS1 = 0
1506 13:42:49.849019 DQM Delay:
1507 13:42:49.852007 DQM0 = 19, DQM1 = 17
1508 13:42:49.852121 DQ Delay:
1509 13:42:49.855270 DQ0 =21, DQ1 =22, DQ2 =24, DQ3 =14
1510 13:42:49.858804 DQ4 =21, DQ5 =17, DQ6 =18, DQ7 =20
1511 13:42:49.861934 DQ8 =14, DQ9 =17, DQ10 =23, DQ11 =15
1512 13:42:49.865425 DQ12 =17, DQ13 =17, DQ14 =18, DQ15 =20
1513 13:42:49.865547
1514 13:42:49.865648
1515 13:42:49.865739
1516 13:42:49.868617 [DramC_TX_OE_Calibration] TA2
1517 13:42:49.871901 Original DQ_B0 (3 6) =30, OEN = 27
1518 13:42:49.875039 Original DQ_B1 (3 6) =30, OEN = 27
1519 13:42:49.878181 23, 0x0, End_B0=23 End_B1=23
1520 13:42:49.881381 24, 0x0, End_B0=24 End_B1=24
1521 13:42:49.881502 25, 0x0, End_B0=25 End_B1=25
1522 13:42:49.884790 26, 0x0, End_B0=26 End_B1=26
1523 13:42:49.888058 27, 0x0, End_B0=27 End_B1=27
1524 13:42:49.891563 28, 0x0, End_B0=28 End_B1=28
1525 13:42:49.894681 29, 0x0, End_B0=29 End_B1=29
1526 13:42:49.894765 30, 0x0, End_B0=30 End_B1=30
1527 13:42:49.897849 31, 0xFFFF, End_B0=30 End_B1=30
1528 13:42:49.904666 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1529 13:42:49.911004 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1530 13:42:49.911156
1531 13:42:49.911256
1532 13:42:49.911349 Write Rank0 MR23 =0x3f
1533 13:42:49.914114 [DQSOSC]
1534 13:42:49.920815 [DQSOSCAuto] RK0, (LSB)MR18= 0xc0c0, (MSB)MR19= 0x202, tDQSOscB0 = 447 ps tDQSOscB1 = 447 ps
1535 13:42:49.927322 CH0_RK0: MR19=0x202, MR18=0xC0C0, DQSOSC=447, MR23=63, INC=12, DEC=18
1536 13:42:49.930524 Write Rank0 MR23 =0x3f
1537 13:42:49.930652 [DQSOSC]
1538 13:42:49.937257 [DQSOSCAuto] RK0, (LSB)MR18= 0xc0c0, (MSB)MR19= 0x202, tDQSOscB0 = 447 ps tDQSOscB1 = 447 ps
1539 13:42:49.940304 CH0 RK0: MR19=202, MR18=C0C0
1540 13:42:49.943811 [RankSwap] Rank num 2, (Multi 1), Rank 1
1541 13:42:49.946867 Write Rank0 MR2 =0xad
1542 13:42:49.946997 [Write Leveling]
1543 13:42:49.950244 delay byte0 byte1 byte2 byte3
1544 13:42:49.950359
1545 13:42:49.953378 10 0 0
1546 13:42:49.953500 11 0 0
1547 13:42:49.957014 12 0 0
1548 13:42:49.957139 13 0 0
1549 13:42:49.957242 14 0 0
1550 13:42:49.960299 15 0 0
1551 13:42:49.960420 16 0 0
1552 13:42:49.963378 17 0 0
1553 13:42:49.963629 18 0 0
1554 13:42:49.963705 19 0 0
1555 13:42:49.966516 20 0 0
1556 13:42:49.966596 21 0 0
1557 13:42:49.970001 22 0 0
1558 13:42:49.970092 23 0 0
1559 13:42:49.973105 24 0 ff
1560 13:42:49.973201 25 0 ff
1561 13:42:49.973270 26 0 ff
1562 13:42:49.976474 27 ff ff
1563 13:42:49.976601 28 ff ff
1564 13:42:49.980022 29 ff ff
1565 13:42:49.980142 30 ff ff
1566 13:42:49.983229 31 ff ff
1567 13:42:49.983319 32 ff ff
1568 13:42:49.986368 33 ff ff
1569 13:42:49.989543 pass bytecount = 0xff (0xff: all bytes pass)
1570 13:42:49.989642
1571 13:42:49.989711 DQS0 dly: 27
1572 13:42:49.992854 DQS1 dly: 24
1573 13:42:49.992953 Write Rank0 MR2 =0x2d
1574 13:42:49.999238 [RankSwap] Rank num 2, (Multi 1), Rank 0
1575 13:42:49.999379 Write Rank1 MR1 =0xd6
1576 13:42:49.999483 [Gating]
1577 13:42:50.002720 ==
1578 13:42:50.006017 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1579 13:42:50.009379 fsp= 1, odt_onoff= 1, Byte mode= 0
1580 13:42:50.009503 ==
1581 13:42:50.012711 3 1 0 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1582 13:42:50.019132 3 1 4 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1583 13:42:50.022225 3 1 8 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1584 13:42:50.025616 3 1 12 |2c2b 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
1585 13:42:50.032066 3 1 16 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
1586 13:42:50.035656 3 1 20 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
1587 13:42:50.038762 3 1 24 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
1588 13:42:50.045456 [Byte 0] Lead/lag falling Transition (3, 1, 24)
1589 13:42:50.048703 3 1 28 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1590 13:42:50.051790 3 2 0 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1591 13:42:50.058373 3 2 4 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1592 13:42:50.061585 3 2 8 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1593 13:42:50.065096 3 2 12 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1594 13:42:50.071350 3 2 16 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1595 13:42:50.074793 [Byte 0] Lead/lag Transition tap number (7)
1596 13:42:50.078119 3 2 20 |303 2c2b |(11 11)(11 11) |(0 0)(0 0)| 0
1597 13:42:50.081231 3 2 24 |1413 2a29 |(11 11)(11 11) |(0 0)(0 0)| 0
1598 13:42:50.087853 3 2 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1599 13:42:50.091078 3 3 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1600 13:42:50.094344 3 3 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1601 13:42:50.100818 3 3 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1602 13:42:50.104296 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1603 13:42:50.107443 3 3 16 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1604 13:42:50.114269 3 3 20 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1605 13:42:50.117548 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1606 13:42:50.120864 [Byte 1] Lead/lag falling Transition (3, 3, 24)
1607 13:42:50.127186 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1608 13:42:50.130425 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1609 13:42:50.133741 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1610 13:42:50.140256 3 4 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1611 13:42:50.143490 3 4 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1612 13:42:50.146700 3 4 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1613 13:42:50.153508 3 4 20 |2c2b 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1614 13:42:50.156529 3 4 24 |3d3d e0d |(11 11)(11 11) |(1 1)(1 1)| 0
1615 13:42:50.160077 3 4 28 |3d3d b0a |(11 11)(11 11) |(1 1)(1 1)| 0
1616 13:42:50.166465 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1617 13:42:50.169701 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1618 13:42:50.173240 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1619 13:42:50.179578 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1620 13:42:50.182739 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1621 13:42:50.185949 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1622 13:42:50.192765 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1623 13:42:50.195807 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1624 13:42:50.199409 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1625 13:42:50.205618 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1626 13:42:50.208785 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1627 13:42:50.212315 [Byte 0] Lead/lag falling Transition (3, 6, 8)
1628 13:42:50.218772 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1629 13:42:50.222091 [Byte 1] Lead/lag falling Transition (3, 6, 12)
1630 13:42:50.225371 3 6 16 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
1631 13:42:50.228728 [Byte 0] Lead/lag Transition tap number (3)
1632 13:42:50.235028 3 6 20 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
1633 13:42:50.238241 [Byte 1] Lead/lag Transition tap number (3)
1634 13:42:50.241784 3 6 24 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
1635 13:42:50.244935 [Byte 0]First pass (3, 6, 24)
1636 13:42:50.248358 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1637 13:42:50.251419 [Byte 1]First pass (3, 6, 28)
1638 13:42:50.254861 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1639 13:42:50.258121 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1640 13:42:50.264615 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1641 13:42:50.267973 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1642 13:42:50.271151 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1643 13:42:50.274406 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1644 13:42:50.281231 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1645 13:42:50.284214 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1646 13:42:50.287354 All bytes gating window > 1UI, Early break!
1647 13:42:50.287451
1648 13:42:50.290649 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 14)
1649 13:42:50.290748
1650 13:42:50.294118 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 18)
1651 13:42:50.294236
1652 13:42:50.294330
1653 13:42:50.297176
1654 13:42:50.300668 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 14)
1655 13:42:50.300774
1656 13:42:50.303719 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 18)
1657 13:42:50.303798
1658 13:42:50.303873
1659 13:42:50.306964 Write Rank1 MR1 =0x56
1660 13:42:50.307040
1661 13:42:50.310613 best RODT dly(2T, 0.5T) = (2, 3)
1662 13:42:50.310692
1663 13:42:50.313705 best RODT dly(2T, 0.5T) = (2, 3)
1664 13:42:50.313793 ==
1665 13:42:50.316831 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1666 13:42:50.320328 fsp= 1, odt_onoff= 1, Byte mode= 0
1667 13:42:50.320425 ==
1668 13:42:50.326744 Start DQ dly to find pass range UseTestEngine =0
1669 13:42:50.329980 x-axis: bit #, y-axis: DQ dly (-127~63)
1670 13:42:50.330078 RX Vref Scan = 0
1671 13:42:50.333457 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1672 13:42:50.336503 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1673 13:42:50.339673 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1674 13:42:50.343283 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1675 13:42:50.346544 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1676 13:42:50.346669 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1677 13:42:50.349936 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1678 13:42:50.352952 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1679 13:42:50.356480 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1680 13:42:50.359666 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1681 13:42:50.362760 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1682 13:42:50.366162 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1683 13:42:50.369152 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1684 13:42:50.372406 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1685 13:42:50.375904 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1686 13:42:50.376032 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1687 13:42:50.379171 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1688 13:42:50.382333 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1689 13:42:50.385810 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1690 13:42:50.388953 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1691 13:42:50.392172 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1692 13:42:50.395312 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1693 13:42:50.398910 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1694 13:42:50.399040 -3, [0] xxxxxxxx oxxxxxxx [MSB]
1695 13:42:50.402072 -2, [0] xxxoxxxx oxxoxxxx [MSB]
1696 13:42:50.405136 -1, [0] xxxoxxxx oxxoxxxx [MSB]
1697 13:42:50.408447 0, [0] xxxoxoxx ooxoooxx [MSB]
1698 13:42:50.411655 1, [0] xxxoxoox ooxoooxx [MSB]
1699 13:42:50.415277 2, [0] xxxoxoox ooxoooxx [MSB]
1700 13:42:50.418465 3, [0] xxxooooo ooxoooox [MSB]
1701 13:42:50.418557 4, [0] xoxooooo ooxoooox [MSB]
1702 13:42:50.421708 5, [0] ooxooooo ooxooooo [MSB]
1703 13:42:50.425210 32, [0] oooxoooo oooooooo [MSB]
1704 13:42:50.428294 33, [0] oooxoooo oooooooo [MSB]
1705 13:42:50.431605 34, [0] oooxoooo xooxoooo [MSB]
1706 13:42:50.434942 35, [0] oooxoooo xxoxoooo [MSB]
1707 13:42:50.438070 36, [0] oooxoxxo xxoxxxxo [MSB]
1708 13:42:50.438223 37, [0] oooxoxxx xxoxxxxo [MSB]
1709 13:42:50.441401 38, [0] oooxoxxx xxoxxxxo [MSB]
1710 13:42:50.444677 39, [0] ooxxxxxx xxoxxxxx [MSB]
1711 13:42:50.447797 40, [0] xoxxxxxx xxoxxxxx [MSB]
1712 13:42:50.451131 41, [0] xxxxxxxx xxoxxxxx [MSB]
1713 13:42:50.454612 42, [0] xxxxxxxx xxoxxxxx [MSB]
1714 13:42:50.457598 43, [0] xxxxxxxx xxxxxxxx [MSB]
1715 13:42:50.461268 iDelay=43, Bit 0, Center 22 (5 ~ 39) 35
1716 13:42:50.464460 iDelay=43, Bit 1, Center 22 (4 ~ 40) 37
1717 13:42:50.467759 iDelay=43, Bit 2, Center 22 (6 ~ 38) 33
1718 13:42:50.470840 iDelay=43, Bit 3, Center 14 (-2 ~ 31) 34
1719 13:42:50.474126 iDelay=43, Bit 4, Center 20 (3 ~ 38) 36
1720 13:42:50.477537 iDelay=43, Bit 5, Center 17 (0 ~ 35) 36
1721 13:42:50.480765 iDelay=43, Bit 6, Center 18 (1 ~ 35) 35
1722 13:42:50.483879 iDelay=43, Bit 7, Center 19 (3 ~ 36) 34
1723 13:42:50.487105 iDelay=43, Bit 8, Center 15 (-3 ~ 33) 37
1724 13:42:50.490492 iDelay=43, Bit 9, Center 17 (0 ~ 34) 35
1725 13:42:50.497064 iDelay=43, Bit 10, Center 24 (6 ~ 42) 37
1726 13:42:50.500182 iDelay=43, Bit 11, Center 15 (-2 ~ 33) 36
1727 13:42:50.503724 iDelay=43, Bit 12, Center 17 (0 ~ 35) 36
1728 13:42:50.506853 iDelay=43, Bit 13, Center 17 (0 ~ 35) 36
1729 13:42:50.510309 iDelay=43, Bit 14, Center 19 (3 ~ 35) 33
1730 13:42:50.513422 iDelay=43, Bit 15, Center 21 (5 ~ 38) 34
1731 13:42:50.513516 ==
1732 13:42:50.520098 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1733 13:42:50.523246 fsp= 1, odt_onoff= 1, Byte mode= 0
1734 13:42:50.523342 ==
1735 13:42:50.523409 DQS Delay:
1736 13:42:50.526392 DQS0 = 0, DQS1 = 0
1737 13:42:50.526515 DQM Delay:
1738 13:42:50.529637 DQM0 = 19, DQM1 = 18
1739 13:42:50.529728 DQ Delay:
1740 13:42:50.533202 DQ0 =22, DQ1 =22, DQ2 =22, DQ3 =14
1741 13:42:50.536246 DQ4 =20, DQ5 =17, DQ6 =18, DQ7 =19
1742 13:42:50.539497 DQ8 =15, DQ9 =17, DQ10 =24, DQ11 =15
1743 13:42:50.543064 DQ12 =17, DQ13 =17, DQ14 =19, DQ15 =21
1744 13:42:50.543159
1745 13:42:50.543228
1746 13:42:50.543290 DramC Write-DBI off
1747 13:42:50.546042 ==
1748 13:42:50.549637 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1749 13:42:50.552915 fsp= 1, odt_onoff= 1, Byte mode= 0
1750 13:42:50.553010 ==
1751 13:42:50.556367 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1752 13:42:50.556458
1753 13:42:50.559182 Begin, DQ Scan Range 920~1176
1754 13:42:50.559284
1755 13:42:50.559351
1756 13:42:50.562487 TX Vref Scan disable
1757 13:42:50.565947 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1758 13:42:50.569195 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1759 13:42:50.572451 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1760 13:42:50.575644 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1761 13:42:50.578811 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1762 13:42:50.582303 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1763 13:42:50.585597 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1764 13:42:50.592097 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1765 13:42:50.595166 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1766 13:42:50.598716 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1767 13:42:50.601759 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1768 13:42:50.604942 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1769 13:42:50.608426 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1770 13:42:50.611533 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1771 13:42:50.615073 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1772 13:42:50.618084 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1773 13:42:50.621616 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1774 13:42:50.624819 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1775 13:42:50.627857 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1776 13:42:50.634575 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1777 13:42:50.637676 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1778 13:42:50.641195 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1779 13:42:50.644418 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1780 13:42:50.647662 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1781 13:42:50.650810 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1782 13:42:50.654293 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1783 13:42:50.657350 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1784 13:42:50.660708 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1785 13:42:50.664158 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1786 13:42:50.667292 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1787 13:42:50.670714 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1788 13:42:50.673869 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1789 13:42:50.680542 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1790 13:42:50.683735 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1791 13:42:50.686909 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1792 13:42:50.690049 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1793 13:42:50.693617 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1794 13:42:50.696681 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1795 13:42:50.700107 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1796 13:42:50.703274 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1797 13:42:50.706442 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1798 13:42:50.709996 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1799 13:42:50.713090 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1800 13:42:50.716285 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1801 13:42:50.719768 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1802 13:42:50.722733 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1803 13:42:50.726410 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1804 13:42:50.732687 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1805 13:42:50.735952 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
1806 13:42:50.739408 969 |3 6 9|[0] xxxxxxxx oxxxxxxx [MSB]
1807 13:42:50.742594 970 |3 6 10|[0] xxxxxxxx oxxoxxxx [MSB]
1808 13:42:50.745749 971 |3 6 11|[0] xxxxxxxx ooxoxoox [MSB]
1809 13:42:50.749128 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1810 13:42:50.752577 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1811 13:42:50.755585 974 |3 6 14|[0] xxxxxxxx ooxoooox [MSB]
1812 13:42:50.758779 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
1813 13:42:50.762232 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1814 13:42:50.765457 977 |3 6 17|[0] xoxoooox oooooooo [MSB]
1815 13:42:50.768604 978 |3 6 18|[0] ooxooooo oooooooo [MSB]
1816 13:42:50.776485 989 |3 6 29|[0] oooooooo oooxoooo [MSB]
1817 13:42:50.779737 990 |3 6 30|[0] oooooooo oooxoooo [MSB]
1818 13:42:50.782906 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1819 13:42:50.786291 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1820 13:42:50.789372 993 |3 6 33|[0] oooxoooo xxxxxxxx [MSB]
1821 13:42:50.792893 994 |3 6 34|[0] oooxoxoo xxxxxxxx [MSB]
1822 13:42:50.796233 995 |3 6 35|[0] oooxoxoo xxxxxxxx [MSB]
1823 13:42:50.799263 996 |3 6 36|[0] oooxoxxo xxxxxxxx [MSB]
1824 13:42:50.802819 997 |3 6 37|[0] oooxoxxo xxxxxxxx [MSB]
1825 13:42:50.805659 998 |3 6 38|[0] xxxxxxxx xxxxxxxx [MSB]
1826 13:42:50.809134 Byte0, DQ PI dly=986, DQM PI dly= 986
1827 13:42:50.815580 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
1828 13:42:50.815694
1829 13:42:50.818803 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
1830 13:42:50.818897
1831 13:42:50.822380 Byte1, DQ PI dly=980, DQM PI dly= 980
1832 13:42:50.825504 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
1833 13:42:50.825597
1834 13:42:50.832207 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
1835 13:42:50.832316
1836 13:42:50.832384 ==
1837 13:42:50.835388 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1838 13:42:50.838642 fsp= 1, odt_onoff= 1, Byte mode= 0
1839 13:42:50.838732 ==
1840 13:42:50.845298 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1841 13:42:50.845406
1842 13:42:50.848436 Begin, DQ Scan Range 956~1020
1843 13:42:50.848526 Write Rank1 MR14 =0x0
1844 13:42:50.856658
1845 13:42:50.856791 CH=0, VrefRange= 0, VrefLevel = 0
1846 13:42:50.863415 TX Bit0 (981~992) 12 986, Bit8 (971~984) 14 977,
1847 13:42:50.866437 TX Bit1 (979~992) 14 985, Bit9 (975~984) 10 979,
1848 13:42:50.873122 TX Bit2 (981~992) 12 986, Bit10 (978~991) 14 984,
1849 13:42:50.876303 TX Bit3 (976~989) 14 982, Bit11 (974~983) 10 978,
1850 13:42:50.879763 TX Bit4 (979~992) 14 985, Bit12 (975~984) 10 979,
1851 13:42:50.886324 TX Bit5 (978~988) 11 983, Bit13 (974~986) 13 980,
1852 13:42:50.889547 TX Bit6 (978~991) 14 984, Bit14 (974~990) 17 982,
1853 13:42:50.896092 TX Bit7 (979~992) 14 985, Bit15 (978~991) 14 984,
1854 13:42:50.896216
1855 13:42:50.899427 wait MRW command Rank1 MR14 =0x2 fired (1)
1856 13:42:50.899550 Write Rank1 MR14 =0x2
1857 13:42:50.908476
1858 13:42:50.908599 CH=0, VrefRange= 0, VrefLevel = 2
1859 13:42:50.914752 TX Bit0 (981~993) 13 987, Bit8 (971~984) 14 977,
1860 13:42:50.918210 TX Bit1 (979~993) 15 986, Bit9 (974~984) 11 979,
1861 13:42:50.924727 TX Bit2 (981~992) 12 986, Bit10 (977~991) 15 984,
1862 13:42:50.927930 TX Bit3 (975~990) 16 982, Bit11 (973~983) 11 978,
1863 13:42:50.931389 TX Bit4 (979~992) 14 985, Bit12 (975~984) 10 979,
1864 13:42:50.937872 TX Bit5 (978~990) 13 984, Bit13 (974~986) 13 980,
1865 13:42:50.940973 TX Bit6 (978~991) 14 984, Bit14 (974~991) 18 982,
1866 13:42:50.947653 TX Bit7 (979~993) 15 986, Bit15 (977~991) 15 984,
1867 13:42:50.947778
1868 13:42:50.947848 Write Rank1 MR14 =0x4
1869 13:42:50.956255
1870 13:42:50.956380 CH=0, VrefRange= 0, VrefLevel = 4
1871 13:42:50.962905 TX Bit0 (980~993) 14 986, Bit8 (971~985) 15 978,
1872 13:42:50.965923 TX Bit1 (979~994) 16 986, Bit9 (974~985) 12 979,
1873 13:42:50.972775 TX Bit2 (980~993) 14 986, Bit10 (977~992) 16 984,
1874 13:42:50.976011 TX Bit3 (974~990) 17 982, Bit11 (973~984) 12 978,
1875 13:42:50.979102 TX Bit4 (979~993) 15 986, Bit12 (974~986) 13 980,
1876 13:42:50.985922 TX Bit5 (977~990) 14 983, Bit13 (974~987) 14 980,
1877 13:42:50.989139 TX Bit6 (977~992) 16 984, Bit14 (974~991) 18 982,
1878 13:42:50.995745 TX Bit7 (979~994) 16 986, Bit15 (976~992) 17 984,
1879 13:42:50.995866
1880 13:42:50.998845 wait MRW command Rank1 MR14 =0x6 fired (1)
1881 13:42:50.999062 Write Rank1 MR14 =0x6
1882 13:42:51.008231
1883 13:42:51.008360 CH=0, VrefRange= 0, VrefLevel = 6
1884 13:42:51.014595 TX Bit0 (979~994) 16 986, Bit8 (970~986) 17 978,
1885 13:42:51.017907 TX Bit1 (978~995) 18 986, Bit9 (974~986) 13 980,
1886 13:42:51.024574 TX Bit2 (980~993) 14 986, Bit10 (977~993) 17 985,
1887 13:42:51.027857 TX Bit3 (974~991) 18 982, Bit11 (972~985) 14 978,
1888 13:42:51.031295 TX Bit4 (978~994) 17 986, Bit12 (974~986) 13 980,
1889 13:42:51.037658 TX Bit5 (977~991) 15 984, Bit13 (973~989) 17 981,
1890 13:42:51.041101 TX Bit6 (977~992) 16 984, Bit14 (973~991) 19 982,
1891 13:42:51.047467 TX Bit7 (978~994) 17 986, Bit15 (976~992) 17 984,
1892 13:42:51.047587
1893 13:42:51.047670 Write Rank1 MR14 =0x8
1894 13:42:51.056629
1895 13:42:51.056777 CH=0, VrefRange= 0, VrefLevel = 8
1896 13:42:51.062797 TX Bit0 (979~995) 17 987, Bit8 (970~987) 18 978,
1897 13:42:51.066120 TX Bit1 (978~995) 18 986, Bit9 (973~987) 15 980,
1898 13:42:51.072858 TX Bit2 (979~994) 16 986, Bit10 (976~993) 18 984,
1899 13:42:51.075886 TX Bit3 (974~991) 18 982, Bit11 (972~985) 14 978,
1900 13:42:51.079232 TX Bit4 (978~994) 17 986, Bit12 (973~987) 15 980,
1901 13:42:51.085818 TX Bit5 (977~991) 15 984, Bit13 (973~989) 17 981,
1902 13:42:51.089040 TX Bit6 (977~993) 17 985, Bit14 (973~992) 20 982,
1903 13:42:51.095629 TX Bit7 (978~995) 18 986, Bit15 (976~993) 18 984,
1904 13:42:51.095758
1905 13:42:51.095862 Write Rank1 MR14 =0xa
1906 13:42:51.104965
1907 13:42:51.108225 CH=0, VrefRange= 0, VrefLevel = 10
1908 13:42:51.111382 TX Bit0 (979~996) 18 987, Bit8 (969~987) 19 978,
1909 13:42:51.114601 TX Bit1 (978~997) 20 987, Bit9 (972~988) 17 980,
1910 13:42:51.121303 TX Bit2 (979~995) 17 987, Bit10 (976~994) 19 985,
1911 13:42:51.124621 TX Bit3 (973~991) 19 982, Bit11 (971~986) 16 978,
1912 13:42:51.127907 TX Bit4 (978~995) 18 986, Bit12 (973~988) 16 980,
1913 13:42:51.134390 TX Bit5 (977~992) 16 984, Bit13 (972~990) 19 981,
1914 13:42:51.137617 TX Bit6 (977~993) 17 985, Bit14 (973~992) 20 982,
1915 13:42:51.144173 TX Bit7 (978~996) 19 987, Bit15 (976~994) 19 985,
1916 13:42:51.144326
1917 13:42:51.144432 Write Rank1 MR14 =0xc
1918 13:42:51.153464
1919 13:42:51.156533 CH=0, VrefRange= 0, VrefLevel = 12
1920 13:42:51.160137 TX Bit0 (979~997) 19 988, Bit8 (969~988) 20 978,
1921 13:42:51.163291 TX Bit1 (978~998) 21 988, Bit9 (972~989) 18 980,
1922 13:42:51.169638 TX Bit2 (979~996) 18 987, Bit10 (976~993) 18 984,
1923 13:42:51.173267 TX Bit3 (973~991) 19 982, Bit11 (970~987) 18 978,
1924 13:42:51.176515 TX Bit4 (978~996) 19 987, Bit12 (973~989) 17 981,
1925 13:42:51.182854 TX Bit5 (976~992) 17 984, Bit13 (973~990) 18 981,
1926 13:42:51.186220 TX Bit6 (977~994) 18 985, Bit14 (972~992) 21 982,
1927 13:42:51.192742 TX Bit7 (978~997) 20 987, Bit15 (976~993) 18 984,
1928 13:42:51.192889
1929 13:42:51.192992 Write Rank1 MR14 =0xe
1930 13:42:51.202145
1931 13:42:51.205288 CH=0, VrefRange= 0, VrefLevel = 14
1932 13:42:51.208733 TX Bit0 (978~998) 21 988, Bit8 (969~989) 21 979,
1933 13:42:51.211827 TX Bit1 (978~998) 21 988, Bit9 (972~990) 19 981,
1934 13:42:51.218468 TX Bit2 (979~997) 19 988, Bit10 (976~995) 20 985,
1935 13:42:51.222063 TX Bit3 (973~992) 20 982, Bit11 (970~988) 19 979,
1936 13:42:51.225077 TX Bit4 (978~997) 20 987, Bit12 (972~990) 19 981,
1937 13:42:51.231646 TX Bit5 (976~993) 18 984, Bit13 (972~990) 19 981,
1938 13:42:51.234971 TX Bit6 (977~995) 19 986, Bit14 (972~993) 22 982,
1939 13:42:51.241605 TX Bit7 (978~998) 21 988, Bit15 (976~995) 20 985,
1940 13:42:51.241722
1941 13:42:51.241811 Write Rank1 MR14 =0x10
1942 13:42:51.250938
1943 13:42:51.254154 CH=0, VrefRange= 0, VrefLevel = 16
1944 13:42:51.257437 TX Bit0 (978~998) 21 988, Bit8 (969~990) 22 979,
1945 13:42:51.260837 TX Bit1 (978~998) 21 988, Bit9 (971~990) 20 980,
1946 13:42:51.267136 TX Bit2 (979~998) 20 988, Bit10 (975~996) 22 985,
1947 13:42:51.270735 TX Bit3 (972~992) 21 982, Bit11 (969~988) 20 978,
1948 13:42:51.273937 TX Bit4 (978~998) 21 988, Bit12 (972~990) 19 981,
1949 13:42:51.280256 TX Bit5 (976~993) 18 984, Bit13 (971~991) 21 981,
1950 13:42:51.283809 TX Bit6 (976~995) 20 985, Bit14 (972~993) 22 982,
1951 13:42:51.290121 TX Bit7 (978~998) 21 988, Bit15 (975~995) 21 985,
1952 13:42:51.290242
1953 13:42:51.290309 Write Rank1 MR14 =0x12
1954 13:42:51.299880
1955 13:42:51.303078 CH=0, VrefRange= 0, VrefLevel = 18
1956 13:42:51.306556 TX Bit0 (978~999) 22 988, Bit8 (969~990) 22 979,
1957 13:42:51.309638 TX Bit1 (978~999) 22 988, Bit9 (970~991) 22 980,
1958 13:42:51.316220 TX Bit2 (978~998) 21 988, Bit10 (975~997) 23 986,
1959 13:42:51.319371 TX Bit3 (971~993) 23 982, Bit11 (969~989) 21 979,
1960 13:42:51.322636 TX Bit4 (977~998) 22 987, Bit12 (971~991) 21 981,
1961 13:42:51.329332 TX Bit5 (976~994) 19 985, Bit13 (971~991) 21 981,
1962 13:42:51.332400 TX Bit6 (976~996) 21 986, Bit14 (971~994) 24 982,
1963 13:42:51.339065 TX Bit7 (978~999) 22 988, Bit15 (975~996) 22 985,
1964 13:42:51.339206
1965 13:42:51.339304 Write Rank1 MR14 =0x14
1966 13:42:51.349126
1967 13:42:51.352081 CH=0, VrefRange= 0, VrefLevel = 20
1968 13:42:51.355339 TX Bit0 (978~999) 22 988, Bit8 (968~990) 23 979,
1969 13:42:51.358830 TX Bit1 (977~999) 23 988, Bit9 (970~990) 21 980,
1970 13:42:51.365312 TX Bit2 (978~999) 22 988, Bit10 (975~997) 23 986,
1971 13:42:51.368601 TX Bit3 (971~993) 23 982, Bit11 (969~990) 22 979,
1972 13:42:51.371771 TX Bit4 (977~998) 22 987, Bit12 (971~991) 21 981,
1973 13:42:51.378250 TX Bit5 (975~995) 21 985, Bit13 (970~992) 23 981,
1974 13:42:51.381434 TX Bit6 (976~997) 22 986, Bit14 (971~994) 24 982,
1975 13:42:51.388265 TX Bit7 (978~999) 22 988, Bit15 (975~997) 23 986,
1976 13:42:51.388407
1977 13:42:51.388505 Write Rank1 MR14 =0x16
1978 13:42:51.397906
1979 13:42:51.401434 CH=0, VrefRange= 0, VrefLevel = 22
1980 13:42:51.404719 TX Bit0 (978~1000) 23 989, Bit8 (968~991) 24 979,
1981 13:42:51.407809 TX Bit1 (977~999) 23 988, Bit9 (970~991) 22 980,
1982 13:42:51.414487 TX Bit2 (978~999) 22 988, Bit10 (975~997) 23 986,
1983 13:42:51.418099 TX Bit3 (971~993) 23 982, Bit11 (969~990) 22 979,
1984 13:42:51.420844 TX Bit4 (977~999) 23 988, Bit12 (970~991) 22 980,
1985 13:42:51.427240 TX Bit5 (975~995) 21 985, Bit13 (970~992) 23 981,
1986 13:42:51.430748 TX Bit6 (976~998) 23 987, Bit14 (970~995) 26 982,
1987 13:42:51.437315 TX Bit7 (977~999) 23 988, Bit15 (975~997) 23 986,
1988 13:42:51.437450
1989 13:42:51.437522 Write Rank1 MR14 =0x18
1990 13:42:51.447270
1991 13:42:51.450453 CH=0, VrefRange= 0, VrefLevel = 24
1992 13:42:51.453754 TX Bit0 (978~1000) 23 989, Bit8 (968~991) 24 979,
1993 13:42:51.457038 TX Bit1 (977~1000) 24 988, Bit9 (970~991) 22 980,
1994 13:42:51.463634 TX Bit2 (978~999) 22 988, Bit10 (975~998) 24 986,
1995 13:42:51.466739 TX Bit3 (971~994) 24 982, Bit11 (968~991) 24 979,
1996 13:42:51.470072 TX Bit4 (977~999) 23 988, Bit12 (970~992) 23 981,
1997 13:42:51.476727 TX Bit5 (975~996) 22 985, Bit13 (970~993) 24 981,
1998 13:42:51.480017 TX Bit6 (975~998) 24 986, Bit14 (970~996) 27 983,
1999 13:42:51.486499 TX Bit7 (977~1000) 24 988, Bit15 (975~998) 24 986,
2000 13:42:51.486652
2001 13:42:51.486751 Write Rank1 MR14 =0x1a
2002 13:42:51.496801
2003 13:42:51.499950 CH=0, VrefRange= 0, VrefLevel = 26
2004 13:42:51.503312 TX Bit0 (978~1001) 24 989, Bit8 (968~991) 24 979,
2005 13:42:51.506685 TX Bit1 (977~1000) 24 988, Bit9 (969~991) 23 980,
2006 13:42:51.512777 TX Bit2 (978~999) 22 988, Bit10 (975~998) 24 986,
2007 13:42:51.516352 TX Bit3 (970~995) 26 982, Bit11 (968~991) 24 979,
2008 13:42:51.519598 TX Bit4 (977~999) 23 988, Bit12 (970~992) 23 981,
2009 13:42:51.526014 TX Bit5 (974~996) 23 985, Bit13 (969~993) 25 981,
2010 13:42:51.529415 TX Bit6 (975~999) 25 987, Bit14 (969~996) 28 982,
2011 13:42:51.536065 TX Bit7 (977~1000) 24 988, Bit15 (974~998) 25 986,
2012 13:42:51.536221
2013 13:42:51.536322 Write Rank1 MR14 =0x1c
2014 13:42:51.546080
2015 13:42:51.549562 CH=0, VrefRange= 0, VrefLevel = 28
2016 13:42:51.552661 TX Bit0 (977~1001) 25 989, Bit8 (968~992) 25 980,
2017 13:42:51.556089 TX Bit1 (977~1001) 25 989, Bit9 (969~992) 24 980,
2018 13:42:51.562595 TX Bit2 (978~1000) 23 989, Bit10 (975~999) 25 987,
2019 13:42:51.565736 TX Bit3 (970~995) 26 982, Bit11 (968~991) 24 979,
2020 13:42:51.572429 TX Bit4 (977~1000) 24 988, Bit12 (970~993) 24 981,
2021 13:42:51.575707 TX Bit5 (974~997) 24 985, Bit13 (969~993) 25 981,
2022 13:42:51.578777 TX Bit6 (975~999) 25 987, Bit14 (969~996) 28 982,
2023 13:42:51.585557 TX Bit7 (977~1001) 25 989, Bit15 (974~998) 25 986,
2024 13:42:51.585693
2025 13:42:51.585796 Write Rank1 MR14 =0x1e
2026 13:42:51.596040
2027 13:42:51.599409 CH=0, VrefRange= 0, VrefLevel = 30
2028 13:42:51.602645 TX Bit0 (978~1002) 25 990, Bit8 (967~992) 26 979,
2029 13:42:51.605636 TX Bit1 (977~1000) 24 988, Bit9 (969~992) 24 980,
2030 13:42:51.612439 TX Bit2 (978~1000) 23 989, Bit10 (974~999) 26 986,
2031 13:42:51.615447 TX Bit3 (970~995) 26 982, Bit11 (968~992) 25 980,
2032 13:42:51.622288 TX Bit4 (977~1000) 24 988, Bit12 (969~993) 25 981,
2033 13:42:51.625430 TX Bit5 (974~998) 25 986, Bit13 (969~993) 25 981,
2034 13:42:51.628707 TX Bit6 (976~999) 24 987, Bit14 (970~995) 26 982,
2035 13:42:51.635374 TX Bit7 (977~1001) 25 989, Bit15 (974~998) 25 986,
2036 13:42:51.635502
2037 13:42:51.635571 Write Rank1 MR14 =0x20
2038 13:42:51.645535
2039 13:42:51.648870 CH=0, VrefRange= 0, VrefLevel = 32
2040 13:42:51.652416 TX Bit0 (978~1002) 25 990, Bit8 (967~992) 26 979,
2041 13:42:51.655424 TX Bit1 (977~1000) 24 988, Bit9 (969~992) 24 980,
2042 13:42:51.662134 TX Bit2 (978~1000) 23 989, Bit10 (974~999) 26 986,
2043 13:42:51.665516 TX Bit3 (970~995) 26 982, Bit11 (968~992) 25 980,
2044 13:42:51.672108 TX Bit4 (977~1000) 24 988, Bit12 (969~993) 25 981,
2045 13:42:51.675039 TX Bit5 (974~998) 25 986, Bit13 (969~993) 25 981,
2046 13:42:51.678367 TX Bit6 (976~999) 24 987, Bit14 (970~995) 26 982,
2047 13:42:51.685120 TX Bit7 (977~1001) 25 989, Bit15 (974~998) 25 986,
2048 13:42:51.685230
2049 13:42:51.685300 Write Rank1 MR14 =0x22
2050 13:42:51.695492
2051 13:42:51.698777 CH=0, VrefRange= 0, VrefLevel = 34
2052 13:42:51.701958 TX Bit0 (978~1002) 25 990, Bit8 (967~992) 26 979,
2053 13:42:51.705292 TX Bit1 (977~1000) 24 988, Bit9 (969~992) 24 980,
2054 13:42:51.711653 TX Bit2 (978~1000) 23 989, Bit10 (974~999) 26 986,
2055 13:42:51.715095 TX Bit3 (970~995) 26 982, Bit11 (968~992) 25 980,
2056 13:42:51.721495 TX Bit4 (977~1000) 24 988, Bit12 (969~993) 25 981,
2057 13:42:51.724676 TX Bit5 (974~998) 25 986, Bit13 (969~993) 25 981,
2058 13:42:51.727910 TX Bit6 (976~999) 24 987, Bit14 (970~995) 26 982,
2059 13:42:51.734691 TX Bit7 (977~1001) 25 989, Bit15 (974~998) 25 986,
2060 13:42:51.734820
2061 13:42:51.734889 Write Rank1 MR14 =0x24
2062 13:42:51.745133
2063 13:42:51.748299 CH=0, VrefRange= 0, VrefLevel = 36
2064 13:42:51.751680 TX Bit0 (978~1002) 25 990, Bit8 (967~992) 26 979,
2065 13:42:51.755025 TX Bit1 (977~1000) 24 988, Bit9 (969~992) 24 980,
2066 13:42:51.761276 TX Bit2 (978~1000) 23 989, Bit10 (974~999) 26 986,
2067 13:42:51.764667 TX Bit3 (970~995) 26 982, Bit11 (968~992) 25 980,
2068 13:42:51.771286 TX Bit4 (977~1000) 24 988, Bit12 (969~993) 25 981,
2069 13:42:51.774600 TX Bit5 (974~998) 25 986, Bit13 (969~993) 25 981,
2070 13:42:51.777920 TX Bit6 (976~999) 24 987, Bit14 (970~995) 26 982,
2071 13:42:51.784634 TX Bit7 (977~1001) 25 989, Bit15 (974~998) 25 986,
2072 13:42:51.784761
2073 13:42:51.784852 Write Rank1 MR14 =0x26
2074 13:42:51.794657
2075 13:42:51.798152 CH=0, VrefRange= 0, VrefLevel = 38
2076 13:42:51.801454 TX Bit0 (978~1002) 25 990, Bit8 (967~992) 26 979,
2077 13:42:51.804671 TX Bit1 (977~1000) 24 988, Bit9 (969~992) 24 980,
2078 13:42:51.810931 TX Bit2 (978~1000) 23 989, Bit10 (974~999) 26 986,
2079 13:42:51.814297 TX Bit3 (970~995) 26 982, Bit11 (968~992) 25 980,
2080 13:42:51.820735 TX Bit4 (977~1000) 24 988, Bit12 (969~993) 25 981,
2081 13:42:51.824119 TX Bit5 (974~998) 25 986, Bit13 (969~993) 25 981,
2082 13:42:51.827336 TX Bit6 (976~999) 24 987, Bit14 (970~995) 26 982,
2083 13:42:51.834172 TX Bit7 (977~1001) 25 989, Bit15 (974~998) 25 986,
2084 13:42:51.834300
2085 13:42:51.834393
2086 13:42:51.837395 TX Vref found, early break! 371< 378
2087 13:42:51.840598 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
2088 13:42:51.843765 u1DelayCellOfst[0]=10 cells (8 PI)
2089 13:42:51.846964 u1DelayCellOfst[1]=7 cells (6 PI)
2090 13:42:51.850184 u1DelayCellOfst[2]=9 cells (7 PI)
2091 13:42:51.853432 u1DelayCellOfst[3]=0 cells (0 PI)
2092 13:42:51.856930 u1DelayCellOfst[4]=7 cells (6 PI)
2093 13:42:51.860149 u1DelayCellOfst[5]=5 cells (4 PI)
2094 13:42:51.863252 u1DelayCellOfst[6]=6 cells (5 PI)
2095 13:42:51.866879 u1DelayCellOfst[7]=9 cells (7 PI)
2096 13:42:51.870027 Byte0, DQ PI dly=982, DQM PI dly= 986
2097 13:42:51.873214 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
2098 13:42:51.873332
2099 13:42:51.876500 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
2100 13:42:51.876588
2101 13:42:51.879904 u1DelayCellOfst[8]=0 cells (0 PI)
2102 13:42:51.883020 u1DelayCellOfst[9]=1 cells (1 PI)
2103 13:42:51.886098 u1DelayCellOfst[10]=9 cells (7 PI)
2104 13:42:51.889571 u1DelayCellOfst[11]=1 cells (1 PI)
2105 13:42:51.892982 u1DelayCellOfst[12]=2 cells (2 PI)
2106 13:42:51.896049 u1DelayCellOfst[13]=2 cells (2 PI)
2107 13:42:51.899432 u1DelayCellOfst[14]=3 cells (3 PI)
2108 13:42:51.902623 u1DelayCellOfst[15]=9 cells (7 PI)
2109 13:42:51.905995 Byte1, DQ PI dly=979, DQM PI dly= 982
2110 13:42:51.909188 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
2111 13:42:51.909371
2112 13:42:51.915842 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
2113 13:42:51.916032
2114 13:42:51.919046 wait MRW command Rank1 MR14 =0x1e fired (1)
2115 13:42:51.922381 Write Rank1 MR14 =0x1e
2116 13:42:51.922561
2117 13:42:51.922675 Final TX Range 0 Vref 30
2118 13:42:51.922771
2119 13:42:51.929026 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2120 13:42:51.929190
2121 13:42:51.935211 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2122 13:42:51.945307 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2123 13:42:51.951619 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2124 13:42:51.951734 Write Rank1 MR3 =0xb0
2125 13:42:51.954894 DramC Write-DBI on
2126 13:42:51.954984 ==
2127 13:42:51.958556 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2128 13:42:51.961613 fsp= 1, odt_onoff= 1, Byte mode= 0
2129 13:42:51.961705 ==
2130 13:42:51.968057 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2131 13:42:51.968161
2132 13:42:51.971347 Begin, DQ Scan Range 702~766
2133 13:42:51.971475
2134 13:42:51.971546
2135 13:42:51.971608 TX Vref Scan disable
2136 13:42:51.974443 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2137 13:42:51.978085 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2138 13:42:51.984416 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2139 13:42:51.987736 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2140 13:42:51.990991 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2141 13:42:51.994276 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2142 13:42:51.997433 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2143 13:42:52.000984 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2144 13:42:52.004049 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2145 13:42:52.007268 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2146 13:42:52.010702 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2147 13:42:52.014046 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2148 13:42:52.017195 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2149 13:42:52.020366 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2150 13:42:52.023840 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2151 13:42:52.027095 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2152 13:42:52.030348 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
2153 13:42:52.039725 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2154 13:42:52.042600 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2155 13:42:52.046237 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2156 13:42:52.049416 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2157 13:42:52.052682 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2158 13:42:52.055861 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2159 13:42:52.059041 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2160 13:42:52.062641 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
2161 13:42:52.065862 746 |2 6 42|[0] xxxxxxxx xxxxxxxx [MSB]
2162 13:42:52.069057 Byte0, DQ PI dly=732, DQM PI dly= 732
2163 13:42:52.075534 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 28)
2164 13:42:52.075628
2165 13:42:52.078750 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 28)
2166 13:42:52.078872
2167 13:42:52.082306 Byte1, DQ PI dly=724, DQM PI dly= 724
2168 13:42:52.085469 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 20)
2169 13:42:52.085556
2170 13:42:52.092073 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 20)
2171 13:42:52.092178
2172 13:42:52.098620 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2173 13:42:52.104948 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2174 13:42:52.111665 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2175 13:42:52.114825 Write Rank1 MR3 =0x30
2176 13:42:52.114913 DramC Write-DBI off
2177 13:42:52.114980
2178 13:42:52.115041 [DATLAT]
2179 13:42:52.118043 Freq=1600, CH0 RK1, use_rxtx_scan=0
2180 13:42:52.118133
2181 13:42:52.121357 DATLAT Default: 0x10
2182 13:42:52.124507 7, 0xFFFF, sum=0
2183 13:42:52.124597 8, 0xFFFF, sum=0
2184 13:42:52.124665 9, 0xFFFF, sum=0
2185 13:42:52.127949 10, 0xFFFF, sum=0
2186 13:42:52.128038 11, 0xFFFF, sum=0
2187 13:42:52.131186 12, 0xFFFF, sum=0
2188 13:42:52.131296 13, 0xFFFF, sum=0
2189 13:42:52.134847 14, 0x0, sum=1
2190 13:42:52.134943 15, 0x0, sum=2
2191 13:42:52.137535 16, 0x0, sum=3
2192 13:42:52.137637 17, 0x0, sum=4
2193 13:42:52.144239 pattern=2 first_step=14 total pass=5 best_step=16
2194 13:42:52.144330 ==
2195 13:42:52.147344 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2196 13:42:52.150740 fsp= 1, odt_onoff= 1, Byte mode= 0
2197 13:42:52.150852 ==
2198 13:42:52.157232 Start DQ dly to find pass range UseTestEngine =1
2199 13:42:52.160399 x-axis: bit #, y-axis: DQ dly (-127~63)
2200 13:42:52.160514 RX Vref Scan = 0
2201 13:42:52.163921 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2202 13:42:52.167558 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2203 13:42:52.170731 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2204 13:42:52.173853 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2205 13:42:52.173951 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2206 13:42:52.177354 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2207 13:42:52.180582 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2208 13:42:52.183609 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2209 13:42:52.187113 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2210 13:42:52.190299 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2211 13:42:52.193571 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2212 13:42:52.196942 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2213 13:42:52.200312 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2214 13:42:52.203347 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2215 13:42:52.203485 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2216 13:42:52.206650 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2217 13:42:52.209838 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2218 13:42:52.213048 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2219 13:42:52.216611 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2220 13:42:52.219759 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2221 13:42:52.223019 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2222 13:42:52.226352 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2223 13:42:52.226439 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2224 13:42:52.229468 -3, [0] xxxoxxxx oxxxxxxx [MSB]
2225 13:42:52.232826 -2, [0] xxxoxxxx ooxoxoxx [MSB]
2226 13:42:52.236021 -1, [0] xxxoxxxx ooxoxoxx [MSB]
2227 13:42:52.239324 0, [0] xxxoxoxx ooxoooxx [MSB]
2228 13:42:52.242623 1, [0] xxxoxoox ooxoooxx [MSB]
2229 13:42:52.245996 2, [0] xxxoxoox ooxoooox [MSB]
2230 13:42:52.246084 3, [0] xxxoxooo ooxoooox [MSB]
2231 13:42:52.249350 4, [0] oxxoxooo ooxooooo [MSB]
2232 13:42:52.254075 32, [0] oooxoooo oooooooo [MSB]
2233 13:42:52.257271 33, [0] oooxoooo xooxoooo [MSB]
2234 13:42:52.260352 34, [0] oooxoooo xooxoooo [MSB]
2235 13:42:52.263742 35, [0] oooxoxoo xxoxxxoo [MSB]
2236 13:42:52.267084 36, [0] oooxoxxo xxoxxxoo [MSB]
2237 13:42:52.270370 37, [0] oooxoxxo xxoxxxxo [MSB]
2238 13:42:52.273481 38, [0] oooxoxxx xxoxxxxx [MSB]
2239 13:42:52.273568 39, [0] oxoxxxxx xxoxxxxx [MSB]
2240 13:42:52.276911 40, [0] xxoxxxxx xxoxxxxx [MSB]
2241 13:42:52.280075 41, [0] xxxxxxxx xxxxxxxx [MSB]
2242 13:42:52.283257 iDelay=41, Bit 0, Center 21 (4 ~ 39) 36
2243 13:42:52.286490 iDelay=41, Bit 1, Center 21 (5 ~ 38) 34
2244 13:42:52.289940 iDelay=41, Bit 2, Center 22 (5 ~ 40) 36
2245 13:42:52.296677 iDelay=41, Bit 3, Center 14 (-3 ~ 31) 35
2246 13:42:52.299690 iDelay=41, Bit 4, Center 21 (5 ~ 38) 34
2247 13:42:52.303158 iDelay=41, Bit 5, Center 17 (0 ~ 34) 35
2248 13:42:52.306202 iDelay=41, Bit 6, Center 18 (1 ~ 35) 35
2249 13:42:52.309446 iDelay=41, Bit 7, Center 20 (3 ~ 37) 35
2250 13:42:52.312698 iDelay=41, Bit 8, Center 14 (-3 ~ 32) 36
2251 13:42:52.316309 iDelay=41, Bit 9, Center 16 (-2 ~ 34) 37
2252 13:42:52.319398 iDelay=41, Bit 10, Center 22 (5 ~ 40) 36
2253 13:42:52.322640 iDelay=41, Bit 11, Center 15 (-2 ~ 32) 35
2254 13:42:52.325875 iDelay=41, Bit 12, Center 17 (0 ~ 34) 35
2255 13:42:52.332344 iDelay=41, Bit 13, Center 16 (-2 ~ 34) 37
2256 13:42:52.335696 iDelay=41, Bit 14, Center 19 (2 ~ 36) 35
2257 13:42:52.339191 iDelay=41, Bit 15, Center 20 (4 ~ 37) 34
2258 13:42:52.339276 ==
2259 13:42:52.342186 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2260 13:42:52.345681 fsp= 1, odt_onoff= 1, Byte mode= 0
2261 13:42:52.345766 ==
2262 13:42:52.348878 DQS Delay:
2263 13:42:52.348963 DQS0 = 0, DQS1 = 0
2264 13:42:52.352051 DQM Delay:
2265 13:42:52.352136 DQM0 = 19, DQM1 = 17
2266 13:42:52.352203 DQ Delay:
2267 13:42:52.355368 DQ0 =21, DQ1 =21, DQ2 =22, DQ3 =14
2268 13:42:52.358752 DQ4 =21, DQ5 =17, DQ6 =18, DQ7 =20
2269 13:42:52.362158 DQ8 =14, DQ9 =16, DQ10 =22, DQ11 =15
2270 13:42:52.365160 DQ12 =17, DQ13 =16, DQ14 =19, DQ15 =20
2271 13:42:52.365244
2272 13:42:52.365310
2273 13:42:52.368495
2274 13:42:52.368605 [DramC_TX_OE_Calibration] TA2
2275 13:42:52.371729 Original DQ_B0 (3 6) =30, OEN = 27
2276 13:42:52.375028 Original DQ_B1 (3 6) =30, OEN = 27
2277 13:42:52.378388 23, 0x0, End_B0=23 End_B1=23
2278 13:42:52.381597 24, 0x0, End_B0=24 End_B1=24
2279 13:42:52.385041 25, 0x0, End_B0=25 End_B1=25
2280 13:42:52.385127 26, 0x0, End_B0=26 End_B1=26
2281 13:42:52.388293 27, 0x0, End_B0=27 End_B1=27
2282 13:42:52.391446 28, 0x0, End_B0=28 End_B1=28
2283 13:42:52.394754 29, 0x0, End_B0=29 End_B1=29
2284 13:42:52.398151 30, 0x0, End_B0=30 End_B1=30
2285 13:42:52.398238 31, 0xFFFF, End_B0=30 End_B1=30
2286 13:42:52.404457 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2287 13:42:52.411110 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2288 13:42:52.411196
2289 13:42:52.411262
2290 13:42:52.414287 Write Rank1 MR23 =0x3f
2291 13:42:52.414372 [DQSOSC]
2292 13:42:52.421049 [DQSOSCAuto] RK1, (LSB)MR18= 0xa6a6, (MSB)MR19= 0x202, tDQSOscB0 = 464 ps tDQSOscB1 = 464 ps
2293 13:42:52.427355 CH0_RK1: MR19=0x202, MR18=0xA6A6, DQSOSC=464, MR23=63, INC=11, DEC=17
2294 13:42:52.430619 Write Rank1 MR23 =0x3f
2295 13:42:52.430703 [DQSOSC]
2296 13:42:52.437379 [DQSOSCAuto] RK1, (LSB)MR18= 0xa6a6, (MSB)MR19= 0x202, tDQSOscB0 = 464 ps tDQSOscB1 = 464 ps
2297 13:42:52.440438 CH0 RK1: MR19=202, MR18=A6A6
2298 13:42:52.443644 [RxdqsGatingPostProcess] freq 1600
2299 13:42:52.450181 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2300 13:42:52.450267 Rank: 0
2301 13:42:52.453799 best DQS0 dly(2T, 0.5T) = (2, 6)
2302 13:42:52.457103 best DQS1 dly(2T, 0.5T) = (2, 6)
2303 13:42:52.460367 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2304 13:42:52.463487 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2305 13:42:52.463572 Rank: 1
2306 13:42:52.466624 best DQS0 dly(2T, 0.5T) = (2, 6)
2307 13:42:52.469868 best DQS1 dly(2T, 0.5T) = (2, 6)
2308 13:42:52.473099 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2309 13:42:52.476370 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2310 13:42:52.479808 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2311 13:42:52.483044 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2312 13:42:52.489600 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2313 13:42:52.489685 Write Rank0 MR13 =0x59
2314 13:42:52.492996 ==
2315 13:42:52.496246 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2316 13:42:52.499446 fsp= 1, odt_onoff= 1, Byte mode= 0
2317 13:42:52.499539 ==
2318 13:42:52.502685 === u2Vref_new: 0x56 --> 0x3a
2319 13:42:52.505833 === u2Vref_new: 0x58 --> 0x58
2320 13:42:52.509304 === u2Vref_new: 0x5a --> 0x5a
2321 13:42:52.512390 === u2Vref_new: 0x5c --> 0x78
2322 13:42:52.515653 === u2Vref_new: 0x5e --> 0x7a
2323 13:42:52.518943 === u2Vref_new: 0x60 --> 0x90
2324 13:42:52.522142 [CA 0] Center 38 (13~63) winsize 51
2325 13:42:52.525322 [CA 1] Center 37 (11~63) winsize 53
2326 13:42:52.528871 [CA 2] Center 34 (6~63) winsize 58
2327 13:42:52.532011 [CA 3] Center 35 (7~63) winsize 57
2328 13:42:52.535229 [CA 4] Center 34 (5~63) winsize 59
2329 13:42:52.538654 [CA 5] Center 28 (-1~58) winsize 60
2330 13:42:52.538738
2331 13:42:52.542043 [CATrainingPosCal] consider 1 rank data
2332 13:42:52.545241 u2DelayCellTimex100 = 744/100 ps
2333 13:42:52.548471 CA0 delay=38 (13~63),Diff = 10 PI (13 cell)
2334 13:42:52.551643 CA1 delay=37 (11~63),Diff = 9 PI (11 cell)
2335 13:42:52.555170 CA2 delay=34 (6~63),Diff = 6 PI (7 cell)
2336 13:42:52.558422 CA3 delay=35 (7~63),Diff = 7 PI (9 cell)
2337 13:42:52.561449 CA4 delay=34 (5~63),Diff = 6 PI (7 cell)
2338 13:42:52.564831 CA5 delay=28 (-1~58),Diff = 0 PI (0 cell)
2339 13:42:52.564915
2340 13:42:52.571584 CA PerBit enable=1, Macro0, CA PI delay=28
2341 13:42:52.571709 === u2Vref_new: 0x5a --> 0x5a
2342 13:42:52.571777
2343 13:42:52.574696 Vref(ca) range 1: 26
2344 13:42:52.574810
2345 13:42:52.577937 CS Dly= 12 (43-0-32)
2346 13:42:52.578039 Write Rank0 MR13 =0xd8
2347 13:42:52.581318 Write Rank0 MR13 =0xd8
2348 13:42:52.584438 Write Rank0 MR12 =0x5a
2349 13:42:52.584522 Write Rank1 MR13 =0x59
2350 13:42:52.584587 ==
2351 13:42:52.591101 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2352 13:42:52.594443 fsp= 1, odt_onoff= 1, Byte mode= 0
2353 13:42:52.594528 ==
2354 13:42:52.597381 === u2Vref_new: 0x56 --> 0x3a
2355 13:42:52.600751 === u2Vref_new: 0x58 --> 0x58
2356 13:42:52.603887 === u2Vref_new: 0x5a --> 0x5a
2357 13:42:52.607258 === u2Vref_new: 0x5c --> 0x78
2358 13:42:52.607344 === u2Vref_new: 0x5e --> 0x7a
2359 13:42:52.610909 === u2Vref_new: 0x60 --> 0x90
2360 13:42:52.614430 [CA 0] Center 37 (12~63) winsize 52
2361 13:42:52.617661 [CA 1] Center 37 (11~63) winsize 53
2362 13:42:52.620868 [CA 2] Center 33 (4~63) winsize 60
2363 13:42:52.624185 [CA 3] Center 35 (7~63) winsize 57
2364 13:42:52.627337 [CA 4] Center 33 (4~63) winsize 60
2365 13:42:52.630436 [CA 5] Center 28 (-1~57) winsize 59
2366 13:42:52.630521
2367 13:42:52.634013 [CATrainingPosCal] consider 2 rank data
2368 13:42:52.637115 u2DelayCellTimex100 = 744/100 ps
2369 13:42:52.640666 CA0 delay=38 (13~63),Diff = 10 PI (13 cell)
2370 13:42:52.647200 CA1 delay=37 (11~63),Diff = 9 PI (11 cell)
2371 13:42:52.650429 CA2 delay=34 (6~63),Diff = 6 PI (7 cell)
2372 13:42:52.653796 CA3 delay=35 (7~63),Diff = 7 PI (9 cell)
2373 13:42:52.656766 CA4 delay=34 (5~63),Diff = 6 PI (7 cell)
2374 13:42:52.660043 CA5 delay=28 (-1~57),Diff = 0 PI (0 cell)
2375 13:42:52.660127
2376 13:42:52.663438 CA PerBit enable=1, Macro0, CA PI delay=28
2377 13:42:52.666896 === u2Vref_new: 0x5e --> 0x7a
2378 13:42:52.666981
2379 13:42:52.669749 Vref(ca) range 1: 30
2380 13:42:52.669836
2381 13:42:52.669902 CS Dly= 10 (41-0-32)
2382 13:42:52.673240 Write Rank1 MR13 =0xd8
2383 13:42:52.676502 Write Rank1 MR13 =0xd8
2384 13:42:52.676585 Write Rank1 MR12 =0x5e
2385 13:42:52.679625 [RankSwap] Rank num 2, (Multi 1), Rank 0
2386 13:42:52.682908 Write Rank0 MR2 =0xad
2387 13:42:52.682991 [Write Leveling]
2388 13:42:52.686336 delay byte0 byte1 byte2 byte3
2389 13:42:52.686419
2390 13:42:52.689693 10 0 0
2391 13:42:52.689777 11 0 0
2392 13:42:52.692811 12 0 0
2393 13:42:52.692896 13 0 0
2394 13:42:52.692962 14 0 0
2395 13:42:52.696248 15 0 0
2396 13:42:52.696335 16 0 0
2397 13:42:52.699276 17 0 0
2398 13:42:52.699360 18 0 0
2399 13:42:52.702709 19 0 0
2400 13:42:52.702796 20 0 0
2401 13:42:52.702864 21 0 0
2402 13:42:52.705871 22 0 0
2403 13:42:52.705956 23 0 0
2404 13:42:52.709216 24 0 0
2405 13:42:52.709301 25 0 0
2406 13:42:52.712320 26 0 0
2407 13:42:52.712405 27 0 0
2408 13:42:52.712472 28 0 ff
2409 13:42:52.715683 29 0 ff
2410 13:42:52.715768 30 0 ff
2411 13:42:52.718782 31 0 ff
2412 13:42:52.718868 32 0 ff
2413 13:42:52.722219 33 0 ff
2414 13:42:52.722305 34 0 ff
2415 13:42:52.725440 35 ff ff
2416 13:42:52.725526 36 0 ff
2417 13:42:52.728723 37 ff ff
2418 13:42:52.728810 38 ff ff
2419 13:42:52.728876 39 ff ff
2420 13:42:52.732020 40 ff ff
2421 13:42:52.732106 41 ff ff
2422 13:42:52.735151 42 ff ff
2423 13:42:52.735237 43 ff ff
2424 13:42:52.742100 pass bytecount = 0xff (0xff: all bytes pass)
2425 13:42:52.742185
2426 13:42:52.742252 DQS0 dly: 37
2427 13:42:52.742314 DQS1 dly: 28
2428 13:42:52.745028 Write Rank0 MR2 =0x2d
2429 13:42:52.748421 [RankSwap] Rank num 2, (Multi 1), Rank 0
2430 13:42:52.751944 Write Rank0 MR1 =0xd6
2431 13:42:52.752029 [Gating]
2432 13:42:52.752095 ==
2433 13:42:52.758147 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2434 13:42:52.761726 fsp= 1, odt_onoff= 1, Byte mode= 0
2435 13:42:52.761812 ==
2436 13:42:52.764654 3 1 0 |2c2b 202 |(11 11)(11 11) |(1 1)(0 0)| 0
2437 13:42:52.768118 3 1 4 |2c2b 3635 |(11 11)(11 11) |(1 1)(0 0)| 0
2438 13:42:52.774763 3 1 8 |2c2b 3635 |(11 11)(11 11) |(1 1)(0 0)| 0
2439 13:42:52.777970 3 1 12 |2c2b e0e |(11 11)(11 11) |(1 1)(1 1)| 0
2440 13:42:52.781238 3 1 16 |2c2b 3636 |(11 11)(0 0) |(1 0)(0 0)| 0
2441 13:42:52.784354 3 1 20 |2c2b 3635 |(11 11)(11 11) |(1 0)(1 1)| 0
2442 13:42:52.791065 3 1 24 |2c2b 3635 |(11 11)(11 11) |(1 0)(1 1)| 0
2443 13:42:52.794212 3 1 28 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
2444 13:42:52.797653 3 2 0 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
2445 13:42:52.804199 3 2 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
2446 13:42:52.807365 3 2 8 |2c2b 3332 |(11 11)(11 11) |(1 0)(0 1)| 0
2447 13:42:52.810467 3 2 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
2448 13:42:52.817032 3 2 16 |303 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
2449 13:42:52.820399 3 2 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
2450 13:42:52.823417 3 2 24 |3534 1716 |(11 11)(11 11) |(0 0)(1 1)| 0
2451 13:42:52.830075 [Byte 1] Lead/lag Transition tap number (1)
2452 13:42:52.833564 3 2 28 |3534 3d3d |(11 11)(11 11) |(0 0)(0 0)| 0
2453 13:42:52.836766 3 3 0 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2454 13:42:52.843329 3 3 4 |3534 3b3b |(11 11)(11 11) |(0 0)(1 1)| 0
2455 13:42:52.846652 3 3 8 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2456 13:42:52.849825 3 3 12 |3534 1514 |(11 11)(11 11) |(1 1)(1 1)| 0
2457 13:42:52.856363 3 3 16 |3534 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0
2458 13:42:52.859571 3 3 20 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2459 13:42:52.862795 [Byte 0] Lead/lag falling Transition (3, 3, 20)
2460 13:42:52.869435 3 3 24 |3534 403 |(11 11)(11 11) |(0 1)(1 1)| 0
2461 13:42:52.872962 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2462 13:42:52.876065 [Byte 1] Lead/lag falling Transition (3, 3, 28)
2463 13:42:52.882695 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2464 13:42:52.885674 [Byte 1] Lead/lag Transition tap number (2)
2465 13:42:52.889290 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2466 13:42:52.892431 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2467 13:42:52.898892 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2468 13:42:52.902417 3 4 16 |403 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2469 13:42:52.905427 3 4 20 |c0c 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2470 13:42:52.912035 3 4 24 |3d3d 505 |(11 11)(11 11) |(1 1)(1 1)| 0
2471 13:42:52.915463 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2472 13:42:52.918490 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2473 13:42:52.925043 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2474 13:42:52.928386 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2475 13:42:52.931474 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2476 13:42:52.938374 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2477 13:42:52.941695 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2478 13:42:52.944885 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2479 13:42:52.951128 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2480 13:42:52.954623 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2481 13:42:52.957928 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2482 13:42:52.964397 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2483 13:42:52.967558 [Byte 0] Lead/lag falling Transition (3, 6, 8)
2484 13:42:52.971052 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2485 13:42:52.974267 [Byte 0] Lead/lag Transition tap number (2)
2486 13:42:52.980669 [Byte 1] Lead/lag falling Transition (3, 6, 12)
2487 13:42:52.983878 3 6 16 |1e1e 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2488 13:42:52.987375 3 6 20 |4646 3e3d |(0 0)(11 11) |(0 0)(1 0)| 0
2489 13:42:52.990447 [Byte 0]First pass (3, 6, 20)
2490 13:42:52.994036 [Byte 1] Lead/lag Transition tap number (3)
2491 13:42:53.000447 3 6 24 |4646 404 |(0 0)(11 11) |(0 0)(0 0)| 0
2492 13:42:53.003726 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2493 13:42:53.006896 [Byte 1]First pass (3, 6, 28)
2494 13:42:53.010164 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2495 13:42:53.013435 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2496 13:42:53.016757 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2497 13:42:53.019924 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2498 13:42:53.026525 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2499 13:42:53.030101 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2500 13:42:53.033515 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2501 13:42:53.036308 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2502 13:42:53.042845 All bytes gating window > 1UI, Early break!
2503 13:42:53.042930
2504 13:42:53.046189 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 12)
2505 13:42:53.046274
2506 13:42:53.049366 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 18)
2507 13:42:53.049451
2508 13:42:53.049518
2509 13:42:53.049579
2510 13:42:53.053246 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
2511 13:42:53.053331
2512 13:42:53.059332 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 18)
2513 13:42:53.059419
2514 13:42:53.059495
2515 13:42:53.059558 Write Rank0 MR1 =0x56
2516 13:42:53.059618
2517 13:42:53.062476 best RODT dly(2T, 0.5T) = (2, 3)
2518 13:42:53.062561
2519 13:42:53.065991 best RODT dly(2T, 0.5T) = (2, 3)
2520 13:42:53.066076 ==
2521 13:42:53.072368 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2522 13:42:53.075815 fsp= 1, odt_onoff= 1, Byte mode= 0
2523 13:42:53.075901 ==
2524 13:42:53.079025 Start DQ dly to find pass range UseTestEngine =0
2525 13:42:53.082246 x-axis: bit #, y-axis: DQ dly (-127~63)
2526 13:42:53.085387 RX Vref Scan = 0
2527 13:42:53.089116 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2528 13:42:53.089203 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2529 13:42:53.092184 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2530 13:42:53.095347 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2531 13:42:53.098444 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2532 13:42:53.101752 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2533 13:42:53.105296 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2534 13:42:53.108451 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2535 13:42:53.111552 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2536 13:42:53.115015 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2537 13:42:53.115103 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2538 13:42:53.118162 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2539 13:42:53.121635 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2540 13:42:53.124700 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2541 13:42:53.128090 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2542 13:42:53.131259 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2543 13:42:53.134844 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2544 13:42:53.137919 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2545 13:42:53.141053 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2546 13:42:53.141140 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2547 13:42:53.144627 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2548 13:42:53.147699 -5, [0] xxxxxxxx xxxxxxxo [MSB]
2549 13:42:53.150992 -4, [0] xxxxxxxx xxxxxxxo [MSB]
2550 13:42:53.154182 -3, [0] xxxxxxxx xxxxxxxo [MSB]
2551 13:42:53.157575 -2, [0] xxxxxxxx xoxxxxxo [MSB]
2552 13:42:53.160689 -1, [0] xxxoxxxx ooxxxxxo [MSB]
2553 13:42:53.163870 0, [0] xxxoxxxx ooxxxxxo [MSB]
2554 13:42:53.163957 1, [0] xxooxxxo ooxxxxxo [MSB]
2555 13:42:53.167408 2, [0] xxooxxxo oooxxxxo [MSB]
2556 13:42:53.170566 3, [0] xxooxxxo ooooxxoo [MSB]
2557 13:42:53.173885 4, [0] xooooxxo oooooooo [MSB]
2558 13:42:53.176986 5, [0] oooooxxo oooooooo [MSB]
2559 13:42:53.180391 6, [0] oooooxoo oooooooo [MSB]
2560 13:42:53.180478 32, [0] oooooooo ooooooox [MSB]
2561 13:42:53.183563 33, [0] oooooooo ooooooox [MSB]
2562 13:42:53.187184 34, [0] oooooooo ooooooox [MSB]
2563 13:42:53.190429 35, [0] ooxooooo oxooooox [MSB]
2564 13:42:53.193624 36, [0] ooxxoooo oxooooox [MSB]
2565 13:42:53.196730 37, [0] ooxxoooo xxooooox [MSB]
2566 13:42:53.199984 38, [0] ooxxoooo xxooooox [MSB]
2567 13:42:53.203264 39, [0] oxxxooox xxxxooox [MSB]
2568 13:42:53.203351 40, [0] oxxxxoox xxxxxoox [MSB]
2569 13:42:53.206710 41, [0] xxxxxoxx xxxxxxxx [MSB]
2570 13:42:53.209951 42, [0] xxxxxoxx xxxxxxxx [MSB]
2571 13:42:53.213185 43, [0] xxxxxxxx xxxxxxxx [MSB]
2572 13:42:53.216441 iDelay=43, Bit 0, Center 22 (5 ~ 40) 36
2573 13:42:53.219437 iDelay=43, Bit 1, Center 21 (4 ~ 38) 35
2574 13:42:53.222909 iDelay=43, Bit 2, Center 17 (1 ~ 34) 34
2575 13:42:53.226368 iDelay=43, Bit 3, Center 17 (-1 ~ 35) 37
2576 13:42:53.229467 iDelay=43, Bit 4, Center 21 (4 ~ 39) 36
2577 13:42:53.236049 iDelay=43, Bit 5, Center 24 (7 ~ 42) 36
2578 13:42:53.239468 iDelay=43, Bit 6, Center 23 (6 ~ 40) 35
2579 13:42:53.242763 iDelay=43, Bit 7, Center 19 (1 ~ 38) 38
2580 13:42:53.245975 iDelay=43, Bit 8, Center 17 (-1 ~ 36) 38
2581 13:42:53.249215 iDelay=43, Bit 9, Center 16 (-2 ~ 34) 37
2582 13:42:53.252475 iDelay=43, Bit 10, Center 20 (2 ~ 38) 37
2583 13:42:53.255602 iDelay=43, Bit 11, Center 20 (3 ~ 38) 36
2584 13:42:53.258813 iDelay=43, Bit 12, Center 21 (4 ~ 39) 36
2585 13:42:53.262088 iDelay=43, Bit 13, Center 22 (4 ~ 40) 37
2586 13:42:53.265456 iDelay=43, Bit 14, Center 21 (3 ~ 40) 38
2587 13:42:53.271938 iDelay=43, Bit 15, Center 13 (-5 ~ 31) 37
2588 13:42:53.272023 ==
2589 13:42:53.275110 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2590 13:42:53.278661 fsp= 1, odt_onoff= 1, Byte mode= 0
2591 13:42:53.278747 ==
2592 13:42:53.281749 DQS Delay:
2593 13:42:53.281834 DQS0 = 0, DQS1 = 0
2594 13:42:53.281900 DQM Delay:
2595 13:42:53.285192 DQM0 = 20, DQM1 = 18
2596 13:42:53.285277 DQ Delay:
2597 13:42:53.288314 DQ0 =22, DQ1 =21, DQ2 =17, DQ3 =17
2598 13:42:53.291622 DQ4 =21, DQ5 =24, DQ6 =23, DQ7 =19
2599 13:42:53.294750 DQ8 =17, DQ9 =16, DQ10 =20, DQ11 =20
2600 13:42:53.298004 DQ12 =21, DQ13 =22, DQ14 =21, DQ15 =13
2601 13:42:53.298089
2602 13:42:53.298155
2603 13:42:53.301463 DramC Write-DBI off
2604 13:42:53.301547 ==
2605 13:42:53.304692 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2606 13:42:53.307948 fsp= 1, odt_onoff= 1, Byte mode= 0
2607 13:42:53.311383 ==
2608 13:42:53.314403 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2609 13:42:53.314488
2610 13:42:53.317697 Begin, DQ Scan Range 924~1180
2611 13:42:53.317783
2612 13:42:53.317849
2613 13:42:53.317908 TX Vref Scan disable
2614 13:42:53.320913 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
2615 13:42:53.327731 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
2616 13:42:53.330934 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
2617 13:42:53.334020 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
2618 13:42:53.337493 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
2619 13:42:53.340604 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2620 13:42:53.344186 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2621 13:42:53.347404 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2622 13:42:53.350594 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2623 13:42:53.353721 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2624 13:42:53.357280 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2625 13:42:53.360445 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2626 13:42:53.363622 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2627 13:42:53.370098 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2628 13:42:53.373295 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2629 13:42:53.376778 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2630 13:42:53.380083 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2631 13:42:53.383314 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2632 13:42:53.386615 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2633 13:42:53.389744 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2634 13:42:53.393164 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2635 13:42:53.396509 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2636 13:42:53.399769 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2637 13:42:53.402768 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2638 13:42:53.406291 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2639 13:42:53.409747 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2640 13:42:53.416058 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2641 13:42:53.419177 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2642 13:42:53.422646 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2643 13:42:53.425948 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2644 13:42:53.429078 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2645 13:42:53.432198 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2646 13:42:53.435620 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2647 13:42:53.438989 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2648 13:42:53.442367 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2649 13:42:53.445523 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2650 13:42:53.448864 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2651 13:42:53.452106 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2652 13:42:53.455197 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2653 13:42:53.458715 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2654 13:42:53.465136 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2655 13:42:53.468341 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2656 13:42:53.471739 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2657 13:42:53.474860 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2658 13:42:53.478200 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2659 13:42:53.481425 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2660 13:42:53.484911 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
2661 13:42:53.487965 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
2662 13:42:53.491130 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
2663 13:42:53.494691 973 |3 6 13|[0] xxxxxxxx xoxxxxxo [MSB]
2664 13:42:53.497745 974 |3 6 14|[0] xxxxxxxx ooxxxxxo [MSB]
2665 13:42:53.501081 975 |3 6 15|[0] xxxxxxxx ooxxxxxo [MSB]
2666 13:42:53.504443 976 |3 6 16|[0] xxxxxxxx oooxoxxo [MSB]
2667 13:42:53.507558 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
2668 13:42:53.510780 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
2669 13:42:53.517411 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB]
2670 13:42:53.520621 980 |3 6 20|[0] xxxxxxxx oooooooo [MSB]
2671 13:42:53.524136 981 |3 6 21|[0] xxxxxxxx oooooooo [MSB]
2672 13:42:53.527261 982 |3 6 22|[0] xxxxxxxx oooooooo [MSB]
2673 13:42:53.530456 983 |3 6 23|[0] xxxxxxxx oooooooo [MSB]
2674 13:42:53.533984 984 |3 6 24|[0] xooooxoo oooooooo [MSB]
2675 13:42:53.536952 991 |3 6 31|[0] oooooooo ooooooox [MSB]
2676 13:42:53.540277 992 |3 6 32|[0] oooooooo oxooooox [MSB]
2677 13:42:53.543547 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
2678 13:42:53.550040 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
2679 13:42:53.553365 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
2680 13:42:53.556857 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
2681 13:42:53.560023 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
2682 13:42:53.563226 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
2683 13:42:53.566733 999 |3 6 39|[0] oooooooo xxxxxxxx [MSB]
2684 13:42:53.569910 1000 |3 6 40|[0] oooooooo xxxxxxxx [MSB]
2685 13:42:53.573141 1001 |3 6 41|[0] oooxoooo xxxxxxxx [MSB]
2686 13:42:53.576379 1002 |3 6 42|[0] oooxoooo xxxxxxxx [MSB]
2687 13:42:53.579656 1003 |3 6 43|[0] oooxoooo xxxxxxxx [MSB]
2688 13:42:53.582879 1004 |3 6 44|[0] ooxxoooo xxxxxxxx [MSB]
2689 13:42:53.589403 1005 |3 6 45|[0] ooxxoooo xxxxxxxx [MSB]
2690 13:42:53.592931 1006 |3 6 46|[0] oxxxxxxx xxxxxxxx [MSB]
2691 13:42:53.596160 1007 |3 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
2692 13:42:53.599183 Byte0, DQ PI dly=993, DQM PI dly= 993
2693 13:42:53.602739 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 33)
2694 13:42:53.602844
2695 13:42:53.609080 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 33)
2696 13:42:53.609168
2697 13:42:53.612437 Byte1, DQ PI dly=982, DQM PI dly= 982
2698 13:42:53.615882 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
2699 13:42:53.615967
2700 13:42:53.618955 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
2701 13:42:53.619040
2702 13:42:53.619106 ==
2703 13:42:53.625724 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2704 13:42:53.628848 fsp= 1, odt_onoff= 1, Byte mode= 0
2705 13:42:53.628936 ==
2706 13:42:53.632336 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2707 13:42:53.632422
2708 13:42:53.635432 Begin, DQ Scan Range 958~1022
2709 13:42:53.638611 Write Rank0 MR14 =0x0
2710 13:42:53.646694
2711 13:42:53.646779 CH=1, VrefRange= 0, VrefLevel = 0
2712 13:42:53.653120 TX Bit0 (986~1001) 16 993, Bit8 (976~990) 15 983,
2713 13:42:53.656355 TX Bit1 (985~1000) 16 992, Bit9 (977~987) 11 982,
2714 13:42:53.662797 TX Bit2 (984~998) 15 991, Bit10 (978~992) 15 985,
2715 13:42:53.665916 TX Bit3 (981~996) 16 988, Bit11 (980~991) 12 985,
2716 13:42:53.669177 TX Bit4 (985~999) 15 992, Bit12 (978~991) 14 984,
2717 13:42:53.676019 TX Bit5 (987~1001) 15 994, Bit13 (980~992) 13 986,
2718 13:42:53.679207 TX Bit6 (985~1000) 16 992, Bit14 (979~991) 13 985,
2719 13:42:53.685865 TX Bit7 (985~999) 15 992, Bit15 (975~983) 9 979,
2720 13:42:53.685953
2721 13:42:53.686019 Write Rank0 MR14 =0x2
2722 13:42:53.695694
2723 13:42:53.695782 CH=1, VrefRange= 0, VrefLevel = 2
2724 13:42:53.701991 TX Bit0 (986~1002) 17 994, Bit8 (976~990) 15 983,
2725 13:42:53.705450 TX Bit1 (985~1001) 17 993, Bit9 (976~988) 13 982,
2726 13:42:53.711742 TX Bit2 (984~999) 16 991, Bit10 (977~992) 16 984,
2727 13:42:53.715367 TX Bit3 (980~997) 18 988, Bit11 (979~991) 13 985,
2728 13:42:53.718588 TX Bit4 (984~1000) 17 992, Bit12 (978~991) 14 984,
2729 13:42:53.725031 TX Bit5 (986~1001) 16 993, Bit13 (979~993) 15 986,
2730 13:42:53.728292 TX Bit6 (985~1000) 16 992, Bit14 (978~991) 14 984,
2731 13:42:53.734721 TX Bit7 (985~1000) 16 992, Bit15 (975~984) 10 979,
2732 13:42:53.734809
2733 13:42:53.734876 Write Rank0 MR14 =0x4
2734 13:42:53.745281
2735 13:42:53.745365 CH=1, VrefRange= 0, VrefLevel = 4
2736 13:42:53.751926 TX Bit0 (986~1003) 18 994, Bit8 (975~990) 16 982,
2737 13:42:53.755050 TX Bit1 (984~1002) 19 993, Bit9 (975~989) 15 982,
2738 13:42:53.761384 TX Bit2 (983~999) 17 991, Bit10 (977~992) 16 984,
2739 13:42:53.764525 TX Bit3 (980~998) 19 989, Bit11 (979~992) 14 985,
2740 13:42:53.771210 TX Bit4 (984~1001) 18 992, Bit12 (977~992) 16 984,
2741 13:42:53.774526 TX Bit5 (986~1002) 17 994, Bit13 (979~994) 16 986,
2742 13:42:53.777678 TX Bit6 (985~1001) 17 993, Bit14 (978~991) 14 984,
2743 13:42:53.784178 TX Bit7 (985~1001) 17 993, Bit15 (974~985) 12 979,
2744 13:42:53.784263
2745 13:42:53.784330 Write Rank0 MR14 =0x6
2746 13:42:53.794844
2747 13:42:53.794946 CH=1, VrefRange= 0, VrefLevel = 6
2748 13:42:53.801175 TX Bit0 (986~1004) 19 995, Bit8 (976~991) 16 983,
2749 13:42:53.804791 TX Bit1 (984~1003) 20 993, Bit9 (975~990) 16 982,
2750 13:42:53.811376 TX Bit2 (983~1000) 18 991, Bit10 (977~993) 17 985,
2751 13:42:53.814597 TX Bit3 (980~998) 19 989, Bit11 (978~992) 15 985,
2752 13:42:53.820931 TX Bit4 (984~1002) 19 993, Bit12 (978~992) 15 985,
2753 13:42:53.824162 TX Bit5 (985~1004) 20 994, Bit13 (979~994) 16 986,
2754 13:42:53.827636 TX Bit6 (985~1002) 18 993, Bit14 (978~992) 15 985,
2755 13:42:53.834138 TX Bit7 (985~1001) 17 993, Bit15 (974~986) 13 980,
2756 13:42:53.834228
2757 13:42:53.834294 Write Rank0 MR14 =0x8
2758 13:42:53.844760
2759 13:42:53.844845 CH=1, VrefRange= 0, VrefLevel = 8
2760 13:42:53.851292 TX Bit0 (985~1005) 21 995, Bit8 (975~991) 17 983,
2761 13:42:53.854531 TX Bit1 (984~1004) 21 994, Bit9 (975~990) 16 982,
2762 13:42:53.861162 TX Bit2 (983~1000) 18 991, Bit10 (977~994) 18 985,
2763 13:42:53.864320 TX Bit3 (979~998) 20 988, Bit11 (978~993) 16 985,
2764 13:42:53.870900 TX Bit4 (984~1002) 19 993, Bit12 (977~993) 17 985,
2765 13:42:53.874018 TX Bit5 (985~1004) 20 994, Bit13 (978~995) 18 986,
2766 13:42:53.877342 TX Bit6 (985~1002) 18 993, Bit14 (977~993) 17 985,
2767 13:42:53.884148 TX Bit7 (985~1002) 18 993, Bit15 (972~987) 16 979,
2768 13:42:53.884241
2769 13:42:53.884308 Write Rank0 MR14 =0xa
2770 13:42:53.894531
2771 13:42:53.897883 CH=1, VrefRange= 0, VrefLevel = 10
2772 13:42:53.901108 TX Bit0 (985~1005) 21 995, Bit8 (975~992) 18 983,
2773 13:42:53.904538 TX Bit1 (985~1005) 21 995, Bit9 (975~990) 16 982,
2774 13:42:53.911061 TX Bit2 (983~1001) 19 992, Bit10 (977~994) 18 985,
2775 13:42:53.914373 TX Bit3 (979~998) 20 988, Bit11 (978~993) 16 985,
2776 13:42:53.920753 TX Bit4 (984~1003) 20 993, Bit12 (977~994) 18 985,
2777 13:42:53.923890 TX Bit5 (985~1005) 21 995, Bit13 (978~995) 18 986,
2778 13:42:53.927490 TX Bit6 (985~1003) 19 994, Bit14 (977~993) 17 985,
2779 13:42:53.933724 TX Bit7 (984~1003) 20 993, Bit15 (972~988) 17 980,
2780 13:42:53.933812
2781 13:42:53.933879 Write Rank0 MR14 =0xc
2782 13:42:53.944922
2783 13:42:53.948138 CH=1, VrefRange= 0, VrefLevel = 12
2784 13:42:53.951266 TX Bit0 (985~1005) 21 995, Bit8 (975~992) 18 983,
2785 13:42:53.954474 TX Bit1 (984~1005) 22 994, Bit9 (974~991) 18 982,
2786 13:42:53.961184 TX Bit2 (982~1002) 21 992, Bit10 (976~995) 20 985,
2787 13:42:53.964645 TX Bit3 (979~999) 21 989, Bit11 (978~994) 17 986,
2788 13:42:53.970769 TX Bit4 (983~1004) 22 993, Bit12 (977~995) 19 986,
2789 13:42:53.974118 TX Bit5 (985~1005) 21 995, Bit13 (978~997) 20 987,
2790 13:42:53.977674 TX Bit6 (984~1004) 21 994, Bit14 (977~994) 18 985,
2791 13:42:53.983964 TX Bit7 (984~1003) 20 993, Bit15 (970~989) 20 979,
2792 13:42:53.984050
2793 13:42:53.984117 Write Rank0 MR14 =0xe
2794 13:42:53.994728
2795 13:42:53.998016 CH=1, VrefRange= 0, VrefLevel = 14
2796 13:42:54.001525 TX Bit0 (985~1006) 22 995, Bit8 (975~992) 18 983,
2797 13:42:54.004836 TX Bit1 (984~1005) 22 994, Bit9 (974~991) 18 982,
2798 13:42:54.011311 TX Bit2 (982~1002) 21 992, Bit10 (976~996) 21 986,
2799 13:42:54.014543 TX Bit3 (978~999) 22 988, Bit11 (977~995) 19 986,
2800 13:42:54.021196 TX Bit4 (983~1005) 23 994, Bit12 (977~996) 20 986,
2801 13:42:54.024456 TX Bit5 (985~1006) 22 995, Bit13 (978~997) 20 987,
2802 13:42:54.027466 TX Bit6 (984~1005) 22 994, Bit14 (977~995) 19 986,
2803 13:42:54.034271 TX Bit7 (984~1004) 21 994, Bit15 (971~990) 20 980,
2804 13:42:54.034357
2805 13:42:54.034424 Write Rank0 MR14 =0x10
2806 13:42:54.045192
2807 13:42:54.048398 CH=1, VrefRange= 0, VrefLevel = 16
2808 13:42:54.051632 TX Bit0 (985~1006) 22 995, Bit8 (974~993) 20 983,
2809 13:42:54.055112 TX Bit1 (984~1005) 22 994, Bit9 (973~991) 19 982,
2810 13:42:54.061733 TX Bit2 (981~1003) 23 992, Bit10 (976~997) 22 986,
2811 13:42:54.064795 TX Bit3 (978~1000) 23 989, Bit11 (977~996) 20 986,
2812 13:42:54.071403 TX Bit4 (983~1005) 23 994, Bit12 (977~997) 21 987,
2813 13:42:54.074502 TX Bit5 (985~1006) 22 995, Bit13 (977~997) 21 987,
2814 13:42:54.077627 TX Bit6 (984~1005) 22 994, Bit14 (976~995) 20 985,
2815 13:42:54.084366 TX Bit7 (984~1005) 22 994, Bit15 (970~990) 21 980,
2816 13:42:54.084452
2817 13:42:54.087635 Write Rank0 MR14 =0x12
2818 13:42:54.095431
2819 13:42:54.099063 CH=1, VrefRange= 0, VrefLevel = 18
2820 13:42:54.101937 TX Bit0 (985~1006) 22 995, Bit8 (973~994) 22 983,
2821 13:42:54.105593 TX Bit1 (983~1006) 24 994, Bit9 (973~992) 20 982,
2822 13:42:54.111906 TX Bit2 (981~1004) 24 992, Bit10 (976~997) 22 986,
2823 13:42:54.115323 TX Bit3 (978~1000) 23 989, Bit11 (977~997) 21 987,
2824 13:42:54.121688 TX Bit4 (983~1005) 23 994, Bit12 (976~997) 22 986,
2825 13:42:54.125133 TX Bit5 (984~1006) 23 995, Bit13 (977~998) 22 987,
2826 13:42:54.128154 TX Bit6 (984~1005) 22 994, Bit14 (976~996) 21 986,
2827 13:42:54.134672 TX Bit7 (984~1005) 22 994, Bit15 (971~991) 21 981,
2828 13:42:54.134757
2829 13:42:54.138022 Write Rank0 MR14 =0x14
2830 13:42:54.146082
2831 13:42:54.149286 CH=1, VrefRange= 0, VrefLevel = 20
2832 13:42:54.152363 TX Bit0 (984~1006) 23 995, Bit8 (973~995) 23 984,
2833 13:42:54.155589 TX Bit1 (983~1006) 24 994, Bit9 (972~992) 21 982,
2834 13:42:54.162241 TX Bit2 (980~1004) 25 992, Bit10 (975~998) 24 986,
2835 13:42:54.165888 TX Bit3 (978~1000) 23 989, Bit11 (977~998) 22 987,
2836 13:42:54.172282 TX Bit4 (982~1006) 25 994, Bit12 (976~998) 23 987,
2837 13:42:54.175418 TX Bit5 (984~1006) 23 995, Bit13 (977~998) 22 987,
2838 13:42:54.178866 TX Bit6 (984~1006) 23 995, Bit14 (976~997) 22 986,
2839 13:42:54.185017 TX Bit7 (983~1005) 23 994, Bit15 (970~991) 22 980,
2840 13:42:54.185103
2841 13:42:54.188576 Write Rank0 MR14 =0x16
2842 13:42:54.196279
2843 13:42:54.199833 CH=1, VrefRange= 0, VrefLevel = 22
2844 13:42:54.203043 TX Bit0 (984~1007) 24 995, Bit8 (972~995) 24 983,
2845 13:42:54.206247 TX Bit1 (983~1006) 24 994, Bit9 (972~992) 21 982,
2846 13:42:54.212586 TX Bit2 (980~1005) 26 992, Bit10 (975~998) 24 986,
2847 13:42:54.216265 TX Bit3 (978~1001) 24 989, Bit11 (976~998) 23 987,
2848 13:42:54.222724 TX Bit4 (982~1006) 25 994, Bit12 (976~998) 23 987,
2849 13:42:54.225965 TX Bit5 (984~1006) 23 995, Bit13 (977~998) 22 987,
2850 13:42:54.229069 TX Bit6 (984~1006) 23 995, Bit14 (976~998) 23 987,
2851 13:42:54.235460 TX Bit7 (983~1005) 23 994, Bit15 (970~991) 22 980,
2852 13:42:54.235547
2853 13:42:54.238715 Write Rank0 MR14 =0x18
2854 13:42:54.247174
2855 13:42:54.250246 CH=1, VrefRange= 0, VrefLevel = 24
2856 13:42:54.253463 TX Bit0 (984~1007) 24 995, Bit8 (972~996) 25 984,
2857 13:42:54.256890 TX Bit1 (982~1006) 25 994, Bit9 (972~993) 22 982,
2858 13:42:54.263315 TX Bit2 (980~1005) 26 992, Bit10 (975~998) 24 986,
2859 13:42:54.266569 TX Bit3 (978~1002) 25 990, Bit11 (976~998) 23 987,
2860 13:42:54.272978 TX Bit4 (982~1006) 25 994, Bit12 (976~998) 23 987,
2861 13:42:54.276334 TX Bit5 (984~1006) 23 995, Bit13 (977~999) 23 988,
2862 13:42:54.279736 TX Bit6 (983~1006) 24 994, Bit14 (975~998) 24 986,
2863 13:42:54.286367 TX Bit7 (983~1006) 24 994, Bit15 (970~991) 22 980,
2864 13:42:54.286482
2865 13:42:54.289584 Write Rank0 MR14 =0x1a
2866 13:42:54.297602
2867 13:42:54.300730 CH=1, VrefRange= 0, VrefLevel = 26
2868 13:42:54.304227 TX Bit0 (984~1007) 24 995, Bit8 (972~997) 26 984,
2869 13:42:54.307344 TX Bit1 (982~1006) 25 994, Bit9 (971~994) 24 982,
2870 13:42:54.313991 TX Bit2 (980~1005) 26 992, Bit10 (975~998) 24 986,
2871 13:42:54.317135 TX Bit3 (977~1002) 26 989, Bit11 (976~999) 24 987,
2872 13:42:54.323948 TX Bit4 (981~1006) 26 993, Bit12 (975~998) 24 986,
2873 13:42:54.327023 TX Bit5 (984~1007) 24 995, Bit13 (976~999) 24 987,
2874 13:42:54.330124 TX Bit6 (983~1006) 24 994, Bit14 (976~998) 23 987,
2875 13:42:54.336878 TX Bit7 (982~1006) 25 994, Bit15 (969~991) 23 980,
2876 13:42:54.336990
2877 13:42:54.339977 Write Rank0 MR14 =0x1c
2878 13:42:54.347991
2879 13:42:54.351096 CH=1, VrefRange= 0, VrefLevel = 28
2880 13:42:54.354669 TX Bit0 (984~1007) 24 995, Bit8 (972~997) 26 984,
2881 13:42:54.357849 TX Bit1 (982~1007) 26 994, Bit9 (971~994) 24 982,
2882 13:42:54.364226 TX Bit2 (979~1006) 28 992, Bit10 (975~998) 24 986,
2883 13:42:54.367649 TX Bit3 (977~1003) 27 990, Bit11 (976~999) 24 987,
2884 13:42:54.374134 TX Bit4 (982~1006) 25 994, Bit12 (975~998) 24 986,
2885 13:42:54.377422 TX Bit5 (983~1007) 25 995, Bit13 (976~999) 24 987,
2886 13:42:54.380582 TX Bit6 (983~1006) 24 994, Bit14 (975~998) 24 986,
2887 13:42:54.387132 TX Bit7 (982~1006) 25 994, Bit15 (969~992) 24 980,
2888 13:42:54.387240
2889 13:42:54.390489 Write Rank0 MR14 =0x1e
2890 13:42:54.398514
2891 13:42:54.401896 CH=1, VrefRange= 0, VrefLevel = 30
2892 13:42:54.405190 TX Bit0 (984~1008) 25 996, Bit8 (971~996) 26 983,
2893 13:42:54.408640 TX Bit1 (981~1007) 27 994, Bit9 (971~994) 24 982,
2894 13:42:54.415019 TX Bit2 (979~1006) 28 992, Bit10 (974~998) 25 986,
2895 13:42:54.418262 TX Bit3 (977~1003) 27 990, Bit11 (976~999) 24 987,
2896 13:42:54.424741 TX Bit4 (983~1006) 24 994, Bit12 (975~998) 24 986,
2897 13:42:54.428041 TX Bit5 (983~1007) 25 995, Bit13 (976~999) 24 987,
2898 13:42:54.431276 TX Bit6 (983~1007) 25 995, Bit14 (975~999) 25 987,
2899 13:42:54.438109 TX Bit7 (982~1006) 25 994, Bit15 (969~992) 24 980,
2900 13:42:54.438194
2901 13:42:54.441237 Write Rank0 MR14 =0x20
2902 13:42:54.449217
2903 13:42:54.452767 CH=1, VrefRange= 0, VrefLevel = 32
2904 13:42:54.455863 TX Bit0 (984~1008) 25 996, Bit8 (971~996) 26 983,
2905 13:42:54.459037 TX Bit1 (981~1007) 27 994, Bit9 (971~994) 24 982,
2906 13:42:54.465795 TX Bit2 (979~1006) 28 992, Bit10 (974~998) 25 986,
2907 13:42:54.469059 TX Bit3 (977~1003) 27 990, Bit11 (976~999) 24 987,
2908 13:42:54.475625 TX Bit4 (983~1006) 24 994, Bit12 (975~998) 24 986,
2909 13:42:54.478871 TX Bit5 (983~1007) 25 995, Bit13 (976~999) 24 987,
2910 13:42:54.481843 TX Bit6 (983~1007) 25 995, Bit14 (975~999) 25 987,
2911 13:42:54.488676 TX Bit7 (982~1006) 25 994, Bit15 (969~992) 24 980,
2912 13:42:54.488760
2913 13:42:54.491481 Write Rank0 MR14 =0x22
2914 13:42:54.499740
2915 13:42:54.503033 CH=1, VrefRange= 0, VrefLevel = 34
2916 13:42:54.506391 TX Bit0 (984~1008) 25 996, Bit8 (971~996) 26 983,
2917 13:42:54.509543 TX Bit1 (981~1007) 27 994, Bit9 (971~994) 24 982,
2918 13:42:54.516235 TX Bit2 (979~1006) 28 992, Bit10 (974~998) 25 986,
2919 13:42:54.519550 TX Bit3 (977~1003) 27 990, Bit11 (976~999) 24 987,
2920 13:42:54.526033 TX Bit4 (983~1006) 24 994, Bit12 (975~998) 24 986,
2921 13:42:54.529236 TX Bit5 (983~1007) 25 995, Bit13 (976~999) 24 987,
2922 13:42:54.532506 TX Bit6 (983~1007) 25 995, Bit14 (975~999) 25 987,
2923 13:42:54.539144 TX Bit7 (982~1006) 25 994, Bit15 (969~992) 24 980,
2924 13:42:54.539235
2925 13:42:54.542291 Write Rank0 MR14 =0x24
2926 13:42:54.550212
2927 13:42:54.553704 CH=1, VrefRange= 0, VrefLevel = 36
2928 13:42:54.556855 TX Bit0 (984~1008) 25 996, Bit8 (971~996) 26 983,
2929 13:42:54.560012 TX Bit1 (981~1007) 27 994, Bit9 (971~994) 24 982,
2930 13:42:54.566773 TX Bit2 (979~1006) 28 992, Bit10 (974~998) 25 986,
2931 13:42:54.570091 TX Bit3 (977~1003) 27 990, Bit11 (976~999) 24 987,
2932 13:42:54.576466 TX Bit4 (983~1006) 24 994, Bit12 (975~998) 24 986,
2933 13:42:54.579640 TX Bit5 (983~1007) 25 995, Bit13 (976~999) 24 987,
2934 13:42:54.583106 TX Bit6 (983~1007) 25 995, Bit14 (975~999) 25 987,
2935 13:42:54.589671 TX Bit7 (982~1006) 25 994, Bit15 (969~992) 24 980,
2936 13:42:54.589756
2937 13:42:54.592803 Write Rank0 MR14 =0x26
2938 13:42:54.600863
2939 13:42:54.603974 CH=1, VrefRange= 0, VrefLevel = 38
2940 13:42:54.607744 TX Bit0 (984~1008) 25 996, Bit8 (971~996) 26 983,
2941 13:42:54.610807 TX Bit1 (981~1007) 27 994, Bit9 (971~994) 24 982,
2942 13:42:54.617374 TX Bit2 (979~1006) 28 992, Bit10 (974~998) 25 986,
2943 13:42:54.620575 TX Bit3 (977~1003) 27 990, Bit11 (976~999) 24 987,
2944 13:42:54.627114 TX Bit4 (983~1006) 24 994, Bit12 (975~998) 24 986,
2945 13:42:54.630299 TX Bit5 (983~1007) 25 995, Bit13 (976~999) 24 987,
2946 13:42:54.633635 TX Bit6 (983~1007) 25 995, Bit14 (975~999) 25 987,
2947 13:42:54.640231 TX Bit7 (982~1006) 25 994, Bit15 (969~992) 24 980,
2948 13:42:54.640317
2949 13:42:54.640383
2950 13:42:54.643251 TX Vref found, early break! 375< 381
2951 13:42:54.646916 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
2952 13:42:54.650066 u1DelayCellOfst[0]=7 cells (6 PI)
2953 13:42:54.653333 u1DelayCellOfst[1]=5 cells (4 PI)
2954 13:42:54.656562 u1DelayCellOfst[2]=2 cells (2 PI)
2955 13:42:54.659632 u1DelayCellOfst[3]=0 cells (0 PI)
2956 13:42:54.663006 u1DelayCellOfst[4]=5 cells (4 PI)
2957 13:42:54.666249 u1DelayCellOfst[5]=6 cells (5 PI)
2958 13:42:54.669771 u1DelayCellOfst[6]=6 cells (5 PI)
2959 13:42:54.673001 u1DelayCellOfst[7]=5 cells (4 PI)
2960 13:42:54.676081 Byte0, DQ PI dly=990, DQM PI dly= 993
2961 13:42:54.679609 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 30)
2962 13:42:54.679694
2963 13:42:54.682741 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 30)
2964 13:42:54.685953
2965 13:42:54.686037 u1DelayCellOfst[8]=3 cells (3 PI)
2966 13:42:54.689513 u1DelayCellOfst[9]=2 cells (2 PI)
2967 13:42:54.692494 u1DelayCellOfst[10]=7 cells (6 PI)
2968 13:42:54.695940 u1DelayCellOfst[11]=9 cells (7 PI)
2969 13:42:54.698964 u1DelayCellOfst[12]=7 cells (6 PI)
2970 13:42:54.702388 u1DelayCellOfst[13]=9 cells (7 PI)
2971 13:42:54.705539 u1DelayCellOfst[14]=9 cells (7 PI)
2972 13:42:54.709049 u1DelayCellOfst[15]=0 cells (0 PI)
2973 13:42:54.712363 Byte1, DQ PI dly=980, DQM PI dly= 983
2974 13:42:54.715471 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
2975 13:42:54.715557
2976 13:42:54.722159 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
2977 13:42:54.722245
2978 13:42:54.722311 Write Rank0 MR14 =0x1e
2979 13:42:54.722373
2980 13:42:54.725264 Final TX Range 0 Vref 30
2981 13:42:54.725349
2982 13:42:54.731988 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2983 13:42:54.732074
2984 13:42:54.738314 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2985 13:42:54.744960 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2986 13:42:54.754873 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2987 13:42:54.754959 Write Rank0 MR3 =0xb0
2988 13:42:54.757993 DramC Write-DBI on
2989 13:42:54.758078 ==
2990 13:42:54.761192 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2991 13:42:54.764409 fsp= 1, odt_onoff= 1, Byte mode= 0
2992 13:42:54.764494 ==
2993 13:42:54.771193 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2994 13:42:54.771278
2995 13:42:54.771343 Begin, DQ Scan Range 703~767
2996 13:42:54.771404
2997 13:42:54.774426
2998 13:42:54.774510 TX Vref Scan disable
2999 13:42:54.777691 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3000 13:42:54.781217 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3001 13:42:54.784416 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3002 13:42:54.787542 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3003 13:42:54.790685 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3004 13:42:54.797308 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3005 13:42:54.800617 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3006 13:42:54.803980 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3007 13:42:54.807128 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3008 13:42:54.810512 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3009 13:42:54.813821 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3010 13:42:54.816799 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3011 13:42:54.820105 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3012 13:42:54.823685 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3013 13:42:54.826807 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3014 13:42:54.830102 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3015 13:42:54.833359 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3016 13:42:54.836492 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3017 13:42:54.839647 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3018 13:42:54.843235 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3019 13:42:54.849692 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
3020 13:42:54.852819 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
3021 13:42:54.856268 725 |2 6 21|[0] xxxxxxxx oooooooo [MSB]
3022 13:42:54.862621 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3023 13:42:54.866058 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3024 13:42:54.869260 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3025 13:42:54.872401 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3026 13:42:54.875741 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3027 13:42:54.879253 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3028 13:42:54.882562 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3029 13:42:54.885673 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3030 13:42:54.888780 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3031 13:42:54.892339 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
3032 13:42:54.895441 752 |2 6 48|[0] xxxxxxxx xxxxxxxx [MSB]
3033 13:42:54.898679 Byte0, DQ PI dly=738, DQM PI dly= 738
3034 13:42:54.905288 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 34)
3035 13:42:54.905374
3036 13:42:54.908523 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 34)
3037 13:42:54.908610
3038 13:42:54.911862 Byte1, DQ PI dly=728, DQM PI dly= 728
3039 13:42:54.918475 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 24)
3040 13:42:54.918561
3041 13:42:54.921669 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 24)
3042 13:42:54.921755
3043 13:42:54.928319 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3044 13:42:54.934861 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3045 13:42:54.941343 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3046 13:42:54.944449 Write Rank0 MR3 =0x30
3047 13:42:54.944534 DramC Write-DBI off
3048 13:42:54.944601
3049 13:42:54.948032 [DATLAT]
3050 13:42:54.951141 Freq=1600, CH1 RK0, use_rxtx_scan=0
3051 13:42:54.951226
3052 13:42:54.951291 DATLAT Default: 0xf
3053 13:42:54.954470 7, 0xFFFF, sum=0
3054 13:42:54.954556 8, 0xFFFF, sum=0
3055 13:42:54.957522 9, 0xFFFF, sum=0
3056 13:42:54.957608 10, 0xFFFF, sum=0
3057 13:42:54.961050 11, 0xFFFF, sum=0
3058 13:42:54.961138 12, 0xFFFF, sum=0
3059 13:42:54.964123 13, 0xFFFF, sum=0
3060 13:42:54.964209 14, 0x0, sum=1
3061 13:42:54.964276 15, 0x0, sum=2
3062 13:42:54.967309 16, 0x0, sum=3
3063 13:42:54.967395 17, 0x0, sum=4
3064 13:42:54.973918 pattern=2 first_step=14 total pass=5 best_step=16
3065 13:42:54.974002 ==
3066 13:42:54.977161 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3067 13:42:54.980819 fsp= 1, odt_onoff= 1, Byte mode= 0
3068 13:42:54.980905 ==
3069 13:42:54.987259 Start DQ dly to find pass range UseTestEngine =1
3070 13:42:54.990430 x-axis: bit #, y-axis: DQ dly (-127~63)
3071 13:42:54.990516 RX Vref Scan = 1
3072 13:42:55.098411
3073 13:42:55.098521 RX Vref found, early break!
3074 13:42:55.098586
3075 13:42:55.104970 Final RX Vref 11, apply to both rank0 and 1
3076 13:42:55.105054 ==
3077 13:42:55.108192 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3078 13:42:55.111240 fsp= 1, odt_onoff= 1, Byte mode= 0
3079 13:42:55.111338 ==
3080 13:42:55.114789 DQS Delay:
3081 13:42:55.114871 DQS0 = 0, DQS1 = 0
3082 13:42:55.114973 DQM Delay:
3083 13:42:55.117830 DQM0 = 20, DQM1 = 18
3084 13:42:55.117915 DQ Delay:
3085 13:42:55.121289 DQ0 =21, DQ1 =21, DQ2 =18, DQ3 =15
3086 13:42:55.124565 DQ4 =20, DQ5 =23, DQ6 =22, DQ7 =20
3087 13:42:55.127530 DQ8 =17, DQ9 =15, DQ10 =19, DQ11 =20
3088 13:42:55.131016 DQ12 =20, DQ13 =21, DQ14 =21, DQ15 =12
3089 13:42:55.131101
3090 13:42:55.131166
3091 13:42:55.131226
3092 13:42:55.134306 [DramC_TX_OE_Calibration] TA2
3093 13:42:55.137667 Original DQ_B0 (3 6) =30, OEN = 27
3094 13:42:55.140913 Original DQ_B1 (3 6) =30, OEN = 27
3095 13:42:55.143991 23, 0x0, End_B0=23 End_B1=23
3096 13:42:55.147365 24, 0x0, End_B0=24 End_B1=24
3097 13:42:55.147485 25, 0x0, End_B0=25 End_B1=25
3098 13:42:55.150548 26, 0x0, End_B0=26 End_B1=26
3099 13:42:55.153729 27, 0x0, End_B0=27 End_B1=27
3100 13:42:55.157335 28, 0x0, End_B0=28 End_B1=28
3101 13:42:55.160551 29, 0x0, End_B0=29 End_B1=29
3102 13:42:55.160638 30, 0x0, End_B0=30 End_B1=30
3103 13:42:55.163629 31, 0xFFFF, End_B0=30 End_B1=30
3104 13:42:55.170421 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3105 13:42:55.176844 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3106 13:42:55.176930
3107 13:42:55.176995
3108 13:42:55.177056 Write Rank0 MR23 =0x3f
3109 13:42:55.180254 [DQSOSC]
3110 13:42:55.186905 [DQSOSCAuto] RK0, (LSB)MR18= 0xb8b8, (MSB)MR19= 0x202, tDQSOscB0 = 452 ps tDQSOscB1 = 452 ps
3111 13:42:55.193183 CH1_RK0: MR19=0x202, MR18=0xB8B8, DQSOSC=452, MR23=63, INC=12, DEC=18
3112 13:42:55.196297 Write Rank0 MR23 =0x3f
3113 13:42:55.196382 [DQSOSC]
3114 13:42:55.203029 [DQSOSCAuto] RK0, (LSB)MR18= 0xb7b7, (MSB)MR19= 0x202, tDQSOscB0 = 453 ps tDQSOscB1 = 453 ps
3115 13:42:55.206251 CH1 RK0: MR19=202, MR18=B7B7
3116 13:42:55.209677 [RankSwap] Rank num 2, (Multi 1), Rank 1
3117 13:42:55.212832 Write Rank0 MR2 =0xad
3118 13:42:55.212917 [Write Leveling]
3119 13:42:55.215974 delay byte0 byte1 byte2 byte3
3120 13:42:55.216059
3121 13:42:55.219190 10 0 0
3122 13:42:55.219276 11 0 0
3123 13:42:55.222319 12 0 0
3124 13:42:55.222405 13 0 0
3125 13:42:55.222472 14 0 0
3126 13:42:55.225910 15 0 0
3127 13:42:55.225996 16 0 0
3128 13:42:55.229114 17 0 0
3129 13:42:55.229201 18 0 0
3130 13:42:55.232371 19 0 0
3131 13:42:55.232457 20 0 0
3132 13:42:55.232525 21 0 0
3133 13:42:55.235676 22 0 0
3134 13:42:55.235763 23 0 0
3135 13:42:55.238709 24 0 0
3136 13:42:55.238796 25 0 0
3137 13:42:55.238863 26 0 0
3138 13:42:55.242329 27 0 0
3139 13:42:55.242415 28 0 ff
3140 13:42:55.245361 29 0 ff
3141 13:42:55.245448 30 0 ff
3142 13:42:55.248564 31 0 ff
3143 13:42:55.248651 32 0 ff
3144 13:42:55.252007 33 0 ff
3145 13:42:55.252093 34 0 ff
3146 13:42:55.252161 35 ff ff
3147 13:42:55.255016 36 ff ff
3148 13:42:55.255101 37 ff ff
3149 13:42:55.258518 38 ff ff
3150 13:42:55.258610 39 ff ff
3151 13:42:55.261674 40 ff ff
3152 13:42:55.261760 41 ff ff
3153 13:42:55.268388 pass bytecount = 0xff (0xff: all bytes pass)
3154 13:42:55.268474
3155 13:42:55.268541 DQS0 dly: 35
3156 13:42:55.268605 DQS1 dly: 28
3157 13:42:55.271690 Write Rank0 MR2 =0x2d
3158 13:42:55.274739 [RankSwap] Rank num 2, (Multi 1), Rank 0
3159 13:42:55.277973 Write Rank1 MR1 =0xd6
3160 13:42:55.278059 [Gating]
3161 13:42:55.278125 ==
3162 13:42:55.284779 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3163 13:42:55.287888 fsp= 1, odt_onoff= 1, Byte mode= 0
3164 13:42:55.287973 ==
3165 13:42:55.291078 3 1 0 |2c2b 3636 |(11 11)(0 0) |(1 1)(1 1)| 0
3166 13:42:55.294654 3 1 4 |2c2b 3535 |(11 11)(11 11) |(1 1)(0 0)| 0
3167 13:42:55.297840 3 1 8 |2c2b 3535 |(11 11)(0 0) |(1 1)(1 1)| 0
3168 13:42:55.304405 3 1 12 |2c2b 2322 |(11 11)(1 1) |(0 0)(1 1)| 0
3169 13:42:55.307680 3 1 16 |2c2b 3635 |(11 11)(11 11) |(1 0)(0 0)| 0
3170 13:42:55.310848 3 1 20 |2c2b 100 |(11 11)(11 11) |(1 0)(1 1)| 0
3171 13:42:55.317253 3 1 24 |2c2b 1818 |(11 11)(11 11) |(1 0)(1 1)| 0
3172 13:42:55.320755 3 1 28 |2c2b 3433 |(11 11)(11 11) |(1 0)(1 1)| 0
3173 13:42:55.323850 [Byte 1] Lead/lag falling Transition (3, 1, 28)
3174 13:42:55.330695 3 2 0 |2c2b 3535 |(11 11)(11 11) |(1 0)(0 1)| 0
3175 13:42:55.333876 3 2 4 |2c2b 3131 |(11 11)(10 10) |(1 0)(0 1)| 0
3176 13:42:55.336875 3 2 8 |2c2b 3333 |(11 11)(11 11) |(1 0)(0 1)| 0
3177 13:42:55.343472 3 2 12 |2c2b 100 |(11 11)(11 11) |(1 0)(0 1)| 0
3178 13:42:55.346907 3 2 16 |2c2b 100f |(11 11)(11 11) |(0 0)(0 1)| 0
3179 13:42:55.350216 3 2 20 |201 3434 |(11 11)(11 11) |(0 0)(0 1)| 0
3180 13:42:55.356837 [Byte 1] Lead/lag Transition tap number (7)
3181 13:42:55.359969 3 2 24 |3534 1515 |(11 11)(11 11) |(0 0)(0 0)| 0
3182 13:42:55.363179 3 2 28 |3534 3d3c |(11 11)(11 11) |(0 0)(1 1)| 0
3183 13:42:55.369862 3 3 0 |3534 3939 |(11 11)(11 11) |(0 0)(0 0)| 0
3184 13:42:55.373154 3 3 4 |3534 3939 |(11 11)(0 0) |(0 0)(1 1)| 0
3185 13:42:55.376278 3 3 8 |3534 3b3b |(11 11)(11 11) |(0 0)(1 1)| 0
3186 13:42:55.379410 3 3 12 |3534 908 |(11 11)(11 11) |(0 0)(1 1)| 0
3187 13:42:55.386028 3 3 16 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
3188 13:42:55.389298 3 3 20 |3534 3b3a |(11 11)(11 11) |(1 1)(1 1)| 0
3189 13:42:55.392600 3 3 24 |3534 3a3a |(11 11)(11 11) |(1 1)(1 1)| 0
3190 13:42:55.398996 [Byte 0] Lead/lag falling Transition (3, 3, 24)
3191 13:42:55.402523 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
3192 13:42:55.405543 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
3193 13:42:55.412277 [Byte 1] Lead/lag falling Transition (3, 4, 0)
3194 13:42:55.415385 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3195 13:42:55.419045 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3196 13:42:55.425337 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3197 13:42:55.428709 3 4 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3198 13:42:55.431842 3 4 20 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3199 13:42:55.438556 3 4 24 |3d3d 706 |(11 11)(11 11) |(1 1)(1 1)| 0
3200 13:42:55.441645 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3201 13:42:55.444996 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3202 13:42:55.451382 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3203 13:42:55.454682 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3204 13:42:55.457843 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3205 13:42:55.464453 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3206 13:42:55.467991 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3207 13:42:55.471259 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3208 13:42:55.477786 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3209 13:42:55.481002 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3210 13:42:55.484168 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3211 13:42:55.490533 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3212 13:42:55.494029 [Byte 0] Lead/lag falling Transition (3, 6, 8)
3213 13:42:55.497441 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3214 13:42:55.500395 [Byte 0] Lead/lag Transition tap number (2)
3215 13:42:55.507219 3 6 16 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3216 13:42:55.510207 [Byte 1] Lead/lag falling Transition (3, 6, 16)
3217 13:42:55.513505 3 6 20 |403 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3218 13:42:55.520173 3 6 24 |4646 605 |(0 0)(11 11) |(0 0)(1 0)| 0
3219 13:42:55.520281 [Byte 0]First pass (3, 6, 24)
3220 13:42:55.526962 [Byte 1] Lead/lag Transition tap number (3)
3221 13:42:55.529920 3 6 28 |4646 3e3e |(0 0)(11 11) |(0 0)(0 0)| 0
3222 13:42:55.533477 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3223 13:42:55.536761 [Byte 1]First pass (3, 7, 0)
3224 13:42:55.539991 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3225 13:42:55.543131 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3226 13:42:55.546327 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3227 13:42:55.552936 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3228 13:42:55.556321 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3229 13:42:55.559524 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3230 13:42:55.562542 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3231 13:42:55.569225 4 0 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3232 13:42:55.572857 All bytes gating window > 1UI, Early break!
3233 13:42:55.572942
3234 13:42:55.575671 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 12)
3235 13:42:55.575756
3236 13:42:55.579204 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 22)
3237 13:42:55.579289
3238 13:42:55.579355
3239 13:42:55.579416
3240 13:42:55.582491 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
3241 13:42:55.585625
3242 13:42:55.588897 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 22)
3243 13:42:55.589011
3244 13:42:55.589124
3245 13:42:55.589216 Write Rank1 MR1 =0x56
3246 13:42:55.589304
3247 13:42:55.592146 best RODT dly(2T, 0.5T) = (2, 3)
3248 13:42:55.592246
3249 13:42:55.595646 best RODT dly(2T, 0.5T) = (2, 3)
3250 13:42:55.595748 ==
3251 13:42:55.602253 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3252 13:42:55.605409 fsp= 1, odt_onoff= 1, Byte mode= 0
3253 13:42:55.605493 ==
3254 13:42:55.608621 Start DQ dly to find pass range UseTestEngine =0
3255 13:42:55.611813 x-axis: bit #, y-axis: DQ dly (-127~63)
3256 13:42:55.615270 RX Vref Scan = 0
3257 13:42:55.618596 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3258 13:42:55.621804 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3259 13:42:55.625042 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3260 13:42:55.625137 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3261 13:42:55.628426 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3262 13:42:55.631607 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3263 13:42:55.634769 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3264 13:42:55.638316 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3265 13:42:55.641557 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3266 13:42:55.645090 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3267 13:42:55.647748 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3268 13:42:55.651066 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3269 13:42:55.651151 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3270 13:42:55.654561 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3271 13:42:55.657574 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3272 13:42:55.660935 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3273 13:42:55.664412 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3274 13:42:55.667608 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3275 13:42:55.671006 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3276 13:42:55.674184 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3277 13:42:55.677274 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3278 13:42:55.677360 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3279 13:42:55.680843 -4, [0] xxxxxxxx xxxxxxxo [MSB]
3280 13:42:55.684055 -3, [0] xxxxxxxx xxxxxxxo [MSB]
3281 13:42:55.687219 -2, [0] xxxoxxxx xoxxxxxo [MSB]
3282 13:42:55.690478 -1, [0] xxxoxxxx ooxxxxxo [MSB]
3283 13:42:55.693668 0, [0] xxxoxxxx ooxxxxxo [MSB]
3284 13:42:55.697189 1, [0] xxxoxxxx ooxxxxxo [MSB]
3285 13:42:55.697302 2, [0] xxooxxxx ooxxoxxo [MSB]
3286 13:42:55.700443 3, [0] xxooxxxo oooxoxxo [MSB]
3287 13:42:55.703415 4, [0] oooooxxo oooooooo [MSB]
3288 13:42:55.706869 32, [0] oooooooo ooooooox [MSB]
3289 13:42:55.710023 33, [0] oooooooo ooooooox [MSB]
3290 13:42:55.713641 34, [0] oooooooo oxooooox [MSB]
3291 13:42:55.716656 35, [0] ooxxoooo oxooooox [MSB]
3292 13:42:55.716742 36, [0] ooxxoooo xxooooox [MSB]
3293 13:42:55.719830 37, [0] ooxxoooo xxooooox [MSB]
3294 13:42:55.723365 38, [0] ooxxoooo xxooooox [MSB]
3295 13:42:55.726514 39, [0] oxxxooox xxooooox [MSB]
3296 13:42:55.729901 40, [0] oxxxooox xxxxooox [MSB]
3297 13:42:55.733087 41, [0] oxxxxoxx xxxxxoox [MSB]
3298 13:42:55.736419 42, [0] xxxxxoxx xxxxxxxx [MSB]
3299 13:42:55.739642 43, [0] xxxxxxxx xxxxxxxx [MSB]
3300 13:42:55.743102 iDelay=43, Bit 0, Center 22 (4 ~ 41) 38
3301 13:42:55.746316 iDelay=43, Bit 1, Center 21 (4 ~ 38) 35
3302 13:42:55.749303 iDelay=43, Bit 2, Center 18 (2 ~ 34) 33
3303 13:42:55.752565 iDelay=43, Bit 3, Center 16 (-2 ~ 34) 37
3304 13:42:55.756026 iDelay=43, Bit 4, Center 22 (4 ~ 40) 37
3305 13:42:55.759265 iDelay=43, Bit 5, Center 23 (5 ~ 42) 38
3306 13:42:55.762736 iDelay=43, Bit 6, Center 22 (5 ~ 40) 36
3307 13:42:55.765666 iDelay=43, Bit 7, Center 20 (3 ~ 38) 36
3308 13:42:55.769044 iDelay=43, Bit 8, Center 17 (-1 ~ 35) 37
3309 13:42:55.772352 iDelay=43, Bit 9, Center 15 (-2 ~ 33) 36
3310 13:42:55.779076 iDelay=43, Bit 10, Center 21 (3 ~ 39) 37
3311 13:42:55.782028 iDelay=43, Bit 11, Center 21 (4 ~ 39) 36
3312 13:42:55.785515 iDelay=43, Bit 12, Center 21 (2 ~ 40) 39
3313 13:42:55.788609 iDelay=43, Bit 13, Center 22 (4 ~ 41) 38
3314 13:42:55.791937 iDelay=43, Bit 14, Center 22 (4 ~ 41) 38
3315 13:42:55.795408 iDelay=43, Bit 15, Center 13 (-4 ~ 31) 36
3316 13:42:55.795509 ==
3317 13:42:55.801870 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3318 13:42:55.805030 fsp= 1, odt_onoff= 1, Byte mode= 0
3319 13:42:55.805107 ==
3320 13:42:55.805169 DQS Delay:
3321 13:42:55.808399 DQS0 = 0, DQS1 = 0
3322 13:42:55.808476 DQM Delay:
3323 13:42:55.808539 DQM0 = 20, DQM1 = 19
3324 13:42:55.811823 DQ Delay:
3325 13:42:55.815051 DQ0 =22, DQ1 =21, DQ2 =18, DQ3 =16
3326 13:42:55.818189 DQ4 =22, DQ5 =23, DQ6 =22, DQ7 =20
3327 13:42:55.821649 DQ8 =17, DQ9 =15, DQ10 =21, DQ11 =21
3328 13:42:55.824674 DQ12 =21, DQ13 =22, DQ14 =22, DQ15 =13
3329 13:42:55.824779
3330 13:42:55.824849
3331 13:42:55.824913 DramC Write-DBI off
3332 13:42:55.824970 ==
3333 13:42:55.831086 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3334 13:42:55.834587 fsp= 1, odt_onoff= 1, Byte mode= 0
3335 13:42:55.834661 ==
3336 13:42:55.838002 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3337 13:42:55.838073
3338 13:42:55.841308 Begin, DQ Scan Range 924~1180
3339 13:42:55.841391
3340 13:42:55.841455
3341 13:42:55.844247 TX Vref Scan disable
3342 13:42:55.847830 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
3343 13:42:55.851030 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
3344 13:42:55.854239 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
3345 13:42:55.857379 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
3346 13:42:55.860751 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3347 13:42:55.863927 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3348 13:42:55.867370 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3349 13:42:55.873799 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3350 13:42:55.876956 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3351 13:42:55.880425 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3352 13:42:55.883640 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3353 13:42:55.886871 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3354 13:42:55.890247 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3355 13:42:55.893479 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3356 13:42:55.896815 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3357 13:42:55.900257 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3358 13:42:55.903260 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3359 13:42:55.906469 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3360 13:42:55.909980 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3361 13:42:55.913161 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3362 13:42:55.919574 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3363 13:42:55.922774 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3364 13:42:55.926189 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3365 13:42:55.929667 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3366 13:42:55.932804 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3367 13:42:55.936062 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3368 13:42:55.939270 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3369 13:42:55.942634 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3370 13:42:55.945935 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3371 13:42:55.949211 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3372 13:42:55.952275 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3373 13:42:55.955850 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3374 13:42:55.962331 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3375 13:42:55.965398 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3376 13:42:55.969449 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3377 13:42:55.971912 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3378 13:42:55.975213 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3379 13:42:55.978501 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3380 13:42:55.981682 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3381 13:42:55.984914 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3382 13:42:55.988423 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3383 13:42:55.991588 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3384 13:42:55.994773 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3385 13:42:55.998030 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3386 13:42:56.001347 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3387 13:42:56.004587 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3388 13:42:56.008206 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3389 13:42:56.011350 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3390 13:42:56.017984 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
3391 13:42:56.020835 973 |3 6 13|[0] xxxxxxxx xxxxxxxo [MSB]
3392 13:42:56.024111 974 |3 6 14|[0] xxxxxxxx xxxxxxxo [MSB]
3393 13:42:56.027642 975 |3 6 15|[0] xxxxxxxx ooxxxxxo [MSB]
3394 13:42:56.031082 976 |3 6 16|[0] xxxxxxxx oooxxxoo [MSB]
3395 13:42:56.034206 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
3396 13:42:56.037279 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
3397 13:42:56.040567 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB]
3398 13:42:56.044104 980 |3 6 20|[0] xxxxxxxx oooooooo [MSB]
3399 13:42:56.047225 981 |3 6 21|[0] xxxxxxxx oooooooo [MSB]
3400 13:42:56.050598 982 |3 6 22|[0] xxxxxxxx oooooooo [MSB]
3401 13:42:56.053932 983 |3 6 23|[0] xooooxoo oooooooo [MSB]
3402 13:42:56.061230 991 |3 6 31|[0] oooooooo ooooooox [MSB]
3403 13:42:56.064364 992 |3 6 32|[0] oooooooo oxooooox [MSB]
3404 13:42:56.067867 993 |3 6 33|[0] oooooooo xxooooox [MSB]
3405 13:42:56.071128 994 |3 6 34|[0] oooooooo xxooooox [MSB]
3406 13:42:56.074574 995 |3 6 35|[0] oooooooo xxooooox [MSB]
3407 13:42:56.077368 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
3408 13:42:56.080656 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
3409 13:42:56.084134 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
3410 13:42:56.087497 999 |3 6 39|[0] oooxoooo xxxxxxxx [MSB]
3411 13:42:56.090785 1000 |3 6 40|[0] oooxoooo xxxxxxxx [MSB]
3412 13:42:56.093823 1001 |3 6 41|[0] oooxoooo xxxxxxxx [MSB]
3413 13:42:56.100224 1002 |3 6 42|[0] oooxoooo xxxxxxxx [MSB]
3414 13:42:56.103737 1003 |3 6 43|[0] ooxxoooo xxxxxxxx [MSB]
3415 13:42:56.106894 1004 |3 6 44|[0] ooxxooox xxxxxxxx [MSB]
3416 13:42:56.110196 1005 |3 6 45|[0] ooxxooox xxxxxxxx [MSB]
3417 13:42:56.113445 1006 |3 6 46|[0] xxxxxxxx xxxxxxxx [MSB]
3418 13:42:56.116585 Byte0, DQ PI dly=992, DQM PI dly= 992
3419 13:42:56.120189 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 32)
3420 13:42:56.120306
3421 13:42:56.126596 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 32)
3422 13:42:56.126717
3423 13:42:56.129905 Byte1, DQ PI dly=983, DQM PI dly= 983
3424 13:42:56.133285 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
3425 13:42:56.133406
3426 13:42:56.136307 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
3427 13:42:56.136427
3428 13:42:56.139750 ==
3429 13:42:56.142923 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3430 13:42:56.146136 fsp= 1, odt_onoff= 1, Byte mode= 0
3431 13:42:56.146255 ==
3432 13:42:56.149646 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3433 13:42:56.149761
3434 13:42:56.152712 Begin, DQ Scan Range 959~1023
3435 13:42:56.156066 Write Rank1 MR14 =0x0
3436 13:42:56.164457
3437 13:42:56.164574 CH=1, VrefRange= 0, VrefLevel = 0
3438 13:42:56.170915 TX Bit0 (985~1002) 18 993, Bit8 (978~988) 11 983,
3439 13:42:56.174428 TX Bit1 (985~999) 15 992, Bit9 (977~987) 11 982,
3440 13:42:56.180750 TX Bit2 (983~998) 16 990, Bit10 (978~992) 15 985,
3441 13:42:56.184217 TX Bit3 (980~992) 13 986, Bit11 (979~992) 14 985,
3442 13:42:56.187481 TX Bit4 (984~999) 16 991, Bit12 (980~991) 12 985,
3443 13:42:56.193873 TX Bit5 (985~1001) 17 993, Bit13 (980~993) 14 986,
3444 13:42:56.197058 TX Bit6 (985~999) 15 992, Bit14 (978~991) 14 984,
3445 13:42:56.203546 TX Bit7 (985~998) 14 991, Bit15 (974~984) 11 979,
3446 13:42:56.203668
3447 13:42:56.203775 Write Rank1 MR14 =0x2
3448 13:42:56.213528
3449 13:42:56.213656 CH=1, VrefRange= 0, VrefLevel = 2
3450 13:42:56.219977 TX Bit0 (985~1003) 19 994, Bit8 (977~990) 14 983,
3451 13:42:56.223167 TX Bit1 (984~1000) 17 992, Bit9 (976~988) 13 982,
3452 13:42:56.229885 TX Bit2 (983~998) 16 990, Bit10 (978~992) 15 985,
3453 13:42:56.232986 TX Bit3 (980~995) 16 987, Bit11 (978~992) 15 985,
3454 13:42:56.236454 TX Bit4 (984~1000) 17 992, Bit12 (980~991) 12 985,
3455 13:42:56.243231 TX Bit5 (985~1002) 18 993, Bit13 (979~993) 15 986,
3456 13:42:56.246248 TX Bit6 (985~1000) 16 992, Bit14 (978~991) 14 984,
3457 13:42:56.252861 TX Bit7 (985~998) 14 991, Bit15 (974~985) 12 979,
3458 13:42:56.252953
3459 13:42:56.253020 Write Rank1 MR14 =0x4
3460 13:42:56.262895
3461 13:42:56.262980 CH=1, VrefRange= 0, VrefLevel = 4
3462 13:42:56.269496 TX Bit0 (985~1003) 19 994, Bit8 (977~990) 14 983,
3463 13:42:56.272916 TX Bit1 (984~1001) 18 992, Bit9 (976~989) 14 982,
3464 13:42:56.279258 TX Bit2 (983~999) 17 991, Bit10 (977~993) 17 985,
3465 13:42:56.282513 TX Bit3 (980~995) 16 987, Bit11 (978~993) 16 985,
3466 13:42:56.285640 TX Bit4 (984~1001) 18 992, Bit12 (979~992) 14 985,
3467 13:42:56.292208 TX Bit5 (985~1003) 19 994, Bit13 (979~994) 16 986,
3468 13:42:56.295565 TX Bit6 (984~1001) 18 992, Bit14 (978~992) 15 985,
3469 13:42:56.302404 TX Bit7 (985~999) 15 992, Bit15 (973~985) 13 979,
3470 13:42:56.302491
3471 13:42:56.302568 Write Rank1 MR14 =0x6
3472 13:42:56.312582
3473 13:42:56.312705 CH=1, VrefRange= 0, VrefLevel = 6
3474 13:42:56.318970 TX Bit0 (985~1004) 20 994, Bit8 (977~990) 14 983,
3475 13:42:56.322358 TX Bit1 (984~1001) 18 992, Bit9 (976~990) 15 983,
3476 13:42:56.328936 TX Bit2 (982~999) 18 990, Bit10 (977~994) 18 985,
3477 13:42:56.332156 TX Bit3 (979~996) 18 987, Bit11 (978~994) 17 986,
3478 13:42:56.335246 TX Bit4 (983~1002) 20 992, Bit12 (978~992) 15 985,
3479 13:42:56.341815 TX Bit5 (985~1003) 19 994, Bit13 (979~995) 17 987,
3480 13:42:56.345081 TX Bit6 (984~1001) 18 992, Bit14 (977~992) 16 984,
3481 13:42:56.351521 TX Bit7 (984~999) 16 991, Bit15 (973~987) 15 980,
3482 13:42:56.351615
3483 13:42:56.351682 Write Rank1 MR14 =0x8
3484 13:42:56.362108
3485 13:42:56.362193 CH=1, VrefRange= 0, VrefLevel = 8
3486 13:42:56.368664 TX Bit0 (984~1004) 21 994, Bit8 (976~991) 16 983,
3487 13:42:56.371763 TX Bit1 (984~1002) 19 993, Bit9 (975~990) 16 982,
3488 13:42:56.378302 TX Bit2 (982~1000) 19 991, Bit10 (977~994) 18 985,
3489 13:42:56.381572 TX Bit3 (979~997) 19 988, Bit11 (978~994) 17 986,
3490 13:42:56.388338 TX Bit4 (984~1002) 19 993, Bit12 (978~993) 16 985,
3491 13:42:56.391533 TX Bit5 (984~1004) 21 994, Bit13 (978~996) 19 987,
3492 13:42:56.394681 TX Bit6 (984~1002) 19 993, Bit14 (977~993) 17 985,
3493 13:42:56.401312 TX Bit7 (984~1000) 17 992, Bit15 (972~988) 17 980,
3494 13:42:56.401400
3495 13:42:56.401465 Write Rank1 MR14 =0xa
3496 13:42:56.411879
3497 13:42:56.415188 CH=1, VrefRange= 0, VrefLevel = 10
3498 13:42:56.418350 TX Bit0 (985~1005) 21 995, Bit8 (976~991) 16 983,
3499 13:42:56.421679 TX Bit1 (984~1003) 20 993, Bit9 (975~991) 17 983,
3500 13:42:56.428310 TX Bit2 (982~1000) 19 991, Bit10 (976~995) 20 985,
3501 13:42:56.431290 TX Bit3 (979~997) 19 988, Bit11 (978~995) 18 986,
3502 13:42:56.437877 TX Bit4 (983~1003) 21 993, Bit12 (978~994) 17 986,
3503 13:42:56.441426 TX Bit5 (985~1005) 21 995, Bit13 (978~997) 20 987,
3504 13:42:56.444466 TX Bit6 (984~1003) 20 993, Bit14 (977~994) 18 985,
3505 13:42:56.451093 TX Bit7 (984~1001) 18 992, Bit15 (972~989) 18 980,
3506 13:42:56.451179
3507 13:42:56.451245 Write Rank1 MR14 =0xc
3508 13:42:56.461838
3509 13:42:56.465068 CH=1, VrefRange= 0, VrefLevel = 12
3510 13:42:56.468278 TX Bit0 (984~1005) 22 994, Bit8 (976~991) 16 983,
3511 13:42:56.471641 TX Bit1 (983~1004) 22 993, Bit9 (974~991) 18 982,
3512 13:42:56.478202 TX Bit2 (981~1001) 21 991, Bit10 (976~996) 21 986,
3513 13:42:56.481320 TX Bit3 (978~998) 21 988, Bit11 (977~996) 20 986,
3514 13:42:56.488040 TX Bit4 (983~1004) 22 993, Bit12 (977~994) 18 985,
3515 13:42:56.491183 TX Bit5 (985~1005) 21 995, Bit13 (978~997) 20 987,
3516 13:42:56.494415 TX Bit6 (983~1004) 22 993, Bit14 (977~995) 19 986,
3517 13:42:56.501072 TX Bit7 (984~1002) 19 993, Bit15 (971~990) 20 980,
3518 13:42:56.501158
3519 13:42:56.501223 Write Rank1 MR14 =0xe
3520 13:42:56.511895
3521 13:42:56.515052 CH=1, VrefRange= 0, VrefLevel = 14
3522 13:42:56.518235 TX Bit0 (984~1005) 22 994, Bit8 (976~992) 17 984,
3523 13:42:56.521547 TX Bit1 (984~1004) 21 994, Bit9 (975~991) 17 983,
3524 13:42:56.528218 TX Bit2 (981~1001) 21 991, Bit10 (976~997) 22 986,
3525 13:42:56.531514 TX Bit3 (978~998) 21 988, Bit11 (977~997) 21 987,
3526 13:42:56.537991 TX Bit4 (983~1005) 23 994, Bit12 (978~995) 18 986,
3527 13:42:56.541289 TX Bit5 (984~1005) 22 994, Bit13 (977~997) 21 987,
3528 13:42:56.544419 TX Bit6 (983~1005) 23 994, Bit14 (977~995) 19 986,
3529 13:42:56.551015 TX Bit7 (984~1002) 19 993, Bit15 (971~990) 20 980,
3530 13:42:56.551100
3531 13:42:56.551167 Write Rank1 MR14 =0x10
3532 13:42:56.562044
3533 13:42:56.565421 CH=1, VrefRange= 0, VrefLevel = 16
3534 13:42:56.568390 TX Bit0 (984~1006) 23 995, Bit8 (976~992) 17 984,
3535 13:42:56.571917 TX Bit1 (983~1004) 22 993, Bit9 (974~991) 18 982,
3536 13:42:56.578424 TX Bit2 (980~1002) 23 991, Bit10 (976~997) 22 986,
3537 13:42:56.581672 TX Bit3 (978~998) 21 988, Bit11 (977~998) 22 987,
3538 13:42:56.588268 TX Bit4 (982~1005) 24 993, Bit12 (977~996) 20 986,
3539 13:42:56.591368 TX Bit5 (984~1005) 22 994, Bit13 (977~998) 22 987,
3540 13:42:56.594574 TX Bit6 (983~1005) 23 994, Bit14 (976~996) 21 986,
3541 13:42:56.601426 TX Bit7 (983~1003) 21 993, Bit15 (971~991) 21 981,
3542 13:42:56.601508
3543 13:42:56.601574 Write Rank1 MR14 =0x12
3544 13:42:56.612165
3545 13:42:56.615341 CH=1, VrefRange= 0, VrefLevel = 18
3546 13:42:56.618596 TX Bit0 (984~1006) 23 995, Bit8 (975~993) 19 984,
3547 13:42:56.621806 TX Bit1 (983~1005) 23 994, Bit9 (974~992) 19 983,
3548 13:42:56.628469 TX Bit2 (980~1002) 23 991, Bit10 (976~998) 23 987,
3549 13:42:56.631797 TX Bit3 (978~999) 22 988, Bit11 (976~998) 23 987,
3550 13:42:56.638253 TX Bit4 (982~1005) 24 993, Bit12 (977~997) 21 987,
3551 13:42:56.641622 TX Bit5 (984~1005) 22 994, Bit13 (977~998) 22 987,
3552 13:42:56.644676 TX Bit6 (983~1005) 23 994, Bit14 (976~997) 22 986,
3553 13:42:56.651506 TX Bit7 (983~1004) 22 993, Bit15 (970~991) 22 980,
3554 13:42:56.651593
3555 13:42:56.651669 Write Rank1 MR14 =0x14
3556 13:42:56.662315
3557 13:42:56.665519 CH=1, VrefRange= 0, VrefLevel = 20
3558 13:42:56.668684 TX Bit0 (984~1006) 23 995, Bit8 (975~993) 19 984,
3559 13:42:56.672045 TX Bit1 (982~1005) 24 993, Bit9 (973~992) 20 982,
3560 13:42:56.678805 TX Bit2 (979~1003) 25 991, Bit10 (975~998) 24 986,
3561 13:42:56.681908 TX Bit3 (978~999) 22 988, Bit11 (976~998) 23 987,
3562 13:42:56.688393 TX Bit4 (982~1005) 24 993, Bit12 (977~997) 21 987,
3563 13:42:56.691581 TX Bit5 (983~1006) 24 994, Bit13 (977~999) 23 988,
3564 13:42:56.694984 TX Bit6 (982~1005) 24 993, Bit14 (976~997) 22 986,
3565 13:42:56.701434 TX Bit7 (982~1004) 23 993, Bit15 (970~991) 22 980,
3566 13:42:56.701530
3567 13:42:56.701596 Write Rank1 MR14 =0x16
3568 13:42:56.712516
3569 13:42:56.715885 CH=1, VrefRange= 0, VrefLevel = 22
3570 13:42:56.719104 TX Bit0 (983~1006) 24 994, Bit8 (974~994) 21 984,
3571 13:42:56.722193 TX Bit1 (982~1006) 25 994, Bit9 (973~992) 20 982,
3572 13:42:56.728883 TX Bit2 (979~1004) 26 991, Bit10 (975~998) 24 986,
3573 13:42:56.732041 TX Bit3 (978~1000) 23 989, Bit11 (976~999) 24 987,
3574 13:42:56.738524 TX Bit4 (981~1005) 25 993, Bit12 (976~998) 23 987,
3575 13:42:56.742046 TX Bit5 (983~1006) 24 994, Bit13 (977~999) 23 988,
3576 13:42:56.745353 TX Bit6 (982~1006) 25 994, Bit14 (975~998) 24 986,
3577 13:42:56.751756 TX Bit7 (982~1005) 24 993, Bit15 (970~991) 22 980,
3578 13:42:56.751842
3579 13:42:56.754943 wait MRW command Rank1 MR14 =0x18 fired (1)
3580 13:42:56.758519 Write Rank1 MR14 =0x18
3581 13:42:56.766625
3582 13:42:56.769965 CH=1, VrefRange= 0, VrefLevel = 24
3583 13:42:56.773096 TX Bit0 (983~1006) 24 994, Bit8 (974~995) 22 984,
3584 13:42:56.776622 TX Bit1 (983~1006) 24 994, Bit9 (972~993) 22 982,
3585 13:42:56.783210 TX Bit2 (979~1005) 27 992, Bit10 (975~999) 25 987,
3586 13:42:56.786369 TX Bit3 (977~1000) 24 988, Bit11 (976~999) 24 987,
3587 13:42:56.792760 TX Bit4 (981~1006) 26 993, Bit12 (976~998) 23 987,
3588 13:42:56.795929 TX Bit5 (983~1006) 24 994, Bit13 (977~999) 23 988,
3589 13:42:56.799405 TX Bit6 (982~1006) 25 994, Bit14 (975~998) 24 986,
3590 13:42:56.805829 TX Bit7 (982~1005) 24 993, Bit15 (969~992) 24 980,
3591 13:42:56.805915
3592 13:42:56.808882 Write Rank1 MR14 =0x1a
3593 13:42:56.817055
3594 13:42:56.820393 CH=1, VrefRange= 0, VrefLevel = 26
3595 13:42:56.823665 TX Bit0 (983~1007) 25 995, Bit8 (973~996) 24 984,
3596 13:42:56.827231 TX Bit1 (982~1006) 25 994, Bit9 (972~994) 23 983,
3597 13:42:56.833630 TX Bit2 (978~1005) 28 991, Bit10 (975~998) 24 986,
3598 13:42:56.836852 TX Bit3 (977~1001) 25 989, Bit11 (976~999) 24 987,
3599 13:42:56.843422 TX Bit4 (981~1006) 26 993, Bit12 (976~998) 23 987,
3600 13:42:56.846645 TX Bit5 (982~1006) 25 994, Bit13 (976~999) 24 987,
3601 13:42:56.849702 TX Bit6 (981~1006) 26 993, Bit14 (975~998) 24 986,
3602 13:42:56.856426 TX Bit7 (982~1006) 25 994, Bit15 (969~992) 24 980,
3603 13:42:56.856511
3604 13:42:56.859630 Write Rank1 MR14 =0x1c
3605 13:42:56.867666
3606 13:42:56.871031 CH=1, VrefRange= 0, VrefLevel = 28
3607 13:42:56.874234 TX Bit0 (982~1007) 26 994, Bit8 (974~997) 24 985,
3608 13:42:56.877397 TX Bit1 (981~1006) 26 993, Bit9 (972~994) 23 983,
3609 13:42:56.884070 TX Bit2 (979~1005) 27 992, Bit10 (975~999) 25 987,
3610 13:42:56.887352 TX Bit3 (977~1002) 26 989, Bit11 (975~999) 25 987,
3611 13:42:56.893878 TX Bit4 (980~1006) 27 993, Bit12 (976~998) 23 987,
3612 13:42:56.897052 TX Bit5 (982~1006) 25 994, Bit13 (976~999) 24 987,
3613 13:42:56.900166 TX Bit6 (981~1006) 26 993, Bit14 (976~999) 24 987,
3614 13:42:56.906930 TX Bit7 (982~1006) 25 994, Bit15 (969~992) 24 980,
3615 13:42:56.907016
3616 13:42:56.910060 Write Rank1 MR14 =0x1e
3617 13:42:56.917910
3618 13:42:56.921159 CH=1, VrefRange= 0, VrefLevel = 30
3619 13:42:56.924785 TX Bit0 (982~1007) 26 994, Bit8 (972~996) 25 984,
3620 13:42:56.927756 TX Bit1 (981~1006) 26 993, Bit9 (971~994) 24 982,
3621 13:42:56.934460 TX Bit2 (978~1005) 28 991, Bit10 (976~998) 23 987,
3622 13:42:56.937651 TX Bit3 (977~1001) 25 989, Bit11 (975~999) 25 987,
3623 13:42:56.944250 TX Bit4 (980~1006) 27 993, Bit12 (975~999) 25 987,
3624 13:42:56.947370 TX Bit5 (982~1007) 26 994, Bit13 (976~999) 24 987,
3625 13:42:56.950998 TX Bit6 (981~1006) 26 993, Bit14 (975~999) 25 987,
3626 13:42:56.957243 TX Bit7 (980~1006) 27 993, Bit15 (969~992) 24 980,
3627 13:42:56.957328
3628 13:42:56.960391 Write Rank1 MR14 =0x20
3629 13:42:56.968494
3630 13:42:56.971682 CH=1, VrefRange= 0, VrefLevel = 32
3631 13:42:56.975151 TX Bit0 (982~1007) 26 994, Bit8 (972~996) 25 984,
3632 13:42:56.978222 TX Bit1 (981~1006) 26 993, Bit9 (971~994) 24 982,
3633 13:42:56.984658 TX Bit2 (978~1005) 28 991, Bit10 (976~998) 23 987,
3634 13:42:56.987996 TX Bit3 (977~1001) 25 989, Bit11 (975~999) 25 987,
3635 13:42:56.994679 TX Bit4 (980~1006) 27 993, Bit12 (975~999) 25 987,
3636 13:42:56.997996 TX Bit5 (982~1007) 26 994, Bit13 (976~999) 24 987,
3637 13:42:57.001154 TX Bit6 (981~1006) 26 993, Bit14 (975~999) 25 987,
3638 13:42:57.007556 TX Bit7 (980~1006) 27 993, Bit15 (969~992) 24 980,
3639 13:42:57.007662
3640 13:42:57.010970 Write Rank1 MR14 =0x22
3641 13:42:57.018793
3642 13:42:57.022173 CH=1, VrefRange= 0, VrefLevel = 34
3643 13:42:57.025571 TX Bit0 (982~1007) 26 994, Bit8 (972~996) 25 984,
3644 13:42:57.028846 TX Bit1 (981~1006) 26 993, Bit9 (971~994) 24 982,
3645 13:42:57.035384 TX Bit2 (978~1005) 28 991, Bit10 (976~998) 23 987,
3646 13:42:57.038462 TX Bit3 (977~1001) 25 989, Bit11 (975~999) 25 987,
3647 13:42:57.045211 TX Bit4 (980~1006) 27 993, Bit12 (975~999) 25 987,
3648 13:42:57.048640 TX Bit5 (982~1007) 26 994, Bit13 (976~999) 24 987,
3649 13:42:57.051894 TX Bit6 (981~1006) 26 993, Bit14 (975~999) 25 987,
3650 13:42:57.058075 TX Bit7 (980~1006) 27 993, Bit15 (969~992) 24 980,
3651 13:42:57.058160
3652 13:42:57.061406 Write Rank1 MR14 =0x24
3653 13:42:57.069370
3654 13:42:57.072757 CH=1, VrefRange= 0, VrefLevel = 36
3655 13:42:57.076023 TX Bit0 (982~1007) 26 994, Bit8 (972~996) 25 984,
3656 13:42:57.079170 TX Bit1 (981~1006) 26 993, Bit9 (971~994) 24 982,
3657 13:42:57.085790 TX Bit2 (978~1005) 28 991, Bit10 (976~998) 23 987,
3658 13:42:57.088997 TX Bit3 (977~1001) 25 989, Bit11 (975~999) 25 987,
3659 13:42:57.095631 TX Bit4 (980~1006) 27 993, Bit12 (975~999) 25 987,
3660 13:42:57.098941 TX Bit5 (982~1007) 26 994, Bit13 (976~999) 24 987,
3661 13:42:57.102055 TX Bit6 (981~1006) 26 993, Bit14 (975~999) 25 987,
3662 13:42:57.108734 TX Bit7 (980~1006) 27 993, Bit15 (969~992) 24 980,
3663 13:42:57.108814
3664 13:42:57.108876
3665 13:42:57.112014 TX Vref found, early break! 383< 385
3666 13:42:57.115106 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
3667 13:42:57.118577 u1DelayCellOfst[0]=6 cells (5 PI)
3668 13:42:57.121826 u1DelayCellOfst[1]=5 cells (4 PI)
3669 13:42:57.125066 u1DelayCellOfst[2]=2 cells (2 PI)
3670 13:42:57.128598 u1DelayCellOfst[3]=0 cells (0 PI)
3671 13:42:57.131606 u1DelayCellOfst[4]=5 cells (4 PI)
3672 13:42:57.134910 u1DelayCellOfst[5]=6 cells (5 PI)
3673 13:42:57.138388 u1DelayCellOfst[6]=5 cells (4 PI)
3674 13:42:57.141627 u1DelayCellOfst[7]=5 cells (4 PI)
3675 13:42:57.144674 Byte0, DQ PI dly=989, DQM PI dly= 991
3676 13:42:57.148084 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 29)
3677 13:42:57.148169
3678 13:42:57.151381 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 29)
3679 13:42:57.154579
3680 13:42:57.154664 u1DelayCellOfst[8]=5 cells (4 PI)
3681 13:42:57.157958 u1DelayCellOfst[9]=2 cells (2 PI)
3682 13:42:57.161063 u1DelayCellOfst[10]=9 cells (7 PI)
3683 13:42:57.164370 u1DelayCellOfst[11]=9 cells (7 PI)
3684 13:42:57.167640 u1DelayCellOfst[12]=9 cells (7 PI)
3685 13:42:57.170745 u1DelayCellOfst[13]=9 cells (7 PI)
3686 13:42:57.174046 u1DelayCellOfst[14]=9 cells (7 PI)
3687 13:42:57.177365 u1DelayCellOfst[15]=0 cells (0 PI)
3688 13:42:57.180712 Byte1, DQ PI dly=980, DQM PI dly= 983
3689 13:42:57.183829 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
3690 13:42:57.183914
3691 13:42:57.190356 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
3692 13:42:57.190440
3693 13:42:57.190505 Write Rank1 MR14 =0x1e
3694 13:42:57.190565
3695 13:42:57.193938 Final TX Range 0 Vref 30
3696 13:42:57.194022
3697 13:42:57.200590 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3698 13:42:57.200674
3699 13:42:57.206741 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3700 13:42:57.213390 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3701 13:42:57.223182 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3702 13:42:57.223295 Write Rank1 MR3 =0xb0
3703 13:42:57.226428 DramC Write-DBI on
3704 13:42:57.226530 ==
3705 13:42:57.229630 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3706 13:42:57.232809 fsp= 1, odt_onoff= 1, Byte mode= 0
3707 13:42:57.232884 ==
3708 13:42:57.239567 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3709 13:42:57.239642
3710 13:42:57.239704 Begin, DQ Scan Range 703~767
3711 13:42:57.242795
3712 13:42:57.242865
3713 13:42:57.242922 TX Vref Scan disable
3714 13:42:57.245972 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3715 13:42:57.249132 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3716 13:42:57.252553 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3717 13:42:57.255599 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3718 13:42:57.259051 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3719 13:42:57.265726 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3720 13:42:57.268743 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3721 13:42:57.272227 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3722 13:42:57.275382 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3723 13:42:57.278584 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3724 13:42:57.282036 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3725 13:42:57.285417 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3726 13:42:57.288718 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3727 13:42:57.291891 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3728 13:42:57.295098 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3729 13:42:57.298636 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3730 13:42:57.301781 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3731 13:42:57.305065 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3732 13:42:57.308255 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3733 13:42:57.314942 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3734 13:42:57.317873 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
3735 13:42:57.321255 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
3736 13:42:57.327690 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3737 13:42:57.331324 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3738 13:42:57.334548 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3739 13:42:57.337693 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3740 13:42:57.340927 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3741 13:42:57.344083 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3742 13:42:57.347402 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3743 13:42:57.350758 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3744 13:42:57.354011 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3745 13:42:57.357267 751 |2 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
3746 13:42:57.360602 Byte0, DQ PI dly=737, DQM PI dly= 737
3747 13:42:57.367198 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 33)
3748 13:42:57.367278
3749 13:42:57.370475 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 33)
3750 13:42:57.370551
3751 13:42:57.373851 Byte1, DQ PI dly=728, DQM PI dly= 728
3752 13:42:57.377059 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 24)
3753 13:42:57.377132
3754 13:42:57.383389 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 24)
3755 13:42:57.383496
3756 13:42:57.390020 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3757 13:42:57.396621 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3758 13:42:57.403269 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3759 13:42:57.406523 Write Rank1 MR3 =0x30
3760 13:42:57.406627 DramC Write-DBI off
3761 13:42:57.406711
3762 13:42:57.409788 [DATLAT]
3763 13:42:57.412907 Freq=1600, CH1 RK1, use_rxtx_scan=0
3764 13:42:57.412991
3765 13:42:57.413057 DATLAT Default: 0x10
3766 13:42:57.416116 7, 0xFFFF, sum=0
3767 13:42:57.416201 8, 0xFFFF, sum=0
3768 13:42:57.419618 9, 0xFFFF, sum=0
3769 13:42:57.419704 10, 0xFFFF, sum=0
3770 13:42:57.422765 11, 0xFFFF, sum=0
3771 13:42:57.422850 12, 0xFFFF, sum=0
3772 13:42:57.426189 13, 0xFFFF, sum=0
3773 13:42:57.426274 14, 0x0, sum=1
3774 13:42:57.426342 15, 0x0, sum=2
3775 13:42:57.429356 16, 0x0, sum=3
3776 13:42:57.429441 17, 0x0, sum=4
3777 13:42:57.436002 pattern=2 first_step=14 total pass=5 best_step=16
3778 13:42:57.436087 ==
3779 13:42:57.439176 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3780 13:42:57.442611 fsp= 1, odt_onoff= 1, Byte mode= 0
3781 13:42:57.442701 ==
3782 13:42:57.448959 Start DQ dly to find pass range UseTestEngine =1
3783 13:42:57.452351 x-axis: bit #, y-axis: DQ dly (-127~63)
3784 13:42:57.452436 RX Vref Scan = 0
3785 13:42:57.455671 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3786 13:42:57.458629 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3787 13:42:57.461882 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3788 13:42:57.465498 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3789 13:42:57.468566 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3790 13:42:57.468653 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3791 13:42:57.472011 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3792 13:42:57.475088 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3793 13:42:57.478464 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3794 13:42:57.481652 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3795 13:42:57.484843 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3796 13:42:57.488392 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3797 13:42:57.491581 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3798 13:42:57.494747 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3799 13:42:57.497938 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3800 13:42:57.498025 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3801 13:42:57.501356 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3802 13:42:57.504581 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3803 13:42:57.507989 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3804 13:42:57.511333 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3805 13:42:57.514663 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3806 13:42:57.517762 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3807 13:42:57.521065 -4, [0] xxxxxxxx xxxxxxxo [MSB]
3808 13:42:57.521151 -3, [0] xxxxxxxx xoxxxxxo [MSB]
3809 13:42:57.524224 -2, [0] xxxoxxxx xoxxxxxo [MSB]
3810 13:42:57.527698 -1, [0] xxxoxxxx ooxxxxxo [MSB]
3811 13:42:57.530863 0, [0] xxxoxxxx ooxxxxxo [MSB]
3812 13:42:57.534037 1, [0] xxxoxxxx ooxxxxxo [MSB]
3813 13:42:57.537353 2, [0] xxxoxxxx oooxxxxo [MSB]
3814 13:42:57.540751 3, [0] xoooxxxo oooooxxo [MSB]
3815 13:42:57.540839 4, [0] oooooxxo oooooooo [MSB]
3816 13:42:57.543658 5, [0] oooooxxo oooooooo [MSB]
3817 13:42:57.548481 32, [0] oooooooo ooooooox [MSB]
3818 13:42:57.551588 33, [0] oooooooo ooooooox [MSB]
3819 13:42:57.555174 34, [0] oooxoooo oxooooox [MSB]
3820 13:42:57.558676 35, [0] ooxxoooo oxooooox [MSB]
3821 13:42:57.561667 36, [0] ooxxoooo xxooooox [MSB]
3822 13:42:57.564746 37, [0] ooxxoooo xxooooox [MSB]
3823 13:42:57.568129 38, [0] ooxxoooo xxooxoox [MSB]
3824 13:42:57.568216 39, [0] ooxxooox xxxxxoox [MSB]
3825 13:42:57.571317 40, [0] oxxxxoox xxxxxxox [MSB]
3826 13:42:57.574560 41, [0] xxxxxxxx xxxxxxxx [MSB]
3827 13:42:57.577733 iDelay=41, Bit 0, Center 22 (4 ~ 40) 37
3828 13:42:57.581024 iDelay=41, Bit 1, Center 21 (3 ~ 39) 37
3829 13:42:57.584548 iDelay=41, Bit 2, Center 18 (3 ~ 34) 32
3830 13:42:57.591199 iDelay=41, Bit 3, Center 15 (-2 ~ 33) 36
3831 13:42:57.594303 iDelay=41, Bit 4, Center 21 (4 ~ 39) 36
3832 13:42:57.597470 iDelay=41, Bit 5, Center 23 (6 ~ 40) 35
3833 13:42:57.600593 iDelay=41, Bit 6, Center 23 (6 ~ 40) 35
3834 13:42:57.604238 iDelay=41, Bit 7, Center 20 (3 ~ 38) 36
3835 13:42:57.607384 iDelay=41, Bit 8, Center 17 (-1 ~ 35) 37
3836 13:42:57.610769 iDelay=41, Bit 9, Center 15 (-3 ~ 33) 37
3837 13:42:57.613743 iDelay=41, Bit 10, Center 20 (2 ~ 38) 37
3838 13:42:57.617051 iDelay=41, Bit 11, Center 20 (3 ~ 38) 36
3839 13:42:57.620598 iDelay=41, Bit 12, Center 20 (3 ~ 37) 35
3840 13:42:57.623642 iDelay=41, Bit 13, Center 21 (4 ~ 39) 36
3841 13:42:57.630329 iDelay=41, Bit 14, Center 22 (4 ~ 40) 37
3842 13:42:57.633803 iDelay=41, Bit 15, Center 13 (-4 ~ 31) 36
3843 13:42:57.633888 ==
3844 13:42:57.636727 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3845 13:42:57.640247 fsp= 1, odt_onoff= 1, Byte mode= 0
3846 13:42:57.640333 ==
3847 13:42:57.643290 DQS Delay:
3848 13:42:57.643375 DQS0 = 0, DQS1 = 0
3849 13:42:57.646878 DQM Delay:
3850 13:42:57.646962 DQM0 = 20, DQM1 = 18
3851 13:42:57.647028 DQ Delay:
3852 13:42:57.649894 DQ0 =22, DQ1 =21, DQ2 =18, DQ3 =15
3853 13:42:57.653187 DQ4 =21, DQ5 =23, DQ6 =23, DQ7 =20
3854 13:42:57.656405 DQ8 =17, DQ9 =15, DQ10 =20, DQ11 =20
3855 13:42:57.659677 DQ12 =20, DQ13 =21, DQ14 =22, DQ15 =13
3856 13:42:57.659763
3857 13:42:57.659828
3858 13:42:57.659888
3859 13:42:57.662985 [DramC_TX_OE_Calibration] TA2
3860 13:42:57.666421 Original DQ_B0 (3 6) =30, OEN = 27
3861 13:42:57.669437 Original DQ_B1 (3 6) =30, OEN = 27
3862 13:42:57.672683 23, 0x0, End_B0=23 End_B1=23
3863 13:42:57.676037 24, 0x0, End_B0=24 End_B1=24
3864 13:42:57.679198 25, 0x0, End_B0=25 End_B1=25
3865 13:42:57.679285 26, 0x0, End_B0=26 End_B1=26
3866 13:42:57.682789 27, 0x0, End_B0=27 End_B1=27
3867 13:42:57.685996 28, 0x0, End_B0=28 End_B1=28
3868 13:42:57.689142 29, 0x0, End_B0=29 End_B1=29
3869 13:42:57.692335 30, 0x0, End_B0=30 End_B1=30
3870 13:42:57.692421 31, 0xFFFF, End_B0=30 End_B1=30
3871 13:42:57.699110 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3872 13:42:57.705578 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3873 13:42:57.705664
3874 13:42:57.705730
3875 13:42:57.705790 Write Rank1 MR23 =0x3f
3876 13:42:57.708943 [DQSOSC]
3877 13:42:57.715243 [DQSOSCAuto] RK1, (LSB)MR18= 0xb8b8, (MSB)MR19= 0x202, tDQSOscB0 = 452 ps tDQSOscB1 = 452 ps
3878 13:42:57.721942 CH1_RK1: MR19=0x202, MR18=0xB8B8, DQSOSC=452, MR23=63, INC=12, DEC=18
3879 13:42:57.725235 Write Rank1 MR23 =0x3f
3880 13:42:57.725320 [DQSOSC]
3881 13:42:57.731729 [DQSOSCAuto] RK1, (LSB)MR18= 0xb6b6, (MSB)MR19= 0x202, tDQSOscB0 = 453 ps tDQSOscB1 = 453 ps
3882 13:42:57.735109 CH1 RK1: MR19=202, MR18=B6B6
3883 13:42:57.738170 [RxdqsGatingPostProcess] freq 1600
3884 13:42:57.745000 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3885 13:42:57.745085 Rank: 0
3886 13:42:57.748068 best DQS0 dly(2T, 0.5T) = (2, 6)
3887 13:42:57.751277 best DQS1 dly(2T, 0.5T) = (2, 6)
3888 13:42:57.754594 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3889 13:42:57.758049 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3890 13:42:57.758133 Rank: 1
3891 13:42:57.761380 best DQS0 dly(2T, 0.5T) = (2, 6)
3892 13:42:57.764589 best DQS1 dly(2T, 0.5T) = (2, 6)
3893 13:42:57.767609 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3894 13:42:57.771060 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3895 13:42:57.774300 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3896 13:42:57.777692 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3897 13:42:57.784254 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3898 13:42:57.784340
3899 13:42:57.784405
3900 13:42:57.787294 [Calibration Summary] Freqency 1600
3901 13:42:57.787379 CH 0, Rank 0
3902 13:42:57.790924 All Pass.
3903 13:42:57.791008
3904 13:42:57.791073 CH 0, Rank 1
3905 13:42:57.791133 All Pass.
3906 13:42:57.791191
3907 13:42:57.794094 CH 1, Rank 0
3908 13:42:57.794179 All Pass.
3909 13:42:57.794245
3910 13:42:57.794305 CH 1, Rank 1
3911 13:42:57.797213 All Pass.
3912 13:42:57.797297
3913 13:42:57.803569 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3914 13:42:57.810466 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3915 13:42:57.816841 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3916 13:42:57.820302 Write Rank0 MR3 =0xb0
3917 13:42:57.826794 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3918 13:42:57.833348 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3919 13:42:57.839933 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3920 13:42:57.840018 Write Rank1 MR3 =0xb0
3921 13:42:57.846218 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3922 13:42:57.856392 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3923 13:42:57.862792 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3924 13:42:57.862877 Write Rank0 MR3 =0xb0
3925 13:42:57.869240 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3926 13:42:57.876018 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3927 13:42:57.885815 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3928 13:42:57.885901 Write Rank1 MR3 =0xb0
3929 13:42:57.888745 DramC Write-DBI on
3930 13:42:57.892322 [GetDramInforAfterCalByMRR] Vendor 6.
3931 13:42:57.895399 [GetDramInforAfterCalByMRR] Revision 505.
3932 13:42:57.895499 MR8 1111
3933 13:42:57.901963 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3934 13:42:57.902048 MR8 1111
3935 13:42:57.905476 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3936 13:42:57.908639 MR8 1111
3937 13:42:57.911873 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3938 13:42:57.911959 MR8 1111
3939 13:42:57.918315 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3940 13:42:57.928380 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3941 13:42:57.928467 Write Rank0 MR13 =0xd0
3942 13:42:57.931683 Write Rank1 MR13 =0xd0
3943 13:42:57.931768 Write Rank0 MR13 =0xd0
3944 13:42:57.934861 Write Rank1 MR13 =0xd0
3945 13:42:57.938145 Save calibration result to emmc
3946 13:42:57.938230
3947 13:42:57.938295
3948 13:42:57.941320 [DramcModeReg_Check] Freq_1600, FSP_1
3949 13:42:57.944634 FSP_1, CH_0, RK0
3950 13:42:57.944719 Write Rank0 MR13 =0xd8
3951 13:42:57.947852 MR12 = 0x5c (global = 0x5c) match
3952 13:42:57.951185 MR14 = 0x1e (global = 0x1e) match
3953 13:42:57.954315 FSP_1, CH_0, RK1
3954 13:42:57.954401 Write Rank1 MR13 =0xd8
3955 13:42:57.957854 MR12 = 0x60 (global = 0x60) match
3956 13:42:57.961059 MR14 = 0x1e (global = 0x1e) match
3957 13:42:57.964211 FSP_1, CH_1, RK0
3958 13:42:57.964296 Write Rank0 MR13 =0xd8
3959 13:42:57.967715 MR12 = 0x5a (global = 0x5a) match
3960 13:42:57.970933 MR14 = 0x1e (global = 0x1e) match
3961 13:42:57.974130 FSP_1, CH_1, RK1
3962 13:42:57.974215 Write Rank1 MR13 =0xd8
3963 13:42:57.977210 MR12 = 0x5e (global = 0x5e) match
3964 13:42:57.980688 MR14 = 0x1e (global = 0x1e) match
3965 13:42:57.980773
3966 13:42:57.987225 [MEM_TEST] 02: After DFS, before run time config
3967 13:42:57.996854 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3968 13:42:57.996943
3969 13:42:57.997010 [TA2_TEST]
3970 13:42:57.997070 === TA2 HW
3971 13:42:58.000132 TA2 PAT: XTALK
3972 13:42:58.003426 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3973 13:42:58.010256 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3974 13:42:58.013433 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3975 13:42:58.019817 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3976 13:42:58.019903
3977 13:42:58.019973
3978 13:42:58.020039 Settings after calibration
3979 13:42:58.020103
3980 13:42:58.023107 [DramcRunTimeConfig]
3981 13:42:58.026247 TransferPLLToSPMControl - MODE SW PHYPLL
3982 13:42:58.029735 TX_TRACKING: ON
3983 13:42:58.029825 RX_TRACKING: ON
3984 13:42:58.029891 HW_GATING: ON
3985 13:42:58.032665 HW_GATING DBG: OFF
3986 13:42:58.032750 ddr_geometry:1
3987 13:42:58.036030 ddr_geometry:1
3988 13:42:58.036115 ddr_geometry:1
3989 13:42:58.039348 ddr_geometry:1
3990 13:42:58.039434 ddr_geometry:1
3991 13:42:58.039512 ddr_geometry:1
3992 13:42:58.042658 ddr_geometry:1
3993 13:42:58.042752 ddr_geometry:1
3994 13:42:58.045916 High Freq DUMMY_READ_FOR_TRACKING: ON
3995 13:42:58.049314 ZQCS_ENABLE_LP4: OFF
3996 13:42:58.052714 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
3997 13:42:58.055890 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
3998 13:42:58.055975 SPM_CONTROL_AFTERK: ON
3999 13:42:58.059140 IMPEDANCE_TRACKING: ON
4000 13:42:58.062429 TEMP_SENSOR: ON
4001 13:42:58.062515 PER_BANK_REFRESH: ON
4002 13:42:58.065555 HW_SAVE_FOR_SR: ON
4003 13:42:58.068985 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4004 13:42:58.072314 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
4005 13:42:58.075375 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
4006 13:42:58.075474 Read ODT Tracking: ON
4007 13:42:58.078652 =========================
4008 13:42:58.078738
4009 13:42:58.078804 [TA2_TEST]
4010 13:42:58.081827 === TA2 HW
4011 13:42:58.085296 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
4012 13:42:58.091870 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
4013 13:42:58.094978 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
4014 13:42:58.101834 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
4015 13:42:58.101922
4016 13:42:58.104809 [MEM_TEST] 03: After run time config
4017 13:42:58.114565 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
4018 13:42:58.117828 [complex_mem_test] start addr:0x40024000, len:131072
4019 13:42:58.322052 1st complex R/W mem test pass
4020 13:42:58.328892 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
4021 13:42:58.332159 sync preloader write leveling
4022 13:42:58.335336 sync preloader cbt_mr12
4023 13:42:58.338317 sync preloader cbt_clk_dly
4024 13:42:58.338426 sync preloader cbt_cmd_dly
4025 13:42:58.341672 sync preloader cbt_cs
4026 13:42:58.344882 sync preloader cbt_ca_perbit_delay
4027 13:42:58.348482 sync preloader clk_delay
4028 13:42:58.348566 sync preloader dqs_delay
4029 13:42:58.351400 sync preloader u1Gating2T_Save
4030 13:42:58.354925 sync preloader u1Gating05T_Save
4031 13:42:58.358222 sync preloader u1Gatingfine_tune_Save
4032 13:42:58.361274 sync preloader u1Gatingucpass_count_Save
4033 13:42:58.364865 sync preloader u1TxWindowPerbitVref_Save
4034 13:42:58.367823 sync preloader u1TxCenter_min_Save
4035 13:42:58.371322 sync preloader u1TxCenter_max_Save
4036 13:42:58.374575 sync preloader u1Txwin_center_Save
4037 13:42:58.377697 sync preloader u1Txfirst_pass_Save
4038 13:42:58.380765 sync preloader u1Txlast_pass_Save
4039 13:42:58.384147 sync preloader u1RxDatlat_Save
4040 13:42:58.387376 sync preloader u1RxWinPerbitVref_Save
4041 13:42:58.390834 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4042 13:42:58.394081 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4043 13:42:58.397299 sync preloader delay_cell_unit
4044 13:42:58.403629 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
4045 13:42:58.407208 sync preloader write leveling
4046 13:42:58.410316 sync preloader cbt_mr12
4047 13:42:58.410403 sync preloader cbt_clk_dly
4048 13:42:58.413373 sync preloader cbt_cmd_dly
4049 13:42:58.416872 sync preloader cbt_cs
4050 13:42:58.420160 sync preloader cbt_ca_perbit_delay
4051 13:42:58.420247 sync preloader clk_delay
4052 13:42:58.423349 sync preloader dqs_delay
4053 13:42:58.426518 sync preloader u1Gating2T_Save
4054 13:42:58.430059 sync preloader u1Gating05T_Save
4055 13:42:58.433289 sync preloader u1Gatingfine_tune_Save
4056 13:42:58.436413 sync preloader u1Gatingucpass_count_Save
4057 13:42:58.439577 sync preloader u1TxWindowPerbitVref_Save
4058 13:42:58.443078 sync preloader u1TxCenter_min_Save
4059 13:42:58.446280 sync preloader u1TxCenter_max_Save
4060 13:42:58.449403 sync preloader u1Txwin_center_Save
4061 13:42:58.452813 sync preloader u1Txfirst_pass_Save
4062 13:42:58.455903 sync preloader u1Txlast_pass_Save
4063 13:42:58.459326 sync preloader u1RxDatlat_Save
4064 13:42:58.462465 sync preloader u1RxWinPerbitVref_Save
4065 13:42:58.465957 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4066 13:42:58.468910 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4067 13:42:58.472164 sync preloader delay_cell_unit
4068 13:42:58.478878 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
4069 13:42:58.482392 sync preloader write leveling
4070 13:42:58.485580 sync preloader cbt_mr12
4071 13:42:58.485694 sync preloader cbt_clk_dly
4072 13:42:58.488782 sync preloader cbt_cmd_dly
4073 13:42:58.492053 sync preloader cbt_cs
4074 13:42:58.495321 sync preloader cbt_ca_perbit_delay
4075 13:42:58.495407 sync preloader clk_delay
4076 13:42:58.498595 sync preloader dqs_delay
4077 13:42:58.501859 sync preloader u1Gating2T_Save
4078 13:42:58.504917 sync preloader u1Gating05T_Save
4079 13:42:58.508126 sync preloader u1Gatingfine_tune_Save
4080 13:42:58.511708 sync preloader u1Gatingucpass_count_Save
4081 13:42:58.514989 sync preloader u1TxWindowPerbitVref_Save
4082 13:42:58.518355 sync preloader u1TxCenter_min_Save
4083 13:42:58.521493 sync preloader u1TxCenter_max_Save
4084 13:42:58.524627 sync preloader u1Txwin_center_Save
4085 13:42:58.527918 sync preloader u1Txfirst_pass_Save
4086 13:42:58.531354 sync preloader u1Txlast_pass_Save
4087 13:42:58.534308 sync preloader u1RxDatlat_Save
4088 13:42:58.537831 sync preloader u1RxWinPerbitVref_Save
4089 13:42:58.540980 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4090 13:42:58.544439 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4091 13:42:58.547816 sync preloader delay_cell_unit
4092 13:42:58.551015 just_for_test_dump_coreboot_params dump all params
4093 13:42:58.554195 dump source = 0x0
4094 13:42:58.557317 dump params frequency:1600
4095 13:42:58.557420 dump params rank number:2
4096 13:42:58.557521
4097 13:42:58.560867 dump params write leveling
4098 13:42:58.563919 write leveling[0][0][0] = 0x1f
4099 13:42:58.567357 write leveling[0][0][1] = 0x1a
4100 13:42:58.570465 write leveling[0][1][0] = 0x1b
4101 13:42:58.570550 write leveling[0][1][1] = 0x18
4102 13:42:58.573762 write leveling[1][0][0] = 0x25
4103 13:42:58.576924 write leveling[1][0][1] = 0x1c
4104 13:42:58.580221 write leveling[1][1][0] = 0x23
4105 13:42:58.583772 write leveling[1][1][1] = 0x1c
4106 13:42:58.583857 dump params cbt_cs
4107 13:42:58.586960 cbt_cs[0][0] = 0x6
4108 13:42:58.587045 cbt_cs[0][1] = 0x6
4109 13:42:58.590112 cbt_cs[1][0] = 0xb
4110 13:42:58.590197 cbt_cs[1][1] = 0xb
4111 13:42:58.593340 dump params cbt_mr12
4112 13:42:58.596577 cbt_mr12[0][0] = 0x1c
4113 13:42:58.596661 cbt_mr12[0][1] = 0x20
4114 13:42:58.600044 cbt_mr12[1][0] = 0x1a
4115 13:42:58.600129 cbt_mr12[1][1] = 0x1e
4116 13:42:58.603202 dump params tx window
4117 13:42:58.606304 tx_center_min[0][0][0] = 983
4118 13:42:58.609708 tx_center_max[0][0][0] = 990
4119 13:42:58.609794 tx_center_min[0][0][1] = 978
4120 13:42:58.613106 tx_center_max[0][0][1] = 985
4121 13:42:58.616408 tx_center_min[0][1][0] = 982
4122 13:42:58.619578 tx_center_max[0][1][0] = 990
4123 13:42:58.622814 tx_center_min[0][1][1] = 979
4124 13:42:58.622900 tx_center_max[0][1][1] = 986
4125 13:42:58.626265 tx_center_min[1][0][0] = 990
4126 13:42:58.629654 tx_center_max[1][0][0] = 996
4127 13:42:58.632826 tx_center_min[1][0][1] = 980
4128 13:42:58.635858 tx_center_max[1][0][1] = 987
4129 13:42:58.635944 tx_center_min[1][1][0] = 989
4130 13:42:58.639090 tx_center_max[1][1][0] = 994
4131 13:42:58.642808 tx_center_min[1][1][1] = 980
4132 13:42:58.645868 tx_center_max[1][1][1] = 987
4133 13:42:58.645955 dump params tx window
4134 13:42:58.649239 tx_win_center[0][0][0] = 990
4135 13:42:58.652489 tx_first_pass[0][0][0] = 978
4136 13:42:58.655729 tx_last_pass[0][0][0] = 1002
4137 13:42:58.658918 tx_win_center[0][0][1] = 989
4138 13:42:58.659004 tx_first_pass[0][0][1] = 977
4139 13:42:58.662150 tx_last_pass[0][0][1] = 1001
4140 13:42:58.665325 tx_win_center[0][0][2] = 990
4141 13:42:58.668827 tx_first_pass[0][0][2] = 978
4142 13:42:58.671962 tx_last_pass[0][0][2] = 1002
4143 13:42:58.672056 tx_win_center[0][0][3] = 983
4144 13:42:58.675410 tx_first_pass[0][0][3] = 972
4145 13:42:58.678400 tx_last_pass[0][0][3] = 995
4146 13:42:58.681748 tx_win_center[0][0][4] = 988
4147 13:42:58.684892 tx_first_pass[0][0][4] = 977
4148 13:42:58.684964 tx_last_pass[0][0][4] = 1000
4149 13:42:58.688393 tx_win_center[0][0][5] = 986
4150 13:42:58.691619 tx_first_pass[0][0][5] = 975
4151 13:42:58.694845 tx_last_pass[0][0][5] = 998
4152 13:42:58.698026 tx_win_center[0][0][6] = 987
4153 13:42:58.698111 tx_first_pass[0][0][6] = 976
4154 13:42:58.701603 tx_last_pass[0][0][6] = 999
4155 13:42:58.704603 tx_win_center[0][0][7] = 989
4156 13:42:58.708124 tx_first_pass[0][0][7] = 977
4157 13:42:58.711372 tx_last_pass[0][0][7] = 1001
4158 13:42:58.711494 tx_win_center[0][0][8] = 978
4159 13:42:58.714512 tx_first_pass[0][0][8] = 967
4160 13:42:58.717641 tx_last_pass[0][0][8] = 990
4161 13:42:58.720967 tx_win_center[0][0][9] = 980
4162 13:42:58.724578 tx_first_pass[0][0][9] = 968
4163 13:42:58.724662 tx_last_pass[0][0][9] = 992
4164 13:42:58.727664 tx_win_center[0][0][10] = 985
4165 13:42:58.730986 tx_first_pass[0][0][10] = 973
4166 13:42:58.734416 tx_last_pass[0][0][10] = 997
4167 13:42:58.737688 tx_win_center[0][0][11] = 979
4168 13:42:58.737772 tx_first_pass[0][0][11] = 967
4169 13:42:58.740701 tx_last_pass[0][0][11] = 991
4170 13:42:58.744468 tx_win_center[0][0][12] = 981
4171 13:42:58.747281 tx_first_pass[0][0][12] = 969
4172 13:42:58.750433 tx_last_pass[0][0][12] = 993
4173 13:42:58.750518 tx_win_center[0][0][13] = 981
4174 13:42:58.753759 tx_first_pass[0][0][13] = 969
4175 13:42:58.757070 tx_last_pass[0][0][13] = 993
4176 13:42:58.760638 tx_win_center[0][0][14] = 982
4177 13:42:58.763580 tx_first_pass[0][0][14] = 969
4178 13:42:58.767090 tx_last_pass[0][0][14] = 996
4179 13:42:58.767174 tx_win_center[0][0][15] = 985
4180 13:42:58.770195 tx_first_pass[0][0][15] = 972
4181 13:42:58.773593 tx_last_pass[0][0][15] = 998
4182 13:42:58.776858 tx_win_center[0][1][0] = 990
4183 13:42:58.780038 tx_first_pass[0][1][0] = 978
4184 13:42:58.780122 tx_last_pass[0][1][0] = 1002
4185 13:42:58.783436 tx_win_center[0][1][1] = 988
4186 13:42:58.786748 tx_first_pass[0][1][1] = 977
4187 13:42:58.789797 tx_last_pass[0][1][1] = 1000
4188 13:42:58.793125 tx_win_center[0][1][2] = 989
4189 13:42:58.793210 tx_first_pass[0][1][2] = 978
4190 13:42:58.796700 tx_last_pass[0][1][2] = 1000
4191 13:42:58.799554 tx_win_center[0][1][3] = 982
4192 13:42:58.803067 tx_first_pass[0][1][3] = 970
4193 13:42:58.806220 tx_last_pass[0][1][3] = 995
4194 13:42:58.806304 tx_win_center[0][1][4] = 988
4195 13:42:58.809660 tx_first_pass[0][1][4] = 977
4196 13:42:58.812664 tx_last_pass[0][1][4] = 1000
4197 13:42:58.816256 tx_win_center[0][1][5] = 986
4198 13:42:58.819251 tx_first_pass[0][1][5] = 974
4199 13:42:58.819325 tx_last_pass[0][1][5] = 998
4200 13:42:58.822842 tx_win_center[0][1][6] = 987
4201 13:42:58.826017 tx_first_pass[0][1][6] = 976
4202 13:42:58.829193 tx_last_pass[0][1][6] = 999
4203 13:42:58.829265 tx_win_center[0][1][7] = 989
4204 13:42:58.832419 tx_first_pass[0][1][7] = 977
4205 13:42:58.835590 tx_last_pass[0][1][7] = 1001
4206 13:42:58.838873 tx_win_center[0][1][8] = 979
4207 13:42:58.842845 tx_first_pass[0][1][8] = 967
4208 13:42:58.842930 tx_last_pass[0][1][8] = 992
4209 13:42:58.845411 tx_win_center[0][1][9] = 980
4210 13:42:58.848970 tx_first_pass[0][1][9] = 969
4211 13:42:58.852170 tx_last_pass[0][1][9] = 992
4212 13:42:58.855396 tx_win_center[0][1][10] = 986
4213 13:42:58.855491 tx_first_pass[0][1][10] = 974
4214 13:42:58.858715 tx_last_pass[0][1][10] = 999
4215 13:42:58.861894 tx_win_center[0][1][11] = 980
4216 13:42:58.865012 tx_first_pass[0][1][11] = 968
4217 13:42:58.868435 tx_last_pass[0][1][11] = 992
4218 13:42:58.871770 tx_win_center[0][1][12] = 981
4219 13:42:58.871855 tx_first_pass[0][1][12] = 969
4220 13:42:58.874902 tx_last_pass[0][1][12] = 993
4221 13:42:58.878147 tx_win_center[0][1][13] = 981
4222 13:42:58.881701 tx_first_pass[0][1][13] = 969
4223 13:42:58.884667 tx_last_pass[0][1][13] = 993
4224 13:42:58.884753 tx_win_center[0][1][14] = 982
4225 13:42:58.888120 tx_first_pass[0][1][14] = 970
4226 13:42:58.891383 tx_last_pass[0][1][14] = 995
4227 13:42:58.894694 tx_win_center[0][1][15] = 986
4228 13:42:58.897930 tx_first_pass[0][1][15] = 974
4229 13:42:58.898015 tx_last_pass[0][1][15] = 998
4230 13:42:58.901067 tx_win_center[1][0][0] = 996
4231 13:42:58.904318 tx_first_pass[1][0][0] = 984
4232 13:42:58.907876 tx_last_pass[1][0][0] = 1008
4233 13:42:58.911054 tx_win_center[1][0][1] = 994
4234 13:42:58.911165 tx_first_pass[1][0][1] = 981
4235 13:42:58.914471 tx_last_pass[1][0][1] = 1007
4236 13:42:58.917583 tx_win_center[1][0][2] = 992
4237 13:42:58.920737 tx_first_pass[1][0][2] = 979
4238 13:42:58.924065 tx_last_pass[1][0][2] = 1006
4239 13:42:58.924139 tx_win_center[1][0][3] = 990
4240 13:42:58.927204 tx_first_pass[1][0][3] = 977
4241 13:42:58.930412 tx_last_pass[1][0][3] = 1003
4242 13:42:58.933906 tx_win_center[1][0][4] = 994
4243 13:42:58.937080 tx_first_pass[1][0][4] = 983
4244 13:42:58.937158 tx_last_pass[1][0][4] = 1006
4245 13:42:58.940312 tx_win_center[1][0][5] = 995
4246 13:42:58.943995 tx_first_pass[1][0][5] = 983
4247 13:42:58.947016 tx_last_pass[1][0][5] = 1007
4248 13:42:58.950142 tx_win_center[1][0][6] = 995
4249 13:42:58.950211 tx_first_pass[1][0][6] = 983
4250 13:42:58.953729 tx_last_pass[1][0][6] = 1007
4251 13:42:58.956866 tx_win_center[1][0][7] = 994
4252 13:42:58.960066 tx_first_pass[1][0][7] = 982
4253 13:42:58.963272 tx_last_pass[1][0][7] = 1006
4254 13:42:58.963339 tx_win_center[1][0][8] = 983
4255 13:42:58.966917 tx_first_pass[1][0][8] = 971
4256 13:42:58.970049 tx_last_pass[1][0][8] = 996
4257 13:42:58.973206 tx_win_center[1][0][9] = 982
4258 13:42:58.976389 tx_first_pass[1][0][9] = 971
4259 13:42:58.976473 tx_last_pass[1][0][9] = 994
4260 13:42:58.979620 tx_win_center[1][0][10] = 986
4261 13:42:58.983128 tx_first_pass[1][0][10] = 974
4262 13:42:58.986417 tx_last_pass[1][0][10] = 998
4263 13:42:58.989625 tx_win_center[1][0][11] = 987
4264 13:42:58.993593 tx_first_pass[1][0][11] = 976
4265 13:42:58.993677 tx_last_pass[1][0][11] = 999
4266 13:42:58.996660 tx_win_center[1][0][12] = 986
4267 13:42:58.999264 tx_first_pass[1][0][12] = 975
4268 13:42:59.002556 tx_last_pass[1][0][12] = 998
4269 13:42:59.005913 tx_win_center[1][0][13] = 987
4270 13:42:59.006001 tx_first_pass[1][0][13] = 976
4271 13:42:59.008894 tx_last_pass[1][0][13] = 999
4272 13:42:59.012203 tx_win_center[1][0][14] = 987
4273 13:42:59.015572 tx_first_pass[1][0][14] = 975
4274 13:42:59.018681 tx_last_pass[1][0][14] = 999
4275 13:42:59.018765 tx_win_center[1][0][15] = 980
4276 13:42:59.022217 tx_first_pass[1][0][15] = 969
4277 13:42:59.025375 tx_last_pass[1][0][15] = 992
4278 13:42:59.028535 tx_win_center[1][1][0] = 994
4279 13:42:59.031802 tx_first_pass[1][1][0] = 982
4280 13:42:59.035344 tx_last_pass[1][1][0] = 1007
4281 13:42:59.035474 tx_win_center[1][1][1] = 993
4282 13:42:59.038526 tx_first_pass[1][1][1] = 981
4283 13:42:59.041667 tx_last_pass[1][1][1] = 1006
4284 13:42:59.045224 tx_win_center[1][1][2] = 991
4285 13:42:59.048401 tx_first_pass[1][1][2] = 978
4286 13:42:59.048485 tx_last_pass[1][1][2] = 1005
4287 13:42:59.051643 tx_win_center[1][1][3] = 989
4288 13:42:59.055070 tx_first_pass[1][1][3] = 977
4289 13:42:59.058300 tx_last_pass[1][1][3] = 1001
4290 13:42:59.058384 tx_win_center[1][1][4] = 993
4291 13:42:59.061582 tx_first_pass[1][1][4] = 980
4292 13:42:59.064736 tx_last_pass[1][1][4] = 1006
4293 13:42:59.067991 tx_win_center[1][1][5] = 994
4294 13:42:59.071194 tx_first_pass[1][1][5] = 982
4295 13:42:59.071278 tx_last_pass[1][1][5] = 1007
4296 13:42:59.074415 tx_win_center[1][1][6] = 993
4297 13:42:59.078008 tx_first_pass[1][1][6] = 981
4298 13:42:59.081224 tx_last_pass[1][1][6] = 1006
4299 13:42:59.084428 tx_win_center[1][1][7] = 993
4300 13:42:59.084512 tx_first_pass[1][1][7] = 980
4301 13:42:59.087579 tx_last_pass[1][1][7] = 1006
4302 13:42:59.091011 tx_win_center[1][1][8] = 984
4303 13:42:59.094221 tx_first_pass[1][1][8] = 972
4304 13:42:59.097574 tx_last_pass[1][1][8] = 996
4305 13:42:59.097659 tx_win_center[1][1][9] = 982
4306 13:42:59.100655 tx_first_pass[1][1][9] = 971
4307 13:42:59.103938 tx_last_pass[1][1][9] = 994
4308 13:42:59.107427 tx_win_center[1][1][10] = 987
4309 13:42:59.110750 tx_first_pass[1][1][10] = 976
4310 13:42:59.110833 tx_last_pass[1][1][10] = 998
4311 13:42:59.113759 tx_win_center[1][1][11] = 987
4312 13:42:59.117206 tx_first_pass[1][1][11] = 975
4313 13:42:59.120392 tx_last_pass[1][1][11] = 999
4314 13:42:59.123605 tx_win_center[1][1][12] = 987
4315 13:42:59.126818 tx_first_pass[1][1][12] = 975
4316 13:42:59.126913 tx_last_pass[1][1][12] = 999
4317 13:42:59.130180 tx_win_center[1][1][13] = 987
4318 13:42:59.133439 tx_first_pass[1][1][13] = 976
4319 13:42:59.136624 tx_last_pass[1][1][13] = 999
4320 13:42:59.140056 tx_win_center[1][1][14] = 987
4321 13:42:59.140165 tx_first_pass[1][1][14] = 975
4322 13:42:59.143372 tx_last_pass[1][1][14] = 999
4323 13:42:59.146439 tx_win_center[1][1][15] = 980
4324 13:42:59.149929 tx_first_pass[1][1][15] = 969
4325 13:42:59.152940 tx_last_pass[1][1][15] = 992
4326 13:42:59.153025 dump params rx window
4327 13:42:59.156291 rx_firspass[0][0][0] = 7
4328 13:42:59.159613 rx_lastpass[0][0][0] = 36
4329 13:42:59.159699 rx_firspass[0][0][1] = 7
4330 13:42:59.162763 rx_lastpass[0][0][1] = 36
4331 13:42:59.166021 rx_firspass[0][0][2] = 5
4332 13:42:59.169576 rx_lastpass[0][0][2] = 39
4333 13:42:59.169653 rx_firspass[0][0][3] = -3
4334 13:42:59.172781 rx_lastpass[0][0][3] = 30
4335 13:42:59.175862 rx_firspass[0][0][4] = 6
4336 13:42:59.175946 rx_lastpass[0][0][4] = 36
4337 13:42:59.179393 rx_firspass[0][0][5] = 2
4338 13:42:59.182539 rx_lastpass[0][0][5] = 33
4339 13:42:59.185748 rx_firspass[0][0][6] = 3
4340 13:42:59.185833 rx_lastpass[0][0][6] = 33
4341 13:42:59.189008 rx_firspass[0][0][7] = 4
4342 13:42:59.192270 rx_lastpass[0][0][7] = 36
4343 13:42:59.192354 rx_firspass[0][0][8] = -1
4344 13:42:59.195805 rx_lastpass[0][0][8] = 30
4345 13:42:59.198817 rx_firspass[0][0][9] = 2
4346 13:42:59.202362 rx_lastpass[0][0][9] = 32
4347 13:42:59.202446 rx_firspass[0][0][10] = 9
4348 13:42:59.205542 rx_lastpass[0][0][10] = 37
4349 13:42:59.208652 rx_firspass[0][0][11] = 1
4350 13:42:59.211837 rx_lastpass[0][0][11] = 30
4351 13:42:59.211920 rx_firspass[0][0][12] = 3
4352 13:42:59.215420 rx_lastpass[0][0][12] = 31
4353 13:42:59.218549 rx_firspass[0][0][13] = 2
4354 13:42:59.218632 rx_lastpass[0][0][13] = 31
4355 13:42:59.221729 rx_firspass[0][0][14] = 1
4356 13:42:59.224955 rx_lastpass[0][0][14] = 35
4357 13:42:59.228234 rx_firspass[0][0][15] = 4
4358 13:42:59.228317 rx_lastpass[0][0][15] = 36
4359 13:42:59.231411 rx_firspass[0][1][0] = 4
4360 13:42:59.234906 rx_lastpass[0][1][0] = 39
4361 13:42:59.238005 rx_firspass[0][1][1] = 5
4362 13:42:59.238089 rx_lastpass[0][1][1] = 38
4363 13:42:59.241604 rx_firspass[0][1][2] = 5
4364 13:42:59.244593 rx_lastpass[0][1][2] = 40
4365 13:42:59.244679 rx_firspass[0][1][3] = -3
4366 13:42:59.247849 rx_lastpass[0][1][3] = 31
4367 13:42:59.251038 rx_firspass[0][1][4] = 5
4368 13:42:59.254480 rx_lastpass[0][1][4] = 38
4369 13:42:59.254563 rx_firspass[0][1][5] = 0
4370 13:42:59.257838 rx_lastpass[0][1][5] = 34
4371 13:42:59.260787 rx_firspass[0][1][6] = 1
4372 13:42:59.260870 rx_lastpass[0][1][6] = 35
4373 13:42:59.264313 rx_firspass[0][1][7] = 3
4374 13:42:59.267378 rx_lastpass[0][1][7] = 37
4375 13:42:59.270694 rx_firspass[0][1][8] = -3
4376 13:42:59.270778 rx_lastpass[0][1][8] = 32
4377 13:42:59.273994 rx_firspass[0][1][9] = -2
4378 13:42:59.277207 rx_lastpass[0][1][9] = 34
4379 13:42:59.277317 rx_firspass[0][1][10] = 5
4380 13:42:59.280576 rx_lastpass[0][1][10] = 40
4381 13:42:59.283829 rx_firspass[0][1][11] = -2
4382 13:42:59.287312 rx_lastpass[0][1][11] = 32
4383 13:42:59.287420 rx_firspass[0][1][12] = 0
4384 13:42:59.290495 rx_lastpass[0][1][12] = 34
4385 13:42:59.293711 rx_firspass[0][1][13] = -2
4386 13:42:59.297224 rx_lastpass[0][1][13] = 34
4387 13:42:59.297308 rx_firspass[0][1][14] = 2
4388 13:42:59.300481 rx_lastpass[0][1][14] = 36
4389 13:42:59.303552 rx_firspass[0][1][15] = 4
4390 13:42:59.307091 rx_lastpass[0][1][15] = 37
4391 13:42:59.307175 rx_firspass[1][0][0] = 6
4392 13:42:59.309989 rx_lastpass[1][0][0] = 36
4393 13:42:59.313514 rx_firspass[1][0][1] = 4
4394 13:42:59.313628 rx_lastpass[1][0][1] = 37
4395 13:42:59.316706 rx_firspass[1][0][2] = 1
4396 13:42:59.319902 rx_lastpass[1][0][2] = 34
4397 13:42:59.323122 rx_firspass[1][0][3] = 0
4398 13:42:59.323199 rx_lastpass[1][0][3] = 31
4399 13:42:59.326563 rx_firspass[1][0][4] = 5
4400 13:42:59.329783 rx_lastpass[1][0][4] = 35
4401 13:42:59.329871 rx_firspass[1][0][5] = 9
4402 13:42:59.333080 rx_lastpass[1][0][5] = 38
4403 13:42:59.336187 rx_firspass[1][0][6] = 6
4404 13:42:59.339696 rx_lastpass[1][0][6] = 38
4405 13:42:59.339780 rx_firspass[1][0][7] = 5
4406 13:42:59.342861 rx_lastpass[1][0][7] = 35
4407 13:42:59.346001 rx_firspass[1][0][8] = 0
4408 13:42:59.346084 rx_lastpass[1][0][8] = 33
4409 13:42:59.349443 rx_firspass[1][0][9] = -1
4410 13:42:59.352666 rx_lastpass[1][0][9] = 32
4411 13:42:59.355848 rx_firspass[1][0][10] = 3
4412 13:42:59.355931 rx_lastpass[1][0][10] = 36
4413 13:42:59.359326 rx_firspass[1][0][11] = 4
4414 13:42:59.362464 rx_lastpass[1][0][11] = 36
4415 13:42:59.365628 rx_firspass[1][0][12] = 5
4416 13:42:59.365711 rx_lastpass[1][0][12] = 35
4417 13:42:59.369103 rx_firspass[1][0][13] = 6
4418 13:42:59.372109 rx_lastpass[1][0][13] = 36
4419 13:42:59.372194 rx_firspass[1][0][14] = 5
4420 13:42:59.375585 rx_lastpass[1][0][14] = 36
4421 13:42:59.378654 rx_firspass[1][0][15] = -3
4422 13:42:59.382010 rx_lastpass[1][0][15] = 29
4423 13:42:59.382087 rx_firspass[1][1][0] = 4
4424 13:42:59.385178 rx_lastpass[1][1][0] = 40
4425 13:42:59.388558 rx_firspass[1][1][1] = 3
4426 13:42:59.391960 rx_lastpass[1][1][1] = 39
4427 13:42:59.392032 rx_firspass[1][1][2] = 3
4428 13:42:59.395261 rx_lastpass[1][1][2] = 34
4429 13:42:59.398627 rx_firspass[1][1][3] = -2
4430 13:42:59.398698 rx_lastpass[1][1][3] = 33
4431 13:42:59.401837 rx_firspass[1][1][4] = 4
4432 13:42:59.404998 rx_lastpass[1][1][4] = 39
4433 13:42:59.408279 rx_firspass[1][1][5] = 6
4434 13:42:59.408363 rx_lastpass[1][1][5] = 40
4435 13:42:59.411624 rx_firspass[1][1][6] = 6
4436 13:42:59.414887 rx_lastpass[1][1][6] = 40
4437 13:42:59.414973 rx_firspass[1][1][7] = 3
4438 13:42:59.417977 rx_lastpass[1][1][7] = 38
4439 13:42:59.421235 rx_firspass[1][1][8] = -1
4440 13:42:59.424835 rx_lastpass[1][1][8] = 35
4441 13:42:59.424917 rx_firspass[1][1][9] = -3
4442 13:42:59.428081 rx_lastpass[1][1][9] = 33
4443 13:42:59.431282 rx_firspass[1][1][10] = 2
4444 13:42:59.434305 rx_lastpass[1][1][10] = 38
4445 13:42:59.434388 rx_firspass[1][1][11] = 3
4446 13:42:59.437922 rx_lastpass[1][1][11] = 38
4447 13:42:59.441119 rx_firspass[1][1][12] = 3
4448 13:42:59.441203 rx_lastpass[1][1][12] = 37
4449 13:42:59.444514 rx_firspass[1][1][13] = 4
4450 13:42:59.447640 rx_lastpass[1][1][13] = 39
4451 13:42:59.450787 rx_firspass[1][1][14] = 4
4452 13:42:59.450865 rx_lastpass[1][1][14] = 40
4453 13:42:59.454286 rx_firspass[1][1][15] = -4
4454 13:42:59.457153 rx_lastpass[1][1][15] = 31
4455 13:42:59.460869 dump params clk_delay
4456 13:42:59.460950 clk_delay[0] = 0
4457 13:42:59.461019 clk_delay[1] = 0
4458 13:42:59.464021 dump params dqs_delay
4459 13:42:59.467099 dqs_delay[0][0] = -1
4460 13:42:59.467170 dqs_delay[0][1] = 0
4461 13:42:59.470217 dqs_delay[1][0] = 0
4462 13:42:59.470336 dqs_delay[1][1] = -1
4463 13:42:59.473799 dump params delay_cell_unit = 744
4464 13:42:59.476978 dump source = 0x0
4465 13:42:59.480067 dump params frequency:1200
4466 13:42:59.480140 dump params rank number:2
4467 13:42:59.480202
4468 13:42:59.483463 dump params write leveling
4469 13:42:59.486640 write leveling[0][0][0] = 0x0
4470 13:42:59.490213 write leveling[0][0][1] = 0x0
4471 13:42:59.490289 write leveling[0][1][0] = 0x0
4472 13:42:59.493251 write leveling[0][1][1] = 0x0
4473 13:42:59.496727 write leveling[1][0][0] = 0x0
4474 13:42:59.500003 write leveling[1][0][1] = 0x0
4475 13:42:59.503170 write leveling[1][1][0] = 0x0
4476 13:42:59.506470 write leveling[1][1][1] = 0x0
4477 13:42:59.506554 dump params cbt_cs
4478 13:42:59.509522 cbt_cs[0][0] = 0x0
4479 13:42:59.509605 cbt_cs[0][1] = 0x0
4480 13:42:59.513037 cbt_cs[1][0] = 0x0
4481 13:42:59.513121 cbt_cs[1][1] = 0x0
4482 13:42:59.516258 dump params cbt_mr12
4483 13:42:59.516343 cbt_mr12[0][0] = 0x0
4484 13:42:59.519540 cbt_mr12[0][1] = 0x0
4485 13:42:59.522825 cbt_mr12[1][0] = 0x0
4486 13:42:59.522909 cbt_mr12[1][1] = 0x0
4487 13:42:59.526061 dump params tx window
4488 13:42:59.526146 tx_center_min[0][0][0] = 0
4489 13:42:59.529218 tx_center_max[0][0][0] = 0
4490 13:42:59.532818 tx_center_min[0][0][1] = 0
4491 13:42:59.535845 tx_center_max[0][0][1] = 0
4492 13:42:59.535929 tx_center_min[0][1][0] = 0
4493 13:42:59.539315 tx_center_max[0][1][0] = 0
4494 13:42:59.542559 tx_center_min[0][1][1] = 0
4495 13:42:59.545658 tx_center_max[0][1][1] = 0
4496 13:42:59.545743 tx_center_min[1][0][0] = 0
4497 13:42:59.549156 tx_center_max[1][0][0] = 0
4498 13:42:59.552343 tx_center_min[1][0][1] = 0
4499 13:42:59.555443 tx_center_max[1][0][1] = 0
4500 13:42:59.555539 tx_center_min[1][1][0] = 0
4501 13:42:59.558920 tx_center_max[1][1][0] = 0
4502 13:42:59.562160 tx_center_min[1][1][1] = 0
4503 13:42:59.565630 tx_center_max[1][1][1] = 0
4504 13:42:59.565715 dump params tx window
4505 13:42:59.568857 tx_win_center[0][0][0] = 0
4506 13:42:59.572076 tx_first_pass[0][0][0] = 0
4507 13:42:59.575222 tx_last_pass[0][0][0] = 0
4508 13:42:59.575306 tx_win_center[0][0][1] = 0
4509 13:42:59.578373 tx_first_pass[0][0][1] = 0
4510 13:42:59.581582 tx_last_pass[0][0][1] = 0
4511 13:42:59.581667 tx_win_center[0][0][2] = 0
4512 13:42:59.585131 tx_first_pass[0][0][2] = 0
4513 13:42:59.588201 tx_last_pass[0][0][2] = 0
4514 13:42:59.591677 tx_win_center[0][0][3] = 0
4515 13:42:59.591761 tx_first_pass[0][0][3] = 0
4516 13:42:59.594889 tx_last_pass[0][0][3] = 0
4517 13:42:59.598177 tx_win_center[0][0][4] = 0
4518 13:42:59.601597 tx_first_pass[0][0][4] = 0
4519 13:42:59.601682 tx_last_pass[0][0][4] = 0
4520 13:42:59.604711 tx_win_center[0][0][5] = 0
4521 13:42:59.607670 tx_first_pass[0][0][5] = 0
4522 13:42:59.611171 tx_last_pass[0][0][5] = 0
4523 13:42:59.611256 tx_win_center[0][0][6] = 0
4524 13:42:59.614337 tx_first_pass[0][0][6] = 0
4525 13:42:59.617540 tx_last_pass[0][0][6] = 0
4526 13:42:59.620900 tx_win_center[0][0][7] = 0
4527 13:42:59.620978 tx_first_pass[0][0][7] = 0
4528 13:42:59.624281 tx_last_pass[0][0][7] = 0
4529 13:42:59.627639 tx_win_center[0][0][8] = 0
4530 13:42:59.630705 tx_first_pass[0][0][8] = 0
4531 13:42:59.630814 tx_last_pass[0][0][8] = 0
4532 13:42:59.633852 tx_win_center[0][0][9] = 0
4533 13:42:59.637174 tx_first_pass[0][0][9] = 0
4534 13:42:59.637259 tx_last_pass[0][0][9] = 0
4535 13:42:59.640605 tx_win_center[0][0][10] = 0
4536 13:42:59.643653 tx_first_pass[0][0][10] = 0
4537 13:42:59.647252 tx_last_pass[0][0][10] = 0
4538 13:42:59.647351 tx_win_center[0][0][11] = 0
4539 13:42:59.650346 tx_first_pass[0][0][11] = 0
4540 13:42:59.653853 tx_last_pass[0][0][11] = 0
4541 13:42:59.656963 tx_win_center[0][0][12] = 0
4542 13:42:59.660170 tx_first_pass[0][0][12] = 0
4543 13:42:59.660243 tx_last_pass[0][0][12] = 0
4544 13:42:59.663652 tx_win_center[0][0][13] = 0
4545 13:42:59.666862 tx_first_pass[0][0][13] = 0
4546 13:42:59.670063 tx_last_pass[0][0][13] = 0
4547 13:42:59.670132 tx_win_center[0][0][14] = 0
4548 13:42:59.673177 tx_first_pass[0][0][14] = 0
4549 13:42:59.676395 tx_last_pass[0][0][14] = 0
4550 13:42:59.679637 tx_win_center[0][0][15] = 0
4551 13:42:59.679721 tx_first_pass[0][0][15] = 0
4552 13:42:59.683060 tx_last_pass[0][0][15] = 0
4553 13:42:59.686140 tx_win_center[0][1][0] = 0
4554 13:42:59.689811 tx_first_pass[0][1][0] = 0
4555 13:42:59.689895 tx_last_pass[0][1][0] = 0
4556 13:42:59.693035 tx_win_center[0][1][1] = 0
4557 13:42:59.696099 tx_first_pass[0][1][1] = 0
4558 13:42:59.699528 tx_last_pass[0][1][1] = 0
4559 13:42:59.699612 tx_win_center[0][1][2] = 0
4560 13:42:59.702553 tx_first_pass[0][1][2] = 0
4561 13:42:59.706134 tx_last_pass[0][1][2] = 0
4562 13:42:59.709392 tx_win_center[0][1][3] = 0
4563 13:42:59.709477 tx_first_pass[0][1][3] = 0
4564 13:42:59.712608 tx_last_pass[0][1][3] = 0
4565 13:42:59.715975 tx_win_center[0][1][4] = 0
4566 13:42:59.719104 tx_first_pass[0][1][4] = 0
4567 13:42:59.719192 tx_last_pass[0][1][4] = 0
4568 13:42:59.722285 tx_win_center[0][1][5] = 0
4569 13:42:59.725467 tx_first_pass[0][1][5] = 0
4570 13:42:59.725566 tx_last_pass[0][1][5] = 0
4571 13:42:59.728781 tx_win_center[0][1][6] = 0
4572 13:42:59.732251 tx_first_pass[0][1][6] = 0
4573 13:42:59.735624 tx_last_pass[0][1][6] = 0
4574 13:42:59.735736 tx_win_center[0][1][7] = 0
4575 13:42:59.738538 tx_first_pass[0][1][7] = 0
4576 13:42:59.742008 tx_last_pass[0][1][7] = 0
4577 13:42:59.745368 tx_win_center[0][1][8] = 0
4578 13:42:59.745453 tx_first_pass[0][1][8] = 0
4579 13:42:59.748331 tx_last_pass[0][1][8] = 0
4580 13:42:59.751849 tx_win_center[0][1][9] = 0
4581 13:42:59.754891 tx_first_pass[0][1][9] = 0
4582 13:42:59.754983 tx_last_pass[0][1][9] = 0
4583 13:42:59.758433 tx_win_center[0][1][10] = 0
4584 13:42:59.761590 tx_first_pass[0][1][10] = 0
4585 13:42:59.764643 tx_last_pass[0][1][10] = 0
4586 13:42:59.764728 tx_win_center[0][1][11] = 0
4587 13:42:59.768076 tx_first_pass[0][1][11] = 0
4588 13:42:59.771569 tx_last_pass[0][1][11] = 0
4589 13:42:59.774764 tx_win_center[0][1][12] = 0
4590 13:42:59.774848 tx_first_pass[0][1][12] = 0
4591 13:42:59.778005 tx_last_pass[0][1][12] = 0
4592 13:42:59.781405 tx_win_center[0][1][13] = 0
4593 13:42:59.784626 tx_first_pass[0][1][13] = 0
4594 13:42:59.784711 tx_last_pass[0][1][13] = 0
4595 13:42:59.787880 tx_win_center[0][1][14] = 0
4596 13:42:59.791039 tx_first_pass[0][1][14] = 0
4597 13:42:59.794180 tx_last_pass[0][1][14] = 0
4598 13:42:59.797432 tx_win_center[0][1][15] = 0
4599 13:42:59.797517 tx_first_pass[0][1][15] = 0
4600 13:42:59.801066 tx_last_pass[0][1][15] = 0
4601 13:42:59.804199 tx_win_center[1][0][0] = 0
4602 13:42:59.807304 tx_first_pass[1][0][0] = 0
4603 13:42:59.807388 tx_last_pass[1][0][0] = 0
4604 13:42:59.810811 tx_win_center[1][0][1] = 0
4605 13:42:59.813796 tx_first_pass[1][0][1] = 0
4606 13:42:59.813881 tx_last_pass[1][0][1] = 0
4607 13:42:59.817247 tx_win_center[1][0][2] = 0
4608 13:42:59.820426 tx_first_pass[1][0][2] = 0
4609 13:42:59.823646 tx_last_pass[1][0][2] = 0
4610 13:42:59.823729 tx_win_center[1][0][3] = 0
4611 13:42:59.826962 tx_first_pass[1][0][3] = 0
4612 13:42:59.830136 tx_last_pass[1][0][3] = 0
4613 13:42:59.833302 tx_win_center[1][0][4] = 0
4614 13:42:59.833396 tx_first_pass[1][0][4] = 0
4615 13:42:59.836640 tx_last_pass[1][0][4] = 0
4616 13:42:59.839873 tx_win_center[1][0][5] = 0
4617 13:42:59.843431 tx_first_pass[1][0][5] = 0
4618 13:42:59.843519 tx_last_pass[1][0][5] = 0
4619 13:42:59.846469 tx_win_center[1][0][6] = 0
4620 13:42:59.849851 tx_first_pass[1][0][6] = 0
4621 13:42:59.853032 tx_last_pass[1][0][6] = 0
4622 13:42:59.853118 tx_win_center[1][0][7] = 0
4623 13:42:59.856544 tx_first_pass[1][0][7] = 0
4624 13:42:59.859560 tx_last_pass[1][0][7] = 0
4625 13:42:59.859645 tx_win_center[1][0][8] = 0
4626 13:42:59.863067 tx_first_pass[1][0][8] = 0
4627 13:42:59.866463 tx_last_pass[1][0][8] = 0
4628 13:42:59.869557 tx_win_center[1][0][9] = 0
4629 13:42:59.869642 tx_first_pass[1][0][9] = 0
4630 13:42:59.872973 tx_last_pass[1][0][9] = 0
4631 13:42:59.876121 tx_win_center[1][0][10] = 0
4632 13:42:59.879288 tx_first_pass[1][0][10] = 0
4633 13:42:59.879399 tx_last_pass[1][0][10] = 0
4634 13:42:59.882570 tx_win_center[1][0][11] = 0
4635 13:42:59.886020 tx_first_pass[1][0][11] = 0
4636 13:42:59.889170 tx_last_pass[1][0][11] = 0
4637 13:42:59.892408 tx_win_center[1][0][12] = 0
4638 13:42:59.892493 tx_first_pass[1][0][12] = 0
4639 13:42:59.895947 tx_last_pass[1][0][12] = 0
4640 13:42:59.899067 tx_win_center[1][0][13] = 0
4641 13:42:59.902247 tx_first_pass[1][0][13] = 0
4642 13:42:59.902332 tx_last_pass[1][0][13] = 0
4643 13:42:59.905802 tx_win_center[1][0][14] = 0
4644 13:42:59.908871 tx_first_pass[1][0][14] = 0
4645 13:42:59.911987 tx_last_pass[1][0][14] = 0
4646 13:42:59.912072 tx_win_center[1][0][15] = 0
4647 13:42:59.915415 tx_first_pass[1][0][15] = 0
4648 13:42:59.918540 tx_last_pass[1][0][15] = 0
4649 13:42:59.921963 tx_win_center[1][1][0] = 0
4650 13:42:59.922049 tx_first_pass[1][1][0] = 0
4651 13:42:59.925234 tx_last_pass[1][1][0] = 0
4652 13:42:59.928674 tx_win_center[1][1][1] = 0
4653 13:42:59.931852 tx_first_pass[1][1][1] = 0
4654 13:42:59.931937 tx_last_pass[1][1][1] = 0
4655 13:42:59.935217 tx_win_center[1][1][2] = 0
4656 13:42:59.938218 tx_first_pass[1][1][2] = 0
4657 13:42:59.941648 tx_last_pass[1][1][2] = 0
4658 13:42:59.941733 tx_win_center[1][1][3] = 0
4659 13:42:59.945022 tx_first_pass[1][1][3] = 0
4660 13:42:59.948068 tx_last_pass[1][1][3] = 0
4661 13:42:59.948152 tx_win_center[1][1][4] = 0
4662 13:42:59.951244 tx_first_pass[1][1][4] = 0
4663 13:42:59.954863 tx_last_pass[1][1][4] = 0
4664 13:42:59.958065 tx_win_center[1][1][5] = 0
4665 13:42:59.958150 tx_first_pass[1][1][5] = 0
4666 13:42:59.961294 tx_last_pass[1][1][5] = 0
4667 13:42:59.964625 tx_win_center[1][1][6] = 0
4668 13:42:59.968157 tx_first_pass[1][1][6] = 0
4669 13:42:59.968241 tx_last_pass[1][1][6] = 0
4670 13:42:59.971225 tx_win_center[1][1][7] = 0
4671 13:42:59.974255 tx_first_pass[1][1][7] = 0
4672 13:42:59.977796 tx_last_pass[1][1][7] = 0
4673 13:42:59.977881 tx_win_center[1][1][8] = 0
4674 13:42:59.980723 tx_first_pass[1][1][8] = 0
4675 13:42:59.984267 tx_last_pass[1][1][8] = 0
4676 13:42:59.987431 tx_win_center[1][1][9] = 0
4677 13:42:59.987522 tx_first_pass[1][1][9] = 0
4678 13:42:59.990532 tx_last_pass[1][1][9] = 0
4679 13:42:59.994031 tx_win_center[1][1][10] = 0
4680 13:42:59.997171 tx_first_pass[1][1][10] = 0
4681 13:42:59.997256 tx_last_pass[1][1][10] = 0
4682 13:43:00.000380 tx_win_center[1][1][11] = 0
4683 13:43:00.003896 tx_first_pass[1][1][11] = 0
4684 13:43:00.007053 tx_last_pass[1][1][11] = 0
4685 13:43:00.007137 tx_win_center[1][1][12] = 0
4686 13:43:00.010131 tx_first_pass[1][1][12] = 0
4687 13:43:00.013628 tx_last_pass[1][1][12] = 0
4688 13:43:00.016930 tx_win_center[1][1][13] = 0
4689 13:43:00.017016 tx_first_pass[1][1][13] = 0
4690 13:43:00.020119 tx_last_pass[1][1][13] = 0
4691 13:43:00.023280 tx_win_center[1][1][14] = 0
4692 13:43:00.026438 tx_first_pass[1][1][14] = 0
4693 13:43:00.026522 tx_last_pass[1][1][14] = 0
4694 13:43:00.030009 tx_win_center[1][1][15] = 0
4695 13:43:00.033087 tx_first_pass[1][1][15] = 0
4696 13:43:00.036674 tx_last_pass[1][1][15] = 0
4697 13:43:00.036759 dump params rx window
4698 13:43:00.039702 rx_firspass[0][0][0] = 0
4699 13:43:00.043042 rx_lastpass[0][0][0] = 0
4700 13:43:00.043127 rx_firspass[0][0][1] = 0
4701 13:43:00.046539 rx_lastpass[0][0][1] = 0
4702 13:43:00.049437 rx_firspass[0][0][2] = 0
4703 13:43:00.052827 rx_lastpass[0][0][2] = 0
4704 13:43:00.052912 rx_firspass[0][0][3] = 0
4705 13:43:00.056057 rx_lastpass[0][0][3] = 0
4706 13:43:00.059609 rx_firspass[0][0][4] = 0
4707 13:43:00.059694 rx_lastpass[0][0][4] = 0
4708 13:43:00.062858 rx_firspass[0][0][5] = 0
4709 13:43:00.066005 rx_lastpass[0][0][5] = 0
4710 13:43:00.066090 rx_firspass[0][0][6] = 0
4711 13:43:00.069234 rx_lastpass[0][0][6] = 0
4712 13:43:00.072718 rx_firspass[0][0][7] = 0
4713 13:43:00.075872 rx_lastpass[0][0][7] = 0
4714 13:43:00.075956 rx_firspass[0][0][8] = 0
4715 13:43:00.079156 rx_lastpass[0][0][8] = 0
4716 13:43:00.082290 rx_firspass[0][0][9] = 0
4717 13:43:00.082374 rx_lastpass[0][0][9] = 0
4718 13:43:00.085540 rx_firspass[0][0][10] = 0
4719 13:43:00.089013 rx_lastpass[0][0][10] = 0
4720 13:43:00.089098 rx_firspass[0][0][11] = 0
4721 13:43:00.091996 rx_lastpass[0][0][11] = 0
4722 13:43:00.095345 rx_firspass[0][0][12] = 0
4723 13:43:00.098526 rx_lastpass[0][0][12] = 0
4724 13:43:00.098637 rx_firspass[0][0][13] = 0
4725 13:43:00.102119 rx_lastpass[0][0][13] = 0
4726 13:43:00.105347 rx_firspass[0][0][14] = 0
4727 13:43:00.108553 rx_lastpass[0][0][14] = 0
4728 13:43:00.108637 rx_firspass[0][0][15] = 0
4729 13:43:00.111776 rx_lastpass[0][0][15] = 0
4730 13:43:00.114938 rx_firspass[0][1][0] = 0
4731 13:43:00.115049 rx_lastpass[0][1][0] = 0
4732 13:43:00.118169 rx_firspass[0][1][1] = 0
4733 13:43:00.121491 rx_lastpass[0][1][1] = 0
4734 13:43:00.121603 rx_firspass[0][1][2] = 0
4735 13:43:00.124765 rx_lastpass[0][1][2] = 0
4736 13:43:00.127977 rx_firspass[0][1][3] = 0
4737 13:43:00.131233 rx_lastpass[0][1][3] = 0
4738 13:43:00.131317 rx_firspass[0][1][4] = 0
4739 13:43:00.134803 rx_lastpass[0][1][4] = 0
4740 13:43:00.137839 rx_firspass[0][1][5] = 0
4741 13:43:00.137924 rx_lastpass[0][1][5] = 0
4742 13:43:00.141296 rx_firspass[0][1][6] = 0
4743 13:43:00.144566 rx_lastpass[0][1][6] = 0
4744 13:43:00.144650 rx_firspass[0][1][7] = 0
4745 13:43:00.147505 rx_lastpass[0][1][7] = 0
4746 13:43:00.150888 rx_firspass[0][1][8] = 0
4747 13:43:00.154092 rx_lastpass[0][1][8] = 0
4748 13:43:00.154177 rx_firspass[0][1][9] = 0
4749 13:43:00.157598 rx_lastpass[0][1][9] = 0
4750 13:43:00.160936 rx_firspass[0][1][10] = 0
4751 13:43:00.161021 rx_lastpass[0][1][10] = 0
4752 13:43:00.164216 rx_firspass[0][1][11] = 0
4753 13:43:00.167374 rx_lastpass[0][1][11] = 0
4754 13:43:00.170406 rx_firspass[0][1][12] = 0
4755 13:43:00.170491 rx_lastpass[0][1][12] = 0
4756 13:43:00.173659 rx_firspass[0][1][13] = 0
4757 13:43:00.177044 rx_lastpass[0][1][13] = 0
4758 13:43:00.177129 rx_firspass[0][1][14] = 0
4759 13:43:00.180573 rx_lastpass[0][1][14] = 0
4760 13:43:00.183590 rx_firspass[0][1][15] = 0
4761 13:43:00.187039 rx_lastpass[0][1][15] = 0
4762 13:43:00.187123 rx_firspass[1][0][0] = 0
4763 13:43:00.190149 rx_lastpass[1][0][0] = 0
4764 13:43:00.193700 rx_firspass[1][0][1] = 0
4765 13:43:00.193783 rx_lastpass[1][0][1] = 0
4766 13:43:00.196626 rx_firspass[1][0][2] = 0
4767 13:43:00.200121 rx_lastpass[1][0][2] = 0
4768 13:43:00.203256 rx_firspass[1][0][3] = 0
4769 13:43:00.203340 rx_lastpass[1][0][3] = 0
4770 13:43:00.206528 rx_firspass[1][0][4] = 0
4771 13:43:00.209713 rx_lastpass[1][0][4] = 0
4772 13:43:00.209798 rx_firspass[1][0][5] = 0
4773 13:43:00.213335 rx_lastpass[1][0][5] = 0
4774 13:43:00.216548 rx_firspass[1][0][6] = 0
4775 13:43:00.216633 rx_lastpass[1][0][6] = 0
4776 13:43:00.219809 rx_firspass[1][0][7] = 0
4777 13:43:00.222864 rx_lastpass[1][0][7] = 0
4778 13:43:00.226272 rx_firspass[1][0][8] = 0
4779 13:43:00.226358 rx_lastpass[1][0][8] = 0
4780 13:43:00.229547 rx_firspass[1][0][9] = 0
4781 13:43:00.232825 rx_lastpass[1][0][9] = 0
4782 13:43:00.232910 rx_firspass[1][0][10] = 0
4783 13:43:00.235978 rx_lastpass[1][0][10] = 0
4784 13:43:00.239205 rx_firspass[1][0][11] = 0
4785 13:43:00.242384 rx_lastpass[1][0][11] = 0
4786 13:43:00.242469 rx_firspass[1][0][12] = 0
4787 13:43:00.245749 rx_lastpass[1][0][12] = 0
4788 13:43:00.249002 rx_firspass[1][0][13] = 0
4789 13:43:00.249087 rx_lastpass[1][0][13] = 0
4790 13:43:00.252415 rx_firspass[1][0][14] = 0
4791 13:43:00.255705 rx_lastpass[1][0][14] = 0
4792 13:43:00.258879 rx_firspass[1][0][15] = 0
4793 13:43:00.258963 rx_lastpass[1][0][15] = 0
4794 13:43:00.262081 rx_firspass[1][1][0] = 0
4795 13:43:00.265265 rx_lastpass[1][1][0] = 0
4796 13:43:00.265349 rx_firspass[1][1][1] = 0
4797 13:43:00.268782 rx_lastpass[1][1][1] = 0
4798 13:43:00.272075 rx_firspass[1][1][2] = 0
4799 13:43:00.275314 rx_lastpass[1][1][2] = 0
4800 13:43:00.275424 rx_firspass[1][1][3] = 0
4801 13:43:00.278457 rx_lastpass[1][1][3] = 0
4802 13:43:00.281920 rx_firspass[1][1][4] = 0
4803 13:43:00.282004 rx_lastpass[1][1][4] = 0
4804 13:43:00.285067 rx_firspass[1][1][5] = 0
4805 13:43:00.288459 rx_lastpass[1][1][5] = 0
4806 13:43:00.288544 rx_firspass[1][1][6] = 0
4807 13:43:00.291716 rx_lastpass[1][1][6] = 0
4808 13:43:00.295195 rx_firspass[1][1][7] = 0
4809 13:43:00.295279 rx_lastpass[1][1][7] = 0
4810 13:43:00.297980 rx_firspass[1][1][8] = 0
4811 13:43:00.301402 rx_lastpass[1][1][8] = 0
4812 13:43:00.304921 rx_firspass[1][1][9] = 0
4813 13:43:00.305005 rx_lastpass[1][1][9] = 0
4814 13:43:00.308193 rx_firspass[1][1][10] = 0
4815 13:43:00.311217 rx_lastpass[1][1][10] = 0
4816 13:43:00.311301 rx_firspass[1][1][11] = 0
4817 13:43:00.314409 rx_lastpass[1][1][11] = 0
4818 13:43:00.317918 rx_firspass[1][1][12] = 0
4819 13:43:00.321114 rx_lastpass[1][1][12] = 0
4820 13:43:00.321202 rx_firspass[1][1][13] = 0
4821 13:43:00.324391 rx_lastpass[1][1][13] = 0
4822 13:43:00.327588 rx_firspass[1][1][14] = 0
4823 13:43:00.331075 rx_lastpass[1][1][14] = 0
4824 13:43:00.331157 rx_firspass[1][1][15] = 0
4825 13:43:00.334260 rx_lastpass[1][1][15] = 0
4826 13:43:00.337630 dump params clk_delay
4827 13:43:00.337715 clk_delay[0] = 0
4828 13:43:00.340867 clk_delay[1] = 0
4829 13:43:00.340951 dump params dqs_delay
4830 13:43:00.344066 dqs_delay[0][0] = 0
4831 13:43:00.344151 dqs_delay[0][1] = 0
4832 13:43:00.347213 dqs_delay[1][0] = 0
4833 13:43:00.347330 dqs_delay[1][1] = 0
4834 13:43:00.350504 dump params delay_cell_unit = 744
4835 13:43:00.353842 dump source = 0x0
4836 13:43:00.353928 dump params frequency:800
4837 13:43:00.357026 dump params rank number:2
4838 13:43:00.357111
4839 13:43:00.360199 dump params write leveling
4840 13:43:00.363495 write leveling[0][0][0] = 0x0
4841 13:43:00.366781 write leveling[0][0][1] = 0x0
4842 13:43:00.366894 write leveling[0][1][0] = 0x0
4843 13:43:00.370042 write leveling[0][1][1] = 0x0
4844 13:43:00.373245 write leveling[1][0][0] = 0x0
4845 13:43:00.376834 write leveling[1][0][1] = 0x0
4846 13:43:00.379839 write leveling[1][1][0] = 0x0
4847 13:43:00.383165 write leveling[1][1][1] = 0x0
4848 13:43:00.383278 dump params cbt_cs
4849 13:43:00.386424 cbt_cs[0][0] = 0x0
4850 13:43:00.386528 cbt_cs[0][1] = 0x0
4851 13:43:00.389988 cbt_cs[1][0] = 0x0
4852 13:43:00.390096 cbt_cs[1][1] = 0x0
4853 13:43:00.392911 dump params cbt_mr12
4854 13:43:00.393031 cbt_mr12[0][0] = 0x0
4855 13:43:00.396580 cbt_mr12[0][1] = 0x0
4856 13:43:00.396688 cbt_mr12[1][0] = 0x0
4857 13:43:00.399523 cbt_mr12[1][1] = 0x0
4858 13:43:00.402734 dump params tx window
4859 13:43:00.402808 tx_center_min[0][0][0] = 0
4860 13:43:00.406312 tx_center_max[0][0][0] = 0
4861 13:43:00.409544 tx_center_min[0][0][1] = 0
4862 13:43:00.412889 tx_center_max[0][0][1] = 0
4863 13:43:00.412983 tx_center_min[0][1][0] = 0
4864 13:43:00.415848 tx_center_max[0][1][0] = 0
4865 13:43:00.419185 tx_center_min[0][1][1] = 0
4866 13:43:00.422349 tx_center_max[0][1][1] = 0
4867 13:43:00.422465 tx_center_min[1][0][0] = 0
4868 13:43:00.425887 tx_center_max[1][0][0] = 0
4869 13:43:00.429194 tx_center_min[1][0][1] = 0
4870 13:43:00.432310 tx_center_max[1][0][1] = 0
4871 13:43:00.432389 tx_center_min[1][1][0] = 0
4872 13:43:00.435806 tx_center_max[1][1][0] = 0
4873 13:43:00.438989 tx_center_min[1][1][1] = 0
4874 13:43:00.442208 tx_center_max[1][1][1] = 0
4875 13:43:00.442304 dump params tx window
4876 13:43:00.445302 tx_win_center[0][0][0] = 0
4877 13:43:00.448534 tx_first_pass[0][0][0] = 0
4878 13:43:00.448620 tx_last_pass[0][0][0] = 0
4879 13:43:00.452022 tx_win_center[0][0][1] = 0
4880 13:43:00.455242 tx_first_pass[0][0][1] = 0
4881 13:43:00.458492 tx_last_pass[0][0][1] = 0
4882 13:43:00.458604 tx_win_center[0][0][2] = 0
4883 13:43:00.461754 tx_first_pass[0][0][2] = 0
4884 13:43:00.464979 tx_last_pass[0][0][2] = 0
4885 13:43:00.468144 tx_win_center[0][0][3] = 0
4886 13:43:00.468259 tx_first_pass[0][0][3] = 0
4887 13:43:00.471925 tx_last_pass[0][0][3] = 0
4888 13:43:00.475002 tx_win_center[0][0][4] = 0
4889 13:43:00.478019 tx_first_pass[0][0][4] = 0
4890 13:43:00.478133 tx_last_pass[0][0][4] = 0
4891 13:43:00.481591 tx_win_center[0][0][5] = 0
4892 13:43:00.484538 tx_first_pass[0][0][5] = 0
4893 13:43:00.488137 tx_last_pass[0][0][5] = 0
4894 13:43:00.488224 tx_win_center[0][0][6] = 0
4895 13:43:00.491238 tx_first_pass[0][0][6] = 0
4896 13:43:00.494604 tx_last_pass[0][0][6] = 0
4897 13:43:00.494689 tx_win_center[0][0][7] = 0
4898 13:43:00.497851 tx_first_pass[0][0][7] = 0
4899 13:43:00.501051 tx_last_pass[0][0][7] = 0
4900 13:43:00.504405 tx_win_center[0][0][8] = 0
4901 13:43:00.504491 tx_first_pass[0][0][8] = 0
4902 13:43:00.507731 tx_last_pass[0][0][8] = 0
4903 13:43:00.510907 tx_win_center[0][0][9] = 0
4904 13:43:00.514217 tx_first_pass[0][0][9] = 0
4905 13:43:00.514308 tx_last_pass[0][0][9] = 0
4906 13:43:00.517273 tx_win_center[0][0][10] = 0
4907 13:43:00.520561 tx_first_pass[0][0][10] = 0
4908 13:43:00.523717 tx_last_pass[0][0][10] = 0
4909 13:43:00.523809 tx_win_center[0][0][11] = 0
4910 13:43:00.526991 tx_first_pass[0][0][11] = 0
4911 13:43:00.530242 tx_last_pass[0][0][11] = 0
4912 13:43:00.533481 tx_win_center[0][0][12] = 0
4913 13:43:00.536922 tx_first_pass[0][0][12] = 0
4914 13:43:00.537007 tx_last_pass[0][0][12] = 0
4915 13:43:00.540227 tx_win_center[0][0][13] = 0
4916 13:43:00.543665 tx_first_pass[0][0][13] = 0
4917 13:43:00.546896 tx_last_pass[0][0][13] = 0
4918 13:43:00.546981 tx_win_center[0][0][14] = 0
4919 13:43:00.550019 tx_first_pass[0][0][14] = 0
4920 13:43:00.553174 tx_last_pass[0][0][14] = 0
4921 13:43:00.556569 tx_win_center[0][0][15] = 0
4922 13:43:00.556646 tx_first_pass[0][0][15] = 0
4923 13:43:00.559644 tx_last_pass[0][0][15] = 0
4924 13:43:00.563323 tx_win_center[0][1][0] = 0
4925 13:43:00.566567 tx_first_pass[0][1][0] = 0
4926 13:43:00.566638 tx_last_pass[0][1][0] = 0
4927 13:43:00.569751 tx_win_center[0][1][1] = 0
4928 13:43:00.573120 tx_first_pass[0][1][1] = 0
4929 13:43:00.576183 tx_last_pass[0][1][1] = 0
4930 13:43:00.576268 tx_win_center[0][1][2] = 0
4931 13:43:00.579410 tx_first_pass[0][1][2] = 0
4932 13:43:00.582713 tx_last_pass[0][1][2] = 0
4933 13:43:00.586186 tx_win_center[0][1][3] = 0
4934 13:43:00.586271 tx_first_pass[0][1][3] = 0
4935 13:43:00.589236 tx_last_pass[0][1][3] = 0
4936 13:43:00.592631 tx_win_center[0][1][4] = 0
4937 13:43:00.595756 tx_first_pass[0][1][4] = 0
4938 13:43:00.595852 tx_last_pass[0][1][4] = 0
4939 13:43:00.598978 tx_win_center[0][1][5] = 0
4940 13:43:00.602292 tx_first_pass[0][1][5] = 0
4941 13:43:00.602378 tx_last_pass[0][1][5] = 0
4942 13:43:00.605670 tx_win_center[0][1][6] = 0
4943 13:43:00.608969 tx_first_pass[0][1][6] = 0
4944 13:43:00.612099 tx_last_pass[0][1][6] = 0
4945 13:43:00.612211 tx_win_center[0][1][7] = 0
4946 13:43:00.615835 tx_first_pass[0][1][7] = 0
4947 13:43:00.618699 tx_last_pass[0][1][7] = 0
4948 13:43:00.622110 tx_win_center[0][1][8] = 0
4949 13:43:00.622223 tx_first_pass[0][1][8] = 0
4950 13:43:00.625375 tx_last_pass[0][1][8] = 0
4951 13:43:00.628568 tx_win_center[0][1][9] = 0
4952 13:43:00.631968 tx_first_pass[0][1][9] = 0
4953 13:43:00.632054 tx_last_pass[0][1][9] = 0
4954 13:43:00.635323 tx_win_center[0][1][10] = 0
4955 13:43:00.638407 tx_first_pass[0][1][10] = 0
4956 13:43:00.641705 tx_last_pass[0][1][10] = 0
4957 13:43:00.641791 tx_win_center[0][1][11] = 0
4958 13:43:00.645060 tx_first_pass[0][1][11] = 0
4959 13:43:00.648139 tx_last_pass[0][1][11] = 0
4960 13:43:00.651432 tx_win_center[0][1][12] = 0
4961 13:43:00.651527 tx_first_pass[0][1][12] = 0
4962 13:43:00.654586 tx_last_pass[0][1][12] = 0
4963 13:43:00.658205 tx_win_center[0][1][13] = 0
4964 13:43:00.661276 tx_first_pass[0][1][13] = 0
4965 13:43:00.661362 tx_last_pass[0][1][13] = 0
4966 13:43:00.664452 tx_win_center[0][1][14] = 0
4967 13:43:00.667748 tx_first_pass[0][1][14] = 0
4968 13:43:00.671018 tx_last_pass[0][1][14] = 0
4969 13:43:00.674203 tx_win_center[0][1][15] = 0
4970 13:43:00.674292 tx_first_pass[0][1][15] = 0
4971 13:43:00.677506 tx_last_pass[0][1][15] = 0
4972 13:43:00.680760 tx_win_center[1][0][0] = 0
4973 13:43:00.684251 tx_first_pass[1][0][0] = 0
4974 13:43:00.684343 tx_last_pass[1][0][0] = 0
4975 13:43:00.687586 tx_win_center[1][0][1] = 0
4976 13:43:00.690543 tx_first_pass[1][0][1] = 0
4977 13:43:00.690628 tx_last_pass[1][0][1] = 0
4978 13:43:00.694026 tx_win_center[1][0][2] = 0
4979 13:43:00.697338 tx_first_pass[1][0][2] = 0
4980 13:43:00.700656 tx_last_pass[1][0][2] = 0
4981 13:43:00.700742 tx_win_center[1][0][3] = 0
4982 13:43:00.704013 tx_first_pass[1][0][3] = 0
4983 13:43:00.707155 tx_last_pass[1][0][3] = 0
4984 13:43:00.710406 tx_win_center[1][0][4] = 0
4985 13:43:00.710491 tx_first_pass[1][0][4] = 0
4986 13:43:00.713552 tx_last_pass[1][0][4] = 0
4987 13:43:00.717084 tx_win_center[1][0][5] = 0
4988 13:43:00.720179 tx_first_pass[1][0][5] = 0
4989 13:43:00.720264 tx_last_pass[1][0][5] = 0
4990 13:43:00.723770 tx_win_center[1][0][6] = 0
4991 13:43:00.726819 tx_first_pass[1][0][6] = 0
4992 13:43:00.730098 tx_last_pass[1][0][6] = 0
4993 13:43:00.730183 tx_win_center[1][0][7] = 0
4994 13:43:00.733467 tx_first_pass[1][0][7] = 0
4995 13:43:00.736735 tx_last_pass[1][0][7] = 0
4996 13:43:00.736821 tx_win_center[1][0][8] = 0
4997 13:43:00.739909 tx_first_pass[1][0][8] = 0
4998 13:43:00.743032 tx_last_pass[1][0][8] = 0
4999 13:43:00.746548 tx_win_center[1][0][9] = 0
5000 13:43:00.746651 tx_first_pass[1][0][9] = 0
5001 13:43:00.749574 tx_last_pass[1][0][9] = 0
5002 13:43:00.752802 tx_win_center[1][0][10] = 0
5003 13:43:00.756158 tx_first_pass[1][0][10] = 0
5004 13:43:00.756243 tx_last_pass[1][0][10] = 0
5005 13:43:00.759337 tx_win_center[1][0][11] = 0
5006 13:43:00.762672 tx_first_pass[1][0][11] = 0
5007 13:43:00.765913 tx_last_pass[1][0][11] = 0
5008 13:43:00.769457 tx_win_center[1][0][12] = 0
5009 13:43:00.769544 tx_first_pass[1][0][12] = 0
5010 13:43:00.772625 tx_last_pass[1][0][12] = 0
5011 13:43:00.775805 tx_win_center[1][0][13] = 0
5012 13:43:00.778901 tx_first_pass[1][0][13] = 0
5013 13:43:00.778986 tx_last_pass[1][0][13] = 0
5014 13:43:00.782443 tx_win_center[1][0][14] = 0
5015 13:43:00.785589 tx_first_pass[1][0][14] = 0
5016 13:43:00.788820 tx_last_pass[1][0][14] = 0
5017 13:43:00.788905 tx_win_center[1][0][15] = 0
5018 13:43:00.792135 tx_first_pass[1][0][15] = 0
5019 13:43:00.795296 tx_last_pass[1][0][15] = 0
5020 13:43:00.798666 tx_win_center[1][1][0] = 0
5021 13:43:00.798751 tx_first_pass[1][1][0] = 0
5022 13:43:00.801884 tx_last_pass[1][1][0] = 0
5023 13:43:00.805025 tx_win_center[1][1][1] = 0
5024 13:43:00.808669 tx_first_pass[1][1][1] = 0
5025 13:43:00.808754 tx_last_pass[1][1][1] = 0
5026 13:43:00.811583 tx_win_center[1][1][2] = 0
5027 13:43:00.815028 tx_first_pass[1][1][2] = 0
5028 13:43:00.818211 tx_last_pass[1][1][2] = 0
5029 13:43:00.818297 tx_win_center[1][1][3] = 0
5030 13:43:00.821459 tx_first_pass[1][1][3] = 0
5031 13:43:00.824722 tx_last_pass[1][1][3] = 0
5032 13:43:00.824807 tx_win_center[1][1][4] = 0
5033 13:43:00.828270 tx_first_pass[1][1][4] = 0
5034 13:43:00.831329 tx_last_pass[1][1][4] = 0
5035 13:43:00.834885 tx_win_center[1][1][5] = 0
5036 13:43:00.834971 tx_first_pass[1][1][5] = 0
5037 13:43:00.838028 tx_last_pass[1][1][5] = 0
5038 13:43:00.841422 tx_win_center[1][1][6] = 0
5039 13:43:00.844487 tx_first_pass[1][1][6] = 0
5040 13:43:00.844571 tx_last_pass[1][1][6] = 0
5041 13:43:00.847808 tx_win_center[1][1][7] = 0
5042 13:43:00.851211 tx_first_pass[1][1][7] = 0
5043 13:43:00.854452 tx_last_pass[1][1][7] = 0
5044 13:43:00.854537 tx_win_center[1][1][8] = 0
5045 13:43:00.857564 tx_first_pass[1][1][8] = 0
5046 13:43:00.860985 tx_last_pass[1][1][8] = 0
5047 13:43:00.864077 tx_win_center[1][1][9] = 0
5048 13:43:00.864162 tx_first_pass[1][1][9] = 0
5049 13:43:00.867242 tx_last_pass[1][1][9] = 0
5050 13:43:00.870502 tx_win_center[1][1][10] = 0
5051 13:43:00.873951 tx_first_pass[1][1][10] = 0
5052 13:43:00.874036 tx_last_pass[1][1][10] = 0
5053 13:43:00.877219 tx_win_center[1][1][11] = 0
5054 13:43:00.880492 tx_first_pass[1][1][11] = 0
5055 13:43:00.883863 tx_last_pass[1][1][11] = 0
5056 13:43:00.883942 tx_win_center[1][1][12] = 0
5057 13:43:00.886891 tx_first_pass[1][1][12] = 0
5058 13:43:00.890498 tx_last_pass[1][1][12] = 0
5059 13:43:00.893572 tx_win_center[1][1][13] = 0
5060 13:43:00.893646 tx_first_pass[1][1][13] = 0
5061 13:43:00.896938 tx_last_pass[1][1][13] = 0
5062 13:43:00.900128 tx_win_center[1][1][14] = 0
5063 13:43:00.903556 tx_first_pass[1][1][14] = 0
5064 13:43:00.903629 tx_last_pass[1][1][14] = 0
5065 13:43:00.906485 tx_win_center[1][1][15] = 0
5066 13:43:00.910033 tx_first_pass[1][1][15] = 0
5067 13:43:00.913087 tx_last_pass[1][1][15] = 0
5068 13:43:00.913173 dump params rx window
5069 13:43:00.916663 rx_firspass[0][0][0] = 0
5070 13:43:00.919897 rx_lastpass[0][0][0] = 0
5071 13:43:00.919982 rx_firspass[0][0][1] = 0
5072 13:43:00.923059 rx_lastpass[0][0][1] = 0
5073 13:43:00.926218 rx_firspass[0][0][2] = 0
5074 13:43:00.929490 rx_lastpass[0][0][2] = 0
5075 13:43:00.929574 rx_firspass[0][0][3] = 0
5076 13:43:00.933113 rx_lastpass[0][0][3] = 0
5077 13:43:00.936262 rx_firspass[0][0][4] = 0
5078 13:43:00.936374 rx_lastpass[0][0][4] = 0
5079 13:43:00.939320 rx_firspass[0][0][5] = 0
5080 13:43:00.942562 rx_lastpass[0][0][5] = 0
5081 13:43:00.942648 rx_firspass[0][0][6] = 0
5082 13:43:00.946246 rx_lastpass[0][0][6] = 0
5083 13:43:00.949396 rx_firspass[0][0][7] = 0
5084 13:43:00.952523 rx_lastpass[0][0][7] = 0
5085 13:43:00.952609 rx_firspass[0][0][8] = 0
5086 13:43:00.955699 rx_lastpass[0][0][8] = 0
5087 13:43:00.959110 rx_firspass[0][0][9] = 0
5088 13:43:00.959194 rx_lastpass[0][0][9] = 0
5089 13:43:00.962329 rx_firspass[0][0][10] = 0
5090 13:43:00.965702 rx_lastpass[0][0][10] = 0
5091 13:43:00.965777 rx_firspass[0][0][11] = 0
5092 13:43:00.968660 rx_lastpass[0][0][11] = 0
5093 13:43:00.972034 rx_firspass[0][0][12] = 0
5094 13:43:00.975471 rx_lastpass[0][0][12] = 0
5095 13:43:00.975554 rx_firspass[0][0][13] = 0
5096 13:43:00.978600 rx_lastpass[0][0][13] = 0
5097 13:43:00.981970 rx_firspass[0][0][14] = 0
5098 13:43:00.985082 rx_lastpass[0][0][14] = 0
5099 13:43:00.985161 rx_firspass[0][0][15] = 0
5100 13:43:00.988604 rx_lastpass[0][0][15] = 0
5101 13:43:00.991761 rx_firspass[0][1][0] = 0
5102 13:43:00.991846 rx_lastpass[0][1][0] = 0
5103 13:43:00.994995 rx_firspass[0][1][1] = 0
5104 13:43:00.998392 rx_lastpass[0][1][1] = 0
5105 13:43:00.998514 rx_firspass[0][1][2] = 0
5106 13:43:01.001464 rx_lastpass[0][1][2] = 0
5107 13:43:01.004976 rx_firspass[0][1][3] = 0
5108 13:43:01.008195 rx_lastpass[0][1][3] = 0
5109 13:43:01.008280 rx_firspass[0][1][4] = 0
5110 13:43:01.011313 rx_lastpass[0][1][4] = 0
5111 13:43:01.014823 rx_firspass[0][1][5] = 0
5112 13:43:01.014907 rx_lastpass[0][1][5] = 0
5113 13:43:01.018102 rx_firspass[0][1][6] = 0
5114 13:43:01.021303 rx_lastpass[0][1][6] = 0
5115 13:43:01.021414 rx_firspass[0][1][7] = 0
5116 13:43:01.024630 rx_lastpass[0][1][7] = 0
5117 13:43:01.027801 rx_firspass[0][1][8] = 0
5118 13:43:01.030949 rx_lastpass[0][1][8] = 0
5119 13:43:01.031034 rx_firspass[0][1][9] = 0
5120 13:43:01.034193 rx_lastpass[0][1][9] = 0
5121 13:43:01.037756 rx_firspass[0][1][10] = 0
5122 13:43:01.037841 rx_lastpass[0][1][10] = 0
5123 13:43:01.041069 rx_firspass[0][1][11] = 0
5124 13:43:01.043978 rx_lastpass[0][1][11] = 0
5125 13:43:01.047604 rx_firspass[0][1][12] = 0
5126 13:43:01.047689 rx_lastpass[0][1][12] = 0
5127 13:43:01.050858 rx_firspass[0][1][13] = 0
5128 13:43:01.054074 rx_lastpass[0][1][13] = 0
5129 13:43:01.054170 rx_firspass[0][1][14] = 0
5130 13:43:01.057201 rx_lastpass[0][1][14] = 0
5131 13:43:01.060396 rx_firspass[0][1][15] = 0
5132 13:43:01.063970 rx_lastpass[0][1][15] = 0
5133 13:43:01.064049 rx_firspass[1][0][0] = 0
5134 13:43:01.067215 rx_lastpass[1][0][0] = 0
5135 13:43:01.070270 rx_firspass[1][0][1] = 0
5136 13:43:01.070346 rx_lastpass[1][0][1] = 0
5137 13:43:01.073450 rx_firspass[1][0][2] = 0
5138 13:43:01.077055 rx_lastpass[1][0][2] = 0
5139 13:43:01.080254 rx_firspass[1][0][3] = 0
5140 13:43:01.080328 rx_lastpass[1][0][3] = 0
5141 13:43:01.083267 rx_firspass[1][0][4] = 0
5142 13:43:01.086863 rx_lastpass[1][0][4] = 0
5143 13:43:01.086934 rx_firspass[1][0][5] = 0
5144 13:43:01.089945 rx_lastpass[1][0][5] = 0
5145 13:43:01.093316 rx_firspass[1][0][6] = 0
5146 13:43:01.093387 rx_lastpass[1][0][6] = 0
5147 13:43:01.096399 rx_firspass[1][0][7] = 0
5148 13:43:01.099638 rx_lastpass[1][0][7] = 0
5149 13:43:01.099710 rx_firspass[1][0][8] = 0
5150 13:43:01.103185 rx_lastpass[1][0][8] = 0
5151 13:43:01.106208 rx_firspass[1][0][9] = 0
5152 13:43:01.109469 rx_lastpass[1][0][9] = 0
5153 13:43:01.109555 rx_firspass[1][0][10] = 0
5154 13:43:01.113097 rx_lastpass[1][0][10] = 0
5155 13:43:01.116196 rx_firspass[1][0][11] = 0
5156 13:43:01.116281 rx_lastpass[1][0][11] = 0
5157 13:43:01.119390 rx_firspass[1][0][12] = 0
5158 13:43:01.122825 rx_lastpass[1][0][12] = 0
5159 13:43:01.125949 rx_firspass[1][0][13] = 0
5160 13:43:01.126033 rx_lastpass[1][0][13] = 0
5161 13:43:01.129248 rx_firspass[1][0][14] = 0
5162 13:43:01.132573 rx_lastpass[1][0][14] = 0
5163 13:43:01.135698 rx_firspass[1][0][15] = 0
5164 13:43:01.135783 rx_lastpass[1][0][15] = 0
5165 13:43:01.139218 rx_firspass[1][1][0] = 0
5166 13:43:01.142451 rx_lastpass[1][1][0] = 0
5167 13:43:01.142536 rx_firspass[1][1][1] = 0
5168 13:43:01.145664 rx_lastpass[1][1][1] = 0
5169 13:43:01.148803 rx_firspass[1][1][2] = 0
5170 13:43:01.148887 rx_lastpass[1][1][2] = 0
5171 13:43:01.152034 rx_firspass[1][1][3] = 0
5172 13:43:01.155598 rx_lastpass[1][1][3] = 0
5173 13:43:01.158941 rx_firspass[1][1][4] = 0
5174 13:43:01.159025 rx_lastpass[1][1][4] = 0
5175 13:43:01.162090 rx_firspass[1][1][5] = 0
5176 13:43:01.165294 rx_lastpass[1][1][5] = 0
5177 13:43:01.165379 rx_firspass[1][1][6] = 0
5178 13:43:01.168415 rx_lastpass[1][1][6] = 0
5179 13:43:01.171937 rx_firspass[1][1][7] = 0
5180 13:43:01.172023 rx_lastpass[1][1][7] = 0
5181 13:43:01.175004 rx_firspass[1][1][8] = 0
5182 13:43:01.178269 rx_lastpass[1][1][8] = 0
5183 13:43:01.181596 rx_firspass[1][1][9] = 0
5184 13:43:01.181681 rx_lastpass[1][1][9] = 0
5185 13:43:01.185150 rx_firspass[1][1][10] = 0
5186 13:43:01.188278 rx_lastpass[1][1][10] = 0
5187 13:43:01.188363 rx_firspass[1][1][11] = 0
5188 13:43:01.191392 rx_lastpass[1][1][11] = 0
5189 13:43:01.194902 rx_firspass[1][1][12] = 0
5190 13:43:01.198096 rx_lastpass[1][1][12] = 0
5191 13:43:01.198181 rx_firspass[1][1][13] = 0
5192 13:43:01.201490 rx_lastpass[1][1][13] = 0
5193 13:43:01.204741 rx_firspass[1][1][14] = 0
5194 13:43:01.204826 rx_lastpass[1][1][14] = 0
5195 13:43:01.207910 rx_firspass[1][1][15] = 0
5196 13:43:01.211205 rx_lastpass[1][1][15] = 0
5197 13:43:01.214341 dump params clk_delay
5198 13:43:01.214426 clk_delay[0] = 0
5199 13:43:01.214492 clk_delay[1] = 0
5200 13:43:01.217579 dump params dqs_delay
5201 13:43:01.221147 dqs_delay[0][0] = 0
5202 13:43:01.221233 dqs_delay[0][1] = 0
5203 13:43:01.224191 dqs_delay[1][0] = 0
5204 13:43:01.224276 dqs_delay[1][1] = 0
5205 13:43:01.227724 dump params delay_cell_unit = 744
5206 13:43:01.230864 mt_set_emi_preloader end
5207 13:43:01.234016 [mt_mem_init] dram size: 0x100000000, rank number: 2
5208 13:43:01.240372 [complex_mem_test] start addr:0x40000000, len:20480
5209 13:43:01.276077 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5210 13:43:01.282469 [complex_mem_test] start addr:0x80000000, len:20480
5211 13:43:01.318571 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5212 13:43:01.325135 [complex_mem_test] start addr:0xc0000000, len:20480
5213 13:43:01.360914 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5214 13:43:01.367600 [complex_mem_test] start addr:0x56000000, len:8192
5215 13:43:01.384069 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5216 13:43:01.387270 ddr_geometry:1
5217 13:43:01.390544 [complex_mem_test] start addr:0x80000000, len:8192
5218 13:43:01.407818 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5219 13:43:01.410992 dram_init: dram init end (result: 0)
5220 13:43:01.417516 Successfully loaded DRAM blobs and ran DRAM calibration
5221 13:43:01.427802 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5222 13:43:01.427898 CBMEM:
5223 13:43:01.430700 IMD: root @ 00000000fffff000 254 entries.
5224 13:43:01.434241 IMD: root @ 00000000ffffec00 62 entries.
5225 13:43:01.440834 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5226 13:43:01.447124 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5227 13:43:01.450784 in-header: 03 a1 00 00 08 00 00 00
5228 13:43:01.453985 in-data: 84 60 60 10 00 00 00 00
5229 13:43:01.457093 Chrome EC: clear events_b mask to 0x0000000020004000
5230 13:43:01.463603 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5231 13:43:01.467294 in-header: 03 fd 00 00 00 00 00 00
5232 13:43:01.470395 in-data:
5233 13:43:01.473603 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5234 13:43:01.476822 CBFS @ 21000 size 3d4000
5235 13:43:01.480241 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5236 13:43:01.483344 CBFS: Locating 'fallback/ramstage'
5237 13:43:01.486535 CBFS: Found @ offset 10d40 size d563
5238 13:43:01.509663 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5239 13:43:01.521934 Accumulated console time in romstage 13599 ms
5240 13:43:01.522126
5241 13:43:01.522307
5242 13:43:01.531775 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5243 13:43:01.535120 ARM64: Exception handlers installed.
5244 13:43:01.535217 ARM64: Testing exception
5245 13:43:01.538177 ARM64: Done test exception
5246 13:43:01.541591 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5247 13:43:01.544643 Manufacturer: ef
5248 13:43:01.551220 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5249 13:43:01.554764 WARNING: RO_VPD is uninitialized or empty.
5250 13:43:01.557984 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5251 13:43:01.561093 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5252 13:43:01.571491 read SPI 0x550600 0x3a00: 4532 us, 3276 KB/s, 26.208 Mbps
5253 13:43:01.574900 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5254 13:43:01.581526 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5255 13:43:01.581645 Enumerating buses...
5256 13:43:01.587963 Show all devs... Before device enumeration.
5257 13:43:01.588049 Root Device: enabled 1
5258 13:43:01.591101 CPU_CLUSTER: 0: enabled 1
5259 13:43:01.594677 CPU: 00: enabled 1
5260 13:43:01.594761 Compare with tree...
5261 13:43:01.597913 Root Device: enabled 1
5262 13:43:01.597998 CPU_CLUSTER: 0: enabled 1
5263 13:43:01.601052 CPU: 00: enabled 1
5264 13:43:01.604441 Root Device scanning...
5265 13:43:01.607601 root_dev_scan_bus for Root Device
5266 13:43:01.607686 CPU_CLUSTER: 0 enabled
5267 13:43:01.610882 root_dev_scan_bus for Root Device done
5268 13:43:01.617600 scan_bus: scanning of bus Root Device took 10689 usecs
5269 13:43:01.617687 done
5270 13:43:01.620762 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5271 13:43:01.623797 Allocating resources...
5272 13:43:01.627312 Reading resources...
5273 13:43:01.630678 Root Device read_resources bus 0 link: 0
5274 13:43:01.633866 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5275 13:43:01.637001 CPU: 00 missing read_resources
5276 13:43:01.640386 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5277 13:43:01.643512 Root Device read_resources bus 0 link: 0 done
5278 13:43:01.646756 Done reading resources.
5279 13:43:01.650177 Show resources in subtree (Root Device)...After reading.
5280 13:43:01.656622 Root Device child on link 0 CPU_CLUSTER: 0
5281 13:43:01.660071 CPU_CLUSTER: 0 child on link 0 CPU: 00
5282 13:43:01.666390 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5283 13:43:01.670004 CPU: 00
5284 13:43:01.670097 Setting resources...
5285 13:43:01.676237 Root Device assign_resources, bus 0 link: 0
5286 13:43:01.679702 CPU_CLUSTER: 0 missing set_resources
5287 13:43:01.682760 Root Device assign_resources, bus 0 link: 0
5288 13:43:01.682847 Done setting resources.
5289 13:43:01.689644 Show resources in subtree (Root Device)...After assigning values.
5290 13:43:01.692895 Root Device child on link 0 CPU_CLUSTER: 0
5291 13:43:01.696030 CPU_CLUSTER: 0 child on link 0 CPU: 00
5292 13:43:01.705875 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5293 13:43:01.705965 CPU: 00
5294 13:43:01.709188 Done allocating resources.
5295 13:43:01.715759 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5296 13:43:01.715849 Enabling resources...
5297 13:43:01.715916 done.
5298 13:43:01.722388 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5299 13:43:01.722478 Initializing devices...
5300 13:43:01.725537 Root Device init ...
5301 13:43:01.728625 mainboard_init: Starting display init.
5302 13:43:01.731908 ADC[4]: Raw value=75836 ID=0
5303 13:43:01.754149 anx7625_power_on_init: Init interface.
5304 13:43:01.757809 anx7625_disable_pd_protocol: Disabled PD feature.
5305 13:43:01.764129 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5306 13:43:01.821370 anx7625_start_dp_work: Secure OCM version=00
5307 13:43:01.824516 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5308 13:43:01.841639 sp_tx_get_edid_block: EDID Block = 1
5309 13:43:01.959086 Extracted contents:
5310 13:43:01.962050 header: 00 ff ff ff ff ff ff 00
5311 13:43:01.965460 serial number: 06 af 5c 14 00 00 00 00 00 1a
5312 13:43:01.968791 version: 01 04
5313 13:43:01.971913 basic params: 95 1a 0e 78 02
5314 13:43:01.975207 chroma info: 99 85 95 55 56 92 28 22 50 54
5315 13:43:01.978367 established: 00 00 00
5316 13:43:01.984855 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5317 13:43:01.992005 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5318 13:43:01.998286 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5319 13:43:02.001397 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5320 13:43:02.007886 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5321 13:43:02.010992 extensions: 00
5322 13:43:02.011088 checksum: ae
5323 13:43:02.014438
5324 13:43:02.017488 Manufacturer: AUO Model 145c Serial Number 0
5325 13:43:02.017583 Made week 0 of 2016
5326 13:43:02.020843 EDID version: 1.4
5327 13:43:02.020940 Digital display
5328 13:43:02.024024 6 bits per primary color channel
5329 13:43:02.027376 DisplayPort interface
5330 13:43:02.030646 Maximum image size: 26 cm x 14 cm
5331 13:43:02.030742 Gamma: 220%
5332 13:43:02.030812 Check DPMS levels
5333 13:43:02.034170 Supported color formats: RGB 4:4:4
5334 13:43:02.040786 First detailed timing is preferred timing
5335 13:43:02.040904 Established timings supported:
5336 13:43:02.043892 Standard timings supported:
5337 13:43:02.047243 Detailed timings
5338 13:43:02.050394 Hex of detail: ce1d56ea50001a3030204600009010000018
5339 13:43:02.056800 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5340 13:43:02.060441 0556 0586 05a6 0640 hborder 0
5341 13:43:02.063644 0300 0304 030a 031a vborder 0
5342 13:43:02.066616 -hsync -vsync
5343 13:43:02.066712 Did detailed timing
5344 13:43:02.073070 Hex of detail: 0000000f0000000000000000000000000020
5345 13:43:02.076226 Manufacturer-specified data, tag 15
5346 13:43:02.079772 Hex of detail: 000000fe0041554f0a202020202020202020
5347 13:43:02.082875 ASCII string: AUO
5348 13:43:02.086058 Hex of detail: 000000fe004231313658414230312e34200a
5349 13:43:02.089647 ASCII string: B116XAB01.4
5350 13:43:02.089747 Checksum
5351 13:43:02.092711 Checksum: 0xae (valid)
5352 13:43:02.096043 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5353 13:43:02.099368 DSI data_rate: 457800000 bps
5354 13:43:02.105794 anx7625_parse_edid: set default k value to 0x3d for panel
5355 13:43:02.109355 anx7625_parse_edid: pixelclock(76300).
5356 13:43:02.112647 hactive(1366), hsync(32), hfp(48), hbp(154)
5357 13:43:02.115790 vactive(768), vsync(6), vfp(4), vbp(16)
5358 13:43:02.118968 anx7625_dsi_config: config dsi.
5359 13:43:02.127015 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5360 13:43:02.147890 anx7625_dsi_config: success to config DSI
5361 13:43:02.151237 anx7625_dp_start: MIPI phy setup OK.
5362 13:43:02.154849 [SSUSB] Setting up USB HOST controller...
5363 13:43:02.157978 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5364 13:43:02.161209 [SSUSB] phy power-on done.
5365 13:43:02.164786 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5366 13:43:02.167999 in-header: 03 fc 01 00 00 00 00 00
5367 13:43:02.168095 in-data:
5368 13:43:02.174866 handle_proto3_response: EC response with error code: 1
5369 13:43:02.174978 SPM: pcm index = 1
5370 13:43:02.181159 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5371 13:43:02.181257 CBFS @ 21000 size 3d4000
5372 13:43:02.187517 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5373 13:43:02.190851 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5374 13:43:02.194067 CBFS: Found @ offset 1e7c0 size 1026
5375 13:43:02.200924 read SPI 0x3f808 0x1026: 1271 us, 3252 KB/s, 26.016 Mbps
5376 13:43:02.204313 SPM: binary array size = 2988
5377 13:43:02.207677 SPM: version = pcm_allinone_v1.17.2_20180829
5378 13:43:02.210686 SPM binary loaded in 32 msecs
5379 13:43:02.219515 spm_kick_im_to_fetch: ptr = 000000004021eec2
5380 13:43:02.222583 spm_kick_im_to_fetch: len = 2988
5381 13:43:02.222686 SPM: spm_kick_pcm_to_run
5382 13:43:02.225734 SPM: spm_kick_pcm_to_run done
5383 13:43:02.229158 SPM: spm_init done in 52 msecs
5384 13:43:02.232245 Root Device init finished in 505257 usecs
5385 13:43:02.235690 CPU_CLUSTER: 0 init ...
5386 13:43:02.245334 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5387 13:43:02.248877 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5388 13:43:02.252009 CBFS @ 21000 size 3d4000
5389 13:43:02.255431 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5390 13:43:02.258645 CBFS: Locating 'sspm.bin'
5391 13:43:02.261899 CBFS: Found @ offset 208c0 size 41cb
5392 13:43:02.272398 read SPI 0x418f8 0x41cb: 5142 us, 3275 KB/s, 26.200 Mbps
5393 13:43:02.280399 CPU_CLUSTER: 0 init finished in 42799 usecs
5394 13:43:02.280522 Devices initialized
5395 13:43:02.283641 Show all devs... After init.
5396 13:43:02.286863 Root Device: enabled 1
5397 13:43:02.286952 CPU_CLUSTER: 0: enabled 1
5398 13:43:02.289994 CPU: 00: enabled 1
5399 13:43:02.293469 BS: BS_DEV_INIT times (ms): entry 0 run 234 exit 0
5400 13:43:02.299841 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5401 13:43:02.303340 ELOG: NV offset 0x558000 size 0x1000
5402 13:43:02.306298 read SPI 0x558000 0x1000: 1259 us, 3253 KB/s, 26.024 Mbps
5403 13:43:02.313060 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5404 13:43:02.319575 ELOG: Event(17) added with size 13 at 2024-07-18 13:43:02 UTC
5405 13:43:02.322954 out: cmd=0x121: 03 db 21 01 00 00 00 00
5406 13:43:02.326195 in-header: 03 e6 00 00 2c 00 00 00
5407 13:43:02.339294 in-data: 46 4b 00 00 00 00 00 00 02 10 00 00 06 80 00 00 68 7d 01 00 06 80 00 00 52 1e 06 00 06 80 00 00 e1 40 01 00 06 80 00 00 40 70 02 00
5408 13:43:02.342642 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5409 13:43:02.345739 in-header: 03 19 00 00 08 00 00 00
5410 13:43:02.349296 in-data: a2 e0 47 00 13 00 00 00
5411 13:43:02.352546 Chrome EC: UHEPI supported
5412 13:43:02.358719 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5413 13:43:02.362337 in-header: 03 e1 00 00 08 00 00 00
5414 13:43:02.365453 in-data: 84 20 60 10 00 00 00 00
5415 13:43:02.368587 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5416 13:43:02.375202 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5417 13:43:02.378754 in-header: 03 e1 00 00 08 00 00 00
5418 13:43:02.381888 in-data: 84 20 60 10 00 00 00 00
5419 13:43:02.388511 ELOG: Event(A1) added with size 10 at 2024-07-18 13:43:02 UTC
5420 13:43:02.394867 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5421 13:43:02.398076 ELOG: Event(A0) added with size 9 at 2024-07-18 13:43:02 UTC
5422 13:43:02.401224 elog_add_boot_reason: Logged dev mode boot
5423 13:43:02.404455 Finalize devices...
5424 13:43:02.408130 Devices finalized
5425 13:43:02.411336 BS: BS_POST_DEVICE times (ms): entry 2 run 0 exit 0
5426 13:43:02.414439 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5427 13:43:02.420923 ELOG: Event(91) added with size 10 at 2024-07-18 13:43:02 UTC
5428 13:43:02.424226 Writing coreboot table at 0xffeda000
5429 13:43:02.427465 0. 0000000000114000-000000000011efff: RAMSTAGE
5430 13:43:02.434308 1. 0000000040000000-000000004023cfff: RAMSTAGE
5431 13:43:02.437327 2. 000000004023d000-00000000545fffff: RAM
5432 13:43:02.440740 3. 0000000054600000-000000005465ffff: BL31
5433 13:43:02.443865 4. 0000000054660000-00000000ffed9fff: RAM
5434 13:43:02.450424 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5435 13:43:02.453642 6. 0000000100000000-000000013fffffff: RAM
5436 13:43:02.457040 Passing 5 GPIOs to payload:
5437 13:43:02.460167 NAME | PORT | POLARITY | VALUE
5438 13:43:02.466763 write protect | 0x00000096 | low | high
5439 13:43:02.470064 EC in RW | 0x000000b1 | high | undefined
5440 13:43:02.473504 EC interrupt | 0x00000097 | low | undefined
5441 13:43:02.480247 TPM interrupt | 0x00000099 | high | undefined
5442 13:43:02.483414 speaker enable | 0x000000af | high | undefined
5443 13:43:02.486566 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5444 13:43:02.489766 in-header: 03 f7 00 00 02 00 00 00
5445 13:43:02.492942 in-data: 04 00
5446 13:43:02.493021 Board ID: 4
5447 13:43:02.496345 ADC[3]: Raw value=215404 ID=1
5448 13:43:02.496435 RAM code: 1
5449 13:43:02.499569 SKU ID: 16
5450 13:43:02.502792 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5451 13:43:02.506282 CBFS @ 21000 size 3d4000
5452 13:43:02.509429 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5453 13:43:02.515804 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum db86
5454 13:43:02.519396 coreboot table: 940 bytes.
5455 13:43:02.522458 IMD ROOT 0. 00000000fffff000 00001000
5456 13:43:02.525834 IMD SMALL 1. 00000000ffffe000 00001000
5457 13:43:02.529028 CONSOLE 2. 00000000fffde000 00020000
5458 13:43:02.532472 FMAP 3. 00000000fffdd000 0000047c
5459 13:43:02.535609 TIME STAMP 4. 00000000fffdc000 00000910
5460 13:43:02.542320 RAMOOPS 5. 00000000ffedc000 00100000
5461 13:43:02.545383 COREBOOT 6. 00000000ffeda000 00002000
5462 13:43:02.545482 IMD small region:
5463 13:43:02.548784 IMD ROOT 0. 00000000ffffec00 00000400
5464 13:43:02.552095 VBOOT WORK 1. 00000000ffffeb00 00000100
5465 13:43:02.558274 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5466 13:43:02.561735 VPD 3. 00000000ffffea60 0000006c
5467 13:43:02.565053 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5468 13:43:02.571695 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5469 13:43:02.574983 in-header: 03 e1 00 00 08 00 00 00
5470 13:43:02.577978 in-data: 84 20 60 10 00 00 00 00
5471 13:43:02.584637 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5472 13:43:02.584755 CBFS @ 21000 size 3d4000
5473 13:43:02.591263 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5474 13:43:02.594458 CBFS: Locating 'fallback/payload'
5475 13:43:02.601964 CBFS: Found @ offset dc040 size 439a0
5476 13:43:02.689805 read SPI 0xfd078 0x439a0: 84379 us, 3281 KB/s, 26.248 Mbps
5477 13:43:02.693386 Checking segment from ROM address 0x0000000040003a00
5478 13:43:02.699726 Checking segment from ROM address 0x0000000040003a1c
5479 13:43:02.702854 Loading segment from ROM address 0x0000000040003a00
5480 13:43:02.706485 code (compression=0)
5481 13:43:02.716018 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5482 13:43:02.722765 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5483 13:43:02.726003 it's not compressed!
5484 13:43:02.729200 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5485 13:43:02.735758 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5486 13:43:02.744222 Loading segment from ROM address 0x0000000040003a1c
5487 13:43:02.747415 Entry Point 0x0000000080000000
5488 13:43:02.747558 Loaded segments
5489 13:43:02.754226 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5490 13:43:02.757220 Jumping to boot code at 0000000080000000(00000000ffeda000)
5491 13:43:02.767231 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5492 13:43:02.773581 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5493 13:43:02.773706 CBFS @ 21000 size 3d4000
5494 13:43:02.780356 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5495 13:43:02.783727 CBFS: Locating 'fallback/bl31'
5496 13:43:02.786842 CBFS: Found @ offset 36dc0 size 5820
5497 13:43:02.798178 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5498 13:43:02.801436 Checking segment from ROM address 0x0000000040003a00
5499 13:43:02.807803 Checking segment from ROM address 0x0000000040003a1c
5500 13:43:02.810917 Loading segment from ROM address 0x0000000040003a00
5501 13:43:02.814502 code (compression=1)
5502 13:43:02.824365 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5503 13:43:02.830845 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5504 13:43:02.830973 using LZMA
5505 13:43:02.839999 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5506 13:43:02.846297 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5507 13:43:02.849809 Loading segment from ROM address 0x0000000040003a1c
5508 13:43:02.853004 Entry Point 0x0000000054601000
5509 13:43:02.853098 Loaded segments
5510 13:43:02.856273 NOTICE: MT8183 bl31_setup
5511 13:43:02.863640 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5512 13:43:02.866978 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5513 13:43:02.870021 INFO: [DEVAPC] dump DEVAPC registers:
5514 13:43:02.880001 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5515 13:43:02.886605 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5516 13:43:02.896296 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5517 13:43:02.903119 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5518 13:43:02.912635 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5519 13:43:02.919344 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5520 13:43:02.929107 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5521 13:43:02.935481 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5522 13:43:02.945432 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5523 13:43:02.951865 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5524 13:43:02.962033 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5525 13:43:02.968395 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5526 13:43:02.978227 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5527 13:43:02.984862 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5528 13:43:02.991425 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5529 13:43:03.001152 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5530 13:43:03.007735 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5531 13:43:03.014319 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5532 13:43:03.020795 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5533 13:43:03.027356 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5534 13:43:03.037215 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5535 13:43:03.043575 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5536 13:43:03.047138 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5537 13:43:03.050299 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5538 13:43:03.053671 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5539 13:43:03.056862 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5540 13:43:03.060075 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5541 13:43:03.066532 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5542 13:43:03.069948 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5543 13:43:03.072919 WARNING: region 0:
5544 13:43:03.076209 WARNING: apc:0x168, sa:0x0, ea:0xfff
5545 13:43:03.079614 WARNING: region 1:
5546 13:43:03.082810 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5547 13:43:03.082909 WARNING: region 2:
5548 13:43:03.086144 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5549 13:43:03.089353 WARNING: region 3:
5550 13:43:03.092742 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5551 13:43:03.096100 WARNING: region 4:
5552 13:43:03.099333 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5553 13:43:03.099421 WARNING: region 5:
5554 13:43:03.102679 WARNING: apc:0x0, sa:0x0, ea:0x0
5555 13:43:03.105812 WARNING: region 6:
5556 13:43:03.109155 WARNING: apc:0x0, sa:0x0, ea:0x0
5557 13:43:03.109248 WARNING: region 7:
5558 13:43:03.112382 WARNING: apc:0x0, sa:0x0, ea:0x0
5559 13:43:03.118793 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5560 13:43:03.122299 INFO: SPM: enable SPMC mode
5561 13:43:03.125364 NOTICE: spm_boot_init() start
5562 13:43:03.128888 NOTICE: spm_boot_init() end
5563 13:43:03.131983 INFO: BL31: Initializing runtime services
5564 13:43:03.138608 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5565 13:43:03.141927 INFO: BL31: Preparing for EL3 exit to normal world
5566 13:43:03.145131 INFO: Entry point address = 0x80000000
5567 13:43:03.148226 INFO: SPSR = 0x8
5568 13:43:03.170111
5569 13:43:03.170258
5570 13:43:03.170327
5571 13:43:03.170847 end: 2.2.3 depthcharge-start (duration 00:00:24) [common]
5572 13:43:03.170950 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
5573 13:43:03.171033 Setting prompt string to ['jacuzzi:']
5574 13:43:03.171106 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:27)
5575 13:43:03.173574 Starting depthcharge on Juniper...
5576 13:43:03.173663
5577 13:43:03.176645 vboot_handoff: creating legacy vboot_handoff structure
5578 13:43:03.176735
5579 13:43:03.180093 ec_init(0): CrosEC protocol v3 supported (544, 544)
5580 13:43:03.183297
5581 13:43:03.183387 Wipe memory regions:
5582 13:43:03.183464
5583 13:43:03.186460 [0x00000040000000, 0x00000054600000)
5584 13:43:03.229696
5585 13:43:03.229842 [0x00000054660000, 0x00000080000000)
5586 13:43:03.321059
5587 13:43:03.321208 [0x000000811994a0, 0x000000ffeda000)
5588 13:43:03.580592
5589 13:43:03.580795 [0x00000100000000, 0x00000140000000)
5590 13:43:03.713320
5591 13:43:03.716743 Initializing XHCI USB controller at 0x11200000.
5592 13:43:03.739616
5593 13:43:03.742676 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5594 13:43:03.742775
5595 13:43:03.742843
5596 13:43:03.743118 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5597 13:43:03.743204 Sending line: 'tftpboot 192.168.201.1 14879035/tftp-deploy-nycbem4k/kernel/image.itb 14879035/tftp-deploy-nycbem4k/kernel/cmdline '
5599 13:43:03.843742 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5600 13:43:03.843833 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:26)
5601 13:43:03.847738 jacuzzi: tftpboot 192.168.201.1 14879035/tftp-deploy-nycbem4k/kernel/image.itp-deploy-nycbem4k/kernel/cmdline
5602 13:43:03.847826
5603 13:43:03.847893 Waiting for link
5604 13:43:04.253765
5605 13:43:04.253907 R8152: Initializing
5606 13:43:04.253978
5607 13:43:04.256915 Version 9 (ocp_data = 6010)
5608 13:43:04.257005
5609 13:43:04.260100 R8152: Done initializing
5610 13:43:04.260198
5611 13:43:04.260264 Adding net device
5612 13:43:04.645648
5613 13:43:04.645795 done.
5614 13:43:04.645864
5615 13:43:04.645926 MAC: 00:e0:4c:78:85:cb
5616 13:43:04.645986
5617 13:43:04.649129 Sending DHCP discover... done.
5618 13:43:04.649238
5619 13:43:04.652186 Waiting for reply... done.
5620 13:43:04.652295
5621 13:43:04.655477 Sending DHCP request... done.
5622 13:43:04.655584
5623 13:43:04.683995 Waiting for reply... done.
5624 13:43:04.684152
5625 13:43:04.684252 My ip is 192.168.201.22
5626 13:43:04.684348
5627 13:43:04.687445 The DHCP server ip is 192.168.201.1
5628 13:43:04.687562
5629 13:43:04.693767 TFTP server IP predefined by user: 192.168.201.1
5630 13:43:04.693903
5631 13:43:04.700377 Bootfile predefined by user: 14879035/tftp-deploy-nycbem4k/kernel/image.itb
5632 13:43:04.700485
5633 13:43:04.703575 Sending tftp read request... done.
5634 13:43:04.703664
5635 13:43:04.703755 Waiting for the transfer...
5636 13:43:04.703850
5637 13:43:04.966858 00000000 ################################################################
5638 13:43:04.966994
5639 13:43:05.247349 00080000 ################################################################
5640 13:43:05.247525
5641 13:43:05.503057 00100000 ################################################################
5642 13:43:05.503189
5643 13:43:05.756973 00180000 ################################################################
5644 13:43:05.757137
5645 13:43:06.034892 00200000 ################################################################
5646 13:43:06.035027
5647 13:43:06.312353 00280000 ################################################################
5648 13:43:06.312475
5649 13:43:06.595696 00300000 ################################################################
5650 13:43:06.595825
5651 13:43:06.876156 00380000 ################################################################
5652 13:43:06.876290
5653 13:43:07.134324 00400000 ################################################################
5654 13:43:07.134462
5655 13:43:07.386134 00480000 ################################################################
5656 13:43:07.386341
5657 13:43:07.635096 00500000 ################################################################
5658 13:43:07.635282
5659 13:43:07.888996 00580000 ################################################################
5660 13:43:07.889134
5661 13:43:08.140694 00600000 ################################################################
5662 13:43:08.140869
5663 13:43:08.392821 00680000 ################################################################
5664 13:43:08.392968
5665 13:43:08.645834 00700000 ################################################################
5666 13:43:08.645998
5667 13:43:08.893756 00780000 ################################################################
5668 13:43:08.893943
5669 13:43:09.152762 00800000 ################################################################
5670 13:43:09.152909
5671 13:43:09.413955 00880000 ################################################################
5672 13:43:09.414148
5673 13:43:09.667081 00900000 ################################################################
5674 13:43:09.667268
5675 13:43:09.924099 00980000 ################################################################
5676 13:43:09.924287
5677 13:43:10.179440 00a00000 ################################################################
5678 13:43:10.179666
5679 13:43:10.439711 00a80000 ################################################################
5680 13:43:10.439857
5681 13:43:10.704508 00b00000 ################################################################
5682 13:43:10.704708
5683 13:43:10.964466 00b80000 ################################################################
5684 13:43:10.964661
5685 13:43:11.226702 00c00000 ################################################################
5686 13:43:11.226891
5687 13:43:11.488121 00c80000 ################################################################
5688 13:43:11.488310
5689 13:43:11.745779 00d00000 ################################################################
5690 13:43:11.745916
5691 13:43:11.997924 00d80000 ################################################################
5692 13:43:11.998058
5693 13:43:12.257717 00e00000 ################################################################
5694 13:43:12.257904
5695 13:43:12.510523 00e80000 ################################################################
5696 13:43:12.510688
5697 13:43:12.764429 00f00000 ################################################################
5698 13:43:12.764597
5699 13:43:13.018616 00f80000 ################################################################
5700 13:43:13.018838
5701 13:43:13.274091 01000000 ################################################################
5702 13:43:13.274259
5703 13:43:13.551049 01080000 ################################################################
5704 13:43:13.551232
5705 13:43:13.832128 01100000 ################################################################
5706 13:43:13.832313
5707 13:43:14.108038 01180000 ################################################################
5708 13:43:14.108223
5709 13:43:14.398328 01200000 ################################################################
5710 13:43:14.398463
5711 13:43:14.708663 01280000 ################################################################
5712 13:43:14.708801
5713 13:43:15.014530 01300000 ################################################################
5714 13:43:15.014670
5715 13:43:15.313038 01380000 ################################################################
5716 13:43:15.313186
5717 13:43:15.598306 01400000 ################################################################
5718 13:43:15.598429
5719 13:43:15.897188 01480000 ################################################################
5720 13:43:15.897313
5721 13:43:16.180678 01500000 ################################################################
5722 13:43:16.180809
5723 13:43:16.459564 01580000 ################################################################
5724 13:43:16.459688
5725 13:43:16.722211 01600000 ################################################################
5726 13:43:16.722335
5727 13:43:17.002373 01680000 ################################################################
5728 13:43:17.002503
5729 13:43:17.266402 01700000 ################################################################
5730 13:43:17.266526
5731 13:43:17.527998 01780000 ################################################################
5732 13:43:17.528120
5733 13:43:17.788525 01800000 ################################################################
5734 13:43:17.788653
5735 13:43:18.049743 01880000 ################################################################
5736 13:43:18.049879
5737 13:43:18.308362 01900000 ################################################################
5738 13:43:18.308514
5739 13:43:18.558396 01980000 ################################################################
5740 13:43:18.558543
5741 13:43:18.807268 01a00000 ################################################################
5742 13:43:18.807417
5743 13:43:19.065904 01a80000 ################################################################
5744 13:43:19.066029
5745 13:43:19.312784 01b00000 ################################################################
5746 13:43:19.312938
5747 13:43:19.567653 01b80000 ################################################################
5748 13:43:19.567808
5749 13:43:19.828925 01c00000 ################################################################
5750 13:43:19.829077
5751 13:43:20.076917 01c80000 ################################################################
5752 13:43:20.077051
5753 13:43:20.330962 01d00000 ################################################################
5754 13:43:20.331097
5755 13:43:20.588153 01d80000 ################################################################
5756 13:43:20.588306
5757 13:43:20.803020 01e00000 ###################################################### done.
5758 13:43:20.803170
5759 13:43:20.806646 The bootfile was 31898186 bytes long.
5760 13:43:20.806757
5761 13:43:20.809668 Sending tftp read request... done.
5762 13:43:20.809772
5763 13:43:20.809864 Waiting for the transfer...
5764 13:43:20.809954
5765 13:43:20.812832 00000000 # done.
5766 13:43:20.812928
5767 13:43:20.819788 Command line loaded dynamically from TFTP file: 14879035/tftp-deploy-nycbem4k/kernel/cmdline
5768 13:43:20.819887
5769 13:43:20.845755 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14879035/extract-nfsrootfs-6fdsh4oj,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5770 13:43:20.845883
5771 13:43:20.849229 Loading FIT.
5772 13:43:20.849318
5773 13:43:20.852351 Image ramdisk-1 has 18723980 bytes.
5774 13:43:20.852438
5775 13:43:20.852524 Image fdt-1 has 57695 bytes.
5776 13:43:20.852604
5777 13:43:20.855763 Image kernel-1 has 13114469 bytes.
5778 13:43:20.855853
5779 13:43:20.865248 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5780 13:43:20.865342
5781 13:43:20.878498 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5782 13:43:20.878611
5783 13:43:20.881901 Choosing best match conf-1 for compat google,juniper-sku16.
5784 13:43:20.887023
5785 13:43:20.890992 Connected to device vid:did:rid of 1ae0:0028:00
5786 13:43:20.898361
5787 13:43:20.901633 tpm_get_response: command 0x17b, return code 0x0
5788 13:43:20.901744
5789 13:43:20.904934 tpm_cleanup: add release locality here.
5790 13:43:20.905039
5791 13:43:20.907852 Shutting down all USB controllers.
5792 13:43:20.907958
5793 13:43:20.911355 Removing current net device
5794 13:43:20.911495
5795 13:43:20.914530 Exiting depthcharge with code 4 at timestamp: 34976614
5796 13:43:20.914640
5797 13:43:20.921155 LZMA decompressing kernel-1 to 0x80193568
5798 13:43:20.921349
5799 13:43:20.924371 LZMA decompressing kernel-1 to 0x40000000
5800 13:43:22.787136
5801 13:43:22.787297 jumping to kernel
5802 13:43:22.788213 end: 2.2.4 bootloader-commands (duration 00:00:20) [common]
5803 13:43:22.788348 start: 2.2.5 auto-login-action (timeout 00:04:07) [common]
5804 13:43:22.788453 Setting prompt string to ['Linux version [0-9]']
5805 13:43:22.788557 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5806 13:43:22.788659 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5807 13:43:22.862225
5808 13:43:22.865511 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5809 13:43:22.868979 start: 2.2.5.1 login-action (timeout 00:04:07) [common]
5810 13:43:22.869106 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5811 13:43:22.869211 Setting prompt string to []
5812 13:43:22.869359 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5813 13:43:22.869496 Using line separator: #'\n'#
5814 13:43:22.869615 No login prompt set.
5815 13:43:22.869734 Parsing kernel messages
5816 13:43:22.869846 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5817 13:43:22.870086 [login-action] Waiting for messages, (timeout 00:04:07)
5818 13:43:22.870210 Waiting using forced prompt support (timeout 00:02:04)
5819 13:43:22.888255 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j272990-arm64-gcc-12-defconfig-arm64-chromebook-fgzcq) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024
5820 13:43:22.891777 [ 0.000000] random: crng init done
5821 13:43:22.894719 [ 0.000000] Machine model: Google juniper sku16 board
5822 13:43:22.898020 [ 0.000000] efi: UEFI not found.
5823 13:43:22.907858 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5824 13:43:22.914549 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5825 13:43:22.924469 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5826 13:43:22.927727 [ 0.000000] printk: bootconsole [mtk8250] enabled
5827 13:43:22.936250 [ 0.000000] NUMA: No NUMA configuration found
5828 13:43:22.942537 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5829 13:43:22.948926 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bda00-0x13f7bffff]
5830 13:43:22.949068 [ 0.000000] Zone ranges:
5831 13:43:22.955832 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5832 13:43:22.958875 [ 0.000000] DMA32 empty
5833 13:43:22.965481 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5834 13:43:22.968815 [ 0.000000] Movable zone start for each node
5835 13:43:22.972129 [ 0.000000] Early memory node ranges
5836 13:43:22.978539 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5837 13:43:22.985053 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5838 13:43:22.991544 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5839 13:43:22.998120 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5840 13:43:23.004825 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5841 13:43:23.011034 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5842 13:43:23.032786 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5843 13:43:23.039001 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5844 13:43:23.045646 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5845 13:43:23.048882 [ 0.000000] psci: probing for conduit method from DT.
5846 13:43:23.055477 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5847 13:43:23.058849 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5848 13:43:23.065134 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5849 13:43:23.068455 [ 0.000000] psci: SMC Calling Convention v1.1
5850 13:43:23.075027 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5851 13:43:23.078309 [ 0.000000] Detected VIPT I-cache on CPU0
5852 13:43:23.085031 [ 0.000000] CPU features: detected: GIC system register CPU interface
5853 13:43:23.091422 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5854 13:43:23.098248 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5855 13:43:23.104859 [ 0.000000] CPU features: detected: ARM erratum 845719
5856 13:43:23.108126 [ 0.000000] alternatives: applying boot alternatives
5857 13:43:23.114625 [ 0.000000] Fallback order for Node 0: 0
5858 13:43:23.121060 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5859 13:43:23.124332 [ 0.000000] Policy zone: Normal
5860 13:43:23.150707 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14879035/extract-nfsrootfs-6fdsh4oj,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5861 13:43:23.163675 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5862 13:43:23.170309 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5863 13:43:23.179964 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5864 13:43:23.186563 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
5865 13:43:23.189803 <6>[ 0.000000] software IO TLB: area num 8.
5866 13:43:23.216564 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5867 13:43:23.274371 <6>[ 0.000000] Memory: 3896780K/4191232K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 261684K reserved, 32768K cma-reserved)
5868 13:43:23.280865 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5869 13:43:23.287641 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5870 13:43:23.290826 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5871 13:43:23.297175 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5872 13:43:23.303934 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5873 13:43:23.310300 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5874 13:43:23.316848 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5875 13:43:23.323363 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5876 13:43:23.329904 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5877 13:43:23.339741 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5878 13:43:23.346540 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5879 13:43:23.349791 <6>[ 0.000000] GICv3: 640 SPIs implemented
5880 13:43:23.353181 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5881 13:43:23.359421 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5882 13:43:23.362844 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5883 13:43:23.369615 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5884 13:43:23.382544 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5885 13:43:23.392224 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5886 13:43:23.402098 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5887 13:43:23.411492 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5888 13:43:23.424419 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5889 13:43:23.430956 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5890 13:43:23.438024 <6>[ 0.009462] Console: colour dummy device 80x25
5891 13:43:23.441297 <6>[ 0.014500] printk: console [tty1] enabled
5892 13:43:23.454435 <6>[ 0.018891] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5893 13:43:23.457679 <6>[ 0.029357] pid_max: default: 32768 minimum: 301
5894 13:43:23.464192 <6>[ 0.034237] LSM: Security Framework initializing
5895 13:43:23.470966 <6>[ 0.039151] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5896 13:43:23.477296 <6>[ 0.046774] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5897 13:43:23.484414 <4>[ 0.055654] cacheinfo: Unable to detect cache hierarchy for CPU 0
5898 13:43:23.494494 <6>[ 0.062284] cblist_init_generic: Setting adjustable number of callback queues.
5899 13:43:23.500879 <6>[ 0.069729] cblist_init_generic: Setting shift to 3 and lim to 1.
5900 13:43:23.507239 <6>[ 0.076083] cblist_init_generic: Setting adjustable number of callback queues.
5901 13:43:23.513818 <6>[ 0.083528] cblist_init_generic: Setting shift to 3 and lim to 1.
5902 13:43:23.517060 <6>[ 0.089926] rcu: Hierarchical SRCU implementation.
5903 13:43:23.523519 <6>[ 0.094953] rcu: Max phase no-delay instances is 1000.
5904 13:43:23.531750 <6>[ 0.102862] EFI services will not be available.
5905 13:43:23.534674 <6>[ 0.107811] smp: Bringing up secondary CPUs ...
5906 13:43:23.545449 <6>[ 0.113105] Detected VIPT I-cache on CPU1
5907 13:43:23.552158 <4>[ 0.113153] cacheinfo: Unable to detect cache hierarchy for CPU 1
5908 13:43:23.558555 <6>[ 0.113161] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5909 13:43:23.565123 <6>[ 0.113195] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5910 13:43:23.568527 <6>[ 0.113776] Detected VIPT I-cache on CPU2
5911 13:43:23.574956 <4>[ 0.113809] cacheinfo: Unable to detect cache hierarchy for CPU 2
5912 13:43:23.581550 <6>[ 0.113814] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5913 13:43:23.588627 <6>[ 0.113825] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5914 13:43:23.594930 <6>[ 0.114271] Detected VIPT I-cache on CPU3
5915 13:43:23.601239 <4>[ 0.114303] cacheinfo: Unable to detect cache hierarchy for CPU 3
5916 13:43:23.607754 <6>[ 0.114308] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5917 13:43:23.614664 <6>[ 0.114319] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5918 13:43:23.617841 <6>[ 0.114891] CPU features: detected: Spectre-v2
5919 13:43:23.624235 <6>[ 0.114901] CPU features: detected: Spectre-BHB
5920 13:43:23.627408 <6>[ 0.114905] CPU features: detected: ARM erratum 858921
5921 13:43:23.634411 <6>[ 0.114910] Detected VIPT I-cache on CPU4
5922 13:43:23.637291 <4>[ 0.114958] cacheinfo: Unable to detect cache hierarchy for CPU 4
5923 13:43:23.647087 <6>[ 0.114965] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5924 13:43:23.653800 <6>[ 0.114973] arch_timer: Enabling local workaround for ARM erratum 858921
5925 13:43:23.657062 <6>[ 0.114984] arch_timer: CPU4: Trapping CNTVCT access
5926 13:43:23.663517 <6>[ 0.114992] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5927 13:43:23.670098 <6>[ 0.115478] Detected VIPT I-cache on CPU5
5928 13:43:23.676679 <4>[ 0.115519] cacheinfo: Unable to detect cache hierarchy for CPU 5
5929 13:43:23.683198 <6>[ 0.115525] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5930 13:43:23.689867 <6>[ 0.115532] arch_timer: Enabling local workaround for ARM erratum 858921
5931 13:43:23.696256 <6>[ 0.115538] arch_timer: CPU5: Trapping CNTVCT access
5932 13:43:23.702972 <6>[ 0.115543] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5933 13:43:23.706165 <6>[ 0.116078] Detected VIPT I-cache on CPU6
5934 13:43:23.712871 <4>[ 0.116124] cacheinfo: Unable to detect cache hierarchy for CPU 6
5935 13:43:23.719417 <6>[ 0.116130] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5936 13:43:23.725978 <6>[ 0.116136] arch_timer: Enabling local workaround for ARM erratum 858921
5937 13:43:23.732450 <6>[ 0.116143] arch_timer: CPU6: Trapping CNTVCT access
5938 13:43:23.738695 <6>[ 0.116148] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5939 13:43:23.742003 <6>[ 0.116678] Detected VIPT I-cache on CPU7
5940 13:43:23.748849 <4>[ 0.116721] cacheinfo: Unable to detect cache hierarchy for CPU 7
5941 13:43:23.755242 <6>[ 0.116728] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5942 13:43:23.761967 <6>[ 0.116735] arch_timer: Enabling local workaround for ARM erratum 858921
5943 13:43:23.768450 <6>[ 0.116741] arch_timer: CPU7: Trapping CNTVCT access
5944 13:43:23.774805 <6>[ 0.116746] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5945 13:43:23.778384 <6>[ 0.116794] smp: Brought up 1 node, 8 CPUs
5946 13:43:23.784748 <6>[ 0.355668] SMP: Total of 8 processors activated.
5947 13:43:23.791612 <6>[ 0.360604] CPU features: detected: 32-bit EL0 Support
5948 13:43:23.794707 <6>[ 0.365976] CPU features: detected: 32-bit EL1 Support
5949 13:43:23.801134 <6>[ 0.371342] CPU features: detected: CRC32 instructions
5950 13:43:23.804477 <6>[ 0.376768] CPU: All CPU(s) started at EL2
5951 13:43:23.811103 <6>[ 0.381106] alternatives: applying system-wide alternatives
5952 13:43:23.817788 <6>[ 0.389133] devtmpfs: initialized
5953 13:43:23.833383 <6>[ 0.398093] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5954 13:43:23.839988 <6>[ 0.408040] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5955 13:43:23.846474 <6>[ 0.415760] pinctrl core: initialized pinctrl subsystem
5956 13:43:23.849715 <6>[ 0.422882] DMI not present or invalid.
5957 13:43:23.856304 <6>[ 0.427250] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5958 13:43:23.866297 <6>[ 0.434156] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5959 13:43:23.872738 <6>[ 0.441686] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5960 13:43:23.882469 <6>[ 0.449937] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5961 13:43:23.889050 <6>[ 0.458115] audit: initializing netlink subsys (disabled)
5962 13:43:23.895610 <5>[ 0.463820] audit: type=2000 audit(0.332:1): state=initialized audit_enabled=0 res=1
5963 13:43:23.901914 <6>[ 0.464796] thermal_sys: Registered thermal governor 'step_wise'
5964 13:43:23.908470 <6>[ 0.471786] thermal_sys: Registered thermal governor 'power_allocator'
5965 13:43:23.911604 <6>[ 0.478083] cpuidle: using governor menu
5966 13:43:23.918508 <6>[ 0.489045] NET: Registered PF_QIPCRTR protocol family
5967 13:43:23.924925 <6>[ 0.494542] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5968 13:43:23.931198 <6>[ 0.501641] ASID allocator initialised with 32768 entries
5969 13:43:23.937613 <6>[ 0.508405] Serial: AMBA PL011 UART driver
5970 13:43:23.948687 <4>[ 0.519729] Trying to register duplicate clock ID: 113
5971 13:43:24.008173 <6>[ 0.576161] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5972 13:43:24.022430 <6>[ 0.590540] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5973 13:43:24.025837 <6>[ 0.600312] KASLR enabled
5974 13:43:24.040241 <6>[ 0.608249] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
5975 13:43:24.046610 <6>[ 0.615251] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
5976 13:43:24.053107 <6>[ 0.621727] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
5977 13:43:24.059860 <6>[ 0.628718] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
5978 13:43:24.066427 <6>[ 0.635192] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
5979 13:43:24.073003 <6>[ 0.642181] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
5980 13:43:24.079388 <6>[ 0.648655] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
5981 13:43:24.086262 <6>[ 0.655644] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
5982 13:43:24.092559 <6>[ 0.663176] ACPI: Interpreter disabled.
5983 13:43:24.099763 <6>[ 0.671178] iommu: Default domain type: Translated
5984 13:43:24.106293 <6>[ 0.676341] iommu: DMA domain TLB invalidation policy: strict mode
5985 13:43:24.109720 <5>[ 0.682964] SCSI subsystem initialized
5986 13:43:24.116236 <6>[ 0.687412] usbcore: registered new interface driver usbfs
5987 13:43:24.122791 <6>[ 0.693139] usbcore: registered new interface driver hub
5988 13:43:24.129131 <6>[ 0.698682] usbcore: registered new device driver usb
5989 13:43:24.132700 <6>[ 0.705005] pps_core: LinuxPPS API ver. 1 registered
5990 13:43:24.142194 <6>[ 0.710191] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
5991 13:43:24.148971 <6>[ 0.719516] PTP clock support registered
5992 13:43:24.152170 <6>[ 0.723768] EDAC MC: Ver: 3.0.0
5993 13:43:24.155350 <6>[ 0.729413] FPGA manager framework
5994 13:43:24.161981 <6>[ 0.733091] Advanced Linux Sound Architecture Driver Initialized.
5995 13:43:24.165194 <6>[ 0.739833] vgaarb: loaded
5996 13:43:24.171726 <6>[ 0.742964] clocksource: Switched to clocksource arch_sys_counter
5997 13:43:24.178137 <5>[ 0.749397] VFS: Disk quotas dquot_6.6.0
5998 13:43:24.184862 <6>[ 0.753572] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
5999 13:43:24.188130 <6>[ 0.760745] pnp: PnP ACPI: disabled
6000 13:43:24.196629 <6>[ 0.767611] NET: Registered PF_INET protocol family
6001 13:43:24.202857 <6>[ 0.772835] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
6002 13:43:24.214859 <6>[ 0.782747] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
6003 13:43:24.224400 <6>[ 0.791501] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
6004 13:43:24.231162 <6>[ 0.799452] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
6005 13:43:24.237348 <6>[ 0.807684] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
6006 13:43:24.247844 <6>[ 0.815776] TCP: Hash tables configured (established 32768 bind 32768)
6007 13:43:24.254398 <6>[ 0.822604] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
6008 13:43:24.260774 <6>[ 0.829578] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
6009 13:43:24.267527 <6>[ 0.837058] NET: Registered PF_UNIX/PF_LOCAL protocol family
6010 13:43:24.273875 <6>[ 0.843183] RPC: Registered named UNIX socket transport module.
6011 13:43:24.277213 <6>[ 0.849328] RPC: Registered udp transport module.
6012 13:43:24.283648 <6>[ 0.854253] RPC: Registered tcp transport module.
6013 13:43:24.290215 <6>[ 0.859177] RPC: Registered tcp NFSv4.1 backchannel transport module.
6014 13:43:24.293464 <6>[ 0.865831] PCI: CLS 0 bytes, default 64
6015 13:43:24.296804 <6>[ 0.870090] Unpacking initramfs...
6016 13:43:24.318953 <6>[ 0.887035] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
6017 13:43:24.328705 <6>[ 0.895774] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
6018 13:43:24.331905 <6>[ 0.904689] kvm [1]: IPA Size Limit: 40 bits
6019 13:43:24.339812 <6>[ 0.911047] kvm [1]: vgic-v2@c420000
6020 13:43:24.346207 <6>[ 0.914870] kvm [1]: GIC system register CPU interface enabled
6021 13:43:24.349397 <6>[ 0.921068] kvm [1]: vgic interrupt IRQ18
6022 13:43:24.355932 <6>[ 0.925431] kvm [1]: Hyp mode initialized successfully
6023 13:43:24.359170 <5>[ 0.931777] Initialise system trusted keyrings
6024 13:43:24.365590 <6>[ 0.936625] workingset: timestamp_bits=42 max_order=20 bucket_order=0
6025 13:43:24.375203 <6>[ 0.946541] squashfs: version 4.0 (2009/01/31) Phillip Lougher
6026 13:43:24.381700 <5>[ 0.952975] NFS: Registering the id_resolver key type
6027 13:43:24.384863 <5>[ 0.958282] Key type id_resolver registered
6028 13:43:24.391353 <5>[ 0.962693] Key type id_legacy registered
6029 13:43:24.397887 <6>[ 0.967005] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
6030 13:43:24.404273 <6>[ 0.973928] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
6031 13:43:24.410872 <6>[ 0.981679] 9p: Installing v9fs 9p2000 file system support
6032 13:43:24.438789 <5>[ 1.010062] Key type asymmetric registered
6033 13:43:24.441937 <5>[ 1.014408] Asymmetric key parser 'x509' registered
6034 13:43:24.451866 <6>[ 1.019563] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
6035 13:43:24.454979 <6>[ 1.027184] io scheduler mq-deadline registered
6036 13:43:24.458589 <6>[ 1.031944] io scheduler kyber registered
6037 13:43:24.481595 <6>[ 1.052721] EINJ: ACPI disabled.
6038 13:43:24.488059 <4>[ 1.056499] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
6039 13:43:24.525887 <6>[ 1.097281] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
6040 13:43:24.534483 <6>[ 1.105746] printk: console [ttyS0] disabled
6041 13:43:24.562663 <6>[ 1.130406] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
6042 13:43:24.568878 <6>[ 1.139886] printk: console [ttyS0] enabled
6043 13:43:24.572442 <6>[ 1.139886] printk: console [ttyS0] enabled
6044 13:43:24.578704 <6>[ 1.148805] printk: bootconsole [mtk8250] disabled
6045 13:43:24.582030 <6>[ 1.148805] printk: bootconsole [mtk8250] disabled
6046 13:43:24.591862 <3>[ 1.159341] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
6047 13:43:24.598397 <3>[ 1.167720] mt6577-uart 11003000.serial: Error applying setting, reverse things back
6048 13:43:24.628144 <6>[ 1.196131] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
6049 13:43:24.634658 <6>[ 1.205787] serial serial0: tty port ttyS1 registered
6050 13:43:24.641358 <6>[ 1.212346] SuperH (H)SCI(F) driver initialized
6051 13:43:24.644629 <6>[ 1.217844] msm_serial: driver initialized
6052 13:43:24.660208 <6>[ 1.228154] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
6053 13:43:24.670038 <6>[ 1.236756] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
6054 13:43:24.676525 <6>[ 1.245331] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
6055 13:43:24.686192 <6>[ 1.253901] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
6056 13:43:24.695956 <6>[ 1.262556] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
6057 13:43:24.702796 <6>[ 1.271218] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
6058 13:43:24.712377 <6>[ 1.279957] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
6059 13:43:24.722206 <6>[ 1.288696] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
6060 13:43:24.728674 <6>[ 1.297260] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
6061 13:43:24.738168 <6>[ 1.306061] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
6062 13:43:24.747101 <4>[ 1.318442] cacheinfo: Unable to detect cache hierarchy for CPU 0
6063 13:43:24.756494 <6>[ 1.327783] loop: module loaded
6064 13:43:24.768479 <6>[ 1.339729] vsim1: Bringing 1800000uV into 2700000-2700000uV
6065 13:43:24.786395 <6>[ 1.357801] megasas: 07.719.03.00-rc1
6066 13:43:24.795222 <6>[ 1.366687] spi-nor spi1.0: w25q64dw (8192 Kbytes)
6067 13:43:24.810824 <6>[ 1.378331] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
6068 13:43:24.823481 <6>[ 1.394925] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
6069 13:43:24.883714 <6>[ 1.448561] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.3.25/cr50_v1.9308_87_mp.398-a
6070 13:43:24.928155 <6>[ 1.499420] Freeing initrd memory: 18280K
6071 13:43:24.941608 <4>[ 1.509383] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
6072 13:43:24.948186 <4>[ 1.518622] CPU: 6 PID: 1 Comm: swapper/0 Not tainted 6.1.96-cip24 #1
6073 13:43:24.954714 <4>[ 1.525320] Hardware name: Google juniper sku16 board (DT)
6074 13:43:24.957909 <4>[ 1.531060] Call trace:
6075 13:43:24.961136 <4>[ 1.533760] dump_backtrace.part.0+0xe0/0xf0
6076 13:43:24.964486 <4>[ 1.538298] show_stack+0x18/0x30
6077 13:43:24.970843 <4>[ 1.541871] dump_stack_lvl+0x64/0x80
6078 13:43:24.974052 <4>[ 1.545791] dump_stack+0x18/0x34
6079 13:43:24.977603 <4>[ 1.549361] sysfs_warn_dup+0x64/0x80
6080 13:43:24.980747 <4>[ 1.553282] sysfs_do_create_link_sd+0xf0/0x100
6081 13:43:24.987223 <4>[ 1.558069] sysfs_create_link+0x20/0x40
6082 13:43:24.990796 <4>[ 1.562249] bus_add_device+0x64/0x120
6083 13:43:24.993877 <4>[ 1.566255] device_add+0x354/0x7ec
6084 13:43:24.997119 <4>[ 1.570001] of_device_add+0x44/0x60
6085 13:43:25.003948 <4>[ 1.573835] of_platform_device_create_pdata+0x90/0x124
6086 13:43:25.007116 <4>[ 1.579316] of_platform_bus_create+0x154/0x380
6087 13:43:25.013800 <4>[ 1.584103] of_platform_populate+0x50/0xfc
6088 13:43:25.017088 <4>[ 1.588542] parse_mtd_partitions+0x1d8/0x4e0
6089 13:43:25.020258 <4>[ 1.593157] mtd_device_parse_register+0xec/0x2e0
6090 13:43:25.027048 <4>[ 1.598118] spi_nor_probe+0x280/0x2f4
6091 13:43:25.030445 <4>[ 1.602124] spi_mem_probe+0x6c/0xc0
6092 13:43:25.033685 <4>[ 1.605955] spi_probe+0x84/0xe4
6093 13:43:25.036826 <4>[ 1.609441] really_probe+0xbc/0x2dc
6094 13:43:25.040357 <4>[ 1.613271] __driver_probe_device+0x78/0x114
6095 13:43:25.046798 <4>[ 1.617882] driver_probe_device+0xd8/0x15c
6096 13:43:25.050287 <4>[ 1.622320] __device_attach_driver+0xb8/0x134
6097 13:43:25.053477 <4>[ 1.627019] bus_for_each_drv+0x7c/0xd4
6098 13:43:25.060023 <4>[ 1.631113] __device_attach+0x9c/0x1a0
6099 13:43:25.063233 <4>[ 1.635203] device_initial_probe+0x14/0x20
6100 13:43:25.066530 <4>[ 1.639641] bus_probe_device+0x98/0xa0
6101 13:43:25.069916 <4>[ 1.643730] device_add+0x3c0/0x7ec
6102 13:43:25.076289 <4>[ 1.647474] __spi_add_device+0x78/0x120
6103 13:43:25.079584 <4>[ 1.651653] spi_add_device+0x44/0x80
6104 13:43:25.083223 <4>[ 1.655570] spi_register_controller+0x704/0xb20
6105 13:43:25.089704 <4>[ 1.660442] devm_spi_register_controller+0x4c/0xac
6106 13:43:25.092825 <4>[ 1.665576] mtk_spi_probe+0x4f4/0x684
6107 13:43:25.096108 <4>[ 1.669580] platform_probe+0x68/0xc0
6108 13:43:25.102690 <4>[ 1.673498] really_probe+0xbc/0x2dc
6109 13:43:25.105844 <4>[ 1.677328] __driver_probe_device+0x78/0x114
6110 13:43:25.109302 <4>[ 1.681939] driver_probe_device+0xd8/0x15c
6111 13:43:25.115763 <4>[ 1.686377] __driver_attach+0x94/0x19c
6112 13:43:25.119143 <4>[ 1.690467] bus_for_each_dev+0x74/0xd0
6113 13:43:25.122253 <4>[ 1.694560] driver_attach+0x24/0x30
6114 13:43:25.125624 <4>[ 1.698390] bus_add_driver+0x154/0x20c
6115 13:43:25.128656 <4>[ 1.702481] driver_register+0x78/0x130
6116 13:43:25.135406 <4>[ 1.706571] __platform_driver_register+0x28/0x34
6117 13:43:25.138676 <4>[ 1.711532] mtk_spi_driver_init+0x1c/0x28
6118 13:43:25.145135 <4>[ 1.715888] do_one_initcall+0x64/0x1dc
6119 13:43:25.148381 <4>[ 1.719978] kernel_init_freeable+0x218/0x284
6120 13:43:25.151932 <4>[ 1.724594] kernel_init+0x24/0x12c
6121 13:43:25.154935 <4>[ 1.728339] ret_from_fork+0x10/0x20
6122 13:43:25.166023 <6>[ 1.737095] tun: Universal TUN/TAP device driver, 1.6
6123 13:43:25.169313 <6>[ 1.743435] thunder_xcv, ver 1.0
6124 13:43:25.175792 <6>[ 1.746937] thunder_bgx, ver 1.0
6125 13:43:25.175924 <6>[ 1.750445] nicpf, ver 1.0
6126 13:43:25.186822 <6>[ 1.754818] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
6127 13:43:25.189938 <6>[ 1.762302] hns3: Copyright (c) 2017 Huawei Corporation.
6128 13:43:25.196712 <6>[ 1.767899] hclge is initializing
6129 13:43:25.200103 <6>[ 1.771486] e1000: Intel(R) PRO/1000 Network Driver
6130 13:43:25.206453 <6>[ 1.776621] e1000: Copyright (c) 1999-2006 Intel Corporation.
6131 13:43:25.212927 <6>[ 1.782647] e1000e: Intel(R) PRO/1000 Network Driver
6132 13:43:25.216484 <6>[ 1.787870] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
6133 13:43:25.222752 <6>[ 1.794064] igb: Intel(R) Gigabit Ethernet Network Driver
6134 13:43:25.229390 <6>[ 1.799720] igb: Copyright (c) 2007-2014 Intel Corporation.
6135 13:43:25.235842 <6>[ 1.805565] igbvf: Intel(R) Gigabit Virtual Function Network Driver
6136 13:43:25.242400 <6>[ 1.812090] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
6137 13:43:25.245622 <6>[ 1.818646] sky2: driver version 1.30
6138 13:43:25.252631 <6>[ 1.823913] usbcore: registered new device driver r8152-cfgselector
6139 13:43:25.259382 <6>[ 1.830458] usbcore: registered new interface driver r8152
6140 13:43:25.265550 <6>[ 1.836286] VFIO - User Level meta-driver version: 0.3
6141 13:43:25.272845 <6>[ 1.844101] mtu3 11201000.usb: uwk - reg:0x420, version:101
6142 13:43:25.279639 <4>[ 1.849970] mtu3 11201000.usb: supply vbus not found, using dummy regulator
6143 13:43:25.286011 <6>[ 1.857243] mtu3 11201000.usb: dr_mode: 1, drd: auto
6144 13:43:25.292585 <6>[ 1.862469] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
6145 13:43:25.295963 <6>[ 1.868644] mtu3 11201000.usb: usb3-drd: 0
6146 13:43:25.306244 <6>[ 1.874215] mtu3 11201000.usb: xHCI platform device register success...
6147 13:43:25.313018 <4>[ 1.882843] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
6148 13:43:25.319287 <6>[ 1.890790] xhci-mtk 11200000.usb: xHCI Host Controller
6149 13:43:25.326092 <6>[ 1.896293] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
6150 13:43:25.332821 <6>[ 1.904029] xhci-mtk 11200000.usb: USB3 root hub has no ports
6151 13:43:25.342814 <6>[ 1.910038] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
6152 13:43:25.349357 <6>[ 1.919460] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
6153 13:43:25.355784 <6>[ 1.925539] xhci-mtk 11200000.usb: xHCI Host Controller
6154 13:43:25.362434 <6>[ 1.931028] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
6155 13:43:25.368963 <6>[ 1.938687] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
6156 13:43:25.372116 <6>[ 1.945498] hub 1-0:1.0: USB hub found
6157 13:43:25.378631 <6>[ 1.949528] hub 1-0:1.0: 1 port detected
6158 13:43:25.388380 <6>[ 1.954881] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
6159 13:43:25.391770 <6>[ 1.963503] hub 2-0:1.0: USB hub found
6160 13:43:25.398228 <3>[ 1.967561] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
6161 13:43:25.404768 <6>[ 1.975466] usbcore: registered new interface driver usb-storage
6162 13:43:25.411659 <6>[ 1.982050] usbcore: registered new device driver onboard-usb-hub
6163 13:43:25.423237 <4>[ 1.991075] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
6164 13:43:25.432291 <6>[ 2.003293] mt6397-rtc mt6358-rtc: registered as rtc0
6165 13:43:25.442096 <6>[ 2.008769] mt6397-rtc mt6358-rtc: setting system clock to 2024-07-18T13:43:25 UTC (1721310205)
6166 13:43:25.448374 <6>[ 2.018646] i2c_dev: i2c /dev entries driver
6167 13:43:25.458309 <6>[ 2.025020] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6168 13:43:25.464908 <6>[ 2.033340] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6169 13:43:25.471644 <6>[ 2.042243] i2c 4-0058: Fixed dependency cycle(s) with /panel
6170 13:43:25.478011 <6>[ 2.048272] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
6171 13:43:25.496299 <6>[ 2.067677] cpu cpu0: EM: created perf domain
6172 13:43:25.509650 <6>[ 2.073164] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
6173 13:43:25.512824 <6>[ 2.084443] cpu cpu4: EM: created perf domain
6174 13:43:25.520333 <6>[ 2.091511] sdhci: Secure Digital Host Controller Interface driver
6175 13:43:25.526699 <6>[ 2.097957] sdhci: Copyright(c) Pierre Ossman
6176 13:43:25.533427 <6>[ 2.103371] Synopsys Designware Multimedia Card Interface Driver
6177 13:43:25.539813 <6>[ 2.103851] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
6178 13:43:25.543317 <6>[ 2.110421] sdhci-pltfm: SDHCI platform and OF driver helper
6179 13:43:25.551578 <6>[ 2.122949] ledtrig-cpu: registered to indicate activity on CPUs
6180 13:43:25.559395 <6>[ 2.130622] usbcore: registered new interface driver usbhid
6181 13:43:25.565951 <6>[ 2.136460] usbhid: USB HID core driver
6182 13:43:25.572966 <6>[ 2.140778] spi_master spi2: will run message pump with realtime priority
6183 13:43:25.579957 <4>[ 2.140913] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
6184 13:43:25.586683 <4>[ 2.155080] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
6185 13:43:25.599567 <6>[ 2.159556] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
6186 13:43:25.616344 <6>[ 2.177403] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
6187 13:43:25.622918 <4>[ 2.189648] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6188 13:43:25.629384 <6>[ 2.198534] cros-ec-spi spi2.0: Chrome EC device registered
6189 13:43:25.638976 <4>[ 2.206836] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6190 13:43:25.649851 <4>[ 2.217768] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6191 13:43:25.656446 <4>[ 2.226683] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6192 13:43:25.662875 <6>[ 2.234261] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x13014
6193 13:43:25.669680 <6>[ 2.238776] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6194 13:43:25.676202 <6>[ 2.242261] mmc0: new HS400 MMC card at address 0001
6195 13:43:25.682679 <6>[ 2.253776] mmcblk0: mmc0:0001 DA4032 29.1 GiB
6196 13:43:25.691615 <6>[ 2.262977] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6197 13:43:25.701875 <6>[ 2.273148] mmcblk0boot0: mmc0:0001 DA4032 4.00 MiB
6198 13:43:25.708529 <6>[ 2.279790] mmcblk0boot1: mmc0:0001 DA4032 4.00 MiB
6199 13:43:25.718511 <6>[ 2.280161] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6200 13:43:25.724939 <6>[ 2.285925] mmcblk0rpmb: mmc0:0001 DA4032 16.0 MiB, chardev (507:0)
6201 13:43:25.735664 <6>[ 2.298004] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6202 13:43:25.748244 <6>[ 2.304604] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6203 13:43:25.751319 <6>[ 2.312658] NET: Registered PF_PACKET protocol family
6204 13:43:25.761430 <6>[ 2.323328] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6205 13:43:25.768039 <6>[ 2.328596] 9pnet: Installing 9P2000 support
6206 13:43:25.771297 <5>[ 2.343138] Key type dns_resolver registered
6207 13:43:25.777795 <6>[ 2.348122] registered taskstats version 1
6208 13:43:25.781066 <5>[ 2.352488] Loading compiled-in X.509 certificates
6209 13:43:25.798864 <6>[ 2.367124] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6210 13:43:25.827705 <3>[ 2.395746] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6211 13:43:25.853570 <6>[ 2.418134] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6212 13:43:25.863632 <6>[ 2.431519] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6213 13:43:25.873201 <6>[ 2.440100] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6214 13:43:25.879759 <6>[ 2.448623] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6215 13:43:25.889463 <6>[ 2.457143] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6216 13:43:25.899664 <6>[ 2.465663] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6217 13:43:25.905946 <6>[ 2.474182] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6218 13:43:25.915721 <6>[ 2.482700] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6219 13:43:25.922367 <6>[ 2.491910] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6220 13:43:25.928908 <6>[ 2.499429] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6221 13:43:25.935443 <6>[ 2.506713] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6222 13:43:25.945778 <6>[ 2.513957] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6223 13:43:25.952399 <6>[ 2.521413] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6224 13:43:25.955846 <6>[ 2.521670] hub 1-1:1.0: USB hub found
6225 13:43:25.962507 <6>[ 2.529747] panfrost 13040000.gpu: clock rate = 511999970
6226 13:43:25.965391 <6>[ 2.532510] hub 1-1:1.0: 3 ports detected
6227 13:43:25.975205 <6>[ 2.537792] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6228 13:43:25.985013 <6>[ 2.551930] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6229 13:43:25.991517 <6>[ 2.559941] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6230 13:43:26.004714 <6>[ 2.568381] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6231 13:43:26.011097 <6>[ 2.580459] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6232 13:43:26.021906 <6>[ 2.589840] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6233 13:43:26.031692 <6>[ 2.598536] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6234 13:43:26.041458 <6>[ 2.607685] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6235 13:43:26.051043 <6>[ 2.616817] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6236 13:43:26.057650 <6>[ 2.625947] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6237 13:43:26.067394 <6>[ 2.635248] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6238 13:43:26.077152 <6>[ 2.644550] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6239 13:43:26.087136 <6>[ 2.654025] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6240 13:43:26.097022 <6>[ 2.663499] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6241 13:43:26.106383 <6>[ 2.672626] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6242 13:43:26.178422 <6>[ 2.746511] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6243 13:43:26.188188 <6>[ 2.755468] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6244 13:43:26.199209 <6>[ 2.767189] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6245 13:43:26.274765 <6>[ 2.842999] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6246 13:43:26.885419 <6>[ 3.035247] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6247 13:43:26.894988 <4>[ 3.152367] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6248 13:43:26.901479 <4>[ 3.152385] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6249 13:43:26.908091 <6>[ 3.189046] r8152 1-1.2:1.0 eth0: v1.12.13
6250 13:43:26.914566 <6>[ 3.266995] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6251 13:43:26.920804 <6>[ 3.436609] Console: switching to colour frame buffer device 170x48
6252 13:43:26.930630 <6>[ 3.497242] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6253 13:43:26.948517 <6>[ 3.513233] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6254 13:43:26.965895 <6>[ 3.530548] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6255 13:43:26.975443 <6>[ 3.542856] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6256 13:43:26.981915 <6>[ 3.551230] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6257 13:43:26.994962 <6>[ 3.555949] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6258 13:43:27.009513 <6>[ 3.574215] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6259 13:43:28.274592 <6>[ 4.846031] r8152 1-1.2:1.0 eth0: carrier on
6260 13:43:31.431714 <5>[ 4.866989] Sending DHCP requests .., OK
6261 13:43:31.438288 <6>[ 8.007312] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.22
6262 13:43:31.441665 <6>[ 8.015747] IP-Config: Complete:
6263 13:43:31.454497 <6>[ 8.019320] device=eth0, hwaddr=00:e0:4c:78:85:cb, ipaddr=192.168.201.22, mask=255.255.255.0, gw=192.168.201.1
6264 13:43:31.464300 <6>[ 8.030219] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-2, domain=lava-rack, nis-domain=(none)
6265 13:43:31.476495 <6>[ 8.044582] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6266 13:43:31.485279 <6>[ 8.044592] nameserver0=192.168.201.1
6267 13:43:31.492982 <6>[ 8.064437] clk: Disabling unused clocks
6268 13:43:31.498050 <6>[ 8.072421] ALSA device list:
6269 13:43:31.507337 <6>[ 8.078511] No soundcards found.
6270 13:43:31.516107 <6>[ 8.087400] Freeing unused kernel memory: 8512K
6271 13:43:31.523409 <6>[ 8.094582] Run /init as init process
6272 13:43:31.536021 Loading, please wait...
6273 13:43:31.573325 Starting systemd-udevd version 252.22-1~deb12u1
6274 13:43:31.869920 <3>[ 8.440883] thermal_sys: Failed to find 'trips' node
6275 13:43:31.879423 <3>[ 8.446878] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6276 13:43:31.885940 <3>[ 8.454934] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6277 13:43:31.897416 <4>[ 8.465217] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6278 13:43:31.906995 <3>[ 8.465563] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6279 13:43:31.913418 <4>[ 8.473410] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6280 13:43:31.923322 <3>[ 8.474550] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6281 13:43:31.933134 <3>[ 8.474570] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6282 13:43:31.939788 <3>[ 8.474599] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6283 13:43:31.949802 <3>[ 8.474675] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6284 13:43:31.959818 <3>[ 8.474698] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6285 13:43:31.965980 <3>[ 8.474705] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6286 13:43:31.977625 <3>[ 8.474714] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6287 13:43:31.988241 <6>[ 8.474715] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6288 13:43:31.998490 <3>[ 8.474725] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6289 13:43:32.007940 <3>[ 8.474766] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6290 13:43:32.014659 <3>[ 8.474977] thermal_sys: Failed to find 'trips' node
6291 13:43:32.024233 <3>[ 8.474979] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6292 13:43:32.033967 <3>[ 8.474983] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6293 13:43:32.043810 <4>[ 8.474986] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6294 13:43:32.053689 <4>[ 8.477300] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6295 13:43:32.063448 <6>[ 8.480733] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6296 13:43:32.074422 <3>[ 8.483379] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6297 13:43:32.084080 <6>[ 8.499556] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6298 13:43:32.095188 <6>[ 8.501155] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6299 13:43:32.108363 <3>[ 8.508338] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6300 13:43:32.114809 <4>[ 8.526504] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6301 13:43:32.125691 <3>[ 8.534317] elan_i2c 2-0015: Error applying setting, reverse things back
6302 13:43:32.128857 <6>[ 8.571873] mc: Linux media interface: v0.10
6303 13:43:32.142746 <3>[ 8.627977] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6304 13:43:32.152520 <5>[ 8.672801] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6305 13:43:32.159585 <6>[ 8.694303] videodev: Linux video capture interface: v2.00
6306 13:43:32.166051 <5>[ 8.710808] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6307 13:43:32.184215 <5>[ 8.751860] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6308 13:43:32.193741 <6>[ 8.758329] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6309 13:43:32.200460 <6>[ 8.758848] cs_system_cfg: CoreSight Configuration manager initialised
6310 13:43:32.210142 <4>[ 8.760303] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6311 13:43:32.216772 <6>[ 8.777291] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6312 13:43:32.223105 <6>[ 8.786670] cfg80211: failed to load regulatory.db
6313 13:43:32.229688 <6>[ 8.794808] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6314 13:43:32.236786 <6>[ 8.796070] Bluetooth: Core ver 2.22
6315 13:43:32.242941 <6>[ 8.796174] NET: Registered PF_BLUETOOTH protocol family
6316 13:43:32.249675 <6>[ 8.796178] Bluetooth: HCI device and connection manager initialized
6317 13:43:32.257359 <6>[ 8.796196] Bluetooth: HCI socket layer initialized
6318 13:43:32.264889 <6>[ 8.796202] Bluetooth: L2CAP socket layer initialized
6319 13:43:32.272844 <6>[ 8.796216] Bluetooth: SCO socket layer initialized
6320 13:43:32.279989 <3>[ 8.817971] mtk-scp 10500000.scp: invalid resource
6321 13:43:32.302044 <6>[ 8.869731] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6322 13:43:32.311813 <3>[ 8.870073] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6323 13:43:32.321436 <4>[ 8.880417] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6324 13:43:32.328188 <4>[ 8.880417] Fallback method does not support PEC.
6325 13:43:32.476558 <3>[ 8.891515] debugfs: File 'Playback' in directory 'dapm' already present!
6326 13:43:32.477948 <6>[ 8.902947] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6327 13:43:32.478460 <3>[ 8.911512] debugfs: File 'Capture' in directory 'dapm' already present!
6328 13:43:32.478878 <3>[ 8.928354] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6329 13:43:32.479120 <6>[ 8.931958] remoteproc remoteproc0: scp is available
6330 13:43:32.479329 <6>[ 8.932192] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6331 13:43:32.479572 <6>[ 8.943551] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6332 13:43:32.479782 <3>[ 8.950903] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6333 13:43:32.479996 <4>[ 8.953669] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6334 13:43:32.480191 <6>[ 8.963981] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6335 13:43:32.480406 <6>[ 8.969487] remoteproc remoteproc0: powering up scp
6336 13:43:32.480630 <4>[ 9.016137] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6337 13:43:32.480755 <6>[ 9.016779] Bluetooth: HCI UART driver ver 2.3
6338 13:43:32.480879 <3>[ 9.024965] remoteproc remoteproc0: request_firmware failed: -2
6339 13:43:32.481000 <6>[ 9.025008] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6340 13:43:32.481119 <6>[ 9.027526] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6341 13:43:32.483937 <6>[ 9.029772] Bluetooth: HCI UART protocol H4 registered
6342 13:43:32.487287 <6>[ 9.046447] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6343 13:43:32.495279 <6>[ 9.054037] Bluetooth: HCI UART protocol LL registered
6344 13:43:32.501675 <6>[ 9.070745] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6345 13:43:32.508269 <6>[ 9.072744] Bluetooth: HCI UART protocol Three-wire (H5) registered
6346 13:43:32.518000 <6>[ 9.077181] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video0 (81,0)
6347 13:43:32.527880 <6>[ 9.078273] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input6
6348 13:43:32.534579 <6>[ 9.081610] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video1
6349 13:43:32.543652 <6>[ 9.085661] Bluetooth: HCI UART protocol Broadcom registered
6350 13:43:32.558611 <6>[ 9.092151] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6351 13:43:32.568354 <6>[ 9.092165] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6352 13:43:32.581217 <6>[ 9.092560] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6353 13:43:32.588078 <6>[ 9.100027] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6354 13:43:32.594631 <6>[ 9.148572] Bluetooth: hci0: setting up ROME/QCA6390
6355 13:43:32.602478 <6>[ 9.149058] Bluetooth: HCI UART protocol QCA registered
6356 13:43:32.609091 <6>[ 9.150032] Bluetooth: HCI UART protocol Marvell registered
6357 13:43:32.623479 <6>[ 9.175430] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6358 13:43:32.656089 <6>[ 9.227258] usbcore: registered new interface driver uvcvideo
6359 13:43:32.674788 <6>[ 9.242656] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6360 13:43:32.700718 Begin: Loading essential drivers ... done.
6361 13:43:32.704006 Begin: Running /scripts/init-premount ... done.
6362 13:43:32.710444 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
6363 13:43:32.720381 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
6364 13:43:32.723654 Device /sys/class/net/eth0 found
6365 13:43:32.723758 done.
6366 13:43:32.740197 Begin: Waiting up to 180 secs for any network device to become available ... done.
6367 13:43:32.780086 IP-Config: eth0 hardware address 00:e0:4c:78:85:cb mtu 1500 DHCP
6368 13:43:32.822742 <3>[ 9.393770] Bluetooth: hci0: Frame reassembly failed (-84)
6369 13:43:33.041852 <6>[ 9.609832] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6370 13:43:33.104871 <6>[ 9.676019] Bluetooth: hci0: QCA Product ID :0x00000008
6371 13:43:33.113636 <6>[ 9.684799] Bluetooth: hci0: QCA SOC Version :0x00000044
6372 13:43:33.123139 <6>[ 9.694240] Bluetooth: hci0: QCA ROM Version :0x00000302
6373 13:43:33.129834 <4>[ 9.697336] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6374 13:43:33.136062 <6>[ 9.699901] Bluetooth: hci0: QCA Patch Version:0x00000111
6375 13:43:33.144893 <6>[ 9.699911] Bluetooth: hci0: QCA controller version 0x00440302
6376 13:43:33.154336 <4>[ 9.716637] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6377 13:43:33.161152 <6>[ 9.722021] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6378 13:43:33.167786 <4>[ 9.732874] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6379 13:43:33.177591 <4>[ 9.736128] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6380 13:43:33.184002 <4>[ 9.744745] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6381 13:43:33.190247 <3>[ 9.753346] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6382 13:43:33.207422 <3>[ 9.776866] Bluetooth: hci0: QCA Failed to download patch (-2)
6383 13:43:33.596240 IP-Config: eth0 complete (dhcp from 192.168.201.1):
6384 13:43:33.603023 address: 192.168.201.22 broadcast: 192.168.201.255 netmask: 255.255.255.0
6385 13:43:33.609420 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
6386 13:43:33.615921 host : mt8183-kukui-jacuzzi-juniper-sku16-cbg-2
6387 13:43:33.622533 domain : lava-rack
6388 13:43:33.628873 rootserver: 192.168.201.1 rootpath:
6389 13:43:33.629018 filename :
6390 13:43:33.644390 done.
6391 13:43:33.652250 Begin: Running /scripts/nfs-bottom ... done.
6392 13:43:33.668350 Begin: Running /scripts/init-bottom ... done.
6393 13:43:34.975489 <6>[ 11.546765] NET: Registered PF_INET6 protocol family
6394 13:43:34.987941 <6>[ 11.559292] Segment Routing with IPv6
6395 13:43:34.996555 <6>[ 11.567792] In-situ OAM (IOAM) with IPv6
6396 13:43:35.170892 <30>[ 11.712556] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6397 13:43:35.188944 <30>[ 11.760282] systemd[1]: Detected architecture arm64.
6398 13:43:35.200905
6399 13:43:35.203975 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6400 13:43:35.204063
6401 13:43:35.233567 <30>[ 11.804646] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6402 13:43:36.217659 <30>[ 12.785570] systemd[1]: Queued start job for default target graphical.target.
6403 13:43:36.264358 <30>[ 12.832080] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6404 13:43:36.277049 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6405 13:43:36.297574 <30>[ 12.865457] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6406 13:43:36.311536 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6407 13:43:36.329333 <30>[ 12.897406] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6408 13:43:36.344197 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6409 13:43:36.364552 <30>[ 12.932608] systemd[1]: Created slice user.slice - User and Session Slice.
6410 13:43:36.377579 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6411 13:43:36.399232 <30>[ 12.963580] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6412 13:43:36.412613 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6413 13:43:36.434744 <30>[ 12.999400] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6414 13:43:36.447343 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6415 13:43:36.476601 <30>[ 13.031334] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6416 13:43:36.493348 <30>[ 13.061232] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6417 13:43:36.501468 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6418 13:43:36.519380 <30>[ 13.087163] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6419 13:43:36.532689 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6420 13:43:36.551386 <30>[ 13.119242] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6421 13:43:36.566013 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6422 13:43:36.580291 <30>[ 13.151249] systemd[1]: Reached target paths.target - Path Units.
6423 13:43:36.594812 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6424 13:43:36.611479 <30>[ 13.179165] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6425 13:43:36.624278 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6426 13:43:36.643202 <30>[ 13.211137] systemd[1]: Reached target slices.target - Slice Units.
6427 13:43:36.654916 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6428 13:43:36.668785 <30>[ 13.239198] systemd[1]: Reached target swap.target - Swaps.
6429 13:43:36.679266 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6430 13:43:36.699376 <30>[ 13.267227] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6431 13:43:36.713398 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6432 13:43:36.731543 <30>[ 13.299561] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6433 13:43:36.745866 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6434 13:43:36.766270 <30>[ 13.334263] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6435 13:43:36.780108 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6436 13:43:36.801374 <30>[ 13.368880] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6437 13:43:36.815344 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6438 13:43:36.832344 <30>[ 13.399886] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6439 13:43:36.844276 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6440 13:43:36.865110 <30>[ 13.432836] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6441 13:43:36.878745 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6442 13:43:36.898418 <30>[ 13.466287] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6443 13:43:36.911697 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6444 13:43:36.927774 <30>[ 13.495756] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6445 13:43:36.940991 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6446 13:43:36.991389 <30>[ 13.559392] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6447 13:43:37.004521 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6448 13:43:37.017756 <30>[ 13.585747] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6449 13:43:37.031529 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6450 13:43:37.091974 <30>[ 13.659750] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6451 13:43:37.104550 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6452 13:43:37.130769 <30>[ 13.692214] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6453 13:43:37.179934 <30>[ 13.747800] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6454 13:43:37.192918 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6455 13:43:37.221810 <30>[ 13.789571] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6456 13:43:37.233242 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6457 13:43:37.276490 <30>[ 13.844173] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6458 13:43:37.287941 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6459 13:43:37.308206 <30>[ 13.876107] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6460 13:43:37.322840 Starting [0;1;39mmodpr<6>[ 13.888811] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6461 13:43:37.326078 obe@drm.service[0m - Load Kernel Module drm...
6462 13:43:37.352996 <30>[ 13.920624] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6463 13:43:37.364708 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6464 13:43:37.404206 <30>[ 13.971882] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
6465 13:43:37.415320 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
6466 13:43:37.436388 <30>[ 14.004059] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6467 13:43:37.444971 Startin<6>[ 14.016758] fuse: init (API version 7.37)
6468 13:43:37.451523 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6469 13:43:37.500326 <30>[ 14.067977] systemd[1]: Starting systemd-journald.service - Journal Service...
6470 13:43:37.510435 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6471 13:43:37.536478 <30>[ 14.104389] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6472 13:43:37.546604 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6473 13:43:37.570623 <30>[ 14.135084] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6474 13:43:37.582729 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6475 13:43:37.605771 <30>[ 14.173577] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6476 13:43:37.618485 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6477 13:43:37.656081 <30>[ 14.223919] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6478 13:43:37.668279 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6479 13:43:37.693437 <30>[ 14.261192] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
6480 13:43:37.703909 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
6481 13:43:37.724267 <30>[ 14.291965] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
6482 13:43:37.733698 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
6483 13:43:37.749704 <3>[ 14.317166] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6484 13:43:37.760114 <30>[ 14.327153] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
6485 13:43:37.766611 <3>[ 14.333260] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6486 13:43:37.777463 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
6487 13:43:37.790556 <3>[ 14.358058] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6488 13:43:37.800966 <30>[ 14.368059] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
6489 13:43:37.810814 <3>[ 14.374395] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6490 13:43:37.827396 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static D<3>[ 14.394730] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6491 13:43:37.827502 evice Nodes.
6492 13:43:37.844889 <3>[ 14.412593] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6493 13:43:37.855654 <30>[ 14.422488] systemd[1]: modprobe@configfs.service: Deactivated successfully.
6494 13:43:37.862203 <3>[ 14.428953] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6495 13:43:37.872453 <30>[ 14.430820] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
6496 13:43:37.878963 <3>[ 14.445408] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6497 13:43:37.902874 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Modu<3>[ 14.470297] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6498 13:43:37.903021 le configfs.
6499 13:43:37.920912 <30>[ 14.488388] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
6500 13:43:37.927385 <3>[ 14.489983] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6501 13:43:37.934613 <30>[ 14.496173] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
6502 13:43:37.951304 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6503 13:43:37.972525 <30>[ 14.540195] systemd[1]: Started systemd-journald.service - Journal Service.
6504 13:43:37.983064 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6505 13:43:38.004181 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6506 13:43:38.026788 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6507 13:43:38.046642 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
6508 13:43:38.065858 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6509 13:43:38.084948 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6510 13:43:38.105213 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6511 13:43:38.124785 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
6512 13:43:38.147148 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6513 13:43:38.163571 <4>[ 14.721516] synth uevent: /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:i2c-tunnel/i2c-12/12-000b/power_supply/sbs-12-000b: failed to send uevent
6514 13:43:38.173353 <3>[ 14.740353] power_supply sbs-12-000b: uevent: failed to send synthetic uevent: -5
6515 13:43:38.208676 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
6516 13:43:38.233567 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6517 13:43:38.262569 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
6518 13:43:38.290924 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6519 13:43:38.320735 <46>[ 14.888656] systemd-journald[323]: Received client request to flush runtime journal.
6520 13:43:38.352890 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
6521 13:43:38.580782 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6522 13:43:38.911732 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6523 13:43:38.934509 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
6524 13:43:38.953075 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6525 13:43:38.974159 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6526 13:43:39.439238 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6527 13:43:39.794428 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6528 13:43:39.814230 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6529 13:43:39.868482 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6530 13:43:39.990728 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6531 13:43:40.008514 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6532 13:43:40.028018 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6533 13:43:40.072452 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6534 13:43:40.097813 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6535 13:43:40.340148 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6536 13:43:40.383858 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6537 13:43:40.459979 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6538 13:43:40.729605 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6539 13:43:40.753366 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
6540 13:43:40.771750 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6541 13:43:40.788065 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6542 13:43:40.828645 Starting [0;1;39msystemd-backlight…ess of backlight:backlight_lcd0...
6543 13:43:40.908909 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6544 13:43:40.933695 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6545 13:43:40.956381 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6546 13:43:41.016675 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6547 13:43:41.133314 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6548 13:43:41.161965 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6549 13:43:41.191012 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6550 13:43:41.215353 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6551 13:43:41.233802 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6552 13:43:41.254666 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6553 13:43:41.277964 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6554 13:43:41.305108 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6555 13:43:41.328872 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6556 13:43:41.353699 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6557 13:43:41.369252 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6558 13:43:41.391792 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6559 13:43:41.413694 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6560 13:43:41.437694 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
6561 13:43:41.458446 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
6562 13:43:41.476424 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
6563 13:43:41.498624 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
6564 13:43:41.519316 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6565 13:43:41.536247 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6566 13:43:41.555989 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6567 13:43:41.574637 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6568 13:43:41.592533 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6569 13:43:41.613603 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6570 13:43:41.673041 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
6571 13:43:41.939121 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6572 13:43:42.141986 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
6573 13:43:42.212365 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6574 13:43:42.234836 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6575 13:43:42.252523 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6576 13:43:42.283162 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
6577 13:43:42.304035 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6578 13:43:42.376362 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6579 13:43:42.429612 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6580 13:43:42.478387 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6581 13:43:42.496919 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6582 13:43:42.516106 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
6583 13:43:42.535086 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6584 13:43:42.556070 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6585 13:43:42.574076 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6586 13:43:42.627035 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6587 13:43:42.677641 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6588 13:43:42.751383
6589 13:43:42.754411 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6590 13:43:42.754523
6591 13:43:42.757871 debian-bookworm-arm64 login: root (automatic login)
6592 13:43:42.757955
6593 13:43:43.079285 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024 aarch64
6594 13:43:43.079416
6595 13:43:43.085628 The programs included with the Debian GNU/Linux system are free software;
6596 13:43:43.092041 the exact distribution terms for each program are described in the
6597 13:43:43.095613 individual files in /usr/share/doc/*/copyright.
6598 13:43:43.095701
6599 13:43:43.102007 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6600 13:43:43.105264 permitted by applicable law.
6601 13:43:44.251869 Matched prompt #10: / #
6603 13:43:44.252220 Setting prompt string to ['/ #']
6604 13:43:44.252352 end: 2.2.5.1 login-action (duration 00:00:21) [common]
6606 13:43:44.252628 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
6607 13:43:44.252757 start: 2.2.6 expect-shell-connection (timeout 00:03:46) [common]
6608 13:43:44.252855 Setting prompt string to ['/ #']
6609 13:43:44.252940 Forcing a shell prompt, looking for ['/ #']
6610 13:43:44.253023 Sending line: ''
6612 13:43:44.303435 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6613 13:43:44.303530 Waiting using forced prompt support (timeout 00:02:30)
6614 13:43:44.308388 / #
6615 13:43:44.308734 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6616 13:43:44.308848 start: 2.2.7 export-device-env (timeout 00:03:46) [common]
6617 13:43:44.308935 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14879035/extract-nfsrootfs-6fdsh4oj'"
6619 13:43:44.414410 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14879035/extract-nfsrootfs-6fdsh4oj'
6620 13:43:44.414692 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
6622 13:43:44.520336 / # export NFS_SERVER_IP='192.168.201.1'
6623 13:43:44.520654 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6624 13:43:44.520761 end: 2.2 depthcharge-retry (duration 00:01:14) [common]
6625 13:43:44.520857 end: 2 depthcharge-action (duration 00:01:14) [common]
6626 13:43:44.520952 start: 3 lava-test-retry (timeout 00:08:03) [common]
6627 13:43:44.521040 start: 3.1 lava-test-shell (timeout 00:08:03) [common]
6628 13:43:44.521115 Using namespace: common
6629 13:43:44.521189 Sending line: '#'
6631 13:43:44.621677 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6632 13:43:44.626612 / # #
6633 13:43:44.626938 Using /lava-14879035
6634 13:43:44.627043 Sending line: 'export SHELL=/bin/bash'
6636 13:43:44.732398 / # export SHELL=/bin/bash
6637 13:43:44.732756 Sending line: '. /lava-14879035/environment'
6639 13:43:44.838470 / # . /lava-14879035/environment
6640 13:43:44.842968 Sending line: '/lava-14879035/bin/lava-test-runner /lava-14879035/0'
6642 13:43:44.943485 Test shell timeout: 10s (minimum of the action and connection timeout)
6643 13:43:44.948251 / # /lava-14879035/bin/lava-test-runner /lava-14879035/0
6644 13:43:45.167659 + export TESTRUN_ID=0_timesync-off
6645 13:43:45.170910 + TESTRUN_ID=0_timesync-off
6646 13:43:45.174261 + cd /lava-14879035/0/tests/0_timesync-off
6647 13:43:45.177761 ++ cat uuid
6648 13:43:45.177853 + UUID=14879035_1.6.2.3.1
6649 13:43:45.180666 + set +x
6650 13:43:45.183856 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14879035_1.6.2.3.1>
6651 13:43:45.184123 Received signal: <STARTRUN> 0_timesync-off 14879035_1.6.2.3.1
6652 13:43:45.184208 Starting test lava.0_timesync-off (14879035_1.6.2.3.1)
6653 13:43:45.184294 Skipping test definition patterns.
6654 13:43:45.187290 + systemctl stop systemd-timesyncd
6655 13:43:45.235158 + set +x
6656 13:43:45.238491 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14879035_1.6.2.3.1>
6657 13:43:45.238756 Received signal: <ENDRUN> 0_timesync-off 14879035_1.6.2.3.1
6658 13:43:45.238840 Ending use of test pattern.
6659 13:43:45.238906 Ending test lava.0_timesync-off (14879035_1.6.2.3.1), duration 0.05
6661 13:43:45.293816 + export TESTRUN_ID=1_kselftest-arm64
6662 13:43:45.293976 + TESTRUN_ID=1_kselftest-arm64
6663 13:43:45.300573 + cd /lava-14879035/0/tests/1_kselftest-arm64
6664 13:43:45.300680 ++ cat uuid
6665 13:43:45.303607 + UUID=14879035_1.6.2.3.5
6666 13:43:45.303698 + set +x
6667 13:43:45.310247 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 14879035_1.6.2.3.5>
6668 13:43:45.310533 Received signal: <STARTRUN> 1_kselftest-arm64 14879035_1.6.2.3.5
6669 13:43:45.310606 Starting test lava.1_kselftest-arm64 (14879035_1.6.2.3.5)
6670 13:43:45.310695 Skipping test definition patterns.
6671 13:43:45.313309 + cd ./automated/linux/kselftest/
6672 13:43:45.339613 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b mt8183-kukui-jacuzzi-juniper-sku16 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
6673 13:43:45.362427 INFO: install_deps skipped
6674 13:43:46.085248 --2024-07-18 13:43:46-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz
6675 13:43:46.103319 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
6676 13:43:46.233538 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
6677 13:43:46.364555 HTTP request sent, awaiting response... 200 OK
6678 13:43:46.368055 Length: 1919140 (1.8M) [application/octet-stream]
6679 13:43:46.370964 Saving to: 'kselftest_armhf.tar.gz'
6680 13:43:46.371080
6681 13:43:46.371177
6682 13:43:46.622205 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
6683 13:43:46.879407 kselftest_armhf.tar 2%[ ] 44.98K 176KB/s
6684 13:43:47.136464 kselftest_armhf.tar 11%[=> ] 213.25K 417KB/s
6685 13:43:47.394999 kselftest_armhf.tar 22%[===> ] 422.05K 550KB/s
6686 13:43:47.554691 kselftest_armhf.tar 71%[=============> ] 1.31M 1.28MB/s
6687 13:43:47.561467 kselftest_armhf.tar 100%[===================>] 1.83M 1.55MB/s in 1.2s
6688 13:43:47.561568
6689 13:43:47.729936 2024-07-18 13:43:47 (1.55 MB/s) - 'kselftest_armhf.tar.gz' saved [1919140/1919140]
6690 13:43:47.730074
6691 13:43:55.109729 skiplist:
6692 13:43:55.113143 ========================================
6693 13:43:55.116297 ========================================
6694 13:43:55.165977 arm64:tags_test
6695 13:43:55.169333 arm64:run_tags_test.sh
6696 13:43:55.169431 arm64:fake_sigreturn_bad_magic
6697 13:43:55.172702 arm64:fake_sigreturn_bad_size
6698 13:43:55.175603 arm64:fake_sigreturn_bad_size_for_magic0
6699 13:43:55.179044 arm64:fake_sigreturn_duplicated_fpsimd
6700 13:43:55.182332 arm64:fake_sigreturn_misaligned_sp
6701 13:43:55.185751 arm64:fake_sigreturn_missing_fpsimd
6702 13:43:55.188652 arm64:fake_sigreturn_sme_change_vl
6703 13:43:55.192082 arm64:fake_sigreturn_sve_change_vl
6704 13:43:55.195413 arm64:mangle_pstate_invalid_compat_toggle
6705 13:43:55.198538 arm64:mangle_pstate_invalid_daif_bits
6706 13:43:55.205108 arm64:mangle_pstate_invalid_mode_el1h
6707 13:43:55.208494 arm64:mangle_pstate_invalid_mode_el1t
6708 13:43:55.211499 arm64:mangle_pstate_invalid_mode_el2h
6709 13:43:55.214912 arm64:mangle_pstate_invalid_mode_el2t
6710 13:43:55.218489 arm64:mangle_pstate_invalid_mode_el3h
6711 13:43:55.221441 arm64:mangle_pstate_invalid_mode_el3t
6712 13:43:55.221527 arm64:sme_trap_no_sm
6713 13:43:55.224799 arm64:sme_trap_non_streaming
6714 13:43:55.227975 arm64:sme_trap_za
6715 13:43:55.228060 arm64:sme_vl
6716 13:43:55.228126 arm64:ssve_regs
6717 13:43:55.231408 arm64:sve_regs
6718 13:43:55.231514 arm64:sve_vl
6719 13:43:55.234464 arm64:za_no_regs
6720 13:43:55.234549 arm64:za_regs
6721 13:43:55.234615 arm64:pac
6722 13:43:55.238053 arm64:fp-stress
6723 13:43:55.238140 arm64:sve-ptrace
6724 13:43:55.240945 arm64:sve-probe-vls
6725 13:43:55.241031 arm64:vec-syscfg
6726 13:43:55.244245 arm64:za-fork
6727 13:43:55.244335 arm64:za-ptrace
6728 13:43:55.247663 arm64:check_buffer_fill
6729 13:43:55.250762 arm64:check_child_memory
6730 13:43:55.250848 arm64:check_gcr_el1_cswitch
6731 13:43:55.254140 arm64:check_ksm_options
6732 13:43:55.257413 arm64:check_mmap_options
6733 13:43:55.257498 arm64:check_prctl
6734 13:43:55.260537 arm64:check_tags_inclusion
6735 13:43:55.263874 arm64:check_user_mem
6736 13:43:55.263959 arm64:btitest
6737 13:43:55.264025 arm64:nobtitest
6738 13:43:55.267272 arm64:hwcap
6739 13:43:55.267382 arm64:ptrace
6740 13:43:55.270333 arm64:syscall-abi
6741 13:43:55.270418 arm64:tpidr2
6742 13:43:55.273753 ============== Tests to run ===============
6743 13:43:55.277122 arm64:tags_test
6744 13:43:55.277222 arm64:run_tags_test.sh
6745 13:43:55.280057 arm64:fake_sigreturn_bad_magic
6746 13:43:55.283535 arm64:fake_sigreturn_bad_size
6747 13:43:55.286884 arm64:fake_sigreturn_bad_size_for_magic0
6748 13:43:55.290011 arm64:fake_sigreturn_duplicated_fpsimd
6749 13:43:55.293046 arm64:fake_sigreturn_misaligned_sp
6750 13:43:55.296497 arm64:fake_sigreturn_missing_fpsimd
6751 13:43:55.299830 arm64:fake_sigreturn_sme_change_vl
6752 13:43:55.302840 arm64:fake_sigreturn_sve_change_vl
6753 13:43:55.306353 arm64:mangle_pstate_invalid_compat_toggle
6754 13:43:55.309475 arm64:mangle_pstate_invalid_daif_bits
6755 13:43:55.312793 arm64:mangle_pstate_invalid_mode_el1h
6756 13:43:55.316269 arm64:mangle_pstate_invalid_mode_el1t
6757 13:43:55.319218 arm64:mangle_pstate_invalid_mode_el2h
6758 13:43:55.322621 arm64:mangle_pstate_invalid_mode_el2t
6759 13:43:55.325924 arm64:mangle_pstate_invalid_mode_el3h
6760 13:43:55.328902 arm64:mangle_pstate_invalid_mode_el3t
6761 13:43:55.332306 arm64:sme_trap_no_sm
6762 13:43:55.335641 arm64:sme_trap_non_streaming
6763 13:43:55.335722 arm64:sme_trap_za
6764 13:43:55.338935 arm64:sme_vl
6765 13:43:55.339047 arm64:ssve_regs
6766 13:43:55.341964 arm64:sve_regs
6767 13:43:55.342089 arm64:sve_vl
6768 13:43:55.342188 arm64:za_no_regs
6769 13:43:55.345513 arm64:za_regs
6770 13:43:55.345642 arm64:pac
6771 13:43:55.348905 arm64:fp-stress
6772 13:43:55.349015 arm64:sve-ptrace
6773 13:43:55.352014 arm64:sve-probe-vls
6774 13:43:55.352165 arm64:vec-syscfg
6775 13:43:55.352262 arm64:za-fork
6776 13:43:55.355431 arm64:za-ptrace
6777 13:43:55.358698 arm64:check_buffer_fill
6778 13:43:55.358785 arm64:check_child_memory
6779 13:43:55.361924 arm64:check_gcr_el1_cswitch
6780 13:43:55.365023 arm64:check_ksm_options
6781 13:43:55.365107 arm64:check_mmap_options
6782 13:43:55.368569 arm64:check_prctl
6783 13:43:55.371844 arm64:check_tags_inclusion
6784 13:43:55.371929 arm64:check_user_mem
6785 13:43:55.374761 arm64:btitest
6786 13:43:55.374881 arm64:nobtitest
6787 13:43:55.374949 arm64:hwcap
6788 13:43:55.378214 arm64:ptrace
6789 13:43:55.378299 arm64:syscall-abi
6790 13:43:55.381572 arm64:tpidr2
6791 13:43:55.384777 ===========End Tests to run ===============
6792 13:43:55.384919 shardfile-arm64 pass
6793 13:43:55.648416 <12>[ 32.218576] kselftest: Running tests in arm64
6794 13:43:55.659132 TAP version 13
6795 13:43:55.676758 1..48
6796 13:43:55.698097 # selftests: arm64: tags_test
6797 13:43:56.964699 ok 1 selftests: arm64: tags_test
6798 13:43:56.983993 # selftests: arm64: run_tags_test.sh
6799 13:43:57.062377 # --------------------
6800 13:43:57.065650 # running tags test
6801 13:43:57.066039 # --------------------
6802 13:43:57.068663 # [PASS]
6803 13:43:57.071998 ok 2 selftests: arm64: run_tags_test.sh
6804 13:43:57.087717 # selftests: arm64: fake_sigreturn_bad_magic
6805 13:43:57.148974 # Registered handlers for all signals.
6806 13:43:57.149428 # Detected MINSTKSIGSZ:4720
6807 13:43:57.152372 # Testcase initialized.
6808 13:43:57.155541 # uc context validated.
6809 13:43:57.158805 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6810 13:43:57.162417 # Handled SIG_COPYCTX
6811 13:43:57.162852 # Available space:3568
6812 13:43:57.168679 # Using badly built context - ERR: BAD MAGIC !
6813 13:43:57.175567 # SIG_OK -- SP:0xFFFFEECE3470 si_addr@:0xffffeece3470 si_code:2 token@:0xffffeece2210 offset:-4704
6814 13:43:57.178391 # ==>> completed. PASS(1)
6815 13:43:57.185275 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
6816 13:43:57.191446 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEECE2210
6817 13:43:57.198153 ok 3 selftests: arm64: fake_sigreturn_bad_magic
6818 13:43:57.201318 # selftests: arm64: fake_sigreturn_bad_size
6819 13:43:57.260225 # Registered handlers for all signals.
6820 13:43:57.260708 # Detected MINSTKSIGSZ:4720
6821 13:43:57.263376 # Testcase initialized.
6822 13:43:57.266753 # uc context validated.
6823 13:43:57.270018 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6824 13:43:57.273095 # Handled SIG_COPYCTX
6825 13:43:57.273610 # Available space:3568
6826 13:43:57.276351 # uc context validated.
6827 13:43:57.283088 # Using badly built context - ERR: Bad size for esr_context
6828 13:43:57.292826 # SIG_OK -- SP:0xFFFFF1A3C1F0 si_addr@:0xfffff1a3c1f0 si_code:2 token@:0xfffff1a3af90 offset:-4704
6829 13:43:57.293233 # ==>> completed. PASS(1)
6830 13:43:57.299597 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
6831 13:43:57.305971 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF1A3AF90
6832 13:43:57.312194 ok 4 selftests: arm64: fake_sigreturn_bad_size
6833 13:43:57.315429 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
6834 13:43:57.356260 # Registered handlers for all signals.
6835 13:43:57.356753 # Detected MINSTKSIGSZ:4720
6836 13:43:57.359323 # Testcase initialized.
6837 13:43:57.362511 # uc context validated.
6838 13:43:57.365996 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6839 13:43:57.369107 # Handled SIG_COPYCTX
6840 13:43:57.372514 # Available space:3568
6841 13:43:57.375958 # Using badly built context - ERR: Bad size for terminator
6842 13:43:57.385566 # SIG_OK -- SP:0xFFFFDA49D470 si_addr@:0xffffda49d470 si_code:2 token@:0xffffda49c210 offset:-4704
6843 13:43:57.388622 # ==>> completed. PASS(1)
6844 13:43:57.395307 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
6845 13:43:57.401851 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDA49C210
6846 13:43:57.408287 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
6847 13:43:57.411621 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
6848 13:43:57.462243 # Registered handlers for all signals.
6849 13:43:57.462718 # Detected MINSTKSIGSZ:4720
6850 13:43:57.465381 # Testcase initialized.
6851 13:43:57.468452 # uc context validated.
6852 13:43:57.471832 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6853 13:43:57.475096 # Handled SIG_COPYCTX
6854 13:43:57.475789 # Available space:3568
6855 13:43:57.481775 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
6856 13:43:57.491629 # SIG_OK -- SP:0xFFFFD56025C0 si_addr@:0xffffd56025c0 si_code:2 token@:0xffffd5601360 offset:-4704
6857 13:43:57.494811 # ==>> completed. PASS(1)
6858 13:43:57.501290 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
6859 13:43:57.508298 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD5601360
6860 13:43:57.511598 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
6861 13:43:57.518206 # selftests: arm64: fake_sigreturn_misaligned_sp
6862 13:43:57.593079 # Registered handlers for all signals.
6863 13:43:57.593336 # Detected MINSTKSIGSZ:4720
6864 13:43:57.593472 # Testcase initialized.
6865 13:43:57.593594 # uc context validated.
6866 13:43:57.593712 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6867 13:43:57.593846 # Handled SIG_COPYCTX
6868 13:43:57.595421 # SIG_OK -- SP:0xFFFFDBE06943 si_addr@:0xffffdbe06943 si_code:2 token@:0xffffdbe06943 offset:0
6869 13:43:57.595652 # ==>> completed. PASS(1)
6870 13:43:57.605125 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
6871 13:43:57.608490 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDBE06943
6872 13:43:57.614987 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
6873 13:43:57.618172 # selftests: arm64: fake_sigreturn_missing_fpsimd
6874 13:43:57.666223 # Registered handlers for all signals.
6875 13:43:57.666632 # Detected MINSTKSIGSZ:4720
6876 13:43:57.669517 # Testcase initialized.
6877 13:43:57.672532 # uc context validated.
6878 13:43:57.675864 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6879 13:43:57.679044 # Handled SIG_COPYCTX
6880 13:43:57.682553 # Mangling template header. Spare space:4096
6881 13:43:57.685778 # Using badly built context - ERR: Missing FPSIMD
6882 13:43:57.695411 # SIG_OK -- SP:0xFFFFF7112A60 si_addr@:0xfffff7112a60 si_code:2 token@:0xfffff7111800 offset:-4704
6883 13:43:57.698792 # ==>> completed. PASS(1)
6884 13:43:57.705229 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
6885 13:43:57.711576 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF7111800
6886 13:43:57.718279 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
6887 13:43:57.721182 # selftests: arm64: fake_sigreturn_sme_change_vl
6888 13:43:57.777300 # Registered handlers for all signals.
6889 13:43:57.777419 # Detected MINSTKSIGSZ:4720
6890 13:43:57.780615 # ==>> completed. SKIP.
6891 13:43:57.787198 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
6892 13:43:57.790300 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
6893 13:43:57.796881 # selftests: arm64: fake_sigreturn_sve_change_vl
6894 13:43:57.874545 # Registered handlers for all signals.
6895 13:43:57.874661 # Detected MINSTKSIGSZ:4720
6896 13:43:57.878018 # ==>> completed. SKIP.
6897 13:43:57.884538 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
6898 13:43:57.887557 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
6899 13:43:57.895266 # selftests: arm64: mangle_pstate_invalid_compat_toggle
6900 13:43:57.972530 # Registered handlers for all signals.
6901 13:43:57.972658 # Detected MINSTKSIGSZ:4720
6902 13:43:57.975988 # Testcase initialized.
6903 13:43:57.979350 # uc context validated.
6904 13:43:57.979490 # Handled SIG_TRIG
6905 13:43:57.989118 # SIG_OK -- SP:0xFFFFC2684E80 si_addr@:0xffffc2684e80 si_code:2 token@:(nil) offset:-281473943359104
6906 13:43:57.992159 # ==>> completed. PASS(1)
6907 13:43:57.998674 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
6908 13:43:58.005370 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
6909 13:43:58.008412 # selftests: arm64: mangle_pstate_invalid_daif_bits
6910 13:43:58.077274 # Registered handlers for all signals.
6911 13:43:58.077403 # Detected MINSTKSIGSZ:4720
6912 13:43:58.080703 # Testcase initialized.
6913 13:43:58.083741 # uc context validated.
6914 13:43:58.083830 # Handled SIG_TRIG
6915 13:43:58.093827 # SIG_OK -- SP:0xFFFFFD00BC00 si_addr@:0xfffffd00bc00 si_code:2 token@:(nil) offset:-281474926427136
6916 13:43:58.096946 # ==>> completed. PASS(1)
6917 13:43:58.103697 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
6918 13:43:58.106719 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
6919 13:43:58.113083 # selftests: arm64: mangle_pstate_invalid_mode_el1h
6920 13:43:58.179048 # Registered handlers for all signals.
6921 13:43:58.179167 # Detected MINSTKSIGSZ:4720
6922 13:43:58.182360 # Testcase initialized.
6923 13:43:58.185525 # uc context validated.
6924 13:43:58.185631 # Handled SIG_TRIG
6925 13:43:58.195533 # SIG_OK -- SP:0xFFFFCFA1CCB0 si_addr@:0xffffcfa1ccb0 si_code:2 token@:(nil) offset:-281474165230768
6926 13:43:58.198653 # ==>> completed. PASS(1)
6927 13:43:58.204955 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
6928 13:43:58.208170 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
6929 13:43:58.214909 # selftests: arm64: mangle_pstate_invalid_mode_el1t
6930 13:43:58.272224 # Registered handlers for all signals.
6931 13:43:58.272354 # Detected MINSTKSIGSZ:4720
6932 13:43:58.275475 # Testcase initialized.
6933 13:43:58.278437 # uc context validated.
6934 13:43:58.278521 # Handled SIG_TRIG
6935 13:43:58.288402 # SIG_OK -- SP:0xFFFFD43B7EC0 si_addr@:0xffffd43b7ec0 si_code:2 token@:(nil) offset:-281474242412224
6936 13:43:58.291562 # ==>> completed. PASS(1)
6937 13:43:58.297985 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
6938 13:43:58.301484 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
6939 13:43:58.307913 # selftests: arm64: mangle_pstate_invalid_mode_el2h
6940 13:43:58.371888 # Registered handlers for all signals.
6941 13:43:58.372044 # Detected MINSTKSIGSZ:4720
6942 13:43:58.374964 # Testcase initialized.
6943 13:43:58.378395 # uc context validated.
6944 13:43:58.378501 # Handled SIG_TRIG
6945 13:43:58.388147 # SIG_OK -- SP:0xFFFFF6759BD0 si_addr@:0xfffff6759bd0 si_code:2 token@:(nil) offset:-281474816646096
6946 13:43:58.391192 # ==>> completed. PASS(1)
6947 13:43:58.397906 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
6948 13:43:58.401073 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
6949 13:43:58.407427 # selftests: arm64: mangle_pstate_invalid_mode_el2t
6950 13:43:58.464820 # Registered handlers for all signals.
6951 13:43:58.464965 # Detected MINSTKSIGSZ:4720
6952 13:43:58.467946 # Testcase initialized.
6953 13:43:58.471580 # uc context validated.
6954 13:43:58.471664 # Handled SIG_TRIG
6955 13:43:58.481160 # SIG_OK -- SP:0xFFFFE1254450 si_addr@:0xffffe1254450 si_code:2 token@:(nil) offset:-281474459059280
6956 13:43:58.484447 # ==>> completed. PASS(1)
6957 13:43:58.491114 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
6958 13:43:58.494392 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
6959 13:43:58.500929 # selftests: arm64: mangle_pstate_invalid_mode_el3h
6960 13:43:58.561690 # Registered handlers for all signals.
6961 13:43:58.561825 # Detected MINSTKSIGSZ:4720
6962 13:43:58.565035 # Testcase initialized.
6963 13:43:58.568079 # uc context validated.
6964 13:43:58.568163 # Handled SIG_TRIG
6965 13:43:58.577927 # SIG_OK -- SP:0xFFFFE81BF2E0 si_addr@:0xffffe81bf2e0 si_code:2 token@:(nil) offset:-281474575889120
6966 13:43:58.581305 # ==>> completed. PASS(1)
6967 13:43:58.587762 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
6968 13:43:58.591233 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
6969 13:43:58.597485 # selftests: arm64: mangle_pstate_invalid_mode_el3t
6970 13:43:58.652668 # Registered handlers for all signals.
6971 13:43:58.652786 # Detected MINSTKSIGSZ:4720
6972 13:43:58.656099 # Testcase initialized.
6973 13:43:58.659229 # uc context validated.
6974 13:43:58.659332 # Handled SIG_TRIG
6975 13:43:58.669269 # SIG_OK -- SP:0xFFFFD1EBCFC0 si_addr@:0xffffd1ebcfc0 si_code:2 token@:(nil) offset:-281474203635648
6976 13:43:58.672281 # ==>> completed. PASS(1)
6977 13:43:58.678807 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
6978 13:43:58.682232 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
6979 13:43:58.685385 # selftests: arm64: sme_trap_no_sm
6980 13:43:58.732188 # Registered handlers for all signals.
6981 13:43:58.732289 # Detected MINSTKSIGSZ:4720
6982 13:43:58.735567 # ==>> completed. SKIP.
6983 13:43:58.745268 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
6984 13:43:58.748610 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
6985 13:43:58.751903 # selftests: arm64: sme_trap_non_streaming
6986 13:43:58.818133 # Registered handlers for all signals.
6987 13:43:58.818232 # Detected MINSTKSIGSZ:4720
6988 13:43:58.821362 # ==>> completed. SKIP.
6989 13:43:58.831283 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
6990 13:43:58.837987 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
6991 13:43:58.841209 # selftests: arm64: sme_trap_za
6992 13:43:58.915728 # Registered handlers for all signals.
6993 13:43:58.915828 # Detected MINSTKSIGSZ:4720
6994 13:43:58.919035 # Testcase initialized.
6995 13:43:58.928787 # SIG_OK -- SP:0xFFFFCA074C30 si_addr@:0xaaaad86f2480 si_code:1 token@:(nil) offset:-187650752324736
6996 13:43:58.931771 # ==>> completed. PASS(1)
6997 13:43:58.938329 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
6998 13:43:58.941673 ok 21 selftests: arm64: sme_trap_za
6999 13:43:58.941760 # selftests: arm64: sme_vl
7000 13:43:59.004722 # Registered handlers for all signals.
7001 13:43:59.004823 # Detected MINSTKSIGSZ:4720
7002 13:43:59.008117 # ==>> completed. SKIP.
7003 13:43:59.014459 # # SME VL :: Check that we get the right SME VL reported
7004 13:43:59.017714 ok 22 selftests: arm64: sme_vl # SKIP
7005 13:43:59.024191 # selftests: arm64: ssve_regs
7006 13:43:59.108909 # Registered handlers for all signals.
7007 13:43:59.109025 # Detected MINSTKSIGSZ:4720
7008 13:43:59.112178 # ==>> completed. SKIP.
7009 13:43:59.121690 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
7010 13:43:59.125279 ok 23 selftests: arm64: ssve_regs # SKIP
7011 13:43:59.128337 # selftests: arm64: sve_regs
7012 13:43:59.219349 # Registered handlers for all signals.
7013 13:43:59.219499 # Detected MINSTKSIGSZ:4720
7014 13:43:59.222352 # ==>> completed. SKIP.
7015 13:43:59.229173 # # SVE registers :: Check that we get the right SVE registers reported
7016 13:43:59.232119 ok 24 selftests: arm64: sve_regs # SKIP
7017 13:43:59.237591 # selftests: arm64: sve_vl
7018 13:43:59.331545 # Registered handlers for all signals.
7019 13:43:59.331662 # Detected MINSTKSIGSZ:4720
7020 13:43:59.334494 # ==>> completed. SKIP.
7021 13:43:59.341204 # # SVE VL :: Check that we get the right SVE VL reported
7022 13:43:59.344482 ok 25 selftests: arm64: sve_vl # SKIP
7023 13:43:59.353143 # selftests: arm64: za_no_regs
7024 13:43:59.431073 # Registered handlers for all signals.
7025 13:43:59.431192 # Detected MINSTKSIGSZ:4720
7026 13:43:59.434313 # ==>> completed. SKIP.
7027 13:43:59.441112 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
7028 13:43:59.444067 ok 26 selftests: arm64: za_no_regs # SKIP
7029 13:43:59.449960 # selftests: arm64: za_regs
7030 13:43:59.526636 # Registered handlers for all signals.
7031 13:43:59.526754 # Detected MINSTKSIGSZ:4720
7032 13:43:59.530047 # ==>> completed. SKIP.
7033 13:43:59.536810 # # ZA register :: Check that we get the right ZA registers reported
7034 13:43:59.539783 ok 27 selftests: arm64: za_regs # SKIP
7035 13:43:59.546518 # selftests: arm64: pac
7036 13:43:59.612841 # TAP version 13
7037 13:43:59.612969 # 1..7
7038 13:43:59.616417 # # Starting 7 tests from 1 test cases.
7039 13:43:59.619490 # # RUN global.corrupt_pac ...
7040 13:43:59.622525 # # SKIP PAUTH not enabled
7041 13:43:59.625904 # # OK global.corrupt_pac
7042 13:43:59.629403 # ok 1 # SKIP PAUTH not enabled
7043 13:43:59.635783 # # RUN global.pac_instructions_not_nop ...
7044 13:43:59.639021 # # SKIP PAUTH not enabled
7045 13:43:59.642377 # # OK global.pac_instructions_not_nop
7046 13:43:59.645401 # ok 2 # SKIP PAUTH not enabled
7047 13:43:59.651882 # # RUN global.pac_instructions_not_nop_generic ...
7048 13:43:59.655083 # # SKIP Generic PAUTH not enabled
7049 13:43:59.661846 # # OK global.pac_instructions_not_nop_generic
7050 13:43:59.664892 # ok 3 # SKIP Generic PAUTH not enabled
7051 13:43:59.668340 # # RUN global.single_thread_different_keys ...
7052 13:43:59.671629 # # SKIP PAUTH not enabled
7053 13:43:59.678081 # # OK global.single_thread_different_keys
7054 13:43:59.681430 # ok 4 # SKIP PAUTH not enabled
7055 13:43:59.684348 # # RUN global.exec_changed_keys ...
7056 13:43:59.687651 # # SKIP PAUTH not enabled
7057 13:43:59.691280 # # OK global.exec_changed_keys
7058 13:43:59.694322 # ok 5 # SKIP PAUTH not enabled
7059 13:43:59.700825 # # RUN global.context_switch_keep_keys ...
7060 13:43:59.704081 # # SKIP PAUTH not enabled
7061 13:43:59.707290 # # OK global.context_switch_keep_keys
7062 13:43:59.710700 # ok 6 # SKIP PAUTH not enabled
7063 13:43:59.717120 # # RUN global.context_switch_keep_keys_generic ...
7064 13:43:59.720440 # # SKIP Generic PAUTH not enabled
7065 13:43:59.723786 # # OK global.context_switch_keep_keys_generic
7066 13:43:59.730370 # ok 7 # SKIP Generic PAUTH not enabled
7067 13:43:59.730455 # # PASSED: 7 / 7 tests passed.
7068 13:43:59.736669 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
7069 13:43:59.740105 ok 28 selftests: arm64: pac
7070 13:43:59.743298 # selftests: arm64: fp-stress
7071 13:44:03.534835 <6>[ 40.108768] vaux18: disabling
7072 13:44:03.538250 <6>[ 40.112143] vio28: disabling
7073 13:44:09.711565 # TAP version 13
7074 13:44:09.711717 # 1..16
7075 13:44:09.714461 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
7076 13:44:09.717755 # # Will run for 10s
7077 13:44:09.717936 # # Started FPSIMD-0-0
7078 13:44:09.721007 # # Started FPSIMD-0-1
7079 13:44:09.724482 # # Started FPSIMD-1-0
7080 13:44:09.724684 # # Started FPSIMD-1-1
7081 13:44:09.727858 # # Started FPSIMD-2-0
7082 13:44:09.730965 # # Started FPSIMD-2-1
7083 13:44:09.731184 # # Started FPSIMD-3-0
7084 13:44:09.734281 # # Started FPSIMD-3-1
7085 13:44:09.734457 # # Started FPSIMD-4-0
7086 13:44:09.737552 # # Started FPSIMD-4-1
7087 13:44:09.740894 # # Started FPSIMD-5-0
7088 13:44:09.741046 # # Started FPSIMD-5-1
7089 13:44:09.744145 # # Started FPSIMD-6-0
7090 13:44:09.747388 # # Started FPSIMD-6-1
7091 13:44:09.747588 # # Started FPSIMD-7-0
7092 13:44:09.750700 # # Started FPSIMD-7-1
7093 13:44:09.753789 # # FPSIMD-0-0: Vector length: 128 bits
7094 13:44:09.757255 # # FPSIMD-0-0: PID: 1193
7095 13:44:09.760401 # # FPSIMD-6-0: Vector length: 128 bits
7096 13:44:09.763678 # # FPSIMD-6-0: PID: 1205
7097 13:44:09.766928 # # FPSIMD-1-0: Vector length: 128 bits
7098 13:44:09.767103 # # FPSIMD-1-0: PID: 1195
7099 13:44:09.770099 # # FPSIMD-2-0: Vector length: 128 bits
7100 13:44:09.773383 # # FPSIMD-2-0: PID: 1197
7101 13:44:09.776823 # # FPSIMD-0-1: Vector length: 128 bits
7102 13:44:09.779985 # # FPSIMD-0-1: PID: 1194
7103 13:44:09.783158 # # FPSIMD-1-1: Vector length: 128 bits
7104 13:44:09.786639 # # FPSIMD-1-1: PID: 1196
7105 13:44:09.789690 # # FPSIMD-5-0: Vector length: 128 bits
7106 13:44:09.793229 # # FPSIMD-5-0: PID: 1203
7107 13:44:09.796571 # # FPSIMD-2-1: Vector length: 128 bits
7108 13:44:09.796739 # # FPSIMD-2-1: PID: 1198
7109 13:44:09.802921 # # FPSIMD-5-1: Vector length: 128 bits
7110 13:44:09.803099 # # FPSIMD-5-1: PID: 1204
7111 13:44:09.806324 # # FPSIMD-4-1: Vector length: 128 bits
7112 13:44:09.809467 # # FPSIMD-4-1: PID: 1202
7113 13:44:09.812593 # # FPSIMD-3-1: Vector length: 128 bits
7114 13:44:09.816237 # # FPSIMD-3-1: PID: 1200
7115 13:44:09.819290 # # FPSIMD-6-1: Vector length: 128 bits
7116 13:44:09.822281 # # FPSIMD-6-1: PID: 1206
7117 13:44:09.825882 # # FPSIMD-7-0: Vector length: 128 bits
7118 13:44:09.828914 # # FPSIMD-7-0: PID: 1207
7119 13:44:09.832137 # # FPSIMD-4-0: Vector length: 128 bits
7120 13:44:09.832301 # # FPSIMD-4-0: PID: 1201
7121 13:44:09.835654 # # FPSIMD-7-1: Vector length: 128 bits
7122 13:44:09.838814 # # FPSIMD-7-1: PID: 1208
7123 13:44:09.842356 # # FPSIMD-3-0: Vector length: 128 bits
7124 13:44:09.845427 # # FPSIMD-3-0: PID: 1199
7125 13:44:09.848544 # # Finishing up...
7126 13:44:09.855093 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=725895, signals=10
7127 13:44:09.861753 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=801981, signals=10
7128 13:44:09.868194 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=780229, signals=10
7129 13:44:09.874614 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=920386, signals=10
7130 13:44:09.881022 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=911914, signals=10
7131 13:44:09.891078 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=732558, signals=10
7132 13:44:09.897617 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=742164, signals=10
7133 13:44:09.897795 # ok 1 FPSIMD-0-0
7134 13:44:09.900890 # ok 2 FPSIMD-0-1
7135 13:44:09.901054 # ok 3 FPSIMD-1-0
7136 13:44:09.903867 # ok 4 FPSIMD-1-1
7137 13:44:09.904020 # ok 5 FPSIMD-2-0
7138 13:44:09.907360 # ok 6 FPSIMD-2-1
7139 13:44:09.907525 # ok 7 FPSIMD-3-0
7140 13:44:09.910482 # ok 8 FPSIMD-3-1
7141 13:44:09.910639 # ok 9 FPSIMD-4-0
7142 13:44:09.914012 # ok 10 FPSIMD-4-1
7143 13:44:09.917200 # ok 11 FPSIMD-5-0
7144 13:44:09.917361 # ok 12 FPSIMD-5-1
7145 13:44:09.920365 # ok 13 FPSIMD-6-0
7146 13:44:09.920528 # ok 14 FPSIMD-6-1
7147 13:44:09.923789 # ok 15 FPSIMD-7-0
7148 13:44:09.923914 # ok 16 FPSIMD-7-1
7149 13:44:09.929911 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=709652, signals=9
7150 13:44:09.940028 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=858571, signals=10
7151 13:44:09.946275 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=679878, signals=10
7152 13:44:09.952975 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=866523, signals=10
7153 13:44:09.959589 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=782585, signals=10
7154 13:44:09.966026 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=821678, signals=10
7155 13:44:09.972593 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=695437, signals=9
7156 13:44:09.982527 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=856437, signals=10
7157 13:44:09.988785 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1054690, signals=10
7158 13:44:09.995487 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
7159 13:44:09.995624 ok 29 selftests: arm64: fp-stress
7160 13:44:09.998624 # selftests: arm64: sve-ptrace
7161 13:44:10.001914 # TAP version 13
7162 13:44:10.002097 # 1..4104
7163 13:44:10.005177 # ok 2 # SKIP SVE not available
7164 13:44:10.008386 # # Planned tests != run tests (4104 != 1)
7165 13:44:10.014857 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7166 13:44:10.018263 ok 30 selftests: arm64: sve-ptrace # SKIP
7167 13:44:10.021359 # selftests: arm64: sve-probe-vls
7168 13:44:10.021526 # TAP version 13
7169 13:44:10.021599 # 1..2
7170 13:44:10.025041 # ok 2 # SKIP SVE not available
7171 13:44:10.028137 # # Planned tests != run tests (2 != 1)
7172 13:44:10.034474 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7173 13:44:10.037756 ok 31 selftests: arm64: sve-probe-vls # SKIP
7174 13:44:10.041062 # selftests: arm64: vec-syscfg
7175 13:44:10.044268 # TAP version 13
7176 13:44:10.044423 # 1..20
7177 13:44:10.047425 # ok 1 # SKIP SVE not supported
7178 13:44:10.051009 # ok 2 # SKIP SVE not supported
7179 13:44:10.051162 # ok 3 # SKIP SVE not supported
7180 13:44:10.054105 # ok 4 # SKIP SVE not supported
7181 13:44:10.057609 # ok 5 # SKIP SVE not supported
7182 13:44:10.060972 # ok 6 # SKIP SVE not supported
7183 13:44:10.064058 # ok 7 # SKIP SVE not supported
7184 13:44:10.067215 # ok 8 # SKIP SVE not supported
7185 13:44:10.070268 # ok 9 # SKIP SVE not supported
7186 13:44:10.073569 # ok 10 # SKIP SVE not supported
7187 13:44:10.073737 # ok 11 # SKIP SME not supported
7188 13:44:10.077145 # ok 12 # SKIP SME not supported
7189 13:44:10.080162 # ok 13 # SKIP SME not supported
7190 13:44:10.083424 # ok 14 # SKIP SME not supported
7191 13:44:10.086559 # ok 15 # SKIP SME not supported
7192 13:44:10.090111 # ok 16 # SKIP SME not supported
7193 13:44:10.093268 # ok 17 # SKIP SME not supported
7194 13:44:10.096748 # ok 18 # SKIP SME not supported
7195 13:44:10.099889 # ok 19 # SKIP SME not supported
7196 13:44:10.103107 # ok 20 # SKIP SME not supported
7197 13:44:10.106270 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
7198 13:44:10.109510 ok 32 selftests: arm64: vec-syscfg
7199 13:44:10.113019 # selftests: arm64: za-fork
7200 13:44:10.113193 # TAP version 13
7201 13:44:10.116138 # 1..1
7202 13:44:10.116287 # # PID: 1284
7203 13:44:10.119304 # # SME support not present
7204 13:44:10.119445 # ok 0 skipped
7205 13:44:10.126042 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7206 13:44:10.129156 ok 33 selftests: arm64: za-fork
7207 13:44:10.129311 # selftests: arm64: za-ptrace
7208 13:44:10.168559 # TAP version 13
7209 13:44:10.168701 # 1..1
7210 13:44:10.171934 # ok 2 # SKIP SME not available
7211 13:44:10.178510 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7212 13:44:10.181476 ok 34 selftests: arm64: za-ptrace # SKIP
7213 13:44:10.191178 # selftests: arm64: check_buffer_fill
7214 13:44:10.269807 # # SKIP: MTE features unavailable
7215 13:44:10.279978 ok 35 selftests: arm64: check_buffer_fill # SKIP
7216 13:44:10.297207 # selftests: arm64: check_child_memory
7217 13:44:10.376891 # # SKIP: MTE features unavailable
7218 13:44:10.386501 ok 36 selftests: arm64: check_child_memory # SKIP
7219 13:44:10.401092 # selftests: arm64: check_gcr_el1_cswitch
7220 13:44:10.463877 # # SKIP: MTE features unavailable
7221 13:44:10.473219 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
7222 13:44:10.489335 # selftests: arm64: check_ksm_options
7223 13:44:10.560781 # # SKIP: MTE features unavailable
7224 13:44:10.568474 ok 38 selftests: arm64: check_ksm_options # SKIP
7225 13:44:10.587779 # selftests: arm64: check_mmap_options
7226 13:44:10.692520 # # SKIP: MTE features unavailable
7227 13:44:10.702689 ok 39 selftests: arm64: check_mmap_options # SKIP
7228 13:44:10.714158 # selftests: arm64: check_prctl
7229 13:44:10.781875 # TAP version 13
7230 13:44:10.782058 # 1..5
7231 13:44:10.785216 # ok 1 check_basic_read
7232 13:44:10.785361 # ok 2 NONE
7233 13:44:10.788171 # ok 3 # SKIP SYNC
7234 13:44:10.788326 # ok 4 # SKIP ASYNC
7235 13:44:10.791508 # ok 5 # SKIP SYNC+ASYNC
7236 13:44:10.795141 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
7237 13:44:10.798137 ok 40 selftests: arm64: check_prctl
7238 13:44:10.804723 # selftests: arm64: check_tags_inclusion
7239 13:44:10.860586 # # SKIP: MTE features unavailable
7240 13:44:10.869853 ok 41 selftests: arm64: check_tags_inclusion # SKIP
7241 13:44:10.883108 # selftests: arm64: check_user_mem
7242 13:44:10.952283 # # SKIP: MTE features unavailable
7243 13:44:10.960271 ok 42 selftests: arm64: check_user_mem # SKIP
7244 13:44:10.970915 # selftests: arm64: btitest
7245 13:44:11.049044 # TAP version 13
7246 13:44:11.049181 # 1..18
7247 13:44:11.052526 # # HWCAP_PACA not present
7248 13:44:11.055601 # # HWCAP2_BTI not present
7249 13:44:11.059112 # # Test binary built for BTI
7250 13:44:11.062279 # ok 1 nohint_func/call_using_br_x0 # SKIP
7251 13:44:11.065361 # ok 1 nohint_func/call_using_br_x16 # SKIP
7252 13:44:11.068452 # ok 1 nohint_func/call_using_blr # SKIP
7253 13:44:11.071960 # ok 1 bti_none_func/call_using_br_x0 # SKIP
7254 13:44:11.078526 # ok 1 bti_none_func/call_using_br_x16 # SKIP
7255 13:44:11.081474 # ok 1 bti_none_func/call_using_blr # SKIP
7256 13:44:11.084956 # ok 1 bti_c_func/call_using_br_x0 # SKIP
7257 13:44:11.088165 # ok 1 bti_c_func/call_using_br_x16 # SKIP
7258 13:44:11.091286 # ok 1 bti_c_func/call_using_blr # SKIP
7259 13:44:11.094968 # ok 1 bti_j_func/call_using_br_x0 # SKIP
7260 13:44:11.097984 # ok 1 bti_j_func/call_using_br_x16 # SKIP
7261 13:44:11.104303 # ok 1 bti_j_func/call_using_blr # SKIP
7262 13:44:11.107756 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
7263 13:44:11.111049 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
7264 13:44:11.114180 # ok 1 bti_jc_func/call_using_blr # SKIP
7265 13:44:11.117254 # ok 1 paciasp_func/call_using_br_x0 # SKIP
7266 13:44:11.123785 # ok 1 paciasp_func/call_using_br_x16 # SKIP
7267 13:44:11.127138 # ok 1 paciasp_func/call_using_blr # SKIP
7268 13:44:11.130323 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
7269 13:44:11.133707 # # WARNING - EXPECTED TEST COUNT WRONG
7270 13:44:11.137133 ok 43 selftests: arm64: btitest
7271 13:44:11.140132 # selftests: arm64: nobtitest
7272 13:44:11.147085 # TAP version 13
7273 13:44:11.147275 # 1..18
7274 13:44:11.150471 # # HWCAP_PACA not present
7275 13:44:11.153605 # # HWCAP2_BTI not present
7276 13:44:11.157002 # # Test binary not built for BTI
7277 13:44:11.160224 # ok 1 nohint_func/call_using_br_x0 # SKIP
7278 13:44:11.163530 # ok 1 nohint_func/call_using_br_x16 # SKIP
7279 13:44:11.166448 # ok 1 nohint_func/call_using_blr # SKIP
7280 13:44:11.170044 # ok 1 bti_none_func/call_using_br_x0 # SKIP
7281 13:44:11.176612 # ok 1 bti_none_func/call_using_br_x16 # SKIP
7282 13:44:11.179846 # ok 1 bti_none_func/call_using_blr # SKIP
7283 13:44:11.182958 # ok 1 bti_c_func/call_using_br_x0 # SKIP
7284 13:44:11.186431 # ok 1 bti_c_func/call_using_br_x16 # SKIP
7285 13:44:11.189650 # ok 1 bti_c_func/call_using_blr # SKIP
7286 13:44:11.192858 # ok 1 bti_j_func/call_using_br_x0 # SKIP
7287 13:44:11.199430 # ok 1 bti_j_func/call_using_br_x16 # SKIP
7288 13:44:11.202431 # ok 1 bti_j_func/call_using_blr # SKIP
7289 13:44:11.205845 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
7290 13:44:11.209057 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
7291 13:44:11.212406 # ok 1 bti_jc_func/call_using_blr # SKIP
7292 13:44:11.215599 # ok 1 paciasp_func/call_using_br_x0 # SKIP
7293 13:44:11.222243 # ok 1 paciasp_func/call_using_br_x16 # SKIP
7294 13:44:11.225300 # ok 1 paciasp_func/call_using_blr # SKIP
7295 13:44:11.228522 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
7296 13:44:11.235025 # # WARNING - EXPECTED TEST COUNT WRONG
7297 13:44:11.235214 ok 44 selftests: arm64: nobtitest
7298 13:44:11.238369 # selftests: arm64: hwcap
7299 13:44:11.243207 # TAP version 13
7300 13:44:11.243372 # 1..28
7301 13:44:11.246484 # ok 1 cpuinfo_match_RNG
7302 13:44:11.250053 # # SIGILL reported for RNG
7303 13:44:11.250182 # ok 2 # SKIP sigill_RNG
7304 13:44:11.253010 # ok 3 cpuinfo_match_SME
7305 13:44:11.256318 # ok 4 sigill_SME
7306 13:44:11.256471 # ok 5 cpuinfo_match_SVE
7307 13:44:11.259776 # ok 6 sigill_SVE
7308 13:44:11.262931 # ok 7 cpuinfo_match_SVE 2
7309 13:44:11.263073 # # SIGILL reported for SVE 2
7310 13:44:11.266171 # ok 8 # SKIP sigill_SVE 2
7311 13:44:11.269578 # ok 9 cpuinfo_match_SVE AES
7312 13:44:11.272650 # # SIGILL reported for SVE AES
7313 13:44:11.276204 # ok 10 # SKIP sigill_SVE AES
7314 13:44:11.279207 # ok 11 cpuinfo_match_SVE2 PMULL
7315 13:44:11.282613 # # SIGILL reported for SVE2 PMULL
7316 13:44:11.282764 # ok 12 # SKIP sigill_SVE2 PMULL
7317 13:44:11.285848 # ok 13 cpuinfo_match_SVE2 BITPERM
7318 13:44:11.288867 # # SIGILL reported for SVE2 BITPERM
7319 13:44:11.292390 # ok 14 # SKIP sigill_SVE2 BITPERM
7320 13:44:11.295417 # ok 15 cpuinfo_match_SVE2 SHA3
7321 13:44:11.298945 # # SIGILL reported for SVE2 SHA3
7322 13:44:11.301979 # ok 16 # SKIP sigill_SVE2 SHA3
7323 13:44:11.305485 # ok 17 cpuinfo_match_SVE2 SM4
7324 13:44:11.308548 # # SIGILL reported for SVE2 SM4
7325 13:44:11.311655 # ok 18 # SKIP sigill_SVE2 SM4
7326 13:44:11.315222 # ok 19 cpuinfo_match_SVE2 I8MM
7327 13:44:11.318343 # # SIGILL reported for SVE2 I8MM
7328 13:44:11.318485 # ok 20 # SKIP sigill_SVE2 I8MM
7329 13:44:11.321543 # ok 21 cpuinfo_match_SVE2 F32MM
7330 13:44:11.325082 # # SIGILL reported for SVE2 F32MM
7331 13:44:11.328076 # ok 22 # SKIP sigill_SVE2 F32MM
7332 13:44:11.331298 # ok 23 cpuinfo_match_SVE2 F64MM
7333 13:44:11.334635 # # SIGILL reported for SVE2 F64MM
7334 13:44:11.337908 # ok 24 # SKIP sigill_SVE2 F64MM
7335 13:44:11.341288 # ok 25 cpuinfo_match_SVE2 BF16
7336 13:44:11.344508 # # SIGILL reported for SVE2 BF16
7337 13:44:11.347966 # ok 26 # SKIP sigill_SVE2 BF16
7338 13:44:11.351198 # ok 27 cpuinfo_match_SVE2 EBF16
7339 13:44:11.354345 # ok 28 # SKIP sigill_SVE2 EBF16
7340 13:44:11.357795 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
7341 13:44:11.360867 ok 45 selftests: arm64: hwcap
7342 13:44:11.364135 # selftests: arm64: ptrace
7343 13:44:11.364317 # TAP version 13
7344 13:44:11.367349 # 1..7
7345 13:44:11.367519 # # Parent is 1526, child is 1527
7346 13:44:11.370755 # ok 1 read_tpidr_one
7347 13:44:11.374002 # ok 2 write_tpidr_one
7348 13:44:11.374183 # ok 3 verify_tpidr_one
7349 13:44:11.377014 # ok 4 count_tpidrs
7350 13:44:11.380363 # ok 5 tpidr2_write
7351 13:44:11.380528 # ok 6 tpidr2_read
7352 13:44:11.383909 # ok 7 write_tpidr_only
7353 13:44:11.387022 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
7354 13:44:11.390148 ok 46 selftests: arm64: ptrace
7355 13:44:11.393356 # selftests: arm64: syscall-abi
7356 13:44:11.450209 # TAP version 13
7357 13:44:11.450388 # 1..2
7358 13:44:11.453152 # ok 1 getpid() FPSIMD
7359 13:44:11.456773 # ok 2 sched_yield() FPSIMD
7360 13:44:11.459968 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
7361 13:44:11.462949 ok 47 selftests: arm64: syscall-abi
7362 13:44:11.476499 # selftests: arm64: tpidr2
7363 13:44:11.542084 # Segmentation fault
7364 13:44:11.550075 not ok 48 selftests: arm64: tpidr2 # exit=139
7365 13:44:14.081696 arm64_tags_test pass
7366 13:44:14.085135 arm64_run_tags_test_sh pass
7367 13:44:14.088195 arm64_fake_sigreturn_bad_magic pass
7368 13:44:14.091650 arm64_fake_sigreturn_bad_size pass
7369 13:44:14.094803 arm64_fake_sigreturn_bad_size_for_magic0 pass
7370 13:44:14.097991 arm64_fake_sigreturn_duplicated_fpsimd pass
7371 13:44:14.101575 arm64_fake_sigreturn_misaligned_sp pass
7372 13:44:14.104369 arm64_fake_sigreturn_missing_fpsimd pass
7373 13:44:14.111222 arm64_fake_sigreturn_sme_change_vl skip
7374 13:44:14.114398 arm64_fake_sigreturn_sve_change_vl skip
7375 13:44:14.117627 arm64_mangle_pstate_invalid_compat_toggle pass
7376 13:44:14.120789 arm64_mangle_pstate_invalid_daif_bits pass
7377 13:44:14.124296 arm64_mangle_pstate_invalid_mode_el1h pass
7378 13:44:14.127420 arm64_mangle_pstate_invalid_mode_el1t pass
7379 13:44:14.134162 arm64_mangle_pstate_invalid_mode_el2h pass
7380 13:44:14.137336 arm64_mangle_pstate_invalid_mode_el2t pass
7381 13:44:14.140654 arm64_mangle_pstate_invalid_mode_el3h pass
7382 13:44:14.143642 arm64_mangle_pstate_invalid_mode_el3t pass
7383 13:44:14.147245 arm64_sme_trap_no_sm skip
7384 13:44:14.150223 arm64_sme_trap_non_streaming skip
7385 13:44:14.150388 arm64_sme_trap_za pass
7386 13:44:14.153692 arm64_sme_vl skip
7387 13:44:14.153854 arm64_ssve_regs skip
7388 13:44:14.156659 arm64_sve_regs skip
7389 13:44:14.160214 arm64_sve_vl skip
7390 13:44:14.160418 arm64_za_no_regs skip
7391 13:44:14.163529 arm64_za_regs skip
7392 13:44:14.166725 arm64_pac_PAUTH_not_enabled skip
7393 13:44:14.169954 arm64_pac_PAUTH_not_enabled_dup2 skip
7394 13:44:14.173094 arm64_pac_Generic_PAUTH_not_enabled skip
7395 13:44:14.176388 arm64_pac_PAUTH_not_enabled_dup3 skip
7396 13:44:14.179653 arm64_pac_PAUTH_not_enabled_dup4 skip
7397 13:44:14.182832 arm64_pac_PAUTH_not_enabled_dup5 skip
7398 13:44:14.186139 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
7399 13:44:14.189344 arm64_pac pass
7400 13:44:14.192504 arm64_fp-stress_FPSIMD-0-0 pass
7401 13:44:14.192663 arm64_fp-stress_FPSIMD-0-1 pass
7402 13:44:14.196268 arm64_fp-stress_FPSIMD-1-0 pass
7403 13:44:14.199185 arm64_fp-stress_FPSIMD-1-1 pass
7404 13:44:14.202292 arm64_fp-stress_FPSIMD-2-0 pass
7405 13:44:14.205804 arm64_fp-stress_FPSIMD-2-1 pass
7406 13:44:14.208964 arm64_fp-stress_FPSIMD-3-0 pass
7407 13:44:14.212378 arm64_fp-stress_FPSIMD-3-1 pass
7408 13:44:14.215728 arm64_fp-stress_FPSIMD-4-0 pass
7409 13:44:14.218885 arm64_fp-stress_FPSIMD-4-1 pass
7410 13:44:14.222107 arm64_fp-stress_FPSIMD-5-0 pass
7411 13:44:14.225212 arm64_fp-stress_FPSIMD-5-1 pass
7412 13:44:14.225374 arm64_fp-stress_FPSIMD-6-0 pass
7413 13:44:14.228672 arm64_fp-stress_FPSIMD-6-1 pass
7414 13:44:14.231738 arm64_fp-stress_FPSIMD-7-0 pass
7415 13:44:14.234905 arm64_fp-stress_FPSIMD-7-1 pass
7416 13:44:14.238443 arm64_fp-stress pass
7417 13:44:14.241495 arm64_sve-ptrace_SVE_not_available skip
7418 13:44:14.244626 arm64_sve-ptrace skip
7419 13:44:14.248138 arm64_sve-probe-vls_SVE_not_available skip
7420 13:44:14.248290 arm64_sve-probe-vls skip
7421 13:44:14.254561 arm64_vec-syscfg_SVE_not_supported skip
7422 13:44:14.257764 arm64_vec-syscfg_SVE_not_supported_dup2 skip
7423 13:44:14.261063 arm64_vec-syscfg_SVE_not_supported_dup3 skip
7424 13:44:14.264471 arm64_vec-syscfg_SVE_not_supported_dup4 skip
7425 13:44:14.270918 arm64_vec-syscfg_SVE_not_supported_dup5 skip
7426 13:44:14.274344 arm64_vec-syscfg_SVE_not_supported_dup6 skip
7427 13:44:14.277579 arm64_vec-syscfg_SVE_not_supported_dup7 skip
7428 13:44:14.280667 arm64_vec-syscfg_SVE_not_supported_dup8 skip
7429 13:44:14.287220 arm64_vec-syscfg_SVE_not_supported_dup9 skip
7430 13:44:14.290502 arm64_vec-syscfg_SVE_not_supported_dup10 skip
7431 13:44:14.293793 arm64_vec-syscfg_SME_not_supported skip
7432 13:44:14.297136 arm64_vec-syscfg_SME_not_supported_dup2 skip
7433 13:44:14.303367 arm64_vec-syscfg_SME_not_supported_dup3 skip
7434 13:44:14.306860 arm64_vec-syscfg_SME_not_supported_dup4 skip
7435 13:44:14.309890 arm64_vec-syscfg_SME_not_supported_dup5 skip
7436 13:44:14.313349 arm64_vec-syscfg_SME_not_supported_dup6 skip
7437 13:44:14.320035 arm64_vec-syscfg_SME_not_supported_dup7 skip
7438 13:44:14.323009 arm64_vec-syscfg_SME_not_supported_dup8 skip
7439 13:44:14.326119 arm64_vec-syscfg_SME_not_supported_dup9 skip
7440 13:44:14.332626 arm64_vec-syscfg_SME_not_supported_dup10 skip
7441 13:44:14.332806 arm64_vec-syscfg pass
7442 13:44:14.336151 arm64_za-fork_skipped pass
7443 13:44:14.339229 arm64_za-fork pass
7444 13:44:14.342655 arm64_za-ptrace_SME_not_available skip
7445 13:44:14.342809 arm64_za-ptrace skip
7446 13:44:14.345676 arm64_check_buffer_fill skip
7447 13:44:14.349270 arm64_check_child_memory skip
7448 13:44:14.352314 arm64_check_gcr_el1_cswitch skip
7449 13:44:14.355688 arm64_check_ksm_options skip
7450 13:44:14.355879 arm64_check_mmap_options skip
7451 13:44:14.362010 arm64_check_prctl_check_basic_read pass
7452 13:44:14.362167 arm64_check_prctl_NONE pass
7453 13:44:14.365272 arm64_check_prctl_SYNC skip
7454 13:44:14.368732 arm64_check_prctl_ASYNC skip
7455 13:44:14.371901 arm64_check_prctl_SYNC_ASYNC skip
7456 13:44:14.375374 arm64_check_prctl pass
7457 13:44:14.378450 arm64_check_tags_inclusion skip
7458 13:44:14.378624 arm64_check_user_mem skip
7459 13:44:14.385110 arm64_btitest_nohint_func_call_using_br_x0 skip
7460 13:44:14.388202 arm64_btitest_nohint_func_call_using_br_x16 skip
7461 13:44:14.391603 arm64_btitest_nohint_func_call_using_blr skip
7462 13:44:14.398046 arm64_btitest_bti_none_func_call_using_br_x0 skip
7463 13:44:14.401404 arm64_btitest_bti_none_func_call_using_br_x16 skip
7464 13:44:14.404603 arm64_btitest_bti_none_func_call_using_blr skip
7465 13:44:14.411168 arm64_btitest_bti_c_func_call_using_br_x0 skip
7466 13:44:14.414252 arm64_btitest_bti_c_func_call_using_br_x16 skip
7467 13:44:14.417952 arm64_btitest_bti_c_func_call_using_blr skip
7468 13:44:14.424057 arm64_btitest_bti_j_func_call_using_br_x0 skip
7469 13:44:14.427426 arm64_btitest_bti_j_func_call_using_br_x16 skip
7470 13:44:14.430946 arm64_btitest_bti_j_func_call_using_blr skip
7471 13:44:14.437439 arm64_btitest_bti_jc_func_call_using_br_x0 skip
7472 13:44:14.440448 arm64_btitest_bti_jc_func_call_using_br_x16 skip
7473 13:44:14.443890 arm64_btitest_bti_jc_func_call_using_blr skip
7474 13:44:14.447042 arm64_btitest_paciasp_func_call_using_br_x0 skip
7475 13:44:14.453581 arm64_btitest_paciasp_func_call_using_br_x16 skip
7476 13:44:14.456702 arm64_btitest_paciasp_func_call_using_blr skip
7477 13:44:14.460147 arm64_btitest pass
7478 13:44:14.463528 arm64_nobtitest_nohint_func_call_using_br_x0 skip
7479 13:44:14.466495 arm64_nobtitest_nohint_func_call_using_br_x16 skip
7480 13:44:14.473276 arm64_nobtitest_nohint_func_call_using_blr skip
7481 13:44:14.476361 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
7482 13:44:14.483028 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
7483 13:44:14.486083 arm64_nobtitest_bti_none_func_call_using_blr skip
7484 13:44:14.489564 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
7485 13:44:14.495865 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
7486 13:44:14.499055 arm64_nobtitest_bti_c_func_call_using_blr skip
7487 13:44:14.502512 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
7488 13:44:14.509088 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
7489 13:44:14.512026 arm64_nobtitest_bti_j_func_call_using_blr skip
7490 13:44:14.515248 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
7491 13:44:14.521911 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
7492 13:44:14.525124 arm64_nobtitest_bti_jc_func_call_using_blr skip
7493 13:44:14.528627 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
7494 13:44:14.534969 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
7495 13:44:14.538350 arm64_nobtitest_paciasp_func_call_using_blr skip
7496 13:44:14.541320 arm64_nobtitest pass
7497 13:44:14.544883 arm64_hwcap_cpuinfo_match_RNG pass
7498 13:44:14.545028 arm64_hwcap_sigill_RNG skip
7499 13:44:14.548067 arm64_hwcap_cpuinfo_match_SME pass
7500 13:44:14.551152 arm64_hwcap_sigill_SME pass
7501 13:44:14.554600 arm64_hwcap_cpuinfo_match_SVE pass
7502 13:44:14.558112 arm64_hwcap_sigill_SVE pass
7503 13:44:14.561274 arm64_hwcap_cpuinfo_match_SVE_2 pass
7504 13:44:14.564293 arm64_hwcap_sigill_SVE_2 skip
7505 13:44:14.567350 arm64_hwcap_cpuinfo_match_SVE_AES pass
7506 13:44:14.570856 arm64_hwcap_sigill_SVE_AES skip
7507 13:44:14.574096 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
7508 13:44:14.577325 arm64_hwcap_sigill_SVE2_PMULL skip
7509 13:44:14.580656 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
7510 13:44:14.583944 arm64_hwcap_sigill_SVE2_BITPERM skip
7511 13:44:14.587234 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
7512 13:44:14.590230 arm64_hwcap_sigill_SVE2_SHA3 skip
7513 13:44:14.593483 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
7514 13:44:14.596666 arm64_hwcap_sigill_SVE2_SM4 skip
7515 13:44:14.600181 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
7516 13:44:14.603171 arm64_hwcap_sigill_SVE2_I8MM skip
7517 13:44:14.606492 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
7518 13:44:14.610027 arm64_hwcap_sigill_SVE2_F32MM skip
7519 13:44:14.613092 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
7520 13:44:14.616252 arm64_hwcap_sigill_SVE2_F64MM skip
7521 13:44:14.623006 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
7522 13:44:14.623201 arm64_hwcap_sigill_SVE2_BF16 skip
7523 13:44:14.629353 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
7524 13:44:14.632645 arm64_hwcap_sigill_SVE2_EBF16 skip
7525 13:44:14.632819 arm64_hwcap pass
7526 13:44:14.635812 arm64_ptrace_read_tpidr_one pass
7527 13:44:14.639032 arm64_ptrace_write_tpidr_one pass
7528 13:44:14.642471 arm64_ptrace_verify_tpidr_one pass
7529 13:44:14.645631 arm64_ptrace_count_tpidrs pass
7530 13:44:14.649059 arm64_ptrace_tpidr2_write pass
7531 13:44:14.649257 arm64_ptrace_tpidr2_read pass
7532 13:44:14.652324 arm64_ptrace_write_tpidr_only pass
7533 13:44:14.655506 arm64_ptrace pass
7534 13:44:14.658983 arm64_syscall-abi_getpid_FPSIMD pass
7535 13:44:14.662044 arm64_syscall-abi_sched_yield_FPSIMD pass
7536 13:44:14.665486 arm64_syscall-abi pass
7537 13:44:14.665650 arm64_tpidr2 fail
7538 13:44:14.668712 + ../../utils/send-to-lava.sh ./output/result.txt
7539 13:44:14.675233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
7540 13:44:14.675637 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
7542 13:44:14.681612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
7543 13:44:14.681971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
7545 13:44:14.688250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
7546 13:44:14.688603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
7548 13:44:14.694636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
7549 13:44:14.694994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
7551 13:44:14.700987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
7552 13:44:14.701294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
7554 13:44:14.723532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
7555 13:44:14.723876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
7557 13:44:14.764040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
7558 13:44:14.764444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
7560 13:44:14.802147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
7561 13:44:14.802482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
7563 13:44:14.838757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
7564 13:44:14.839116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
7566 13:44:14.874450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
7567 13:44:14.874815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
7569 13:44:14.913458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
7570 13:44:14.913835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
7572 13:44:14.950157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
7573 13:44:14.950515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
7575 13:44:14.986684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
7576 13:44:14.987032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
7578 13:44:15.025124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
7579 13:44:15.025482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
7581 13:44:15.089019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
7582 13:44:15.089388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
7584 13:44:15.123659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
7585 13:44:15.124025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
7587 13:44:15.163231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
7588 13:44:15.163595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
7590 13:44:15.200411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
7591 13:44:15.200777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
7593 13:44:15.241204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
7594 13:44:15.241516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
7596 13:44:15.281268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
7597 13:44:15.281608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
7599 13:44:15.321599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
7600 13:44:15.321937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
7602 13:44:15.354080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
7603 13:44:15.354378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
7605 13:44:15.390443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
7606 13:44:15.390809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
7608 13:44:15.428166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
7609 13:44:15.428475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
7611 13:44:15.466632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
7612 13:44:15.467014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
7614 13:44:15.501571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
7615 13:44:15.501929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
7617 13:44:15.538635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
7618 13:44:15.538975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
7620 13:44:15.575291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
7621 13:44:15.575676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
7623 13:44:15.616414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
7625 13:44:15.619286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
7626 13:44:15.656542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
7627 13:44:15.656906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
7629 13:44:15.695830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
7630 13:44:15.696159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
7632 13:44:15.736363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
7633 13:44:15.736692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
7635 13:44:15.773467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
7636 13:44:15.773782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
7638 13:44:15.809677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
7639 13:44:15.810019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
7641 13:44:15.849094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
7642 13:44:15.849471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
7644 13:44:15.883003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
7645 13:44:15.883341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
7647 13:44:15.923310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
7649 13:44:15.926221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
7650 13:44:15.960135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
7652 13:44:15.963044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
7653 13:44:15.995141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
7655 13:44:15.998402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
7656 13:44:16.038965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
7658 13:44:16.042200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
7659 13:44:16.076782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
7661 13:44:16.079450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
7662 13:44:16.115499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
7664 13:44:16.118568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
7665 13:44:16.153367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
7667 13:44:16.156292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
7668 13:44:16.191148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
7670 13:44:16.194300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
7671 13:44:16.229644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
7673 13:44:16.232822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
7674 13:44:16.266400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
7676 13:44:16.269403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
7677 13:44:16.305592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
7679 13:44:16.308354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
7680 13:44:16.341748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
7682 13:44:16.344737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
7683 13:44:16.381305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
7685 13:44:16.384223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
7686 13:44:16.417192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
7688 13:44:16.420503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
7689 13:44:16.452539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
7691 13:44:16.455427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
7692 13:44:16.488552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
7694 13:44:16.491744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
7695 13:44:16.526866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
7696 13:44:16.527165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
7698 13:44:16.567049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
7699 13:44:16.567347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
7701 13:44:16.599975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
7702 13:44:16.600299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
7704 13:44:16.642349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
7705 13:44:16.642687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
7707 13:44:16.675234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
7708 13:44:16.675553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
7710 13:44:16.715204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
7711 13:44:16.715536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
7713 13:44:16.755260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
7714 13:44:16.755569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
7716 13:44:16.795752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
7717 13:44:16.796039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
7719 13:44:16.833047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
7720 13:44:16.833333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
7722 13:44:16.867503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
7723 13:44:16.867810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
7725 13:44:16.932753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
7726 13:44:16.933064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
7728 13:44:16.956367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
7729 13:44:16.956663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
7731 13:44:16.993729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
7732 13:44:16.994111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
7734 13:44:17.031233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
7735 13:44:17.031560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
7737 13:44:17.066182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
7738 13:44:17.066545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
7740 13:44:17.103182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
7741 13:44:17.103485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
7743 13:44:17.144338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
7744 13:44:17.144639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
7746 13:44:17.181043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
7747 13:44:17.181416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
7749 13:44:17.216615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
7750 13:44:17.216909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
7752 13:44:17.253039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
7753 13:44:17.253364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
7755 13:44:17.287504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
7756 13:44:17.287830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
7758 13:44:17.330718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
7759 13:44:17.331022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
7761 13:44:17.371827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
7762 13:44:17.372136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
7764 13:44:17.410674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
7765 13:44:17.410964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
7767 13:44:17.449468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
7768 13:44:17.449763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
7770 13:44:17.485879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
7771 13:44:17.486177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
7773 13:44:17.525249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
7774 13:44:17.525557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
7776 13:44:17.561652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
7777 13:44:17.561978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
7779 13:44:17.602011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
7780 13:44:17.602314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
7782 13:44:17.635559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
7783 13:44:17.635849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
7785 13:44:17.672741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
7786 13:44:17.673024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
7788 13:44:17.710847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
7789 13:44:17.711158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
7791 13:44:17.749300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
7793 13:44:17.752173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
7794 13:44:17.784867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
7795 13:44:17.785182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
7797 13:44:17.821458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
7798 13:44:17.821739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
7800 13:44:17.861811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
7801 13:44:17.862094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
7803 13:44:17.895223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
7804 13:44:17.895533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
7806 13:44:17.932183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
7807 13:44:17.932462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
7809 13:44:17.969109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
7810 13:44:17.969403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
7812 13:44:18.008187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
7813 13:44:18.008477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
7815 13:44:18.039972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
7816 13:44:18.040238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
7818 13:44:18.076261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
7820 13:44:18.079501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
7821 13:44:18.112627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
7822 13:44:18.112915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
7824 13:44:18.153317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
7825 13:44:18.153598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
7827 13:44:18.192764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
7828 13:44:18.193049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
7830 13:44:18.233216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
7831 13:44:18.233495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
7833 13:44:18.269804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
7834 13:44:18.270083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
7836 13:44:18.308338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
7837 13:44:18.308639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
7839 13:44:18.344459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
7840 13:44:18.344795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
7842 13:44:18.383054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
7843 13:44:18.383394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
7845 13:44:18.420555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
7846 13:44:18.420877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
7848 13:44:18.459812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
7849 13:44:18.460127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
7851 13:44:18.496676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
7852 13:44:18.496965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
7854 13:44:18.535866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
7855 13:44:18.536147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
7857 13:44:18.569754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
7858 13:44:18.570028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
7860 13:44:18.608728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
7861 13:44:18.609011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
7863 13:44:18.645578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
7864 13:44:18.645858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
7866 13:44:18.684589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
7867 13:44:18.684872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
7869 13:44:18.721436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
7870 13:44:18.721720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
7872 13:44:18.757176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
7873 13:44:18.757454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
7875 13:44:18.795410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
7876 13:44:18.795727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
7878 13:44:18.828339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
7879 13:44:18.828624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
7881 13:44:18.868059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
7882 13:44:18.868383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
7884 13:44:18.907065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
7885 13:44:18.907368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
7887 13:44:18.946321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
7888 13:44:18.946636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
7890 13:44:18.984115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
7891 13:44:18.984436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
7893 13:44:19.020681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
7894 13:44:19.020996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
7896 13:44:19.059979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
7897 13:44:19.060333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
7899 13:44:19.097488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
7900 13:44:19.097832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
7902 13:44:19.135172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
7903 13:44:19.135482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
7905 13:44:19.172820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
7906 13:44:19.173165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
7908 13:44:19.209244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
7909 13:44:19.209550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
7911 13:44:19.245422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
7912 13:44:19.245746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
7914 13:44:19.281567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
7915 13:44:19.281885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
7917 13:44:19.317255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
7918 13:44:19.317560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
7920 13:44:19.360043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
7921 13:44:19.360369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
7923 13:44:19.397757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
7924 13:44:19.398052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
7926 13:44:19.436600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
7927 13:44:19.436885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
7929 13:44:19.476503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
7930 13:44:19.476788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
7932 13:44:19.516003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
7933 13:44:19.516282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
7935 13:44:19.550298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
7936 13:44:19.550600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
7938 13:44:19.593507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
7939 13:44:19.593859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
7941 13:44:19.625261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
7942 13:44:19.625559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
7944 13:44:19.667269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
7945 13:44:19.667566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
7947 13:44:19.701690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
7948 13:44:19.702040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
7950 13:44:19.743406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
7951 13:44:19.743746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
7953 13:44:19.779260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
7954 13:44:19.779583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
7956 13:44:19.820630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
7957 13:44:19.820962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
7959 13:44:19.852172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
7960 13:44:19.852492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
7962 13:44:19.890310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
7963 13:44:19.890610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
7965 13:44:19.923592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
7967 13:44:19.926508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
7968 13:44:19.966756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
7969 13:44:19.967067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
7971 13:44:20.005383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
7972 13:44:20.005693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
7974 13:44:20.045186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
7975 13:44:20.045490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
7977 13:44:20.083820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
7978 13:44:20.084107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
7980 13:44:20.121445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
7981 13:44:20.121752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
7983 13:44:20.161219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
7984 13:44:20.161491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
7986 13:44:20.198853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
7987 13:44:20.199148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
7989 13:44:20.235149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
7991 13:44:20.237987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
7992 13:44:20.277110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
7993 13:44:20.277391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
7995 13:44:20.315434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
7996 13:44:20.315756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
7998 13:44:20.357757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
7999 13:44:20.358081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
8001 13:44:20.397663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
8002 13:44:20.397948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
8004 13:44:20.437712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
8005 13:44:20.438047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
8007 13:44:20.475498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
8008 13:44:20.475781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
8010 13:44:20.514467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
8011 13:44:20.514758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
8013 13:44:20.552604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
8014 13:44:20.552897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
8016 13:44:20.591681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
8017 13:44:20.591983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
8019 13:44:20.629844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
8020 13:44:20.630160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
8022 13:44:20.663868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
8023 13:44:20.664152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
8025 13:44:20.702107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
8027 13:44:20.704940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
8028 13:44:20.740790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
8029 13:44:20.741093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
8031 13:44:20.777116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
8032 13:44:20.777398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
8034 13:44:20.811445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
8035 13:44:20.811756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
8037 13:44:20.851861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
8038 13:44:20.852155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
8040 13:44:20.888955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
8041 13:44:20.889316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
8043 13:44:20.927733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
8044 13:44:20.928082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
8046 13:44:20.962926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
8047 13:44:20.963260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
8049 13:44:21.000819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
8050 13:44:21.001143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
8052 13:44:21.040271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
8053 13:44:21.040621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
8055 13:44:21.074649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
8056 13:44:21.074934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
8058 13:44:21.112171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=fail>
8059 13:44:21.112346 + set +x
8060 13:44:21.112641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=fail
8062 13:44:21.118680 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 14879035_1.6.2.3.5>
8063 13:44:21.118977 Received signal: <ENDRUN> 1_kselftest-arm64 14879035_1.6.2.3.5
8064 13:44:21.119099 Ending use of test pattern.
8065 13:44:21.119208 Ending test lava.1_kselftest-arm64 (14879035_1.6.2.3.5), duration 35.81
8067 13:44:21.121885 <LAVA_TEST_RUNNER EXIT>
8068 13:44:21.122178 ok: lava_test_shell seems to have completed
8069 13:44:21.124102 shardfile-arm64: pass
arm64_tags_test: pass
arm64_run_tags_test_sh: pass
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_fp-stress: pass
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-probe-vls: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg: pass
arm64_za-fork_skipped: pass
arm64_za-fork: pass
arm64_za-ptrace_SME_not_available: skip
arm64_za-ptrace: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest: pass
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_SVE_AES: skip
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_write_tpidr_only: pass
arm64_ptrace: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_syscall-abi: pass
arm64_tpidr2: fail
8070 13:44:21.124406 end: 3.1 lava-test-shell (duration 00:00:37) [common]
8071 13:44:21.124552 end: 3 lava-test-retry (duration 00:00:37) [common]
8072 13:44:21.124697 start: 4 finalize (timeout 00:07:27) [common]
8073 13:44:21.124847 start: 4.1 power-off (timeout 00:00:30) [common]
8074 13:44:21.125089 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-2', '--port=1', '--command=off']
8075 13:44:23.205489 >> Command sent successfully.
8076 13:44:23.209568 Returned 0 in 2 seconds
8077 13:44:23.209802 end: 4.1 power-off (duration 00:00:02) [common]
8079 13:44:23.210227 start: 4.2 read-feedback (timeout 00:07:25) [common]
8080 13:44:23.210462 Listened to connection for namespace 'common' for up to 1s
8081 13:44:24.211483 Finalising connection for namespace 'common'
8082 13:44:24.211710 Disconnecting from shell: Finalise
8083 13:44:24.211843 / #
8084 13:44:24.312169 end: 4.2 read-feedback (duration 00:00:01) [common]
8085 13:44:24.312332 end: 4 finalize (duration 00:00:03) [common]
8086 13:44:24.312450 Cleaning after the job
8087 13:44:24.312569 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879035/tftp-deploy-nycbem4k/ramdisk
8088 13:44:24.313245 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879035/tftp-deploy-nycbem4k/kernel
8089 13:44:24.315832 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879035/tftp-deploy-nycbem4k/dtb
8090 13:44:24.316013 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879035/tftp-deploy-nycbem4k/nfsrootfs
8091 13:44:24.331727 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879035/tftp-deploy-nycbem4k/modules
8092 13:44:24.333131 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14879035
8093 13:44:27.388672 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14879035
8094 13:44:27.388868 Job finished correctly