Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 33
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 13:26:11.354009 lava-dispatcher, installed at version: 2024.05
2 13:26:11.354216 start: 0 validate
3 13:26:11.354329 Start time: 2024-07-18 13:26:11.354323+00:00 (UTC)
4 13:26:11.354459 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:26:11.354599 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 13:26:11.856679 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:26:11.856839 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 13:26:12.114798 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:26:12.114981 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:26:12.376194 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:26:12.376339 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:26:12.634873 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:26:12.635032 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 13:26:12.886008 validate duration: 1.53
16 13:26:12.886257 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:26:12.886354 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:26:12.886432 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:26:12.886586 Not decompressing ramdisk as can be used compressed.
20 13:26:12.886673 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 13:26:12.886732 saving as /var/lib/lava/dispatcher/tmp/14879058/tftp-deploy-136pl3gy/ramdisk/initrd.cpio.gz
22 13:26:12.886791 total size: 5628169 (5 MB)
23 13:26:12.887761 progress 0 % (0 MB)
24 13:26:12.889606 progress 5 % (0 MB)
25 13:26:12.891132 progress 10 % (0 MB)
26 13:26:12.892524 progress 15 % (0 MB)
27 13:26:12.894072 progress 20 % (1 MB)
28 13:26:12.895440 progress 25 % (1 MB)
29 13:26:12.896945 progress 30 % (1 MB)
30 13:26:12.898499 progress 35 % (1 MB)
31 13:26:12.899838 progress 40 % (2 MB)
32 13:26:12.901423 progress 45 % (2 MB)
33 13:26:12.902796 progress 50 % (2 MB)
34 13:26:12.904302 progress 55 % (2 MB)
35 13:26:12.905824 progress 60 % (3 MB)
36 13:26:12.907146 progress 65 % (3 MB)
37 13:26:12.908601 progress 70 % (3 MB)
38 13:26:12.909994 progress 75 % (4 MB)
39 13:26:12.911479 progress 80 % (4 MB)
40 13:26:12.912775 progress 85 % (4 MB)
41 13:26:12.914301 progress 90 % (4 MB)
42 13:26:12.915738 progress 95 % (5 MB)
43 13:26:12.917066 progress 100 % (5 MB)
44 13:26:12.917305 5 MB downloaded in 0.03 s (175.94 MB/s)
45 13:26:12.917448 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:26:12.917702 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:26:12.917780 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:26:12.917854 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:26:12.917987 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 13:26:12.918049 saving as /var/lib/lava/dispatcher/tmp/14879058/tftp-deploy-136pl3gy/kernel/Image
52 13:26:12.918100 total size: 54813184 (52 MB)
53 13:26:12.918153 No compression specified
54 13:26:12.919202 progress 0 % (0 MB)
55 13:26:12.932696 progress 5 % (2 MB)
56 13:26:12.946346 progress 10 % (5 MB)
57 13:26:12.960094 progress 15 % (7 MB)
58 13:26:12.973928 progress 20 % (10 MB)
59 13:26:12.987769 progress 25 % (13 MB)
60 13:26:13.000821 progress 30 % (15 MB)
61 13:26:13.013994 progress 35 % (18 MB)
62 13:26:13.027657 progress 40 % (20 MB)
63 13:26:13.041602 progress 45 % (23 MB)
64 13:26:13.055543 progress 50 % (26 MB)
65 13:26:13.069516 progress 55 % (28 MB)
66 13:26:13.083234 progress 60 % (31 MB)
67 13:26:13.097000 progress 65 % (34 MB)
68 13:26:13.110271 progress 70 % (36 MB)
69 13:26:13.123716 progress 75 % (39 MB)
70 13:26:13.137335 progress 80 % (41 MB)
71 13:26:13.150629 progress 85 % (44 MB)
72 13:26:13.164124 progress 90 % (47 MB)
73 13:26:13.177511 progress 95 % (49 MB)
74 13:26:13.190785 progress 100 % (52 MB)
75 13:26:13.190998 52 MB downloaded in 0.27 s (191.55 MB/s)
76 13:26:13.191146 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:26:13.191364 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:26:13.191445 start: 1.3 download-retry (timeout 00:10:00) [common]
80 13:26:13.191520 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 13:26:13.191688 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:26:13.191773 saving as /var/lib/lava/dispatcher/tmp/14879058/tftp-deploy-136pl3gy/dtb/mt8192-asurada-spherion-r0.dtb
83 13:26:13.191852 total size: 47258 (0 MB)
84 13:26:13.191936 No compression specified
85 13:26:13.193306 progress 69 % (0 MB)
86 13:26:13.193576 progress 100 % (0 MB)
87 13:26:13.193720 0 MB downloaded in 0.00 s (24.15 MB/s)
88 13:26:13.193840 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:26:13.194039 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:26:13.194112 start: 1.4 download-retry (timeout 00:10:00) [common]
92 13:26:13.194198 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 13:26:13.194305 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 13:26:13.194364 saving as /var/lib/lava/dispatcher/tmp/14879058/tftp-deploy-136pl3gy/nfsrootfs/full.rootfs.tar
95 13:26:13.194415 total size: 120894716 (115 MB)
96 13:26:13.194468 Using unxz to decompress xz
97 13:26:13.195729 progress 0 % (0 MB)
98 13:26:13.531413 progress 5 % (5 MB)
99 13:26:13.871518 progress 10 % (11 MB)
100 13:26:14.205996 progress 15 % (17 MB)
101 13:26:14.519154 progress 20 % (23 MB)
102 13:26:14.821473 progress 25 % (28 MB)
103 13:26:15.159164 progress 30 % (34 MB)
104 13:26:15.473290 progress 35 % (40 MB)
105 13:26:15.642066 progress 40 % (46 MB)
106 13:26:15.825913 progress 45 % (51 MB)
107 13:26:16.118451 progress 50 % (57 MB)
108 13:26:16.465701 progress 55 % (63 MB)
109 13:26:16.800996 progress 60 % (69 MB)
110 13:26:17.132448 progress 65 % (74 MB)
111 13:26:17.462484 progress 70 % (80 MB)
112 13:26:17.800515 progress 75 % (86 MB)
113 13:26:18.125949 progress 80 % (92 MB)
114 13:26:18.450186 progress 85 % (98 MB)
115 13:26:18.773300 progress 90 % (103 MB)
116 13:26:19.084943 progress 95 % (109 MB)
117 13:26:19.426912 progress 100 % (115 MB)
118 13:26:19.432111 115 MB downloaded in 6.24 s (18.48 MB/s)
119 13:26:19.432281 end: 1.4.1 http-download (duration 00:00:06) [common]
121 13:26:19.432516 end: 1.4 download-retry (duration 00:00:06) [common]
122 13:26:19.432632 start: 1.5 download-retry (timeout 00:09:53) [common]
123 13:26:19.432744 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 13:26:19.432912 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 13:26:19.432976 saving as /var/lib/lava/dispatcher/tmp/14879058/tftp-deploy-136pl3gy/modules/modules.tar
126 13:26:19.433031 total size: 8611320 (8 MB)
127 13:26:19.433086 Using unxz to decompress xz
128 13:26:19.434342 progress 0 % (0 MB)
129 13:26:19.454826 progress 5 % (0 MB)
130 13:26:19.479199 progress 10 % (0 MB)
131 13:26:19.502956 progress 15 % (1 MB)
132 13:26:19.526881 progress 20 % (1 MB)
133 13:26:19.550112 progress 25 % (2 MB)
134 13:26:19.573345 progress 30 % (2 MB)
135 13:26:19.595558 progress 35 % (2 MB)
136 13:26:19.621708 progress 40 % (3 MB)
137 13:26:19.645798 progress 45 % (3 MB)
138 13:26:19.669704 progress 50 % (4 MB)
139 13:26:19.693945 progress 55 % (4 MB)
140 13:26:19.717702 progress 60 % (4 MB)
141 13:26:19.740649 progress 65 % (5 MB)
142 13:26:19.765795 progress 70 % (5 MB)
143 13:26:19.792332 progress 75 % (6 MB)
144 13:26:19.819332 progress 80 % (6 MB)
145 13:26:19.842857 progress 85 % (7 MB)
146 13:26:19.866101 progress 90 % (7 MB)
147 13:26:19.889089 progress 95 % (7 MB)
148 13:26:19.911663 progress 100 % (8 MB)
149 13:26:19.917180 8 MB downloaded in 0.48 s (16.96 MB/s)
150 13:26:19.917381 end: 1.5.1 http-download (duration 00:00:00) [common]
152 13:26:19.917602 end: 1.5 download-retry (duration 00:00:00) [common]
153 13:26:19.917681 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 13:26:19.917757 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 13:26:23.481694 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14879058/extract-nfsrootfs-h0v4silq
156 13:26:23.481874 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 13:26:23.481971 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 13:26:23.482139 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t
159 13:26:23.482262 makedir: /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin
160 13:26:23.482358 makedir: /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/tests
161 13:26:23.482448 makedir: /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/results
162 13:26:23.482529 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-add-keys
163 13:26:23.482656 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-add-sources
164 13:26:23.482778 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-background-process-start
165 13:26:23.482894 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-background-process-stop
166 13:26:23.483016 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-common-functions
167 13:26:23.483136 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-echo-ipv4
168 13:26:23.483249 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-install-packages
169 13:26:23.483366 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-installed-packages
170 13:26:23.483482 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-os-build
171 13:26:23.483600 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-probe-channel
172 13:26:23.483712 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-probe-ip
173 13:26:23.483823 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-target-ip
174 13:26:23.483941 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-target-mac
175 13:26:23.484049 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-target-storage
176 13:26:23.484164 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-test-case
177 13:26:23.484282 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-test-event
178 13:26:23.484393 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-test-feedback
179 13:26:23.484506 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-test-raise
180 13:26:23.484619 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-test-reference
181 13:26:23.484732 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-test-runner
182 13:26:23.484845 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-test-set
183 13:26:23.484954 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-test-shell
184 13:26:23.485077 Updating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-add-keys (debian)
185 13:26:23.485220 Updating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-add-sources (debian)
186 13:26:23.485389 Updating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-install-packages (debian)
187 13:26:23.485520 Updating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-installed-packages (debian)
188 13:26:23.485649 Updating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/bin/lava-os-build (debian)
189 13:26:23.485759 Creating /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/environment
190 13:26:23.485849 LAVA metadata
191 13:26:23.485912 - LAVA_JOB_ID=14879058
192 13:26:23.485969 - LAVA_DISPATCHER_IP=192.168.201.1
193 13:26:23.486075 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 13:26:23.486132 skipped lava-vland-overlay
195 13:26:23.486198 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 13:26:23.486269 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 13:26:23.486321 skipped lava-multinode-overlay
198 13:26:23.486390 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 13:26:23.486463 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 13:26:23.486530 Loading test definitions
201 13:26:23.486606 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 13:26:23.486664 Using /lava-14879058 at stage 0
203 13:26:23.486946 uuid=14879058_1.6.2.3.1 testdef=None
204 13:26:23.487028 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 13:26:23.487102 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 13:26:23.487499 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 13:26:23.487700 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 13:26:23.488217 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 13:26:23.488431 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 13:26:23.488928 runner path: /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/0/tests/0_timesync-off test_uuid 14879058_1.6.2.3.1
213 13:26:23.489073 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 13:26:23.489315 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 13:26:23.489379 Using /lava-14879058 at stage 0
217 13:26:23.489467 Fetching tests from https://github.com/kernelci/test-definitions.git
218 13:26:23.489545 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/0/tests/1_kselftest-arm64'
219 13:26:26.586927 Running '/usr/bin/git checkout kernelci.org
220 13:26:26.732622 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 13:26:26.732988 uuid=14879058_1.6.2.3.5 testdef=None
222 13:26:26.733091 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 13:26:26.733329 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 13:26:26.734024 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 13:26:26.734224 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 13:26:26.735100 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 13:26:26.735311 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 13:26:26.736160 runner path: /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/0/tests/1_kselftest-arm64 test_uuid 14879058_1.6.2.3.5
232 13:26:26.736239 BOARD='mt8192-asurada-spherion-r0'
233 13:26:26.736298 BRANCH='cip'
234 13:26:26.736351 SKIPFILE='/dev/null'
235 13:26:26.736401 SKIP_INSTALL='True'
236 13:26:26.736450 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz'
237 13:26:26.736501 TST_CASENAME=''
238 13:26:26.736549 TST_CMDFILES='arm64'
239 13:26:26.736680 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 13:26:26.736859 Creating lava-test-runner.conf files
242 13:26:26.736915 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14879058/lava-overlay-are26a0t/lava-14879058/0 for stage 0
243 13:26:26.736994 - 0_timesync-off
244 13:26:26.737053 - 1_kselftest-arm64
245 13:26:26.737139 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 13:26:26.737215 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 13:26:33.927787 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 13:26:33.927917 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 13:26:33.928003 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 13:26:33.928082 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 13:26:33.928159 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 13:26:34.069139 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 13:26:34.069298 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 13:26:34.069375 extracting modules file /var/lib/lava/dispatcher/tmp/14879058/tftp-deploy-136pl3gy/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14879058/extract-nfsrootfs-h0v4silq
255 13:26:34.282926 extracting modules file /var/lib/lava/dispatcher/tmp/14879058/tftp-deploy-136pl3gy/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14879058/extract-overlay-ramdisk-aj9408fq/ramdisk
256 13:26:34.501476 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 13:26:34.501614 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 13:26:34.501697 [common] Applying overlay to NFS
259 13:26:34.501756 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14879058/compress-overlay-0gz92gz4/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14879058/extract-nfsrootfs-h0v4silq
260 13:26:35.326918 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 13:26:35.327060 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 13:26:35.327140 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 13:26:35.327217 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 13:26:35.327285 Building ramdisk /var/lib/lava/dispatcher/tmp/14879058/extract-overlay-ramdisk-aj9408fq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14879058/extract-overlay-ramdisk-aj9408fq/ramdisk
265 13:26:35.613343 >> 129966 blocks
266 13:26:37.645896 rename /var/lib/lava/dispatcher/tmp/14879058/extract-overlay-ramdisk-aj9408fq/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14879058/tftp-deploy-136pl3gy/ramdisk/ramdisk.cpio.gz
267 13:26:37.646067 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 13:26:37.646155 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 13:26:37.646231 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 13:26:37.646309 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14879058/tftp-deploy-136pl3gy/kernel/Image']
271 13:26:52.504059 Returned 0 in 14 seconds
272 13:26:52.504267 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14879058/tftp-deploy-136pl3gy/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14879058/tftp-deploy-136pl3gy/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14879058/tftp-deploy-136pl3gy/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14879058/tftp-deploy-136pl3gy/kernel/image.itb
273 13:26:52.883528 output: FIT description: Kernel Image image with one or more FDT blobs
274 13:26:52.883658 output: Created: Thu Jul 18 14:26:52 2024
275 13:26:52.883720 output: Image 0 (kernel-1)
276 13:26:52.883776 output: Description:
277 13:26:52.883828 output: Created: Thu Jul 18 14:26:52 2024
278 13:26:52.883887 output: Type: Kernel Image
279 13:26:52.883941 output: Compression: lzma compressed
280 13:26:52.883993 output: Data Size: 13114469 Bytes = 12807.10 KiB = 12.51 MiB
281 13:26:52.884043 output: Architecture: AArch64
282 13:26:52.884091 output: OS: Linux
283 13:26:52.884139 output: Load Address: 0x00000000
284 13:26:52.884186 output: Entry Point: 0x00000000
285 13:26:52.884234 output: Hash algo: crc32
286 13:26:52.884281 output: Hash value: a47b020b
287 13:26:52.884329 output: Image 1 (fdt-1)
288 13:26:52.884376 output: Description: mt8192-asurada-spherion-r0
289 13:26:52.884423 output: Created: Thu Jul 18 14:26:52 2024
290 13:26:52.884470 output: Type: Flat Device Tree
291 13:26:52.884516 output: Compression: uncompressed
292 13:26:52.884602 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 13:26:52.884680 output: Architecture: AArch64
294 13:26:52.884775 output: Hash algo: crc32
295 13:26:52.884836 output: Hash value: 0f8e4d2e
296 13:26:52.884883 output: Image 2 (ramdisk-1)
297 13:26:52.884930 output: Description: unavailable
298 13:26:52.884977 output: Created: Thu Jul 18 14:26:52 2024
299 13:26:52.885025 output: Type: RAMDisk Image
300 13:26:52.885072 output: Compression: uncompressed
301 13:26:52.885119 output: Data Size: 18719426 Bytes = 18280.69 KiB = 17.85 MiB
302 13:26:52.885165 output: Architecture: AArch64
303 13:26:52.885211 output: OS: Linux
304 13:26:52.885297 output: Load Address: unavailable
305 13:26:52.885343 output: Entry Point: unavailable
306 13:26:52.885390 output: Hash algo: crc32
307 13:26:52.885437 output: Hash value: ae29cbcb
308 13:26:52.885483 output: Default Configuration: 'conf-1'
309 13:26:52.885530 output: Configuration 0 (conf-1)
310 13:26:52.885577 output: Description: mt8192-asurada-spherion-r0
311 13:26:52.885623 output: Kernel: kernel-1
312 13:26:52.885670 output: Init Ramdisk: ramdisk-1
313 13:26:52.885717 output: FDT: fdt-1
314 13:26:52.885763 output: Loadables: kernel-1
315 13:26:52.885810 output:
316 13:26:52.885908 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 13:26:52.885980 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 13:26:52.886053 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 13:26:52.886126 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 13:26:52.886182 No LXC device requested
321 13:26:52.886246 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 13:26:52.886315 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 13:26:52.886381 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 13:26:52.886435 Checking files for TFTP limit of 4294967296 bytes.
325 13:26:52.886797 end: 1 tftp-deploy (duration 00:00:40) [common]
326 13:26:52.886884 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 13:26:52.886963 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 13:26:52.887050 substitutions:
329 13:26:52.887108 - {DTB}: 14879058/tftp-deploy-136pl3gy/dtb/mt8192-asurada-spherion-r0.dtb
330 13:26:52.887163 - {INITRD}: 14879058/tftp-deploy-136pl3gy/ramdisk/ramdisk.cpio.gz
331 13:26:52.887215 - {KERNEL}: 14879058/tftp-deploy-136pl3gy/kernel/Image
332 13:26:52.887266 - {LAVA_MAC}: None
333 13:26:52.887315 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14879058/extract-nfsrootfs-h0v4silq
334 13:26:52.887364 - {NFS_SERVER_IP}: 192.168.201.1
335 13:26:52.887412 - {PRESEED_CONFIG}: None
336 13:26:52.887467 - {PRESEED_LOCAL}: None
337 13:26:52.887517 - {RAMDISK}: 14879058/tftp-deploy-136pl3gy/ramdisk/ramdisk.cpio.gz
338 13:26:52.887564 - {ROOT_PART}: None
339 13:26:52.887612 - {ROOT}: None
340 13:26:52.887659 - {SERVER_IP}: 192.168.201.1
341 13:26:52.887705 - {TEE}: None
342 13:26:52.887753 Parsed boot commands:
343 13:26:52.887799 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 13:26:52.887931 Parsed boot commands: tftpboot 192.168.201.1 14879058/tftp-deploy-136pl3gy/kernel/image.itb 14879058/tftp-deploy-136pl3gy/kernel/cmdline
345 13:26:52.888009 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 13:26:52.888081 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 13:26:52.888152 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 13:26:52.888222 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 13:26:52.888276 Not connected, no need to disconnect.
350 13:26:52.888339 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 13:26:52.888406 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 13:26:52.888459 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 13:26:52.891225 Setting prompt string to ['lava-test: # ']
354 13:26:52.891521 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 13:26:52.891617 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 13:26:52.891705 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 13:26:52.891802 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 13:26:52.891989 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=reboot']
359 13:27:02.043101 >> Command sent successfully.
360 13:27:02.061527 Returned 0 in 9 seconds
361 13:27:02.062129 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 13:27:02.063113 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 13:27:02.063523 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 13:27:02.063868 Setting prompt string to 'Starting depthcharge on Spherion...'
366 13:27:02.064152 Changing prompt to 'Starting depthcharge on Spherion...'
367 13:27:02.064439 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 13:27:02.066012 [Enter `^Ec?' for help]
369 13:27:03.433721
370 13:27:03.433859
371 13:27:03.433919 F0: 102B 0000
372 13:27:03.433975
373 13:27:03.434026 F3: 1001 0000 [0200]
374 13:27:03.434081
375 13:27:03.437711 F3: 1001 0000
376 13:27:03.437789
377 13:27:03.437848 F7: 102D 0000
378 13:27:03.437905
379 13:27:03.437958 F1: 0000 0000
380 13:27:03.441163
381 13:27:03.441259 V0: 0000 0000 [0001]
382 13:27:03.441332
383 13:27:03.441385 00: 0007 8000
384 13:27:03.441438
385 13:27:03.444362 01: 0000 0000
386 13:27:03.444438
387 13:27:03.444495 BP: 0C00 0209 [0000]
388 13:27:03.444548
389 13:27:03.447951 G0: 1182 0000
390 13:27:03.448024
391 13:27:03.448081 EC: 0000 0021 [4000]
392 13:27:03.448134
393 13:27:03.451709 S7: 0000 0000 [0000]
394 13:27:03.451783
395 13:27:03.451840 CC: 0000 0000 [0001]
396 13:27:03.451892
397 13:27:03.455062 T0: 0000 0040 [010F]
398 13:27:03.455136
399 13:27:03.455192 Jump to BL
400 13:27:03.455245
401 13:27:03.480965
402 13:27:03.481040
403 13:27:03.487278 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 13:27:03.491095 ARM64: Exception handlers installed.
405 13:27:03.494328 ARM64: Testing exception
406 13:27:03.498892 ARM64: Done test exception
407 13:27:03.505769 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 13:27:03.516177 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 13:27:03.524023 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 13:27:03.531033 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 13:27:03.537600 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 13:27:03.545779 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 13:27:03.558383 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 13:27:03.565134 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 13:27:03.583829 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 13:27:03.587520 WDT: Last reset was cold boot
417 13:27:03.591569 SPI1(PAD0) initialized at 2873684 Hz
418 13:27:03.594410 SPI5(PAD0) initialized at 992727 Hz
419 13:27:03.597581 VBOOT: Loading verstage.
420 13:27:03.601072 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 13:27:03.605183 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 13:27:03.612002 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 13:27:03.616063 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 13:27:03.623000 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 13:27:03.630299 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 13:27:03.639849 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
427 13:27:03.639962
428 13:27:03.640021
429 13:27:03.650614 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 13:27:03.650693 ARM64: Exception handlers installed.
431 13:27:03.654191 ARM64: Testing exception
432 13:27:03.658146 ARM64: Done test exception
433 13:27:03.661303 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 13:27:03.664946 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 13:27:03.680675 Probing TPM: . done!
436 13:27:03.680750 TPM ready after 0 ms
437 13:27:03.684299 Connected to device vid:did:rid of 1ae0:0028:00
438 13:27:03.739946 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
439 13:27:03.740043 Initialized TPM device CR50 revision 0
440 13:27:03.751176 tlcl_send_startup: Startup return code is 0
441 13:27:03.751255 TPM: setup succeeded
442 13:27:03.762800 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 13:27:03.771205 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 13:27:03.781209 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 13:27:03.789981 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 13:27:03.793541 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 13:27:03.797126 in-header: 03 07 00 00 08 00 00 00
448 13:27:03.800480 in-data: aa e4 47 04 13 02 00 00
449 13:27:03.803553 Chrome EC: UHEPI supported
450 13:27:03.810160 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 13:27:03.813587 in-header: 03 a9 00 00 08 00 00 00
452 13:27:03.817149 in-data: 84 60 60 08 00 00 00 00
453 13:27:03.817231 Phase 1
454 13:27:03.824093 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 13:27:03.830093 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 13:27:03.833939 VB2:vb2_check_recovery() Recovery was requested manually
457 13:27:03.840632 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
458 13:27:03.840710 Recovery requested (1009000e)
459 13:27:03.849154 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 13:27:03.855178 tlcl_extend: response is 0
461 13:27:03.862988 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 13:27:03.868409 tlcl_extend: response is 0
463 13:27:03.875344 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 13:27:03.895636 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 13:27:03.902166 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 13:27:03.902242
467 13:27:03.902300
468 13:27:03.912296 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 13:27:03.915353 ARM64: Exception handlers installed.
470 13:27:03.918590 ARM64: Testing exception
471 13:27:03.918665 ARM64: Done test exception
472 13:27:03.941673 pmic_efuse_setting: Set efuses in 11 msecs
473 13:27:03.944324 pmwrap_interface_init: Select PMIF_VLD_RDY
474 13:27:03.951296 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 13:27:03.955048 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 13:27:03.960829 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 13:27:03.964403 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 13:27:03.971366 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 13:27:03.974549 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 13:27:03.977767 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 13:27:03.984806 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 13:27:03.987577 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 13:27:03.994503 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 13:27:03.998097 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 13:27:04.001030 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 13:27:04.007987 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 13:27:04.014142 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 13:27:04.017545 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 13:27:04.024307 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 13:27:04.031186 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 13:27:04.037559 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 13:27:04.041038 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 13:27:04.047562 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 13:27:04.054645 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 13:27:04.057591 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 13:27:04.064684 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 13:27:04.067892 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 13:27:04.074823 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 13:27:04.081206 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 13:27:04.084652 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 13:27:04.091182 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 13:27:04.094455 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 13:27:04.101154 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 13:27:04.104119 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 13:27:04.111153 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 13:27:04.114172 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 13:27:04.121173 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 13:27:04.124377 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 13:27:04.131013 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 13:27:04.134194 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 13:27:04.141437 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 13:27:04.144633 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 13:27:04.148393 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 13:27:04.152626 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 13:27:04.159552 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 13:27:04.162851 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 13:27:04.166388 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 13:27:04.169730 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 13:27:04.176627 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 13:27:04.180508 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 13:27:04.183952 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 13:27:04.186907 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 13:27:04.194020 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 13:27:04.196946 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 13:27:04.203536 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
526 13:27:04.213698 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 13:27:04.217334 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 13:27:04.226782 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 13:27:04.233588 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 13:27:04.237005 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 13:27:04.244042 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 13:27:04.247070 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 13:27:04.254235 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x1d
534 13:27:04.260686 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 13:27:04.264166 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 13:27:04.267838 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 13:27:04.279197 [RTC]rtc_get_frequency_meter,154: input=15, output=764
538 13:27:04.288127 [RTC]rtc_get_frequency_meter,154: input=23, output=948
539 13:27:04.297915 [RTC]rtc_get_frequency_meter,154: input=19, output=856
540 13:27:04.307083 [RTC]rtc_get_frequency_meter,154: input=17, output=811
541 13:27:04.316671 [RTC]rtc_get_frequency_meter,154: input=16, output=787
542 13:27:04.326078 [RTC]rtc_get_frequency_meter,154: input=16, output=787
543 13:27:04.335901 [RTC]rtc_get_frequency_meter,154: input=17, output=811
544 13:27:04.339157 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 13:27:04.346823 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 13:27:04.349785 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 13:27:04.353092 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 13:27:04.359589 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 13:27:04.362794 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 13:27:04.366371 ADC[4]: Raw value=670063 ID=5
551 13:27:04.366760 ADC[3]: Raw value=212917 ID=1
552 13:27:04.369284 RAM Code: 0x51
553 13:27:04.372691 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 13:27:04.379744 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 13:27:04.386168 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
556 13:27:04.393389 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
557 13:27:04.396263 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 13:27:04.399857 in-header: 03 07 00 00 08 00 00 00
559 13:27:04.402788 in-data: aa e4 47 04 13 02 00 00
560 13:27:04.406306 Chrome EC: UHEPI supported
561 13:27:04.412820 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 13:27:04.416105 in-header: 03 a9 00 00 08 00 00 00
563 13:27:04.419357 in-data: 84 60 60 08 00 00 00 00
564 13:27:04.423176 MRC: failed to locate region type 0.
565 13:27:04.429593 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 13:27:04.429982 DRAM-K: Running full calibration
567 13:27:04.435826 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
568 13:27:04.439644 header.status = 0x0
569 13:27:04.442920 header.version = 0x6 (expected: 0x6)
570 13:27:04.446291 header.size = 0xd00 (expected: 0xd00)
571 13:27:04.446677 header.flags = 0x0
572 13:27:04.452875 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 13:27:04.470802 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 13:27:04.477496 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 13:27:04.480918 dram_init: ddr_geometry: 0
576 13:27:04.484277 [EMI] MDL number = 0
577 13:27:04.484662 [EMI] Get MDL freq = 0
578 13:27:04.487872 dram_init: ddr_type: 0
579 13:27:04.488257 is_discrete_lpddr4: 1
580 13:27:04.490777 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 13:27:04.491164
582 13:27:04.491459
583 13:27:04.494302 [Bian_co] ETT version 0.0.0.1
584 13:27:04.500662 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
585 13:27:04.501050
586 13:27:04.504031 dramc_set_vcore_voltage set vcore to 650000
587 13:27:04.507413 Read voltage for 800, 4
588 13:27:04.507798 Vio18 = 0
589 13:27:04.508099 Vcore = 650000
590 13:27:04.508379 Vdram = 0
591 13:27:04.511107 Vddq = 0
592 13:27:04.511493 Vmddr = 0
593 13:27:04.513978 dram_init: config_dvfs: 1
594 13:27:04.517376 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 13:27:04.524226 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 13:27:04.527397 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 13:27:04.530657 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 13:27:04.533991 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 13:27:04.537296 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 13:27:04.540897 MEM_TYPE=3, freq_sel=18
601 13:27:04.543885 sv_algorithm_assistance_LP4_1600
602 13:27:04.547149 ============ PULL DRAM RESETB DOWN ============
603 13:27:04.550526 ========== PULL DRAM RESETB DOWN end =========
604 13:27:04.557326 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 13:27:04.560710 ===================================
606 13:27:04.564505 LPDDR4 DRAM CONFIGURATION
607 13:27:04.567501 ===================================
608 13:27:04.567950 EX_ROW_EN[0] = 0x0
609 13:27:04.570894 EX_ROW_EN[1] = 0x0
610 13:27:04.571384 LP4Y_EN = 0x0
611 13:27:04.574319 WORK_FSP = 0x0
612 13:27:04.574851 WL = 0x2
613 13:27:04.578002 RL = 0x2
614 13:27:04.578449 BL = 0x2
615 13:27:04.580754 RPST = 0x0
616 13:27:04.581265 RD_PRE = 0x0
617 13:27:04.584759 WR_PRE = 0x1
618 13:27:04.585417 WR_PST = 0x0
619 13:27:04.587528 DBI_WR = 0x0
620 13:27:04.588043 DBI_RD = 0x0
621 13:27:04.590842 OTF = 0x1
622 13:27:04.593877 ===================================
623 13:27:04.597514 ===================================
624 13:27:04.598044 ANA top config
625 13:27:04.600963 ===================================
626 13:27:04.604151 DLL_ASYNC_EN = 0
627 13:27:04.607415 ALL_SLAVE_EN = 1
628 13:27:04.610695 NEW_RANK_MODE = 1
629 13:27:04.611222 DLL_IDLE_MODE = 1
630 13:27:04.614473 LP45_APHY_COMB_EN = 1
631 13:27:04.617703 TX_ODT_DIS = 1
632 13:27:04.620793 NEW_8X_MODE = 1
633 13:27:04.624027 ===================================
634 13:27:04.627661 ===================================
635 13:27:04.630602 data_rate = 1600
636 13:27:04.631122 CKR = 1
637 13:27:04.633985 DQ_P2S_RATIO = 8
638 13:27:04.637536 ===================================
639 13:27:04.640743 CA_P2S_RATIO = 8
640 13:27:04.644251 DQ_CA_OPEN = 0
641 13:27:04.647217 DQ_SEMI_OPEN = 0
642 13:27:04.647617 CA_SEMI_OPEN = 0
643 13:27:04.651227 CA_FULL_RATE = 0
644 13:27:04.654206 DQ_CKDIV4_EN = 1
645 13:27:04.657502 CA_CKDIV4_EN = 1
646 13:27:04.660459 CA_PREDIV_EN = 0
647 13:27:04.663888 PH8_DLY = 0
648 13:27:04.664384 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 13:27:04.667776 DQ_AAMCK_DIV = 4
650 13:27:04.670946 CA_AAMCK_DIV = 4
651 13:27:04.674649 CA_ADMCK_DIV = 4
652 13:27:04.677384 DQ_TRACK_CA_EN = 0
653 13:27:04.680677 CA_PICK = 800
654 13:27:04.684616 CA_MCKIO = 800
655 13:27:04.685014 MCKIO_SEMI = 0
656 13:27:04.687127 PLL_FREQ = 3068
657 13:27:04.690662 DQ_UI_PI_RATIO = 32
658 13:27:04.694748 CA_UI_PI_RATIO = 0
659 13:27:04.697380 ===================================
660 13:27:04.700683 ===================================
661 13:27:04.703961 memory_type:LPDDR4
662 13:27:04.704347 GP_NUM : 10
663 13:27:04.707058 SRAM_EN : 1
664 13:27:04.710420 MD32_EN : 0
665 13:27:04.713761 ===================================
666 13:27:04.714147 [ANA_INIT] >>>>>>>>>>>>>>
667 13:27:04.717561 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 13:27:04.720653 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 13:27:04.724334 ===================================
670 13:27:04.727009 data_rate = 1600,PCW = 0X7600
671 13:27:04.730620 ===================================
672 13:27:04.733662 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 13:27:04.740335 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 13:27:04.743781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 13:27:04.751022 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 13:27:04.754129 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 13:27:04.757625 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 13:27:04.758026 [ANA_INIT] flow start
679 13:27:04.760530 [ANA_INIT] PLL >>>>>>>>
680 13:27:04.763926 [ANA_INIT] PLL <<<<<<<<
681 13:27:04.764309 [ANA_INIT] MIDPI >>>>>>>>
682 13:27:04.767570 [ANA_INIT] MIDPI <<<<<<<<
683 13:27:04.770652 [ANA_INIT] DLL >>>>>>>>
684 13:27:04.771036 [ANA_INIT] flow end
685 13:27:04.777334 ============ LP4 DIFF to SE enter ============
686 13:27:04.780871 ============ LP4 DIFF to SE exit ============
687 13:27:04.784152 [ANA_INIT] <<<<<<<<<<<<<
688 13:27:04.787088 [Flow] Enable top DCM control >>>>>
689 13:27:04.787487 [Flow] Enable top DCM control <<<<<
690 13:27:04.791072 Enable DLL master slave shuffle
691 13:27:04.796919 ==============================================================
692 13:27:04.800517 Gating Mode config
693 13:27:04.803851 ==============================================================
694 13:27:04.807093 Config description:
695 13:27:04.818007 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 13:27:04.821180 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 13:27:04.829348 SELPH_MODE 0: By rank 1: By Phase
698 13:27:04.832899 ==============================================================
699 13:27:04.836377 GAT_TRACK_EN = 1
700 13:27:04.839952 RX_GATING_MODE = 2
701 13:27:04.843587 RX_GATING_TRACK_MODE = 2
702 13:27:04.843986 SELPH_MODE = 1
703 13:27:04.847650 PICG_EARLY_EN = 1
704 13:27:04.850836 VALID_LAT_VALUE = 1
705 13:27:04.857202 ==============================================================
706 13:27:04.860977 Enter into Gating configuration >>>>
707 13:27:04.864206 Exit from Gating configuration <<<<
708 13:27:04.867585 Enter into DVFS_PRE_config >>>>>
709 13:27:04.877348 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 13:27:04.880996 Exit from DVFS_PRE_config <<<<<
711 13:27:04.884163 Enter into PICG configuration >>>>
712 13:27:04.887512 Exit from PICG configuration <<<<
713 13:27:04.890911 [RX_INPUT] configuration >>>>>
714 13:27:04.893994 [RX_INPUT] configuration <<<<<
715 13:27:04.897323 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 13:27:04.903792 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 13:27:04.911219 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 13:27:04.914186 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 13:27:04.920864 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 13:27:04.927463 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 13:27:04.930820 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 13:27:04.934309 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 13:27:04.940462 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 13:27:04.944106 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 13:27:04.947636 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 13:27:04.953963 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 13:27:04.957479 ===================================
728 13:27:04.957866 LPDDR4 DRAM CONFIGURATION
729 13:27:04.960420 ===================================
730 13:27:04.964094 EX_ROW_EN[0] = 0x0
731 13:27:04.964482 EX_ROW_EN[1] = 0x0
732 13:27:04.967626 LP4Y_EN = 0x0
733 13:27:04.968133 WORK_FSP = 0x0
734 13:27:04.971072 WL = 0x2
735 13:27:04.974261 RL = 0x2
736 13:27:04.974648 BL = 0x2
737 13:27:04.977637 RPST = 0x0
738 13:27:04.978025 RD_PRE = 0x0
739 13:27:04.980791 WR_PRE = 0x1
740 13:27:04.981173 WR_PST = 0x0
741 13:27:04.984296 DBI_WR = 0x0
742 13:27:04.984677 DBI_RD = 0x0
743 13:27:04.987565 OTF = 0x1
744 13:27:04.990757 ===================================
745 13:27:04.994121 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 13:27:04.997297 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 13:27:05.000921 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 13:27:05.004398 ===================================
749 13:27:05.007897 LPDDR4 DRAM CONFIGURATION
750 13:27:05.011259 ===================================
751 13:27:05.013849 EX_ROW_EN[0] = 0x10
752 13:27:05.014235 EX_ROW_EN[1] = 0x0
753 13:27:05.017287 LP4Y_EN = 0x0
754 13:27:05.017674 WORK_FSP = 0x0
755 13:27:05.020780 WL = 0x2
756 13:27:05.021164 RL = 0x2
757 13:27:05.023874 BL = 0x2
758 13:27:05.024261 RPST = 0x0
759 13:27:05.027227 RD_PRE = 0x0
760 13:27:05.030577 WR_PRE = 0x1
761 13:27:05.030962 WR_PST = 0x0
762 13:27:05.034675 DBI_WR = 0x0
763 13:27:05.035235 DBI_RD = 0x0
764 13:27:05.037687 OTF = 0x1
765 13:27:05.040697 ===================================
766 13:27:05.043855 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 13:27:05.048878 nWR fixed to 40
768 13:27:05.052324 [ModeRegInit_LP4] CH0 RK0
769 13:27:05.052709 [ModeRegInit_LP4] CH0 RK1
770 13:27:05.056050 [ModeRegInit_LP4] CH1 RK0
771 13:27:05.059034 [ModeRegInit_LP4] CH1 RK1
772 13:27:05.059426 match AC timing 12
773 13:27:05.065939 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
774 13:27:05.069322 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 13:27:05.072489 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 13:27:05.079289 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 13:27:05.082372 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 13:27:05.082817 [EMI DOE] emi_dcm 0
779 13:27:05.089421 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 13:27:05.089810 ==
781 13:27:05.092519 Dram Type= 6, Freq= 0, CH_0, rank 0
782 13:27:05.096252 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
783 13:27:05.096764 ==
784 13:27:05.102905 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 13:27:05.109284 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 13:27:05.116348 [CA 0] Center 37 (7~68) winsize 62
787 13:27:05.119771 [CA 1] Center 37 (7~68) winsize 62
788 13:27:05.123588 [CA 2] Center 35 (5~66) winsize 62
789 13:27:05.126793 [CA 3] Center 35 (5~66) winsize 62
790 13:27:05.130148 [CA 4] Center 34 (4~65) winsize 62
791 13:27:05.133017 [CA 5] Center 33 (3~64) winsize 62
792 13:27:05.133530
793 13:27:05.136467 [CmdBusTrainingLP45] Vref(ca) range 1: 30
794 13:27:05.136926
795 13:27:05.140471 [CATrainingPosCal] consider 1 rank data
796 13:27:05.143778 u2DelayCellTimex100 = 270/100 ps
797 13:27:05.147028 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 13:27:05.150687 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
799 13:27:05.153920 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 13:27:05.156883 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
801 13:27:05.163909 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
802 13:27:05.166852 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 13:27:05.167321
804 13:27:05.170409 CA PerBit enable=1, Macro0, CA PI delay=33
805 13:27:05.170852
806 13:27:05.173804 [CBTSetCACLKResult] CA Dly = 33
807 13:27:05.174238 CS Dly: 5 (0~36)
808 13:27:05.174709 ==
809 13:27:05.176885 Dram Type= 6, Freq= 0, CH_0, rank 1
810 13:27:05.183541 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 13:27:05.183628 ==
812 13:27:05.186491 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 13:27:05.192936 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 13:27:05.202076 [CA 0] Center 37 (7~68) winsize 62
815 13:27:05.205888 [CA 1] Center 37 (6~68) winsize 63
816 13:27:05.208748 [CA 2] Center 35 (4~66) winsize 63
817 13:27:05.212967 [CA 3] Center 35 (4~66) winsize 63
818 13:27:05.215363 [CA 4] Center 33 (3~64) winsize 62
819 13:27:05.218780 [CA 5] Center 34 (3~65) winsize 63
820 13:27:05.218918
821 13:27:05.222349 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 13:27:05.222506
823 13:27:05.225578 [CATrainingPosCal] consider 2 rank data
824 13:27:05.229164 u2DelayCellTimex100 = 270/100 ps
825 13:27:05.232845 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 13:27:05.235685 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 13:27:05.242437 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 13:27:05.246422 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
829 13:27:05.249673 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
830 13:27:05.252295 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 13:27:05.252679
832 13:27:05.255731 CA PerBit enable=1, Macro0, CA PI delay=33
833 13:27:05.256278
834 13:27:05.259112 [CBTSetCACLKResult] CA Dly = 33
835 13:27:05.259500 CS Dly: 5 (0~37)
836 13:27:05.259802
837 13:27:05.262759 ----->DramcWriteLeveling(PI) begin...
838 13:27:05.266585 ==
839 13:27:05.267103 Dram Type= 6, Freq= 0, CH_0, rank 0
840 13:27:05.273125 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
841 13:27:05.273589 ==
842 13:27:05.276066 Write leveling (Byte 0): 30 => 30
843 13:27:05.279515 Write leveling (Byte 1): 29 => 29
844 13:27:05.279902 DramcWriteLeveling(PI) end<-----
845 13:27:05.283030
846 13:27:05.283413 ==
847 13:27:05.286447 Dram Type= 6, Freq= 0, CH_0, rank 0
848 13:27:05.289097 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 13:27:05.289548 ==
850 13:27:05.292765 [Gating] SW mode calibration
851 13:27:05.299359 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 13:27:05.302954 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 13:27:05.309520 0 6 0 | B1->B0 | 3434 3131 | 0 0 | (0 1) (0 1)
854 13:27:05.312543 0 6 4 | B1->B0 | 2828 2424 | 0 0 | (1 1) (0 0)
855 13:27:05.316186 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 13:27:05.322639 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 13:27:05.325794 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 13:27:05.329308 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 13:27:05.335656 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 13:27:05.339112 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 13:27:05.342964 0 7 0 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
862 13:27:05.349530 0 7 4 | B1->B0 | 3a3a 4242 | 1 0 | (0 0) (0 0)
863 13:27:05.352717 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 13:27:05.356465 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 13:27:05.362404 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 13:27:05.365645 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 13:27:05.369497 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 13:27:05.375882 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 13:27:05.378978 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
870 13:27:05.382444 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 13:27:05.389395 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 13:27:05.392694 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 13:27:05.396452 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 13:27:05.399231 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 13:27:05.406369 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 13:27:05.409316 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 13:27:05.413280 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 13:27:05.419663 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 13:27:05.422857 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 13:27:05.426390 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 13:27:05.432733 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 13:27:05.436263 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 13:27:05.439272 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 13:27:05.446259 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 13:27:05.449678 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
886 13:27:05.453195 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 13:27:05.456077 Total UI for P1: 0, mck2ui 16
888 13:27:05.459845 best dqsien dly found for B0: ( 0, 10, 0)
889 13:27:05.463083 Total UI for P1: 0, mck2ui 16
890 13:27:05.466444 best dqsien dly found for B1: ( 0, 10, 0)
891 13:27:05.469457 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
892 13:27:05.472682 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
893 13:27:05.473066
894 13:27:05.475974 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
895 13:27:05.479302 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
896 13:27:05.483560 [Gating] SW calibration Done
897 13:27:05.483944 ==
898 13:27:05.486101 Dram Type= 6, Freq= 0, CH_0, rank 0
899 13:27:05.492564 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 13:27:05.492950 ==
901 13:27:05.493297 RX Vref Scan: 0
902 13:27:05.493592
903 13:27:05.496149 RX Vref 0 -> 0, step: 1
904 13:27:05.496534
905 13:27:05.499429 RX Delay -130 -> 252, step: 16
906 13:27:05.503027 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
907 13:27:05.506632 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
908 13:27:05.509937 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
909 13:27:05.513210 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
910 13:27:05.519808 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
911 13:27:05.522973 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
912 13:27:05.526351 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
913 13:27:05.529606 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
914 13:27:05.533361 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
915 13:27:05.539829 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
916 13:27:05.542736 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
917 13:27:05.546475 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
918 13:27:05.549654 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
919 13:27:05.552575 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
920 13:27:05.559505 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
921 13:27:05.563226 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
922 13:27:05.563611 ==
923 13:27:05.566402 Dram Type= 6, Freq= 0, CH_0, rank 0
924 13:27:05.569523 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
925 13:27:05.569980 ==
926 13:27:05.572989 DQS Delay:
927 13:27:05.573417 DQS0 = 0, DQS1 = 0
928 13:27:05.573724 DQM Delay:
929 13:27:05.576241 DQM0 = 86, DQM1 = 75
930 13:27:05.576622 DQ Delay:
931 13:27:05.579391 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
932 13:27:05.582481 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
933 13:27:05.585922 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =69
934 13:27:05.589367 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
935 13:27:05.589755
936 13:27:05.590051
937 13:27:05.590322 ==
938 13:27:05.592850 Dram Type= 6, Freq= 0, CH_0, rank 0
939 13:27:05.599569 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
940 13:27:05.600002 ==
941 13:27:05.600335
942 13:27:05.600638
943 13:27:05.600927 TX Vref Scan disable
944 13:27:05.603267 == TX Byte 0 ==
945 13:27:05.606244 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
946 13:27:05.609627 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
947 13:27:05.613192 == TX Byte 1 ==
948 13:27:05.616362 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
949 13:27:05.619388 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
950 13:27:05.622849 ==
951 13:27:05.626800 Dram Type= 6, Freq= 0, CH_0, rank 0
952 13:27:05.629643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
953 13:27:05.629983 ==
954 13:27:05.641679 TX Vref=22, minBit 0, minWin=27, winSum=444
955 13:27:05.645003 TX Vref=24, minBit 4, minWin=27, winSum=448
956 13:27:05.647958 TX Vref=26, minBit 4, minWin=27, winSum=451
957 13:27:05.651701 TX Vref=28, minBit 4, minWin=27, winSum=453
958 13:27:05.654630 TX Vref=30, minBit 0, minWin=28, winSum=455
959 13:27:05.658381 TX Vref=32, minBit 0, minWin=28, winSum=454
960 13:27:05.665183 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
961 13:27:05.665280
962 13:27:05.668186 Final TX Range 1 Vref 30
963 13:27:05.668272
964 13:27:05.668338 ==
965 13:27:05.671684 Dram Type= 6, Freq= 0, CH_0, rank 0
966 13:27:05.674645 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
967 13:27:05.674720 ==
968 13:27:05.674778
969 13:27:05.678259
970 13:27:05.678335 TX Vref Scan disable
971 13:27:05.681688 == TX Byte 0 ==
972 13:27:05.685072 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
973 13:27:05.687938 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
974 13:27:05.691276 == TX Byte 1 ==
975 13:27:05.694958 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
976 13:27:05.698415 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
977 13:27:05.701670
978 13:27:05.701746 [DATLAT]
979 13:27:05.701806 Freq=800, CH0 RK0
980 13:27:05.701862
981 13:27:05.704642 DATLAT Default: 0xa
982 13:27:05.704719 0, 0xFFFF, sum = 0
983 13:27:05.708073 1, 0xFFFF, sum = 0
984 13:27:05.708176 2, 0xFFFF, sum = 0
985 13:27:05.711350 3, 0xFFFF, sum = 0
986 13:27:05.711428 4, 0xFFFF, sum = 0
987 13:27:05.714803 5, 0xFFFF, sum = 0
988 13:27:05.718262 6, 0xFFFF, sum = 0
989 13:27:05.718342 7, 0xFFFF, sum = 0
990 13:27:05.718403 8, 0x0, sum = 1
991 13:27:05.721701 9, 0x0, sum = 2
992 13:27:05.721780 10, 0x0, sum = 3
993 13:27:05.724964 11, 0x0, sum = 4
994 13:27:05.725067 best_step = 9
995 13:27:05.725153
996 13:27:05.725241 ==
997 13:27:05.728538 Dram Type= 6, Freq= 0, CH_0, rank 0
998 13:27:05.734936 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
999 13:27:05.735019 ==
1000 13:27:05.735081 RX Vref Scan: 1
1001 13:27:05.735136
1002 13:27:05.738412 Set Vref Range= 32 -> 127
1003 13:27:05.738503
1004 13:27:05.741588 RX Vref 32 -> 127, step: 1
1005 13:27:05.741672
1006 13:27:05.741746 RX Delay -111 -> 252, step: 8
1007 13:27:05.744868
1008 13:27:05.744951 Set Vref, RX VrefLevel [Byte0]: 32
1009 13:27:05.747900 [Byte1]: 32
1010 13:27:05.752531
1011 13:27:05.752614 Set Vref, RX VrefLevel [Byte0]: 33
1012 13:27:05.755473 [Byte1]: 33
1013 13:27:05.760317
1014 13:27:05.760399 Set Vref, RX VrefLevel [Byte0]: 34
1015 13:27:05.763190 [Byte1]: 34
1016 13:27:05.767874
1017 13:27:05.767957 Set Vref, RX VrefLevel [Byte0]: 35
1018 13:27:05.771101 [Byte1]: 35
1019 13:27:05.775265
1020 13:27:05.775347 Set Vref, RX VrefLevel [Byte0]: 36
1021 13:27:05.778671 [Byte1]: 36
1022 13:27:05.783017
1023 13:27:05.783114 Set Vref, RX VrefLevel [Byte0]: 37
1024 13:27:05.786097 [Byte1]: 37
1025 13:27:05.791151
1026 13:27:05.791259 Set Vref, RX VrefLevel [Byte0]: 38
1027 13:27:05.793988 [Byte1]: 38
1028 13:27:05.798550
1029 13:27:05.798678 Set Vref, RX VrefLevel [Byte0]: 39
1030 13:27:05.801853 [Byte1]: 39
1031 13:27:05.806333
1032 13:27:05.806478 Set Vref, RX VrefLevel [Byte0]: 40
1033 13:27:05.809647 [Byte1]: 40
1034 13:27:05.813723
1035 13:27:05.813918 Set Vref, RX VrefLevel [Byte0]: 41
1036 13:27:05.816983 [Byte1]: 41
1037 13:27:05.821176
1038 13:27:05.824813 Set Vref, RX VrefLevel [Byte0]: 42
1039 13:27:05.825204 [Byte1]: 42
1040 13:27:05.829724
1041 13:27:05.830179 Set Vref, RX VrefLevel [Byte0]: 43
1042 13:27:05.832551 [Byte1]: 43
1043 13:27:05.836876
1044 13:27:05.837294 Set Vref, RX VrefLevel [Byte0]: 44
1045 13:27:05.840439 [Byte1]: 44
1046 13:27:05.844476
1047 13:27:05.844913 Set Vref, RX VrefLevel [Byte0]: 45
1048 13:27:05.847530 [Byte1]: 45
1049 13:27:05.852015
1050 13:27:05.852399 Set Vref, RX VrefLevel [Byte0]: 46
1051 13:27:05.855636 [Byte1]: 46
1052 13:27:05.859657
1053 13:27:05.860045 Set Vref, RX VrefLevel [Byte0]: 47
1054 13:27:05.863375 [Byte1]: 47
1055 13:27:05.867960
1056 13:27:05.868465 Set Vref, RX VrefLevel [Byte0]: 48
1057 13:27:05.870680 [Byte1]: 48
1058 13:27:05.875267
1059 13:27:05.875771 Set Vref, RX VrefLevel [Byte0]: 49
1060 13:27:05.878141 [Byte1]: 49
1061 13:27:05.883144
1062 13:27:05.883655 Set Vref, RX VrefLevel [Byte0]: 50
1063 13:27:05.886284 [Byte1]: 50
1064 13:27:05.891587
1065 13:27:05.892105 Set Vref, RX VrefLevel [Byte0]: 51
1066 13:27:05.893813 [Byte1]: 51
1067 13:27:05.898233
1068 13:27:05.898657 Set Vref, RX VrefLevel [Byte0]: 52
1069 13:27:05.901114 [Byte1]: 52
1070 13:27:05.906072
1071 13:27:05.906576 Set Vref, RX VrefLevel [Byte0]: 53
1072 13:27:05.909096 [Byte1]: 53
1073 13:27:05.913750
1074 13:27:05.914176 Set Vref, RX VrefLevel [Byte0]: 54
1075 13:27:05.916928 [Byte1]: 54
1076 13:27:05.921381
1077 13:27:05.921809 Set Vref, RX VrefLevel [Byte0]: 55
1078 13:27:05.924361 [Byte1]: 55
1079 13:27:05.928948
1080 13:27:05.929404 Set Vref, RX VrefLevel [Byte0]: 56
1081 13:27:05.931937 [Byte1]: 56
1082 13:27:05.936460
1083 13:27:05.936885 Set Vref, RX VrefLevel [Byte0]: 57
1084 13:27:05.939606 [Byte1]: 57
1085 13:27:05.943833
1086 13:27:05.944395 Set Vref, RX VrefLevel [Byte0]: 58
1087 13:27:05.947388 [Byte1]: 58
1088 13:27:05.952156
1089 13:27:05.952580 Set Vref, RX VrefLevel [Byte0]: 59
1090 13:27:05.954741 [Byte1]: 59
1091 13:27:05.959275
1092 13:27:05.959698 Set Vref, RX VrefLevel [Byte0]: 60
1093 13:27:05.962737 [Byte1]: 60
1094 13:27:05.967185
1095 13:27:05.967612 Set Vref, RX VrefLevel [Byte0]: 61
1096 13:27:05.970949 [Byte1]: 61
1097 13:27:05.974667
1098 13:27:05.975053 Set Vref, RX VrefLevel [Byte0]: 62
1099 13:27:05.978513 [Byte1]: 62
1100 13:27:05.982028
1101 13:27:05.982415 Set Vref, RX VrefLevel [Byte0]: 63
1102 13:27:05.985718 [Byte1]: 63
1103 13:27:05.990186
1104 13:27:05.990568 Set Vref, RX VrefLevel [Byte0]: 64
1105 13:27:05.993693 [Byte1]: 64
1106 13:27:05.997142
1107 13:27:05.997567 Set Vref, RX VrefLevel [Byte0]: 65
1108 13:27:06.001072 [Byte1]: 65
1109 13:27:06.005190
1110 13:27:06.005610 Set Vref, RX VrefLevel [Byte0]: 66
1111 13:27:06.008083 [Byte1]: 66
1112 13:27:06.012393
1113 13:27:06.012788 Set Vref, RX VrefLevel [Byte0]: 67
1114 13:27:06.016043 [Byte1]: 67
1115 13:27:06.020561
1116 13:27:06.020950 Set Vref, RX VrefLevel [Byte0]: 68
1117 13:27:06.023531 [Byte1]: 68
1118 13:27:06.027972
1119 13:27:06.028357 Set Vref, RX VrefLevel [Byte0]: 69
1120 13:27:06.031498 [Byte1]: 69
1121 13:27:06.035707
1122 13:27:06.036094 Set Vref, RX VrefLevel [Byte0]: 70
1123 13:27:06.039171 [Byte1]: 70
1124 13:27:06.042891
1125 13:27:06.043276 Set Vref, RX VrefLevel [Byte0]: 71
1126 13:27:06.046293 [Byte1]: 71
1127 13:27:06.051001
1128 13:27:06.051386 Set Vref, RX VrefLevel [Byte0]: 72
1129 13:27:06.054113 [Byte1]: 72
1130 13:27:06.058711
1131 13:27:06.059095 Set Vref, RX VrefLevel [Byte0]: 73
1132 13:27:06.061984 [Byte1]: 73
1133 13:27:06.066244
1134 13:27:06.066651 Set Vref, RX VrefLevel [Byte0]: 74
1135 13:27:06.069182 [Byte1]: 74
1136 13:27:06.073715
1137 13:27:06.074100 Final RX Vref Byte 0 = 51 to rank0
1138 13:27:06.077162 Final RX Vref Byte 1 = 54 to rank0
1139 13:27:06.080701 Final RX Vref Byte 0 = 51 to rank1
1140 13:27:06.083665 Final RX Vref Byte 1 = 54 to rank1==
1141 13:27:06.087202 Dram Type= 6, Freq= 0, CH_0, rank 0
1142 13:27:06.090710 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1143 13:27:06.093674 ==
1144 13:27:06.094058 DQS Delay:
1145 13:27:06.094358 DQS0 = 0, DQS1 = 0
1146 13:27:06.097071 DQM Delay:
1147 13:27:06.097490 DQM0 = 83, DQM1 = 72
1148 13:27:06.100582 DQ Delay:
1149 13:27:06.100968 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1150 13:27:06.104538 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1151 13:27:06.107393 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1152 13:27:06.110348 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1153 13:27:06.110737
1154 13:27:06.113687
1155 13:27:06.120666 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c3c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1156 13:27:06.124019 CH0 RK0: MR19=606, MR18=3C3C
1157 13:27:06.131599 CH0_RK0: MR19=0x606, MR18=0x3C3C, DQSOSC=394, MR23=63, INC=95, DEC=63
1158 13:27:06.132007
1159 13:27:06.134336 ----->DramcWriteLeveling(PI) begin...
1160 13:27:06.134666 ==
1161 13:27:06.137740 Dram Type= 6, Freq= 0, CH_0, rank 1
1162 13:27:06.140343 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1163 13:27:06.140734 ==
1164 13:27:06.143970 Write leveling (Byte 0): 28 => 28
1165 13:27:06.147246 Write leveling (Byte 1): 28 => 28
1166 13:27:06.150847 DramcWriteLeveling(PI) end<-----
1167 13:27:06.151236
1168 13:27:06.151528 ==
1169 13:27:06.153666 Dram Type= 6, Freq= 0, CH_0, rank 1
1170 13:27:06.157473 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1171 13:27:06.157866 ==
1172 13:27:06.160653 [Gating] SW mode calibration
1173 13:27:06.167278 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1174 13:27:06.173629 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1175 13:27:06.177198 0 6 0 | B1->B0 | 3232 3030 | 0 0 | (0 1) (0 0)
1176 13:27:06.180184 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 13:27:06.187388 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 13:27:06.190816 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 13:27:06.194120 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 13:27:06.200226 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 13:27:06.203697 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 13:27:06.206916 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 13:27:06.213505 0 7 0 | B1->B0 | 2828 2d2d | 0 1 | (0 0) (0 0)
1184 13:27:06.216603 0 7 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1185 13:27:06.219882 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 13:27:06.226476 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 13:27:06.229811 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 13:27:06.233770 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 13:27:06.236822 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 13:27:06.243525 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 13:27:06.246823 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1192 13:27:06.249860 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1193 13:27:06.256359 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 13:27:06.259844 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 13:27:06.263056 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 13:27:06.270540 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 13:27:06.273647 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 13:27:06.276615 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 13:27:06.283618 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 13:27:06.286575 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 13:27:06.289946 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 13:27:06.297088 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 13:27:06.299992 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 13:27:06.303471 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 13:27:06.310363 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 13:27:06.313446 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:27:06.316937 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1208 13:27:06.320076 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 13:27:06.323469 Total UI for P1: 0, mck2ui 16
1210 13:27:06.326947 best dqsien dly found for B0: ( 0, 10, 0)
1211 13:27:06.330130 Total UI for P1: 0, mck2ui 16
1212 13:27:06.333679 best dqsien dly found for B1: ( 0, 10, 0)
1213 13:27:06.336855 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1214 13:27:06.340200 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1215 13:27:06.343543
1216 13:27:06.346774 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1217 13:27:06.350479 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1218 13:27:06.353531 [Gating] SW calibration Done
1219 13:27:06.353607 ==
1220 13:27:06.357008 Dram Type= 6, Freq= 0, CH_0, rank 1
1221 13:27:06.400814 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1222 13:27:06.400899 ==
1223 13:27:06.401002 RX Vref Scan: 0
1224 13:27:06.401058
1225 13:27:06.401110 RX Vref 0 -> 0, step: 1
1226 13:27:06.401341
1227 13:27:06.401397 RX Delay -130 -> 252, step: 16
1228 13:27:06.401447 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1229 13:27:06.401495 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1230 13:27:06.401723 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1231 13:27:06.402359 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1232 13:27:06.402599 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1233 13:27:06.402654 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1234 13:27:06.402879 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1235 13:27:06.403229 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1236 13:27:06.403286 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1237 13:27:06.445165 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1238 13:27:06.445453 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1239 13:27:06.445527 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1240 13:27:06.445585 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1241 13:27:06.445649 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1242 13:27:06.446430 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1243 13:27:06.446875 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1244 13:27:06.446950 ==
1245 13:27:06.447008 Dram Type= 6, Freq= 0, CH_0, rank 1
1246 13:27:06.447241 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1247 13:27:06.447298 ==
1248 13:27:06.447350 DQS Delay:
1249 13:27:06.447417 DQS0 = 0, DQS1 = 0
1250 13:27:06.447502 DQM Delay:
1251 13:27:06.447555 DQM0 = 81, DQM1 = 74
1252 13:27:06.447606 DQ Delay:
1253 13:27:06.469170 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =69
1254 13:27:06.469282 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1255 13:27:06.469521 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1256 13:27:06.469581 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1257 13:27:06.469634
1258 13:27:06.469685
1259 13:27:06.469734 ==
1260 13:27:06.469783 Dram Type= 6, Freq= 0, CH_0, rank 1
1261 13:27:06.469832 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1262 13:27:06.469880 ==
1263 13:27:06.469928
1264 13:27:06.469976
1265 13:27:06.472678 TX Vref Scan disable
1266 13:27:06.472752 == TX Byte 0 ==
1267 13:27:06.476313 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1268 13:27:06.479928 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1269 13:27:06.480004 == TX Byte 1 ==
1270 13:27:06.486443 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1271 13:27:06.489329 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1272 13:27:06.489404 ==
1273 13:27:06.492834 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 13:27:06.496305 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1275 13:27:06.496381 ==
1276 13:27:06.511077 TX Vref=22, minBit 0, minWin=27, winSum=442
1277 13:27:06.513647 TX Vref=24, minBit 0, minWin=28, winSum=453
1278 13:27:06.517103 TX Vref=26, minBit 14, minWin=27, winSum=451
1279 13:27:06.520210 TX Vref=28, minBit 2, minWin=28, winSum=456
1280 13:27:06.523626 TX Vref=30, minBit 2, minWin=28, winSum=459
1281 13:27:06.529962 TX Vref=32, minBit 2, minWin=28, winSum=459
1282 13:27:06.533875 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 30
1283 13:27:06.533950
1284 13:27:06.536519 Final TX Range 1 Vref 30
1285 13:27:06.536594
1286 13:27:06.536651 ==
1287 13:27:06.540144 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 13:27:06.543162 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1289 13:27:06.543238 ==
1290 13:27:06.546564
1291 13:27:06.546638
1292 13:27:06.546697 TX Vref Scan disable
1293 13:27:06.549980 == TX Byte 0 ==
1294 13:27:06.553151 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1295 13:27:06.559886 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1296 13:27:06.559963 == TX Byte 1 ==
1297 13:27:06.563138 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1298 13:27:06.566644 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1299 13:27:06.570925
1300 13:27:06.570999 [DATLAT]
1301 13:27:06.571058 Freq=800, CH0 RK1
1302 13:27:06.571112
1303 13:27:06.573207 DATLAT Default: 0x9
1304 13:27:06.573321 0, 0xFFFF, sum = 0
1305 13:27:06.577105 1, 0xFFFF, sum = 0
1306 13:27:06.577182 2, 0xFFFF, sum = 0
1307 13:27:06.580290 3, 0xFFFF, sum = 0
1308 13:27:06.580366 4, 0xFFFF, sum = 0
1309 13:27:06.583669 5, 0xFFFF, sum = 0
1310 13:27:06.586570 6, 0xFFFF, sum = 0
1311 13:27:06.586647 7, 0xFFFF, sum = 0
1312 13:27:06.586706 8, 0x0, sum = 1
1313 13:27:06.589773 9, 0x0, sum = 2
1314 13:27:06.589848 10, 0x0, sum = 3
1315 13:27:06.593847 11, 0x0, sum = 4
1316 13:27:06.593923 best_step = 9
1317 13:27:06.593981
1318 13:27:06.594034 ==
1319 13:27:06.596804 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 13:27:06.603549 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1321 13:27:06.603624 ==
1322 13:27:06.603682 RX Vref Scan: 0
1323 13:27:06.603736
1324 13:27:06.606712 RX Vref 0 -> 0, step: 1
1325 13:27:06.606787
1326 13:27:06.610173 RX Delay -111 -> 252, step: 8
1327 13:27:06.613193 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1328 13:27:06.616755 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1329 13:27:06.623371 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1330 13:27:06.626541 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1331 13:27:06.629959 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1332 13:27:06.633146 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1333 13:27:06.636826 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1334 13:27:06.639964 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1335 13:27:06.646487 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1336 13:27:06.650219 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1337 13:27:06.653782 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1338 13:27:06.656994 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1339 13:27:06.660350 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1340 13:27:06.666894 iDelay=217, Bit 13, Center 76 (-39 ~ 192) 232
1341 13:27:06.669864 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1342 13:27:06.673540 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1343 13:27:06.673616 ==
1344 13:27:06.676768 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 13:27:06.680297 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1346 13:27:06.683584 ==
1347 13:27:06.683659 DQS Delay:
1348 13:27:06.683718 DQS0 = 0, DQS1 = 0
1349 13:27:06.686706 DQM Delay:
1350 13:27:06.686780 DQM0 = 85, DQM1 = 73
1351 13:27:06.690229 DQ Delay:
1352 13:27:06.690304 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =80
1353 13:27:06.693155 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1354 13:27:06.696940 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1355 13:27:06.699805 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1356 13:27:06.699880
1357 13:27:06.703587
1358 13:27:06.710358 [DQSOSCAuto] RK1, (LSB)MR18= 0x4545, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1359 13:27:06.713299 CH0 RK1: MR19=606, MR18=4545
1360 13:27:06.720446 CH0_RK1: MR19=0x606, MR18=0x4545, DQSOSC=392, MR23=63, INC=96, DEC=64
1361 13:27:06.723264 [RxdqsGatingPostProcess] freq 800
1362 13:27:06.726711 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1363 13:27:06.730348 Pre-setting of DQS Precalculation
1364 13:27:06.733551 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1365 13:27:06.736886 ==
1366 13:27:06.740333 Dram Type= 6, Freq= 0, CH_1, rank 0
1367 13:27:06.743552 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1368 13:27:06.743717 ==
1369 13:27:06.746872 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1370 13:27:06.753498 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1371 13:27:06.763192 [CA 0] Center 36 (6~67) winsize 62
1372 13:27:06.766263 [CA 1] Center 36 (5~67) winsize 63
1373 13:27:06.769663 [CA 2] Center 34 (4~65) winsize 62
1374 13:27:06.773991 [CA 3] Center 34 (3~65) winsize 63
1375 13:27:06.776417 [CA 4] Center 33 (3~64) winsize 62
1376 13:27:06.779968 [CA 5] Center 33 (3~64) winsize 62
1377 13:27:06.780393
1378 13:27:06.783507 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1379 13:27:06.783929
1380 13:27:06.786795 [CATrainingPosCal] consider 1 rank data
1381 13:27:06.790040 u2DelayCellTimex100 = 270/100 ps
1382 13:27:06.793533 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1383 13:27:06.796761 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1384 13:27:06.803287 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1385 13:27:06.806465 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1386 13:27:06.810161 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1387 13:27:06.813617 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1388 13:27:06.814042
1389 13:27:06.816420 CA PerBit enable=1, Macro0, CA PI delay=33
1390 13:27:06.816843
1391 13:27:06.820200 [CBTSetCACLKResult] CA Dly = 33
1392 13:27:06.820707 CS Dly: 4 (0~35)
1393 13:27:06.821039 ==
1394 13:27:06.823753 Dram Type= 6, Freq= 0, CH_1, rank 1
1395 13:27:06.830274 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1396 13:27:06.830702 ==
1397 13:27:06.833661 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1398 13:27:06.840575 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1399 13:27:06.849924 [CA 0] Center 36 (6~67) winsize 62
1400 13:27:06.852570 [CA 1] Center 36 (5~67) winsize 63
1401 13:27:06.855894 [CA 2] Center 34 (4~65) winsize 62
1402 13:27:06.859358 [CA 3] Center 33 (3~64) winsize 62
1403 13:27:06.862912 [CA 4] Center 33 (3~63) winsize 61
1404 13:27:06.865854 [CA 5] Center 33 (3~63) winsize 61
1405 13:27:06.866279
1406 13:27:06.869302 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1407 13:27:06.869802
1408 13:27:06.873300 [CATrainingPosCal] consider 2 rank data
1409 13:27:06.875544 u2DelayCellTimex100 = 270/100 ps
1410 13:27:06.879362 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1411 13:27:06.882636 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1412 13:27:06.889941 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1413 13:27:06.892193 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1414 13:27:06.895674 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
1415 13:27:06.899165 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1416 13:27:06.899591
1417 13:27:06.902262 CA PerBit enable=1, Macro0, CA PI delay=33
1418 13:27:06.902688
1419 13:27:06.905716 [CBTSetCACLKResult] CA Dly = 33
1420 13:27:06.906220 CS Dly: 4 (0~36)
1421 13:27:06.906554
1422 13:27:06.908715 ----->DramcWriteLeveling(PI) begin...
1423 13:27:06.912415 ==
1424 13:27:06.915602 Dram Type= 6, Freq= 0, CH_1, rank 0
1425 13:27:06.918998 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1426 13:27:06.919499 ==
1427 13:27:06.922057 Write leveling (Byte 0): 24 => 24
1428 13:27:06.925852 Write leveling (Byte 1): 25 => 25
1429 13:27:06.929113 DramcWriteLeveling(PI) end<-----
1430 13:27:06.929652
1431 13:27:06.929985 ==
1432 13:27:06.932654 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 13:27:06.935875 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1434 13:27:06.936304 ==
1435 13:27:06.938806 [Gating] SW mode calibration
1436 13:27:06.945921 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1437 13:27:06.948937 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1438 13:27:06.955667 0 6 0 | B1->B0 | 2f2f 2525 | 0 0 | (1 1) (0 0)
1439 13:27:06.959378 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1440 13:27:06.962673 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 13:27:06.969387 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 13:27:06.972435 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 13:27:06.975626 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 13:27:06.982162 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 13:27:06.985938 0 6 28 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
1446 13:27:06.988759 0 7 0 | B1->B0 | 3131 3e3e | 0 0 | (1 1) (0 0)
1447 13:27:06.996554 0 7 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1448 13:27:06.999203 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1449 13:27:07.002670 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1450 13:27:07.009112 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1451 13:27:07.012653 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1452 13:27:07.015857 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1453 13:27:07.022755 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1454 13:27:07.025595 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1455 13:27:07.029296 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1456 13:27:07.035699 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 13:27:07.039146 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 13:27:07.042575 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 13:27:07.045798 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 13:27:07.052821 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 13:27:07.055659 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 13:27:07.058881 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 13:27:07.066013 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 13:27:07.068782 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 13:27:07.072156 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 13:27:07.078884 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 13:27:07.082377 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1468 13:27:07.086269 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1469 13:27:07.092080 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1470 13:27:07.095445 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1471 13:27:07.099810 Total UI for P1: 0, mck2ui 16
1472 13:27:07.102333 best dqsien dly found for B0: ( 0, 9, 30)
1473 13:27:07.105904 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1474 13:27:07.108923 Total UI for P1: 0, mck2ui 16
1475 13:27:07.112102 best dqsien dly found for B1: ( 0, 10, 0)
1476 13:27:07.115792 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1477 13:27:07.119478 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1478 13:27:07.119907
1479 13:27:07.125423 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1480 13:27:07.128766 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1481 13:27:07.129195 [Gating] SW calibration Done
1482 13:27:07.132309 ==
1483 13:27:07.132808 Dram Type= 6, Freq= 0, CH_1, rank 0
1484 13:27:07.139028 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1485 13:27:07.139460 ==
1486 13:27:07.139796 RX Vref Scan: 0
1487 13:27:07.140104
1488 13:27:07.142380 RX Vref 0 -> 0, step: 1
1489 13:27:07.142806
1490 13:27:07.145819 RX Delay -130 -> 252, step: 16
1491 13:27:07.148842 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1492 13:27:07.152447 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1493 13:27:07.155895 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1494 13:27:07.162243 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1495 13:27:07.165415 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1496 13:27:07.168874 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1497 13:27:07.171933 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1498 13:27:07.175236 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1499 13:27:07.181831 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1500 13:27:07.185299 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1501 13:27:07.189112 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1502 13:27:07.192262 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1503 13:27:07.196006 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1504 13:27:07.202013 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1505 13:27:07.205462 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1506 13:27:07.208546 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1507 13:27:07.209074 ==
1508 13:27:07.212277 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 13:27:07.215225 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1510 13:27:07.218483 ==
1511 13:27:07.218910 DQS Delay:
1512 13:27:07.219242 DQS0 = 0, DQS1 = 0
1513 13:27:07.222291 DQM Delay:
1514 13:27:07.222802 DQM0 = 81, DQM1 = 70
1515 13:27:07.226082 DQ Delay:
1516 13:27:07.226614 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1517 13:27:07.228784 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1518 13:27:07.232241 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1519 13:27:07.235820 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1520 13:27:07.236334
1521 13:27:07.238529
1522 13:27:07.239033 ==
1523 13:27:07.241829 Dram Type= 6, Freq= 0, CH_1, rank 0
1524 13:27:07.245313 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1525 13:27:07.245746 ==
1526 13:27:07.246077
1527 13:27:07.246380
1528 13:27:07.248556 TX Vref Scan disable
1529 13:27:07.248985 == TX Byte 0 ==
1530 13:27:07.255080 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1531 13:27:07.258840 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1532 13:27:07.259349 == TX Byte 1 ==
1533 13:27:07.265408 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1534 13:27:07.268096 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1535 13:27:07.268522 ==
1536 13:27:07.271382 Dram Type= 6, Freq= 0, CH_1, rank 0
1537 13:27:07.275142 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1538 13:27:07.275654 ==
1539 13:27:07.289063 TX Vref=22, minBit 9, minWin=27, winSum=445
1540 13:27:07.292305 TX Vref=24, minBit 10, minWin=27, winSum=450
1541 13:27:07.295570 TX Vref=26, minBit 2, minWin=28, winSum=457
1542 13:27:07.298529 TX Vref=28, minBit 3, minWin=28, winSum=457
1543 13:27:07.302105 TX Vref=30, minBit 3, minWin=28, winSum=458
1544 13:27:07.309328 TX Vref=32, minBit 3, minWin=28, winSum=457
1545 13:27:07.311687 [TxChooseVref] Worse bit 3, Min win 28, Win sum 458, Final Vref 30
1546 13:27:07.312117
1547 13:27:07.314970 Final TX Range 1 Vref 30
1548 13:27:07.315515
1549 13:27:07.315850 ==
1550 13:27:07.318436 Dram Type= 6, Freq= 0, CH_1, rank 0
1551 13:27:07.321909 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1552 13:27:07.322341 ==
1553 13:27:07.324916
1554 13:27:07.325379
1555 13:27:07.325713 TX Vref Scan disable
1556 13:27:07.328382 == TX Byte 0 ==
1557 13:27:07.332386 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1558 13:27:07.335427 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1559 13:27:07.338371 == TX Byte 1 ==
1560 13:27:07.341820 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1561 13:27:07.348109 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1562 13:27:07.348535
1563 13:27:07.348862 [DATLAT]
1564 13:27:07.349165 Freq=800, CH1 RK0
1565 13:27:07.349516
1566 13:27:07.351874 DATLAT Default: 0xa
1567 13:27:07.352301 0, 0xFFFF, sum = 0
1568 13:27:07.355049 1, 0xFFFF, sum = 0
1569 13:27:07.355482 2, 0xFFFF, sum = 0
1570 13:27:07.358502 3, 0xFFFF, sum = 0
1571 13:27:07.361913 4, 0xFFFF, sum = 0
1572 13:27:07.362426 5, 0xFFFF, sum = 0
1573 13:27:07.364563 6, 0xFFFF, sum = 0
1574 13:27:07.364994 7, 0xFFFF, sum = 0
1575 13:27:07.368106 8, 0x0, sum = 1
1576 13:27:07.368618 9, 0x0, sum = 2
1577 13:27:07.368961 10, 0x0, sum = 3
1578 13:27:07.371737 11, 0x0, sum = 4
1579 13:27:07.372257 best_step = 9
1580 13:27:07.372589
1581 13:27:07.372891 ==
1582 13:27:07.374827 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 13:27:07.381699 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1584 13:27:07.382209 ==
1585 13:27:07.382544 RX Vref Scan: 1
1586 13:27:07.382850
1587 13:27:07.384776 Set Vref Range= 32 -> 127
1588 13:27:07.385316
1589 13:27:07.388307 RX Vref 32 -> 127, step: 1
1590 13:27:07.388814
1591 13:27:07.391530 RX Delay -111 -> 252, step: 8
1592 13:27:07.392039
1593 13:27:07.395429 Set Vref, RX VrefLevel [Byte0]: 32
1594 13:27:07.398586 [Byte1]: 32
1595 13:27:07.399093
1596 13:27:07.401284 Set Vref, RX VrefLevel [Byte0]: 33
1597 13:27:07.404974 [Byte1]: 33
1598 13:27:07.405570
1599 13:27:07.408543 Set Vref, RX VrefLevel [Byte0]: 34
1600 13:27:07.411229 [Byte1]: 34
1601 13:27:07.415095
1602 13:27:07.415551 Set Vref, RX VrefLevel [Byte0]: 35
1603 13:27:07.417803 [Byte1]: 35
1604 13:27:07.422871
1605 13:27:07.423381 Set Vref, RX VrefLevel [Byte0]: 36
1606 13:27:07.425423 [Byte1]: 36
1607 13:27:07.430427
1608 13:27:07.430931 Set Vref, RX VrefLevel [Byte0]: 37
1609 13:27:07.433538 [Byte1]: 37
1610 13:27:07.437877
1611 13:27:07.438389 Set Vref, RX VrefLevel [Byte0]: 38
1612 13:27:07.441178 [Byte1]: 38
1613 13:27:07.445459
1614 13:27:07.445884 Set Vref, RX VrefLevel [Byte0]: 39
1615 13:27:07.448707 [Byte1]: 39
1616 13:27:07.453245
1617 13:27:07.453672 Set Vref, RX VrefLevel [Byte0]: 40
1618 13:27:07.456111 [Byte1]: 40
1619 13:27:07.460715
1620 13:27:07.461140 Set Vref, RX VrefLevel [Byte0]: 41
1621 13:27:07.464157 [Byte1]: 41
1622 13:27:07.467990
1623 13:27:07.468419 Set Vref, RX VrefLevel [Byte0]: 42
1624 13:27:07.471553 [Byte1]: 42
1625 13:27:07.476233
1626 13:27:07.476739 Set Vref, RX VrefLevel [Byte0]: 43
1627 13:27:07.479644 [Byte1]: 43
1628 13:27:07.483566
1629 13:27:07.484085 Set Vref, RX VrefLevel [Byte0]: 44
1630 13:27:07.487133 [Byte1]: 44
1631 13:27:07.491087
1632 13:27:07.491559 Set Vref, RX VrefLevel [Byte0]: 45
1633 13:27:07.495011 [Byte1]: 45
1634 13:27:07.498912
1635 13:27:07.499338 Set Vref, RX VrefLevel [Byte0]: 46
1636 13:27:07.502368 [Byte1]: 46
1637 13:27:07.506754
1638 13:27:07.507257 Set Vref, RX VrefLevel [Byte0]: 47
1639 13:27:07.510188 [Byte1]: 47
1640 13:27:07.514420
1641 13:27:07.514846 Set Vref, RX VrefLevel [Byte0]: 48
1642 13:27:07.517339 [Byte1]: 48
1643 13:27:07.521884
1644 13:27:07.522391 Set Vref, RX VrefLevel [Byte0]: 49
1645 13:27:07.525357 [Byte1]: 49
1646 13:27:07.529650
1647 13:27:07.530156 Set Vref, RX VrefLevel [Byte0]: 50
1648 13:27:07.533376 [Byte1]: 50
1649 13:27:07.537148
1650 13:27:07.537703 Set Vref, RX VrefLevel [Byte0]: 51
1651 13:27:07.540619 [Byte1]: 51
1652 13:27:07.544818
1653 13:27:07.545274 Set Vref, RX VrefLevel [Byte0]: 52
1654 13:27:07.548238 [Byte1]: 52
1655 13:27:07.552518
1656 13:27:07.552943 Set Vref, RX VrefLevel [Byte0]: 53
1657 13:27:07.556271 [Byte1]: 53
1658 13:27:07.559987
1659 13:27:07.560414 Set Vref, RX VrefLevel [Byte0]: 54
1660 13:27:07.562993 [Byte1]: 54
1661 13:27:07.567549
1662 13:27:07.567969 Set Vref, RX VrefLevel [Byte0]: 55
1663 13:27:07.570944 [Byte1]: 55
1664 13:27:07.575320
1665 13:27:07.575820 Set Vref, RX VrefLevel [Byte0]: 56
1666 13:27:07.578909 [Byte1]: 56
1667 13:27:07.582696
1668 13:27:07.583120 Set Vref, RX VrefLevel [Byte0]: 57
1669 13:27:07.586211 [Byte1]: 57
1670 13:27:07.591056
1671 13:27:07.591554 Set Vref, RX VrefLevel [Byte0]: 58
1672 13:27:07.594004 [Byte1]: 58
1673 13:27:07.597982
1674 13:27:07.598422 Set Vref, RX VrefLevel [Byte0]: 59
1675 13:27:07.601249 [Byte1]: 59
1676 13:27:07.605710
1677 13:27:07.606211 Set Vref, RX VrefLevel [Byte0]: 60
1678 13:27:07.609662 [Byte1]: 60
1679 13:27:07.613502
1680 13:27:07.613926 Set Vref, RX VrefLevel [Byte0]: 61
1681 13:27:07.617053 [Byte1]: 61
1682 13:27:07.621405
1683 13:27:07.621897 Set Vref, RX VrefLevel [Byte0]: 62
1684 13:27:07.624917 [Byte1]: 62
1685 13:27:07.628976
1686 13:27:07.629633 Set Vref, RX VrefLevel [Byte0]: 63
1687 13:27:07.632462 [Byte1]: 63
1688 13:27:07.636362
1689 13:27:07.636861 Set Vref, RX VrefLevel [Byte0]: 64
1690 13:27:07.639773 [Byte1]: 64
1691 13:27:07.646125
1692 13:27:07.646568 Set Vref, RX VrefLevel [Byte0]: 65
1693 13:27:07.647216 [Byte1]: 65
1694 13:27:07.652423
1695 13:27:07.652955 Set Vref, RX VrefLevel [Byte0]: 66
1696 13:27:07.654835 [Byte1]: 66
1697 13:27:07.659085
1698 13:27:07.659508 Set Vref, RX VrefLevel [Byte0]: 67
1699 13:27:07.662654 [Byte1]: 67
1700 13:27:07.667153
1701 13:27:07.667654 Set Vref, RX VrefLevel [Byte0]: 68
1702 13:27:07.670253 [Byte1]: 68
1703 13:27:07.674972
1704 13:27:07.675472 Set Vref, RX VrefLevel [Byte0]: 69
1705 13:27:07.677883 [Byte1]: 69
1706 13:27:07.682446
1707 13:27:07.682971 Set Vref, RX VrefLevel [Byte0]: 70
1708 13:27:07.685880 [Byte1]: 70
1709 13:27:07.690088
1710 13:27:07.690602 Set Vref, RX VrefLevel [Byte0]: 71
1711 13:27:07.693660 [Byte1]: 71
1712 13:27:07.698616
1713 13:27:07.699127 Set Vref, RX VrefLevel [Byte0]: 72
1714 13:27:07.701132 [Byte1]: 72
1715 13:27:07.705368
1716 13:27:07.705872 Set Vref, RX VrefLevel [Byte0]: 73
1717 13:27:07.708852 [Byte1]: 73
1718 13:27:07.713076
1719 13:27:07.713551 Set Vref, RX VrefLevel [Byte0]: 74
1720 13:27:07.716118 [Byte1]: 74
1721 13:27:07.720461
1722 13:27:07.720958 Set Vref, RX VrefLevel [Byte0]: 75
1723 13:27:07.727044 [Byte1]: 75
1724 13:27:07.727538
1725 13:27:07.729859 Final RX Vref Byte 0 = 62 to rank0
1726 13:27:07.733801 Final RX Vref Byte 1 = 52 to rank0
1727 13:27:07.737511 Final RX Vref Byte 0 = 62 to rank1
1728 13:27:07.740700 Final RX Vref Byte 1 = 52 to rank1==
1729 13:27:07.744863 Dram Type= 6, Freq= 0, CH_1, rank 0
1730 13:27:07.746755 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1731 13:27:07.747184 ==
1732 13:27:07.747514 DQS Delay:
1733 13:27:07.750106 DQS0 = 0, DQS1 = 0
1734 13:27:07.750542 DQM Delay:
1735 13:27:07.753573 DQM0 = 79, DQM1 = 72
1736 13:27:07.754070 DQ Delay:
1737 13:27:07.756813 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1738 13:27:07.760044 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
1739 13:27:07.763369 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1740 13:27:07.766523 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1741 13:27:07.766946
1742 13:27:07.767269
1743 13:27:07.773672 [DQSOSCAuto] RK0, (LSB)MR18= 0x5858, (MSB)MR19= 0x606, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
1744 13:27:07.777277 CH1 RK0: MR19=606, MR18=5858
1745 13:27:07.784138 CH1_RK0: MR19=0x606, MR18=0x5858, DQSOSC=387, MR23=63, INC=98, DEC=65
1746 13:27:07.784625
1747 13:27:07.787022 ----->DramcWriteLeveling(PI) begin...
1748 13:27:07.787530 ==
1749 13:27:07.790244 Dram Type= 6, Freq= 0, CH_1, rank 1
1750 13:27:07.794102 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1751 13:27:07.794608 ==
1752 13:27:07.796917 Write leveling (Byte 0): 25 => 25
1753 13:27:07.800777 Write leveling (Byte 1): 25 => 25
1754 13:27:07.803434 DramcWriteLeveling(PI) end<-----
1755 13:27:07.803859
1756 13:27:07.804183 ==
1757 13:27:07.806868 Dram Type= 6, Freq= 0, CH_1, rank 1
1758 13:27:07.813789 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1759 13:27:07.814286 ==
1760 13:27:07.814618 [Gating] SW mode calibration
1761 13:27:07.823761 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1762 13:27:07.826836 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1763 13:27:07.830446 0 6 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
1764 13:27:07.836699 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1765 13:27:07.840252 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1766 13:27:07.843846 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1767 13:27:07.850148 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1768 13:27:07.853636 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1769 13:27:07.856937 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1770 13:27:07.863626 0 6 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1771 13:27:07.867454 0 7 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1772 13:27:07.870278 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1773 13:27:07.876873 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1774 13:27:07.880547 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1775 13:27:07.883963 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1776 13:27:07.890297 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1777 13:27:07.893437 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1778 13:27:07.897402 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1779 13:27:07.903506 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1780 13:27:07.906908 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1781 13:27:07.910160 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1782 13:27:07.913351 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1783 13:27:07.920595 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1784 13:27:07.923327 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1785 13:27:07.926877 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1786 13:27:07.933846 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1787 13:27:07.936932 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1788 13:27:07.940268 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1789 13:27:07.946715 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1790 13:27:07.949741 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1791 13:27:07.953341 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1792 13:27:07.960149 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1793 13:27:07.963872 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1794 13:27:07.966664 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1795 13:27:07.973603 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1796 13:27:07.974114 Total UI for P1: 0, mck2ui 16
1797 13:27:07.980328 best dqsien dly found for B0: ( 0, 9, 28)
1798 13:27:07.983702 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1799 13:27:07.986879 Total UI for P1: 0, mck2ui 16
1800 13:27:07.990681 best dqsien dly found for B1: ( 0, 10, 0)
1801 13:27:07.993323 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1802 13:27:07.996940 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1803 13:27:07.997420
1804 13:27:08.000467 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1805 13:27:08.003553 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1806 13:27:08.006764 [Gating] SW calibration Done
1807 13:27:08.007274 ==
1808 13:27:08.009666 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 13:27:08.013272 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1810 13:27:08.013796 ==
1811 13:27:08.017125 RX Vref Scan: 0
1812 13:27:08.017622
1813 13:27:08.020501 RX Vref 0 -> 0, step: 1
1814 13:27:08.020926
1815 13:27:08.023119 RX Delay -130 -> 252, step: 16
1816 13:27:08.026768 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1817 13:27:08.030079 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1818 13:27:08.033410 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1819 13:27:08.036587 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1820 13:27:08.040325 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1821 13:27:08.046892 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1822 13:27:08.050177 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1823 13:27:08.053461 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1824 13:27:08.056817 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1825 13:27:08.059823 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1826 13:27:08.066554 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1827 13:27:08.070740 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1828 13:27:08.073428 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1829 13:27:08.076508 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1830 13:27:08.083255 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1831 13:27:08.086630 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1832 13:27:08.087134 ==
1833 13:27:08.090339 Dram Type= 6, Freq= 0, CH_1, rank 1
1834 13:27:08.093448 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1835 13:27:08.093879 ==
1836 13:27:08.096581 DQS Delay:
1837 13:27:08.097007 DQS0 = 0, DQS1 = 0
1838 13:27:08.097374 DQM Delay:
1839 13:27:08.099728 DQM0 = 84, DQM1 = 73
1840 13:27:08.100231 DQ Delay:
1841 13:27:08.103107 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1842 13:27:08.106194 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1843 13:27:08.109686 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61
1844 13:27:08.112920 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1845 13:27:08.113384
1846 13:27:08.113716
1847 13:27:08.114019 ==
1848 13:27:08.116274 Dram Type= 6, Freq= 0, CH_1, rank 1
1849 13:27:08.120079 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1850 13:27:08.122973 ==
1851 13:27:08.123564
1852 13:27:08.123905
1853 13:27:08.124210 TX Vref Scan disable
1854 13:27:08.126732 == TX Byte 0 ==
1855 13:27:08.130246 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1856 13:27:08.132772 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1857 13:27:08.136357 == TX Byte 1 ==
1858 13:27:08.139734 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1859 13:27:08.143041 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1860 13:27:08.146716 ==
1861 13:27:08.149579 Dram Type= 6, Freq= 0, CH_1, rank 1
1862 13:27:08.153131 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1863 13:27:08.153713 ==
1864 13:27:08.165689 TX Vref=22, minBit 0, minWin=28, winSum=450
1865 13:27:08.168625 TX Vref=24, minBit 0, minWin=28, winSum=454
1866 13:27:08.172312 TX Vref=26, minBit 1, minWin=28, winSum=460
1867 13:27:08.175095 TX Vref=28, minBit 8, minWin=28, winSum=460
1868 13:27:08.178364 TX Vref=30, minBit 8, minWin=28, winSum=461
1869 13:27:08.181378 TX Vref=32, minBit 0, minWin=28, winSum=454
1870 13:27:08.188734 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 30
1871 13:27:08.189284
1872 13:27:08.191618 Final TX Range 1 Vref 30
1873 13:27:08.192090
1874 13:27:08.192435 ==
1875 13:27:08.195405 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 13:27:08.198523 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1877 13:27:08.198965 ==
1878 13:27:08.199295
1879 13:27:08.201773
1880 13:27:08.202196 TX Vref Scan disable
1881 13:27:08.204785 == TX Byte 0 ==
1882 13:27:08.208275 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1883 13:27:08.212159 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1884 13:27:08.214834 == TX Byte 1 ==
1885 13:27:08.218126 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1886 13:27:08.221834 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1887 13:27:08.224422
1888 13:27:08.224847 [DATLAT]
1889 13:27:08.225176 Freq=800, CH1 RK1
1890 13:27:08.225550
1891 13:27:08.228478 DATLAT Default: 0x9
1892 13:27:08.228987 0, 0xFFFF, sum = 0
1893 13:27:08.231934 1, 0xFFFF, sum = 0
1894 13:27:08.232366 2, 0xFFFF, sum = 0
1895 13:27:08.234569 3, 0xFFFF, sum = 0
1896 13:27:08.238067 4, 0xFFFF, sum = 0
1897 13:27:08.238523 5, 0xFFFF, sum = 0
1898 13:27:08.241065 6, 0xFFFF, sum = 0
1899 13:27:08.241522 7, 0xFFFF, sum = 0
1900 13:27:08.241885 8, 0x0, sum = 1
1901 13:27:08.244513 9, 0x0, sum = 2
1902 13:27:08.244943 10, 0x0, sum = 3
1903 13:27:08.249061 11, 0x0, sum = 4
1904 13:27:08.249589 best_step = 9
1905 13:27:08.249920
1906 13:27:08.250222 ==
1907 13:27:08.251501 Dram Type= 6, Freq= 0, CH_1, rank 1
1908 13:27:08.257777 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1909 13:27:08.258296 ==
1910 13:27:08.258632 RX Vref Scan: 0
1911 13:27:08.259021
1912 13:27:08.261217 RX Vref 0 -> 0, step: 1
1913 13:27:08.261688
1914 13:27:08.265117 RX Delay -111 -> 252, step: 8
1915 13:27:08.268375 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1916 13:27:08.271380 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1917 13:27:08.278056 iDelay=209, Bit 2, Center 72 (-47 ~ 192) 240
1918 13:27:08.281343 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1919 13:27:08.284869 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1920 13:27:08.288188 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
1921 13:27:08.291190 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1922 13:27:08.297978 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1923 13:27:08.301404 iDelay=209, Bit 8, Center 56 (-63 ~ 176) 240
1924 13:27:08.304597 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1925 13:27:08.308144 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1926 13:27:08.311659 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1927 13:27:08.317823 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1928 13:27:08.321330 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1929 13:27:08.324761 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1930 13:27:08.328202 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1931 13:27:08.328670 ==
1932 13:27:08.331500 Dram Type= 6, Freq= 0, CH_1, rank 1
1933 13:27:08.337917 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1934 13:27:08.338306 ==
1935 13:27:08.338606 DQS Delay:
1936 13:27:08.338882 DQS0 = 0, DQS1 = 0
1937 13:27:08.341204 DQM Delay:
1938 13:27:08.341611 DQM0 = 82, DQM1 = 72
1939 13:27:08.344720 DQ Delay:
1940 13:27:08.348171 DQ0 =84, DQ1 =80, DQ2 =72, DQ3 =80
1941 13:27:08.348558 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =80
1942 13:27:08.351331 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1943 13:27:08.355197 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =76
1944 13:27:08.357796
1945 13:27:08.358176
1946 13:27:08.364637 [DQSOSCAuto] RK1, (LSB)MR18= 0x4242, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1947 13:27:08.368553 CH1 RK1: MR19=606, MR18=4242
1948 13:27:08.374807 CH1_RK1: MR19=0x606, MR18=0x4242, DQSOSC=393, MR23=63, INC=95, DEC=63
1949 13:27:08.378344 [RxdqsGatingPostProcess] freq 800
1950 13:27:08.381403 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1951 13:27:08.385097 Pre-setting of DQS Precalculation
1952 13:27:08.388570 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1953 13:27:08.398172 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1954 13:27:08.404948 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1955 13:27:08.405409
1956 13:27:08.405742
1957 13:27:08.407977 [Calibration Summary] 1600 Mbps
1958 13:27:08.408399 CH 0, Rank 0
1959 13:27:08.411387 SW Impedance : PASS
1960 13:27:08.412029 DUTY Scan : NO K
1961 13:27:08.415292 ZQ Calibration : PASS
1962 13:27:08.418055 Jitter Meter : NO K
1963 13:27:08.418482 CBT Training : PASS
1964 13:27:08.420954 Write leveling : PASS
1965 13:27:08.424755 RX DQS gating : PASS
1966 13:27:08.425287 RX DQ/DQS(RDDQC) : PASS
1967 13:27:08.428447 TX DQ/DQS : PASS
1968 13:27:08.431127 RX DATLAT : PASS
1969 13:27:08.431556 RX DQ/DQS(Engine): PASS
1970 13:27:08.434753 TX OE : NO K
1971 13:27:08.435258 All Pass.
1972 13:27:08.435609
1973 13:27:08.437762 CH 0, Rank 1
1974 13:27:08.438183 SW Impedance : PASS
1975 13:27:08.441625 DUTY Scan : NO K
1976 13:27:08.444755 ZQ Calibration : PASS
1977 13:27:08.445292 Jitter Meter : NO K
1978 13:27:08.448047 CBT Training : PASS
1979 13:27:08.448469 Write leveling : PASS
1980 13:27:08.451011 RX DQS gating : PASS
1981 13:27:08.454645 RX DQ/DQS(RDDQC) : PASS
1982 13:27:08.455066 TX DQ/DQS : PASS
1983 13:27:08.457953 RX DATLAT : PASS
1984 13:27:08.461683 RX DQ/DQS(Engine): PASS
1985 13:27:08.462186 TX OE : NO K
1986 13:27:08.464746 All Pass.
1987 13:27:08.465164
1988 13:27:08.465516 CH 1, Rank 0
1989 13:27:08.467950 SW Impedance : PASS
1990 13:27:08.468466 DUTY Scan : NO K
1991 13:27:08.471354 ZQ Calibration : PASS
1992 13:27:08.474753 Jitter Meter : NO K
1993 13:27:08.475256 CBT Training : PASS
1994 13:27:08.477733 Write leveling : PASS
1995 13:27:08.481590 RX DQS gating : PASS
1996 13:27:08.482095 RX DQ/DQS(RDDQC) : PASS
1997 13:27:08.484900 TX DQ/DQS : PASS
1998 13:27:08.488038 RX DATLAT : PASS
1999 13:27:08.488539 RX DQ/DQS(Engine): PASS
2000 13:27:08.491549 TX OE : NO K
2001 13:27:08.492083 All Pass.
2002 13:27:08.492422
2003 13:27:08.494855 CH 1, Rank 1
2004 13:27:08.495358 SW Impedance : PASS
2005 13:27:08.498121 DUTY Scan : NO K
2006 13:27:08.498630 ZQ Calibration : PASS
2007 13:27:08.501659 Jitter Meter : NO K
2008 13:27:08.504472 CBT Training : PASS
2009 13:27:08.504903 Write leveling : PASS
2010 13:27:08.508007 RX DQS gating : PASS
2011 13:27:08.511222 RX DQ/DQS(RDDQC) : PASS
2012 13:27:08.511734 TX DQ/DQS : PASS
2013 13:27:08.514482 RX DATLAT : PASS
2014 13:27:08.517817 RX DQ/DQS(Engine): PASS
2015 13:27:08.518245 TX OE : NO K
2016 13:27:08.521160 All Pass.
2017 13:27:08.521636
2018 13:27:08.521973 DramC Write-DBI off
2019 13:27:08.524649 PER_BANK_REFRESH: Hybrid Mode
2020 13:27:08.525154 TX_TRACKING: ON
2021 13:27:08.528137 [GetDramInforAfterCalByMRR] Vendor 6.
2022 13:27:08.534807 [GetDramInforAfterCalByMRR] Revision 606.
2023 13:27:08.537824 [GetDramInforAfterCalByMRR] Revision 2 0.
2024 13:27:08.538253 MR0 0x3939
2025 13:27:08.538584 MR8 0x1111
2026 13:27:08.540846 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2027 13:27:08.541318
2028 13:27:08.544774 MR0 0x3939
2029 13:27:08.545335 MR8 0x1111
2030 13:27:08.548069 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2031 13:27:08.548498
2032 13:27:08.557569 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2033 13:27:08.560898 [FAST_K] Save calibration result to emmc
2034 13:27:08.564221 [FAST_K] Save calibration result to emmc
2035 13:27:08.567800 dram_init: config_dvfs: 1
2036 13:27:08.570992 dramc_set_vcore_voltage set vcore to 662500
2037 13:27:08.574305 Read voltage for 1200, 2
2038 13:27:08.574733 Vio18 = 0
2039 13:27:08.575064 Vcore = 662500
2040 13:27:08.577786 Vdram = 0
2041 13:27:08.578298 Vddq = 0
2042 13:27:08.578629 Vmddr = 0
2043 13:27:08.584314 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2044 13:27:08.588025 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2045 13:27:08.591199 MEM_TYPE=3, freq_sel=15
2046 13:27:08.594776 sv_algorithm_assistance_LP4_1600
2047 13:27:08.597653 ============ PULL DRAM RESETB DOWN ============
2048 13:27:08.601407 ========== PULL DRAM RESETB DOWN end =========
2049 13:27:08.607692 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2050 13:27:08.611195 ===================================
2051 13:27:08.611695 LPDDR4 DRAM CONFIGURATION
2052 13:27:08.614768 ===================================
2053 13:27:08.617684 EX_ROW_EN[0] = 0x0
2054 13:27:08.621286 EX_ROW_EN[1] = 0x0
2055 13:27:08.621797 LP4Y_EN = 0x0
2056 13:27:08.624339 WORK_FSP = 0x0
2057 13:27:08.624842 WL = 0x4
2058 13:27:08.627725 RL = 0x4
2059 13:27:08.628225 BL = 0x2
2060 13:27:08.630898 RPST = 0x0
2061 13:27:08.631324 RD_PRE = 0x0
2062 13:27:08.634418 WR_PRE = 0x1
2063 13:27:08.634917 WR_PST = 0x0
2064 13:27:08.637482 DBI_WR = 0x0
2065 13:27:08.637981 DBI_RD = 0x0
2066 13:27:08.641037 OTF = 0x1
2067 13:27:08.644014 ===================================
2068 13:27:08.647399 ===================================
2069 13:27:08.647899 ANA top config
2070 13:27:08.651313 ===================================
2071 13:27:08.653849 DLL_ASYNC_EN = 0
2072 13:27:08.657199 ALL_SLAVE_EN = 0
2073 13:27:08.660709 NEW_RANK_MODE = 1
2074 13:27:08.661138 DLL_IDLE_MODE = 1
2075 13:27:08.664361 LP45_APHY_COMB_EN = 1
2076 13:27:08.667620 TX_ODT_DIS = 1
2077 13:27:08.671024 NEW_8X_MODE = 1
2078 13:27:08.673986 ===================================
2079 13:27:08.677303 ===================================
2080 13:27:08.680768 data_rate = 2400
2081 13:27:08.681196 CKR = 1
2082 13:27:08.683695 DQ_P2S_RATIO = 8
2083 13:27:08.687240 ===================================
2084 13:27:08.690688 CA_P2S_RATIO = 8
2085 13:27:08.694229 DQ_CA_OPEN = 0
2086 13:27:08.697214 DQ_SEMI_OPEN = 0
2087 13:27:08.697672 CA_SEMI_OPEN = 0
2088 13:27:08.700536 CA_FULL_RATE = 0
2089 13:27:08.703573 DQ_CKDIV4_EN = 0
2090 13:27:08.707408 CA_CKDIV4_EN = 0
2091 13:27:08.710585 CA_PREDIV_EN = 0
2092 13:27:08.713977 PH8_DLY = 17
2093 13:27:08.714147 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2094 13:27:08.717364 DQ_AAMCK_DIV = 4
2095 13:27:08.720241 CA_AAMCK_DIV = 4
2096 13:27:08.724202 CA_ADMCK_DIV = 4
2097 13:27:08.727262 DQ_TRACK_CA_EN = 0
2098 13:27:08.730317 CA_PICK = 1200
2099 13:27:08.733752 CA_MCKIO = 1200
2100 13:27:08.733860 MCKIO_SEMI = 0
2101 13:27:08.736726 PLL_FREQ = 2366
2102 13:27:08.740290 DQ_UI_PI_RATIO = 32
2103 13:27:08.743704 CA_UI_PI_RATIO = 0
2104 13:27:08.747075 ===================================
2105 13:27:08.750325 ===================================
2106 13:27:08.753536 memory_type:LPDDR4
2107 13:27:08.753645 GP_NUM : 10
2108 13:27:08.756870 SRAM_EN : 1
2109 13:27:08.760364 MD32_EN : 0
2110 13:27:08.763806 ===================================
2111 13:27:08.763915 [ANA_INIT] >>>>>>>>>>>>>>
2112 13:27:08.767016 <<<<<< [CONFIGURE PHASE]: ANA_TX
2113 13:27:08.770595 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2114 13:27:08.773940 ===================================
2115 13:27:08.777029 data_rate = 2400,PCW = 0X5b00
2116 13:27:08.780647 ===================================
2117 13:27:08.783443 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2118 13:27:08.789908 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2119 13:27:08.793537 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2120 13:27:08.799981 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2121 13:27:08.803469 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2122 13:27:08.807324 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2123 13:27:08.807572 [ANA_INIT] flow start
2124 13:27:08.810085 [ANA_INIT] PLL >>>>>>>>
2125 13:27:08.813884 [ANA_INIT] PLL <<<<<<<<
2126 13:27:08.814205 [ANA_INIT] MIDPI >>>>>>>>
2127 13:27:08.817494 [ANA_INIT] MIDPI <<<<<<<<
2128 13:27:08.820808 [ANA_INIT] DLL >>>>>>>>
2129 13:27:08.821168 [ANA_INIT] DLL <<<<<<<<
2130 13:27:08.824211 [ANA_INIT] flow end
2131 13:27:08.827285 ============ LP4 DIFF to SE enter ============
2132 13:27:08.833825 ============ LP4 DIFF to SE exit ============
2133 13:27:08.834342 [ANA_INIT] <<<<<<<<<<<<<
2134 13:27:08.837775 [Flow] Enable top DCM control >>>>>
2135 13:27:08.840633 [Flow] Enable top DCM control <<<<<
2136 13:27:08.844163 Enable DLL master slave shuffle
2137 13:27:08.850854 ==============================================================
2138 13:27:08.851366 Gating Mode config
2139 13:27:08.858007 ==============================================================
2140 13:27:08.860449 Config description:
2141 13:27:08.867080 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2142 13:27:08.874065 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2143 13:27:08.880326 SELPH_MODE 0: By rank 1: By Phase
2144 13:27:08.884051 ==============================================================
2145 13:27:08.887822 GAT_TRACK_EN = 1
2146 13:27:08.890431 RX_GATING_MODE = 2
2147 13:27:08.894062 RX_GATING_TRACK_MODE = 2
2148 13:27:08.897384 SELPH_MODE = 1
2149 13:27:08.900691 PICG_EARLY_EN = 1
2150 13:27:08.903952 VALID_LAT_VALUE = 1
2151 13:27:08.911319 ==============================================================
2152 13:27:08.914219 Enter into Gating configuration >>>>
2153 13:27:08.917351 Exit from Gating configuration <<<<
2154 13:27:08.920596 Enter into DVFS_PRE_config >>>>>
2155 13:27:08.930724 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2156 13:27:08.933742 Exit from DVFS_PRE_config <<<<<
2157 13:27:08.937161 Enter into PICG configuration >>>>
2158 13:27:08.940603 Exit from PICG configuration <<<<
2159 13:27:08.941146 [RX_INPUT] configuration >>>>>
2160 13:27:08.943650 [RX_INPUT] configuration <<<<<
2161 13:27:08.950698 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2162 13:27:08.957286 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2163 13:27:08.960467 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2164 13:27:08.966926 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2165 13:27:08.973687 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2166 13:27:08.980262 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2167 13:27:08.983605 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2168 13:27:08.986971 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2169 13:27:08.993854 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2170 13:27:08.996932 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2171 13:27:09.000230 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2172 13:27:09.003975 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2173 13:27:09.008217 ===================================
2174 13:27:09.010834 LPDDR4 DRAM CONFIGURATION
2175 13:27:09.013831 ===================================
2176 13:27:09.017351 EX_ROW_EN[0] = 0x0
2177 13:27:09.017854 EX_ROW_EN[1] = 0x0
2178 13:27:09.020292 LP4Y_EN = 0x0
2179 13:27:09.020726 WORK_FSP = 0x0
2180 13:27:09.023435 WL = 0x4
2181 13:27:09.023863 RL = 0x4
2182 13:27:09.027325 BL = 0x2
2183 13:27:09.027824 RPST = 0x0
2184 13:27:09.030580 RD_PRE = 0x0
2185 13:27:09.031012 WR_PRE = 0x1
2186 13:27:09.033416 WR_PST = 0x0
2187 13:27:09.033851 DBI_WR = 0x0
2188 13:27:09.037384 DBI_RD = 0x0
2189 13:27:09.040411 OTF = 0x1
2190 13:27:09.043868 ===================================
2191 13:27:09.046976 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2192 13:27:09.050050 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2193 13:27:09.053732 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2194 13:27:09.056965 ===================================
2195 13:27:09.060220 LPDDR4 DRAM CONFIGURATION
2196 13:27:09.063874 ===================================
2197 13:27:09.066856 EX_ROW_EN[0] = 0x10
2198 13:27:09.067308 EX_ROW_EN[1] = 0x0
2199 13:27:09.070224 LP4Y_EN = 0x0
2200 13:27:09.070657 WORK_FSP = 0x0
2201 13:27:09.074108 WL = 0x4
2202 13:27:09.074613 RL = 0x4
2203 13:27:09.076583 BL = 0x2
2204 13:27:09.077010 RPST = 0x0
2205 13:27:09.079761 RD_PRE = 0x0
2206 13:27:09.080188 WR_PRE = 0x1
2207 13:27:09.083988 WR_PST = 0x0
2208 13:27:09.084419 DBI_WR = 0x0
2209 13:27:09.086831 DBI_RD = 0x0
2210 13:27:09.087257 OTF = 0x1
2211 13:27:09.090237 ===================================
2212 13:27:09.096859 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2213 13:27:09.097441 ==
2214 13:27:09.100155 Dram Type= 6, Freq= 0, CH_0, rank 0
2215 13:27:09.106957 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2216 13:27:09.107492 ==
2217 13:27:09.107835 [Duty_Offset_Calibration]
2218 13:27:09.110073 B0:0 B1:2 CA:1
2219 13:27:09.110501
2220 13:27:09.113543 [DutyScan_Calibration_Flow] k_type=0
2221 13:27:09.122500
2222 13:27:09.123021 ==CLK 0==
2223 13:27:09.125565 Final CLK duty delay cell = 0
2224 13:27:09.129427 [0] MAX Duty = 5093%(X100), DQS PI = 12
2225 13:27:09.132513 [0] MIN Duty = 4938%(X100), DQS PI = 54
2226 13:27:09.133052 [0] AVG Duty = 5015%(X100)
2227 13:27:09.135911
2228 13:27:09.139598 CH0 CLK Duty spec in!! Max-Min= 155%
2229 13:27:09.142383 [DutyScan_Calibration_Flow] ====Done====
2230 13:27:09.142828
2231 13:27:09.145392 [DutyScan_Calibration_Flow] k_type=1
2232 13:27:09.161479
2233 13:27:09.161992 ==DQS 0 ==
2234 13:27:09.165081 Final DQS duty delay cell = 0
2235 13:27:09.168155 [0] MAX Duty = 5125%(X100), DQS PI = 32
2236 13:27:09.171526 [0] MIN Duty = 5031%(X100), DQS PI = 6
2237 13:27:09.172030 [0] AVG Duty = 5078%(X100)
2238 13:27:09.174845
2239 13:27:09.175339 ==DQS 1 ==
2240 13:27:09.177928 Final DQS duty delay cell = 0
2241 13:27:09.181851 [0] MAX Duty = 5062%(X100), DQS PI = 58
2242 13:27:09.184533 [0] MIN Duty = 4906%(X100), DQS PI = 14
2243 13:27:09.184967 [0] AVG Duty = 4984%(X100)
2244 13:27:09.187986
2245 13:27:09.191856 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2246 13:27:09.192413
2247 13:27:09.194846 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2248 13:27:09.198840 [DutyScan_Calibration_Flow] ====Done====
2249 13:27:09.199340
2250 13:27:09.201370 [DutyScan_Calibration_Flow] k_type=3
2251 13:27:09.218697
2252 13:27:09.219201 ==DQM 0 ==
2253 13:27:09.222526 Final DQM duty delay cell = 0
2254 13:27:09.225668 [0] MAX Duty = 5156%(X100), DQS PI = 22
2255 13:27:09.228853 [0] MIN Duty = 4969%(X100), DQS PI = 40
2256 13:27:09.232041 [0] AVG Duty = 5062%(X100)
2257 13:27:09.232540
2258 13:27:09.232873 ==DQM 1 ==
2259 13:27:09.236215 Final DQM duty delay cell = 4
2260 13:27:09.238700 [4] MAX Duty = 5187%(X100), DQS PI = 54
2261 13:27:09.241969 [4] MIN Duty = 5000%(X100), DQS PI = 18
2262 13:27:09.245434 [4] AVG Duty = 5093%(X100)
2263 13:27:09.245934
2264 13:27:09.248507 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2265 13:27:09.249005
2266 13:27:09.252108 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2267 13:27:09.255760 [DutyScan_Calibration_Flow] ====Done====
2268 13:27:09.256187
2269 13:27:09.258280 [DutyScan_Calibration_Flow] k_type=2
2270 13:27:09.273635
2271 13:27:09.274137 ==DQ 0 ==
2272 13:27:09.277040 Final DQ duty delay cell = -4
2273 13:27:09.280091 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2274 13:27:09.283962 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2275 13:27:09.286704 [-4] AVG Duty = 4937%(X100)
2276 13:27:09.287132
2277 13:27:09.287469 ==DQ 1 ==
2278 13:27:09.290262 Final DQ duty delay cell = -4
2279 13:27:09.293894 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2280 13:27:09.297261 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2281 13:27:09.300567 [-4] AVG Duty = 4969%(X100)
2282 13:27:09.301013
2283 13:27:09.303651 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2284 13:27:09.304085
2285 13:27:09.307158 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2286 13:27:09.310045 [DutyScan_Calibration_Flow] ====Done====
2287 13:27:09.310482 ==
2288 13:27:09.313302 Dram Type= 6, Freq= 0, CH_1, rank 0
2289 13:27:09.317055 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2290 13:27:09.317658 ==
2291 13:27:09.319976 [Duty_Offset_Calibration]
2292 13:27:09.320536 B0:0 B1:4 CA:-5
2293 13:27:09.321020
2294 13:27:09.323510 [DutyScan_Calibration_Flow] k_type=0
2295 13:27:09.333963
2296 13:27:09.334450 ==CLK 0==
2297 13:27:09.337255 Final CLK duty delay cell = 0
2298 13:27:09.341138 [0] MAX Duty = 5094%(X100), DQS PI = 24
2299 13:27:09.344136 [0] MIN Duty = 4844%(X100), DQS PI = 46
2300 13:27:09.344761 [0] AVG Duty = 4969%(X100)
2301 13:27:09.347494
2302 13:27:09.350324 CH1 CLK Duty spec in!! Max-Min= 250%
2303 13:27:09.354115 [DutyScan_Calibration_Flow] ====Done====
2304 13:27:09.354549
2305 13:27:09.357420 [DutyScan_Calibration_Flow] k_type=1
2306 13:27:09.373398
2307 13:27:09.373901 ==DQS 0 ==
2308 13:27:09.376985 Final DQS duty delay cell = 0
2309 13:27:09.380377 [0] MAX Duty = 5125%(X100), DQS PI = 16
2310 13:27:09.383364 [0] MIN Duty = 4875%(X100), DQS PI = 40
2311 13:27:09.383797 [0] AVG Duty = 5000%(X100)
2312 13:27:09.386657
2313 13:27:09.387084 ==DQS 1 ==
2314 13:27:09.389815 Final DQS duty delay cell = 0
2315 13:27:09.393339 [0] MAX Duty = 5125%(X100), DQS PI = 18
2316 13:27:09.396667 [0] MIN Duty = 5031%(X100), DQS PI = 44
2317 13:27:09.397170 [0] AVG Duty = 5078%(X100)
2318 13:27:09.400903
2319 13:27:09.403192 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2320 13:27:09.403582
2321 13:27:09.406369 CH1 DQS 1 Duty spec in!! Max-Min= 94%
2322 13:27:09.410092 [DutyScan_Calibration_Flow] ====Done====
2323 13:27:09.410479
2324 13:27:09.413158 [DutyScan_Calibration_Flow] k_type=3
2325 13:27:09.428520
2326 13:27:09.428996 ==DQM 0 ==
2327 13:27:09.431705 Final DQM duty delay cell = -4
2328 13:27:09.434680 [-4] MAX Duty = 5093%(X100), DQS PI = 32
2329 13:27:09.438667 [-4] MIN Duty = 4875%(X100), DQS PI = 38
2330 13:27:09.441652 [-4] AVG Duty = 4984%(X100)
2331 13:27:09.442087
2332 13:27:09.442418 ==DQM 1 ==
2333 13:27:09.445042 Final DQM duty delay cell = -4
2334 13:27:09.447816 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2335 13:27:09.451335 [-4] MIN Duty = 4875%(X100), DQS PI = 60
2336 13:27:09.454666 [-4] AVG Duty = 4968%(X100)
2337 13:27:09.455081
2338 13:27:09.458083 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2339 13:27:09.458475
2340 13:27:09.461573 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2341 13:27:09.464459 [DutyScan_Calibration_Flow] ====Done====
2342 13:27:09.464846
2343 13:27:09.468165 [DutyScan_Calibration_Flow] k_type=2
2344 13:27:09.485166
2345 13:27:09.485708 ==DQ 0 ==
2346 13:27:09.489210 Final DQ duty delay cell = 0
2347 13:27:09.492210 [0] MAX Duty = 5062%(X100), DQS PI = 0
2348 13:27:09.495489 [0] MIN Duty = 4969%(X100), DQS PI = 44
2349 13:27:09.495997 [0] AVG Duty = 5015%(X100)
2350 13:27:09.496332
2351 13:27:09.498935 ==DQ 1 ==
2352 13:27:09.501931 Final DQ duty delay cell = 0
2353 13:27:09.505452 [0] MAX Duty = 5031%(X100), DQS PI = 8
2354 13:27:09.508561 [0] MIN Duty = 4875%(X100), DQS PI = 32
2355 13:27:09.509064 [0] AVG Duty = 4953%(X100)
2356 13:27:09.509472
2357 13:27:09.512139 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2358 13:27:09.512648
2359 13:27:09.515486 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2360 13:27:09.522057 [DutyScan_Calibration_Flow] ====Done====
2361 13:27:09.525587 nWR fixed to 30
2362 13:27:09.526100 [ModeRegInit_LP4] CH0 RK0
2363 13:27:09.528663 [ModeRegInit_LP4] CH0 RK1
2364 13:27:09.531508 [ModeRegInit_LP4] CH1 RK0
2365 13:27:09.531943 [ModeRegInit_LP4] CH1 RK1
2366 13:27:09.535036 match AC timing 6
2367 13:27:09.538362 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2368 13:27:09.542225 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2369 13:27:09.548436 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2370 13:27:09.551986 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2371 13:27:09.558406 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2372 13:27:09.558917 ==
2373 13:27:09.561908 Dram Type= 6, Freq= 0, CH_0, rank 0
2374 13:27:09.564811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2375 13:27:09.565295 ==
2376 13:27:09.571612 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2377 13:27:09.575061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2378 13:27:09.585218 [CA 0] Center 39 (9~70) winsize 62
2379 13:27:09.588150 [CA 1] Center 39 (9~70) winsize 62
2380 13:27:09.591447 [CA 2] Center 36 (5~67) winsize 63
2381 13:27:09.594662 [CA 3] Center 35 (5~66) winsize 62
2382 13:27:09.598241 [CA 4] Center 34 (3~65) winsize 63
2383 13:27:09.601432 [CA 5] Center 33 (3~64) winsize 62
2384 13:27:09.601862
2385 13:27:09.605195 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2386 13:27:09.605727
2387 13:27:09.608179 [CATrainingPosCal] consider 1 rank data
2388 13:27:09.611440 u2DelayCellTimex100 = 270/100 ps
2389 13:27:09.615059 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2390 13:27:09.618565 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2391 13:27:09.624654 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2392 13:27:09.628262 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2393 13:27:09.631450 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2394 13:27:09.634931 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2395 13:27:09.635445
2396 13:27:09.637844 CA PerBit enable=1, Macro0, CA PI delay=33
2397 13:27:09.638343
2398 13:27:09.640977 [CBTSetCACLKResult] CA Dly = 33
2399 13:27:09.641628 CS Dly: 7 (0~38)
2400 13:27:09.644373 ==
2401 13:27:09.648408 Dram Type= 6, Freq= 0, CH_0, rank 1
2402 13:27:09.650998 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2403 13:27:09.651497 ==
2404 13:27:09.654508 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2405 13:27:09.660863 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2406 13:27:09.670405 [CA 0] Center 39 (8~70) winsize 63
2407 13:27:09.674142 [CA 1] Center 39 (8~70) winsize 63
2408 13:27:09.677400 [CA 2] Center 36 (5~67) winsize 63
2409 13:27:09.680595 [CA 3] Center 35 (4~66) winsize 63
2410 13:27:09.683815 [CA 4] Center 33 (3~64) winsize 62
2411 13:27:09.687084 [CA 5] Center 34 (3~65) winsize 63
2412 13:27:09.687513
2413 13:27:09.690118 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2414 13:27:09.690617
2415 13:27:09.693964 [CATrainingPosCal] consider 2 rank data
2416 13:27:09.697198 u2DelayCellTimex100 = 270/100 ps
2417 13:27:09.700409 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2418 13:27:09.703849 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2419 13:27:09.710721 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2420 13:27:09.713824 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2421 13:27:09.717375 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2422 13:27:09.720921 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2423 13:27:09.721485
2424 13:27:09.724211 CA PerBit enable=1, Macro0, CA PI delay=33
2425 13:27:09.724689
2426 13:27:09.727028 [CBTSetCACLKResult] CA Dly = 33
2427 13:27:09.727486 CS Dly: 7 (0~39)
2428 13:27:09.727824
2429 13:27:09.730374 ----->DramcWriteLeveling(PI) begin...
2430 13:27:09.733993 ==
2431 13:27:09.737085 Dram Type= 6, Freq= 0, CH_0, rank 0
2432 13:27:09.740342 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2433 13:27:09.740775 ==
2434 13:27:09.743942 Write leveling (Byte 0): 28 => 28
2435 13:27:09.746712 Write leveling (Byte 1): 27 => 27
2436 13:27:09.750135 DramcWriteLeveling(PI) end<-----
2437 13:27:09.750647
2438 13:27:09.750983 ==
2439 13:27:09.753614 Dram Type= 6, Freq= 0, CH_0, rank 0
2440 13:27:09.756679 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2441 13:27:09.757113 ==
2442 13:27:09.760051 [Gating] SW mode calibration
2443 13:27:09.767177 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2444 13:27:09.773570 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2445 13:27:09.776963 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2446 13:27:09.780457 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2447 13:27:09.784063 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2448 13:27:09.790479 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2449 13:27:09.794244 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2450 13:27:09.797187 0 11 20 | B1->B0 | 2d2d 2b2b | 1 0 | (1 0) (1 0)
2451 13:27:09.803744 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2452 13:27:09.806643 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2453 13:27:09.810244 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2454 13:27:09.817116 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2455 13:27:09.820257 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2456 13:27:09.824032 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2457 13:27:09.830319 0 12 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2458 13:27:09.833873 0 12 20 | B1->B0 | 3c3c 4545 | 0 0 | (0 0) (0 0)
2459 13:27:09.836911 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2460 13:27:09.844228 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2461 13:27:09.846898 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2462 13:27:09.850353 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2463 13:27:09.856949 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2464 13:27:09.860504 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2465 13:27:09.864163 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2466 13:27:09.867854 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2467 13:27:09.874179 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2468 13:27:09.877176 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2469 13:27:09.880532 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2470 13:27:09.888643 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2471 13:27:09.890466 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2472 13:27:09.894309 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2473 13:27:09.900619 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2474 13:27:09.904068 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2475 13:27:09.907407 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2476 13:27:09.914191 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2477 13:27:09.917321 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2478 13:27:09.920741 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2479 13:27:09.927294 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2480 13:27:09.930683 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2481 13:27:09.934083 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2482 13:27:09.937617 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2483 13:27:09.944533 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2484 13:27:09.947083 Total UI for P1: 0, mck2ui 16
2485 13:27:09.950648 best dqsien dly found for B0: ( 0, 15, 20)
2486 13:27:09.954322 Total UI for P1: 0, mck2ui 16
2487 13:27:09.957479 best dqsien dly found for B1: ( 0, 15, 20)
2488 13:27:09.960881 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2489 13:27:09.963946 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2490 13:27:09.964385
2491 13:27:09.967549 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2492 13:27:09.970835 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2493 13:27:09.974186 [Gating] SW calibration Done
2494 13:27:09.974703 ==
2495 13:27:09.977122 Dram Type= 6, Freq= 0, CH_0, rank 0
2496 13:27:09.980784 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2497 13:27:09.981375 ==
2498 13:27:09.983795 RX Vref Scan: 0
2499 13:27:09.984307
2500 13:27:09.987080 RX Vref 0 -> 0, step: 1
2501 13:27:09.987606
2502 13:27:09.988037 RX Delay -40 -> 252, step: 8
2503 13:27:09.994109 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2504 13:27:09.997672 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2505 13:27:10.000629 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2506 13:27:10.004307 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2507 13:27:10.007195 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2508 13:27:10.014077 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2509 13:27:10.017390 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2510 13:27:10.020830 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2511 13:27:10.024207 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2512 13:27:10.026888 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2513 13:27:10.031084 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2514 13:27:10.037109 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2515 13:27:10.040992 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2516 13:27:10.044224 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2517 13:27:10.047199 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2518 13:27:10.050992 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2519 13:27:10.053794 ==
2520 13:27:10.057567 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 13:27:10.060662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2522 13:27:10.061095 ==
2523 13:27:10.061467 DQS Delay:
2524 13:27:10.064135 DQS0 = 0, DQS1 = 0
2525 13:27:10.064561 DQM Delay:
2526 13:27:10.067285 DQM0 = 115, DQM1 = 106
2527 13:27:10.067786 DQ Delay:
2528 13:27:10.070652 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2529 13:27:10.074143 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2530 13:27:10.077593 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2531 13:27:10.080470 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2532 13:27:10.080973
2533 13:27:10.081347
2534 13:27:10.081655 ==
2535 13:27:10.084176 Dram Type= 6, Freq= 0, CH_0, rank 0
2536 13:27:10.090455 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2537 13:27:10.090970 ==
2538 13:27:10.091360
2539 13:27:10.091671
2540 13:27:10.091964 TX Vref Scan disable
2541 13:27:10.094024 == TX Byte 0 ==
2542 13:27:10.097285 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2543 13:27:10.101342 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2544 13:27:10.104032 == TX Byte 1 ==
2545 13:27:10.107799 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2546 13:27:10.110627 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2547 13:27:10.114696 ==
2548 13:27:10.117470 Dram Type= 6, Freq= 0, CH_0, rank 0
2549 13:27:10.120658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2550 13:27:10.121161 ==
2551 13:27:10.131518 TX Vref=22, minBit 10, minWin=25, winSum=422
2552 13:27:10.135419 TX Vref=24, minBit 10, minWin=25, winSum=423
2553 13:27:10.138559 TX Vref=26, minBit 8, minWin=26, winSum=434
2554 13:27:10.141835 TX Vref=28, minBit 11, minWin=26, winSum=437
2555 13:27:10.145536 TX Vref=30, minBit 10, minWin=26, winSum=438
2556 13:27:10.152145 TX Vref=32, minBit 8, minWin=26, winSum=437
2557 13:27:10.155279 [TxChooseVref] Worse bit 10, Min win 26, Win sum 438, Final Vref 30
2558 13:27:10.155794
2559 13:27:10.158502 Final TX Range 1 Vref 30
2560 13:27:10.158943
2561 13:27:10.159373 ==
2562 13:27:10.162215 Dram Type= 6, Freq= 0, CH_0, rank 0
2563 13:27:10.165457 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2564 13:27:10.168578 ==
2565 13:27:10.169095
2566 13:27:10.169579
2567 13:27:10.170000 TX Vref Scan disable
2568 13:27:10.172347 == TX Byte 0 ==
2569 13:27:10.176020 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2570 13:27:10.182147 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2571 13:27:10.182672 == TX Byte 1 ==
2572 13:27:10.185327 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2573 13:27:10.192438 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2574 13:27:10.192953
2575 13:27:10.193451 [DATLAT]
2576 13:27:10.193861 Freq=1200, CH0 RK0
2577 13:27:10.194260
2578 13:27:10.195449 DATLAT Default: 0xd
2579 13:27:10.195886 0, 0xFFFF, sum = 0
2580 13:27:10.198563 1, 0xFFFF, sum = 0
2581 13:27:10.199079 2, 0xFFFF, sum = 0
2582 13:27:10.202110 3, 0xFFFF, sum = 0
2583 13:27:10.205017 4, 0xFFFF, sum = 0
2584 13:27:10.205613 5, 0xFFFF, sum = 0
2585 13:27:10.208889 6, 0xFFFF, sum = 0
2586 13:27:10.209458 7, 0xFFFF, sum = 0
2587 13:27:10.211918 8, 0xFFFF, sum = 0
2588 13:27:10.212364 9, 0xFFFF, sum = 0
2589 13:27:10.215584 10, 0xFFFF, sum = 0
2590 13:27:10.216108 11, 0x0, sum = 1
2591 13:27:10.218894 12, 0x0, sum = 2
2592 13:27:10.219341 13, 0x0, sum = 3
2593 13:27:10.222476 14, 0x0, sum = 4
2594 13:27:10.222910 best_step = 12
2595 13:27:10.223239
2596 13:27:10.223544 ==
2597 13:27:10.225622 Dram Type= 6, Freq= 0, CH_0, rank 0
2598 13:27:10.228536 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2599 13:27:10.228969 ==
2600 13:27:10.232505 RX Vref Scan: 1
2601 13:27:10.233123
2602 13:27:10.235355 Set Vref Range= 32 -> 127
2603 13:27:10.235862
2604 13:27:10.236197 RX Vref 32 -> 127, step: 1
2605 13:27:10.236508
2606 13:27:10.238451 RX Delay -21 -> 252, step: 4
2607 13:27:10.238880
2608 13:27:10.241842 Set Vref, RX VrefLevel [Byte0]: 32
2609 13:27:10.245920 [Byte1]: 32
2610 13:27:10.248528
2611 13:27:10.249026 Set Vref, RX VrefLevel [Byte0]: 33
2612 13:27:10.251855 [Byte1]: 33
2613 13:27:10.256606
2614 13:27:10.257118 Set Vref, RX VrefLevel [Byte0]: 34
2615 13:27:10.260021 [Byte1]: 34
2616 13:27:10.264383
2617 13:27:10.264811 Set Vref, RX VrefLevel [Byte0]: 35
2618 13:27:10.268373 [Byte1]: 35
2619 13:27:10.272456
2620 13:27:10.273092 Set Vref, RX VrefLevel [Byte0]: 36
2621 13:27:10.275645 [Byte1]: 36
2622 13:27:10.280303
2623 13:27:10.280804 Set Vref, RX VrefLevel [Byte0]: 37
2624 13:27:10.283744 [Byte1]: 37
2625 13:27:10.288717
2626 13:27:10.289220 Set Vref, RX VrefLevel [Byte0]: 38
2627 13:27:10.291614 [Byte1]: 38
2628 13:27:10.296300
2629 13:27:10.296799 Set Vref, RX VrefLevel [Byte0]: 39
2630 13:27:10.299955 [Byte1]: 39
2631 13:27:10.304750
2632 13:27:10.305310 Set Vref, RX VrefLevel [Byte0]: 40
2633 13:27:10.307558 [Byte1]: 40
2634 13:27:10.311799
2635 13:27:10.312231 Set Vref, RX VrefLevel [Byte0]: 41
2636 13:27:10.315909 [Byte1]: 41
2637 13:27:10.319975
2638 13:27:10.320567 Set Vref, RX VrefLevel [Byte0]: 42
2639 13:27:10.323489 [Byte1]: 42
2640 13:27:10.328153
2641 13:27:10.328582 Set Vref, RX VrefLevel [Byte0]: 43
2642 13:27:10.331325 [Byte1]: 43
2643 13:27:10.335954
2644 13:27:10.336383 Set Vref, RX VrefLevel [Byte0]: 44
2645 13:27:10.339438 [Byte1]: 44
2646 13:27:10.343676
2647 13:27:10.344192 Set Vref, RX VrefLevel [Byte0]: 45
2648 13:27:10.347807 [Byte1]: 45
2649 13:27:10.351437
2650 13:27:10.351869 Set Vref, RX VrefLevel [Byte0]: 46
2651 13:27:10.354982 [Byte1]: 46
2652 13:27:10.360324
2653 13:27:10.360842 Set Vref, RX VrefLevel [Byte0]: 47
2654 13:27:10.362944 [Byte1]: 47
2655 13:27:10.367584
2656 13:27:10.368094 Set Vref, RX VrefLevel [Byte0]: 48
2657 13:27:10.370513 [Byte1]: 48
2658 13:27:10.375659
2659 13:27:10.376163 Set Vref, RX VrefLevel [Byte0]: 49
2660 13:27:10.379426 [Byte1]: 49
2661 13:27:10.383111
2662 13:27:10.383538 Set Vref, RX VrefLevel [Byte0]: 50
2663 13:27:10.386960 [Byte1]: 50
2664 13:27:10.391269
2665 13:27:10.391775 Set Vref, RX VrefLevel [Byte0]: 51
2666 13:27:10.394918 [Byte1]: 51
2667 13:27:10.399304
2668 13:27:10.399812 Set Vref, RX VrefLevel [Byte0]: 52
2669 13:27:10.402586 [Byte1]: 52
2670 13:27:10.407488
2671 13:27:10.407994 Set Vref, RX VrefLevel [Byte0]: 53
2672 13:27:10.410378 [Byte1]: 53
2673 13:27:10.415100
2674 13:27:10.415601 Set Vref, RX VrefLevel [Byte0]: 54
2675 13:27:10.418123 [Byte1]: 54
2676 13:27:10.423131
2677 13:27:10.423554 Set Vref, RX VrefLevel [Byte0]: 55
2678 13:27:10.426248 [Byte1]: 55
2679 13:27:10.431432
2680 13:27:10.431934 Set Vref, RX VrefLevel [Byte0]: 56
2681 13:27:10.434138 [Byte1]: 56
2682 13:27:10.439297
2683 13:27:10.439805 Set Vref, RX VrefLevel [Byte0]: 57
2684 13:27:10.442025 [Byte1]: 57
2685 13:27:10.446692
2686 13:27:10.447193 Set Vref, RX VrefLevel [Byte0]: 58
2687 13:27:10.449934 [Byte1]: 58
2688 13:27:10.454684
2689 13:27:10.455188 Set Vref, RX VrefLevel [Byte0]: 59
2690 13:27:10.457845 [Byte1]: 59
2691 13:27:10.462464
2692 13:27:10.462963 Set Vref, RX VrefLevel [Byte0]: 60
2693 13:27:10.466266 [Byte1]: 60
2694 13:27:10.470866
2695 13:27:10.471369 Set Vref, RX VrefLevel [Byte0]: 61
2696 13:27:10.473713 [Byte1]: 61
2697 13:27:10.478378
2698 13:27:10.478849 Set Vref, RX VrefLevel [Byte0]: 62
2699 13:27:10.481623 [Byte1]: 62
2700 13:27:10.486267
2701 13:27:10.486790 Set Vref, RX VrefLevel [Byte0]: 63
2702 13:27:10.489909 [Byte1]: 63
2703 13:27:10.494091
2704 13:27:10.494520 Set Vref, RX VrefLevel [Byte0]: 64
2705 13:27:10.497644 [Byte1]: 64
2706 13:27:10.502323
2707 13:27:10.502750 Set Vref, RX VrefLevel [Byte0]: 65
2708 13:27:10.505584 [Byte1]: 65
2709 13:27:10.510226
2710 13:27:10.510653 Set Vref, RX VrefLevel [Byte0]: 66
2711 13:27:10.513920 [Byte1]: 66
2712 13:27:10.517942
2713 13:27:10.518458 Final RX Vref Byte 0 = 47 to rank0
2714 13:27:10.521058 Final RX Vref Byte 1 = 47 to rank0
2715 13:27:10.524659 Final RX Vref Byte 0 = 47 to rank1
2716 13:27:10.527604 Final RX Vref Byte 1 = 47 to rank1==
2717 13:27:10.530957 Dram Type= 6, Freq= 0, CH_0, rank 0
2718 13:27:10.537958 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2719 13:27:10.538539 ==
2720 13:27:10.538892 DQS Delay:
2721 13:27:10.539201 DQS0 = 0, DQS1 = 0
2722 13:27:10.540932 DQM Delay:
2723 13:27:10.541419 DQM0 = 113, DQM1 = 105
2724 13:27:10.544700 DQ Delay:
2725 13:27:10.547746 DQ0 =110, DQ1 =114, DQ2 =110, DQ3 =108
2726 13:27:10.551121 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120
2727 13:27:10.554709 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2728 13:27:10.558109 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2729 13:27:10.558539
2730 13:27:10.558868
2731 13:27:10.564652 [DQSOSCAuto] RK0, (LSB)MR18= 0xd0d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2732 13:27:10.568042 CH0 RK0: MR19=404, MR18=D0D
2733 13:27:10.574706 CH0_RK0: MR19=0x404, MR18=0xD0D, DQSOSC=405, MR23=63, INC=39, DEC=26
2734 13:27:10.575140
2735 13:27:10.578019 ----->DramcWriteLeveling(PI) begin...
2736 13:27:10.578456 ==
2737 13:27:10.581276 Dram Type= 6, Freq= 0, CH_0, rank 1
2738 13:27:10.584568 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2739 13:27:10.585000 ==
2740 13:27:10.588024 Write leveling (Byte 0): 25 => 25
2741 13:27:10.591381 Write leveling (Byte 1): 25 => 25
2742 13:27:10.594623 DramcWriteLeveling(PI) end<-----
2743 13:27:10.595010
2744 13:27:10.595308 ==
2745 13:27:10.597696 Dram Type= 6, Freq= 0, CH_0, rank 1
2746 13:27:10.601126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2747 13:27:10.604687 ==
2748 13:27:10.605154 [Gating] SW mode calibration
2749 13:27:10.614682 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2750 13:27:10.618217 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2751 13:27:10.621616 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2752 13:27:10.627667 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2753 13:27:10.631236 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2754 13:27:10.634922 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2755 13:27:10.641394 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2756 13:27:10.644439 0 11 20 | B1->B0 | 2e2e 2626 | 0 0 | (0 1) (1 0)
2757 13:27:10.647933 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2758 13:27:10.654672 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2759 13:27:10.658476 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2760 13:27:10.661169 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2761 13:27:10.668161 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2762 13:27:10.671129 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2763 13:27:10.674243 0 12 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2764 13:27:10.681085 0 12 20 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
2765 13:27:10.684604 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2766 13:27:10.687938 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2767 13:27:10.691249 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2768 13:27:10.697878 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2769 13:27:10.701076 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2770 13:27:10.704326 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2771 13:27:10.711107 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2772 13:27:10.714586 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2773 13:27:10.718158 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2774 13:27:10.724513 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2775 13:27:10.727814 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2776 13:27:10.731654 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2777 13:27:10.737428 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2778 13:27:10.740866 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2779 13:27:10.744621 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2780 13:27:10.751516 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2781 13:27:10.754296 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2782 13:27:10.757949 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2783 13:27:10.764568 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2784 13:27:10.768085 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2785 13:27:10.770921 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2786 13:27:10.778152 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2787 13:27:10.781264 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2788 13:27:10.784558 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2789 13:27:10.787921 Total UI for P1: 0, mck2ui 16
2790 13:27:10.791233 best dqsien dly found for B0: ( 0, 15, 16)
2791 13:27:10.794118 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2792 13:27:10.797491 Total UI for P1: 0, mck2ui 16
2793 13:27:10.801257 best dqsien dly found for B1: ( 0, 15, 18)
2794 13:27:10.804580 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2795 13:27:10.811327 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2796 13:27:10.811837
2797 13:27:10.814384 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2798 13:27:10.817777 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2799 13:27:10.821269 [Gating] SW calibration Done
2800 13:27:10.821779 ==
2801 13:27:10.824217 Dram Type= 6, Freq= 0, CH_0, rank 1
2802 13:27:10.828065 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2803 13:27:10.828590 ==
2804 13:27:10.831280 RX Vref Scan: 0
2805 13:27:10.831795
2806 13:27:10.832130 RX Vref 0 -> 0, step: 1
2807 13:27:10.832439
2808 13:27:10.834312 RX Delay -40 -> 252, step: 8
2809 13:27:10.837265 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2810 13:27:10.844081 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2811 13:27:10.847667 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2812 13:27:10.851397 iDelay=200, Bit 3, Center 107 (40 ~ 175) 136
2813 13:27:10.853964 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2814 13:27:10.857885 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2815 13:27:10.864106 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2816 13:27:10.866817 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2817 13:27:10.870274 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2818 13:27:10.873444 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2819 13:27:10.877566 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2820 13:27:10.884112 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2821 13:27:10.887406 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2822 13:27:10.890352 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2823 13:27:10.894134 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2824 13:27:10.896807 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2825 13:27:10.900896 ==
2826 13:27:10.901462 Dram Type= 6, Freq= 0, CH_0, rank 1
2827 13:27:10.907146 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2828 13:27:10.907657 ==
2829 13:27:10.907997 DQS Delay:
2830 13:27:10.910456 DQS0 = 0, DQS1 = 0
2831 13:27:10.910884 DQM Delay:
2832 13:27:10.913635 DQM0 = 114, DQM1 = 106
2833 13:27:10.914061 DQ Delay:
2834 13:27:10.917271 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =107
2835 13:27:10.920246 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2836 13:27:10.923467 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
2837 13:27:10.927461 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2838 13:27:10.927964
2839 13:27:10.928294
2840 13:27:10.928594 ==
2841 13:27:10.929906 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 13:27:10.936514 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2843 13:27:10.937033 ==
2844 13:27:10.937538
2845 13:27:10.937856
2846 13:27:10.938158 TX Vref Scan disable
2847 13:27:10.940088 == TX Byte 0 ==
2848 13:27:10.943513 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2849 13:27:10.947115 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2850 13:27:10.950281 == TX Byte 1 ==
2851 13:27:10.953379 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2852 13:27:10.956948 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2853 13:27:10.959758 ==
2854 13:27:10.964003 Dram Type= 6, Freq= 0, CH_0, rank 1
2855 13:27:10.966537 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2856 13:27:10.967052 ==
2857 13:27:10.977795 TX Vref=22, minBit 1, minWin=25, winSum=415
2858 13:27:10.980907 TX Vref=24, minBit 1, minWin=25, winSum=416
2859 13:27:10.984394 TX Vref=26, minBit 5, minWin=25, winSum=419
2860 13:27:10.987473 TX Vref=28, minBit 1, minWin=26, winSum=427
2861 13:27:10.990832 TX Vref=30, minBit 1, minWin=26, winSum=430
2862 13:27:10.994050 TX Vref=32, minBit 1, minWin=26, winSum=430
2863 13:27:11.001204 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
2864 13:27:11.001666
2865 13:27:11.004331 Final TX Range 1 Vref 30
2866 13:27:11.004861
2867 13:27:11.005203 ==
2868 13:27:11.007632 Dram Type= 6, Freq= 0, CH_0, rank 1
2869 13:27:11.011419 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2870 13:27:11.011851 ==
2871 13:27:11.012182
2872 13:27:11.014452
2873 13:27:11.014878 TX Vref Scan disable
2874 13:27:11.018229 == TX Byte 0 ==
2875 13:27:11.020729 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2876 13:27:11.024180 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2877 13:27:11.027951 == TX Byte 1 ==
2878 13:27:11.030876 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2879 13:27:11.034235 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2880 13:27:11.034665
2881 13:27:11.038161 [DATLAT]
2882 13:27:11.038587 Freq=1200, CH0 RK1
2883 13:27:11.038923
2884 13:27:11.040966 DATLAT Default: 0xc
2885 13:27:11.041526 0, 0xFFFF, sum = 0
2886 13:27:11.044980 1, 0xFFFF, sum = 0
2887 13:27:11.045536 2, 0xFFFF, sum = 0
2888 13:27:11.048171 3, 0xFFFF, sum = 0
2889 13:27:11.048684 4, 0xFFFF, sum = 0
2890 13:27:11.050742 5, 0xFFFF, sum = 0
2891 13:27:11.051258 6, 0xFFFF, sum = 0
2892 13:27:11.054348 7, 0xFFFF, sum = 0
2893 13:27:11.057890 8, 0xFFFF, sum = 0
2894 13:27:11.058404 9, 0xFFFF, sum = 0
2895 13:27:11.060619 10, 0xFFFF, sum = 0
2896 13:27:11.061052 11, 0x0, sum = 1
2897 13:27:11.061430 12, 0x0, sum = 2
2898 13:27:11.064722 13, 0x0, sum = 3
2899 13:27:11.065298 14, 0x0, sum = 4
2900 13:27:11.067619 best_step = 12
2901 13:27:11.068129
2902 13:27:11.068460 ==
2903 13:27:11.071021 Dram Type= 6, Freq= 0, CH_0, rank 1
2904 13:27:11.074868 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2905 13:27:11.075398 ==
2906 13:27:11.077771 RX Vref Scan: 0
2907 13:27:11.078200
2908 13:27:11.078534 RX Vref 0 -> 0, step: 1
2909 13:27:11.078839
2910 13:27:11.080818 RX Delay -21 -> 252, step: 4
2911 13:27:11.088057 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2912 13:27:11.091561 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2913 13:27:11.094747 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2914 13:27:11.097562 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2915 13:27:11.101373 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2916 13:27:11.108069 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2917 13:27:11.111269 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2918 13:27:11.114275 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2919 13:27:11.117953 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2920 13:27:11.121472 iDelay=195, Bit 9, Center 88 (27 ~ 150) 124
2921 13:27:11.128261 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2922 13:27:11.131450 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2923 13:27:11.134404 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2924 13:27:11.138140 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2925 13:27:11.140944 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2926 13:27:11.148123 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2927 13:27:11.148632 ==
2928 13:27:11.151584 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 13:27:11.154336 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2930 13:27:11.154768 ==
2931 13:27:11.155102 DQS Delay:
2932 13:27:11.157761 DQS0 = 0, DQS1 = 0
2933 13:27:11.158271 DQM Delay:
2934 13:27:11.161596 DQM0 = 114, DQM1 = 105
2935 13:27:11.162112 DQ Delay:
2936 13:27:11.164883 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2937 13:27:11.167482 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =122
2938 13:27:11.171184 DQ8 =94, DQ9 =88, DQ10 =110, DQ11 =96
2939 13:27:11.174488 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2940 13:27:11.174998
2941 13:27:11.175334
2942 13:27:11.184273 [DQSOSCAuto] RK1, (LSB)MR18= 0xf0f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2943 13:27:11.188231 CH0 RK1: MR19=404, MR18=F0F
2944 13:27:11.191315 CH0_RK1: MR19=0x404, MR18=0xF0F, DQSOSC=404, MR23=63, INC=40, DEC=26
2945 13:27:11.194625 [RxdqsGatingPostProcess] freq 1200
2946 13:27:11.201260 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2947 13:27:11.204247 Pre-setting of DQS Precalculation
2948 13:27:11.207670 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2949 13:27:11.208100 ==
2950 13:27:11.211431 Dram Type= 6, Freq= 0, CH_1, rank 0
2951 13:27:11.218195 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2952 13:27:11.218704 ==
2953 13:27:11.221333 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2954 13:27:11.227619 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2955 13:27:11.236613 [CA 0] Center 37 (7~68) winsize 62
2956 13:27:11.239695 [CA 1] Center 37 (7~68) winsize 62
2957 13:27:11.243062 [CA 2] Center 34 (4~65) winsize 62
2958 13:27:11.245928 [CA 3] Center 33 (3~64) winsize 62
2959 13:27:11.249527 [CA 4] Center 32 (2~63) winsize 62
2960 13:27:11.253161 [CA 5] Center 32 (1~63) winsize 63
2961 13:27:11.253723
2962 13:27:11.255935 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2963 13:27:11.256362
2964 13:27:11.259552 [CATrainingPosCal] consider 1 rank data
2965 13:27:11.262877 u2DelayCellTimex100 = 270/100 ps
2966 13:27:11.266380 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2967 13:27:11.269704 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2968 13:27:11.276456 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2969 13:27:11.279668 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2970 13:27:11.282773 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2971 13:27:11.286338 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2972 13:27:11.286846
2973 13:27:11.289945 CA PerBit enable=1, Macro0, CA PI delay=32
2974 13:27:11.290455
2975 13:27:11.293287 [CBTSetCACLKResult] CA Dly = 32
2976 13:27:11.293797 CS Dly: 6 (0~37)
2977 13:27:11.294138 ==
2978 13:27:11.296216 Dram Type= 6, Freq= 0, CH_1, rank 1
2979 13:27:11.303303 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2980 13:27:11.303811 ==
2981 13:27:11.306569 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2982 13:27:11.313183 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2983 13:27:11.321568 [CA 0] Center 37 (6~68) winsize 63
2984 13:27:11.324783 [CA 1] Center 37 (7~68) winsize 62
2985 13:27:11.328640 [CA 2] Center 33 (3~64) winsize 62
2986 13:27:11.331891 [CA 3] Center 33 (3~64) winsize 62
2987 13:27:11.334660 [CA 4] Center 32 (2~63) winsize 62
2988 13:27:11.337672 [CA 5] Center 32 (1~63) winsize 63
2989 13:27:11.338098
2990 13:27:11.341394 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2991 13:27:11.341905
2992 13:27:11.344652 [CATrainingPosCal] consider 2 rank data
2993 13:27:11.348061 u2DelayCellTimex100 = 270/100 ps
2994 13:27:11.351388 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2995 13:27:11.355031 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2996 13:27:11.361411 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2997 13:27:11.364799 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2998 13:27:11.368187 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2999 13:27:11.371555 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
3000 13:27:11.371986
3001 13:27:11.374749 CA PerBit enable=1, Macro0, CA PI delay=32
3002 13:27:11.375174
3003 13:27:11.378378 [CBTSetCACLKResult] CA Dly = 32
3004 13:27:11.378901 CS Dly: 6 (0~38)
3005 13:27:11.379240
3006 13:27:11.381125 ----->DramcWriteLeveling(PI) begin...
3007 13:27:11.384900 ==
3008 13:27:11.385436 Dram Type= 6, Freq= 0, CH_1, rank 0
3009 13:27:11.391951 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3010 13:27:11.392467 ==
3011 13:27:11.395005 Write leveling (Byte 0): 20 => 20
3012 13:27:11.398317 Write leveling (Byte 1): 22 => 22
3013 13:27:11.398749 DramcWriteLeveling(PI) end<-----
3014 13:27:11.401456
3015 13:27:11.401963 ==
3016 13:27:11.404906 Dram Type= 6, Freq= 0, CH_1, rank 0
3017 13:27:11.408344 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3018 13:27:11.408776 ==
3019 13:27:11.411884 [Gating] SW mode calibration
3020 13:27:11.418087 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3021 13:27:11.421540 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3022 13:27:11.428285 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3023 13:27:11.431744 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3024 13:27:11.435126 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3025 13:27:11.441938 0 11 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3026 13:27:11.445091 0 11 16 | B1->B0 | 3333 2929 | 0 0 | (0 1) (0 0)
3027 13:27:11.448636 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3028 13:27:11.454764 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3029 13:27:11.458115 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3030 13:27:11.461334 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3031 13:27:11.468459 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3032 13:27:11.471735 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3033 13:27:11.475113 0 12 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
3034 13:27:11.481388 0 12 16 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
3035 13:27:11.484838 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3036 13:27:11.487853 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3037 13:27:11.495204 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3038 13:27:11.498001 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3039 13:27:11.500846 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3040 13:27:11.508338 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3041 13:27:11.511266 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3042 13:27:11.514262 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3043 13:27:11.517834 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3044 13:27:11.524139 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3045 13:27:11.527801 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3046 13:27:11.531116 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3047 13:27:11.537507 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3048 13:27:11.541354 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3049 13:27:11.544301 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3050 13:27:11.551165 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3051 13:27:11.554636 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3052 13:27:11.557991 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3053 13:27:11.564549 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3054 13:27:11.567628 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3055 13:27:11.571600 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3056 13:27:11.578062 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3057 13:27:11.581141 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3058 13:27:11.584335 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3059 13:27:11.590958 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3060 13:27:11.591465 Total UI for P1: 0, mck2ui 16
3061 13:27:11.597625 best dqsien dly found for B0: ( 0, 15, 16)
3062 13:27:11.601351 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3063 13:27:11.604182 Total UI for P1: 0, mck2ui 16
3064 13:27:11.607838 best dqsien dly found for B1: ( 0, 15, 20)
3065 13:27:11.612111 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3066 13:27:11.614395 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
3067 13:27:11.614826
3068 13:27:11.617805 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3069 13:27:11.621420 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
3070 13:27:11.624442 [Gating] SW calibration Done
3071 13:27:11.624868 ==
3072 13:27:11.627678 Dram Type= 6, Freq= 0, CH_1, rank 0
3073 13:27:11.631022 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3074 13:27:11.634261 ==
3075 13:27:11.634687 RX Vref Scan: 0
3076 13:27:11.635015
3077 13:27:11.637594 RX Vref 0 -> 0, step: 1
3078 13:27:11.638017
3079 13:27:11.638344 RX Delay -40 -> 252, step: 8
3080 13:27:11.644405 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3081 13:27:11.647510 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3082 13:27:11.651253 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3083 13:27:11.654446 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3084 13:27:11.658062 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3085 13:27:11.664004 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3086 13:27:11.668310 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3087 13:27:11.670930 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3088 13:27:11.674044 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3089 13:27:11.677654 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3090 13:27:11.684985 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3091 13:27:11.688177 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3092 13:27:11.691328 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3093 13:27:11.694507 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3094 13:27:11.697873 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3095 13:27:11.704385 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3096 13:27:11.704896 ==
3097 13:27:11.708173 Dram Type= 6, Freq= 0, CH_1, rank 0
3098 13:27:11.711386 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3099 13:27:11.711886 ==
3100 13:27:11.712229 DQS Delay:
3101 13:27:11.714750 DQS0 = 0, DQS1 = 0
3102 13:27:11.715179 DQM Delay:
3103 13:27:11.717921 DQM0 = 116, DQM1 = 108
3104 13:27:11.718352 DQ Delay:
3105 13:27:11.720783 DQ0 =123, DQ1 =107, DQ2 =107, DQ3 =115
3106 13:27:11.724295 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3107 13:27:11.728182 DQ8 =87, DQ9 =95, DQ10 =107, DQ11 =103
3108 13:27:11.731227 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3109 13:27:11.731737
3110 13:27:11.732221
3111 13:27:11.734196 ==
3112 13:27:11.737559 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 13:27:11.740953 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3114 13:27:11.741485 ==
3115 13:27:11.741984
3116 13:27:11.742314
3117 13:27:11.744390 TX Vref Scan disable
3118 13:27:11.744819 == TX Byte 0 ==
3119 13:27:11.748337 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3120 13:27:11.754461 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3121 13:27:11.754893 == TX Byte 1 ==
3122 13:27:11.757590 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3123 13:27:11.765117 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3124 13:27:11.765689 ==
3125 13:27:11.767993 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 13:27:11.770739 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3127 13:27:11.771176 ==
3128 13:27:11.782624 TX Vref=22, minBit 7, minWin=24, winSum=416
3129 13:27:11.786195 TX Vref=24, minBit 3, minWin=25, winSum=421
3130 13:27:11.789349 TX Vref=26, minBit 3, minWin=26, winSum=429
3131 13:27:11.792770 TX Vref=28, minBit 1, minWin=26, winSum=428
3132 13:27:11.796120 TX Vref=30, minBit 1, minWin=26, winSum=431
3133 13:27:11.802149 TX Vref=32, minBit 3, minWin=26, winSum=431
3134 13:27:11.806484 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
3135 13:27:11.806919
3136 13:27:11.808824 Final TX Range 1 Vref 30
3137 13:27:11.809294
3138 13:27:11.809765 ==
3139 13:27:11.812604 Dram Type= 6, Freq= 0, CH_1, rank 0
3140 13:27:11.816377 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3141 13:27:11.818904 ==
3142 13:27:11.819411
3143 13:27:11.819741
3144 13:27:11.820047 TX Vref Scan disable
3145 13:27:11.822156 == TX Byte 0 ==
3146 13:27:11.825731 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3147 13:27:11.832552 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3148 13:27:11.833059 == TX Byte 1 ==
3149 13:27:11.836096 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3150 13:27:11.842258 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3151 13:27:11.842695
3152 13:27:11.843028 [DATLAT]
3153 13:27:11.843333 Freq=1200, CH1 RK0
3154 13:27:11.843630
3155 13:27:11.845583 DATLAT Default: 0xd
3156 13:27:11.846012 0, 0xFFFF, sum = 0
3157 13:27:11.849326 1, 0xFFFF, sum = 0
3158 13:27:11.852446 2, 0xFFFF, sum = 0
3159 13:27:11.852957 3, 0xFFFF, sum = 0
3160 13:27:11.855328 4, 0xFFFF, sum = 0
3161 13:27:11.855763 5, 0xFFFF, sum = 0
3162 13:27:11.858698 6, 0xFFFF, sum = 0
3163 13:27:11.859132 7, 0xFFFF, sum = 0
3164 13:27:11.862455 8, 0xFFFF, sum = 0
3165 13:27:11.862972 9, 0xFFFF, sum = 0
3166 13:27:11.865149 10, 0xFFFF, sum = 0
3167 13:27:11.865647 11, 0x0, sum = 1
3168 13:27:11.868971 12, 0x0, sum = 2
3169 13:27:11.869564 13, 0x0, sum = 3
3170 13:27:11.872545 14, 0x0, sum = 4
3171 13:27:11.873058 best_step = 12
3172 13:27:11.873459
3173 13:27:11.873828 ==
3174 13:27:11.875244 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 13:27:11.878793 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3176 13:27:11.879310 ==
3177 13:27:11.882264 RX Vref Scan: 1
3178 13:27:11.882695
3179 13:27:11.885036 Set Vref Range= 32 -> 127
3180 13:27:11.885603
3181 13:27:11.885956 RX Vref 32 -> 127, step: 1
3182 13:27:11.888558
3183 13:27:11.889087 RX Delay -29 -> 252, step: 4
3184 13:27:11.889501
3185 13:27:11.892076 Set Vref, RX VrefLevel [Byte0]: 32
3186 13:27:11.895208 [Byte1]: 32
3187 13:27:11.899199
3188 13:27:11.899632 Set Vref, RX VrefLevel [Byte0]: 33
3189 13:27:11.902571 [Byte1]: 33
3190 13:27:11.907493
3191 13:27:11.908057 Set Vref, RX VrefLevel [Byte0]: 34
3192 13:27:11.910790 [Byte1]: 34
3193 13:27:11.915050
3194 13:27:11.915553 Set Vref, RX VrefLevel [Byte0]: 35
3195 13:27:11.918816 [Byte1]: 35
3196 13:27:11.923065
3197 13:27:11.923491 Set Vref, RX VrefLevel [Byte0]: 36
3198 13:27:11.926306 [Byte1]: 36
3199 13:27:11.931124
3200 13:27:11.931633 Set Vref, RX VrefLevel [Byte0]: 37
3201 13:27:11.934384 [Byte1]: 37
3202 13:27:11.939064
3203 13:27:11.939493 Set Vref, RX VrefLevel [Byte0]: 38
3204 13:27:11.942241 [Byte1]: 38
3205 13:27:11.947594
3206 13:27:11.948105 Set Vref, RX VrefLevel [Byte0]: 39
3207 13:27:11.950420 [Byte1]: 39
3208 13:27:11.955021
3209 13:27:11.955453 Set Vref, RX VrefLevel [Byte0]: 40
3210 13:27:11.958448 [Byte1]: 40
3211 13:27:11.963102
3212 13:27:11.963626 Set Vref, RX VrefLevel [Byte0]: 41
3213 13:27:11.966174 [Byte1]: 41
3214 13:27:11.970806
3215 13:27:11.971309 Set Vref, RX VrefLevel [Byte0]: 42
3216 13:27:11.973973 [Byte1]: 42
3217 13:27:11.978726
3218 13:27:11.979238 Set Vref, RX VrefLevel [Byte0]: 43
3219 13:27:11.982378 [Byte1]: 43
3220 13:27:11.986951
3221 13:27:11.987462 Set Vref, RX VrefLevel [Byte0]: 44
3222 13:27:11.989874 [Byte1]: 44
3223 13:27:11.995122
3224 13:27:11.995635 Set Vref, RX VrefLevel [Byte0]: 45
3225 13:27:11.997970 [Byte1]: 45
3226 13:27:12.002797
3227 13:27:12.003223 Set Vref, RX VrefLevel [Byte0]: 46
3228 13:27:12.005943 [Byte1]: 46
3229 13:27:12.010836
3230 13:27:12.011348 Set Vref, RX VrefLevel [Byte0]: 47
3231 13:27:12.014187 [Byte1]: 47
3232 13:27:12.018463
3233 13:27:12.018899 Set Vref, RX VrefLevel [Byte0]: 48
3234 13:27:12.022238 [Byte1]: 48
3235 13:27:12.026547
3236 13:27:12.027080 Set Vref, RX VrefLevel [Byte0]: 49
3237 13:27:12.029630 [Byte1]: 49
3238 13:27:12.034502
3239 13:27:12.035011 Set Vref, RX VrefLevel [Byte0]: 50
3240 13:27:12.037858 [Byte1]: 50
3241 13:27:12.042681
3242 13:27:12.043105 Set Vref, RX VrefLevel [Byte0]: 51
3243 13:27:12.046141 [Byte1]: 51
3244 13:27:12.050797
3245 13:27:12.051380 Set Vref, RX VrefLevel [Byte0]: 52
3246 13:27:12.053707 [Byte1]: 52
3247 13:27:12.058580
3248 13:27:12.059006 Set Vref, RX VrefLevel [Byte0]: 53
3249 13:27:12.061730 [Byte1]: 53
3250 13:27:12.066507
3251 13:27:12.067018 Set Vref, RX VrefLevel [Byte0]: 54
3252 13:27:12.070181 [Byte1]: 54
3253 13:27:12.074063
3254 13:27:12.074569 Set Vref, RX VrefLevel [Byte0]: 55
3255 13:27:12.077713 [Byte1]: 55
3256 13:27:12.082294
3257 13:27:12.082803 Set Vref, RX VrefLevel [Byte0]: 56
3258 13:27:12.086024 [Byte1]: 56
3259 13:27:12.090905
3260 13:27:12.091409 Set Vref, RX VrefLevel [Byte0]: 57
3261 13:27:12.093716 [Byte1]: 57
3262 13:27:12.098041
3263 13:27:12.098660 Set Vref, RX VrefLevel [Byte0]: 58
3264 13:27:12.101492 [Byte1]: 58
3265 13:27:12.106143
3266 13:27:12.106648 Set Vref, RX VrefLevel [Byte0]: 59
3267 13:27:12.109642 [Byte1]: 59
3268 13:27:12.114352
3269 13:27:12.114856 Set Vref, RX VrefLevel [Byte0]: 60
3270 13:27:12.117309 [Byte1]: 60
3271 13:27:12.121821
3272 13:27:12.122330 Set Vref, RX VrefLevel [Byte0]: 61
3273 13:27:12.125499 [Byte1]: 61
3274 13:27:12.129867
3275 13:27:12.130459 Set Vref, RX VrefLevel [Byte0]: 62
3276 13:27:12.133353 [Byte1]: 62
3277 13:27:12.137856
3278 13:27:12.138283 Set Vref, RX VrefLevel [Byte0]: 63
3279 13:27:12.141152 [Byte1]: 63
3280 13:27:12.146345
3281 13:27:12.146849 Set Vref, RX VrefLevel [Byte0]: 64
3282 13:27:12.148793 [Byte1]: 64
3283 13:27:12.153777
3284 13:27:12.154203 Set Vref, RX VrefLevel [Byte0]: 65
3285 13:27:12.157196 [Byte1]: 65
3286 13:27:12.162130
3287 13:27:12.162777 Set Vref, RX VrefLevel [Byte0]: 66
3288 13:27:12.165329 [Byte1]: 66
3289 13:27:12.170033
3290 13:27:12.170555 Set Vref, RX VrefLevel [Byte0]: 67
3291 13:27:12.173541 [Byte1]: 67
3292 13:27:12.178205
3293 13:27:12.178714 Set Vref, RX VrefLevel [Byte0]: 68
3294 13:27:12.180764 [Byte1]: 68
3295 13:27:12.185843
3296 13:27:12.186356 Final RX Vref Byte 0 = 54 to rank0
3297 13:27:12.189306 Final RX Vref Byte 1 = 50 to rank0
3298 13:27:12.192574 Final RX Vref Byte 0 = 54 to rank1
3299 13:27:12.195541 Final RX Vref Byte 1 = 50 to rank1==
3300 13:27:12.198907 Dram Type= 6, Freq= 0, CH_1, rank 0
3301 13:27:12.205928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3302 13:27:12.206440 ==
3303 13:27:12.206778 DQS Delay:
3304 13:27:12.207082 DQS0 = 0, DQS1 = 0
3305 13:27:12.208862 DQM Delay:
3306 13:27:12.209409 DQM0 = 115, DQM1 = 105
3307 13:27:12.212254 DQ Delay:
3308 13:27:12.215193 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3309 13:27:12.218820 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =114
3310 13:27:12.222304 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3311 13:27:12.225043 DQ12 =114, DQ13 =116, DQ14 =114, DQ15 =112
3312 13:27:12.225515
3313 13:27:12.225848
3314 13:27:12.235438 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
3315 13:27:12.235942 CH1 RK0: MR19=404, MR18=1B1B
3316 13:27:12.242475 CH1_RK0: MR19=0x404, MR18=0x1B1B, DQSOSC=399, MR23=63, INC=41, DEC=27
3317 13:27:12.243001
3318 13:27:12.245502 ----->DramcWriteLeveling(PI) begin...
3319 13:27:12.246015 ==
3320 13:27:12.249023 Dram Type= 6, Freq= 0, CH_1, rank 1
3321 13:27:12.251742 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3322 13:27:12.255507 ==
3323 13:27:12.258730 Write leveling (Byte 0): 21 => 21
3324 13:27:12.259297 Write leveling (Byte 1): 21 => 21
3325 13:27:12.261840 DramcWriteLeveling(PI) end<-----
3326 13:27:12.262263
3327 13:27:12.262658 ==
3328 13:27:12.265334 Dram Type= 6, Freq= 0, CH_1, rank 1
3329 13:27:12.271583 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3330 13:27:12.272105 ==
3331 13:27:12.275555 [Gating] SW mode calibration
3332 13:27:12.282234 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3333 13:27:12.284874 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3334 13:27:12.291564 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3335 13:27:12.294955 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3336 13:27:12.298233 0 11 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3337 13:27:12.304900 0 11 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
3338 13:27:12.308791 0 11 16 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (1 0)
3339 13:27:12.311767 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3340 13:27:12.318697 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3341 13:27:12.321548 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3342 13:27:12.325033 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3343 13:27:12.328285 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3344 13:27:12.335263 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3345 13:27:12.338579 0 12 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
3346 13:27:12.341803 0 12 16 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
3347 13:27:12.348031 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3348 13:27:12.351502 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3349 13:27:12.355155 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3350 13:27:12.361761 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3351 13:27:12.364409 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3352 13:27:12.368167 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3353 13:27:12.375380 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3354 13:27:12.378237 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3355 13:27:12.381333 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3356 13:27:12.388229 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3357 13:27:12.391794 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3358 13:27:12.394791 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3359 13:27:12.401157 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3360 13:27:12.405044 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3361 13:27:12.408127 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3362 13:27:12.415037 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3363 13:27:12.417955 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3364 13:27:12.421837 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3365 13:27:12.427638 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3366 13:27:12.431283 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3367 13:27:12.434773 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3368 13:27:12.441634 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3369 13:27:12.444599 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3370 13:27:12.447478 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3371 13:27:12.450950 Total UI for P1: 0, mck2ui 16
3372 13:27:12.454456 best dqsien dly found for B0: ( 0, 15, 14)
3373 13:27:12.460625 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3374 13:27:12.461048 Total UI for P1: 0, mck2ui 16
3375 13:27:12.464510 best dqsien dly found for B1: ( 0, 15, 16)
3376 13:27:12.470736 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3377 13:27:12.474129 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3378 13:27:12.474552
3379 13:27:12.477774 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3380 13:27:12.481147 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3381 13:27:12.484084 [Gating] SW calibration Done
3382 13:27:12.484507 ==
3383 13:27:12.487052 Dram Type= 6, Freq= 0, CH_1, rank 1
3384 13:27:12.490609 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3385 13:27:12.491049 ==
3386 13:27:12.494481 RX Vref Scan: 0
3387 13:27:12.494991
3388 13:27:12.495319 RX Vref 0 -> 0, step: 1
3389 13:27:12.495619
3390 13:27:12.497620 RX Delay -40 -> 252, step: 8
3391 13:27:12.500307 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3392 13:27:12.507021 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3393 13:27:12.510598 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3394 13:27:12.514150 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3395 13:27:12.516813 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3396 13:27:12.520628 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3397 13:27:12.526847 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3398 13:27:12.530375 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3399 13:27:12.534179 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3400 13:27:12.536764 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3401 13:27:12.540398 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3402 13:27:12.547123 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3403 13:27:12.550467 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3404 13:27:12.553747 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3405 13:27:12.557298 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3406 13:27:12.564019 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3407 13:27:12.564528 ==
3408 13:27:12.567020 Dram Type= 6, Freq= 0, CH_1, rank 1
3409 13:27:12.570455 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3410 13:27:12.570980 ==
3411 13:27:12.571316 DQS Delay:
3412 13:27:12.573373 DQS0 = 0, DQS1 = 0
3413 13:27:12.573795 DQM Delay:
3414 13:27:12.576570 DQM0 = 115, DQM1 = 106
3415 13:27:12.576990 DQ Delay:
3416 13:27:12.580059 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3417 13:27:12.583918 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3418 13:27:12.586680 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =103
3419 13:27:12.590148 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3420 13:27:12.590602
3421 13:27:12.590938
3422 13:27:12.591236 ==
3423 13:27:12.593368 Dram Type= 6, Freq= 0, CH_1, rank 1
3424 13:27:12.599894 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3425 13:27:12.600390 ==
3426 13:27:12.600724
3427 13:27:12.601024
3428 13:27:12.601358 TX Vref Scan disable
3429 13:27:12.604228 == TX Byte 0 ==
3430 13:27:12.606631 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3431 13:27:12.610692 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3432 13:27:12.614154 == TX Byte 1 ==
3433 13:27:12.617339 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3434 13:27:12.620460 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3435 13:27:12.623576 ==
3436 13:27:12.627233 Dram Type= 6, Freq= 0, CH_1, rank 1
3437 13:27:12.630799 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3438 13:27:12.631302 ==
3439 13:27:12.641294 TX Vref=22, minBit 9, minWin=25, winSum=420
3440 13:27:12.644951 TX Vref=24, minBit 9, minWin=25, winSum=424
3441 13:27:12.647884 TX Vref=26, minBit 3, minWin=26, winSum=429
3442 13:27:12.651406 TX Vref=28, minBit 9, minWin=26, winSum=432
3443 13:27:12.654979 TX Vref=30, minBit 9, minWin=26, winSum=430
3444 13:27:12.661333 TX Vref=32, minBit 9, minWin=26, winSum=431
3445 13:27:12.664633 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 28
3446 13:27:12.665153
3447 13:27:12.667920 Final TX Range 1 Vref 28
3448 13:27:12.668346
3449 13:27:12.668674 ==
3450 13:27:12.671249 Dram Type= 6, Freq= 0, CH_1, rank 1
3451 13:27:12.673995 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3452 13:27:12.674426 ==
3453 13:27:12.677536
3454 13:27:12.677957
3455 13:27:12.678285 TX Vref Scan disable
3456 13:27:12.681361 == TX Byte 0 ==
3457 13:27:12.684512 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3458 13:27:12.690507 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3459 13:27:12.690938 == TX Byte 1 ==
3460 13:27:12.694272 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3461 13:27:12.700881 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3462 13:27:12.701407
3463 13:27:12.701743 [DATLAT]
3464 13:27:12.702044 Freq=1200, CH1 RK1
3465 13:27:12.702335
3466 13:27:12.704324 DATLAT Default: 0xc
3467 13:27:12.704829 0, 0xFFFF, sum = 0
3468 13:27:12.707418 1, 0xFFFF, sum = 0
3469 13:27:12.710380 2, 0xFFFF, sum = 0
3470 13:27:12.710812 3, 0xFFFF, sum = 0
3471 13:27:12.713802 4, 0xFFFF, sum = 0
3472 13:27:12.714235 5, 0xFFFF, sum = 0
3473 13:27:12.717475 6, 0xFFFF, sum = 0
3474 13:27:12.717912 7, 0xFFFF, sum = 0
3475 13:27:12.720892 8, 0xFFFF, sum = 0
3476 13:27:12.721444 9, 0xFFFF, sum = 0
3477 13:27:12.724236 10, 0xFFFF, sum = 0
3478 13:27:12.724666 11, 0x0, sum = 1
3479 13:27:12.727442 12, 0x0, sum = 2
3480 13:27:12.727897 13, 0x0, sum = 3
3481 13:27:12.730935 14, 0x0, sum = 4
3482 13:27:12.731457 best_step = 12
3483 13:27:12.731795
3484 13:27:12.732101 ==
3485 13:27:12.733816 Dram Type= 6, Freq= 0, CH_1, rank 1
3486 13:27:12.737315 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3487 13:27:12.737826 ==
3488 13:27:12.740326 RX Vref Scan: 0
3489 13:27:12.740747
3490 13:27:12.744077 RX Vref 0 -> 0, step: 1
3491 13:27:12.744633
3492 13:27:12.745032 RX Delay -29 -> 252, step: 4
3493 13:27:12.751833 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3494 13:27:12.755032 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3495 13:27:12.758143 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3496 13:27:12.761289 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3497 13:27:12.764913 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3498 13:27:12.771632 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3499 13:27:12.774753 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3500 13:27:12.777958 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3501 13:27:12.781011 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3502 13:27:12.784896 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3503 13:27:12.791554 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3504 13:27:12.794556 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3505 13:27:12.797544 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3506 13:27:12.800999 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3507 13:27:12.807562 iDelay=199, Bit 14, Center 116 (47 ~ 186) 140
3508 13:27:12.810931 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3509 13:27:12.811361 ==
3510 13:27:12.814336 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 13:27:12.817592 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3512 13:27:12.818020 ==
3513 13:27:12.818379 DQS Delay:
3514 13:27:12.821135 DQS0 = 0, DQS1 = 0
3515 13:27:12.821604 DQM Delay:
3516 13:27:12.824122 DQM0 = 114, DQM1 = 103
3517 13:27:12.824544 DQ Delay:
3518 13:27:12.827550 DQ0 =114, DQ1 =110, DQ2 =108, DQ3 =112
3519 13:27:12.830901 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3520 13:27:12.834236 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3521 13:27:12.837622 DQ12 =112, DQ13 =110, DQ14 =116, DQ15 =110
3522 13:27:12.840864
3523 13:27:12.841277
3524 13:27:12.847707 [DQSOSCAuto] RK1, (LSB)MR18= 0xc0c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3525 13:27:12.850428 CH1 RK1: MR19=404, MR18=C0C
3526 13:27:12.857679 CH1_RK1: MR19=0x404, MR18=0xC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3527 13:27:12.858369 [RxdqsGatingPostProcess] freq 1200
3528 13:27:12.863608 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3529 13:27:12.867370 Pre-setting of DQS Precalculation
3530 13:27:12.874018 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3531 13:27:12.880863 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3532 13:27:12.887144 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3533 13:27:12.887533
3534 13:27:12.887832
3535 13:27:12.891097 [Calibration Summary] 2400 Mbps
3536 13:27:12.891579 CH 0, Rank 0
3537 13:27:12.893475 SW Impedance : PASS
3538 13:27:12.897650 DUTY Scan : NO K
3539 13:27:12.898110 ZQ Calibration : PASS
3540 13:27:12.899950 Jitter Meter : NO K
3541 13:27:12.903620 CBT Training : PASS
3542 13:27:12.904082 Write leveling : PASS
3543 13:27:12.907217 RX DQS gating : PASS
3544 13:27:12.907687 RX DQ/DQS(RDDQC) : PASS
3545 13:27:12.910359 TX DQ/DQS : PASS
3546 13:27:12.913457 RX DATLAT : PASS
3547 13:27:12.913849 RX DQ/DQS(Engine): PASS
3548 13:27:12.917313 TX OE : NO K
3549 13:27:12.917827 All Pass.
3550 13:27:12.918136
3551 13:27:12.920244 CH 0, Rank 1
3552 13:27:12.920713 SW Impedance : PASS
3553 13:27:12.923253 DUTY Scan : NO K
3554 13:27:12.927283 ZQ Calibration : PASS
3555 13:27:12.927818 Jitter Meter : NO K
3556 13:27:12.930082 CBT Training : PASS
3557 13:27:12.933881 Write leveling : PASS
3558 13:27:12.934398 RX DQS gating : PASS
3559 13:27:12.936980 RX DQ/DQS(RDDQC) : PASS
3560 13:27:12.940308 TX DQ/DQS : PASS
3561 13:27:12.940817 RX DATLAT : PASS
3562 13:27:12.943308 RX DQ/DQS(Engine): PASS
3563 13:27:12.946854 TX OE : NO K
3564 13:27:12.947370 All Pass.
3565 13:27:12.947702
3566 13:27:12.948007 CH 1, Rank 0
3567 13:27:12.950120 SW Impedance : PASS
3568 13:27:12.953352 DUTY Scan : NO K
3569 13:27:12.953860 ZQ Calibration : PASS
3570 13:27:12.956902 Jitter Meter : NO K
3571 13:27:12.961283 CBT Training : PASS
3572 13:27:12.961803 Write leveling : PASS
3573 13:27:12.963624 RX DQS gating : PASS
3574 13:27:12.964136 RX DQ/DQS(RDDQC) : PASS
3575 13:27:12.966936 TX DQ/DQS : PASS
3576 13:27:12.970089 RX DATLAT : PASS
3577 13:27:12.970595 RX DQ/DQS(Engine): PASS
3578 13:27:12.973456 TX OE : NO K
3579 13:27:12.973968 All Pass.
3580 13:27:12.974300
3581 13:27:12.976438 CH 1, Rank 1
3582 13:27:12.976865 SW Impedance : PASS
3583 13:27:12.980047 DUTY Scan : NO K
3584 13:27:12.983535 ZQ Calibration : PASS
3585 13:27:12.984041 Jitter Meter : NO K
3586 13:27:12.986250 CBT Training : PASS
3587 13:27:12.989903 Write leveling : PASS
3588 13:27:12.990405 RX DQS gating : PASS
3589 13:27:12.993300 RX DQ/DQS(RDDQC) : PASS
3590 13:27:12.996310 TX DQ/DQS : PASS
3591 13:27:12.996812 RX DATLAT : PASS
3592 13:27:12.999826 RX DQ/DQS(Engine): PASS
3593 13:27:13.002870 TX OE : NO K
3594 13:27:13.003302 All Pass.
3595 13:27:13.003634
3596 13:27:13.003939 DramC Write-DBI off
3597 13:27:13.006427 PER_BANK_REFRESH: Hybrid Mode
3598 13:27:13.010048 TX_TRACKING: ON
3599 13:27:13.016258 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3600 13:27:13.019992 [FAST_K] Save calibration result to emmc
3601 13:27:13.025968 dramc_set_vcore_voltage set vcore to 650000
3602 13:27:13.026446 Read voltage for 600, 5
3603 13:27:13.029740 Vio18 = 0
3604 13:27:13.030183 Vcore = 650000
3605 13:27:13.030518 Vdram = 0
3606 13:27:13.033513 Vddq = 0
3607 13:27:13.034021 Vmddr = 0
3608 13:27:13.036505 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3609 13:27:13.042577 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3610 13:27:13.046247 MEM_TYPE=3, freq_sel=19
3611 13:27:13.049462 sv_algorithm_assistance_LP4_1600
3612 13:27:13.052817 ============ PULL DRAM RESETB DOWN ============
3613 13:27:13.056638 ========== PULL DRAM RESETB DOWN end =========
3614 13:27:13.062683 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3615 13:27:13.066093 ===================================
3616 13:27:13.066605 LPDDR4 DRAM CONFIGURATION
3617 13:27:13.069516 ===================================
3618 13:27:13.072708 EX_ROW_EN[0] = 0x0
3619 13:27:13.073220 EX_ROW_EN[1] = 0x0
3620 13:27:13.075595 LP4Y_EN = 0x0
3621 13:27:13.076026 WORK_FSP = 0x0
3622 13:27:13.079297 WL = 0x2
3623 13:27:13.079801 RL = 0x2
3624 13:27:13.082816 BL = 0x2
3625 13:27:13.085507 RPST = 0x0
3626 13:27:13.085954 RD_PRE = 0x0
3627 13:27:13.088914 WR_PRE = 0x1
3628 13:27:13.089444 WR_PST = 0x0
3629 13:27:13.092518 DBI_WR = 0x0
3630 13:27:13.093020 DBI_RD = 0x0
3631 13:27:13.095947 OTF = 0x1
3632 13:27:13.098949 ===================================
3633 13:27:13.102138 ===================================
3634 13:27:13.102570 ANA top config
3635 13:27:13.106187 ===================================
3636 13:27:13.109327 DLL_ASYNC_EN = 0
3637 13:27:13.112102 ALL_SLAVE_EN = 1
3638 13:27:13.112530 NEW_RANK_MODE = 1
3639 13:27:13.115318 DLL_IDLE_MODE = 1
3640 13:27:13.118946 LP45_APHY_COMB_EN = 1
3641 13:27:13.122488 TX_ODT_DIS = 1
3642 13:27:13.125213 NEW_8X_MODE = 1
3643 13:27:13.125678 ===================================
3644 13:27:13.128493 ===================================
3645 13:27:13.132086 data_rate = 1200
3646 13:27:13.135435 CKR = 1
3647 13:27:13.138438 DQ_P2S_RATIO = 8
3648 13:27:13.141984 ===================================
3649 13:27:13.145414 CA_P2S_RATIO = 8
3650 13:27:13.149358 DQ_CA_OPEN = 0
3651 13:27:13.152175 DQ_SEMI_OPEN = 0
3652 13:27:13.152604 CA_SEMI_OPEN = 0
3653 13:27:13.154850 CA_FULL_RATE = 0
3654 13:27:13.158374 DQ_CKDIV4_EN = 1
3655 13:27:13.162194 CA_CKDIV4_EN = 1
3656 13:27:13.165497 CA_PREDIV_EN = 0
3657 13:27:13.168466 PH8_DLY = 0
3658 13:27:13.168972 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3659 13:27:13.172038 DQ_AAMCK_DIV = 4
3660 13:27:13.174953 CA_AAMCK_DIV = 4
3661 13:27:13.178189 CA_ADMCK_DIV = 4
3662 13:27:13.181443 DQ_TRACK_CA_EN = 0
3663 13:27:13.185290 CA_PICK = 600
3664 13:27:13.187982 CA_MCKIO = 600
3665 13:27:13.188466 MCKIO_SEMI = 0
3666 13:27:13.191705 PLL_FREQ = 2288
3667 13:27:13.195496 DQ_UI_PI_RATIO = 32
3668 13:27:13.198132 CA_UI_PI_RATIO = 0
3669 13:27:13.201309 ===================================
3670 13:27:13.204676 ===================================
3671 13:27:13.207996 memory_type:LPDDR4
3672 13:27:13.208497 GP_NUM : 10
3673 13:27:13.211051 SRAM_EN : 1
3674 13:27:13.215029 MD32_EN : 0
3675 13:27:13.217969 ===================================
3676 13:27:13.218462 [ANA_INIT] >>>>>>>>>>>>>>
3677 13:27:13.221146 <<<<<< [CONFIGURE PHASE]: ANA_TX
3678 13:27:13.224753 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3679 13:27:13.228242 ===================================
3680 13:27:13.230850 data_rate = 1200,PCW = 0X5800
3681 13:27:13.234649 ===================================
3682 13:27:13.237716 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3683 13:27:13.243844 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3684 13:27:13.247590 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3685 13:27:13.254066 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3686 13:27:13.257319 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3687 13:27:13.260603 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3688 13:27:13.261117 [ANA_INIT] flow start
3689 13:27:13.264159 [ANA_INIT] PLL >>>>>>>>
3690 13:27:13.267861 [ANA_INIT] PLL <<<<<<<<
3691 13:27:13.270949 [ANA_INIT] MIDPI >>>>>>>>
3692 13:27:13.271458 [ANA_INIT] MIDPI <<<<<<<<
3693 13:27:13.273939 [ANA_INIT] DLL >>>>>>>>
3694 13:27:13.277269 [ANA_INIT] flow end
3695 13:27:13.280847 ============ LP4 DIFF to SE enter ============
3696 13:27:13.284091 ============ LP4 DIFF to SE exit ============
3697 13:27:13.287223 [ANA_INIT] <<<<<<<<<<<<<
3698 13:27:13.290713 [Flow] Enable top DCM control >>>>>
3699 13:27:13.293737 [Flow] Enable top DCM control <<<<<
3700 13:27:13.297488 Enable DLL master slave shuffle
3701 13:27:13.300682 ==============================================================
3702 13:27:13.303432 Gating Mode config
3703 13:27:13.310513 ==============================================================
3704 13:27:13.311040 Config description:
3705 13:27:13.320725 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3706 13:27:13.326707 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3707 13:27:13.330049 SELPH_MODE 0: By rank 1: By Phase
3708 13:27:13.336900 ==============================================================
3709 13:27:13.339866 GAT_TRACK_EN = 1
3710 13:27:13.343226 RX_GATING_MODE = 2
3711 13:27:13.346737 RX_GATING_TRACK_MODE = 2
3712 13:27:13.349950 SELPH_MODE = 1
3713 13:27:13.353057 PICG_EARLY_EN = 1
3714 13:27:13.356446 VALID_LAT_VALUE = 1
3715 13:27:13.359504 ==============================================================
3716 13:27:13.363037 Enter into Gating configuration >>>>
3717 13:27:13.366214 Exit from Gating configuration <<<<
3718 13:27:13.369027 Enter into DVFS_PRE_config >>>>>
3719 13:27:13.382595 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3720 13:27:13.385506 Exit from DVFS_PRE_config <<<<<
3721 13:27:13.388973 Enter into PICG configuration >>>>
3722 13:27:13.389102 Exit from PICG configuration <<<<
3723 13:27:13.392509 [RX_INPUT] configuration >>>>>
3724 13:27:13.395498 [RX_INPUT] configuration <<<<<
3725 13:27:13.402279 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3726 13:27:13.405237 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3727 13:27:13.412471 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3728 13:27:13.419068 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3729 13:27:13.425600 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3730 13:27:13.432051 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3731 13:27:13.435765 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3732 13:27:13.438748 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3733 13:27:13.442344 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3734 13:27:13.449107 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3735 13:27:13.452145 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3736 13:27:13.455542 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3737 13:27:13.458776 ===================================
3738 13:27:13.462065 LPDDR4 DRAM CONFIGURATION
3739 13:27:13.465293 ===================================
3740 13:27:13.468467 EX_ROW_EN[0] = 0x0
3741 13:27:13.468684 EX_ROW_EN[1] = 0x0
3742 13:27:13.472382 LP4Y_EN = 0x0
3743 13:27:13.472807 WORK_FSP = 0x0
3744 13:27:13.475930 WL = 0x2
3745 13:27:13.476341 RL = 0x2
3746 13:27:13.479026 BL = 0x2
3747 13:27:13.479537 RPST = 0x0
3748 13:27:13.482047 RD_PRE = 0x0
3749 13:27:13.482562 WR_PRE = 0x1
3750 13:27:13.485140 WR_PST = 0x0
3751 13:27:13.485593 DBI_WR = 0x0
3752 13:27:13.488846 DBI_RD = 0x0
3753 13:27:13.492277 OTF = 0x1
3754 13:27:13.495726 ===================================
3755 13:27:13.498422 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3756 13:27:13.501898 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3757 13:27:13.505311 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3758 13:27:13.508830 ===================================
3759 13:27:13.511905 LPDDR4 DRAM CONFIGURATION
3760 13:27:13.515287 ===================================
3761 13:27:13.518525 EX_ROW_EN[0] = 0x10
3762 13:27:13.518957 EX_ROW_EN[1] = 0x0
3763 13:27:13.522285 LP4Y_EN = 0x0
3764 13:27:13.522789 WORK_FSP = 0x0
3765 13:27:13.524955 WL = 0x2
3766 13:27:13.525421 RL = 0x2
3767 13:27:13.528868 BL = 0x2
3768 13:27:13.529431 RPST = 0x0
3769 13:27:13.532267 RD_PRE = 0x0
3770 13:27:13.532772 WR_PRE = 0x1
3771 13:27:13.535320 WR_PST = 0x0
3772 13:27:13.535748 DBI_WR = 0x0
3773 13:27:13.538230 DBI_RD = 0x0
3774 13:27:13.538659 OTF = 0x1
3775 13:27:13.541920 ===================================
3776 13:27:13.548594 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3777 13:27:13.553322 nWR fixed to 30
3778 13:27:13.556365 [ModeRegInit_LP4] CH0 RK0
3779 13:27:13.556849 [ModeRegInit_LP4] CH0 RK1
3780 13:27:13.559892 [ModeRegInit_LP4] CH1 RK0
3781 13:27:13.562852 [ModeRegInit_LP4] CH1 RK1
3782 13:27:13.563284 match AC timing 16
3783 13:27:13.569861 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3784 13:27:13.573053 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3785 13:27:13.576664 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3786 13:27:13.583489 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3787 13:27:13.586019 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3788 13:27:13.586446 ==
3789 13:27:13.589138 Dram Type= 6, Freq= 0, CH_0, rank 0
3790 13:27:13.593205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3791 13:27:13.593750 ==
3792 13:27:13.599335 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3793 13:27:13.606311 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3794 13:27:13.609643 [CA 0] Center 35 (5~66) winsize 62
3795 13:27:13.613597 [CA 1] Center 35 (5~66) winsize 62
3796 13:27:13.615878 [CA 2] Center 34 (4~65) winsize 62
3797 13:27:13.619432 [CA 3] Center 34 (4~65) winsize 62
3798 13:27:13.622753 [CA 4] Center 33 (3~64) winsize 62
3799 13:27:13.626341 [CA 5] Center 33 (3~64) winsize 62
3800 13:27:13.626770
3801 13:27:13.629714 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3802 13:27:13.630144
3803 13:27:13.633009 [CATrainingPosCal] consider 1 rank data
3804 13:27:13.636285 u2DelayCellTimex100 = 270/100 ps
3805 13:27:13.639542 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3806 13:27:13.643054 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3807 13:27:13.646058 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3808 13:27:13.649279 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3809 13:27:13.652774 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3810 13:27:13.659584 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3811 13:27:13.660017
3812 13:27:13.662406 CA PerBit enable=1, Macro0, CA PI delay=33
3813 13:27:13.662839
3814 13:27:13.666189 [CBTSetCACLKResult] CA Dly = 33
3815 13:27:13.666724 CS Dly: 4 (0~35)
3816 13:27:13.667063 ==
3817 13:27:13.669276 Dram Type= 6, Freq= 0, CH_0, rank 1
3818 13:27:13.672904 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3819 13:27:13.676009 ==
3820 13:27:13.679378 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3821 13:27:13.685923 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3822 13:27:13.688911 [CA 0] Center 35 (5~66) winsize 62
3823 13:27:13.692202 [CA 1] Center 35 (5~66) winsize 62
3824 13:27:13.696231 [CA 2] Center 34 (4~65) winsize 62
3825 13:27:13.699196 [CA 3] Center 34 (4~65) winsize 62
3826 13:27:13.702301 [CA 4] Center 33 (3~64) winsize 62
3827 13:27:13.705966 [CA 5] Center 33 (3~64) winsize 62
3828 13:27:13.706476
3829 13:27:13.709067 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3830 13:27:13.709524
3831 13:27:13.712710 [CATrainingPosCal] consider 2 rank data
3832 13:27:13.715222 u2DelayCellTimex100 = 270/100 ps
3833 13:27:13.718966 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3834 13:27:13.722386 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3835 13:27:13.725986 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3836 13:27:13.729425 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3837 13:27:13.735557 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3838 13:27:13.739085 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3839 13:27:13.739598
3840 13:27:13.742117 CA PerBit enable=1, Macro0, CA PI delay=33
3841 13:27:13.742630
3842 13:27:13.745441 [CBTSetCACLKResult] CA Dly = 33
3843 13:27:13.745885 CS Dly: 4 (0~35)
3844 13:27:13.746316
3845 13:27:13.749028 ----->DramcWriteLeveling(PI) begin...
3846 13:27:13.749609 ==
3847 13:27:13.751934 Dram Type= 6, Freq= 0, CH_0, rank 0
3848 13:27:13.758577 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3849 13:27:13.759024 ==
3850 13:27:13.761863 Write leveling (Byte 0): 30 => 30
3851 13:27:13.765683 Write leveling (Byte 1): 30 => 30
3852 13:27:13.766191 DramcWriteLeveling(PI) end<-----
3853 13:27:13.768445
3854 13:27:13.768944 ==
3855 13:27:13.771776 Dram Type= 6, Freq= 0, CH_0, rank 0
3856 13:27:13.775250 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3857 13:27:13.775754 ==
3858 13:27:13.778534 [Gating] SW mode calibration
3859 13:27:13.784861 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3860 13:27:13.788723 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3861 13:27:13.795068 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3862 13:27:13.798377 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3863 13:27:13.801404 0 5 8 | B1->B0 | 3131 2f2f | 1 1 | (1 1) (1 1)
3864 13:27:13.808355 0 5 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3865 13:27:13.811636 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3866 13:27:13.814983 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3867 13:27:13.822123 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3868 13:27:13.824899 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3869 13:27:13.828446 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3870 13:27:13.834979 0 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3871 13:27:13.837929 0 6 8 | B1->B0 | 2b2b 3131 | 0 0 | (0 0) (0 0)
3872 13:27:13.841510 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3873 13:27:13.848501 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3874 13:27:13.851425 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3875 13:27:13.854804 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3876 13:27:13.861072 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3877 13:27:13.864186 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3878 13:27:13.867784 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3879 13:27:13.874330 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3880 13:27:13.877493 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3881 13:27:13.881162 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3882 13:27:13.887972 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3883 13:27:13.891281 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3884 13:27:13.894364 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3885 13:27:13.900937 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3886 13:27:13.904324 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3887 13:27:13.907416 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3888 13:27:13.914640 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3889 13:27:13.917326 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3890 13:27:13.920837 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3891 13:27:13.927250 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3892 13:27:13.930237 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3893 13:27:13.933695 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3894 13:27:13.940729 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3895 13:27:13.943849 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3896 13:27:13.946939 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3897 13:27:13.950707 Total UI for P1: 0, mck2ui 16
3898 13:27:13.953599 best dqsien dly found for B0: ( 0, 9, 8)
3899 13:27:13.957060 Total UI for P1: 0, mck2ui 16
3900 13:27:13.960124 best dqsien dly found for B1: ( 0, 9, 10)
3901 13:27:13.964328 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3902 13:27:13.966878 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3903 13:27:13.967313
3904 13:27:13.970401 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3905 13:27:13.977025 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3906 13:27:13.977582 [Gating] SW calibration Done
3907 13:27:13.980171 ==
3908 13:27:13.980603 Dram Type= 6, Freq= 0, CH_0, rank 0
3909 13:27:13.987086 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3910 13:27:13.987596 ==
3911 13:27:13.987933 RX Vref Scan: 0
3912 13:27:13.988240
3913 13:27:13.990127 RX Vref 0 -> 0, step: 1
3914 13:27:13.990554
3915 13:27:13.993682 RX Delay -230 -> 252, step: 16
3916 13:27:13.997022 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3917 13:27:13.999823 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3918 13:27:14.007008 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3919 13:27:14.010300 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3920 13:27:14.013369 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3921 13:27:14.016731 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3922 13:27:14.020437 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3923 13:27:14.026623 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3924 13:27:14.030138 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3925 13:27:14.033274 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3926 13:27:14.036324 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3927 13:27:14.042958 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3928 13:27:14.046350 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3929 13:27:14.049797 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3930 13:27:14.053597 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3931 13:27:14.059790 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3932 13:27:14.060301 ==
3933 13:27:14.063163 Dram Type= 6, Freq= 0, CH_0, rank 0
3934 13:27:14.066226 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3935 13:27:14.066654 ==
3936 13:27:14.066985 DQS Delay:
3937 13:27:14.069064 DQS0 = 0, DQS1 = 0
3938 13:27:14.069524 DQM Delay:
3939 13:27:14.073385 DQM0 = 38, DQM1 = 33
3940 13:27:14.073906 DQ Delay:
3941 13:27:14.076052 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3942 13:27:14.079273 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3943 13:27:14.083340 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3944 13:27:14.085990 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3945 13:27:14.086498
3946 13:27:14.086827
3947 13:27:14.087129 ==
3948 13:27:14.089191 Dram Type= 6, Freq= 0, CH_0, rank 0
3949 13:27:14.095607 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3950 13:27:14.096120 ==
3951 13:27:14.096454
3952 13:27:14.096757
3953 13:27:14.097044 TX Vref Scan disable
3954 13:27:14.099369 == TX Byte 0 ==
3955 13:27:14.102231 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3956 13:27:14.108658 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3957 13:27:14.109154 == TX Byte 1 ==
3958 13:27:14.112205 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3959 13:27:14.119067 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3960 13:27:14.119561 ==
3961 13:27:14.122207 Dram Type= 6, Freq= 0, CH_0, rank 0
3962 13:27:14.125703 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3963 13:27:14.126133 ==
3964 13:27:14.126461
3965 13:27:14.126763
3966 13:27:14.129076 TX Vref Scan disable
3967 13:27:14.132398 == TX Byte 0 ==
3968 13:27:14.135455 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3969 13:27:14.138680 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3970 13:27:14.142454 == TX Byte 1 ==
3971 13:27:14.145693 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3972 13:27:14.148667 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3973 13:27:14.149093
3974 13:27:14.149466 [DATLAT]
3975 13:27:14.152292 Freq=600, CH0 RK0
3976 13:27:14.152799
3977 13:27:14.155444 DATLAT Default: 0x9
3978 13:27:14.156000 0, 0xFFFF, sum = 0
3979 13:27:14.158382 1, 0xFFFF, sum = 0
3980 13:27:14.158817 2, 0xFFFF, sum = 0
3981 13:27:14.162165 3, 0xFFFF, sum = 0
3982 13:27:14.162679 4, 0xFFFF, sum = 0
3983 13:27:14.165690 5, 0xFFFF, sum = 0
3984 13:27:14.166204 6, 0xFFFF, sum = 0
3985 13:27:14.168820 7, 0x0, sum = 1
3986 13:27:14.169376 8, 0x0, sum = 2
3987 13:27:14.169721 9, 0x0, sum = 3
3988 13:27:14.172615 10, 0x0, sum = 4
3989 13:27:14.173051 best_step = 8
3990 13:27:14.173415
3991 13:27:14.174962 ==
3992 13:27:14.175389 Dram Type= 6, Freq= 0, CH_0, rank 0
3993 13:27:14.182472 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3994 13:27:14.182983 ==
3995 13:27:14.183318 RX Vref Scan: 1
3996 13:27:14.183624
3997 13:27:14.184896 RX Vref 0 -> 0, step: 1
3998 13:27:14.185358
3999 13:27:14.188597 RX Delay -195 -> 252, step: 8
4000 13:27:14.189022
4001 13:27:14.191808 Set Vref, RX VrefLevel [Byte0]: 47
4002 13:27:14.194744 [Byte1]: 47
4003 13:27:14.195166
4004 13:27:14.198371 Final RX Vref Byte 0 = 47 to rank0
4005 13:27:14.202183 Final RX Vref Byte 1 = 47 to rank0
4006 13:27:14.204497 Final RX Vref Byte 0 = 47 to rank1
4007 13:27:14.207725 Final RX Vref Byte 1 = 47 to rank1==
4008 13:27:14.211565 Dram Type= 6, Freq= 0, CH_0, rank 0
4009 13:27:14.214957 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4010 13:27:14.218105 ==
4011 13:27:14.218530 DQS Delay:
4012 13:27:14.218859 DQS0 = 0, DQS1 = 0
4013 13:27:14.221503 DQM Delay:
4014 13:27:14.222009 DQM0 = 40, DQM1 = 29
4015 13:27:14.224942 DQ Delay:
4016 13:27:14.225493 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
4017 13:27:14.227914 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =52
4018 13:27:14.231405 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4019 13:27:14.234209 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
4020 13:27:14.238011
4021 13:27:14.238433
4022 13:27:14.244411 [DQSOSCAuto] RK0, (LSB)MR18= 0x5858, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4023 13:27:14.248183 CH0 RK0: MR19=808, MR18=5858
4024 13:27:14.254067 CH0_RK0: MR19=0x808, MR18=0x5858, DQSOSC=393, MR23=63, INC=169, DEC=113
4025 13:27:14.254563
4026 13:27:14.257730 ----->DramcWriteLeveling(PI) begin...
4027 13:27:14.258242 ==
4028 13:27:14.261281 Dram Type= 6, Freq= 0, CH_0, rank 1
4029 13:27:14.264273 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4030 13:27:14.264781 ==
4031 13:27:14.267278 Write leveling (Byte 0): 29 => 29
4032 13:27:14.271525 Write leveling (Byte 1): 29 => 29
4033 13:27:14.274152 DramcWriteLeveling(PI) end<-----
4034 13:27:14.274658
4035 13:27:14.274989 ==
4036 13:27:14.277595 Dram Type= 6, Freq= 0, CH_0, rank 1
4037 13:27:14.281325 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4038 13:27:14.281853 ==
4039 13:27:14.284147 [Gating] SW mode calibration
4040 13:27:14.290479 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4041 13:27:14.297281 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4042 13:27:14.300718 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4043 13:27:14.307221 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4044 13:27:14.310773 0 5 8 | B1->B0 | 3333 2f2f | 1 1 | (1 0) (0 0)
4045 13:27:14.314154 0 5 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4046 13:27:14.317533 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 13:27:14.324012 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 13:27:14.327041 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 13:27:14.330424 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 13:27:14.337288 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 13:27:14.340532 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 13:27:14.343892 0 6 8 | B1->B0 | 2f2f 3232 | 0 0 | (0 0) (0 0)
4053 13:27:14.350648 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 13:27:14.353673 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 13:27:14.357158 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 13:27:14.363871 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 13:27:14.367229 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 13:27:14.370151 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 13:27:14.376837 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 13:27:14.380126 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4061 13:27:14.383545 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 13:27:14.390608 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 13:27:14.393259 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 13:27:14.396591 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 13:27:14.403425 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 13:27:14.406478 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 13:27:14.410015 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 13:27:14.416349 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 13:27:14.419619 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 13:27:14.422893 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 13:27:14.429535 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 13:27:14.432839 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 13:27:14.436239 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 13:27:14.442488 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 13:27:14.445886 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4076 13:27:14.448958 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4077 13:27:14.455635 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 13:27:14.459154 Total UI for P1: 0, mck2ui 16
4079 13:27:14.462909 best dqsien dly found for B0: ( 0, 9, 6)
4080 13:27:14.465917 Total UI for P1: 0, mck2ui 16
4081 13:27:14.469019 best dqsien dly found for B1: ( 0, 9, 8)
4082 13:27:14.472347 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4083 13:27:14.476226 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4084 13:27:14.476750
4085 13:27:14.479036 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4086 13:27:14.482551 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4087 13:27:14.485480 [Gating] SW calibration Done
4088 13:27:14.485994 ==
4089 13:27:14.488777 Dram Type= 6, Freq= 0, CH_0, rank 1
4090 13:27:14.492054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4091 13:27:14.492592 ==
4092 13:27:14.495608 RX Vref Scan: 0
4093 13:27:14.496106
4094 13:27:14.496547 RX Vref 0 -> 0, step: 1
4095 13:27:14.498757
4096 13:27:14.499276 RX Delay -230 -> 252, step: 16
4097 13:27:14.505465 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4098 13:27:14.508669 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4099 13:27:14.512151 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4100 13:27:14.515502 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4101 13:27:14.522575 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4102 13:27:14.525619 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4103 13:27:14.528473 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4104 13:27:14.531954 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4105 13:27:14.535249 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4106 13:27:14.541619 iDelay=218, Bit 9, Center 17 (-134 ~ 169) 304
4107 13:27:14.545189 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4108 13:27:14.548334 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4109 13:27:14.551809 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4110 13:27:14.558069 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4111 13:27:14.561996 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4112 13:27:14.564896 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4113 13:27:14.565478 ==
4114 13:27:14.568054 Dram Type= 6, Freq= 0, CH_0, rank 1
4115 13:27:14.571539 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4116 13:27:14.574587 ==
4117 13:27:14.575013 DQS Delay:
4118 13:27:14.575343 DQS0 = 0, DQS1 = 0
4119 13:27:14.577735 DQM Delay:
4120 13:27:14.578176 DQM0 = 41, DQM1 = 32
4121 13:27:14.581622 DQ Delay:
4122 13:27:14.584439 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4123 13:27:14.584870 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4124 13:27:14.588021 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4125 13:27:14.591235 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4126 13:27:14.594540
4127 13:27:14.594964
4128 13:27:14.595295 ==
4129 13:27:14.598688 Dram Type= 6, Freq= 0, CH_0, rank 1
4130 13:27:14.601079 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4131 13:27:14.601546 ==
4132 13:27:14.601883
4133 13:27:14.602190
4134 13:27:14.604560 TX Vref Scan disable
4135 13:27:14.604989 == TX Byte 0 ==
4136 13:27:14.611299 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4137 13:27:14.614560 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4138 13:27:14.614994 == TX Byte 1 ==
4139 13:27:14.621335 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4140 13:27:14.624113 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4141 13:27:14.624746 ==
4142 13:27:14.627493 Dram Type= 6, Freq= 0, CH_0, rank 1
4143 13:27:14.631168 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4144 13:27:14.631602 ==
4145 13:27:14.631936
4146 13:27:14.634070
4147 13:27:14.634496 TX Vref Scan disable
4148 13:27:14.637179 == TX Byte 0 ==
4149 13:27:14.640880 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4150 13:27:14.647249 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4151 13:27:14.647682 == TX Byte 1 ==
4152 13:27:14.651167 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4153 13:27:14.656986 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4154 13:27:14.657463
4155 13:27:14.657800 [DATLAT]
4156 13:27:14.658104 Freq=600, CH0 RK1
4157 13:27:14.658399
4158 13:27:14.660657 DATLAT Default: 0x8
4159 13:27:14.661086 0, 0xFFFF, sum = 0
4160 13:27:14.663635 1, 0xFFFF, sum = 0
4161 13:27:14.667811 2, 0xFFFF, sum = 0
4162 13:27:14.668336 3, 0xFFFF, sum = 0
4163 13:27:14.670252 4, 0xFFFF, sum = 0
4164 13:27:14.670686 5, 0xFFFF, sum = 0
4165 13:27:14.673631 6, 0xFFFF, sum = 0
4166 13:27:14.674067 7, 0x0, sum = 1
4167 13:27:14.674410 8, 0x0, sum = 2
4168 13:27:14.677215 9, 0x0, sum = 3
4169 13:27:14.677684 10, 0x0, sum = 4
4170 13:27:14.680409 best_step = 8
4171 13:27:14.680863
4172 13:27:14.681195 ==
4173 13:27:14.683605 Dram Type= 6, Freq= 0, CH_0, rank 1
4174 13:27:14.687318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4175 13:27:14.687829 ==
4176 13:27:14.690337 RX Vref Scan: 0
4177 13:27:14.690765
4178 13:27:14.691098 RX Vref 0 -> 0, step: 1
4179 13:27:14.691406
4180 13:27:14.693283 RX Delay -179 -> 252, step: 8
4181 13:27:14.700966 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4182 13:27:14.704280 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4183 13:27:14.707376 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4184 13:27:14.711612 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4185 13:27:14.717327 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4186 13:27:14.720935 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4187 13:27:14.724814 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4188 13:27:14.727775 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4189 13:27:14.734312 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4190 13:27:14.737284 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4191 13:27:14.740539 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4192 13:27:14.744252 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4193 13:27:14.747416 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4194 13:27:14.754184 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4195 13:27:14.757451 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4196 13:27:14.760531 iDelay=205, Bit 15, Center 40 (-107 ~ 188) 296
4197 13:27:14.761037 ==
4198 13:27:14.764110 Dram Type= 6, Freq= 0, CH_0, rank 1
4199 13:27:14.770840 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4200 13:27:14.771348 ==
4201 13:27:14.771685 DQS Delay:
4202 13:27:14.773736 DQS0 = 0, DQS1 = 0
4203 13:27:14.774241 DQM Delay:
4204 13:27:14.774578 DQM0 = 41, DQM1 = 31
4205 13:27:14.777152 DQ Delay:
4206 13:27:14.780634 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4207 13:27:14.783757 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4208 13:27:14.787294 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4209 13:27:14.790087 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4210 13:27:14.790519
4211 13:27:14.790848
4212 13:27:14.796833 [DQSOSCAuto] RK1, (LSB)MR18= 0x7070, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4213 13:27:14.800580 CH0 RK1: MR19=808, MR18=7070
4214 13:27:14.806579 CH0_RK1: MR19=0x808, MR18=0x7070, DQSOSC=388, MR23=63, INC=174, DEC=116
4215 13:27:14.810283 [RxdqsGatingPostProcess] freq 600
4216 13:27:14.813450 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4217 13:27:14.817443 Pre-setting of DQS Precalculation
4218 13:27:14.823659 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4219 13:27:14.824180 ==
4220 13:27:14.827213 Dram Type= 6, Freq= 0, CH_1, rank 0
4221 13:27:14.830543 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4222 13:27:14.831125 ==
4223 13:27:14.836761 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4224 13:27:14.843266 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4225 13:27:14.846375 [CA 0] Center 35 (5~66) winsize 62
4226 13:27:14.850033 [CA 1] Center 35 (5~66) winsize 62
4227 13:27:14.852936 [CA 2] Center 33 (3~64) winsize 62
4228 13:27:14.856739 [CA 3] Center 33 (3~64) winsize 62
4229 13:27:14.860386 [CA 4] Center 33 (2~64) winsize 63
4230 13:27:14.863316 [CA 5] Center 33 (2~64) winsize 63
4231 13:27:14.863823
4232 13:27:14.866710 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4233 13:27:14.867216
4234 13:27:14.869834 [CATrainingPosCal] consider 1 rank data
4235 13:27:14.872959 u2DelayCellTimex100 = 270/100 ps
4236 13:27:14.877188 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4237 13:27:14.879762 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4238 13:27:14.883380 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4239 13:27:14.886009 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4240 13:27:14.889614 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4241 13:27:14.892917 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4242 13:27:14.893416
4243 13:27:14.896003 CA PerBit enable=1, Macro0, CA PI delay=33
4244 13:27:14.900537
4245 13:27:14.901040 [CBTSetCACLKResult] CA Dly = 33
4246 13:27:14.902957 CS Dly: 4 (0~35)
4247 13:27:14.903384 ==
4248 13:27:14.906046 Dram Type= 6, Freq= 0, CH_1, rank 1
4249 13:27:14.909352 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4250 13:27:14.909787 ==
4251 13:27:14.916138 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4252 13:27:14.922558 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4253 13:27:14.925913 [CA 0] Center 34 (4~65) winsize 62
4254 13:27:14.929622 [CA 1] Center 34 (4~65) winsize 62
4255 13:27:14.932486 [CA 2] Center 33 (3~64) winsize 62
4256 13:27:14.936348 [CA 3] Center 33 (3~64) winsize 62
4257 13:27:14.940164 [CA 4] Center 32 (2~63) winsize 62
4258 13:27:14.942797 [CA 5] Center 32 (2~63) winsize 62
4259 13:27:14.943362
4260 13:27:14.946083 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4261 13:27:14.946583
4262 13:27:14.949300 [CATrainingPosCal] consider 2 rank data
4263 13:27:14.952130 u2DelayCellTimex100 = 270/100 ps
4264 13:27:14.955661 CA0 delay=35 (5~65),Diff = 3 PI (28 cell)
4265 13:27:14.959176 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4266 13:27:14.962309 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4267 13:27:14.965994 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4268 13:27:14.969365 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4269 13:27:14.972320 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4270 13:27:14.975669
4271 13:27:14.978877 CA PerBit enable=1, Macro0, CA PI delay=32
4272 13:27:14.979324
4273 13:27:14.982496 [CBTSetCACLKResult] CA Dly = 32
4274 13:27:14.983002 CS Dly: 4 (0~36)
4275 13:27:14.983422
4276 13:27:14.985275 ----->DramcWriteLeveling(PI) begin...
4277 13:27:14.985735 ==
4278 13:27:14.989055 Dram Type= 6, Freq= 0, CH_1, rank 0
4279 13:27:14.991959 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4280 13:27:14.995341 ==
4281 13:27:14.998864 Write leveling (Byte 0): 30 => 30
4282 13:27:14.999295 Write leveling (Byte 1): 29 => 29
4283 13:27:15.002357 DramcWriteLeveling(PI) end<-----
4284 13:27:15.002793
4285 13:27:15.003126 ==
4286 13:27:15.004952 Dram Type= 6, Freq= 0, CH_1, rank 0
4287 13:27:15.012430 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4288 13:27:15.013305 ==
4289 13:27:15.015352 [Gating] SW mode calibration
4290 13:27:15.021641 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4291 13:27:15.024814 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4292 13:27:15.031657 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4293 13:27:15.035290 0 5 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 1)
4294 13:27:15.038058 0 5 8 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
4295 13:27:15.044618 0 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4296 13:27:15.048418 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4297 13:27:15.051674 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4298 13:27:15.058571 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4299 13:27:15.061429 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4300 13:27:15.064591 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4301 13:27:15.071426 0 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4302 13:27:15.074314 0 6 8 | B1->B0 | 3636 3e3e | 0 0 | (0 0) (0 0)
4303 13:27:15.077778 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4304 13:27:15.084605 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4305 13:27:15.088019 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4306 13:27:15.090813 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4307 13:27:15.097852 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4308 13:27:15.101290 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4309 13:27:15.104246 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4310 13:27:15.111260 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4311 13:27:15.114245 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 13:27:15.117326 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 13:27:15.120819 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 13:27:15.127260 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 13:27:15.130780 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 13:27:15.133859 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 13:27:15.141369 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 13:27:15.144291 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4319 13:27:15.147584 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4320 13:27:15.154219 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4321 13:27:15.157597 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4322 13:27:15.161310 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4323 13:27:15.167468 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4324 13:27:15.170873 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4325 13:27:15.173967 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4326 13:27:15.180456 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4327 13:27:15.183947 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4328 13:27:15.187731 Total UI for P1: 0, mck2ui 16
4329 13:27:15.190753 best dqsien dly found for B0: ( 0, 9, 8)
4330 13:27:15.194499 Total UI for P1: 0, mck2ui 16
4331 13:27:15.197159 best dqsien dly found for B1: ( 0, 9, 8)
4332 13:27:15.201427 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4333 13:27:15.203874 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4334 13:27:15.204302
4335 13:27:15.207544 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4336 13:27:15.211073 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4337 13:27:15.213826 [Gating] SW calibration Done
4338 13:27:15.214254 ==
4339 13:27:15.217559 Dram Type= 6, Freq= 0, CH_1, rank 0
4340 13:27:15.220964 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4341 13:27:15.223686 ==
4342 13:27:15.224117 RX Vref Scan: 0
4343 13:27:15.224449
4344 13:27:15.227305 RX Vref 0 -> 0, step: 1
4345 13:27:15.227812
4346 13:27:15.230020 RX Delay -230 -> 252, step: 16
4347 13:27:15.233446 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4348 13:27:15.237209 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4349 13:27:15.240130 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4350 13:27:15.246853 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4351 13:27:15.250052 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4352 13:27:15.254100 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4353 13:27:15.256744 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4354 13:27:15.260494 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4355 13:27:15.267138 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4356 13:27:15.270172 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4357 13:27:15.273610 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4358 13:27:15.276946 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4359 13:27:15.284049 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4360 13:27:15.286595 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4361 13:27:15.289770 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4362 13:27:15.292727 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4363 13:27:15.292803 ==
4364 13:27:15.296222 Dram Type= 6, Freq= 0, CH_1, rank 0
4365 13:27:15.303054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4366 13:27:15.303130 ==
4367 13:27:15.303189 DQS Delay:
4368 13:27:15.306407 DQS0 = 0, DQS1 = 0
4369 13:27:15.306482 DQM Delay:
4370 13:27:15.306540 DQM0 = 39, DQM1 = 32
4371 13:27:15.309237 DQ Delay:
4372 13:27:15.313017 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4373 13:27:15.315811 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4374 13:27:15.319443 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4375 13:27:15.322898 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4376 13:27:15.322973
4377 13:27:15.323031
4378 13:27:15.323084 ==
4379 13:27:15.325858 Dram Type= 6, Freq= 0, CH_1, rank 0
4380 13:27:15.329507 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4381 13:27:15.329582 ==
4382 13:27:15.329640
4383 13:27:15.329692
4384 13:27:15.332519 TX Vref Scan disable
4385 13:27:15.336083 == TX Byte 0 ==
4386 13:27:15.338978 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4387 13:27:15.342414 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4388 13:27:15.345874 == TX Byte 1 ==
4389 13:27:15.348999 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4390 13:27:15.352906 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4391 13:27:15.352980 ==
4392 13:27:15.356079 Dram Type= 6, Freq= 0, CH_1, rank 0
4393 13:27:15.359372 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4394 13:27:15.359447 ==
4395 13:27:15.362479
4396 13:27:15.362552
4397 13:27:15.362609 TX Vref Scan disable
4398 13:27:15.365980 == TX Byte 0 ==
4399 13:27:15.369591 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4400 13:27:15.376206 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4401 13:27:15.376281 == TX Byte 1 ==
4402 13:27:15.379175 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4403 13:27:15.386072 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4404 13:27:15.386146
4405 13:27:15.386203 [DATLAT]
4406 13:27:15.386256 Freq=600, CH1 RK0
4407 13:27:15.386307
4408 13:27:15.389882 DATLAT Default: 0x9
4409 13:27:15.389957 0, 0xFFFF, sum = 0
4410 13:27:15.392914 1, 0xFFFF, sum = 0
4411 13:27:15.392990 2, 0xFFFF, sum = 0
4412 13:27:15.396397 3, 0xFFFF, sum = 0
4413 13:27:15.396472 4, 0xFFFF, sum = 0
4414 13:27:15.399473 5, 0xFFFF, sum = 0
4415 13:27:15.402917 6, 0xFFFF, sum = 0
4416 13:27:15.402993 7, 0x0, sum = 1
4417 13:27:15.403051 8, 0x0, sum = 2
4418 13:27:15.406092 9, 0x0, sum = 3
4419 13:27:15.406168 10, 0x0, sum = 4
4420 13:27:15.409484 best_step = 8
4421 13:27:15.409558
4422 13:27:15.409614 ==
4423 13:27:15.412853 Dram Type= 6, Freq= 0, CH_1, rank 0
4424 13:27:15.416306 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4425 13:27:15.416381 ==
4426 13:27:15.419304 RX Vref Scan: 1
4427 13:27:15.419378
4428 13:27:15.419436 RX Vref 0 -> 0, step: 1
4429 13:27:15.419489
4430 13:27:15.423273 RX Delay -195 -> 252, step: 8
4431 13:27:15.423347
4432 13:27:15.426129 Set Vref, RX VrefLevel [Byte0]: 54
4433 13:27:15.429062 [Byte1]: 50
4434 13:27:15.432987
4435 13:27:15.433064 Final RX Vref Byte 0 = 54 to rank0
4436 13:27:15.436767 Final RX Vref Byte 1 = 50 to rank0
4437 13:27:15.439967 Final RX Vref Byte 0 = 54 to rank1
4438 13:27:15.443665 Final RX Vref Byte 1 = 50 to rank1==
4439 13:27:15.446282 Dram Type= 6, Freq= 0, CH_1, rank 0
4440 13:27:15.452680 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4441 13:27:15.452755 ==
4442 13:27:15.452813 DQS Delay:
4443 13:27:15.456015 DQS0 = 0, DQS1 = 0
4444 13:27:15.456087 DQM Delay:
4445 13:27:15.456144 DQM0 = 37, DQM1 = 31
4446 13:27:15.459811 DQ Delay:
4447 13:27:15.462545 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4448 13:27:15.466384 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4449 13:27:15.469486 DQ8 =12, DQ9 =20, DQ10 =36, DQ11 =24
4450 13:27:15.473168 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
4451 13:27:15.473269
4452 13:27:15.473329
4453 13:27:15.479508 [DQSOSCAuto] RK0, (LSB)MR18= 0x7a7a, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4454 13:27:15.483176 CH1 RK0: MR19=808, MR18=7A7A
4455 13:27:15.489520 CH1_RK0: MR19=0x808, MR18=0x7A7A, DQSOSC=387, MR23=63, INC=175, DEC=116
4456 13:27:15.489613
4457 13:27:15.492871 ----->DramcWriteLeveling(PI) begin...
4458 13:27:15.492947 ==
4459 13:27:15.495825 Dram Type= 6, Freq= 0, CH_1, rank 1
4460 13:27:15.499212 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4461 13:27:15.499287 ==
4462 13:27:15.502521 Write leveling (Byte 0): 28 => 28
4463 13:27:15.505858 Write leveling (Byte 1): 28 => 28
4464 13:27:15.509245 DramcWriteLeveling(PI) end<-----
4465 13:27:15.509321
4466 13:27:15.509380 ==
4467 13:27:15.512272 Dram Type= 6, Freq= 0, CH_1, rank 1
4468 13:27:15.515605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4469 13:27:15.519317 ==
4470 13:27:15.519391 [Gating] SW mode calibration
4471 13:27:15.525752 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4472 13:27:15.532503 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4473 13:27:15.535966 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 13:27:15.542289 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
4475 13:27:15.545764 0 5 8 | B1->B0 | 3030 2424 | 0 1 | (0 1) (0 0)
4476 13:27:15.549215 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 13:27:15.555578 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 13:27:15.559285 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 13:27:15.561909 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 13:27:15.569032 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 13:27:15.571972 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 13:27:15.575812 0 6 4 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
4483 13:27:15.581860 0 6 8 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
4484 13:27:15.585696 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 13:27:15.588392 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 13:27:15.595320 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 13:27:15.598916 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 13:27:15.601797 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 13:27:15.608661 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4490 13:27:15.611634 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4491 13:27:15.615003 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 13:27:15.621536 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 13:27:15.625103 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 13:27:15.628485 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 13:27:15.635005 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 13:27:15.638378 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 13:27:15.641842 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 13:27:15.648723 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 13:27:15.651996 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 13:27:15.655604 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 13:27:15.661909 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 13:27:15.665378 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 13:27:15.668302 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 13:27:15.675216 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 13:27:15.678624 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4506 13:27:15.681270 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4507 13:27:15.687950 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 13:27:15.688435 Total UI for P1: 0, mck2ui 16
4509 13:27:15.694439 best dqsien dly found for B0: ( 0, 9, 2)
4510 13:27:15.694863 Total UI for P1: 0, mck2ui 16
4511 13:27:15.698090 best dqsien dly found for B1: ( 0, 9, 6)
4512 13:27:15.704426 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4513 13:27:15.708081 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4514 13:27:15.708584
4515 13:27:15.711189 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4516 13:27:15.714483 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4517 13:27:15.718911 [Gating] SW calibration Done
4518 13:27:15.719552 ==
4519 13:27:15.720911 Dram Type= 6, Freq= 0, CH_1, rank 1
4520 13:27:15.724623 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4521 13:27:15.725050 ==
4522 13:27:15.727827 RX Vref Scan: 0
4523 13:27:15.728248
4524 13:27:15.728580 RX Vref 0 -> 0, step: 1
4525 13:27:15.728883
4526 13:27:15.731414 RX Delay -230 -> 252, step: 16
4527 13:27:15.734162 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4528 13:27:15.740846 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4529 13:27:15.743995 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4530 13:27:15.746913 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4531 13:27:15.750480 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4532 13:27:15.756981 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4533 13:27:15.760648 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4534 13:27:15.763775 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4535 13:27:15.767010 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4536 13:27:15.770324 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4537 13:27:15.777187 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4538 13:27:15.780088 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4539 13:27:15.783384 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4540 13:27:15.787011 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4541 13:27:15.793189 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4542 13:27:15.797004 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4543 13:27:15.797482 ==
4544 13:27:15.800619 Dram Type= 6, Freq= 0, CH_1, rank 1
4545 13:27:15.803484 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4546 13:27:15.803910 ==
4547 13:27:15.807226 DQS Delay:
4548 13:27:15.807671 DQS0 = 0, DQS1 = 0
4549 13:27:15.810298 DQM Delay:
4550 13:27:15.810731 DQM0 = 40, DQM1 = 35
4551 13:27:15.811063 DQ Delay:
4552 13:27:15.813566 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4553 13:27:15.816798 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4554 13:27:15.820338 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4555 13:27:15.823278 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4556 13:27:15.823748
4557 13:27:15.824201
4558 13:27:15.824649 ==
4559 13:27:15.826671 Dram Type= 6, Freq= 0, CH_1, rank 1
4560 13:27:15.833397 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4561 13:27:15.833900 ==
4562 13:27:15.834245
4563 13:27:15.834549
4564 13:27:15.837215 TX Vref Scan disable
4565 13:27:15.837829 == TX Byte 0 ==
4566 13:27:15.840392 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4567 13:27:15.847426 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4568 13:27:15.847851 == TX Byte 1 ==
4569 13:27:15.850175 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4570 13:27:15.856464 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4571 13:27:15.856887 ==
4572 13:27:15.860072 Dram Type= 6, Freq= 0, CH_1, rank 1
4573 13:27:15.863013 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4574 13:27:15.863438 ==
4575 13:27:15.863764
4576 13:27:15.864070
4577 13:27:15.866510 TX Vref Scan disable
4578 13:27:15.869830 == TX Byte 0 ==
4579 13:27:15.873257 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4580 13:27:15.876092 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4581 13:27:15.879510 == TX Byte 1 ==
4582 13:27:15.882946 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4583 13:27:15.886210 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4584 13:27:15.886596
4585 13:27:15.889581 [DATLAT]
4586 13:27:15.889962 Freq=600, CH1 RK1
4587 13:27:15.890262
4588 13:27:15.892542 DATLAT Default: 0x8
4589 13:27:15.892924 0, 0xFFFF, sum = 0
4590 13:27:15.895949 1, 0xFFFF, sum = 0
4591 13:27:15.896337 2, 0xFFFF, sum = 0
4592 13:27:15.899184 3, 0xFFFF, sum = 0
4593 13:27:15.899581 4, 0xFFFF, sum = 0
4594 13:27:15.902714 5, 0xFFFF, sum = 0
4595 13:27:15.903104 6, 0xFFFF, sum = 0
4596 13:27:15.906105 7, 0x0, sum = 1
4597 13:27:15.906496 8, 0x0, sum = 2
4598 13:27:15.909053 9, 0x0, sum = 3
4599 13:27:15.909480 10, 0x0, sum = 4
4600 13:27:15.912377 best_step = 8
4601 13:27:15.912761
4602 13:27:15.913064 ==
4603 13:27:15.915601 Dram Type= 6, Freq= 0, CH_1, rank 1
4604 13:27:15.919419 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4605 13:27:15.919806 ==
4606 13:27:15.922278 RX Vref Scan: 0
4607 13:27:15.922663
4608 13:27:15.922959 RX Vref 0 -> 0, step: 1
4609 13:27:15.923233
4610 13:27:15.925736 RX Delay -195 -> 252, step: 8
4611 13:27:15.933056 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4612 13:27:15.936187 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4613 13:27:15.939046 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4614 13:27:15.942671 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4615 13:27:15.948835 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4616 13:27:15.952400 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4617 13:27:15.955563 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4618 13:27:15.959417 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4619 13:27:15.965619 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4620 13:27:15.969078 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4621 13:27:15.972283 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4622 13:27:15.975650 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4623 13:27:15.981971 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4624 13:27:15.985269 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4625 13:27:15.988849 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4626 13:27:15.992076 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4627 13:27:15.992461 ==
4628 13:27:15.995024 Dram Type= 6, Freq= 0, CH_1, rank 1
4629 13:27:16.001767 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4630 13:27:16.002170 ==
4631 13:27:16.002473 DQS Delay:
4632 13:27:16.005005 DQS0 = 0, DQS1 = 0
4633 13:27:16.005437 DQM Delay:
4634 13:27:16.005742 DQM0 = 37, DQM1 = 29
4635 13:27:16.008158 DQ Delay:
4636 13:27:16.011566 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4637 13:27:16.015009 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4638 13:27:16.018791 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4639 13:27:16.021530 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4640 13:27:16.021916
4641 13:27:16.022213
4642 13:27:16.027996 [DQSOSCAuto] RK1, (LSB)MR18= 0x6161, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4643 13:27:16.031418 CH1 RK1: MR19=808, MR18=6161
4644 13:27:16.039008 CH1_RK1: MR19=0x808, MR18=0x6161, DQSOSC=391, MR23=63, INC=171, DEC=114
4645 13:27:16.041333 [RxdqsGatingPostProcess] freq 600
4646 13:27:16.047913 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4647 13:27:16.048344 Pre-setting of DQS Precalculation
4648 13:27:16.054877 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4649 13:27:16.061024 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4650 13:27:16.067705 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4651 13:27:16.068136
4652 13:27:16.068464
4653 13:27:16.071308 [Calibration Summary] 1200 Mbps
4654 13:27:16.074309 CH 0, Rank 0
4655 13:27:16.074733 SW Impedance : PASS
4656 13:27:16.077573 DUTY Scan : NO K
4657 13:27:16.081136 ZQ Calibration : PASS
4658 13:27:16.081577 Jitter Meter : NO K
4659 13:27:16.084368 CBT Training : PASS
4660 13:27:16.087268 Write leveling : PASS
4661 13:27:16.087652 RX DQS gating : PASS
4662 13:27:16.091069 RX DQ/DQS(RDDQC) : PASS
4663 13:27:16.091456 TX DQ/DQS : PASS
4664 13:27:16.093944 RX DATLAT : PASS
4665 13:27:16.097387 RX DQ/DQS(Engine): PASS
4666 13:27:16.097776 TX OE : NO K
4667 13:27:16.100543 All Pass.
4668 13:27:16.100922
4669 13:27:16.101218 CH 0, Rank 1
4670 13:27:16.103845 SW Impedance : PASS
4671 13:27:16.104228 DUTY Scan : NO K
4672 13:27:16.107610 ZQ Calibration : PASS
4673 13:27:16.110849 Jitter Meter : NO K
4674 13:27:16.111233 CBT Training : PASS
4675 13:27:16.113795 Write leveling : PASS
4676 13:27:16.117578 RX DQS gating : PASS
4677 13:27:16.117963 RX DQ/DQS(RDDQC) : PASS
4678 13:27:16.120295 TX DQ/DQS : PASS
4679 13:27:16.123698 RX DATLAT : PASS
4680 13:27:16.124084 RX DQ/DQS(Engine): PASS
4681 13:27:16.127248 TX OE : NO K
4682 13:27:16.127636 All Pass.
4683 13:27:16.127938
4684 13:27:16.130011 CH 1, Rank 0
4685 13:27:16.130395 SW Impedance : PASS
4686 13:27:16.133912 DUTY Scan : NO K
4687 13:27:16.137160 ZQ Calibration : PASS
4688 13:27:16.137579 Jitter Meter : NO K
4689 13:27:16.140173 CBT Training : PASS
4690 13:27:16.143745 Write leveling : PASS
4691 13:27:16.144132 RX DQS gating : PASS
4692 13:27:16.146492 RX DQ/DQS(RDDQC) : PASS
4693 13:27:16.150067 TX DQ/DQS : PASS
4694 13:27:16.150454 RX DATLAT : PASS
4695 13:27:16.153917 RX DQ/DQS(Engine): PASS
4696 13:27:16.156460 TX OE : NO K
4697 13:27:16.156845 All Pass.
4698 13:27:16.157158
4699 13:27:16.157501 CH 1, Rank 1
4700 13:27:16.159953 SW Impedance : PASS
4701 13:27:16.163294 DUTY Scan : NO K
4702 13:27:16.163683 ZQ Calibration : PASS
4703 13:27:16.167280 Jitter Meter : NO K
4704 13:27:16.167664 CBT Training : PASS
4705 13:27:16.170067 Write leveling : PASS
4706 13:27:16.173538 RX DQS gating : PASS
4707 13:27:16.173926 RX DQ/DQS(RDDQC) : PASS
4708 13:27:16.176377 TX DQ/DQS : PASS
4709 13:27:16.179824 RX DATLAT : PASS
4710 13:27:16.180210 RX DQ/DQS(Engine): PASS
4711 13:27:16.183300 TX OE : NO K
4712 13:27:16.183688 All Pass.
4713 13:27:16.183986
4714 13:27:16.186432 DramC Write-DBI off
4715 13:27:16.190004 PER_BANK_REFRESH: Hybrid Mode
4716 13:27:16.190386 TX_TRACKING: ON
4717 13:27:16.200177 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4718 13:27:16.203121 [FAST_K] Save calibration result to emmc
4719 13:27:16.206325 dramc_set_vcore_voltage set vcore to 662500
4720 13:27:16.209706 Read voltage for 933, 3
4721 13:27:16.210092 Vio18 = 0
4722 13:27:16.210388 Vcore = 662500
4723 13:27:16.213142 Vdram = 0
4724 13:27:16.213573 Vddq = 0
4725 13:27:16.213877 Vmddr = 0
4726 13:27:16.220006 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4727 13:27:16.222758 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4728 13:27:16.226188 MEM_TYPE=3, freq_sel=17
4729 13:27:16.229806 sv_algorithm_assistance_LP4_1600
4730 13:27:16.233090 ============ PULL DRAM RESETB DOWN ============
4731 13:27:16.236175 ========== PULL DRAM RESETB DOWN end =========
4732 13:27:16.242684 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4733 13:27:16.245843 ===================================
4734 13:27:16.249368 LPDDR4 DRAM CONFIGURATION
4735 13:27:16.253134 ===================================
4736 13:27:16.253847 EX_ROW_EN[0] = 0x0
4737 13:27:16.256309 EX_ROW_EN[1] = 0x0
4738 13:27:16.256693 LP4Y_EN = 0x0
4739 13:27:16.259760 WORK_FSP = 0x0
4740 13:27:16.260244 WL = 0x3
4741 13:27:16.262644 RL = 0x3
4742 13:27:16.263042 BL = 0x2
4743 13:27:16.266190 RPST = 0x0
4744 13:27:16.266576 RD_PRE = 0x0
4745 13:27:16.269558 WR_PRE = 0x1
4746 13:27:16.269942 WR_PST = 0x0
4747 13:27:16.273059 DBI_WR = 0x0
4748 13:27:16.273490 DBI_RD = 0x0
4749 13:27:16.276135 OTF = 0x1
4750 13:27:16.279756 ===================================
4751 13:27:16.282497 ===================================
4752 13:27:16.282886 ANA top config
4753 13:27:16.286001 ===================================
4754 13:27:16.289320 DLL_ASYNC_EN = 0
4755 13:27:16.292891 ALL_SLAVE_EN = 1
4756 13:27:16.295924 NEW_RANK_MODE = 1
4757 13:27:16.296336 DLL_IDLE_MODE = 1
4758 13:27:16.299143 LP45_APHY_COMB_EN = 1
4759 13:27:16.302417 TX_ODT_DIS = 1
4760 13:27:16.305992 NEW_8X_MODE = 1
4761 13:27:16.308749 ===================================
4762 13:27:16.312719 ===================================
4763 13:27:16.315645 data_rate = 1866
4764 13:27:16.319161 CKR = 1
4765 13:27:16.319639 DQ_P2S_RATIO = 8
4766 13:27:16.322509 ===================================
4767 13:27:16.325623 CA_P2S_RATIO = 8
4768 13:27:16.328900 DQ_CA_OPEN = 0
4769 13:27:16.331963 DQ_SEMI_OPEN = 0
4770 13:27:16.335801 CA_SEMI_OPEN = 0
4771 13:27:16.338568 CA_FULL_RATE = 0
4772 13:27:16.339059 DQ_CKDIV4_EN = 1
4773 13:27:16.342237 CA_CKDIV4_EN = 1
4774 13:27:16.345823 CA_PREDIV_EN = 0
4775 13:27:16.349062 PH8_DLY = 0
4776 13:27:16.352558 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4777 13:27:16.355600 DQ_AAMCK_DIV = 4
4778 13:27:16.356167 CA_AAMCK_DIV = 4
4779 13:27:16.358906 CA_ADMCK_DIV = 4
4780 13:27:16.362434 DQ_TRACK_CA_EN = 0
4781 13:27:16.365190 CA_PICK = 933
4782 13:27:16.368810 CA_MCKIO = 933
4783 13:27:16.372263 MCKIO_SEMI = 0
4784 13:27:16.375573 PLL_FREQ = 3732
4785 13:27:16.375992 DQ_UI_PI_RATIO = 32
4786 13:27:16.379210 CA_UI_PI_RATIO = 0
4787 13:27:16.381891 ===================================
4788 13:27:16.385899 ===================================
4789 13:27:16.388739 memory_type:LPDDR4
4790 13:27:16.392006 GP_NUM : 10
4791 13:27:16.392397 SRAM_EN : 1
4792 13:27:16.395484 MD32_EN : 0
4793 13:27:16.398414 ===================================
4794 13:27:16.398768 [ANA_INIT] >>>>>>>>>>>>>>
4795 13:27:16.401897 <<<<<< [CONFIGURE PHASE]: ANA_TX
4796 13:27:16.405449 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4797 13:27:16.409155 ===================================
4798 13:27:16.411624 data_rate = 1866,PCW = 0X8f00
4799 13:27:16.415521 ===================================
4800 13:27:16.418603 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4801 13:27:16.425259 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4802 13:27:16.432040 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4803 13:27:16.435255 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4804 13:27:16.438874 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4805 13:27:16.442997 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4806 13:27:16.445667 [ANA_INIT] flow start
4807 13:27:16.446131 [ANA_INIT] PLL >>>>>>>>
4808 13:27:16.448337 [ANA_INIT] PLL <<<<<<<<
4809 13:27:16.452072 [ANA_INIT] MIDPI >>>>>>>>
4810 13:27:16.452577 [ANA_INIT] MIDPI <<<<<<<<
4811 13:27:16.454811 [ANA_INIT] DLL >>>>>>>>
4812 13:27:16.458260 [ANA_INIT] flow end
4813 13:27:16.461660 ============ LP4 DIFF to SE enter ============
4814 13:27:16.464774 ============ LP4 DIFF to SE exit ============
4815 13:27:16.468677 [ANA_INIT] <<<<<<<<<<<<<
4816 13:27:16.471452 [Flow] Enable top DCM control >>>>>
4817 13:27:16.475200 [Flow] Enable top DCM control <<<<<
4818 13:27:16.477890 Enable DLL master slave shuffle
4819 13:27:16.481401 ==============================================================
4820 13:27:16.484837 Gating Mode config
4821 13:27:16.491286 ==============================================================
4822 13:27:16.491807 Config description:
4823 13:27:16.501340 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4824 13:27:16.508383 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4825 13:27:16.515027 SELPH_MODE 0: By rank 1: By Phase
4826 13:27:16.517551 ==============================================================
4827 13:27:16.520853 GAT_TRACK_EN = 1
4828 13:27:16.524083 RX_GATING_MODE = 2
4829 13:27:16.527555 RX_GATING_TRACK_MODE = 2
4830 13:27:16.531197 SELPH_MODE = 1
4831 13:27:16.534551 PICG_EARLY_EN = 1
4832 13:27:16.538043 VALID_LAT_VALUE = 1
4833 13:27:16.540838 ==============================================================
4834 13:27:16.544046 Enter into Gating configuration >>>>
4835 13:27:16.547626 Exit from Gating configuration <<<<
4836 13:27:16.551208 Enter into DVFS_PRE_config >>>>>
4837 13:27:16.564380 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4838 13:27:16.567342 Exit from DVFS_PRE_config <<<<<
4839 13:27:16.571053 Enter into PICG configuration >>>>
4840 13:27:16.571443 Exit from PICG configuration <<<<
4841 13:27:16.574215 [RX_INPUT] configuration >>>>>
4842 13:27:16.577766 [RX_INPUT] configuration <<<<<
4843 13:27:16.584145 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4844 13:27:16.587578 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4845 13:27:16.594041 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4846 13:27:16.600644 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4847 13:27:16.607377 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4848 13:27:16.614201 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4849 13:27:16.617681 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4850 13:27:16.620657 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4851 13:27:16.624240 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4852 13:27:16.630864 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4853 13:27:16.633702 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4854 13:27:16.637352 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4855 13:27:16.640417 ===================================
4856 13:27:16.643493 LPDDR4 DRAM CONFIGURATION
4857 13:27:16.646926 ===================================
4858 13:27:16.650015 EX_ROW_EN[0] = 0x0
4859 13:27:16.650439 EX_ROW_EN[1] = 0x0
4860 13:27:16.653403 LP4Y_EN = 0x0
4861 13:27:16.653862 WORK_FSP = 0x0
4862 13:27:16.657084 WL = 0x3
4863 13:27:16.657630 RL = 0x3
4864 13:27:16.661311 BL = 0x2
4865 13:27:16.661736 RPST = 0x0
4866 13:27:16.663741 RD_PRE = 0x0
4867 13:27:16.664236 WR_PRE = 0x1
4868 13:27:16.666943 WR_PST = 0x0
4869 13:27:16.667371 DBI_WR = 0x0
4870 13:27:16.670185 DBI_RD = 0x0
4871 13:27:16.673664 OTF = 0x1
4872 13:27:16.674089 ===================================
4873 13:27:16.679806 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4874 13:27:16.683259 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4875 13:27:16.686987 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4876 13:27:16.689800 ===================================
4877 13:27:16.693424 LPDDR4 DRAM CONFIGURATION
4878 13:27:16.696355 ===================================
4879 13:27:16.699924 EX_ROW_EN[0] = 0x10
4880 13:27:16.700446 EX_ROW_EN[1] = 0x0
4881 13:27:16.703858 LP4Y_EN = 0x0
4882 13:27:16.704433 WORK_FSP = 0x0
4883 13:27:16.706572 WL = 0x3
4884 13:27:16.707172 RL = 0x3
4885 13:27:16.709586 BL = 0x2
4886 13:27:16.710062 RPST = 0x0
4887 13:27:16.713475 RD_PRE = 0x0
4888 13:27:16.713885 WR_PRE = 0x1
4889 13:27:16.716292 WR_PST = 0x0
4890 13:27:16.716709 DBI_WR = 0x0
4891 13:27:16.719395 DBI_RD = 0x0
4892 13:27:16.722886 OTF = 0x1
4893 13:27:16.726421 ===================================
4894 13:27:16.729696 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4895 13:27:16.734791 nWR fixed to 30
4896 13:27:16.737993 [ModeRegInit_LP4] CH0 RK0
4897 13:27:16.738382 [ModeRegInit_LP4] CH0 RK1
4898 13:27:16.741051 [ModeRegInit_LP4] CH1 RK0
4899 13:27:16.745048 [ModeRegInit_LP4] CH1 RK1
4900 13:27:16.745478 match AC timing 8
4901 13:27:16.751251 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4902 13:27:16.754961 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4903 13:27:16.757918 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4904 13:27:16.764536 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4905 13:27:16.767592 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4906 13:27:16.768097 ==
4907 13:27:16.771144 Dram Type= 6, Freq= 0, CH_0, rank 0
4908 13:27:16.774398 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4909 13:27:16.774830 ==
4910 13:27:16.781151 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4911 13:27:16.788021 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4912 13:27:16.791127 [CA 0] Center 38 (8~69) winsize 62
4913 13:27:16.793934 [CA 1] Center 38 (8~69) winsize 62
4914 13:27:16.797648 [CA 2] Center 36 (5~67) winsize 63
4915 13:27:16.800722 [CA 3] Center 35 (5~66) winsize 62
4916 13:27:16.804135 [CA 4] Center 34 (4~65) winsize 62
4917 13:27:16.807259 [CA 5] Center 34 (4~65) winsize 62
4918 13:27:16.807686
4919 13:27:16.810541 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4920 13:27:16.810971
4921 13:27:16.813944 [CATrainingPosCal] consider 1 rank data
4922 13:27:16.817413 u2DelayCellTimex100 = 270/100 ps
4923 13:27:16.820965 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4924 13:27:16.824142 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4925 13:27:16.827377 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4926 13:27:16.830751 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4927 13:27:16.837405 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4928 13:27:16.840397 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4929 13:27:16.840829
4930 13:27:16.843735 CA PerBit enable=1, Macro0, CA PI delay=34
4931 13:27:16.844167
4932 13:27:16.847490 [CBTSetCACLKResult] CA Dly = 34
4933 13:27:16.847996 CS Dly: 7 (0~38)
4934 13:27:16.848376 ==
4935 13:27:16.850511 Dram Type= 6, Freq= 0, CH_0, rank 1
4936 13:27:16.857074 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4937 13:27:16.857620 ==
4938 13:27:16.860206 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4939 13:27:16.866879 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4940 13:27:16.870859 [CA 0] Center 38 (8~69) winsize 62
4941 13:27:16.873343 [CA 1] Center 38 (8~69) winsize 62
4942 13:27:16.876864 [CA 2] Center 36 (5~67) winsize 63
4943 13:27:16.880075 [CA 3] Center 35 (5~66) winsize 62
4944 13:27:16.883146 [CA 4] Center 34 (4~64) winsize 61
4945 13:27:16.886787 [CA 5] Center 34 (4~65) winsize 62
4946 13:27:16.887291
4947 13:27:16.890260 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4948 13:27:16.890767
4949 13:27:16.893584 [CATrainingPosCal] consider 2 rank data
4950 13:27:16.897013 u2DelayCellTimex100 = 270/100 ps
4951 13:27:16.900239 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4952 13:27:16.903269 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4953 13:27:16.909691 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4954 13:27:16.913173 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4955 13:27:16.916488 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4956 13:27:16.919860 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4957 13:27:16.920365
4958 13:27:16.923125 CA PerBit enable=1, Macro0, CA PI delay=34
4959 13:27:16.923556
4960 13:27:16.926488 [CBTSetCACLKResult] CA Dly = 34
4961 13:27:16.926987 CS Dly: 7 (0~39)
4962 13:27:16.927323
4963 13:27:16.930156 ----->DramcWriteLeveling(PI) begin...
4964 13:27:16.932624 ==
4965 13:27:16.936237 Dram Type= 6, Freq= 0, CH_0, rank 0
4966 13:27:16.939767 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4967 13:27:16.940201 ==
4968 13:27:16.943224 Write leveling (Byte 0): 27 => 27
4969 13:27:16.946202 Write leveling (Byte 1): 27 => 27
4970 13:27:16.949483 DramcWriteLeveling(PI) end<-----
4971 13:27:16.949913
4972 13:27:16.950243 ==
4973 13:27:16.952480 Dram Type= 6, Freq= 0, CH_0, rank 0
4974 13:27:16.956364 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4975 13:27:16.956910 ==
4976 13:27:16.959766 [Gating] SW mode calibration
4977 13:27:16.965897 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4978 13:27:16.972637 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4979 13:27:16.976552 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4980 13:27:16.979691 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4981 13:27:16.986091 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4982 13:27:16.989217 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4983 13:27:16.992483 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4984 13:27:16.999250 0 10 20 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (0 1)
4985 13:27:17.002953 0 10 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (1 0)
4986 13:27:17.005636 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4987 13:27:17.012360 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4988 13:27:17.015517 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4989 13:27:17.019422 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4990 13:27:17.025605 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4991 13:27:17.029634 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4992 13:27:17.032177 0 11 20 | B1->B0 | 2c2c 3333 | 0 0 | (0 0) (0 0)
4993 13:27:17.038963 0 11 24 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4994 13:27:17.042160 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4995 13:27:17.045626 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4996 13:27:17.049187 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4997 13:27:17.055858 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4998 13:27:17.058813 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4999 13:27:17.061743 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5000 13:27:17.068658 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5001 13:27:17.071692 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5002 13:27:17.075631 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5003 13:27:17.082245 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5004 13:27:17.085171 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5005 13:27:17.088289 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5006 13:27:17.095212 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5007 13:27:17.098881 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5008 13:27:17.101472 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5009 13:27:17.108148 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5010 13:27:17.111690 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5011 13:27:17.115408 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5012 13:27:17.121685 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5013 13:27:17.124995 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5014 13:27:17.127974 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5015 13:27:17.135200 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5016 13:27:17.138148 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5017 13:27:17.141571 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5018 13:27:17.148207 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5019 13:27:17.148713 Total UI for P1: 0, mck2ui 16
5020 13:27:17.154769 best dqsien dly found for B0: ( 0, 14, 24)
5021 13:27:17.155295 Total UI for P1: 0, mck2ui 16
5022 13:27:17.161328 best dqsien dly found for B1: ( 0, 14, 24)
5023 13:27:17.164389 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
5024 13:27:17.167906 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
5025 13:27:17.168458
5026 13:27:17.171159 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 24)
5027 13:27:17.174579 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 24)
5028 13:27:17.177906 [Gating] SW calibration Done
5029 13:27:17.178336 ==
5030 13:27:17.181068 Dram Type= 6, Freq= 0, CH_0, rank 0
5031 13:27:17.184571 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5032 13:27:17.185001 ==
5033 13:27:17.188047 RX Vref Scan: 0
5034 13:27:17.188556
5035 13:27:17.188894 RX Vref 0 -> 0, step: 1
5036 13:27:17.189204
5037 13:27:17.191218 RX Delay -80 -> 252, step: 8
5038 13:27:17.197536 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5039 13:27:17.200860 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5040 13:27:17.204655 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5041 13:27:17.208101 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5042 13:27:17.211802 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5043 13:27:17.214403 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5044 13:27:17.217985 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5045 13:27:17.224543 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5046 13:27:17.227583 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5047 13:27:17.230616 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5048 13:27:17.234532 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5049 13:27:17.237596 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5050 13:27:17.244414 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5051 13:27:17.247396 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5052 13:27:17.250867 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5053 13:27:17.254520 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5054 13:27:17.255040 ==
5055 13:27:17.257805 Dram Type= 6, Freq= 0, CH_0, rank 0
5056 13:27:17.263863 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5057 13:27:17.264381 ==
5058 13:27:17.264815 DQS Delay:
5059 13:27:17.267600 DQS0 = 0, DQS1 = 0
5060 13:27:17.268033 DQM Delay:
5061 13:27:17.268456 DQM0 = 96, DQM1 = 84
5062 13:27:17.270725 DQ Delay:
5063 13:27:17.274030 DQ0 =91, DQ1 =95, DQ2 =95, DQ3 =91
5064 13:27:17.277487 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5065 13:27:17.280450 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =79
5066 13:27:17.284438 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5067 13:27:17.285120
5068 13:27:17.285603
5069 13:27:17.286007 ==
5070 13:27:17.287334 Dram Type= 6, Freq= 0, CH_0, rank 0
5071 13:27:17.291159 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5072 13:27:17.291682 ==
5073 13:27:17.292113
5074 13:27:17.292515
5075 13:27:17.294222 TX Vref Scan disable
5076 13:27:17.294797 == TX Byte 0 ==
5077 13:27:17.300700 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5078 13:27:17.303434 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5079 13:27:17.303958 == TX Byte 1 ==
5080 13:27:17.310693 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5081 13:27:17.314224 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5082 13:27:17.314737 ==
5083 13:27:17.317221 Dram Type= 6, Freq= 0, CH_0, rank 0
5084 13:27:17.320482 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5085 13:27:17.320925 ==
5086 13:27:17.321469
5087 13:27:17.323799
5088 13:27:17.324233 TX Vref Scan disable
5089 13:27:17.327049 == TX Byte 0 ==
5090 13:27:17.330944 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5091 13:27:17.333433 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5092 13:27:17.337096 == TX Byte 1 ==
5093 13:27:17.340340 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5094 13:27:17.343775 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5095 13:27:17.344364
5096 13:27:17.347432 [DATLAT]
5097 13:27:17.348042 Freq=933, CH0 RK0
5098 13:27:17.348582
5099 13:27:17.350128 DATLAT Default: 0xd
5100 13:27:17.350577 0, 0xFFFF, sum = 0
5101 13:27:17.353329 1, 0xFFFF, sum = 0
5102 13:27:17.353772 2, 0xFFFF, sum = 0
5103 13:27:17.356951 3, 0xFFFF, sum = 0
5104 13:27:17.357515 4, 0xFFFF, sum = 0
5105 13:27:17.360340 5, 0xFFFF, sum = 0
5106 13:27:17.360827 6, 0xFFFF, sum = 0
5107 13:27:17.363893 7, 0xFFFF, sum = 0
5108 13:27:17.366893 8, 0xFFFF, sum = 0
5109 13:27:17.367333 9, 0xFFFF, sum = 0
5110 13:27:17.370478 10, 0x0, sum = 1
5111 13:27:17.371001 11, 0x0, sum = 2
5112 13:27:17.371445 12, 0x0, sum = 3
5113 13:27:17.373593 13, 0x0, sum = 4
5114 13:27:17.374254 best_step = 11
5115 13:27:17.374764
5116 13:27:17.375128 ==
5117 13:27:17.376815 Dram Type= 6, Freq= 0, CH_0, rank 0
5118 13:27:17.383584 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5119 13:27:17.384077 ==
5120 13:27:17.384407 RX Vref Scan: 1
5121 13:27:17.384713
5122 13:27:17.386779 RX Vref 0 -> 0, step: 1
5123 13:27:17.387220
5124 13:27:17.390095 RX Delay -69 -> 252, step: 4
5125 13:27:17.390527
5126 13:27:17.393761 Set Vref, RX VrefLevel [Byte0]: 47
5127 13:27:17.396498 [Byte1]: 47
5128 13:27:17.397058
5129 13:27:17.400093 Final RX Vref Byte 0 = 47 to rank0
5130 13:27:17.403754 Final RX Vref Byte 1 = 47 to rank0
5131 13:27:17.406893 Final RX Vref Byte 0 = 47 to rank1
5132 13:27:17.410247 Final RX Vref Byte 1 = 47 to rank1==
5133 13:27:17.413527 Dram Type= 6, Freq= 0, CH_0, rank 0
5134 13:27:17.417136 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5135 13:27:17.417818 ==
5136 13:27:17.419973 DQS Delay:
5137 13:27:17.420360 DQS0 = 0, DQS1 = 0
5138 13:27:17.423437 DQM Delay:
5139 13:27:17.423823 DQM0 = 96, DQM1 = 86
5140 13:27:17.424121 DQ Delay:
5141 13:27:17.427085 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =92
5142 13:27:17.429889 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =104
5143 13:27:17.433313 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =78
5144 13:27:17.436903 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =96
5145 13:27:17.437336
5146 13:27:17.440186
5147 13:27:17.446600 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5148 13:27:17.450073 CH0 RK0: MR19=505, MR18=2424
5149 13:27:17.456867 CH0_RK0: MR19=0x505, MR18=0x2424, DQSOSC=410, MR23=63, INC=64, DEC=42
5150 13:27:17.457394
5151 13:27:17.459667 ----->DramcWriteLeveling(PI) begin...
5152 13:27:17.460068 ==
5153 13:27:17.463105 Dram Type= 6, Freq= 0, CH_0, rank 1
5154 13:27:17.466229 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5155 13:27:17.466620 ==
5156 13:27:17.469876 Write leveling (Byte 0): 28 => 28
5157 13:27:17.473028 Write leveling (Byte 1): 27 => 27
5158 13:27:17.476533 DramcWriteLeveling(PI) end<-----
5159 13:27:17.476994
5160 13:27:17.477342 ==
5161 13:27:17.479290 Dram Type= 6, Freq= 0, CH_0, rank 1
5162 13:27:17.482541 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5163 13:27:17.482931 ==
5164 13:27:17.486381 [Gating] SW mode calibration
5165 13:27:17.492824 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5166 13:27:17.499366 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5167 13:27:17.502874 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 13:27:17.506275 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 13:27:17.512757 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 13:27:17.516337 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 13:27:17.519979 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 13:27:17.526095 0 10 20 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
5173 13:27:17.529752 0 10 24 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
5174 13:27:17.533292 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 13:27:17.539039 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 13:27:17.542532 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 13:27:17.545955 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 13:27:17.552502 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 13:27:17.555808 0 11 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5180 13:27:17.558837 0 11 20 | B1->B0 | 2d2d 3434 | 0 0 | (0 0) (0 0)
5181 13:27:17.565663 0 11 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5182 13:27:17.569043 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 13:27:17.572366 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 13:27:17.578965 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 13:27:17.582392 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 13:27:17.585838 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 13:27:17.592174 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 13:27:17.595641 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5189 13:27:17.599178 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5190 13:27:17.605429 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 13:27:17.608650 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 13:27:17.611832 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 13:27:17.619238 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 13:27:17.622105 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 13:27:17.625804 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 13:27:17.632324 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 13:27:17.635357 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 13:27:17.638551 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 13:27:17.645352 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 13:27:17.648823 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 13:27:17.651470 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 13:27:17.658880 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 13:27:17.661505 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5204 13:27:17.665506 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5205 13:27:17.672188 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 13:27:17.672688 Total UI for P1: 0, mck2ui 16
5207 13:27:17.675509 best dqsien dly found for B0: ( 0, 14, 20)
5208 13:27:17.678220 Total UI for P1: 0, mck2ui 16
5209 13:27:17.681876 best dqsien dly found for B1: ( 0, 14, 18)
5210 13:27:17.688118 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5211 13:27:17.691427 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5212 13:27:17.691860
5213 13:27:17.694803 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5214 13:27:17.697913 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5215 13:27:17.701188 [Gating] SW calibration Done
5216 13:27:17.701659 ==
5217 13:27:17.705036 Dram Type= 6, Freq= 0, CH_0, rank 1
5218 13:27:17.708067 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5219 13:27:17.708524 ==
5220 13:27:17.711533 RX Vref Scan: 0
5221 13:27:17.711959
5222 13:27:17.712291 RX Vref 0 -> 0, step: 1
5223 13:27:17.712598
5224 13:27:17.714969 RX Delay -80 -> 252, step: 8
5225 13:27:17.718029 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5226 13:27:17.724586 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5227 13:27:17.727846 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5228 13:27:17.731117 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5229 13:27:17.734382 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5230 13:27:17.737943 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5231 13:27:17.741553 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5232 13:27:17.744416 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5233 13:27:17.751453 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5234 13:27:17.754458 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5235 13:27:17.757872 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5236 13:27:17.760661 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5237 13:27:17.767665 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5238 13:27:17.771592 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5239 13:27:17.774331 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5240 13:27:17.778137 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5241 13:27:17.778602 ==
5242 13:27:17.781223 Dram Type= 6, Freq= 0, CH_0, rank 1
5243 13:27:17.784798 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5244 13:27:17.785300 ==
5245 13:27:17.787624 DQS Delay:
5246 13:27:17.788084 DQS0 = 0, DQS1 = 0
5247 13:27:17.791291 DQM Delay:
5248 13:27:17.791755 DQM0 = 95, DQM1 = 84
5249 13:27:17.792061 DQ Delay:
5250 13:27:17.794305 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5251 13:27:17.797621 DQ4 =99, DQ5 =83, DQ6 =99, DQ7 =107
5252 13:27:17.800775 DQ8 =71, DQ9 =67, DQ10 =83, DQ11 =79
5253 13:27:17.804268 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =95
5254 13:27:17.804795
5255 13:27:17.807350
5256 13:27:17.807773 ==
5257 13:27:17.810900 Dram Type= 6, Freq= 0, CH_0, rank 1
5258 13:27:17.814420 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5259 13:27:17.814886 ==
5260 13:27:17.815290
5261 13:27:17.815721
5262 13:27:17.817065 TX Vref Scan disable
5263 13:27:17.817506 == TX Byte 0 ==
5264 13:27:17.824282 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5265 13:27:17.827425 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5266 13:27:17.827822 == TX Byte 1 ==
5267 13:27:17.834370 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5268 13:27:17.837165 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5269 13:27:17.837653 ==
5270 13:27:17.841182 Dram Type= 6, Freq= 0, CH_0, rank 1
5271 13:27:17.844143 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5272 13:27:17.844671 ==
5273 13:27:17.845109
5274 13:27:17.845557
5275 13:27:17.847210 TX Vref Scan disable
5276 13:27:17.850705 == TX Byte 0 ==
5277 13:27:17.853931 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5278 13:27:17.857432 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5279 13:27:17.861124 == TX Byte 1 ==
5280 13:27:17.864251 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5281 13:27:17.867044 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5282 13:27:17.867485
5283 13:27:17.871069 [DATLAT]
5284 13:27:17.871583 Freq=933, CH0 RK1
5285 13:27:17.872016
5286 13:27:17.873821 DATLAT Default: 0xb
5287 13:27:17.874254 0, 0xFFFF, sum = 0
5288 13:27:17.877635 1, 0xFFFF, sum = 0
5289 13:27:17.878141 2, 0xFFFF, sum = 0
5290 13:27:17.880506 3, 0xFFFF, sum = 0
5291 13:27:17.881011 4, 0xFFFF, sum = 0
5292 13:27:17.884038 5, 0xFFFF, sum = 0
5293 13:27:17.884553 6, 0xFFFF, sum = 0
5294 13:27:17.887458 7, 0xFFFF, sum = 0
5295 13:27:17.887967 8, 0xFFFF, sum = 0
5296 13:27:17.890862 9, 0xFFFF, sum = 0
5297 13:27:17.891372 10, 0x0, sum = 1
5298 13:27:17.894125 11, 0x0, sum = 2
5299 13:27:17.894636 12, 0x0, sum = 3
5300 13:27:17.896995 13, 0x0, sum = 4
5301 13:27:17.897470 best_step = 11
5302 13:27:17.897806
5303 13:27:17.898113 ==
5304 13:27:17.899851 Dram Type= 6, Freq= 0, CH_0, rank 1
5305 13:27:17.906958 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5306 13:27:17.907462 ==
5307 13:27:17.907798 RX Vref Scan: 0
5308 13:27:17.908110
5309 13:27:17.910040 RX Vref 0 -> 0, step: 1
5310 13:27:17.910472
5311 13:27:17.913456 RX Delay -77 -> 252, step: 4
5312 13:27:17.917248 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5313 13:27:17.920007 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5314 13:27:17.926282 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5315 13:27:17.929799 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5316 13:27:17.932929 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5317 13:27:17.936369 iDelay=203, Bit 5, Center 88 (-5 ~ 182) 188
5318 13:27:17.939816 iDelay=203, Bit 6, Center 102 (11 ~ 194) 184
5319 13:27:17.943486 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5320 13:27:17.949495 iDelay=203, Bit 8, Center 76 (-9 ~ 162) 172
5321 13:27:17.952838 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5322 13:27:17.956538 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5323 13:27:17.959675 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5324 13:27:17.962966 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5325 13:27:17.969778 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5326 13:27:17.973124 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5327 13:27:17.976223 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5328 13:27:17.976653 ==
5329 13:27:17.979988 Dram Type= 6, Freq= 0, CH_0, rank 1
5330 13:27:17.983446 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5331 13:27:17.983958 ==
5332 13:27:17.986436 DQS Delay:
5333 13:27:17.986863 DQS0 = 0, DQS1 = 0
5334 13:27:17.989910 DQM Delay:
5335 13:27:17.990418 DQM0 = 97, DQM1 = 86
5336 13:27:17.990755 DQ Delay:
5337 13:27:17.992843 DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =92
5338 13:27:17.996247 DQ4 =102, DQ5 =88, DQ6 =102, DQ7 =108
5339 13:27:17.999772 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5340 13:27:18.002911 DQ12 =94, DQ13 =90, DQ14 =100, DQ15 =94
5341 13:27:18.003339
5342 13:27:18.005973
5343 13:27:18.012662 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e2e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5344 13:27:18.015611 CH0 RK1: MR19=505, MR18=2E2E
5345 13:27:18.022710 CH0_RK1: MR19=0x505, MR18=0x2E2E, DQSOSC=407, MR23=63, INC=65, DEC=43
5346 13:27:18.025656 [RxdqsGatingPostProcess] freq 933
5347 13:27:18.029547 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5348 13:27:18.032613 Pre-setting of DQS Precalculation
5349 13:27:18.039036 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5350 13:27:18.039467 ==
5351 13:27:18.042148 Dram Type= 6, Freq= 0, CH_1, rank 0
5352 13:27:18.045666 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5353 13:27:18.046059 ==
5354 13:27:18.053142 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5355 13:27:18.056215 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5356 13:27:18.059987 [CA 0] Center 37 (7~68) winsize 62
5357 13:27:18.063167 [CA 1] Center 37 (6~68) winsize 63
5358 13:27:18.066260 [CA 2] Center 34 (4~65) winsize 62
5359 13:27:18.069565 [CA 3] Center 34 (4~65) winsize 62
5360 13:27:18.072853 [CA 4] Center 33 (2~64) winsize 63
5361 13:27:18.076202 [CA 5] Center 33 (2~64) winsize 63
5362 13:27:18.076621
5363 13:27:18.079621 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5364 13:27:18.080018
5365 13:27:18.083042 [CATrainingPosCal] consider 1 rank data
5366 13:27:18.087096 u2DelayCellTimex100 = 270/100 ps
5367 13:27:18.089565 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5368 13:27:18.093300 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5369 13:27:18.099572 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5370 13:27:18.103076 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5371 13:27:18.105951 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5372 13:27:18.109462 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5373 13:27:18.110001
5374 13:27:18.113034 CA PerBit enable=1, Macro0, CA PI delay=33
5375 13:27:18.113587
5376 13:27:18.116293 [CBTSetCACLKResult] CA Dly = 33
5377 13:27:18.116796 CS Dly: 5 (0~36)
5378 13:27:18.119292 ==
5379 13:27:18.122510 Dram Type= 6, Freq= 0, CH_1, rank 1
5380 13:27:18.126021 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5381 13:27:18.126342 ==
5382 13:27:18.128876 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5383 13:27:18.135835 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5384 13:27:18.139403 [CA 0] Center 37 (6~68) winsize 63
5385 13:27:18.142866 [CA 1] Center 37 (6~68) winsize 63
5386 13:27:18.146589 [CA 2] Center 34 (4~65) winsize 62
5387 13:27:18.149792 [CA 3] Center 34 (4~65) winsize 62
5388 13:27:18.152785 [CA 4] Center 33 (2~64) winsize 63
5389 13:27:18.156015 [CA 5] Center 33 (2~64) winsize 63
5390 13:27:18.156289
5391 13:27:18.159183 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5392 13:27:18.159460
5393 13:27:18.162409 [CATrainingPosCal] consider 2 rank data
5394 13:27:18.165887 u2DelayCellTimex100 = 270/100 ps
5395 13:27:18.168935 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5396 13:27:18.175905 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5397 13:27:18.179300 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5398 13:27:18.182745 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5399 13:27:18.186203 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5400 13:27:18.189432 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5401 13:27:18.189930
5402 13:27:18.193132 CA PerBit enable=1, Macro0, CA PI delay=33
5403 13:27:18.193681
5404 13:27:18.196399 [CBTSetCACLKResult] CA Dly = 33
5405 13:27:18.196917 CS Dly: 5 (0~37)
5406 13:27:18.199112
5407 13:27:18.202680 ----->DramcWriteLeveling(PI) begin...
5408 13:27:18.203217 ==
5409 13:27:18.205973 Dram Type= 6, Freq= 0, CH_1, rank 0
5410 13:27:18.209217 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5411 13:27:18.209766 ==
5412 13:27:18.212459 Write leveling (Byte 0): 24 => 24
5413 13:27:18.216263 Write leveling (Byte 1): 24 => 24
5414 13:27:18.219705 DramcWriteLeveling(PI) end<-----
5415 13:27:18.220239
5416 13:27:18.220570 ==
5417 13:27:18.222598 Dram Type= 6, Freq= 0, CH_1, rank 0
5418 13:27:18.226164 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5419 13:27:18.226669 ==
5420 13:27:18.229013 [Gating] SW mode calibration
5421 13:27:18.235811 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5422 13:27:18.242350 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5423 13:27:18.245778 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5424 13:27:18.248827 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5425 13:27:18.255868 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5426 13:27:18.259287 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5427 13:27:18.262036 0 10 16 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
5428 13:27:18.268999 0 10 20 | B1->B0 | 3333 2929 | 0 0 | (0 1) (1 0)
5429 13:27:18.271997 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5430 13:27:18.275159 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5431 13:27:18.281886 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5432 13:27:18.285942 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5433 13:27:18.288824 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5434 13:27:18.295514 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5435 13:27:18.299253 0 11 16 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5436 13:27:18.301954 0 11 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
5437 13:27:18.308643 0 11 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5438 13:27:18.311632 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5439 13:27:18.314958 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5440 13:27:18.321381 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5441 13:27:18.325879 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5442 13:27:18.328444 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5443 13:27:18.335870 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5444 13:27:18.338367 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5445 13:27:18.341643 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5446 13:27:18.348216 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 13:27:18.351274 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 13:27:18.355325 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 13:27:18.357767 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 13:27:18.364529 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 13:27:18.367906 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 13:27:18.371005 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 13:27:18.377864 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5454 13:27:18.381299 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5455 13:27:18.384770 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5456 13:27:18.391177 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5457 13:27:18.394875 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5458 13:27:18.398168 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5459 13:27:18.404610 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5460 13:27:18.408121 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5461 13:27:18.411162 Total UI for P1: 0, mck2ui 16
5462 13:27:18.414170 best dqsien dly found for B0: ( 0, 14, 18)
5463 13:27:18.417655 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5464 13:27:18.424243 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5465 13:27:18.427403 Total UI for P1: 0, mck2ui 16
5466 13:27:18.431228 best dqsien dly found for B1: ( 0, 14, 22)
5467 13:27:18.434496 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5468 13:27:18.437613 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5469 13:27:18.438017
5470 13:27:18.440605 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5471 13:27:18.444709 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5472 13:27:18.447658 [Gating] SW calibration Done
5473 13:27:18.448044 ==
5474 13:27:18.450359 Dram Type= 6, Freq= 0, CH_1, rank 0
5475 13:27:18.453832 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5476 13:27:18.454221 ==
5477 13:27:18.457446 RX Vref Scan: 0
5478 13:27:18.457833
5479 13:27:18.460575 RX Vref 0 -> 0, step: 1
5480 13:27:18.460963
5481 13:27:18.461300 RX Delay -80 -> 252, step: 8
5482 13:27:18.467202 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5483 13:27:18.470420 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5484 13:27:18.473758 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5485 13:27:18.477303 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5486 13:27:18.480454 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5487 13:27:18.484336 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5488 13:27:18.490515 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5489 13:27:18.493950 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5490 13:27:18.497268 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5491 13:27:18.500233 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5492 13:27:18.504041 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5493 13:27:18.510513 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5494 13:27:18.513468 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5495 13:27:18.516870 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5496 13:27:18.520722 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5497 13:27:18.523871 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5498 13:27:18.524271 ==
5499 13:27:18.527024 Dram Type= 6, Freq= 0, CH_1, rank 0
5500 13:27:18.533399 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5501 13:27:18.533790 ==
5502 13:27:18.534094 DQS Delay:
5503 13:27:18.534374 DQS0 = 0, DQS1 = 0
5504 13:27:18.537612 DQM Delay:
5505 13:27:18.537999 DQM0 = 95, DQM1 = 88
5506 13:27:18.539980 DQ Delay:
5507 13:27:18.543842 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5508 13:27:18.547160 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5509 13:27:18.550149 DQ8 =71, DQ9 =75, DQ10 =95, DQ11 =79
5510 13:27:18.553642 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99
5511 13:27:18.554031
5512 13:27:18.554327
5513 13:27:18.554601 ==
5514 13:27:18.556807 Dram Type= 6, Freq= 0, CH_1, rank 0
5515 13:27:18.560207 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5516 13:27:18.560637 ==
5517 13:27:18.560970
5518 13:27:18.561321
5519 13:27:18.563062 TX Vref Scan disable
5520 13:27:18.563485 == TX Byte 0 ==
5521 13:27:18.569760 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5522 13:27:18.573306 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5523 13:27:18.573700 == TX Byte 1 ==
5524 13:27:18.580895 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5525 13:27:18.583444 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5526 13:27:18.583947 ==
5527 13:27:18.586885 Dram Type= 6, Freq= 0, CH_1, rank 0
5528 13:27:18.590239 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5529 13:27:18.590673 ==
5530 13:27:18.591002
5531 13:27:18.591305
5532 13:27:18.593610 TX Vref Scan disable
5533 13:27:18.597324 == TX Byte 0 ==
5534 13:27:18.600148 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5535 13:27:18.603445 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5536 13:27:18.606240 == TX Byte 1 ==
5537 13:27:18.609732 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5538 13:27:18.613158 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5539 13:27:18.616778
5540 13:27:18.617414 [DATLAT]
5541 13:27:18.617771 Freq=933, CH1 RK0
5542 13:27:18.618085
5543 13:27:18.620082 DATLAT Default: 0xd
5544 13:27:18.620584 0, 0xFFFF, sum = 0
5545 13:27:18.623399 1, 0xFFFF, sum = 0
5546 13:27:18.623839 2, 0xFFFF, sum = 0
5547 13:27:18.626484 3, 0xFFFF, sum = 0
5548 13:27:18.626999 4, 0xFFFF, sum = 0
5549 13:27:18.629689 5, 0xFFFF, sum = 0
5550 13:27:18.633095 6, 0xFFFF, sum = 0
5551 13:27:18.633554 7, 0xFFFF, sum = 0
5552 13:27:18.636636 8, 0xFFFF, sum = 0
5553 13:27:18.637309 9, 0xFFFF, sum = 0
5554 13:27:18.639698 10, 0x0, sum = 1
5555 13:27:18.640213 11, 0x0, sum = 2
5556 13:27:18.640558 12, 0x0, sum = 3
5557 13:27:18.643080 13, 0x0, sum = 4
5558 13:27:18.643517 best_step = 11
5559 13:27:18.643849
5560 13:27:18.646045 ==
5561 13:27:18.646475 Dram Type= 6, Freq= 0, CH_1, rank 0
5562 13:27:18.652848 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5563 13:27:18.653420 ==
5564 13:27:18.653782 RX Vref Scan: 1
5565 13:27:18.654094
5566 13:27:18.656593 RX Vref 0 -> 0, step: 1
5567 13:27:18.657095
5568 13:27:18.660188 RX Delay -69 -> 252, step: 4
5569 13:27:18.660691
5570 13:27:18.663375 Set Vref, RX VrefLevel [Byte0]: 54
5571 13:27:18.666095 [Byte1]: 50
5572 13:27:18.666527
5573 13:27:18.669676 Final RX Vref Byte 0 = 54 to rank0
5574 13:27:18.672944 Final RX Vref Byte 1 = 50 to rank0
5575 13:27:18.676274 Final RX Vref Byte 0 = 54 to rank1
5576 13:27:18.679838 Final RX Vref Byte 1 = 50 to rank1==
5577 13:27:18.682673 Dram Type= 6, Freq= 0, CH_1, rank 0
5578 13:27:18.686043 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5579 13:27:18.686502 ==
5580 13:27:18.689597 DQS Delay:
5581 13:27:18.690191 DQS0 = 0, DQS1 = 0
5582 13:27:18.692494 DQM Delay:
5583 13:27:18.692997 DQM0 = 94, DQM1 = 87
5584 13:27:18.695964 DQ Delay:
5585 13:27:18.696478 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =90
5586 13:27:18.699271 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =92
5587 13:27:18.702564 DQ8 =70, DQ9 =78, DQ10 =88, DQ11 =80
5588 13:27:18.706170 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5589 13:27:18.706716
5590 13:27:18.709169
5591 13:27:18.717692 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b3b, (MSB)MR19= 0x505, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
5592 13:27:18.718885 CH1 RK0: MR19=505, MR18=3B3B
5593 13:27:18.725565 CH1_RK0: MR19=0x505, MR18=0x3B3B, DQSOSC=403, MR23=63, INC=66, DEC=44
5594 13:27:18.726023
5595 13:27:18.729122 ----->DramcWriteLeveling(PI) begin...
5596 13:27:18.729549 ==
5597 13:27:18.732787 Dram Type= 6, Freq= 0, CH_1, rank 1
5598 13:27:18.735719 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5599 13:27:18.736233 ==
5600 13:27:18.738834 Write leveling (Byte 0): 27 => 27
5601 13:27:18.742518 Write leveling (Byte 1): 22 => 22
5602 13:27:18.745923 DramcWriteLeveling(PI) end<-----
5603 13:27:18.746347
5604 13:27:18.746671 ==
5605 13:27:18.749265 Dram Type= 6, Freq= 0, CH_1, rank 1
5606 13:27:18.752414 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5607 13:27:18.752847 ==
5608 13:27:18.755924 [Gating] SW mode calibration
5609 13:27:18.762450 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5610 13:27:18.768702 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5611 13:27:18.772028 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 13:27:18.775777 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 13:27:18.782107 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 13:27:18.785832 0 10 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5615 13:27:18.789052 0 10 16 | B1->B0 | 3434 2727 | 0 0 | (0 0) (0 0)
5616 13:27:18.795297 0 10 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5617 13:27:18.798317 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 13:27:18.801544 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 13:27:18.808200 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 13:27:18.812334 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 13:27:18.815523 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 13:27:18.821519 0 11 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5623 13:27:18.825289 0 11 16 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
5624 13:27:18.828219 0 11 20 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
5625 13:27:18.835940 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 13:27:18.838303 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 13:27:18.841331 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 13:27:18.848245 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 13:27:18.851466 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 13:27:18.854616 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 13:27:18.861258 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5632 13:27:18.864769 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5633 13:27:18.867978 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 13:27:18.874559 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 13:27:18.878104 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 13:27:18.881480 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 13:27:18.888018 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 13:27:18.891257 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 13:27:18.894586 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 13:27:18.901357 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 13:27:18.904294 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 13:27:18.907942 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 13:27:18.914299 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 13:27:18.917816 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 13:27:18.921495 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 13:27:18.928005 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 13:27:18.930918 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5648 13:27:18.934023 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5649 13:27:18.941128 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 13:27:18.941706 Total UI for P1: 0, mck2ui 16
5651 13:27:18.947932 best dqsien dly found for B0: ( 0, 14, 18)
5652 13:27:18.948457 Total UI for P1: 0, mck2ui 16
5653 13:27:18.953750 best dqsien dly found for B1: ( 0, 14, 18)
5654 13:27:18.957827 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5655 13:27:18.960754 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5656 13:27:18.961330
5657 13:27:18.964264 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5658 13:27:18.967106 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5659 13:27:18.970798 [Gating] SW calibration Done
5660 13:27:18.971236 ==
5661 13:27:18.973735 Dram Type= 6, Freq= 0, CH_1, rank 1
5662 13:27:18.976749 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5663 13:27:18.977195 ==
5664 13:27:18.980049 RX Vref Scan: 0
5665 13:27:18.980490
5666 13:27:18.980932 RX Vref 0 -> 0, step: 1
5667 13:27:18.983568
5668 13:27:18.984147 RX Delay -80 -> 252, step: 8
5669 13:27:18.989818 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5670 13:27:18.993565 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5671 13:27:18.996676 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5672 13:27:19.000014 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5673 13:27:19.003505 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5674 13:27:19.006373 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5675 13:27:19.013107 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5676 13:27:19.016506 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5677 13:27:19.019705 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5678 13:27:19.023062 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5679 13:27:19.026865 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5680 13:27:19.033785 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5681 13:27:19.037006 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5682 13:27:19.039613 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5683 13:27:19.043529 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5684 13:27:19.047020 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5685 13:27:19.047499 ==
5686 13:27:19.049847 Dram Type= 6, Freq= 0, CH_1, rank 1
5687 13:27:19.057385 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5688 13:27:19.057897 ==
5689 13:27:19.058369 DQS Delay:
5690 13:27:19.058781 DQS0 = 0, DQS1 = 0
5691 13:27:19.060864 DQM Delay:
5692 13:27:19.061411 DQM0 = 99, DQM1 = 87
5693 13:27:19.063275 DQ Delay:
5694 13:27:19.066173 DQ0 =103, DQ1 =91, DQ2 =91, DQ3 =95
5695 13:27:19.069812 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5696 13:27:19.073000 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =75
5697 13:27:19.076109 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5698 13:27:19.076618
5699 13:27:19.077082
5700 13:27:19.077541 ==
5701 13:27:19.079840 Dram Type= 6, Freq= 0, CH_1, rank 1
5702 13:27:19.082669 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5703 13:27:19.083192 ==
5704 13:27:19.083632
5705 13:27:19.084038
5706 13:27:19.085593 TX Vref Scan disable
5707 13:27:19.089601 == TX Byte 0 ==
5708 13:27:19.092715 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5709 13:27:19.096319 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5710 13:27:19.099796 == TX Byte 1 ==
5711 13:27:19.102440 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5712 13:27:19.105956 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5713 13:27:19.106404 ==
5714 13:27:19.109852 Dram Type= 6, Freq= 0, CH_1, rank 1
5715 13:27:19.112355 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5716 13:27:19.112801 ==
5717 13:27:19.115813
5718 13:27:19.116249
5719 13:27:19.116687 TX Vref Scan disable
5720 13:27:19.119898 == TX Byte 0 ==
5721 13:27:19.122649 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5722 13:27:19.129494 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5723 13:27:19.130014 == TX Byte 1 ==
5724 13:27:19.132955 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5725 13:27:19.139033 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5726 13:27:19.139550
5727 13:27:19.139988 [DATLAT]
5728 13:27:19.140394 Freq=933, CH1 RK1
5729 13:27:19.140794
5730 13:27:19.142402 DATLAT Default: 0xb
5731 13:27:19.142844 0, 0xFFFF, sum = 0
5732 13:27:19.146293 1, 0xFFFF, sum = 0
5733 13:27:19.146815 2, 0xFFFF, sum = 0
5734 13:27:19.149358 3, 0xFFFF, sum = 0
5735 13:27:19.152982 4, 0xFFFF, sum = 0
5736 13:27:19.153636 5, 0xFFFF, sum = 0
5737 13:27:19.155687 6, 0xFFFF, sum = 0
5738 13:27:19.156201 7, 0xFFFF, sum = 0
5739 13:27:19.159473 8, 0xFFFF, sum = 0
5740 13:27:19.159982 9, 0xFFFF, sum = 0
5741 13:27:19.162773 10, 0x0, sum = 1
5742 13:27:19.163314 11, 0x0, sum = 2
5743 13:27:19.165593 12, 0x0, sum = 3
5744 13:27:19.166044 13, 0x0, sum = 4
5745 13:27:19.166490 best_step = 11
5746 13:27:19.166894
5747 13:27:19.168998 ==
5748 13:27:19.172304 Dram Type= 6, Freq= 0, CH_1, rank 1
5749 13:27:19.175276 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5750 13:27:19.175720 ==
5751 13:27:19.176160 RX Vref Scan: 0
5752 13:27:19.176573
5753 13:27:19.179095 RX Vref 0 -> 0, step: 1
5754 13:27:19.179605
5755 13:27:19.182667 RX Delay -69 -> 252, step: 4
5756 13:27:19.186087 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5757 13:27:19.192086 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5758 13:27:19.195975 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5759 13:27:19.198599 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5760 13:27:19.202212 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5761 13:27:19.205887 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5762 13:27:19.208870 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5763 13:27:19.215267 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5764 13:27:19.218478 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5765 13:27:19.221996 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5766 13:27:19.226229 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184
5767 13:27:19.228826 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5768 13:27:19.236310 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5769 13:27:19.238764 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5770 13:27:19.242236 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5771 13:27:19.245432 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5772 13:27:19.245937 ==
5773 13:27:19.249010 Dram Type= 6, Freq= 0, CH_1, rank 1
5774 13:27:19.252799 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5775 13:27:19.253349 ==
5776 13:27:19.255600 DQS Delay:
5777 13:27:19.256163 DQS0 = 0, DQS1 = 0
5778 13:27:19.258750 DQM Delay:
5779 13:27:19.259250 DQM0 = 95, DQM1 = 87
5780 13:27:19.259578 DQ Delay:
5781 13:27:19.262468 DQ0 =94, DQ1 =90, DQ2 =88, DQ3 =92
5782 13:27:19.264954 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5783 13:27:19.269052 DQ8 =74, DQ9 =74, DQ10 =86, DQ11 =78
5784 13:27:19.272217 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5785 13:27:19.272652
5786 13:27:19.275353
5787 13:27:19.281914 [DQSOSCAuto] RK1, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5788 13:27:19.285013 CH1 RK1: MR19=505, MR18=2525
5789 13:27:19.291794 CH1_RK1: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42
5790 13:27:19.295172 [RxdqsGatingPostProcess] freq 933
5791 13:27:19.298103 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5792 13:27:19.301881 Pre-setting of DQS Precalculation
5793 13:27:19.308828 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5794 13:27:19.315223 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5795 13:27:19.321439 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5796 13:27:19.321872
5797 13:27:19.322272
5798 13:27:19.325086 [Calibration Summary] 1866 Mbps
5799 13:27:19.325624 CH 0, Rank 0
5800 13:27:19.328089 SW Impedance : PASS
5801 13:27:19.331623 DUTY Scan : NO K
5802 13:27:19.332066 ZQ Calibration : PASS
5803 13:27:19.334660 Jitter Meter : NO K
5804 13:27:19.338286 CBT Training : PASS
5805 13:27:19.338748 Write leveling : PASS
5806 13:27:19.341433 RX DQS gating : PASS
5807 13:27:19.344587 RX DQ/DQS(RDDQC) : PASS
5808 13:27:19.345086 TX DQ/DQS : PASS
5809 13:27:19.348098 RX DATLAT : PASS
5810 13:27:19.348601 RX DQ/DQS(Engine): PASS
5811 13:27:19.351876 TX OE : NO K
5812 13:27:19.352384 All Pass.
5813 13:27:19.352720
5814 13:27:19.354701 CH 0, Rank 1
5815 13:27:19.355132 SW Impedance : PASS
5816 13:27:19.357962 DUTY Scan : NO K
5817 13:27:19.361656 ZQ Calibration : PASS
5818 13:27:19.362161 Jitter Meter : NO K
5819 13:27:19.364413 CBT Training : PASS
5820 13:27:19.367950 Write leveling : PASS
5821 13:27:19.368456 RX DQS gating : PASS
5822 13:27:19.371110 RX DQ/DQS(RDDQC) : PASS
5823 13:27:19.375085 TX DQ/DQS : PASS
5824 13:27:19.375602 RX DATLAT : PASS
5825 13:27:19.378198 RX DQ/DQS(Engine): PASS
5826 13:27:19.381298 TX OE : NO K
5827 13:27:19.381805 All Pass.
5828 13:27:19.382140
5829 13:27:19.382447 CH 1, Rank 0
5830 13:27:19.384202 SW Impedance : PASS
5831 13:27:19.387932 DUTY Scan : NO K
5832 13:27:19.388467 ZQ Calibration : PASS
5833 13:27:19.390592 Jitter Meter : NO K
5834 13:27:19.394482 CBT Training : PASS
5835 13:27:19.394988 Write leveling : PASS
5836 13:27:19.397917 RX DQS gating : PASS
5837 13:27:19.400723 RX DQ/DQS(RDDQC) : PASS
5838 13:27:19.401149 TX DQ/DQS : PASS
5839 13:27:19.403879 RX DATLAT : PASS
5840 13:27:19.404312 RX DQ/DQS(Engine): PASS
5841 13:27:19.407827 TX OE : NO K
5842 13:27:19.408256 All Pass.
5843 13:27:19.408588
5844 13:27:19.411058 CH 1, Rank 1
5845 13:27:19.414184 SW Impedance : PASS
5846 13:27:19.414610 DUTY Scan : NO K
5847 13:27:19.417131 ZQ Calibration : PASS
5848 13:27:19.417601 Jitter Meter : NO K
5849 13:27:19.420616 CBT Training : PASS
5850 13:27:19.424053 Write leveling : PASS
5851 13:27:19.424558 RX DQS gating : PASS
5852 13:27:19.427645 RX DQ/DQS(RDDQC) : PASS
5853 13:27:19.430287 TX DQ/DQS : PASS
5854 13:27:19.430722 RX DATLAT : PASS
5855 13:27:19.433934 RX DQ/DQS(Engine): PASS
5856 13:27:19.437082 TX OE : NO K
5857 13:27:19.437555 All Pass.
5858 13:27:19.437883
5859 13:27:19.440474 DramC Write-DBI off
5860 13:27:19.440897 PER_BANK_REFRESH: Hybrid Mode
5861 13:27:19.443559 TX_TRACKING: ON
5862 13:27:19.450246 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5863 13:27:19.457376 [FAST_K] Save calibration result to emmc
5864 13:27:19.460686 dramc_set_vcore_voltage set vcore to 650000
5865 13:27:19.461112 Read voltage for 400, 6
5866 13:27:19.464193 Vio18 = 0
5867 13:27:19.464695 Vcore = 650000
5868 13:27:19.465030 Vdram = 0
5869 13:27:19.467328 Vddq = 0
5870 13:27:19.467829 Vmddr = 0
5871 13:27:19.470268 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5872 13:27:19.477393 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5873 13:27:19.480853 MEM_TYPE=3, freq_sel=20
5874 13:27:19.484247 sv_algorithm_assistance_LP4_800
5875 13:27:19.486970 ============ PULL DRAM RESETB DOWN ============
5876 13:27:19.490306 ========== PULL DRAM RESETB DOWN end =========
5877 13:27:19.496757 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5878 13:27:19.499920 ===================================
5879 13:27:19.500351 LPDDR4 DRAM CONFIGURATION
5880 13:27:19.503469 ===================================
5881 13:27:19.507248 EX_ROW_EN[0] = 0x0
5882 13:27:19.507678 EX_ROW_EN[1] = 0x0
5883 13:27:19.510267 LP4Y_EN = 0x0
5884 13:27:19.510801 WORK_FSP = 0x0
5885 13:27:19.513379 WL = 0x2
5886 13:27:19.513808 RL = 0x2
5887 13:27:19.516987 BL = 0x2
5888 13:27:19.520279 RPST = 0x0
5889 13:27:19.520782 RD_PRE = 0x0
5890 13:27:19.523342 WR_PRE = 0x1
5891 13:27:19.523847 WR_PST = 0x0
5892 13:27:19.526639 DBI_WR = 0x0
5893 13:27:19.527066 DBI_RD = 0x0
5894 13:27:19.530111 OTF = 0x1
5895 13:27:19.533426 ===================================
5896 13:27:19.537135 ===================================
5897 13:27:19.537695 ANA top config
5898 13:27:19.540034 ===================================
5899 13:27:19.542885 DLL_ASYNC_EN = 0
5900 13:27:19.546343 ALL_SLAVE_EN = 1
5901 13:27:19.546773 NEW_RANK_MODE = 1
5902 13:27:19.549614 DLL_IDLE_MODE = 1
5903 13:27:19.553673 LP45_APHY_COMB_EN = 1
5904 13:27:19.556816 TX_ODT_DIS = 1
5905 13:27:19.559856 NEW_8X_MODE = 1
5906 13:27:19.560559 ===================================
5907 13:27:19.562944 ===================================
5908 13:27:19.566364 data_rate = 800
5909 13:27:19.569758 CKR = 1
5910 13:27:19.573337 DQ_P2S_RATIO = 4
5911 13:27:19.576405 ===================================
5912 13:27:19.579671 CA_P2S_RATIO = 4
5913 13:27:19.582981 DQ_CA_OPEN = 0
5914 13:27:19.585964 DQ_SEMI_OPEN = 1
5915 13:27:19.586533 CA_SEMI_OPEN = 1
5916 13:27:19.589365 CA_FULL_RATE = 0
5917 13:27:19.592969 DQ_CKDIV4_EN = 0
5918 13:27:19.596134 CA_CKDIV4_EN = 1
5919 13:27:19.599407 CA_PREDIV_EN = 0
5920 13:27:19.602710 PH8_DLY = 0
5921 13:27:19.603096 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5922 13:27:19.606276 DQ_AAMCK_DIV = 0
5923 13:27:19.609211 CA_AAMCK_DIV = 0
5924 13:27:19.612356 CA_ADMCK_DIV = 4
5925 13:27:19.616066 DQ_TRACK_CA_EN = 0
5926 13:27:19.619038 CA_PICK = 800
5927 13:27:19.622692 CA_MCKIO = 400
5928 13:27:19.623084 MCKIO_SEMI = 400
5929 13:27:19.625849 PLL_FREQ = 3016
5930 13:27:19.628716 DQ_UI_PI_RATIO = 32
5931 13:27:19.632190 CA_UI_PI_RATIO = 32
5932 13:27:19.635643 ===================================
5933 13:27:19.639315 ===================================
5934 13:27:19.642381 memory_type:LPDDR4
5935 13:27:19.643029 GP_NUM : 10
5936 13:27:19.646435 SRAM_EN : 1
5937 13:27:19.648921 MD32_EN : 0
5938 13:27:19.652557 ===================================
5939 13:27:19.653040 [ANA_INIT] >>>>>>>>>>>>>>
5940 13:27:19.656423 <<<<<< [CONFIGURE PHASE]: ANA_TX
5941 13:27:19.658773 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5942 13:27:19.662565 ===================================
5943 13:27:19.665178 data_rate = 800,PCW = 0X7400
5944 13:27:19.669002 ===================================
5945 13:27:19.672135 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5946 13:27:19.678899 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5947 13:27:19.688806 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5948 13:27:19.695398 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5949 13:27:19.699325 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5950 13:27:19.702167 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5951 13:27:19.702650 [ANA_INIT] flow start
5952 13:27:19.705862 [ANA_INIT] PLL >>>>>>>>
5953 13:27:19.708752 [ANA_INIT] PLL <<<<<<<<
5954 13:27:19.709212 [ANA_INIT] MIDPI >>>>>>>>
5955 13:27:19.712434 [ANA_INIT] MIDPI <<<<<<<<
5956 13:27:19.715953 [ANA_INIT] DLL >>>>>>>>
5957 13:27:19.716465 [ANA_INIT] flow end
5958 13:27:19.722219 ============ LP4 DIFF to SE enter ============
5959 13:27:19.725544 ============ LP4 DIFF to SE exit ============
5960 13:27:19.726055 [ANA_INIT] <<<<<<<<<<<<<
5961 13:27:19.728331 [Flow] Enable top DCM control >>>>>
5962 13:27:19.731496 [Flow] Enable top DCM control <<<<<
5963 13:27:19.735537 Enable DLL master slave shuffle
5964 13:27:19.741960 ==============================================================
5965 13:27:19.744960 Gating Mode config
5966 13:27:19.748337 ==============================================================
5967 13:27:19.751530 Config description:
5968 13:27:19.761762 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5969 13:27:19.768195 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5970 13:27:19.771535 SELPH_MODE 0: By rank 1: By Phase
5971 13:27:19.778214 ==============================================================
5972 13:27:19.781586 GAT_TRACK_EN = 0
5973 13:27:19.784965 RX_GATING_MODE = 2
5974 13:27:19.788096 RX_GATING_TRACK_MODE = 2
5975 13:27:19.791064 SELPH_MODE = 1
5976 13:27:19.791703 PICG_EARLY_EN = 1
5977 13:27:19.794881 VALID_LAT_VALUE = 1
5978 13:27:19.801077 ==============================================================
5979 13:27:19.804746 Enter into Gating configuration >>>>
5980 13:27:19.808211 Exit from Gating configuration <<<<
5981 13:27:19.811044 Enter into DVFS_PRE_config >>>>>
5982 13:27:19.820983 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5983 13:27:19.824519 Exit from DVFS_PRE_config <<<<<
5984 13:27:19.828474 Enter into PICG configuration >>>>
5985 13:27:19.831309 Exit from PICG configuration <<<<
5986 13:27:19.834661 [RX_INPUT] configuration >>>>>
5987 13:27:19.838381 [RX_INPUT] configuration <<<<<
5988 13:27:19.840699 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5989 13:27:19.848284 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5990 13:27:19.854480 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5991 13:27:19.860838 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5992 13:27:19.867692 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5993 13:27:19.871175 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5994 13:27:19.878035 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5995 13:27:19.881318 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5996 13:27:19.884200 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5997 13:27:19.887744 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5998 13:27:19.894188 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5999 13:27:19.897607 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6000 13:27:19.900813 ===================================
6001 13:27:19.903713 LPDDR4 DRAM CONFIGURATION
6002 13:27:19.907259 ===================================
6003 13:27:19.907815 EX_ROW_EN[0] = 0x0
6004 13:27:19.910535 EX_ROW_EN[1] = 0x0
6005 13:27:19.910978 LP4Y_EN = 0x0
6006 13:27:19.913709 WORK_FSP = 0x0
6007 13:27:19.914278 WL = 0x2
6008 13:27:19.916993 RL = 0x2
6009 13:27:19.917544 BL = 0x2
6010 13:27:19.920849 RPST = 0x0
6011 13:27:19.923839 RD_PRE = 0x0
6012 13:27:19.924270 WR_PRE = 0x1
6013 13:27:19.927311 WR_PST = 0x0
6014 13:27:19.927740 DBI_WR = 0x0
6015 13:27:19.930672 DBI_RD = 0x0
6016 13:27:19.931236 OTF = 0x1
6017 13:27:19.933850 ===================================
6018 13:27:19.936731 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6019 13:27:19.943717 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6020 13:27:19.947314 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6021 13:27:19.950466 ===================================
6022 13:27:19.953506 LPDDR4 DRAM CONFIGURATION
6023 13:27:19.956906 ===================================
6024 13:27:19.957341 EX_ROW_EN[0] = 0x10
6025 13:27:19.960693 EX_ROW_EN[1] = 0x0
6026 13:27:19.961155 LP4Y_EN = 0x0
6027 13:27:19.964169 WORK_FSP = 0x0
6028 13:27:19.964635 WL = 0x2
6029 13:27:19.967065 RL = 0x2
6030 13:27:19.967456 BL = 0x2
6031 13:27:19.970103 RPST = 0x0
6032 13:27:19.970490 RD_PRE = 0x0
6033 13:27:19.974015 WR_PRE = 0x1
6034 13:27:19.974403 WR_PST = 0x0
6035 13:27:19.976682 DBI_WR = 0x0
6036 13:27:19.980522 DBI_RD = 0x0
6037 13:27:19.981001 OTF = 0x1
6038 13:27:19.983789 ===================================
6039 13:27:19.989968 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6040 13:27:19.993678 nWR fixed to 30
6041 13:27:19.996983 [ModeRegInit_LP4] CH0 RK0
6042 13:27:19.997494 [ModeRegInit_LP4] CH0 RK1
6043 13:27:20.000977 [ModeRegInit_LP4] CH1 RK0
6044 13:27:20.004116 [ModeRegInit_LP4] CH1 RK1
6045 13:27:20.004585 match AC timing 18
6046 13:27:20.010783 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6047 13:27:20.013576 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6048 13:27:20.016983 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6049 13:27:20.023663 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6050 13:27:20.027019 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6051 13:27:20.027528 ==
6052 13:27:20.030119 Dram Type= 6, Freq= 0, CH_0, rank 0
6053 13:27:20.033458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6054 13:27:20.033969 ==
6055 13:27:20.039963 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6056 13:27:20.046741 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6057 13:27:20.050054 [CA 0] Center 36 (8~64) winsize 57
6058 13:27:20.053959 [CA 1] Center 36 (8~64) winsize 57
6059 13:27:20.056408 [CA 2] Center 36 (8~64) winsize 57
6060 13:27:20.060378 [CA 3] Center 36 (8~64) winsize 57
6061 13:27:20.060808 [CA 4] Center 36 (8~64) winsize 57
6062 13:27:20.063253 [CA 5] Center 36 (8~64) winsize 57
6063 13:27:20.063756
6064 13:27:20.070113 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6065 13:27:20.070606
6066 13:27:20.072872 [CATrainingPosCal] consider 1 rank data
6067 13:27:20.076960 u2DelayCellTimex100 = 270/100 ps
6068 13:27:20.080092 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6069 13:27:20.083311 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6070 13:27:20.086263 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6071 13:27:20.090523 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6072 13:27:20.093101 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6073 13:27:20.096720 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6074 13:27:20.097221
6075 13:27:20.100102 CA PerBit enable=1, Macro0, CA PI delay=36
6076 13:27:20.100525
6077 13:27:20.103181 [CBTSetCACLKResult] CA Dly = 36
6078 13:27:20.106931 CS Dly: 1 (0~32)
6079 13:27:20.107427 ==
6080 13:27:20.109451 Dram Type= 6, Freq= 0, CH_0, rank 1
6081 13:27:20.112911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6082 13:27:20.113371 ==
6083 13:27:20.119713 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6084 13:27:20.126631 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6085 13:27:20.127203 [CA 0] Center 36 (8~64) winsize 57
6086 13:27:20.129780 [CA 1] Center 36 (8~64) winsize 57
6087 13:27:20.133114 [CA 2] Center 36 (8~64) winsize 57
6088 13:27:20.136290 [CA 3] Center 36 (8~64) winsize 57
6089 13:27:20.139630 [CA 4] Center 36 (8~64) winsize 57
6090 13:27:20.142855 [CA 5] Center 36 (8~64) winsize 57
6091 13:27:20.143296
6092 13:27:20.145851 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6093 13:27:20.146280
6094 13:27:20.149315 [CATrainingPosCal] consider 2 rank data
6095 13:27:20.152676 u2DelayCellTimex100 = 270/100 ps
6096 13:27:20.155773 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6097 13:27:20.162441 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6098 13:27:20.165839 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6099 13:27:20.168918 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6100 13:27:20.172621 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6101 13:27:20.176094 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6102 13:27:20.176596
6103 13:27:20.178711 CA PerBit enable=1, Macro0, CA PI delay=36
6104 13:27:20.179149
6105 13:27:20.183873 [CBTSetCACLKResult] CA Dly = 36
6106 13:27:20.184382 CS Dly: 1 (0~32)
6107 13:27:20.185779
6108 13:27:20.189118 ----->DramcWriteLeveling(PI) begin...
6109 13:27:20.189692 ==
6110 13:27:20.192486 Dram Type= 6, Freq= 0, CH_0, rank 0
6111 13:27:20.195353 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6112 13:27:20.195857 ==
6113 13:27:20.198937 Write leveling (Byte 0): 32 => 0
6114 13:27:20.202306 Write leveling (Byte 1): 32 => 0
6115 13:27:20.205910 DramcWriteLeveling(PI) end<-----
6116 13:27:20.206420
6117 13:27:20.206753 ==
6118 13:27:20.208961 Dram Type= 6, Freq= 0, CH_0, rank 0
6119 13:27:20.212463 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6120 13:27:20.212969 ==
6121 13:27:20.215248 [Gating] SW mode calibration
6122 13:27:20.221924 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6123 13:27:20.228691 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6124 13:27:20.231895 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6125 13:27:20.235224 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6126 13:27:20.241775 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6127 13:27:20.245740 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6128 13:27:20.248440 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6129 13:27:20.255157 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6130 13:27:20.258528 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6131 13:27:20.262105 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6132 13:27:20.268850 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6133 13:27:20.269274 Total UI for P1: 0, mck2ui 16
6134 13:27:20.274639 best dqsien dly found for B0: ( 0, 10, 16)
6135 13:27:20.275029 Total UI for P1: 0, mck2ui 16
6136 13:27:20.278139 best dqsien dly found for B1: ( 0, 10, 24)
6137 13:27:20.285006 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6138 13:27:20.288755 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6139 13:27:20.289216
6140 13:27:20.291517 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6141 13:27:20.294975 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6142 13:27:20.298283 [Gating] SW calibration Done
6143 13:27:20.298768 ==
6144 13:27:20.301760 Dram Type= 6, Freq= 0, CH_0, rank 0
6145 13:27:20.305188 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6146 13:27:20.305710 ==
6147 13:27:20.308111 RX Vref Scan: 0
6148 13:27:20.308570
6149 13:27:20.308871 RX Vref 0 -> 0, step: 1
6150 13:27:20.309147
6151 13:27:20.311747 RX Delay -410 -> 252, step: 16
6152 13:27:20.318195 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6153 13:27:20.321294 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6154 13:27:20.325088 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6155 13:27:20.327938 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6156 13:27:20.334635 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6157 13:27:20.337475 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6158 13:27:20.341040 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6159 13:27:20.344365 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6160 13:27:20.350643 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6161 13:27:20.355105 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6162 13:27:20.357869 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6163 13:27:20.360959 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6164 13:27:20.367992 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6165 13:27:20.370829 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6166 13:27:20.374533 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6167 13:27:20.380788 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6168 13:27:20.381297 ==
6169 13:27:20.383902 Dram Type= 6, Freq= 0, CH_0, rank 0
6170 13:27:20.387849 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6171 13:27:20.388315 ==
6172 13:27:20.388621 DQS Delay:
6173 13:27:20.390509 DQS0 = 51, DQS1 = 59
6174 13:27:20.390894 DQM Delay:
6175 13:27:20.394180 DQM0 = 12, DQM1 = 15
6176 13:27:20.394643 DQ Delay:
6177 13:27:20.397608 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6178 13:27:20.400588 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6179 13:27:20.404017 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6180 13:27:20.407229 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6181 13:27:20.407690
6182 13:27:20.407989
6183 13:27:20.408262 ==
6184 13:27:20.410649 Dram Type= 6, Freq= 0, CH_0, rank 0
6185 13:27:20.413594 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6186 13:27:20.413985 ==
6187 13:27:20.414284
6188 13:27:20.414556
6189 13:27:20.417175 TX Vref Scan disable
6190 13:27:20.417666 == TX Byte 0 ==
6191 13:27:20.423381 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6192 13:27:20.427058 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6193 13:27:20.427534 == TX Byte 1 ==
6194 13:27:20.434213 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6195 13:27:20.436567 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6196 13:27:20.436955 ==
6197 13:27:20.440107 Dram Type= 6, Freq= 0, CH_0, rank 0
6198 13:27:20.443670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6199 13:27:20.444060 ==
6200 13:27:20.447283
6201 13:27:20.447754
6202 13:27:20.448055 TX Vref Scan disable
6203 13:27:20.450153 == TX Byte 0 ==
6204 13:27:20.453716 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6205 13:27:20.456456 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6206 13:27:20.460003 == TX Byte 1 ==
6207 13:27:20.463217 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6208 13:27:20.467152 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6209 13:27:20.467738
6210 13:27:20.469724 [DATLAT]
6211 13:27:20.470115 Freq=400, CH0 RK0
6212 13:27:20.470418
6213 13:27:20.473035 DATLAT Default: 0xf
6214 13:27:20.473573 0, 0xFFFF, sum = 0
6215 13:27:20.476165 1, 0xFFFF, sum = 0
6216 13:27:20.476557 2, 0xFFFF, sum = 0
6217 13:27:20.479430 3, 0xFFFF, sum = 0
6218 13:27:20.479827 4, 0xFFFF, sum = 0
6219 13:27:20.483228 5, 0xFFFF, sum = 0
6220 13:27:20.483718 6, 0xFFFF, sum = 0
6221 13:27:20.487075 7, 0xFFFF, sum = 0
6222 13:27:20.487557 8, 0xFFFF, sum = 0
6223 13:27:20.489707 9, 0xFFFF, sum = 0
6224 13:27:20.490117 10, 0xFFFF, sum = 0
6225 13:27:20.493107 11, 0xFFFF, sum = 0
6226 13:27:20.493667 12, 0x0, sum = 1
6227 13:27:20.496304 13, 0x0, sum = 2
6228 13:27:20.496839 14, 0x0, sum = 3
6229 13:27:20.499624 15, 0x0, sum = 4
6230 13:27:20.500063 best_step = 13
6231 13:27:20.500398
6232 13:27:20.500708 ==
6233 13:27:20.502615 Dram Type= 6, Freq= 0, CH_0, rank 0
6234 13:27:20.509648 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6235 13:27:20.510156 ==
6236 13:27:20.510491 RX Vref Scan: 1
6237 13:27:20.510797
6238 13:27:20.512706 RX Vref 0 -> 0, step: 1
6239 13:27:20.513221
6240 13:27:20.516121 RX Delay -359 -> 252, step: 8
6241 13:27:20.516608
6242 13:27:20.519282 Set Vref, RX VrefLevel [Byte0]: 47
6243 13:27:20.522328 [Byte1]: 47
6244 13:27:20.526020
6245 13:27:20.526521 Final RX Vref Byte 0 = 47 to rank0
6246 13:27:20.529829 Final RX Vref Byte 1 = 47 to rank0
6247 13:27:20.532785 Final RX Vref Byte 0 = 47 to rank1
6248 13:27:20.535761 Final RX Vref Byte 1 = 47 to rank1==
6249 13:27:20.539183 Dram Type= 6, Freq= 0, CH_0, rank 0
6250 13:27:20.545625 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6251 13:27:20.546059 ==
6252 13:27:20.546409 DQS Delay:
6253 13:27:20.549141 DQS0 = 52, DQS1 = 68
6254 13:27:20.549610 DQM Delay:
6255 13:27:20.549976 DQM0 = 9, DQM1 = 16
6256 13:27:20.552270 DQ Delay:
6257 13:27:20.555818 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6258 13:27:20.556251 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6259 13:27:20.559480 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6260 13:27:20.562152 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6261 13:27:20.562607
6262 13:27:20.565710
6263 13:27:20.572165 [DQSOSCAuto] RK0, (LSB)MR18= 0xa4a4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6264 13:27:20.575613 CH0 RK0: MR19=C0C, MR18=A4A4
6265 13:27:20.582224 CH0_RK0: MR19=0xC0C, MR18=0xA4A4, DQSOSC=389, MR23=63, INC=390, DEC=260
6266 13:27:20.582700 ==
6267 13:27:20.585891 Dram Type= 6, Freq= 0, CH_0, rank 1
6268 13:27:20.589210 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6269 13:27:20.589759 ==
6270 13:27:20.592493 [Gating] SW mode calibration
6271 13:27:20.599424 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6272 13:27:20.605678 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6273 13:27:20.608849 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6274 13:27:20.612721 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6275 13:27:20.618516 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 13:27:20.622047 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6277 13:27:20.624914 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 13:27:20.631831 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 13:27:20.635291 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 13:27:20.638367 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6281 13:27:20.645101 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6282 13:27:20.645654 Total UI for P1: 0, mck2ui 16
6283 13:27:20.648612 best dqsien dly found for B0: ( 0, 10, 16)
6284 13:27:20.651363 Total UI for P1: 0, mck2ui 16
6285 13:27:20.654725 best dqsien dly found for B1: ( 0, 10, 16)
6286 13:27:20.661597 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6287 13:27:20.665065 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6288 13:27:20.665551
6289 13:27:20.668152 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6290 13:27:20.671129 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6291 13:27:20.674750 [Gating] SW calibration Done
6292 13:27:20.675253 ==
6293 13:27:20.678024 Dram Type= 6, Freq= 0, CH_0, rank 1
6294 13:27:20.681525 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6295 13:27:20.682080 ==
6296 13:27:20.684426 RX Vref Scan: 0
6297 13:27:20.684963
6298 13:27:20.685352 RX Vref 0 -> 0, step: 1
6299 13:27:20.685680
6300 13:27:20.687765 RX Delay -410 -> 252, step: 16
6301 13:27:20.694591 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6302 13:27:20.697971 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6303 13:27:20.700951 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6304 13:27:20.704201 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6305 13:27:20.711937 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6306 13:27:20.714479 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6307 13:27:20.717521 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6308 13:27:20.721573 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6309 13:27:20.727390 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6310 13:27:20.731181 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6311 13:27:20.733938 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6312 13:27:20.737614 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6313 13:27:20.744383 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6314 13:27:20.747457 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6315 13:27:20.750471 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6316 13:27:20.757002 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6317 13:27:20.757507 ==
6318 13:27:20.760826 Dram Type= 6, Freq= 0, CH_0, rank 1
6319 13:27:20.763434 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6320 13:27:20.763836 ==
6321 13:27:20.764166 DQS Delay:
6322 13:27:20.767268 DQS0 = 43, DQS1 = 59
6323 13:27:20.767699 DQM Delay:
6324 13:27:20.770523 DQM0 = 7, DQM1 = 15
6325 13:27:20.770954 DQ Delay:
6326 13:27:20.774319 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6327 13:27:20.777399 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6328 13:27:20.780239 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6329 13:27:20.783792 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6330 13:27:20.784182
6331 13:27:20.784489
6332 13:27:20.784831 ==
6333 13:27:20.786671 Dram Type= 6, Freq= 0, CH_0, rank 1
6334 13:27:20.790198 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6335 13:27:20.790589 ==
6336 13:27:20.790898
6337 13:27:20.791179
6338 13:27:20.793572 TX Vref Scan disable
6339 13:27:20.794043 == TX Byte 0 ==
6340 13:27:20.800373 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6341 13:27:20.803256 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6342 13:27:20.803648 == TX Byte 1 ==
6343 13:27:20.810072 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6344 13:27:20.813614 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6345 13:27:20.814076 ==
6346 13:27:20.816473 Dram Type= 6, Freq= 0, CH_0, rank 1
6347 13:27:20.820392 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6348 13:27:20.820899 ==
6349 13:27:20.821294
6350 13:27:20.821620
6351 13:27:20.822998 TX Vref Scan disable
6352 13:27:20.826607 == TX Byte 0 ==
6353 13:27:20.830064 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6354 13:27:20.833961 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6355 13:27:20.836174 == TX Byte 1 ==
6356 13:27:20.839409 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6357 13:27:20.843053 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6358 13:27:20.843447
6359 13:27:20.843755 [DATLAT]
6360 13:27:20.846002 Freq=400, CH0 RK1
6361 13:27:20.846390
6362 13:27:20.846771 DATLAT Default: 0xd
6363 13:27:20.849472 0, 0xFFFF, sum = 0
6364 13:27:20.849892 1, 0xFFFF, sum = 0
6365 13:27:20.852814 2, 0xFFFF, sum = 0
6366 13:27:20.856337 3, 0xFFFF, sum = 0
6367 13:27:20.856744 4, 0xFFFF, sum = 0
6368 13:27:20.859718 5, 0xFFFF, sum = 0
6369 13:27:20.860129 6, 0xFFFF, sum = 0
6370 13:27:20.862762 7, 0xFFFF, sum = 0
6371 13:27:20.863282 8, 0xFFFF, sum = 0
6372 13:27:20.866184 9, 0xFFFF, sum = 0
6373 13:27:20.866657 10, 0xFFFF, sum = 0
6374 13:27:20.869643 11, 0xFFFF, sum = 0
6375 13:27:20.870117 12, 0x0, sum = 1
6376 13:27:20.872380 13, 0x0, sum = 2
6377 13:27:20.872836 14, 0x0, sum = 3
6378 13:27:20.876073 15, 0x0, sum = 4
6379 13:27:20.876542 best_step = 13
6380 13:27:20.876946
6381 13:27:20.877390 ==
6382 13:27:20.879266 Dram Type= 6, Freq= 0, CH_0, rank 1
6383 13:27:20.882658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6384 13:27:20.883119 ==
6385 13:27:20.886093 RX Vref Scan: 0
6386 13:27:20.886413
6387 13:27:20.889050 RX Vref 0 -> 0, step: 1
6388 13:27:20.889429
6389 13:27:20.889649 RX Delay -359 -> 252, step: 8
6390 13:27:20.898555 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6391 13:27:20.901464 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6392 13:27:20.905010 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6393 13:27:20.911992 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6394 13:27:20.914557 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6395 13:27:20.918049 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6396 13:27:20.921274 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6397 13:27:20.924796 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6398 13:27:20.931491 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6399 13:27:20.934779 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6400 13:27:20.938322 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6401 13:27:20.945151 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6402 13:27:20.948486 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6403 13:27:20.951884 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6404 13:27:20.954515 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6405 13:27:20.961721 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6406 13:27:20.962208 ==
6407 13:27:20.965086 Dram Type= 6, Freq= 0, CH_0, rank 1
6408 13:27:20.968132 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6409 13:27:20.968630 ==
6410 13:27:20.968974 DQS Delay:
6411 13:27:20.971201 DQS0 = 52, DQS1 = 60
6412 13:27:20.971726 DQM Delay:
6413 13:27:20.975068 DQM0 = 10, DQM1 = 9
6414 13:27:20.975570 DQ Delay:
6415 13:27:20.977971 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6416 13:27:20.981396 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6417 13:27:20.985131 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6418 13:27:20.987936 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =16
6419 13:27:20.988430
6420 13:27:20.988764
6421 13:27:20.994258 [DQSOSCAuto] RK1, (LSB)MR18= 0xc8c8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6422 13:27:20.997919 CH0 RK1: MR19=C0C, MR18=C8C8
6423 13:27:21.004785 CH0_RK1: MR19=0xC0C, MR18=0xC8C8, DQSOSC=385, MR23=63, INC=398, DEC=265
6424 13:27:21.007713 [RxdqsGatingPostProcess] freq 400
6425 13:27:21.014565 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6426 13:27:21.017937 Pre-setting of DQS Precalculation
6427 13:27:21.020604 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6428 13:27:21.021032 ==
6429 13:27:21.024491 Dram Type= 6, Freq= 0, CH_1, rank 0
6430 13:27:21.027230 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6431 13:27:21.027659 ==
6432 13:27:21.034651 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6433 13:27:21.040770 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6434 13:27:21.043955 [CA 0] Center 36 (8~64) winsize 57
6435 13:27:21.048096 [CA 1] Center 36 (8~64) winsize 57
6436 13:27:21.051553 [CA 2] Center 36 (8~64) winsize 57
6437 13:27:21.054343 [CA 3] Center 36 (8~64) winsize 57
6438 13:27:21.057720 [CA 4] Center 36 (8~64) winsize 57
6439 13:27:21.058226 [CA 5] Center 36 (8~64) winsize 57
6440 13:27:21.060458
6441 13:27:21.064527 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6442 13:27:21.065025
6443 13:27:21.067233 [CATrainingPosCal] consider 1 rank data
6444 13:27:21.071134 u2DelayCellTimex100 = 270/100 ps
6445 13:27:21.074087 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6446 13:27:21.077431 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6447 13:27:21.081013 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6448 13:27:21.083754 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6449 13:27:21.087203 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6450 13:27:21.090536 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6451 13:27:21.091041
6452 13:27:21.093696 CA PerBit enable=1, Macro0, CA PI delay=36
6453 13:27:21.094132
6454 13:27:21.097397 [CBTSetCACLKResult] CA Dly = 36
6455 13:27:21.100467 CS Dly: 1 (0~32)
6456 13:27:21.100972 ==
6457 13:27:21.103603 Dram Type= 6, Freq= 0, CH_1, rank 1
6458 13:27:21.106759 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6459 13:27:21.107189 ==
6460 13:27:21.113562 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6461 13:27:21.120065 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6462 13:27:21.123262 [CA 0] Center 36 (8~64) winsize 57
6463 13:27:21.123694 [CA 1] Center 36 (8~64) winsize 57
6464 13:27:21.127186 [CA 2] Center 36 (8~64) winsize 57
6465 13:27:21.130948 [CA 3] Center 36 (8~64) winsize 57
6466 13:27:21.133491 [CA 4] Center 36 (8~64) winsize 57
6467 13:27:21.137073 [CA 5] Center 36 (8~64) winsize 57
6468 13:27:21.137566
6469 13:27:21.140326 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6470 13:27:21.140854
6471 13:27:21.143392 [CATrainingPosCal] consider 2 rank data
6472 13:27:21.147354 u2DelayCellTimex100 = 270/100 ps
6473 13:27:21.150734 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6474 13:27:21.156977 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6475 13:27:21.160007 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6476 13:27:21.163801 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6477 13:27:21.167029 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6478 13:27:21.169855 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6479 13:27:21.170300
6480 13:27:21.173378 CA PerBit enable=1, Macro0, CA PI delay=36
6481 13:27:21.173901
6482 13:27:21.177155 [CBTSetCACLKResult] CA Dly = 36
6483 13:27:21.177756 CS Dly: 1 (0~32)
6484 13:27:21.180752
6485 13:27:21.183178 ----->DramcWriteLeveling(PI) begin...
6486 13:27:21.183631 ==
6487 13:27:21.187143 Dram Type= 6, Freq= 0, CH_1, rank 0
6488 13:27:21.190141 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6489 13:27:21.190588 ==
6490 13:27:21.193087 Write leveling (Byte 0): 32 => 0
6491 13:27:21.196458 Write leveling (Byte 1): 32 => 0
6492 13:27:21.200002 DramcWriteLeveling(PI) end<-----
6493 13:27:21.200442
6494 13:27:21.200875 ==
6495 13:27:21.202753 Dram Type= 6, Freq= 0, CH_1, rank 0
6496 13:27:21.206105 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6497 13:27:21.206550 ==
6498 13:27:21.209494 [Gating] SW mode calibration
6499 13:27:21.216215 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6500 13:27:21.222834 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6501 13:27:21.226213 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6502 13:27:21.229528 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6503 13:27:21.236404 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6504 13:27:21.240306 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6505 13:27:21.242687 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 13:27:21.249885 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6507 13:27:21.252876 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6508 13:27:21.256169 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6509 13:27:21.263068 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6510 13:27:21.263704 Total UI for P1: 0, mck2ui 16
6511 13:27:21.269136 best dqsien dly found for B0: ( 0, 10, 16)
6512 13:27:21.269744 Total UI for P1: 0, mck2ui 16
6513 13:27:21.276000 best dqsien dly found for B1: ( 0, 10, 16)
6514 13:27:21.279735 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6515 13:27:21.282219 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6516 13:27:21.282653
6517 13:27:21.285750 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6518 13:27:21.289134 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6519 13:27:21.292225 [Gating] SW calibration Done
6520 13:27:21.292655 ==
6521 13:27:21.295280 Dram Type= 6, Freq= 0, CH_1, rank 0
6522 13:27:21.298802 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6523 13:27:21.299319 ==
6524 13:27:21.302869 RX Vref Scan: 0
6525 13:27:21.303383
6526 13:27:21.303727 RX Vref 0 -> 0, step: 1
6527 13:27:21.305303
6528 13:27:21.305731 RX Delay -410 -> 252, step: 16
6529 13:27:21.312369 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6530 13:27:21.315493 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6531 13:27:21.318863 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6532 13:27:21.322021 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6533 13:27:21.328946 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6534 13:27:21.332193 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6535 13:27:21.334897 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6536 13:27:21.338655 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6537 13:27:21.345260 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6538 13:27:21.348226 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6539 13:27:21.352030 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6540 13:27:21.354868 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6541 13:27:21.361516 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6542 13:27:21.365040 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6543 13:27:21.369029 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6544 13:27:21.374840 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6545 13:27:21.375368 ==
6546 13:27:21.378406 Dram Type= 6, Freq= 0, CH_1, rank 0
6547 13:27:21.381122 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6548 13:27:21.381607 ==
6549 13:27:21.382046 DQS Delay:
6550 13:27:21.384762 DQS0 = 43, DQS1 = 59
6551 13:27:21.385210 DQM Delay:
6552 13:27:21.388530 DQM0 = 6, DQM1 = 16
6553 13:27:21.389056 DQ Delay:
6554 13:27:21.391552 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6555 13:27:21.394778 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6556 13:27:21.398186 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6557 13:27:21.401052 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =32
6558 13:27:21.401536
6559 13:27:21.401975
6560 13:27:21.402388 ==
6561 13:27:21.404471 Dram Type= 6, Freq= 0, CH_1, rank 0
6562 13:27:21.408011 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6563 13:27:21.408531 ==
6564 13:27:21.409067
6565 13:27:21.409542
6566 13:27:21.410928 TX Vref Scan disable
6567 13:27:21.414548 == TX Byte 0 ==
6568 13:27:21.418063 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6569 13:27:21.421375 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6570 13:27:21.424283 == TX Byte 1 ==
6571 13:27:21.428128 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6572 13:27:21.431458 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6573 13:27:21.431963 ==
6574 13:27:21.434452 Dram Type= 6, Freq= 0, CH_1, rank 0
6575 13:27:21.437647 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6576 13:27:21.440923 ==
6577 13:27:21.441471
6578 13:27:21.441813
6579 13:27:21.442119 TX Vref Scan disable
6580 13:27:21.444232 == TX Byte 0 ==
6581 13:27:21.447811 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6582 13:27:21.450525 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6583 13:27:21.454116 == TX Byte 1 ==
6584 13:27:21.457651 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6585 13:27:21.460970 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6586 13:27:21.461471
6587 13:27:21.464262 [DATLAT]
6588 13:27:21.464792 Freq=400, CH1 RK0
6589 13:27:21.465269
6590 13:27:21.467538 DATLAT Default: 0xf
6591 13:27:21.467996 0, 0xFFFF, sum = 0
6592 13:27:21.470404 1, 0xFFFF, sum = 0
6593 13:27:21.470854 2, 0xFFFF, sum = 0
6594 13:27:21.473945 3, 0xFFFF, sum = 0
6595 13:27:21.474400 4, 0xFFFF, sum = 0
6596 13:27:21.477389 5, 0xFFFF, sum = 0
6597 13:27:21.477841 6, 0xFFFF, sum = 0
6598 13:27:21.480552 7, 0xFFFF, sum = 0
6599 13:27:21.481104 8, 0xFFFF, sum = 0
6600 13:27:21.483927 9, 0xFFFF, sum = 0
6601 13:27:21.484567 10, 0xFFFF, sum = 0
6602 13:27:21.487295 11, 0xFFFF, sum = 0
6603 13:27:21.487829 12, 0x0, sum = 1
6604 13:27:21.490695 13, 0x0, sum = 2
6605 13:27:21.491131 14, 0x0, sum = 3
6606 13:27:21.493528 15, 0x0, sum = 4
6607 13:27:21.493964 best_step = 13
6608 13:27:21.494298
6609 13:27:21.494611 ==
6610 13:27:21.496977 Dram Type= 6, Freq= 0, CH_1, rank 0
6611 13:27:21.503451 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6612 13:27:21.503844 ==
6613 13:27:21.504149 RX Vref Scan: 1
6614 13:27:21.504429
6615 13:27:21.507084 RX Vref 0 -> 0, step: 1
6616 13:27:21.507473
6617 13:27:21.510032 RX Delay -359 -> 252, step: 8
6618 13:27:21.510420
6619 13:27:21.513806 Set Vref, RX VrefLevel [Byte0]: 54
6620 13:27:21.517013 [Byte1]: 50
6621 13:27:21.520452
6622 13:27:21.520867 Final RX Vref Byte 0 = 54 to rank0
6623 13:27:21.523470 Final RX Vref Byte 1 = 50 to rank0
6624 13:27:21.526762 Final RX Vref Byte 0 = 54 to rank1
6625 13:27:21.530575 Final RX Vref Byte 1 = 50 to rank1==
6626 13:27:21.533179 Dram Type= 6, Freq= 0, CH_1, rank 0
6627 13:27:21.540599 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6628 13:27:21.540987 ==
6629 13:27:21.541263 DQS Delay:
6630 13:27:21.543382 DQS0 = 48, DQS1 = 64
6631 13:27:21.543712 DQM Delay:
6632 13:27:21.543952 DQM0 = 8, DQM1 = 16
6633 13:27:21.547085 DQ Delay:
6634 13:27:21.549940 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =4
6635 13:27:21.550387 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6636 13:27:21.554094 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6637 13:27:21.556906 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6638 13:27:21.557492
6639 13:27:21.557837
6640 13:27:21.566476 [DQSOSCAuto] RK0, (LSB)MR18= 0xe2e2, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6641 13:27:21.570083 CH1 RK0: MR19=C0C, MR18=E2E2
6642 13:27:21.576709 CH1_RK0: MR19=0xC0C, MR18=0xE2E2, DQSOSC=382, MR23=63, INC=404, DEC=269
6643 13:27:21.577216 ==
6644 13:27:21.580246 Dram Type= 6, Freq= 0, CH_1, rank 1
6645 13:27:21.584090 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6646 13:27:21.584618 ==
6647 13:27:21.586300 [Gating] SW mode calibration
6648 13:27:21.593652 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6649 13:27:21.596823 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6650 13:27:21.603379 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6651 13:27:21.607046 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6652 13:27:21.609887 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6653 13:27:21.616292 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6654 13:27:21.619735 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6655 13:27:21.623092 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6656 13:27:21.629676 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6657 13:27:21.632830 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6658 13:27:21.636869 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6659 13:27:21.639786 Total UI for P1: 0, mck2ui 16
6660 13:27:21.643054 best dqsien dly found for B0: ( 0, 10, 16)
6661 13:27:21.645944 Total UI for P1: 0, mck2ui 16
6662 13:27:21.649893 best dqsien dly found for B1: ( 0, 10, 16)
6663 13:27:21.652785 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6664 13:27:21.659661 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6665 13:27:21.660096
6666 13:27:21.662688 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6667 13:27:21.666374 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6668 13:27:21.669561 [Gating] SW calibration Done
6669 13:27:21.669996 ==
6670 13:27:21.672557 Dram Type= 6, Freq= 0, CH_1, rank 1
6671 13:27:21.676262 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6672 13:27:21.676777 ==
6673 13:27:21.680160 RX Vref Scan: 0
6674 13:27:21.680664
6675 13:27:21.681005 RX Vref 0 -> 0, step: 1
6676 13:27:21.681370
6677 13:27:21.682503 RX Delay -410 -> 252, step: 16
6678 13:27:21.686042 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6679 13:27:21.693153 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6680 13:27:21.695803 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6681 13:27:21.699975 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6682 13:27:21.702958 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6683 13:27:21.708890 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6684 13:27:21.712586 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6685 13:27:21.716095 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6686 13:27:21.719314 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6687 13:27:21.725706 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6688 13:27:21.729667 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6689 13:27:21.732524 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6690 13:27:21.739071 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6691 13:27:21.742482 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6692 13:27:21.745597 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6693 13:27:21.749272 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6694 13:27:21.749705 ==
6695 13:27:21.752485 Dram Type= 6, Freq= 0, CH_1, rank 1
6696 13:27:21.758878 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6697 13:27:21.759310 ==
6698 13:27:21.759645 DQS Delay:
6699 13:27:21.762163 DQS0 = 43, DQS1 = 59
6700 13:27:21.762587 DQM Delay:
6701 13:27:21.765841 DQM0 = 10, DQM1 = 18
6702 13:27:21.766340 DQ Delay:
6703 13:27:21.768542 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6704 13:27:21.772365 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6705 13:27:21.772785 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6706 13:27:21.778710 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6707 13:27:21.779212
6708 13:27:21.779545
6709 13:27:21.779846 ==
6710 13:27:21.781983 Dram Type= 6, Freq= 0, CH_1, rank 1
6711 13:27:21.785325 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6712 13:27:21.785838 ==
6713 13:27:21.786341
6714 13:27:21.786664
6715 13:27:21.788483 TX Vref Scan disable
6716 13:27:21.788983 == TX Byte 0 ==
6717 13:27:21.795498 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6718 13:27:21.798770 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6719 13:27:21.799372 == TX Byte 1 ==
6720 13:27:21.801309 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6721 13:27:21.808062 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6722 13:27:21.808508 ==
6723 13:27:21.811273 Dram Type= 6, Freq= 0, CH_1, rank 1
6724 13:27:21.814592 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6725 13:27:21.815074 ==
6726 13:27:21.815451
6727 13:27:21.815762
6728 13:27:21.818498 TX Vref Scan disable
6729 13:27:21.818979 == TX Byte 0 ==
6730 13:27:21.824680 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6731 13:27:21.828209 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6732 13:27:21.828745 == TX Byte 1 ==
6733 13:27:21.834768 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6734 13:27:21.838108 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6735 13:27:21.838504
6736 13:27:21.838894 [DATLAT]
6737 13:27:21.841145 Freq=400, CH1 RK1
6738 13:27:21.841575
6739 13:27:21.841876 DATLAT Default: 0xd
6740 13:27:21.844927 0, 0xFFFF, sum = 0
6741 13:27:21.845405 1, 0xFFFF, sum = 0
6742 13:27:21.847917 2, 0xFFFF, sum = 0
6743 13:27:21.848309 3, 0xFFFF, sum = 0
6744 13:27:21.851491 4, 0xFFFF, sum = 0
6745 13:27:21.851884 5, 0xFFFF, sum = 0
6746 13:27:21.854265 6, 0xFFFF, sum = 0
6747 13:27:21.854661 7, 0xFFFF, sum = 0
6748 13:27:21.857981 8, 0xFFFF, sum = 0
6749 13:27:21.858375 9, 0xFFFF, sum = 0
6750 13:27:21.860836 10, 0xFFFF, sum = 0
6751 13:27:21.864298 11, 0xFFFF, sum = 0
6752 13:27:21.864741 12, 0x0, sum = 1
6753 13:27:21.865053 13, 0x0, sum = 2
6754 13:27:21.867994 14, 0x0, sum = 3
6755 13:27:21.868387 15, 0x0, sum = 4
6756 13:27:21.870922 best_step = 13
6757 13:27:21.871307
6758 13:27:21.871683 ==
6759 13:27:21.873967 Dram Type= 6, Freq= 0, CH_1, rank 1
6760 13:27:21.877562 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6761 13:27:21.877968 ==
6762 13:27:21.881063 RX Vref Scan: 0
6763 13:27:21.881486
6764 13:27:21.881790 RX Vref 0 -> 0, step: 1
6765 13:27:21.882071
6766 13:27:21.884235 RX Delay -359 -> 252, step: 8
6767 13:27:21.892905 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6768 13:27:21.895921 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6769 13:27:21.899258 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6770 13:27:21.902156 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6771 13:27:21.908736 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6772 13:27:21.912419 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6773 13:27:21.915515 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6774 13:27:21.919362 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6775 13:27:21.925469 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6776 13:27:21.929354 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6777 13:27:21.932043 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6778 13:27:21.938982 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6779 13:27:21.942195 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6780 13:27:21.945531 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6781 13:27:21.949107 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6782 13:27:21.955948 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6783 13:27:21.956338 ==
6784 13:27:21.959079 Dram Type= 6, Freq= 0, CH_1, rank 1
6785 13:27:21.962613 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6786 13:27:21.963003 ==
6787 13:27:21.963305 DQS Delay:
6788 13:27:21.965650 DQS0 = 48, DQS1 = 64
6789 13:27:21.966036 DQM Delay:
6790 13:27:21.969086 DQM0 = 9, DQM1 = 15
6791 13:27:21.969516 DQ Delay:
6792 13:27:21.972115 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6793 13:27:21.975619 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6794 13:27:21.979205 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6795 13:27:21.982316 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6796 13:27:21.982867
6797 13:27:21.983522
6798 13:27:21.988653 [DQSOSCAuto] RK1, (LSB)MR18= 0xb2b2, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6799 13:27:21.992416 CH1 RK1: MR19=C0C, MR18=B2B2
6800 13:27:21.998870 CH1_RK1: MR19=0xC0C, MR18=0xB2B2, DQSOSC=387, MR23=63, INC=394, DEC=262
6801 13:27:22.002516 [RxdqsGatingPostProcess] freq 400
6802 13:27:22.005358 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6803 13:27:22.008960 Pre-setting of DQS Precalculation
6804 13:27:22.016172 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6805 13:27:22.021781 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6806 13:27:22.028682 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6807 13:27:22.029093
6808 13:27:22.029455
6809 13:27:22.031847 [Calibration Summary] 800 Mbps
6810 13:27:22.035157 CH 0, Rank 0
6811 13:27:22.035547 SW Impedance : PASS
6812 13:27:22.038807 DUTY Scan : NO K
6813 13:27:22.041923 ZQ Calibration : PASS
6814 13:27:22.042312 Jitter Meter : NO K
6815 13:27:22.045343 CBT Training : PASS
6816 13:27:22.048557 Write leveling : PASS
6817 13:27:22.049032 RX DQS gating : PASS
6818 13:27:22.051681 RX DQ/DQS(RDDQC) : PASS
6819 13:27:22.052069 TX DQ/DQS : PASS
6820 13:27:22.054811 RX DATLAT : PASS
6821 13:27:22.058863 RX DQ/DQS(Engine): PASS
6822 13:27:22.059382 TX OE : NO K
6823 13:27:22.061518 All Pass.
6824 13:27:22.061944
6825 13:27:22.062275 CH 0, Rank 1
6826 13:27:22.064966 SW Impedance : PASS
6827 13:27:22.065556 DUTY Scan : NO K
6828 13:27:22.068711 ZQ Calibration : PASS
6829 13:27:22.071475 Jitter Meter : NO K
6830 13:27:22.071906 CBT Training : PASS
6831 13:27:22.074992 Write leveling : NO K
6832 13:27:22.078593 RX DQS gating : PASS
6833 13:27:22.079022 RX DQ/DQS(RDDQC) : PASS
6834 13:27:22.082181 TX DQ/DQS : PASS
6835 13:27:22.085568 RX DATLAT : PASS
6836 13:27:22.086080 RX DQ/DQS(Engine): PASS
6837 13:27:22.087946 TX OE : NO K
6838 13:27:22.088378 All Pass.
6839 13:27:22.088779
6840 13:27:22.091583 CH 1, Rank 0
6841 13:27:22.092086 SW Impedance : PASS
6842 13:27:22.094665 DUTY Scan : NO K
6843 13:27:22.098594 ZQ Calibration : PASS
6844 13:27:22.099109 Jitter Meter : NO K
6845 13:27:22.101861 CBT Training : PASS
6846 13:27:22.104652 Write leveling : PASS
6847 13:27:22.105086 RX DQS gating : PASS
6848 13:27:22.108274 RX DQ/DQS(RDDQC) : PASS
6849 13:27:22.108786 TX DQ/DQS : PASS
6850 13:27:22.111629 RX DATLAT : PASS
6851 13:27:22.115383 RX DQ/DQS(Engine): PASS
6852 13:27:22.115808 TX OE : NO K
6853 13:27:22.117964 All Pass.
6854 13:27:22.118389
6855 13:27:22.118720 CH 1, Rank 1
6856 13:27:22.121439 SW Impedance : PASS
6857 13:27:22.121865 DUTY Scan : NO K
6858 13:27:22.124398 ZQ Calibration : PASS
6859 13:27:22.127940 Jitter Meter : NO K
6860 13:27:22.128366 CBT Training : PASS
6861 13:27:22.131673 Write leveling : NO K
6862 13:27:22.134769 RX DQS gating : PASS
6863 13:27:22.135196 RX DQ/DQS(RDDQC) : PASS
6864 13:27:22.138284 TX DQ/DQS : PASS
6865 13:27:22.141493 RX DATLAT : PASS
6866 13:27:22.141878 RX DQ/DQS(Engine): PASS
6867 13:27:22.144244 TX OE : NO K
6868 13:27:22.144629 All Pass.
6869 13:27:22.145008
6870 13:27:22.148415 DramC Write-DBI off
6871 13:27:22.151194 PER_BANK_REFRESH: Hybrid Mode
6872 13:27:22.151594 TX_TRACKING: ON
6873 13:27:22.161320 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6874 13:27:22.164146 [FAST_K] Save calibration result to emmc
6875 13:27:22.167527 dramc_set_vcore_voltage set vcore to 725000
6876 13:27:22.170793 Read voltage for 1600, 0
6877 13:27:22.171179 Vio18 = 0
6878 13:27:22.171476 Vcore = 725000
6879 13:27:22.174355 Vdram = 0
6880 13:27:22.174738 Vddq = 0
6881 13:27:22.175049 Vmddr = 0
6882 13:27:22.180973 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6883 13:27:22.184146 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6884 13:27:22.187855 MEM_TYPE=3, freq_sel=13
6885 13:27:22.191587 sv_algorithm_assistance_LP4_3733
6886 13:27:22.193815 ============ PULL DRAM RESETB DOWN ============
6887 13:27:22.197594 ========== PULL DRAM RESETB DOWN end =========
6888 13:27:22.204510 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6889 13:27:22.207683 ===================================
6890 13:27:22.210737 LPDDR4 DRAM CONFIGURATION
6891 13:27:22.214030 ===================================
6892 13:27:22.214561 EX_ROW_EN[0] = 0x0
6893 13:27:22.217492 EX_ROW_EN[1] = 0x0
6894 13:27:22.217921 LP4Y_EN = 0x0
6895 13:27:22.220604 WORK_FSP = 0x1
6896 13:27:22.221110 WL = 0x5
6897 13:27:22.224118 RL = 0x5
6898 13:27:22.224624 BL = 0x2
6899 13:27:22.227039 RPST = 0x0
6900 13:27:22.227547 RD_PRE = 0x0
6901 13:27:22.230405 WR_PRE = 0x1
6902 13:27:22.230833 WR_PST = 0x1
6903 13:27:22.233686 DBI_WR = 0x0
6904 13:27:22.237071 DBI_RD = 0x0
6905 13:27:22.237638 OTF = 0x1
6906 13:27:22.240717 ===================================
6907 13:27:22.243565 ===================================
6908 13:27:22.244091 ANA top config
6909 13:27:22.246911 ===================================
6910 13:27:22.250354 DLL_ASYNC_EN = 0
6911 13:27:22.253964 ALL_SLAVE_EN = 0
6912 13:27:22.256827 NEW_RANK_MODE = 1
6913 13:27:22.260605 DLL_IDLE_MODE = 1
6914 13:27:22.261112 LP45_APHY_COMB_EN = 1
6915 13:27:22.263749 TX_ODT_DIS = 0
6916 13:27:22.266985 NEW_8X_MODE = 1
6917 13:27:22.270168 ===================================
6918 13:27:22.273191 ===================================
6919 13:27:22.276701 data_rate = 3200
6920 13:27:22.280048 CKR = 1
6921 13:27:22.280589 DQ_P2S_RATIO = 8
6922 13:27:22.283403 ===================================
6923 13:27:22.286495 CA_P2S_RATIO = 8
6924 13:27:22.290129 DQ_CA_OPEN = 0
6925 13:27:22.293567 DQ_SEMI_OPEN = 0
6926 13:27:22.296630 CA_SEMI_OPEN = 0
6927 13:27:22.299818 CA_FULL_RATE = 0
6928 13:27:22.300332 DQ_CKDIV4_EN = 0
6929 13:27:22.303488 CA_CKDIV4_EN = 0
6930 13:27:22.306570 CA_PREDIV_EN = 0
6931 13:27:22.310121 PH8_DLY = 12
6932 13:27:22.312848 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6933 13:27:22.316659 DQ_AAMCK_DIV = 4
6934 13:27:22.317168 CA_AAMCK_DIV = 4
6935 13:27:22.319725 CA_ADMCK_DIV = 4
6936 13:27:22.323473 DQ_TRACK_CA_EN = 0
6937 13:27:22.326168 CA_PICK = 1600
6938 13:27:22.329909 CA_MCKIO = 1600
6939 13:27:22.333374 MCKIO_SEMI = 0
6940 13:27:22.337470 PLL_FREQ = 3068
6941 13:27:22.337982 DQ_UI_PI_RATIO = 32
6942 13:27:22.339916 CA_UI_PI_RATIO = 0
6943 13:27:22.343279 ===================================
6944 13:27:22.346604 ===================================
6945 13:27:22.350159 memory_type:LPDDR4
6946 13:27:22.352989 GP_NUM : 10
6947 13:27:22.353539 SRAM_EN : 1
6948 13:27:22.356892 MD32_EN : 0
6949 13:27:22.359720 ===================================
6950 13:27:22.362885 [ANA_INIT] >>>>>>>>>>>>>>
6951 13:27:22.363320 <<<<<< [CONFIGURE PHASE]: ANA_TX
6952 13:27:22.369879 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6953 13:27:22.370391 ===================================
6954 13:27:22.372930 data_rate = 3200,PCW = 0X7600
6955 13:27:22.376200 ===================================
6956 13:27:22.379599 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6957 13:27:22.386560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6958 13:27:22.393017 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6959 13:27:22.396439 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6960 13:27:22.399458 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6961 13:27:22.402646 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6962 13:27:22.406036 [ANA_INIT] flow start
6963 13:27:22.406467 [ANA_INIT] PLL >>>>>>>>
6964 13:27:22.409581 [ANA_INIT] PLL <<<<<<<<
6965 13:27:22.412921 [ANA_INIT] MIDPI >>>>>>>>
6966 13:27:22.415884 [ANA_INIT] MIDPI <<<<<<<<
6967 13:27:22.416382 [ANA_INIT] DLL >>>>>>>>
6968 13:27:22.419256 [ANA_INIT] DLL <<<<<<<<
6969 13:27:22.422255 [ANA_INIT] flow end
6970 13:27:22.425762 ============ LP4 DIFF to SE enter ============
6971 13:27:22.429095 ============ LP4 DIFF to SE exit ============
6972 13:27:22.432303 [ANA_INIT] <<<<<<<<<<<<<
6973 13:27:22.435754 [Flow] Enable top DCM control >>>>>
6974 13:27:22.439756 [Flow] Enable top DCM control <<<<<
6975 13:27:22.440141 Enable DLL master slave shuffle
6976 13:27:22.445777 ==============================================================
6977 13:27:22.449742 Gating Mode config
6978 13:27:22.452570 ==============================================================
6979 13:27:22.456376 Config description:
6980 13:27:22.466127 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6981 13:27:22.472921 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6982 13:27:22.475690 SELPH_MODE 0: By rank 1: By Phase
6983 13:27:22.482582 ==============================================================
6984 13:27:22.486129 GAT_TRACK_EN = 1
6985 13:27:22.489386 RX_GATING_MODE = 2
6986 13:27:22.492889 RX_GATING_TRACK_MODE = 2
6987 13:27:22.495901 SELPH_MODE = 1
6988 13:27:22.496410 PICG_EARLY_EN = 1
6989 13:27:22.498847 VALID_LAT_VALUE = 1
6990 13:27:22.505553 ==============================================================
6991 13:27:22.508757 Enter into Gating configuration >>>>
6992 13:27:22.512467 Exit from Gating configuration <<<<
6993 13:27:22.515585 Enter into DVFS_PRE_config >>>>>
6994 13:27:22.526057 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6995 13:27:22.528851 Exit from DVFS_PRE_config <<<<<
6996 13:27:22.531978 Enter into PICG configuration >>>>
6997 13:27:22.535479 Exit from PICG configuration <<<<
6998 13:27:22.539207 [RX_INPUT] configuration >>>>>
6999 13:27:22.542173 [RX_INPUT] configuration <<<<<
7000 13:27:22.545373 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7001 13:27:22.552345 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7002 13:27:22.558500 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7003 13:27:22.565218 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7004 13:27:22.572162 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7005 13:27:22.578577 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7006 13:27:22.582002 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7007 13:27:22.585183 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7008 13:27:22.588616 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7009 13:27:22.595458 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7010 13:27:22.598552 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7011 13:27:22.601701 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7012 13:27:22.605283 ===================================
7013 13:27:22.608856 LPDDR4 DRAM CONFIGURATION
7014 13:27:22.611625 ===================================
7015 13:27:22.612128 EX_ROW_EN[0] = 0x0
7016 13:27:22.615188 EX_ROW_EN[1] = 0x0
7017 13:27:22.615609 LP4Y_EN = 0x0
7018 13:27:22.618204 WORK_FSP = 0x1
7019 13:27:22.618629 WL = 0x5
7020 13:27:22.621956 RL = 0x5
7021 13:27:22.625285 BL = 0x2
7022 13:27:22.625708 RPST = 0x0
7023 13:27:22.628138 RD_PRE = 0x0
7024 13:27:22.628623 WR_PRE = 0x1
7025 13:27:22.631750 WR_PST = 0x1
7026 13:27:22.632169 DBI_WR = 0x0
7027 13:27:22.634744 DBI_RD = 0x0
7028 13:27:22.635210 OTF = 0x1
7029 13:27:22.638495 ===================================
7030 13:27:22.641944 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7031 13:27:22.648002 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7032 13:27:22.651638 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7033 13:27:22.655261 ===================================
7034 13:27:22.658073 LPDDR4 DRAM CONFIGURATION
7035 13:27:22.661588 ===================================
7036 13:27:22.662097 EX_ROW_EN[0] = 0x10
7037 13:27:22.664822 EX_ROW_EN[1] = 0x0
7038 13:27:22.665287 LP4Y_EN = 0x0
7039 13:27:22.668552 WORK_FSP = 0x1
7040 13:27:22.669059 WL = 0x5
7041 13:27:22.671491 RL = 0x5
7042 13:27:22.671911 BL = 0x2
7043 13:27:22.674944 RPST = 0x0
7044 13:27:22.677975 RD_PRE = 0x0
7045 13:27:22.678478 WR_PRE = 0x1
7046 13:27:22.681584 WR_PST = 0x1
7047 13:27:22.682091 DBI_WR = 0x0
7048 13:27:22.684990 DBI_RD = 0x0
7049 13:27:22.685525 OTF = 0x1
7050 13:27:22.687985 ===================================
7051 13:27:22.694508 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7052 13:27:22.695029 ==
7053 13:27:22.697782 Dram Type= 6, Freq= 0, CH_0, rank 0
7054 13:27:22.701299 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7055 13:27:22.701818 ==
7056 13:27:22.704694 [Duty_Offset_Calibration]
7057 13:27:22.707931 B0:0 B1:2 CA:1
7058 13:27:22.708357
7059 13:27:22.710892 [DutyScan_Calibration_Flow] k_type=0
7060 13:27:22.719161
7061 13:27:22.719236 ==CLK 0==
7062 13:27:22.721924 Final CLK duty delay cell = 0
7063 13:27:22.725528 [0] MAX Duty = 5156%(X100), DQS PI = 22
7064 13:27:22.729047 [0] MIN Duty = 4938%(X100), DQS PI = 50
7065 13:27:22.729113 [0] AVG Duty = 5047%(X100)
7066 13:27:22.732397
7067 13:27:22.735898 CH0 CLK Duty spec in!! Max-Min= 218%
7068 13:27:22.738950 [DutyScan_Calibration_Flow] ====Done====
7069 13:27:22.739093
7070 13:27:22.742363 [DutyScan_Calibration_Flow] k_type=1
7071 13:27:22.759271
7072 13:27:22.759446 ==DQS 0 ==
7073 13:27:22.762462 Final DQS duty delay cell = 0
7074 13:27:22.765815 [0] MAX Duty = 5125%(X100), DQS PI = 34
7075 13:27:22.769080 [0] MIN Duty = 5031%(X100), DQS PI = 8
7076 13:27:22.772500 [0] AVG Duty = 5078%(X100)
7077 13:27:22.772727
7078 13:27:22.772861 ==DQS 1 ==
7079 13:27:22.775804 Final DQS duty delay cell = 0
7080 13:27:22.779466 [0] MAX Duty = 5031%(X100), DQS PI = 2
7081 13:27:22.782363 [0] MIN Duty = 4876%(X100), DQS PI = 18
7082 13:27:22.785707 [0] AVG Duty = 4953%(X100)
7083 13:27:22.786036
7084 13:27:22.789477 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7085 13:27:22.789830
7086 13:27:22.792599 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7087 13:27:22.796441 [DutyScan_Calibration_Flow] ====Done====
7088 13:27:22.796947
7089 13:27:22.799099 [DutyScan_Calibration_Flow] k_type=3
7090 13:27:22.816663
7091 13:27:22.817165 ==DQM 0 ==
7092 13:27:22.819642 Final DQM duty delay cell = 0
7093 13:27:22.823003 [0] MAX Duty = 5187%(X100), DQS PI = 24
7094 13:27:22.826377 [0] MIN Duty = 4907%(X100), DQS PI = 42
7095 13:27:22.830115 [0] AVG Duty = 5047%(X100)
7096 13:27:22.830652
7097 13:27:22.830994 ==DQM 1 ==
7098 13:27:22.832815 Final DQM duty delay cell = 0
7099 13:27:22.836344 [0] MAX Duty = 5031%(X100), DQS PI = 52
7100 13:27:22.839634 [0] MIN Duty = 4782%(X100), DQS PI = 12
7101 13:27:22.842584 [0] AVG Duty = 4906%(X100)
7102 13:27:22.843009
7103 13:27:22.846082 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7104 13:27:22.846586
7105 13:27:22.849604 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7106 13:27:22.853484 [DutyScan_Calibration_Flow] ====Done====
7107 13:27:22.853998
7108 13:27:22.856276 [DutyScan_Calibration_Flow] k_type=2
7109 13:27:22.873542
7110 13:27:22.874048 ==DQ 0 ==
7111 13:27:22.876243 Final DQ duty delay cell = 0
7112 13:27:22.879461 [0] MAX Duty = 5218%(X100), DQS PI = 18
7113 13:27:22.883270 [0] MIN Duty = 4938%(X100), DQS PI = 56
7114 13:27:22.883781 [0] AVG Duty = 5078%(X100)
7115 13:27:22.886027
7116 13:27:22.886529 ==DQ 1 ==
7117 13:27:22.889428 Final DQ duty delay cell = -4
7118 13:27:22.893505 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7119 13:27:22.896863 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7120 13:27:22.899252 [-4] AVG Duty = 4953%(X100)
7121 13:27:22.899677
7122 13:27:22.902908 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7123 13:27:22.903406
7124 13:27:22.905904 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7125 13:27:22.909542 [DutyScan_Calibration_Flow] ====Done====
7126 13:27:22.909966 ==
7127 13:27:22.912385 Dram Type= 6, Freq= 0, CH_1, rank 0
7128 13:27:22.916250 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7129 13:27:22.916756 ==
7130 13:27:22.918750 [Duty_Offset_Calibration]
7131 13:27:22.919226 B0:0 B1:4 CA:-5
7132 13:27:22.919636
7133 13:27:22.922261 [DutyScan_Calibration_Flow] k_type=0
7134 13:27:22.933594
7135 13:27:22.934147 ==CLK 0==
7136 13:27:22.936972 Final CLK duty delay cell = 0
7137 13:27:22.940183 [0] MAX Duty = 5125%(X100), DQS PI = 44
7138 13:27:22.943285 [0] MIN Duty = 4938%(X100), DQS PI = 12
7139 13:27:22.946843 [0] AVG Duty = 5031%(X100)
7140 13:27:22.947268
7141 13:27:22.949534 CH1 CLK Duty spec in!! Max-Min= 187%
7142 13:27:22.952823 [DutyScan_Calibration_Flow] ====Done====
7143 13:27:22.953287
7144 13:27:22.956481 [DutyScan_Calibration_Flow] k_type=1
7145 13:27:22.972148
7146 13:27:22.972789 ==DQS 0 ==
7147 13:27:22.975487 Final DQS duty delay cell = 0
7148 13:27:22.979246 [0] MAX Duty = 5124%(X100), DQS PI = 46
7149 13:27:22.982560 [0] MIN Duty = 4907%(X100), DQS PI = 8
7150 13:27:22.982989 [0] AVG Duty = 5015%(X100)
7151 13:27:22.985671
7152 13:27:22.986125 ==DQS 1 ==
7153 13:27:22.988714 Final DQS duty delay cell = -4
7154 13:27:22.992358 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7155 13:27:22.995850 [-4] MIN Duty = 4875%(X100), DQS PI = 8
7156 13:27:22.999407 [-4] AVG Duty = 4922%(X100)
7157 13:27:22.999798
7158 13:27:23.001927 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7159 13:27:23.002319
7160 13:27:23.005387 CH1 DQS 1 Duty spec in!! Max-Min= 94%
7161 13:27:23.008743 [DutyScan_Calibration_Flow] ====Done====
7162 13:27:23.009343
7163 13:27:23.012300 [DutyScan_Calibration_Flow] k_type=3
7164 13:27:23.027706
7165 13:27:23.028230 ==DQM 0 ==
7166 13:27:23.031277 Final DQM duty delay cell = -4
7167 13:27:23.034159 [-4] MAX Duty = 5031%(X100), DQS PI = 0
7168 13:27:23.037748 [-4] MIN Duty = 4782%(X100), DQS PI = 10
7169 13:27:23.041161 [-4] AVG Duty = 4906%(X100)
7170 13:27:23.041611
7171 13:27:23.041913 ==DQM 1 ==
7172 13:27:23.044026 Final DQM duty delay cell = -4
7173 13:27:23.047355 [-4] MAX Duty = 5031%(X100), DQS PI = 34
7174 13:27:23.050707 [-4] MIN Duty = 4907%(X100), DQS PI = 6
7175 13:27:23.053811 [-4] AVG Duty = 4969%(X100)
7176 13:27:23.054266
7177 13:27:23.057320 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7178 13:27:23.057717
7179 13:27:23.060782 CH1 DQM 1 Duty spec in!! Max-Min= 124%
7180 13:27:23.063902 [DutyScan_Calibration_Flow] ====Done====
7181 13:27:23.064286
7182 13:27:23.067559 [DutyScan_Calibration_Flow] k_type=2
7183 13:27:23.085426
7184 13:27:23.085923 ==DQ 0 ==
7185 13:27:23.088445 Final DQ duty delay cell = 0
7186 13:27:23.092241 [0] MAX Duty = 5093%(X100), DQS PI = 24
7187 13:27:23.094997 [0] MIN Duty = 4969%(X100), DQS PI = 14
7188 13:27:23.095425 [0] AVG Duty = 5031%(X100)
7189 13:27:23.098485
7190 13:27:23.099333 ==DQ 1 ==
7191 13:27:23.101702 Final DQ duty delay cell = 0
7192 13:27:23.104892 [0] MAX Duty = 5062%(X100), DQS PI = 22
7193 13:27:23.108356 [0] MIN Duty = 4844%(X100), DQS PI = 56
7194 13:27:23.108800 [0] AVG Duty = 4953%(X100)
7195 13:27:23.111570
7196 13:27:23.114848 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7197 13:27:23.115278
7198 13:27:23.118091 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7199 13:27:23.121547 [DutyScan_Calibration_Flow] ====Done====
7200 13:27:23.124925 nWR fixed to 30
7201 13:27:23.128080 [ModeRegInit_LP4] CH0 RK0
7202 13:27:23.128469 [ModeRegInit_LP4] CH0 RK1
7203 13:27:23.131645 [ModeRegInit_LP4] CH1 RK0
7204 13:27:23.134464 [ModeRegInit_LP4] CH1 RK1
7205 13:27:23.134851 match AC timing 4
7206 13:27:23.141417 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7207 13:27:23.144943 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7208 13:27:23.148034 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7209 13:27:23.154504 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7210 13:27:23.157613 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7211 13:27:23.158045 [MiockJmeterHQA]
7212 13:27:23.158377
7213 13:27:23.161170 [DramcMiockJmeter] u1RxGatingPI = 0
7214 13:27:23.164208 0 : 4254, 4029
7215 13:27:23.164649 4 : 4253, 4026
7216 13:27:23.167768 8 : 4253, 4027
7217 13:27:23.168207 12 : 4252, 4027
7218 13:27:23.168549 16 : 4363, 4138
7219 13:27:23.171098 20 : 4252, 4027
7220 13:27:23.171616 24 : 4252, 4027
7221 13:27:23.174236 28 : 4253, 4026
7222 13:27:23.174678 32 : 4255, 4030
7223 13:27:23.177645 36 : 4252, 4027
7224 13:27:23.178085 40 : 4253, 4027
7225 13:27:23.181082 44 : 4366, 4140
7226 13:27:23.181651 48 : 4252, 4027
7227 13:27:23.184405 52 : 4255, 4029
7228 13:27:23.184847 56 : 4250, 4026
7229 13:27:23.185193 60 : 4361, 4137
7230 13:27:23.187739 64 : 4250, 4027
7231 13:27:23.188181 68 : 4361, 4137
7232 13:27:23.190785 72 : 4250, 4027
7233 13:27:23.191228 76 : 4250, 4026
7234 13:27:23.194155 80 : 4250, 4026
7235 13:27:23.194597 84 : 4252, 4030
7236 13:27:23.197744 88 : 4361, 4137
7237 13:27:23.198305 92 : 4250, 4027
7238 13:27:23.198656 96 : 4360, 4137
7239 13:27:23.200942 100 : 4250, 2078
7240 13:27:23.201436 104 : 4361, 0
7241 13:27:23.203774 108 : 4360, 0
7242 13:27:23.204447 112 : 4247, 0
7243 13:27:23.204860 116 : 4250, 0
7244 13:27:23.207722 120 : 4250, 0
7245 13:27:23.208162 124 : 4249, 0
7246 13:27:23.210443 128 : 4250, 0
7247 13:27:23.210880 132 : 4250, 0
7248 13:27:23.211221 136 : 4249, 0
7249 13:27:23.213945 140 : 4250, 0
7250 13:27:23.214412 144 : 4361, 0
7251 13:27:23.217121 148 : 4249, 0
7252 13:27:23.217571 152 : 4250, 0
7253 13:27:23.217886 156 : 4250, 0
7254 13:27:23.220361 160 : 4360, 0
7255 13:27:23.220755 164 : 4360, 0
7256 13:27:23.224058 168 : 4250, 0
7257 13:27:23.224530 172 : 4250, 0
7258 13:27:23.224842 176 : 4361, 0
7259 13:27:23.227077 180 : 4250, 0
7260 13:27:23.227478 184 : 4250, 0
7261 13:27:23.227792 188 : 4249, 0
7262 13:27:23.230610 192 : 4249, 0
7263 13:27:23.231007 196 : 4361, 0
7264 13:27:23.233561 200 : 4249, 0
7265 13:27:23.233960 204 : 4250, 0
7266 13:27:23.234274 208 : 4250, 0
7267 13:27:23.236869 212 : 4250, 0
7268 13:27:23.237297 216 : 4249, 0
7269 13:27:23.240571 220 : 4250, 366
7270 13:27:23.240969 224 : 4249, 3950
7271 13:27:23.244257 228 : 4250, 4027
7272 13:27:23.244726 232 : 4361, 4138
7273 13:27:23.245036 236 : 4250, 4027
7274 13:27:23.247279 240 : 4360, 4138
7275 13:27:23.247681 244 : 4249, 4027
7276 13:27:23.250714 248 : 4250, 4026
7277 13:27:23.251189 252 : 4250, 4027
7278 13:27:23.253966 256 : 4252, 4030
7279 13:27:23.254378 260 : 4249, 4027
7280 13:27:23.257150 264 : 4250, 4026
7281 13:27:23.257660 268 : 4250, 4027
7282 13:27:23.260390 272 : 4252, 4030
7283 13:27:23.260789 276 : 4249, 4027
7284 13:27:23.263699 280 : 4360, 4137
7285 13:27:23.264096 284 : 4361, 4137
7286 13:27:23.266861 288 : 4250, 4027
7287 13:27:23.267261 292 : 4363, 4140
7288 13:27:23.270729 296 : 4249, 4027
7289 13:27:23.271210 300 : 4250, 4026
7290 13:27:23.271524 304 : 4250, 4027
7291 13:27:23.273727 308 : 4252, 4030
7292 13:27:23.274246 312 : 4249, 4027
7293 13:27:23.276916 316 : 4250, 4026
7294 13:27:23.277336 320 : 4250, 4027
7295 13:27:23.280939 324 : 4252, 4030
7296 13:27:23.281463 328 : 4249, 4027
7297 13:27:23.283484 332 : 4360, 4137
7298 13:27:23.283879 336 : 4361, 4060
7299 13:27:23.286641 340 : 4250, 2064
7300 13:27:23.287037
7301 13:27:23.287342 MIOCK jitter meter ch=0
7302 13:27:23.287637
7303 13:27:23.290196 1T = (340-100) = 240 dly cells
7304 13:27:23.296753 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7305 13:27:23.297248 ==
7306 13:27:23.300316 Dram Type= 6, Freq= 0, CH_0, rank 0
7307 13:27:23.303656 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7308 13:27:23.304216 ==
7309 13:27:23.310255 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7310 13:27:23.313892 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7311 13:27:23.316909 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7312 13:27:23.323388 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7313 13:27:23.332436 [CA 0] Center 42 (12~73) winsize 62
7314 13:27:23.335611 [CA 1] Center 42 (12~73) winsize 62
7315 13:27:23.339186 [CA 2] Center 39 (9~69) winsize 61
7316 13:27:23.342341 [CA 3] Center 38 (9~68) winsize 60
7317 13:27:23.345706 [CA 4] Center 36 (6~67) winsize 62
7318 13:27:23.349077 [CA 5] Center 36 (6~66) winsize 61
7319 13:27:23.349560
7320 13:27:23.352109 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7321 13:27:23.352612
7322 13:27:23.358681 [CATrainingPosCal] consider 1 rank data
7323 13:27:23.359180 u2DelayCellTimex100 = 271/100 ps
7324 13:27:23.365974 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7325 13:27:23.368926 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7326 13:27:23.372446 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7327 13:27:23.375926 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7328 13:27:23.378486 CA4 delay=36 (6~67),Diff = 0 PI (0 cell)
7329 13:27:23.381833 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7330 13:27:23.382267
7331 13:27:23.385081 CA PerBit enable=1, Macro0, CA PI delay=36
7332 13:27:23.385600
7333 13:27:23.388903 [CBTSetCACLKResult] CA Dly = 36
7334 13:27:23.392169 CS Dly: 10 (0~41)
7335 13:27:23.395499 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7336 13:27:23.398902 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7337 13:27:23.399414 ==
7338 13:27:23.402181 Dram Type= 6, Freq= 0, CH_0, rank 1
7339 13:27:23.408807 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7340 13:27:23.409536 ==
7341 13:27:23.411788 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7342 13:27:23.418719 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7343 13:27:23.421857 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7344 13:27:23.428110 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7345 13:27:23.435452 [CA 0] Center 42 (12~73) winsize 62
7346 13:27:23.438708 [CA 1] Center 41 (11~72) winsize 62
7347 13:27:23.441803 [CA 2] Center 38 (9~68) winsize 60
7348 13:27:23.445221 [CA 3] Center 37 (7~67) winsize 61
7349 13:27:23.447970 [CA 4] Center 35 (5~65) winsize 61
7350 13:27:23.451682 [CA 5] Center 35 (5~66) winsize 62
7351 13:27:23.452230
7352 13:27:23.455279 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7353 13:27:23.455790
7354 13:27:23.461442 [CATrainingPosCal] consider 2 rank data
7355 13:27:23.461877 u2DelayCellTimex100 = 271/100 ps
7356 13:27:23.468133 CA0 delay=42 (12~73),Diff = 7 PI (25 cell)
7357 13:27:23.471972 CA1 delay=42 (12~72),Diff = 7 PI (25 cell)
7358 13:27:23.474604 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7359 13:27:23.477991 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7360 13:27:23.481876 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7361 13:27:23.485014 CA5 delay=36 (6~66),Diff = 1 PI (3 cell)
7362 13:27:23.485639
7363 13:27:23.488015 CA PerBit enable=1, Macro0, CA PI delay=35
7364 13:27:23.488443
7365 13:27:23.491388 [CBTSetCACLKResult] CA Dly = 35
7366 13:27:23.494691 CS Dly: 11 (0~43)
7367 13:27:23.498807 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7368 13:27:23.501699 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7369 13:27:23.502218
7370 13:27:23.505174 ----->DramcWriteLeveling(PI) begin...
7371 13:27:23.505644 ==
7372 13:27:23.507878 Dram Type= 6, Freq= 0, CH_0, rank 0
7373 13:27:23.514228 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7374 13:27:23.514661 ==
7375 13:27:23.518123 Write leveling (Byte 0): 28 => 28
7376 13:27:23.521092 Write leveling (Byte 1): 26 => 26
7377 13:27:23.521552 DramcWriteLeveling(PI) end<-----
7378 13:27:23.524323
7379 13:27:23.524744 ==
7380 13:27:23.527596 Dram Type= 6, Freq= 0, CH_0, rank 0
7381 13:27:23.531443 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7382 13:27:23.531870 ==
7383 13:27:23.534457 [Gating] SW mode calibration
7384 13:27:23.540868 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7385 13:27:23.544538 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7386 13:27:23.551084 0 12 0 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
7387 13:27:23.554595 0 12 4 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
7388 13:27:23.557265 0 12 8 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
7389 13:27:23.564196 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7390 13:27:23.567313 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7391 13:27:23.570761 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7392 13:27:23.577469 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7393 13:27:23.580808 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7394 13:27:23.584415 0 13 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
7395 13:27:23.590477 0 13 4 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (1 0)
7396 13:27:23.593876 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7397 13:27:23.597408 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7398 13:27:23.603453 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7399 13:27:23.607310 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7400 13:27:23.610375 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7401 13:27:23.617412 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7402 13:27:23.620154 0 14 0 | B1->B0 | 2323 3c3c | 0 1 | (0 0) (0 0)
7403 13:27:23.623687 0 14 4 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
7404 13:27:23.629847 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7405 13:27:23.633149 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7406 13:27:23.636754 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7407 13:27:23.643016 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7408 13:27:23.646560 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7409 13:27:23.650083 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7410 13:27:23.656299 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7411 13:27:23.659884 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7412 13:27:23.663243 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7413 13:27:23.670285 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7414 13:27:23.673453 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7415 13:27:23.676860 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7416 13:27:23.683097 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7417 13:27:23.686363 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7418 13:27:23.690030 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7419 13:27:23.696376 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7420 13:27:23.700473 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7421 13:27:23.703342 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7422 13:27:23.710541 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7423 13:27:23.712879 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7424 13:27:23.716711 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7425 13:27:23.723029 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7426 13:27:23.725901 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7427 13:27:23.729400 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7428 13:27:23.732511 Total UI for P1: 0, mck2ui 16
7429 13:27:23.735924 best dqsien dly found for B0: ( 1, 1, 0)
7430 13:27:23.742585 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7431 13:27:23.746095 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7432 13:27:23.749539 Total UI for P1: 0, mck2ui 16
7433 13:27:23.752823 best dqsien dly found for B1: ( 1, 1, 6)
7434 13:27:23.756301 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7435 13:27:23.759490 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7436 13:27:23.759992
7437 13:27:23.762746 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7438 13:27:23.766002 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7439 13:27:23.769566 [Gating] SW calibration Done
7440 13:27:23.770074 ==
7441 13:27:23.772490 Dram Type= 6, Freq= 0, CH_0, rank 0
7442 13:27:23.775850 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7443 13:27:23.776360 ==
7444 13:27:23.779398 RX Vref Scan: 0
7445 13:27:23.779919
7446 13:27:23.782146 RX Vref 0 -> 0, step: 1
7447 13:27:23.782575
7448 13:27:23.782906 RX Delay 0 -> 252, step: 8
7449 13:27:23.789395 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
7450 13:27:23.792463 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7451 13:27:23.796262 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7452 13:27:23.799104 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7453 13:27:23.802070 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7454 13:27:23.809032 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7455 13:27:23.812535 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7456 13:27:23.815652 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7457 13:27:23.819145 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7458 13:27:23.822258 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7459 13:27:23.829112 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7460 13:27:23.832179 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7461 13:27:23.835798 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7462 13:27:23.838478 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7463 13:27:23.842246 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7464 13:27:23.848378 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7465 13:27:23.848781 ==
7466 13:27:23.852375 Dram Type= 6, Freq= 0, CH_0, rank 0
7467 13:27:23.855401 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7468 13:27:23.855872 ==
7469 13:27:23.856176 DQS Delay:
7470 13:27:23.858641 DQS0 = 0, DQS1 = 0
7471 13:27:23.859032 DQM Delay:
7472 13:27:23.861611 DQM0 = 131, DQM1 = 124
7473 13:27:23.862004 DQ Delay:
7474 13:27:23.865389 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
7475 13:27:23.868748 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7476 13:27:23.872142 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7477 13:27:23.875602 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7478 13:27:23.879011
7479 13:27:23.879526
7480 13:27:23.879859 ==
7481 13:27:23.881896 Dram Type= 6, Freq= 0, CH_0, rank 0
7482 13:27:23.885818 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7483 13:27:23.886335 ==
7484 13:27:23.886677
7485 13:27:23.886982
7486 13:27:23.888380 TX Vref Scan disable
7487 13:27:23.888809 == TX Byte 0 ==
7488 13:27:23.894981 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7489 13:27:23.898656 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7490 13:27:23.899179 == TX Byte 1 ==
7491 13:27:23.905384 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7492 13:27:23.908889 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7493 13:27:23.909485 ==
7494 13:27:23.911927 Dram Type= 6, Freq= 0, CH_0, rank 0
7495 13:27:23.915000 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7496 13:27:23.915433 ==
7497 13:27:23.928334
7498 13:27:23.931396 TX Vref early break, caculate TX vref
7499 13:27:23.934998 TX Vref=16, minBit 9, minWin=21, winSum=370
7500 13:27:23.938137 TX Vref=18, minBit 9, minWin=22, winSum=384
7501 13:27:23.941565 TX Vref=20, minBit 8, minWin=23, winSum=392
7502 13:27:23.944340 TX Vref=22, minBit 8, minWin=23, winSum=399
7503 13:27:23.947936 TX Vref=24, minBit 9, minWin=24, winSum=408
7504 13:27:23.954623 TX Vref=26, minBit 9, minWin=24, winSum=411
7505 13:27:23.957699 TX Vref=28, minBit 8, minWin=24, winSum=417
7506 13:27:23.961051 TX Vref=30, minBit 8, minWin=24, winSum=409
7507 13:27:23.964498 TX Vref=32, minBit 8, minWin=23, winSum=399
7508 13:27:23.967714 TX Vref=34, minBit 8, minWin=23, winSum=390
7509 13:27:23.974604 [TxChooseVref] Worse bit 8, Min win 24, Win sum 417, Final Vref 28
7510 13:27:23.975091
7511 13:27:23.977409 Final TX Range 0 Vref 28
7512 13:27:23.977806
7513 13:27:23.978233 ==
7514 13:27:23.980820 Dram Type= 6, Freq= 0, CH_0, rank 0
7515 13:27:23.984889 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7516 13:27:23.985396 ==
7517 13:27:23.985702
7518 13:27:23.985979
7519 13:27:23.988017 TX Vref Scan disable
7520 13:27:23.994149 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7521 13:27:23.994605 == TX Byte 0 ==
7522 13:27:23.997979 u2DelayCellOfst[0]=10 cells (3 PI)
7523 13:27:24.000872 u2DelayCellOfst[1]=18 cells (5 PI)
7524 13:27:24.004276 u2DelayCellOfst[2]=14 cells (4 PI)
7525 13:27:24.007495 u2DelayCellOfst[3]=10 cells (3 PI)
7526 13:27:24.010475 u2DelayCellOfst[4]=7 cells (2 PI)
7527 13:27:24.013798 u2DelayCellOfst[5]=0 cells (0 PI)
7528 13:27:24.017844 u2DelayCellOfst[6]=18 cells (5 PI)
7529 13:27:24.020410 u2DelayCellOfst[7]=18 cells (5 PI)
7530 13:27:24.024256 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7531 13:27:24.027200 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7532 13:27:24.030443 == TX Byte 1 ==
7533 13:27:24.033798 u2DelayCellOfst[8]=3 cells (1 PI)
7534 13:27:24.036607 u2DelayCellOfst[9]=0 cells (0 PI)
7535 13:27:24.040202 u2DelayCellOfst[10]=10 cells (3 PI)
7536 13:27:24.040617 u2DelayCellOfst[11]=3 cells (1 PI)
7537 13:27:24.043418 u2DelayCellOfst[12]=14 cells (4 PI)
7538 13:27:24.046618 u2DelayCellOfst[13]=14 cells (4 PI)
7539 13:27:24.049981 u2DelayCellOfst[14]=18 cells (5 PI)
7540 13:27:24.053570 u2DelayCellOfst[15]=14 cells (4 PI)
7541 13:27:24.060017 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7542 13:27:24.063789 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7543 13:27:24.064182 DramC Write-DBI on
7544 13:27:24.064483 ==
7545 13:27:24.066758 Dram Type= 6, Freq= 0, CH_0, rank 0
7546 13:27:24.073762 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7547 13:27:24.074219 ==
7548 13:27:24.074526
7549 13:27:24.074804
7550 13:27:24.075071 TX Vref Scan disable
7551 13:27:24.077752 == TX Byte 0 ==
7552 13:27:24.081009 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7553 13:27:24.084675 == TX Byte 1 ==
7554 13:27:24.087739 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7555 13:27:24.090950 DramC Write-DBI off
7556 13:27:24.091337
7557 13:27:24.091637 [DATLAT]
7558 13:27:24.091917 Freq=1600, CH0 RK0
7559 13:27:24.092184
7560 13:27:24.094025 DATLAT Default: 0xf
7561 13:27:24.094566 0, 0xFFFF, sum = 0
7562 13:27:24.097927 1, 0xFFFF, sum = 0
7563 13:27:24.100929 2, 0xFFFF, sum = 0
7564 13:27:24.101364 3, 0xFFFF, sum = 0
7565 13:27:24.104152 4, 0xFFFF, sum = 0
7566 13:27:24.104620 5, 0xFFFF, sum = 0
7567 13:27:24.107850 6, 0xFFFF, sum = 0
7568 13:27:24.108323 7, 0xFFFF, sum = 0
7569 13:27:24.110464 8, 0xFFFF, sum = 0
7570 13:27:24.110933 9, 0xFFFF, sum = 0
7571 13:27:24.114324 10, 0xFFFF, sum = 0
7572 13:27:24.114736 11, 0xFFFF, sum = 0
7573 13:27:24.117832 12, 0xBFF, sum = 0
7574 13:27:24.118301 13, 0x0, sum = 1
7575 13:27:24.120980 14, 0x0, sum = 2
7576 13:27:24.121418 15, 0x0, sum = 3
7577 13:27:24.123985 16, 0x0, sum = 4
7578 13:27:24.124454 best_step = 14
7579 13:27:24.124757
7580 13:27:24.125036 ==
7581 13:27:24.128005 Dram Type= 6, Freq= 0, CH_0, rank 0
7582 13:27:24.131222 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7583 13:27:24.133874 ==
7584 13:27:24.134344 RX Vref Scan: 1
7585 13:27:24.134651
7586 13:27:24.137467 Set Vref Range= 24 -> 127
7587 13:27:24.137933
7588 13:27:24.140484 RX Vref 24 -> 127, step: 1
7589 13:27:24.140872
7590 13:27:24.141175 RX Delay 11 -> 252, step: 4
7591 13:27:24.141497
7592 13:27:24.144218 Set Vref, RX VrefLevel [Byte0]: 24
7593 13:27:24.146931 [Byte1]: 24
7594 13:27:24.151083
7595 13:27:24.151474 Set Vref, RX VrefLevel [Byte0]: 25
7596 13:27:24.154424 [Byte1]: 25
7597 13:27:24.158859
7598 13:27:24.159250 Set Vref, RX VrefLevel [Byte0]: 26
7599 13:27:24.162000 [Byte1]: 26
7600 13:27:24.165924
7601 13:27:24.166386 Set Vref, RX VrefLevel [Byte0]: 27
7602 13:27:24.169564 [Byte1]: 27
7603 13:27:24.173993
7604 13:27:24.174458 Set Vref, RX VrefLevel [Byte0]: 28
7605 13:27:24.177741 [Byte1]: 28
7606 13:27:24.181796
7607 13:27:24.182258 Set Vref, RX VrefLevel [Byte0]: 29
7608 13:27:24.184855 [Byte1]: 29
7609 13:27:24.189559
7610 13:27:24.190036 Set Vref, RX VrefLevel [Byte0]: 30
7611 13:27:24.192060 [Byte1]: 30
7612 13:27:24.196855
7613 13:27:24.197341 Set Vref, RX VrefLevel [Byte0]: 31
7614 13:27:24.199582 [Byte1]: 31
7615 13:27:24.204259
7616 13:27:24.204760 Set Vref, RX VrefLevel [Byte0]: 32
7617 13:27:24.207692 [Byte1]: 32
7618 13:27:24.211794
7619 13:27:24.212225 Set Vref, RX VrefLevel [Byte0]: 33
7620 13:27:24.214876 [Byte1]: 33
7621 13:27:24.219929
7622 13:27:24.220432 Set Vref, RX VrefLevel [Byte0]: 34
7623 13:27:24.222697 [Byte1]: 34
7624 13:27:24.227703
7625 13:27:24.228092 Set Vref, RX VrefLevel [Byte0]: 35
7626 13:27:24.230495 [Byte1]: 35
7627 13:27:24.234262
7628 13:27:24.234650 Set Vref, RX VrefLevel [Byte0]: 36
7629 13:27:24.237958 [Byte1]: 36
7630 13:27:24.241822
7631 13:27:24.242369 Set Vref, RX VrefLevel [Byte0]: 37
7632 13:27:24.245193 [Byte1]: 37
7633 13:27:24.249695
7634 13:27:24.250089 Set Vref, RX VrefLevel [Byte0]: 38
7635 13:27:24.253121 [Byte1]: 38
7636 13:27:24.257702
7637 13:27:24.258094 Set Vref, RX VrefLevel [Byte0]: 39
7638 13:27:24.260379 [Byte1]: 39
7639 13:27:24.264930
7640 13:27:24.265472 Set Vref, RX VrefLevel [Byte0]: 40
7641 13:27:24.268494 [Byte1]: 40
7642 13:27:24.272888
7643 13:27:24.273320 Set Vref, RX VrefLevel [Byte0]: 41
7644 13:27:24.276165 [Byte1]: 41
7645 13:27:24.280089
7646 13:27:24.280600 Set Vref, RX VrefLevel [Byte0]: 42
7647 13:27:24.283456 [Byte1]: 42
7648 13:27:24.287806
7649 13:27:24.288232 Set Vref, RX VrefLevel [Byte0]: 43
7650 13:27:24.290882 [Byte1]: 43
7651 13:27:24.295806
7652 13:27:24.296264 Set Vref, RX VrefLevel [Byte0]: 44
7653 13:27:24.298931 [Byte1]: 44
7654 13:27:24.303056
7655 13:27:24.303441 Set Vref, RX VrefLevel [Byte0]: 45
7656 13:27:24.306029 [Byte1]: 45
7657 13:27:24.310770
7658 13:27:24.311192 Set Vref, RX VrefLevel [Byte0]: 46
7659 13:27:24.314356 [Byte1]: 46
7660 13:27:24.318453
7661 13:27:24.318841 Set Vref, RX VrefLevel [Byte0]: 47
7662 13:27:24.321728 [Byte1]: 47
7663 13:27:24.325747
7664 13:27:24.326139 Set Vref, RX VrefLevel [Byte0]: 48
7665 13:27:24.329044 [Byte1]: 48
7666 13:27:24.333792
7667 13:27:24.334260 Set Vref, RX VrefLevel [Byte0]: 49
7668 13:27:24.336496 [Byte1]: 49
7669 13:27:24.341112
7670 13:27:24.341572 Set Vref, RX VrefLevel [Byte0]: 50
7671 13:27:24.344391 [Byte1]: 50
7672 13:27:24.348991
7673 13:27:24.349421 Set Vref, RX VrefLevel [Byte0]: 51
7674 13:27:24.351968 [Byte1]: 51
7675 13:27:24.356522
7676 13:27:24.356925 Set Vref, RX VrefLevel [Byte0]: 52
7677 13:27:24.360246 [Byte1]: 52
7678 13:27:24.363956
7679 13:27:24.364345 Set Vref, RX VrefLevel [Byte0]: 53
7680 13:27:24.367927 [Byte1]: 53
7681 13:27:24.371822
7682 13:27:24.372296 Set Vref, RX VrefLevel [Byte0]: 54
7683 13:27:24.374899 [Byte1]: 54
7684 13:27:24.379355
7685 13:27:24.379760 Set Vref, RX VrefLevel [Byte0]: 55
7686 13:27:24.382978 [Byte1]: 55
7687 13:27:24.387009
7688 13:27:24.387423 Set Vref, RX VrefLevel [Byte0]: 56
7689 13:27:24.390067 [Byte1]: 56
7690 13:27:24.394415
7691 13:27:24.394801 Set Vref, RX VrefLevel [Byte0]: 57
7692 13:27:24.397390 [Byte1]: 57
7693 13:27:24.402697
7694 13:27:24.403166 Set Vref, RX VrefLevel [Byte0]: 58
7695 13:27:24.405608 [Byte1]: 58
7696 13:27:24.409835
7697 13:27:24.410302 Set Vref, RX VrefLevel [Byte0]: 59
7698 13:27:24.413045 [Byte1]: 59
7699 13:27:24.417842
7700 13:27:24.418303 Set Vref, RX VrefLevel [Byte0]: 60
7701 13:27:24.420589 [Byte1]: 60
7702 13:27:24.425206
7703 13:27:24.425759 Set Vref, RX VrefLevel [Byte0]: 61
7704 13:27:24.428189 [Byte1]: 61
7705 13:27:24.432793
7706 13:27:24.433358 Set Vref, RX VrefLevel [Byte0]: 62
7707 13:27:24.435963 [Byte1]: 62
7708 13:27:24.440449
7709 13:27:24.441165 Set Vref, RX VrefLevel [Byte0]: 63
7710 13:27:24.443588 [Byte1]: 63
7711 13:27:24.447719
7712 13:27:24.448229 Set Vref, RX VrefLevel [Byte0]: 64
7713 13:27:24.451326 [Byte1]: 64
7714 13:27:24.455200
7715 13:27:24.455586 Set Vref, RX VrefLevel [Byte0]: 65
7716 13:27:24.458659 [Byte1]: 65
7717 13:27:24.462764
7718 13:27:24.463155 Set Vref, RX VrefLevel [Byte0]: 66
7719 13:27:24.465877 [Byte1]: 66
7720 13:27:24.471280
7721 13:27:24.471748 Set Vref, RX VrefLevel [Byte0]: 67
7722 13:27:24.473948 [Byte1]: 67
7723 13:27:24.478045
7724 13:27:24.478515 Set Vref, RX VrefLevel [Byte0]: 68
7725 13:27:24.481270 [Byte1]: 68
7726 13:27:24.485751
7727 13:27:24.486223 Set Vref, RX VrefLevel [Byte0]: 69
7728 13:27:24.489190 [Byte1]: 69
7729 13:27:24.493900
7730 13:27:24.494419 Set Vref, RX VrefLevel [Byte0]: 70
7731 13:27:24.496496 [Byte1]: 70
7732 13:27:24.500980
7733 13:27:24.501463 Set Vref, RX VrefLevel [Byte0]: 71
7734 13:27:24.504851 [Byte1]: 71
7735 13:27:24.508840
7736 13:27:24.509393 Set Vref, RX VrefLevel [Byte0]: 72
7737 13:27:24.512139 [Byte1]: 72
7738 13:27:24.516148
7739 13:27:24.516536 Final RX Vref Byte 0 = 53 to rank0
7740 13:27:24.519842 Final RX Vref Byte 1 = 56 to rank0
7741 13:27:24.522780 Final RX Vref Byte 0 = 53 to rank1
7742 13:27:24.526142 Final RX Vref Byte 1 = 56 to rank1==
7743 13:27:24.529667 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 13:27:24.536472 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7745 13:27:24.536988 ==
7746 13:27:24.537367 DQS Delay:
7747 13:27:24.537676 DQS0 = 0, DQS1 = 0
7748 13:27:24.539303 DQM Delay:
7749 13:27:24.539809 DQM0 = 126, DQM1 = 121
7750 13:27:24.542926 DQ Delay:
7751 13:27:24.545713 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7752 13:27:24.549303 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7753 13:27:24.552436 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7754 13:27:24.555955 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7755 13:27:24.556479
7756 13:27:24.556925
7757 13:27:24.557404
7758 13:27:24.559437 [DramC_TX_OE_Calibration] TA2
7759 13:27:24.561871 Original DQ_B0 (3 6) =30, OEN = 27
7760 13:27:24.565229 Original DQ_B1 (3 6) =30, OEN = 27
7761 13:27:24.568870 24, 0x0, End_B0=24 End_B1=24
7762 13:27:24.568965 25, 0x0, End_B0=25 End_B1=25
7763 13:27:24.572078 26, 0x0, End_B0=26 End_B1=26
7764 13:27:24.575572 27, 0x0, End_B0=27 End_B1=27
7765 13:27:24.579316 28, 0x0, End_B0=28 End_B1=28
7766 13:27:24.582225 29, 0x0, End_B0=29 End_B1=29
7767 13:27:24.582379 30, 0x0, End_B0=30 End_B1=30
7768 13:27:24.586076 31, 0x4141, End_B0=30 End_B1=30
7769 13:27:24.588487 Byte0 end_step=30 best_step=27
7770 13:27:24.592176 Byte1 end_step=30 best_step=27
7771 13:27:24.595546 Byte0 TX OE(2T, 0.5T) = (3, 3)
7772 13:27:24.598892 Byte1 TX OE(2T, 0.5T) = (3, 3)
7773 13:27:24.599124
7774 13:27:24.599255
7775 13:27:24.605478 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7776 13:27:24.608824 CH0 RK0: MR19=303, MR18=1C1C
7777 13:27:24.615792 CH0_RK0: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
7778 13:27:24.616149
7779 13:27:24.619202 ----->DramcWriteLeveling(PI) begin...
7780 13:27:24.619645 ==
7781 13:27:24.622588 Dram Type= 6, Freq= 0, CH_0, rank 1
7782 13:27:24.626150 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7783 13:27:24.626648 ==
7784 13:27:24.628992 Write leveling (Byte 0): 29 => 29
7785 13:27:24.632518 Write leveling (Byte 1): 27 => 27
7786 13:27:24.635960 DramcWriteLeveling(PI) end<-----
7787 13:27:24.636476
7788 13:27:24.636813 ==
7789 13:27:24.639541 Dram Type= 6, Freq= 0, CH_0, rank 1
7790 13:27:24.642248 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7791 13:27:24.642678 ==
7792 13:27:24.645455 [Gating] SW mode calibration
7793 13:27:24.652446 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7794 13:27:24.658643 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7795 13:27:24.662591 0 12 0 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
7796 13:27:24.668877 0 12 4 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7797 13:27:24.671942 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7798 13:27:24.675480 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7799 13:27:24.681837 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7800 13:27:24.685358 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7801 13:27:24.688420 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7802 13:27:24.695096 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7803 13:27:24.698227 0 13 0 | B1->B0 | 3434 2d2d | 1 1 | (1 0) (1 0)
7804 13:27:24.701901 0 13 4 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
7805 13:27:24.705584 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7806 13:27:24.711554 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7807 13:27:24.715067 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7808 13:27:24.718396 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7809 13:27:24.725352 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7810 13:27:24.728050 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7811 13:27:24.731317 0 14 0 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
7812 13:27:24.738563 0 14 4 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7813 13:27:24.742101 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7814 13:27:24.745314 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7815 13:27:24.751725 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7816 13:27:24.754817 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7817 13:27:24.758031 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7818 13:27:24.764426 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7819 13:27:24.768215 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7820 13:27:24.771689 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7821 13:27:24.777883 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7822 13:27:24.781445 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7823 13:27:24.785137 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7824 13:27:24.791175 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7825 13:27:24.794668 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7826 13:27:24.797893 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7827 13:27:24.804292 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7828 13:27:24.807783 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7829 13:27:24.810920 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7830 13:27:24.817921 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7831 13:27:24.820937 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7832 13:27:24.824519 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7833 13:27:24.830918 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7834 13:27:24.834527 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7835 13:27:24.837654 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7836 13:27:24.843817 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7837 13:27:24.847959 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7838 13:27:24.850751 Total UI for P1: 0, mck2ui 16
7839 13:27:24.853712 best dqsien dly found for B0: ( 1, 1, 0)
7840 13:27:24.857131 Total UI for P1: 0, mck2ui 16
7841 13:27:24.860940 best dqsien dly found for B1: ( 1, 1, 2)
7842 13:27:24.863809 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7843 13:27:24.867312 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7844 13:27:24.867728
7845 13:27:24.870874 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7846 13:27:24.873779 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7847 13:27:24.877667 [Gating] SW calibration Done
7848 13:27:24.878058 ==
7849 13:27:24.880618 Dram Type= 6, Freq= 0, CH_0, rank 1
7850 13:27:24.883984 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7851 13:27:24.884375 ==
7852 13:27:24.886934 RX Vref Scan: 0
7853 13:27:24.887321
7854 13:27:24.890297 RX Vref 0 -> 0, step: 1
7855 13:27:24.890688
7856 13:27:24.890990 RX Delay 0 -> 252, step: 8
7857 13:27:24.897188 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7858 13:27:24.900510 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7859 13:27:24.903848 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7860 13:27:24.907032 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7861 13:27:24.910528 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7862 13:27:24.916963 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7863 13:27:24.920409 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7864 13:27:24.923516 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7865 13:27:24.926852 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7866 13:27:24.930469 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7867 13:27:24.937193 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7868 13:27:24.940195 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7869 13:27:24.943312 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7870 13:27:24.947687 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7871 13:27:24.950328 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7872 13:27:24.956887 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7873 13:27:24.957409 ==
7874 13:27:24.960525 Dram Type= 6, Freq= 0, CH_0, rank 1
7875 13:27:24.963572 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7876 13:27:24.964064 ==
7877 13:27:24.964372 DQS Delay:
7878 13:27:24.966372 DQS0 = 0, DQS1 = 0
7879 13:27:24.966761 DQM Delay:
7880 13:27:24.969917 DQM0 = 131, DQM1 = 124
7881 13:27:24.970381 DQ Delay:
7882 13:27:24.973677 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7883 13:27:24.976609 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =143
7884 13:27:24.979700 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7885 13:27:24.983768 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7886 13:27:24.986234
7887 13:27:24.986662
7888 13:27:24.986994 ==
7889 13:27:24.989857 Dram Type= 6, Freq= 0, CH_0, rank 1
7890 13:27:24.993337 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7891 13:27:24.993808 ==
7892 13:27:24.994119
7893 13:27:24.994400
7894 13:27:24.996330 TX Vref Scan disable
7895 13:27:24.996796 == TX Byte 0 ==
7896 13:27:25.003136 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7897 13:27:25.006397 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7898 13:27:25.006865 == TX Byte 1 ==
7899 13:27:25.013067 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7900 13:27:25.016159 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7901 13:27:25.016616 ==
7902 13:27:25.019857 Dram Type= 6, Freq= 0, CH_0, rank 1
7903 13:27:25.023131 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7904 13:27:25.023570 ==
7905 13:27:25.038075
7906 13:27:25.040770 TX Vref early break, caculate TX vref
7907 13:27:25.044202 TX Vref=16, minBit 7, minWin=22, winSum=375
7908 13:27:25.047935 TX Vref=18, minBit 1, minWin=23, winSum=391
7909 13:27:25.051333 TX Vref=20, minBit 1, minWin=23, winSum=396
7910 13:27:25.054393 TX Vref=22, minBit 1, minWin=23, winSum=397
7911 13:27:25.057675 TX Vref=24, minBit 8, minWin=23, winSum=406
7912 13:27:25.064164 TX Vref=26, minBit 1, minWin=25, winSum=411
7913 13:27:25.067002 TX Vref=28, minBit 1, minWin=24, winSum=415
7914 13:27:25.070324 TX Vref=30, minBit 8, minWin=24, winSum=408
7915 13:27:25.074104 TX Vref=32, minBit 7, minWin=24, winSum=402
7916 13:27:25.077493 TX Vref=34, minBit 8, minWin=23, winSum=396
7917 13:27:25.080258 TX Vref=36, minBit 8, minWin=22, winSum=385
7918 13:27:25.086755 [TxChooseVref] Worse bit 1, Min win 25, Win sum 411, Final Vref 26
7919 13:27:25.087220
7920 13:27:25.090437 Final TX Range 0 Vref 26
7921 13:27:25.090925
7922 13:27:25.091234 ==
7923 13:27:25.093891 Dram Type= 6, Freq= 0, CH_0, rank 1
7924 13:27:25.097466 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7925 13:27:25.098002 ==
7926 13:27:25.098343
7927 13:27:25.100930
7928 13:27:25.101412 TX Vref Scan disable
7929 13:27:25.107877 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7930 13:27:25.108355 == TX Byte 0 ==
7931 13:27:25.110202 u2DelayCellOfst[0]=10 cells (3 PI)
7932 13:27:25.113772 u2DelayCellOfst[1]=18 cells (5 PI)
7933 13:27:25.117458 u2DelayCellOfst[2]=14 cells (4 PI)
7934 13:27:25.120671 u2DelayCellOfst[3]=10 cells (3 PI)
7935 13:27:25.123732 u2DelayCellOfst[4]=10 cells (3 PI)
7936 13:27:25.127381 u2DelayCellOfst[5]=0 cells (0 PI)
7937 13:27:25.130064 u2DelayCellOfst[6]=18 cells (5 PI)
7938 13:27:25.133411 u2DelayCellOfst[7]=18 cells (5 PI)
7939 13:27:25.136643 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7940 13:27:25.139856 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7941 13:27:25.143454 == TX Byte 1 ==
7942 13:27:25.147094 u2DelayCellOfst[8]=3 cells (1 PI)
7943 13:27:25.150321 u2DelayCellOfst[9]=0 cells (0 PI)
7944 13:27:25.153416 u2DelayCellOfst[10]=10 cells (3 PI)
7945 13:27:25.156994 u2DelayCellOfst[11]=3 cells (1 PI)
7946 13:27:25.157654 u2DelayCellOfst[12]=14 cells (4 PI)
7947 13:27:25.159819 u2DelayCellOfst[13]=14 cells (4 PI)
7948 13:27:25.162865 u2DelayCellOfst[14]=18 cells (5 PI)
7949 13:27:25.166478 u2DelayCellOfst[15]=14 cells (4 PI)
7950 13:27:25.173007 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7951 13:27:25.176137 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7952 13:27:25.176650 DramC Write-DBI on
7953 13:27:25.179707 ==
7954 13:27:25.182914 Dram Type= 6, Freq= 0, CH_0, rank 1
7955 13:27:25.186304 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7956 13:27:25.186699 ==
7957 13:27:25.187002
7958 13:27:25.187279
7959 13:27:25.189733 TX Vref Scan disable
7960 13:27:25.190125 == TX Byte 0 ==
7961 13:27:25.196659 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7962 13:27:25.197130 == TX Byte 1 ==
7963 13:27:25.200301 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7964 13:27:25.203352 DramC Write-DBI off
7965 13:27:25.203741
7966 13:27:25.204042 [DATLAT]
7967 13:27:25.206547 Freq=1600, CH0 RK1
7968 13:27:25.207013
7969 13:27:25.207316 DATLAT Default: 0xe
7970 13:27:25.209947 0, 0xFFFF, sum = 0
7971 13:27:25.210414 1, 0xFFFF, sum = 0
7972 13:27:25.213385 2, 0xFFFF, sum = 0
7973 13:27:25.213861 3, 0xFFFF, sum = 0
7974 13:27:25.216182 4, 0xFFFF, sum = 0
7975 13:27:25.216580 5, 0xFFFF, sum = 0
7976 13:27:25.219301 6, 0xFFFF, sum = 0
7977 13:27:25.222914 7, 0xFFFF, sum = 0
7978 13:27:25.223460 8, 0xFFFF, sum = 0
7979 13:27:25.226334 9, 0xFFFF, sum = 0
7980 13:27:25.226806 10, 0xFFFF, sum = 0
7981 13:27:25.229543 11, 0xFFFF, sum = 0
7982 13:27:25.229941 12, 0x8FFF, sum = 0
7983 13:27:25.233120 13, 0x0, sum = 1
7984 13:27:25.233636 14, 0x0, sum = 2
7985 13:27:25.236100 15, 0x0, sum = 3
7986 13:27:25.236572 16, 0x0, sum = 4
7987 13:27:25.236883 best_step = 14
7988 13:27:25.239760
7989 13:27:25.240244 ==
7990 13:27:25.242334 Dram Type= 6, Freq= 0, CH_0, rank 1
7991 13:27:25.245690 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7992 13:27:25.246083 ==
7993 13:27:25.246389 RX Vref Scan: 0
7994 13:27:25.246670
7995 13:27:25.249020 RX Vref 0 -> 0, step: 1
7996 13:27:25.249448
7997 13:27:25.252620 RX Delay 11 -> 252, step: 4
7998 13:27:25.256474 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7999 13:27:25.262991 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
8000 13:27:25.265551 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
8001 13:27:25.268978 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8002 13:27:25.272400 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8003 13:27:25.276228 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8004 13:27:25.282472 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8005 13:27:25.285840 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
8006 13:27:25.288640 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
8007 13:27:25.292390 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
8008 13:27:25.296045 iDelay=195, Bit 10, Center 120 (67 ~ 174) 108
8009 13:27:25.302294 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
8010 13:27:25.305335 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
8011 13:27:25.308882 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8012 13:27:25.311871 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8013 13:27:25.315530 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8014 13:27:25.319171 ==
8015 13:27:25.322517 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 13:27:25.325029 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8017 13:27:25.325499 ==
8018 13:27:25.325838 DQS Delay:
8019 13:27:25.328356 DQS0 = 0, DQS1 = 0
8020 13:27:25.328858 DQM Delay:
8021 13:27:25.331920 DQM0 = 128, DQM1 = 120
8022 13:27:25.332429 DQ Delay:
8023 13:27:25.335084 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124
8024 13:27:25.338453 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8025 13:27:25.342086 DQ8 =110, DQ9 =106, DQ10 =120, DQ11 =112
8026 13:27:25.344816 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
8027 13:27:25.345294
8028 13:27:25.345640
8029 13:27:25.345946
8030 13:27:25.348273 [DramC_TX_OE_Calibration] TA2
8031 13:27:25.351931 Original DQ_B0 (3 6) =30, OEN = 27
8032 13:27:25.355972 Original DQ_B1 (3 6) =30, OEN = 27
8033 13:27:25.358439 24, 0x0, End_B0=24 End_B1=24
8034 13:27:25.361336 25, 0x0, End_B0=25 End_B1=25
8035 13:27:25.361736 26, 0x0, End_B0=26 End_B1=26
8036 13:27:25.365043 27, 0x0, End_B0=27 End_B1=27
8037 13:27:25.368150 28, 0x0, End_B0=28 End_B1=28
8038 13:27:25.371363 29, 0x0, End_B0=29 End_B1=29
8039 13:27:25.374709 30, 0x0, End_B0=30 End_B1=30
8040 13:27:25.375108 31, 0x4545, End_B0=30 End_B1=30
8041 13:27:25.378502 Byte0 end_step=30 best_step=27
8042 13:27:25.381106 Byte1 end_step=30 best_step=27
8043 13:27:25.384633 Byte0 TX OE(2T, 0.5T) = (3, 3)
8044 13:27:25.388690 Byte1 TX OE(2T, 0.5T) = (3, 3)
8045 13:27:25.389078
8046 13:27:25.389438
8047 13:27:25.394483 [DQSOSCAuto] RK1, (LSB)MR18= 0x2424, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8048 13:27:25.397808 CH0 RK1: MR19=303, MR18=2424
8049 13:27:25.404342 CH0_RK1: MR19=0x303, MR18=0x2424, DQSOSC=391, MR23=63, INC=24, DEC=16
8050 13:27:25.407755 [RxdqsGatingPostProcess] freq 1600
8051 13:27:25.414645 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8052 13:27:25.417875 Pre-setting of DQS Precalculation
8053 13:27:25.420924 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8054 13:27:25.421380 ==
8055 13:27:25.424465 Dram Type= 6, Freq= 0, CH_1, rank 0
8056 13:27:25.427770 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8057 13:27:25.428408 ==
8058 13:27:25.434965 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8059 13:27:25.437402 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8060 13:27:25.444514 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8061 13:27:25.447572 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8062 13:27:25.457029 [CA 0] Center 41 (11~71) winsize 61
8063 13:27:25.460315 [CA 1] Center 41 (11~72) winsize 62
8064 13:27:25.463289 [CA 2] Center 37 (8~67) winsize 60
8065 13:27:25.466945 [CA 3] Center 36 (7~66) winsize 60
8066 13:27:25.470164 [CA 4] Center 34 (4~64) winsize 61
8067 13:27:25.473162 [CA 5] Center 34 (5~64) winsize 60
8068 13:27:25.473631
8069 13:27:25.476835 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8070 13:27:25.477263
8071 13:27:25.480186 [CATrainingPosCal] consider 1 rank data
8072 13:27:25.483551 u2DelayCellTimex100 = 271/100 ps
8073 13:27:25.489761 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8074 13:27:25.493280 CA1 delay=41 (11~72),Diff = 7 PI (25 cell)
8075 13:27:25.497080 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8076 13:27:25.499864 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8077 13:27:25.503322 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8078 13:27:25.507242 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8079 13:27:25.507712
8080 13:27:25.510153 CA PerBit enable=1, Macro0, CA PI delay=34
8081 13:27:25.510624
8082 13:27:25.513250 [CBTSetCACLKResult] CA Dly = 34
8083 13:27:25.516760 CS Dly: 8 (0~39)
8084 13:27:25.519887 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8085 13:27:25.523599 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8086 13:27:25.524008 ==
8087 13:27:25.526223 Dram Type= 6, Freq= 0, CH_1, rank 1
8088 13:27:25.533216 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8089 13:27:25.533730 ==
8090 13:27:25.536380 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8091 13:27:25.543278 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8092 13:27:25.547101 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8093 13:27:25.552623 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8094 13:27:25.559467 [CA 0] Center 41 (11~71) winsize 61
8095 13:27:25.562705 [CA 1] Center 40 (10~71) winsize 62
8096 13:27:25.565729 [CA 2] Center 36 (7~66) winsize 60
8097 13:27:25.569454 [CA 3] Center 36 (7~65) winsize 59
8098 13:27:25.573005 [CA 4] Center 34 (5~64) winsize 60
8099 13:27:25.575836 [CA 5] Center 34 (4~64) winsize 61
8100 13:27:25.576301
8101 13:27:25.579252 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8102 13:27:25.579643
8103 13:27:25.582947 [CATrainingPosCal] consider 2 rank data
8104 13:27:25.585786 u2DelayCellTimex100 = 271/100 ps
8105 13:27:25.592564 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8106 13:27:25.595726 CA1 delay=41 (11~71),Diff = 7 PI (25 cell)
8107 13:27:25.599192 CA2 delay=37 (8~66),Diff = 3 PI (10 cell)
8108 13:27:25.602310 CA3 delay=36 (7~65),Diff = 2 PI (7 cell)
8109 13:27:25.605619 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
8110 13:27:25.609444 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8111 13:27:25.609914
8112 13:27:25.612591 CA PerBit enable=1, Macro0, CA PI delay=34
8113 13:27:25.613111
8114 13:27:25.615875 [CBTSetCACLKResult] CA Dly = 34
8115 13:27:25.619503 CS Dly: 9 (0~41)
8116 13:27:25.621943 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8117 13:27:25.625653 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8118 13:27:25.626083
8119 13:27:25.628482 ----->DramcWriteLeveling(PI) begin...
8120 13:27:25.628918 ==
8121 13:27:25.631862 Dram Type= 6, Freq= 0, CH_1, rank 0
8122 13:27:25.638611 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8123 13:27:25.639159 ==
8124 13:27:25.641840 Write leveling (Byte 0): 23 => 23
8125 13:27:25.645582 Write leveling (Byte 1): 23 => 23
8126 13:27:25.646084 DramcWriteLeveling(PI) end<-----
8127 13:27:25.646421
8128 13:27:25.648873 ==
8129 13:27:25.651923 Dram Type= 6, Freq= 0, CH_1, rank 0
8130 13:27:25.655672 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8131 13:27:25.656180 ==
8132 13:27:25.658490 [Gating] SW mode calibration
8133 13:27:25.665833 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8134 13:27:25.668734 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8135 13:27:25.675641 0 12 0 | B1->B0 | 2929 3434 | 0 1 | (1 1) (1 1)
8136 13:27:25.678499 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8137 13:27:25.682139 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8138 13:27:25.688601 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8139 13:27:25.691888 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8140 13:27:25.695449 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8141 13:27:25.701922 0 12 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8142 13:27:25.705185 0 12 28 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 0)
8143 13:27:25.708597 0 13 0 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
8144 13:27:25.715576 0 13 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8145 13:27:25.718008 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8146 13:27:25.721940 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8147 13:27:25.728004 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8148 13:27:25.731519 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8149 13:27:25.734643 0 13 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8150 13:27:25.741617 0 13 28 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8151 13:27:25.744935 0 14 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
8152 13:27:25.748011 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8153 13:27:25.754795 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8154 13:27:25.757957 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8155 13:27:25.760982 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8156 13:27:25.768232 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8157 13:27:25.770638 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8158 13:27:25.774152 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8159 13:27:25.781475 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8160 13:27:25.783756 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8161 13:27:25.787384 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8162 13:27:25.793816 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8163 13:27:25.797113 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8164 13:27:25.800487 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8165 13:27:25.807067 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8166 13:27:25.810815 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8167 13:27:25.814395 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8168 13:27:25.820482 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8169 13:27:25.823694 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8170 13:27:25.827456 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8171 13:27:25.833594 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8172 13:27:25.836827 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8173 13:27:25.840641 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8174 13:27:25.847431 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8175 13:27:25.850172 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8176 13:27:25.853481 Total UI for P1: 0, mck2ui 16
8177 13:27:25.856829 best dqsien dly found for B0: ( 1, 0, 26)
8178 13:27:25.860205 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8179 13:27:25.864020 Total UI for P1: 0, mck2ui 16
8180 13:27:25.867124 best dqsien dly found for B1: ( 1, 1, 0)
8181 13:27:25.870102 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8182 13:27:25.873805 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8183 13:27:25.874233
8184 13:27:25.876896 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8185 13:27:25.880668 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8186 13:27:25.884238 [Gating] SW calibration Done
8187 13:27:25.884635 ==
8188 13:27:25.886733 Dram Type= 6, Freq= 0, CH_1, rank 0
8189 13:27:25.893635 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8190 13:27:25.894100 ==
8191 13:27:25.894408 RX Vref Scan: 0
8192 13:27:25.894687
8193 13:27:25.896794 RX Vref 0 -> 0, step: 1
8194 13:27:25.897184
8195 13:27:25.899842 RX Delay 0 -> 252, step: 8
8196 13:27:25.903301 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8197 13:27:25.906878 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8198 13:27:25.909956 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8199 13:27:25.913369 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8200 13:27:25.919844 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8201 13:27:25.923785 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8202 13:27:25.926672 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8203 13:27:25.930470 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8204 13:27:25.933539 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8205 13:27:25.940120 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8206 13:27:25.943293 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8207 13:27:25.946196 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8208 13:27:25.949584 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8209 13:27:25.956473 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8210 13:27:25.959901 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8211 13:27:25.963238 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8212 13:27:25.963667 ==
8213 13:27:25.966432 Dram Type= 6, Freq= 0, CH_1, rank 0
8214 13:27:25.969566 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8215 13:27:25.969996 ==
8216 13:27:25.972997 DQS Delay:
8217 13:27:25.973459 DQS0 = 0, DQS1 = 0
8218 13:27:25.976517 DQM Delay:
8219 13:27:25.977026 DQM0 = 130, DQM1 = 126
8220 13:27:25.977410 DQ Delay:
8221 13:27:25.979719 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8222 13:27:25.986356 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8223 13:27:25.989400 DQ8 =107, DQ9 =119, DQ10 =127, DQ11 =115
8224 13:27:25.992807 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8225 13:27:25.993334
8226 13:27:25.993670
8227 13:27:25.993976 ==
8228 13:27:25.996311 Dram Type= 6, Freq= 0, CH_1, rank 0
8229 13:27:25.999569 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8230 13:27:26.000092 ==
8231 13:27:26.000429
8232 13:27:26.000734
8233 13:27:26.002480 TX Vref Scan disable
8234 13:27:26.006038 == TX Byte 0 ==
8235 13:27:26.009874 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8236 13:27:26.013132 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8237 13:27:26.015893 == TX Byte 1 ==
8238 13:27:26.019485 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8239 13:27:26.022721 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8240 13:27:26.023225 ==
8241 13:27:26.026142 Dram Type= 6, Freq= 0, CH_1, rank 0
8242 13:27:26.029262 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8243 13:27:26.032742 ==
8244 13:27:26.043129
8245 13:27:26.046408 TX Vref early break, caculate TX vref
8246 13:27:26.049648 TX Vref=16, minBit 3, minWin=21, winSum=364
8247 13:27:26.053265 TX Vref=18, minBit 3, minWin=22, winSum=376
8248 13:27:26.056385 TX Vref=20, minBit 0, minWin=23, winSum=383
8249 13:27:26.059847 TX Vref=22, minBit 0, minWin=24, winSum=395
8250 13:27:26.063060 TX Vref=24, minBit 3, minWin=23, winSum=401
8251 13:27:26.069570 TX Vref=26, minBit 0, minWin=25, winSum=409
8252 13:27:26.073294 TX Vref=28, minBit 3, minWin=24, winSum=412
8253 13:27:26.076478 TX Vref=30, minBit 10, minWin=24, winSum=406
8254 13:27:26.079505 TX Vref=32, minBit 0, minWin=24, winSum=397
8255 13:27:26.082963 TX Vref=34, minBit 1, minWin=23, winSum=385
8256 13:27:26.089698 [TxChooseVref] Worse bit 0, Min win 25, Win sum 409, Final Vref 26
8257 13:27:26.090359
8258 13:27:26.093025 Final TX Range 0 Vref 26
8259 13:27:26.093632
8260 13:27:26.093977 ==
8261 13:27:26.096347 Dram Type= 6, Freq= 0, CH_1, rank 0
8262 13:27:26.099552 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8263 13:27:26.100060 ==
8264 13:27:26.100516
8265 13:27:26.100958
8266 13:27:26.102553 TX Vref Scan disable
8267 13:27:26.109460 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8268 13:27:26.109896 == TX Byte 0 ==
8269 13:27:26.112995 u2DelayCellOfst[0]=18 cells (5 PI)
8270 13:27:26.116248 u2DelayCellOfst[1]=10 cells (3 PI)
8271 13:27:26.118922 u2DelayCellOfst[2]=0 cells (0 PI)
8272 13:27:26.122960 u2DelayCellOfst[3]=10 cells (3 PI)
8273 13:27:26.125561 u2DelayCellOfst[4]=10 cells (3 PI)
8274 13:27:26.129248 u2DelayCellOfst[5]=18 cells (5 PI)
8275 13:27:26.132894 u2DelayCellOfst[6]=18 cells (5 PI)
8276 13:27:26.135444 u2DelayCellOfst[7]=7 cells (2 PI)
8277 13:27:26.139493 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8278 13:27:26.142539 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8279 13:27:26.145435 == TX Byte 1 ==
8280 13:27:26.148855 u2DelayCellOfst[8]=0 cells (0 PI)
8281 13:27:26.149434 u2DelayCellOfst[9]=7 cells (2 PI)
8282 13:27:26.152260 u2DelayCellOfst[10]=10 cells (3 PI)
8283 13:27:26.155612 u2DelayCellOfst[11]=3 cells (1 PI)
8284 13:27:26.158778 u2DelayCellOfst[12]=18 cells (5 PI)
8285 13:27:26.162096 u2DelayCellOfst[13]=18 cells (5 PI)
8286 13:27:26.165782 u2DelayCellOfst[14]=21 cells (6 PI)
8287 13:27:26.168539 u2DelayCellOfst[15]=18 cells (5 PI)
8288 13:27:26.175617 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8289 13:27:26.179438 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8290 13:27:26.179953 DramC Write-DBI on
8291 13:27:26.180288 ==
8292 13:27:26.182305 Dram Type= 6, Freq= 0, CH_1, rank 0
8293 13:27:26.189051 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8294 13:27:26.189601 ==
8295 13:27:26.189941
8296 13:27:26.190243
8297 13:27:26.190530 TX Vref Scan disable
8298 13:27:26.192829 == TX Byte 0 ==
8299 13:27:26.196371 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8300 13:27:26.199279 == TX Byte 1 ==
8301 13:27:26.202377 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8302 13:27:26.206420 DramC Write-DBI off
8303 13:27:26.206950
8304 13:27:26.207396 [DATLAT]
8305 13:27:26.207849 Freq=1600, CH1 RK0
8306 13:27:26.208171
8307 13:27:26.208866 DATLAT Default: 0xf
8308 13:27:26.209313 0, 0xFFFF, sum = 0
8309 13:27:26.212514 1, 0xFFFF, sum = 0
8310 13:27:26.215901 2, 0xFFFF, sum = 0
8311 13:27:26.216334 3, 0xFFFF, sum = 0
8312 13:27:26.219096 4, 0xFFFF, sum = 0
8313 13:27:26.219776 5, 0xFFFF, sum = 0
8314 13:27:26.222096 6, 0xFFFF, sum = 0
8315 13:27:26.222532 7, 0xFFFF, sum = 0
8316 13:27:26.225914 8, 0xFFFF, sum = 0
8317 13:27:26.226423 9, 0xFFFF, sum = 0
8318 13:27:26.229049 10, 0xFFFF, sum = 0
8319 13:27:26.229535 11, 0xFFFF, sum = 0
8320 13:27:26.231901 12, 0x8F7F, sum = 0
8321 13:27:26.232331 13, 0x0, sum = 1
8322 13:27:26.235265 14, 0x0, sum = 2
8323 13:27:26.235705 15, 0x0, sum = 3
8324 13:27:26.238758 16, 0x0, sum = 4
8325 13:27:26.239271 best_step = 14
8326 13:27:26.239603
8327 13:27:26.239906 ==
8328 13:27:26.242280 Dram Type= 6, Freq= 0, CH_1, rank 0
8329 13:27:26.249083 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8330 13:27:26.249671 ==
8331 13:27:26.250019 RX Vref Scan: 1
8332 13:27:26.250325
8333 13:27:26.252241 Set Vref Range= 24 -> 127
8334 13:27:26.252667
8335 13:27:26.254980 RX Vref 24 -> 127, step: 1
8336 13:27:26.255410
8337 13:27:26.255743 RX Delay 3 -> 252, step: 4
8338 13:27:26.256051
8339 13:27:26.258589 Set Vref, RX VrefLevel [Byte0]: 24
8340 13:27:26.262137 [Byte1]: 24
8341 13:27:26.266185
8342 13:27:26.266686 Set Vref, RX VrefLevel [Byte0]: 25
8343 13:27:26.268827 [Byte1]: 25
8344 13:27:26.273750
8345 13:27:26.274176 Set Vref, RX VrefLevel [Byte0]: 26
8346 13:27:26.276820 [Byte1]: 26
8347 13:27:26.281325
8348 13:27:26.281830 Set Vref, RX VrefLevel [Byte0]: 27
8349 13:27:26.284943 [Byte1]: 27
8350 13:27:26.288746
8351 13:27:26.289301 Set Vref, RX VrefLevel [Byte0]: 28
8352 13:27:26.292235 [Byte1]: 28
8353 13:27:26.297002
8354 13:27:26.297569 Set Vref, RX VrefLevel [Byte0]: 29
8355 13:27:26.299466 [Byte1]: 29
8356 13:27:26.304558
8357 13:27:26.305103 Set Vref, RX VrefLevel [Byte0]: 30
8358 13:27:26.307541 [Byte1]: 30
8359 13:27:26.312212
8360 13:27:26.312718 Set Vref, RX VrefLevel [Byte0]: 31
8361 13:27:26.318263 [Byte1]: 31
8362 13:27:26.318697
8363 13:27:26.321726 Set Vref, RX VrefLevel [Byte0]: 32
8364 13:27:26.324847 [Byte1]: 32
8365 13:27:26.325304
8366 13:27:26.328489 Set Vref, RX VrefLevel [Byte0]: 33
8367 13:27:26.331480 [Byte1]: 33
8368 13:27:26.334722
8369 13:27:26.335152 Set Vref, RX VrefLevel [Byte0]: 34
8370 13:27:26.338061 [Byte1]: 34
8371 13:27:26.342245
8372 13:27:26.342320 Set Vref, RX VrefLevel [Byte0]: 35
8373 13:27:26.345420 [Byte1]: 35
8374 13:27:26.349531
8375 13:27:26.349605 Set Vref, RX VrefLevel [Byte0]: 36
8376 13:27:26.352892 [Byte1]: 36
8377 13:27:26.357678
8378 13:27:26.357753 Set Vref, RX VrefLevel [Byte0]: 37
8379 13:27:26.360895 [Byte1]: 37
8380 13:27:26.365389
8381 13:27:26.365464 Set Vref, RX VrefLevel [Byte0]: 38
8382 13:27:26.367823 [Byte1]: 38
8383 13:27:26.373107
8384 13:27:26.373276 Set Vref, RX VrefLevel [Byte0]: 39
8385 13:27:26.376204 [Byte1]: 39
8386 13:27:26.380594
8387 13:27:26.380768 Set Vref, RX VrefLevel [Byte0]: 40
8388 13:27:26.383831 [Byte1]: 40
8389 13:27:26.387971
8390 13:27:26.388144 Set Vref, RX VrefLevel [Byte0]: 41
8391 13:27:26.390988 [Byte1]: 41
8392 13:27:26.395679
8393 13:27:26.395802 Set Vref, RX VrefLevel [Byte0]: 42
8394 13:27:26.398885 [Byte1]: 42
8395 13:27:26.403592
8396 13:27:26.403814 Set Vref, RX VrefLevel [Byte0]: 43
8397 13:27:26.407375 [Byte1]: 43
8398 13:27:26.410915
8399 13:27:26.411166 Set Vref, RX VrefLevel [Byte0]: 44
8400 13:27:26.414565 [Byte1]: 44
8401 13:27:26.418544
8402 13:27:26.418817 Set Vref, RX VrefLevel [Byte0]: 45
8403 13:27:26.422588 [Byte1]: 45
8404 13:27:26.426944
8405 13:27:26.427453 Set Vref, RX VrefLevel [Byte0]: 46
8406 13:27:26.429505 [Byte1]: 46
8407 13:27:26.434297
8408 13:27:26.434976 Set Vref, RX VrefLevel [Byte0]: 47
8409 13:27:26.437521 [Byte1]: 47
8410 13:27:26.442014
8411 13:27:26.442527 Set Vref, RX VrefLevel [Byte0]: 48
8412 13:27:26.445149 [Byte1]: 48
8413 13:27:26.449895
8414 13:27:26.450389 Set Vref, RX VrefLevel [Byte0]: 49
8415 13:27:26.452649 [Byte1]: 49
8416 13:27:26.457505
8417 13:27:26.458071 Set Vref, RX VrefLevel [Byte0]: 50
8418 13:27:26.460591 [Byte1]: 50
8419 13:27:26.465077
8420 13:27:26.465534 Set Vref, RX VrefLevel [Byte0]: 51
8421 13:27:26.468218 [Byte1]: 51
8422 13:27:26.472500
8423 13:27:26.472999 Set Vref, RX VrefLevel [Byte0]: 52
8424 13:27:26.476058 [Byte1]: 52
8425 13:27:26.480385
8426 13:27:26.480893 Set Vref, RX VrefLevel [Byte0]: 53
8427 13:27:26.483373 [Byte1]: 53
8428 13:27:26.487932
8429 13:27:26.488435 Set Vref, RX VrefLevel [Byte0]: 54
8430 13:27:26.491227 [Byte1]: 54
8431 13:27:26.495720
8432 13:27:26.496336 Set Vref, RX VrefLevel [Byte0]: 55
8433 13:27:26.498424 [Byte1]: 55
8434 13:27:26.502909
8435 13:27:26.503333 Set Vref, RX VrefLevel [Byte0]: 56
8436 13:27:26.505939 [Byte1]: 56
8437 13:27:26.510535
8438 13:27:26.510956 Set Vref, RX VrefLevel [Byte0]: 57
8439 13:27:26.514132 [Byte1]: 57
8440 13:27:26.518011
8441 13:27:26.518413 Set Vref, RX VrefLevel [Byte0]: 58
8442 13:27:26.521209 [Byte1]: 58
8443 13:27:26.525896
8444 13:27:26.526275 Set Vref, RX VrefLevel [Byte0]: 59
8445 13:27:26.529304 [Byte1]: 59
8446 13:27:26.533157
8447 13:27:26.533419 Set Vref, RX VrefLevel [Byte0]: 60
8448 13:27:26.536823 [Byte1]: 60
8449 13:27:26.540942
8450 13:27:26.541157 Set Vref, RX VrefLevel [Byte0]: 61
8451 13:27:26.544738 [Byte1]: 61
8452 13:27:26.548736
8453 13:27:26.548968 Set Vref, RX VrefLevel [Byte0]: 62
8454 13:27:26.552395 [Byte1]: 62
8455 13:27:26.556539
8456 13:27:26.556850 Set Vref, RX VrefLevel [Byte0]: 63
8457 13:27:26.559844 [Byte1]: 63
8458 13:27:26.564396
8459 13:27:26.564857 Set Vref, RX VrefLevel [Byte0]: 64
8460 13:27:26.567652 [Byte1]: 64
8461 13:27:26.572203
8462 13:27:26.572579 Set Vref, RX VrefLevel [Byte0]: 65
8463 13:27:26.574981 [Byte1]: 65
8464 13:27:26.579830
8465 13:27:26.580210 Set Vref, RX VrefLevel [Byte0]: 66
8466 13:27:26.583089 [Byte1]: 66
8467 13:27:26.587146
8468 13:27:26.587526 Set Vref, RX VrefLevel [Byte0]: 67
8469 13:27:26.590391 [Byte1]: 67
8470 13:27:26.594769
8471 13:27:26.595154 Set Vref, RX VrefLevel [Byte0]: 68
8472 13:27:26.598126 [Byte1]: 68
8473 13:27:26.602899
8474 13:27:26.603359 Set Vref, RX VrefLevel [Byte0]: 69
8475 13:27:26.605564 [Byte1]: 69
8476 13:27:26.610264
8477 13:27:26.610856 Set Vref, RX VrefLevel [Byte0]: 70
8478 13:27:26.613279 [Byte1]: 70
8479 13:27:26.617996
8480 13:27:26.618463 Set Vref, RX VrefLevel [Byte0]: 71
8481 13:27:26.621395 [Byte1]: 71
8482 13:27:26.625570
8483 13:27:26.626038 Set Vref, RX VrefLevel [Byte0]: 72
8484 13:27:26.628620 [Byte1]: 72
8485 13:27:26.633362
8486 13:27:26.633839 Set Vref, RX VrefLevel [Byte0]: 73
8487 13:27:26.636466 [Byte1]: 73
8488 13:27:26.640822
8489 13:27:26.641338 Set Vref, RX VrefLevel [Byte0]: 74
8490 13:27:26.644162 [Byte1]: 74
8491 13:27:26.648313
8492 13:27:26.648693 Set Vref, RX VrefLevel [Byte0]: 75
8493 13:27:26.651999 [Byte1]: 75
8494 13:27:26.656219
8495 13:27:26.656691 Final RX Vref Byte 0 = 63 to rank0
8496 13:27:26.659311 Final RX Vref Byte 1 = 55 to rank0
8497 13:27:26.662624 Final RX Vref Byte 0 = 63 to rank1
8498 13:27:26.666207 Final RX Vref Byte 1 = 55 to rank1==
8499 13:27:26.669080 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 13:27:26.676023 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8501 13:27:26.676489 ==
8502 13:27:26.676798 DQS Delay:
8503 13:27:26.677072 DQS0 = 0, DQS1 = 0
8504 13:27:26.679069 DQM Delay:
8505 13:27:26.679451 DQM0 = 129, DQM1 = 123
8506 13:27:26.682729 DQ Delay:
8507 13:27:26.686153 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =128
8508 13:27:26.689529 DQ4 =130, DQ5 =138, DQ6 =138, DQ7 =124
8509 13:27:26.692997 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =112
8510 13:27:26.696136 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =132
8511 13:27:26.696606
8512 13:27:26.696923
8513 13:27:26.697358
8514 13:27:26.699198 [DramC_TX_OE_Calibration] TA2
8515 13:27:26.702785 Original DQ_B0 (3 6) =30, OEN = 27
8516 13:27:26.706104 Original DQ_B1 (3 6) =30, OEN = 27
8517 13:27:26.709439 24, 0x0, End_B0=24 End_B1=24
8518 13:27:26.709911 25, 0x0, End_B0=25 End_B1=25
8519 13:27:26.712232 26, 0x0, End_B0=26 End_B1=26
8520 13:27:26.716078 27, 0x0, End_B0=27 End_B1=27
8521 13:27:26.719063 28, 0x0, End_B0=28 End_B1=28
8522 13:27:26.722753 29, 0x0, End_B0=29 End_B1=29
8523 13:27:26.723222 30, 0x0, End_B0=30 End_B1=30
8524 13:27:26.725905 31, 0x4141, End_B0=30 End_B1=30
8525 13:27:26.728864 Byte0 end_step=30 best_step=27
8526 13:27:26.732172 Byte1 end_step=30 best_step=27
8527 13:27:26.735654 Byte0 TX OE(2T, 0.5T) = (3, 3)
8528 13:27:26.739146 Byte1 TX OE(2T, 0.5T) = (3, 3)
8529 13:27:26.739607
8530 13:27:26.739954
8531 13:27:26.745600 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b2b, (MSB)MR19= 0x303, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
8532 13:27:26.749128 CH1 RK0: MR19=303, MR18=2B2B
8533 13:27:26.755818 CH1_RK0: MR19=0x303, MR18=0x2B2B, DQSOSC=388, MR23=63, INC=24, DEC=16
8534 13:27:26.756284
8535 13:27:26.758416 ----->DramcWriteLeveling(PI) begin...
8536 13:27:26.758808 ==
8537 13:27:26.762095 Dram Type= 6, Freq= 0, CH_1, rank 1
8538 13:27:26.765284 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8539 13:27:26.765718 ==
8540 13:27:26.768969 Write leveling (Byte 0): 22 => 22
8541 13:27:26.772212 Write leveling (Byte 1): 20 => 20
8542 13:27:26.775529 DramcWriteLeveling(PI) end<-----
8543 13:27:26.775957
8544 13:27:26.776291 ==
8545 13:27:26.778820 Dram Type= 6, Freq= 0, CH_1, rank 1
8546 13:27:26.782275 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8547 13:27:26.782801 ==
8548 13:27:26.785163 [Gating] SW mode calibration
8549 13:27:26.792277 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8550 13:27:26.798449 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8551 13:27:26.801755 0 12 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8552 13:27:26.808319 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8553 13:27:26.812267 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8554 13:27:26.814762 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8555 13:27:26.822126 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8556 13:27:26.825396 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8557 13:27:26.828966 0 12 24 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 1)
8558 13:27:26.835613 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8559 13:27:26.838334 0 13 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8560 13:27:26.841437 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8561 13:27:26.845537 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8562 13:27:26.851512 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8563 13:27:26.854583 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8564 13:27:26.858683 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8565 13:27:26.865049 0 13 24 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8566 13:27:26.867960 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8567 13:27:26.872195 0 14 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8568 13:27:26.878363 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8569 13:27:26.881544 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8570 13:27:26.884840 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8571 13:27:26.891517 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8572 13:27:26.894738 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8573 13:27:26.897724 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8574 13:27:26.905054 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8575 13:27:26.908245 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8576 13:27:26.911862 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8577 13:27:26.917982 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8578 13:27:26.920846 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8579 13:27:26.924993 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8580 13:27:26.931569 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8581 13:27:26.934535 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8582 13:27:26.937669 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8583 13:27:26.944755 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8584 13:27:26.947759 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8585 13:27:26.951075 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8586 13:27:26.957356 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8587 13:27:26.961081 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8588 13:27:26.963999 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8589 13:27:26.970934 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8590 13:27:26.974011 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8591 13:27:26.977470 Total UI for P1: 0, mck2ui 16
8592 13:27:26.980864 best dqsien dly found for B0: ( 1, 0, 24)
8593 13:27:26.983739 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8594 13:27:26.991523 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8595 13:27:26.992029 Total UI for P1: 0, mck2ui 16
8596 13:27:26.997706 best dqsien dly found for B1: ( 1, 0, 30)
8597 13:27:27.000868 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8598 13:27:27.004137 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8599 13:27:27.004733
8600 13:27:27.007936 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8601 13:27:27.010849 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8602 13:27:27.014355 [Gating] SW calibration Done
8603 13:27:27.014778 ==
8604 13:27:27.017412 Dram Type= 6, Freq= 0, CH_1, rank 1
8605 13:27:27.021068 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8606 13:27:27.021651 ==
8607 13:27:27.024409 RX Vref Scan: 0
8608 13:27:27.024909
8609 13:27:27.025334 RX Vref 0 -> 0, step: 1
8610 13:27:27.025765
8611 13:27:27.027788 RX Delay 0 -> 252, step: 8
8612 13:27:27.030439 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8613 13:27:27.034125 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8614 13:27:27.041316 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8615 13:27:27.044025 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8616 13:27:27.046875 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8617 13:27:27.050371 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8618 13:27:27.054157 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8619 13:27:27.060569 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8620 13:27:27.063432 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8621 13:27:27.066966 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8622 13:27:27.069963 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8623 13:27:27.077064 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8624 13:27:27.080431 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8625 13:27:27.083613 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8626 13:27:27.086919 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8627 13:27:27.090359 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8628 13:27:27.093736 ==
8629 13:27:27.094239 Dram Type= 6, Freq= 0, CH_1, rank 1
8630 13:27:27.100618 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8631 13:27:27.101123 ==
8632 13:27:27.101723 DQS Delay:
8633 13:27:27.103423 DQS0 = 0, DQS1 = 0
8634 13:27:27.103848 DQM Delay:
8635 13:27:27.107045 DQM0 = 130, DQM1 = 124
8636 13:27:27.107547 DQ Delay:
8637 13:27:27.110467 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8638 13:27:27.113406 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =127
8639 13:27:27.116296 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8640 13:27:27.119941 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8641 13:27:27.120471
8642 13:27:27.120897
8643 13:27:27.121431 ==
8644 13:27:27.123160 Dram Type= 6, Freq= 0, CH_1, rank 1
8645 13:27:27.129986 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8646 13:27:27.130518 ==
8647 13:27:27.130959
8648 13:27:27.131362
8649 13:27:27.131753 TX Vref Scan disable
8650 13:27:27.133969 == TX Byte 0 ==
8651 13:27:27.136435 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8652 13:27:27.143773 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8653 13:27:27.144295 == TX Byte 1 ==
8654 13:27:27.146853 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8655 13:27:27.153382 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8656 13:27:27.153925 ==
8657 13:27:27.156555 Dram Type= 6, Freq= 0, CH_1, rank 1
8658 13:27:27.160228 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8659 13:27:27.160736 ==
8660 13:27:27.173459
8661 13:27:27.176958 TX Vref early break, caculate TX vref
8662 13:27:27.179624 TX Vref=16, minBit 0, minWin=22, winSum=382
8663 13:27:27.183245 TX Vref=18, minBit 0, minWin=23, winSum=386
8664 13:27:27.186941 TX Vref=20, minBit 7, minWin=23, winSum=397
8665 13:27:27.189382 TX Vref=22, minBit 1, minWin=24, winSum=405
8666 13:27:27.193287 TX Vref=24, minBit 2, minWin=24, winSum=410
8667 13:27:27.199925 TX Vref=26, minBit 0, minWin=25, winSum=422
8668 13:27:27.203076 TX Vref=28, minBit 0, minWin=25, winSum=422
8669 13:27:27.206164 TX Vref=30, minBit 0, minWin=24, winSum=417
8670 13:27:27.209802 TX Vref=32, minBit 0, minWin=25, winSum=412
8671 13:27:27.212462 TX Vref=34, minBit 0, minWin=22, winSum=401
8672 13:27:27.219148 TX Vref=36, minBit 0, minWin=23, winSum=394
8673 13:27:27.222445 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 26
8674 13:27:27.222869
8675 13:27:27.225935 Final TX Range 0 Vref 26
8676 13:27:27.226402
8677 13:27:27.226729 ==
8678 13:27:27.229953 Dram Type= 6, Freq= 0, CH_1, rank 1
8679 13:27:27.232442 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8680 13:27:27.236232 ==
8681 13:27:27.236752
8682 13:27:27.237086
8683 13:27:27.237461 TX Vref Scan disable
8684 13:27:27.242169 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8685 13:27:27.242597 == TX Byte 0 ==
8686 13:27:27.245888 u2DelayCellOfst[0]=18 cells (5 PI)
8687 13:27:27.248943 u2DelayCellOfst[1]=10 cells (3 PI)
8688 13:27:27.252401 u2DelayCellOfst[2]=0 cells (0 PI)
8689 13:27:27.255677 u2DelayCellOfst[3]=10 cells (3 PI)
8690 13:27:27.258897 u2DelayCellOfst[4]=10 cells (3 PI)
8691 13:27:27.262230 u2DelayCellOfst[5]=18 cells (5 PI)
8692 13:27:27.265839 u2DelayCellOfst[6]=18 cells (5 PI)
8693 13:27:27.268685 u2DelayCellOfst[7]=7 cells (2 PI)
8694 13:27:27.271993 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8695 13:27:27.275127 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8696 13:27:27.278340 == TX Byte 1 ==
8697 13:27:27.282222 u2DelayCellOfst[8]=0 cells (0 PI)
8698 13:27:27.285581 u2DelayCellOfst[9]=3 cells (1 PI)
8699 13:27:27.288355 u2DelayCellOfst[10]=10 cells (3 PI)
8700 13:27:27.291719 u2DelayCellOfst[11]=3 cells (1 PI)
8701 13:27:27.295673 u2DelayCellOfst[12]=14 cells (4 PI)
8702 13:27:27.298572 u2DelayCellOfst[13]=18 cells (5 PI)
8703 13:27:27.301277 u2DelayCellOfst[14]=18 cells (5 PI)
8704 13:27:27.304890 u2DelayCellOfst[15]=18 cells (5 PI)
8705 13:27:27.308172 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8706 13:27:27.311314 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8707 13:27:27.314847 DramC Write-DBI on
8708 13:27:27.315404 ==
8709 13:27:27.318024 Dram Type= 6, Freq= 0, CH_1, rank 1
8710 13:27:27.321684 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8711 13:27:27.322158 ==
8712 13:27:27.322496
8713 13:27:27.322797
8714 13:27:27.324549 TX Vref Scan disable
8715 13:27:27.324976 == TX Byte 0 ==
8716 13:27:27.331263 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8717 13:27:27.331774 == TX Byte 1 ==
8718 13:27:27.334985 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8719 13:27:27.338465 DramC Write-DBI off
8720 13:27:27.339053
8721 13:27:27.339395 [DATLAT]
8722 13:27:27.341348 Freq=1600, CH1 RK1
8723 13:27:27.341889
8724 13:27:27.342224 DATLAT Default: 0xe
8725 13:27:27.344710 0, 0xFFFF, sum = 0
8726 13:27:27.345174 1, 0xFFFF, sum = 0
8727 13:27:27.347690 2, 0xFFFF, sum = 0
8728 13:27:27.348304 3, 0xFFFF, sum = 0
8729 13:27:27.351648 4, 0xFFFF, sum = 0
8730 13:27:27.354890 5, 0xFFFF, sum = 0
8731 13:27:27.355328 6, 0xFFFF, sum = 0
8732 13:27:27.357708 7, 0xFFFF, sum = 0
8733 13:27:27.358138 8, 0xFFFF, sum = 0
8734 13:27:27.361188 9, 0xFFFF, sum = 0
8735 13:27:27.361667 10, 0xFFFF, sum = 0
8736 13:27:27.364851 11, 0xFFFF, sum = 0
8737 13:27:27.365323 12, 0xF5F, sum = 0
8738 13:27:27.368160 13, 0x0, sum = 1
8739 13:27:27.368673 14, 0x0, sum = 2
8740 13:27:27.370910 15, 0x0, sum = 3
8741 13:27:27.371359 16, 0x0, sum = 4
8742 13:27:27.374377 best_step = 14
8743 13:27:27.374800
8744 13:27:27.375123 ==
8745 13:27:27.377947 Dram Type= 6, Freq= 0, CH_1, rank 1
8746 13:27:27.381021 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8747 13:27:27.381638 ==
8748 13:27:27.384423 RX Vref Scan: 0
8749 13:27:27.385124
8750 13:27:27.385565 RX Vref 0 -> 0, step: 1
8751 13:27:27.385887
8752 13:27:27.387518 RX Delay 3 -> 252, step: 4
8753 13:27:27.390885 iDelay=195, Bit 0, Center 130 (79 ~ 182) 104
8754 13:27:27.397530 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8755 13:27:27.401000 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8756 13:27:27.404566 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8757 13:27:27.407692 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8758 13:27:27.410674 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8759 13:27:27.417480 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8760 13:27:27.420667 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8761 13:27:27.424885 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8762 13:27:27.427679 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8763 13:27:27.430930 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8764 13:27:27.437310 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8765 13:27:27.440678 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120
8766 13:27:27.444279 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8767 13:27:27.447229 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8768 13:27:27.453960 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8769 13:27:27.454474 ==
8770 13:27:27.456956 Dram Type= 6, Freq= 0, CH_1, rank 1
8771 13:27:27.460103 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8772 13:27:27.460538 ==
8773 13:27:27.460872 DQS Delay:
8774 13:27:27.463920 DQS0 = 0, DQS1 = 0
8775 13:27:27.464426 DQM Delay:
8776 13:27:27.466687 DQM0 = 127, DQM1 = 122
8777 13:27:27.467112 DQ Delay:
8778 13:27:27.470290 DQ0 =130, DQ1 =122, DQ2 =118, DQ3 =124
8779 13:27:27.473643 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8780 13:27:27.477110 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =114
8781 13:27:27.480280 DQ12 =130, DQ13 =132, DQ14 =134, DQ15 =132
8782 13:27:27.480787
8783 13:27:27.483818
8784 13:27:27.484319
8785 13:27:27.484651 [DramC_TX_OE_Calibration] TA2
8786 13:27:27.486449 Original DQ_B0 (3 6) =30, OEN = 27
8787 13:27:27.490034 Original DQ_B1 (3 6) =30, OEN = 27
8788 13:27:27.493683 24, 0x0, End_B0=24 End_B1=24
8789 13:27:27.496781 25, 0x0, End_B0=25 End_B1=25
8790 13:27:27.500066 26, 0x0, End_B0=26 End_B1=26
8791 13:27:27.500574 27, 0x0, End_B0=27 End_B1=27
8792 13:27:27.503412 28, 0x0, End_B0=28 End_B1=28
8793 13:27:27.506918 29, 0x0, End_B0=29 End_B1=29
8794 13:27:27.510160 30, 0x0, End_B0=30 End_B1=30
8795 13:27:27.513673 31, 0x4545, End_B0=30 End_B1=30
8796 13:27:27.514186 Byte0 end_step=30 best_step=27
8797 13:27:27.516750 Byte1 end_step=30 best_step=27
8798 13:27:27.519587 Byte0 TX OE(2T, 0.5T) = (3, 3)
8799 13:27:27.522896 Byte1 TX OE(2T, 0.5T) = (3, 3)
8800 13:27:27.523321
8801 13:27:27.523649
8802 13:27:27.532836 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8803 13:27:27.533410 CH1 RK1: MR19=303, MR18=1E1E
8804 13:27:27.539671 CH1_RK1: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15
8805 13:27:27.542910 [RxdqsGatingPostProcess] freq 1600
8806 13:27:27.549667 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8807 13:27:27.552572 Pre-setting of DQS Precalculation
8808 13:27:27.555873 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8809 13:27:27.562471 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8810 13:27:27.572139 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8811 13:27:27.572583
8812 13:27:27.572911
8813 13:27:27.575659 [Calibration Summary] 3200 Mbps
8814 13:27:27.576084 CH 0, Rank 0
8815 13:27:27.579158 SW Impedance : PASS
8816 13:27:27.579661 DUTY Scan : NO K
8817 13:27:27.582892 ZQ Calibration : PASS
8818 13:27:27.585582 Jitter Meter : NO K
8819 13:27:27.586023 CBT Training : PASS
8820 13:27:27.589401 Write leveling : PASS
8821 13:27:27.589911 RX DQS gating : PASS
8822 13:27:27.592802 RX DQ/DQS(RDDQC) : PASS
8823 13:27:27.596158 TX DQ/DQS : PASS
8824 13:27:27.596813 RX DATLAT : PASS
8825 13:27:27.599531 RX DQ/DQS(Engine): PASS
8826 13:27:27.602049 TX OE : PASS
8827 13:27:27.602481 All Pass.
8828 13:27:27.602809
8829 13:27:27.603112 CH 0, Rank 1
8830 13:27:27.605378 SW Impedance : PASS
8831 13:27:27.609096 DUTY Scan : NO K
8832 13:27:27.609666 ZQ Calibration : PASS
8833 13:27:27.612403 Jitter Meter : NO K
8834 13:27:27.615706 CBT Training : PASS
8835 13:27:27.616158 Write leveling : PASS
8836 13:27:27.618418 RX DQS gating : PASS
8837 13:27:27.622172 RX DQ/DQS(RDDQC) : PASS
8838 13:27:27.622595 TX DQ/DQS : PASS
8839 13:27:27.625309 RX DATLAT : PASS
8840 13:27:27.628925 RX DQ/DQS(Engine): PASS
8841 13:27:27.629496 TX OE : PASS
8842 13:27:27.631736 All Pass.
8843 13:27:27.632158
8844 13:27:27.632482 CH 1, Rank 0
8845 13:27:27.635315 SW Impedance : PASS
8846 13:27:27.635736 DUTY Scan : NO K
8847 13:27:27.638243 ZQ Calibration : PASS
8848 13:27:27.641977 Jitter Meter : NO K
8849 13:27:27.642401 CBT Training : PASS
8850 13:27:27.645329 Write leveling : PASS
8851 13:27:27.648617 RX DQS gating : PASS
8852 13:27:27.649003 RX DQ/DQS(RDDQC) : PASS
8853 13:27:27.651744 TX DQ/DQS : PASS
8854 13:27:27.655036 RX DATLAT : PASS
8855 13:27:27.655419 RX DQ/DQS(Engine): PASS
8856 13:27:27.658174 TX OE : PASS
8857 13:27:27.658585 All Pass.
8858 13:27:27.658884
8859 13:27:27.662113 CH 1, Rank 1
8860 13:27:27.662500 SW Impedance : PASS
8861 13:27:27.664762 DUTY Scan : NO K
8862 13:27:27.665166 ZQ Calibration : PASS
8863 13:27:27.668788 Jitter Meter : NO K
8864 13:27:27.671480 CBT Training : PASS
8865 13:27:27.671887 Write leveling : PASS
8866 13:27:27.674526 RX DQS gating : PASS
8867 13:27:27.678435 RX DQ/DQS(RDDQC) : PASS
8868 13:27:27.678845 TX DQ/DQS : PASS
8869 13:27:27.681406 RX DATLAT : PASS
8870 13:27:27.685010 RX DQ/DQS(Engine): PASS
8871 13:27:27.685423 TX OE : PASS
8872 13:27:27.688368 All Pass.
8873 13:27:27.688750
8874 13:27:27.689131 DramC Write-DBI on
8875 13:27:27.691211 PER_BANK_REFRESH: Hybrid Mode
8876 13:27:27.694526 TX_TRACKING: ON
8877 13:27:27.701708 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8878 13:27:27.711115 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8879 13:27:27.718318 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8880 13:27:27.721114 [FAST_K] Save calibration result to emmc
8881 13:27:27.724710 sync common calibartion params.
8882 13:27:27.725094 sync cbt_mode0:0, 1:0
8883 13:27:27.727685 dram_init: ddr_geometry: 0
8884 13:27:27.731213 dram_init: ddr_geometry: 0
8885 13:27:27.731598 dram_init: ddr_geometry: 0
8886 13:27:27.734126 0:dram_rank_size:80000000
8887 13:27:27.737683 1:dram_rank_size:80000000
8888 13:27:27.744390 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8889 13:27:27.744781 DFS_SHUFFLE_HW_MODE: ON
8890 13:27:27.747535 dramc_set_vcore_voltage set vcore to 725000
8891 13:27:27.750754 Read voltage for 1600, 0
8892 13:27:27.751140 Vio18 = 0
8893 13:27:27.754409 Vcore = 725000
8894 13:27:27.754804 Vdram = 0
8895 13:27:27.755102 Vddq = 0
8896 13:27:27.757294 Vmddr = 0
8897 13:27:27.757680 switch to 3200 Mbps bootup
8898 13:27:27.760789 [DramcRunTimeConfig]
8899 13:27:27.761189 PHYPLL
8900 13:27:27.764722 DPM_CONTROL_AFTERK: ON
8901 13:27:27.765102 PER_BANK_REFRESH: ON
8902 13:27:27.767152 REFRESH_OVERHEAD_REDUCTION: ON
8903 13:27:27.770915 CMD_PICG_NEW_MODE: OFF
8904 13:27:27.771389 XRTWTW_NEW_MODE: ON
8905 13:27:27.773936 XRTRTR_NEW_MODE: ON
8906 13:27:27.774343 TX_TRACKING: ON
8907 13:27:27.777273 RDSEL_TRACKING: OFF
8908 13:27:27.780833 DQS Precalculation for DVFS: ON
8909 13:27:27.781334 RX_TRACKING: OFF
8910 13:27:27.784330 HW_GATING DBG: ON
8911 13:27:27.784791 ZQCS_ENABLE_LP4: ON
8912 13:27:27.787380 RX_PICG_NEW_MODE: ON
8913 13:27:27.787763 TX_PICG_NEW_MODE: ON
8914 13:27:27.791070 ENABLE_RX_DCM_DPHY: ON
8915 13:27:27.794204 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8916 13:27:27.797270 DUMMY_READ_FOR_TRACKING: OFF
8917 13:27:27.797677 !!! SPM_CONTROL_AFTERK: OFF
8918 13:27:27.800711 !!! SPM could not control APHY
8919 13:27:27.804040 IMPEDANCE_TRACKING: ON
8920 13:27:27.804425 TEMP_SENSOR: ON
8921 13:27:27.807068 HW_SAVE_FOR_SR: OFF
8922 13:27:27.810493 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8923 13:27:27.814150 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8924 13:27:27.814617 Read ODT Tracking: ON
8925 13:27:27.817158 Refresh Rate DeBounce: ON
8926 13:27:27.820513 DFS_NO_QUEUE_FLUSH: ON
8927 13:27:27.823678 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8928 13:27:27.827503 ENABLE_DFS_RUNTIME_MRW: OFF
8929 13:27:27.827963 DDR_RESERVE_NEW_MODE: ON
8930 13:27:27.830097 MR_CBT_SWITCH_FREQ: ON
8931 13:27:27.833748 =========================
8932 13:27:27.850670 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8933 13:27:27.854380 dram_init: ddr_geometry: 0
8934 13:27:27.872768 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8935 13:27:27.876098 dram_init: dram init end (result: 0)
8936 13:27:27.882650 DRAM-K: Full calibration passed in 23439 msecs
8937 13:27:27.885746 MRC: failed to locate region type 0.
8938 13:27:27.886173 DRAM rank0 size:0x80000000,
8939 13:27:27.889138 DRAM rank1 size=0x80000000
8940 13:27:27.898924 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8941 13:27:27.905932 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8942 13:27:27.912386 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8943 13:27:27.918669 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8944 13:27:27.921906 DRAM rank0 size:0x80000000,
8945 13:27:27.925667 DRAM rank1 size=0x80000000
8946 13:27:27.926165 CBMEM:
8947 13:27:27.928603 IMD: root @ 0xfffff000 254 entries.
8948 13:27:27.931940 IMD: root @ 0xffffec00 62 entries.
8949 13:27:27.935200 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8950 13:27:27.938528 WARNING: RO_VPD is uninitialized or empty.
8951 13:27:27.945090 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8952 13:27:27.952091 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8953 13:27:27.964553 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8954 13:27:27.976192 BS: romstage times (exec / console): total (unknown) / 22975 ms
8955 13:27:27.976696
8956 13:27:27.977025
8957 13:27:27.987384 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8958 13:27:27.989132 ARM64: Exception handlers installed.
8959 13:27:27.992648 ARM64: Testing exception
8960 13:27:27.996237 ARM64: Done test exception
8961 13:27:27.996744 Enumerating buses...
8962 13:27:27.998910 Show all devs... Before device enumeration.
8963 13:27:28.003253 Root Device: enabled 1
8964 13:27:28.006436 CPU_CLUSTER: 0: enabled 1
8965 13:27:28.006941 CPU: 00: enabled 1
8966 13:27:28.009282 Compare with tree...
8967 13:27:28.009784 Root Device: enabled 1
8968 13:27:28.012745 CPU_CLUSTER: 0: enabled 1
8969 13:27:28.015424 CPU: 00: enabled 1
8970 13:27:28.015847 Root Device scanning...
8971 13:27:28.019141 scan_static_bus for Root Device
8972 13:27:28.022416 CPU_CLUSTER: 0 enabled
8973 13:27:28.025899 scan_static_bus for Root Device done
8974 13:27:28.029218 scan_bus: bus Root Device finished in 8 msecs
8975 13:27:28.029678 done
8976 13:27:28.035810 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8977 13:27:28.039004 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8978 13:27:28.045327 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8979 13:27:28.048710 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8980 13:27:28.052042 Allocating resources...
8981 13:27:28.055395 Reading resources...
8982 13:27:28.058719 Root Device read_resources bus 0 link: 0
8983 13:27:28.059165 DRAM rank0 size:0x80000000,
8984 13:27:28.062776 DRAM rank1 size=0x80000000
8985 13:27:28.065700 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8986 13:27:28.068885 CPU: 00 missing read_resources
8987 13:27:28.075146 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8988 13:27:28.078512 Root Device read_resources bus 0 link: 0 done
8989 13:27:28.079028 Done reading resources.
8990 13:27:28.085342 Show resources in subtree (Root Device)...After reading.
8991 13:27:28.088661 Root Device child on link 0 CPU_CLUSTER: 0
8992 13:27:28.091634 CPU_CLUSTER: 0 child on link 0 CPU: 00
8993 13:27:28.101652 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8994 13:27:28.102150 CPU: 00
8995 13:27:28.105066 Root Device assign_resources, bus 0 link: 0
8996 13:27:28.108846 CPU_CLUSTER: 0 missing set_resources
8997 13:27:28.115279 Root Device assign_resources, bus 0 link: 0 done
8998 13:27:28.115787 Done setting resources.
8999 13:27:28.121572 Show resources in subtree (Root Device)...After assigning values.
9000 13:27:28.124860 Root Device child on link 0 CPU_CLUSTER: 0
9001 13:27:28.128731 CPU_CLUSTER: 0 child on link 0 CPU: 00
9002 13:27:28.138115 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
9003 13:27:28.138626 CPU: 00
9004 13:27:28.141703 Done allocating resources.
9005 13:27:28.148191 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9006 13:27:28.148697 Enabling resources...
9007 13:27:28.149029 done.
9008 13:27:28.155008 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9009 13:27:28.155514 Initializing devices...
9010 13:27:28.158069 Root Device init
9011 13:27:28.158519 init hardware done!
9012 13:27:28.161529 0x00000018: ctrlr->caps
9013 13:27:28.164413 52.000 MHz: ctrlr->f_max
9014 13:27:28.164843 0.400 MHz: ctrlr->f_min
9015 13:27:28.168135 0x40ff8080: ctrlr->voltages
9016 13:27:28.170902 sclk: 390625
9017 13:27:28.171331 Bus Width = 1
9018 13:27:28.171663 sclk: 390625
9019 13:27:28.174490 Bus Width = 1
9020 13:27:28.175005 Early init status = 3
9021 13:27:28.181157 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9022 13:27:28.184376 in-header: 03 fc 00 00 01 00 00 00
9023 13:27:28.187958 in-data: 00
9024 13:27:28.190830 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9025 13:27:28.199996 in-header: 03 fd 00 00 00 00 00 00
9026 13:27:28.200448 in-data:
9027 13:27:28.203213 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9028 13:27:28.207815 in-header: 03 fc 00 00 01 00 00 00
9029 13:27:28.211462 in-data: 00
9030 13:27:28.214226 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9031 13:27:28.220011 in-header: 03 fd 00 00 00 00 00 00
9032 13:27:28.223427 in-data:
9033 13:27:28.226808 [SSUSB] Setting up USB HOST controller...
9034 13:27:28.230677 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9035 13:27:28.233838 [SSUSB] phy power-on done.
9036 13:27:28.236969 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9037 13:27:28.243760 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9038 13:27:28.246423 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9039 13:27:28.253480 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9040 13:27:28.260401 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9041 13:27:28.266699 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9042 13:27:28.273557 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9043 13:27:28.280217 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9044 13:27:28.283085 SPM: binary array size = 0x9dc
9045 13:27:28.286872 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9046 13:27:28.293136 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9047 13:27:28.299638 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9048 13:27:28.306216 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9049 13:27:28.309367 configure_display: Starting display init
9050 13:27:28.343801 anx7625_power_on_init: Init interface.
9051 13:27:28.346457 anx7625_disable_pd_protocol: Disabled PD feature.
9052 13:27:28.350182 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9053 13:27:28.378146 anx7625_start_dp_work: Secure OCM version=00
9054 13:27:28.381760 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9055 13:27:28.396310 sp_tx_get_edid_block: EDID Block = 1
9056 13:27:28.498845 Extracted contents:
9057 13:27:28.501807 header: 00 ff ff ff ff ff ff 00
9058 13:27:28.505220 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9059 13:27:28.508654 version: 01 04
9060 13:27:28.511864 basic params: 95 1f 11 78 0a
9061 13:27:28.515514 chroma info: 76 90 94 55 54 90 27 21 50 54
9062 13:27:28.518444 established: 00 00 00
9063 13:27:28.524900 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9064 13:27:28.528535 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9065 13:27:28.534562 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9066 13:27:28.541311 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9067 13:27:28.547940 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9068 13:27:28.550927 extensions: 00
9069 13:27:28.551451 checksum: fb
9070 13:27:28.551789
9071 13:27:28.554298 Manufacturer: IVO Model 57d Serial Number 0
9072 13:27:28.558034 Made week 0 of 2020
9073 13:27:28.560877 EDID version: 1.4
9074 13:27:28.561538 Digital display
9075 13:27:28.564562 6 bits per primary color channel
9076 13:27:28.564993 DisplayPort interface
9077 13:27:28.567770 Maximum image size: 31 cm x 17 cm
9078 13:27:28.571392 Gamma: 220%
9079 13:27:28.571816 Check DPMS levels
9080 13:27:28.574778 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9081 13:27:28.581359 First detailed timing is preferred timing
9082 13:27:28.581826 Established timings supported:
9083 13:27:28.584861 Standard timings supported:
9084 13:27:28.588030 Detailed timings
9085 13:27:28.590923 Hex of detail: 383680a07038204018303c0035ae10000019
9086 13:27:28.597999 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9087 13:27:28.601047 0780 0798 07c8 0820 hborder 0
9088 13:27:28.604429 0438 043b 0447 0458 vborder 0
9089 13:27:28.607933 -hsync -vsync
9090 13:27:28.608395 Did detailed timing
9091 13:27:28.614358 Hex of detail: 000000000000000000000000000000000000
9092 13:27:28.617800 Manufacturer-specified data, tag 0
9093 13:27:28.621071 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9094 13:27:28.624253 ASCII string: InfoVision
9095 13:27:28.627486 Hex of detail: 000000fe00523134304e574635205248200a
9096 13:27:28.630736 ASCII string: R140NWF5 RH
9097 13:27:28.631123 Checksum
9098 13:27:28.634359 Checksum: 0xfb (valid)
9099 13:27:28.637491 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9100 13:27:28.641290 DSI data_rate: 832800000 bps
9101 13:27:28.647980 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9102 13:27:28.650497 anx7625_parse_edid: pixelclock(138800).
9103 13:27:28.654244 hactive(1920), hsync(48), hfp(24), hbp(88)
9104 13:27:28.657333 vactive(1080), vsync(12), vfp(3), vbp(17)
9105 13:27:28.661049 anx7625_dsi_config: config dsi.
9106 13:27:28.667263 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9107 13:27:28.680265 anx7625_dsi_config: success to config DSI
9108 13:27:28.684384 anx7625_dp_start: MIPI phy setup OK.
9109 13:27:28.687266 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9110 13:27:28.690195 mtk_ddp_mode_set invalid vrefresh 60
9111 13:27:28.693754 main_disp_path_setup
9112 13:27:28.694136 ovl_layer_smi_id_en
9113 13:27:28.696896 ovl_layer_smi_id_en
9114 13:27:28.697326 ccorr_config
9115 13:27:28.697750 aal_config
9116 13:27:28.700451 gamma_config
9117 13:27:28.700914 postmask_config
9118 13:27:28.703384 dither_config
9119 13:27:28.706957 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9120 13:27:28.713908 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9121 13:27:28.717411 Root Device init finished in 555 msecs
9122 13:27:28.720324 CPU_CLUSTER: 0 init
9123 13:27:28.727472 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9124 13:27:28.730209 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9125 13:27:28.733762 APU_MBOX 0x190000b0 = 0x10001
9126 13:27:28.736736 APU_MBOX 0x190001b0 = 0x10001
9127 13:27:28.740394 APU_MBOX 0x190005b0 = 0x10001
9128 13:27:28.743703 APU_MBOX 0x190006b0 = 0x10001
9129 13:27:28.747561 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9130 13:27:28.759612 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9131 13:27:28.771894 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9132 13:27:28.778270 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9133 13:27:28.789899 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9134 13:27:28.798934 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9135 13:27:28.802367 CPU_CLUSTER: 0 init finished in 81 msecs
9136 13:27:28.806104 Devices initialized
9137 13:27:28.809209 Show all devs... After init.
9138 13:27:28.809647 Root Device: enabled 1
9139 13:27:28.812190 CPU_CLUSTER: 0: enabled 1
9140 13:27:28.815751 CPU: 00: enabled 1
9141 13:27:28.819152 BS: BS_DEV_INIT run times (exec / console): 214 / 447 ms
9142 13:27:28.822014 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9143 13:27:28.825406 ELOG: NV offset 0x57f000 size 0x1000
9144 13:27:28.832538 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9145 13:27:28.838963 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9146 13:27:28.841881 ELOG: Event(17) added with size 13 at 2024-07-18 13:27:28 UTC
9147 13:27:28.845592 out: cmd=0x121: 03 db 21 01 00 00 00 00
9148 13:27:28.849688 in-header: 03 6d 00 00 2c 00 00 00
9149 13:27:28.862391 in-data: d5 6d 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9150 13:27:28.869106 ELOG: Event(A1) added with size 10 at 2024-07-18 13:27:28 UTC
9151 13:27:28.875877 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9152 13:27:28.883048 ELOG: Event(A0) added with size 9 at 2024-07-18 13:27:28 UTC
9153 13:27:28.885986 elog_add_boot_reason: Logged dev mode boot
9154 13:27:28.889180 BS: BS_POST_DEVICE entry times (exec / console): 1 / 64 ms
9155 13:27:28.892704 Finalize devices...
9156 13:27:28.893214 Devices finalized
9157 13:27:28.899018 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9158 13:27:28.901849 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9159 13:27:28.905798 in-header: 03 07 00 00 08 00 00 00
9160 13:27:28.908754 in-data: aa e4 47 04 13 02 00 00
9161 13:27:28.912967 Chrome EC: UHEPI supported
9162 13:27:28.918925 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9163 13:27:28.922159 in-header: 03 a9 00 00 08 00 00 00
9164 13:27:28.925103 in-data: 84 60 60 08 00 00 00 00
9165 13:27:28.928464 ELOG: Event(91) added with size 10 at 2024-07-18 13:27:28 UTC
9166 13:27:28.935310 Chrome EC: clear events_b mask to 0x0000000020004000
9167 13:27:28.941636 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9168 13:27:28.945754 in-header: 03 fd 00 00 00 00 00 00
9169 13:27:28.946183 in-data:
9170 13:27:28.952301 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9171 13:27:28.955468 Writing coreboot table at 0xffe64000
9172 13:27:28.958948 0. 000000000010a000-0000000000113fff: RAMSTAGE
9173 13:27:28.962161 1. 0000000040000000-00000000400fffff: RAM
9174 13:27:28.965961 2. 0000000040100000-000000004032afff: RAMSTAGE
9175 13:27:28.968953 3. 000000004032b000-00000000545fffff: RAM
9176 13:27:28.975917 4. 0000000054600000-000000005465ffff: BL31
9177 13:27:28.978720 5. 0000000054660000-00000000ffe63fff: RAM
9178 13:27:28.981994 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9179 13:27:28.988433 7. 0000000100000000-000000013fffffff: RAM
9180 13:27:28.988941 Passing 5 GPIOs to payload:
9181 13:27:28.995362 NAME | PORT | POLARITY | VALUE
9182 13:27:28.998798 EC in RW | 0x000000aa | low | undefined
9183 13:27:29.005308 EC interrupt | 0x00000005 | low | undefined
9184 13:27:29.008828 TPM interrupt | 0x000000ab | high | undefined
9185 13:27:29.012301 SD card detect | 0x00000011 | high | undefined
9186 13:27:29.018756 speaker enable | 0x00000093 | high | undefined
9187 13:27:29.021693 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9188 13:27:29.025058 in-header: 03 f8 00 00 02 00 00 00
9189 13:27:29.025532 in-data: 03 00
9190 13:27:29.028283 ADC[4]: Raw value=668958 ID=5
9191 13:27:29.031326 ADC[3]: Raw value=212549 ID=1
9192 13:27:29.031769 RAM Code: 0x51
9193 13:27:29.034931 ADC[6]: Raw value=74778 ID=0
9194 13:27:29.038499 ADC[5]: Raw value=211444 ID=1
9195 13:27:29.038943 SKU Code: 0x1
9196 13:27:29.044821 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a7d8
9197 13:27:29.048308 coreboot table: 964 bytes.
9198 13:27:29.051777 IMD ROOT 0. 0xfffff000 0x00001000
9199 13:27:29.055006 IMD SMALL 1. 0xffffe000 0x00001000
9200 13:27:29.058132 RO MCACHE 2. 0xffffc000 0x00001104
9201 13:27:29.061128 CONSOLE 3. 0xfff7c000 0x00080000
9202 13:27:29.064487 FMAP 4. 0xfff7b000 0x00000452
9203 13:27:29.067941 TIME STAMP 5. 0xfff7a000 0x00000910
9204 13:27:29.071296 VBOOT WORK 6. 0xfff66000 0x00014000
9205 13:27:29.074731 RAMOOPS 7. 0xffe66000 0x00100000
9206 13:27:29.078543 COREBOOT 8. 0xffe64000 0x00002000
9207 13:27:29.079076 IMD small region:
9208 13:27:29.081352 IMD ROOT 0. 0xffffec00 0x00000400
9209 13:27:29.084679 VPD 1. 0xffffeb80 0x0000006c
9210 13:27:29.088404 MMC STATUS 2. 0xffffeb60 0x00000004
9211 13:27:29.094584 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9212 13:27:29.101296 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9213 13:27:29.140876 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9214 13:27:29.144205 Checking segment from ROM address 0x40100000
9215 13:27:29.147626 Checking segment from ROM address 0x4010001c
9216 13:27:29.154706 Loading segment from ROM address 0x40100000
9217 13:27:29.155219 code (compression=0)
9218 13:27:29.164357 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9219 13:27:29.171047 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9220 13:27:29.171574 it's not compressed!
9221 13:27:29.177887 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9222 13:27:29.183897 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9223 13:27:29.201386 Loading segment from ROM address 0x4010001c
9224 13:27:29.201910 Entry Point 0x80000000
9225 13:27:29.204481 Loaded segments
9226 13:27:29.208099 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9227 13:27:29.214433 Jumping to boot code at 0x80000000(0xffe64000)
9228 13:27:29.220855 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9229 13:27:29.227681 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9230 13:27:29.235597 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9231 13:27:29.239158 Checking segment from ROM address 0x40100000
9232 13:27:29.242484 Checking segment from ROM address 0x4010001c
9233 13:27:29.248831 Loading segment from ROM address 0x40100000
9234 13:27:29.249390 code (compression=1)
9235 13:27:29.255431 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9236 13:27:29.265321 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9237 13:27:29.265756 using LZMA
9238 13:27:29.273947 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9239 13:27:29.280617 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9240 13:27:29.283735 Loading segment from ROM address 0x4010001c
9241 13:27:29.284167 Entry Point 0x54601000
9242 13:27:29.287197 Loaded segments
9243 13:27:29.290624 NOTICE: MT8192 bl31_setup
9244 13:27:29.297727 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9245 13:27:29.300598 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9246 13:27:29.304010 WARNING: region 0:
9247 13:27:29.307218 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9248 13:27:29.307646 WARNING: region 1:
9249 13:27:29.313825 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9250 13:27:29.317620 WARNING: region 2:
9251 13:27:29.320383 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9252 13:27:29.324051 WARNING: region 3:
9253 13:27:29.326967 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9254 13:27:29.330750 WARNING: region 4:
9255 13:27:29.337366 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9256 13:27:29.337878 WARNING: region 5:
9257 13:27:29.340526 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9258 13:27:29.343672 WARNING: region 6:
9259 13:27:29.346896 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9260 13:27:29.349997 WARNING: region 7:
9261 13:27:29.353839 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9262 13:27:29.360195 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9263 13:27:29.363228 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9264 13:27:29.371014 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9265 13:27:29.373632 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9266 13:27:29.377331 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9267 13:27:29.383903 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9268 13:27:29.386857 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9269 13:27:29.389907 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9270 13:27:29.397040 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9271 13:27:29.399866 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9272 13:27:29.403874 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9273 13:27:29.410199 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9274 13:27:29.413815 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9275 13:27:29.420382 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9276 13:27:29.423558 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9277 13:27:29.426487 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9278 13:27:29.433297 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9279 13:27:29.437038 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9280 13:27:29.439866 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9281 13:27:29.446875 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9282 13:27:29.449933 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9283 13:27:29.456923 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9284 13:27:29.459871 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9285 13:27:29.463561 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9286 13:27:29.470116 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9287 13:27:29.473641 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9288 13:27:29.480139 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9289 13:27:29.483184 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9290 13:27:29.486453 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9291 13:27:29.493021 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9292 13:27:29.496044 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9293 13:27:29.503374 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9294 13:27:29.506178 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9295 13:27:29.509859 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9296 13:27:29.513506 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9297 13:27:29.519943 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9298 13:27:29.523388 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9299 13:27:29.525954 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9300 13:27:29.529825 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9301 13:27:29.536573 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9302 13:27:29.539271 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9303 13:27:29.543341 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9304 13:27:29.546156 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9305 13:27:29.552714 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9306 13:27:29.556062 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9307 13:27:29.559376 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9308 13:27:29.562644 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9309 13:27:29.569640 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9310 13:27:29.573431 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9311 13:27:29.580339 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9312 13:27:29.583309 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9313 13:27:29.586161 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9314 13:27:29.592649 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9315 13:27:29.595650 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9316 13:27:29.602867 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9317 13:27:29.606160 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9318 13:27:29.612865 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9319 13:27:29.616213 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9320 13:27:29.619191 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9321 13:27:29.626090 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9322 13:27:29.628929 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9323 13:27:29.635932 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9324 13:27:29.639208 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9325 13:27:29.645882 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9326 13:27:29.650168 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9327 13:27:29.655607 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9328 13:27:29.659247 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9329 13:27:29.662297 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9330 13:27:29.669317 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9331 13:27:29.672122 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9332 13:27:29.679095 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9333 13:27:29.682334 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9334 13:27:29.689435 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9335 13:27:29.691953 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9336 13:27:29.695529 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9337 13:27:29.702888 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9338 13:27:29.705192 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9339 13:27:29.711705 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9340 13:27:29.714868 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9341 13:27:29.721891 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9342 13:27:29.724938 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9343 13:27:29.731866 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9344 13:27:29.734782 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9345 13:27:29.737940 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9346 13:27:29.744677 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9347 13:27:29.747817 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9348 13:27:29.754795 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9349 13:27:29.757848 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9350 13:27:29.764437 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9351 13:27:29.767946 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9352 13:27:29.770961 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9353 13:27:29.778165 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9354 13:27:29.781682 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9355 13:27:29.788018 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9356 13:27:29.791683 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9357 13:27:29.798556 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9358 13:27:29.801569 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9359 13:27:29.804575 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9360 13:27:29.808128 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9361 13:27:29.815148 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9362 13:27:29.818225 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9363 13:27:29.821320 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9364 13:27:29.828556 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9365 13:27:29.831470 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9366 13:27:29.837943 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9367 13:27:29.841521 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9368 13:27:29.845076 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9369 13:27:29.851360 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9370 13:27:29.854509 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9371 13:27:29.861359 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9372 13:27:29.864642 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9373 13:27:29.868061 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9374 13:27:29.874470 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9375 13:27:29.878023 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9376 13:27:29.884535 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9377 13:27:29.888193 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9378 13:27:29.891090 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9379 13:27:29.897566 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9380 13:27:29.900803 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9381 13:27:29.904895 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9382 13:27:29.907792 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9383 13:27:29.914933 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9384 13:27:29.917965 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9385 13:27:29.921346 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9386 13:27:29.927980 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9387 13:27:29.930898 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9388 13:27:29.934541 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9389 13:27:29.941177 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9390 13:27:29.944078 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9391 13:27:29.951155 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9392 13:27:29.953861 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9393 13:27:29.957413 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9394 13:27:29.964074 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9395 13:27:29.967185 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9396 13:27:29.970777 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9397 13:27:29.977780 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9398 13:27:29.980705 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9399 13:27:29.987828 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9400 13:27:29.990510 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9401 13:27:29.994075 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9402 13:27:30.000353 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9403 13:27:30.004243 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9404 13:27:30.010590 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9405 13:27:30.014669 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9406 13:27:30.017384 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9407 13:27:30.023593 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9408 13:27:30.027134 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9409 13:27:30.034371 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9410 13:27:30.037611 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9411 13:27:30.040964 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9412 13:27:30.047109 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9413 13:27:30.050277 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9414 13:27:30.056632 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9415 13:27:30.060511 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9416 13:27:30.063767 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9417 13:27:30.070751 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9418 13:27:30.073494 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9419 13:27:30.080681 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9420 13:27:30.084007 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9421 13:27:30.086897 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9422 13:27:30.093390 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9423 13:27:30.096849 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9424 13:27:30.103712 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9425 13:27:30.107201 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9426 13:27:30.110463 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9427 13:27:30.116487 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9428 13:27:30.120174 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9429 13:27:30.123343 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9430 13:27:30.130028 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9431 13:27:30.133581 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9432 13:27:30.140624 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9433 13:27:30.143434 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9434 13:27:30.146769 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9435 13:27:30.152884 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9436 13:27:30.156510 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9437 13:27:30.163204 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9438 13:27:30.167172 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9439 13:27:30.169538 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9440 13:27:30.176738 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9441 13:27:30.179740 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9442 13:27:30.187159 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9443 13:27:30.189380 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9444 13:27:30.193007 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9445 13:27:30.199946 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9446 13:27:30.203292 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9447 13:27:30.209616 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9448 13:27:30.213070 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9449 13:27:30.216085 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9450 13:27:30.223255 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9451 13:27:30.226179 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9452 13:27:30.232906 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9453 13:27:30.236601 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9454 13:27:30.239096 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9455 13:27:30.246145 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9456 13:27:30.249341 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9457 13:27:30.256087 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9458 13:27:30.259343 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9459 13:27:30.265622 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9460 13:27:30.269509 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9461 13:27:30.272521 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9462 13:27:30.279177 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9463 13:27:30.282094 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9464 13:27:30.289380 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9465 13:27:30.292319 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9466 13:27:30.298867 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9467 13:27:30.302902 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9468 13:27:30.305963 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9469 13:27:30.311934 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9470 13:27:30.315260 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9471 13:27:30.321789 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9472 13:27:30.325304 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9473 13:27:30.328848 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9474 13:27:30.335036 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9475 13:27:30.338248 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9476 13:27:30.344679 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9477 13:27:30.348217 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9478 13:27:30.355609 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9479 13:27:30.358541 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9480 13:27:30.362162 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9481 13:27:30.368484 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9482 13:27:30.371643 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9483 13:27:30.378088 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9484 13:27:30.381731 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9485 13:27:30.384639 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9486 13:27:30.391641 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9487 13:27:30.394973 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9488 13:27:30.401547 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9489 13:27:30.404800 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9490 13:27:30.411426 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9491 13:27:30.415371 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9492 13:27:30.418179 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9493 13:27:30.422121 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9494 13:27:30.424712 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9495 13:27:30.431353 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9496 13:27:30.435060 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9497 13:27:30.438326 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9498 13:27:30.444366 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9499 13:27:30.447999 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9500 13:27:30.451521 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9501 13:27:30.458009 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9502 13:27:30.461220 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9503 13:27:30.467698 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9504 13:27:30.470996 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9505 13:27:30.474350 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9506 13:27:30.481377 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9507 13:27:30.484829 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9508 13:27:30.491854 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9509 13:27:30.493937 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9510 13:27:30.497732 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9511 13:27:30.504490 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9512 13:27:30.507732 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9513 13:27:30.511708 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9514 13:27:30.517451 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9515 13:27:30.520844 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9516 13:27:30.524642 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9517 13:27:30.530863 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9518 13:27:30.534567 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9519 13:27:30.540704 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9520 13:27:30.544123 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9521 13:27:30.547799 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9522 13:27:30.554573 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9523 13:27:30.557598 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9524 13:27:30.560424 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9525 13:27:30.567288 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9526 13:27:30.570617 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9527 13:27:30.573858 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9528 13:27:30.580702 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9529 13:27:30.584024 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9530 13:27:30.587385 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9531 13:27:30.593957 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9532 13:27:30.596837 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9533 13:27:30.600647 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9534 13:27:30.604093 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9535 13:27:30.607951 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9536 13:27:30.613644 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9537 13:27:30.617142 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9538 13:27:30.620686 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9539 13:27:30.627070 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9540 13:27:30.630671 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9541 13:27:30.633692 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9542 13:27:30.637020 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9543 13:27:30.643476 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9544 13:27:30.646905 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9545 13:27:30.653584 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9546 13:27:30.656930 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9547 13:27:30.660390 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9548 13:27:30.667001 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9549 13:27:30.670309 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9550 13:27:30.677017 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9551 13:27:30.680037 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9552 13:27:30.683055 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9553 13:27:30.689711 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9554 13:27:30.693315 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9555 13:27:30.700400 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9556 13:27:30.703426 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9557 13:27:30.706927 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9558 13:27:30.713860 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9559 13:27:30.717662 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9560 13:27:30.723530 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9561 13:27:30.726888 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9562 13:27:30.730219 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9563 13:27:30.736725 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9564 13:27:30.740193 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9565 13:27:30.746958 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9566 13:27:30.750132 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9567 13:27:30.753627 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9568 13:27:30.759821 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9569 13:27:30.762983 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9570 13:27:30.770159 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9571 13:27:30.773312 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9572 13:27:30.780073 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9573 13:27:30.782701 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9574 13:27:30.786412 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9575 13:27:30.792873 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9576 13:27:30.796263 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9577 13:27:30.802842 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9578 13:27:30.805932 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9579 13:27:30.809610 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9580 13:27:30.816230 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9581 13:27:30.819475 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9582 13:27:30.825905 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9583 13:27:30.829452 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9584 13:27:30.833336 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9585 13:27:30.839426 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9586 13:27:30.842277 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9587 13:27:30.849288 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9588 13:27:30.852570 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9589 13:27:30.858983 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9590 13:27:30.862790 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9591 13:27:30.865884 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9592 13:27:30.872579 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9593 13:27:30.875459 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9594 13:27:30.882466 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9595 13:27:30.885485 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9596 13:27:30.889267 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9597 13:27:30.895436 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9598 13:27:30.899004 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9599 13:27:30.905549 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9600 13:27:30.909030 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9601 13:27:30.911814 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9602 13:27:30.918814 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9603 13:27:30.922184 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9604 13:27:30.928626 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9605 13:27:30.931986 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9606 13:27:30.938505 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9607 13:27:30.941965 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9608 13:27:30.945094 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9609 13:27:30.951988 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9610 13:27:30.955238 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9611 13:27:30.961787 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9612 13:27:30.965681 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9613 13:27:30.968304 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9614 13:27:30.974996 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9615 13:27:30.978275 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9616 13:27:30.984826 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9617 13:27:30.987758 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9618 13:27:30.994394 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9619 13:27:30.997886 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9620 13:27:31.004653 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9621 13:27:31.007850 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9622 13:27:31.010751 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9623 13:27:31.017774 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9624 13:27:31.021100 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9625 13:27:31.027792 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9626 13:27:31.030921 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9627 13:27:31.038122 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9628 13:27:31.041279 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9629 13:27:31.044225 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9630 13:27:31.050712 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9631 13:27:31.054076 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9632 13:27:31.061026 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9633 13:27:31.063877 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9634 13:27:31.071107 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9635 13:27:31.074323 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9636 13:27:31.081571 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9637 13:27:31.084310 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9638 13:27:31.087429 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9639 13:27:31.094319 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9640 13:27:31.097410 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9641 13:27:31.103919 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9642 13:27:31.107361 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9643 13:27:31.114086 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9644 13:27:31.117688 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9645 13:27:31.120371 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9646 13:27:31.127585 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9647 13:27:31.130299 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9648 13:27:31.137214 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9649 13:27:31.140579 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9650 13:27:31.147149 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9651 13:27:31.150460 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9652 13:27:31.156933 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9653 13:27:31.160258 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9654 13:27:31.163633 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9655 13:27:31.170638 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9656 13:27:31.173579 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9657 13:27:31.180579 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9658 13:27:31.184018 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9659 13:27:31.190440 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9660 13:27:31.193931 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9661 13:27:31.197135 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9662 13:27:31.203537 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9663 13:27:31.206910 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9664 13:27:31.213760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9665 13:27:31.217112 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9666 13:27:31.220098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9667 13:27:31.226996 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9668 13:27:31.229952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9669 13:27:31.237479 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9670 13:27:31.239751 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9671 13:27:31.246738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9672 13:27:31.249673 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9673 13:27:31.256649 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9674 13:27:31.259975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9675 13:27:31.266761 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9676 13:27:31.270172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9677 13:27:31.276588 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9678 13:27:31.279803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9679 13:27:31.286616 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9680 13:27:31.290116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9681 13:27:31.296200 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9682 13:27:31.299221 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9683 13:27:31.306216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9684 13:27:31.309465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9685 13:27:31.316622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9686 13:27:31.319464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9687 13:27:31.326578 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9688 13:27:31.329519 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9689 13:27:31.336440 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9690 13:27:31.339894 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9691 13:27:31.346324 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9692 13:27:31.349806 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9693 13:27:31.356372 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9694 13:27:31.359328 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9695 13:27:31.366257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9696 13:27:31.369612 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9697 13:27:31.370030 INFO: [APUAPC] vio 0
9698 13:27:31.376924 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9699 13:27:31.380503 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9700 13:27:31.384315 INFO: [APUAPC] D0_APC_0: 0x400510
9701 13:27:31.386918 INFO: [APUAPC] D0_APC_1: 0x0
9702 13:27:31.390532 INFO: [APUAPC] D0_APC_2: 0x1540
9703 13:27:31.393866 INFO: [APUAPC] D0_APC_3: 0x0
9704 13:27:31.396782 INFO: [APUAPC] D1_APC_0: 0xffffffff
9705 13:27:31.400273 INFO: [APUAPC] D1_APC_1: 0xffffffff
9706 13:27:31.403677 INFO: [APUAPC] D1_APC_2: 0x3fffff
9707 13:27:31.407280 INFO: [APUAPC] D1_APC_3: 0x0
9708 13:27:31.410388 INFO: [APUAPC] D2_APC_0: 0xffffffff
9709 13:27:31.414260 INFO: [APUAPC] D2_APC_1: 0xffffffff
9710 13:27:31.417166 INFO: [APUAPC] D2_APC_2: 0x3fffff
9711 13:27:31.420547 INFO: [APUAPC] D2_APC_3: 0x0
9712 13:27:31.423702 INFO: [APUAPC] D3_APC_0: 0xffffffff
9713 13:27:31.426941 INFO: [APUAPC] D3_APC_1: 0xffffffff
9714 13:27:31.430455 INFO: [APUAPC] D3_APC_2: 0x3fffff
9715 13:27:31.430531 INFO: [APUAPC] D3_APC_3: 0x0
9716 13:27:31.433527 INFO: [APUAPC] D4_APC_0: 0xffffffff
9717 13:27:31.440271 INFO: [APUAPC] D4_APC_1: 0xffffffff
9718 13:27:31.440359 INFO: [APUAPC] D4_APC_2: 0x3fffff
9719 13:27:31.443454 INFO: [APUAPC] D4_APC_3: 0x0
9720 13:27:31.446908 INFO: [APUAPC] D5_APC_0: 0xffffffff
9721 13:27:31.450395 INFO: [APUAPC] D5_APC_1: 0xffffffff
9722 13:27:31.453888 INFO: [APUAPC] D5_APC_2: 0x3fffff
9723 13:27:31.457129 INFO: [APUAPC] D5_APC_3: 0x0
9724 13:27:31.460317 INFO: [APUAPC] D6_APC_0: 0xffffffff
9725 13:27:31.463302 INFO: [APUAPC] D6_APC_1: 0xffffffff
9726 13:27:31.466852 INFO: [APUAPC] D6_APC_2: 0x3fffff
9727 13:27:31.470343 INFO: [APUAPC] D6_APC_3: 0x0
9728 13:27:31.473308 INFO: [APUAPC] D7_APC_0: 0xffffffff
9729 13:27:31.476691 INFO: [APUAPC] D7_APC_1: 0xffffffff
9730 13:27:31.479781 INFO: [APUAPC] D7_APC_2: 0x3fffff
9731 13:27:31.483428 INFO: [APUAPC] D7_APC_3: 0x0
9732 13:27:31.487022 INFO: [APUAPC] D8_APC_0: 0xffffffff
9733 13:27:31.490157 INFO: [APUAPC] D8_APC_1: 0xffffffff
9734 13:27:31.493084 INFO: [APUAPC] D8_APC_2: 0x3fffff
9735 13:27:31.496677 INFO: [APUAPC] D8_APC_3: 0x0
9736 13:27:31.499505 INFO: [APUAPC] D9_APC_0: 0xffffffff
9737 13:27:31.502691 INFO: [APUAPC] D9_APC_1: 0xffffffff
9738 13:27:31.506165 INFO: [APUAPC] D9_APC_2: 0x3fffff
9739 13:27:31.509783 INFO: [APUAPC] D9_APC_3: 0x0
9740 13:27:31.512825 INFO: [APUAPC] D10_APC_0: 0xffffffff
9741 13:27:31.515959 INFO: [APUAPC] D10_APC_1: 0xffffffff
9742 13:27:31.519696 INFO: [APUAPC] D10_APC_2: 0x3fffff
9743 13:27:31.522830 INFO: [APUAPC] D10_APC_3: 0x0
9744 13:27:31.526362 INFO: [APUAPC] D11_APC_0: 0xffffffff
9745 13:27:31.529660 INFO: [APUAPC] D11_APC_1: 0xffffffff
9746 13:27:31.534122 INFO: [APUAPC] D11_APC_2: 0x3fffff
9747 13:27:31.536410 INFO: [APUAPC] D11_APC_3: 0x0
9748 13:27:31.539625 INFO: [APUAPC] D12_APC_0: 0xffffffff
9749 13:27:31.542886 INFO: [APUAPC] D12_APC_1: 0xffffffff
9750 13:27:31.546124 INFO: [APUAPC] D12_APC_2: 0x3fffff
9751 13:27:31.549305 INFO: [APUAPC] D12_APC_3: 0x0
9752 13:27:31.552613 INFO: [APUAPC] D13_APC_0: 0xffffffff
9753 13:27:31.556063 INFO: [APUAPC] D13_APC_1: 0xffffffff
9754 13:27:31.559534 INFO: [APUAPC] D13_APC_2: 0x3fffff
9755 13:27:31.562363 INFO: [APUAPC] D13_APC_3: 0x0
9756 13:27:31.566123 INFO: [APUAPC] D14_APC_0: 0xffffffff
9757 13:27:31.569706 INFO: [APUAPC] D14_APC_1: 0xffffffff
9758 13:27:31.572564 INFO: [APUAPC] D14_APC_2: 0x3fffff
9759 13:27:31.576082 INFO: [APUAPC] D14_APC_3: 0x0
9760 13:27:31.579054 INFO: [APUAPC] D15_APC_0: 0xffffffff
9761 13:27:31.582968 INFO: [APUAPC] D15_APC_1: 0xffffffff
9762 13:27:31.585900 INFO: [APUAPC] D15_APC_2: 0x3fffff
9763 13:27:31.589527 INFO: [APUAPC] D15_APC_3: 0x0
9764 13:27:31.592614 INFO: [APUAPC] APC_CON: 0x4
9765 13:27:31.595939 INFO: [NOCDAPC] D0_APC_0: 0x0
9766 13:27:31.599136 INFO: [NOCDAPC] D0_APC_1: 0x0
9767 13:27:31.602964 INFO: [NOCDAPC] D1_APC_0: 0x0
9768 13:27:31.606679 INFO: [NOCDAPC] D1_APC_1: 0xfff
9769 13:27:31.609196 INFO: [NOCDAPC] D2_APC_0: 0x0
9770 13:27:31.609667 INFO: [NOCDAPC] D2_APC_1: 0xfff
9771 13:27:31.612434 INFO: [NOCDAPC] D3_APC_0: 0x0
9772 13:27:31.615967 INFO: [NOCDAPC] D3_APC_1: 0xfff
9773 13:27:31.619664 INFO: [NOCDAPC] D4_APC_0: 0x0
9774 13:27:31.622747 INFO: [NOCDAPC] D4_APC_1: 0xfff
9775 13:27:31.626297 INFO: [NOCDAPC] D5_APC_0: 0x0
9776 13:27:31.629022 INFO: [NOCDAPC] D5_APC_1: 0xfff
9777 13:27:31.632710 INFO: [NOCDAPC] D6_APC_0: 0x0
9778 13:27:31.636151 INFO: [NOCDAPC] D6_APC_1: 0xfff
9779 13:27:31.639374 INFO: [NOCDAPC] D7_APC_0: 0x0
9780 13:27:31.642884 INFO: [NOCDAPC] D7_APC_1: 0xfff
9781 13:27:31.643309 INFO: [NOCDAPC] D8_APC_0: 0x0
9782 13:27:31.645723 INFO: [NOCDAPC] D8_APC_1: 0xfff
9783 13:27:31.649200 INFO: [NOCDAPC] D9_APC_0: 0x0
9784 13:27:31.652194 INFO: [NOCDAPC] D9_APC_1: 0xfff
9785 13:27:31.655695 INFO: [NOCDAPC] D10_APC_0: 0x0
9786 13:27:31.658858 INFO: [NOCDAPC] D10_APC_1: 0xfff
9787 13:27:31.662544 INFO: [NOCDAPC] D11_APC_0: 0x0
9788 13:27:31.665443 INFO: [NOCDAPC] D11_APC_1: 0xfff
9789 13:27:31.668974 INFO: [NOCDAPC] D12_APC_0: 0x0
9790 13:27:31.671842 INFO: [NOCDAPC] D12_APC_1: 0xfff
9791 13:27:31.675213 INFO: [NOCDAPC] D13_APC_0: 0x0
9792 13:27:31.679214 INFO: [NOCDAPC] D13_APC_1: 0xfff
9793 13:27:31.682492 INFO: [NOCDAPC] D14_APC_0: 0x0
9794 13:27:31.685332 INFO: [NOCDAPC] D14_APC_1: 0xfff
9795 13:27:31.688529 INFO: [NOCDAPC] D15_APC_0: 0x0
9796 13:27:31.688928 INFO: [NOCDAPC] D15_APC_1: 0xfff
9797 13:27:31.692365 INFO: [NOCDAPC] APC_CON: 0x4
9798 13:27:31.695417 INFO: [APUAPC] set_apusys_apc done
9799 13:27:31.699038 INFO: [DEVAPC] devapc_init done
9800 13:27:31.705192 INFO: GICv3 without legacy support detected.
9801 13:27:31.708351 INFO: ARM GICv3 driver initialized in EL3
9802 13:27:31.711632 INFO: Maximum SPI INTID supported: 639
9803 13:27:31.715029 INFO: BL31: Initializing runtime services
9804 13:27:31.721746 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9805 13:27:31.725279 INFO: SPM: enable CPC mode
9806 13:27:31.728164 INFO: mcdi ready for mcusys-off-idle and system suspend
9807 13:27:31.734933 INFO: BL31: Preparing for EL3 exit to normal world
9808 13:27:31.738069 INFO: Entry point address = 0x80000000
9809 13:27:31.738505 INFO: SPSR = 0x8
9810 13:27:31.745129
9811 13:27:31.745564
9812 13:27:31.745970
9813 13:27:31.748099 Starting depthcharge on Spherion...
9814 13:27:31.748651
9815 13:27:31.749114 Wipe memory regions:
9816 13:27:31.749484
9817 13:27:31.751755 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
9818 13:27:31.752323 start: 2.2.4 bootloader-commands (timeout 00:04:21) [common]
9819 13:27:31.752903 Setting prompt string to ['asurada:']
9820 13:27:31.753460 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:21)
9821 13:27:31.754328 [0x00000040000000, 0x00000054600000)
9822 13:27:31.874142
9823 13:27:31.874615 [0x00000054660000, 0x00000080000000)
9824 13:27:32.135020
9825 13:27:32.135534 [0x000000821a7280, 0x000000ffe64000)
9826 13:27:32.879862
9827 13:27:32.880387 [0x00000100000000, 0x00000140000000)
9828 13:27:33.261304
9829 13:27:33.264027 Initializing XHCI USB controller at 0x11200000.
9830 13:27:34.302193
9831 13:27:34.305420 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9832 13:27:34.305851
9833 13:27:34.306187
9834 13:27:34.306897 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9835 13:27:34.307291 Sending line: 'tftpboot 192.168.201.1 14879058/tftp-deploy-136pl3gy/kernel/image.itb 14879058/tftp-deploy-136pl3gy/kernel/cmdline '
9837 13:27:34.408679 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9838 13:27:34.409458 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:18)
9839 13:27:34.413967 asurada: tftpboot 192.168.201.1 14879058/tftp-deploy-136pl3gy/kernel/image.itp-deploy-136pl3gy/kernel/cmdline
9840 13:27:34.414373
9841 13:27:34.414704 Waiting for link
9842 13:27:34.572373
9843 13:27:34.572907 R8152: Initializing
9844 13:27:34.573294
9845 13:27:34.575109 Version 9 (ocp_data = 6010)
9846 13:27:34.575535
9847 13:27:34.579004 R8152: Done initializing
9848 13:27:34.579510
9849 13:27:34.579845 Adding net device
9850 13:27:36.589516
9851 13:27:36.589659 done.
9852 13:27:36.589726
9853 13:27:36.589786 MAC: 00:e0:4c:68:03:bd
9854 13:27:36.589845
9855 13:27:36.592441 Sending DHCP discover... done.
9856 13:27:36.592541
9857 13:27:43.234737 Waiting for reply... done.
9858 13:27:43.234872
9859 13:27:43.234936 Sending DHCP request... done.
9860 13:27:43.237160
9861 13:27:43.254000 Waiting for reply... done.
9862 13:27:43.254135
9863 13:27:43.254197 My ip is 192.168.201.16
9864 13:27:43.254250
9865 13:27:43.256933 The DHCP server ip is 192.168.201.1
9866 13:27:43.257020
9867 13:27:43.263989 TFTP server IP predefined by user: 192.168.201.1
9868 13:27:43.264128
9869 13:27:43.270657 Bootfile predefined by user: 14879058/tftp-deploy-136pl3gy/kernel/image.itb
9870 13:27:43.270791
9871 13:27:43.275526 Sending tftp read request... done.
9872 13:27:43.275671
9873 13:27:43.275751 Waiting for the transfer...
9874 13:27:43.275812
9875 13:27:43.531028 00000000 ################################################################
9876 13:27:43.531154
9877 13:27:43.790307 00080000 ################################################################
9878 13:27:43.790431
9879 13:27:44.040745 00100000 ################################################################
9880 13:27:44.040864
9881 13:27:44.303128 00180000 ################################################################
9882 13:27:44.303273
9883 13:27:44.575598 00200000 ################################################################
9884 13:27:44.575713
9885 13:27:44.855713 00280000 ################################################################
9886 13:27:44.855841
9887 13:27:45.139044 00300000 ################################################################
9888 13:27:45.139169
9889 13:27:45.432822 00380000 ################################################################
9890 13:27:45.432964
9891 13:27:45.711609 00400000 ################################################################
9892 13:27:45.711734
9893 13:27:45.986555 00480000 ################################################################
9894 13:27:45.986684
9895 13:27:46.245742 00500000 ################################################################
9896 13:27:46.245865
9897 13:27:46.500025 00580000 ################################################################
9898 13:27:46.500144
9899 13:27:46.784658 00600000 ################################################################
9900 13:27:46.784775
9901 13:27:47.059973 00680000 ################################################################
9902 13:27:47.060101
9903 13:27:47.320728 00700000 ################################################################
9904 13:27:47.320855
9905 13:27:47.579287 00780000 ################################################################
9906 13:27:47.579413
9907 13:27:47.846046 00800000 ################################################################
9908 13:27:47.846171
9909 13:27:48.100813 00880000 ################################################################
9910 13:27:48.100936
9911 13:27:48.373075 00900000 ################################################################
9912 13:27:48.373204
9913 13:27:48.655029 00980000 ################################################################
9914 13:27:48.655154
9915 13:27:48.919427 00a00000 ################################################################
9916 13:27:48.919552
9917 13:27:49.197999 00a80000 ################################################################
9918 13:27:49.198115
9919 13:27:49.468802 00b00000 ################################################################
9920 13:27:49.468926
9921 13:27:49.741072 00b80000 ################################################################
9922 13:27:49.741215
9923 13:27:50.033427 00c00000 ################################################################
9924 13:27:50.033548
9925 13:27:50.300156 00c80000 ################################################################
9926 13:27:50.300280
9927 13:27:50.590695 00d00000 ################################################################
9928 13:27:50.590820
9929 13:27:50.879434 00d80000 ################################################################
9930 13:27:50.879554
9931 13:27:51.150011 00e00000 ################################################################
9932 13:27:51.150126
9933 13:27:51.420138 00e80000 ################################################################
9934 13:27:51.420262
9935 13:27:51.713616 00f00000 ################################################################
9936 13:27:51.713741
9937 13:27:51.984111 00f80000 ################################################################
9938 13:27:51.984232
9939 13:27:52.246750 01000000 ################################################################
9940 13:27:52.246888
9941 13:27:52.497353 01080000 ################################################################
9942 13:27:52.497479
9943 13:27:52.774835 01100000 ################################################################
9944 13:27:52.774954
9945 13:27:53.066495 01180000 ################################################################
9946 13:27:53.066618
9947 13:27:53.325780 01200000 ################################################################
9948 13:27:53.325898
9949 13:27:53.601399 01280000 ################################################################
9950 13:27:53.601526
9951 13:27:53.900274 01300000 ################################################################
9952 13:27:53.900404
9953 13:27:54.182484 01380000 ################################################################
9954 13:27:54.182609
9955 13:27:54.462718 01400000 ################################################################
9956 13:27:54.462836
9957 13:27:54.732560 01480000 ################################################################
9958 13:27:54.732687
9959 13:27:55.007336 01500000 ################################################################
9960 13:27:55.007459
9961 13:27:55.258052 01580000 ################################################################
9962 13:27:55.258167
9963 13:27:55.528149 01600000 ################################################################
9964 13:27:55.528269
9965 13:27:55.785947 01680000 ################################################################
9966 13:27:55.786089
9967 13:27:56.051060 01700000 ################################################################
9968 13:27:56.051182
9969 13:27:56.332571 01780000 ################################################################
9970 13:27:56.332693
9971 13:27:56.603072 01800000 ################################################################
9972 13:27:56.603191
9973 13:27:56.858093 01880000 ################################################################
9974 13:27:56.858234
9975 13:27:57.115204 01900000 ################################################################
9976 13:27:57.115326
9977 13:27:57.365987 01980000 ################################################################
9978 13:27:57.366116
9979 13:27:57.622283 01a00000 ################################################################
9980 13:27:57.622405
9981 13:27:57.874935 01a80000 ################################################################
9982 13:27:57.875058
9983 13:27:58.140275 01b00000 ################################################################
9984 13:27:58.140404
9985 13:27:58.432394 01b80000 ################################################################
9986 13:27:58.432521
9987 13:27:58.729884 01c00000 ################################################################
9988 13:27:58.730004
9989 13:27:59.027781 01c80000 ################################################################
9990 13:27:59.027896
9991 13:27:59.322607 01d00000 ################################################################
9992 13:27:59.322732
9993 13:27:59.620206 01d80000 ################################################################
9994 13:27:59.620326
9995 13:27:59.861768 01e00000 #################################################### done.
9996 13:27:59.861908
9997 13:27:59.865118 The bootfile was 31883182 bytes long.
9998 13:27:59.865203
9999 13:27:59.868738 Sending tftp read request... done.
10000 13:27:59.868892
10001 13:27:59.868977 Waiting for the transfer...
10002 13:27:59.869055
10003 13:27:59.871703 00000000 # done.
10004 13:27:59.871813
10005 13:27:59.878217 Command line loaded dynamically from TFTP file: 14879058/tftp-deploy-136pl3gy/kernel/cmdline
10006 13:27:59.878322
10007 13:27:59.901419 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14879058/extract-nfsrootfs-h0v4silq,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10008 13:27:59.901664
10009 13:27:59.901798 Loading FIT.
10010 13:27:59.901940
10011 13:27:59.904908 Image ramdisk-1 has 18719426 bytes.
10012 13:27:59.905161
10013 13:27:59.908535 Image fdt-1 has 47258 bytes.
10014 13:27:59.908841
10015 13:27:59.911166 Image kernel-1 has 13114469 bytes.
10016 13:27:59.911397
10017 13:27:59.921475 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10018 13:27:59.921940
10019 13:27:59.938502 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10020 13:27:59.938944
10021 13:27:59.944778 Choosing best match conf-1 for compat google,spherion-rev3.
10022 13:27:59.945250
10023 13:27:59.952817 Connected to device vid:did:rid of 1ae0:0028:00
10024 13:27:59.960231
10025 13:27:59.962567 tpm_get_response: command 0x17b, return code 0x0
10026 13:27:59.963007
10027 13:27:59.966095 ec_init: CrosEC protocol v3 supported (256, 248)
10028 13:27:59.970085
10029 13:27:59.973347 tpm_cleanup: add release locality here.
10030 13:27:59.973851
10031 13:27:59.974184 Shutting down all USB controllers.
10032 13:27:59.976546
10033 13:27:59.976971 Removing current net device
10034 13:27:59.977341
10035 13:27:59.983389 Exiting depthcharge with code 4 at timestamp: 56498688
10036 13:27:59.983906
10037 13:27:59.986574 LZMA decompressing kernel-1 to 0x821a6718
10038 13:27:59.987005
10039 13:27:59.989653 LZMA decompressing kernel-1 to 0x40000000
10040 13:28:01.604435
10041 13:28:01.604937 jumping to kernel
10042 13:28:01.606742 end: 2.2.4 bootloader-commands (duration 00:00:30) [common]
10043 13:28:01.607249 start: 2.2.5 auto-login-action (timeout 00:03:51) [common]
10044 13:28:01.607614 Setting prompt string to ['Linux version [0-9]']
10045 13:28:01.607957 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10046 13:28:01.608305 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10047 13:28:01.654326
10048 13:28:01.657300 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10049 13:28:01.661585 start: 2.2.5.1 login-action (timeout 00:03:51) [common]
10050 13:28:01.662162 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10051 13:28:01.662541 Setting prompt string to []
10052 13:28:01.662932 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10053 13:28:01.663282 Using line separator: #'\n'#
10054 13:28:01.663796 No login prompt set.
10055 13:28:01.664176 Parsing kernel messages
10056 13:28:01.664469 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10057 13:28:01.665018 [login-action] Waiting for messages, (timeout 00:03:51)
10058 13:28:01.665401 Waiting using forced prompt support (timeout 00:01:56)
10059 13:28:01.680907 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j272990-arm64-gcc-12-defconfig-arm64-chromebook-fgzcq) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024
10060 13:28:01.683813 [ 0.000000] random: crng init done
10061 13:28:01.686863 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10062 13:28:01.690236 [ 0.000000] efi: UEFI not found.
10063 13:28:01.700491 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10064 13:28:01.707117 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10065 13:28:01.717032 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10066 13:28:01.726961 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10067 13:28:01.733858 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10068 13:28:01.736778 [ 0.000000] printk: bootconsole [mtk8250] enabled
10069 13:28:01.745321 [ 0.000000] NUMA: No NUMA configuration found
10070 13:28:01.752147 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10071 13:28:01.758304 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10072 13:28:01.758803 [ 0.000000] Zone ranges:
10073 13:28:01.765080 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10074 13:28:01.768553 [ 0.000000] DMA32 empty
10075 13:28:01.775259 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10076 13:28:01.778127 [ 0.000000] Movable zone start for each node
10077 13:28:01.781845 [ 0.000000] Early memory node ranges
10078 13:28:01.787904 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10079 13:28:01.794644 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10080 13:28:01.801553 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10081 13:28:01.808115 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10082 13:28:01.815243 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10083 13:28:01.821413 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10084 13:28:01.852337 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10085 13:28:01.858998 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10086 13:28:01.865457 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10087 13:28:01.868668 [ 0.000000] psci: probing for conduit method from DT.
10088 13:28:01.875590 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10089 13:28:01.878387 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10090 13:28:01.885378 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10091 13:28:01.888537 [ 0.000000] psci: SMC Calling Convention v1.2
10092 13:28:01.894851 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10093 13:28:01.898668 [ 0.000000] Detected VIPT I-cache on CPU0
10094 13:28:01.904761 [ 0.000000] CPU features: detected: GIC system register CPU interface
10095 13:28:01.911371 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10096 13:28:01.917909 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10097 13:28:01.924751 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10098 13:28:01.934929 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10099 13:28:01.941588 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10100 13:28:01.944428 [ 0.000000] alternatives: applying boot alternatives
10101 13:28:01.950761 [ 0.000000] Fallback order for Node 0: 0
10102 13:28:01.957988 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10103 13:28:01.960776 [ 0.000000] Policy zone: Normal
10104 13:28:01.983844 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14879058/extract-nfsrootfs-h0v4silq,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10105 13:28:01.993891 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10106 13:28:02.004127 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10107 13:28:02.010647 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10108 13:28:02.020979 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10109 13:28:02.023913 <6>[ 0.000000] software IO TLB: area num 8.
10110 13:28:02.079234 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10111 13:28:02.159729 <6>[ 0.000000] Memory: 3831368K/4191232K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 327096K reserved, 32768K cma-reserved)
10112 13:28:02.166085 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10113 13:28:02.172735 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10114 13:28:02.176269 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10115 13:28:02.182881 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10116 13:28:02.189353 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10117 13:28:02.192973 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10118 13:28:02.202655 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10119 13:28:02.209448 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10120 13:28:02.215618 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10121 13:28:02.222730 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10122 13:28:02.225491 <6>[ 0.000000] GICv3: 608 SPIs implemented
10123 13:28:02.228869 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10124 13:28:02.235675 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10125 13:28:02.238780 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10126 13:28:02.245459 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10127 13:28:02.259051 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10128 13:28:02.271705 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10129 13:28:02.278733 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10130 13:28:02.286396 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10131 13:28:02.299388 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10132 13:28:02.306193 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10133 13:28:02.312383 <6>[ 0.009173] Console: colour dummy device 80x25
10134 13:28:02.322887 <6>[ 0.013905] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10135 13:28:02.329188 <6>[ 0.024412] pid_max: default: 32768 minimum: 301
10136 13:28:02.332525 <6>[ 0.029285] LSM: Security Framework initializing
10137 13:28:02.338764 <6>[ 0.034197] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10138 13:28:02.348934 <6>[ 0.041803] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10139 13:28:02.356040 <6>[ 0.051038] cblist_init_generic: Setting adjustable number of callback queues.
10140 13:28:02.361222 <6>[ 0.058478] cblist_init_generic: Setting shift to 3 and lim to 1.
10141 13:28:02.371878 <6>[ 0.064819] cblist_init_generic: Setting adjustable number of callback queues.
10142 13:28:02.378059 <6>[ 0.072246] cblist_init_generic: Setting shift to 3 and lim to 1.
10143 13:28:02.381167 <6>[ 0.078646] rcu: Hierarchical SRCU implementation.
10144 13:28:02.387723 <6>[ 0.083661] rcu: Max phase no-delay instances is 1000.
10145 13:28:02.394478 <6>[ 0.090689] EFI services will not be available.
10146 13:28:02.398193 <6>[ 0.095648] smp: Bringing up secondary CPUs ...
10147 13:28:02.406311 <6>[ 0.100727] Detected VIPT I-cache on CPU1
10148 13:28:02.412339 <6>[ 0.100799] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10149 13:28:02.419095 <6>[ 0.100830] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10150 13:28:02.422407 <6>[ 0.101164] Detected VIPT I-cache on CPU2
10151 13:28:02.432173 <6>[ 0.101216] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10152 13:28:02.438656 <6>[ 0.101232] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10153 13:28:02.442367 <6>[ 0.101494] Detected VIPT I-cache on CPU3
10154 13:28:02.448701 <6>[ 0.101543] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10155 13:28:02.455684 <6>[ 0.101557] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10156 13:28:02.462423 <6>[ 0.101863] CPU features: detected: Spectre-v4
10157 13:28:02.465571 <6>[ 0.101869] CPU features: detected: Spectre-BHB
10158 13:28:02.468496 <6>[ 0.101875] Detected PIPT I-cache on CPU4
10159 13:28:02.475563 <6>[ 0.101934] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10160 13:28:02.485438 <6>[ 0.101951] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10161 13:28:02.488298 <6>[ 0.102242] Detected PIPT I-cache on CPU5
10162 13:28:02.495300 <6>[ 0.102304] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10163 13:28:02.501503 <6>[ 0.102320] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10164 13:28:02.504805 <6>[ 0.102603] Detected PIPT I-cache on CPU6
10165 13:28:02.515314 <6>[ 0.102667] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10166 13:28:02.521136 <6>[ 0.102683] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10167 13:28:02.524933 <6>[ 0.102982] Detected PIPT I-cache on CPU7
10168 13:28:02.531476 <6>[ 0.103048] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10169 13:28:02.537634 <6>[ 0.103063] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10170 13:28:02.541077 <6>[ 0.103111] smp: Brought up 1 node, 8 CPUs
10171 13:28:02.548004 <6>[ 0.244586] SMP: Total of 8 processors activated.
10172 13:28:02.554330 <6>[ 0.249507] CPU features: detected: 32-bit EL0 Support
10173 13:28:02.561133 <6>[ 0.254870] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10174 13:28:02.568649 <6>[ 0.263670] CPU features: detected: Common not Private translations
10175 13:28:02.573963 <6>[ 0.270147] CPU features: detected: CRC32 instructions
10176 13:28:02.580795 <6>[ 0.275498] CPU features: detected: RCpc load-acquire (LDAPR)
10177 13:28:02.584098 <6>[ 0.281495] CPU features: detected: LSE atomic instructions
10178 13:28:02.590475 <6>[ 0.287277] CPU features: detected: Privileged Access Never
10179 13:28:02.597145 <6>[ 0.293092] CPU features: detected: RAS Extension Support
10180 13:28:02.603719 <6>[ 0.298701] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10181 13:28:02.607797 <6>[ 0.305922] CPU: All CPU(s) started at EL2
10182 13:28:02.613636 <6>[ 0.310239] alternatives: applying system-wide alternatives
10183 13:28:02.623488 <6>[ 0.320258] devtmpfs: initialized
10184 13:28:02.638164 <6>[ 0.328363] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10185 13:28:02.644800 <6>[ 0.338318] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10186 13:28:02.651690 <6>[ 0.346561] pinctrl core: initialized pinctrl subsystem
10187 13:28:02.654798 <6>[ 0.353229] DMI not present or invalid.
10188 13:28:02.661287 <6>[ 0.357632] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10189 13:28:02.671684 <6>[ 0.364508] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10190 13:28:02.677964 <6>[ 0.371954] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10191 13:28:02.688245 <6>[ 0.380043] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10192 13:28:02.691332 <6>[ 0.388195] audit: initializing netlink subsys (disabled)
10193 13:28:02.701388 <5>[ 0.393887] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10194 13:28:02.707744 <6>[ 0.394597] thermal_sys: Registered thermal governor 'step_wise'
10195 13:28:02.714537 <6>[ 0.401849] thermal_sys: Registered thermal governor 'power_allocator'
10196 13:28:02.717920 <6>[ 0.408104] cpuidle: using governor menu
10197 13:28:02.724991 <6>[ 0.419058] NET: Registered PF_QIPCRTR protocol family
10198 13:28:02.730601 <6>[ 0.424563] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10199 13:28:02.734228 <6>[ 0.431667] ASID allocator initialised with 32768 entries
10200 13:28:02.741887 <6>[ 0.438224] Serial: AMBA PL011 UART driver
10201 13:28:02.751327 <4>[ 0.447526] Trying to register duplicate clock ID: 134
10202 13:28:02.808975 <6>[ 0.508766] KASLR enabled
10203 13:28:02.823111 <6>[ 0.516435] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10204 13:28:02.829893 <6>[ 0.523447] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10205 13:28:02.836572 <6>[ 0.529937] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10206 13:28:02.843583 <6>[ 0.536944] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10207 13:28:02.850062 <6>[ 0.543428] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10208 13:28:02.856387 <6>[ 0.550430] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10209 13:28:02.863080 <6>[ 0.556915] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10210 13:28:02.869855 <6>[ 0.563918] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10211 13:28:02.873547 <6>[ 0.571432] ACPI: Interpreter disabled.
10212 13:28:02.881894 <6>[ 0.577845] iommu: Default domain type: Translated
10213 13:28:02.887549 <6>[ 0.582959] iommu: DMA domain TLB invalidation policy: strict mode
10214 13:28:02.891741 <5>[ 0.589607] SCSI subsystem initialized
10215 13:28:02.897544 <6>[ 0.593746] usbcore: registered new interface driver usbfs
10216 13:28:02.904160 <6>[ 0.599476] usbcore: registered new interface driver hub
10217 13:28:02.908032 <6>[ 0.605030] usbcore: registered new device driver usb
10218 13:28:02.914861 <6>[ 0.611127] pps_core: LinuxPPS API ver. 1 registered
10219 13:28:02.925028 <6>[ 0.616317] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10220 13:28:02.928834 <6>[ 0.625659] PTP clock support registered
10221 13:28:02.930797 <6>[ 0.629900] EDAC MC: Ver: 3.0.0
10222 13:28:02.938639 <6>[ 0.635054] FPGA manager framework
10223 13:28:02.945361 <6>[ 0.638738] Advanced Linux Sound Architecture Driver Initialized.
10224 13:28:02.948096 <6>[ 0.645525] vgaarb: loaded
10225 13:28:02.955057 <6>[ 0.648688] clocksource: Switched to clocksource arch_sys_counter
10226 13:28:02.958751 <5>[ 0.655129] VFS: Disk quotas dquot_6.6.0
10227 13:28:02.964973 <6>[ 0.659309] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10228 13:28:02.968306 <6>[ 0.666494] pnp: PnP ACPI: disabled
10229 13:28:02.977009 <6>[ 0.673161] NET: Registered PF_INET protocol family
10230 13:28:02.983363 <6>[ 0.678543] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10231 13:28:02.995450 <6>[ 0.688539] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10232 13:28:03.005617 <6>[ 0.697325] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10233 13:28:03.011860 <6>[ 0.705292] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10234 13:28:03.018022 <6>[ 0.713695] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10235 13:28:03.029221 <6>[ 0.722345] TCP: Hash tables configured (established 32768 bind 32768)
10236 13:28:03.036219 <6>[ 0.729205] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10237 13:28:03.042426 <6>[ 0.736222] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10238 13:28:03.049004 <6>[ 0.743740] NET: Registered PF_UNIX/PF_LOCAL protocol family
10239 13:28:03.055699 <6>[ 0.749862] RPC: Registered named UNIX socket transport module.
10240 13:28:03.059359 <6>[ 0.756015] RPC: Registered udp transport module.
10241 13:28:03.065412 <6>[ 0.760947] RPC: Registered tcp transport module.
10242 13:28:03.072163 <6>[ 0.765880] RPC: Registered tcp NFSv4.1 backchannel transport module.
10243 13:28:03.075446 <6>[ 0.772543] PCI: CLS 0 bytes, default 64
10244 13:28:03.078880 <6>[ 0.776837] Unpacking initramfs...
10245 13:28:03.108407 <6>[ 0.801281] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10246 13:28:03.117982 <6>[ 0.809956] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10247 13:28:03.121468 <6>[ 0.818802] kvm [1]: IPA Size Limit: 40 bits
10248 13:28:03.128133 <6>[ 0.823330] kvm [1]: GICv3: no GICV resource entry
10249 13:28:03.131162 <6>[ 0.828349] kvm [1]: disabling GICv2 emulation
10250 13:28:03.137613 <6>[ 0.833037] kvm [1]: GIC system register CPU interface enabled
10251 13:28:03.141394 <6>[ 0.839202] kvm [1]: vgic interrupt IRQ18
10252 13:28:03.147541 <6>[ 0.843555] kvm [1]: VHE mode initialized successfully
10253 13:28:03.154207 <5>[ 0.849980] Initialise system trusted keyrings
10254 13:28:03.160744 <6>[ 0.854779] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10255 13:28:03.168321 <6>[ 0.864700] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10256 13:28:03.174754 <5>[ 0.871070] NFS: Registering the id_resolver key type
10257 13:28:03.178043 <5>[ 0.876368] Key type id_resolver registered
10258 13:28:03.184697 <5>[ 0.880784] Key type id_legacy registered
10259 13:28:03.191637 <6>[ 0.885081] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10260 13:28:03.197966 <6>[ 0.892002] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10261 13:28:03.204102 <6>[ 0.899742] 9p: Installing v9fs 9p2000 file system support
10262 13:28:03.241213 <5>[ 0.937689] Key type asymmetric registered
10263 13:28:03.244542 <5>[ 0.942024] Asymmetric key parser 'x509' registered
10264 13:28:03.253927 <6>[ 0.947196] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10265 13:28:03.257299 <6>[ 0.954811] io scheduler mq-deadline registered
10266 13:28:03.260874 <6>[ 0.959570] io scheduler kyber registered
10267 13:28:03.280113 <6>[ 0.976848] EINJ: ACPI disabled.
10268 13:28:03.313370 <4>[ 1.003182] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10269 13:28:03.322858 <4>[ 1.013823] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10270 13:28:03.338059 <6>[ 1.034896] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10271 13:28:03.346979 <6>[ 1.042965] printk: console [ttyS0] disabled
10272 13:28:03.374590 <6>[ 1.067599] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10273 13:28:03.381860 <6>[ 1.077079] printk: console [ttyS0] enabled
10274 13:28:03.384420 <6>[ 1.077079] printk: console [ttyS0] enabled
10275 13:28:03.390928 <6>[ 1.085975] printk: bootconsole [mtk8250] disabled
10276 13:28:03.394107 <6>[ 1.085975] printk: bootconsole [mtk8250] disabled
10277 13:28:03.400806 <6>[ 1.097125] SuperH (H)SCI(F) driver initialized
10278 13:28:03.404338 <6>[ 1.102420] msm_serial: driver initialized
10279 13:28:03.418557 <6>[ 1.111495] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10280 13:28:03.428548 <6>[ 1.120051] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10281 13:28:03.434957 <6>[ 1.128592] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10282 13:28:03.444991 <6>[ 1.137220] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10283 13:28:03.455012 <6>[ 1.145927] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10284 13:28:03.461572 <6>[ 1.154640] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10285 13:28:03.471373 <6>[ 1.163180] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10286 13:28:03.477867 <6>[ 1.171987] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10287 13:28:03.487808 <6>[ 1.180529] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10288 13:28:03.499922 <6>[ 1.196155] loop: module loaded
10289 13:28:03.506152 <6>[ 1.202118] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10290 13:28:03.529161 <4>[ 1.225424] mtk-pmic-keys: Failed to locate of_node [id: -1]
10291 13:28:03.536806 <6>[ 1.232417] megasas: 07.719.03.00-rc1
10292 13:28:03.545976 <6>[ 1.242269] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10293 13:28:03.552848 <6>[ 1.244116] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10294 13:28:03.567599 <6>[ 1.264167] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10295 13:28:03.624772 <6>[ 1.314439] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10296 13:28:03.876346 <6>[ 1.572212] Freeing initrd memory: 18276K
10297 13:28:03.887159 <6>[ 1.583943] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10298 13:28:03.898404 <6>[ 1.594826] tun: Universal TUN/TAP device driver, 1.6
10299 13:28:03.901927 <6>[ 1.600902] thunder_xcv, ver 1.0
10300 13:28:03.904875 <6>[ 1.604396] thunder_bgx, ver 1.0
10301 13:28:03.908006 <6>[ 1.607893] nicpf, ver 1.0
10302 13:28:03.918850 <6>[ 1.611917] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10303 13:28:03.922002 <6>[ 1.619393] hns3: Copyright (c) 2017 Huawei Corporation.
10304 13:28:03.928504 <6>[ 1.624981] hclge is initializing
10305 13:28:03.931797 <6>[ 1.628553] e1000: Intel(R) PRO/1000 Network Driver
10306 13:28:03.938373 <6>[ 1.633683] e1000: Copyright (c) 1999-2006 Intel Corporation.
10307 13:28:03.942016 <6>[ 1.639695] e1000e: Intel(R) PRO/1000 Network Driver
10308 13:28:03.948849 <6>[ 1.644911] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10309 13:28:03.955541 <6>[ 1.651099] igb: Intel(R) Gigabit Ethernet Network Driver
10310 13:28:03.961866 <6>[ 1.656750] igb: Copyright (c) 2007-2014 Intel Corporation.
10311 13:28:03.968312 <6>[ 1.662586] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10312 13:28:03.975283 <6>[ 1.669104] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10313 13:28:03.978408 <6>[ 1.675565] sky2: driver version 1.30
10314 13:28:03.985022 <6>[ 1.680497] usbcore: registered new device driver r8152-cfgselector
10315 13:28:03.991472 <6>[ 1.687031] usbcore: registered new interface driver r8152
10316 13:28:03.995217 <6>[ 1.692855] VFIO - User Level meta-driver version: 0.3
10317 13:28:04.004477 <6>[ 1.701084] usbcore: registered new interface driver usb-storage
10318 13:28:04.011061 <6>[ 1.707524] usbcore: registered new device driver onboard-usb-hub
10319 13:28:04.020668 <6>[ 1.716639] mt6397-rtc mt6359-rtc: registered as rtc0
10320 13:28:04.030805 <6>[ 1.722104] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-18T13:28:04 UTC (1721309284)
10321 13:28:04.033516 <6>[ 1.731673] i2c_dev: i2c /dev entries driver
10322 13:28:04.046992 <4>[ 1.743768] cpu cpu0: supply cpu not found, using dummy regulator
10323 13:28:04.053907 <4>[ 1.750184] cpu cpu1: supply cpu not found, using dummy regulator
10324 13:28:04.061463 <4>[ 1.756585] cpu cpu2: supply cpu not found, using dummy regulator
10325 13:28:04.067260 <4>[ 1.762999] cpu cpu3: supply cpu not found, using dummy regulator
10326 13:28:04.073593 <4>[ 1.769396] cpu cpu4: supply cpu not found, using dummy regulator
10327 13:28:04.080222 <4>[ 1.775805] cpu cpu5: supply cpu not found, using dummy regulator
10328 13:28:04.087046 <4>[ 1.782206] cpu cpu6: supply cpu not found, using dummy regulator
10329 13:28:04.093383 <4>[ 1.788599] cpu cpu7: supply cpu not found, using dummy regulator
10330 13:28:04.113803 <6>[ 1.809213] cpu cpu0: EM: created perf domain
10331 13:28:04.116052 <6>[ 1.814143] cpu cpu4: EM: created perf domain
10332 13:28:04.123398 <6>[ 1.819696] sdhci: Secure Digital Host Controller Interface driver
10333 13:28:04.129733 <6>[ 1.826128] sdhci: Copyright(c) Pierre Ossman
10334 13:28:04.136414 <6>[ 1.831048] Synopsys Designware Multimedia Card Interface Driver
10335 13:28:04.143621 <6>[ 1.837646] sdhci-pltfm: SDHCI platform and OF driver helper
10336 13:28:04.146316 <6>[ 1.837807] mmc0: CQHCI version 5.10
10337 13:28:04.153151 <6>[ 1.847686] ledtrig-cpu: registered to indicate activity on CPUs
10338 13:28:04.159894 <6>[ 1.854709] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10339 13:28:04.166171 <6>[ 1.861737] usbcore: registered new interface driver usbhid
10340 13:28:04.169414 <6>[ 1.867558] usbhid: USB HID core driver
10341 13:28:04.176251 <6>[ 1.871759] spi_master spi0: will run message pump with realtime priority
10342 13:28:04.223365 <6>[ 1.913485] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10343 13:28:04.243089 <6>[ 1.929078] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10344 13:28:04.246395 <6>[ 1.941480] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15c14
10345 13:28:04.253348 <6>[ 1.944146] cros-ec-spi spi0.0: Chrome EC device registered
10346 13:28:04.256313 <6>[ 1.954531] mmc0: Command Queue Engine enabled
10347 13:28:04.263032 <6>[ 1.959254] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10348 13:28:04.270284 <6>[ 1.966817] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10349 13:28:04.280429 <6>[ 1.967934] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10350 13:28:04.286621 <6>[ 1.975599] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10351 13:28:04.290090 <6>[ 1.981938] NET: Registered PF_PACKET protocol family
10352 13:28:04.297191 <6>[ 1.988235] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10353 13:28:04.300207 <6>[ 1.992231] 9pnet: Installing 9P2000 support
10354 13:28:04.306702 <6>[ 1.997993] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10355 13:28:04.310475 <5>[ 2.001922] Key type dns_resolver registered
10356 13:28:04.316786 <6>[ 2.007765] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10357 13:28:04.319838 <6>[ 2.012155] registered taskstats version 1
10358 13:28:04.326460 <5>[ 2.022545] Loading compiled-in X.509 certificates
10359 13:28:04.353142 <4>[ 2.043254] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10360 13:28:04.363707 <4>[ 2.053980] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10361 13:28:04.377310 <6>[ 2.073894] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10362 13:28:04.384543 <6>[ 2.080821] xhci-mtk 11200000.usb: xHCI Host Controller
10363 13:28:04.394039 <6>[ 2.086576] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10364 13:28:04.401389 <6>[ 2.094444] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10365 13:28:04.407234 <6>[ 2.103874] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10366 13:28:04.414137 <6>[ 2.110044] xhci-mtk 11200000.usb: xHCI Host Controller
10367 13:28:04.421076 <6>[ 2.115535] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10368 13:28:04.430233 <6>[ 2.123186] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10369 13:28:04.433435 <6>[ 2.130963] hub 1-0:1.0: USB hub found
10370 13:28:04.436852 <6>[ 2.134987] hub 1-0:1.0: 1 port detected
10371 13:28:04.446988 <6>[ 2.139258] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10372 13:28:04.450565 <6>[ 2.147985] hub 2-0:1.0: USB hub found
10373 13:28:04.454289 <6>[ 2.152004] hub 2-0:1.0: 1 port detected
10374 13:28:04.461739 <6>[ 2.158534] mtk-msdc 11f70000.mmc: Got CD GPIO
10375 13:28:04.480257 <6>[ 2.173475] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10376 13:28:04.490351 <6>[ 2.181850] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10377 13:28:04.496723 <6>[ 2.190189] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10378 13:28:04.507103 <6>[ 2.198528] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10379 13:28:04.513205 <6>[ 2.206865] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10380 13:28:04.522893 <6>[ 2.215204] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10381 13:28:04.529799 <6>[ 2.223542] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10382 13:28:04.539621 <6>[ 2.231880] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10383 13:28:04.546801 <6>[ 2.240218] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10384 13:28:04.556956 <6>[ 2.248557] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10385 13:28:04.562783 <6>[ 2.256899] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10386 13:28:04.573162 <6>[ 2.265237] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10387 13:28:04.579443 <6>[ 2.273575] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10388 13:28:04.589275 <6>[ 2.281913] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10389 13:28:04.597081 <6>[ 2.290250] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10390 13:28:04.602728 <6>[ 2.298952] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10391 13:28:04.609570 <6>[ 2.306109] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10392 13:28:04.617364 <6>[ 2.312866] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10393 13:28:04.626724 <6>[ 2.319606] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10394 13:28:04.632375 <6>[ 2.326512] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10395 13:28:04.639373 <6>[ 2.333349] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10396 13:28:04.649351 <6>[ 2.342480] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10397 13:28:04.659297 <6>[ 2.351603] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10398 13:28:04.669704 <6>[ 2.360897] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10399 13:28:04.678730 <6>[ 2.370364] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10400 13:28:04.688840 <6>[ 2.379831] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10401 13:28:04.695880 <6>[ 2.388950] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10402 13:28:04.705745 <6>[ 2.398416] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10403 13:28:04.715073 <6>[ 2.407534] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10404 13:28:04.725082 <6>[ 2.416844] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10405 13:28:04.735476 <6>[ 2.427005] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10406 13:28:04.745582 <6>[ 2.438516] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10407 13:28:04.753288 <6>[ 2.449579] Trying to probe devices needed for running init ...
10408 13:28:04.763288 <3>[ 2.456820] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10409 13:28:04.843682 <6>[ 2.537295] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10410 13:28:04.873161 <6>[ 2.570090] hub 2-1:1.0: USB hub found
10411 13:28:04.876558 <6>[ 2.574618] hub 2-1:1.0: 3 ports detected
10412 13:28:04.887525 <6>[ 2.584190] hub 2-1:1.0: USB hub found
10413 13:28:04.891404 <6>[ 2.588595] hub 2-1:1.0: 3 ports detected
10414 13:28:04.995848 <6>[ 2.688952] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10415 13:28:05.148902 <6>[ 2.845707] hub 1-1:1.0: USB hub found
10416 13:28:05.152267 <6>[ 2.850089] hub 1-1:1.0: 4 ports detected
10417 13:28:05.166730 <6>[ 2.863380] hub 1-1:1.0: USB hub found
10418 13:28:05.170022 <6>[ 2.867802] hub 1-1:1.0: 4 ports detected
10419 13:28:05.228222 <6>[ 2.921153] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10420 13:28:05.336366 <6>[ 3.029634] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10421 13:28:05.372790 <4>[ 3.065907] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10422 13:28:05.382431 <4>[ 3.075028] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10423 13:28:05.425784 <6>[ 3.122601] r8152 2-1.3:1.0 eth0: v1.12.13
10424 13:28:05.495572 <6>[ 3.188998] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10425 13:28:05.628857 <6>[ 3.324915] hub 1-1.4:1.0: USB hub found
10426 13:28:05.631519 <6>[ 3.329592] hub 1-1.4:1.0: 2 ports detected
10427 13:28:05.646203 <6>[ 3.342452] hub 1-1.4:1.0: USB hub found
10428 13:28:05.649941 <6>[ 3.347103] hub 1-1.4:1.0: 2 ports detected
10429 13:28:05.947553 <6>[ 3.641017] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10430 13:28:06.143093 <6>[ 3.836843] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10431 13:28:07.031943 <6>[ 4.727274] r8152 2-1.3:1.0 eth0: carrier on
10432 13:28:09.551420 <5>[ 4.752765] Sending DHCP requests .., OK
10433 13:28:09.558571 <6>[ 7.253088] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10434 13:28:09.561438 <6>[ 7.261374] IP-Config: Complete:
10435 13:28:09.575314 <6>[ 7.264873] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10436 13:28:09.581755 <6>[ 7.275594] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10437 13:28:09.588337 <6>[ 7.284211] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10438 13:28:09.594417 <6>[ 7.284221] nameserver0=192.168.201.1
10439 13:28:09.597698 <6>[ 7.296361] clk: Disabling unused clocks
10440 13:28:09.602052 <6>[ 7.301897] ALSA device list:
10441 13:28:09.607649 <6>[ 7.305175] No soundcards found.
10442 13:28:09.616461 <6>[ 7.312808] Freeing unused kernel memory: 8512K
10443 13:28:09.618611 <6>[ 7.317713] Run /init as init process
10444 13:28:09.628420 Loading, please wait...
10445 13:28:09.653614 Starting systemd-udevd version 252.22-1~deb12u1
10446 13:28:09.874387 <6>[ 7.568327] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10447 13:28:09.881330 <6>[ 7.569830] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10448 13:28:09.894920 <6>[ 7.588962] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10449 13:28:09.901975 <6>[ 7.597160] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10450 13:28:09.911953 <4>[ 7.605350] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10451 13:28:09.918423 <6>[ 7.614923] remoteproc remoteproc0: scp is available
10452 13:28:09.925132 <6>[ 7.615090] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10453 13:28:09.934797 <6>[ 7.616196] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10454 13:28:09.941621 <6>[ 7.616235] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10455 13:28:09.952409 <6>[ 7.616241] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10456 13:28:09.957870 <3>[ 7.618965] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10457 13:28:09.968675 <3>[ 7.618976] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10458 13:28:09.974935 <3>[ 7.618980] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10459 13:28:09.984385 <3>[ 7.619070] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10460 13:28:09.991316 <3>[ 7.619073] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10461 13:28:10.000876 <3>[ 7.619075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10462 13:28:10.008801 <3>[ 7.619082] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10463 13:28:10.014839 <3>[ 7.619086] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10464 13:28:10.025674 <3>[ 7.619112] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10465 13:28:10.032502 <3>[ 7.619132] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10466 13:28:10.038952 <3>[ 7.619135] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10467 13:28:10.049638 <3>[ 7.619139] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10468 13:28:10.055567 <3>[ 7.619161] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10469 13:28:10.065838 <3>[ 7.619163] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10470 13:28:10.072294 <3>[ 7.619166] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10471 13:28:10.081858 <3>[ 7.619169] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10472 13:28:10.088302 <3>[ 7.619171] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10473 13:28:10.098389 <3>[ 7.619182] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10474 13:28:10.101469 <6>[ 7.624099] remoteproc remoteproc0: powering up scp
10475 13:28:10.112379 <6>[ 7.628249] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10476 13:28:10.118010 <6>[ 7.635812] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10477 13:28:10.124743 <6>[ 7.635832] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10478 13:28:10.131896 <4>[ 7.636741] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10479 13:28:10.137992 <4>[ 7.636914] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10480 13:28:10.147971 <6>[ 7.644849] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10481 13:28:10.151551 <6>[ 7.647526] mc: Linux media interface: v0.10
10482 13:28:10.157729 <6>[ 7.656080] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10483 13:28:10.167665 <6>[ 7.661419] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10484 13:28:10.174294 <4>[ 7.681603] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10485 13:28:10.181044 <4>[ 7.681603] Fallback method does not support PEC.
10486 13:28:10.188415 <6>[ 7.685710] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10487 13:28:10.197139 <3>[ 7.708518] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10488 13:28:10.207125 <6>[ 7.710122] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10489 13:28:10.213693 <3>[ 7.737721] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10490 13:28:10.220645 <6>[ 7.738147] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10491 13:28:10.227352 <6>[ 7.738151] pci_bus 0000:00: root bus resource [bus 00-ff]
10492 13:28:10.233884 <6>[ 7.738155] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10493 13:28:10.243714 <6>[ 7.738157] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10494 13:28:10.250921 <6>[ 7.738185] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10495 13:28:10.257184 <6>[ 7.738197] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10496 13:28:10.264306 <6>[ 7.738262] pci 0000:00:00.0: supports D1 D2
10497 13:28:10.269954 <6>[ 7.738263] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10498 13:28:10.277297 <6>[ 7.739136] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10499 13:28:10.283467 <6>[ 7.739200] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10500 13:28:10.289621 <6>[ 7.739224] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10501 13:28:10.299568 <6>[ 7.739239] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10502 13:28:10.306760 <6>[ 7.739254] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10503 13:28:10.310763 <6>[ 7.739354] pci 0000:01:00.0: supports D1 D2
10504 13:28:10.316608 <6>[ 7.739355] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10505 13:28:10.326197 <6>[ 7.743572] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10506 13:28:10.336118 <6>[ 7.745758] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10507 13:28:10.346007 <6>[ 7.746183] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10508 13:28:10.353046 <6>[ 7.752847] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10509 13:28:10.360005 <6>[ 7.775394] videodev: Linux video capture interface: v2.00
10510 13:28:10.366202 <6>[ 7.783048] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10511 13:28:10.372427 <6>[ 7.783079] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10512 13:28:10.382003 <6>[ 7.783133] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10513 13:28:10.389179 <6>[ 7.783141] remoteproc remoteproc0: remote processor scp is now up
10514 13:28:10.396415 <6>[ 7.794305] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10515 13:28:10.405671 <6>[ 7.799182] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10516 13:28:10.412284 <6>[ 7.799194] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10517 13:28:10.421819 <6>[ 7.799207] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10518 13:28:10.428758 <6>[ 7.807463] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10519 13:28:10.438261 <6>[ 7.812243] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10520 13:28:10.441955 <6>[ 7.812256] pci 0000:00:00.0: PCI bridge to [bus 01]
10521 13:28:10.444833 <6>[ 7.813210] Bluetooth: Core ver 2.22
10522 13:28:10.451300 <6>[ 7.813336] NET: Registered PF_BLUETOOTH protocol family
10523 13:28:10.458004 <6>[ 7.813343] Bluetooth: HCI device and connection manager initialized
10524 13:28:10.465052 <6>[ 7.813364] Bluetooth: HCI socket layer initialized
10525 13:28:10.467888 <6>[ 7.813374] Bluetooth: L2CAP socket layer initialized
10526 13:28:10.474858 <6>[ 7.813390] Bluetooth: SCO socket layer initialized
10527 13:28:10.481298 <6>[ 7.855043] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10528 13:28:10.488101 <6>[ 7.860978] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10529 13:28:10.494582 <6>[ 7.861181] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10530 13:28:10.500700 <6>[ 7.869700] usbcore: registered new interface driver btusb
10531 13:28:10.510743 <4>[ 7.870364] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10532 13:28:10.517858 <3>[ 7.870375] Bluetooth: hci0: Failed to load firmware file (-2)
10533 13:28:10.523977 <3>[ 7.870379] Bluetooth: hci0: Failed to set up firmware (-2)
10534 13:28:10.534174 <4>[ 7.870382] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10535 13:28:10.547122 <6>[ 7.870711] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10536 13:28:10.550561 <6>[ 7.870801] usbcore: registered new interface driver uvcvideo
10537 13:28:10.557165 <6>[ 7.883091] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10538 13:28:10.563587 <6>[ 7.883246] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10539 13:28:10.570327 <6>[ 8.267551] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10540 13:28:10.593501 <5>[ 8.287822] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10541 13:28:10.614781 <5>[ 8.308597] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10542 13:28:10.621210 <5>[ 8.316122] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10543 13:28:10.630815 <4>[ 8.324618] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10544 13:28:10.637513 <6>[ 8.333520] cfg80211: failed to load regulatory.db
10545 13:28:10.694518 <6>[ 8.388212] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10546 13:28:10.700611 <6>[ 8.395819] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10547 13:28:10.723807 <6>[ 8.420927] mt7921e 0000:01:00.0: ASIC revision: 79610010
10548 13:28:10.827854 <6>[ 8.521705] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10549 13:28:10.830380 <6>[ 8.521705]
10550 13:28:10.838805 Begin: Loading essential drivers ... done.
10551 13:28:10.842039 Begin: Running /scripts/init-premount ... done.
10552 13:28:10.848868 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10553 13:28:10.858748 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10554 13:28:10.861537 Device /sys/class/net/eth0 found
10555 13:28:10.861968 done.
10556 13:28:10.868723 Begin: Waiting up to 180 secs for any network device to become available ... done.
10557 13:28:10.919430 IP-Config: eth0 hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10558 13:28:10.926515 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10559 13:28:10.933164 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10560 13:28:10.938968 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10561 13:28:10.946066 host : mt8192-asurada-spherion-r0-cbg-4
10562 13:28:10.952561 domain : lava-rack
10563 13:28:10.955464 rootserver: 192.168.201.1 rootpath:
10564 13:28:10.955897 filename :
10565 13:28:11.004687 done.
10566 13:28:11.012244 Begin: Running /scripts/nfs-bottom ... done.
10567 13:28:11.028252 Begin: Running /scripts/init-bottom ... done.
10568 13:28:11.098183 <6>[ 8.792358] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10569 13:28:12.393276 <6>[ 10.090562] NET: Registered PF_INET6 protocol family
10570 13:28:12.400382 <6>[ 10.098211] Segment Routing with IPv6
10571 13:28:12.403930 <6>[ 10.102218] In-situ OAM (IOAM) with IPv6
10572 13:28:12.582895 <30>[ 10.254175] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10573 13:28:12.590012 <30>[ 10.287379] systemd[1]: Detected architecture arm64.
10574 13:28:12.598784
10575 13:28:12.602318 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10576 13:28:12.602843
10577 13:28:12.627971 <30>[ 10.325902] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10578 13:28:13.733965 <30>[ 11.428350] systemd[1]: Queued start job for default target graphical.target.
10579 13:28:13.763712 <30>[ 11.458298] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10580 13:28:13.770591 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10581 13:28:13.792604 <30>[ 11.486728] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10582 13:28:13.802425 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10583 13:28:13.820871 <30>[ 11.514754] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10584 13:28:13.830042 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10585 13:28:13.848651 <30>[ 11.543103] systemd[1]: Created slice user.slice - User and Session Slice.
10586 13:28:13.855384 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10587 13:28:13.878557 <30>[ 11.569847] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10588 13:28:13.888884 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10589 13:28:13.906174 <30>[ 11.597314] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10590 13:28:13.912466 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10591 13:28:13.941039 <30>[ 11.625626] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10592 13:28:13.951776 <30>[ 11.645544] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10593 13:28:13.957816 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10594 13:28:13.974984 <30>[ 11.669017] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10595 13:28:13.981111 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10596 13:28:13.998202 <30>[ 11.693034] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10597 13:28:14.008630 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10598 13:28:14.023797 <30>[ 11.721113] systemd[1]: Reached target paths.target - Path Units.
10599 13:28:14.030042 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10600 13:28:14.051035 <30>[ 11.745413] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10601 13:28:14.057806 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10602 13:28:14.071701 <30>[ 11.768983] systemd[1]: Reached target slices.target - Slice Units.
10603 13:28:14.081304 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10604 13:28:14.095641 <30>[ 11.793023] systemd[1]: Reached target swap.target - Swaps.
10605 13:28:14.101837 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10606 13:28:14.122716 <30>[ 11.817070] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10607 13:28:14.132249 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10608 13:28:14.150725 <30>[ 11.845435] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10609 13:28:14.160063 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10610 13:28:14.181458 <30>[ 11.876388] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10611 13:28:14.191074 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10612 13:28:14.207546 <30>[ 11.902416] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10613 13:28:14.217429 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10614 13:28:14.234411 <30>[ 11.929679] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10615 13:28:14.241205 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10616 13:28:14.259866 <30>[ 11.954522] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10617 13:28:14.269904 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10618 13:28:14.289367 <30>[ 11.984203] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10619 13:28:14.299593 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10620 13:28:14.315433 <30>[ 12.009482] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10621 13:28:14.324795 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10622 13:28:14.374959 <30>[ 12.069175] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10623 13:28:14.381172 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10624 13:28:14.403028 <30>[ 12.097716] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10625 13:28:14.409929 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10626 13:28:14.458829 <30>[ 12.153195] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10627 13:28:14.465099 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10628 13:28:14.489950 <30>[ 12.177638] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10629 13:28:14.504527 <30>[ 12.199469] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10630 13:28:14.515244 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10631 13:28:14.534255 <30>[ 12.228910] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10632 13:28:14.541011 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10633 13:28:14.567728 <30>[ 12.262548] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10634 13:28:14.574663 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10635 13:28:14.601610 <30>[ 12.296198] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10636 13:28:14.608273 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10637 13:28:14.620875 <6>[ 12.315670] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10638 13:28:14.663126 <30>[ 12.357717] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10639 13:28:14.673197 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10640 13:28:14.696041 <30>[ 12.390796] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10641 13:28:14.703017 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10642 13:28:14.727801 <30>[ 12.422319] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10643 13:28:14.733690 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10644 13:28:14.754143 <6>[ 12.451939] fuse: init (API version 7.37)
10645 13:28:14.791389 <30>[ 12.485890] systemd[1]: Starting systemd-journald.service - Journal Service...
10646 13:28:14.797862 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10647 13:28:14.830899 <30>[ 12.525163] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10648 13:28:14.837170 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10649 13:28:14.862129 <30>[ 12.553812] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10650 13:28:14.868946 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10651 13:28:14.895853 <30>[ 12.590142] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10652 13:28:14.905080 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10653 13:28:14.936995 <3>[ 12.631108] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10654 13:28:14.963064 <30>[ 12.657408] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10655 13:28:14.972852 <3>[ 12.661127] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10656 13:28:14.979439 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10657 13:28:15.003629 <30>[ 12.698537] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10658 13:28:15.010591 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10659 13:28:15.023764 <3>[ 12.718700] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10660 13:28:15.034214 <30>[ 12.728956] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10661 13:28:15.044108 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10662 13:28:15.059354 <30>[ 12.753288] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10663 13:28:15.065781 <3>[ 12.756209] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10664 13:28:15.075074 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10665 13:28:15.095319 <30>[ 12.790152] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10666 13:28:15.105019 <3>[ 12.791367] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10667 13:28:15.114968 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10668 13:28:15.132799 <30>[ 12.826925] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10669 13:28:15.139336 <3>[ 12.830542] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10670 13:28:15.149115 <30>[ 12.835397] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10671 13:28:15.155447 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10672 13:28:15.170689 <3>[ 12.866010] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10673 13:28:15.181095 <30>[ 12.875887] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10674 13:28:15.188991 <30>[ 12.883674] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10675 13:28:15.202083 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 12.895477] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10676 13:28:15.205198 m_mod.s…e[0m - Load Kernel Module dm_mod.
10677 13:28:15.222541 <30>[ 12.919657] systemd[1]: modprobe@drm.service: Deactivated successfully.
10678 13:28:15.231832 <3>[ 12.926541] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10679 13:28:15.238508 <30>[ 12.927483] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10680 13:28:15.248516 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10681 13:28:15.261761 <3>[ 12.956288] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10682 13:28:15.273071 <30>[ 12.967388] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10683 13:28:15.283156 <30>[ 12.975902] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10684 13:28:15.293334 [[0;32m OK [<3>[ 12.985512] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10685 13:28:15.299744 0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10686 13:28:15.317150 <30>[ 13.014672] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10687 13:28:15.327784 <30>[ 13.022304] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10688 13:28:15.341202 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m <3>[ 13.034909] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10689 13:28:15.344374 - Load Kernel Module fuse.
10690 13:28:15.367249 <30>[ 13.062063] systemd[1]: modprobe@loop.service: Deactivated successfully.
10691 13:28:15.374423 <30>[ 13.069543] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10692 13:28:15.381181 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10693 13:28:15.397765 <4>[ 13.085047] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10694 13:28:15.404517 <3>[ 13.101464] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10695 13:28:15.414254 <30>[ 13.102277] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10696 13:28:15.421960 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10697 13:28:15.446977 <30>[ 13.137696] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10698 13:28:15.453408 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10699 13:28:15.471018 <30>[ 13.165329] systemd[1]: Started systemd-journald.service - Journal Service.
10700 13:28:15.477277 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10701 13:28:15.495319 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10702 13:28:15.514791 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10703 13:28:15.536211 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10704 13:28:15.594843 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10705 13:28:15.619692 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10706 13:28:15.643767 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10707 13:28:15.668842 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10708 13:28:15.696183 <46>[ 13.391065] systemd-journald[306]: Received client request to flush runtime journal.
10709 13:28:15.706129 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10710 13:28:15.759186 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10711 13:28:16.036827 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10712 13:28:16.054532 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10713 13:28:16.075782 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10714 13:28:16.095302 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10715 13:28:17.135879 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10716 13:28:17.164409 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10717 13:28:17.227338 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10718 13:28:17.333626 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10719 13:28:17.354849 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10720 13:28:17.370237 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10721 13:28:17.422547 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10722 13:28:17.448793 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10723 13:28:17.653672 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10724 13:28:17.708158 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10725 13:28:17.734112 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10726 13:28:18.053273 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10727 13:28:18.079306 <6>[ 15.777573] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10728 13:28:18.092256 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10729 13:28:18.148454 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10730 13:28:18.225155 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10731 13:28:18.262919 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10732 13:28:18.283647 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10733 13:28:18.303395 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10734 13:28:18.331409 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10735 13:28:18.357189 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10736 13:28:18.371976 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10737 13:28:18.435300 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10738 13:28:18.454700 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10739 13:28:18.504315 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10740 13:28:18.668809 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10741 13:28:18.686593 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10742 13:28:18.702749 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10743 13:28:18.718625 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10744 13:28:18.744648 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10745 13:28:18.765871 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10746 13:28:18.782592 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10747 13:28:18.802191 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10748 13:28:18.821674 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10749 13:28:18.837860 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10750 13:28:18.856683 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10751 13:28:18.874169 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10752 13:28:18.890652 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10753 13:28:18.940410 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10754 13:28:19.051933 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10755 13:28:19.172255 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10756 13:28:19.200451 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10757 13:28:19.298284 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10758 13:28:19.346982 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10759 13:28:19.365710 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10760 13:28:19.391825 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10761 13:28:19.397896 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10762 13:28:19.430873 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10763 13:28:19.462928 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10764 13:28:19.489205 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10765 13:28:19.508198 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10766 13:28:19.552780 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10767 13:28:19.607407 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10768 13:28:19.711210
10769 13:28:19.714117 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10770 13:28:19.714545
10771 13:28:19.717724 debian-bookworm-arm64 login: root (automatic login)
10772 13:28:19.718196
10773 13:28:20.018331 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024 aarch64
10774 13:28:20.018843
10775 13:28:20.024555 The programs included with the Debian GNU/Linux system are free software;
10776 13:28:20.030981 the exact distribution terms for each program are described in the
10777 13:28:20.034693 individual files in /usr/share/doc/*/copyright.
10778 13:28:20.035076
10779 13:28:20.040511 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10780 13:28:20.044186 permitted by applicable law.
10781 13:28:21.126543 Matched prompt #10: / #
10783 13:28:21.127559 Setting prompt string to ['/ #']
10784 13:28:21.127968 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10786 13:28:21.128835 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10787 13:28:21.129264 start: 2.2.6 expect-shell-connection (timeout 00:03:32) [common]
10788 13:28:21.129576 Setting prompt string to ['/ #']
10789 13:28:21.129854 Forcing a shell prompt, looking for ['/ #']
10790 13:28:21.130128 Sending line: ''
10792 13:28:21.181302 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10793 13:28:21.181738 Waiting using forced prompt support (timeout 00:02:30)
10794 13:28:21.187673 / #
10795 13:28:21.188541 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10796 13:28:21.189024 start: 2.2.7 export-device-env (timeout 00:03:32) [common]
10797 13:28:21.189459 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14879058/extract-nfsrootfs-h0v4silq'"
10799 13:28:21.296718 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14879058/extract-nfsrootfs-h0v4silq'
10800 13:28:21.297505 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
10802 13:28:21.404999 / # export NFS_SERVER_IP='192.168.201.1'
10803 13:28:21.405910 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10804 13:28:21.406406 end: 2.2 depthcharge-retry (duration 00:01:29) [common]
10805 13:28:21.406911 end: 2 depthcharge-action (duration 00:01:29) [common]
10806 13:28:21.407378 start: 3 lava-test-retry (timeout 00:07:51) [common]
10807 13:28:21.407818 start: 3.1 lava-test-shell (timeout 00:07:51) [common]
10808 13:28:21.408200 Using namespace: common
10809 13:28:21.408558 Sending line: '#'
10811 13:28:21.509984 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10812 13:28:21.516672 / # #
10813 13:28:21.517471 Using /lava-14879058
10814 13:28:21.517829 Sending line: 'export SHELL=/bin/bash'
10816 13:28:21.625754 / # export SHELL=/bin/bash
10817 13:28:21.626498 Sending line: '. /lava-14879058/environment'
10819 13:28:21.734448 / # . /lava-14879058/environment
10820 13:28:21.741026 Sending line: '/lava-14879058/bin/lava-test-runner /lava-14879058/0'
10822 13:28:21.842577 Test shell timeout: 10s (minimum of the action and connection timeout)
10823 13:28:21.848975 / # /lava-14879058/bin/lava-test-runner /lava-14879058/0
10824 13:28:22.104982 + export TESTRUN_ID=0_timesync-off
10825 13:28:22.108496 + TESTRUN_ID=0_timesync-off
10826 13:28:22.111352 + cd /lava-14879058/0/tests/0_timesync-off
10827 13:28:22.115104 ++ cat uuid
10828 13:28:22.118454 + UUID=14879058_1.6.2.3.1
10829 13:28:22.118844 + set +x
10830 13:28:22.125084 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14879058_1.6.2.3.1>
10831 13:28:22.125899 Received signal: <STARTRUN> 0_timesync-off 14879058_1.6.2.3.1
10832 13:28:22.126271 Starting test lava.0_timesync-off (14879058_1.6.2.3.1)
10833 13:28:22.126686 Skipping test definition patterns.
10834 13:28:22.128436 + systemctl stop systemd-timesyncd
10835 13:28:22.205372 + set +x
10836 13:28:22.207640 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14879058_1.6.2.3.1>
10837 13:28:22.208309 Received signal: <ENDRUN> 0_timesync-off 14879058_1.6.2.3.1
10838 13:28:22.208699 Ending use of test pattern.
10839 13:28:22.209007 Ending test lava.0_timesync-off (14879058_1.6.2.3.1), duration 0.08
10841 13:28:22.279847 + export TESTRUN_ID=1_kselftest-arm64
10842 13:28:22.280412 + TESTRUN_ID=1_kselftest-arm64
10843 13:28:22.286172 + cd /lava-14879058/0/tests/1_kselftest-arm64
10844 13:28:22.286578 ++ cat uuid
10845 13:28:22.289973 + UUID=14879058_1.6.2.3.5
10846 13:28:22.290384 + set +x
10847 13:28:22.296985 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 14879058_1.6.2.3.5>
10848 13:28:22.297840 Received signal: <STARTRUN> 1_kselftest-arm64 14879058_1.6.2.3.5
10849 13:28:22.298231 Starting test lava.1_kselftest-arm64 (14879058_1.6.2.3.5)
10850 13:28:22.298727 Skipping test definition patterns.
10851 13:28:22.299626 + cd ./automated/linux/kselftest/
10852 13:28:22.326080 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
10853 13:28:22.369628 INFO: install_deps skipped
10854 13:28:22.876558 --2024-07-18 13:28:23-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz
10855 13:28:22.891876 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10856 13:28:23.021191 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10857 13:28:23.152814 HTTP request sent, awaiting response... 200 OK
10858 13:28:23.156214 Length: 1919140 (1.8M) [application/octet-stream]
10859 13:28:23.159560 Saving to: 'kselftest_armhf.tar.gz'
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10866 13:28:24.200773 kselftest_armhf.tar 100%[===================>] 1.83M 1.76MB/s in 1.0s
10867 13:28:24.201421
10868 13:28:24.368568 2024-07-18 13:28:24 (1.76 MB/s) - 'kselftest_armhf.tar.gz' saved [1919140/1919140]
10869 13:28:24.368736
10870 13:28:31.063527 skiplist:
10871 13:28:31.066441 ========================================
10872 13:28:31.070036 ========================================
10873 13:28:31.120688 arm64:tags_test
10874 13:28:31.123483 arm64:run_tags_test.sh
10875 13:28:31.123875 arm64:fake_sigreturn_bad_magic
10876 13:28:31.127097 arm64:fake_sigreturn_bad_size
10877 13:28:31.130369 arm64:fake_sigreturn_bad_size_for_magic0
10878 13:28:31.133842 arm64:fake_sigreturn_duplicated_fpsimd
10879 13:28:31.137137 arm64:fake_sigreturn_misaligned_sp
10880 13:28:31.140878 arm64:fake_sigreturn_missing_fpsimd
10881 13:28:31.143375 arm64:fake_sigreturn_sme_change_vl
10882 13:28:31.146754 arm64:fake_sigreturn_sve_change_vl
10883 13:28:31.150486 arm64:mangle_pstate_invalid_compat_toggle
10884 13:28:31.153585 arm64:mangle_pstate_invalid_daif_bits
10885 13:28:31.156558 arm64:mangle_pstate_invalid_mode_el1h
10886 13:28:31.160459 arm64:mangle_pstate_invalid_mode_el1t
10887 13:28:31.163886 arm64:mangle_pstate_invalid_mode_el2h
10888 13:28:31.166729 arm64:mangle_pstate_invalid_mode_el2t
10889 13:28:31.170188 arm64:mangle_pstate_invalid_mode_el3h
10890 13:28:31.176849 arm64:mangle_pstate_invalid_mode_el3t
10891 13:28:31.177265 arm64:sme_trap_no_sm
10892 13:28:31.179838 arm64:sme_trap_non_streaming
10893 13:28:31.180244 arm64:sme_trap_za
10894 13:28:31.183108 arm64:sme_vl
10895 13:28:31.183492 arm64:ssve_regs
10896 13:28:31.186228 arm64:sve_regs
10897 13:28:31.186620 arm64:sve_vl
10898 13:28:31.186922 arm64:za_no_regs
10899 13:28:31.189577 arm64:za_regs
10900 13:28:31.189968 arm64:pac
10901 13:28:31.193021 arm64:fp-stress
10902 13:28:31.193447 arm64:sve-ptrace
10903 13:28:31.196712 arm64:sve-probe-vls
10904 13:28:31.197135 arm64:vec-syscfg
10905 13:28:31.197506 arm64:za-fork
10906 13:28:31.199836 arm64:za-ptrace
10907 13:28:31.203053 arm64:check_buffer_fill
10908 13:28:31.203489 arm64:check_child_memory
10909 13:28:31.206289 arm64:check_gcr_el1_cswitch
10910 13:28:31.209411 arm64:check_ksm_options
10911 13:28:31.209805 arm64:check_mmap_options
10912 13:28:31.212752 arm64:check_prctl
10913 13:28:31.215936 arm64:check_tags_inclusion
10914 13:28:31.216354 arm64:check_user_mem
10915 13:28:31.219646 arm64:btitest
10916 13:28:31.220034 arm64:nobtitest
10917 13:28:31.220349 arm64:hwcap
10918 13:28:31.222742 arm64:ptrace
10919 13:28:31.223150 arm64:syscall-abi
10920 13:28:31.226273 arm64:tpidr2
10921 13:28:31.229610 ============== Tests to run ===============
10922 13:28:31.230007 arm64:tags_test
10923 13:28:31.232634 arm64:run_tags_test.sh
10924 13:28:31.236314 arm64:fake_sigreturn_bad_magic
10925 13:28:31.239147 arm64:fake_sigreturn_bad_size
10926 13:28:31.242565 arm64:fake_sigreturn_bad_size_for_magic0
10927 13:28:31.246269 arm64:fake_sigreturn_duplicated_fpsimd
10928 13:28:31.248877 arm64:fake_sigreturn_misaligned_sp
10929 13:28:31.252637 arm64:fake_sigreturn_missing_fpsimd
10930 13:28:31.257649 arm64:fake_sigreturn_sme_change_vl
10931 13:28:31.258742 arm64:fake_sigreturn_sve_change_vl
10932 13:28:31.262083 arm64:mangle_pstate_invalid_compat_toggle
10933 13:28:31.264978 arm64:mangle_pstate_invalid_daif_bits
10934 13:28:31.269086 arm64:mangle_pstate_invalid_mode_el1h
10935 13:28:31.272283 arm64:mangle_pstate_invalid_mode_el1t
10936 13:28:31.275708 arm64:mangle_pstate_invalid_mode_el2h
10937 13:28:31.278880 arm64:mangle_pstate_invalid_mode_el2t
10938 13:28:31.281874 arm64:mangle_pstate_invalid_mode_el3h
10939 13:28:31.285413 arm64:mangle_pstate_invalid_mode_el3t
10940 13:28:31.285848 arm64:sme_trap_no_sm
10941 13:28:31.288673 arm64:sme_trap_non_streaming
10942 13:28:31.292222 arm64:sme_trap_za
10943 13:28:31.292651 arm64:sme_vl
10944 13:28:31.292982 arm64:ssve_regs
10945 13:28:31.295631 arm64:sve_regs
10946 13:28:31.296021 arm64:sve_vl
10947 13:28:31.298653 arm64:za_no_regs
10948 13:28:31.299044 arm64:za_regs
10949 13:28:31.299350 arm64:pac
10950 13:28:31.301874 arm64:fp-stress
10951 13:28:31.302262 arm64:sve-ptrace
10952 13:28:31.305381 arm64:sve-probe-vls
10953 13:28:31.305774 arm64:vec-syscfg
10954 13:28:31.308656 arm64:za-fork
10955 13:28:31.309094 arm64:za-ptrace
10956 13:28:31.312085 arm64:check_buffer_fill
10957 13:28:31.315874 arm64:check_child_memory
10958 13:28:31.316264 arm64:check_gcr_el1_cswitch
10959 13:28:31.318390 arm64:check_ksm_options
10960 13:28:31.321414 arm64:check_mmap_options
10961 13:28:31.321828 arm64:check_prctl
10962 13:28:31.325062 arm64:check_tags_inclusion
10963 13:28:31.325511 arm64:check_user_mem
10964 13:28:31.328682 arm64:btitest
10965 13:28:31.329071 arm64:nobtitest
10966 13:28:31.331755 arm64:hwcap
10967 13:28:31.332142 arm64:ptrace
10968 13:28:31.332443 arm64:syscall-abi
10969 13:28:31.335455 arm64:tpidr2
10970 13:28:31.338312 ===========End Tests to run ===============
10971 13:28:31.341857 shardfile-arm64 pass
10972 13:28:31.569396 <12>[ 29.269628] kselftest: Running tests in arm64
10973 13:28:31.579377 TAP version 13
10974 13:28:31.594509 1..48
10975 13:28:31.615498 # selftests: arm64: tags_test
10976 13:28:32.081206 ok 1 selftests: arm64: tags_test
10977 13:28:32.097459 # selftests: arm64: run_tags_test.sh
10978 13:28:32.154192 # --------------------
10979 13:28:32.157212 # running tags test
10980 13:28:32.157691 # --------------------
10981 13:28:32.160092 # [PASS]
10982 13:28:32.163872 ok 2 selftests: arm64: run_tags_test.sh
10983 13:28:32.178620 # selftests: arm64: fake_sigreturn_bad_magic
10984 13:28:32.235888 # Registered handlers for all signals.
10985 13:28:32.236432 # Detected MINSTKSIGSZ:4720
10986 13:28:32.239368 # Testcase initialized.
10987 13:28:32.242165 # uc context validated.
10988 13:28:32.245979 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
10989 13:28:32.249186 # Handled SIG_COPYCTX
10990 13:28:32.249662 # Available space:3568
10991 13:28:32.255813 # Using badly built context - ERR: BAD MAGIC !
10992 13:28:32.262351 # SIG_OK -- SP:0xFFFFFB526380 si_addr@:0xfffffb526380 si_code:2 token@:0xfffffb525120 offset:-4704
10993 13:28:32.265591 # ==>> completed. PASS(1)
10994 13:28:32.271599 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
10995 13:28:32.278396 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFB525120
10996 13:28:32.284823 ok 3 selftests: arm64: fake_sigreturn_bad_magic
10997 13:28:32.287942 # selftests: arm64: fake_sigreturn_bad_size
10998 13:28:32.339863 # Registered handlers for all signals.
10999 13:28:32.340379 # Detected MINSTKSIGSZ:4720
11000 13:28:32.343122 # Testcase initialized.
11001 13:28:32.346133 # uc context validated.
11002 13:28:32.349818 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11003 13:28:32.352309 # Handled SIG_COPYCTX
11004 13:28:32.352743 # Available space:3568
11005 13:28:32.355491 # uc context validated.
11006 13:28:32.362926 # Using badly built context - ERR: Bad size for esr_context
11007 13:28:32.368790 # SIG_OK -- SP:0xFFFFE11CDF00 si_addr@:0xffffe11cdf00 si_code:2 token@:0xffffe11ccca0 offset:-4704
11008 13:28:32.372212 # ==>> completed. PASS(1)
11009 13:28:32.378488 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11010 13:28:32.385064 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE11CCCA0
11011 13:28:32.388735 ok 4 selftests: arm64: fake_sigreturn_bad_size
11012 13:28:32.395748 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11013 13:28:32.430868 # Registered handlers for all signals.
11014 13:28:32.431424 # Detected MINSTKSIGSZ:4720
11015 13:28:32.433842 # Testcase initialized.
11016 13:28:32.437588 # uc context validated.
11017 13:28:32.441046 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11018 13:28:32.444538 # Handled SIG_COPYCTX
11019 13:28:32.444990 # Available space:3568
11020 13:28:32.451032 # Using badly built context - ERR: Bad size for terminator
11021 13:28:32.460508 # SIG_OK -- SP:0xFFFFC2094440 si_addr@:0xffffc2094440 si_code:2 token@:0xffffc20931e0 offset:-4704
11022 13:28:32.461097 # ==>> completed. PASS(1)
11023 13:28:32.471795 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11024 13:28:32.477019 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC20931E0
11025 13:28:32.480182 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11026 13:28:32.486951 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11027 13:28:32.525299 # Registered handlers for all signals.
11028 13:28:32.525819 # Detected MINSTKSIGSZ:4720
11029 13:28:32.528623 # Testcase initialized.
11030 13:28:32.532012 # uc context validated.
11031 13:28:32.535328 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11032 13:28:32.538882 # Handled SIG_COPYCTX
11033 13:28:32.539318 # Available space:3568
11034 13:28:32.545309 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11035 13:28:32.555192 # SIG_OK -- SP:0xFFFFC04D8410 si_addr@:0xffffc04d8410 si_code:2 token@:0xffffc04d71b0 offset:-4704
11036 13:28:32.555633 # ==>> completed. PASS(1)
11037 13:28:32.565163 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11038 13:28:32.571696 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC04D71B0
11039 13:28:32.575292 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11040 13:28:32.577943 # selftests: arm64: fake_sigreturn_misaligned_sp
11041 13:28:32.601394 # Registered handlers for all signals.
11042 13:28:32.601897 # Detected MINSTKSIGSZ:4720
11043 13:28:32.603407 # Testcase initialized.
11044 13:28:32.606282 # uc context validated.
11045 13:28:32.609637 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11046 13:28:32.613610 # Handled SIG_COPYCTX
11047 13:28:32.619612 # SIG_OK -- SP:0xFFFFE3293E93 si_addr@:0xffffe3293e93 si_code:2 token@:0xffffe3293e93 offset:0
11048 13:28:32.623403 # ==>> completed. PASS(1)
11049 13:28:32.629170 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11050 13:28:32.636070 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE3293E93
11051 13:28:32.642363 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11052 13:28:32.646150 # selftests: arm64: fake_sigreturn_missing_fpsimd
11053 13:28:32.682061 # Registered handlers for all signals.
11054 13:28:32.682605 # Detected MINSTKSIGSZ:4720
11055 13:28:32.684946 # Testcase initialized.
11056 13:28:32.688386 # uc context validated.
11057 13:28:32.692181 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11058 13:28:32.695218 # Handled SIG_COPYCTX
11059 13:28:32.698730 # Mangling template header. Spare space:4096
11060 13:28:32.702044 # Using badly built context - ERR: Missing FPSIMD
11061 13:28:32.711648 # SIG_OK -- SP:0xFFFFC3780F90 si_addr@:0xffffc3780f90 si_code:2 token@:0xffffc377fd30 offset:-4704
11062 13:28:32.714891 # ==>> completed. PASS(1)
11063 13:28:32.721482 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11064 13:28:32.728722 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC377FD30
11065 13:28:32.731104 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11066 13:28:32.738011 # selftests: arm64: fake_sigreturn_sme_change_vl
11067 13:28:32.758103 # Registered handlers for all signals.
11068 13:28:32.758617 # Detected MINSTKSIGSZ:4720
11069 13:28:32.761312 # ==>> completed. SKIP.
11070 13:28:32.768278 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11071 13:28:32.771311 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11072 13:28:32.779607 # selftests: arm64: fake_sigreturn_sve_change_vl
11073 13:28:32.831698 # Registered handlers for all signals.
11074 13:28:32.832200 # Detected MINSTKSIGSZ:4720
11075 13:28:32.834890 # ==>> completed. SKIP.
11076 13:28:32.841775 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11077 13:28:32.844658 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11078 13:28:32.851878 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11079 13:28:32.909358 # Registered handlers for all signals.
11080 13:28:32.909888 # Detected MINSTKSIGSZ:4720
11081 13:28:32.913439 # Testcase initialized.
11082 13:28:32.915830 # uc context validated.
11083 13:28:32.916263 # Handled SIG_TRIG
11084 13:28:32.925928 # SIG_OK -- SP:0xFFFFCB48D4B0 si_addr@:0xffffcb48d4b0 si_code:2 token@:(nil) offset:-281474092291248
11085 13:28:32.929563 # ==>> completed. PASS(1)
11086 13:28:32.935842 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11087 13:28:32.942441 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11088 13:28:32.945858 # selftests: arm64: mangle_pstate_invalid_daif_bits
11089 13:28:33.017359 # Registered handlers for all signals.
11090 13:28:33.017869 # Detected MINSTKSIGSZ:4720
11091 13:28:33.021443 # Testcase initialized.
11092 13:28:33.024556 # uc context validated.
11093 13:28:33.024986 # Handled SIG_TRIG
11094 13:28:33.034320 # SIG_OK -- SP:0xFFFFD1A770E0 si_addr@:0xffffd1a770e0 si_code:2 token@:(nil) offset:-281474199154912
11095 13:28:33.037267 # ==>> completed. PASS(1)
11096 13:28:33.043601 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11097 13:28:33.047219 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11098 13:28:33.054125 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11099 13:28:33.099441 # Registered handlers for all signals.
11100 13:28:33.099859 # Detected MINSTKSIGSZ:4720
11101 13:28:33.102645 # Testcase initialized.
11102 13:28:33.105770 # uc context validated.
11103 13:28:33.106164 # Handled SIG_TRIG
11104 13:28:33.115812 # SIG_OK -- SP:0xFFFFFB8A9070 si_addr@:0xfffffb8a9070 si_code:2 token@:(nil) offset:-281474901905520
11105 13:28:33.119715 # ==>> completed. PASS(1)
11106 13:28:33.125977 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11107 13:28:33.128905 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11108 13:28:33.136149 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11109 13:28:33.167082 # Registered handlers for all signals.
11110 13:28:33.167649 # Detected MINSTKSIGSZ:4720
11111 13:28:33.170374 # Testcase initialized.
11112 13:28:33.174182 # uc context validated.
11113 13:28:33.174679 # Handled SIG_TRIG
11114 13:28:33.183263 # SIG_OK -- SP:0xFFFFF2ECBCF0 si_addr@:0xfffff2ecbcf0 si_code:2 token@:(nil) offset:-281474757344496
11115 13:28:33.187852 # ==>> completed. PASS(1)
11116 13:28:33.193705 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11117 13:28:33.197178 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11118 13:28:33.203482 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11119 13:28:33.247128 # Registered handlers for all signals.
11120 13:28:33.247556 # Detected MINSTKSIGSZ:4720
11121 13:28:33.250752 # Testcase initialized.
11122 13:28:33.254666 # uc context validated.
11123 13:28:33.255120 # Handled SIG_TRIG
11124 13:28:33.264077 # SIG_OK -- SP:0xFFFFC10C2100 si_addr@:0xffffc10c2100 si_code:2 token@:(nil) offset:-281473920540928
11125 13:28:33.267510 # ==>> completed. PASS(1)
11126 13:28:33.273619 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11127 13:28:33.276809 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11128 13:28:33.283652 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11129 13:28:33.328412 # Registered handlers for all signals.
11130 13:28:33.328869 # Detected MINSTKSIGSZ:4720
11131 13:28:33.332349 # Testcase initialized.
11132 13:28:33.335235 # uc context validated.
11133 13:28:33.335739 # Handled SIG_TRIG
11134 13:28:33.345162 # SIG_OK -- SP:0xFFFFCF92AD60 si_addr@:0xffffcf92ad60 si_code:2 token@:(nil) offset:-281474164239712
11135 13:28:33.348187 # ==>> completed. PASS(1)
11136 13:28:33.355055 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11137 13:28:33.358017 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11138 13:28:33.365611 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11139 13:28:33.406507 # Registered handlers for all signals.
11140 13:28:33.406597 # Detected MINSTKSIGSZ:4720
11141 13:28:33.410482 # Testcase initialized.
11142 13:28:33.413072 # uc context validated.
11143 13:28:33.413181 # Handled SIG_TRIG
11144 13:28:33.422918 # SIG_OK -- SP:0xFFFFE2B5FC80 si_addr@:0xffffe2b5fc80 si_code:2 token@:(nil) offset:-281474485320832
11145 13:28:33.426169 # ==>> completed. PASS(1)
11146 13:28:33.432776 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11147 13:28:33.436103 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11148 13:28:33.442473 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11149 13:28:33.471009 # Registered handlers for all signals.
11150 13:28:33.471098 # Detected MINSTKSIGSZ:4720
11151 13:28:33.474076 # Testcase initialized.
11152 13:28:33.477594 # uc context validated.
11153 13:28:33.477688 # Handled SIG_TRIG
11154 13:28:33.488054 # SIG_OK -- SP:0xFFFFECBAE390 si_addr@:0xffffecbae390 si_code:2 token@:(nil) offset:-281474653414288
11155 13:28:33.490941 # ==>> completed. PASS(1)
11156 13:28:33.497336 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11157 13:28:33.500657 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11158 13:28:33.504461 # selftests: arm64: sme_trap_no_sm
11159 13:28:33.532302 # Registered handlers for all signals.
11160 13:28:33.532376 # Detected MINSTKSIGSZ:4720
11161 13:28:33.535922 # ==>> completed. SKIP.
11162 13:28:33.545656 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11163 13:28:33.549195 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11164 13:28:33.552250 # selftests: arm64: sme_trap_non_streaming
11165 13:28:33.618035 # Registered handlers for all signals.
11166 13:28:33.618577 # Detected MINSTKSIGSZ:4720
11167 13:28:33.620777 # ==>> completed. SKIP.
11168 13:28:33.630909 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11169 13:28:33.637260 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11170 13:28:33.641063 # selftests: arm64: sme_trap_za
11171 13:28:33.697334 # Registered handlers for all signals.
11172 13:28:33.697842 # Detected MINSTKSIGSZ:4720
11173 13:28:33.700709 # Testcase initialized.
11174 13:28:33.710092 # SIG_OK -- SP:0xFFFFE1CBE610 si_addr@:0xaaaacb452480 si_code:1 token@:(nil) offset:-187650531468416
11175 13:28:33.710555 # ==>> completed. PASS(1)
11176 13:28:33.720210 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11177 13:28:33.723362 ok 21 selftests: arm64: sme_trap_za
11178 13:28:33.723965 # selftests: arm64: sme_vl
11179 13:28:33.786412 # Registered handlers for all signals.
11180 13:28:33.786817 # Detected MINSTKSIGSZ:4720
11181 13:28:33.789422 # ==>> completed. SKIP.
11182 13:28:33.796611 # # SME VL :: Check that we get the right SME VL reported
11183 13:28:33.799838 ok 22 selftests: arm64: sme_vl # SKIP
11184 13:28:33.802821 # selftests: arm64: ssve_regs
11185 13:28:33.858962 # Registered handlers for all signals.
11186 13:28:33.859453 # Detected MINSTKSIGSZ:4720
11187 13:28:33.862589 # ==>> completed. SKIP.
11188 13:28:33.869155 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11189 13:28:33.875121 ok 23 selftests: arm64: ssve_regs # SKIP
11190 13:28:33.879157 # selftests: arm64: sve_regs
11191 13:28:33.944258 # Registered handlers for all signals.
11192 13:28:33.944552 # Detected MINSTKSIGSZ:4720
11193 13:28:33.947408 # ==>> completed. SKIP.
11194 13:28:33.953902 # # SVE registers :: Check that we get the right SVE registers reported
11195 13:28:33.957431 ok 24 selftests: arm64: sve_regs # SKIP
11196 13:28:33.961584 # selftests: arm64: sve_vl
11197 13:28:34.019686 # Registered handlers for all signals.
11198 13:28:34.020204 # Detected MINSTKSIGSZ:4720
11199 13:28:34.022759 # ==>> completed. SKIP.
11200 13:28:34.029678 # # SVE VL :: Check that we get the right SVE VL reported
11201 13:28:34.032242 ok 25 selftests: arm64: sve_vl # SKIP
11202 13:28:34.035558 # selftests: arm64: za_no_regs
11203 13:28:34.108638 # Registered handlers for all signals.
11204 13:28:34.109335 # Detected MINSTKSIGSZ:4720
11205 13:28:34.111015 # ==>> completed. SKIP.
11206 13:28:34.117960 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11207 13:28:34.120965 ok 26 selftests: arm64: za_no_regs # SKIP
11208 13:28:34.125552 # selftests: arm64: za_regs
11209 13:28:34.187154 # Registered handlers for all signals.
11210 13:28:34.187647 # Detected MINSTKSIGSZ:4720
11211 13:28:34.190512 # ==>> completed. SKIP.
11212 13:28:34.197119 # # ZA register :: Check that we get the right ZA registers reported
11213 13:28:34.200537 ok 27 selftests: arm64: za_regs # SKIP
11214 13:28:34.207976 # selftests: arm64: pac
11215 13:28:34.249977 # TAP version 13
11216 13:28:34.250371 # 1..7
11217 13:28:34.253175 # # Starting 7 tests from 1 test cases.
11218 13:28:34.257084 # # RUN global.corrupt_pac ...
11219 13:28:34.260115 # # SKIP PAUTH not enabled
11220 13:28:34.263463 # # OK global.corrupt_pac
11221 13:28:34.266646 # ok 1 # SKIP PAUTH not enabled
11222 13:28:34.273215 # # RUN global.pac_instructions_not_nop ...
11223 13:28:34.276349 # # SKIP PAUTH not enabled
11224 13:28:34.280351 # # OK global.pac_instructions_not_nop
11225 13:28:34.283382 # ok 2 # SKIP PAUTH not enabled
11226 13:28:34.289838 # # RUN global.pac_instructions_not_nop_generic ...
11227 13:28:34.293335 # # SKIP Generic PAUTH not enabled
11228 13:28:34.296563 # # OK global.pac_instructions_not_nop_generic
11229 13:28:34.303132 # ok 3 # SKIP Generic PAUTH not enabled
11230 13:28:34.306194 # # RUN global.single_thread_different_keys ...
11231 13:28:34.309384 # # SKIP PAUTH not enabled
11232 13:28:34.315936 # # OK global.single_thread_different_keys
11233 13:28:34.316479 # ok 4 # SKIP PAUTH not enabled
11234 13:28:34.322790 # # RUN global.exec_changed_keys ...
11235 13:28:34.326411 # # SKIP PAUTH not enabled
11236 13:28:34.329568 # # OK global.exec_changed_keys
11237 13:28:34.332760 # ok 5 # SKIP PAUTH not enabled
11238 13:28:34.336059 # # RUN global.context_switch_keep_keys ...
11239 13:28:34.339129 # # SKIP PAUTH not enabled
11240 13:28:34.346039 # # OK global.context_switch_keep_keys
11241 13:28:34.349335 # ok 6 # SKIP PAUTH not enabled
11242 13:28:34.352949 # # RUN global.context_switch_keep_keys_generic ...
11243 13:28:34.355780 # # SKIP Generic PAUTH not enabled
11244 13:28:34.362524 # # OK global.context_switch_keep_keys_generic
11245 13:28:34.365891 # ok 7 # SKIP Generic PAUTH not enabled
11246 13:28:34.369091 # # PASSED: 7 / 7 tests passed.
11247 13:28:34.372851 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11248 13:28:34.376248 ok 28 selftests: arm64: pac
11249 13:28:34.378767 # selftests: arm64: fp-stress
11250 13:28:40.264870 <6>[ 37.968789] vpu: disabling
11251 13:28:40.267852 <6>[ 37.971838] vproc2: disabling
11252 13:28:40.270907 <6>[ 37.975114] vproc1: disabling
11253 13:28:40.274835 <6>[ 37.978384] vaud18: disabling
11254 13:28:40.281046 <6>[ 37.981817] vsram_others: disabling
11255 13:28:40.284135 <6>[ 37.985709] va09: disabling
11256 13:28:40.287678 <6>[ 37.988827] vsram_md: disabling
11257 13:28:40.291238 <6>[ 37.992323] Vgpu: disabling
11258 13:28:44.320811 # TAP version 13
11259 13:28:44.321390 # 1..16
11260 13:28:44.324186 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11261 13:28:44.326980 # # Will run for 10s
11262 13:28:44.327467 # # Started FPSIMD-0-0
11263 13:28:44.330533 # # Started FPSIMD-0-1
11264 13:28:44.333718 # # Started FPSIMD-1-0
11265 13:28:44.334222 # # Started FPSIMD-1-1
11266 13:28:44.337075 # # Started FPSIMD-2-0
11267 13:28:44.337601 # # Started FPSIMD-2-1
11268 13:28:44.340308 # # Started FPSIMD-3-0
11269 13:28:44.344114 # # Started FPSIMD-3-1
11270 13:28:44.344547 # # Started FPSIMD-4-0
11271 13:28:44.347260 # # Started FPSIMD-4-1
11272 13:28:44.350037 # # Started FPSIMD-5-0
11273 13:28:44.350550 # # Started FPSIMD-5-1
11274 13:28:44.353842 # # Started FPSIMD-6-0
11275 13:28:44.357078 # # Started FPSIMD-6-1
11276 13:28:44.357745 # # Started FPSIMD-7-0
11277 13:28:44.360715 # # Started FPSIMD-7-1
11278 13:28:44.363425 # # FPSIMD-0-0: Vector length: 128 bits
11279 13:28:44.367101 # # FPSIMD-0-0: PID: 1165
11280 13:28:44.370456 # # FPSIMD-3-0: Vector length: 128 bits
11281 13:28:44.370951 # # FPSIMD-3-0: PID: 1171
11282 13:28:44.373725 # # FPSIMD-1-0: Vector length: 128 bits
11283 13:28:44.376717 # # FPSIMD-1-0: PID: 1167
11284 13:28:44.381058 # # FPSIMD-1-1: Vector length: 128 bits
11285 13:28:44.383483 # # FPSIMD-1-1: PID: 1168
11286 13:28:44.386619 # # FPSIMD-2-0: Vector length: 128 bits
11287 13:28:44.389725 # # FPSIMD-2-0: PID: 1169
11288 13:28:44.393449 # # FPSIMD-2-1: Vector length: 128 bits
11289 13:28:44.396484 # # FPSIMD-2-1: PID: 1170
11290 13:28:44.400824 # # FPSIMD-0-1: Vector length: 128 bits
11291 13:28:44.401348 # # FPSIMD-0-1: PID: 1166
11292 13:28:44.403125 # # FPSIMD-3-1: Vector length: 128 bits
11293 13:28:44.407007 # # FPSIMD-3-1: PID: 1172
11294 13:28:44.410083 # # FPSIMD-4-1: Vector length: 128 bits
11295 13:28:44.412965 # # FPSIMD-4-1: PID: 1174
11296 13:28:44.416728 # # FPSIMD-6-0: Vector length: 128 bits
11297 13:28:44.419720 # # FPSIMD-6-0: PID: 1177
11298 13:28:44.423185 # # FPSIMD-7-0: Vector length: 128 bits
11299 13:28:44.423578 # # FPSIMD-7-0: PID: 1179
11300 13:28:44.429300 # # FPSIMD-6-1: Vector length: 128 bits
11301 13:28:44.429805 # # FPSIMD-6-1: PID: 1178
11302 13:28:44.432549 # # FPSIMD-7-1: Vector length: 128 bits
11303 13:28:44.435716 # # FPSIMD-7-1: PID: 1180
11304 13:28:44.439071 # # FPSIMD-5-1: Vector length: 128 bits
11305 13:28:44.442484 # # FPSIMD-5-1: PID: 1176
11306 13:28:44.445858 # # FPSIMD-5-0: Vector length: 128 bits
11307 13:28:44.449085 # # FPSIMD-5-0: PID: 1175
11308 13:28:44.452362 # # FPSIMD-4-0: Vector length: 128 bits
11309 13:28:44.452505 # # FPSIMD-4-0: PID: 1173
11310 13:28:44.455936 # # Finishing up...
11311 13:28:44.461957 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=994259, signals=10
11312 13:28:44.468839 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=2188232, signals=10
11313 13:28:44.476470 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=2195963, signals=10
11314 13:28:44.485433 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=978496, signals=10
11315 13:28:44.492274 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1038885, signals=10
11316 13:28:44.498845 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=2133161, signals=10
11317 13:28:44.505187 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=2180921, signals=10
11318 13:28:44.508891 # ok 1 FPSIMD-0-0
11319 13:28:44.509454 # ok 2 FPSIMD-0-1
11320 13:28:44.512160 # ok 3 FPSIMD-1-0
11321 13:28:44.512625 # ok 4 FPSIMD-1-1
11322 13:28:44.515480 # ok 5 FPSIMD-2-0
11323 13:28:44.516011 # ok 6 FPSIMD-2-1
11324 13:28:44.518342 # ok 7 FPSIMD-3-0
11325 13:28:44.519000 # ok 8 FPSIMD-3-1
11326 13:28:44.521937 # ok 9 FPSIMD-4-0
11327 13:28:44.522327 # ok 10 FPSIMD-4-1
11328 13:28:44.524908 # ok 11 FPSIMD-5-0
11329 13:28:44.525444 # ok 12 FPSIMD-5-1
11330 13:28:44.528242 # ok 13 FPSIMD-6-0
11331 13:28:44.528648 # ok 14 FPSIMD-6-1
11332 13:28:44.531489 # ok 15 FPSIMD-7-0
11333 13:28:44.531882 # ok 16 FPSIMD-7-1
11334 13:28:44.541795 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1042489, signals=9
11335 13:28:44.548005 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1031199, signals=10
11336 13:28:44.555009 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=979110, signals=10
11337 13:28:44.561423 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=986289, signals=10
11338 13:28:44.568346 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1136811, signals=9
11339 13:28:44.574504 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=992506, signals=10
11340 13:28:44.580951 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=980148, signals=10
11341 13:28:44.592195 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=994636, signals=10
11342 13:28:44.597769 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1049705, signals=9
11343 13:28:44.601514 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11344 13:28:44.604649 ok 29 selftests: arm64: fp-stress
11345 13:28:44.607683 # selftests: arm64: sve-ptrace
11346 13:28:44.611645 # TAP version 13
11347 13:28:44.612113 # 1..4104
11348 13:28:44.614460 # ok 2 # SKIP SVE not available
11349 13:28:44.617820 # # Planned tests != run tests (4104 != 1)
11350 13:28:44.621105 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11351 13:28:44.627846 ok 30 selftests: arm64: sve-ptrace # SKIP
11352 13:28:44.628246 # selftests: arm64: sve-probe-vls
11353 13:28:44.630963 # TAP version 13
11354 13:28:44.631537 # 1..2
11355 13:28:44.634085 # ok 2 # SKIP SVE not available
11356 13:28:44.637315 # # Planned tests != run tests (2 != 1)
11357 13:28:44.644310 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11358 13:28:44.646826 ok 31 selftests: arm64: sve-probe-vls # SKIP
11359 13:28:44.651096 # selftests: arm64: vec-syscfg
11360 13:28:44.651558 # TAP version 13
11361 13:28:44.651924 # 1..20
11362 13:28:44.653742 # ok 1 # SKIP SVE not supported
11363 13:28:44.657750 # ok 2 # SKIP SVE not supported
11364 13:28:44.660578 # ok 3 # SKIP SVE not supported
11365 13:28:44.663639 # ok 4 # SKIP SVE not supported
11366 13:28:44.667291 # ok 5 # SKIP SVE not supported
11367 13:28:44.670325 # ok 6 # SKIP SVE not supported
11368 13:28:44.670772 # ok 7 # SKIP SVE not supported
11369 13:28:44.674139 # ok 8 # SKIP SVE not supported
11370 13:28:44.677783 # ok 9 # SKIP SVE not supported
11371 13:28:44.680364 # ok 10 # SKIP SVE not supported
11372 13:28:44.683901 # ok 11 # SKIP SME not supported
11373 13:28:44.686702 # ok 12 # SKIP SME not supported
11374 13:28:44.689924 # ok 13 # SKIP SME not supported
11375 13:28:44.693347 # ok 14 # SKIP SME not supported
11376 13:28:44.697323 # ok 15 # SKIP SME not supported
11377 13:28:44.697797 # ok 16 # SKIP SME not supported
11378 13:28:44.700785 # ok 17 # SKIP SME not supported
11379 13:28:44.703738 # ok 18 # SKIP SME not supported
11380 13:28:44.707158 # ok 19 # SKIP SME not supported
11381 13:28:44.709828 # ok 20 # SKIP SME not supported
11382 13:28:44.717670 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11383 13:28:44.720994 ok 32 selftests: arm64: vec-syscfg
11384 13:28:44.721582 # selftests: arm64: za-fork
11385 13:28:44.722917 # TAP version 13
11386 13:28:44.723451 # 1..1
11387 13:28:44.723960 # # PID: 1257
11388 13:28:44.727139 # # SME support not present
11389 13:28:44.729738 # ok 0 skipped
11390 13:28:44.733197 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11391 13:28:44.736500 ok 33 selftests: arm64: za-fork
11392 13:28:44.740608 # selftests: arm64: za-ptrace
11393 13:28:44.741001 # TAP version 13
11394 13:28:44.741350 # 1..1
11395 13:28:44.743619 # ok 2 # SKIP SME not available
11396 13:28:44.750160 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11397 13:28:44.753063 ok 34 selftests: arm64: za-ptrace # SKIP
11398 13:28:44.756951 # selftests: arm64: check_buffer_fill
11399 13:28:44.783997 # # SKIP: MTE features unavailable
11400 13:28:44.791212 ok 35 selftests: arm64: check_buffer_fill # SKIP
11401 13:28:44.809036 # selftests: arm64: check_child_memory
11402 13:28:44.866088 # # SKIP: MTE features unavailable
11403 13:28:44.872590 ok 36 selftests: arm64: check_child_memory # SKIP
11404 13:28:44.888319 # selftests: arm64: check_gcr_el1_cswitch
11405 13:28:44.941867 # # SKIP: MTE features unavailable
11406 13:28:44.949419 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11407 13:28:44.964451 # selftests: arm64: check_ksm_options
11408 13:28:44.999944 # # SKIP: MTE features unavailable
11409 13:28:45.006795 ok 38 selftests: arm64: check_ksm_options # SKIP
11410 13:28:45.022401 # selftests: arm64: check_mmap_options
11411 13:28:45.098695 # # SKIP: MTE features unavailable
11412 13:28:45.106476 ok 39 selftests: arm64: check_mmap_options # SKIP
11413 13:28:45.119178 # selftests: arm64: check_prctl
11414 13:28:45.194253 # TAP version 13
11415 13:28:45.194760 # 1..5
11416 13:28:45.197913 # ok 1 check_basic_read
11417 13:28:45.198343 # ok 2 NONE
11418 13:28:45.201274 # ok 3 # SKIP SYNC
11419 13:28:45.201731 # ok 4 # SKIP ASYNC
11420 13:28:45.204641 # ok 5 # SKIP SYNC+ASYNC
11421 13:28:45.207565 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11422 13:28:45.211126 ok 40 selftests: arm64: check_prctl
11423 13:28:45.219535 # selftests: arm64: check_tags_inclusion
11424 13:28:45.300707 # # SKIP: MTE features unavailable
11425 13:28:45.310398 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11426 13:28:45.325826 # selftests: arm64: check_user_mem
11427 13:28:45.380942 # # SKIP: MTE features unavailable
11428 13:28:45.389052 ok 42 selftests: arm64: check_user_mem # SKIP
11429 13:28:45.403380 # selftests: arm64: btitest
11430 13:28:45.458907 # TAP version 13
11431 13:28:45.459425 # 1..18
11432 13:28:45.462108 # # HWCAP_PACA not present
11433 13:28:45.465870 # # HWCAP2_BTI not present
11434 13:28:45.466402 # # Test binary built for BTI
11435 13:28:45.471900 # ok 1 nohint_func/call_using_br_x0 # SKIP
11436 13:28:45.475471 # ok 1 nohint_func/call_using_br_x16 # SKIP
11437 13:28:45.478671 # ok 1 nohint_func/call_using_blr # SKIP
11438 13:28:45.481523 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11439 13:28:45.485182 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11440 13:28:45.488138 # ok 1 bti_none_func/call_using_blr # SKIP
11441 13:28:45.495203 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11442 13:28:45.498524 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11443 13:28:45.501690 # ok 1 bti_c_func/call_using_blr # SKIP
11444 13:28:45.505348 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11445 13:28:45.507937 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11446 13:28:45.511250 # ok 1 bti_j_func/call_using_blr # SKIP
11447 13:28:45.514712 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11448 13:28:45.522153 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11449 13:28:45.525350 # ok 1 bti_jc_func/call_using_blr # SKIP
11450 13:28:45.528861 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11451 13:28:45.531402 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11452 13:28:45.534874 # ok 1 paciasp_func/call_using_blr # SKIP
11453 13:28:45.541382 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11454 13:28:45.544857 # # WARNING - EXPECTED TEST COUNT WRONG
11455 13:28:45.547893 ok 43 selftests: arm64: btitest
11456 13:28:45.548300 # selftests: arm64: nobtitest
11457 13:28:45.551147 # TAP version 13
11458 13:28:45.551677 # 1..18
11459 13:28:45.554695 # # HWCAP_PACA not present
11460 13:28:45.557630 # # HWCAP2_BTI not present
11461 13:28:45.561075 # # Test binary not built for BTI
11462 13:28:45.564092 # ok 1 nohint_func/call_using_br_x0 # SKIP
11463 13:28:45.567815 # ok 1 nohint_func/call_using_br_x16 # SKIP
11464 13:28:45.570764 # ok 1 nohint_func/call_using_blr # SKIP
11465 13:28:45.574203 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11466 13:28:45.578010 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11467 13:28:45.584199 # ok 1 bti_none_func/call_using_blr # SKIP
11468 13:28:45.587363 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11469 13:28:45.591186 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11470 13:28:45.594132 # ok 1 bti_c_func/call_using_blr # SKIP
11471 13:28:45.597768 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11472 13:28:45.600402 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11473 13:28:45.604048 # ok 1 bti_j_func/call_using_blr # SKIP
11474 13:28:45.607752 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11475 13:28:45.613718 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11476 13:28:45.617629 # ok 1 bti_jc_func/call_using_blr # SKIP
11477 13:28:45.620420 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11478 13:28:45.623899 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11479 13:28:45.627020 # ok 1 paciasp_func/call_using_blr # SKIP
11480 13:28:45.633578 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11481 13:28:45.637171 # # WARNING - EXPECTED TEST COUNT WRONG
11482 13:28:45.640306 ok 44 selftests: arm64: nobtitest
11483 13:28:45.643821 # selftests: arm64: hwcap
11484 13:28:45.644262 # TAP version 13
11485 13:28:45.644600 # 1..28
11486 13:28:45.647238 # ok 1 cpuinfo_match_RNG
11487 13:28:45.650461 # # SIGILL reported for RNG
11488 13:28:45.650848 # ok 2 # SKIP sigill_RNG
11489 13:28:45.653362 # ok 3 cpuinfo_match_SME
11490 13:28:45.656713 # ok 4 sigill_SME
11491 13:28:45.657097 # ok 5 cpuinfo_match_SVE
11492 13:28:45.660348 # ok 6 sigill_SVE
11493 13:28:45.660917 # ok 7 cpuinfo_match_SVE 2
11494 13:28:45.663497 # # SIGILL reported for SVE 2
11495 13:28:45.666431 # ok 8 # SKIP sigill_SVE 2
11496 13:28:45.670182 # ok 9 cpuinfo_match_SVE AES
11497 13:28:45.673536 # # SIGILL reported for SVE AES
11498 13:28:45.676674 # ok 10 # SKIP sigill_SVE AES
11499 13:28:45.677064 # ok 11 cpuinfo_match_SVE2 PMULL
11500 13:28:45.679876 # # SIGILL reported for SVE2 PMULL
11501 13:28:45.683182 # ok 12 # SKIP sigill_SVE2 PMULL
11502 13:28:45.686509 # ok 13 cpuinfo_match_SVE2 BITPERM
11503 13:28:45.689740 # # SIGILL reported for SVE2 BITPERM
11504 13:28:45.693129 # ok 14 # SKIP sigill_SVE2 BITPERM
11505 13:28:45.696910 # ok 15 cpuinfo_match_SVE2 SHA3
11506 13:28:45.700170 # # SIGILL reported for SVE2 SHA3
11507 13:28:45.703165 # ok 16 # SKIP sigill_SVE2 SHA3
11508 13:28:45.706224 # ok 17 cpuinfo_match_SVE2 SM4
11509 13:28:45.709527 # # SIGILL reported for SVE2 SM4
11510 13:28:45.709916 # ok 18 # SKIP sigill_SVE2 SM4
11511 13:28:45.713139 # ok 19 cpuinfo_match_SVE2 I8MM
11512 13:28:45.716416 # # SIGILL reported for SVE2 I8MM
11513 13:28:45.719242 # ok 20 # SKIP sigill_SVE2 I8MM
11514 13:28:45.722621 # ok 21 cpuinfo_match_SVE2 F32MM
11515 13:28:45.726326 # # SIGILL reported for SVE2 F32MM
11516 13:28:45.729311 # ok 22 # SKIP sigill_SVE2 F32MM
11517 13:28:45.732745 # ok 23 cpuinfo_match_SVE2 F64MM
11518 13:28:45.736099 # # SIGILL reported for SVE2 F64MM
11519 13:28:45.736483 # ok 24 # SKIP sigill_SVE2 F64MM
11520 13:28:45.739520 # ok 25 cpuinfo_match_SVE2 BF16
11521 13:28:45.743428 # # SIGILL reported for SVE2 BF16
11522 13:28:45.747226 # ok 26 # SKIP sigill_SVE2 BF16
11523 13:28:45.749488 # ok 27 cpuinfo_match_SVE2 EBF16
11524 13:28:45.752938 # ok 28 # SKIP sigill_SVE2 EBF16
11525 13:28:45.759455 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11526 13:28:45.759861 ok 45 selftests: arm64: hwcap
11527 13:28:45.762216 # selftests: arm64: ptrace
11528 13:28:45.765621 # TAP version 13
11529 13:28:45.766014 # 1..7
11530 13:28:45.769326 # # Parent is 1499, child is 1500
11531 13:28:45.769720 # ok 1 read_tpidr_one
11532 13:28:45.772683 # ok 2 write_tpidr_one
11533 13:28:45.776222 # ok 3 verify_tpidr_one
11534 13:28:45.776740 # ok 4 count_tpidrs
11535 13:28:45.779287 # ok 5 tpidr2_write
11536 13:28:45.779805 # ok 6 tpidr2_read
11537 13:28:45.782614 # ok 7 write_tpidr_only
11538 13:28:45.785294 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11539 13:28:45.788665 ok 46 selftests: arm64: ptrace
11540 13:28:45.791713 # selftests: arm64: syscall-abi
11541 13:28:45.801882 # TAP version 13
11542 13:28:45.802409 # 1..2
11543 13:28:45.805005 # ok 1 getpid() FPSIMD
11544 13:28:45.808729 # ok 2 sched_yield() FPSIMD
11545 13:28:45.811450 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11546 13:28:45.814836 ok 47 selftests: arm64: syscall-abi
11547 13:28:45.822800 # selftests: arm64: tpidr2
11548 13:28:45.893819 # Segmentation fault
11549 13:28:45.901588 not ok 48 selftests: arm64: tpidr2 # exit=139
11550 13:28:47.427769 arm64_tags_test pass
11551 13:28:47.431209 arm64_run_tags_test_sh pass
11552 13:28:47.435322 arm64_fake_sigreturn_bad_magic pass
11553 13:28:47.438113 arm64_fake_sigreturn_bad_size pass
11554 13:28:47.441923 arm64_fake_sigreturn_bad_size_for_magic0 pass
11555 13:28:47.444889 arm64_fake_sigreturn_duplicated_fpsimd pass
11556 13:28:47.447825 arm64_fake_sigreturn_misaligned_sp pass
11557 13:28:47.451271 arm64_fake_sigreturn_missing_fpsimd pass
11558 13:28:47.455240 arm64_fake_sigreturn_sme_change_vl skip
11559 13:28:47.457914 arm64_fake_sigreturn_sve_change_vl skip
11560 13:28:47.463998 arm64_mangle_pstate_invalid_compat_toggle pass
11561 13:28:47.467628 arm64_mangle_pstate_invalid_daif_bits pass
11562 13:28:47.470901 arm64_mangle_pstate_invalid_mode_el1h pass
11563 13:28:47.474465 arm64_mangle_pstate_invalid_mode_el1t pass
11564 13:28:47.478097 arm64_mangle_pstate_invalid_mode_el2h pass
11565 13:28:47.483900 arm64_mangle_pstate_invalid_mode_el2t pass
11566 13:28:47.487236 arm64_mangle_pstate_invalid_mode_el3h pass
11567 13:28:47.490852 arm64_mangle_pstate_invalid_mode_el3t pass
11568 13:28:47.494384 arm64_sme_trap_no_sm skip
11569 13:28:47.494885 arm64_sme_trap_non_streaming skip
11570 13:28:47.497586 arm64_sme_trap_za pass
11571 13:28:47.500860 arm64_sme_vl skip
11572 13:28:47.501336 arm64_ssve_regs skip
11573 13:28:47.504316 arm64_sve_regs skip
11574 13:28:47.504817 arm64_sve_vl skip
11575 13:28:47.507491 arm64_za_no_regs skip
11576 13:28:47.507999 arm64_za_regs skip
11577 13:28:47.510895 arm64_pac_PAUTH_not_enabled skip
11578 13:28:47.514402 arm64_pac_PAUTH_not_enabled_dup2 skip
11579 13:28:47.517405 arm64_pac_Generic_PAUTH_not_enabled skip
11580 13:28:47.520676 arm64_pac_PAUTH_not_enabled_dup3 skip
11581 13:28:47.524133 arm64_pac_PAUTH_not_enabled_dup4 skip
11582 13:28:47.527492 arm64_pac_PAUTH_not_enabled_dup5 skip
11583 13:28:47.533688 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
11584 13:28:47.534227 arm64_pac pass
11585 13:28:47.537351 arm64_fp-stress_FPSIMD-0-0 pass
11586 13:28:47.540278 arm64_fp-stress_FPSIMD-0-1 pass
11587 13:28:47.543839 arm64_fp-stress_FPSIMD-1-0 pass
11588 13:28:47.547517 arm64_fp-stress_FPSIMD-1-1 pass
11589 13:28:47.548043 arm64_fp-stress_FPSIMD-2-0 pass
11590 13:28:47.550103 arm64_fp-stress_FPSIMD-2-1 pass
11591 13:28:47.553476 arm64_fp-stress_FPSIMD-3-0 pass
11592 13:28:47.557864 arm64_fp-stress_FPSIMD-3-1 pass
11593 13:28:47.559950 arm64_fp-stress_FPSIMD-4-0 pass
11594 13:28:47.563234 arm64_fp-stress_FPSIMD-4-1 pass
11595 13:28:47.566376 arm64_fp-stress_FPSIMD-5-0 pass
11596 13:28:47.566818 arm64_fp-stress_FPSIMD-5-1 pass
11597 13:28:47.570004 arm64_fp-stress_FPSIMD-6-0 pass
11598 13:28:47.573484 arm64_fp-stress_FPSIMD-6-1 pass
11599 13:28:47.576891 arm64_fp-stress_FPSIMD-7-0 pass
11600 13:28:47.580086 arm64_fp-stress_FPSIMD-7-1 pass
11601 13:28:47.583072 arm64_fp-stress pass
11602 13:28:47.586536 arm64_sve-ptrace_SVE_not_available skip
11603 13:28:47.587042 arm64_sve-ptrace skip
11604 13:28:47.589667 arm64_sve-probe-vls_SVE_not_available skip
11605 13:28:47.593122 arm64_sve-probe-vls skip
11606 13:28:47.596783 arm64_vec-syscfg_SVE_not_supported skip
11607 13:28:47.599849 arm64_vec-syscfg_SVE_not_supported_dup2 skip
11608 13:28:47.606694 arm64_vec-syscfg_SVE_not_supported_dup3 skip
11609 13:28:47.610079 arm64_vec-syscfg_SVE_not_supported_dup4 skip
11610 13:28:47.613393 arm64_vec-syscfg_SVE_not_supported_dup5 skip
11611 13:28:47.616366 arm64_vec-syscfg_SVE_not_supported_dup6 skip
11612 13:28:47.619273 arm64_vec-syscfg_SVE_not_supported_dup7 skip
11613 13:28:47.626678 arm64_vec-syscfg_SVE_not_supported_dup8 skip
11614 13:28:47.629731 arm64_vec-syscfg_SVE_not_supported_dup9 skip
11615 13:28:47.632784 arm64_vec-syscfg_SVE_not_supported_dup10 skip
11616 13:28:47.636328 arm64_vec-syscfg_SME_not_supported skip
11617 13:28:47.639918 arm64_vec-syscfg_SME_not_supported_dup2 skip
11618 13:28:47.646534 arm64_vec-syscfg_SME_not_supported_dup3 skip
11619 13:28:47.649742 arm64_vec-syscfg_SME_not_supported_dup4 skip
11620 13:28:47.652819 arm64_vec-syscfg_SME_not_supported_dup5 skip
11621 13:28:47.655985 arm64_vec-syscfg_SME_not_supported_dup6 skip
11622 13:28:47.658927 arm64_vec-syscfg_SME_not_supported_dup7 skip
11623 13:28:47.665680 arm64_vec-syscfg_SME_not_supported_dup8 skip
11624 13:28:47.669688 arm64_vec-syscfg_SME_not_supported_dup9 skip
11625 13:28:47.673488 arm64_vec-syscfg_SME_not_supported_dup10 skip
11626 13:28:47.675660 arm64_vec-syscfg pass
11627 13:28:47.676109 arm64_za-fork_skipped pass
11628 13:28:47.679492 arm64_za-fork pass
11629 13:28:47.682712 arm64_za-ptrace_SME_not_available skip
11630 13:28:47.686002 arm64_za-ptrace skip
11631 13:28:47.686453 arm64_check_buffer_fill skip
11632 13:28:47.689068 arm64_check_child_memory skip
11633 13:28:47.692797 arm64_check_gcr_el1_cswitch skip
11634 13:28:47.695799 arm64_check_ksm_options skip
11635 13:28:47.698698 arm64_check_mmap_options skip
11636 13:28:47.701956 arm64_check_prctl_check_basic_read pass
11637 13:28:47.702384 arm64_check_prctl_NONE pass
11638 13:28:47.705532 arm64_check_prctl_SYNC skip
11639 13:28:47.708727 arm64_check_prctl_ASYNC skip
11640 13:28:47.712580 arm64_check_prctl_SYNC_ASYNC skip
11641 13:28:47.715609 arm64_check_prctl pass
11642 13:28:47.716112 arm64_check_tags_inclusion skip
11643 13:28:47.718528 arm64_check_user_mem skip
11644 13:28:47.722038 arm64_btitest_nohint_func_call_using_br_x0 skip
11645 13:28:47.728699 arm64_btitest_nohint_func_call_using_br_x16 skip
11646 13:28:47.731801 arm64_btitest_nohint_func_call_using_blr skip
11647 13:28:47.735188 arm64_btitest_bti_none_func_call_using_br_x0 skip
11648 13:28:47.741719 arm64_btitest_bti_none_func_call_using_br_x16 skip
11649 13:28:47.745611 arm64_btitest_bti_none_func_call_using_blr skip
11650 13:28:47.748188 arm64_btitest_bti_c_func_call_using_br_x0 skip
11651 13:28:47.755228 arm64_btitest_bti_c_func_call_using_br_x16 skip
11652 13:28:47.758386 arm64_btitest_bti_c_func_call_using_blr skip
11653 13:28:47.761187 arm64_btitest_bti_j_func_call_using_br_x0 skip
11654 13:28:47.765030 arm64_btitest_bti_j_func_call_using_br_x16 skip
11655 13:28:47.770982 arm64_btitest_bti_j_func_call_using_blr skip
11656 13:28:47.774503 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11657 13:28:47.777948 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11658 13:28:47.781304 arm64_btitest_bti_jc_func_call_using_blr skip
11659 13:28:47.787727 arm64_btitest_paciasp_func_call_using_br_x0 skip
11660 13:28:47.790834 arm64_btitest_paciasp_func_call_using_br_x16 skip
11661 13:28:47.794138 arm64_btitest_paciasp_func_call_using_blr skip
11662 13:28:47.797573 arm64_btitest pass
11663 13:28:47.801019 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11664 13:28:47.807369 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11665 13:28:47.811027 arm64_nobtitest_nohint_func_call_using_blr skip
11666 13:28:47.814153 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11667 13:28:47.820330 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11668 13:28:47.824275 arm64_nobtitest_bti_none_func_call_using_blr skip
11669 13:28:47.827273 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11670 13:28:47.833870 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11671 13:28:47.837133 arm64_nobtitest_bti_c_func_call_using_blr skip
11672 13:28:47.840476 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11673 13:28:47.846842 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11674 13:28:47.850571 arm64_nobtitest_bti_j_func_call_using_blr skip
11675 13:28:47.854018 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11676 13:28:47.857055 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11677 13:28:47.863816 arm64_nobtitest_bti_jc_func_call_using_blr skip
11678 13:28:47.867361 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11679 13:28:47.873480 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11680 13:28:47.877105 arm64_nobtitest_paciasp_func_call_using_blr skip
11681 13:28:47.877560 arm64_nobtitest pass
11682 13:28:47.880841 arm64_hwcap_cpuinfo_match_RNG pass
11683 13:28:47.883440 arm64_hwcap_sigill_RNG skip
11684 13:28:47.887319 arm64_hwcap_cpuinfo_match_SME pass
11685 13:28:47.889779 arm64_hwcap_sigill_SME pass
11686 13:28:47.893140 arm64_hwcap_cpuinfo_match_SVE pass
11687 13:28:47.896907 arm64_hwcap_sigill_SVE pass
11688 13:28:47.900392 arm64_hwcap_cpuinfo_match_SVE_2 pass
11689 13:28:47.900776 arm64_hwcap_sigill_SVE_2 skip
11690 13:28:47.903530 arm64_hwcap_cpuinfo_match_SVE_AES pass
11691 13:28:47.907178 arm64_hwcap_sigill_SVE_AES skip
11692 13:28:47.910201 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11693 13:28:47.913284 arm64_hwcap_sigill_SVE2_PMULL skip
11694 13:28:47.920265 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11695 13:28:47.923579 arm64_hwcap_sigill_SVE2_BITPERM skip
11696 13:28:47.926651 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11697 13:28:47.929682 arm64_hwcap_sigill_SVE2_SHA3 skip
11698 13:28:47.933575 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11699 13:28:47.936409 arm64_hwcap_sigill_SVE2_SM4 skip
11700 13:28:47.939577 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11701 13:28:47.943556 arm64_hwcap_sigill_SVE2_I8MM skip
11702 13:28:47.946269 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11703 13:28:47.949135 arm64_hwcap_sigill_SVE2_F32MM skip
11704 13:28:47.952666 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11705 13:28:47.956212 arm64_hwcap_sigill_SVE2_F64MM skip
11706 13:28:47.959467 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11707 13:28:47.962593 arm64_hwcap_sigill_SVE2_BF16 skip
11708 13:28:47.966054 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11709 13:28:47.969343 arm64_hwcap_sigill_SVE2_EBF16 skip
11710 13:28:47.969758 arm64_hwcap pass
11711 13:28:47.972531 arm64_ptrace_read_tpidr_one pass
11712 13:28:47.976071 arm64_ptrace_write_tpidr_one pass
11713 13:28:47.979443 arm64_ptrace_verify_tpidr_one pass
11714 13:28:47.982845 arm64_ptrace_count_tpidrs pass
11715 13:28:47.985918 arm64_ptrace_tpidr2_write pass
11716 13:28:47.989215 arm64_ptrace_tpidr2_read pass
11717 13:28:47.989710 arm64_ptrace_write_tpidr_only pass
11718 13:28:47.992801 arm64_ptrace pass
11719 13:28:47.995529 arm64_syscall-abi_getpid_FPSIMD pass
11720 13:28:47.999285 arm64_syscall-abi_sched_yield_FPSIMD pass
11721 13:28:48.003422 arm64_syscall-abi pass
11722 13:28:48.003975 arm64_tpidr2 fail
11723 13:28:48.009621 + ../../utils/send-to-lava.sh ./output/result.txt
11724 13:28:48.012202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11725 13:28:48.013088 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11727 13:28:48.019506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11728 13:28:48.020483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11730 13:28:48.025496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11731 13:28:48.026157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11733 13:28:48.032077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11734 13:28:48.032842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11736 13:28:48.038911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11737 13:28:48.039526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11739 13:28:48.080012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11740 13:28:48.080665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
11742 13:28:48.124758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
11743 13:28:48.125415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
11745 13:28:48.170804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
11746 13:28:48.171060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
11748 13:28:48.219078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
11749 13:28:48.219836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
11751 13:28:48.263255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
11752 13:28:48.263536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
11754 13:28:48.310704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
11755 13:28:48.310949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
11757 13:28:48.349386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
11758 13:28:48.349636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
11760 13:28:48.391200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
11761 13:28:48.391833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
11763 13:28:48.438816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
11764 13:28:48.439065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
11766 13:28:48.481299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
11767 13:28:48.481607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
11769 13:28:48.525429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
11770 13:28:48.525674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
11772 13:28:48.566955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
11773 13:28:48.567205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
11775 13:28:48.609121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
11776 13:28:48.609491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
11778 13:28:48.649970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
11779 13:28:48.650231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
11781 13:28:48.689528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
11782 13:28:48.690025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
11784 13:28:48.738768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
11786 13:28:48.742043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
11787 13:28:48.789283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
11788 13:28:48.789923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
11790 13:28:48.839857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
11791 13:28:48.840489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
11793 13:28:48.892475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
11794 13:28:48.893102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
11796 13:28:48.938033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
11797 13:28:48.938478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
11799 13:28:48.988600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
11800 13:28:48.989243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
11802 13:28:49.036646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
11803 13:28:49.037308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
11805 13:28:49.086483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
11806 13:28:49.087103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
11808 13:28:49.135466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
11810 13:28:49.138209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
11811 13:28:49.186228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
11812 13:28:49.186873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
11814 13:28:49.235432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
11815 13:28:49.235694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
11817 13:28:49.277727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
11818 13:28:49.278090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
11820 13:28:49.314554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
11821 13:28:49.315183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
11823 13:28:49.356507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
11824 13:28:49.357126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
11826 13:28:49.405860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
11827 13:28:49.406492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
11829 13:28:49.455215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
11830 13:28:49.455835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
11832 13:28:49.504163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
11833 13:28:49.504801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
11835 13:28:49.554266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
11836 13:28:49.554937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
11838 13:28:49.603509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
11839 13:28:49.604155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
11841 13:28:49.650841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
11842 13:28:49.651515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
11844 13:28:49.699422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
11845 13:28:49.700038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
11847 13:28:49.746475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
11848 13:28:49.747155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
11850 13:28:49.795139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
11851 13:28:49.795394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
11853 13:28:49.834545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
11854 13:28:49.834795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
11856 13:28:49.874622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
11857 13:28:49.875459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
11859 13:28:49.924113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
11860 13:28:49.924740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
11862 13:28:49.977755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
11863 13:28:49.978492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
11865 13:28:50.026523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
11866 13:28:50.027226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
11868 13:28:50.078992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
11869 13:28:50.079712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
11871 13:28:50.129965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
11872 13:28:50.130594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
11874 13:28:50.178880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
11875 13:28:50.179584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
11877 13:28:50.228654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
11878 13:28:50.229323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
11880 13:28:50.276657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
11881 13:28:50.277356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
11883 13:28:50.325345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
11884 13:28:50.326076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
11886 13:28:50.370984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
11887 13:28:50.371769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
11889 13:28:50.422052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
11890 13:28:50.422929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
11892 13:28:50.466119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
11893 13:28:50.466962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
11895 13:28:50.522212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
11896 13:28:50.522979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
11898 13:28:50.570769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
11899 13:28:50.571441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
11901 13:28:50.622639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
11902 13:28:50.623318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
11904 13:28:50.670113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
11905 13:28:50.670915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
11907 13:28:50.721552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
11908 13:28:50.722292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
11910 13:28:50.769042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
11911 13:28:50.769911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
11913 13:28:50.822102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
11914 13:28:50.822923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
11916 13:28:50.872172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
11917 13:28:50.872922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
11919 13:28:50.923896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
11920 13:28:50.924588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
11922 13:28:50.974047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
11923 13:28:50.974749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
11925 13:28:51.023242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
11926 13:28:51.023969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
11928 13:28:51.074308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
11929 13:28:51.074986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
11931 13:28:51.126828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
11932 13:28:51.127458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
11934 13:28:51.177406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
11935 13:28:51.177661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
11937 13:28:51.221174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
11938 13:28:51.221486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
11940 13:28:51.266712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
11941 13:28:51.267431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
11943 13:28:51.315827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
11944 13:28:51.316681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
11946 13:28:51.362585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
11947 13:28:51.363269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
11949 13:28:51.410473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
11950 13:28:51.410723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
11952 13:28:51.455245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
11953 13:28:51.455543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
11955 13:28:51.484858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
11956 13:28:51.485110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
11958 13:28:51.517728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
11959 13:28:51.518510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
11961 13:28:51.566733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
11962 13:28:51.567376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
11964 13:28:51.621891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
11965 13:28:51.622611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
11967 13:28:51.668346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
11968 13:28:51.669088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
11970 13:28:51.719544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
11971 13:28:51.720203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
11973 13:28:51.769947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
11974 13:28:51.770621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
11976 13:28:51.824465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
11978 13:28:51.827888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
11979 13:28:51.874156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
11980 13:28:51.874831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
11982 13:28:51.923563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
11983 13:28:51.924186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
11985 13:28:51.978295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
11986 13:28:51.978937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
11988 13:28:52.025864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
11989 13:28:52.026534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
11991 13:28:52.075903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
11992 13:28:52.076580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
11994 13:28:52.126260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
11995 13:28:52.126894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
11997 13:28:52.178540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
11999 13:28:52.181558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12000 13:28:52.227901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12001 13:28:52.228521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12003 13:28:52.276638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12004 13:28:52.277454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12006 13:28:52.323297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12007 13:28:52.323938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12009 13:28:52.381918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12010 13:28:52.382762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12012 13:28:52.429510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12013 13:28:52.430290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12015 13:28:52.479589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12016 13:28:52.480359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12018 13:28:52.528048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12019 13:28:52.528835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12021 13:28:52.576503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12022 13:28:52.577207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12024 13:28:52.623760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12025 13:28:52.624474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12027 13:28:52.674332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12028 13:28:52.675025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12030 13:28:52.725932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12031 13:28:52.726711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12033 13:28:52.768589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12034 13:28:52.768837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12036 13:28:52.813960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12037 13:28:52.814212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12039 13:28:52.857687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12040 13:28:52.857935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12042 13:28:52.897568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12043 13:28:52.897862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12045 13:28:52.938057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12046 13:28:52.938349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12048 13:28:52.982684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12049 13:28:52.982944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12051 13:28:53.023365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12052 13:28:53.023656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12054 13:28:53.064519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12055 13:28:53.064809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12057 13:28:53.108785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12058 13:28:53.109516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12060 13:28:53.153572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12061 13:28:53.153832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12063 13:28:53.189869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12064 13:28:53.190545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12066 13:28:53.241604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12067 13:28:53.242312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12069 13:28:53.292341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12070 13:28:53.292988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12072 13:28:53.342342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12073 13:28:53.343112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12075 13:28:53.393804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12076 13:28:53.394467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12078 13:28:53.443883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12079 13:28:53.444560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12081 13:28:53.492730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12082 13:28:53.493392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12084 13:28:53.545726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12085 13:28:53.546380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12087 13:28:53.595718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12088 13:28:53.596346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12090 13:28:53.649083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12091 13:28:53.649916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12093 13:28:53.697593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12094 13:28:53.698226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12096 13:28:53.745432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12097 13:28:53.746065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12099 13:28:53.794572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12100 13:28:53.795245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12102 13:28:53.845732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12103 13:28:53.846394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12105 13:28:53.895641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12106 13:28:53.896307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12108 13:28:53.948497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12109 13:28:53.948863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12111 13:28:53.986022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12112 13:28:53.986275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12114 13:28:54.025763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12115 13:28:54.026086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12117 13:28:54.068394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12118 13:28:54.068662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12120 13:28:54.115244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12121 13:28:54.115867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12123 13:28:54.161779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12124 13:28:54.162508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12126 13:28:54.207219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12127 13:28:54.207932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12129 13:28:54.250582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12131 13:28:54.253169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12132 13:28:54.286444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12133 13:28:54.286690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12135 13:28:54.328279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12136 13:28:54.328521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12138 13:28:54.361418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12139 13:28:54.361671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12141 13:28:54.397592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12142 13:28:54.397853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12144 13:28:54.437259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12145 13:28:54.437633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12147 13:28:54.484594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12148 13:28:54.484844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12150 13:28:54.520929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12151 13:28:54.521175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12153 13:28:54.564954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12154 13:28:54.565201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12156 13:28:54.606109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12157 13:28:54.606383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12159 13:28:54.642428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12160 13:28:54.642669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12162 13:28:54.688417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12163 13:28:54.689031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12165 13:28:54.735876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12166 13:28:54.736146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12168 13:28:54.775510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12170 13:28:54.778204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12171 13:28:54.813281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12172 13:28:54.813536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12174 13:28:54.845500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12175 13:28:54.845749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12177 13:28:54.885604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12178 13:28:54.885876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12180 13:28:54.917210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12182 13:28:54.920020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12183 13:28:54.958859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12184 13:28:54.959488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12186 13:28:55.007958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12187 13:28:55.008650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12189 13:28:55.056288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12190 13:28:55.056976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12192 13:28:55.107789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12193 13:28:55.108426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12195 13:28:55.154190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12196 13:28:55.154809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12198 13:28:55.201174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12200 13:28:55.204688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12201 13:28:55.251075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12202 13:28:55.251703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12204 13:28:55.300595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12205 13:28:55.301217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12207 13:28:55.340105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12208 13:28:55.340753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12210 13:28:55.386613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12212 13:28:55.389924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12213 13:28:55.436516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12215 13:28:55.439349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12216 13:28:55.489711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12217 13:28:55.490392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12219 13:28:55.535400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12220 13:28:55.536018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12222 13:28:55.583073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12223 13:28:55.583700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12225 13:28:55.632290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12226 13:28:55.632997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12228 13:28:55.683979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12229 13:28:55.684622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12231 13:28:55.733599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12232 13:28:55.734259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12234 13:28:55.789774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12235 13:28:55.790447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12237 13:28:55.834977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12238 13:28:55.835237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12240 13:28:55.878307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12241 13:28:55.878727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12243 13:28:55.922038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=fail>
12244 13:28:55.922127 + set +x
12245 13:28:55.922358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=fail
12247 13:28:55.928451 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 14879058_1.6.2.3.5>
12248 13:28:55.928722 Received signal: <ENDRUN> 1_kselftest-arm64 14879058_1.6.2.3.5
12249 13:28:55.928830 Ending use of test pattern.
12250 13:28:55.929013 Ending test lava.1_kselftest-arm64 (14879058_1.6.2.3.5), duration 33.63
12252 13:28:55.931521 <LAVA_TEST_RUNNER EXIT>
12253 13:28:55.931823 ok: lava_test_shell seems to have completed
12254 13:28:55.932871 shardfile-arm64: pass
arm64_tags_test: pass
arm64_run_tags_test_sh: pass
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_fp-stress: pass
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-probe-vls: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg: pass
arm64_za-fork_skipped: pass
arm64_za-fork: pass
arm64_za-ptrace_SME_not_available: skip
arm64_za-ptrace: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest: pass
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_SVE_AES: skip
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_write_tpidr_only: pass
arm64_ptrace: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_syscall-abi: pass
arm64_tpidr2: fail
12255 13:28:55.933071 end: 3.1 lava-test-shell (duration 00:00:35) [common]
12256 13:28:55.933173 end: 3 lava-test-retry (duration 00:00:35) [common]
12257 13:28:55.933281 start: 4 finalize (timeout 00:07:17) [common]
12258 13:28:55.933381 start: 4.1 power-off (timeout 00:00:30) [common]
12259 13:28:55.933532 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
12260 13:28:58.005595 >> Command sent successfully.
12261 13:28:58.012447 Returned 0 in 2 seconds
12262 13:28:58.012583 end: 4.1 power-off (duration 00:00:02) [common]
12264 13:28:58.012790 start: 4.2 read-feedback (timeout 00:07:15) [common]
12265 13:28:58.012939 Listened to connection for namespace 'common' for up to 1s
12266 13:28:59.013511 Finalising connection for namespace 'common'
12267 13:28:59.014116 Disconnecting from shell: Finalise
12268 13:28:59.014491 / #
12269 13:28:59.115444 end: 4.2 read-feedback (duration 00:00:01) [common]
12270 13:28:59.116084 end: 4 finalize (duration 00:00:03) [common]
12271 13:28:59.116648 Cleaning after the job
12272 13:28:59.117139 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879058/tftp-deploy-136pl3gy/ramdisk
12273 13:28:59.128046 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879058/tftp-deploy-136pl3gy/kernel
12274 13:28:59.162235 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879058/tftp-deploy-136pl3gy/dtb
12275 13:28:59.162561 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879058/tftp-deploy-136pl3gy/nfsrootfs
12276 13:28:59.229479 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879058/tftp-deploy-136pl3gy/modules
12277 13:28:59.234693 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14879058
12278 13:28:59.810549 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14879058
12279 13:28:59.810723 Job finished correctly