Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 38
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 13:06:58.514873 lava-dispatcher, installed at version: 2024.05
2 13:06:58.515069 start: 0 validate
3 13:06:58.515189 Start time: 2024-07-18 13:06:58.515184+00:00 (UTC)
4 13:06:58.515318 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:06:58.515461 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 13:06:58.775052 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:06:58.775220 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 13:07:10.036172 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:07:10.036753 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:07:10.295080 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:07:10.295278 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:07:10.793889 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:07:10.794400 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 13:07:12.800649 validate duration: 14.29
16 13:07:12.801049 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:07:12.801198 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:07:12.801344 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:07:12.801572 Not decompressing ramdisk as can be used compressed.
20 13:07:12.801715 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 13:07:12.801854 saving as /var/lib/lava/dispatcher/tmp/14878994/tftp-deploy-o87jl0sz/ramdisk/initrd.cpio.gz
22 13:07:12.801949 total size: 5628169 (5 MB)
23 13:07:12.803250 progress 0 % (0 MB)
24 13:07:12.805666 progress 5 % (0 MB)
25 13:07:12.808212 progress 10 % (0 MB)
26 13:07:12.810376 progress 15 % (0 MB)
27 13:07:12.812824 progress 20 % (1 MB)
28 13:07:12.814986 progress 25 % (1 MB)
29 13:07:12.817389 progress 30 % (1 MB)
30 13:07:12.819748 progress 35 % (1 MB)
31 13:07:12.821883 progress 40 % (2 MB)
32 13:07:12.824362 progress 45 % (2 MB)
33 13:07:12.826502 progress 50 % (2 MB)
34 13:07:12.828936 progress 55 % (2 MB)
35 13:07:12.831304 progress 60 % (3 MB)
36 13:07:12.833502 progress 65 % (3 MB)
37 13:07:12.835836 progress 70 % (3 MB)
38 13:07:12.837931 progress 75 % (4 MB)
39 13:07:12.840318 progress 80 % (4 MB)
40 13:07:12.842386 progress 85 % (4 MB)
41 13:07:12.843886 progress 90 % (4 MB)
42 13:07:12.845365 progress 95 % (5 MB)
43 13:07:12.846714 progress 100 % (5 MB)
44 13:07:12.846920 5 MB downloaded in 0.04 s (119.37 MB/s)
45 13:07:12.847068 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:07:12.847288 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:07:12.847369 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:07:12.847446 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:07:12.847585 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 13:07:12.847649 saving as /var/lib/lava/dispatcher/tmp/14878994/tftp-deploy-o87jl0sz/kernel/Image
52 13:07:12.847702 total size: 54813184 (52 MB)
53 13:07:12.847756 No compression specified
54 13:07:12.848762 progress 0 % (0 MB)
55 13:07:12.862082 progress 5 % (2 MB)
56 13:07:12.876724 progress 10 % (5 MB)
57 13:07:12.890471 progress 15 % (7 MB)
58 13:07:12.905306 progress 20 % (10 MB)
59 13:07:12.920070 progress 25 % (13 MB)
60 13:07:12.934361 progress 30 % (15 MB)
61 13:07:12.949474 progress 35 % (18 MB)
62 13:07:12.963200 progress 40 % (20 MB)
63 13:07:12.977780 progress 45 % (23 MB)
64 13:07:12.991616 progress 50 % (26 MB)
65 13:07:13.005250 progress 55 % (28 MB)
66 13:07:13.018381 progress 60 % (31 MB)
67 13:07:13.032046 progress 65 % (34 MB)
68 13:07:13.046324 progress 70 % (36 MB)
69 13:07:13.059881 progress 75 % (39 MB)
70 13:07:13.073566 progress 80 % (41 MB)
71 13:07:13.088595 progress 85 % (44 MB)
72 13:07:13.102182 progress 90 % (47 MB)
73 13:07:13.115846 progress 95 % (49 MB)
74 13:07:13.129022 progress 100 % (52 MB)
75 13:07:13.129295 52 MB downloaded in 0.28 s (185.64 MB/s)
76 13:07:13.129440 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:07:13.129645 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:07:13.129725 start: 1.3 download-retry (timeout 00:10:00) [common]
80 13:07:13.129800 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 13:07:13.129951 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:07:13.130039 saving as /var/lib/lava/dispatcher/tmp/14878994/tftp-deploy-o87jl0sz/dtb/mt8192-asurada-spherion-r0.dtb
83 13:07:13.130145 total size: 47258 (0 MB)
84 13:07:13.130206 No compression specified
85 13:07:13.131474 progress 69 % (0 MB)
86 13:07:13.131764 progress 100 % (0 MB)
87 13:07:13.131906 0 MB downloaded in 0.00 s (25.62 MB/s)
88 13:07:13.132048 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:07:13.132265 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:07:13.132348 start: 1.4 download-retry (timeout 00:10:00) [common]
92 13:07:13.132429 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 13:07:13.132538 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 13:07:13.132611 saving as /var/lib/lava/dispatcher/tmp/14878994/tftp-deploy-o87jl0sz/nfsrootfs/full.rootfs.tar
95 13:07:13.132663 total size: 120894716 (115 MB)
96 13:07:13.132722 Using unxz to decompress xz
97 13:07:13.134229 progress 0 % (0 MB)
98 13:07:13.475448 progress 5 % (5 MB)
99 13:07:13.832027 progress 10 % (11 MB)
100 13:07:14.185281 progress 15 % (17 MB)
101 13:07:14.521648 progress 20 % (23 MB)
102 13:07:14.830486 progress 25 % (28 MB)
103 13:07:15.182710 progress 30 % (34 MB)
104 13:07:15.504530 progress 35 % (40 MB)
105 13:07:15.683915 progress 40 % (46 MB)
106 13:07:15.868078 progress 45 % (51 MB)
107 13:07:16.174797 progress 50 % (57 MB)
108 13:07:16.531016 progress 55 % (63 MB)
109 13:07:16.868374 progress 60 % (69 MB)
110 13:07:17.212265 progress 65 % (74 MB)
111 13:07:17.553102 progress 70 % (80 MB)
112 13:07:17.907540 progress 75 % (86 MB)
113 13:07:18.239550 progress 80 % (92 MB)
114 13:07:18.587318 progress 85 % (98 MB)
115 13:07:18.925423 progress 90 % (103 MB)
116 13:07:19.255505 progress 95 % (109 MB)
117 13:07:19.608918 progress 100 % (115 MB)
118 13:07:19.614331 115 MB downloaded in 6.48 s (17.79 MB/s)
119 13:07:19.614502 end: 1.4.1 http-download (duration 00:00:06) [common]
121 13:07:19.614718 end: 1.4 download-retry (duration 00:00:06) [common]
122 13:07:19.614798 start: 1.5 download-retry (timeout 00:09:53) [common]
123 13:07:19.614875 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 13:07:19.615009 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 13:07:19.615072 saving as /var/lib/lava/dispatcher/tmp/14878994/tftp-deploy-o87jl0sz/modules/modules.tar
126 13:07:19.615126 total size: 8611320 (8 MB)
127 13:07:19.615182 Using unxz to decompress xz
128 13:07:19.616417 progress 0 % (0 MB)
129 13:07:19.636993 progress 5 % (0 MB)
130 13:07:19.661615 progress 10 % (0 MB)
131 13:07:19.686406 progress 15 % (1 MB)
132 13:07:19.712299 progress 20 % (1 MB)
133 13:07:19.736569 progress 25 % (2 MB)
134 13:07:19.761488 progress 30 % (2 MB)
135 13:07:19.785127 progress 35 % (2 MB)
136 13:07:19.812456 progress 40 % (3 MB)
137 13:07:19.837333 progress 45 % (3 MB)
138 13:07:19.861372 progress 50 % (4 MB)
139 13:07:19.885718 progress 55 % (4 MB)
140 13:07:19.909854 progress 60 % (4 MB)
141 13:07:19.933251 progress 65 % (5 MB)
142 13:07:19.959095 progress 70 % (5 MB)
143 13:07:19.986776 progress 75 % (6 MB)
144 13:07:20.013913 progress 80 % (6 MB)
145 13:07:20.037406 progress 85 % (7 MB)
146 13:07:20.060462 progress 90 % (7 MB)
147 13:07:20.083668 progress 95 % (7 MB)
148 13:07:20.106277 progress 100 % (8 MB)
149 13:07:20.111774 8 MB downloaded in 0.50 s (16.54 MB/s)
150 13:07:20.111931 end: 1.5.1 http-download (duration 00:00:00) [common]
152 13:07:20.112145 end: 1.5 download-retry (duration 00:00:00) [common]
153 13:07:20.112225 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 13:07:20.112302 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 13:07:23.674976 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14878994/extract-nfsrootfs-wgu7z_rn
156 13:07:23.675186 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 13:07:23.675282 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 13:07:23.675466 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4
159 13:07:23.675589 makedir: /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin
160 13:07:23.675686 makedir: /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/tests
161 13:07:23.675776 makedir: /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/results
162 13:07:23.675865 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-add-keys
163 13:07:23.675998 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-add-sources
164 13:07:23.676126 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-background-process-start
165 13:07:23.676263 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-background-process-stop
166 13:07:23.676393 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-common-functions
167 13:07:23.676513 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-echo-ipv4
168 13:07:23.676631 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-install-packages
169 13:07:23.676745 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-installed-packages
170 13:07:23.676859 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-os-build
171 13:07:23.676978 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-probe-channel
172 13:07:23.677093 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-probe-ip
173 13:07:23.677207 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-target-ip
174 13:07:23.677322 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-target-mac
175 13:07:23.677439 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-target-storage
176 13:07:23.677557 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-test-case
177 13:07:23.677675 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-test-event
178 13:07:23.677788 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-test-feedback
179 13:07:23.677903 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-test-raise
180 13:07:23.678016 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-test-reference
181 13:07:23.678142 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-test-runner
182 13:07:23.678257 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-test-set
183 13:07:23.678370 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-test-shell
184 13:07:23.678490 Updating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-add-keys (debian)
185 13:07:23.680023 Updating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-add-sources (debian)
186 13:07:23.680174 Updating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-install-packages (debian)
187 13:07:23.680305 Updating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-installed-packages (debian)
188 13:07:23.680436 Updating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/bin/lava-os-build (debian)
189 13:07:23.680549 Creating /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/environment
190 13:07:23.680643 LAVA metadata
191 13:07:23.680712 - LAVA_JOB_ID=14878994
192 13:07:23.680775 - LAVA_DISPATCHER_IP=192.168.201.1
193 13:07:23.680886 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 13:07:23.680945 skipped lava-vland-overlay
195 13:07:23.681016 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 13:07:23.681091 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 13:07:23.681147 skipped lava-multinode-overlay
198 13:07:23.681213 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 13:07:23.681285 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 13:07:23.681352 Loading test definitions
201 13:07:23.681435 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 13:07:23.681498 Using /lava-14878994 at stage 0
203 13:07:23.681794 uuid=14878994_1.6.2.3.1 testdef=None
204 13:07:23.681881 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 13:07:23.681958 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 13:07:23.682403 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 13:07:23.682607 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 13:07:23.683122 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 13:07:23.683337 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 13:07:23.703834 runner path: /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/0/tests/0_timesync-off test_uuid 14878994_1.6.2.3.1
213 13:07:23.704034 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 13:07:23.704251 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 13:07:23.704321 Using /lava-14878994 at stage 0
217 13:07:23.704414 Fetching tests from https://github.com/kernelci/test-definitions.git
218 13:07:23.704492 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/0/tests/1_kselftest-rtc'
219 13:07:27.620441 Running '/usr/bin/git checkout kernelci.org
220 13:07:27.771021 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 13:07:27.771553 uuid=14878994_1.6.2.3.5 testdef=None
222 13:07:27.771696 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 13:07:27.771983 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 13:07:27.772951 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 13:07:27.773253 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 13:07:27.774628 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 13:07:27.774943 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 13:07:27.776232 runner path: /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/0/tests/1_kselftest-rtc test_uuid 14878994_1.6.2.3.5
232 13:07:27.776340 BOARD='mt8192-asurada-spherion-r0'
233 13:07:27.776423 BRANCH='cip'
234 13:07:27.776502 SKIPFILE='/dev/null'
235 13:07:27.776578 SKIP_INSTALL='True'
236 13:07:27.776655 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz'
237 13:07:27.776735 TST_CASENAME=''
238 13:07:27.776812 TST_CMDFILES='rtc'
239 13:07:27.776992 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 13:07:27.777276 Creating lava-test-runner.conf files
242 13:07:27.777359 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14878994/lava-overlay-ieg6tsa4/lava-14878994/0 for stage 0
243 13:07:27.777478 - 0_timesync-off
244 13:07:27.777565 - 1_kselftest-rtc
245 13:07:27.777686 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 13:07:27.777796 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 13:07:35.025863 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 13:07:35.026025 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 13:07:35.026126 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 13:07:35.026224 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 13:07:35.026302 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 13:07:35.177201 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 13:07:35.177377 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 13:07:35.177480 extracting modules file /var/lib/lava/dispatcher/tmp/14878994/tftp-deploy-o87jl0sz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14878994/extract-nfsrootfs-wgu7z_rn
255 13:07:35.458900 extracting modules file /var/lib/lava/dispatcher/tmp/14878994/tftp-deploy-o87jl0sz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14878994/extract-overlay-ramdisk-rae_wd81/ramdisk
256 13:07:35.701082 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 13:07:35.701231 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 13:07:35.701315 [common] Applying overlay to NFS
259 13:07:35.701375 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14878994/compress-overlay-ukk337o7/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14878994/extract-nfsrootfs-wgu7z_rn
260 13:07:36.533526 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 13:07:36.533681 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 13:07:36.533798 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 13:07:36.533907 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 13:07:36.534006 Building ramdisk /var/lib/lava/dispatcher/tmp/14878994/extract-overlay-ramdisk-rae_wd81/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14878994/extract-overlay-ramdisk-rae_wd81/ramdisk
265 13:07:36.808980 >> 129966 blocks
266 13:07:38.932679 rename /var/lib/lava/dispatcher/tmp/14878994/extract-overlay-ramdisk-rae_wd81/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14878994/tftp-deploy-o87jl0sz/ramdisk/ramdisk.cpio.gz
267 13:07:38.932854 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 13:07:38.932966 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 13:07:38.933059 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 13:07:38.933136 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14878994/tftp-deploy-o87jl0sz/kernel/Image']
271 13:07:54.163027 Returned 0 in 15 seconds
272 13:07:54.163239 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14878994/tftp-deploy-o87jl0sz/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14878994/tftp-deploy-o87jl0sz/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14878994/tftp-deploy-o87jl0sz/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14878994/tftp-deploy-o87jl0sz/kernel/image.itb
273 13:07:54.528342 output: FIT description: Kernel Image image with one or more FDT blobs
274 13:07:54.528477 output: Created: Thu Jul 18 14:07:54 2024
275 13:07:54.528544 output: Image 0 (kernel-1)
276 13:07:54.528598 output: Description:
277 13:07:54.528650 output: Created: Thu Jul 18 14:07:54 2024
278 13:07:54.528701 output: Type: Kernel Image
279 13:07:54.528752 output: Compression: lzma compressed
280 13:07:54.528805 output: Data Size: 13114469 Bytes = 12807.10 KiB = 12.51 MiB
281 13:07:54.528856 output: Architecture: AArch64
282 13:07:54.528905 output: OS: Linux
283 13:07:54.528952 output: Load Address: 0x00000000
284 13:07:54.529001 output: Entry Point: 0x00000000
285 13:07:54.529049 output: Hash algo: crc32
286 13:07:54.529098 output: Hash value: a47b020b
287 13:07:54.529146 output: Image 1 (fdt-1)
288 13:07:54.529193 output: Description: mt8192-asurada-spherion-r0
289 13:07:54.529241 output: Created: Thu Jul 18 14:07:54 2024
290 13:07:54.529289 output: Type: Flat Device Tree
291 13:07:54.529337 output: Compression: uncompressed
292 13:07:54.529385 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 13:07:54.529433 output: Architecture: AArch64
294 13:07:54.529481 output: Hash algo: crc32
295 13:07:54.529527 output: Hash value: 0f8e4d2e
296 13:07:54.529574 output: Image 2 (ramdisk-1)
297 13:07:54.529621 output: Description: unavailable
298 13:07:54.529669 output: Created: Thu Jul 18 14:07:54 2024
299 13:07:54.529716 output: Type: RAMDisk Image
300 13:07:54.529812 output: Compression: uncompressed
301 13:07:54.529863 output: Data Size: 18718181 Bytes = 18279.47 KiB = 17.85 MiB
302 13:07:54.529911 output: Architecture: AArch64
303 13:07:54.529959 output: OS: Linux
304 13:07:54.530006 output: Load Address: unavailable
305 13:07:54.530054 output: Entry Point: unavailable
306 13:07:54.530132 output: Hash algo: crc32
307 13:07:54.530198 output: Hash value: d0dffadc
308 13:07:54.530246 output: Default Configuration: 'conf-1'
309 13:07:54.530294 output: Configuration 0 (conf-1)
310 13:07:54.530341 output: Description: mt8192-asurada-spherion-r0
311 13:07:54.530389 output: Kernel: kernel-1
312 13:07:54.530437 output: Init Ramdisk: ramdisk-1
313 13:07:54.530485 output: FDT: fdt-1
314 13:07:54.530533 output: Loadables: kernel-1
315 13:07:54.530581 output:
316 13:07:54.530686 end: 1.6.8.1 prepare-fit (duration 00:00:16) [common]
317 13:07:54.530761 end: 1.6.8 prepare-kernel (duration 00:00:16) [common]
318 13:07:54.530836 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 13:07:54.530910 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 13:07:54.530968 No LXC device requested
321 13:07:54.531034 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 13:07:54.531105 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 13:07:54.531173 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 13:07:54.531227 Checking files for TFTP limit of 4294967296 bytes.
325 13:07:54.531610 end: 1 tftp-deploy (duration 00:00:42) [common]
326 13:07:54.531700 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 13:07:54.531795 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 13:07:54.531900 substitutions:
329 13:07:54.531958 - {DTB}: 14878994/tftp-deploy-o87jl0sz/dtb/mt8192-asurada-spherion-r0.dtb
330 13:07:54.532012 - {INITRD}: 14878994/tftp-deploy-o87jl0sz/ramdisk/ramdisk.cpio.gz
331 13:07:54.532065 - {KERNEL}: 14878994/tftp-deploy-o87jl0sz/kernel/Image
332 13:07:54.532116 - {LAVA_MAC}: None
333 13:07:54.532166 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14878994/extract-nfsrootfs-wgu7z_rn
334 13:07:54.532216 - {NFS_SERVER_IP}: 192.168.201.1
335 13:07:54.532265 - {PRESEED_CONFIG}: None
336 13:07:54.532322 - {PRESEED_LOCAL}: None
337 13:07:54.532371 - {RAMDISK}: 14878994/tftp-deploy-o87jl0sz/ramdisk/ramdisk.cpio.gz
338 13:07:54.532420 - {ROOT_PART}: None
339 13:07:54.532468 - {ROOT}: None
340 13:07:54.532516 - {SERVER_IP}: 192.168.201.1
341 13:07:54.532564 - {TEE}: None
342 13:07:54.532612 Parsed boot commands:
343 13:07:54.532659 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 13:07:54.532811 Parsed boot commands: tftpboot 192.168.201.1 14878994/tftp-deploy-o87jl0sz/kernel/image.itb 14878994/tftp-deploy-o87jl0sz/kernel/cmdline
345 13:07:54.532892 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 13:07:54.532967 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 13:07:54.533040 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 13:07:54.533109 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 13:07:54.533164 Not connected, no need to disconnect.
350 13:07:54.533229 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 13:07:54.533297 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 13:07:54.533351 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 13:07:54.536657 Setting prompt string to ['lava-test: # ']
354 13:07:54.537031 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 13:07:54.537147 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 13:07:54.537269 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 13:07:54.537354 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 13:07:54.537530 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=reboot']
359 13:08:03.679170 >> Command sent successfully.
360 13:08:03.682092 Returned 0 in 9 seconds
361 13:08:03.682303 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 13:08:03.682517 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 13:08:03.682604 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 13:08:03.682676 Setting prompt string to 'Starting depthcharge on Spherion...'
366 13:08:03.682733 Changing prompt to 'Starting depthcharge on Spherion...'
367 13:08:03.682795 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 13:08:03.683121 [Enter `^Ec?' for help]
369 13:08:04.911213
370 13:08:04.911354
371 13:08:04.911449 F0: 102B 0000
372 13:08:04.911539
373 13:08:04.911619 F3: 1001 0000 [0200]
374 13:08:04.914580
375 13:08:04.914659 F3: 1001 0000
376 13:08:04.914722
377 13:08:04.914777 F7: 102D 0000
378 13:08:04.914827
379 13:08:04.917718 F1: 0000 0000
380 13:08:04.917806
381 13:08:04.917891 V0: 0000 0000 [0001]
382 13:08:04.917971
383 13:08:04.921183 00: 0007 8000
384 13:08:04.921275
385 13:08:04.921356 01: 0000 0000
386 13:08:04.921447
387 13:08:04.924412 BP: 0C00 0209 [0000]
388 13:08:04.924501
389 13:08:04.924579 G0: 1182 0000
390 13:08:04.924656
391 13:08:04.927525 EC: 0000 0021 [4000]
392 13:08:04.927586
393 13:08:04.927638 S7: 0000 0000 [0000]
394 13:08:04.927687
395 13:08:04.930992 CC: 0000 0000 [0001]
396 13:08:04.931057
397 13:08:04.931111 T0: 0000 0040 [010F]
398 13:08:04.931161
399 13:08:04.934335 Jump to BL
400 13:08:04.934398
401 13:08:04.958429
402 13:08:04.958528
403 13:08:04.968158 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 13:08:04.971244 ARM64: Exception handlers installed.
405 13:08:04.971308 ARM64: Testing exception
406 13:08:04.974745 ARM64: Done test exception
407 13:08:04.981131 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 13:08:04.991315 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 13:08:04.998560 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 13:08:05.008751 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 13:08:05.015757 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 13:08:05.026007 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 13:08:05.035806 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 13:08:05.042790 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 13:08:05.061096 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 13:08:05.064203 WDT: Last reset was cold boot
417 13:08:05.067877 SPI1(PAD0) initialized at 2873684 Hz
418 13:08:05.070818 SPI5(PAD0) initialized at 992727 Hz
419 13:08:05.074574 VBOOT: Loading verstage.
420 13:08:05.081144 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 13:08:05.084253 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 13:08:05.087858 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 13:08:05.091363 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 13:08:05.098413 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 13:08:05.105060 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 13:08:05.116009 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
427 13:08:05.116104
428 13:08:05.116196
429 13:08:05.126260 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 13:08:05.129162 ARM64: Exception handlers installed.
431 13:08:05.132936 ARM64: Testing exception
432 13:08:05.133006 ARM64: Done test exception
433 13:08:05.139412 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 13:08:05.143011 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 13:08:05.157310 Probing TPM: . done!
436 13:08:05.157413 TPM ready after 0 ms
437 13:08:05.164101 Connected to device vid:did:rid of 1ae0:0028:00
438 13:08:05.170569 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
439 13:08:05.222040 Initialized TPM device CR50 revision 0
440 13:08:05.236072 tlcl_send_startup: Startup return code is 0
441 13:08:05.236149 TPM: setup succeeded
442 13:08:05.249739 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 13:08:05.259040 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 13:08:05.270526 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 13:08:05.280342 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 13:08:05.284183 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 13:08:05.287933 in-header: 03 07 00 00 08 00 00 00
448 13:08:05.291641 in-data: aa e4 47 04 13 02 00 00
449 13:08:05.291740 Chrome EC: UHEPI supported
450 13:08:05.298509 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 13:08:05.303922 in-header: 03 a9 00 00 08 00 00 00
452 13:08:05.306711 in-data: 84 60 60 08 00 00 00 00
453 13:08:05.306809 Phase 1
454 13:08:05.314034 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 13:08:05.317770 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 13:08:05.321632 VB2:vb2_check_recovery() Recovery was requested manually
457 13:08:05.328663 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
458 13:08:05.332622 Recovery requested (1009000e)
459 13:08:05.341037 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 13:08:05.346663 tlcl_extend: response is 0
461 13:08:05.355877 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 13:08:05.361080 tlcl_extend: response is 0
463 13:08:05.368256 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 13:08:05.388684 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 13:08:05.395998 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 13:08:05.396087
467 13:08:05.396166
468 13:08:05.403573 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 13:08:05.407330 ARM64: Exception handlers installed.
470 13:08:05.410817 ARM64: Testing exception
471 13:08:05.414460 ARM64: Done test exception
472 13:08:05.433795 pmic_efuse_setting: Set efuses in 11 msecs
473 13:08:05.437860 pmwrap_interface_init: Select PMIF_VLD_RDY
474 13:08:05.441308 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 13:08:05.448846 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 13:08:05.452397 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 13:08:05.456316 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 13:08:05.464163 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 13:08:05.467321 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 13:08:05.471392 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 13:08:05.474693 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 13:08:05.482467 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 13:08:05.485647 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 13:08:05.489370 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 13:08:05.496785 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 13:08:05.500282 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 13:08:05.504101 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 13:08:05.511564 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 13:08:05.519370 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 13:08:05.522894 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 13:08:05.529946 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 13:08:05.533315 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 13:08:05.539751 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 13:08:05.546466 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 13:08:05.549576 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 13:08:05.556398 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 13:08:05.563445 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 13:08:05.566384 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 13:08:05.573046 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 13:08:05.576642 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 13:08:05.582857 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 13:08:05.586480 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 13:08:05.593121 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 13:08:05.596199 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 13:08:05.602904 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 13:08:05.606623 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 13:08:05.613691 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 13:08:05.616763 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 13:08:05.623531 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 13:08:05.627033 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 13:08:05.633439 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 13:08:05.637056 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 13:08:05.640425 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 13:08:05.646974 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 13:08:05.650561 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 13:08:05.653956 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 13:08:05.657650 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 13:08:05.663926 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 13:08:05.666817 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 13:08:05.670650 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 13:08:05.676923 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 13:08:05.680451 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 13:08:05.683568 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 13:08:05.686912 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 13:08:05.696651 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
526 13:08:05.703954 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 13:08:05.710549 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 13:08:05.716809 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 13:08:05.726828 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 13:08:05.730414 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 13:08:05.733358 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 13:08:05.740203 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 13:08:05.747014 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x21
534 13:08:05.752978 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 13:08:05.756506 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 13:08:05.759619 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 13:08:05.770688 [RTC]rtc_get_frequency_meter,154: input=15, output=794
538 13:08:05.774458 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 13:08:05.780620 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 13:08:05.784558 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
541 13:08:05.787302 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 13:08:05.790682 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
543 13:08:05.794370 ADC[4]: Raw value=896670 ID=7
544 13:08:05.797662 ADC[3]: Raw value=212700 ID=1
545 13:08:05.797760 RAM Code: 0x71
546 13:08:05.805122 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 13:08:05.808918 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 13:08:05.816250 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 13:08:05.822459 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 13:08:05.825922 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 13:08:05.829661 in-header: 03 07 00 00 08 00 00 00
552 13:08:05.833537 in-data: aa e4 47 04 13 02 00 00
553 13:08:05.837038 Chrome EC: UHEPI supported
554 13:08:05.843272 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 13:08:05.846380 in-header: 03 a9 00 00 08 00 00 00
556 13:08:05.849878 in-data: 84 60 60 08 00 00 00 00
557 13:08:05.852851 MRC: failed to locate region type 0.
558 13:08:05.859589 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 13:08:05.863028 DRAM-K: Running full calibration
560 13:08:05.869926 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 13:08:05.870025 header.status = 0x0
562 13:08:05.872887 header.version = 0x6 (expected: 0x6)
563 13:08:05.876673 header.size = 0xd00 (expected: 0xd00)
564 13:08:05.879692 header.flags = 0x0
565 13:08:05.886678 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 13:08:05.903238 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
567 13:08:05.910127 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 13:08:05.913150 dram_init: ddr_geometry: 2
569 13:08:05.913252 [EMI] MDL number = 2
570 13:08:05.916434 [EMI] Get MDL freq = 0
571 13:08:05.919897 dram_init: ddr_type: 0
572 13:08:05.920019 is_discrete_lpddr4: 1
573 13:08:05.923207 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 13:08:05.923329
575 13:08:05.923422
576 13:08:05.926256 [Bian_co] ETT version 0.0.0.1
577 13:08:05.933275 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 13:08:05.933436
579 13:08:05.936971 dramc_set_vcore_voltage set vcore to 650000
580 13:08:05.937216 Read voltage for 800, 4
581 13:08:05.940165 Vio18 = 0
582 13:08:05.940359 Vcore = 650000
583 13:08:05.940574 Vdram = 0
584 13:08:05.943146 Vddq = 0
585 13:08:05.943399 Vmddr = 0
586 13:08:05.947241 dram_init: config_dvfs: 1
587 13:08:05.950647 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 13:08:05.957227 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 13:08:05.960052 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 13:08:05.963687 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 13:08:05.967226 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 13:08:05.970012 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 13:08:05.973652 MEM_TYPE=3, freq_sel=18
594 13:08:05.977254 sv_algorithm_assistance_LP4_1600
595 13:08:05.980509 ============ PULL DRAM RESETB DOWN ============
596 13:08:05.983871 ========== PULL DRAM RESETB DOWN end =========
597 13:08:05.990322 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 13:08:05.994046 ===================================
599 13:08:05.994714 LPDDR4 DRAM CONFIGURATION
600 13:08:05.996686 ===================================
601 13:08:06.000132 EX_ROW_EN[0] = 0x0
602 13:08:06.003732 EX_ROW_EN[1] = 0x0
603 13:08:06.004150 LP4Y_EN = 0x0
604 13:08:06.006923 WORK_FSP = 0x0
605 13:08:06.007515 WL = 0x2
606 13:08:06.010152 RL = 0x2
607 13:08:06.010674 BL = 0x2
608 13:08:06.013687 RPST = 0x0
609 13:08:06.014281 RD_PRE = 0x0
610 13:08:06.016940 WR_PRE = 0x1
611 13:08:06.017346 WR_PST = 0x0
612 13:08:06.020209 DBI_WR = 0x0
613 13:08:06.020610 DBI_RD = 0x0
614 13:08:06.024072 OTF = 0x1
615 13:08:06.027143 ===================================
616 13:08:06.030746 ===================================
617 13:08:06.031267 ANA top config
618 13:08:06.034010 ===================================
619 13:08:06.036905 DLL_ASYNC_EN = 0
620 13:08:06.040413 ALL_SLAVE_EN = 1
621 13:08:06.040805 NEW_RANK_MODE = 1
622 13:08:06.043475 DLL_IDLE_MODE = 1
623 13:08:06.046979 LP45_APHY_COMB_EN = 1
624 13:08:06.050168 TX_ODT_DIS = 1
625 13:08:06.053993 NEW_8X_MODE = 1
626 13:08:06.057111 ===================================
627 13:08:06.060145 ===================================
628 13:08:06.060533 data_rate = 1600
629 13:08:06.063833 CKR = 1
630 13:08:06.066569 DQ_P2S_RATIO = 8
631 13:08:06.070077 ===================================
632 13:08:06.073757 CA_P2S_RATIO = 8
633 13:08:06.076856 DQ_CA_OPEN = 0
634 13:08:06.080233 DQ_SEMI_OPEN = 0
635 13:08:06.080739 CA_SEMI_OPEN = 0
636 13:08:06.083738 CA_FULL_RATE = 0
637 13:08:06.086952 DQ_CKDIV4_EN = 1
638 13:08:06.090520 CA_CKDIV4_EN = 1
639 13:08:06.093508 CA_PREDIV_EN = 0
640 13:08:06.097075 PH8_DLY = 0
641 13:08:06.097455 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 13:08:06.100497 DQ_AAMCK_DIV = 4
643 13:08:06.103679 CA_AAMCK_DIV = 4
644 13:08:06.106759 CA_ADMCK_DIV = 4
645 13:08:06.110294 DQ_TRACK_CA_EN = 0
646 13:08:06.113644 CA_PICK = 800
647 13:08:06.114027 CA_MCKIO = 800
648 13:08:06.117158 MCKIO_SEMI = 0
649 13:08:06.120210 PLL_FREQ = 3068
650 13:08:06.123542 DQ_UI_PI_RATIO = 32
651 13:08:06.126955 CA_UI_PI_RATIO = 0
652 13:08:06.130044 ===================================
653 13:08:06.133891 ===================================
654 13:08:06.136891 memory_type:LPDDR4
655 13:08:06.137282 GP_NUM : 10
656 13:08:06.140051 SRAM_EN : 1
657 13:08:06.140461 MD32_EN : 0
658 13:08:06.143605 ===================================
659 13:08:06.146873 [ANA_INIT] >>>>>>>>>>>>>>
660 13:08:06.150066 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 13:08:06.153130 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 13:08:06.156837 ===================================
663 13:08:06.159913 data_rate = 1600,PCW = 0X7600
664 13:08:06.163677 ===================================
665 13:08:06.166489 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 13:08:06.169932 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 13:08:06.176986 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 13:08:06.183330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 13:08:06.186637 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 13:08:06.189787 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 13:08:06.190322 [ANA_INIT] flow start
672 13:08:06.193255 [ANA_INIT] PLL >>>>>>>>
673 13:08:06.196830 [ANA_INIT] PLL <<<<<<<<
674 13:08:06.197214 [ANA_INIT] MIDPI >>>>>>>>
675 13:08:06.199735 [ANA_INIT] MIDPI <<<<<<<<
676 13:08:06.203349 [ANA_INIT] DLL >>>>>>>>
677 13:08:06.203765 [ANA_INIT] flow end
678 13:08:06.207052 ============ LP4 DIFF to SE enter ============
679 13:08:06.213319 ============ LP4 DIFF to SE exit ============
680 13:08:06.213707 [ANA_INIT] <<<<<<<<<<<<<
681 13:08:06.217058 [Flow] Enable top DCM control >>>>>
682 13:08:06.220209 [Flow] Enable top DCM control <<<<<
683 13:08:06.223404 Enable DLL master slave shuffle
684 13:08:06.229989 ==============================================================
685 13:08:06.230341 Gating Mode config
686 13:08:06.236596 ==============================================================
687 13:08:06.239875 Config description:
688 13:08:06.249977 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 13:08:06.253373 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 13:08:06.259959 SELPH_MODE 0: By rank 1: By Phase
691 13:08:06.266427 ==============================================================
692 13:08:06.266502 GAT_TRACK_EN = 1
693 13:08:06.270252 RX_GATING_MODE = 2
694 13:08:06.273640 RX_GATING_TRACK_MODE = 2
695 13:08:06.276734 SELPH_MODE = 1
696 13:08:06.279823 PICG_EARLY_EN = 1
697 13:08:06.283275 VALID_LAT_VALUE = 1
698 13:08:06.290696 ==============================================================
699 13:08:06.293550 Enter into Gating configuration >>>>
700 13:08:06.296868 Exit from Gating configuration <<<<
701 13:08:06.300225 Enter into DVFS_PRE_config >>>>>
702 13:08:06.309818 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 13:08:06.313452 Exit from DVFS_PRE_config <<<<<
704 13:08:06.316764 Enter into PICG configuration >>>>
705 13:08:06.320122 Exit from PICG configuration <<<<
706 13:08:06.323722 [RX_INPUT] configuration >>>>>
707 13:08:06.323795 [RX_INPUT] configuration <<<<<
708 13:08:06.329965 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 13:08:06.336806 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 13:08:06.339859 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 13:08:06.346661 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 13:08:06.353549 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 13:08:06.360037 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 13:08:06.363321 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 13:08:06.366822 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 13:08:06.373914 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 13:08:06.377088 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 13:08:06.380343 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 13:08:06.383791 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 13:08:06.387494 ===================================
721 13:08:06.390346 LPDDR4 DRAM CONFIGURATION
722 13:08:06.393860 ===================================
723 13:08:06.397194 EX_ROW_EN[0] = 0x0
724 13:08:06.397268 EX_ROW_EN[1] = 0x0
725 13:08:06.400184 LP4Y_EN = 0x0
726 13:08:06.400258 WORK_FSP = 0x0
727 13:08:06.403570 WL = 0x2
728 13:08:06.403645 RL = 0x2
729 13:08:06.406962 BL = 0x2
730 13:08:06.407047 RPST = 0x0
731 13:08:06.410380 RD_PRE = 0x0
732 13:08:06.410454 WR_PRE = 0x1
733 13:08:06.413703 WR_PST = 0x0
734 13:08:06.413776 DBI_WR = 0x0
735 13:08:06.416883 DBI_RD = 0x0
736 13:08:06.416957 OTF = 0x1
737 13:08:06.420196 ===================================
738 13:08:06.427145 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 13:08:06.430548 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 13:08:06.433745 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 13:08:06.437175 ===================================
742 13:08:06.440097 LPDDR4 DRAM CONFIGURATION
743 13:08:06.443603 ===================================
744 13:08:06.443677 EX_ROW_EN[0] = 0x10
745 13:08:06.447355 EX_ROW_EN[1] = 0x0
746 13:08:06.450359 LP4Y_EN = 0x0
747 13:08:06.450434 WORK_FSP = 0x0
748 13:08:06.453449 WL = 0x2
749 13:08:06.453522 RL = 0x2
750 13:08:06.457859 BL = 0x2
751 13:08:06.457934 RPST = 0x0
752 13:08:06.461135 RD_PRE = 0x0
753 13:08:06.461208 WR_PRE = 0x1
754 13:08:06.464586 WR_PST = 0x0
755 13:08:06.464660 DBI_WR = 0x0
756 13:08:06.468098 DBI_RD = 0x0
757 13:08:06.468172 OTF = 0x1
758 13:08:06.471928 ===================================
759 13:08:06.479449 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 13:08:06.482850 nWR fixed to 40
761 13:08:06.482936 [ModeRegInit_LP4] CH0 RK0
762 13:08:06.486543 [ModeRegInit_LP4] CH0 RK1
763 13:08:06.486636 [ModeRegInit_LP4] CH1 RK0
764 13:08:06.489777 [ModeRegInit_LP4] CH1 RK1
765 13:08:06.493581 match AC timing 13
766 13:08:06.496836 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 13:08:06.500466 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 13:08:06.503759 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 13:08:06.510131 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 13:08:06.514033 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 13:08:06.517464 [EMI DOE] emi_dcm 0
772 13:08:06.520417 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 13:08:06.520688 ==
774 13:08:06.523899 Dram Type= 6, Freq= 0, CH_0, rank 0
775 13:08:06.527576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 13:08:06.527826 ==
777 13:08:06.534090 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 13:08:06.540428 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 13:08:06.549197 [CA 0] Center 38 (7~69) winsize 63
780 13:08:06.552342 [CA 1] Center 37 (7~68) winsize 62
781 13:08:06.556058 [CA 2] Center 35 (5~66) winsize 62
782 13:08:06.559177 [CA 3] Center 35 (5~66) winsize 62
783 13:08:06.562349 [CA 4] Center 34 (4~65) winsize 62
784 13:08:06.565719 [CA 5] Center 34 (3~65) winsize 63
785 13:08:06.566335
786 13:08:06.569361 [CmdBusTrainingLP45] Vref(ca) range 1: 34
787 13:08:06.569747
788 13:08:06.572452 [CATrainingPosCal] consider 1 rank data
789 13:08:06.576059 u2DelayCellTimex100 = 270/100 ps
790 13:08:06.579406 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
791 13:08:06.582286 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
792 13:08:06.589553 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
793 13:08:06.592051 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
794 13:08:06.595730 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
795 13:08:06.598799 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
796 13:08:06.599183
797 13:08:06.602389 CA PerBit enable=1, Macro0, CA PI delay=34
798 13:08:06.602772
799 13:08:06.606706 [CBTSetCACLKResult] CA Dly = 34
800 13:08:06.607177 CS Dly: 6 (0~37)
801 13:08:06.607559 ==
802 13:08:06.609644 Dram Type= 6, Freq= 0, CH_0, rank 1
803 13:08:06.613334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 13:08:06.616110 ==
805 13:08:06.619658 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 13:08:06.626418 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 13:08:06.635656 [CA 0] Center 38 (7~69) winsize 63
808 13:08:06.639071 [CA 1] Center 37 (7~68) winsize 62
809 13:08:06.642071 [CA 2] Center 35 (5~66) winsize 62
810 13:08:06.645538 [CA 3] Center 35 (5~66) winsize 62
811 13:08:06.649046 [CA 4] Center 34 (4~65) winsize 62
812 13:08:06.652136 [CA 5] Center 34 (3~65) winsize 63
813 13:08:06.652585
814 13:08:06.655883 [CmdBusTrainingLP45] Vref(ca) range 1: 34
815 13:08:06.656340
816 13:08:06.658830 [CATrainingPosCal] consider 2 rank data
817 13:08:06.662414 u2DelayCellTimex100 = 270/100 ps
818 13:08:06.665528 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 13:08:06.669116 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
820 13:08:06.675536 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 13:08:06.679154 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 13:08:06.682401 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 13:08:06.685586 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
824 13:08:06.685998
825 13:08:06.688767 CA PerBit enable=1, Macro0, CA PI delay=34
826 13:08:06.689166
827 13:08:06.692590 [CBTSetCACLKResult] CA Dly = 34
828 13:08:06.693002 CS Dly: 6 (0~37)
829 13:08:06.693315
830 13:08:06.696067 ----->DramcWriteLeveling(PI) begin...
831 13:08:06.698540 ==
832 13:08:06.698947 Dram Type= 6, Freq= 0, CH_0, rank 0
833 13:08:06.705793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 13:08:06.706238 ==
835 13:08:06.708886 Write leveling (Byte 0): 32 => 32
836 13:08:06.712157 Write leveling (Byte 1): 32 => 32
837 13:08:06.712700 DramcWriteLeveling(PI) end<-----
838 13:08:06.715242
839 13:08:06.715655 ==
840 13:08:06.718547 Dram Type= 6, Freq= 0, CH_0, rank 0
841 13:08:06.722430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 13:08:06.722843 ==
843 13:08:06.725752 [Gating] SW mode calibration
844 13:08:06.732374 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 13:08:06.735572 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 13:08:06.742567 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 13:08:06.745810 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 13:08:06.749051 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
849 13:08:06.755602 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
850 13:08:06.758840 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 13:08:06.762236 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 13:08:06.769186 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 13:08:06.772191 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 13:08:06.775405 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 13:08:06.782295 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 13:08:06.785326 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 13:08:06.789218 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 13:08:06.792337 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 13:08:06.799016 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 13:08:06.802492 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 13:08:06.805662 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 13:08:06.812352 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 13:08:06.815633 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
864 13:08:06.818915 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
865 13:08:06.825943 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 13:08:06.828963 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 13:08:06.832445 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 13:08:06.839085 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 13:08:06.842210 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 13:08:06.845805 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 13:08:06.852809 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 13:08:06.855637 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 13:08:06.859422 0 9 12 | B1->B0 | 2c2c 3434 | 0 0 | (0 0) (0 0)
874 13:08:06.862653 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 13:08:06.869066 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 13:08:06.872411 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 13:08:06.875820 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 13:08:06.882591 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 13:08:06.885941 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 13:08:06.889563 0 10 8 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 1)
881 13:08:06.896319 0 10 12 | B1->B0 | 3030 2424 | 0 0 | (0 1) (0 0)
882 13:08:06.899378 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 13:08:06.902434 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 13:08:06.909299 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 13:08:06.912467 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 13:08:06.916035 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 13:08:06.922564 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 13:08:06.926061 0 11 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
889 13:08:06.929331 0 11 12 | B1->B0 | 3535 4242 | 1 0 | (0 0) (0 0)
890 13:08:06.936006 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 13:08:06.939246 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 13:08:06.942649 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 13:08:06.949447 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 13:08:06.952365 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 13:08:06.955985 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 13:08:06.958909 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
897 13:08:06.965794 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
898 13:08:06.969328 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 13:08:06.972916 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 13:08:06.979828 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 13:08:06.982626 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 13:08:06.986274 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 13:08:06.992887 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 13:08:06.996022 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 13:08:06.999345 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 13:08:07.006293 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 13:08:07.009267 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 13:08:07.012782 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 13:08:07.019318 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 13:08:07.022813 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 13:08:07.025908 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 13:08:07.032476 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
913 13:08:07.036358 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
914 13:08:07.040001 Total UI for P1: 0, mck2ui 16
915 13:08:07.043626 best dqsien dly found for B0: ( 0, 14, 8)
916 13:08:07.046408 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
917 13:08:07.050219 Total UI for P1: 0, mck2ui 16
918 13:08:07.053373 best dqsien dly found for B1: ( 0, 14, 12)
919 13:08:07.056941 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
920 13:08:07.060239 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
921 13:08:07.060802
922 13:08:07.063141 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
923 13:08:07.066920 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
924 13:08:07.069720 [Gating] SW calibration Done
925 13:08:07.070295 ==
926 13:08:07.073157 Dram Type= 6, Freq= 0, CH_0, rank 0
927 13:08:07.076901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 13:08:07.079863 ==
929 13:08:07.080426 RX Vref Scan: 0
930 13:08:07.080763
931 13:08:07.083436 RX Vref 0 -> 0, step: 1
932 13:08:07.083974
933 13:08:07.086876 RX Delay -130 -> 252, step: 16
934 13:08:07.089787 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
935 13:08:07.093379 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
936 13:08:07.096791 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
937 13:08:07.100339 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
938 13:08:07.103135 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
939 13:08:07.110035 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
940 13:08:07.113390 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
941 13:08:07.116522 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
942 13:08:07.120055 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
943 13:08:07.123231 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
944 13:08:07.129957 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
945 13:08:07.133125 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
946 13:08:07.136646 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
947 13:08:07.140126 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
948 13:08:07.146541 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
949 13:08:07.149561 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
950 13:08:07.149956 ==
951 13:08:07.153134 Dram Type= 6, Freq= 0, CH_0, rank 0
952 13:08:07.156359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 13:08:07.156750 ==
954 13:08:07.157048 DQS Delay:
955 13:08:07.159909 DQS0 = 0, DQS1 = 0
956 13:08:07.160297 DQM Delay:
957 13:08:07.163254 DQM0 = 83, DQM1 = 70
958 13:08:07.163638 DQ Delay:
959 13:08:07.166939 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
960 13:08:07.169993 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
961 13:08:07.173089 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
962 13:08:07.176768 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
963 13:08:07.177152
964 13:08:07.177447
965 13:08:07.177719 ==
966 13:08:07.179956 Dram Type= 6, Freq= 0, CH_0, rank 0
967 13:08:07.183585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 13:08:07.186635 ==
969 13:08:07.187021
970 13:08:07.187316
971 13:08:07.187593 TX Vref Scan disable
972 13:08:07.190449 == TX Byte 0 ==
973 13:08:07.193732 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
974 13:08:07.196615 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
975 13:08:07.200335 == TX Byte 1 ==
976 13:08:07.203662 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
977 13:08:07.206859 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
978 13:08:07.207250 ==
979 13:08:07.209758 Dram Type= 6, Freq= 0, CH_0, rank 0
980 13:08:07.216662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 13:08:07.217053 ==
982 13:08:07.228400 TX Vref=22, minBit 14, minWin=26, winSum=437
983 13:08:07.231686 TX Vref=24, minBit 1, minWin=27, winSum=442
984 13:08:07.234929 TX Vref=26, minBit 7, minWin=27, winSum=442
985 13:08:07.238606 TX Vref=28, minBit 0, minWin=27, winSum=442
986 13:08:07.241845 TX Vref=30, minBit 9, minWin=27, winSum=442
987 13:08:07.245224 TX Vref=32, minBit 2, minWin=27, winSum=443
988 13:08:07.252064 [TxChooseVref] Worse bit 2, Min win 27, Win sum 443, Final Vref 32
989 13:08:07.252455
990 13:08:07.255668 Final TX Range 1 Vref 32
991 13:08:07.256049
992 13:08:07.256341 ==
993 13:08:07.258557 Dram Type= 6, Freq= 0, CH_0, rank 0
994 13:08:07.262189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
995 13:08:07.262580 ==
996 13:08:07.262881
997 13:08:07.265240
998 13:08:07.265625 TX Vref Scan disable
999 13:08:07.268298 == TX Byte 0 ==
1000 13:08:07.272156 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1001 13:08:07.275460 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1002 13:08:07.278367 == TX Byte 1 ==
1003 13:08:07.282084 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1004 13:08:07.285072 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1005 13:08:07.288319
1006 13:08:07.288700 [DATLAT]
1007 13:08:07.288999 Freq=800, CH0 RK0
1008 13:08:07.289277
1009 13:08:07.291901 DATLAT Default: 0xa
1010 13:08:07.292395 0, 0xFFFF, sum = 0
1011 13:08:07.295152 1, 0xFFFF, sum = 0
1012 13:08:07.295539 2, 0xFFFF, sum = 0
1013 13:08:07.298633 3, 0xFFFF, sum = 0
1014 13:08:07.299025 4, 0xFFFF, sum = 0
1015 13:08:07.302184 5, 0xFFFF, sum = 0
1016 13:08:07.302579 6, 0xFFFF, sum = 0
1017 13:08:07.305035 7, 0xFFFF, sum = 0
1018 13:08:07.308440 8, 0xFFFF, sum = 0
1019 13:08:07.308835 9, 0x0, sum = 1
1020 13:08:07.309137 10, 0x0, sum = 2
1021 13:08:07.311580 11, 0x0, sum = 3
1022 13:08:07.311976 12, 0x0, sum = 4
1023 13:08:07.315005 best_step = 10
1024 13:08:07.315444
1025 13:08:07.315749 ==
1026 13:08:07.318451 Dram Type= 6, Freq= 0, CH_0, rank 0
1027 13:08:07.321832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1028 13:08:07.322399 ==
1029 13:08:07.324808 RX Vref Scan: 1
1030 13:08:07.325210
1031 13:08:07.325525 Set Vref Range= 32 -> 127
1032 13:08:07.325820
1033 13:08:07.328450 RX Vref 32 -> 127, step: 1
1034 13:08:07.328868
1035 13:08:07.332166 RX Delay -111 -> 252, step: 8
1036 13:08:07.332574
1037 13:08:07.335200 Set Vref, RX VrefLevel [Byte0]: 32
1038 13:08:07.338678 [Byte1]: 32
1039 13:08:07.339092
1040 13:08:07.341692 Set Vref, RX VrefLevel [Byte0]: 33
1041 13:08:07.345026 [Byte1]: 33
1042 13:08:07.348776
1043 13:08:07.349176 Set Vref, RX VrefLevel [Byte0]: 34
1044 13:08:07.352260 [Byte1]: 34
1045 13:08:07.356481
1046 13:08:07.356901 Set Vref, RX VrefLevel [Byte0]: 35
1047 13:08:07.359818 [Byte1]: 35
1048 13:08:07.364328
1049 13:08:07.364814 Set Vref, RX VrefLevel [Byte0]: 36
1050 13:08:07.367381 [Byte1]: 36
1051 13:08:07.371953
1052 13:08:07.372490 Set Vref, RX VrefLevel [Byte0]: 37
1053 13:08:07.375003 [Byte1]: 37
1054 13:08:07.379223
1055 13:08:07.379759 Set Vref, RX VrefLevel [Byte0]: 38
1056 13:08:07.382981 [Byte1]: 38
1057 13:08:07.387044
1058 13:08:07.387464 Set Vref, RX VrefLevel [Byte0]: 39
1059 13:08:07.390154 [Byte1]: 39
1060 13:08:07.395213
1061 13:08:07.395617 Set Vref, RX VrefLevel [Byte0]: 40
1062 13:08:07.397932 [Byte1]: 40
1063 13:08:07.402423
1064 13:08:07.402977 Set Vref, RX VrefLevel [Byte0]: 41
1065 13:08:07.406171 [Byte1]: 41
1066 13:08:07.409765
1067 13:08:07.410326 Set Vref, RX VrefLevel [Byte0]: 42
1068 13:08:07.413167 [Byte1]: 42
1069 13:08:07.417927
1070 13:08:07.418380 Set Vref, RX VrefLevel [Byte0]: 43
1071 13:08:07.420889 [Byte1]: 43
1072 13:08:07.425240
1073 13:08:07.425645 Set Vref, RX VrefLevel [Byte0]: 44
1074 13:08:07.428607 [Byte1]: 44
1075 13:08:07.433201
1076 13:08:07.433583 Set Vref, RX VrefLevel [Byte0]: 45
1077 13:08:07.436231 [Byte1]: 45
1078 13:08:07.440619
1079 13:08:07.441026 Set Vref, RX VrefLevel [Byte0]: 46
1080 13:08:07.444077 [Byte1]: 46
1081 13:08:07.448745
1082 13:08:07.449187 Set Vref, RX VrefLevel [Byte0]: 47
1083 13:08:07.451558 [Byte1]: 47
1084 13:08:07.456074
1085 13:08:07.456629 Set Vref, RX VrefLevel [Byte0]: 48
1086 13:08:07.459069 [Byte1]: 48
1087 13:08:07.463601
1088 13:08:07.464000 Set Vref, RX VrefLevel [Byte0]: 49
1089 13:08:07.466679 [Byte1]: 49
1090 13:08:07.471367
1091 13:08:07.471854 Set Vref, RX VrefLevel [Byte0]: 50
1092 13:08:07.474949 [Byte1]: 50
1093 13:08:07.479223
1094 13:08:07.479630 Set Vref, RX VrefLevel [Byte0]: 51
1095 13:08:07.482281 [Byte1]: 51
1096 13:08:07.486682
1097 13:08:07.487102 Set Vref, RX VrefLevel [Byte0]: 52
1098 13:08:07.490079 [Byte1]: 52
1099 13:08:07.494134
1100 13:08:07.494540 Set Vref, RX VrefLevel [Byte0]: 53
1101 13:08:07.497257 [Byte1]: 53
1102 13:08:07.501626
1103 13:08:07.502011 Set Vref, RX VrefLevel [Byte0]: 54
1104 13:08:07.505258 [Byte1]: 54
1105 13:08:07.509709
1106 13:08:07.510095 Set Vref, RX VrefLevel [Byte0]: 55
1107 13:08:07.512462 [Byte1]: 55
1108 13:08:07.516791
1109 13:08:07.517180 Set Vref, RX VrefLevel [Byte0]: 56
1110 13:08:07.520293 [Byte1]: 56
1111 13:08:07.524381
1112 13:08:07.524935 Set Vref, RX VrefLevel [Byte0]: 57
1113 13:08:07.528106 [Byte1]: 57
1114 13:08:07.532226
1115 13:08:07.532634 Set Vref, RX VrefLevel [Byte0]: 58
1116 13:08:07.535613 [Byte1]: 58
1117 13:08:07.539807
1118 13:08:07.540220 Set Vref, RX VrefLevel [Byte0]: 59
1119 13:08:07.543463 [Byte1]: 59
1120 13:08:07.547842
1121 13:08:07.548255 Set Vref, RX VrefLevel [Byte0]: 60
1122 13:08:07.550918 [Byte1]: 60
1123 13:08:07.555039
1124 13:08:07.555451 Set Vref, RX VrefLevel [Byte0]: 61
1125 13:08:07.559052 [Byte1]: 61
1126 13:08:07.562742
1127 13:08:07.563162 Set Vref, RX VrefLevel [Byte0]: 62
1128 13:08:07.566368 [Byte1]: 62
1129 13:08:07.570620
1130 13:08:07.571027 Set Vref, RX VrefLevel [Byte0]: 63
1131 13:08:07.574083 [Byte1]: 63
1132 13:08:07.578383
1133 13:08:07.578765 Set Vref, RX VrefLevel [Byte0]: 64
1134 13:08:07.581407 [Byte1]: 64
1135 13:08:07.585900
1136 13:08:07.586356 Set Vref, RX VrefLevel [Byte0]: 65
1137 13:08:07.589436 [Byte1]: 65
1138 13:08:07.593487
1139 13:08:07.594055 Set Vref, RX VrefLevel [Byte0]: 66
1140 13:08:07.596574 [Byte1]: 66
1141 13:08:07.601064
1142 13:08:07.601449 Set Vref, RX VrefLevel [Byte0]: 67
1143 13:08:07.607463 [Byte1]: 67
1144 13:08:07.607902
1145 13:08:07.611339 Set Vref, RX VrefLevel [Byte0]: 68
1146 13:08:07.614050 [Byte1]: 68
1147 13:08:07.614503
1148 13:08:07.617446 Set Vref, RX VrefLevel [Byte0]: 69
1149 13:08:07.620961 [Byte1]: 69
1150 13:08:07.624174
1151 13:08:07.624562 Set Vref, RX VrefLevel [Byte0]: 70
1152 13:08:07.627108 [Byte1]: 70
1153 13:08:07.631595
1154 13:08:07.631981 Set Vref, RX VrefLevel [Byte0]: 71
1155 13:08:07.634875 [Byte1]: 71
1156 13:08:07.639104
1157 13:08:07.639548 Set Vref, RX VrefLevel [Byte0]: 72
1158 13:08:07.642787 [Byte1]: 72
1159 13:08:07.646856
1160 13:08:07.647255 Set Vref, RX VrefLevel [Byte0]: 73
1161 13:08:07.650093 [Byte1]: 73
1162 13:08:07.655006
1163 13:08:07.655467 Set Vref, RX VrefLevel [Byte0]: 74
1164 13:08:07.657874 [Byte1]: 74
1165 13:08:07.662392
1166 13:08:07.662850 Set Vref, RX VrefLevel [Byte0]: 75
1167 13:08:07.665887 [Byte1]: 75
1168 13:08:07.670209
1169 13:08:07.670610 Set Vref, RX VrefLevel [Byte0]: 76
1170 13:08:07.673085 [Byte1]: 76
1171 13:08:07.677924
1172 13:08:07.678360 Set Vref, RX VrefLevel [Byte0]: 77
1173 13:08:07.680918 [Byte1]: 77
1174 13:08:07.685028
1175 13:08:07.685462 Set Vref, RX VrefLevel [Byte0]: 78
1176 13:08:07.688768 [Byte1]: 78
1177 13:08:07.692909
1178 13:08:07.693531 Set Vref, RX VrefLevel [Byte0]: 79
1179 13:08:07.696168 [Byte1]: 79
1180 13:08:07.700755
1181 13:08:07.701176 Final RX Vref Byte 0 = 59 to rank0
1182 13:08:07.703949 Final RX Vref Byte 1 = 54 to rank0
1183 13:08:07.707436 Final RX Vref Byte 0 = 59 to rank1
1184 13:08:07.710991 Final RX Vref Byte 1 = 54 to rank1==
1185 13:08:07.713889 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 13:08:07.720671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 13:08:07.721077 ==
1188 13:08:07.721472 DQS Delay:
1189 13:08:07.721841 DQS0 = 0, DQS1 = 0
1190 13:08:07.723837 DQM Delay:
1191 13:08:07.724232 DQM0 = 82, DQM1 = 67
1192 13:08:07.727248 DQ Delay:
1193 13:08:07.730423 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1194 13:08:07.730832 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1195 13:08:07.734084 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1196 13:08:07.737383 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1197 13:08:07.740922
1198 13:08:07.741319
1199 13:08:07.747151 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e2d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
1200 13:08:07.750666 CH0 RK0: MR19=606, MR18=2E2D
1201 13:08:07.757232 CH0_RK0: MR19=0x606, MR18=0x2E2D, DQSOSC=398, MR23=63, INC=93, DEC=62
1202 13:08:07.757637
1203 13:08:07.760433 ----->DramcWriteLeveling(PI) begin...
1204 13:08:07.760837 ==
1205 13:08:07.763752 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 13:08:07.767579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 13:08:07.768108 ==
1208 13:08:07.770599 Write leveling (Byte 0): 32 => 32
1209 13:08:07.774224 Write leveling (Byte 1): 30 => 30
1210 13:08:07.777341 DramcWriteLeveling(PI) end<-----
1211 13:08:07.777724
1212 13:08:07.778022 ==
1213 13:08:07.780989 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 13:08:07.784385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 13:08:07.784817 ==
1216 13:08:07.787144 [Gating] SW mode calibration
1217 13:08:07.793726 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 13:08:07.800665 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 13:08:07.803784 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1220 13:08:07.807539 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1221 13:08:07.813961 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1222 13:08:07.817143 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 13:08:07.820735 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 13:08:07.827488 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 13:08:07.830353 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 13:08:07.834191 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 13:08:07.881038 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 13:08:07.881573 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 13:08:07.882031 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 13:08:07.882801 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 13:08:07.883216 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 13:08:07.883646 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 13:08:07.884051 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 13:08:07.884362 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 13:08:07.884647 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 13:08:07.884920 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 13:08:07.885195 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1238 13:08:07.886582 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 13:08:07.893239 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 13:08:07.896713 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 13:08:07.900163 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 13:08:07.903222 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 13:08:07.909816 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 13:08:07.913619 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 13:08:07.916803 0 9 8 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
1246 13:08:07.923459 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 13:08:07.927014 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 13:08:07.930072 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 13:08:07.936618 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 13:08:07.940310 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 13:08:07.943735 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 13:08:07.949959 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
1253 13:08:07.953684 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (1 0)
1254 13:08:07.957154 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1255 13:08:07.963717 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 13:08:07.967060 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 13:08:07.969998 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 13:08:07.976815 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 13:08:07.980747 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 13:08:07.984098 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1261 13:08:07.986899 0 11 8 | B1->B0 | 3939 3d3d | 0 1 | (0 0) (0 0)
1262 13:08:07.993428 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 13:08:07.997044 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 13:08:07.999819 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 13:08:08.006641 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 13:08:08.009729 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 13:08:08.013370 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 13:08:08.019969 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1269 13:08:08.023252 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1270 13:08:08.026780 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 13:08:08.032937 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 13:08:08.036864 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 13:08:08.039760 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 13:08:08.046349 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 13:08:08.049798 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 13:08:08.053014 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 13:08:08.059718 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 13:08:08.063153 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 13:08:08.066172 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 13:08:08.072770 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 13:08:08.076534 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 13:08:08.079610 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 13:08:08.082875 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 13:08:08.089905 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 13:08:08.093342 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1286 13:08:08.096273 Total UI for P1: 0, mck2ui 16
1287 13:08:08.099766 best dqsien dly found for B0: ( 0, 14, 6)
1288 13:08:08.103322 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1289 13:08:08.106192 Total UI for P1: 0, mck2ui 16
1290 13:08:08.109912 best dqsien dly found for B1: ( 0, 14, 8)
1291 13:08:08.112871 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1292 13:08:08.116612 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1293 13:08:08.116719
1294 13:08:08.122692 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1295 13:08:08.126116 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1296 13:08:08.126240 [Gating] SW calibration Done
1297 13:08:08.129543 ==
1298 13:08:08.132915 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 13:08:08.136318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 13:08:08.136416 ==
1301 13:08:08.136502 RX Vref Scan: 0
1302 13:08:08.136595
1303 13:08:08.139712 RX Vref 0 -> 0, step: 1
1304 13:08:08.139812
1305 13:08:08.143521 RX Delay -130 -> 252, step: 16
1306 13:08:08.146603 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1307 13:08:08.149715 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1308 13:08:08.153221 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1309 13:08:08.160441 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1310 13:08:08.163317 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1311 13:08:08.166840 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1312 13:08:08.169759 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1313 13:08:08.172926 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1314 13:08:08.179551 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1315 13:08:08.183132 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1316 13:08:08.186346 iDelay=206, Bit 10, Center 61 (-66 ~ 189) 256
1317 13:08:08.189714 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1318 13:08:08.192830 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1319 13:08:08.199694 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1320 13:08:08.203375 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1321 13:08:08.206905 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1322 13:08:08.206973 ==
1323 13:08:08.210003 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 13:08:08.212956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 13:08:08.213035 ==
1326 13:08:08.216182 DQS Delay:
1327 13:08:08.216274 DQS0 = 0, DQS1 = 0
1328 13:08:08.219919 DQM Delay:
1329 13:08:08.220014 DQM0 = 75, DQM1 = 68
1330 13:08:08.220098 DQ Delay:
1331 13:08:08.223023 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1332 13:08:08.226582 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =85
1333 13:08:08.229980 DQ8 =61, DQ9 =53, DQ10 =61, DQ11 =61
1334 13:08:08.233071 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1335 13:08:08.233199
1336 13:08:08.233272
1337 13:08:08.236626 ==
1338 13:08:08.239553 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 13:08:08.243078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 13:08:08.243145 ==
1341 13:08:08.243201
1342 13:08:08.243253
1343 13:08:08.246471 TX Vref Scan disable
1344 13:08:08.246538 == TX Byte 0 ==
1345 13:08:08.250035 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1346 13:08:08.256720 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1347 13:08:08.256788 == TX Byte 1 ==
1348 13:08:08.259762 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1349 13:08:08.267079 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1350 13:08:08.267152 ==
1351 13:08:08.269877 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 13:08:08.272883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 13:08:08.272976 ==
1354 13:08:08.286323 TX Vref=22, minBit 0, minWin=27, winSum=435
1355 13:08:08.289911 TX Vref=24, minBit 1, minWin=27, winSum=438
1356 13:08:08.293071 TX Vref=26, minBit 1, minWin=27, winSum=443
1357 13:08:08.296849 TX Vref=28, minBit 1, minWin=27, winSum=441
1358 13:08:08.299877 TX Vref=30, minBit 1, minWin=27, winSum=442
1359 13:08:08.303174 TX Vref=32, minBit 2, minWin=27, winSum=444
1360 13:08:08.309533 [TxChooseVref] Worse bit 2, Min win 27, Win sum 444, Final Vref 32
1361 13:08:08.309630
1362 13:08:08.312952 Final TX Range 1 Vref 32
1363 13:08:08.313037
1364 13:08:08.313131 ==
1365 13:08:08.315999 Dram Type= 6, Freq= 0, CH_0, rank 1
1366 13:08:08.319481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 13:08:08.319585 ==
1368 13:08:08.322727
1369 13:08:08.322806
1370 13:08:08.322865 TX Vref Scan disable
1371 13:08:08.326427 == TX Byte 0 ==
1372 13:08:08.329468 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1373 13:08:08.336105 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1374 13:08:08.336177 == TX Byte 1 ==
1375 13:08:08.339525 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1376 13:08:08.343104 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1377 13:08:08.346610
1378 13:08:08.346680 [DATLAT]
1379 13:08:08.346736 Freq=800, CH0 RK1
1380 13:08:08.346790
1381 13:08:08.349576 DATLAT Default: 0xa
1382 13:08:08.349669 0, 0xFFFF, sum = 0
1383 13:08:08.352902 1, 0xFFFF, sum = 0
1384 13:08:08.352970 2, 0xFFFF, sum = 0
1385 13:08:08.356420 3, 0xFFFF, sum = 0
1386 13:08:08.356517 4, 0xFFFF, sum = 0
1387 13:08:08.359483 5, 0xFFFF, sum = 0
1388 13:08:08.359575 6, 0xFFFF, sum = 0
1389 13:08:08.363312 7, 0xFFFF, sum = 0
1390 13:08:08.366287 8, 0xFFFF, sum = 0
1391 13:08:08.366355 9, 0x0, sum = 1
1392 13:08:08.366410 10, 0x0, sum = 2
1393 13:08:08.370030 11, 0x0, sum = 3
1394 13:08:08.370152 12, 0x0, sum = 4
1395 13:08:08.372894 best_step = 10
1396 13:08:08.372982
1397 13:08:08.373061 ==
1398 13:08:08.376402 Dram Type= 6, Freq= 0, CH_0, rank 1
1399 13:08:08.379937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1400 13:08:08.380003 ==
1401 13:08:08.382934 RX Vref Scan: 0
1402 13:08:08.382998
1403 13:08:08.383051 RX Vref 0 -> 0, step: 1
1404 13:08:08.383104
1405 13:08:08.386269 RX Delay -111 -> 252, step: 8
1406 13:08:08.393018 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1407 13:08:08.396843 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1408 13:08:08.399951 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1409 13:08:08.403192 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1410 13:08:08.406856 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1411 13:08:08.413149 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1412 13:08:08.416423 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1413 13:08:08.419844 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1414 13:08:08.423156 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1415 13:08:08.426754 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1416 13:08:08.433581 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1417 13:08:08.436714 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1418 13:08:08.439781 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1419 13:08:08.443356 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1420 13:08:08.447191 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1421 13:08:08.454015 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1422 13:08:08.454545 ==
1423 13:08:08.456717 Dram Type= 6, Freq= 0, CH_0, rank 1
1424 13:08:08.460198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 13:08:08.460772 ==
1426 13:08:08.461311 DQS Delay:
1427 13:08:08.463688 DQS0 = 0, DQS1 = 0
1428 13:08:08.464112 DQM Delay:
1429 13:08:08.466692 DQM0 = 79, DQM1 = 69
1430 13:08:08.467293 DQ Delay:
1431 13:08:08.470563 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1432 13:08:08.473674 DQ4 =80, DQ5 =64, DQ6 =92, DQ7 =88
1433 13:08:08.476738 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =64
1434 13:08:08.480478 DQ12 =76, DQ13 =72, DQ14 =80, DQ15 =80
1435 13:08:08.480901
1436 13:08:08.481225
1437 13:08:08.486838 [DQSOSCAuto] RK1, (LSB)MR18= 0x4e2a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
1438 13:08:08.490733 CH0 RK1: MR19=606, MR18=4E2A
1439 13:08:08.497292 CH0_RK1: MR19=0x606, MR18=0x4E2A, DQSOSC=390, MR23=63, INC=97, DEC=64
1440 13:08:08.500850 [RxdqsGatingPostProcess] freq 800
1441 13:08:08.507070 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1442 13:08:08.510199 Pre-setting of DQS Precalculation
1443 13:08:08.513740 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1444 13:08:08.514203 ==
1445 13:08:08.517441 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 13:08:08.520490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 13:08:08.520923 ==
1448 13:08:08.526965 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1449 13:08:08.533777 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1450 13:08:08.541951 [CA 0] Center 36 (6~66) winsize 61
1451 13:08:08.545416 [CA 1] Center 36 (6~67) winsize 62
1452 13:08:08.548889 [CA 2] Center 34 (5~64) winsize 60
1453 13:08:08.551790 [CA 3] Center 34 (4~64) winsize 61
1454 13:08:08.555167 [CA 4] Center 34 (5~64) winsize 60
1455 13:08:08.558850 [CA 5] Center 33 (3~64) winsize 62
1456 13:08:08.559283
1457 13:08:08.562035 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1458 13:08:08.562650
1459 13:08:08.565330 [CATrainingPosCal] consider 1 rank data
1460 13:08:08.568369 u2DelayCellTimex100 = 270/100 ps
1461 13:08:08.572346 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1462 13:08:08.574933 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1463 13:08:08.581768 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1464 13:08:08.585303 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1465 13:08:08.588583 CA4 delay=34 (5~64),Diff = 1 PI (7 cell)
1466 13:08:08.592138 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1467 13:08:08.592602
1468 13:08:08.595045 CA PerBit enable=1, Macro0, CA PI delay=33
1469 13:08:08.595477
1470 13:08:08.598786 [CBTSetCACLKResult] CA Dly = 33
1471 13:08:08.599221 CS Dly: 5 (0~36)
1472 13:08:08.599556 ==
1473 13:08:08.601587 Dram Type= 6, Freq= 0, CH_1, rank 1
1474 13:08:08.608568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 13:08:08.609001 ==
1476 13:08:08.611800 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1477 13:08:08.618448 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1478 13:08:08.628045 [CA 0] Center 36 (6~66) winsize 61
1479 13:08:08.631503 [CA 1] Center 36 (6~67) winsize 62
1480 13:08:08.634468 [CA 2] Center 34 (4~65) winsize 62
1481 13:08:08.638193 [CA 3] Center 34 (4~64) winsize 61
1482 13:08:08.641234 [CA 4] Center 34 (4~65) winsize 62
1483 13:08:08.644415 [CA 5] Center 33 (3~64) winsize 62
1484 13:08:08.644813
1485 13:08:08.648301 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1486 13:08:08.648701
1487 13:08:08.651420 [CATrainingPosCal] consider 2 rank data
1488 13:08:08.654634 u2DelayCellTimex100 = 270/100 ps
1489 13:08:08.657945 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1490 13:08:08.661534 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1491 13:08:08.668032 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1492 13:08:08.671708 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1493 13:08:08.674707 CA4 delay=34 (5~64),Diff = 1 PI (7 cell)
1494 13:08:08.678206 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1495 13:08:08.678607
1496 13:08:08.681240 CA PerBit enable=1, Macro0, CA PI delay=33
1497 13:08:08.681782
1498 13:08:08.684592 [CBTSetCACLKResult] CA Dly = 33
1499 13:08:08.685123 CS Dly: 6 (0~38)
1500 13:08:08.685514
1501 13:08:08.688054 ----->DramcWriteLeveling(PI) begin...
1502 13:08:08.691210 ==
1503 13:08:08.691612 Dram Type= 6, Freq= 0, CH_1, rank 0
1504 13:08:08.697850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1505 13:08:08.698304 ==
1506 13:08:08.701334 Write leveling (Byte 0): 28 => 28
1507 13:08:08.704367 Write leveling (Byte 1): 32 => 32
1508 13:08:08.708036 DramcWriteLeveling(PI) end<-----
1509 13:08:08.708423
1510 13:08:08.708719 ==
1511 13:08:08.711172 Dram Type= 6, Freq= 0, CH_1, rank 0
1512 13:08:08.714353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1513 13:08:08.714746 ==
1514 13:08:08.718187 [Gating] SW mode calibration
1515 13:08:08.724964 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1516 13:08:08.727936 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1517 13:08:08.734317 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1518 13:08:08.737898 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1519 13:08:08.741083 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 13:08:08.747760 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 13:08:08.751201 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 13:08:08.754459 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 13:08:08.761293 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 13:08:08.765089 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 13:08:08.768467 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 13:08:08.774924 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 13:08:08.777801 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 13:08:08.781381 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 13:08:08.787835 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 13:08:08.791301 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 13:08:08.794599 0 7 24 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1532 13:08:08.801181 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 13:08:08.804641 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 13:08:08.807966 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1535 13:08:08.811390 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 13:08:08.818030 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 13:08:08.820980 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 13:08:08.824526 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 13:08:08.831481 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 13:08:08.834720 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 13:08:08.837702 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 13:08:08.844832 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 13:08:08.847988 0 9 8 | B1->B0 | 2a2a 2b2b | 0 1 | (0 0) (1 1)
1544 13:08:08.851710 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 13:08:08.858075 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 13:08:08.861361 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 13:08:08.864657 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 13:08:08.870940 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 13:08:08.874987 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 13:08:08.878047 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1551 13:08:08.884507 0 10 8 | B1->B0 | 2e2e 2626 | 0 0 | (0 1) (0 0)
1552 13:08:08.887531 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 13:08:08.891197 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 13:08:08.897703 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 13:08:08.901324 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 13:08:08.904878 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 13:08:08.907893 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 13:08:08.914972 0 11 4 | B1->B0 | 2626 2727 | 0 0 | (0 0) (0 0)
1559 13:08:08.918637 0 11 8 | B1->B0 | 3939 3333 | 0 0 | (0 0) (0 0)
1560 13:08:08.921307 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 13:08:08.927831 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 13:08:08.931148 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 13:08:08.935023 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 13:08:08.941299 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 13:08:08.944227 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 13:08:08.947675 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 13:08:08.954398 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1568 13:08:08.957916 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 13:08:08.961062 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 13:08:08.967497 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 13:08:08.970911 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 13:08:08.974193 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 13:08:08.980656 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 13:08:08.983885 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 13:08:08.987292 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 13:08:08.994022 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 13:08:08.997697 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 13:08:09.000609 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 13:08:09.007234 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 13:08:09.010792 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 13:08:09.013572 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 13:08:09.020690 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1583 13:08:09.023718 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1584 13:08:09.027118 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1585 13:08:09.030591 Total UI for P1: 0, mck2ui 16
1586 13:08:09.033796 best dqsien dly found for B0: ( 0, 14, 6)
1587 13:08:09.037824 Total UI for P1: 0, mck2ui 16
1588 13:08:09.040567 best dqsien dly found for B1: ( 0, 14, 8)
1589 13:08:09.044114 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1590 13:08:09.047044 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1591 13:08:09.047436
1592 13:08:09.050437 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1593 13:08:09.057391 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1594 13:08:09.057800 [Gating] SW calibration Done
1595 13:08:09.058230 ==
1596 13:08:09.060700 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 13:08:09.066903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 13:08:09.067425 ==
1599 13:08:09.067877 RX Vref Scan: 0
1600 13:08:09.068329
1601 13:08:09.070610 RX Vref 0 -> 0, step: 1
1602 13:08:09.071013
1603 13:08:09.074058 RX Delay -130 -> 252, step: 16
1604 13:08:09.077072 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1605 13:08:09.080875 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1606 13:08:09.084153 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1607 13:08:09.090688 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1608 13:08:09.093598 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1609 13:08:09.097080 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1610 13:08:09.100417 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1611 13:08:09.104171 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1612 13:08:09.107179 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1613 13:08:09.114042 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1614 13:08:09.117195 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1615 13:08:09.120324 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1616 13:08:09.123877 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1617 13:08:09.130781 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1618 13:08:09.133579 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1619 13:08:09.137429 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1620 13:08:09.137834 ==
1621 13:08:09.140367 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 13:08:09.143585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 13:08:09.143980 ==
1624 13:08:09.146922 DQS Delay:
1625 13:08:09.147308 DQS0 = 0, DQS1 = 0
1626 13:08:09.150484 DQM Delay:
1627 13:08:09.150936 DQM0 = 81, DQM1 = 71
1628 13:08:09.151329 DQ Delay:
1629 13:08:09.153677 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1630 13:08:09.157262 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1631 13:08:09.160195 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1632 13:08:09.163860 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1633 13:08:09.164230
1634 13:08:09.164539
1635 13:08:09.164817 ==
1636 13:08:09.167489 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 13:08:09.173510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 13:08:09.173865 ==
1639 13:08:09.174194
1640 13:08:09.174484
1641 13:08:09.174758 TX Vref Scan disable
1642 13:08:09.177803 == TX Byte 0 ==
1643 13:08:09.180783 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1644 13:08:09.187174 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1645 13:08:09.187521 == TX Byte 1 ==
1646 13:08:09.190846 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1647 13:08:09.197631 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1648 13:08:09.198050 ==
1649 13:08:09.200766 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 13:08:09.203979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 13:08:09.204369 ==
1652 13:08:09.216926 TX Vref=22, minBit 1, minWin=26, winSum=438
1653 13:08:09.219954 TX Vref=24, minBit 1, minWin=27, winSum=443
1654 13:08:09.223495 TX Vref=26, minBit 1, minWin=27, winSum=442
1655 13:08:09.226861 TX Vref=28, minBit 5, minWin=27, winSum=448
1656 13:08:09.230400 TX Vref=30, minBit 6, minWin=27, winSum=449
1657 13:08:09.233579 TX Vref=32, minBit 5, minWin=27, winSum=445
1658 13:08:09.240264 [TxChooseVref] Worse bit 6, Min win 27, Win sum 449, Final Vref 30
1659 13:08:09.240791
1660 13:08:09.243970 Final TX Range 1 Vref 30
1661 13:08:09.244498
1662 13:08:09.244941 ==
1663 13:08:09.246728 Dram Type= 6, Freq= 0, CH_1, rank 0
1664 13:08:09.250539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1665 13:08:09.250946 ==
1666 13:08:09.251261
1667 13:08:09.253655
1668 13:08:09.254056 TX Vref Scan disable
1669 13:08:09.256536 == TX Byte 0 ==
1670 13:08:09.260174 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1671 13:08:09.263229 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1672 13:08:09.266687 == TX Byte 1 ==
1673 13:08:09.270088 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1674 13:08:09.273347 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1675 13:08:09.276961
1676 13:08:09.277343 [DATLAT]
1677 13:08:09.277638 Freq=800, CH1 RK0
1678 13:08:09.277914
1679 13:08:09.279959 DATLAT Default: 0xa
1680 13:08:09.280344 0, 0xFFFF, sum = 0
1681 13:08:09.283581 1, 0xFFFF, sum = 0
1682 13:08:09.283972 2, 0xFFFF, sum = 0
1683 13:08:09.286651 3, 0xFFFF, sum = 0
1684 13:08:09.287041 4, 0xFFFF, sum = 0
1685 13:08:09.290415 5, 0xFFFF, sum = 0
1686 13:08:09.293559 6, 0xFFFF, sum = 0
1687 13:08:09.293982 7, 0xFFFF, sum = 0
1688 13:08:09.294516 8, 0x0, sum = 1
1689 13:08:09.296575 9, 0x0, sum = 2
1690 13:08:09.296967 10, 0x0, sum = 3
1691 13:08:09.300159 11, 0x0, sum = 4
1692 13:08:09.300551 best_step = 9
1693 13:08:09.300906
1694 13:08:09.301247 ==
1695 13:08:09.303375 Dram Type= 6, Freq= 0, CH_1, rank 0
1696 13:08:09.309980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1697 13:08:09.310430 ==
1698 13:08:09.310749 RX Vref Scan: 1
1699 13:08:09.311035
1700 13:08:09.313372 Set Vref Range= 32 -> 127
1701 13:08:09.313834
1702 13:08:09.316651 RX Vref 32 -> 127, step: 1
1703 13:08:09.317199
1704 13:08:09.317543 RX Delay -111 -> 252, step: 8
1705 13:08:09.319998
1706 13:08:09.320409 Set Vref, RX VrefLevel [Byte0]: 32
1707 13:08:09.323340 [Byte1]: 32
1708 13:08:09.327872
1709 13:08:09.328261 Set Vref, RX VrefLevel [Byte0]: 33
1710 13:08:09.330689 [Byte1]: 33
1711 13:08:09.335399
1712 13:08:09.335741 Set Vref, RX VrefLevel [Byte0]: 34
1713 13:08:09.338421 [Byte1]: 34
1714 13:08:09.342849
1715 13:08:09.343185 Set Vref, RX VrefLevel [Byte0]: 35
1716 13:08:09.346659 [Byte1]: 35
1717 13:08:09.350389
1718 13:08:09.350727 Set Vref, RX VrefLevel [Byte0]: 36
1719 13:08:09.353685 [Byte1]: 36
1720 13:08:09.358516
1721 13:08:09.358874 Set Vref, RX VrefLevel [Byte0]: 37
1722 13:08:09.361607 [Byte1]: 37
1723 13:08:09.365596
1724 13:08:09.365930 Set Vref, RX VrefLevel [Byte0]: 38
1725 13:08:09.369418 [Byte1]: 38
1726 13:08:09.373932
1727 13:08:09.374321 Set Vref, RX VrefLevel [Byte0]: 39
1728 13:08:09.376868 [Byte1]: 39
1729 13:08:09.381620
1730 13:08:09.381958 Set Vref, RX VrefLevel [Byte0]: 40
1731 13:08:09.384585 [Byte1]: 40
1732 13:08:09.388923
1733 13:08:09.389325 Set Vref, RX VrefLevel [Byte0]: 41
1734 13:08:09.392211 [Byte1]: 41
1735 13:08:09.396714
1736 13:08:09.397233 Set Vref, RX VrefLevel [Byte0]: 42
1737 13:08:09.400236 [Byte1]: 42
1738 13:08:09.404202
1739 13:08:09.404773 Set Vref, RX VrefLevel [Byte0]: 43
1740 13:08:09.407776 [Byte1]: 43
1741 13:08:09.411848
1742 13:08:09.412386 Set Vref, RX VrefLevel [Byte0]: 44
1743 13:08:09.415502 [Byte1]: 44
1744 13:08:09.419479
1745 13:08:09.419922 Set Vref, RX VrefLevel [Byte0]: 45
1746 13:08:09.422708 [Byte1]: 45
1747 13:08:09.427164
1748 13:08:09.427605 Set Vref, RX VrefLevel [Byte0]: 46
1749 13:08:09.430540 [Byte1]: 46
1750 13:08:09.434642
1751 13:08:09.435047 Set Vref, RX VrefLevel [Byte0]: 47
1752 13:08:09.438199 [Byte1]: 47
1753 13:08:09.442265
1754 13:08:09.442630 Set Vref, RX VrefLevel [Byte0]: 48
1755 13:08:09.445875 [Byte1]: 48
1756 13:08:09.450049
1757 13:08:09.450539 Set Vref, RX VrefLevel [Byte0]: 49
1758 13:08:09.453200 [Byte1]: 49
1759 13:08:09.457667
1760 13:08:09.458052 Set Vref, RX VrefLevel [Byte0]: 50
1761 13:08:09.461139 [Byte1]: 50
1762 13:08:09.465178
1763 13:08:09.465581 Set Vref, RX VrefLevel [Byte0]: 51
1764 13:08:09.468382 [Byte1]: 51
1765 13:08:09.473249
1766 13:08:09.473602 Set Vref, RX VrefLevel [Byte0]: 52
1767 13:08:09.475892 [Byte1]: 52
1768 13:08:09.480690
1769 13:08:09.481036 Set Vref, RX VrefLevel [Byte0]: 53
1770 13:08:09.483982 [Byte1]: 53
1771 13:08:09.488418
1772 13:08:09.488760 Set Vref, RX VrefLevel [Byte0]: 54
1773 13:08:09.491415 [Byte1]: 54
1774 13:08:09.495731
1775 13:08:09.496231 Set Vref, RX VrefLevel [Byte0]: 55
1776 13:08:09.501943 [Byte1]: 55
1777 13:08:09.502340
1778 13:08:09.505659 Set Vref, RX VrefLevel [Byte0]: 56
1779 13:08:09.508679 [Byte1]: 56
1780 13:08:09.509022
1781 13:08:09.512283 Set Vref, RX VrefLevel [Byte0]: 57
1782 13:08:09.515757 [Byte1]: 57
1783 13:08:09.519309
1784 13:08:09.519654 Set Vref, RX VrefLevel [Byte0]: 58
1785 13:08:09.522524 [Byte1]: 58
1786 13:08:09.526530
1787 13:08:09.526882 Set Vref, RX VrefLevel [Byte0]: 59
1788 13:08:09.530068 [Byte1]: 59
1789 13:08:09.534456
1790 13:08:09.534798 Set Vref, RX VrefLevel [Byte0]: 60
1791 13:08:09.537505 [Byte1]: 60
1792 13:08:09.541752
1793 13:08:09.542084 Set Vref, RX VrefLevel [Byte0]: 61
1794 13:08:09.545210 [Byte1]: 61
1795 13:08:09.549579
1796 13:08:09.550052 Set Vref, RX VrefLevel [Byte0]: 62
1797 13:08:09.552528 [Byte1]: 62
1798 13:08:09.556883
1799 13:08:09.557337 Set Vref, RX VrefLevel [Byte0]: 63
1800 13:08:09.560303 [Byte1]: 63
1801 13:08:09.565191
1802 13:08:09.565505 Set Vref, RX VrefLevel [Byte0]: 64
1803 13:08:09.567970 [Byte1]: 64
1804 13:08:09.572453
1805 13:08:09.572919 Set Vref, RX VrefLevel [Byte0]: 65
1806 13:08:09.575538 [Byte1]: 65
1807 13:08:09.579834
1808 13:08:09.580240 Set Vref, RX VrefLevel [Byte0]: 66
1809 13:08:09.583585 [Byte1]: 66
1810 13:08:09.587655
1811 13:08:09.587996 Set Vref, RX VrefLevel [Byte0]: 67
1812 13:08:09.591007 [Byte1]: 67
1813 13:08:09.595562
1814 13:08:09.595896 Set Vref, RX VrefLevel [Byte0]: 68
1815 13:08:09.598452 [Byte1]: 68
1816 13:08:09.602979
1817 13:08:09.603376 Set Vref, RX VrefLevel [Byte0]: 69
1818 13:08:09.606069 [Byte1]: 69
1819 13:08:09.610861
1820 13:08:09.611209 Set Vref, RX VrefLevel [Byte0]: 70
1821 13:08:09.613873 [Byte1]: 70
1822 13:08:09.618044
1823 13:08:09.618430 Set Vref, RX VrefLevel [Byte0]: 71
1824 13:08:09.621396 [Byte1]: 71
1825 13:08:09.625884
1826 13:08:09.626400 Set Vref, RX VrefLevel [Byte0]: 72
1827 13:08:09.629176 [Byte1]: 72
1828 13:08:09.633518
1829 13:08:09.633861 Set Vref, RX VrefLevel [Byte0]: 73
1830 13:08:09.636640 [Byte1]: 73
1831 13:08:09.641099
1832 13:08:09.641465 Set Vref, RX VrefLevel [Byte0]: 74
1833 13:08:09.644430 [Byte1]: 74
1834 13:08:09.648630
1835 13:08:09.648999 Set Vref, RX VrefLevel [Byte0]: 75
1836 13:08:09.651964 [Byte1]: 75
1837 13:08:09.656811
1838 13:08:09.657329 Final RX Vref Byte 0 = 59 to rank0
1839 13:08:09.659875 Final RX Vref Byte 1 = 56 to rank0
1840 13:08:09.663110 Final RX Vref Byte 0 = 59 to rank1
1841 13:08:09.666841 Final RX Vref Byte 1 = 56 to rank1==
1842 13:08:09.669752 Dram Type= 6, Freq= 0, CH_1, rank 0
1843 13:08:09.676148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1844 13:08:09.676357 ==
1845 13:08:09.676489 DQS Delay:
1846 13:08:09.676621 DQS0 = 0, DQS1 = 0
1847 13:08:09.679341 DQM Delay:
1848 13:08:09.679493 DQM0 = 81, DQM1 = 72
1849 13:08:09.683089 DQ Delay:
1850 13:08:09.686115 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1851 13:08:09.686263 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1852 13:08:09.689751 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1853 13:08:09.695795 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =76
1854 13:08:09.695987
1855 13:08:09.696107
1856 13:08:09.702868 [DQSOSCAuto] RK0, (LSB)MR18= 0x151e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
1857 13:08:09.706055 CH1 RK0: MR19=606, MR18=151E
1858 13:08:09.712898 CH1_RK0: MR19=0x606, MR18=0x151E, DQSOSC=402, MR23=63, INC=91, DEC=60
1859 13:08:09.712967
1860 13:08:09.715756 ----->DramcWriteLeveling(PI) begin...
1861 13:08:09.715821 ==
1862 13:08:09.719761 Dram Type= 6, Freq= 0, CH_1, rank 1
1863 13:08:09.722690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1864 13:08:09.722758 ==
1865 13:08:09.726068 Write leveling (Byte 0): 28 => 28
1866 13:08:09.729790 Write leveling (Byte 1): 29 => 29
1867 13:08:09.732932 DramcWriteLeveling(PI) end<-----
1868 13:08:09.732998
1869 13:08:09.733052 ==
1870 13:08:09.736413 Dram Type= 6, Freq= 0, CH_1, rank 1
1871 13:08:09.739870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1872 13:08:09.739945 ==
1873 13:08:09.743096 [Gating] SW mode calibration
1874 13:08:09.749611 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1875 13:08:09.756216 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1876 13:08:09.759842 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1877 13:08:09.763302 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1878 13:08:09.769464 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1879 13:08:09.772865 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 13:08:09.776280 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 13:08:09.783071 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 13:08:09.786977 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 13:08:09.789978 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 13:08:09.796631 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 13:08:09.799753 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 13:08:09.803349 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 13:08:09.806542 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 13:08:09.813243 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 13:08:09.816816 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 13:08:09.820240 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 13:08:09.826437 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 13:08:09.830195 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1893 13:08:09.833041 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1894 13:08:09.839898 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 13:08:09.843411 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 13:08:09.846593 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 13:08:09.853135 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 13:08:09.856458 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 13:08:09.860092 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 13:08:09.866503 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 13:08:09.870591 0 9 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
1902 13:08:09.873325 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
1903 13:08:09.879936 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 13:08:09.883409 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 13:08:09.886819 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 13:08:09.892968 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 13:08:09.896702 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 13:08:09.900124 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1909 13:08:09.903301 0 10 4 | B1->B0 | 3131 2b2b | 1 0 | (1 1) (1 0)
1910 13:08:09.910201 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1911 13:08:09.913219 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 13:08:09.916710 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 13:08:09.923305 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 13:08:09.926499 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 13:08:09.930154 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 13:08:09.936781 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1917 13:08:09.939903 0 11 4 | B1->B0 | 2b2b 3b3b | 0 0 | (0 0) (0 0)
1918 13:08:09.943369 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1919 13:08:09.950199 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 13:08:09.953272 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 13:08:09.956543 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 13:08:09.963016 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 13:08:09.966396 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 13:08:09.970160 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 13:08:09.976489 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1926 13:08:09.979874 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1927 13:08:09.983482 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 13:08:09.989786 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 13:08:09.992997 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 13:08:09.996383 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 13:08:09.999899 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 13:08:10.006513 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 13:08:10.009836 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 13:08:10.013232 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 13:08:10.019791 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 13:08:10.023614 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 13:08:10.026927 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 13:08:10.033362 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 13:08:10.037149 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 13:08:10.039853 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 13:08:10.046416 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1942 13:08:10.050317 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1943 13:08:10.053254 Total UI for P1: 0, mck2ui 16
1944 13:08:10.056717 best dqsien dly found for B0: ( 0, 14, 4)
1945 13:08:10.059929 Total UI for P1: 0, mck2ui 16
1946 13:08:10.063436 best dqsien dly found for B1: ( 0, 14, 6)
1947 13:08:10.066800 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1948 13:08:10.069799 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1949 13:08:10.070207
1950 13:08:10.073165 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1951 13:08:10.076438 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1952 13:08:10.079607 [Gating] SW calibration Done
1953 13:08:10.080053 ==
1954 13:08:10.082939 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 13:08:10.086439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 13:08:10.086890 ==
1957 13:08:10.089510 RX Vref Scan: 0
1958 13:08:10.090060
1959 13:08:10.093087 RX Vref 0 -> 0, step: 1
1960 13:08:10.093450
1961 13:08:10.096066 RX Delay -130 -> 252, step: 16
1962 13:08:10.099475 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1963 13:08:10.102559 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1964 13:08:10.106153 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1965 13:08:10.109537 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1966 13:08:10.113002 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1967 13:08:10.119736 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1968 13:08:10.122868 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1969 13:08:10.126096 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1970 13:08:10.129539 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1971 13:08:10.132693 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1972 13:08:10.139413 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1973 13:08:10.142986 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1974 13:08:10.146289 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1975 13:08:10.149424 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1976 13:08:10.156293 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1977 13:08:10.159497 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1978 13:08:10.159572 ==
1979 13:08:10.162389 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 13:08:10.165796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 13:08:10.165872 ==
1982 13:08:10.165930 DQS Delay:
1983 13:08:10.168923 DQS0 = 0, DQS1 = 0
1984 13:08:10.168998 DQM Delay:
1985 13:08:10.172542 DQM0 = 79, DQM1 = 78
1986 13:08:10.172617 DQ Delay:
1987 13:08:10.175593 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1988 13:08:10.179110 DQ4 =77, DQ5 =85, DQ6 =93, DQ7 =77
1989 13:08:10.182962 DQ8 =61, DQ9 =69, DQ10 =85, DQ11 =69
1990 13:08:10.185734 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1991 13:08:10.185823
1992 13:08:10.185903
1993 13:08:10.185981 ==
1994 13:08:10.189327 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 13:08:10.192472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 13:08:10.195778 ==
1997 13:08:10.195844
1998 13:08:10.195917
1999 13:08:10.196005 TX Vref Scan disable
2000 13:08:10.199331 == TX Byte 0 ==
2001 13:08:10.202598 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2002 13:08:10.205694 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2003 13:08:10.209165 == TX Byte 1 ==
2004 13:08:10.212458 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2005 13:08:10.216068 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2006 13:08:10.216135 ==
2007 13:08:10.219205 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 13:08:10.225866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 13:08:10.225933 ==
2010 13:08:10.238221 TX Vref=22, minBit 3, minWin=27, winSum=448
2011 13:08:10.241101 TX Vref=24, minBit 1, minWin=28, winSum=454
2012 13:08:10.244280 TX Vref=26, minBit 0, minWin=28, winSum=457
2013 13:08:10.247862 TX Vref=28, minBit 3, minWin=27, winSum=457
2014 13:08:10.250988 TX Vref=30, minBit 1, minWin=28, winSum=462
2015 13:08:10.254667 TX Vref=32, minBit 5, minWin=27, winSum=457
2016 13:08:10.260942 [TxChooseVref] Worse bit 1, Min win 28, Win sum 462, Final Vref 30
2017 13:08:10.261017
2018 13:08:10.264241 Final TX Range 1 Vref 30
2019 13:08:10.264331
2020 13:08:10.264410 ==
2021 13:08:10.267742 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 13:08:10.270847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 13:08:10.270913 ==
2024 13:08:10.270966
2025 13:08:10.274361
2026 13:08:10.274447 TX Vref Scan disable
2027 13:08:10.277373 == TX Byte 0 ==
2028 13:08:10.281069 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2029 13:08:10.287566 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2030 13:08:10.287656 == TX Byte 1 ==
2031 13:08:10.290955 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2032 13:08:10.297417 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2033 13:08:10.297509
2034 13:08:10.297600 [DATLAT]
2035 13:08:10.297673 Freq=800, CH1 RK1
2036 13:08:10.297726
2037 13:08:10.300905 DATLAT Default: 0x9
2038 13:08:10.300967 0, 0xFFFF, sum = 0
2039 13:08:10.304430 1, 0xFFFF, sum = 0
2040 13:08:10.304501 2, 0xFFFF, sum = 0
2041 13:08:10.307449 3, 0xFFFF, sum = 0
2042 13:08:10.307511 4, 0xFFFF, sum = 0
2043 13:08:10.311024 5, 0xFFFF, sum = 0
2044 13:08:10.314412 6, 0xFFFF, sum = 0
2045 13:08:10.314476 7, 0xFFFF, sum = 0
2046 13:08:10.317718 8, 0xFFFF, sum = 0
2047 13:08:10.317865 9, 0x0, sum = 1
2048 13:08:10.317966 10, 0x0, sum = 2
2049 13:08:10.321144 11, 0x0, sum = 3
2050 13:08:10.321240 12, 0x0, sum = 4
2051 13:08:10.323904 best_step = 10
2052 13:08:10.324001
2053 13:08:10.324084 ==
2054 13:08:10.327713 Dram Type= 6, Freq= 0, CH_1, rank 1
2055 13:08:10.330881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2056 13:08:10.330954 ==
2057 13:08:10.334114 RX Vref Scan: 0
2058 13:08:10.334212
2059 13:08:10.334294 RX Vref 0 -> 0, step: 1
2060 13:08:10.334377
2061 13:08:10.337306 RX Delay -111 -> 252, step: 8
2062 13:08:10.344860 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
2063 13:08:10.347709 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2064 13:08:10.351360 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2065 13:08:10.354271 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2066 13:08:10.357429 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2067 13:08:10.364283 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2068 13:08:10.367970 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2069 13:08:10.370885 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2070 13:08:10.374349 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2071 13:08:10.377763 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2072 13:08:10.384218 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2073 13:08:10.387745 iDelay=209, Bit 11, Center 72 (-47 ~ 192) 240
2074 13:08:10.390918 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
2075 13:08:10.394500 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2076 13:08:10.397841 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2077 13:08:10.404521 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2078 13:08:10.404592 ==
2079 13:08:10.407658 Dram Type= 6, Freq= 0, CH_1, rank 1
2080 13:08:10.410705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2081 13:08:10.410775 ==
2082 13:08:10.410850 DQS Delay:
2083 13:08:10.414342 DQS0 = 0, DQS1 = 0
2084 13:08:10.414406 DQM Delay:
2085 13:08:10.417438 DQM0 = 77, DQM1 = 75
2086 13:08:10.417500 DQ Delay:
2087 13:08:10.421271 DQ0 =84, DQ1 =72, DQ2 =64, DQ3 =72
2088 13:08:10.424093 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2089 13:08:10.427671 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =72
2090 13:08:10.430826 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
2091 13:08:10.430895
2092 13:08:10.430950
2093 13:08:10.440976 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b43, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 398 ps
2094 13:08:10.441046 CH1 RK1: MR19=606, MR18=2B43
2095 13:08:10.447317 CH1_RK1: MR19=0x606, MR18=0x2B43, DQSOSC=393, MR23=63, INC=95, DEC=63
2096 13:08:10.450966 [RxdqsGatingPostProcess] freq 800
2097 13:08:10.457613 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2098 13:08:10.460826 Pre-setting of DQS Precalculation
2099 13:08:10.464846 [DualRankRxdatlatCal] RK0: 9, RK1: 10, Final_Datlat 10
2100 13:08:10.471214 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2101 13:08:10.477919 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2102 13:08:10.477988
2103 13:08:10.478066
2104 13:08:10.480905 [Calibration Summary] 1600 Mbps
2105 13:08:10.484286 CH 0, Rank 0
2106 13:08:10.484380 SW Impedance : PASS
2107 13:08:10.487927 DUTY Scan : NO K
2108 13:08:10.491157 ZQ Calibration : PASS
2109 13:08:10.491249 Jitter Meter : NO K
2110 13:08:10.494504 CBT Training : PASS
2111 13:08:10.497469 Write leveling : PASS
2112 13:08:10.497534 RX DQS gating : PASS
2113 13:08:10.501029 RX DQ/DQS(RDDQC) : PASS
2114 13:08:10.504033 TX DQ/DQS : PASS
2115 13:08:10.504126 RX DATLAT : PASS
2116 13:08:10.507485 RX DQ/DQS(Engine): PASS
2117 13:08:10.507551 TX OE : NO K
2118 13:08:10.510851 All Pass.
2119 13:08:10.510918
2120 13:08:10.510984 CH 0, Rank 1
2121 13:08:10.514362 SW Impedance : PASS
2122 13:08:10.514443 DUTY Scan : NO K
2123 13:08:10.517628 ZQ Calibration : PASS
2124 13:08:10.520915 Jitter Meter : NO K
2125 13:08:10.521005 CBT Training : PASS
2126 13:08:10.524638 Write leveling : PASS
2127 13:08:10.528327 RX DQS gating : PASS
2128 13:08:10.528392 RX DQ/DQS(RDDQC) : PASS
2129 13:08:10.531042 TX DQ/DQS : PASS
2130 13:08:10.534564 RX DATLAT : PASS
2131 13:08:10.534633 RX DQ/DQS(Engine): PASS
2132 13:08:10.538046 TX OE : NO K
2133 13:08:10.538150 All Pass.
2134 13:08:10.538204
2135 13:08:10.541331 CH 1, Rank 0
2136 13:08:10.541393 SW Impedance : PASS
2137 13:08:10.544819 DUTY Scan : NO K
2138 13:08:10.544907 ZQ Calibration : PASS
2139 13:08:10.547835 Jitter Meter : NO K
2140 13:08:10.551138 CBT Training : PASS
2141 13:08:10.551204 Write leveling : PASS
2142 13:08:10.554704 RX DQS gating : PASS
2143 13:08:10.557894 RX DQ/DQS(RDDQC) : PASS
2144 13:08:10.557982 TX DQ/DQS : PASS
2145 13:08:10.561219 RX DATLAT : PASS
2146 13:08:10.564710 RX DQ/DQS(Engine): PASS
2147 13:08:10.564813 TX OE : NO K
2148 13:08:10.568266 All Pass.
2149 13:08:10.568333
2150 13:08:10.568395 CH 1, Rank 1
2151 13:08:10.571359 SW Impedance : PASS
2152 13:08:10.571435 DUTY Scan : NO K
2153 13:08:10.574295 ZQ Calibration : PASS
2154 13:08:10.577976 Jitter Meter : NO K
2155 13:08:10.578036 CBT Training : PASS
2156 13:08:10.581016 Write leveling : PASS
2157 13:08:10.581081 RX DQS gating : PASS
2158 13:08:10.584543 RX DQ/DQS(RDDQC) : PASS
2159 13:08:10.588093 TX DQ/DQS : PASS
2160 13:08:10.588155 RX DATLAT : PASS
2161 13:08:10.591409 RX DQ/DQS(Engine): PASS
2162 13:08:10.594379 TX OE : NO K
2163 13:08:10.594439 All Pass.
2164 13:08:10.594492
2165 13:08:10.598232 DramC Write-DBI off
2166 13:08:10.598316 PER_BANK_REFRESH: Hybrid Mode
2167 13:08:10.601089 TX_TRACKING: ON
2168 13:08:10.604613 [GetDramInforAfterCalByMRR] Vendor 6.
2169 13:08:10.607760 [GetDramInforAfterCalByMRR] Revision 606.
2170 13:08:10.611631 [GetDramInforAfterCalByMRR] Revision 2 0.
2171 13:08:10.611692 MR0 0x3b3b
2172 13:08:10.614607 MR8 0x5151
2173 13:08:10.617752 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2174 13:08:10.617809
2175 13:08:10.617864 MR0 0x3b3b
2176 13:08:10.617914 MR8 0x5151
2177 13:08:10.624392 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2178 13:08:10.624461
2179 13:08:10.631016 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2180 13:08:10.634730 [FAST_K] Save calibration result to emmc
2181 13:08:10.637643 [FAST_K] Save calibration result to emmc
2182 13:08:10.641581 dram_init: config_dvfs: 1
2183 13:08:10.644857 dramc_set_vcore_voltage set vcore to 662500
2184 13:08:10.647924 Read voltage for 1200, 2
2185 13:08:10.647987 Vio18 = 0
2186 13:08:10.651530 Vcore = 662500
2187 13:08:10.651592 Vdram = 0
2188 13:08:10.651644 Vddq = 0
2189 13:08:10.654522 Vmddr = 0
2190 13:08:10.657542 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2191 13:08:10.664222 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2192 13:08:10.664289 MEM_TYPE=3, freq_sel=15
2193 13:08:10.667898 sv_algorithm_assistance_LP4_1600
2194 13:08:10.674282 ============ PULL DRAM RESETB DOWN ============
2195 13:08:10.677924 ========== PULL DRAM RESETB DOWN end =========
2196 13:08:10.681051 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2197 13:08:10.684175 ===================================
2198 13:08:10.687549 LPDDR4 DRAM CONFIGURATION
2199 13:08:10.690985 ===================================
2200 13:08:10.691059 EX_ROW_EN[0] = 0x0
2201 13:08:10.694711 EX_ROW_EN[1] = 0x0
2202 13:08:10.697646 LP4Y_EN = 0x0
2203 13:08:10.697712 WORK_FSP = 0x0
2204 13:08:10.701316 WL = 0x4
2205 13:08:10.701384 RL = 0x4
2206 13:08:10.704587 BL = 0x2
2207 13:08:10.704683 RPST = 0x0
2208 13:08:10.707510 RD_PRE = 0x0
2209 13:08:10.707572 WR_PRE = 0x1
2210 13:08:10.711270 WR_PST = 0x0
2211 13:08:10.711331 DBI_WR = 0x0
2212 13:08:10.714630 DBI_RD = 0x0
2213 13:08:10.714691 OTF = 0x1
2214 13:08:10.717564 ===================================
2215 13:08:10.720928 ===================================
2216 13:08:10.724724 ANA top config
2217 13:08:10.727606 ===================================
2218 13:08:10.727669 DLL_ASYNC_EN = 0
2219 13:08:10.731049 ALL_SLAVE_EN = 0
2220 13:08:10.734040 NEW_RANK_MODE = 1
2221 13:08:10.737426 DLL_IDLE_MODE = 1
2222 13:08:10.737489 LP45_APHY_COMB_EN = 1
2223 13:08:10.741310 TX_ODT_DIS = 1
2224 13:08:10.744106 NEW_8X_MODE = 1
2225 13:08:10.747282 ===================================
2226 13:08:10.750998 ===================================
2227 13:08:10.754385 data_rate = 2400
2228 13:08:10.757376 CKR = 1
2229 13:08:10.761038 DQ_P2S_RATIO = 8
2230 13:08:10.764648 ===================================
2231 13:08:10.764713 CA_P2S_RATIO = 8
2232 13:08:10.767544 DQ_CA_OPEN = 0
2233 13:08:10.771032 DQ_SEMI_OPEN = 0
2234 13:08:10.774507 CA_SEMI_OPEN = 0
2235 13:08:10.777796 CA_FULL_RATE = 0
2236 13:08:10.780872 DQ_CKDIV4_EN = 0
2237 13:08:10.780935 CA_CKDIV4_EN = 0
2238 13:08:10.784447 CA_PREDIV_EN = 0
2239 13:08:10.787423 PH8_DLY = 17
2240 13:08:10.790843 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2241 13:08:10.794210 DQ_AAMCK_DIV = 4
2242 13:08:10.797486 CA_AAMCK_DIV = 4
2243 13:08:10.797552 CA_ADMCK_DIV = 4
2244 13:08:10.800719 DQ_TRACK_CA_EN = 0
2245 13:08:10.804094 CA_PICK = 1200
2246 13:08:10.807852 CA_MCKIO = 1200
2247 13:08:10.811090 MCKIO_SEMI = 0
2248 13:08:10.814021 PLL_FREQ = 2366
2249 13:08:10.817731 DQ_UI_PI_RATIO = 32
2250 13:08:10.817798 CA_UI_PI_RATIO = 0
2251 13:08:10.820773 ===================================
2252 13:08:10.824751 ===================================
2253 13:08:10.827983 memory_type:LPDDR4
2254 13:08:10.831041 GP_NUM : 10
2255 13:08:10.831142 SRAM_EN : 1
2256 13:08:10.834400 MD32_EN : 0
2257 13:08:10.837567 ===================================
2258 13:08:10.840908 [ANA_INIT] >>>>>>>>>>>>>>
2259 13:08:10.840972 <<<<<< [CONFIGURE PHASE]: ANA_TX
2260 13:08:10.844578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2261 13:08:10.847641 ===================================
2262 13:08:10.850989 data_rate = 2400,PCW = 0X5b00
2263 13:08:10.854418 ===================================
2264 13:08:10.857658 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2265 13:08:10.864554 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2266 13:08:10.871116 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2267 13:08:10.874302 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2268 13:08:10.877825 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2269 13:08:10.880790 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2270 13:08:10.884331 [ANA_INIT] flow start
2271 13:08:10.884399 [ANA_INIT] PLL >>>>>>>>
2272 13:08:10.887385 [ANA_INIT] PLL <<<<<<<<
2273 13:08:10.890785 [ANA_INIT] MIDPI >>>>>>>>
2274 13:08:10.890847 [ANA_INIT] MIDPI <<<<<<<<
2275 13:08:10.894272 [ANA_INIT] DLL >>>>>>>>
2276 13:08:10.897385 [ANA_INIT] DLL <<<<<<<<
2277 13:08:10.897450 [ANA_INIT] flow end
2278 13:08:10.904263 ============ LP4 DIFF to SE enter ============
2279 13:08:10.908149 ============ LP4 DIFF to SE exit ============
2280 13:08:10.910687 [ANA_INIT] <<<<<<<<<<<<<
2281 13:08:10.914177 [Flow] Enable top DCM control >>>>>
2282 13:08:10.917292 [Flow] Enable top DCM control <<<<<
2283 13:08:10.917358 Enable DLL master slave shuffle
2284 13:08:10.924247 ==============================================================
2285 13:08:10.927831 Gating Mode config
2286 13:08:10.930566 ==============================================================
2287 13:08:10.933990 Config description:
2288 13:08:10.944221 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2289 13:08:10.951242 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2290 13:08:10.954220 SELPH_MODE 0: By rank 1: By Phase
2291 13:08:10.961091 ==============================================================
2292 13:08:10.964129 GAT_TRACK_EN = 1
2293 13:08:10.967480 RX_GATING_MODE = 2
2294 13:08:10.970988 RX_GATING_TRACK_MODE = 2
2295 13:08:10.971054 SELPH_MODE = 1
2296 13:08:10.974185 PICG_EARLY_EN = 1
2297 13:08:10.977487 VALID_LAT_VALUE = 1
2298 13:08:10.984258 ==============================================================
2299 13:08:10.987909 Enter into Gating configuration >>>>
2300 13:08:10.990724 Exit from Gating configuration <<<<
2301 13:08:10.994089 Enter into DVFS_PRE_config >>>>>
2302 13:08:11.004511 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2303 13:08:11.007544 Exit from DVFS_PRE_config <<<<<
2304 13:08:11.010862 Enter into PICG configuration >>>>
2305 13:08:11.014478 Exit from PICG configuration <<<<
2306 13:08:11.017625 [RX_INPUT] configuration >>>>>
2307 13:08:11.020988 [RX_INPUT] configuration <<<<<
2308 13:08:11.024164 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2309 13:08:11.030658 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2310 13:08:11.037685 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2311 13:08:11.043952 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2312 13:08:11.047484 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2313 13:08:11.054384 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2314 13:08:11.057458 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2315 13:08:11.064039 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2316 13:08:11.067680 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2317 13:08:11.070558 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2318 13:08:11.074126 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2319 13:08:11.080573 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2320 13:08:11.084284 ===================================
2321 13:08:11.084376 LPDDR4 DRAM CONFIGURATION
2322 13:08:11.087564 ===================================
2323 13:08:11.090636 EX_ROW_EN[0] = 0x0
2324 13:08:11.093953 EX_ROW_EN[1] = 0x0
2325 13:08:11.094052 LP4Y_EN = 0x0
2326 13:08:11.097309 WORK_FSP = 0x0
2327 13:08:11.097408 WL = 0x4
2328 13:08:11.100951 RL = 0x4
2329 13:08:11.101045 BL = 0x2
2330 13:08:11.104490 RPST = 0x0
2331 13:08:11.104581 RD_PRE = 0x0
2332 13:08:11.107580 WR_PRE = 0x1
2333 13:08:11.107648 WR_PST = 0x0
2334 13:08:11.111029 DBI_WR = 0x0
2335 13:08:11.111122 DBI_RD = 0x0
2336 13:08:11.114441 OTF = 0x1
2337 13:08:11.117911 ===================================
2338 13:08:11.120841 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2339 13:08:11.124191 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2340 13:08:11.131232 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2341 13:08:11.133947 ===================================
2342 13:08:11.134038 LPDDR4 DRAM CONFIGURATION
2343 13:08:11.137514 ===================================
2344 13:08:11.141033 EX_ROW_EN[0] = 0x10
2345 13:08:11.141138 EX_ROW_EN[1] = 0x0
2346 13:08:11.144193 LP4Y_EN = 0x0
2347 13:08:11.144288 WORK_FSP = 0x0
2348 13:08:11.147745 WL = 0x4
2349 13:08:11.147817 RL = 0x4
2350 13:08:11.150738 BL = 0x2
2351 13:08:11.154426 RPST = 0x0
2352 13:08:11.154521 RD_PRE = 0x0
2353 13:08:11.157568 WR_PRE = 0x1
2354 13:08:11.157637 WR_PST = 0x0
2355 13:08:11.160868 DBI_WR = 0x0
2356 13:08:11.160934 DBI_RD = 0x0
2357 13:08:11.164690 OTF = 0x1
2358 13:08:11.167638 ===================================
2359 13:08:11.171408 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2360 13:08:11.174438 ==
2361 13:08:11.177767 Dram Type= 6, Freq= 0, CH_0, rank 0
2362 13:08:11.180786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2363 13:08:11.180850 ==
2364 13:08:11.184445 [Duty_Offset_Calibration]
2365 13:08:11.184536 B0:2 B1:0 CA:3
2366 13:08:11.184615
2367 13:08:11.187313 [DutyScan_Calibration_Flow] k_type=0
2368 13:08:11.197194
2369 13:08:11.197262 ==CLK 0==
2370 13:08:11.200305 Final CLK duty delay cell = 0
2371 13:08:11.203830 [0] MAX Duty = 5062%(X100), DQS PI = 20
2372 13:08:11.207184 [0] MIN Duty = 4906%(X100), DQS PI = 54
2373 13:08:11.207287 [0] AVG Duty = 4984%(X100)
2374 13:08:11.210548
2375 13:08:11.213517 CH0 CLK Duty spec in!! Max-Min= 156%
2376 13:08:11.217277 [DutyScan_Calibration_Flow] ====Done====
2377 13:08:11.217343
2378 13:08:11.220191 [DutyScan_Calibration_Flow] k_type=1
2379 13:08:11.235318
2380 13:08:11.235412 ==DQS 0 ==
2381 13:08:11.238802 Final DQS duty delay cell = 0
2382 13:08:11.242525 [0] MAX Duty = 5062%(X100), DQS PI = 28
2383 13:08:11.245708 [0] MIN Duty = 4907%(X100), DQS PI = 2
2384 13:08:11.245800 [0] AVG Duty = 4984%(X100)
2385 13:08:11.248866
2386 13:08:11.248955 ==DQS 1 ==
2387 13:08:11.252479 Final DQS duty delay cell = -4
2388 13:08:11.255843 [-4] MAX Duty = 4969%(X100), DQS PI = 34
2389 13:08:11.258837 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2390 13:08:11.262303 [-4] AVG Duty = 4922%(X100)
2391 13:08:11.262373
2392 13:08:11.265560 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2393 13:08:11.265649
2394 13:08:11.269525 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2395 13:08:11.272351 [DutyScan_Calibration_Flow] ====Done====
2396 13:08:11.272442
2397 13:08:11.275438 [DutyScan_Calibration_Flow] k_type=3
2398 13:08:11.292996
2399 13:08:11.293069 ==DQM 0 ==
2400 13:08:11.296240 Final DQM duty delay cell = 0
2401 13:08:11.299477 [0] MAX Duty = 5124%(X100), DQS PI = 28
2402 13:08:11.303054 [0] MIN Duty = 4876%(X100), DQS PI = 0
2403 13:08:11.303122 [0] AVG Duty = 5000%(X100)
2404 13:08:11.306061
2405 13:08:11.306177 ==DQM 1 ==
2406 13:08:11.309479 Final DQM duty delay cell = 4
2407 13:08:11.312687 [4] MAX Duty = 5124%(X100), DQS PI = 50
2408 13:08:11.316441 [4] MIN Duty = 5000%(X100), DQS PI = 12
2409 13:08:11.316506 [4] AVG Duty = 5062%(X100)
2410 13:08:11.319629
2411 13:08:11.323090 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2412 13:08:11.323158
2413 13:08:11.326299 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2414 13:08:11.329556 [DutyScan_Calibration_Flow] ====Done====
2415 13:08:11.329620
2416 13:08:11.333034 [DutyScan_Calibration_Flow] k_type=2
2417 13:08:11.348066
2418 13:08:11.348133 ==DQ 0 ==
2419 13:08:11.351531 Final DQ duty delay cell = -4
2420 13:08:11.354976 [-4] MAX Duty = 5000%(X100), DQS PI = 12
2421 13:08:11.357686 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2422 13:08:11.361305 [-4] AVG Duty = 4953%(X100)
2423 13:08:11.361371
2424 13:08:11.361426 ==DQ 1 ==
2425 13:08:11.364258 Final DQ duty delay cell = -4
2426 13:08:11.367621 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2427 13:08:11.371121 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2428 13:08:11.374504 [-4] AVG Duty = 4938%(X100)
2429 13:08:11.374580
2430 13:08:11.378002 CH0 DQ 0 Duty spec in!! Max-Min= 93%
2431 13:08:11.378088
2432 13:08:11.381000 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2433 13:08:11.384710 [DutyScan_Calibration_Flow] ====Done====
2434 13:08:11.384773 ==
2435 13:08:11.388054 Dram Type= 6, Freq= 0, CH_1, rank 0
2436 13:08:11.391115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2437 13:08:11.391188 ==
2438 13:08:11.394442 [Duty_Offset_Calibration]
2439 13:08:11.394528 B0:1 B1:-2 CA:0
2440 13:08:11.394606
2441 13:08:11.397557 [DutyScan_Calibration_Flow] k_type=0
2442 13:08:11.408397
2443 13:08:11.408469 ==CLK 0==
2444 13:08:11.411850 Final CLK duty delay cell = 0
2445 13:08:11.415100 [0] MAX Duty = 5031%(X100), DQS PI = 18
2446 13:08:11.418503 [0] MIN Duty = 4844%(X100), DQS PI = 2
2447 13:08:11.418577 [0] AVG Duty = 4937%(X100)
2448 13:08:11.418633
2449 13:08:11.421984 CH1 CLK Duty spec in!! Max-Min= 187%
2450 13:08:11.428602 [DutyScan_Calibration_Flow] ====Done====
2451 13:08:11.428672
2452 13:08:11.431745 [DutyScan_Calibration_Flow] k_type=1
2453 13:08:11.446874
2454 13:08:11.446944 ==DQS 0 ==
2455 13:08:11.450020 Final DQS duty delay cell = -4
2456 13:08:11.453418 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2457 13:08:11.457217 [-4] MIN Duty = 4876%(X100), DQS PI = 50
2458 13:08:11.460260 [-4] AVG Duty = 4938%(X100)
2459 13:08:11.460325
2460 13:08:11.460379 ==DQS 1 ==
2461 13:08:11.463417 Final DQS duty delay cell = 0
2462 13:08:11.467020 [0] MAX Duty = 5093%(X100), DQS PI = 0
2463 13:08:11.470174 [0] MIN Duty = 4875%(X100), DQS PI = 26
2464 13:08:11.473633 [0] AVG Duty = 4984%(X100)
2465 13:08:11.473702
2466 13:08:11.476900 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2467 13:08:11.476964
2468 13:08:11.480101 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2469 13:08:11.483392 [DutyScan_Calibration_Flow] ====Done====
2470 13:08:11.483456
2471 13:08:11.486293 [DutyScan_Calibration_Flow] k_type=3
2472 13:08:11.503821
2473 13:08:11.503887 ==DQM 0 ==
2474 13:08:11.506757 Final DQM duty delay cell = 0
2475 13:08:11.510418 [0] MAX Duty = 5000%(X100), DQS PI = 22
2476 13:08:11.513413 [0] MIN Duty = 4844%(X100), DQS PI = 56
2477 13:08:11.513481 [0] AVG Duty = 4922%(X100)
2478 13:08:11.517051
2479 13:08:11.517145 ==DQM 1 ==
2480 13:08:11.520430 Final DQM duty delay cell = 0
2481 13:08:11.523661 [0] MAX Duty = 5031%(X100), DQS PI = 36
2482 13:08:11.527185 [0] MIN Duty = 4907%(X100), DQS PI = 4
2483 13:08:11.527251 [0] AVG Duty = 4969%(X100)
2484 13:08:11.530095
2485 13:08:11.533811 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2486 13:08:11.533878
2487 13:08:11.537059 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2488 13:08:11.540212 [DutyScan_Calibration_Flow] ====Done====
2489 13:08:11.540277
2490 13:08:11.543357 [DutyScan_Calibration_Flow] k_type=2
2491 13:08:11.560246
2492 13:08:11.560319 ==DQ 0 ==
2493 13:08:11.563523 Final DQ duty delay cell = 0
2494 13:08:11.566444 [0] MAX Duty = 5062%(X100), DQS PI = 12
2495 13:08:11.569995 [0] MIN Duty = 4938%(X100), DQS PI = 50
2496 13:08:11.570088 [0] AVG Duty = 5000%(X100)
2497 13:08:11.570207
2498 13:08:11.573168 ==DQ 1 ==
2499 13:08:11.576442 Final DQ duty delay cell = 0
2500 13:08:11.580048 [0] MAX Duty = 5125%(X100), DQS PI = 36
2501 13:08:11.583680 [0] MIN Duty = 4969%(X100), DQS PI = 26
2502 13:08:11.583750 [0] AVG Duty = 5047%(X100)
2503 13:08:11.583804
2504 13:08:11.586567 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2505 13:08:11.586629
2506 13:08:11.593272 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2507 13:08:11.596749 [DutyScan_Calibration_Flow] ====Done====
2508 13:08:11.600220 nWR fixed to 30
2509 13:08:11.600291 [ModeRegInit_LP4] CH0 RK0
2510 13:08:11.603351 [ModeRegInit_LP4] CH0 RK1
2511 13:08:11.606595 [ModeRegInit_LP4] CH1 RK0
2512 13:08:11.606665 [ModeRegInit_LP4] CH1 RK1
2513 13:08:11.610074 match AC timing 7
2514 13:08:11.613135 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2515 13:08:11.616776 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2516 13:08:11.623111 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2517 13:08:11.626463 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2518 13:08:11.633347 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2519 13:08:11.633418 ==
2520 13:08:11.636484 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 13:08:11.640299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 13:08:11.640369 ==
2523 13:08:11.646802 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2524 13:08:11.650339 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2525 13:08:11.659855 [CA 0] Center 40 (10~71) winsize 62
2526 13:08:11.663221 [CA 1] Center 39 (9~70) winsize 62
2527 13:08:11.666685 [CA 2] Center 36 (6~66) winsize 61
2528 13:08:11.670106 [CA 3] Center 35 (5~66) winsize 62
2529 13:08:11.673144 [CA 4] Center 34 (4~65) winsize 62
2530 13:08:11.676717 [CA 5] Center 33 (3~63) winsize 61
2531 13:08:11.676780
2532 13:08:11.680060 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2533 13:08:11.680125
2534 13:08:11.683389 [CATrainingPosCal] consider 1 rank data
2535 13:08:11.687194 u2DelayCellTimex100 = 270/100 ps
2536 13:08:11.690228 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2537 13:08:11.693456 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2538 13:08:11.700356 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2539 13:08:11.703534 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2540 13:08:11.706801 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2541 13:08:11.710474 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2542 13:08:11.710567
2543 13:08:11.713306 CA PerBit enable=1, Macro0, CA PI delay=33
2544 13:08:11.713377
2545 13:08:11.716983 [CBTSetCACLKResult] CA Dly = 33
2546 13:08:11.717048 CS Dly: 7 (0~38)
2547 13:08:11.720013 ==
2548 13:08:11.720077 Dram Type= 6, Freq= 0, CH_0, rank 1
2549 13:08:11.726777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2550 13:08:11.726846 ==
2551 13:08:11.729912 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2552 13:08:11.737177 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2553 13:08:11.746274 [CA 0] Center 40 (10~70) winsize 61
2554 13:08:11.749073 [CA 1] Center 39 (9~70) winsize 62
2555 13:08:11.752902 [CA 2] Center 35 (5~66) winsize 62
2556 13:08:11.755920 [CA 3] Center 35 (5~66) winsize 62
2557 13:08:11.759591 [CA 4] Center 34 (4~65) winsize 62
2558 13:08:11.762591 [CA 5] Center 33 (3~63) winsize 61
2559 13:08:11.762659
2560 13:08:11.766007 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2561 13:08:11.766095
2562 13:08:11.769580 [CATrainingPosCal] consider 2 rank data
2563 13:08:11.772659 u2DelayCellTimex100 = 270/100 ps
2564 13:08:11.776139 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2565 13:08:11.782375 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2566 13:08:11.785972 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2567 13:08:11.789747 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2568 13:08:11.792744 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2569 13:08:11.796020 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2570 13:08:11.796085
2571 13:08:11.799112 CA PerBit enable=1, Macro0, CA PI delay=33
2572 13:08:11.799179
2573 13:08:11.802493 [CBTSetCACLKResult] CA Dly = 33
2574 13:08:11.802561 CS Dly: 8 (0~40)
2575 13:08:11.805961
2576 13:08:11.809349 ----->DramcWriteLeveling(PI) begin...
2577 13:08:11.809418 ==
2578 13:08:11.812860 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 13:08:11.816320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 13:08:11.816385 ==
2581 13:08:11.819619 Write leveling (Byte 0): 32 => 32
2582 13:08:11.822846 Write leveling (Byte 1): 29 => 29
2583 13:08:11.825876 DramcWriteLeveling(PI) end<-----
2584 13:08:11.825942
2585 13:08:11.825997 ==
2586 13:08:11.829512 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 13:08:11.832513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 13:08:11.832576 ==
2589 13:08:11.836107 [Gating] SW mode calibration
2590 13:08:11.843003 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2591 13:08:11.849199 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2592 13:08:11.852915 0 15 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
2593 13:08:11.856066 0 15 4 | B1->B0 | 2828 3333 | 1 0 | (1 1) (0 0)
2594 13:08:11.859244 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 13:08:11.865915 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 13:08:11.869510 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 13:08:11.872771 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 13:08:11.879314 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2599 13:08:11.882605 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2600 13:08:11.885928 1 0 0 | B1->B0 | 3131 2a2a | 0 0 | (0 0) (1 0)
2601 13:08:11.893052 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 13:08:11.896158 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 13:08:11.899149 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 13:08:11.905852 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 13:08:11.909571 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 13:08:11.912715 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 13:08:11.919776 1 0 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2608 13:08:11.922979 1 1 0 | B1->B0 | 2d2d 3c3c | 0 0 | (0 0) (1 1)
2609 13:08:11.926233 1 1 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2610 13:08:11.932786 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 13:08:11.936250 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 13:08:11.939393 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 13:08:11.943292 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 13:08:11.949733 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 13:08:11.952719 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2616 13:08:11.956289 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2617 13:08:11.962578 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2618 13:08:11.966370 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 13:08:11.969687 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 13:08:11.976028 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 13:08:11.979608 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 13:08:11.982591 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 13:08:11.989311 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 13:08:11.992959 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 13:08:11.996399 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 13:08:12.002809 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 13:08:12.006201 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 13:08:12.009298 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 13:08:12.016068 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 13:08:12.019593 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 13:08:12.022857 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2632 13:08:12.029941 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2633 13:08:12.030010 Total UI for P1: 0, mck2ui 16
2634 13:08:12.035951 best dqsien dly found for B0: ( 1, 3, 28)
2635 13:08:12.039461 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2636 13:08:12.042734 Total UI for P1: 0, mck2ui 16
2637 13:08:12.046079 best dqsien dly found for B1: ( 1, 4, 0)
2638 13:08:12.049111 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2639 13:08:12.052812 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2640 13:08:12.052875
2641 13:08:12.055923 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2642 13:08:12.059627 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2643 13:08:12.062867 [Gating] SW calibration Done
2644 13:08:12.062942 ==
2645 13:08:12.066383 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 13:08:12.069616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 13:08:12.069698 ==
2648 13:08:12.072525 RX Vref Scan: 0
2649 13:08:12.072600
2650 13:08:12.072655 RX Vref 0 -> 0, step: 1
2651 13:08:12.076182
2652 13:08:12.076246 RX Delay -40 -> 252, step: 8
2653 13:08:12.082702 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2654 13:08:12.086094 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2655 13:08:12.089115 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2656 13:08:12.092696 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2657 13:08:12.095694 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2658 13:08:12.099257 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2659 13:08:12.105824 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2660 13:08:12.109394 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
2661 13:08:12.112855 iDelay=200, Bit 8, Center 95 (16 ~ 175) 160
2662 13:08:12.115820 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2663 13:08:12.118971 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2664 13:08:12.125824 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2665 13:08:12.129390 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2666 13:08:12.132378 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2667 13:08:12.136294 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2668 13:08:12.139281 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2669 13:08:12.142738 ==
2670 13:08:12.142832 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 13:08:12.149583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 13:08:12.149676 ==
2673 13:08:12.149760 DQS Delay:
2674 13:08:12.153111 DQS0 = 0, DQS1 = 0
2675 13:08:12.153198 DQM Delay:
2676 13:08:12.156132 DQM0 = 111, DQM1 = 103
2677 13:08:12.156194 DQ Delay:
2678 13:08:12.159347 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2679 13:08:12.162789 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =119
2680 13:08:12.165986 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =99
2681 13:08:12.169857 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2682 13:08:12.169921
2683 13:08:12.169974
2684 13:08:12.170043 ==
2685 13:08:12.172729 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 13:08:12.175791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 13:08:12.179584 ==
2688 13:08:12.179647
2689 13:08:12.179699
2690 13:08:12.179749 TX Vref Scan disable
2691 13:08:12.182484 == TX Byte 0 ==
2692 13:08:12.185704 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2693 13:08:12.189231 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2694 13:08:12.192931 == TX Byte 1 ==
2695 13:08:12.195578 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2696 13:08:12.199371 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2697 13:08:12.202719 ==
2698 13:08:12.202810 Dram Type= 6, Freq= 0, CH_0, rank 0
2699 13:08:12.208913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2700 13:08:12.209011 ==
2701 13:08:12.220472 TX Vref=22, minBit 12, minWin=25, winSum=418
2702 13:08:12.223457 TX Vref=24, minBit 1, minWin=26, winSum=421
2703 13:08:12.227210 TX Vref=26, minBit 8, minWin=26, winSum=434
2704 13:08:12.230212 TX Vref=28, minBit 10, minWin=26, winSum=433
2705 13:08:12.233416 TX Vref=30, minBit 8, minWin=26, winSum=438
2706 13:08:12.240938 TX Vref=32, minBit 1, minWin=26, winSum=429
2707 13:08:12.243753 [TxChooseVref] Worse bit 8, Min win 26, Win sum 438, Final Vref 30
2708 13:08:12.243844
2709 13:08:12.246881 Final TX Range 1 Vref 30
2710 13:08:12.246972
2711 13:08:12.247053 ==
2712 13:08:12.250685 Dram Type= 6, Freq= 0, CH_0, rank 0
2713 13:08:12.253860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2714 13:08:12.253953 ==
2715 13:08:12.254036
2716 13:08:12.257372
2717 13:08:12.257446 TX Vref Scan disable
2718 13:08:12.260620 == TX Byte 0 ==
2719 13:08:12.263636 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2720 13:08:12.267247 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2721 13:08:12.270557 == TX Byte 1 ==
2722 13:08:12.273524 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2723 13:08:12.277118 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2724 13:08:12.280594
2725 13:08:12.280662 [DATLAT]
2726 13:08:12.280718 Freq=1200, CH0 RK0
2727 13:08:12.280771
2728 13:08:12.283551 DATLAT Default: 0xd
2729 13:08:12.283612 0, 0xFFFF, sum = 0
2730 13:08:12.286973 1, 0xFFFF, sum = 0
2731 13:08:12.287038 2, 0xFFFF, sum = 0
2732 13:08:12.290827 3, 0xFFFF, sum = 0
2733 13:08:12.290895 4, 0xFFFF, sum = 0
2734 13:08:12.293751 5, 0xFFFF, sum = 0
2735 13:08:12.293814 6, 0xFFFF, sum = 0
2736 13:08:12.297484 7, 0xFFFF, sum = 0
2737 13:08:12.300303 8, 0xFFFF, sum = 0
2738 13:08:12.300380 9, 0xFFFF, sum = 0
2739 13:08:12.303956 10, 0xFFFF, sum = 0
2740 13:08:12.304074 11, 0xFFFF, sum = 0
2741 13:08:12.307096 12, 0x0, sum = 1
2742 13:08:12.307196 13, 0x0, sum = 2
2743 13:08:12.310623 14, 0x0, sum = 3
2744 13:08:12.310698 15, 0x0, sum = 4
2745 13:08:12.310757 best_step = 13
2746 13:08:12.310810
2747 13:08:12.313689 ==
2748 13:08:12.317059 Dram Type= 6, Freq= 0, CH_0, rank 0
2749 13:08:12.320645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2750 13:08:12.320721 ==
2751 13:08:12.320779 RX Vref Scan: 1
2752 13:08:12.320832
2753 13:08:12.323882 Set Vref Range= 32 -> 127
2754 13:08:12.323956
2755 13:08:12.326941 RX Vref 32 -> 127, step: 1
2756 13:08:12.327011
2757 13:08:12.330589 RX Delay -37 -> 252, step: 4
2758 13:08:12.330663
2759 13:08:12.333734 Set Vref, RX VrefLevel [Byte0]: 32
2760 13:08:12.337354 [Byte1]: 32
2761 13:08:12.337428
2762 13:08:12.340347 Set Vref, RX VrefLevel [Byte0]: 33
2763 13:08:12.344031 [Byte1]: 33
2764 13:08:12.347031
2765 13:08:12.347106 Set Vref, RX VrefLevel [Byte0]: 34
2766 13:08:12.350042 [Byte1]: 34
2767 13:08:12.355098
2768 13:08:12.355173 Set Vref, RX VrefLevel [Byte0]: 35
2769 13:08:12.358456 [Byte1]: 35
2770 13:08:12.362846
2771 13:08:12.362921 Set Vref, RX VrefLevel [Byte0]: 36
2772 13:08:12.365999 [Byte1]: 36
2773 13:08:12.370674
2774 13:08:12.370795 Set Vref, RX VrefLevel [Byte0]: 37
2775 13:08:12.374363 [Byte1]: 37
2776 13:08:12.379218
2777 13:08:12.379292 Set Vref, RX VrefLevel [Byte0]: 38
2778 13:08:12.382175 [Byte1]: 38
2779 13:08:12.387183
2780 13:08:12.387258 Set Vref, RX VrefLevel [Byte0]: 39
2781 13:08:12.390589 [Byte1]: 39
2782 13:08:12.394722
2783 13:08:12.394797 Set Vref, RX VrefLevel [Byte0]: 40
2784 13:08:12.398354 [Byte1]: 40
2785 13:08:12.403179
2786 13:08:12.403253 Set Vref, RX VrefLevel [Byte0]: 41
2787 13:08:12.406026 [Byte1]: 41
2788 13:08:12.410870
2789 13:08:12.410944 Set Vref, RX VrefLevel [Byte0]: 42
2790 13:08:12.413971 [Byte1]: 42
2791 13:08:12.418734
2792 13:08:12.418808 Set Vref, RX VrefLevel [Byte0]: 43
2793 13:08:12.422375 [Byte1]: 43
2794 13:08:12.427207
2795 13:08:12.427282 Set Vref, RX VrefLevel [Byte0]: 44
2796 13:08:12.430263 [Byte1]: 44
2797 13:08:12.434809
2798 13:08:12.434885 Set Vref, RX VrefLevel [Byte0]: 45
2799 13:08:12.438048 [Byte1]: 45
2800 13:08:12.442991
2801 13:08:12.443066 Set Vref, RX VrefLevel [Byte0]: 46
2802 13:08:12.445953 [Byte1]: 46
2803 13:08:12.450854
2804 13:08:12.450929 Set Vref, RX VrefLevel [Byte0]: 47
2805 13:08:12.454608 [Byte1]: 47
2806 13:08:12.459174
2807 13:08:12.459249 Set Vref, RX VrefLevel [Byte0]: 48
2808 13:08:12.462027 [Byte1]: 48
2809 13:08:12.467108
2810 13:08:12.467183 Set Vref, RX VrefLevel [Byte0]: 49
2811 13:08:12.469997 [Byte1]: 49
2812 13:08:12.475096
2813 13:08:12.475171 Set Vref, RX VrefLevel [Byte0]: 50
2814 13:08:12.478486 [Byte1]: 50
2815 13:08:12.482773
2816 13:08:12.482848 Set Vref, RX VrefLevel [Byte0]: 51
2817 13:08:12.486072 [Byte1]: 51
2818 13:08:12.491477
2819 13:08:12.491552 Set Vref, RX VrefLevel [Byte0]: 52
2820 13:08:12.494572 [Byte1]: 52
2821 13:08:12.499100
2822 13:08:12.499175 Set Vref, RX VrefLevel [Byte0]: 53
2823 13:08:12.502374 [Byte1]: 53
2824 13:08:12.507151
2825 13:08:12.507225 Set Vref, RX VrefLevel [Byte0]: 54
2826 13:08:12.510251 [Byte1]: 54
2827 13:08:12.514830
2828 13:08:12.514904 Set Vref, RX VrefLevel [Byte0]: 55
2829 13:08:12.518760 [Byte1]: 55
2830 13:08:12.523367
2831 13:08:12.523442 Set Vref, RX VrefLevel [Byte0]: 56
2832 13:08:12.526478 [Byte1]: 56
2833 13:08:12.531376
2834 13:08:12.531451 Set Vref, RX VrefLevel [Byte0]: 57
2835 13:08:12.534575 [Byte1]: 57
2836 13:08:12.539272
2837 13:08:12.539347 Set Vref, RX VrefLevel [Byte0]: 58
2838 13:08:12.542534 [Byte1]: 58
2839 13:08:12.547204
2840 13:08:12.547279 Set Vref, RX VrefLevel [Byte0]: 59
2841 13:08:12.550328 [Byte1]: 59
2842 13:08:12.554844
2843 13:08:12.554919 Set Vref, RX VrefLevel [Byte0]: 60
2844 13:08:12.558021 [Byte1]: 60
2845 13:08:12.563117
2846 13:08:12.563192 Set Vref, RX VrefLevel [Byte0]: 61
2847 13:08:12.566422 [Byte1]: 61
2848 13:08:12.571218
2849 13:08:12.571292 Set Vref, RX VrefLevel [Byte0]: 62
2850 13:08:12.574255 [Byte1]: 62
2851 13:08:12.578816
2852 13:08:12.578907 Set Vref, RX VrefLevel [Byte0]: 63
2853 13:08:12.582450 [Byte1]: 63
2854 13:08:12.586797
2855 13:08:12.586872 Set Vref, RX VrefLevel [Byte0]: 64
2856 13:08:12.590349 [Byte1]: 64
2857 13:08:12.595110
2858 13:08:12.595204 Set Vref, RX VrefLevel [Byte0]: 65
2859 13:08:12.598510 [Byte1]: 65
2860 13:08:12.602726
2861 13:08:12.602819 Set Vref, RX VrefLevel [Byte0]: 66
2862 13:08:12.606538 [Byte1]: 66
2863 13:08:12.611166
2864 13:08:12.611260 Set Vref, RX VrefLevel [Byte0]: 67
2865 13:08:12.614298 [Byte1]: 67
2866 13:08:12.618677
2867 13:08:12.618773 Set Vref, RX VrefLevel [Byte0]: 68
2868 13:08:12.621948 [Byte1]: 68
2869 13:08:12.627007
2870 13:08:12.627099 Set Vref, RX VrefLevel [Byte0]: 69
2871 13:08:12.630465 [Byte1]: 69
2872 13:08:12.635029
2873 13:08:12.635095 Set Vref, RX VrefLevel [Byte0]: 70
2874 13:08:12.638531 [Byte1]: 70
2875 13:08:12.642703
2876 13:08:12.642768 Set Vref, RX VrefLevel [Byte0]: 71
2877 13:08:12.646108 [Byte1]: 71
2878 13:08:12.650785
2879 13:08:12.650859 Set Vref, RX VrefLevel [Byte0]: 72
2880 13:08:12.654349 [Byte1]: 72
2881 13:08:12.659007
2882 13:08:12.659070 Set Vref, RX VrefLevel [Byte0]: 73
2883 13:08:12.662628 [Byte1]: 73
2884 13:08:12.667146
2885 13:08:12.667236 Final RX Vref Byte 0 = 61 to rank0
2886 13:08:12.670767 Final RX Vref Byte 1 = 51 to rank0
2887 13:08:12.673589 Final RX Vref Byte 0 = 61 to rank1
2888 13:08:12.676716 Final RX Vref Byte 1 = 51 to rank1==
2889 13:08:12.680390 Dram Type= 6, Freq= 0, CH_0, rank 0
2890 13:08:12.686971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 13:08:12.687063 ==
2892 13:08:12.687148 DQS Delay:
2893 13:08:12.687228 DQS0 = 0, DQS1 = 0
2894 13:08:12.690582 DQM Delay:
2895 13:08:12.690669 DQM0 = 112, DQM1 = 101
2896 13:08:12.693789 DQ Delay:
2897 13:08:12.697252 DQ0 =110, DQ1 =112, DQ2 =112, DQ3 =108
2898 13:08:12.700147 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2899 13:08:12.703681 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2900 13:08:12.707074 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =110
2901 13:08:12.707165
2902 13:08:12.707246
2903 13:08:12.713995 [DQSOSCAuto] RK0, (LSB)MR18= 0xfefd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
2904 13:08:12.717563 CH0 RK0: MR19=303, MR18=FEFD
2905 13:08:12.723676 CH0_RK0: MR19=0x303, MR18=0xFEFD, DQSOSC=410, MR23=63, INC=39, DEC=26
2906 13:08:12.723768
2907 13:08:12.727113 ----->DramcWriteLeveling(PI) begin...
2908 13:08:12.727205 ==
2909 13:08:12.730212 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 13:08:12.733951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 13:08:12.734042 ==
2912 13:08:12.737001 Write leveling (Byte 0): 32 => 32
2913 13:08:12.740067 Write leveling (Byte 1): 31 => 31
2914 13:08:12.743601 DramcWriteLeveling(PI) end<-----
2915 13:08:12.743663
2916 13:08:12.743717 ==
2917 13:08:12.746683 Dram Type= 6, Freq= 0, CH_0, rank 1
2918 13:08:12.753877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2919 13:08:12.753965 ==
2920 13:08:12.754046 [Gating] SW mode calibration
2921 13:08:12.763643 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2922 13:08:12.767279 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2923 13:08:12.770750 0 15 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
2924 13:08:12.776774 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 13:08:12.780841 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 13:08:12.783741 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 13:08:12.790490 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 13:08:12.793518 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2929 13:08:12.797274 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2930 13:08:12.803711 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (0 1) (0 0)
2931 13:08:12.807473 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2932 13:08:12.810743 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 13:08:12.817044 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 13:08:12.820265 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 13:08:12.824284 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 13:08:12.827286 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2937 13:08:12.833663 1 0 24 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
2938 13:08:12.837286 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2939 13:08:12.840344 1 1 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2940 13:08:12.846904 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 13:08:12.850580 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 13:08:12.853591 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 13:08:12.860132 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 13:08:12.863882 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 13:08:12.867176 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2946 13:08:12.873662 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2947 13:08:12.876854 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2948 13:08:12.880743 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 13:08:12.887083 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 13:08:12.889933 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 13:08:12.893296 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 13:08:12.900363 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 13:08:12.903468 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 13:08:12.906953 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 13:08:12.913280 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 13:08:12.916430 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 13:08:12.920067 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 13:08:12.926820 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 13:08:12.929999 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 13:08:12.933540 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 13:08:12.940240 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 13:08:12.943118 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2963 13:08:12.946732 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2964 13:08:12.950262 Total UI for P1: 0, mck2ui 16
2965 13:08:12.953565 best dqsien dly found for B0: ( 1, 3, 28)
2966 13:08:12.956491 Total UI for P1: 0, mck2ui 16
2967 13:08:12.960090 best dqsien dly found for B1: ( 1, 3, 30)
2968 13:08:12.963353 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2969 13:08:12.966724 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2970 13:08:12.966812
2971 13:08:12.969759 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2972 13:08:12.976516 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2973 13:08:12.976614 [Gating] SW calibration Done
2974 13:08:12.976744 ==
2975 13:08:12.979601 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 13:08:12.986715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 13:08:12.986816 ==
2978 13:08:12.986922 RX Vref Scan: 0
2979 13:08:12.987016
2980 13:08:12.990045 RX Vref 0 -> 0, step: 1
2981 13:08:12.990169
2982 13:08:12.993384 RX Delay -40 -> 252, step: 8
2983 13:08:12.996909 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2984 13:08:12.999927 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2985 13:08:13.003358 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
2986 13:08:13.009915 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2987 13:08:13.012995 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2988 13:08:13.016895 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2989 13:08:13.019923 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2990 13:08:13.023266 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2991 13:08:13.026818 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2992 13:08:13.033074 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2993 13:08:13.036519 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2994 13:08:13.040078 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2995 13:08:13.043072 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2996 13:08:13.046565 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2997 13:08:13.053168 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2998 13:08:13.056687 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2999 13:08:13.056786 ==
3000 13:08:13.059764 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 13:08:13.063114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 13:08:13.063219 ==
3003 13:08:13.066788 DQS Delay:
3004 13:08:13.066860 DQS0 = 0, DQS1 = 0
3005 13:08:13.066920 DQM Delay:
3006 13:08:13.070211 DQM0 = 111, DQM1 = 101
3007 13:08:13.070284 DQ Delay:
3008 13:08:13.073017 DQ0 =111, DQ1 =111, DQ2 =107, DQ3 =107
3009 13:08:13.076121 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
3010 13:08:13.079690 DQ8 =91, DQ9 =83, DQ10 =107, DQ11 =95
3011 13:08:13.083162 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =107
3012 13:08:13.086158
3013 13:08:13.086228
3014 13:08:13.086310 ==
3015 13:08:13.089478 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 13:08:13.093069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 13:08:13.093147 ==
3018 13:08:13.093206
3019 13:08:13.093261
3020 13:08:13.096602 TX Vref Scan disable
3021 13:08:13.096678 == TX Byte 0 ==
3022 13:08:13.103226 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3023 13:08:13.106453 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3024 13:08:13.106531 == TX Byte 1 ==
3025 13:08:13.113031 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3026 13:08:13.116521 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3027 13:08:13.116619 ==
3028 13:08:13.119693 Dram Type= 6, Freq= 0, CH_0, rank 1
3029 13:08:13.123034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 13:08:13.123100 ==
3031 13:08:13.135688 TX Vref=22, minBit 1, minWin=26, winSum=428
3032 13:08:13.138733 TX Vref=24, minBit 2, minWin=26, winSum=429
3033 13:08:13.142481 TX Vref=26, minBit 12, minWin=26, winSum=436
3034 13:08:13.145548 TX Vref=28, minBit 14, minWin=26, winSum=444
3035 13:08:13.148836 TX Vref=30, minBit 3, minWin=27, winSum=440
3036 13:08:13.152584 TX Vref=32, minBit 1, minWin=27, winSum=443
3037 13:08:13.158822 [TxChooseVref] Worse bit 1, Min win 27, Win sum 443, Final Vref 32
3038 13:08:13.158917
3039 13:08:13.162315 Final TX Range 1 Vref 32
3040 13:08:13.162405
3041 13:08:13.162487 ==
3042 13:08:13.165827 Dram Type= 6, Freq= 0, CH_0, rank 1
3043 13:08:13.169038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 13:08:13.169122 ==
3045 13:08:13.169179
3046 13:08:13.172283
3047 13:08:13.172371 TX Vref Scan disable
3048 13:08:13.175626 == TX Byte 0 ==
3049 13:08:13.178757 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3050 13:08:13.182310 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3051 13:08:13.185305 == TX Byte 1 ==
3052 13:08:13.188869 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3053 13:08:13.192304 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3054 13:08:13.192369
3055 13:08:13.195309 [DATLAT]
3056 13:08:13.195379 Freq=1200, CH0 RK1
3057 13:08:13.195437
3058 13:08:13.198786 DATLAT Default: 0xd
3059 13:08:13.198874 0, 0xFFFF, sum = 0
3060 13:08:13.202307 1, 0xFFFF, sum = 0
3061 13:08:13.202379 2, 0xFFFF, sum = 0
3062 13:08:13.205245 3, 0xFFFF, sum = 0
3063 13:08:13.205307 4, 0xFFFF, sum = 0
3064 13:08:13.208681 5, 0xFFFF, sum = 0
3065 13:08:13.208778 6, 0xFFFF, sum = 0
3066 13:08:13.212166 7, 0xFFFF, sum = 0
3067 13:08:13.212262 8, 0xFFFF, sum = 0
3068 13:08:13.215594 9, 0xFFFF, sum = 0
3069 13:08:13.218608 10, 0xFFFF, sum = 0
3070 13:08:13.218673 11, 0xFFFF, sum = 0
3071 13:08:13.222449 12, 0x0, sum = 1
3072 13:08:13.222519 13, 0x0, sum = 2
3073 13:08:13.222574 14, 0x0, sum = 3
3074 13:08:13.225826 15, 0x0, sum = 4
3075 13:08:13.225913 best_step = 13
3076 13:08:13.226003
3077 13:08:13.228876 ==
3078 13:08:13.228936 Dram Type= 6, Freq= 0, CH_0, rank 1
3079 13:08:13.235516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3080 13:08:13.235606 ==
3081 13:08:13.235679 RX Vref Scan: 0
3082 13:08:13.235738
3083 13:08:13.238639 RX Vref 0 -> 0, step: 1
3084 13:08:13.238702
3085 13:08:13.241927 RX Delay -37 -> 252, step: 4
3086 13:08:13.245687 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3087 13:08:13.252294 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3088 13:08:13.255646 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3089 13:08:13.259103 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3090 13:08:13.262300 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3091 13:08:13.265630 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3092 13:08:13.268838 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3093 13:08:13.275460 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3094 13:08:13.278605 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3095 13:08:13.282026 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3096 13:08:13.285580 iDelay=195, Bit 10, Center 102 (31 ~ 174) 144
3097 13:08:13.288697 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3098 13:08:13.295303 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3099 13:08:13.298648 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3100 13:08:13.302552 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3101 13:08:13.305572 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3102 13:08:13.305659 ==
3103 13:08:13.308666 Dram Type= 6, Freq= 0, CH_0, rank 1
3104 13:08:13.315436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 13:08:13.315510 ==
3106 13:08:13.315567 DQS Delay:
3107 13:08:13.315621 DQS0 = 0, DQS1 = 0
3108 13:08:13.318778 DQM Delay:
3109 13:08:13.318839 DQM0 = 110, DQM1 = 100
3110 13:08:13.322172 DQ Delay:
3111 13:08:13.325377 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3112 13:08:13.328723 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3113 13:08:13.332017 DQ8 =90, DQ9 =82, DQ10 =102, DQ11 =92
3114 13:08:13.335284 DQ12 =108, DQ13 =106, DQ14 =114, DQ15 =110
3115 13:08:13.335375
3116 13:08:13.335459
3117 13:08:13.342087 [DQSOSCAuto] RK1, (LSB)MR18= 0x16fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 401 ps
3118 13:08:13.345715 CH0 RK1: MR19=403, MR18=16FE
3119 13:08:13.351965 CH0_RK1: MR19=0x403, MR18=0x16FE, DQSOSC=401, MR23=63, INC=40, DEC=27
3120 13:08:13.355810 [RxdqsGatingPostProcess] freq 1200
3121 13:08:13.361953 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3122 13:08:13.365234 best DQS0 dly(2T, 0.5T) = (0, 11)
3123 13:08:13.365325 best DQS1 dly(2T, 0.5T) = (0, 12)
3124 13:08:13.368921 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3125 13:08:13.372467 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3126 13:08:13.375335 best DQS0 dly(2T, 0.5T) = (0, 11)
3127 13:08:13.378868 best DQS1 dly(2T, 0.5T) = (0, 11)
3128 13:08:13.382498 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3129 13:08:13.386013 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3130 13:08:13.388591 Pre-setting of DQS Precalculation
3131 13:08:13.395614 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3132 13:08:13.395691 ==
3133 13:08:13.398469 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 13:08:13.402293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 13:08:13.402372 ==
3136 13:08:13.408480 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3137 13:08:13.411687 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3138 13:08:13.421705 [CA 0] Center 37 (7~67) winsize 61
3139 13:08:13.425079 [CA 1] Center 37 (7~68) winsize 62
3140 13:08:13.428372 [CA 2] Center 34 (4~64) winsize 61
3141 13:08:13.431689 [CA 3] Center 34 (4~64) winsize 61
3142 13:08:13.434916 [CA 4] Center 34 (4~64) winsize 61
3143 13:08:13.438241 [CA 5] Center 33 (3~63) winsize 61
3144 13:08:13.438374
3145 13:08:13.441422 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3146 13:08:13.441516
3147 13:08:13.445173 [CATrainingPosCal] consider 1 rank data
3148 13:08:13.448106 u2DelayCellTimex100 = 270/100 ps
3149 13:08:13.451730 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3150 13:08:13.454732 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3151 13:08:13.461435 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3152 13:08:13.464495 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3153 13:08:13.468183 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3154 13:08:13.471833 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3155 13:08:13.471899
3156 13:08:13.474817 CA PerBit enable=1, Macro0, CA PI delay=33
3157 13:08:13.474880
3158 13:08:13.478027 [CBTSetCACLKResult] CA Dly = 33
3159 13:08:13.478086 CS Dly: 6 (0~37)
3160 13:08:13.481485 ==
3161 13:08:13.484565 Dram Type= 6, Freq= 0, CH_1, rank 1
3162 13:08:13.488150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3163 13:08:13.488212 ==
3164 13:08:13.491299 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3165 13:08:13.497703 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3166 13:08:13.506957 [CA 0] Center 37 (7~67) winsize 61
3167 13:08:13.510628 [CA 1] Center 37 (7~68) winsize 62
3168 13:08:13.513981 [CA 2] Center 34 (4~65) winsize 62
3169 13:08:13.516942 [CA 3] Center 33 (3~64) winsize 62
3170 13:08:13.520319 [CA 4] Center 34 (4~65) winsize 62
3171 13:08:13.523993 [CA 5] Center 32 (2~63) winsize 62
3172 13:08:13.524061
3173 13:08:13.527163 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3174 13:08:13.527227
3175 13:08:13.530712 [CATrainingPosCal] consider 2 rank data
3176 13:08:13.533744 u2DelayCellTimex100 = 270/100 ps
3177 13:08:13.537142 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3178 13:08:13.540369 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3179 13:08:13.547008 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3180 13:08:13.550362 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3181 13:08:13.554001 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3182 13:08:13.556740 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3183 13:08:13.556804
3184 13:08:13.560499 CA PerBit enable=1, Macro0, CA PI delay=33
3185 13:08:13.560561
3186 13:08:13.563719 [CBTSetCACLKResult] CA Dly = 33
3187 13:08:13.563780 CS Dly: 7 (0~40)
3188 13:08:13.563833
3189 13:08:13.567527 ----->DramcWriteLeveling(PI) begin...
3190 13:08:13.570190 ==
3191 13:08:13.573648 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 13:08:13.577090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 13:08:13.577182 ==
3194 13:08:13.580159 Write leveling (Byte 0): 26 => 26
3195 13:08:13.583501 Write leveling (Byte 1): 28 => 28
3196 13:08:13.586950 DramcWriteLeveling(PI) end<-----
3197 13:08:13.587011
3198 13:08:13.587063 ==
3199 13:08:13.590159 Dram Type= 6, Freq= 0, CH_1, rank 0
3200 13:08:13.593170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3201 13:08:13.593240 ==
3202 13:08:13.597008 [Gating] SW mode calibration
3203 13:08:13.603198 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3204 13:08:13.609864 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3205 13:08:13.613296 0 15 0 | B1->B0 | 2c2c 2828 | 0 1 | (0 0) (0 0)
3206 13:08:13.616377 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 13:08:13.623112 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 13:08:13.626582 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 13:08:13.629661 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 13:08:13.636809 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 13:08:13.640064 0 15 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3212 13:08:13.643038 0 15 28 | B1->B0 | 2828 2b2b | 0 0 | (1 0) (0 0)
3213 13:08:13.649504 1 0 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
3214 13:08:13.653207 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 13:08:13.656686 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 13:08:13.663205 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 13:08:13.666470 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 13:08:13.669964 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 13:08:13.673013 1 0 24 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
3220 13:08:13.679952 1 0 28 | B1->B0 | 4141 4545 | 0 0 | (0 0) (0 0)
3221 13:08:13.682953 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 13:08:13.686682 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 13:08:13.693143 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 13:08:13.696061 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 13:08:13.699185 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 13:08:13.706543 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 13:08:13.709485 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 13:08:13.712522 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3229 13:08:13.719334 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3230 13:08:13.722443 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 13:08:13.726268 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 13:08:13.732641 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 13:08:13.735796 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 13:08:13.739405 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 13:08:13.746330 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 13:08:13.749490 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 13:08:13.752697 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 13:08:13.759153 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 13:08:13.762373 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 13:08:13.766048 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 13:08:13.772665 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 13:08:13.775646 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 13:08:13.779268 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 13:08:13.785793 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3245 13:08:13.789067 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3246 13:08:13.792057 Total UI for P1: 0, mck2ui 16
3247 13:08:13.795843 best dqsien dly found for B0: ( 1, 3, 28)
3248 13:08:13.798712 Total UI for P1: 0, mck2ui 16
3249 13:08:13.802567 best dqsien dly found for B1: ( 1, 3, 28)
3250 13:08:13.805368 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3251 13:08:13.809062 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3252 13:08:13.809129
3253 13:08:13.812148 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3254 13:08:13.815268 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3255 13:08:13.818987 [Gating] SW calibration Done
3256 13:08:13.819084 ==
3257 13:08:13.822213 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 13:08:13.825332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 13:08:13.828891 ==
3260 13:08:13.828955 RX Vref Scan: 0
3261 13:08:13.829008
3262 13:08:13.832374 RX Vref 0 -> 0, step: 1
3263 13:08:13.832438
3264 13:08:13.832491 RX Delay -40 -> 252, step: 8
3265 13:08:13.839043 iDelay=200, Bit 0, Center 119 (40 ~ 199) 160
3266 13:08:13.842733 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3267 13:08:13.845333 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3268 13:08:13.848819 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
3269 13:08:13.851901 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3270 13:08:13.858877 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3271 13:08:13.862468 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3272 13:08:13.865628 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3273 13:08:13.868931 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3274 13:08:13.872205 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3275 13:08:13.878871 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3276 13:08:13.881933 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3277 13:08:13.885754 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3278 13:08:13.888502 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3279 13:08:13.892371 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3280 13:08:13.899049 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3281 13:08:13.899140 ==
3282 13:08:13.902207 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 13:08:13.905681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 13:08:13.905773 ==
3285 13:08:13.905854 DQS Delay:
3286 13:08:13.908608 DQS0 = 0, DQS1 = 0
3287 13:08:13.908673 DQM Delay:
3288 13:08:13.911901 DQM0 = 113, DQM1 = 106
3289 13:08:13.911964 DQ Delay:
3290 13:08:13.915444 DQ0 =119, DQ1 =107, DQ2 =99, DQ3 =111
3291 13:08:13.918588 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3292 13:08:13.922303 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =99
3293 13:08:13.925332 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3294 13:08:13.925394
3295 13:08:13.925450
3296 13:08:13.928351 ==
3297 13:08:13.928414 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 13:08:13.935319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 13:08:13.935407 ==
3300 13:08:13.935475
3301 13:08:13.935526
3302 13:08:13.938498 TX Vref Scan disable
3303 13:08:13.938562 == TX Byte 0 ==
3304 13:08:13.941902 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3305 13:08:13.948349 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3306 13:08:13.948413 == TX Byte 1 ==
3307 13:08:13.951931 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3308 13:08:13.958574 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3309 13:08:13.958641 ==
3310 13:08:13.961801 Dram Type= 6, Freq= 0, CH_1, rank 0
3311 13:08:13.964635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3312 13:08:13.964703 ==
3313 13:08:13.977102 TX Vref=22, minBit 10, minWin=24, winSum=408
3314 13:08:13.980641 TX Vref=24, minBit 11, minWin=24, winSum=411
3315 13:08:13.983744 TX Vref=26, minBit 8, minWin=25, winSum=421
3316 13:08:13.986799 TX Vref=28, minBit 9, minWin=25, winSum=423
3317 13:08:13.990345 TX Vref=30, minBit 9, minWin=24, winSum=423
3318 13:08:13.996872 TX Vref=32, minBit 9, minWin=25, winSum=425
3319 13:08:14.000358 [TxChooseVref] Worse bit 9, Min win 25, Win sum 425, Final Vref 32
3320 13:08:14.000455
3321 13:08:14.003306 Final TX Range 1 Vref 32
3322 13:08:14.003373
3323 13:08:14.003428 ==
3324 13:08:14.007060 Dram Type= 6, Freq= 0, CH_1, rank 0
3325 13:08:14.010484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3326 13:08:14.013139 ==
3327 13:08:14.013207
3328 13:08:14.013287
3329 13:08:14.013364 TX Vref Scan disable
3330 13:08:14.016964 == TX Byte 0 ==
3331 13:08:14.020321 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3332 13:08:14.026509 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3333 13:08:14.026577 == TX Byte 1 ==
3334 13:08:14.029992 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3335 13:08:14.036638 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3336 13:08:14.036704
3337 13:08:14.036758 [DATLAT]
3338 13:08:14.036808 Freq=1200, CH1 RK0
3339 13:08:14.036859
3340 13:08:14.039882 DATLAT Default: 0xd
3341 13:08:14.039941 0, 0xFFFF, sum = 0
3342 13:08:14.043268 1, 0xFFFF, sum = 0
3343 13:08:14.046483 2, 0xFFFF, sum = 0
3344 13:08:14.046544 3, 0xFFFF, sum = 0
3345 13:08:14.049699 4, 0xFFFF, sum = 0
3346 13:08:14.049760 5, 0xFFFF, sum = 0
3347 13:08:14.053113 6, 0xFFFF, sum = 0
3348 13:08:14.053174 7, 0xFFFF, sum = 0
3349 13:08:14.056894 8, 0xFFFF, sum = 0
3350 13:08:14.056965 9, 0xFFFF, sum = 0
3351 13:08:14.059744 10, 0xFFFF, sum = 0
3352 13:08:14.059813 11, 0xFFFF, sum = 0
3353 13:08:14.063655 12, 0x0, sum = 1
3354 13:08:14.063731 13, 0x0, sum = 2
3355 13:08:14.067024 14, 0x0, sum = 3
3356 13:08:14.067100 15, 0x0, sum = 4
3357 13:08:14.069834 best_step = 13
3358 13:08:14.069908
3359 13:08:14.069965 ==
3360 13:08:14.072888 Dram Type= 6, Freq= 0, CH_1, rank 0
3361 13:08:14.076268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3362 13:08:14.076344 ==
3363 13:08:14.076402 RX Vref Scan: 1
3364 13:08:14.076467
3365 13:08:14.079565 Set Vref Range= 32 -> 127
3366 13:08:14.079640
3367 13:08:14.082838 RX Vref 32 -> 127, step: 1
3368 13:08:14.082913
3369 13:08:14.086701 RX Delay -21 -> 252, step: 4
3370 13:08:14.086777
3371 13:08:14.089433 Set Vref, RX VrefLevel [Byte0]: 32
3372 13:08:14.093063 [Byte1]: 32
3373 13:08:14.093139
3374 13:08:14.096411 Set Vref, RX VrefLevel [Byte0]: 33
3375 13:08:14.099360 [Byte1]: 33
3376 13:08:14.103054
3377 13:08:14.103129 Set Vref, RX VrefLevel [Byte0]: 34
3378 13:08:14.106735 [Byte1]: 34
3379 13:08:14.111070
3380 13:08:14.111144 Set Vref, RX VrefLevel [Byte0]: 35
3381 13:08:14.114547 [Byte1]: 35
3382 13:08:14.118846
3383 13:08:14.118920 Set Vref, RX VrefLevel [Byte0]: 36
3384 13:08:14.122465 [Byte1]: 36
3385 13:08:14.126869
3386 13:08:14.126943 Set Vref, RX VrefLevel [Byte0]: 37
3387 13:08:14.130356 [Byte1]: 37
3388 13:08:14.134701
3389 13:08:14.134796 Set Vref, RX VrefLevel [Byte0]: 38
3390 13:08:14.138135 [Byte1]: 38
3391 13:08:14.142980
3392 13:08:14.143046 Set Vref, RX VrefLevel [Byte0]: 39
3393 13:08:14.146044 [Byte1]: 39
3394 13:08:14.150490
3395 13:08:14.150556 Set Vref, RX VrefLevel [Byte0]: 40
3396 13:08:14.153942 [Byte1]: 40
3397 13:08:14.158968
3398 13:08:14.159032 Set Vref, RX VrefLevel [Byte0]: 41
3399 13:08:14.162090 [Byte1]: 41
3400 13:08:14.166543
3401 13:08:14.166610 Set Vref, RX VrefLevel [Byte0]: 42
3402 13:08:14.169992 [Byte1]: 42
3403 13:08:14.175110
3404 13:08:14.175184 Set Vref, RX VrefLevel [Byte0]: 43
3405 13:08:14.178034 [Byte1]: 43
3406 13:08:14.182954
3407 13:08:14.183029 Set Vref, RX VrefLevel [Byte0]: 44
3408 13:08:14.186023 [Byte1]: 44
3409 13:08:14.190313
3410 13:08:14.190387 Set Vref, RX VrefLevel [Byte0]: 45
3411 13:08:14.193472 [Byte1]: 45
3412 13:08:14.198666
3413 13:08:14.198740 Set Vref, RX VrefLevel [Byte0]: 46
3414 13:08:14.201748 [Byte1]: 46
3415 13:08:14.206352
3416 13:08:14.206426 Set Vref, RX VrefLevel [Byte0]: 47
3417 13:08:14.209585 [Byte1]: 47
3418 13:08:14.213908
3419 13:08:14.213982 Set Vref, RX VrefLevel [Byte0]: 48
3420 13:08:14.217361 [Byte1]: 48
3421 13:08:14.221964
3422 13:08:14.222037 Set Vref, RX VrefLevel [Byte0]: 49
3423 13:08:14.225301 [Byte1]: 49
3424 13:08:14.229742
3425 13:08:14.229816 Set Vref, RX VrefLevel [Byte0]: 50
3426 13:08:14.233429 [Byte1]: 50
3427 13:08:14.238447
3428 13:08:14.238521 Set Vref, RX VrefLevel [Byte0]: 51
3429 13:08:14.241319 [Byte1]: 51
3430 13:08:14.245672
3431 13:08:14.245746 Set Vref, RX VrefLevel [Byte0]: 52
3432 13:08:14.248972 [Byte1]: 52
3433 13:08:14.253996
3434 13:08:14.254069 Set Vref, RX VrefLevel [Byte0]: 53
3435 13:08:14.256976 [Byte1]: 53
3436 13:08:14.261605
3437 13:08:14.261680 Set Vref, RX VrefLevel [Byte0]: 54
3438 13:08:14.264783 [Byte1]: 54
3439 13:08:14.269666
3440 13:08:14.269741 Set Vref, RX VrefLevel [Byte0]: 55
3441 13:08:14.273047 [Byte1]: 55
3442 13:08:14.277494
3443 13:08:14.277569 Set Vref, RX VrefLevel [Byte0]: 56
3444 13:08:14.281376 [Byte1]: 56
3445 13:08:14.285263
3446 13:08:14.285339 Set Vref, RX VrefLevel [Byte0]: 57
3447 13:08:14.288860 [Byte1]: 57
3448 13:08:14.293354
3449 13:08:14.293430 Set Vref, RX VrefLevel [Byte0]: 58
3450 13:08:14.296919 [Byte1]: 58
3451 13:08:14.301252
3452 13:08:14.301328 Set Vref, RX VrefLevel [Byte0]: 59
3453 13:08:14.304765 [Byte1]: 59
3454 13:08:14.309492
3455 13:08:14.309567 Set Vref, RX VrefLevel [Byte0]: 60
3456 13:08:14.312369 [Byte1]: 60
3457 13:08:14.316814
3458 13:08:14.316908 Set Vref, RX VrefLevel [Byte0]: 61
3459 13:08:14.323620 [Byte1]: 61
3460 13:08:14.323690
3461 13:08:14.326797 Set Vref, RX VrefLevel [Byte0]: 62
3462 13:08:14.330583 [Byte1]: 62
3463 13:08:14.330650
3464 13:08:14.333657 Set Vref, RX VrefLevel [Byte0]: 63
3465 13:08:14.337009 [Byte1]: 63
3466 13:08:14.341123
3467 13:08:14.341191 Set Vref, RX VrefLevel [Byte0]: 64
3468 13:08:14.344006 [Byte1]: 64
3469 13:08:14.348715
3470 13:08:14.348779 Set Vref, RX VrefLevel [Byte0]: 65
3471 13:08:14.352167 [Byte1]: 65
3472 13:08:14.356874
3473 13:08:14.356968 Final RX Vref Byte 0 = 53 to rank0
3474 13:08:14.360142 Final RX Vref Byte 1 = 48 to rank0
3475 13:08:14.363421 Final RX Vref Byte 0 = 53 to rank1
3476 13:08:14.366663 Final RX Vref Byte 1 = 48 to rank1==
3477 13:08:14.370030 Dram Type= 6, Freq= 0, CH_1, rank 0
3478 13:08:14.376883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 13:08:14.376960 ==
3480 13:08:14.377045 DQS Delay:
3481 13:08:14.377137 DQS0 = 0, DQS1 = 0
3482 13:08:14.380127 DQM Delay:
3483 13:08:14.380189 DQM0 = 114, DQM1 = 104
3484 13:08:14.383483 DQ Delay:
3485 13:08:14.386764 DQ0 =118, DQ1 =108, DQ2 =104, DQ3 =112
3486 13:08:14.389883 DQ4 =112, DQ5 =122, DQ6 =126, DQ7 =112
3487 13:08:14.393276 DQ8 =92, DQ9 =96, DQ10 =104, DQ11 =100
3488 13:08:14.396409 DQ12 =112, DQ13 =110, DQ14 =114, DQ15 =110
3489 13:08:14.396484
3490 13:08:14.396541
3491 13:08:14.406614 [DQSOSCAuto] RK0, (LSB)MR18= 0xf4fb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 415 ps
3492 13:08:14.406690 CH1 RK0: MR19=303, MR18=F4FB
3493 13:08:14.413193 CH1_RK0: MR19=0x303, MR18=0xF4FB, DQSOSC=412, MR23=63, INC=38, DEC=25
3494 13:08:14.413269
3495 13:08:14.416215 ----->DramcWriteLeveling(PI) begin...
3496 13:08:14.416306 ==
3497 13:08:14.419706 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 13:08:14.426325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 13:08:14.426401 ==
3500 13:08:14.429938 Write leveling (Byte 0): 24 => 24
3501 13:08:14.430013 Write leveling (Byte 1): 29 => 29
3502 13:08:14.432874 DramcWriteLeveling(PI) end<-----
3503 13:08:14.432949
3504 13:08:14.436239 ==
3505 13:08:14.436315 Dram Type= 6, Freq= 0, CH_1, rank 1
3506 13:08:14.442739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 13:08:14.442816 ==
3508 13:08:14.445977 [Gating] SW mode calibration
3509 13:08:14.452770 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3510 13:08:14.456479 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3511 13:08:14.462558 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
3512 13:08:14.465927 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 13:08:14.469228 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 13:08:14.475691 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 13:08:14.479370 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 13:08:14.482696 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
3517 13:08:14.489815 0 15 24 | B1->B0 | 3232 2323 | 0 0 | (0 1) (1 0)
3518 13:08:14.492744 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3519 13:08:14.495939 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 13:08:14.502600 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 13:08:14.505811 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 13:08:14.508864 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 13:08:14.515623 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 13:08:14.519338 1 0 20 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
3525 13:08:14.522436 1 0 24 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
3526 13:08:14.526040 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3527 13:08:14.532512 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 13:08:14.536075 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 13:08:14.539270 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 13:08:14.545701 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 13:08:14.549512 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 13:08:14.552327 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3533 13:08:14.559032 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3534 13:08:14.562473 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3535 13:08:14.565897 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 13:08:14.572170 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 13:08:14.575840 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 13:08:14.578768 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 13:08:14.585831 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 13:08:14.588760 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 13:08:14.592131 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 13:08:14.599057 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 13:08:14.602364 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 13:08:14.605663 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 13:08:14.612347 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 13:08:14.615480 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 13:08:14.618828 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 13:08:14.625085 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3549 13:08:14.628720 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3550 13:08:14.631965 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3551 13:08:14.635011 Total UI for P1: 0, mck2ui 16
3552 13:08:14.638418 best dqsien dly found for B0: ( 1, 3, 22)
3553 13:08:14.644987 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3554 13:08:14.645055 Total UI for P1: 0, mck2ui 16
3555 13:08:14.651558 best dqsien dly found for B1: ( 1, 3, 26)
3556 13:08:14.654755 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3557 13:08:14.658398 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3558 13:08:14.658463
3559 13:08:14.661906 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3560 13:08:14.664892 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3561 13:08:14.668103 [Gating] SW calibration Done
3562 13:08:14.668168 ==
3563 13:08:14.671575 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 13:08:14.675222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 13:08:14.675288 ==
3566 13:08:14.678334 RX Vref Scan: 0
3567 13:08:14.678423
3568 13:08:14.678503 RX Vref 0 -> 0, step: 1
3569 13:08:14.678580
3570 13:08:14.681779 RX Delay -40 -> 252, step: 8
3571 13:08:14.684972 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3572 13:08:14.691722 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3573 13:08:14.694991 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3574 13:08:14.698043 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3575 13:08:14.701461 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3576 13:08:14.704835 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3577 13:08:14.711760 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3578 13:08:14.714682 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3579 13:08:14.718402 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
3580 13:08:14.721499 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3581 13:08:14.725069 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3582 13:08:14.731560 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3583 13:08:14.734594 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3584 13:08:14.737836 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3585 13:08:14.741981 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3586 13:08:14.744583 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3587 13:08:14.744645 ==
3588 13:08:14.748289 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 13:08:14.754963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 13:08:14.755027 ==
3591 13:08:14.755084 DQS Delay:
3592 13:08:14.758063 DQS0 = 0, DQS1 = 0
3593 13:08:14.758177 DQM Delay:
3594 13:08:14.761434 DQM0 = 110, DQM1 = 106
3595 13:08:14.761495 DQ Delay:
3596 13:08:14.764719 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3597 13:08:14.768419 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3598 13:08:14.771396 DQ8 =91, DQ9 =95, DQ10 =111, DQ11 =99
3599 13:08:14.774520 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =115
3600 13:08:14.774586
3601 13:08:14.774638
3602 13:08:14.774687 ==
3603 13:08:14.778289 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 13:08:14.781098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 13:08:14.784635 ==
3606 13:08:14.784698
3607 13:08:14.784749
3608 13:08:14.784799 TX Vref Scan disable
3609 13:08:14.787896 == TX Byte 0 ==
3610 13:08:14.791059 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3611 13:08:14.794568 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3612 13:08:14.798088 == TX Byte 1 ==
3613 13:08:14.801482 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3614 13:08:14.804766 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3615 13:08:14.808248 ==
3616 13:08:14.808314 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 13:08:14.814078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 13:08:14.814193 ==
3619 13:08:14.825582 TX Vref=22, minBit 0, minWin=26, winSum=425
3620 13:08:14.829032 TX Vref=24, minBit 0, minWin=26, winSum=430
3621 13:08:14.832282 TX Vref=26, minBit 8, minWin=25, winSum=432
3622 13:08:14.835970 TX Vref=28, minBit 8, minWin=26, winSum=435
3623 13:08:14.838916 TX Vref=30, minBit 8, minWin=26, winSum=432
3624 13:08:14.842628 TX Vref=32, minBit 1, minWin=26, winSum=432
3625 13:08:14.849311 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 28
3626 13:08:14.849455
3627 13:08:14.852557 Final TX Range 1 Vref 28
3628 13:08:14.852659
3629 13:08:14.852715 ==
3630 13:08:14.855540 Dram Type= 6, Freq= 0, CH_1, rank 1
3631 13:08:14.859184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3632 13:08:14.859283 ==
3633 13:08:14.859375
3634 13:08:14.862202
3635 13:08:14.862345 TX Vref Scan disable
3636 13:08:14.865722 == TX Byte 0 ==
3637 13:08:14.869210 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3638 13:08:14.872648 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3639 13:08:14.875830 == TX Byte 1 ==
3640 13:08:14.878765 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3641 13:08:14.882620 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3642 13:08:14.885426
3643 13:08:14.885487 [DATLAT]
3644 13:08:14.885540 Freq=1200, CH1 RK1
3645 13:08:14.885591
3646 13:08:14.888771 DATLAT Default: 0xd
3647 13:08:14.888857 0, 0xFFFF, sum = 0
3648 13:08:14.892497 1, 0xFFFF, sum = 0
3649 13:08:14.892586 2, 0xFFFF, sum = 0
3650 13:08:14.896614 3, 0xFFFF, sum = 0
3651 13:08:14.896705 4, 0xFFFF, sum = 0
3652 13:08:14.898705 5, 0xFFFF, sum = 0
3653 13:08:14.902126 6, 0xFFFF, sum = 0
3654 13:08:14.902220 7, 0xFFFF, sum = 0
3655 13:08:14.905277 8, 0xFFFF, sum = 0
3656 13:08:14.905357 9, 0xFFFF, sum = 0
3657 13:08:14.909018 10, 0xFFFF, sum = 0
3658 13:08:14.909110 11, 0xFFFF, sum = 0
3659 13:08:14.912241 12, 0x0, sum = 1
3660 13:08:14.912333 13, 0x0, sum = 2
3661 13:08:14.915523 14, 0x0, sum = 3
3662 13:08:14.915613 15, 0x0, sum = 4
3663 13:08:14.915685 best_step = 13
3664 13:08:14.918720
3665 13:08:14.918785 ==
3666 13:08:14.922077 Dram Type= 6, Freq= 0, CH_1, rank 1
3667 13:08:14.925559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3668 13:08:14.925626 ==
3669 13:08:14.925681 RX Vref Scan: 0
3670 13:08:14.925733
3671 13:08:14.928645 RX Vref 0 -> 0, step: 1
3672 13:08:14.928705
3673 13:08:14.932002 RX Delay -21 -> 252, step: 4
3674 13:08:14.935195 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3675 13:08:14.942169 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3676 13:08:14.945346 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3677 13:08:14.948718 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3678 13:08:14.951802 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3679 13:08:14.955195 iDelay=195, Bit 5, Center 118 (47 ~ 190) 144
3680 13:08:14.962149 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3681 13:08:14.964969 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3682 13:08:14.968738 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
3683 13:08:14.971801 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3684 13:08:14.975427 iDelay=195, Bit 10, Center 108 (39 ~ 178) 140
3685 13:08:14.981675 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3686 13:08:14.985543 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3687 13:08:14.988494 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3688 13:08:14.992109 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3689 13:08:14.994951 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3690 13:08:14.998295 ==
3691 13:08:14.998357 Dram Type= 6, Freq= 0, CH_1, rank 1
3692 13:08:15.005259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3693 13:08:15.005331 ==
3694 13:08:15.005386 DQS Delay:
3695 13:08:15.008566 DQS0 = 0, DQS1 = 0
3696 13:08:15.008628 DQM Delay:
3697 13:08:15.011528 DQM0 = 110, DQM1 = 107
3698 13:08:15.011595 DQ Delay:
3699 13:08:15.015336 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3700 13:08:15.018120 DQ4 =108, DQ5 =118, DQ6 =120, DQ7 =108
3701 13:08:15.021882 DQ8 =94, DQ9 =100, DQ10 =108, DQ11 =100
3702 13:08:15.024667 DQ12 =118, DQ13 =112, DQ14 =116, DQ15 =114
3703 13:08:15.024734
3704 13:08:15.024791
3705 13:08:15.035122 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa0a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3706 13:08:15.038653 CH1 RK1: MR19=304, MR18=FA0A
3707 13:08:15.041538 CH1_RK1: MR19=0x304, MR18=0xFA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3708 13:08:15.044676 [RxdqsGatingPostProcess] freq 1200
3709 13:08:15.051238 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3710 13:08:15.054953 best DQS0 dly(2T, 0.5T) = (0, 11)
3711 13:08:15.057878 best DQS1 dly(2T, 0.5T) = (0, 11)
3712 13:08:15.061668 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3713 13:08:15.064838 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3714 13:08:15.067799 best DQS0 dly(2T, 0.5T) = (0, 11)
3715 13:08:15.071511 best DQS1 dly(2T, 0.5T) = (0, 11)
3716 13:08:15.074739 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3717 13:08:15.077830 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3718 13:08:15.077906 Pre-setting of DQS Precalculation
3719 13:08:15.084579 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3720 13:08:15.090792 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3721 13:08:15.097663 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3722 13:08:15.097750
3723 13:08:15.100686
3724 13:08:15.100748 [Calibration Summary] 2400 Mbps
3725 13:08:15.104402 CH 0, Rank 0
3726 13:08:15.104467 SW Impedance : PASS
3727 13:08:15.107830 DUTY Scan : NO K
3728 13:08:15.110831 ZQ Calibration : PASS
3729 13:08:15.110894 Jitter Meter : NO K
3730 13:08:15.114254 CBT Training : PASS
3731 13:08:15.117436 Write leveling : PASS
3732 13:08:15.117497 RX DQS gating : PASS
3733 13:08:15.120895 RX DQ/DQS(RDDQC) : PASS
3734 13:08:15.123883 TX DQ/DQS : PASS
3735 13:08:15.123944 RX DATLAT : PASS
3736 13:08:15.127531 RX DQ/DQS(Engine): PASS
3737 13:08:15.130924 TX OE : NO K
3738 13:08:15.130988 All Pass.
3739 13:08:15.131041
3740 13:08:15.131091 CH 0, Rank 1
3741 13:08:15.134262 SW Impedance : PASS
3742 13:08:15.137090 DUTY Scan : NO K
3743 13:08:15.137155 ZQ Calibration : PASS
3744 13:08:15.140852 Jitter Meter : NO K
3745 13:08:15.140943 CBT Training : PASS
3746 13:08:15.143910 Write leveling : PASS
3747 13:08:15.147350 RX DQS gating : PASS
3748 13:08:15.147439 RX DQ/DQS(RDDQC) : PASS
3749 13:08:15.150471 TX DQ/DQS : PASS
3750 13:08:15.153941 RX DATLAT : PASS
3751 13:08:15.154006 RX DQ/DQS(Engine): PASS
3752 13:08:15.157775 TX OE : NO K
3753 13:08:15.157839 All Pass.
3754 13:08:15.157892
3755 13:08:15.160622 CH 1, Rank 0
3756 13:08:15.160685 SW Impedance : PASS
3757 13:08:15.164370 DUTY Scan : NO K
3758 13:08:15.167330 ZQ Calibration : PASS
3759 13:08:15.167396 Jitter Meter : NO K
3760 13:08:15.170764 CBT Training : PASS
3761 13:08:15.174247 Write leveling : PASS
3762 13:08:15.174313 RX DQS gating : PASS
3763 13:08:15.177624 RX DQ/DQS(RDDQC) : PASS
3764 13:08:15.180664 TX DQ/DQS : PASS
3765 13:08:15.180747 RX DATLAT : PASS
3766 13:08:15.183815 RX DQ/DQS(Engine): PASS
3767 13:08:15.187636 TX OE : NO K
3768 13:08:15.187699 All Pass.
3769 13:08:15.187750
3770 13:08:15.187799 CH 1, Rank 1
3771 13:08:15.190656 SW Impedance : PASS
3772 13:08:15.193993 DUTY Scan : NO K
3773 13:08:15.194077 ZQ Calibration : PASS
3774 13:08:15.197271 Jitter Meter : NO K
3775 13:08:15.197331 CBT Training : PASS
3776 13:08:15.200341 Write leveling : PASS
3777 13:08:15.203954 RX DQS gating : PASS
3778 13:08:15.204018 RX DQ/DQS(RDDQC) : PASS
3779 13:08:15.206958 TX DQ/DQS : PASS
3780 13:08:15.211072 RX DATLAT : PASS
3781 13:08:15.211134 RX DQ/DQS(Engine): PASS
3782 13:08:15.213731 TX OE : NO K
3783 13:08:15.213790 All Pass.
3784 13:08:15.213840
3785 13:08:15.217485 DramC Write-DBI off
3786 13:08:15.220405 PER_BANK_REFRESH: Hybrid Mode
3787 13:08:15.220471 TX_TRACKING: ON
3788 13:08:15.230697 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3789 13:08:15.233488 [FAST_K] Save calibration result to emmc
3790 13:08:15.237430 dramc_set_vcore_voltage set vcore to 650000
3791 13:08:15.240646 Read voltage for 600, 5
3792 13:08:15.240740 Vio18 = 0
3793 13:08:15.240822 Vcore = 650000
3794 13:08:15.243449 Vdram = 0
3795 13:08:15.243511 Vddq = 0
3796 13:08:15.243568 Vmddr = 0
3797 13:08:15.250487 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3798 13:08:15.253612 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3799 13:08:15.257140 MEM_TYPE=3, freq_sel=19
3800 13:08:15.260072 sv_algorithm_assistance_LP4_1600
3801 13:08:15.263891 ============ PULL DRAM RESETB DOWN ============
3802 13:08:15.266758 ========== PULL DRAM RESETB DOWN end =========
3803 13:08:15.273764 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3804 13:08:15.277237 ===================================
3805 13:08:15.277320 LPDDR4 DRAM CONFIGURATION
3806 13:08:15.280313 ===================================
3807 13:08:15.283888 EX_ROW_EN[0] = 0x0
3808 13:08:15.286933 EX_ROW_EN[1] = 0x0
3809 13:08:15.286995 LP4Y_EN = 0x0
3810 13:08:15.290526 WORK_FSP = 0x0
3811 13:08:15.290588 WL = 0x2
3812 13:08:15.293667 RL = 0x2
3813 13:08:15.293728 BL = 0x2
3814 13:08:15.296884 RPST = 0x0
3815 13:08:15.296971 RD_PRE = 0x0
3816 13:08:15.300163 WR_PRE = 0x1
3817 13:08:15.300225 WR_PST = 0x0
3818 13:08:15.303735 DBI_WR = 0x0
3819 13:08:15.303799 DBI_RD = 0x0
3820 13:08:15.306818 OTF = 0x1
3821 13:08:15.310312 ===================================
3822 13:08:15.313456 ===================================
3823 13:08:15.313520 ANA top config
3824 13:08:15.316955 ===================================
3825 13:08:15.320259 DLL_ASYNC_EN = 0
3826 13:08:15.323244 ALL_SLAVE_EN = 1
3827 13:08:15.326968 NEW_RANK_MODE = 1
3828 13:08:15.327047 DLL_IDLE_MODE = 1
3829 13:08:15.330455 LP45_APHY_COMB_EN = 1
3830 13:08:15.333762 TX_ODT_DIS = 1
3831 13:08:15.336878 NEW_8X_MODE = 1
3832 13:08:15.340075 ===================================
3833 13:08:15.344067 ===================================
3834 13:08:15.346629 data_rate = 1200
3835 13:08:15.346704 CKR = 1
3836 13:08:15.349994 DQ_P2S_RATIO = 8
3837 13:08:15.353392 ===================================
3838 13:08:15.356701 CA_P2S_RATIO = 8
3839 13:08:15.360153 DQ_CA_OPEN = 0
3840 13:08:15.363515 DQ_SEMI_OPEN = 0
3841 13:08:15.366672 CA_SEMI_OPEN = 0
3842 13:08:15.366748 CA_FULL_RATE = 0
3843 13:08:15.369706 DQ_CKDIV4_EN = 1
3844 13:08:15.373482 CA_CKDIV4_EN = 1
3845 13:08:15.376858 CA_PREDIV_EN = 0
3846 13:08:15.379446 PH8_DLY = 0
3847 13:08:15.382932 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3848 13:08:15.382999 DQ_AAMCK_DIV = 4
3849 13:08:15.386289 CA_AAMCK_DIV = 4
3850 13:08:15.389659 CA_ADMCK_DIV = 4
3851 13:08:15.393143 DQ_TRACK_CA_EN = 0
3852 13:08:15.396301 CA_PICK = 600
3853 13:08:15.400014 CA_MCKIO = 600
3854 13:08:15.402830 MCKIO_SEMI = 0
3855 13:08:15.402894 PLL_FREQ = 2288
3856 13:08:15.406261 DQ_UI_PI_RATIO = 32
3857 13:08:15.409113 CA_UI_PI_RATIO = 0
3858 13:08:15.412578 ===================================
3859 13:08:15.416132 ===================================
3860 13:08:15.419153 memory_type:LPDDR4
3861 13:08:15.422774 GP_NUM : 10
3862 13:08:15.422863 SRAM_EN : 1
3863 13:08:15.425622 MD32_EN : 0
3864 13:08:15.429063 ===================================
3865 13:08:15.432735 [ANA_INIT] >>>>>>>>>>>>>>
3866 13:08:15.432802 <<<<<< [CONFIGURE PHASE]: ANA_TX
3867 13:08:15.436062 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3868 13:08:15.438960 ===================================
3869 13:08:15.442419 data_rate = 1200,PCW = 0X5800
3870 13:08:15.445917 ===================================
3871 13:08:15.448994 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3872 13:08:15.456063 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3873 13:08:15.462117 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3874 13:08:15.465656 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3875 13:08:15.468806 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3876 13:08:15.472217 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3877 13:08:15.475240 [ANA_INIT] flow start
3878 13:08:15.475312 [ANA_INIT] PLL >>>>>>>>
3879 13:08:15.478841 [ANA_INIT] PLL <<<<<<<<
3880 13:08:15.482036 [ANA_INIT] MIDPI >>>>>>>>
3881 13:08:15.482159 [ANA_INIT] MIDPI <<<<<<<<
3882 13:08:15.485492 [ANA_INIT] DLL >>>>>>>>
3883 13:08:15.489339 [ANA_INIT] flow end
3884 13:08:15.492052 ============ LP4 DIFF to SE enter ============
3885 13:08:15.495058 ============ LP4 DIFF to SE exit ============
3886 13:08:15.498704 [ANA_INIT] <<<<<<<<<<<<<
3887 13:08:15.501897 [Flow] Enable top DCM control >>>>>
3888 13:08:15.505814 [Flow] Enable top DCM control <<<<<
3889 13:08:15.508667 Enable DLL master slave shuffle
3890 13:08:15.514956 ==============================================================
3891 13:08:15.515037 Gating Mode config
3892 13:08:15.521945 ==============================================================
3893 13:08:15.522021 Config description:
3894 13:08:15.531877 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3895 13:08:15.538363 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3896 13:08:15.545156 SELPH_MODE 0: By rank 1: By Phase
3897 13:08:15.547893 ==============================================================
3898 13:08:15.551720 GAT_TRACK_EN = 1
3899 13:08:15.554682 RX_GATING_MODE = 2
3900 13:08:15.558422 RX_GATING_TRACK_MODE = 2
3901 13:08:15.561592 SELPH_MODE = 1
3902 13:08:15.564517 PICG_EARLY_EN = 1
3903 13:08:15.568165 VALID_LAT_VALUE = 1
3904 13:08:15.571431 ==============================================================
3905 13:08:15.577705 Enter into Gating configuration >>>>
3906 13:08:15.581494 Exit from Gating configuration <<<<
3907 13:08:15.581571 Enter into DVFS_PRE_config >>>>>
3908 13:08:15.594755 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3909 13:08:15.598010 Exit from DVFS_PRE_config <<<<<
3910 13:08:15.601010 Enter into PICG configuration >>>>
3911 13:08:15.604771 Exit from PICG configuration <<<<
3912 13:08:15.604846 [RX_INPUT] configuration >>>>>
3913 13:08:15.607789 [RX_INPUT] configuration <<<<<
3914 13:08:15.614716 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3915 13:08:15.620563 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3916 13:08:15.624067 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3917 13:08:15.630869 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3918 13:08:15.637550 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3919 13:08:15.644285 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3920 13:08:15.647629 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3921 13:08:15.650563 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3922 13:08:15.657078 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3923 13:08:15.660692 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3924 13:08:15.663882 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3925 13:08:15.670882 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3926 13:08:15.670978 ===================================
3927 13:08:15.673759 LPDDR4 DRAM CONFIGURATION
3928 13:08:15.676886 ===================================
3929 13:08:15.680389 EX_ROW_EN[0] = 0x0
3930 13:08:15.680476 EX_ROW_EN[1] = 0x0
3931 13:08:15.683759 LP4Y_EN = 0x0
3932 13:08:15.683822 WORK_FSP = 0x0
3933 13:08:15.686784 WL = 0x2
3934 13:08:15.690595 RL = 0x2
3935 13:08:15.690660 BL = 0x2
3936 13:08:15.693428 RPST = 0x0
3937 13:08:15.693490 RD_PRE = 0x0
3938 13:08:15.697258 WR_PRE = 0x1
3939 13:08:15.697322 WR_PST = 0x0
3940 13:08:15.700181 DBI_WR = 0x0
3941 13:08:15.700243 DBI_RD = 0x0
3942 13:08:15.703945 OTF = 0x1
3943 13:08:15.707070 ===================================
3944 13:08:15.710297 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3945 13:08:15.713701 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3946 13:08:15.719881 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3947 13:08:15.723383 ===================================
3948 13:08:15.723470 LPDDR4 DRAM CONFIGURATION
3949 13:08:15.726576 ===================================
3950 13:08:15.730040 EX_ROW_EN[0] = 0x10
3951 13:08:15.730162 EX_ROW_EN[1] = 0x0
3952 13:08:15.733646 LP4Y_EN = 0x0
3953 13:08:15.733709 WORK_FSP = 0x0
3954 13:08:15.736617 WL = 0x2
3955 13:08:15.736678 RL = 0x2
3956 13:08:15.739981 BL = 0x2
3957 13:08:15.743116 RPST = 0x0
3958 13:08:15.743190 RD_PRE = 0x0
3959 13:08:15.746413 WR_PRE = 0x1
3960 13:08:15.746478 WR_PST = 0x0
3961 13:08:15.749901 DBI_WR = 0x0
3962 13:08:15.749985 DBI_RD = 0x0
3963 13:08:15.753176 OTF = 0x1
3964 13:08:15.756308 ===================================
3965 13:08:15.762841 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3966 13:08:15.765941 nWR fixed to 30
3967 13:08:15.766031 [ModeRegInit_LP4] CH0 RK0
3968 13:08:15.769672 [ModeRegInit_LP4] CH0 RK1
3969 13:08:15.772733 [ModeRegInit_LP4] CH1 RK0
3970 13:08:15.772820 [ModeRegInit_LP4] CH1 RK1
3971 13:08:15.776317 match AC timing 17
3972 13:08:15.779789 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3973 13:08:15.786441 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3974 13:08:15.789643 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3975 13:08:15.793057 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3976 13:08:15.799571 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3977 13:08:15.799636 ==
3978 13:08:15.802556 Dram Type= 6, Freq= 0, CH_0, rank 0
3979 13:08:15.806010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 13:08:15.806125 ==
3981 13:08:15.812601 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3982 13:08:15.819493 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3983 13:08:15.822367 [CA 0] Center 37 (7~67) winsize 61
3984 13:08:15.825750 [CA 1] Center 37 (7~67) winsize 61
3985 13:08:15.829433 [CA 2] Center 35 (5~65) winsize 61
3986 13:08:15.832469 [CA 3] Center 35 (5~65) winsize 61
3987 13:08:15.836023 [CA 4] Center 34 (4~65) winsize 62
3988 13:08:15.839114 [CA 5] Center 34 (4~65) winsize 62
3989 13:08:15.839177
3990 13:08:15.842685 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3991 13:08:15.842748
3992 13:08:15.845868 [CATrainingPosCal] consider 1 rank data
3993 13:08:15.848919 u2DelayCellTimex100 = 270/100 ps
3994 13:08:15.852246 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3995 13:08:15.855922 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3996 13:08:15.859041 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3997 13:08:15.862672 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3998 13:08:15.865807 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3999 13:08:15.868783 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4000 13:08:15.868848
4001 13:08:15.872330 CA PerBit enable=1, Macro0, CA PI delay=34
4002 13:08:15.875389
4003 13:08:15.875453 [CBTSetCACLKResult] CA Dly = 34
4004 13:08:15.879124 CS Dly: 6 (0~37)
4005 13:08:15.879189 ==
4006 13:08:15.882540 Dram Type= 6, Freq= 0, CH_0, rank 1
4007 13:08:15.885582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4008 13:08:15.885668 ==
4009 13:08:15.892060 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4010 13:08:15.899147 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4011 13:08:15.902389 [CA 0] Center 37 (7~67) winsize 61
4012 13:08:15.905540 [CA 1] Center 36 (6~67) winsize 62
4013 13:08:15.908620 [CA 2] Center 35 (5~65) winsize 61
4014 13:08:15.912238 [CA 3] Center 35 (5~65) winsize 61
4015 13:08:15.915374 [CA 4] Center 34 (4~65) winsize 62
4016 13:08:15.918662 [CA 5] Center 34 (3~65) winsize 63
4017 13:08:15.918726
4018 13:08:15.921892 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4019 13:08:15.921953
4020 13:08:15.925096 [CATrainingPosCal] consider 2 rank data
4021 13:08:15.928813 u2DelayCellTimex100 = 270/100 ps
4022 13:08:15.931691 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4023 13:08:15.935008 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4024 13:08:15.938329 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4025 13:08:15.942386 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4026 13:08:15.945339 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4027 13:08:15.948891 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4028 13:08:15.948955
4029 13:08:15.955168 CA PerBit enable=1, Macro0, CA PI delay=34
4030 13:08:15.955233
4031 13:08:15.958361 [CBTSetCACLKResult] CA Dly = 34
4032 13:08:15.958422 CS Dly: 6 (0~37)
4033 13:08:15.958474
4034 13:08:15.962062 ----->DramcWriteLeveling(PI) begin...
4035 13:08:15.962189 ==
4036 13:08:15.965662 Dram Type= 6, Freq= 0, CH_0, rank 0
4037 13:08:15.968544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4038 13:08:15.968610 ==
4039 13:08:15.972161 Write leveling (Byte 0): 32 => 32
4040 13:08:15.975245 Write leveling (Byte 1): 31 => 31
4041 13:08:15.978495 DramcWriteLeveling(PI) end<-----
4042 13:08:15.978557
4043 13:08:15.978609 ==
4044 13:08:15.981921 Dram Type= 6, Freq= 0, CH_0, rank 0
4045 13:08:15.988488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 13:08:15.988552 ==
4047 13:08:15.988605 [Gating] SW mode calibration
4048 13:08:15.998540 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4049 13:08:16.001965 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4050 13:08:16.004890 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4051 13:08:16.011345 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4052 13:08:16.014607 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4053 13:08:16.017940 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
4054 13:08:16.024705 0 9 16 | B1->B0 | 3030 2d2d | 0 1 | (0 0) (0 0)
4055 13:08:16.028231 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 13:08:16.031320 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 13:08:16.038704 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 13:08:16.041449 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 13:08:16.044946 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 13:08:16.051760 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 13:08:16.054820 0 10 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4062 13:08:16.058331 0 10 16 | B1->B0 | 3131 3a3a | 1 0 | (0 0) (0 0)
4063 13:08:16.064551 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 13:08:16.067811 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 13:08:16.071697 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 13:08:16.078044 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 13:08:16.081755 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 13:08:16.084557 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 13:08:16.091046 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4070 13:08:16.094817 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4071 13:08:16.097740 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 13:08:16.104674 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 13:08:16.108042 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 13:08:16.110925 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 13:08:16.117618 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 13:08:16.121164 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 13:08:16.124279 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 13:08:16.131354 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 13:08:16.134365 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 13:08:16.137735 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 13:08:16.141366 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 13:08:16.147446 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 13:08:16.151461 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 13:08:16.154674 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 13:08:16.161189 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4086 13:08:16.164447 Total UI for P1: 0, mck2ui 16
4087 13:08:16.167892 best dqsien dly found for B0: ( 0, 13, 10)
4088 13:08:16.170921 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4089 13:08:16.174234 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4090 13:08:16.177783 Total UI for P1: 0, mck2ui 16
4091 13:08:16.180858 best dqsien dly found for B1: ( 0, 13, 16)
4092 13:08:16.184398 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4093 13:08:16.187649 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4094 13:08:16.190874
4095 13:08:16.194428 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4096 13:08:16.197950 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4097 13:08:16.200933 [Gating] SW calibration Done
4098 13:08:16.200995 ==
4099 13:08:16.204556 Dram Type= 6, Freq= 0, CH_0, rank 0
4100 13:08:16.207699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4101 13:08:16.207765 ==
4102 13:08:16.207826 RX Vref Scan: 0
4103 13:08:16.207877
4104 13:08:16.210724 RX Vref 0 -> 0, step: 1
4105 13:08:16.210786
4106 13:08:16.214231 RX Delay -230 -> 252, step: 16
4107 13:08:16.217644 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4108 13:08:16.224355 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4109 13:08:16.227183 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4110 13:08:16.230496 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4111 13:08:16.234208 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4112 13:08:16.237781 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4113 13:08:16.244066 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4114 13:08:16.247397 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4115 13:08:16.250286 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4116 13:08:16.253878 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4117 13:08:16.260559 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4118 13:08:16.263908 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4119 13:08:16.266936 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4120 13:08:16.270430 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4121 13:08:16.277086 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4122 13:08:16.280467 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4123 13:08:16.280535 ==
4124 13:08:16.284110 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 13:08:16.287097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 13:08:16.287161 ==
4127 13:08:16.290414 DQS Delay:
4128 13:08:16.290475 DQS0 = 0, DQS1 = 0
4129 13:08:16.290526 DQM Delay:
4130 13:08:16.293750 DQM0 = 38, DQM1 = 29
4131 13:08:16.293837 DQ Delay:
4132 13:08:16.297294 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4133 13:08:16.300124 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4134 13:08:16.303358 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4135 13:08:16.306679 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4136 13:08:16.306744
4137 13:08:16.306797
4138 13:08:16.306848 ==
4139 13:08:16.310609 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 13:08:16.317058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 13:08:16.317125 ==
4142 13:08:16.317181
4143 13:08:16.317233
4144 13:08:16.317289 TX Vref Scan disable
4145 13:08:16.320351 == TX Byte 0 ==
4146 13:08:16.323982 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4147 13:08:16.327089 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4148 13:08:16.330260 == TX Byte 1 ==
4149 13:08:16.333817 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4150 13:08:16.337133 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4151 13:08:16.340290 ==
4152 13:08:16.343893 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 13:08:16.347065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 13:08:16.347128 ==
4155 13:08:16.347188
4156 13:08:16.347239
4157 13:08:16.350122 TX Vref Scan disable
4158 13:08:16.353992 == TX Byte 0 ==
4159 13:08:16.356673 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4160 13:08:16.360310 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4161 13:08:16.363796 == TX Byte 1 ==
4162 13:08:16.366943 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4163 13:08:16.369874 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4164 13:08:16.369955
4165 13:08:16.370035 [DATLAT]
4166 13:08:16.373347 Freq=600, CH0 RK0
4167 13:08:16.373436
4168 13:08:16.373515 DATLAT Default: 0x9
4169 13:08:16.376520 0, 0xFFFF, sum = 0
4170 13:08:16.380204 1, 0xFFFF, sum = 0
4171 13:08:16.380270 2, 0xFFFF, sum = 0
4172 13:08:16.383633 3, 0xFFFF, sum = 0
4173 13:08:16.383698 4, 0xFFFF, sum = 0
4174 13:08:16.386725 5, 0xFFFF, sum = 0
4175 13:08:16.386791 6, 0xFFFF, sum = 0
4176 13:08:16.390469 7, 0xFFFF, sum = 0
4177 13:08:16.390532 8, 0x0, sum = 1
4178 13:08:16.390583 9, 0x0, sum = 2
4179 13:08:16.393184 10, 0x0, sum = 3
4180 13:08:16.393244 11, 0x0, sum = 4
4181 13:08:16.396745 best_step = 9
4182 13:08:16.396804
4183 13:08:16.396853 ==
4184 13:08:16.400044 Dram Type= 6, Freq= 0, CH_0, rank 0
4185 13:08:16.403226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4186 13:08:16.403314 ==
4187 13:08:16.406737 RX Vref Scan: 1
4188 13:08:16.406808
4189 13:08:16.406861 RX Vref 0 -> 0, step: 1
4190 13:08:16.409761
4191 13:08:16.409820 RX Delay -195 -> 252, step: 8
4192 13:08:16.409871
4193 13:08:16.413403 Set Vref, RX VrefLevel [Byte0]: 61
4194 13:08:16.416670 [Byte1]: 51
4195 13:08:16.420773
4196 13:08:16.420848 Final RX Vref Byte 0 = 61 to rank0
4197 13:08:16.423869 Final RX Vref Byte 1 = 51 to rank0
4198 13:08:16.427356 Final RX Vref Byte 0 = 61 to rank1
4199 13:08:16.430879 Final RX Vref Byte 1 = 51 to rank1==
4200 13:08:16.434543 Dram Type= 6, Freq= 0, CH_0, rank 0
4201 13:08:16.440631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 13:08:16.440702 ==
4203 13:08:16.440758 DQS Delay:
4204 13:08:16.443946 DQS0 = 0, DQS1 = 0
4205 13:08:16.444011 DQM Delay:
4206 13:08:16.444069 DQM0 = 33, DQM1 = 29
4207 13:08:16.447212 DQ Delay:
4208 13:08:16.450834 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4209 13:08:16.453775 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =44
4210 13:08:16.456767 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4211 13:08:16.460513 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4212 13:08:16.460573
4213 13:08:16.460624
4214 13:08:16.467202 [DQSOSCAuto] RK0, (LSB)MR18= 0x4141, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4215 13:08:16.470251 CH0 RK0: MR19=808, MR18=4141
4216 13:08:16.477494 CH0_RK0: MR19=0x808, MR18=0x4141, DQSOSC=397, MR23=63, INC=166, DEC=110
4217 13:08:16.477565
4218 13:08:16.480538 ----->DramcWriteLeveling(PI) begin...
4219 13:08:16.480604 ==
4220 13:08:16.483914 Dram Type= 6, Freq= 0, CH_0, rank 1
4221 13:08:16.486977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 13:08:16.487039 ==
4223 13:08:16.490432 Write leveling (Byte 0): 33 => 33
4224 13:08:16.493410 Write leveling (Byte 1): 30 => 30
4225 13:08:16.497039 DramcWriteLeveling(PI) end<-----
4226 13:08:16.497100
4227 13:08:16.497152 ==
4228 13:08:16.500495 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 13:08:16.503667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 13:08:16.503754 ==
4231 13:08:16.507407 [Gating] SW mode calibration
4232 13:08:16.513776 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4233 13:08:16.520299 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4234 13:08:16.523397 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4235 13:08:16.530442 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4236 13:08:16.533822 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4237 13:08:16.536661 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
4238 13:08:16.543695 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
4239 13:08:16.546724 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 13:08:16.549986 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 13:08:16.556906 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 13:08:16.560272 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 13:08:16.563242 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 13:08:16.566840 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 13:08:16.573158 0 10 12 | B1->B0 | 2b2b 2f2f | 0 1 | (0 0) (0 0)
4246 13:08:16.576662 0 10 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4247 13:08:16.579959 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 13:08:16.586797 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 13:08:16.589876 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 13:08:16.593341 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 13:08:16.599485 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 13:08:16.603240 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 13:08:16.606035 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4254 13:08:16.613386 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4255 13:08:16.616738 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 13:08:16.619786 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 13:08:16.626438 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 13:08:16.629400 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 13:08:16.633117 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 13:08:16.639776 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 13:08:16.642966 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 13:08:16.646536 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 13:08:16.652739 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 13:08:16.655874 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 13:08:16.659384 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 13:08:16.666196 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 13:08:16.669255 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 13:08:16.672617 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 13:08:16.679791 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4270 13:08:16.679867 Total UI for P1: 0, mck2ui 16
4271 13:08:16.685998 best dqsien dly found for B0: ( 0, 13, 10)
4272 13:08:16.689514 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 13:08:16.692836 Total UI for P1: 0, mck2ui 16
4274 13:08:16.695753 best dqsien dly found for B1: ( 0, 13, 14)
4275 13:08:16.699392 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4276 13:08:16.702575 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4277 13:08:16.702663
4278 13:08:16.705792 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4279 13:08:16.709788 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4280 13:08:16.712673 [Gating] SW calibration Done
4281 13:08:16.712763 ==
4282 13:08:16.715727 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 13:08:16.719419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 13:08:16.722945 ==
4285 13:08:16.723010 RX Vref Scan: 0
4286 13:08:16.723068
4287 13:08:16.726048 RX Vref 0 -> 0, step: 1
4288 13:08:16.726162
4289 13:08:16.729335 RX Delay -230 -> 252, step: 16
4290 13:08:16.732713 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4291 13:08:16.736366 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4292 13:08:16.739339 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4293 13:08:16.742473 iDelay=218, Bit 3, Center 25 (-150 ~ 201) 352
4294 13:08:16.749211 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4295 13:08:16.752389 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4296 13:08:16.756066 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4297 13:08:16.759585 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4298 13:08:16.766353 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4299 13:08:16.769093 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4300 13:08:16.772877 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4301 13:08:16.775855 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4302 13:08:16.782786 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4303 13:08:16.785925 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4304 13:08:16.789452 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4305 13:08:16.792609 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4306 13:08:16.792685 ==
4307 13:08:16.796047 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 13:08:16.802567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 13:08:16.802647 ==
4310 13:08:16.802706 DQS Delay:
4311 13:08:16.802760 DQS0 = 0, DQS1 = 0
4312 13:08:16.805619 DQM Delay:
4313 13:08:16.805700 DQM0 = 34, DQM1 = 28
4314 13:08:16.809306 DQ Delay:
4315 13:08:16.812571 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =25
4316 13:08:16.812643 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4317 13:08:16.815771 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4318 13:08:16.822696 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4319 13:08:16.822767
4320 13:08:16.822824
4321 13:08:16.822877 ==
4322 13:08:16.825930 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 13:08:16.829192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 13:08:16.829258 ==
4325 13:08:16.829311
4326 13:08:16.829360
4327 13:08:16.832657 TX Vref Scan disable
4328 13:08:16.832731 == TX Byte 0 ==
4329 13:08:16.838956 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4330 13:08:16.842513 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4331 13:08:16.842588 == TX Byte 1 ==
4332 13:08:16.849238 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4333 13:08:16.852046 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4334 13:08:16.852121 ==
4335 13:08:16.855701 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 13:08:16.859009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 13:08:16.859085 ==
4338 13:08:16.859143
4339 13:08:16.861768
4340 13:08:16.861842 TX Vref Scan disable
4341 13:08:16.865408 == TX Byte 0 ==
4342 13:08:16.868977 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4343 13:08:16.872551 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4344 13:08:16.875659 == TX Byte 1 ==
4345 13:08:16.879093 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4346 13:08:16.882150 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4347 13:08:16.885951
4348 13:08:16.886025 [DATLAT]
4349 13:08:16.886083 Freq=600, CH0 RK1
4350 13:08:16.886177
4351 13:08:16.888991 DATLAT Default: 0x9
4352 13:08:16.889066 0, 0xFFFF, sum = 0
4353 13:08:16.892407 1, 0xFFFF, sum = 0
4354 13:08:16.892483 2, 0xFFFF, sum = 0
4355 13:08:16.895815 3, 0xFFFF, sum = 0
4356 13:08:16.898934 4, 0xFFFF, sum = 0
4357 13:08:16.899010 5, 0xFFFF, sum = 0
4358 13:08:16.901886 6, 0xFFFF, sum = 0
4359 13:08:16.901962 7, 0xFFFF, sum = 0
4360 13:08:16.905660 8, 0x0, sum = 1
4361 13:08:16.905761 9, 0x0, sum = 2
4362 13:08:16.905892 10, 0x0, sum = 3
4363 13:08:16.909200 11, 0x0, sum = 4
4364 13:08:16.909277 best_step = 9
4365 13:08:16.909334
4366 13:08:16.909387 ==
4367 13:08:16.912191 Dram Type= 6, Freq= 0, CH_0, rank 1
4368 13:08:16.918536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 13:08:16.918613 ==
4370 13:08:16.918671 RX Vref Scan: 0
4371 13:08:16.918724
4372 13:08:16.922137 RX Vref 0 -> 0, step: 1
4373 13:08:16.922216
4374 13:08:16.925548 RX Delay -195 -> 252, step: 8
4375 13:08:16.928967 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4376 13:08:16.935121 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4377 13:08:16.938537 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4378 13:08:16.942074 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4379 13:08:16.945610 iDelay=205, Bit 4, Center 28 (-131 ~ 188) 320
4380 13:08:16.951737 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4381 13:08:16.955445 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4382 13:08:16.958635 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4383 13:08:16.961547 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4384 13:08:16.965303 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4385 13:08:16.971734 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4386 13:08:16.974834 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4387 13:08:16.978534 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4388 13:08:16.981536 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4389 13:08:16.988228 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4390 13:08:16.991976 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4391 13:08:16.992056 ==
4392 13:08:16.994873 Dram Type= 6, Freq= 0, CH_0, rank 1
4393 13:08:16.998500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 13:08:16.998570 ==
4395 13:08:17.001410 DQS Delay:
4396 13:08:17.001478 DQS0 = 0, DQS1 = 0
4397 13:08:17.001532 DQM Delay:
4398 13:08:17.005127 DQM0 = 33, DQM1 = 27
4399 13:08:17.005187 DQ Delay:
4400 13:08:17.008130 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4401 13:08:17.011603 DQ4 =28, DQ5 =20, DQ6 =44, DQ7 =44
4402 13:08:17.015093 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4403 13:08:17.018331 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4404 13:08:17.018394
4405 13:08:17.018446
4406 13:08:17.028057 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f3e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4407 13:08:17.031623 CH0 RK1: MR19=808, MR18=6F3E
4408 13:08:17.034546 CH0_RK1: MR19=0x808, MR18=0x6F3E, DQSOSC=389, MR23=63, INC=173, DEC=115
4409 13:08:17.038021 [RxdqsGatingPostProcess] freq 600
4410 13:08:17.045091 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4411 13:08:17.047899 Pre-setting of DQS Precalculation
4412 13:08:17.051043 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4413 13:08:17.051111 ==
4414 13:08:17.054863 Dram Type= 6, Freq= 0, CH_1, rank 0
4415 13:08:17.061040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 13:08:17.061110 ==
4417 13:08:17.064953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4418 13:08:17.070946 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4419 13:08:17.075170 [CA 0] Center 36 (6~66) winsize 61
4420 13:08:17.077983 [CA 1] Center 36 (6~66) winsize 61
4421 13:08:17.081572 [CA 2] Center 34 (4~65) winsize 62
4422 13:08:17.084493 [CA 3] Center 34 (3~65) winsize 63
4423 13:08:17.087935 [CA 4] Center 34 (4~65) winsize 62
4424 13:08:17.091591 [CA 5] Center 33 (3~64) winsize 62
4425 13:08:17.091660
4426 13:08:17.094850 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4427 13:08:17.094922
4428 13:08:17.097854 [CATrainingPosCal] consider 1 rank data
4429 13:08:17.100903 u2DelayCellTimex100 = 270/100 ps
4430 13:08:17.104606 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4431 13:08:17.107655 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4432 13:08:17.114160 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4433 13:08:17.117619 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4434 13:08:17.121343 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4435 13:08:17.124156 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4436 13:08:17.124222
4437 13:08:17.127792 CA PerBit enable=1, Macro0, CA PI delay=33
4438 13:08:17.127859
4439 13:08:17.130926 [CBTSetCACLKResult] CA Dly = 33
4440 13:08:17.130999 CS Dly: 5 (0~36)
4441 13:08:17.134508 ==
4442 13:08:17.137511 Dram Type= 6, Freq= 0, CH_1, rank 1
4443 13:08:17.141206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 13:08:17.141275 ==
4445 13:08:17.144254 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4446 13:08:17.150820 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4447 13:08:17.154480 [CA 0] Center 36 (6~66) winsize 61
4448 13:08:17.157953 [CA 1] Center 35 (5~66) winsize 62
4449 13:08:17.161553 [CA 2] Center 34 (4~65) winsize 62
4450 13:08:17.164917 [CA 3] Center 34 (3~65) winsize 63
4451 13:08:17.167879 [CA 4] Center 34 (4~65) winsize 62
4452 13:08:17.171188 [CA 5] Center 33 (3~64) winsize 62
4453 13:08:17.171255
4454 13:08:17.174647 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4455 13:08:17.174715
4456 13:08:17.177774 [CATrainingPosCal] consider 2 rank data
4457 13:08:17.181150 u2DelayCellTimex100 = 270/100 ps
4458 13:08:17.184643 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4459 13:08:17.191137 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4460 13:08:17.194699 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4461 13:08:17.197649 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4462 13:08:17.201441 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4463 13:08:17.204608 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4464 13:08:17.204682
4465 13:08:17.208152 CA PerBit enable=1, Macro0, CA PI delay=33
4466 13:08:17.208222
4467 13:08:17.211056 [CBTSetCACLKResult] CA Dly = 33
4468 13:08:17.211153 CS Dly: 5 (0~37)
4469 13:08:17.214778
4470 13:08:17.217823 ----->DramcWriteLeveling(PI) begin...
4471 13:08:17.217890 ==
4472 13:08:17.220801 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 13:08:17.224211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 13:08:17.224277 ==
4475 13:08:17.227589 Write leveling (Byte 0): 30 => 30
4476 13:08:17.231056 Write leveling (Byte 1): 31 => 31
4477 13:08:17.234529 DramcWriteLeveling(PI) end<-----
4478 13:08:17.234594
4479 13:08:17.234651 ==
4480 13:08:17.237735 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 13:08:17.240851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 13:08:17.240920 ==
4483 13:08:17.244383 [Gating] SW mode calibration
4484 13:08:17.251204 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4485 13:08:17.258036 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4486 13:08:17.261181 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4487 13:08:17.264116 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4488 13:08:17.271009 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4489 13:08:17.274479 0 9 12 | B1->B0 | 3131 3131 | 0 0 | (0 1) (1 1)
4490 13:08:17.277597 0 9 16 | B1->B0 | 2626 2828 | 0 0 | (0 0) (0 0)
4491 13:08:17.284342 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 13:08:17.287461 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 13:08:17.290424 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 13:08:17.294373 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 13:08:17.300433 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 13:08:17.304302 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 13:08:17.307511 0 10 12 | B1->B0 | 3232 3333 | 0 1 | (0 0) (0 0)
4498 13:08:17.313753 0 10 16 | B1->B0 | 4444 4343 | 0 0 | (0 0) (0 0)
4499 13:08:17.317060 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 13:08:17.320650 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 13:08:17.327522 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 13:08:17.330572 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 13:08:17.333903 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 13:08:17.340851 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 13:08:17.343878 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4506 13:08:17.346995 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 13:08:17.353662 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 13:08:17.357253 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 13:08:17.360590 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 13:08:17.366946 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 13:08:17.370822 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 13:08:17.373923 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 13:08:17.380672 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 13:08:17.383818 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 13:08:17.387118 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 13:08:17.393943 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 13:08:17.396851 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 13:08:17.400578 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 13:08:17.407022 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 13:08:17.410387 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 13:08:17.413878 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4522 13:08:17.420178 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4523 13:08:17.420275 Total UI for P1: 0, mck2ui 16
4524 13:08:17.423672 best dqsien dly found for B0: ( 0, 13, 14)
4525 13:08:17.430220 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4526 13:08:17.433558 Total UI for P1: 0, mck2ui 16
4527 13:08:17.437041 best dqsien dly found for B1: ( 0, 13, 14)
4528 13:08:17.440225 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4529 13:08:17.443645 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4530 13:08:17.443712
4531 13:08:17.446796 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4532 13:08:17.449983 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4533 13:08:17.453625 [Gating] SW calibration Done
4534 13:08:17.453718 ==
4535 13:08:17.456466 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 13:08:17.460333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 13:08:17.460428 ==
4538 13:08:17.463479 RX Vref Scan: 0
4539 13:08:17.463567
4540 13:08:17.466843 RX Vref 0 -> 0, step: 1
4541 13:08:17.466928
4542 13:08:17.469650 RX Delay -230 -> 252, step: 16
4543 13:08:17.473333 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4544 13:08:17.476470 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4545 13:08:17.479756 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4546 13:08:17.483082 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4547 13:08:17.489971 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4548 13:08:17.492918 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4549 13:08:17.496343 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4550 13:08:17.499560 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4551 13:08:17.506349 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4552 13:08:17.509884 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4553 13:08:17.512785 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4554 13:08:17.516518 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4555 13:08:17.523035 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4556 13:08:17.526347 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4557 13:08:17.529742 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4558 13:08:17.532796 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4559 13:08:17.532887 ==
4560 13:08:17.536388 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 13:08:17.542791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 13:08:17.542884 ==
4563 13:08:17.542968 DQS Delay:
4564 13:08:17.546110 DQS0 = 0, DQS1 = 0
4565 13:08:17.546176 DQM Delay:
4566 13:08:17.546232 DQM0 = 39, DQM1 = 28
4567 13:08:17.549497 DQ Delay:
4568 13:08:17.553055 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4569 13:08:17.555878 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4570 13:08:17.559135 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4571 13:08:17.562380 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4572 13:08:17.562469
4573 13:08:17.562551
4574 13:08:17.562629 ==
4575 13:08:17.566235 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 13:08:17.569251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 13:08:17.569341 ==
4578 13:08:17.569424
4579 13:08:17.569504
4580 13:08:17.572817 TX Vref Scan disable
4581 13:08:17.572903 == TX Byte 0 ==
4582 13:08:17.579328 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4583 13:08:17.582540 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4584 13:08:17.582634 == TX Byte 1 ==
4585 13:08:17.588924 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4586 13:08:17.592696 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4587 13:08:17.592786 ==
4588 13:08:17.595728 Dram Type= 6, Freq= 0, CH_1, rank 0
4589 13:08:17.599443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 13:08:17.599536 ==
4591 13:08:17.602493
4592 13:08:17.602559
4593 13:08:17.602618 TX Vref Scan disable
4594 13:08:17.605869 == TX Byte 0 ==
4595 13:08:17.609436 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4596 13:08:17.612369 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4597 13:08:17.616225 == TX Byte 1 ==
4598 13:08:17.619577 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4599 13:08:17.622683 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4600 13:08:17.626263
4601 13:08:17.626355 [DATLAT]
4602 13:08:17.626439 Freq=600, CH1 RK0
4603 13:08:17.626521
4604 13:08:17.629147 DATLAT Default: 0x9
4605 13:08:17.629213 0, 0xFFFF, sum = 0
4606 13:08:17.632695 1, 0xFFFF, sum = 0
4607 13:08:17.632785 2, 0xFFFF, sum = 0
4608 13:08:17.635812 3, 0xFFFF, sum = 0
4609 13:08:17.639632 4, 0xFFFF, sum = 0
4610 13:08:17.639720 5, 0xFFFF, sum = 0
4611 13:08:17.642544 6, 0xFFFF, sum = 0
4612 13:08:17.642608 7, 0xFFFF, sum = 0
4613 13:08:17.646064 8, 0x0, sum = 1
4614 13:08:17.646148 9, 0x0, sum = 2
4615 13:08:17.646206 10, 0x0, sum = 3
4616 13:08:17.648870 11, 0x0, sum = 4
4617 13:08:17.648957 best_step = 9
4618 13:08:17.649037
4619 13:08:17.649116 ==
4620 13:08:17.652800 Dram Type= 6, Freq= 0, CH_1, rank 0
4621 13:08:17.659344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 13:08:17.659411 ==
4623 13:08:17.659466 RX Vref Scan: 1
4624 13:08:17.659521
4625 13:08:17.662833 RX Vref 0 -> 0, step: 1
4626 13:08:17.662900
4627 13:08:17.665832 RX Delay -195 -> 252, step: 8
4628 13:08:17.665917
4629 13:08:17.669609 Set Vref, RX VrefLevel [Byte0]: 53
4630 13:08:17.672159 [Byte1]: 48
4631 13:08:17.672248
4632 13:08:17.675723 Final RX Vref Byte 0 = 53 to rank0
4633 13:08:17.679506 Final RX Vref Byte 1 = 48 to rank0
4634 13:08:17.682559 Final RX Vref Byte 0 = 53 to rank1
4635 13:08:17.685651 Final RX Vref Byte 1 = 48 to rank1==
4636 13:08:17.689284 Dram Type= 6, Freq= 0, CH_1, rank 0
4637 13:08:17.692152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 13:08:17.692216 ==
4639 13:08:17.695412 DQS Delay:
4640 13:08:17.695505 DQS0 = 0, DQS1 = 0
4641 13:08:17.699100 DQM Delay:
4642 13:08:17.699189 DQM0 = 37, DQM1 = 28
4643 13:08:17.699269 DQ Delay:
4644 13:08:17.702044 DQ0 =44, DQ1 =28, DQ2 =28, DQ3 =36
4645 13:08:17.705971 DQ4 =36, DQ5 =44, DQ6 =48, DQ7 =36
4646 13:08:17.708940 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4647 13:08:17.712031 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4648 13:08:17.712099
4649 13:08:17.712154
4650 13:08:17.721875 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f3c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 400 ps
4651 13:08:17.725262 CH1 RK0: MR19=808, MR18=2F3C
4652 13:08:17.732166 CH1_RK0: MR19=0x808, MR18=0x2F3C, DQSOSC=398, MR23=63, INC=165, DEC=110
4653 13:08:17.732242
4654 13:08:17.735158 ----->DramcWriteLeveling(PI) begin...
4655 13:08:17.735228 ==
4656 13:08:17.738978 Dram Type= 6, Freq= 0, CH_1, rank 1
4657 13:08:17.742013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 13:08:17.742077 ==
4659 13:08:17.745312 Write leveling (Byte 0): 28 => 28
4660 13:08:17.748672 Write leveling (Byte 1): 31 => 31
4661 13:08:17.751712 DramcWriteLeveling(PI) end<-----
4662 13:08:17.751780
4663 13:08:17.751833 ==
4664 13:08:17.755229 Dram Type= 6, Freq= 0, CH_1, rank 1
4665 13:08:17.759138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4666 13:08:17.759202 ==
4667 13:08:17.761655 [Gating] SW mode calibration
4668 13:08:17.768404 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4669 13:08:17.775172 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4670 13:08:17.778625 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4671 13:08:17.781536 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4672 13:08:17.788114 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4673 13:08:17.791658 0 9 12 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
4674 13:08:17.794944 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4675 13:08:17.801363 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 13:08:17.804649 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 13:08:17.808115 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 13:08:17.814580 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 13:08:17.818270 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 13:08:17.821241 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 13:08:17.828264 0 10 12 | B1->B0 | 3636 3a3a | 1 0 | (0 0) (0 0)
4682 13:08:17.831421 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 13:08:17.834704 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 13:08:17.841082 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 13:08:17.844633 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 13:08:17.848249 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 13:08:17.854895 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 13:08:17.858008 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4689 13:08:17.861517 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4690 13:08:17.868086 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 13:08:17.870956 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 13:08:17.874215 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 13:08:17.877579 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 13:08:17.884208 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 13:08:17.887644 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 13:08:17.890789 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 13:08:17.897460 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 13:08:17.901211 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 13:08:17.904479 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 13:08:17.911325 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 13:08:17.914248 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 13:08:17.917421 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 13:08:17.924282 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 13:08:17.927367 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4705 13:08:17.930661 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4706 13:08:17.934518 Total UI for P1: 0, mck2ui 16
4707 13:08:17.937569 best dqsien dly found for B0: ( 0, 13, 8)
4708 13:08:17.941538 Total UI for P1: 0, mck2ui 16
4709 13:08:17.944132 best dqsien dly found for B1: ( 0, 13, 10)
4710 13:08:17.947836 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4711 13:08:17.951024 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4712 13:08:17.951093
4713 13:08:17.957274 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4714 13:08:17.960812 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4715 13:08:17.960879 [Gating] SW calibration Done
4716 13:08:17.964078 ==
4717 13:08:17.967849 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 13:08:17.970567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 13:08:17.970639 ==
4720 13:08:17.970696 RX Vref Scan: 0
4721 13:08:17.970750
4722 13:08:17.973921 RX Vref 0 -> 0, step: 1
4723 13:08:17.973983
4724 13:08:17.977362 RX Delay -230 -> 252, step: 16
4725 13:08:17.980440 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4726 13:08:17.983789 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4727 13:08:17.990442 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4728 13:08:17.994111 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4729 13:08:17.997601 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4730 13:08:18.000677 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4731 13:08:18.007586 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4732 13:08:18.010754 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4733 13:08:18.013715 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4734 13:08:18.016865 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4735 13:08:18.023549 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4736 13:08:18.026899 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4737 13:08:18.030196 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4738 13:08:18.033728 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4739 13:08:18.036977 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4740 13:08:18.043902 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4741 13:08:18.043998 ==
4742 13:08:18.046856 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 13:08:18.050571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 13:08:18.050660 ==
4745 13:08:18.050728 DQS Delay:
4746 13:08:18.054073 DQS0 = 0, DQS1 = 0
4747 13:08:18.054165 DQM Delay:
4748 13:08:18.056826 DQM0 = 35, DQM1 = 29
4749 13:08:18.056912 DQ Delay:
4750 13:08:18.060500 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4751 13:08:18.063507 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4752 13:08:18.067075 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4753 13:08:18.069939 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4754 13:08:18.070039
4755 13:08:18.070185
4756 13:08:18.070298 ==
4757 13:08:18.073750 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 13:08:18.076808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 13:08:18.080376 ==
4760 13:08:18.080463
4761 13:08:18.080543
4762 13:08:18.080624 TX Vref Scan disable
4763 13:08:18.083405 == TX Byte 0 ==
4764 13:08:18.086717 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4765 13:08:18.090194 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4766 13:08:18.093706 == TX Byte 1 ==
4767 13:08:18.096685 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4768 13:08:18.100204 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4769 13:08:18.103339 ==
4770 13:08:18.106460 Dram Type= 6, Freq= 0, CH_1, rank 1
4771 13:08:18.110073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4772 13:08:18.110186 ==
4773 13:08:18.110243
4774 13:08:18.110298
4775 13:08:18.113030 TX Vref Scan disable
4776 13:08:18.113115 == TX Byte 0 ==
4777 13:08:18.119964 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4778 13:08:18.123017 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4779 13:08:18.126758 == TX Byte 1 ==
4780 13:08:18.129637 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4781 13:08:18.132952 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4782 13:08:18.133018
4783 13:08:18.133072 [DATLAT]
4784 13:08:18.136557 Freq=600, CH1 RK1
4785 13:08:18.136649
4786 13:08:18.136730 DATLAT Default: 0x9
4787 13:08:18.139426 0, 0xFFFF, sum = 0
4788 13:08:18.142927 1, 0xFFFF, sum = 0
4789 13:08:18.142991 2, 0xFFFF, sum = 0
4790 13:08:18.146218 3, 0xFFFF, sum = 0
4791 13:08:18.146286 4, 0xFFFF, sum = 0
4792 13:08:18.149537 5, 0xFFFF, sum = 0
4793 13:08:18.149623 6, 0xFFFF, sum = 0
4794 13:08:18.153161 7, 0xFFFF, sum = 0
4795 13:08:18.153247 8, 0x0, sum = 1
4796 13:08:18.156200 9, 0x0, sum = 2
4797 13:08:18.156285 10, 0x0, sum = 3
4798 13:08:18.156367 11, 0x0, sum = 4
4799 13:08:18.159674 best_step = 9
4800 13:08:18.159758
4801 13:08:18.159834 ==
4802 13:08:18.162846 Dram Type= 6, Freq= 0, CH_1, rank 1
4803 13:08:18.166492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4804 13:08:18.166551 ==
4805 13:08:18.169521 RX Vref Scan: 0
4806 13:08:18.169606
4807 13:08:18.169684 RX Vref 0 -> 0, step: 1
4808 13:08:18.172711
4809 13:08:18.172793 RX Delay -195 -> 252, step: 8
4810 13:08:18.180201 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4811 13:08:18.183514 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4812 13:08:18.186785 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4813 13:08:18.190348 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4814 13:08:18.197310 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4815 13:08:18.200281 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4816 13:08:18.203786 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4817 13:08:18.207071 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4818 13:08:18.210235 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4819 13:08:18.216951 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4820 13:08:18.219997 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4821 13:08:18.223725 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4822 13:08:18.226822 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4823 13:08:18.233596 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4824 13:08:18.236928 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4825 13:08:18.240330 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4826 13:08:18.240422 ==
4827 13:08:18.243128 Dram Type= 6, Freq= 0, CH_1, rank 1
4828 13:08:18.250348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4829 13:08:18.250444 ==
4830 13:08:18.250528 DQS Delay:
4831 13:08:18.250608 DQS0 = 0, DQS1 = 0
4832 13:08:18.253254 DQM Delay:
4833 13:08:18.253336 DQM0 = 35, DQM1 = 29
4834 13:08:18.256798 DQ Delay:
4835 13:08:18.259816 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4836 13:08:18.259903 DQ4 =32, DQ5 =44, DQ6 =48, DQ7 =32
4837 13:08:18.263460 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4838 13:08:18.266887 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4839 13:08:18.270018
4840 13:08:18.270109
4841 13:08:18.276763 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d5d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4842 13:08:18.280037 CH1 RK1: MR19=808, MR18=3D5D
4843 13:08:18.286993 CH1_RK1: MR19=0x808, MR18=0x3D5D, DQSOSC=392, MR23=63, INC=170, DEC=113
4844 13:08:18.290015 [RxdqsGatingPostProcess] freq 600
4845 13:08:18.293311 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4846 13:08:18.296559 Pre-setting of DQS Precalculation
4847 13:08:18.303212 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4848 13:08:18.309869 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4849 13:08:18.316327 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4850 13:08:18.316422
4851 13:08:18.316506
4852 13:08:18.319760 [Calibration Summary] 1200 Mbps
4853 13:08:18.319849 CH 0, Rank 0
4854 13:08:18.323445 SW Impedance : PASS
4855 13:08:18.326661 DUTY Scan : NO K
4856 13:08:18.326723 ZQ Calibration : PASS
4857 13:08:18.330088 Jitter Meter : NO K
4858 13:08:18.333237 CBT Training : PASS
4859 13:08:18.333302 Write leveling : PASS
4860 13:08:18.336431 RX DQS gating : PASS
4861 13:08:18.336517 RX DQ/DQS(RDDQC) : PASS
4862 13:08:18.340009 TX DQ/DQS : PASS
4863 13:08:18.343205 RX DATLAT : PASS
4864 13:08:18.343268 RX DQ/DQS(Engine): PASS
4865 13:08:18.346542 TX OE : NO K
4866 13:08:18.346607 All Pass.
4867 13:08:18.346659
4868 13:08:18.349774 CH 0, Rank 1
4869 13:08:18.349863 SW Impedance : PASS
4870 13:08:18.353025 DUTY Scan : NO K
4871 13:08:18.356054 ZQ Calibration : PASS
4872 13:08:18.356120 Jitter Meter : NO K
4873 13:08:18.359485 CBT Training : PASS
4874 13:08:18.363120 Write leveling : PASS
4875 13:08:18.363182 RX DQS gating : PASS
4876 13:08:18.366229 RX DQ/DQS(RDDQC) : PASS
4877 13:08:18.369754 TX DQ/DQS : PASS
4878 13:08:18.369844 RX DATLAT : PASS
4879 13:08:18.372939 RX DQ/DQS(Engine): PASS
4880 13:08:18.375848 TX OE : NO K
4881 13:08:18.375935 All Pass.
4882 13:08:18.376013
4883 13:08:18.376090 CH 1, Rank 0
4884 13:08:18.379610 SW Impedance : PASS
4885 13:08:18.382945 DUTY Scan : NO K
4886 13:08:18.383004 ZQ Calibration : PASS
4887 13:08:18.386222 Jitter Meter : NO K
4888 13:08:18.389643 CBT Training : PASS
4889 13:08:18.389705 Write leveling : PASS
4890 13:08:18.392685 RX DQS gating : PASS
4891 13:08:18.392769 RX DQ/DQS(RDDQC) : PASS
4892 13:08:18.395921 TX DQ/DQS : PASS
4893 13:08:18.399851 RX DATLAT : PASS
4894 13:08:18.399937 RX DQ/DQS(Engine): PASS
4895 13:08:18.402580 TX OE : NO K
4896 13:08:18.402665 All Pass.
4897 13:08:18.402742
4898 13:08:18.405874 CH 1, Rank 1
4899 13:08:18.405959 SW Impedance : PASS
4900 13:08:18.409650 DUTY Scan : NO K
4901 13:08:18.412747 ZQ Calibration : PASS
4902 13:08:18.412836 Jitter Meter : NO K
4903 13:08:18.416195 CBT Training : PASS
4904 13:08:18.418900 Write leveling : PASS
4905 13:08:18.418962 RX DQS gating : PASS
4906 13:08:18.422707 RX DQ/DQS(RDDQC) : PASS
4907 13:08:18.425776 TX DQ/DQS : PASS
4908 13:08:18.425865 RX DATLAT : PASS
4909 13:08:18.429289 RX DQ/DQS(Engine): PASS
4910 13:08:18.432871 TX OE : NO K
4911 13:08:18.432945 All Pass.
4912 13:08:18.433004
4913 13:08:18.433062 DramC Write-DBI off
4914 13:08:18.436034 PER_BANK_REFRESH: Hybrid Mode
4915 13:08:18.439219 TX_TRACKING: ON
4916 13:08:18.446052 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4917 13:08:18.449068 [FAST_K] Save calibration result to emmc
4918 13:08:18.455719 dramc_set_vcore_voltage set vcore to 662500
4919 13:08:18.455797 Read voltage for 933, 3
4920 13:08:18.455880 Vio18 = 0
4921 13:08:18.458909 Vcore = 662500
4922 13:08:18.458980 Vdram = 0
4923 13:08:18.459036 Vddq = 0
4924 13:08:18.462653 Vmddr = 0
4925 13:08:18.465881 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4926 13:08:18.472613 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4927 13:08:18.475709 MEM_TYPE=3, freq_sel=17
4928 13:08:18.475800 sv_algorithm_assistance_LP4_1600
4929 13:08:18.482499 ============ PULL DRAM RESETB DOWN ============
4930 13:08:18.485680 ========== PULL DRAM RESETB DOWN end =========
4931 13:08:18.489068 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4932 13:08:18.492126 ===================================
4933 13:08:18.495831 LPDDR4 DRAM CONFIGURATION
4934 13:08:18.498511 ===================================
4935 13:08:18.501915 EX_ROW_EN[0] = 0x0
4936 13:08:18.501991 EX_ROW_EN[1] = 0x0
4937 13:08:18.505377 LP4Y_EN = 0x0
4938 13:08:18.505468 WORK_FSP = 0x0
4939 13:08:18.508795 WL = 0x3
4940 13:08:18.508884 RL = 0x3
4941 13:08:18.511950 BL = 0x2
4942 13:08:18.512042 RPST = 0x0
4943 13:08:18.515644 RD_PRE = 0x0
4944 13:08:18.515734 WR_PRE = 0x1
4945 13:08:18.518908 WR_PST = 0x0
4946 13:08:18.518971 DBI_WR = 0x0
4947 13:08:18.522009 DBI_RD = 0x0
4948 13:08:18.522093 OTF = 0x1
4949 13:08:18.525365 ===================================
4950 13:08:18.528704 ===================================
4951 13:08:18.531914 ANA top config
4952 13:08:18.535388 ===================================
4953 13:08:18.538505 DLL_ASYNC_EN = 0
4954 13:08:18.538590 ALL_SLAVE_EN = 1
4955 13:08:18.541846 NEW_RANK_MODE = 1
4956 13:08:18.545554 DLL_IDLE_MODE = 1
4957 13:08:18.548739 LP45_APHY_COMB_EN = 1
4958 13:08:18.551748 TX_ODT_DIS = 1
4959 13:08:18.551810 NEW_8X_MODE = 1
4960 13:08:18.555524 ===================================
4961 13:08:18.558524 ===================================
4962 13:08:18.562016 data_rate = 1866
4963 13:08:18.565206 CKR = 1
4964 13:08:18.568611 DQ_P2S_RATIO = 8
4965 13:08:18.572037 ===================================
4966 13:08:18.575270 CA_P2S_RATIO = 8
4967 13:08:18.578801 DQ_CA_OPEN = 0
4968 13:08:18.578869 DQ_SEMI_OPEN = 0
4969 13:08:18.582097 CA_SEMI_OPEN = 0
4970 13:08:18.584871 CA_FULL_RATE = 0
4971 13:08:18.588652 DQ_CKDIV4_EN = 1
4972 13:08:18.591746 CA_CKDIV4_EN = 1
4973 13:08:18.595150 CA_PREDIV_EN = 0
4974 13:08:18.595217 PH8_DLY = 0
4975 13:08:18.598255 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4976 13:08:18.601913 DQ_AAMCK_DIV = 4
4977 13:08:18.604714 CA_AAMCK_DIV = 4
4978 13:08:18.608286 CA_ADMCK_DIV = 4
4979 13:08:18.611655 DQ_TRACK_CA_EN = 0
4980 13:08:18.611750 CA_PICK = 933
4981 13:08:18.615152 CA_MCKIO = 933
4982 13:08:18.618257 MCKIO_SEMI = 0
4983 13:08:18.621621 PLL_FREQ = 3732
4984 13:08:18.625001 DQ_UI_PI_RATIO = 32
4985 13:08:18.628465 CA_UI_PI_RATIO = 0
4986 13:08:18.631802 ===================================
4987 13:08:18.634736 ===================================
4988 13:08:18.634803 memory_type:LPDDR4
4989 13:08:18.638297 GP_NUM : 10
4990 13:08:18.641799 SRAM_EN : 1
4991 13:08:18.641865 MD32_EN : 0
4992 13:08:18.644748 ===================================
4993 13:08:18.648352 [ANA_INIT] >>>>>>>>>>>>>>
4994 13:08:18.651352 <<<<<< [CONFIGURE PHASE]: ANA_TX
4995 13:08:18.655016 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4996 13:08:18.658034 ===================================
4997 13:08:18.661118 data_rate = 1866,PCW = 0X8f00
4998 13:08:18.664799 ===================================
4999 13:08:18.668399 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5000 13:08:18.671657 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5001 13:08:18.678001 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5002 13:08:18.681080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5003 13:08:18.684724 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5004 13:08:18.687946 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5005 13:08:18.690940 [ANA_INIT] flow start
5006 13:08:18.694433 [ANA_INIT] PLL >>>>>>>>
5007 13:08:18.694523 [ANA_INIT] PLL <<<<<<<<
5008 13:08:18.697701 [ANA_INIT] MIDPI >>>>>>>>
5009 13:08:18.700986 [ANA_INIT] MIDPI <<<<<<<<
5010 13:08:18.704248 [ANA_INIT] DLL >>>>>>>>
5011 13:08:18.704340 [ANA_INIT] flow end
5012 13:08:18.707944 ============ LP4 DIFF to SE enter ============
5013 13:08:18.714352 ============ LP4 DIFF to SE exit ============
5014 13:08:18.714446 [ANA_INIT] <<<<<<<<<<<<<
5015 13:08:18.718285 [Flow] Enable top DCM control >>>>>
5016 13:08:18.721150 [Flow] Enable top DCM control <<<<<
5017 13:08:18.724738 Enable DLL master slave shuffle
5018 13:08:18.731164 ==============================================================
5019 13:08:18.731259 Gating Mode config
5020 13:08:18.737914 ==============================================================
5021 13:08:18.740838 Config description:
5022 13:08:18.751043 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5023 13:08:18.757502 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5024 13:08:18.761117 SELPH_MODE 0: By rank 1: By Phase
5025 13:08:18.767525 ==============================================================
5026 13:08:18.771140 GAT_TRACK_EN = 1
5027 13:08:18.771230 RX_GATING_MODE = 2
5028 13:08:18.774210 RX_GATING_TRACK_MODE = 2
5029 13:08:18.777222 SELPH_MODE = 1
5030 13:08:18.780923 PICG_EARLY_EN = 1
5031 13:08:18.784450 VALID_LAT_VALUE = 1
5032 13:08:18.790704 ==============================================================
5033 13:08:18.793807 Enter into Gating configuration >>>>
5034 13:08:18.797294 Exit from Gating configuration <<<<
5035 13:08:18.800753 Enter into DVFS_PRE_config >>>>>
5036 13:08:18.810780 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5037 13:08:18.814021 Exit from DVFS_PRE_config <<<<<
5038 13:08:18.817238 Enter into PICG configuration >>>>
5039 13:08:18.821252 Exit from PICG configuration <<<<
5040 13:08:18.824371 [RX_INPUT] configuration >>>>>
5041 13:08:18.827437 [RX_INPUT] configuration <<<<<
5042 13:08:18.830464 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5043 13:08:18.837349 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5044 13:08:18.843575 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5045 13:08:18.850740 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5046 13:08:18.853666 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5047 13:08:18.860537 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5048 13:08:18.863716 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5049 13:08:18.870289 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5050 13:08:18.873528 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5051 13:08:18.876941 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5052 13:08:18.880532 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5053 13:08:18.886683 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5054 13:08:18.890162 ===================================
5055 13:08:18.890254 LPDDR4 DRAM CONFIGURATION
5056 13:08:18.893265 ===================================
5057 13:08:18.897017 EX_ROW_EN[0] = 0x0
5058 13:08:18.900290 EX_ROW_EN[1] = 0x0
5059 13:08:18.900381 LP4Y_EN = 0x0
5060 13:08:18.903407 WORK_FSP = 0x0
5061 13:08:18.903486 WL = 0x3
5062 13:08:18.906739 RL = 0x3
5063 13:08:18.906804 BL = 0x2
5064 13:08:18.910363 RPST = 0x0
5065 13:08:18.910454 RD_PRE = 0x0
5066 13:08:18.913547 WR_PRE = 0x1
5067 13:08:18.913635 WR_PST = 0x0
5068 13:08:18.917173 DBI_WR = 0x0
5069 13:08:18.917237 DBI_RD = 0x0
5070 13:08:18.919982 OTF = 0x1
5071 13:08:18.923532 ===================================
5072 13:08:18.926456 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5073 13:08:18.930052 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5074 13:08:18.936839 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5075 13:08:18.940020 ===================================
5076 13:08:18.940112 LPDDR4 DRAM CONFIGURATION
5077 13:08:18.943120 ===================================
5078 13:08:18.946772 EX_ROW_EN[0] = 0x10
5079 13:08:18.950095 EX_ROW_EN[1] = 0x0
5080 13:08:18.950223 LP4Y_EN = 0x0
5081 13:08:18.953266 WORK_FSP = 0x0
5082 13:08:18.953331 WL = 0x3
5083 13:08:18.956753 RL = 0x3
5084 13:08:18.956888 BL = 0x2
5085 13:08:18.959756 RPST = 0x0
5086 13:08:18.959848 RD_PRE = 0x0
5087 13:08:18.963284 WR_PRE = 0x1
5088 13:08:18.963432 WR_PST = 0x0
5089 13:08:18.966731 DBI_WR = 0x0
5090 13:08:18.966864 DBI_RD = 0x0
5091 13:08:18.969726 OTF = 0x1
5092 13:08:18.973435 ===================================
5093 13:08:18.980069 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5094 13:08:18.983277 nWR fixed to 30
5095 13:08:18.983371 [ModeRegInit_LP4] CH0 RK0
5096 13:08:18.986537 [ModeRegInit_LP4] CH0 RK1
5097 13:08:18.989928 [ModeRegInit_LP4] CH1 RK0
5098 13:08:18.992878 [ModeRegInit_LP4] CH1 RK1
5099 13:08:18.992968 match AC timing 9
5100 13:08:18.996261 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5101 13:08:19.003457 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5102 13:08:19.006285 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5103 13:08:19.010190 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5104 13:08:19.016115 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5105 13:08:19.016183 ==
5106 13:08:19.019719 Dram Type= 6, Freq= 0, CH_0, rank 0
5107 13:08:19.023193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 13:08:19.023286 ==
5109 13:08:19.029747 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5110 13:08:19.035995 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5111 13:08:19.039860 [CA 0] Center 38 (8~69) winsize 62
5112 13:08:19.042679 [CA 1] Center 38 (8~69) winsize 62
5113 13:08:19.046208 [CA 2] Center 35 (5~66) winsize 62
5114 13:08:19.049624 [CA 3] Center 35 (5~66) winsize 62
5115 13:08:19.053329 [CA 4] Center 34 (4~65) winsize 62
5116 13:08:19.053398 [CA 5] Center 33 (3~64) winsize 62
5117 13:08:19.056114
5118 13:08:19.059565 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5119 13:08:19.059657
5120 13:08:19.063249 [CATrainingPosCal] consider 1 rank data
5121 13:08:19.066094 u2DelayCellTimex100 = 270/100 ps
5122 13:08:19.069758 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5123 13:08:19.073143 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5124 13:08:19.076351 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5125 13:08:19.079446 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5126 13:08:19.082975 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5127 13:08:19.085975 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5128 13:08:19.086066
5129 13:08:19.089539 CA PerBit enable=1, Macro0, CA PI delay=33
5130 13:08:19.092675
5131 13:08:19.092775 [CBTSetCACLKResult] CA Dly = 33
5132 13:08:19.096174 CS Dly: 7 (0~38)
5133 13:08:19.096285 ==
5134 13:08:19.099189 Dram Type= 6, Freq= 0, CH_0, rank 1
5135 13:08:19.102573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 13:08:19.102718 ==
5137 13:08:19.109357 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5138 13:08:19.115693 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5139 13:08:19.119236 [CA 0] Center 38 (8~69) winsize 62
5140 13:08:19.122562 [CA 1] Center 38 (8~69) winsize 62
5141 13:08:19.126037 [CA 2] Center 35 (5~66) winsize 62
5142 13:08:19.129517 [CA 3] Center 35 (5~66) winsize 62
5143 13:08:19.132428 [CA 4] Center 34 (4~65) winsize 62
5144 13:08:19.135825 [CA 5] Center 33 (3~64) winsize 62
5145 13:08:19.135922
5146 13:08:19.138753 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5147 13:08:19.138823
5148 13:08:19.142415 [CATrainingPosCal] consider 2 rank data
5149 13:08:19.145601 u2DelayCellTimex100 = 270/100 ps
5150 13:08:19.149159 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5151 13:08:19.152826 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5152 13:08:19.155769 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5153 13:08:19.158980 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5154 13:08:19.162025 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5155 13:08:19.165639 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5156 13:08:19.168700
5157 13:08:19.172055 CA PerBit enable=1, Macro0, CA PI delay=33
5158 13:08:19.172150
5159 13:08:19.175500 [CBTSetCACLKResult] CA Dly = 33
5160 13:08:19.175589 CS Dly: 7 (0~39)
5161 13:08:19.175673
5162 13:08:19.179061 ----->DramcWriteLeveling(PI) begin...
5163 13:08:19.179130 ==
5164 13:08:19.181974 Dram Type= 6, Freq= 0, CH_0, rank 0
5165 13:08:19.185840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5166 13:08:19.188796 ==
5167 13:08:19.188862 Write leveling (Byte 0): 30 => 30
5168 13:08:19.192252 Write leveling (Byte 1): 32 => 32
5169 13:08:19.195375 DramcWriteLeveling(PI) end<-----
5170 13:08:19.195446
5171 13:08:19.195501 ==
5172 13:08:19.198961 Dram Type= 6, Freq= 0, CH_0, rank 0
5173 13:08:19.205499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5174 13:08:19.205569 ==
5175 13:08:19.205626 [Gating] SW mode calibration
5176 13:08:19.215401 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5177 13:08:19.218715 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5178 13:08:19.225527 0 14 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5179 13:08:19.228427 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5180 13:08:19.231782 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 13:08:19.235194 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 13:08:19.241716 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 13:08:19.245440 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 13:08:19.248613 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 13:08:19.254970 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5186 13:08:19.258762 0 15 0 | B1->B0 | 3232 2b2b | 0 0 | (0 1) (1 0)
5187 13:08:19.262410 0 15 4 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5188 13:08:19.268395 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 13:08:19.271852 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 13:08:19.275446 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 13:08:19.281645 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 13:08:19.285441 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 13:08:19.288491 0 15 28 | B1->B0 | 2323 2928 | 0 1 | (0 0) (1 1)
5194 13:08:19.294966 1 0 0 | B1->B0 | 2828 3b3b | 0 1 | (1 1) (0 0)
5195 13:08:19.298144 1 0 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5196 13:08:19.301905 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 13:08:19.308479 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 13:08:19.311659 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 13:08:19.314775 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 13:08:19.321991 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 13:08:19.324706 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5202 13:08:19.328294 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5203 13:08:19.335277 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 13:08:19.337989 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 13:08:19.341412 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 13:08:19.347944 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 13:08:19.351763 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 13:08:19.354732 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 13:08:19.361406 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 13:08:19.364830 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 13:08:19.368101 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 13:08:19.374629 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 13:08:19.378026 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 13:08:19.381111 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 13:08:19.387818 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 13:08:19.391482 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 13:08:19.394909 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5218 13:08:19.397995 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5219 13:08:19.401542 Total UI for P1: 0, mck2ui 16
5220 13:08:19.404494 best dqsien dly found for B0: ( 1, 2, 28)
5221 13:08:19.411363 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5222 13:08:19.414362 Total UI for P1: 0, mck2ui 16
5223 13:08:19.418026 best dqsien dly found for B1: ( 1, 3, 0)
5224 13:08:19.421133 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5225 13:08:19.424265 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5226 13:08:19.424329
5227 13:08:19.427962 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5228 13:08:19.430901 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5229 13:08:19.434596 [Gating] SW calibration Done
5230 13:08:19.434662 ==
5231 13:08:19.437652 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 13:08:19.440840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 13:08:19.440906 ==
5234 13:08:19.444304 RX Vref Scan: 0
5235 13:08:19.444369
5236 13:08:19.444426 RX Vref 0 -> 0, step: 1
5237 13:08:19.444477
5238 13:08:19.447501 RX Delay -80 -> 252, step: 8
5239 13:08:19.454432 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5240 13:08:19.457916 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5241 13:08:19.461246 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5242 13:08:19.464127 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5243 13:08:19.467848 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5244 13:08:19.470939 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5245 13:08:19.477591 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5246 13:08:19.480616 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5247 13:08:19.484273 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5248 13:08:19.487135 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5249 13:08:19.490861 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5250 13:08:19.497684 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5251 13:08:19.500736 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5252 13:08:19.503926 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5253 13:08:19.507514 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5254 13:08:19.510501 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5255 13:08:19.510597 ==
5256 13:08:19.514270 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 13:08:19.520556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 13:08:19.520660 ==
5259 13:08:19.520758 DQS Delay:
5260 13:08:19.524123 DQS0 = 0, DQS1 = 0
5261 13:08:19.524220 DQM Delay:
5262 13:08:19.524307 DQM0 = 94, DQM1 = 83
5263 13:08:19.527448 DQ Delay:
5264 13:08:19.530405 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5265 13:08:19.533929 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5266 13:08:19.537096 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =75
5267 13:08:19.540975 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5268 13:08:19.541086
5269 13:08:19.541169
5270 13:08:19.541252 ==
5271 13:08:19.543806 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 13:08:19.546892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 13:08:19.546963 ==
5274 13:08:19.547020
5275 13:08:19.547072
5276 13:08:19.550484 TX Vref Scan disable
5277 13:08:19.553930 == TX Byte 0 ==
5278 13:08:19.557076 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5279 13:08:19.560673 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5280 13:08:19.563850 == TX Byte 1 ==
5281 13:08:19.567164 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5282 13:08:19.570218 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5283 13:08:19.570286 ==
5284 13:08:19.573787 Dram Type= 6, Freq= 0, CH_0, rank 0
5285 13:08:19.577012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 13:08:19.580516 ==
5287 13:08:19.580585
5288 13:08:19.580641
5289 13:08:19.580696 TX Vref Scan disable
5290 13:08:19.583847 == TX Byte 0 ==
5291 13:08:19.587274 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5292 13:08:19.593663 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5293 13:08:19.593756 == TX Byte 1 ==
5294 13:08:19.597447 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5295 13:08:19.604032 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5296 13:08:19.604126
5297 13:08:19.604208 [DATLAT]
5298 13:08:19.604288 Freq=933, CH0 RK0
5299 13:08:19.604371
5300 13:08:19.606973 DATLAT Default: 0xd
5301 13:08:19.607060 0, 0xFFFF, sum = 0
5302 13:08:19.610204 1, 0xFFFF, sum = 0
5303 13:08:19.610269 2, 0xFFFF, sum = 0
5304 13:08:19.613888 3, 0xFFFF, sum = 0
5305 13:08:19.616795 4, 0xFFFF, sum = 0
5306 13:08:19.616860 5, 0xFFFF, sum = 0
5307 13:08:19.620337 6, 0xFFFF, sum = 0
5308 13:08:19.620407 7, 0xFFFF, sum = 0
5309 13:08:19.623992 8, 0xFFFF, sum = 0
5310 13:08:19.624062 9, 0xFFFF, sum = 0
5311 13:08:19.627110 10, 0x0, sum = 1
5312 13:08:19.627172 11, 0x0, sum = 2
5313 13:08:19.627226 12, 0x0, sum = 3
5314 13:08:19.630126 13, 0x0, sum = 4
5315 13:08:19.630191 best_step = 11
5316 13:08:19.630244
5317 13:08:19.633712 ==
5318 13:08:19.633772 Dram Type= 6, Freq= 0, CH_0, rank 0
5319 13:08:19.640659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5320 13:08:19.640725 ==
5321 13:08:19.640779 RX Vref Scan: 1
5322 13:08:19.640831
5323 13:08:19.643452 RX Vref 0 -> 0, step: 1
5324 13:08:19.643515
5325 13:08:19.647071 RX Delay -69 -> 252, step: 4
5326 13:08:19.647137
5327 13:08:19.650422 Set Vref, RX VrefLevel [Byte0]: 61
5328 13:08:19.653660 [Byte1]: 51
5329 13:08:19.653727
5330 13:08:19.656686 Final RX Vref Byte 0 = 61 to rank0
5331 13:08:19.660250 Final RX Vref Byte 1 = 51 to rank0
5332 13:08:19.663448 Final RX Vref Byte 0 = 61 to rank1
5333 13:08:19.667145 Final RX Vref Byte 1 = 51 to rank1==
5334 13:08:19.670469 Dram Type= 6, Freq= 0, CH_0, rank 0
5335 13:08:19.673356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 13:08:19.676913 ==
5337 13:08:19.676978 DQS Delay:
5338 13:08:19.677058 DQS0 = 0, DQS1 = 0
5339 13:08:19.679961 DQM Delay:
5340 13:08:19.680027 DQM0 = 95, DQM1 = 83
5341 13:08:19.683071 DQ Delay:
5342 13:08:19.683137 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5343 13:08:19.686561 DQ4 =94, DQ5 =84, DQ6 =102, DQ7 =106
5344 13:08:19.689762 DQ8 =78, DQ9 =68, DQ10 =82, DQ11 =80
5345 13:08:19.693231 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =90
5346 13:08:19.696782
5347 13:08:19.696848
5348 13:08:19.703522 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5349 13:08:19.706712 CH0 RK0: MR19=505, MR18=1515
5350 13:08:19.713038 CH0_RK0: MR19=0x505, MR18=0x1515, DQSOSC=415, MR23=63, INC=62, DEC=41
5351 13:08:19.713110
5352 13:08:19.716517 ----->DramcWriteLeveling(PI) begin...
5353 13:08:19.716583 ==
5354 13:08:19.719794 Dram Type= 6, Freq= 0, CH_0, rank 1
5355 13:08:19.723189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5356 13:08:19.723254 ==
5357 13:08:19.726663 Write leveling (Byte 0): 29 => 29
5358 13:08:19.729762 Write leveling (Byte 1): 28 => 28
5359 13:08:19.733467 DramcWriteLeveling(PI) end<-----
5360 13:08:19.733568
5361 13:08:19.733635 ==
5362 13:08:19.736491 Dram Type= 6, Freq= 0, CH_0, rank 1
5363 13:08:19.739861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 13:08:19.739925 ==
5365 13:08:19.742924 [Gating] SW mode calibration
5366 13:08:19.749745 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5367 13:08:19.756204 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5368 13:08:19.759440 0 14 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
5369 13:08:19.762985 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 13:08:19.769443 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 13:08:19.772636 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 13:08:19.776356 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 13:08:19.782665 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 13:08:19.786596 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5375 13:08:19.789927 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 1)
5376 13:08:19.796286 0 15 0 | B1->B0 | 2d2d 2323 | 1 0 | (0 0) (0 0)
5377 13:08:19.799909 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 13:08:19.802872 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 13:08:19.809706 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 13:08:19.812654 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 13:08:19.816046 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 13:08:19.822878 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 13:08:19.826067 0 15 28 | B1->B0 | 2727 3b3b | 0 1 | (0 0) (0 0)
5384 13:08:19.829063 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5385 13:08:19.835909 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 13:08:19.839210 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 13:08:19.842357 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 13:08:19.848912 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 13:08:19.852664 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 13:08:19.855545 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 13:08:19.862199 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5392 13:08:19.865600 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5393 13:08:19.868919 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 13:08:19.875315 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 13:08:19.879011 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 13:08:19.882073 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 13:08:19.888664 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 13:08:19.892131 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 13:08:19.895880 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 13:08:19.902250 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 13:08:19.905696 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 13:08:19.908742 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 13:08:19.915496 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 13:08:19.919118 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 13:08:19.922218 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 13:08:19.928452 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5407 13:08:19.931590 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5408 13:08:19.935400 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5409 13:08:19.938830 Total UI for P1: 0, mck2ui 16
5410 13:08:19.941766 best dqsien dly found for B0: ( 1, 2, 26)
5411 13:08:19.945134 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5412 13:08:19.948771 Total UI for P1: 0, mck2ui 16
5413 13:08:19.951749 best dqsien dly found for B1: ( 1, 3, 0)
5414 13:08:19.955080 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5415 13:08:19.958496 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5416 13:08:19.958564
5417 13:08:19.965064 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5418 13:08:19.968687 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5419 13:08:19.972065 [Gating] SW calibration Done
5420 13:08:19.972158 ==
5421 13:08:19.974978 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 13:08:19.978551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 13:08:19.978645 ==
5424 13:08:19.978734 RX Vref Scan: 0
5425 13:08:19.978817
5426 13:08:19.981559 RX Vref 0 -> 0, step: 1
5427 13:08:19.981649
5428 13:08:19.984810 RX Delay -80 -> 252, step: 8
5429 13:08:19.988477 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5430 13:08:19.992145 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5431 13:08:19.995243 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5432 13:08:20.001734 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5433 13:08:20.004781 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5434 13:08:20.008599 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5435 13:08:20.011505 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5436 13:08:20.014694 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5437 13:08:20.021347 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5438 13:08:20.025042 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5439 13:08:20.027993 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5440 13:08:20.031414 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5441 13:08:20.034605 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5442 13:08:20.041627 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5443 13:08:20.044525 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5444 13:08:20.048463 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5445 13:08:20.048557 ==
5446 13:08:20.051356 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 13:08:20.054581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 13:08:20.054669 ==
5449 13:08:20.058117 DQS Delay:
5450 13:08:20.058199 DQS0 = 0, DQS1 = 0
5451 13:08:20.058259 DQM Delay:
5452 13:08:20.061108 DQM0 = 92, DQM1 = 83
5453 13:08:20.061195 DQ Delay:
5454 13:08:20.064815 DQ0 =91, DQ1 =95, DQ2 =87, DQ3 =91
5455 13:08:20.068334 DQ4 =95, DQ5 =75, DQ6 =103, DQ7 =103
5456 13:08:20.071601 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =75
5457 13:08:20.074856 DQ12 =87, DQ13 =95, DQ14 =95, DQ15 =87
5458 13:08:20.074971
5459 13:08:20.075028
5460 13:08:20.075080 ==
5461 13:08:20.077907 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 13:08:20.084406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 13:08:20.084493 ==
5464 13:08:20.084552
5465 13:08:20.084604
5466 13:08:20.084674 TX Vref Scan disable
5467 13:08:20.088426 == TX Byte 0 ==
5468 13:08:20.091761 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5469 13:08:20.098016 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5470 13:08:20.098160 == TX Byte 1 ==
5471 13:08:20.101810 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5472 13:08:20.108308 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5473 13:08:20.108382 ==
5474 13:08:20.111355 Dram Type= 6, Freq= 0, CH_0, rank 1
5475 13:08:20.114618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 13:08:20.114692 ==
5477 13:08:20.114750
5478 13:08:20.114802
5479 13:08:20.117773 TX Vref Scan disable
5480 13:08:20.117881 == TX Byte 0 ==
5481 13:08:20.124885 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5482 13:08:20.127866 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5483 13:08:20.127959 == TX Byte 1 ==
5484 13:08:20.134755 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5485 13:08:20.138255 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5486 13:08:20.138321
5487 13:08:20.138376 [DATLAT]
5488 13:08:20.141546 Freq=933, CH0 RK1
5489 13:08:20.141635
5490 13:08:20.141715 DATLAT Default: 0xb
5491 13:08:20.144527 0, 0xFFFF, sum = 0
5492 13:08:20.144620 1, 0xFFFF, sum = 0
5493 13:08:20.147942 2, 0xFFFF, sum = 0
5494 13:08:20.148031 3, 0xFFFF, sum = 0
5495 13:08:20.151570 4, 0xFFFF, sum = 0
5496 13:08:20.154532 5, 0xFFFF, sum = 0
5497 13:08:20.154601 6, 0xFFFF, sum = 0
5498 13:08:20.158024 7, 0xFFFF, sum = 0
5499 13:08:20.158149 8, 0xFFFF, sum = 0
5500 13:08:20.161669 9, 0xFFFF, sum = 0
5501 13:08:20.161821 10, 0x0, sum = 1
5502 13:08:20.161954 11, 0x0, sum = 2
5503 13:08:20.164635 12, 0x0, sum = 3
5504 13:08:20.164726 13, 0x0, sum = 4
5505 13:08:20.167710 best_step = 11
5506 13:08:20.167801
5507 13:08:20.167910 ==
5508 13:08:20.171267 Dram Type= 6, Freq= 0, CH_0, rank 1
5509 13:08:20.174530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 13:08:20.174600 ==
5511 13:08:20.177595 RX Vref Scan: 0
5512 13:08:20.177689
5513 13:08:20.177774 RX Vref 0 -> 0, step: 1
5514 13:08:20.181537
5515 13:08:20.181634 RX Delay -77 -> 252, step: 4
5516 13:08:20.188437 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5517 13:08:20.192099 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5518 13:08:20.195148 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5519 13:08:20.198795 iDelay=199, Bit 3, Center 86 (-9 ~ 182) 192
5520 13:08:20.201964 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5521 13:08:20.208514 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5522 13:08:20.211700 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5523 13:08:20.215430 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5524 13:08:20.218360 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5525 13:08:20.222011 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5526 13:08:20.228329 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5527 13:08:20.231817 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5528 13:08:20.234807 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5529 13:08:20.238730 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5530 13:08:20.241938 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5531 13:08:20.248454 iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184
5532 13:08:20.248529 ==
5533 13:08:20.251240 Dram Type= 6, Freq= 0, CH_0, rank 1
5534 13:08:20.255053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 13:08:20.255126 ==
5536 13:08:20.255184 DQS Delay:
5537 13:08:20.258221 DQS0 = 0, DQS1 = 0
5538 13:08:20.258296 DQM Delay:
5539 13:08:20.261903 DQM0 = 92, DQM1 = 84
5540 13:08:20.261979 DQ Delay:
5541 13:08:20.264900 DQ0 =92, DQ1 =92, DQ2 =90, DQ3 =86
5542 13:08:20.268151 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =102
5543 13:08:20.271466 DQ8 =76, DQ9 =68, DQ10 =86, DQ11 =76
5544 13:08:20.274713 DQ12 =92, DQ13 =90, DQ14 =94, DQ15 =90
5545 13:08:20.274802
5546 13:08:20.274862
5547 13:08:20.281613 [DQSOSCAuto] RK1, (LSB)MR18= 0x3112, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 406 ps
5548 13:08:20.284746 CH0 RK1: MR19=505, MR18=3112
5549 13:08:20.291407 CH0_RK1: MR19=0x505, MR18=0x3112, DQSOSC=406, MR23=63, INC=65, DEC=43
5550 13:08:20.294630 [RxdqsGatingPostProcess] freq 933
5551 13:08:20.301172 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5552 13:08:20.304809 best DQS0 dly(2T, 0.5T) = (0, 10)
5553 13:08:20.304901 best DQS1 dly(2T, 0.5T) = (0, 11)
5554 13:08:20.308003 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5555 13:08:20.311235 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5556 13:08:20.314545 best DQS0 dly(2T, 0.5T) = (0, 10)
5557 13:08:20.317788 best DQS1 dly(2T, 0.5T) = (0, 11)
5558 13:08:20.321142 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5559 13:08:20.324672 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5560 13:08:20.328368 Pre-setting of DQS Precalculation
5561 13:08:20.334539 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5562 13:08:20.334609 ==
5563 13:08:20.338019 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 13:08:20.341533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 13:08:20.341624 ==
5566 13:08:20.347620 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5567 13:08:20.351242 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5568 13:08:20.355089 [CA 0] Center 36 (7~66) winsize 60
5569 13:08:20.358529 [CA 1] Center 37 (7~67) winsize 61
5570 13:08:20.362081 [CA 2] Center 35 (5~65) winsize 61
5571 13:08:20.365119 [CA 3] Center 34 (4~64) winsize 61
5572 13:08:20.368761 [CA 4] Center 34 (4~65) winsize 62
5573 13:08:20.371827 [CA 5] Center 34 (4~64) winsize 61
5574 13:08:20.371920
5575 13:08:20.375519 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5576 13:08:20.375584
5577 13:08:20.378512 [CATrainingPosCal] consider 1 rank data
5578 13:08:20.381724 u2DelayCellTimex100 = 270/100 ps
5579 13:08:20.384792 CA0 delay=36 (7~66),Diff = 2 PI (12 cell)
5580 13:08:20.391720 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5581 13:08:20.394786 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5582 13:08:20.398038 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5583 13:08:20.401530 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5584 13:08:20.404708 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5585 13:08:20.404782
5586 13:08:20.408334 CA PerBit enable=1, Macro0, CA PI delay=34
5587 13:08:20.408414
5588 13:08:20.411699 [CBTSetCACLKResult] CA Dly = 34
5589 13:08:20.414857 CS Dly: 6 (0~37)
5590 13:08:20.414935 ==
5591 13:08:20.418028 Dram Type= 6, Freq= 0, CH_1, rank 1
5592 13:08:20.421303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 13:08:20.421379 ==
5594 13:08:20.424581 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5595 13:08:20.431430 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5596 13:08:20.435197 [CA 0] Center 37 (7~68) winsize 62
5597 13:08:20.438695 [CA 1] Center 37 (7~68) winsize 62
5598 13:08:20.441863 [CA 2] Center 34 (5~64) winsize 60
5599 13:08:20.445451 [CA 3] Center 33 (3~64) winsize 62
5600 13:08:20.448738 [CA 4] Center 34 (4~65) winsize 62
5601 13:08:20.451937 [CA 5] Center 33 (3~64) winsize 62
5602 13:08:20.452013
5603 13:08:20.455564 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5604 13:08:20.455639
5605 13:08:20.458477 [CATrainingPosCal] consider 2 rank data
5606 13:08:20.461919 u2DelayCellTimex100 = 270/100 ps
5607 13:08:20.465050 CA0 delay=36 (7~66),Diff = 2 PI (12 cell)
5608 13:08:20.471797 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5609 13:08:20.474718 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5610 13:08:20.478275 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5611 13:08:20.481813 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5612 13:08:20.485133 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5613 13:08:20.485207
5614 13:08:20.488078 CA PerBit enable=1, Macro0, CA PI delay=34
5615 13:08:20.488154
5616 13:08:20.492079 [CBTSetCACLKResult] CA Dly = 34
5617 13:08:20.492153 CS Dly: 7 (0~39)
5618 13:08:20.495045
5619 13:08:20.498146 ----->DramcWriteLeveling(PI) begin...
5620 13:08:20.498223 ==
5621 13:08:20.501628 Dram Type= 6, Freq= 0, CH_1, rank 0
5622 13:08:20.504936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5623 13:08:20.505065 ==
5624 13:08:20.508108 Write leveling (Byte 0): 28 => 28
5625 13:08:20.511512 Write leveling (Byte 1): 29 => 29
5626 13:08:20.514638 DramcWriteLeveling(PI) end<-----
5627 13:08:20.514725
5628 13:08:20.514791 ==
5629 13:08:20.518060 Dram Type= 6, Freq= 0, CH_1, rank 0
5630 13:08:20.521677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5631 13:08:20.521754 ==
5632 13:08:20.524950 [Gating] SW mode calibration
5633 13:08:20.531122 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5634 13:08:20.537975 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5635 13:08:20.540990 0 14 0 | B1->B0 | 3333 3333 | 1 1 | (0 0) (1 1)
5636 13:08:20.544385 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 13:08:20.551182 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 13:08:20.554544 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 13:08:20.557922 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 13:08:20.564250 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5641 13:08:20.567862 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5642 13:08:20.570959 0 14 28 | B1->B0 | 2f2f 2f2f | 1 1 | (1 1) (1 0)
5643 13:08:20.577924 0 15 0 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (1 1)
5644 13:08:20.580957 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 13:08:20.584540 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 13:08:20.590965 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 13:08:20.594426 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 13:08:20.597453 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 13:08:20.604323 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 13:08:20.607730 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 0) (0 0)
5651 13:08:20.611241 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 13:08:20.617644 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 13:08:20.621475 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 13:08:20.624338 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 13:08:20.631221 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 13:08:20.634162 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 13:08:20.637471 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 13:08:20.643922 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5659 13:08:20.647565 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5660 13:08:20.650606 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 13:08:20.654298 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 13:08:20.660786 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 13:08:20.664200 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 13:08:20.667216 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 13:08:20.673906 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 13:08:20.677282 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 13:08:20.680790 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 13:08:20.687151 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 13:08:20.690546 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 13:08:20.693935 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 13:08:20.700589 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 13:08:20.703544 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 13:08:20.707204 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 13:08:20.713697 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5675 13:08:20.716725 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5676 13:08:20.720357 Total UI for P1: 0, mck2ui 16
5677 13:08:20.723709 best dqsien dly found for B0: ( 1, 2, 28)
5678 13:08:20.726754 Total UI for P1: 0, mck2ui 16
5679 13:08:20.730208 best dqsien dly found for B1: ( 1, 2, 28)
5680 13:08:20.733861 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5681 13:08:20.736856 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5682 13:08:20.737376
5683 13:08:20.740050 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5684 13:08:20.743624 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5685 13:08:20.746857 [Gating] SW calibration Done
5686 13:08:20.747394 ==
5687 13:08:20.750491 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 13:08:20.757379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 13:08:20.757912 ==
5690 13:08:20.758367 RX Vref Scan: 0
5691 13:08:20.758667
5692 13:08:20.760365 RX Vref 0 -> 0, step: 1
5693 13:08:20.760761
5694 13:08:20.763695 RX Delay -80 -> 252, step: 8
5695 13:08:20.766621 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5696 13:08:20.770061 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5697 13:08:20.773219 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5698 13:08:20.776744 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5699 13:08:20.783378 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5700 13:08:20.786994 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5701 13:08:20.789865 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5702 13:08:20.793179 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5703 13:08:20.797068 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5704 13:08:20.800123 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5705 13:08:20.806950 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5706 13:08:20.810135 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5707 13:08:20.812908 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5708 13:08:20.816403 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5709 13:08:20.819581 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5710 13:08:20.826558 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5711 13:08:20.826942 ==
5712 13:08:20.829900 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 13:08:20.833103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 13:08:20.833490 ==
5715 13:08:20.833783 DQS Delay:
5716 13:08:20.836274 DQS0 = 0, DQS1 = 0
5717 13:08:20.836676 DQM Delay:
5718 13:08:20.839833 DQM0 = 95, DQM1 = 87
5719 13:08:20.840288 DQ Delay:
5720 13:08:20.842839 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5721 13:08:20.846336 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5722 13:08:20.849359 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5723 13:08:20.853081 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =91
5724 13:08:20.853573
5725 13:08:20.853944
5726 13:08:20.854360 ==
5727 13:08:20.856215 Dram Type= 6, Freq= 0, CH_1, rank 0
5728 13:08:20.859972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 13:08:20.860407 ==
5730 13:08:20.862917
5731 13:08:20.863454
5732 13:08:20.863945 TX Vref Scan disable
5733 13:08:20.866301 == TX Byte 0 ==
5734 13:08:20.869919 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5735 13:08:20.872924 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5736 13:08:20.875988 == TX Byte 1 ==
5737 13:08:20.879270 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5738 13:08:20.882822 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5739 13:08:20.883295 ==
5740 13:08:20.886002 Dram Type= 6, Freq= 0, CH_1, rank 0
5741 13:08:20.892957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 13:08:20.893483 ==
5743 13:08:20.893859
5744 13:08:20.894217
5745 13:08:20.894543 TX Vref Scan disable
5746 13:08:20.896777 == TX Byte 0 ==
5747 13:08:20.900582 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5748 13:08:20.906700 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5749 13:08:20.907111 == TX Byte 1 ==
5750 13:08:20.910205 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5751 13:08:20.916772 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5752 13:08:20.917188
5753 13:08:20.917486 [DATLAT]
5754 13:08:20.917947 Freq=933, CH1 RK0
5755 13:08:20.918393
5756 13:08:20.920345 DATLAT Default: 0xd
5757 13:08:20.920748 0, 0xFFFF, sum = 0
5758 13:08:20.923420 1, 0xFFFF, sum = 0
5759 13:08:20.923835 2, 0xFFFF, sum = 0
5760 13:08:20.926912 3, 0xFFFF, sum = 0
5761 13:08:20.930387 4, 0xFFFF, sum = 0
5762 13:08:20.930937 5, 0xFFFF, sum = 0
5763 13:08:20.933881 6, 0xFFFF, sum = 0
5764 13:08:20.934452 7, 0xFFFF, sum = 0
5765 13:08:20.936574 8, 0xFFFF, sum = 0
5766 13:08:20.936982 9, 0xFFFF, sum = 0
5767 13:08:20.940286 10, 0x0, sum = 1
5768 13:08:20.940690 11, 0x0, sum = 2
5769 13:08:20.943437 12, 0x0, sum = 3
5770 13:08:20.943865 13, 0x0, sum = 4
5771 13:08:20.944168 best_step = 11
5772 13:08:20.944454
5773 13:08:20.947331 ==
5774 13:08:20.950758 Dram Type= 6, Freq= 0, CH_1, rank 0
5775 13:08:20.953564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 13:08:20.954132 ==
5777 13:08:20.954542 RX Vref Scan: 1
5778 13:08:20.954882
5779 13:08:20.957141 RX Vref 0 -> 0, step: 1
5780 13:08:20.957546
5781 13:08:20.960102 RX Delay -61 -> 252, step: 4
5782 13:08:20.960613
5783 13:08:20.963342 Set Vref, RX VrefLevel [Byte0]: 53
5784 13:08:20.966667 [Byte1]: 48
5785 13:08:20.967071
5786 13:08:20.970511 Final RX Vref Byte 0 = 53 to rank0
5787 13:08:20.973623 Final RX Vref Byte 1 = 48 to rank0
5788 13:08:20.977096 Final RX Vref Byte 0 = 53 to rank1
5789 13:08:20.980260 Final RX Vref Byte 1 = 48 to rank1==
5790 13:08:20.983415 Dram Type= 6, Freq= 0, CH_1, rank 0
5791 13:08:20.986858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 13:08:20.987243 ==
5793 13:08:20.990063 DQS Delay:
5794 13:08:20.990497 DQS0 = 0, DQS1 = 0
5795 13:08:20.993088 DQM Delay:
5796 13:08:20.993471 DQM0 = 94, DQM1 = 87
5797 13:08:20.993767 DQ Delay:
5798 13:08:20.996497 DQ0 =100, DQ1 =88, DQ2 =82, DQ3 =90
5799 13:08:20.999908 DQ4 =90, DQ5 =104, DQ6 =108, DQ7 =92
5800 13:08:21.003258 DQ8 =78, DQ9 =78, DQ10 =88, DQ11 =82
5801 13:08:21.006417 DQ12 =98, DQ13 =94, DQ14 =92, DQ15 =92
5802 13:08:21.009937
5803 13:08:21.010511
5804 13:08:21.016763 [DQSOSCAuto] RK0, (LSB)MR18= 0x60e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 420 ps
5805 13:08:21.019786 CH1 RK0: MR19=505, MR18=60E
5806 13:08:21.026501 CH1_RK0: MR19=0x505, MR18=0x60E, DQSOSC=417, MR23=63, INC=62, DEC=41
5807 13:08:21.026889
5808 13:08:21.029958 ----->DramcWriteLeveling(PI) begin...
5809 13:08:21.030596 ==
5810 13:08:21.033104 Dram Type= 6, Freq= 0, CH_1, rank 1
5811 13:08:21.036318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5812 13:08:21.036747 ==
5813 13:08:21.039863 Write leveling (Byte 0): 26 => 26
5814 13:08:21.042976 Write leveling (Byte 1): 31 => 31
5815 13:08:21.046511 DramcWriteLeveling(PI) end<-----
5816 13:08:21.046892
5817 13:08:21.047183 ==
5818 13:08:21.049568 Dram Type= 6, Freq= 0, CH_1, rank 1
5819 13:08:21.053067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 13:08:21.053451 ==
5821 13:08:21.056627 [Gating] SW mode calibration
5822 13:08:21.062958 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5823 13:08:21.069538 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5824 13:08:21.072770 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 13:08:21.076031 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 13:08:21.082856 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 13:08:21.085995 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 13:08:21.089246 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 13:08:21.096082 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 13:08:21.099747 0 14 24 | B1->B0 | 3434 2e2e | 0 1 | (0 0) (1 0)
5831 13:08:21.102662 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5832 13:08:21.109151 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 13:08:21.112485 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 13:08:21.115456 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 13:08:21.122666 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 13:08:21.125555 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 13:08:21.129164 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 13:08:21.135743 0 15 24 | B1->B0 | 2e2e 3737 | 1 0 | (0 0) (1 1)
5839 13:08:21.139066 0 15 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5840 13:08:21.142406 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 13:08:21.148961 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 13:08:21.152427 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 13:08:21.155665 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 13:08:21.162688 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 13:08:21.165403 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 13:08:21.169079 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5847 13:08:21.175733 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5848 13:08:21.178810 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 13:08:21.182403 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 13:08:21.188924 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 13:08:21.192958 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 13:08:21.195978 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 13:08:21.199108 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 13:08:21.205626 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 13:08:21.208892 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 13:08:21.212366 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 13:08:21.218710 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 13:08:21.222217 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 13:08:21.225299 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 13:08:21.232020 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 13:08:21.235513 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 13:08:21.238897 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5863 13:08:21.245133 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5864 13:08:21.248685 Total UI for P1: 0, mck2ui 16
5865 13:08:21.252101 best dqsien dly found for B0: ( 1, 2, 24)
5866 13:08:21.254800 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5867 13:08:21.258298 Total UI for P1: 0, mck2ui 16
5868 13:08:21.261866 best dqsien dly found for B1: ( 1, 2, 28)
5869 13:08:21.265113 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5870 13:08:21.268304 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5871 13:08:21.268697
5872 13:08:21.271545 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5873 13:08:21.275373 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5874 13:08:21.278322 [Gating] SW calibration Done
5875 13:08:21.278913 ==
5876 13:08:21.281507 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 13:08:21.288346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 13:08:21.288731 ==
5879 13:08:21.289030 RX Vref Scan: 0
5880 13:08:21.289440
5881 13:08:21.291937 RX Vref 0 -> 0, step: 1
5882 13:08:21.292319
5883 13:08:21.295024 RX Delay -80 -> 252, step: 8
5884 13:08:21.297987 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5885 13:08:21.301509 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5886 13:08:21.305114 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5887 13:08:21.308094 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5888 13:08:21.314684 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5889 13:08:21.317947 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5890 13:08:21.321375 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5891 13:08:21.324911 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5892 13:08:21.328116 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5893 13:08:21.331059 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5894 13:08:21.337902 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5895 13:08:21.341278 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5896 13:08:21.344645 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5897 13:08:21.347728 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5898 13:08:21.351151 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5899 13:08:21.358071 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5900 13:08:21.358522 ==
5901 13:08:21.361389 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 13:08:21.364439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 13:08:21.364898 ==
5904 13:08:21.365226 DQS Delay:
5905 13:08:21.368209 DQS0 = 0, DQS1 = 0
5906 13:08:21.368617 DQM Delay:
5907 13:08:21.371151 DQM0 = 94, DQM1 = 87
5908 13:08:21.371584 DQ Delay:
5909 13:08:21.374984 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5910 13:08:21.377588 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5911 13:08:21.381136 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5912 13:08:21.384236 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5913 13:08:21.384653
5914 13:08:21.384965
5915 13:08:21.385241 ==
5916 13:08:21.388100 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 13:08:21.391364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 13:08:21.394392 ==
5919 13:08:21.394773
5920 13:08:21.395069
5921 13:08:21.395346 TX Vref Scan disable
5922 13:08:21.397894 == TX Byte 0 ==
5923 13:08:21.401154 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5924 13:08:21.404241 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5925 13:08:21.407634 == TX Byte 1 ==
5926 13:08:21.410926 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5927 13:08:21.414477 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5928 13:08:21.417875 ==
5929 13:08:21.418423 Dram Type= 6, Freq= 0, CH_1, rank 1
5930 13:08:21.424328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5931 13:08:21.424713 ==
5932 13:08:21.425013
5933 13:08:21.425283
5934 13:08:21.427582 TX Vref Scan disable
5935 13:08:21.427963 == TX Byte 0 ==
5936 13:08:21.434161 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5937 13:08:21.437548 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5938 13:08:21.437933 == TX Byte 1 ==
5939 13:08:21.444135 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5940 13:08:21.447507 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5941 13:08:21.447889
5942 13:08:21.448184 [DATLAT]
5943 13:08:21.450959 Freq=933, CH1 RK1
5944 13:08:21.451341
5945 13:08:21.451634 DATLAT Default: 0xb
5946 13:08:21.453839 0, 0xFFFF, sum = 0
5947 13:08:21.454270 1, 0xFFFF, sum = 0
5948 13:08:21.457178 2, 0xFFFF, sum = 0
5949 13:08:21.457566 3, 0xFFFF, sum = 0
5950 13:08:21.460458 4, 0xFFFF, sum = 0
5951 13:08:21.460853 5, 0xFFFF, sum = 0
5952 13:08:21.464239 6, 0xFFFF, sum = 0
5953 13:08:21.464627 7, 0xFFFF, sum = 0
5954 13:08:21.467251 8, 0xFFFF, sum = 0
5955 13:08:21.467641 9, 0xFFFF, sum = 0
5956 13:08:21.470598 10, 0x0, sum = 1
5957 13:08:21.470997 11, 0x0, sum = 2
5958 13:08:21.474069 12, 0x0, sum = 3
5959 13:08:21.474642 13, 0x0, sum = 4
5960 13:08:21.477273 best_step = 11
5961 13:08:21.477731
5962 13:08:21.478028 ==
5963 13:08:21.480484 Dram Type= 6, Freq= 0, CH_1, rank 1
5964 13:08:21.483993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5965 13:08:21.484383 ==
5966 13:08:21.487512 RX Vref Scan: 0
5967 13:08:21.487899
5968 13:08:21.488274 RX Vref 0 -> 0, step: 1
5969 13:08:21.488564
5970 13:08:21.490699 RX Delay -69 -> 252, step: 4
5971 13:08:21.497813 iDelay=203, Bit 0, Center 98 (3 ~ 194) 192
5972 13:08:21.500845 iDelay=203, Bit 1, Center 90 (-5 ~ 186) 192
5973 13:08:21.504399 iDelay=203, Bit 2, Center 84 (-9 ~ 178) 188
5974 13:08:21.507728 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5975 13:08:21.511231 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5976 13:08:21.514458 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5977 13:08:21.521601 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5978 13:08:21.524590 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5979 13:08:21.527781 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5980 13:08:21.530832 iDelay=203, Bit 9, Center 78 (-17 ~ 174) 192
5981 13:08:21.534532 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5982 13:08:21.541100 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5983 13:08:21.544123 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5984 13:08:21.547597 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5985 13:08:21.551209 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5986 13:08:21.554093 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5987 13:08:21.554514 ==
5988 13:08:21.557335 Dram Type= 6, Freq= 0, CH_1, rank 1
5989 13:08:21.564239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5990 13:08:21.564625 ==
5991 13:08:21.564924 DQS Delay:
5992 13:08:21.567288 DQS0 = 0, DQS1 = 0
5993 13:08:21.567672 DQM Delay:
5994 13:08:21.567973 DQM0 = 93, DQM1 = 89
5995 13:08:21.570805 DQ Delay:
5996 13:08:21.574334 DQ0 =98, DQ1 =90, DQ2 =84, DQ3 =88
5997 13:08:21.577289 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =90
5998 13:08:21.580481 DQ8 =76, DQ9 =78, DQ10 =92, DQ11 =84
5999 13:08:21.584176 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
6000 13:08:21.584559
6001 13:08:21.584853
6002 13:08:21.590355 [DQSOSCAuto] RK1, (LSB)MR18= 0x1327, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 415 ps
6003 13:08:21.593653 CH1 RK1: MR19=505, MR18=1327
6004 13:08:21.600983 CH1_RK1: MR19=0x505, MR18=0x1327, DQSOSC=409, MR23=63, INC=64, DEC=43
6005 13:08:21.603938 [RxdqsGatingPostProcess] freq 933
6006 13:08:21.607164 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6007 13:08:21.610912 best DQS0 dly(2T, 0.5T) = (0, 10)
6008 13:08:21.613549 best DQS1 dly(2T, 0.5T) = (0, 10)
6009 13:08:21.617133 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6010 13:08:21.620456 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6011 13:08:21.624093 best DQS0 dly(2T, 0.5T) = (0, 10)
6012 13:08:21.627500 best DQS1 dly(2T, 0.5T) = (0, 10)
6013 13:08:21.630403 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6014 13:08:21.634013 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6015 13:08:21.637157 Pre-setting of DQS Precalculation
6016 13:08:21.640727 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6017 13:08:21.650372 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6018 13:08:21.657270 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6019 13:08:21.657693
6020 13:08:21.658017
6021 13:08:21.660500 [Calibration Summary] 1866 Mbps
6022 13:08:21.660924 CH 0, Rank 0
6023 13:08:21.664067 SW Impedance : PASS
6024 13:08:21.664483 DUTY Scan : NO K
6025 13:08:21.667215 ZQ Calibration : PASS
6026 13:08:21.670404 Jitter Meter : NO K
6027 13:08:21.670785 CBT Training : PASS
6028 13:08:21.673873 Write leveling : PASS
6029 13:08:21.676638 RX DQS gating : PASS
6030 13:08:21.677020 RX DQ/DQS(RDDQC) : PASS
6031 13:08:21.680240 TX DQ/DQS : PASS
6032 13:08:21.683262 RX DATLAT : PASS
6033 13:08:21.683642 RX DQ/DQS(Engine): PASS
6034 13:08:21.686580 TX OE : NO K
6035 13:08:21.687012 All Pass.
6036 13:08:21.687311
6037 13:08:21.690189 CH 0, Rank 1
6038 13:08:21.690573 SW Impedance : PASS
6039 13:08:21.693351 DUTY Scan : NO K
6040 13:08:21.696901 ZQ Calibration : PASS
6041 13:08:21.697284 Jitter Meter : NO K
6042 13:08:21.699870 CBT Training : PASS
6043 13:08:21.703394 Write leveling : PASS
6044 13:08:21.703779 RX DQS gating : PASS
6045 13:08:21.706394 RX DQ/DQS(RDDQC) : PASS
6046 13:08:21.706776 TX DQ/DQS : PASS
6047 13:08:21.710336 RX DATLAT : PASS
6048 13:08:21.713149 RX DQ/DQS(Engine): PASS
6049 13:08:21.713532 TX OE : NO K
6050 13:08:21.716405 All Pass.
6051 13:08:21.716786
6052 13:08:21.717079 CH 1, Rank 0
6053 13:08:21.719559 SW Impedance : PASS
6054 13:08:21.720064 DUTY Scan : NO K
6055 13:08:21.723064 ZQ Calibration : PASS
6056 13:08:21.726295 Jitter Meter : NO K
6057 13:08:21.726681 CBT Training : PASS
6058 13:08:21.729870 Write leveling : PASS
6059 13:08:21.732880 RX DQS gating : PASS
6060 13:08:21.733263 RX DQ/DQS(RDDQC) : PASS
6061 13:08:21.736353 TX DQ/DQS : PASS
6062 13:08:21.740023 RX DATLAT : PASS
6063 13:08:21.740405 RX DQ/DQS(Engine): PASS
6064 13:08:21.743278 TX OE : NO K
6065 13:08:21.743666 All Pass.
6066 13:08:21.743961
6067 13:08:21.746197 CH 1, Rank 1
6068 13:08:21.746581 SW Impedance : PASS
6069 13:08:21.749314 DUTY Scan : NO K
6070 13:08:21.753067 ZQ Calibration : PASS
6071 13:08:21.753449 Jitter Meter : NO K
6072 13:08:21.756029 CBT Training : PASS
6073 13:08:21.759198 Write leveling : PASS
6074 13:08:21.759581 RX DQS gating : PASS
6075 13:08:21.762693 RX DQ/DQS(RDDQC) : PASS
6076 13:08:21.763077 TX DQ/DQS : PASS
6077 13:08:21.765860 RX DATLAT : PASS
6078 13:08:21.769876 RX DQ/DQS(Engine): PASS
6079 13:08:21.770304 TX OE : NO K
6080 13:08:21.772572 All Pass.
6081 13:08:21.773033
6082 13:08:21.773270 DramC Write-DBI off
6083 13:08:21.776028 PER_BANK_REFRESH: Hybrid Mode
6084 13:08:21.779387 TX_TRACKING: ON
6085 13:08:21.785494 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6086 13:08:21.788592 [FAST_K] Save calibration result to emmc
6087 13:08:21.795620 dramc_set_vcore_voltage set vcore to 650000
6088 13:08:21.795694 Read voltage for 400, 6
6089 13:08:21.795752 Vio18 = 0
6090 13:08:21.799150 Vcore = 650000
6091 13:08:21.799224 Vdram = 0
6092 13:08:21.799282 Vddq = 0
6093 13:08:21.801850 Vmddr = 0
6094 13:08:21.805198 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6095 13:08:21.811988 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6096 13:08:21.815693 MEM_TYPE=3, freq_sel=20
6097 13:08:21.815788 sv_algorithm_assistance_LP4_800
6098 13:08:21.821853 ============ PULL DRAM RESETB DOWN ============
6099 13:08:21.825345 ========== PULL DRAM RESETB DOWN end =========
6100 13:08:21.829063 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6101 13:08:21.832322 ===================================
6102 13:08:21.835401 LPDDR4 DRAM CONFIGURATION
6103 13:08:21.838295 ===================================
6104 13:08:21.841908 EX_ROW_EN[0] = 0x0
6105 13:08:21.842066 EX_ROW_EN[1] = 0x0
6106 13:08:21.845069 LP4Y_EN = 0x0
6107 13:08:21.845252 WORK_FSP = 0x0
6108 13:08:21.848466 WL = 0x2
6109 13:08:21.848647 RL = 0x2
6110 13:08:21.852023 BL = 0x2
6111 13:08:21.852242 RPST = 0x0
6112 13:08:21.855197 RD_PRE = 0x0
6113 13:08:21.855468 WR_PRE = 0x1
6114 13:08:21.858340 WR_PST = 0x0
6115 13:08:21.858612 DBI_WR = 0x0
6116 13:08:21.861863 DBI_RD = 0x0
6117 13:08:21.862242 OTF = 0x1
6118 13:08:21.865268 ===================================
6119 13:08:21.868788 ===================================
6120 13:08:21.872205 ANA top config
6121 13:08:21.875338 ===================================
6122 13:08:21.878371 DLL_ASYNC_EN = 0
6123 13:08:21.878753 ALL_SLAVE_EN = 1
6124 13:08:21.881599 NEW_RANK_MODE = 1
6125 13:08:21.885189 DLL_IDLE_MODE = 1
6126 13:08:21.888165 LP45_APHY_COMB_EN = 1
6127 13:08:21.891700 TX_ODT_DIS = 1
6128 13:08:21.892084 NEW_8X_MODE = 1
6129 13:08:21.894897 ===================================
6130 13:08:21.898422 ===================================
6131 13:08:21.901332 data_rate = 800
6132 13:08:21.904807 CKR = 1
6133 13:08:21.907962 DQ_P2S_RATIO = 4
6134 13:08:21.911290 ===================================
6135 13:08:21.914553 CA_P2S_RATIO = 4
6136 13:08:21.917880 DQ_CA_OPEN = 0
6137 13:08:21.918323 DQ_SEMI_OPEN = 1
6138 13:08:21.921183 CA_SEMI_OPEN = 1
6139 13:08:21.924854 CA_FULL_RATE = 0
6140 13:08:21.928073 DQ_CKDIV4_EN = 0
6141 13:08:21.931108 CA_CKDIV4_EN = 1
6142 13:08:21.934811 CA_PREDIV_EN = 0
6143 13:08:21.935194 PH8_DLY = 0
6144 13:08:21.937988 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6145 13:08:21.941302 DQ_AAMCK_DIV = 0
6146 13:08:21.944481 CA_AAMCK_DIV = 0
6147 13:08:21.947967 CA_ADMCK_DIV = 4
6148 13:08:21.951677 DQ_TRACK_CA_EN = 0
6149 13:08:21.952077 CA_PICK = 800
6150 13:08:21.954549 CA_MCKIO = 400
6151 13:08:21.957758 MCKIO_SEMI = 400
6152 13:08:21.961402 PLL_FREQ = 3016
6153 13:08:21.964334 DQ_UI_PI_RATIO = 32
6154 13:08:21.967846 CA_UI_PI_RATIO = 32
6155 13:08:21.971277 ===================================
6156 13:08:21.974530 ===================================
6157 13:08:21.977930 memory_type:LPDDR4
6158 13:08:21.978343 GP_NUM : 10
6159 13:08:21.980888 SRAM_EN : 1
6160 13:08:21.981265 MD32_EN : 0
6161 13:08:21.984391 ===================================
6162 13:08:21.987420 [ANA_INIT] >>>>>>>>>>>>>>
6163 13:08:21.991089 <<<<<< [CONFIGURE PHASE]: ANA_TX
6164 13:08:21.994631 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6165 13:08:21.997596 ===================================
6166 13:08:22.001183 data_rate = 800,PCW = 0X7400
6167 13:08:22.004592 ===================================
6168 13:08:22.007372 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6169 13:08:22.010891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6170 13:08:22.024368 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6171 13:08:22.027495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6172 13:08:22.030737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6173 13:08:22.034215 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6174 13:08:22.037732 [ANA_INIT] flow start
6175 13:08:22.040851 [ANA_INIT] PLL >>>>>>>>
6176 13:08:22.041237 [ANA_INIT] PLL <<<<<<<<
6177 13:08:22.043881 [ANA_INIT] MIDPI >>>>>>>>
6178 13:08:22.047617 [ANA_INIT] MIDPI <<<<<<<<
6179 13:08:22.048002 [ANA_INIT] DLL >>>>>>>>
6180 13:08:22.051187 [ANA_INIT] flow end
6181 13:08:22.054058 ============ LP4 DIFF to SE enter ============
6182 13:08:22.061071 ============ LP4 DIFF to SE exit ============
6183 13:08:22.061453 [ANA_INIT] <<<<<<<<<<<<<
6184 13:08:22.064155 [Flow] Enable top DCM control >>>>>
6185 13:08:22.067336 [Flow] Enable top DCM control <<<<<
6186 13:08:22.070938 Enable DLL master slave shuffle
6187 13:08:22.077484 ==============================================================
6188 13:08:22.077876 Gating Mode config
6189 13:08:22.083899 ==============================================================
6190 13:08:22.087532 Config description:
6191 13:08:22.094196 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6192 13:08:22.100908 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6193 13:08:22.107487 SELPH_MODE 0: By rank 1: By Phase
6194 13:08:22.114141 ==============================================================
6195 13:08:22.114528 GAT_TRACK_EN = 0
6196 13:08:22.117213 RX_GATING_MODE = 2
6197 13:08:22.120341 RX_GATING_TRACK_MODE = 2
6198 13:08:22.123703 SELPH_MODE = 1
6199 13:08:22.126984 PICG_EARLY_EN = 1
6200 13:08:22.130132 VALID_LAT_VALUE = 1
6201 13:08:22.136765 ==============================================================
6202 13:08:22.140516 Enter into Gating configuration >>>>
6203 13:08:22.143656 Exit from Gating configuration <<<<
6204 13:08:22.147174 Enter into DVFS_PRE_config >>>>>
6205 13:08:22.157125 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6206 13:08:22.160359 Exit from DVFS_PRE_config <<<<<
6207 13:08:22.163756 Enter into PICG configuration >>>>
6208 13:08:22.166706 Exit from PICG configuration <<<<
6209 13:08:22.170236 [RX_INPUT] configuration >>>>>
6210 13:08:22.170619 [RX_INPUT] configuration <<<<<
6211 13:08:22.176894 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6212 13:08:22.183685 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6213 13:08:22.190194 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6214 13:08:22.193328 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6215 13:08:22.200122 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6216 13:08:22.206701 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6217 13:08:22.210272 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6218 13:08:22.213743 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6219 13:08:22.220434 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6220 13:08:22.223447 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6221 13:08:22.227071 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6222 13:08:22.233192 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6223 13:08:22.236769 ===================================
6224 13:08:22.237195 LPDDR4 DRAM CONFIGURATION
6225 13:08:22.239896 ===================================
6226 13:08:22.243336 EX_ROW_EN[0] = 0x0
6227 13:08:22.246850 EX_ROW_EN[1] = 0x0
6228 13:08:22.247268 LP4Y_EN = 0x0
6229 13:08:22.250027 WORK_FSP = 0x0
6230 13:08:22.250478 WL = 0x2
6231 13:08:22.253371 RL = 0x2
6232 13:08:22.253795 BL = 0x2
6233 13:08:22.256961 RPST = 0x0
6234 13:08:22.257383 RD_PRE = 0x0
6235 13:08:22.259808 WR_PRE = 0x1
6236 13:08:22.260232 WR_PST = 0x0
6237 13:08:22.263369 DBI_WR = 0x0
6238 13:08:22.263793 DBI_RD = 0x0
6239 13:08:22.266720 OTF = 0x1
6240 13:08:22.269984 ===================================
6241 13:08:22.273128 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6242 13:08:22.276976 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6243 13:08:22.283504 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6244 13:08:22.283890 ===================================
6245 13:08:22.286668 LPDDR4 DRAM CONFIGURATION
6246 13:08:22.289909 ===================================
6247 13:08:22.293506 EX_ROW_EN[0] = 0x10
6248 13:08:22.294003 EX_ROW_EN[1] = 0x0
6249 13:08:22.296447 LP4Y_EN = 0x0
6250 13:08:22.296829 WORK_FSP = 0x0
6251 13:08:22.299818 WL = 0x2
6252 13:08:22.300203 RL = 0x2
6253 13:08:22.303018 BL = 0x2
6254 13:08:22.306187 RPST = 0x0
6255 13:08:22.306571 RD_PRE = 0x0
6256 13:08:22.309936 WR_PRE = 0x1
6257 13:08:22.310348 WR_PST = 0x0
6258 13:08:22.313153 DBI_WR = 0x0
6259 13:08:22.313533 DBI_RD = 0x0
6260 13:08:22.316614 OTF = 0x1
6261 13:08:22.319597 ===================================
6262 13:08:22.322683 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6263 13:08:22.328194 nWR fixed to 30
6264 13:08:22.331925 [ModeRegInit_LP4] CH0 RK0
6265 13:08:22.332307 [ModeRegInit_LP4] CH0 RK1
6266 13:08:22.334839 [ModeRegInit_LP4] CH1 RK0
6267 13:08:22.338488 [ModeRegInit_LP4] CH1 RK1
6268 13:08:22.338871 match AC timing 19
6269 13:08:22.344755 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6270 13:08:22.348473 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6271 13:08:22.351620 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6272 13:08:22.358189 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6273 13:08:22.361869 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6274 13:08:22.362282 ==
6275 13:08:22.365034 Dram Type= 6, Freq= 0, CH_0, rank 0
6276 13:08:22.367932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6277 13:08:22.368319 ==
6278 13:08:22.374666 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6279 13:08:22.381663 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6280 13:08:22.384910 [CA 0] Center 36 (8~64) winsize 57
6281 13:08:22.388472 [CA 1] Center 36 (8~64) winsize 57
6282 13:08:22.392076 [CA 2] Center 36 (8~64) winsize 57
6283 13:08:22.392501 [CA 3] Center 36 (8~64) winsize 57
6284 13:08:22.395515 [CA 4] Center 36 (8~64) winsize 57
6285 13:08:22.398379 [CA 5] Center 36 (8~64) winsize 57
6286 13:08:22.398887
6287 13:08:22.404701 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6288 13:08:22.405128
6289 13:08:22.407958 [CATrainingPosCal] consider 1 rank data
6290 13:08:22.411397 u2DelayCellTimex100 = 270/100 ps
6291 13:08:22.415126 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 13:08:22.418555 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 13:08:22.421307 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 13:08:22.424596 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 13:08:22.428104 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 13:08:22.431724 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 13:08:22.432144
6298 13:08:22.434790 CA PerBit enable=1, Macro0, CA PI delay=36
6299 13:08:22.435244
6300 13:08:22.438521 [CBTSetCACLKResult] CA Dly = 36
6301 13:08:22.441524 CS Dly: 1 (0~32)
6302 13:08:22.441949 ==
6303 13:08:22.444622 Dram Type= 6, Freq= 0, CH_0, rank 1
6304 13:08:22.448015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 13:08:22.448441 ==
6306 13:08:22.454856 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6307 13:08:22.458585 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6308 13:08:22.461326 [CA 0] Center 36 (8~64) winsize 57
6309 13:08:22.464602 [CA 1] Center 36 (8~64) winsize 57
6310 13:08:22.468338 [CA 2] Center 36 (8~64) winsize 57
6311 13:08:22.471293 [CA 3] Center 36 (8~64) winsize 57
6312 13:08:22.475222 [CA 4] Center 36 (8~64) winsize 57
6313 13:08:22.478003 [CA 5] Center 36 (8~64) winsize 57
6314 13:08:22.478429
6315 13:08:22.481512 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6316 13:08:22.481893
6317 13:08:22.484970 [CATrainingPosCal] consider 2 rank data
6318 13:08:22.488316 u2DelayCellTimex100 = 270/100 ps
6319 13:08:22.491431 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 13:08:22.494593 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 13:08:22.497738 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 13:08:22.504880 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 13:08:22.507633 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 13:08:22.511437 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 13:08:22.511821
6326 13:08:22.514841 CA PerBit enable=1, Macro0, CA PI delay=36
6327 13:08:22.515301
6328 13:08:22.517894 [CBTSetCACLKResult] CA Dly = 36
6329 13:08:22.518421 CS Dly: 1 (0~32)
6330 13:08:22.518729
6331 13:08:22.521026 ----->DramcWriteLeveling(PI) begin...
6332 13:08:22.521432 ==
6333 13:08:22.524525 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 13:08:22.530805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 13:08:22.531192 ==
6336 13:08:22.534318 Write leveling (Byte 0): 40 => 8
6337 13:08:22.538154 Write leveling (Byte 1): 40 => 8
6338 13:08:22.538543 DramcWriteLeveling(PI) end<-----
6339 13:08:22.540942
6340 13:08:22.541320 ==
6341 13:08:22.544690 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 13:08:22.547792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 13:08:22.548179 ==
6344 13:08:22.550681 [Gating] SW mode calibration
6345 13:08:22.557535 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6346 13:08:22.560954 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6347 13:08:22.567752 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6348 13:08:22.570564 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6349 13:08:22.574396 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6350 13:08:22.580518 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6351 13:08:22.584138 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6352 13:08:22.587242 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6353 13:08:22.594358 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6354 13:08:22.597317 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6355 13:08:22.600889 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6356 13:08:22.604194 Total UI for P1: 0, mck2ui 16
6357 13:08:22.607439 best dqsien dly found for B0: ( 0, 14, 24)
6358 13:08:22.610293 Total UI for P1: 0, mck2ui 16
6359 13:08:22.613955 best dqsien dly found for B1: ( 0, 14, 24)
6360 13:08:22.617151 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6361 13:08:22.620782 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6362 13:08:22.623974
6363 13:08:22.626942 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6364 13:08:22.630184 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6365 13:08:22.633702 [Gating] SW calibration Done
6366 13:08:22.634173 ==
6367 13:08:22.637248 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 13:08:22.640340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 13:08:22.640797 ==
6370 13:08:22.641133 RX Vref Scan: 0
6371 13:08:22.643547
6372 13:08:22.644023 RX Vref 0 -> 0, step: 1
6373 13:08:22.644412
6374 13:08:22.647006 RX Delay -410 -> 252, step: 16
6375 13:08:22.650442 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6376 13:08:22.657007 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6377 13:08:22.660287 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6378 13:08:22.663408 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6379 13:08:22.666826 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6380 13:08:22.673447 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6381 13:08:22.676725 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6382 13:08:22.679797 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6383 13:08:22.683009 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6384 13:08:22.689805 iDelay=230, Bit 9, Center -67 (-330 ~ 197) 528
6385 13:08:22.693533 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6386 13:08:22.696370 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6387 13:08:22.700044 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6388 13:08:22.706629 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6389 13:08:22.709716 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6390 13:08:22.713071 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6391 13:08:22.713492 ==
6392 13:08:22.716796 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 13:08:22.723418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 13:08:22.723893 ==
6395 13:08:22.724221 DQS Delay:
6396 13:08:22.726168 DQS0 = 59, DQS1 = 67
6397 13:08:22.726587 DQM Delay:
6398 13:08:22.726911 DQM0 = 18, DQM1 = 17
6399 13:08:22.729984 DQ Delay:
6400 13:08:22.732762 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6401 13:08:22.736206 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6402 13:08:22.739825 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6403 13:08:22.742839 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6404 13:08:22.743247
6405 13:08:22.743567
6406 13:08:22.743865 ==
6407 13:08:22.746552 Dram Type= 6, Freq= 0, CH_0, rank 0
6408 13:08:22.749348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 13:08:22.749729 ==
6410 13:08:22.750021
6411 13:08:22.750332
6412 13:08:22.752939 TX Vref Scan disable
6413 13:08:22.753317 == TX Byte 0 ==
6414 13:08:22.759118 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6415 13:08:22.762708 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6416 13:08:22.763090 == TX Byte 1 ==
6417 13:08:22.769381 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6418 13:08:22.772822 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6419 13:08:22.773246 ==
6420 13:08:22.776281 Dram Type= 6, Freq= 0, CH_0, rank 0
6421 13:08:22.779395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 13:08:22.779818 ==
6423 13:08:22.780139
6424 13:08:22.780433
6425 13:08:22.782898 TX Vref Scan disable
6426 13:08:22.783320 == TX Byte 0 ==
6427 13:08:22.789398 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6428 13:08:22.792588 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6429 13:08:22.793114 == TX Byte 1 ==
6430 13:08:22.799011 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6431 13:08:22.802662 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6432 13:08:22.803054
6433 13:08:22.803345 [DATLAT]
6434 13:08:22.805622 Freq=400, CH0 RK0
6435 13:08:22.806000
6436 13:08:22.806325 DATLAT Default: 0xf
6437 13:08:22.809283 0, 0xFFFF, sum = 0
6438 13:08:22.809672 1, 0xFFFF, sum = 0
6439 13:08:22.812812 2, 0xFFFF, sum = 0
6440 13:08:22.813199 3, 0xFFFF, sum = 0
6441 13:08:22.815749 4, 0xFFFF, sum = 0
6442 13:08:22.816139 5, 0xFFFF, sum = 0
6443 13:08:22.819627 6, 0xFFFF, sum = 0
6444 13:08:22.820101 7, 0xFFFF, sum = 0
6445 13:08:22.822295 8, 0xFFFF, sum = 0
6446 13:08:22.822683 9, 0xFFFF, sum = 0
6447 13:08:22.825854 10, 0xFFFF, sum = 0
6448 13:08:22.829027 11, 0xFFFF, sum = 0
6449 13:08:22.829415 12, 0xFFFF, sum = 0
6450 13:08:22.832534 13, 0x0, sum = 1
6451 13:08:22.832922 14, 0x0, sum = 2
6452 13:08:22.833223 15, 0x0, sum = 3
6453 13:08:22.835802 16, 0x0, sum = 4
6454 13:08:22.836191 best_step = 14
6455 13:08:22.836486
6456 13:08:22.836756 ==
6457 13:08:22.839207 Dram Type= 6, Freq= 0, CH_0, rank 0
6458 13:08:22.845629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6459 13:08:22.846018 ==
6460 13:08:22.846437 RX Vref Scan: 1
6461 13:08:22.846729
6462 13:08:22.849265 RX Vref 0 -> 0, step: 1
6463 13:08:22.849692
6464 13:08:22.852305 RX Delay -375 -> 252, step: 8
6465 13:08:22.852686
6466 13:08:22.856005 Set Vref, RX VrefLevel [Byte0]: 61
6467 13:08:22.859018 [Byte1]: 51
6468 13:08:22.862606
6469 13:08:22.862987 Final RX Vref Byte 0 = 61 to rank0
6470 13:08:22.866132 Final RX Vref Byte 1 = 51 to rank0
6471 13:08:22.868890 Final RX Vref Byte 0 = 61 to rank1
6472 13:08:22.872692 Final RX Vref Byte 1 = 51 to rank1==
6473 13:08:22.876378 Dram Type= 6, Freq= 0, CH_0, rank 0
6474 13:08:22.882458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 13:08:22.882848 ==
6476 13:08:22.883146 DQS Delay:
6477 13:08:22.883419 DQS0 = 60, DQS1 = 68
6478 13:08:22.885781 DQM Delay:
6479 13:08:22.886202 DQM0 = 13, DQM1 = 13
6480 13:08:22.889180 DQ Delay:
6481 13:08:22.892687 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6482 13:08:22.893137 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6483 13:08:22.895762 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6484 13:08:22.899403 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6485 13:08:22.899789
6486 13:08:22.902390
6487 13:08:22.909124 [DQSOSCAuto] RK0, (LSB)MR18= 0x9491, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
6488 13:08:22.912149 CH0 RK0: MR19=C0C, MR18=9491
6489 13:08:22.919187 CH0_RK0: MR19=0xC0C, MR18=0x9491, DQSOSC=391, MR23=63, INC=386, DEC=257
6490 13:08:22.919614 ==
6491 13:08:22.922680 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 13:08:22.925699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 13:08:22.926147 ==
6494 13:08:22.929115 [Gating] SW mode calibration
6495 13:08:22.935785 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6496 13:08:22.942221 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6497 13:08:22.945516 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6498 13:08:22.948538 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6499 13:08:22.955655 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6500 13:08:22.958623 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6501 13:08:22.962202 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6502 13:08:22.968804 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 13:08:22.972082 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 13:08:22.975320 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 13:08:22.981948 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6506 13:08:22.982459 Total UI for P1: 0, mck2ui 16
6507 13:08:22.985274 best dqsien dly found for B0: ( 0, 14, 24)
6508 13:08:22.988387 Total UI for P1: 0, mck2ui 16
6509 13:08:22.992055 best dqsien dly found for B1: ( 0, 14, 24)
6510 13:08:22.994922 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6511 13:08:23.001578 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6512 13:08:23.002069
6513 13:08:23.004704 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6514 13:08:23.007993 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6515 13:08:23.011587 [Gating] SW calibration Done
6516 13:08:23.012012 ==
6517 13:08:23.015008 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 13:08:23.018146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 13:08:23.018573 ==
6520 13:08:23.021409 RX Vref Scan: 0
6521 13:08:23.021838
6522 13:08:23.022430 RX Vref 0 -> 0, step: 1
6523 13:08:23.022771
6524 13:08:23.024325 RX Delay -410 -> 252, step: 16
6525 13:08:23.031334 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6526 13:08:23.034781 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6527 13:08:23.038144 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6528 13:08:23.041341 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6529 13:08:23.048017 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6530 13:08:23.051577 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6531 13:08:23.054450 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6532 13:08:23.058180 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6533 13:08:23.064780 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6534 13:08:23.068237 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6535 13:08:23.070998 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6536 13:08:23.074190 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6537 13:08:23.081204 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6538 13:08:23.084255 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6539 13:08:23.087726 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6540 13:08:23.091116 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6541 13:08:23.093920 ==
6542 13:08:23.097316 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 13:08:23.100752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 13:08:23.101264 ==
6545 13:08:23.101594 DQS Delay:
6546 13:08:23.104007 DQS0 = 59, DQS1 = 59
6547 13:08:23.104429 DQM Delay:
6548 13:08:23.107463 DQM0 = 17, DQM1 = 10
6549 13:08:23.107880 DQ Delay:
6550 13:08:23.111245 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6551 13:08:23.114087 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6552 13:08:23.117185 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6553 13:08:23.120649 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6554 13:08:23.121071
6555 13:08:23.121392
6556 13:08:23.121688 ==
6557 13:08:23.124418 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 13:08:23.127414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 13:08:23.127850 ==
6560 13:08:23.128280
6561 13:08:23.128642
6562 13:08:23.131121 TX Vref Scan disable
6563 13:08:23.131518 == TX Byte 0 ==
6564 13:08:23.137143 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6565 13:08:23.140181 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6566 13:08:23.140568 == TX Byte 1 ==
6567 13:08:23.147212 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6568 13:08:23.150209 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6569 13:08:23.150714 ==
6570 13:08:23.154014 Dram Type= 6, Freq= 0, CH_0, rank 1
6571 13:08:23.157127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6572 13:08:23.157652 ==
6573 13:08:23.157999
6574 13:08:23.158489
6575 13:08:23.160215 TX Vref Scan disable
6576 13:08:23.163316 == TX Byte 0 ==
6577 13:08:23.167166 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6578 13:08:23.170407 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6579 13:08:23.173087 == TX Byte 1 ==
6580 13:08:23.176505 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6581 13:08:23.179734 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6582 13:08:23.180120
6583 13:08:23.180415 [DATLAT]
6584 13:08:23.183409 Freq=400, CH0 RK1
6585 13:08:23.183843
6586 13:08:23.184144 DATLAT Default: 0xe
6587 13:08:23.186361 0, 0xFFFF, sum = 0
6588 13:08:23.186772 1, 0xFFFF, sum = 0
6589 13:08:23.190214 2, 0xFFFF, sum = 0
6590 13:08:23.193579 3, 0xFFFF, sum = 0
6591 13:08:23.193967 4, 0xFFFF, sum = 0
6592 13:08:23.196506 5, 0xFFFF, sum = 0
6593 13:08:23.196896 6, 0xFFFF, sum = 0
6594 13:08:23.199674 7, 0xFFFF, sum = 0
6595 13:08:23.200067 8, 0xFFFF, sum = 0
6596 13:08:23.203319 9, 0xFFFF, sum = 0
6597 13:08:23.203727 10, 0xFFFF, sum = 0
6598 13:08:23.206506 11, 0xFFFF, sum = 0
6599 13:08:23.207125 12, 0xFFFF, sum = 0
6600 13:08:23.209714 13, 0x0, sum = 1
6601 13:08:23.210325 14, 0x0, sum = 2
6602 13:08:23.212545 15, 0x0, sum = 3
6603 13:08:23.212622 16, 0x0, sum = 4
6604 13:08:23.216246 best_step = 14
6605 13:08:23.216340
6606 13:08:23.216400 ==
6607 13:08:23.219238 Dram Type= 6, Freq= 0, CH_0, rank 1
6608 13:08:23.222721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6609 13:08:23.222792 ==
6610 13:08:23.222850 RX Vref Scan: 0
6611 13:08:23.225723
6612 13:08:23.225798 RX Vref 0 -> 0, step: 1
6613 13:08:23.225856
6614 13:08:23.229641 RX Delay -359 -> 252, step: 8
6615 13:08:23.236954 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6616 13:08:23.240093 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6617 13:08:23.243446 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6618 13:08:23.246691 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6619 13:08:23.253220 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6620 13:08:23.256911 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6621 13:08:23.260597 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6622 13:08:23.264451 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6623 13:08:23.270396 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6624 13:08:23.273371 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6625 13:08:23.276604 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6626 13:08:23.283369 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6627 13:08:23.287431 iDelay=217, Bit 12, Center -44 (-295 ~ 208) 504
6628 13:08:23.290309 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6629 13:08:23.293461 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6630 13:08:23.299702 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6631 13:08:23.299779 ==
6632 13:08:23.303427 Dram Type= 6, Freq= 0, CH_0, rank 1
6633 13:08:23.306613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6634 13:08:23.306689 ==
6635 13:08:23.306747 DQS Delay:
6636 13:08:23.309722 DQS0 = 60, DQS1 = 72
6637 13:08:23.309797 DQM Delay:
6638 13:08:23.313458 DQM0 = 11, DQM1 = 17
6639 13:08:23.313550 DQ Delay:
6640 13:08:23.316308 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6641 13:08:23.319716 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6642 13:08:23.322932 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6643 13:08:23.326585 DQ12 =28, DQ13 =24, DQ14 =28, DQ15 =24
6644 13:08:23.326661
6645 13:08:23.326719
6646 13:08:23.333101 [DQSOSCAuto] RK1, (LSB)MR18= 0xce85, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6647 13:08:23.336120 CH0 RK1: MR19=C0C, MR18=CE85
6648 13:08:23.343205 CH0_RK1: MR19=0xC0C, MR18=0xCE85, DQSOSC=384, MR23=63, INC=400, DEC=267
6649 13:08:23.346588 [RxdqsGatingPostProcess] freq 400
6650 13:08:23.353198 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6651 13:08:23.353312 best DQS0 dly(2T, 0.5T) = (0, 10)
6652 13:08:23.356305 best DQS1 dly(2T, 0.5T) = (0, 10)
6653 13:08:23.359568 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6654 13:08:23.363150 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6655 13:08:23.366134 best DQS0 dly(2T, 0.5T) = (0, 10)
6656 13:08:23.369520 best DQS1 dly(2T, 0.5T) = (0, 10)
6657 13:08:23.373155 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6658 13:08:23.376223 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6659 13:08:23.379454 Pre-setting of DQS Precalculation
6660 13:08:23.386292 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6661 13:08:23.386512 ==
6662 13:08:23.389596 Dram Type= 6, Freq= 0, CH_1, rank 0
6663 13:08:23.392896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6664 13:08:23.393118 ==
6665 13:08:23.399396 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6666 13:08:23.402850 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6667 13:08:23.405949 [CA 0] Center 36 (8~64) winsize 57
6668 13:08:23.409732 [CA 1] Center 36 (8~64) winsize 57
6669 13:08:23.412849 [CA 2] Center 36 (8~64) winsize 57
6670 13:08:23.415975 [CA 3] Center 36 (8~64) winsize 57
6671 13:08:23.419592 [CA 4] Center 36 (8~64) winsize 57
6672 13:08:23.422699 [CA 5] Center 36 (8~64) winsize 57
6673 13:08:23.422918
6674 13:08:23.425962 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6675 13:08:23.426197
6676 13:08:23.429677 [CATrainingPosCal] consider 1 rank data
6677 13:08:23.432908 u2DelayCellTimex100 = 270/100 ps
6678 13:08:23.436257 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 13:08:23.439312 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 13:08:23.442335 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 13:08:23.449109 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 13:08:23.452641 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 13:08:23.456043 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 13:08:23.456395
6685 13:08:23.459782 CA PerBit enable=1, Macro0, CA PI delay=36
6686 13:08:23.460137
6687 13:08:23.462876 [CBTSetCACLKResult] CA Dly = 36
6688 13:08:23.463245 CS Dly: 1 (0~32)
6689 13:08:23.463519 ==
6690 13:08:23.466081 Dram Type= 6, Freq= 0, CH_1, rank 1
6691 13:08:23.472958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 13:08:23.473386 ==
6693 13:08:23.475818 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6694 13:08:23.482645 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6695 13:08:23.486081 [CA 0] Center 36 (8~64) winsize 57
6696 13:08:23.489057 [CA 1] Center 36 (8~64) winsize 57
6697 13:08:23.492465 [CA 2] Center 36 (8~64) winsize 57
6698 13:08:23.496181 [CA 3] Center 36 (8~64) winsize 57
6699 13:08:23.499168 [CA 4] Center 36 (8~64) winsize 57
6700 13:08:23.502727 [CA 5] Center 36 (8~64) winsize 57
6701 13:08:23.503110
6702 13:08:23.505920 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6703 13:08:23.506357
6704 13:08:23.509343 [CATrainingPosCal] consider 2 rank data
6705 13:08:23.512441 u2DelayCellTimex100 = 270/100 ps
6706 13:08:23.515871 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 13:08:23.519316 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 13:08:23.522609 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 13:08:23.525619 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 13:08:23.528737 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 13:08:23.532279 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 13:08:23.535299
6713 13:08:23.538834 CA PerBit enable=1, Macro0, CA PI delay=36
6714 13:08:23.539089
6715 13:08:23.542354 [CBTSetCACLKResult] CA Dly = 36
6716 13:08:23.542597 CS Dly: 1 (0~32)
6717 13:08:23.542791
6718 13:08:23.545646 ----->DramcWriteLeveling(PI) begin...
6719 13:08:23.545857 ==
6720 13:08:23.548594 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 13:08:23.552076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 13:08:23.552358 ==
6723 13:08:23.555382 Write leveling (Byte 0): 40 => 8
6724 13:08:23.558925 Write leveling (Byte 1): 40 => 8
6725 13:08:23.562412 DramcWriteLeveling(PI) end<-----
6726 13:08:23.562642
6727 13:08:23.562802 ==
6728 13:08:23.565526 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 13:08:23.568941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 13:08:23.572477 ==
6731 13:08:23.572684 [Gating] SW mode calibration
6732 13:08:23.581965 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6733 13:08:23.585181 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6734 13:08:23.588866 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6735 13:08:23.595303 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6736 13:08:23.598793 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6737 13:08:23.601906 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6738 13:08:23.608367 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6739 13:08:23.612126 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6740 13:08:23.615123 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6741 13:08:23.621756 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6742 13:08:23.625326 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6743 13:08:23.628883 Total UI for P1: 0, mck2ui 16
6744 13:08:23.631908 best dqsien dly found for B0: ( 0, 14, 24)
6745 13:08:23.635019 Total UI for P1: 0, mck2ui 16
6746 13:08:23.638712 best dqsien dly found for B1: ( 0, 14, 24)
6747 13:08:23.641764 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6748 13:08:23.644952 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6749 13:08:23.645230
6750 13:08:23.648646 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6751 13:08:23.651670 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6752 13:08:23.655287 [Gating] SW calibration Done
6753 13:08:23.655493 ==
6754 13:08:23.658681 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 13:08:23.665130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 13:08:23.665405 ==
6757 13:08:23.665643 RX Vref Scan: 0
6758 13:08:23.665813
6759 13:08:23.668385 RX Vref 0 -> 0, step: 1
6760 13:08:23.668659
6761 13:08:23.671624 RX Delay -410 -> 252, step: 16
6762 13:08:23.675200 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6763 13:08:23.678393 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6764 13:08:23.681975 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6765 13:08:23.688429 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6766 13:08:23.692159 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6767 13:08:23.695064 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6768 13:08:23.698557 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6769 13:08:23.704739 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6770 13:08:23.708507 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6771 13:08:23.711592 iDelay=230, Bit 9, Center -67 (-330 ~ 197) 528
6772 13:08:23.714711 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6773 13:08:23.721461 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6774 13:08:23.724596 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6775 13:08:23.728050 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6776 13:08:23.734991 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6777 13:08:23.738030 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6778 13:08:23.738446 ==
6779 13:08:23.741506 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 13:08:23.744421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 13:08:23.744805 ==
6782 13:08:23.748015 DQS Delay:
6783 13:08:23.748397 DQS0 = 51, DQS1 = 67
6784 13:08:23.748690 DQM Delay:
6785 13:08:23.751039 DQM0 = 12, DQM1 = 18
6786 13:08:23.751421 DQ Delay:
6787 13:08:23.754539 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6788 13:08:23.758150 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6789 13:08:23.761054 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6790 13:08:23.764592 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6791 13:08:23.764974
6792 13:08:23.765267
6793 13:08:23.765533 ==
6794 13:08:23.767846 Dram Type= 6, Freq= 0, CH_1, rank 0
6795 13:08:23.771456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 13:08:23.774881 ==
6797 13:08:23.775288
6798 13:08:23.775736
6799 13:08:23.776165 TX Vref Scan disable
6800 13:08:23.778153 == TX Byte 0 ==
6801 13:08:23.781177 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6802 13:08:23.784180 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6803 13:08:23.787843 == TX Byte 1 ==
6804 13:08:23.791265 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6805 13:08:23.794187 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6806 13:08:23.794722 ==
6807 13:08:23.797922 Dram Type= 6, Freq= 0, CH_1, rank 0
6808 13:08:23.804210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 13:08:23.804780 ==
6810 13:08:23.805259
6811 13:08:23.805869
6812 13:08:23.806427 TX Vref Scan disable
6813 13:08:23.807337 == TX Byte 0 ==
6814 13:08:23.811136 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6815 13:08:23.814166 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6816 13:08:23.817405 == TX Byte 1 ==
6817 13:08:23.820632 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6818 13:08:23.823782 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6819 13:08:23.824207
6820 13:08:23.827527 [DATLAT]
6821 13:08:23.827967 Freq=400, CH1 RK0
6822 13:08:23.828274
6823 13:08:23.830597 DATLAT Default: 0xf
6824 13:08:23.831072 0, 0xFFFF, sum = 0
6825 13:08:23.834129 1, 0xFFFF, sum = 0
6826 13:08:23.834531 2, 0xFFFF, sum = 0
6827 13:08:23.836891 3, 0xFFFF, sum = 0
6828 13:08:23.837407 4, 0xFFFF, sum = 0
6829 13:08:23.840528 5, 0xFFFF, sum = 0
6830 13:08:23.840921 6, 0xFFFF, sum = 0
6831 13:08:23.844033 7, 0xFFFF, sum = 0
6832 13:08:23.844373 8, 0xFFFF, sum = 0
6833 13:08:23.847095 9, 0xFFFF, sum = 0
6834 13:08:23.847374 10, 0xFFFF, sum = 0
6835 13:08:23.850677 11, 0xFFFF, sum = 0
6836 13:08:23.853377 12, 0xFFFF, sum = 0
6837 13:08:23.853661 13, 0x0, sum = 1
6838 13:08:23.856982 14, 0x0, sum = 2
6839 13:08:23.857151 15, 0x0, sum = 3
6840 13:08:23.857281 16, 0x0, sum = 4
6841 13:08:23.860003 best_step = 14
6842 13:08:23.860140
6843 13:08:23.860247 ==
6844 13:08:23.863164 Dram Type= 6, Freq= 0, CH_1, rank 0
6845 13:08:23.866837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6846 13:08:23.866977 ==
6847 13:08:23.869813 RX Vref Scan: 1
6848 13:08:23.869969
6849 13:08:23.873539 RX Vref 0 -> 0, step: 1
6850 13:08:23.873676
6851 13:08:23.873783 RX Delay -375 -> 252, step: 8
6852 13:08:23.873883
6853 13:08:23.876695 Set Vref, RX VrefLevel [Byte0]: 53
6854 13:08:23.879691 [Byte1]: 48
6855 13:08:23.885124
6856 13:08:23.885199 Final RX Vref Byte 0 = 53 to rank0
6857 13:08:23.888969 Final RX Vref Byte 1 = 48 to rank0
6858 13:08:23.891794 Final RX Vref Byte 0 = 53 to rank1
6859 13:08:23.895324 Final RX Vref Byte 1 = 48 to rank1==
6860 13:08:23.898344 Dram Type= 6, Freq= 0, CH_1, rank 0
6861 13:08:23.905581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 13:08:23.905656 ==
6863 13:08:23.905714 DQS Delay:
6864 13:08:23.908697 DQS0 = 52, DQS1 = 68
6865 13:08:23.908771 DQM Delay:
6866 13:08:23.908828 DQM0 = 9, DQM1 = 14
6867 13:08:23.912003 DQ Delay:
6868 13:08:23.914789 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6869 13:08:23.914868 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =8
6870 13:08:23.918508 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6871 13:08:23.921526 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6872 13:08:23.921601
6873 13:08:23.924981
6874 13:08:23.931806 [DQSOSCAuto] RK0, (LSB)MR18= 0x5e71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 397 ps
6875 13:08:23.934713 CH1 RK0: MR19=C0C, MR18=5E71
6876 13:08:23.941364 CH1_RK0: MR19=0xC0C, MR18=0x5E71, DQSOSC=395, MR23=63, INC=378, DEC=252
6877 13:08:23.941461 ==
6878 13:08:23.944858 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 13:08:23.947999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 13:08:23.948074 ==
6881 13:08:23.951129 [Gating] SW mode calibration
6882 13:08:23.958132 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6883 13:08:23.964469 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6884 13:08:23.967743 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6885 13:08:23.971379 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6886 13:08:23.977757 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6887 13:08:23.981484 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6888 13:08:23.984467 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6889 13:08:23.990856 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6890 13:08:23.994368 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6891 13:08:23.997520 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6892 13:08:24.004066 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6893 13:08:24.004153 Total UI for P1: 0, mck2ui 16
6894 13:08:24.007369 best dqsien dly found for B0: ( 0, 14, 24)
6895 13:08:24.011100 Total UI for P1: 0, mck2ui 16
6896 13:08:24.014674 best dqsien dly found for B1: ( 0, 14, 24)
6897 13:08:24.020874 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6898 13:08:24.024219 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6899 13:08:24.024286
6900 13:08:24.027511 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6901 13:08:24.031286 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6902 13:08:24.034714 [Gating] SW calibration Done
6903 13:08:24.034790 ==
6904 13:08:24.037645 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 13:08:24.040692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 13:08:24.040767 ==
6907 13:08:24.044396 RX Vref Scan: 0
6908 13:08:24.044471
6909 13:08:24.044527 RX Vref 0 -> 0, step: 1
6910 13:08:24.044582
6911 13:08:24.047437 RX Delay -410 -> 252, step: 16
6912 13:08:24.054280 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6913 13:08:24.057471 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6914 13:08:24.060455 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6915 13:08:24.064307 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6916 13:08:24.070360 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6917 13:08:24.074011 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6918 13:08:24.076892 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6919 13:08:24.080664 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6920 13:08:24.087077 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6921 13:08:24.090618 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6922 13:08:24.094211 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6923 13:08:24.097123 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6924 13:08:24.103640 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6925 13:08:24.106691 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6926 13:08:24.110129 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6927 13:08:24.113609 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6928 13:08:24.116797 ==
6929 13:08:24.116862 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 13:08:24.123479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 13:08:24.123548 ==
6932 13:08:24.123608 DQS Delay:
6933 13:08:24.126678 DQS0 = 59, DQS1 = 59
6934 13:08:24.126756 DQM Delay:
6935 13:08:24.130194 DQM0 = 19, DQM1 = 12
6936 13:08:24.130269 DQ Delay:
6937 13:08:24.133178 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6938 13:08:24.136900 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6939 13:08:24.140083 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6940 13:08:24.143213 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6941 13:08:24.143288
6942 13:08:24.143345
6943 13:08:24.143398 ==
6944 13:08:24.146855 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 13:08:24.149654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 13:08:24.149730 ==
6947 13:08:24.149788
6948 13:08:24.149842
6949 13:08:24.153257 TX Vref Scan disable
6950 13:08:24.153334 == TX Byte 0 ==
6951 13:08:24.159692 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6952 13:08:24.163205 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6953 13:08:24.163282 == TX Byte 1 ==
6954 13:08:24.169760 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6955 13:08:24.172761 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6956 13:08:24.172826 ==
6957 13:08:24.176324 Dram Type= 6, Freq= 0, CH_1, rank 1
6958 13:08:24.179830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6959 13:08:24.179909 ==
6960 13:08:24.179963
6961 13:08:24.180019
6962 13:08:24.182728 TX Vref Scan disable
6963 13:08:24.182816 == TX Byte 0 ==
6964 13:08:24.189722 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6965 13:08:24.192865 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6966 13:08:24.192936 == TX Byte 1 ==
6967 13:08:24.199700 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6968 13:08:24.202767 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6969 13:08:24.202840
6970 13:08:24.202921 [DATLAT]
6971 13:08:24.206342 Freq=400, CH1 RK1
6972 13:08:24.206407
6973 13:08:24.206461 DATLAT Default: 0xe
6974 13:08:24.209534 0, 0xFFFF, sum = 0
6975 13:08:24.209615 1, 0xFFFF, sum = 0
6976 13:08:24.212666 2, 0xFFFF, sum = 0
6977 13:08:24.212730 3, 0xFFFF, sum = 0
6978 13:08:24.215932 4, 0xFFFF, sum = 0
6979 13:08:24.216021 5, 0xFFFF, sum = 0
6980 13:08:24.219730 6, 0xFFFF, sum = 0
6981 13:08:24.219806 7, 0xFFFF, sum = 0
6982 13:08:24.222640 8, 0xFFFF, sum = 0
6983 13:08:24.226269 9, 0xFFFF, sum = 0
6984 13:08:24.226344 10, 0xFFFF, sum = 0
6985 13:08:24.229635 11, 0xFFFF, sum = 0
6986 13:08:24.229708 12, 0xFFFF, sum = 0
6987 13:08:24.232615 13, 0x0, sum = 1
6988 13:08:24.232683 14, 0x0, sum = 2
6989 13:08:24.235939 15, 0x0, sum = 3
6990 13:08:24.236011 16, 0x0, sum = 4
6991 13:08:24.236084 best_step = 14
6992 13:08:24.239727
6993 13:08:24.239819 ==
6994 13:08:24.242589 Dram Type= 6, Freq= 0, CH_1, rank 1
6995 13:08:24.246086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6996 13:08:24.246196 ==
6997 13:08:24.246253 RX Vref Scan: 0
6998 13:08:24.246306
6999 13:08:24.249116 RX Vref 0 -> 0, step: 1
7000 13:08:24.249203
7001 13:08:24.252482 RX Delay -359 -> 252, step: 8
7002 13:08:24.259671 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7003 13:08:24.263056 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7004 13:08:24.266589 iDelay=217, Bit 2, Center -56 (-303 ~ 192) 496
7005 13:08:24.272766 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7006 13:08:24.276460 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
7007 13:08:24.279595 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7008 13:08:24.282725 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7009 13:08:24.289429 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7010 13:08:24.292701 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7011 13:08:24.295989 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7012 13:08:24.299211 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7013 13:08:24.305769 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7014 13:08:24.309175 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7015 13:08:24.312368 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7016 13:08:24.316043 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7017 13:08:24.322811 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7018 13:08:24.322883 ==
7019 13:08:24.325503 Dram Type= 6, Freq= 0, CH_1, rank 1
7020 13:08:24.329032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7021 13:08:24.329132 ==
7022 13:08:24.329216 DQS Delay:
7023 13:08:24.332260 DQS0 = 56, DQS1 = 64
7024 13:08:24.332359 DQM Delay:
7025 13:08:24.335747 DQM0 = 9, DQM1 = 10
7026 13:08:24.335896 DQ Delay:
7027 13:08:24.339156 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
7028 13:08:24.342601 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =4
7029 13:08:24.345833 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7030 13:08:24.349250 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7031 13:08:24.349356
7032 13:08:24.349415
7033 13:08:24.355763 [DQSOSCAuto] RK1, (LSB)MR18= 0x87b7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 392 ps
7034 13:08:24.358935 CH1 RK1: MR19=C0C, MR18=87B7
7035 13:08:24.365648 CH1_RK1: MR19=0xC0C, MR18=0x87B7, DQSOSC=387, MR23=63, INC=394, DEC=262
7036 13:08:24.369016 [RxdqsGatingPostProcess] freq 400
7037 13:08:24.375886 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7038 13:08:24.375982 best DQS0 dly(2T, 0.5T) = (0, 10)
7039 13:08:24.378973 best DQS1 dly(2T, 0.5T) = (0, 10)
7040 13:08:24.382978 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7041 13:08:24.385658 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7042 13:08:24.389651 best DQS0 dly(2T, 0.5T) = (0, 10)
7043 13:08:24.392572 best DQS1 dly(2T, 0.5T) = (0, 10)
7044 13:08:24.396071 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7045 13:08:24.398965 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7046 13:08:24.402308 Pre-setting of DQS Precalculation
7047 13:08:24.408979 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7048 13:08:24.415785 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7049 13:08:24.422471 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7050 13:08:24.422544
7051 13:08:24.422612
7052 13:08:24.425587 [Calibration Summary] 800 Mbps
7053 13:08:24.425677 CH 0, Rank 0
7054 13:08:24.429346 SW Impedance : PASS
7055 13:08:24.429440 DUTY Scan : NO K
7056 13:08:24.432201 ZQ Calibration : PASS
7057 13:08:24.435454 Jitter Meter : NO K
7058 13:08:24.435523 CBT Training : PASS
7059 13:08:24.439019 Write leveling : PASS
7060 13:08:24.442077 RX DQS gating : PASS
7061 13:08:24.442194 RX DQ/DQS(RDDQC) : PASS
7062 13:08:24.445494 TX DQ/DQS : PASS
7063 13:08:24.448652 RX DATLAT : PASS
7064 13:08:24.448742 RX DQ/DQS(Engine): PASS
7065 13:08:24.452443 TX OE : NO K
7066 13:08:24.452536 All Pass.
7067 13:08:24.452619
7068 13:08:24.455612 CH 0, Rank 1
7069 13:08:24.455694 SW Impedance : PASS
7070 13:08:24.458816 DUTY Scan : NO K
7071 13:08:24.462468 ZQ Calibration : PASS
7072 13:08:24.462562 Jitter Meter : NO K
7073 13:08:24.465275 CBT Training : PASS
7074 13:08:24.468802 Write leveling : NO K
7075 13:08:24.468885 RX DQS gating : PASS
7076 13:08:24.472507 RX DQ/DQS(RDDQC) : PASS
7077 13:08:24.475526 TX DQ/DQS : PASS
7078 13:08:24.475621 RX DATLAT : PASS
7079 13:08:24.478929 RX DQ/DQS(Engine): PASS
7080 13:08:24.479020 TX OE : NO K
7081 13:08:24.482482 All Pass.
7082 13:08:24.482549
7083 13:08:24.482605 CH 1, Rank 0
7084 13:08:24.485486 SW Impedance : PASS
7085 13:08:24.485558 DUTY Scan : NO K
7086 13:08:24.488726 ZQ Calibration : PASS
7087 13:08:24.492454 Jitter Meter : NO K
7088 13:08:24.492552 CBT Training : PASS
7089 13:08:24.495020 Write leveling : PASS
7090 13:08:24.498662 RX DQS gating : PASS
7091 13:08:24.498755 RX DQ/DQS(RDDQC) : PASS
7092 13:08:24.502272 TX DQ/DQS : PASS
7093 13:08:24.505418 RX DATLAT : PASS
7094 13:08:24.505482 RX DQ/DQS(Engine): PASS
7095 13:08:24.508743 TX OE : NO K
7096 13:08:24.508823 All Pass.
7097 13:08:24.508890
7098 13:08:24.511567 CH 1, Rank 1
7099 13:08:24.511631 SW Impedance : PASS
7100 13:08:24.515416 DUTY Scan : NO K
7101 13:08:24.518347 ZQ Calibration : PASS
7102 13:08:24.518409 Jitter Meter : NO K
7103 13:08:24.522018 CBT Training : PASS
7104 13:08:24.525168 Write leveling : NO K
7105 13:08:24.525232 RX DQS gating : PASS
7106 13:08:24.528420 RX DQ/DQS(RDDQC) : PASS
7107 13:08:24.528492 TX DQ/DQS : PASS
7108 13:08:24.532112 RX DATLAT : PASS
7109 13:08:24.534972 RX DQ/DQS(Engine): PASS
7110 13:08:24.535065 TX OE : NO K
7111 13:08:24.538712 All Pass.
7112 13:08:24.538805
7113 13:08:24.538896 DramC Write-DBI off
7114 13:08:24.541880 PER_BANK_REFRESH: Hybrid Mode
7115 13:08:24.545088 TX_TRACKING: ON
7116 13:08:24.551684 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7117 13:08:24.555345 [FAST_K] Save calibration result to emmc
7118 13:08:24.562153 dramc_set_vcore_voltage set vcore to 725000
7119 13:08:24.562222 Read voltage for 1600, 0
7120 13:08:24.562280 Vio18 = 0
7121 13:08:24.564829 Vcore = 725000
7122 13:08:24.564897 Vdram = 0
7123 13:08:24.564953 Vddq = 0
7124 13:08:24.568475 Vmddr = 0
7125 13:08:24.571774 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7126 13:08:24.578555 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7127 13:08:24.581570 MEM_TYPE=3, freq_sel=13
7128 13:08:24.581661 sv_algorithm_assistance_LP4_3733
7129 13:08:24.588384 ============ PULL DRAM RESETB DOWN ============
7130 13:08:24.591890 ========== PULL DRAM RESETB DOWN end =========
7131 13:08:24.595198 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7132 13:08:24.598036 ===================================
7133 13:08:24.601202 LPDDR4 DRAM CONFIGURATION
7134 13:08:24.604537 ===================================
7135 13:08:24.608117 EX_ROW_EN[0] = 0x0
7136 13:08:24.608212 EX_ROW_EN[1] = 0x0
7137 13:08:24.611577 LP4Y_EN = 0x0
7138 13:08:24.611671 WORK_FSP = 0x1
7139 13:08:24.615042 WL = 0x5
7140 13:08:24.615110 RL = 0x5
7141 13:08:24.618012 BL = 0x2
7142 13:08:24.618127 RPST = 0x0
7143 13:08:24.621795 RD_PRE = 0x0
7144 13:08:24.621863 WR_PRE = 0x1
7145 13:08:24.624637 WR_PST = 0x1
7146 13:08:24.624705 DBI_WR = 0x0
7147 13:08:24.628246 DBI_RD = 0x0
7148 13:08:24.628314 OTF = 0x1
7149 13:08:24.631975 ===================================
7150 13:08:24.634583 ===================================
7151 13:08:24.637688 ANA top config
7152 13:08:24.641235 ===================================
7153 13:08:24.644707 DLL_ASYNC_EN = 0
7154 13:08:24.644793 ALL_SLAVE_EN = 0
7155 13:08:24.647954 NEW_RANK_MODE = 1
7156 13:08:24.651543 DLL_IDLE_MODE = 1
7157 13:08:24.654671 LP45_APHY_COMB_EN = 1
7158 13:08:24.657885 TX_ODT_DIS = 0
7159 13:08:24.657988 NEW_8X_MODE = 1
7160 13:08:24.661092 ===================================
7161 13:08:24.664819 ===================================
7162 13:08:24.667910 data_rate = 3200
7163 13:08:24.671083 CKR = 1
7164 13:08:24.674628 DQ_P2S_RATIO = 8
7165 13:08:24.677840 ===================================
7166 13:08:24.681181 CA_P2S_RATIO = 8
7167 13:08:24.681257 DQ_CA_OPEN = 0
7168 13:08:24.684547 DQ_SEMI_OPEN = 0
7169 13:08:24.687645 CA_SEMI_OPEN = 0
7170 13:08:24.691296 CA_FULL_RATE = 0
7171 13:08:24.694391 DQ_CKDIV4_EN = 0
7172 13:08:24.697788 CA_CKDIV4_EN = 0
7173 13:08:24.697863 CA_PREDIV_EN = 0
7174 13:08:24.701485 PH8_DLY = 12
7175 13:08:24.704313 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7176 13:08:24.707505 DQ_AAMCK_DIV = 4
7177 13:08:24.711069 CA_AAMCK_DIV = 4
7178 13:08:24.714642 CA_ADMCK_DIV = 4
7179 13:08:24.714711 DQ_TRACK_CA_EN = 0
7180 13:08:24.717482 CA_PICK = 1600
7181 13:08:24.721291 CA_MCKIO = 1600
7182 13:08:24.724705 MCKIO_SEMI = 0
7183 13:08:24.727470 PLL_FREQ = 3068
7184 13:08:24.730968 DQ_UI_PI_RATIO = 32
7185 13:08:24.734707 CA_UI_PI_RATIO = 0
7186 13:08:24.737645 ===================================
7187 13:08:24.741219 ===================================
7188 13:08:24.741295 memory_type:LPDDR4
7189 13:08:24.744047 GP_NUM : 10
7190 13:08:24.747369 SRAM_EN : 1
7191 13:08:24.747443 MD32_EN : 0
7192 13:08:24.750756 ===================================
7193 13:08:24.754453 [ANA_INIT] >>>>>>>>>>>>>>
7194 13:08:24.757490 <<<<<< [CONFIGURE PHASE]: ANA_TX
7195 13:08:24.761404 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7196 13:08:24.764246 ===================================
7197 13:08:24.767189 data_rate = 3200,PCW = 0X7600
7198 13:08:24.770808 ===================================
7199 13:08:24.773834 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7200 13:08:24.777414 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7201 13:08:24.783879 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7202 13:08:24.787565 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7203 13:08:24.790824 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7204 13:08:24.796984 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7205 13:08:24.797059 [ANA_INIT] flow start
7206 13:08:24.800673 [ANA_INIT] PLL >>>>>>>>
7207 13:08:24.803597 [ANA_INIT] PLL <<<<<<<<
7208 13:08:24.803672 [ANA_INIT] MIDPI >>>>>>>>
7209 13:08:24.807225 [ANA_INIT] MIDPI <<<<<<<<
7210 13:08:24.810485 [ANA_INIT] DLL >>>>>>>>
7211 13:08:24.810560 [ANA_INIT] DLL <<<<<<<<
7212 13:08:24.813953 [ANA_INIT] flow end
7213 13:08:24.817338 ============ LP4 DIFF to SE enter ============
7214 13:08:24.820110 ============ LP4 DIFF to SE exit ============
7215 13:08:24.823888 [ANA_INIT] <<<<<<<<<<<<<
7216 13:08:24.826974 [Flow] Enable top DCM control >>>>>
7217 13:08:24.829982 [Flow] Enable top DCM control <<<<<
7218 13:08:24.833262 Enable DLL master slave shuffle
7219 13:08:24.840137 ==============================================================
7220 13:08:24.840214 Gating Mode config
7221 13:08:24.846807 ==============================================================
7222 13:08:24.846884 Config description:
7223 13:08:24.856647 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7224 13:08:24.863563 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7225 13:08:24.869727 SELPH_MODE 0: By rank 1: By Phase
7226 13:08:24.876183 ==============================================================
7227 13:08:24.876260 GAT_TRACK_EN = 1
7228 13:08:24.879542 RX_GATING_MODE = 2
7229 13:08:24.883063 RX_GATING_TRACK_MODE = 2
7230 13:08:24.886455 SELPH_MODE = 1
7231 13:08:24.889806 PICG_EARLY_EN = 1
7232 13:08:24.892881 VALID_LAT_VALUE = 1
7233 13:08:24.899619 ==============================================================
7234 13:08:24.903155 Enter into Gating configuration >>>>
7235 13:08:24.905955 Exit from Gating configuration <<<<
7236 13:08:24.909490 Enter into DVFS_PRE_config >>>>>
7237 13:08:24.919673 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7238 13:08:24.922652 Exit from DVFS_PRE_config <<<<<
7239 13:08:24.926400 Enter into PICG configuration >>>>
7240 13:08:24.929504 Exit from PICG configuration <<<<
7241 13:08:24.932717 [RX_INPUT] configuration >>>>>
7242 13:08:24.932806 [RX_INPUT] configuration <<<<<
7243 13:08:24.939369 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7244 13:08:24.946212 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7245 13:08:24.952236 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7246 13:08:24.956114 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7247 13:08:24.962661 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7248 13:08:24.969046 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7249 13:08:24.972203 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7250 13:08:24.975628 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7251 13:08:24.982164 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7252 13:08:24.985425 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7253 13:08:24.988737 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7254 13:08:24.995601 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7255 13:08:24.998811 ===================================
7256 13:08:24.998887 LPDDR4 DRAM CONFIGURATION
7257 13:08:25.002000 ===================================
7258 13:08:25.005222 EX_ROW_EN[0] = 0x0
7259 13:08:25.009000 EX_ROW_EN[1] = 0x0
7260 13:08:25.009085 LP4Y_EN = 0x0
7261 13:08:25.012337 WORK_FSP = 0x1
7262 13:08:25.012429 WL = 0x5
7263 13:08:25.015693 RL = 0x5
7264 13:08:25.015794 BL = 0x2
7265 13:08:25.018689 RPST = 0x0
7266 13:08:25.018790 RD_PRE = 0x0
7267 13:08:25.022149 WR_PRE = 0x1
7268 13:08:25.022262 WR_PST = 0x1
7269 13:08:25.025114 DBI_WR = 0x0
7270 13:08:25.025236 DBI_RD = 0x0
7271 13:08:25.029029 OTF = 0x1
7272 13:08:25.032183 ===================================
7273 13:08:25.035222 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7274 13:08:25.038531 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7275 13:08:25.045204 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7276 13:08:25.048276 ===================================
7277 13:08:25.048415 LPDDR4 DRAM CONFIGURATION
7278 13:08:25.051935 ===================================
7279 13:08:25.055054 EX_ROW_EN[0] = 0x10
7280 13:08:25.058544 EX_ROW_EN[1] = 0x0
7281 13:08:25.058701 LP4Y_EN = 0x0
7282 13:08:25.061796 WORK_FSP = 0x1
7283 13:08:25.061978 WL = 0x5
7284 13:08:25.065270 RL = 0x5
7285 13:08:25.065487 BL = 0x2
7286 13:08:25.068126 RPST = 0x0
7287 13:08:25.068343 RD_PRE = 0x0
7288 13:08:25.071779 WR_PRE = 0x1
7289 13:08:25.072049 WR_PST = 0x1
7290 13:08:25.075366 DBI_WR = 0x0
7291 13:08:25.075738 DBI_RD = 0x0
7292 13:08:25.078478 OTF = 0x1
7293 13:08:25.081935 ===================================
7294 13:08:25.088784 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7295 13:08:25.089198 ==
7296 13:08:25.091854 Dram Type= 6, Freq= 0, CH_0, rank 0
7297 13:08:25.095200 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7298 13:08:25.095589 ==
7299 13:08:25.098387 [Duty_Offset_Calibration]
7300 13:08:25.098971 B0:2 B1:0 CA:3
7301 13:08:25.099429
7302 13:08:25.101413 [DutyScan_Calibration_Flow] k_type=0
7303 13:08:25.112231
7304 13:08:25.112631 ==CLK 0==
7305 13:08:25.115535 Final CLK duty delay cell = 0
7306 13:08:25.118955 [0] MAX Duty = 5062%(X100), DQS PI = 20
7307 13:08:25.122130 [0] MIN Duty = 4907%(X100), DQS PI = 6
7308 13:08:25.122526 [0] AVG Duty = 4984%(X100)
7309 13:08:25.125329
7310 13:08:25.125863 CH0 CLK Duty spec in!! Max-Min= 155%
7311 13:08:25.132297 [DutyScan_Calibration_Flow] ====Done====
7312 13:08:25.132837
7313 13:08:25.135367 [DutyScan_Calibration_Flow] k_type=1
7314 13:08:25.152655
7315 13:08:25.153004 ==DQS 0 ==
7316 13:08:25.155420 Final DQS duty delay cell = 0
7317 13:08:25.158795 [0] MAX Duty = 5125%(X100), DQS PI = 30
7318 13:08:25.162183 [0] MIN Duty = 4875%(X100), DQS PI = 50
7319 13:08:25.165146 [0] AVG Duty = 5000%(X100)
7320 13:08:25.165533
7321 13:08:25.165858 ==DQS 1 ==
7322 13:08:25.168846 Final DQS duty delay cell = 0
7323 13:08:25.171856 [0] MAX Duty = 5156%(X100), DQS PI = 32
7324 13:08:25.175297 [0] MIN Duty = 5031%(X100), DQS PI = 12
7325 13:08:25.178610 [0] AVG Duty = 5093%(X100)
7326 13:08:25.178887
7327 13:08:25.181813 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7328 13:08:25.182157
7329 13:08:25.185322 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7330 13:08:25.188411 [DutyScan_Calibration_Flow] ====Done====
7331 13:08:25.188687
7332 13:08:25.191305 [DutyScan_Calibration_Flow] k_type=3
7333 13:08:25.209849
7334 13:08:25.210147 ==DQM 0 ==
7335 13:08:25.213190 Final DQM duty delay cell = 0
7336 13:08:25.217302 [0] MAX Duty = 5156%(X100), DQS PI = 30
7337 13:08:25.220007 [0] MIN Duty = 4875%(X100), DQS PI = 0
7338 13:08:25.220364 [0] AVG Duty = 5015%(X100)
7339 13:08:25.223747
7340 13:08:25.224018 ==DQM 1 ==
7341 13:08:25.226968 Final DQM duty delay cell = 4
7342 13:08:25.230187 [4] MAX Duty = 5156%(X100), DQS PI = 60
7343 13:08:25.233739 [4] MIN Duty = 5000%(X100), DQS PI = 12
7344 13:08:25.234009 [4] AVG Duty = 5078%(X100)
7345 13:08:25.236644
7346 13:08:25.240112 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7347 13:08:25.240387
7348 13:08:25.243547 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7349 13:08:25.246967 [DutyScan_Calibration_Flow] ====Done====
7350 13:08:25.247215
7351 13:08:25.250124 [DutyScan_Calibration_Flow] k_type=2
7352 13:08:25.266501
7353 13:08:25.266755 ==DQ 0 ==
7354 13:08:25.270038 Final DQ duty delay cell = -4
7355 13:08:25.272975 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7356 13:08:25.276173 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7357 13:08:25.279976 [-4] AVG Duty = 4938%(X100)
7358 13:08:25.280211
7359 13:08:25.280406 ==DQ 1 ==
7360 13:08:25.282997 Final DQ duty delay cell = 0
7361 13:08:25.286299 [0] MAX Duty = 5156%(X100), DQS PI = 60
7362 13:08:25.289495 [0] MIN Duty = 5000%(X100), DQS PI = 16
7363 13:08:25.292704 [0] AVG Duty = 5078%(X100)
7364 13:08:25.293006
7365 13:08:25.296399 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7366 13:08:25.296756
7367 13:08:25.299689 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7368 13:08:25.303045 [DutyScan_Calibration_Flow] ====Done====
7369 13:08:25.303473 ==
7370 13:08:25.306505 Dram Type= 6, Freq= 0, CH_1, rank 0
7371 13:08:25.309475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7372 13:08:25.309994 ==
7373 13:08:25.312701 [Duty_Offset_Calibration]
7374 13:08:25.313189 B0:1 B1:-2 CA:1
7375 13:08:25.313624
7376 13:08:25.315923 [DutyScan_Calibration_Flow] k_type=0
7377 13:08:25.326956
7378 13:08:25.327293 ==CLK 0==
7379 13:08:25.329981 Final CLK duty delay cell = 0
7380 13:08:25.333444 [0] MAX Duty = 5062%(X100), DQS PI = 22
7381 13:08:25.336546 [0] MIN Duty = 4844%(X100), DQS PI = 4
7382 13:08:25.336709 [0] AVG Duty = 4953%(X100)
7383 13:08:25.340125
7384 13:08:25.343834 CH1 CLK Duty spec in!! Max-Min= 218%
7385 13:08:25.347264 [DutyScan_Calibration_Flow] ====Done====
7386 13:08:25.347443
7387 13:08:25.349691 [DutyScan_Calibration_Flow] k_type=1
7388 13:08:25.366384
7389 13:08:25.366546 ==DQS 0 ==
7390 13:08:25.370069 Final DQS duty delay cell = 0
7391 13:08:25.373186 [0] MAX Duty = 5187%(X100), DQS PI = 24
7392 13:08:25.376968 [0] MIN Duty = 5031%(X100), DQS PI = 54
7393 13:08:25.379961 [0] AVG Duty = 5109%(X100)
7394 13:08:25.380327
7395 13:08:25.380561 ==DQS 1 ==
7396 13:08:25.383656 Final DQS duty delay cell = 0
7397 13:08:25.386793 [0] MAX Duty = 5093%(X100), DQS PI = 60
7398 13:08:25.390422 [0] MIN Duty = 4844%(X100), DQS PI = 24
7399 13:08:25.393697 [0] AVG Duty = 4968%(X100)
7400 13:08:25.394075
7401 13:08:25.396678 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7402 13:08:25.397060
7403 13:08:25.400077 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7404 13:08:25.403473 [DutyScan_Calibration_Flow] ====Done====
7405 13:08:25.403937
7406 13:08:25.406634 [DutyScan_Calibration_Flow] k_type=3
7407 13:08:25.423722
7408 13:08:25.424185 ==DQM 0 ==
7409 13:08:25.427365 Final DQM duty delay cell = 0
7410 13:08:25.430884 [0] MAX Duty = 5031%(X100), DQS PI = 26
7411 13:08:25.434590 [0] MIN Duty = 4813%(X100), DQS PI = 56
7412 13:08:25.437150 [0] AVG Duty = 4922%(X100)
7413 13:08:25.437571
7414 13:08:25.437905 ==DQM 1 ==
7415 13:08:25.440302 Final DQM duty delay cell = 0
7416 13:08:25.443887 [0] MAX Duty = 5093%(X100), DQS PI = 36
7417 13:08:25.446871 [0] MIN Duty = 4875%(X100), DQS PI = 24
7418 13:08:25.450596 [0] AVG Duty = 4984%(X100)
7419 13:08:25.451024
7420 13:08:25.453670 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7421 13:08:25.454094
7422 13:08:25.457324 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7423 13:08:25.460344 [DutyScan_Calibration_Flow] ====Done====
7424 13:08:25.460768
7425 13:08:25.463330 [DutyScan_Calibration_Flow] k_type=2
7426 13:08:25.481053
7427 13:08:25.481475 ==DQ 0 ==
7428 13:08:25.484306 Final DQ duty delay cell = 0
7429 13:08:25.487340 [0] MAX Duty = 5093%(X100), DQS PI = 20
7430 13:08:25.490813 [0] MIN Duty = 4907%(X100), DQS PI = 62
7431 13:08:25.491197 [0] AVG Duty = 5000%(X100)
7432 13:08:25.491492
7433 13:08:25.494234 ==DQ 1 ==
7434 13:08:25.497831 Final DQ duty delay cell = 0
7435 13:08:25.501181 [0] MAX Duty = 5156%(X100), DQS PI = 34
7436 13:08:25.503941 [0] MIN Duty = 4969%(X100), DQS PI = 24
7437 13:08:25.504396 [0] AVG Duty = 5062%(X100)
7438 13:08:25.504725
7439 13:08:25.507601 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7440 13:08:25.510902
7441 13:08:25.514092 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7442 13:08:25.517305 [DutyScan_Calibration_Flow] ====Done====
7443 13:08:25.520601 nWR fixed to 30
7444 13:08:25.521138 [ModeRegInit_LP4] CH0 RK0
7445 13:08:25.524267 [ModeRegInit_LP4] CH0 RK1
7446 13:08:25.527395 [ModeRegInit_LP4] CH1 RK0
7447 13:08:25.530287 [ModeRegInit_LP4] CH1 RK1
7448 13:08:25.530727 match AC timing 5
7449 13:08:25.533957 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7450 13:08:25.540704 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7451 13:08:25.543632 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7452 13:08:25.550580 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7453 13:08:25.553661 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7454 13:08:25.554193 [MiockJmeterHQA]
7455 13:08:25.554525
7456 13:08:25.556760 [DramcMiockJmeter] u1RxGatingPI = 0
7457 13:08:25.560565 0 : 4254, 4027
7458 13:08:25.561138 4 : 4258, 4030
7459 13:08:25.563779 8 : 4257, 4029
7460 13:08:25.564277 12 : 4363, 4137
7461 13:08:25.564867 16 : 4252, 4027
7462 13:08:25.567181 20 : 4255, 4030
7463 13:08:25.567647 24 : 4253, 4026
7464 13:08:25.570532 28 : 4363, 4137
7465 13:08:25.571147 32 : 4254, 4029
7466 13:08:25.573834 36 : 4363, 4138
7467 13:08:25.574358 40 : 4252, 4027
7468 13:08:25.577452 44 : 4252, 4027
7469 13:08:25.577917 48 : 4253, 4026
7470 13:08:25.578328 52 : 4253, 4026
7471 13:08:25.580233 56 : 4360, 4138
7472 13:08:25.580708 60 : 4252, 4027
7473 13:08:25.583253 64 : 4361, 4137
7474 13:08:25.583762 68 : 4250, 4026
7475 13:08:25.586929 72 : 4250, 4026
7476 13:08:25.587430 76 : 4250, 4027
7477 13:08:25.589949 80 : 4361, 4137
7478 13:08:25.590475 84 : 4250, 4026
7479 13:08:25.590911 88 : 4360, 4138
7480 13:08:25.593606 92 : 4250, 4027
7481 13:08:25.594195 96 : 4250, 4027
7482 13:08:25.596882 100 : 4250, 4026
7483 13:08:25.597324 104 : 4250, 3634
7484 13:08:25.599911 108 : 4250, 1
7485 13:08:25.600339 112 : 4361, 0
7486 13:08:25.600700 116 : 4361, 0
7487 13:08:25.603139 120 : 4362, 0
7488 13:08:25.603591 124 : 4250, 0
7489 13:08:25.606499 128 : 4252, 0
7490 13:08:25.606926 132 : 4250, 0
7491 13:08:25.607256 136 : 4250, 0
7492 13:08:25.610214 140 : 4250, 0
7493 13:08:25.610606 144 : 4250, 0
7494 13:08:25.613036 148 : 4252, 0
7495 13:08:25.613461 152 : 4250, 0
7496 13:08:25.613805 156 : 4250, 0
7497 13:08:25.616157 160 : 4250, 0
7498 13:08:25.616640 164 : 4250, 0
7499 13:08:25.617065 168 : 4361, 0
7500 13:08:25.620028 172 : 4361, 0
7501 13:08:25.620436 176 : 4250, 0
7502 13:08:25.623165 180 : 4250, 0
7503 13:08:25.623687 184 : 4250, 0
7504 13:08:25.624146 188 : 4250, 0
7505 13:08:25.626041 192 : 4250, 0
7506 13:08:25.626511 196 : 4250, 0
7507 13:08:25.629845 200 : 4250, 0
7508 13:08:25.630364 204 : 4361, 0
7509 13:08:25.630680 208 : 4250, 0
7510 13:08:25.632931 212 : 4250, 0
7511 13:08:25.633431 216 : 4250, 0
7512 13:08:25.636044 220 : 4361, 0
7513 13:08:25.636485 224 : 4361, 0
7514 13:08:25.636858 228 : 4250, 0
7515 13:08:25.639986 232 : 4250, 0
7516 13:08:25.640459 236 : 4250, 866
7517 13:08:25.642675 240 : 4253, 4027
7518 13:08:25.643135 244 : 4250, 4027
7519 13:08:25.645901 248 : 4252, 4029
7520 13:08:25.646494 252 : 4250, 4026
7521 13:08:25.649620 256 : 4250, 4026
7522 13:08:25.650048 260 : 4250, 4027
7523 13:08:25.650507 264 : 4250, 4026
7524 13:08:25.652676 268 : 4250, 4027
7525 13:08:25.653151 272 : 4360, 4138
7526 13:08:25.656246 276 : 4360, 4138
7527 13:08:25.656677 280 : 4248, 4024
7528 13:08:25.659420 284 : 4361, 4138
7529 13:08:25.659807 288 : 4360, 4138
7530 13:08:25.662594 292 : 4250, 4026
7531 13:08:25.663047 296 : 4250, 4027
7532 13:08:25.666400 300 : 4250, 4026
7533 13:08:25.666858 304 : 4250, 4027
7534 13:08:25.669279 308 : 4250, 4027
7535 13:08:25.669722 312 : 4250, 4027
7536 13:08:25.672774 316 : 4250, 4026
7537 13:08:25.673183 320 : 4250, 4027
7538 13:08:25.673494 324 : 4360, 4138
7539 13:08:25.675732 328 : 4361, 4137
7540 13:08:25.676097 332 : 4248, 4024
7541 13:08:25.679439 336 : 4361, 4137
7542 13:08:25.679684 340 : 4360, 4138
7543 13:08:25.682297 344 : 4250, 4026
7544 13:08:25.682578 348 : 4250, 4027
7545 13:08:25.685850 352 : 4250, 4021
7546 13:08:25.686171 356 : 4250, 2984
7547 13:08:25.689256 360 : 4250, 0
7548 13:08:25.689657
7549 13:08:25.689889 MIOCK jitter meter ch=0
7550 13:08:25.690090
7551 13:08:25.692306 1T = (360-108) = 252 dly cells
7552 13:08:25.698788 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7553 13:08:25.698860 ==
7554 13:08:25.702425 Dram Type= 6, Freq= 0, CH_0, rank 0
7555 13:08:25.705819 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7556 13:08:25.705886 ==
7557 13:08:25.711797 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7558 13:08:25.715208 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7559 13:08:25.718860 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7560 13:08:25.725306 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7561 13:08:25.735181 [CA 0] Center 43 (13~74) winsize 62
7562 13:08:25.738292 [CA 1] Center 43 (13~74) winsize 62
7563 13:08:25.742116 [CA 2] Center 39 (10~68) winsize 59
7564 13:08:25.745159 [CA 3] Center 39 (10~68) winsize 59
7565 13:08:25.748387 [CA 4] Center 36 (7~66) winsize 60
7566 13:08:25.751918 [CA 5] Center 36 (7~66) winsize 60
7567 13:08:25.752006
7568 13:08:25.754750 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7569 13:08:25.754814
7570 13:08:25.761700 [CATrainingPosCal] consider 1 rank data
7571 13:08:25.761764 u2DelayCellTimex100 = 258/100 ps
7572 13:08:25.768014 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7573 13:08:25.771563 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7574 13:08:25.774828 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7575 13:08:25.777765 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7576 13:08:25.781276 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7577 13:08:25.784625 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7578 13:08:25.784714
7579 13:08:25.788005 CA PerBit enable=1, Macro0, CA PI delay=36
7580 13:08:25.788087
7581 13:08:25.791543 [CBTSetCACLKResult] CA Dly = 36
7582 13:08:25.794860 CS Dly: 11 (0~42)
7583 13:08:25.797891 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7584 13:08:25.801614 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7585 13:08:25.801759 ==
7586 13:08:25.804578 Dram Type= 6, Freq= 0, CH_0, rank 1
7587 13:08:25.811517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7588 13:08:25.811593 ==
7589 13:08:25.814918 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7590 13:08:25.821497 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7591 13:08:25.824401 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7592 13:08:25.831402 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7593 13:08:25.839212 [CA 0] Center 43 (13~74) winsize 62
7594 13:08:25.842449 [CA 1] Center 43 (13~74) winsize 62
7595 13:08:25.846342 [CA 2] Center 39 (10~68) winsize 59
7596 13:08:25.849022 [CA 3] Center 39 (10~68) winsize 59
7597 13:08:25.852210 [CA 4] Center 36 (6~66) winsize 61
7598 13:08:25.855880 [CA 5] Center 36 (6~66) winsize 61
7599 13:08:25.856047
7600 13:08:25.858919 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7601 13:08:25.859015
7602 13:08:25.865397 [CATrainingPosCal] consider 2 rank data
7603 13:08:25.865492 u2DelayCellTimex100 = 258/100 ps
7604 13:08:25.872150 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7605 13:08:25.875424 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7606 13:08:25.879156 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7607 13:08:25.882366 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7608 13:08:25.885230 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7609 13:08:25.888944 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7610 13:08:25.889011
7611 13:08:25.891997 CA PerBit enable=1, Macro0, CA PI delay=36
7612 13:08:25.892089
7613 13:08:25.895400 [CBTSetCACLKResult] CA Dly = 36
7614 13:08:25.898643 CS Dly: 11 (0~43)
7615 13:08:25.901939 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7616 13:08:25.905141 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7617 13:08:25.905233
7618 13:08:25.908955 ----->DramcWriteLeveling(PI) begin...
7619 13:08:25.909021 ==
7620 13:08:25.912139 Dram Type= 6, Freq= 0, CH_0, rank 0
7621 13:08:25.918796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7622 13:08:25.918898 ==
7623 13:08:25.922090 Write leveling (Byte 0): 36 => 36
7624 13:08:25.925575 Write leveling (Byte 1): 29 => 29
7625 13:08:25.925666 DramcWriteLeveling(PI) end<-----
7626 13:08:25.928421
7627 13:08:25.928488 ==
7628 13:08:25.931893 Dram Type= 6, Freq= 0, CH_0, rank 0
7629 13:08:25.935563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7630 13:08:25.935641 ==
7631 13:08:25.939039 [Gating] SW mode calibration
7632 13:08:25.945183 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7633 13:08:25.948461 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7634 13:08:25.954911 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7635 13:08:25.958612 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 13:08:25.961640 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 13:08:25.968366 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 13:08:25.971656 1 4 16 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
7639 13:08:25.975385 1 4 20 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
7640 13:08:25.981472 1 4 24 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7641 13:08:25.985085 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7642 13:08:25.988249 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7643 13:08:25.994991 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7644 13:08:25.998077 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7645 13:08:26.001873 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7646 13:08:26.008263 1 5 16 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
7647 13:08:26.011643 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
7648 13:08:26.014559 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
7649 13:08:26.021592 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7650 13:08:26.024887 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7651 13:08:26.027996 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 13:08:26.034682 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 13:08:26.038120 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7654 13:08:26.041231 1 6 16 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7655 13:08:26.048274 1 6 20 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7656 13:08:26.051450 1 6 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7657 13:08:26.054899 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7658 13:08:26.061394 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7659 13:08:26.064673 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7660 13:08:26.067810 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7661 13:08:26.074814 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7662 13:08:26.078369 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7663 13:08:26.081836 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7664 13:08:26.084655 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7665 13:08:26.091519 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 13:08:26.094733 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 13:08:26.097861 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 13:08:26.104746 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 13:08:26.107697 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 13:08:26.111393 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 13:08:26.117716 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 13:08:26.121383 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 13:08:26.124580 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 13:08:26.131601 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 13:08:26.134468 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 13:08:26.138029 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 13:08:26.144372 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 13:08:26.147731 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7679 13:08:26.151215 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7680 13:08:26.154428 Total UI for P1: 0, mck2ui 16
7681 13:08:26.157839 best dqsien dly found for B0: ( 1, 9, 16)
7682 13:08:26.164282 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7683 13:08:26.167914 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7684 13:08:26.171355 Total UI for P1: 0, mck2ui 16
7685 13:08:26.174468 best dqsien dly found for B1: ( 1, 9, 22)
7686 13:08:26.178014 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7687 13:08:26.181022 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7688 13:08:26.181438
7689 13:08:26.184839 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7690 13:08:26.188161 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7691 13:08:26.190932 [Gating] SW calibration Done
7692 13:08:26.191332 ==
7693 13:08:26.194708 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 13:08:26.197996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 13:08:26.201249 ==
7696 13:08:26.201649 RX Vref Scan: 0
7697 13:08:26.202060
7698 13:08:26.204208 RX Vref 0 -> 0, step: 1
7699 13:08:26.204629
7700 13:08:26.208023 RX Delay 0 -> 252, step: 8
7701 13:08:26.211429 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7702 13:08:26.214546 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7703 13:08:26.217702 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7704 13:08:26.220682 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7705 13:08:26.227818 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7706 13:08:26.231112 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7707 13:08:26.234402 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7708 13:08:26.237932 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7709 13:08:26.240917 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7710 13:08:26.247505 iDelay=192, Bit 9, Center 107 (48 ~ 167) 120
7711 13:08:26.251076 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7712 13:08:26.253946 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7713 13:08:26.257292 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7714 13:08:26.260915 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7715 13:08:26.267390 iDelay=192, Bit 14, Center 131 (72 ~ 191) 120
7716 13:08:26.270579 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7717 13:08:26.271195 ==
7718 13:08:26.273834 Dram Type= 6, Freq= 0, CH_0, rank 0
7719 13:08:26.277479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7720 13:08:26.277879 ==
7721 13:08:26.280219 DQS Delay:
7722 13:08:26.280577 DQS0 = 0, DQS1 = 0
7723 13:08:26.281033 DQM Delay:
7724 13:08:26.283806 DQM0 = 127, DQM1 = 122
7725 13:08:26.284238 DQ Delay:
7726 13:08:26.287197 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7727 13:08:26.290497 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =139
7728 13:08:26.294040 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7729 13:08:26.300529 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
7730 13:08:26.300786
7731 13:08:26.300951
7732 13:08:26.301100 ==
7733 13:08:26.303550 Dram Type= 6, Freq= 0, CH_0, rank 0
7734 13:08:26.307540 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7735 13:08:26.307711 ==
7736 13:08:26.307839
7737 13:08:26.307957
7738 13:08:26.310238 TX Vref Scan disable
7739 13:08:26.310312 == TX Byte 0 ==
7740 13:08:26.316500 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7741 13:08:26.320088 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7742 13:08:26.320176 == TX Byte 1 ==
7743 13:08:26.326436 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7744 13:08:26.330317 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7745 13:08:26.330387 ==
7746 13:08:26.333318 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 13:08:26.336246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 13:08:26.336315 ==
7749 13:08:26.351224
7750 13:08:26.354411 TX Vref early break, caculate TX vref
7751 13:08:26.358330 TX Vref=16, minBit 4, minWin=22, winSum=366
7752 13:08:26.361525 TX Vref=18, minBit 9, minWin=21, winSum=373
7753 13:08:26.364553 TX Vref=20, minBit 4, minWin=23, winSum=382
7754 13:08:26.367789 TX Vref=22, minBit 8, minWin=22, winSum=391
7755 13:08:26.371291 TX Vref=24, minBit 4, minWin=24, winSum=402
7756 13:08:26.377709 TX Vref=26, minBit 4, minWin=25, winSum=413
7757 13:08:26.381278 TX Vref=28, minBit 4, minWin=25, winSum=412
7758 13:08:26.384535 TX Vref=30, minBit 12, minWin=24, winSum=405
7759 13:08:26.387735 TX Vref=32, minBit 8, minWin=23, winSum=396
7760 13:08:26.391578 TX Vref=34, minBit 8, minWin=23, winSum=388
7761 13:08:26.397736 [TxChooseVref] Worse bit 4, Min win 25, Win sum 413, Final Vref 26
7762 13:08:26.397813
7763 13:08:26.401641 Final TX Range 0 Vref 26
7764 13:08:26.401717
7765 13:08:26.401776 ==
7766 13:08:26.404531 Dram Type= 6, Freq= 0, CH_0, rank 0
7767 13:08:26.407837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7768 13:08:26.407924 ==
7769 13:08:26.407986
7770 13:08:26.408040
7771 13:08:26.411704 TX Vref Scan disable
7772 13:08:26.417928 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7773 13:08:26.418007 == TX Byte 0 ==
7774 13:08:26.421124 u2DelayCellOfst[0]=15 cells (4 PI)
7775 13:08:26.425026 u2DelayCellOfst[1]=18 cells (5 PI)
7776 13:08:26.427862 u2DelayCellOfst[2]=11 cells (3 PI)
7777 13:08:26.431006 u2DelayCellOfst[3]=11 cells (3 PI)
7778 13:08:26.435135 u2DelayCellOfst[4]=7 cells (2 PI)
7779 13:08:26.437807 u2DelayCellOfst[5]=0 cells (0 PI)
7780 13:08:26.441107 u2DelayCellOfst[6]=18 cells (5 PI)
7781 13:08:26.444895 u2DelayCellOfst[7]=18 cells (5 PI)
7782 13:08:26.447542 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7783 13:08:26.451166 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7784 13:08:26.454260 == TX Byte 1 ==
7785 13:08:26.454335 u2DelayCellOfst[8]=0 cells (0 PI)
7786 13:08:26.457552 u2DelayCellOfst[9]=3 cells (1 PI)
7787 13:08:26.461130 u2DelayCellOfst[10]=7 cells (2 PI)
7788 13:08:26.464702 u2DelayCellOfst[11]=3 cells (1 PI)
7789 13:08:26.467809 u2DelayCellOfst[12]=11 cells (3 PI)
7790 13:08:26.471009 u2DelayCellOfst[13]=11 cells (3 PI)
7791 13:08:26.474042 u2DelayCellOfst[14]=15 cells (4 PI)
7792 13:08:26.477687 u2DelayCellOfst[15]=11 cells (3 PI)
7793 13:08:26.481057 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7794 13:08:26.487149 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7795 13:08:26.487229 DramC Write-DBI on
7796 13:08:26.487288 ==
7797 13:08:26.490843 Dram Type= 6, Freq= 0, CH_0, rank 0
7798 13:08:26.494416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7799 13:08:26.497123 ==
7800 13:08:26.497189
7801 13:08:26.497245
7802 13:08:26.497296 TX Vref Scan disable
7803 13:08:26.500760 == TX Byte 0 ==
7804 13:08:26.504440 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7805 13:08:26.507464 == TX Byte 1 ==
7806 13:08:26.511065 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7807 13:08:26.514110 DramC Write-DBI off
7808 13:08:26.514200
7809 13:08:26.514275 [DATLAT]
7810 13:08:26.514343 Freq=1600, CH0 RK0
7811 13:08:26.514394
7812 13:08:26.517358 DATLAT Default: 0xf
7813 13:08:26.520747 0, 0xFFFF, sum = 0
7814 13:08:26.520824 1, 0xFFFF, sum = 0
7815 13:08:26.523910 2, 0xFFFF, sum = 0
7816 13:08:26.523986 3, 0xFFFF, sum = 0
7817 13:08:26.527441 4, 0xFFFF, sum = 0
7818 13:08:26.527517 5, 0xFFFF, sum = 0
7819 13:08:26.530747 6, 0xFFFF, sum = 0
7820 13:08:26.530824 7, 0xFFFF, sum = 0
7821 13:08:26.534153 8, 0xFFFF, sum = 0
7822 13:08:26.534231 9, 0xFFFF, sum = 0
7823 13:08:26.537641 10, 0xFFFF, sum = 0
7824 13:08:26.537734 11, 0xFFFF, sum = 0
7825 13:08:26.541014 12, 0xFFFF, sum = 0
7826 13:08:26.541090 13, 0xCFFF, sum = 0
7827 13:08:26.544102 14, 0x0, sum = 1
7828 13:08:26.544178 15, 0x0, sum = 2
7829 13:08:26.547848 16, 0x0, sum = 3
7830 13:08:26.547924 17, 0x0, sum = 4
7831 13:08:26.550908 best_step = 15
7832 13:08:26.550987
7833 13:08:26.551048 ==
7834 13:08:26.554268 Dram Type= 6, Freq= 0, CH_0, rank 0
7835 13:08:26.557317 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7836 13:08:26.557408 ==
7837 13:08:26.560969 RX Vref Scan: 1
7838 13:08:26.561091
7839 13:08:26.561198 Set Vref Range= 24 -> 127
7840 13:08:26.561298
7841 13:08:26.563952 RX Vref 24 -> 127, step: 1
7842 13:08:26.564045
7843 13:08:26.567479 RX Delay 3 -> 252, step: 4
7844 13:08:26.567580
7845 13:08:26.570298 Set Vref, RX VrefLevel [Byte0]: 24
7846 13:08:26.574347 [Byte1]: 24
7847 13:08:26.574471
7848 13:08:26.577361 Set Vref, RX VrefLevel [Byte0]: 25
7849 13:08:26.580555 [Byte1]: 25
7850 13:08:26.584219
7851 13:08:26.584376 Set Vref, RX VrefLevel [Byte0]: 26
7852 13:08:26.587290 [Byte1]: 26
7853 13:08:26.591334
7854 13:08:26.591515 Set Vref, RX VrefLevel [Byte0]: 27
7855 13:08:26.595234 [Byte1]: 27
7856 13:08:26.599399
7857 13:08:26.599667 Set Vref, RX VrefLevel [Byte0]: 28
7858 13:08:26.602409 [Byte1]: 28
7859 13:08:26.607259
7860 13:08:26.607608 Set Vref, RX VrefLevel [Byte0]: 29
7861 13:08:26.610247 [Byte1]: 29
7862 13:08:26.615006
7863 13:08:26.615387 Set Vref, RX VrefLevel [Byte0]: 30
7864 13:08:26.618135 [Byte1]: 30
7865 13:08:26.622599
7866 13:08:26.622979 Set Vref, RX VrefLevel [Byte0]: 31
7867 13:08:26.626134 [Byte1]: 31
7868 13:08:26.630231
7869 13:08:26.630611 Set Vref, RX VrefLevel [Byte0]: 32
7870 13:08:26.633552 [Byte1]: 32
7871 13:08:26.637664
7872 13:08:26.638046 Set Vref, RX VrefLevel [Byte0]: 33
7873 13:08:26.640960 [Byte1]: 33
7874 13:08:26.645240
7875 13:08:26.645621 Set Vref, RX VrefLevel [Byte0]: 34
7876 13:08:26.649544 [Byte1]: 34
7877 13:08:26.652946
7878 13:08:26.653358 Set Vref, RX VrefLevel [Byte0]: 35
7879 13:08:26.656515 [Byte1]: 35
7880 13:08:26.661195
7881 13:08:26.661690 Set Vref, RX VrefLevel [Byte0]: 36
7882 13:08:26.664446 [Byte1]: 36
7883 13:08:26.668586
7884 13:08:26.669106 Set Vref, RX VrefLevel [Byte0]: 37
7885 13:08:26.671741 [Byte1]: 37
7886 13:08:26.675935
7887 13:08:26.676359 Set Vref, RX VrefLevel [Byte0]: 38
7888 13:08:26.679405 [Byte1]: 38
7889 13:08:26.683926
7890 13:08:26.684418 Set Vref, RX VrefLevel [Byte0]: 39
7891 13:08:26.686836 [Byte1]: 39
7892 13:08:26.691173
7893 13:08:26.691595 Set Vref, RX VrefLevel [Byte0]: 40
7894 13:08:26.694745 [Byte1]: 40
7895 13:08:26.699138
7896 13:08:26.699612 Set Vref, RX VrefLevel [Byte0]: 41
7897 13:08:26.702400 [Byte1]: 41
7898 13:08:26.706661
7899 13:08:26.707081 Set Vref, RX VrefLevel [Byte0]: 42
7900 13:08:26.709999 [Byte1]: 42
7901 13:08:26.714515
7902 13:08:26.714933 Set Vref, RX VrefLevel [Byte0]: 43
7903 13:08:26.717990 [Byte1]: 43
7904 13:08:26.721793
7905 13:08:26.722377 Set Vref, RX VrefLevel [Byte0]: 44
7906 13:08:26.725209 [Byte1]: 44
7907 13:08:26.729589
7908 13:08:26.730188 Set Vref, RX VrefLevel [Byte0]: 45
7909 13:08:26.732800 [Byte1]: 45
7910 13:08:26.737220
7911 13:08:26.737642 Set Vref, RX VrefLevel [Byte0]: 46
7912 13:08:26.740873 [Byte1]: 46
7913 13:08:26.744912
7914 13:08:26.745372 Set Vref, RX VrefLevel [Byte0]: 47
7915 13:08:26.748604 [Byte1]: 47
7916 13:08:26.752419
7917 13:08:26.752873 Set Vref, RX VrefLevel [Byte0]: 48
7918 13:08:26.755784 [Byte1]: 48
7919 13:08:26.760444
7920 13:08:26.760907 Set Vref, RX VrefLevel [Byte0]: 49
7921 13:08:26.763637 [Byte1]: 49
7922 13:08:26.768287
7923 13:08:26.768751 Set Vref, RX VrefLevel [Byte0]: 50
7924 13:08:26.771461 [Byte1]: 50
7925 13:08:26.775567
7926 13:08:26.776155 Set Vref, RX VrefLevel [Byte0]: 51
7927 13:08:26.778756 [Byte1]: 51
7928 13:08:26.783129
7929 13:08:26.783579 Set Vref, RX VrefLevel [Byte0]: 52
7930 13:08:26.786228 [Byte1]: 52
7931 13:08:26.790651
7932 13:08:26.791073 Set Vref, RX VrefLevel [Byte0]: 53
7933 13:08:26.793934 [Byte1]: 53
7934 13:08:26.798548
7935 13:08:26.798969 Set Vref, RX VrefLevel [Byte0]: 54
7936 13:08:26.804556 [Byte1]: 54
7937 13:08:26.805024
7938 13:08:26.808380 Set Vref, RX VrefLevel [Byte0]: 55
7939 13:08:26.811283 [Byte1]: 55
7940 13:08:26.811707
7941 13:08:26.814560 Set Vref, RX VrefLevel [Byte0]: 56
7942 13:08:26.818260 [Byte1]: 56
7943 13:08:26.821253
7944 13:08:26.821680 Set Vref, RX VrefLevel [Byte0]: 57
7945 13:08:26.824941 [Byte1]: 57
7946 13:08:26.829260
7947 13:08:26.829750 Set Vref, RX VrefLevel [Byte0]: 58
7948 13:08:26.832672 [Byte1]: 58
7949 13:08:26.836804
7950 13:08:26.837390 Set Vref, RX VrefLevel [Byte0]: 59
7951 13:08:26.840304 [Byte1]: 59
7952 13:08:26.844743
7953 13:08:26.845163 Set Vref, RX VrefLevel [Byte0]: 60
7954 13:08:26.847797 [Byte1]: 60
7955 13:08:26.852402
7956 13:08:26.852824 Set Vref, RX VrefLevel [Byte0]: 61
7957 13:08:26.855269 [Byte1]: 61
7958 13:08:26.859737
7959 13:08:26.860166 Set Vref, RX VrefLevel [Byte0]: 62
7960 13:08:26.863067 [Byte1]: 62
7961 13:08:26.868240
7962 13:08:26.868659 Set Vref, RX VrefLevel [Byte0]: 63
7963 13:08:26.870733 [Byte1]: 63
7964 13:08:26.875317
7965 13:08:26.875783 Set Vref, RX VrefLevel [Byte0]: 64
7966 13:08:26.878712 [Byte1]: 64
7967 13:08:26.882671
7968 13:08:26.883095 Set Vref, RX VrefLevel [Byte0]: 65
7969 13:08:26.886157 [Byte1]: 65
7970 13:08:26.890414
7971 13:08:26.890838 Set Vref, RX VrefLevel [Byte0]: 66
7972 13:08:26.893702 [Byte1]: 66
7973 13:08:26.897852
7974 13:08:26.898618 Set Vref, RX VrefLevel [Byte0]: 67
7975 13:08:26.901287 [Byte1]: 67
7976 13:08:26.905383
7977 13:08:26.905791 Set Vref, RX VrefLevel [Byte0]: 68
7978 13:08:26.908807 [Byte1]: 68
7979 13:08:26.913185
7980 13:08:26.913604 Set Vref, RX VrefLevel [Byte0]: 69
7981 13:08:26.916890 [Byte1]: 69
7982 13:08:26.921023
7983 13:08:26.921470 Set Vref, RX VrefLevel [Byte0]: 70
7984 13:08:26.924324 [Byte1]: 70
7985 13:08:26.928299
7986 13:08:26.928697 Set Vref, RX VrefLevel [Byte0]: 71
7987 13:08:26.932010 [Byte1]: 71
7988 13:08:26.936143
7989 13:08:26.936806 Set Vref, RX VrefLevel [Byte0]: 72
7990 13:08:26.939594 [Byte1]: 72
7991 13:08:26.943847
7992 13:08:26.944224 Set Vref, RX VrefLevel [Byte0]: 73
7993 13:08:26.947306 [Byte1]: 73
7994 13:08:26.952050
7995 13:08:26.952458 Set Vref, RX VrefLevel [Byte0]: 74
7996 13:08:26.954907 [Byte1]: 74
7997 13:08:26.959276
7998 13:08:26.959684 Set Vref, RX VrefLevel [Byte0]: 75
7999 13:08:26.962218 [Byte1]: 75
8000 13:08:26.967038
8001 13:08:26.969863 Set Vref, RX VrefLevel [Byte0]: 76
8002 13:08:26.973269 [Byte1]: 76
8003 13:08:26.973653
8004 13:08:26.976425 Final RX Vref Byte 0 = 63 to rank0
8005 13:08:26.980095 Final RX Vref Byte 1 = 61 to rank0
8006 13:08:26.982969 Final RX Vref Byte 0 = 63 to rank1
8007 13:08:26.986965 Final RX Vref Byte 1 = 61 to rank1==
8008 13:08:26.990012 Dram Type= 6, Freq= 0, CH_0, rank 0
8009 13:08:26.993148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8010 13:08:26.993627 ==
8011 13:08:26.993928 DQS Delay:
8012 13:08:26.996412 DQS0 = 0, DQS1 = 0
8013 13:08:26.996798 DQM Delay:
8014 13:08:26.999739 DQM0 = 126, DQM1 = 119
8015 13:08:27.000123 DQ Delay:
8016 13:08:27.003616 DQ0 =126, DQ1 =126, DQ2 =126, DQ3 =122
8017 13:08:27.006607 DQ4 =126, DQ5 =114, DQ6 =132, DQ7 =138
8018 13:08:27.010467 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8019 13:08:27.012978 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
8020 13:08:27.013464
8021 13:08:27.013831
8022 13:08:27.016996
8023 13:08:27.017554 [DramC_TX_OE_Calibration] TA2
8024 13:08:27.019985 Original DQ_B0 (3 6) =30, OEN = 27
8025 13:08:27.022855 Original DQ_B1 (3 6) =30, OEN = 27
8026 13:08:27.026560 24, 0x0, End_B0=24 End_B1=24
8027 13:08:27.029603 25, 0x0, End_B0=25 End_B1=25
8028 13:08:27.033300 26, 0x0, End_B0=26 End_B1=26
8029 13:08:27.033718 27, 0x0, End_B0=27 End_B1=27
8030 13:08:27.036281 28, 0x0, End_B0=28 End_B1=28
8031 13:08:27.039431 29, 0x0, End_B0=29 End_B1=29
8032 13:08:27.042564 30, 0x0, End_B0=30 End_B1=30
8033 13:08:27.046440 31, 0x4141, End_B0=30 End_B1=30
8034 13:08:27.046825 Byte0 end_step=30 best_step=27
8035 13:08:27.049174 Byte1 end_step=30 best_step=27
8036 13:08:27.052622 Byte0 TX OE(2T, 0.5T) = (3, 3)
8037 13:08:27.056233 Byte1 TX OE(2T, 0.5T) = (3, 3)
8038 13:08:27.056612
8039 13:08:27.057017
8040 13:08:27.062962 [DQSOSCAuto] RK0, (LSB)MR18= 0x1615, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
8041 13:08:27.066007 CH0 RK0: MR19=303, MR18=1615
8042 13:08:27.072693 CH0_RK0: MR19=0x303, MR18=0x1615, DQSOSC=398, MR23=63, INC=23, DEC=15
8043 13:08:27.073114
8044 13:08:27.075701 ----->DramcWriteLeveling(PI) begin...
8045 13:08:27.076086 ==
8046 13:08:27.079458 Dram Type= 6, Freq= 0, CH_0, rank 1
8047 13:08:27.086442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 13:08:27.086920 ==
8049 13:08:27.089323 Write leveling (Byte 0): 33 => 33
8050 13:08:27.089706 Write leveling (Byte 1): 28 => 28
8051 13:08:27.092440 DramcWriteLeveling(PI) end<-----
8052 13:08:27.092906
8053 13:08:27.093271 ==
8054 13:08:27.096308 Dram Type= 6, Freq= 0, CH_0, rank 1
8055 13:08:27.102806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8056 13:08:27.103231 ==
8057 13:08:27.105823 [Gating] SW mode calibration
8058 13:08:27.112611 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8059 13:08:27.115683 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8060 13:08:27.122883 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 13:08:27.125977 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 13:08:27.129581 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 13:08:27.132587 1 4 12 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
8064 13:08:27.139554 1 4 16 | B1->B0 | 2929 3434 | 1 1 | (0 0) (1 1)
8065 13:08:27.142597 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8066 13:08:27.145599 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 13:08:27.152544 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 13:08:27.155466 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 13:08:27.159128 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 13:08:27.165776 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8071 13:08:27.169414 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
8072 13:08:27.172341 1 5 16 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
8073 13:08:27.178961 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 0)
8074 13:08:27.182679 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 13:08:27.185552 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 13:08:27.192183 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 13:08:27.195864 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 13:08:27.198849 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8079 13:08:27.205477 1 6 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8080 13:08:27.209062 1 6 16 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8081 13:08:27.212105 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 13:08:27.218798 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 13:08:27.221853 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 13:08:27.225582 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 13:08:27.232106 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 13:08:27.235680 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 13:08:27.238679 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8088 13:08:27.245173 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8089 13:08:27.248487 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8090 13:08:27.252411 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 13:08:27.258650 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 13:08:27.261503 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 13:08:27.264997 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 13:08:27.271839 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 13:08:27.275178 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 13:08:27.278915 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 13:08:27.285336 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 13:08:27.288250 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 13:08:27.292053 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 13:08:27.298708 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 13:08:27.301754 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 13:08:27.305350 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8103 13:08:27.311798 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8104 13:08:27.312296 Total UI for P1: 0, mck2ui 16
8105 13:08:27.314918 best dqsien dly found for B0: ( 1, 9, 8)
8106 13:08:27.321793 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8107 13:08:27.324794 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8108 13:08:27.328183 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8109 13:08:27.331775 Total UI for P1: 0, mck2ui 16
8110 13:08:27.334883 best dqsien dly found for B1: ( 1, 9, 16)
8111 13:08:27.337966 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8112 13:08:27.344428 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8113 13:08:27.344870
8114 13:08:27.348227 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8115 13:08:27.351412 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8116 13:08:27.354802 [Gating] SW calibration Done
8117 13:08:27.355263 ==
8118 13:08:27.357957 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 13:08:27.361339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 13:08:27.361771 ==
8121 13:08:27.362312 RX Vref Scan: 0
8122 13:08:27.364509
8123 13:08:27.364938 RX Vref 0 -> 0, step: 1
8124 13:08:27.365361
8125 13:08:27.368159 RX Delay 0 -> 252, step: 8
8126 13:08:27.371049 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8127 13:08:27.374770 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8128 13:08:27.381606 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8129 13:08:27.385153 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8130 13:08:27.387920 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8131 13:08:27.390852 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8132 13:08:27.394756 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8133 13:08:27.400836 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8134 13:08:27.404670 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8135 13:08:27.407860 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8136 13:08:27.411147 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8137 13:08:27.414537 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8138 13:08:27.420836 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8139 13:08:27.424272 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8140 13:08:27.428033 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8141 13:08:27.431061 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8142 13:08:27.431488 ==
8143 13:08:27.434351 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 13:08:27.441236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 13:08:27.441706 ==
8146 13:08:27.442171 DQS Delay:
8147 13:08:27.444590 DQS0 = 0, DQS1 = 0
8148 13:08:27.445018 DQM Delay:
8149 13:08:27.445439 DQM0 = 128, DQM1 = 122
8150 13:08:27.447632 DQ Delay:
8151 13:08:27.450761 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8152 13:08:27.454185 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8153 13:08:27.457368 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8154 13:08:27.461282 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8155 13:08:27.461755
8156 13:08:27.462063
8157 13:08:27.462396 ==
8158 13:08:27.464287 Dram Type= 6, Freq= 0, CH_0, rank 1
8159 13:08:27.467572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8160 13:08:27.470523 ==
8161 13:08:27.470907
8162 13:08:27.471225
8163 13:08:27.471508 TX Vref Scan disable
8164 13:08:27.474210 == TX Byte 0 ==
8165 13:08:27.477950 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8166 13:08:27.481042 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8167 13:08:27.484101 == TX Byte 1 ==
8168 13:08:27.487462 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8169 13:08:27.490685 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8170 13:08:27.494225 ==
8171 13:08:27.497292 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 13:08:27.500653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 13:08:27.501076 ==
8174 13:08:27.513613
8175 13:08:27.516589 TX Vref early break, caculate TX vref
8176 13:08:27.519490 TX Vref=16, minBit 8, minWin=21, winSum=367
8177 13:08:27.522748 TX Vref=18, minBit 8, minWin=22, winSum=377
8178 13:08:27.526564 TX Vref=20, minBit 8, minWin=22, winSum=382
8179 13:08:27.529730 TX Vref=22, minBit 8, minWin=23, winSum=387
8180 13:08:27.532957 TX Vref=24, minBit 8, minWin=23, winSum=399
8181 13:08:27.539643 TX Vref=26, minBit 0, minWin=25, winSum=409
8182 13:08:27.542973 TX Vref=28, minBit 8, minWin=24, winSum=410
8183 13:08:27.546560 TX Vref=30, minBit 8, minWin=24, winSum=407
8184 13:08:27.549870 TX Vref=32, minBit 8, minWin=22, winSum=393
8185 13:08:27.552819 TX Vref=34, minBit 8, minWin=22, winSum=387
8186 13:08:27.559522 [TxChooseVref] Worse bit 0, Min win 25, Win sum 409, Final Vref 26
8187 13:08:27.560200
8188 13:08:27.562690 Final TX Range 0 Vref 26
8189 13:08:27.563079
8190 13:08:27.563388 ==
8191 13:08:27.566219 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 13:08:27.569371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 13:08:27.569778 ==
8194 13:08:27.570081
8195 13:08:27.570424
8196 13:08:27.572747 TX Vref Scan disable
8197 13:08:27.579318 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8198 13:08:27.579705 == TX Byte 0 ==
8199 13:08:27.583158 u2DelayCellOfst[0]=15 cells (4 PI)
8200 13:08:27.585942 u2DelayCellOfst[1]=18 cells (5 PI)
8201 13:08:27.589180 u2DelayCellOfst[2]=15 cells (4 PI)
8202 13:08:27.592771 u2DelayCellOfst[3]=15 cells (4 PI)
8203 13:08:27.596020 u2DelayCellOfst[4]=11 cells (3 PI)
8204 13:08:27.599471 u2DelayCellOfst[5]=0 cells (0 PI)
8205 13:08:27.602823 u2DelayCellOfst[6]=22 cells (6 PI)
8206 13:08:27.605958 u2DelayCellOfst[7]=22 cells (6 PI)
8207 13:08:27.609956 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8208 13:08:27.612915 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8209 13:08:27.616221 == TX Byte 1 ==
8210 13:08:27.616695 u2DelayCellOfst[8]=0 cells (0 PI)
8211 13:08:27.619447 u2DelayCellOfst[9]=0 cells (0 PI)
8212 13:08:27.622501 u2DelayCellOfst[10]=7 cells (2 PI)
8213 13:08:27.626042 u2DelayCellOfst[11]=7 cells (2 PI)
8214 13:08:27.629010 u2DelayCellOfst[12]=11 cells (3 PI)
8215 13:08:27.632531 u2DelayCellOfst[13]=15 cells (4 PI)
8216 13:08:27.636139 u2DelayCellOfst[14]=15 cells (4 PI)
8217 13:08:27.639303 u2DelayCellOfst[15]=15 cells (4 PI)
8218 13:08:27.643163 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8219 13:08:27.649098 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8220 13:08:27.649500 DramC Write-DBI on
8221 13:08:27.649801 ==
8222 13:08:27.652516 Dram Type= 6, Freq= 0, CH_0, rank 1
8223 13:08:27.656060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8224 13:08:27.658911 ==
8225 13:08:27.659357
8226 13:08:27.659651
8227 13:08:27.660078 TX Vref Scan disable
8228 13:08:27.662784 == TX Byte 0 ==
8229 13:08:27.665971 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8230 13:08:27.669054 == TX Byte 1 ==
8231 13:08:27.672349 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8232 13:08:27.676139 DramC Write-DBI off
8233 13:08:27.676523
8234 13:08:27.676852 [DATLAT]
8235 13:08:27.677129 Freq=1600, CH0 RK1
8236 13:08:27.677419
8237 13:08:27.678972 DATLAT Default: 0xf
8238 13:08:27.679352 0, 0xFFFF, sum = 0
8239 13:08:27.682168 1, 0xFFFF, sum = 0
8240 13:08:27.685979 2, 0xFFFF, sum = 0
8241 13:08:27.686524 3, 0xFFFF, sum = 0
8242 13:08:27.688957 4, 0xFFFF, sum = 0
8243 13:08:27.689345 5, 0xFFFF, sum = 0
8244 13:08:27.692203 6, 0xFFFF, sum = 0
8245 13:08:27.692713 7, 0xFFFF, sum = 0
8246 13:08:27.696170 8, 0xFFFF, sum = 0
8247 13:08:27.696648 9, 0xFFFF, sum = 0
8248 13:08:27.699049 10, 0xFFFF, sum = 0
8249 13:08:27.699442 11, 0xFFFF, sum = 0
8250 13:08:27.702670 12, 0xFFFF, sum = 0
8251 13:08:27.703127 13, 0xCFFF, sum = 0
8252 13:08:27.705862 14, 0x0, sum = 1
8253 13:08:27.706409 15, 0x0, sum = 2
8254 13:08:27.709188 16, 0x0, sum = 3
8255 13:08:27.709646 17, 0x0, sum = 4
8256 13:08:27.712195 best_step = 15
8257 13:08:27.712642
8258 13:08:27.712972 ==
8259 13:08:27.715977 Dram Type= 6, Freq= 0, CH_0, rank 1
8260 13:08:27.718886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8261 13:08:27.719332 ==
8262 13:08:27.722624 RX Vref Scan: 0
8263 13:08:27.723049
8264 13:08:27.723399 RX Vref 0 -> 0, step: 1
8265 13:08:27.723680
8266 13:08:27.725609 RX Delay 3 -> 252, step: 4
8267 13:08:27.728749 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8268 13:08:27.735242 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8269 13:08:27.738817 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8270 13:08:27.741805 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8271 13:08:27.744929 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8272 13:08:27.748060 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8273 13:08:27.755356 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8274 13:08:27.758332 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8275 13:08:27.761412 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8276 13:08:27.765027 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8277 13:08:27.767973 iDelay=191, Bit 10, Center 118 (63 ~ 174) 112
8278 13:08:27.774825 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8279 13:08:27.778499 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8280 13:08:27.781505 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8281 13:08:27.785007 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8282 13:08:27.791082 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8283 13:08:27.791159 ==
8284 13:08:27.794962 Dram Type= 6, Freq= 0, CH_0, rank 1
8285 13:08:27.798063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8286 13:08:27.798181 ==
8287 13:08:27.798239 DQS Delay:
8288 13:08:27.801196 DQS0 = 0, DQS1 = 0
8289 13:08:27.801271 DQM Delay:
8290 13:08:27.804725 DQM0 = 124, DQM1 = 117
8291 13:08:27.804798 DQ Delay:
8292 13:08:27.807770 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8293 13:08:27.811034 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8294 13:08:27.814377 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8295 13:08:27.817935 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8296 13:08:27.818003
8297 13:08:27.818059
8298 13:08:27.821248
8299 13:08:27.821317 [DramC_TX_OE_Calibration] TA2
8300 13:08:27.824298 Original DQ_B0 (3 6) =30, OEN = 27
8301 13:08:27.827972 Original DQ_B1 (3 6) =30, OEN = 27
8302 13:08:27.831000 24, 0x0, End_B0=24 End_B1=24
8303 13:08:27.834812 25, 0x0, End_B0=25 End_B1=25
8304 13:08:27.837603 26, 0x0, End_B0=26 End_B1=26
8305 13:08:27.837679 27, 0x0, End_B0=27 End_B1=27
8306 13:08:27.840637 28, 0x0, End_B0=28 End_B1=28
8307 13:08:27.844255 29, 0x0, End_B0=29 End_B1=29
8308 13:08:27.847462 30, 0x0, End_B0=30 End_B1=30
8309 13:08:27.851195 31, 0x4141, End_B0=30 End_B1=30
8310 13:08:27.851272 Byte0 end_step=30 best_step=27
8311 13:08:27.854256 Byte1 end_step=30 best_step=27
8312 13:08:27.857610 Byte0 TX OE(2T, 0.5T) = (3, 3)
8313 13:08:27.861018 Byte1 TX OE(2T, 0.5T) = (3, 3)
8314 13:08:27.861093
8315 13:08:27.861150
8316 13:08:27.867655 [DQSOSCAuto] RK1, (LSB)MR18= 0x2714, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
8317 13:08:27.870837 CH0 RK1: MR19=303, MR18=2714
8318 13:08:27.877361 CH0_RK1: MR19=0x303, MR18=0x2714, DQSOSC=390, MR23=63, INC=24, DEC=16
8319 13:08:27.881002 [RxdqsGatingPostProcess] freq 1600
8320 13:08:27.887653 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8321 13:08:27.890704 best DQS0 dly(2T, 0.5T) = (1, 1)
8322 13:08:27.890804 best DQS1 dly(2T, 0.5T) = (1, 1)
8323 13:08:27.893701 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8324 13:08:27.897383 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8325 13:08:27.900844 best DQS0 dly(2T, 0.5T) = (1, 1)
8326 13:08:27.903861 best DQS1 dly(2T, 0.5T) = (1, 1)
8327 13:08:27.907563 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8328 13:08:27.910507 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8329 13:08:27.913570 Pre-setting of DQS Precalculation
8330 13:08:27.920314 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8331 13:08:27.920389 ==
8332 13:08:27.923673 Dram Type= 6, Freq= 0, CH_1, rank 0
8333 13:08:27.926945 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8334 13:08:27.927021 ==
8335 13:08:27.933448 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8336 13:08:27.937012 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8337 13:08:27.940488 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8338 13:08:27.946804 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8339 13:08:27.955219 [CA 0] Center 41 (12~71) winsize 60
8340 13:08:27.958934 [CA 1] Center 42 (12~72) winsize 61
8341 13:08:27.961982 [CA 2] Center 38 (9~67) winsize 59
8342 13:08:27.965112 [CA 3] Center 37 (8~66) winsize 59
8343 13:08:27.968416 [CA 4] Center 37 (8~67) winsize 60
8344 13:08:27.971949 [CA 5] Center 36 (7~66) winsize 60
8345 13:08:27.972024
8346 13:08:27.975088 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8347 13:08:27.975163
8348 13:08:27.978688 [CATrainingPosCal] consider 1 rank data
8349 13:08:27.981971 u2DelayCellTimex100 = 258/100 ps
8350 13:08:27.985479 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8351 13:08:27.991653 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8352 13:08:27.995147 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8353 13:08:27.998613 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8354 13:08:28.001504 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8355 13:08:28.005217 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8356 13:08:28.005291
8357 13:08:28.008296 CA PerBit enable=1, Macro0, CA PI delay=36
8358 13:08:28.008370
8359 13:08:28.011877 [CBTSetCACLKResult] CA Dly = 36
8360 13:08:28.014793 CS Dly: 10 (0~41)
8361 13:08:28.017963 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8362 13:08:28.021582 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8363 13:08:28.021658 ==
8364 13:08:28.024857 Dram Type= 6, Freq= 0, CH_1, rank 1
8365 13:08:28.028029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 13:08:28.031483 ==
8367 13:08:28.035236 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8368 13:08:28.038339 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8369 13:08:28.044720 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8370 13:08:28.048356 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8371 13:08:28.058542 [CA 0] Center 42 (13~71) winsize 59
8372 13:08:28.061776 [CA 1] Center 42 (12~72) winsize 61
8373 13:08:28.065031 [CA 2] Center 37 (8~67) winsize 60
8374 13:08:28.068583 [CA 3] Center 36 (7~66) winsize 60
8375 13:08:28.071683 [CA 4] Center 38 (9~68) winsize 60
8376 13:08:28.074700 [CA 5] Center 36 (6~67) winsize 62
8377 13:08:28.074776
8378 13:08:28.078085 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8379 13:08:28.078212
8380 13:08:28.081451 [CATrainingPosCal] consider 2 rank data
8381 13:08:28.084913 u2DelayCellTimex100 = 258/100 ps
8382 13:08:28.088574 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8383 13:08:28.095145 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8384 13:08:28.098127 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8385 13:08:28.101756 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8386 13:08:28.105251 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8387 13:08:28.108299 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8388 13:08:28.108449
8389 13:08:28.112138 CA PerBit enable=1, Macro0, CA PI delay=36
8390 13:08:28.112212
8391 13:08:28.114897 [CBTSetCACLKResult] CA Dly = 36
8392 13:08:28.118335 CS Dly: 11 (0~44)
8393 13:08:28.121782 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8394 13:08:28.124838 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8395 13:08:28.124936
8396 13:08:28.128329 ----->DramcWriteLeveling(PI) begin...
8397 13:08:28.128422 ==
8398 13:08:28.131298 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 13:08:28.134855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 13:08:28.137872 ==
8401 13:08:28.137973 Write leveling (Byte 0): 25 => 25
8402 13:08:28.141669 Write leveling (Byte 1): 27 => 27
8403 13:08:28.144887 DramcWriteLeveling(PI) end<-----
8404 13:08:28.144989
8405 13:08:28.145072 ==
8406 13:08:28.148522 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 13:08:28.154792 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 13:08:28.154887 ==
8409 13:08:28.158216 [Gating] SW mode calibration
8410 13:08:28.164855 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8411 13:08:28.167962 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8412 13:08:28.174410 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 13:08:28.177584 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 13:08:28.181099 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 13:08:28.187519 1 4 12 | B1->B0 | 2323 2322 | 1 1 | (1 1) (0 0)
8416 13:08:28.191095 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8417 13:08:28.194757 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 13:08:28.200544 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 13:08:28.204299 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 13:08:28.207133 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 13:08:28.213937 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 13:08:28.217088 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 13:08:28.220459 1 5 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (0 1)
8424 13:08:28.227228 1 5 16 | B1->B0 | 2626 2727 | 1 0 | (1 0) (1 0)
8425 13:08:28.230637 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 13:08:28.234305 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 13:08:28.240750 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 13:08:28.244074 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 13:08:28.246942 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 13:08:28.253901 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 13:08:28.256876 1 6 12 | B1->B0 | 2e2e 2f2e | 0 1 | (0 0) (0 0)
8432 13:08:28.260369 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 13:08:28.266914 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 13:08:28.270306 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 13:08:28.273722 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 13:08:28.280431 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 13:08:28.283698 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 13:08:28.286885 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 13:08:28.290269 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 13:08:28.296715 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8441 13:08:28.300214 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8442 13:08:28.303570 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 13:08:28.309897 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 13:08:28.313338 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 13:08:28.317079 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 13:08:28.323227 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 13:08:28.326428 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 13:08:28.330225 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 13:08:28.336831 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 13:08:28.340530 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 13:08:28.343158 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 13:08:28.349784 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 13:08:28.352847 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 13:08:28.356319 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 13:08:28.362802 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 13:08:28.366077 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8457 13:08:28.369673 Total UI for P1: 0, mck2ui 16
8458 13:08:28.372836 best dqsien dly found for B0: ( 1, 9, 14)
8459 13:08:28.376463 Total UI for P1: 0, mck2ui 16
8460 13:08:28.379395 best dqsien dly found for B1: ( 1, 9, 14)
8461 13:08:28.382952 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8462 13:08:28.385989 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8463 13:08:28.386052
8464 13:08:28.389825 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8465 13:08:28.392784 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8466 13:08:28.396352 [Gating] SW calibration Done
8467 13:08:28.396412 ==
8468 13:08:28.399849 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 13:08:28.406017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 13:08:28.406139 ==
8471 13:08:28.406213 RX Vref Scan: 0
8472 13:08:28.406268
8473 13:08:28.409554 RX Vref 0 -> 0, step: 1
8474 13:08:28.409629
8475 13:08:28.412768 RX Delay 0 -> 252, step: 8
8476 13:08:28.416204 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8477 13:08:28.419444 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8478 13:08:28.422716 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8479 13:08:28.426305 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8480 13:08:28.432529 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8481 13:08:28.435924 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8482 13:08:28.438947 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8483 13:08:28.442487 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8484 13:08:28.445965 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8485 13:08:28.452341 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8486 13:08:28.456060 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8487 13:08:28.459090 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8488 13:08:28.462188 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8489 13:08:28.469034 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8490 13:08:28.472045 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8491 13:08:28.475640 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8492 13:08:28.475714 ==
8493 13:08:28.478908 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 13:08:28.482081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 13:08:28.482178 ==
8496 13:08:28.485324 DQS Delay:
8497 13:08:28.485398 DQS0 = 0, DQS1 = 0
8498 13:08:28.488869 DQM Delay:
8499 13:08:28.488971 DQM0 = 132, DQM1 = 126
8500 13:08:28.489056 DQ Delay:
8501 13:08:28.492408 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8502 13:08:28.498661 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8503 13:08:28.502386 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =119
8504 13:08:28.505149 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8505 13:08:28.505215
8506 13:08:28.505285
8507 13:08:28.505337 ==
8508 13:08:28.508370 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 13:08:28.511848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 13:08:28.511936 ==
8511 13:08:28.512025
8512 13:08:28.512103
8513 13:08:28.515567 TX Vref Scan disable
8514 13:08:28.518531 == TX Byte 0 ==
8515 13:08:28.521898 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8516 13:08:28.525155 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8517 13:08:28.528419 == TX Byte 1 ==
8518 13:08:28.531932 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8519 13:08:28.535134 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8520 13:08:28.535205 ==
8521 13:08:28.538106 Dram Type= 6, Freq= 0, CH_1, rank 0
8522 13:08:28.541809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8523 13:08:28.544686 ==
8524 13:08:28.557522
8525 13:08:28.560392 TX Vref early break, caculate TX vref
8526 13:08:28.563993 TX Vref=16, minBit 11, minWin=21, winSum=366
8527 13:08:28.567057 TX Vref=18, minBit 10, minWin=22, winSum=378
8528 13:08:28.570738 TX Vref=20, minBit 5, minWin=23, winSum=389
8529 13:08:28.573500 TX Vref=22, minBit 11, minWin=23, winSum=397
8530 13:08:28.576925 TX Vref=24, minBit 8, minWin=24, winSum=405
8531 13:08:28.583741 TX Vref=26, minBit 5, minWin=25, winSum=417
8532 13:08:28.587143 TX Vref=28, minBit 1, minWin=25, winSum=419
8533 13:08:28.590817 TX Vref=30, minBit 1, minWin=25, winSum=420
8534 13:08:28.593973 TX Vref=32, minBit 0, minWin=24, winSum=407
8535 13:08:28.597197 TX Vref=34, minBit 1, minWin=23, winSum=403
8536 13:08:28.600490 TX Vref=36, minBit 0, minWin=23, winSum=387
8537 13:08:28.607263 [TxChooseVref] Worse bit 1, Min win 25, Win sum 420, Final Vref 30
8538 13:08:28.607342
8539 13:08:28.610428 Final TX Range 0 Vref 30
8540 13:08:28.610503
8541 13:08:28.610561 ==
8542 13:08:28.613487 Dram Type= 6, Freq= 0, CH_1, rank 0
8543 13:08:28.617241 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8544 13:08:28.617318 ==
8545 13:08:28.617376
8546 13:08:28.620282
8547 13:08:28.620356 TX Vref Scan disable
8548 13:08:28.627248 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8549 13:08:28.627325 == TX Byte 0 ==
8550 13:08:28.630389 u2DelayCellOfst[0]=22 cells (6 PI)
8551 13:08:28.633763 u2DelayCellOfst[1]=11 cells (3 PI)
8552 13:08:28.636615 u2DelayCellOfst[2]=0 cells (0 PI)
8553 13:08:28.640229 u2DelayCellOfst[3]=7 cells (2 PI)
8554 13:08:28.643166 u2DelayCellOfst[4]=7 cells (2 PI)
8555 13:08:28.646556 u2DelayCellOfst[5]=22 cells (6 PI)
8556 13:08:28.650251 u2DelayCellOfst[6]=22 cells (6 PI)
8557 13:08:28.653508 u2DelayCellOfst[7]=7 cells (2 PI)
8558 13:08:28.656339 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8559 13:08:28.659643 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8560 13:08:28.663291 == TX Byte 1 ==
8561 13:08:28.666609 u2DelayCellOfst[8]=0 cells (0 PI)
8562 13:08:28.669787 u2DelayCellOfst[9]=7 cells (2 PI)
8563 13:08:28.673434 u2DelayCellOfst[10]=15 cells (4 PI)
8564 13:08:28.676516 u2DelayCellOfst[11]=11 cells (3 PI)
8565 13:08:28.676611 u2DelayCellOfst[12]=18 cells (5 PI)
8566 13:08:28.679516 u2DelayCellOfst[13]=22 cells (6 PI)
8567 13:08:28.683276 u2DelayCellOfst[14]=22 cells (6 PI)
8568 13:08:28.686187 u2DelayCellOfst[15]=22 cells (6 PI)
8569 13:08:28.692887 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8570 13:08:28.696411 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8571 13:08:28.696505 DramC Write-DBI on
8572 13:08:28.699693 ==
8573 13:08:28.702926 Dram Type= 6, Freq= 0, CH_1, rank 0
8574 13:08:28.706501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8575 13:08:28.706570 ==
8576 13:08:28.706627
8577 13:08:28.706680
8578 13:08:28.709380 TX Vref Scan disable
8579 13:08:28.709447 == TX Byte 0 ==
8580 13:08:28.716137 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8581 13:08:28.716203 == TX Byte 1 ==
8582 13:08:28.719210 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8583 13:08:28.722855 DramC Write-DBI off
8584 13:08:28.722920
8585 13:08:28.722973 [DATLAT]
8586 13:08:28.725918 Freq=1600, CH1 RK0
8587 13:08:28.725982
8588 13:08:28.726062 DATLAT Default: 0xf
8589 13:08:28.729655 0, 0xFFFF, sum = 0
8590 13:08:28.729723 1, 0xFFFF, sum = 0
8591 13:08:28.732594 2, 0xFFFF, sum = 0
8592 13:08:28.732658 3, 0xFFFF, sum = 0
8593 13:08:28.735481 4, 0xFFFF, sum = 0
8594 13:08:28.735558 5, 0xFFFF, sum = 0
8595 13:08:28.739425 6, 0xFFFF, sum = 0
8596 13:08:28.742459 7, 0xFFFF, sum = 0
8597 13:08:28.742560 8, 0xFFFF, sum = 0
8598 13:08:28.746220 9, 0xFFFF, sum = 0
8599 13:08:28.746296 10, 0xFFFF, sum = 0
8600 13:08:28.749145 11, 0xFFFF, sum = 0
8601 13:08:28.749221 12, 0xFFFF, sum = 0
8602 13:08:28.752552 13, 0x8FFF, sum = 0
8603 13:08:28.752653 14, 0x0, sum = 1
8604 13:08:28.756197 15, 0x0, sum = 2
8605 13:08:28.756291 16, 0x0, sum = 3
8606 13:08:28.759181 17, 0x0, sum = 4
8607 13:08:28.759270 best_step = 15
8608 13:08:28.759351
8609 13:08:28.759432 ==
8610 13:08:28.762315 Dram Type= 6, Freq= 0, CH_1, rank 0
8611 13:08:28.765701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8612 13:08:28.765781 ==
8613 13:08:28.769353 RX Vref Scan: 1
8614 13:08:28.769428
8615 13:08:28.772371 Set Vref Range= 24 -> 127
8616 13:08:28.772446
8617 13:08:28.772503 RX Vref 24 -> 127, step: 1
8618 13:08:28.775615
8619 13:08:28.775716 RX Delay 11 -> 252, step: 4
8620 13:08:28.775801
8621 13:08:28.778888 Set Vref, RX VrefLevel [Byte0]: 24
8622 13:08:28.782298 [Byte1]: 24
8623 13:08:28.785766
8624 13:08:28.785864 Set Vref, RX VrefLevel [Byte0]: 25
8625 13:08:28.789366 [Byte1]: 25
8626 13:08:28.793462
8627 13:08:28.793537 Set Vref, RX VrefLevel [Byte0]: 26
8628 13:08:28.796676 [Byte1]: 26
8629 13:08:28.800933
8630 13:08:28.801032 Set Vref, RX VrefLevel [Byte0]: 27
8631 13:08:28.804163 [Byte1]: 27
8632 13:08:28.808793
8633 13:08:28.808867 Set Vref, RX VrefLevel [Byte0]: 28
8634 13:08:28.812014 [Byte1]: 28
8635 13:08:28.816578
8636 13:08:28.816648 Set Vref, RX VrefLevel [Byte0]: 29
8637 13:08:28.819672 [Byte1]: 29
8638 13:08:28.823869
8639 13:08:28.823935 Set Vref, RX VrefLevel [Byte0]: 30
8640 13:08:28.826946 [Byte1]: 30
8641 13:08:28.831645
8642 13:08:28.831712 Set Vref, RX VrefLevel [Byte0]: 31
8643 13:08:28.834667 [Byte1]: 31
8644 13:08:28.838815
8645 13:08:28.838890 Set Vref, RX VrefLevel [Byte0]: 32
8646 13:08:28.842493 [Byte1]: 32
8647 13:08:28.846617
8648 13:08:28.846695 Set Vref, RX VrefLevel [Byte0]: 33
8649 13:08:28.849875 [Byte1]: 33
8650 13:08:28.854530
8651 13:08:28.854628 Set Vref, RX VrefLevel [Byte0]: 34
8652 13:08:28.857898 [Byte1]: 34
8653 13:08:28.862193
8654 13:08:28.862272 Set Vref, RX VrefLevel [Byte0]: 35
8655 13:08:28.865377 [Byte1]: 35
8656 13:08:28.869469
8657 13:08:28.869544 Set Vref, RX VrefLevel [Byte0]: 36
8658 13:08:28.872949 [Byte1]: 36
8659 13:08:28.877038
8660 13:08:28.877113 Set Vref, RX VrefLevel [Byte0]: 37
8661 13:08:28.880784 [Byte1]: 37
8662 13:08:28.884993
8663 13:08:28.885067 Set Vref, RX VrefLevel [Byte0]: 38
8664 13:08:28.888088 [Byte1]: 38
8665 13:08:28.892779
8666 13:08:28.892878 Set Vref, RX VrefLevel [Byte0]: 39
8667 13:08:28.895970 [Byte1]: 39
8668 13:08:28.899745
8669 13:08:28.899820 Set Vref, RX VrefLevel [Byte0]: 40
8670 13:08:28.903372 [Byte1]: 40
8671 13:08:28.907793
8672 13:08:28.907868 Set Vref, RX VrefLevel [Byte0]: 41
8673 13:08:28.911092 [Byte1]: 41
8674 13:08:28.915155
8675 13:08:28.915230 Set Vref, RX VrefLevel [Byte0]: 42
8676 13:08:28.918470 [Byte1]: 42
8677 13:08:28.922583
8678 13:08:28.922659 Set Vref, RX VrefLevel [Byte0]: 43
8679 13:08:28.926137 [Byte1]: 43
8680 13:08:28.930405
8681 13:08:28.930482 Set Vref, RX VrefLevel [Byte0]: 44
8682 13:08:28.933714 [Byte1]: 44
8683 13:08:28.938003
8684 13:08:28.938109 Set Vref, RX VrefLevel [Byte0]: 45
8685 13:08:28.941698 [Byte1]: 45
8686 13:08:28.945722
8687 13:08:28.945792 Set Vref, RX VrefLevel [Byte0]: 46
8688 13:08:28.948783 [Byte1]: 46
8689 13:08:28.953098
8690 13:08:28.953197 Set Vref, RX VrefLevel [Byte0]: 47
8691 13:08:28.956621 [Byte1]: 47
8692 13:08:28.960876
8693 13:08:28.960974 Set Vref, RX VrefLevel [Byte0]: 48
8694 13:08:28.964299 [Byte1]: 48
8695 13:08:28.968611
8696 13:08:28.968707 Set Vref, RX VrefLevel [Byte0]: 49
8697 13:08:28.971745 [Byte1]: 49
8698 13:08:28.976457
8699 13:08:28.976552 Set Vref, RX VrefLevel [Byte0]: 50
8700 13:08:28.979633 [Byte1]: 50
8701 13:08:28.983829
8702 13:08:28.983920 Set Vref, RX VrefLevel [Byte0]: 51
8703 13:08:28.987251 [Byte1]: 51
8704 13:08:28.991262
8705 13:08:28.991353 Set Vref, RX VrefLevel [Byte0]: 52
8706 13:08:28.995073 [Byte1]: 52
8707 13:08:28.999059
8708 13:08:28.999131 Set Vref, RX VrefLevel [Byte0]: 53
8709 13:08:29.002312 [Byte1]: 53
8710 13:08:29.006920
8711 13:08:29.006988 Set Vref, RX VrefLevel [Byte0]: 54
8712 13:08:29.009892 [Byte1]: 54
8713 13:08:29.014461
8714 13:08:29.014539 Set Vref, RX VrefLevel [Byte0]: 55
8715 13:08:29.017479 [Byte1]: 55
8716 13:08:29.021948
8717 13:08:29.022039 Set Vref, RX VrefLevel [Byte0]: 56
8718 13:08:29.025311 [Byte1]: 56
8719 13:08:29.029238
8720 13:08:29.029340 Set Vref, RX VrefLevel [Byte0]: 57
8721 13:08:29.032740 [Byte1]: 57
8722 13:08:29.036838
8723 13:08:29.036930 Set Vref, RX VrefLevel [Byte0]: 58
8724 13:08:29.040394 [Byte1]: 58
8725 13:08:29.044770
8726 13:08:29.044842 Set Vref, RX VrefLevel [Byte0]: 59
8727 13:08:29.048186 [Byte1]: 59
8728 13:08:29.052629
8729 13:08:29.052695 Set Vref, RX VrefLevel [Byte0]: 60
8730 13:08:29.055731 [Byte1]: 60
8731 13:08:29.059860
8732 13:08:29.059926 Set Vref, RX VrefLevel [Byte0]: 61
8733 13:08:29.062948 [Byte1]: 61
8734 13:08:29.067302
8735 13:08:29.067398 Set Vref, RX VrefLevel [Byte0]: 62
8736 13:08:29.071042 [Byte1]: 62
8737 13:08:29.074889
8738 13:08:29.074982 Set Vref, RX VrefLevel [Byte0]: 63
8739 13:08:29.078584 [Byte1]: 63
8740 13:08:29.082715
8741 13:08:29.082804 Set Vref, RX VrefLevel [Byte0]: 64
8742 13:08:29.086039 [Byte1]: 64
8743 13:08:29.090275
8744 13:08:29.090379 Set Vref, RX VrefLevel [Byte0]: 65
8745 13:08:29.093496 [Byte1]: 65
8746 13:08:29.098027
8747 13:08:29.098122 Set Vref, RX VrefLevel [Byte0]: 66
8748 13:08:29.100998 [Byte1]: 66
8749 13:08:29.105529
8750 13:08:29.105622 Set Vref, RX VrefLevel [Byte0]: 67
8751 13:08:29.108745 [Byte1]: 67
8752 13:08:29.112832
8753 13:08:29.112924 Set Vref, RX VrefLevel [Byte0]: 68
8754 13:08:29.116946 [Byte1]: 68
8755 13:08:29.120811
8756 13:08:29.120887 Set Vref, RX VrefLevel [Byte0]: 69
8757 13:08:29.123860 [Byte1]: 69
8758 13:08:29.128595
8759 13:08:29.128670 Final RX Vref Byte 0 = 57 to rank0
8760 13:08:29.131398 Final RX Vref Byte 1 = 57 to rank0
8761 13:08:29.134802 Final RX Vref Byte 0 = 57 to rank1
8762 13:08:29.138444 Final RX Vref Byte 1 = 57 to rank1==
8763 13:08:29.141609 Dram Type= 6, Freq= 0, CH_1, rank 0
8764 13:08:29.148219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8765 13:08:29.148296 ==
8766 13:08:29.148354 DQS Delay:
8767 13:08:29.148406 DQS0 = 0, DQS1 = 0
8768 13:08:29.151431 DQM Delay:
8769 13:08:29.151506 DQM0 = 131, DQM1 = 122
8770 13:08:29.154697 DQ Delay:
8771 13:08:29.158441 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =126
8772 13:08:29.161467 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8773 13:08:29.165091 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8774 13:08:29.168261 DQ12 =132, DQ13 =130, DQ14 =130, DQ15 =130
8775 13:08:29.168334
8776 13:08:29.168391
8777 13:08:29.168443
8778 13:08:29.171377 [DramC_TX_OE_Calibration] TA2
8779 13:08:29.175012 Original DQ_B0 (3 6) =30, OEN = 27
8780 13:08:29.178039 Original DQ_B1 (3 6) =30, OEN = 27
8781 13:08:29.181769 24, 0x0, End_B0=24 End_B1=24
8782 13:08:29.181844 25, 0x0, End_B0=25 End_B1=25
8783 13:08:29.184621 26, 0x0, End_B0=26 End_B1=26
8784 13:08:29.188316 27, 0x0, End_B0=27 End_B1=27
8785 13:08:29.190944 28, 0x0, End_B0=28 End_B1=28
8786 13:08:29.194708 29, 0x0, End_B0=29 End_B1=29
8787 13:08:29.194783 30, 0x0, End_B0=30 End_B1=30
8788 13:08:29.197657 31, 0x4141, End_B0=30 End_B1=30
8789 13:08:29.201545 Byte0 end_step=30 best_step=27
8790 13:08:29.204546 Byte1 end_step=30 best_step=27
8791 13:08:29.207621 Byte0 TX OE(2T, 0.5T) = (3, 3)
8792 13:08:29.210742 Byte1 TX OE(2T, 0.5T) = (3, 3)
8793 13:08:29.210815
8794 13:08:29.210872
8795 13:08:29.217661 [DQSOSCAuto] RK0, (LSB)MR18= 0xb10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
8796 13:08:29.220907 CH1 RK0: MR19=303, MR18=B10
8797 13:08:29.227415 CH1_RK0: MR19=0x303, MR18=0xB10, DQSOSC=401, MR23=63, INC=22, DEC=15
8798 13:08:29.227490
8799 13:08:29.230735 ----->DramcWriteLeveling(PI) begin...
8800 13:08:29.230811 ==
8801 13:08:29.234251 Dram Type= 6, Freq= 0, CH_1, rank 1
8802 13:08:29.237786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8803 13:08:29.237861 ==
8804 13:08:29.240785 Write leveling (Byte 0): 24 => 24
8805 13:08:29.243844 Write leveling (Byte 1): 27 => 27
8806 13:08:29.247399 DramcWriteLeveling(PI) end<-----
8807 13:08:29.247468
8808 13:08:29.247524 ==
8809 13:08:29.250576 Dram Type= 6, Freq= 0, CH_1, rank 1
8810 13:08:29.254027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8811 13:08:29.254155 ==
8812 13:08:29.257429 [Gating] SW mode calibration
8813 13:08:29.264340 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8814 13:08:29.270974 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8815 13:08:29.273891 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 13:08:29.280729 1 4 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
8817 13:08:29.283589 1 4 8 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
8818 13:08:29.287363 1 4 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
8819 13:08:29.293982 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8820 13:08:29.296835 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8821 13:08:29.300198 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8822 13:08:29.303711 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8823 13:08:29.310293 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8824 13:08:29.313515 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8825 13:08:29.317172 1 5 8 | B1->B0 | 3434 2a2a | 0 0 | (0 1) (0 1)
8826 13:08:29.323743 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8827 13:08:29.326606 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 13:08:29.330068 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 13:08:29.336593 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 13:08:29.339918 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 13:08:29.343224 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8832 13:08:29.349766 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8833 13:08:29.353260 1 6 8 | B1->B0 | 2929 4343 | 0 1 | (0 0) (0 0)
8834 13:08:29.357029 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8835 13:08:29.363235 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 13:08:29.366389 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 13:08:29.370305 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8838 13:08:29.376453 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 13:08:29.379472 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8840 13:08:29.383202 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 13:08:29.389906 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8842 13:08:29.392725 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8843 13:08:29.396639 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 13:08:29.402784 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 13:08:29.406091 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 13:08:29.409530 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 13:08:29.415742 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 13:08:29.419511 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 13:08:29.422546 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 13:08:29.429155 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 13:08:29.432799 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 13:08:29.435852 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 13:08:29.442066 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 13:08:29.445850 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 13:08:29.448824 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 13:08:29.455550 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 13:08:29.458854 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8858 13:08:29.462050 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8859 13:08:29.465545 Total UI for P1: 0, mck2ui 16
8860 13:08:29.468745 best dqsien dly found for B0: ( 1, 9, 8)
8861 13:08:29.475322 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8862 13:08:29.475390 Total UI for P1: 0, mck2ui 16
8863 13:08:29.481883 best dqsien dly found for B1: ( 1, 9, 12)
8864 13:08:29.485758 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8865 13:08:29.488713 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8866 13:08:29.488776
8867 13:08:29.492243 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8868 13:08:29.495381 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8869 13:08:29.498790 [Gating] SW calibration Done
8870 13:08:29.498851 ==
8871 13:08:29.501807 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 13:08:29.505314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 13:08:29.505375 ==
8874 13:08:29.508387 RX Vref Scan: 0
8875 13:08:29.508472
8876 13:08:29.508552 RX Vref 0 -> 0, step: 1
8877 13:08:29.511863
8878 13:08:29.511923 RX Delay 0 -> 252, step: 8
8879 13:08:29.515262 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8880 13:08:29.521579 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8881 13:08:29.525137 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8882 13:08:29.528642 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8883 13:08:29.531666 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8884 13:08:29.534679 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8885 13:08:29.541633 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8886 13:08:29.545308 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8887 13:08:29.548117 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8888 13:08:29.551371 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8889 13:08:29.554621 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8890 13:08:29.561704 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8891 13:08:29.564770 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8892 13:08:29.568324 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8893 13:08:29.571917 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8894 13:08:29.578087 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8895 13:08:29.578192 ==
8896 13:08:29.581859 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 13:08:29.585401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 13:08:29.585464 ==
8899 13:08:29.585517 DQS Delay:
8900 13:08:29.588594 DQS0 = 0, DQS1 = 0
8901 13:08:29.588655 DQM Delay:
8902 13:08:29.591686 DQM0 = 129, DQM1 = 128
8903 13:08:29.591747 DQ Delay:
8904 13:08:29.594682 DQ0 =135, DQ1 =127, DQ2 =115, DQ3 =127
8905 13:08:29.598616 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8906 13:08:29.601364 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8907 13:08:29.605044 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8908 13:08:29.605105
8909 13:08:29.605155
8910 13:08:29.605205 ==
8911 13:08:29.608274 Dram Type= 6, Freq= 0, CH_1, rank 1
8912 13:08:29.614864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8913 13:08:29.614928 ==
8914 13:08:29.614981
8915 13:08:29.615031
8916 13:08:29.618598 TX Vref Scan disable
8917 13:08:29.618658 == TX Byte 0 ==
8918 13:08:29.621462 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8919 13:08:29.628568 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8920 13:08:29.628669 == TX Byte 1 ==
8921 13:08:29.631571 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8922 13:08:29.638221 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8923 13:08:29.638289 ==
8924 13:08:29.641500 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 13:08:29.644513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 13:08:29.644600 ==
8927 13:08:29.657320
8928 13:08:29.660678 TX Vref early break, caculate TX vref
8929 13:08:29.664240 TX Vref=16, minBit 0, minWin=23, winSum=386
8930 13:08:29.667621 TX Vref=18, minBit 0, minWin=23, winSum=397
8931 13:08:29.670760 TX Vref=20, minBit 5, minWin=24, winSum=408
8932 13:08:29.673856 TX Vref=22, minBit 0, minWin=25, winSum=412
8933 13:08:29.677395 TX Vref=24, minBit 0, minWin=25, winSum=422
8934 13:08:29.683833 TX Vref=26, minBit 0, minWin=25, winSum=429
8935 13:08:29.687206 TX Vref=28, minBit 0, minWin=25, winSum=426
8936 13:08:29.690478 TX Vref=30, minBit 1, minWin=24, winSum=420
8937 13:08:29.694088 TX Vref=32, minBit 1, minWin=25, winSum=418
8938 13:08:29.697621 TX Vref=34, minBit 5, minWin=24, winSum=405
8939 13:08:29.703640 [TxChooseVref] Worse bit 0, Min win 25, Win sum 429, Final Vref 26
8940 13:08:29.703706
8941 13:08:29.707080 Final TX Range 0 Vref 26
8942 13:08:29.707142
8943 13:08:29.707194 ==
8944 13:08:29.710929 Dram Type= 6, Freq= 0, CH_1, rank 1
8945 13:08:29.713809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8946 13:08:29.713894 ==
8947 13:08:29.713971
8948 13:08:29.714047
8949 13:08:29.717267 TX Vref Scan disable
8950 13:08:29.723801 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8951 13:08:29.723877 == TX Byte 0 ==
8952 13:08:29.727256 u2DelayCellOfst[0]=18 cells (5 PI)
8953 13:08:29.730685 u2DelayCellOfst[1]=11 cells (3 PI)
8954 13:08:29.733841 u2DelayCellOfst[2]=0 cells (0 PI)
8955 13:08:29.737253 u2DelayCellOfst[3]=7 cells (2 PI)
8956 13:08:29.740435 u2DelayCellOfst[4]=7 cells (2 PI)
8957 13:08:29.744112 u2DelayCellOfst[5]=18 cells (5 PI)
8958 13:08:29.747108 u2DelayCellOfst[6]=18 cells (5 PI)
8959 13:08:29.747183 u2DelayCellOfst[7]=3 cells (1 PI)
8960 13:08:29.753689 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8961 13:08:29.757291 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8962 13:08:29.757366 == TX Byte 1 ==
8963 13:08:29.760459 u2DelayCellOfst[8]=0 cells (0 PI)
8964 13:08:29.763471 u2DelayCellOfst[9]=7 cells (2 PI)
8965 13:08:29.767218 u2DelayCellOfst[10]=11 cells (3 PI)
8966 13:08:29.769999 u2DelayCellOfst[11]=7 cells (2 PI)
8967 13:08:29.773496 u2DelayCellOfst[12]=15 cells (4 PI)
8968 13:08:29.777324 u2DelayCellOfst[13]=18 cells (5 PI)
8969 13:08:29.780281 u2DelayCellOfst[14]=22 cells (6 PI)
8970 13:08:29.784130 u2DelayCellOfst[15]=18 cells (5 PI)
8971 13:08:29.786791 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8972 13:08:29.793576 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8973 13:08:29.793651 DramC Write-DBI on
8974 13:08:29.793708 ==
8975 13:08:29.796885 Dram Type= 6, Freq= 0, CH_1, rank 1
8976 13:08:29.800384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8977 13:08:29.803301 ==
8978 13:08:29.803375
8979 13:08:29.803432
8980 13:08:29.803487 TX Vref Scan disable
8981 13:08:29.806796 == TX Byte 0 ==
8982 13:08:29.809961 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8983 13:08:29.813185 == TX Byte 1 ==
8984 13:08:29.816732 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8985 13:08:29.820495 DramC Write-DBI off
8986 13:08:29.820569
8987 13:08:29.820627 [DATLAT]
8988 13:08:29.820680 Freq=1600, CH1 RK1
8989 13:08:29.820731
8990 13:08:29.823427 DATLAT Default: 0xf
8991 13:08:29.823502 0, 0xFFFF, sum = 0
8992 13:08:29.826965 1, 0xFFFF, sum = 0
8993 13:08:29.827056 2, 0xFFFF, sum = 0
8994 13:08:29.829988 3, 0xFFFF, sum = 0
8995 13:08:29.833680 4, 0xFFFF, sum = 0
8996 13:08:29.833757 5, 0xFFFF, sum = 0
8997 13:08:29.836568 6, 0xFFFF, sum = 0
8998 13:08:29.836645 7, 0xFFFF, sum = 0
8999 13:08:29.840332 8, 0xFFFF, sum = 0
9000 13:08:29.840408 9, 0xFFFF, sum = 0
9001 13:08:29.843512 10, 0xFFFF, sum = 0
9002 13:08:29.843588 11, 0xFFFF, sum = 0
9003 13:08:29.846661 12, 0xFFFF, sum = 0
9004 13:08:29.846741 13, 0x8FFF, sum = 0
9005 13:08:29.849620 14, 0x0, sum = 1
9006 13:08:29.849714 15, 0x0, sum = 2
9007 13:08:29.853019 16, 0x0, sum = 3
9008 13:08:29.853083 17, 0x0, sum = 4
9009 13:08:29.856404 best_step = 15
9010 13:08:29.856465
9011 13:08:29.856517 ==
9012 13:08:29.859570 Dram Type= 6, Freq= 0, CH_1, rank 1
9013 13:08:29.863367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9014 13:08:29.863443 ==
9015 13:08:29.866562 RX Vref Scan: 0
9016 13:08:29.866636
9017 13:08:29.866694 RX Vref 0 -> 0, step: 1
9018 13:08:29.866749
9019 13:08:29.870053 RX Delay 3 -> 252, step: 4
9020 13:08:29.873098 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
9021 13:08:29.879574 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9022 13:08:29.883049 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
9023 13:08:29.885948 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
9024 13:08:29.889385 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
9025 13:08:29.892857 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9026 13:08:29.899200 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9027 13:08:29.902961 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
9028 13:08:29.906151 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9029 13:08:29.909424 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9030 13:08:29.912838 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9031 13:08:29.919495 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9032 13:08:29.922605 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9033 13:08:29.925866 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9034 13:08:29.929225 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9035 13:08:29.936349 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9036 13:08:29.936424 ==
9037 13:08:29.939040 Dram Type= 6, Freq= 0, CH_1, rank 1
9038 13:08:29.942499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9039 13:08:29.942574 ==
9040 13:08:29.942631 DQS Delay:
9041 13:08:29.945672 DQS0 = 0, DQS1 = 0
9042 13:08:29.945746 DQM Delay:
9043 13:08:29.949333 DQM0 = 127, DQM1 = 125
9044 13:08:29.949407 DQ Delay:
9045 13:08:29.952721 DQ0 =132, DQ1 =126, DQ2 =114, DQ3 =126
9046 13:08:29.956104 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
9047 13:08:29.959426 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120
9048 13:08:29.962464 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =134
9049 13:08:29.962539
9050 13:08:29.962595
9051 13:08:29.965775
9052 13:08:29.965848 [DramC_TX_OE_Calibration] TA2
9053 13:08:29.969340 Original DQ_B0 (3 6) =30, OEN = 27
9054 13:08:29.972307 Original DQ_B1 (3 6) =30, OEN = 27
9055 13:08:29.976254 24, 0x0, End_B0=24 End_B1=24
9056 13:08:29.979391 25, 0x0, End_B0=25 End_B1=25
9057 13:08:29.982621 26, 0x0, End_B0=26 End_B1=26
9058 13:08:29.982697 27, 0x0, End_B0=27 End_B1=27
9059 13:08:29.985740 28, 0x0, End_B0=28 End_B1=28
9060 13:08:29.989404 29, 0x0, End_B0=29 End_B1=29
9061 13:08:29.992428 30, 0x0, End_B0=30 End_B1=30
9062 13:08:29.992503 31, 0x4141, End_B0=30 End_B1=30
9063 13:08:29.995721 Byte0 end_step=30 best_step=27
9064 13:08:29.999243 Byte1 end_step=30 best_step=27
9065 13:08:30.002272 Byte0 TX OE(2T, 0.5T) = (3, 3)
9066 13:08:30.005721 Byte1 TX OE(2T, 0.5T) = (3, 3)
9067 13:08:30.005796
9068 13:08:30.005852
9069 13:08:30.012496 [DQSOSCAuto] RK1, (LSB)MR18= 0x1420, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
9070 13:08:30.015786 CH1 RK1: MR19=303, MR18=1420
9071 13:08:30.022410 CH1_RK1: MR19=0x303, MR18=0x1420, DQSOSC=393, MR23=63, INC=23, DEC=15
9072 13:08:30.025613 [RxdqsGatingPostProcess] freq 1600
9073 13:08:30.032470 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9074 13:08:30.035790 best DQS0 dly(2T, 0.5T) = (1, 1)
9075 13:08:30.035865 best DQS1 dly(2T, 0.5T) = (1, 1)
9076 13:08:30.038642 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9077 13:08:30.042175 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9078 13:08:30.045428 best DQS0 dly(2T, 0.5T) = (1, 1)
9079 13:08:30.048712 best DQS1 dly(2T, 0.5T) = (1, 1)
9080 13:08:30.052558 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9081 13:08:30.055211 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9082 13:08:30.059006 Pre-setting of DQS Precalculation
9083 13:08:30.062159 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9084 13:08:30.072392 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9085 13:08:30.078689 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9086 13:08:30.078769
9087 13:08:30.078828
9088 13:08:30.081796 [Calibration Summary] 3200 Mbps
9089 13:08:30.081870 CH 0, Rank 0
9090 13:08:30.085253 SW Impedance : PASS
9091 13:08:30.085327 DUTY Scan : NO K
9092 13:08:30.088877 ZQ Calibration : PASS
9093 13:08:30.091878 Jitter Meter : NO K
9094 13:08:30.091952 CBT Training : PASS
9095 13:08:30.095483 Write leveling : PASS
9096 13:08:30.098484 RX DQS gating : PASS
9097 13:08:30.098559 RX DQ/DQS(RDDQC) : PASS
9098 13:08:30.102094 TX DQ/DQS : PASS
9099 13:08:30.104981 RX DATLAT : PASS
9100 13:08:30.105055 RX DQ/DQS(Engine): PASS
9101 13:08:30.108535 TX OE : PASS
9102 13:08:30.108609 All Pass.
9103 13:08:30.108667
9104 13:08:30.112050 CH 0, Rank 1
9105 13:08:30.112124 SW Impedance : PASS
9106 13:08:30.114966 DUTY Scan : NO K
9107 13:08:30.118634 ZQ Calibration : PASS
9108 13:08:30.118709 Jitter Meter : NO K
9109 13:08:30.121612 CBT Training : PASS
9110 13:08:30.124802 Write leveling : PASS
9111 13:08:30.124876 RX DQS gating : PASS
9112 13:08:30.128203 RX DQ/DQS(RDDQC) : PASS
9113 13:08:30.128277 TX DQ/DQS : PASS
9114 13:08:30.131900 RX DATLAT : PASS
9115 13:08:30.134844 RX DQ/DQS(Engine): PASS
9116 13:08:30.134919 TX OE : PASS
9117 13:08:30.138609 All Pass.
9118 13:08:30.138683
9119 13:08:30.138740 CH 1, Rank 0
9120 13:08:30.142195 SW Impedance : PASS
9121 13:08:30.142294 DUTY Scan : NO K
9122 13:08:30.145166 ZQ Calibration : PASS
9123 13:08:30.148032 Jitter Meter : NO K
9124 13:08:30.148119 CBT Training : PASS
9125 13:08:30.151609 Write leveling : PASS
9126 13:08:30.154744 RX DQS gating : PASS
9127 13:08:30.154817 RX DQ/DQS(RDDQC) : PASS
9128 13:08:30.158943 TX DQ/DQS : PASS
9129 13:08:30.161390 RX DATLAT : PASS
9130 13:08:30.161465 RX DQ/DQS(Engine): PASS
9131 13:08:30.165161 TX OE : PASS
9132 13:08:30.165235 All Pass.
9133 13:08:30.165292
9134 13:08:30.168040 CH 1, Rank 1
9135 13:08:30.168138 SW Impedance : PASS
9136 13:08:30.171470 DUTY Scan : NO K
9137 13:08:30.174978 ZQ Calibration : PASS
9138 13:08:30.175052 Jitter Meter : NO K
9139 13:08:30.177951 CBT Training : PASS
9140 13:08:30.181095 Write leveling : PASS
9141 13:08:30.181169 RX DQS gating : PASS
9142 13:08:30.184669 RX DQ/DQS(RDDQC) : PASS
9143 13:08:30.187655 TX DQ/DQS : PASS
9144 13:08:30.187729 RX DATLAT : PASS
9145 13:08:30.191096 RX DQ/DQS(Engine): PASS
9146 13:08:30.191171 TX OE : PASS
9147 13:08:30.194642 All Pass.
9148 13:08:30.194716
9149 13:08:30.194773 DramC Write-DBI on
9150 13:08:30.197662 PER_BANK_REFRESH: Hybrid Mode
9151 13:08:30.201306 TX_TRACKING: ON
9152 13:08:30.207772 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9153 13:08:30.217601 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9154 13:08:30.224304 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9155 13:08:30.228000 [FAST_K] Save calibration result to emmc
9156 13:08:30.231389 sync common calibartion params.
9157 13:08:30.231463 sync cbt_mode0:1, 1:1
9158 13:08:30.234851 dram_init: ddr_geometry: 2
9159 13:08:30.237881 dram_init: ddr_geometry: 2
9160 13:08:30.241268 dram_init: ddr_geometry: 2
9161 13:08:30.241343 0:dram_rank_size:100000000
9162 13:08:30.244530 1:dram_rank_size:100000000
9163 13:08:30.251321 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9164 13:08:30.251396 DFS_SHUFFLE_HW_MODE: ON
9165 13:08:30.257752 dramc_set_vcore_voltage set vcore to 725000
9166 13:08:30.257828 Read voltage for 1600, 0
9167 13:08:30.257885 Vio18 = 0
9168 13:08:30.261009 Vcore = 725000
9169 13:08:30.261087 Vdram = 0
9170 13:08:30.261144 Vddq = 0
9171 13:08:30.264603 Vmddr = 0
9172 13:08:30.264677 switch to 3200 Mbps bootup
9173 13:08:30.267801 [DramcRunTimeConfig]
9174 13:08:30.267875 PHYPLL
9175 13:08:30.271263 DPM_CONTROL_AFTERK: ON
9176 13:08:30.271337 PER_BANK_REFRESH: ON
9177 13:08:30.274082 REFRESH_OVERHEAD_REDUCTION: ON
9178 13:08:30.277904 CMD_PICG_NEW_MODE: OFF
9179 13:08:30.277984 XRTWTW_NEW_MODE: ON
9180 13:08:30.281083 XRTRTR_NEW_MODE: ON
9181 13:08:30.281157 TX_TRACKING: ON
9182 13:08:30.284294 RDSEL_TRACKING: OFF
9183 13:08:30.287573 DQS Precalculation for DVFS: ON
9184 13:08:30.287647 RX_TRACKING: OFF
9185 13:08:30.291340 HW_GATING DBG: ON
9186 13:08:30.291414 ZQCS_ENABLE_LP4: ON
9187 13:08:30.294286 RX_PICG_NEW_MODE: ON
9188 13:08:30.294360 TX_PICG_NEW_MODE: ON
9189 13:08:30.297798 ENABLE_RX_DCM_DPHY: ON
9190 13:08:30.300915 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9191 13:08:30.303974 DUMMY_READ_FOR_TRACKING: OFF
9192 13:08:30.307511 !!! SPM_CONTROL_AFTERK: OFF
9193 13:08:30.307590 !!! SPM could not control APHY
9194 13:08:30.310512 IMPEDANCE_TRACKING: ON
9195 13:08:30.313745 TEMP_SENSOR: ON
9196 13:08:30.313820 HW_SAVE_FOR_SR: OFF
9197 13:08:30.317183 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9198 13:08:30.321075 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9199 13:08:30.323784 Read ODT Tracking: ON
9200 13:08:30.323859 Refresh Rate DeBounce: ON
9201 13:08:30.327257 DFS_NO_QUEUE_FLUSH: ON
9202 13:08:30.330346 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9203 13:08:30.333646 ENABLE_DFS_RUNTIME_MRW: OFF
9204 13:08:30.333720 DDR_RESERVE_NEW_MODE: ON
9205 13:08:30.337006 MR_CBT_SWITCH_FREQ: ON
9206 13:08:30.340669 =========================
9207 13:08:30.358317 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9208 13:08:30.361343 dram_init: ddr_geometry: 2
9209 13:08:30.379566 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9210 13:08:30.383164 dram_init: dram init end (result: 0)
9211 13:08:30.389688 DRAM-K: Full calibration passed in 24515 msecs
9212 13:08:30.393178 MRC: failed to locate region type 0.
9213 13:08:30.393254 DRAM rank0 size:0x100000000,
9214 13:08:30.396167 DRAM rank1 size=0x100000000
9215 13:08:30.406415 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9216 13:08:30.413020 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9217 13:08:30.419631 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9218 13:08:30.426134 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9219 13:08:30.429868 DRAM rank0 size:0x100000000,
9220 13:08:30.433039 DRAM rank1 size=0x100000000
9221 13:08:30.433113 CBMEM:
9222 13:08:30.436614 IMD: root @ 0xfffff000 254 entries.
9223 13:08:30.439825 IMD: root @ 0xffffec00 62 entries.
9224 13:08:30.442796 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9225 13:08:30.446190 WARNING: RO_VPD is uninitialized or empty.
9226 13:08:30.452758 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9227 13:08:30.459748 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9228 13:08:30.473129 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9229 13:08:30.484124 BS: romstage times (exec / console): total (unknown) / 23984 ms
9230 13:08:30.484200
9231 13:08:30.484258
9232 13:08:30.493803 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9233 13:08:30.497268 ARM64: Exception handlers installed.
9234 13:08:30.500922 ARM64: Testing exception
9235 13:08:30.503991 ARM64: Done test exception
9236 13:08:30.504066 Enumerating buses...
9237 13:08:30.507616 Show all devs... Before device enumeration.
9238 13:08:30.510668 Root Device: enabled 1
9239 13:08:30.513769 CPU_CLUSTER: 0: enabled 1
9240 13:08:30.513843 CPU: 00: enabled 1
9241 13:08:30.517294 Compare with tree...
9242 13:08:30.517368 Root Device: enabled 1
9243 13:08:30.520889 CPU_CLUSTER: 0: enabled 1
9244 13:08:30.523807 CPU: 00: enabled 1
9245 13:08:30.523881 Root Device scanning...
9246 13:08:30.526887 scan_static_bus for Root Device
9247 13:08:30.530543 CPU_CLUSTER: 0 enabled
9248 13:08:30.533586 scan_static_bus for Root Device done
9249 13:08:30.537026 scan_bus: bus Root Device finished in 8 msecs
9250 13:08:30.537101 done
9251 13:08:30.543775 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9252 13:08:30.547215 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9253 13:08:30.553570 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9254 13:08:30.557144 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9255 13:08:30.560472 Allocating resources...
9256 13:08:30.563571 Reading resources...
9257 13:08:30.567179 Root Device read_resources bus 0 link: 0
9258 13:08:30.567257 DRAM rank0 size:0x100000000,
9259 13:08:30.570312 DRAM rank1 size=0x100000000
9260 13:08:30.573353 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9261 13:08:30.577315 CPU: 00 missing read_resources
9262 13:08:30.583352 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9263 13:08:30.586622 Root Device read_resources bus 0 link: 0 done
9264 13:08:30.586697 Done reading resources.
9265 13:08:30.593242 Show resources in subtree (Root Device)...After reading.
9266 13:08:30.596709 Root Device child on link 0 CPU_CLUSTER: 0
9267 13:08:30.599856 CPU_CLUSTER: 0 child on link 0 CPU: 00
9268 13:08:30.609621 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9269 13:08:30.609694 CPU: 00
9270 13:08:30.613363 Root Device assign_resources, bus 0 link: 0
9271 13:08:30.616515 CPU_CLUSTER: 0 missing set_resources
9272 13:08:30.623213 Root Device assign_resources, bus 0 link: 0 done
9273 13:08:30.623291 Done setting resources.
9274 13:08:30.629564 Show resources in subtree (Root Device)...After assigning values.
9275 13:08:30.632782 Root Device child on link 0 CPU_CLUSTER: 0
9276 13:08:30.636231 CPU_CLUSTER: 0 child on link 0 CPU: 00
9277 13:08:30.646386 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9278 13:08:30.646462 CPU: 00
9279 13:08:30.649445 Done allocating resources.
9280 13:08:30.656278 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9281 13:08:30.656352 Enabling resources...
9282 13:08:30.656408 done.
9283 13:08:30.663194 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9284 13:08:30.663269 Initializing devices...
9285 13:08:30.666030 Root Device init
9286 13:08:30.666165 init hardware done!
9287 13:08:30.669878 0x00000018: ctrlr->caps
9288 13:08:30.672829 52.000 MHz: ctrlr->f_max
9289 13:08:30.672904 0.400 MHz: ctrlr->f_min
9290 13:08:30.675886 0x40ff8080: ctrlr->voltages
9291 13:08:30.679575 sclk: 390625
9292 13:08:30.679649 Bus Width = 1
9293 13:08:30.679705 sclk: 390625
9294 13:08:30.682931 Bus Width = 1
9295 13:08:30.683004 Early init status = 3
9296 13:08:30.689440 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9297 13:08:30.692662 in-header: 03 fc 00 00 01 00 00 00
9298 13:08:30.692736 in-data: 00
9299 13:08:30.699034 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9300 13:08:30.703251 in-header: 03 fd 00 00 00 00 00 00
9301 13:08:30.706020 in-data:
9302 13:08:30.709435 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9303 13:08:30.712663 in-header: 03 fc 00 00 01 00 00 00
9304 13:08:30.716441 in-data: 00
9305 13:08:30.719447 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9306 13:08:30.723986 in-header: 03 fd 00 00 00 00 00 00
9307 13:08:30.727576 in-data:
9308 13:08:30.730698 [SSUSB] Setting up USB HOST controller...
9309 13:08:30.734445 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9310 13:08:30.737205 [SSUSB] phy power-on done.
9311 13:08:30.740683 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9312 13:08:30.747170 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9313 13:08:30.750692 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9314 13:08:30.757042 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9315 13:08:30.764058 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9316 13:08:30.770634 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9317 13:08:30.777227 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9318 13:08:30.783727 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9319 13:08:30.787570 SPM: binary array size = 0x9dc
9320 13:08:30.790419 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9321 13:08:30.797379 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9322 13:08:30.803786 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9323 13:08:30.807240 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9324 13:08:30.813499 configure_display: Starting display init
9325 13:08:30.847243 anx7625_power_on_init: Init interface.
9326 13:08:30.850766 anx7625_disable_pd_protocol: Disabled PD feature.
9327 13:08:30.853870 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9328 13:08:30.881647 anx7625_start_dp_work: Secure OCM version=00
9329 13:08:30.885276 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9330 13:08:30.899801 sp_tx_get_edid_block: EDID Block = 1
9331 13:08:31.002615 Extracted contents:
9332 13:08:31.005671 header: 00 ff ff ff ff ff ff 00
9333 13:08:31.008699 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9334 13:08:31.012081 version: 01 04
9335 13:08:31.015936 basic params: 95 1f 11 78 0a
9336 13:08:31.018852 chroma info: 76 90 94 55 54 90 27 21 50 54
9337 13:08:31.022096 established: 00 00 00
9338 13:08:31.028670 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9339 13:08:31.031868 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9340 13:08:31.038710 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9341 13:08:31.045431 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9342 13:08:31.052047 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9343 13:08:31.055114 extensions: 00
9344 13:08:31.055189 checksum: fb
9345 13:08:31.055245
9346 13:08:31.058621 Manufacturer: IVO Model 57d Serial Number 0
9347 13:08:31.061867 Made week 0 of 2020
9348 13:08:31.061943 EDID version: 1.4
9349 13:08:31.065463 Digital display
9350 13:08:31.068633 6 bits per primary color channel
9351 13:08:31.068710 DisplayPort interface
9352 13:08:31.071883 Maximum image size: 31 cm x 17 cm
9353 13:08:31.075074 Gamma: 220%
9354 13:08:31.075149 Check DPMS levels
9355 13:08:31.078601 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9356 13:08:31.084902 First detailed timing is preferred timing
9357 13:08:31.084978 Established timings supported:
9358 13:08:31.088523 Standard timings supported:
9359 13:08:31.091960 Detailed timings
9360 13:08:31.094917 Hex of detail: 383680a07038204018303c0035ae10000019
9361 13:08:31.101612 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9362 13:08:31.104773 0780 0798 07c8 0820 hborder 0
9363 13:08:31.107866 0438 043b 0447 0458 vborder 0
9364 13:08:31.111584 -hsync -vsync
9365 13:08:31.111659 Did detailed timing
9366 13:08:31.118247 Hex of detail: 000000000000000000000000000000000000
9367 13:08:31.121298 Manufacturer-specified data, tag 0
9368 13:08:31.124705 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9369 13:08:31.128072 ASCII string: InfoVision
9370 13:08:31.131399 Hex of detail: 000000fe00523134304e574635205248200a
9371 13:08:31.134611 ASCII string: R140NWF5 RH
9372 13:08:31.134685 Checksum
9373 13:08:31.138015 Checksum: 0xfb (valid)
9374 13:08:31.140835 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9375 13:08:31.144686 DSI data_rate: 832800000 bps
9376 13:08:31.151137 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9377 13:08:31.154352 anx7625_parse_edid: pixelclock(138800).
9378 13:08:31.157768 hactive(1920), hsync(48), hfp(24), hbp(88)
9379 13:08:31.161017 vactive(1080), vsync(12), vfp(3), vbp(17)
9380 13:08:31.164369 anx7625_dsi_config: config dsi.
9381 13:08:31.170943 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9382 13:08:31.184582 anx7625_dsi_config: success to config DSI
9383 13:08:31.187874 anx7625_dp_start: MIPI phy setup OK.
9384 13:08:31.191194 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9385 13:08:31.193863 mtk_ddp_mode_set invalid vrefresh 60
9386 13:08:31.197810 main_disp_path_setup
9387 13:08:31.197883 ovl_layer_smi_id_en
9388 13:08:31.200983 ovl_layer_smi_id_en
9389 13:08:31.201056 ccorr_config
9390 13:08:31.201112 aal_config
9391 13:08:31.203930 gamma_config
9392 13:08:31.204003 postmask_config
9393 13:08:31.207635 dither_config
9394 13:08:31.210784 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9395 13:08:31.217736 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9396 13:08:31.220743 Root Device init finished in 551 msecs
9397 13:08:31.223769 CPU_CLUSTER: 0 init
9398 13:08:31.230179 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9399 13:08:31.237196 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9400 13:08:31.237269 APU_MBOX 0x190000b0 = 0x10001
9401 13:08:31.240519 APU_MBOX 0x190001b0 = 0x10001
9402 13:08:31.243938 APU_MBOX 0x190005b0 = 0x10001
9403 13:08:31.246969 APU_MBOX 0x190006b0 = 0x10001
9404 13:08:31.253459 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9405 13:08:31.263391 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9406 13:08:31.275826 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9407 13:08:31.282207 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9408 13:08:31.293837 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9409 13:08:31.303656 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9410 13:08:31.306559 CPU_CLUSTER: 0 init finished in 81 msecs
9411 13:08:31.309709 Devices initialized
9412 13:08:31.313200 Show all devs... After init.
9413 13:08:31.313275 Root Device: enabled 1
9414 13:08:31.316383 CPU_CLUSTER: 0: enabled 1
9415 13:08:31.319360 CPU: 00: enabled 1
9416 13:08:31.322991 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9417 13:08:31.326011 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9418 13:08:31.329282 ELOG: NV offset 0x57f000 size 0x1000
9419 13:08:31.336427 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9420 13:08:31.342929 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9421 13:08:31.346321 ELOG: Event(17) added with size 13 at 2024-07-18 13:08:31 UTC
9422 13:08:31.352445 out: cmd=0x121: 03 db 21 01 00 00 00 00
9423 13:08:31.355883 in-header: 03 ac 00 00 2c 00 00 00
9424 13:08:31.365830 in-data: 92 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9425 13:08:31.372807 ELOG: Event(A1) added with size 10 at 2024-07-18 13:08:31 UTC
9426 13:08:31.379284 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9427 13:08:31.386036 ELOG: Event(A0) added with size 9 at 2024-07-18 13:08:31 UTC
9428 13:08:31.389067 elog_add_boot_reason: Logged dev mode boot
9429 13:08:31.395902 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9430 13:08:31.395978 Finalize devices...
9431 13:08:31.399333 Devices finalized
9432 13:08:31.401909 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9433 13:08:31.405805 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9434 13:08:31.408813 in-header: 03 07 00 00 08 00 00 00
9435 13:08:31.412123 in-data: aa e4 47 04 13 02 00 00
9436 13:08:31.415686 Chrome EC: UHEPI supported
9437 13:08:31.422569 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9438 13:08:31.425640 in-header: 03 a9 00 00 08 00 00 00
9439 13:08:31.429134 in-data: 84 60 60 08 00 00 00 00
9440 13:08:31.432082 ELOG: Event(91) added with size 10 at 2024-07-18 13:08:31 UTC
9441 13:08:31.439250 Chrome EC: clear events_b mask to 0x0000000020004000
9442 13:08:31.446141 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9443 13:08:31.449365 in-header: 03 fd 00 00 00 00 00 00
9444 13:08:31.449441 in-data:
9445 13:08:31.456252 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9446 13:08:31.459576 Writing coreboot table at 0xffe64000
9447 13:08:31.462386 0. 000000000010a000-0000000000113fff: RAMSTAGE
9448 13:08:31.465777 1. 0000000040000000-00000000400fffff: RAM
9449 13:08:31.472756 2. 0000000040100000-000000004032afff: RAMSTAGE
9450 13:08:31.475660 3. 000000004032b000-00000000545fffff: RAM
9451 13:08:31.479227 4. 0000000054600000-000000005465ffff: BL31
9452 13:08:31.482289 5. 0000000054660000-00000000ffe63fff: RAM
9453 13:08:31.489058 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9454 13:08:31.492152 7. 0000000100000000-000000023fffffff: RAM
9455 13:08:31.495804 Passing 5 GPIOs to payload:
9456 13:08:31.499664 NAME | PORT | POLARITY | VALUE
9457 13:08:31.502534 EC in RW | 0x000000aa | low | undefined
9458 13:08:31.509077 EC interrupt | 0x00000005 | low | undefined
9459 13:08:31.512551 TPM interrupt | 0x000000ab | high | undefined
9460 13:08:31.518984 SD card detect | 0x00000011 | high | undefined
9461 13:08:31.522063 speaker enable | 0x00000093 | high | undefined
9462 13:08:31.525607 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9463 13:08:31.528646 in-header: 03 f9 00 00 02 00 00 00
9464 13:08:31.528721 in-data: 02 00
9465 13:08:31.532415 ADC[4]: Raw value=895930 ID=7
9466 13:08:31.535380 ADC[3]: Raw value=213070 ID=1
9467 13:08:31.538526 RAM Code: 0x71
9468 13:08:31.538601 ADC[6]: Raw value=74722 ID=0
9469 13:08:31.542107 ADC[5]: Raw value=212700 ID=1
9470 13:08:31.545112 SKU Code: 0x1
9471 13:08:31.548730 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 22d9
9472 13:08:31.551870 coreboot table: 964 bytes.
9473 13:08:31.555340 IMD ROOT 0. 0xfffff000 0x00001000
9474 13:08:31.558646 IMD SMALL 1. 0xffffe000 0x00001000
9475 13:08:31.562065 RO MCACHE 2. 0xffffc000 0x00001104
9476 13:08:31.565112 CONSOLE 3. 0xfff7c000 0x00080000
9477 13:08:31.568581 FMAP 4. 0xfff7b000 0x00000452
9478 13:08:31.571943 TIME STAMP 5. 0xfff7a000 0x00000910
9479 13:08:31.575122 VBOOT WORK 6. 0xfff66000 0x00014000
9480 13:08:31.578579 RAMOOPS 7. 0xffe66000 0x00100000
9481 13:08:31.581673 COREBOOT 8. 0xffe64000 0x00002000
9482 13:08:31.581770 IMD small region:
9483 13:08:31.584716 IMD ROOT 0. 0xffffec00 0x00000400
9484 13:08:31.588288 VPD 1. 0xffffeb80 0x0000006c
9485 13:08:31.595175 MMC STATUS 2. 0xffffeb60 0x00000004
9486 13:08:31.598047 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9487 13:08:31.604876 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9488 13:08:31.645063 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9489 13:08:31.648668 Checking segment from ROM address 0x40100000
9490 13:08:31.651766 Checking segment from ROM address 0x4010001c
9491 13:08:31.658278 Loading segment from ROM address 0x40100000
9492 13:08:31.658353 code (compression=0)
9493 13:08:31.667890 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9494 13:08:31.675048 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9495 13:08:31.675124 it's not compressed!
9496 13:08:31.681593 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9497 13:08:31.687898 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9498 13:08:31.705896 Loading segment from ROM address 0x4010001c
9499 13:08:31.705972 Entry Point 0x80000000
9500 13:08:31.708436 Loaded segments
9501 13:08:31.711991 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9502 13:08:31.718553 Jumping to boot code at 0x80000000(0xffe64000)
9503 13:08:31.725329 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9504 13:08:31.731760 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9505 13:08:31.739688 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9506 13:08:31.743180 Checking segment from ROM address 0x40100000
9507 13:08:31.746489 Checking segment from ROM address 0x4010001c
9508 13:08:31.753115 Loading segment from ROM address 0x40100000
9509 13:08:31.753192 code (compression=1)
9510 13:08:31.759923 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9511 13:08:31.769685 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9512 13:08:31.769762 using LZMA
9513 13:08:31.778334 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9514 13:08:31.784777 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9515 13:08:31.788069 Loading segment from ROM address 0x4010001c
9516 13:08:31.791582 Entry Point 0x54601000
9517 13:08:31.791657 Loaded segments
9518 13:08:31.794797 NOTICE: MT8192 bl31_setup
9519 13:08:31.802124 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9520 13:08:31.805148 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9521 13:08:31.808913 WARNING: region 0:
9522 13:08:31.812216 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9523 13:08:31.812291 WARNING: region 1:
9524 13:08:31.818141 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9525 13:08:31.821566 WARNING: region 2:
9526 13:08:31.825295 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9527 13:08:31.828580 WARNING: region 3:
9528 13:08:31.831735 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9529 13:08:31.835274 WARNING: region 4:
9530 13:08:31.841421 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9531 13:08:31.841496 WARNING: region 5:
9532 13:08:31.844640 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9533 13:08:31.848037 WARNING: region 6:
9534 13:08:31.851278 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9535 13:08:31.854956 WARNING: region 7:
9536 13:08:31.857744 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9537 13:08:31.864655 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9538 13:08:31.868043 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9539 13:08:31.874713 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9540 13:08:31.877797 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9541 13:08:31.880999 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9542 13:08:31.887916 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9543 13:08:31.890920 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9544 13:08:31.894396 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9545 13:08:31.900942 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9546 13:08:31.904399 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9547 13:08:31.911285 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9548 13:08:31.914382 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9549 13:08:31.917446 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9550 13:08:31.924239 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9551 13:08:31.927546 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9552 13:08:31.930847 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9553 13:08:31.937445 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9554 13:08:31.940611 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9555 13:08:31.947613 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9556 13:08:31.950917 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9557 13:08:31.954033 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9558 13:08:31.960837 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9559 13:08:31.963791 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9560 13:08:31.967642 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9561 13:08:31.973874 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9562 13:08:31.977637 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9563 13:08:31.983969 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9564 13:08:31.987769 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9565 13:08:31.993935 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9566 13:08:31.997194 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9567 13:08:32.000446 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9568 13:08:32.007237 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9569 13:08:32.010384 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9570 13:08:32.013752 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9571 13:08:32.016959 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9572 13:08:32.023524 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9573 13:08:32.027352 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9574 13:08:32.030651 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9575 13:08:32.034057 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9576 13:08:32.040295 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9577 13:08:32.043649 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9578 13:08:32.046886 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9579 13:08:32.050820 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9580 13:08:32.057002 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9581 13:08:32.060749 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9582 13:08:32.063998 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9583 13:08:32.070426 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9584 13:08:32.073447 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9585 13:08:32.076673 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9586 13:08:32.083789 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9587 13:08:32.086745 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9588 13:08:32.090460 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9589 13:08:32.096660 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9590 13:08:32.100489 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9591 13:08:32.106828 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9592 13:08:32.110109 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9593 13:08:32.116906 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9594 13:08:32.120169 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9595 13:08:32.123817 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9596 13:08:32.130126 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9597 13:08:32.133145 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9598 13:08:32.139803 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9599 13:08:32.143311 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9600 13:08:32.150092 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9601 13:08:32.153650 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9602 13:08:32.160240 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9603 13:08:32.163197 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9604 13:08:32.166493 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9605 13:08:32.173160 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9606 13:08:32.176271 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9607 13:08:32.182833 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9608 13:08:32.186544 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9609 13:08:32.193019 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9610 13:08:32.196197 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9611 13:08:32.202915 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9612 13:08:32.206008 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9613 13:08:32.209647 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9614 13:08:32.215858 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9615 13:08:32.219377 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9616 13:08:32.225924 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9617 13:08:32.229298 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9618 13:08:32.235884 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9619 13:08:32.239419 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9620 13:08:32.245843 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9621 13:08:32.248999 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9622 13:08:32.252176 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9623 13:08:32.259135 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9624 13:08:32.262399 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9625 13:08:32.269056 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9626 13:08:32.272295 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9627 13:08:32.279181 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9628 13:08:32.282309 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9629 13:08:32.288938 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9630 13:08:32.292573 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9631 13:08:32.295410 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9632 13:08:32.302249 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9633 13:08:32.305342 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9634 13:08:32.308835 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9635 13:08:32.315177 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9636 13:08:32.318750 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9637 13:08:32.321904 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9638 13:08:32.328423 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9639 13:08:32.331892 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9640 13:08:32.335422 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9641 13:08:32.341567 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9642 13:08:32.345230 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9643 13:08:32.351273 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9644 13:08:32.354984 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9645 13:08:32.361394 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9646 13:08:32.365332 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9647 13:08:32.368388 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9648 13:08:32.374368 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9649 13:08:32.377766 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9650 13:08:32.384934 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9651 13:08:32.387824 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9652 13:08:32.391210 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9653 13:08:32.397756 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9654 13:08:32.401253 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9655 13:08:32.404583 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9656 13:08:32.410882 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9657 13:08:32.414658 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9658 13:08:32.417660 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9659 13:08:32.420904 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9660 13:08:32.427671 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9661 13:08:32.430537 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9662 13:08:32.434189 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9663 13:08:32.440962 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9664 13:08:32.444484 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9665 13:08:32.451139 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9666 13:08:32.454269 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9667 13:08:32.457448 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9668 13:08:32.464665 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9669 13:08:32.467719 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9670 13:08:32.470653 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9671 13:08:32.477195 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9672 13:08:32.480508 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9673 13:08:32.487027 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9674 13:08:32.490380 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9675 13:08:32.493467 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9676 13:08:32.500207 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9677 13:08:32.503825 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9678 13:08:32.510449 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9679 13:08:32.513420 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9680 13:08:32.516883 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9681 13:08:32.523590 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9682 13:08:32.526880 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9683 13:08:32.533421 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9684 13:08:32.537028 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9685 13:08:32.540030 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9686 13:08:32.546978 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9687 13:08:32.550095 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9688 13:08:32.556829 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9689 13:08:32.560436 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9690 13:08:32.563571 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9691 13:08:32.570140 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9692 13:08:32.573107 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9693 13:08:32.579974 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9694 13:08:32.583432 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9695 13:08:32.586674 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9696 13:08:32.593592 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9697 13:08:32.596704 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9698 13:08:32.600151 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9699 13:08:32.606873 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9700 13:08:32.609957 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9701 13:08:32.616688 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9702 13:08:32.619555 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9703 13:08:32.623320 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9704 13:08:32.629835 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9705 13:08:32.633154 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9706 13:08:32.639476 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9707 13:08:32.643188 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9708 13:08:32.646260 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9709 13:08:32.652956 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9710 13:08:32.656203 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9711 13:08:32.662990 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9712 13:08:32.666648 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9713 13:08:32.669739 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9714 13:08:32.675883 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9715 13:08:32.679521 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9716 13:08:32.686286 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9717 13:08:32.689158 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9718 13:08:32.692815 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9719 13:08:32.699291 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9720 13:08:32.702419 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9721 13:08:32.709091 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9722 13:08:32.712725 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9723 13:08:32.715955 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9724 13:08:32.722536 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9725 13:08:32.726072 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9726 13:08:32.732691 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9727 13:08:32.735622 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9728 13:08:32.738748 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9729 13:08:32.745745 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9730 13:08:32.749256 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9731 13:08:32.756260 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9732 13:08:32.758816 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9733 13:08:32.765466 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9734 13:08:32.768837 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9735 13:08:32.772678 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9736 13:08:32.779292 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9737 13:08:32.782490 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9738 13:08:32.788839 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9739 13:08:32.792077 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9740 13:08:32.795576 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9741 13:08:32.801934 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9742 13:08:32.805567 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9743 13:08:32.811790 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9744 13:08:32.815175 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9745 13:08:32.822228 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9746 13:08:32.825363 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9747 13:08:32.828637 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9748 13:08:32.835553 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9749 13:08:32.838552 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9750 13:08:32.844869 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9751 13:08:32.848560 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9752 13:08:32.851513 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9753 13:08:32.858381 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9754 13:08:32.861532 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9755 13:08:32.868585 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9756 13:08:32.871487 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9757 13:08:32.878256 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9758 13:08:32.881610 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9759 13:08:32.884637 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9760 13:08:32.891114 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9761 13:08:32.894808 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9762 13:08:32.901592 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9763 13:08:32.904656 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9764 13:08:32.911288 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9765 13:08:32.914834 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9766 13:08:32.917782 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9767 13:08:32.921479 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9768 13:08:32.927859 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9769 13:08:32.931380 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9770 13:08:32.934525 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9771 13:08:32.937547 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9772 13:08:32.944541 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9773 13:08:32.947532 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9774 13:08:32.954192 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9775 13:08:32.957888 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9776 13:08:32.960913 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9777 13:08:32.967710 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9778 13:08:32.970881 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9779 13:08:32.973970 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9780 13:08:32.981054 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9781 13:08:32.984221 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9782 13:08:32.990485 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9783 13:08:32.994558 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9784 13:08:32.997664 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9785 13:08:33.004117 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9786 13:08:33.007655 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9787 13:08:33.010489 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9788 13:08:33.017712 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9789 13:08:33.020498 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9790 13:08:33.023700 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9791 13:08:33.030481 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9792 13:08:33.034260 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9793 13:08:33.040391 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9794 13:08:33.043951 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9795 13:08:33.046998 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9796 13:08:33.053725 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9797 13:08:33.057381 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9798 13:08:33.060510 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9799 13:08:33.067332 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9800 13:08:33.069938 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9801 13:08:33.073824 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9802 13:08:33.079896 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9803 13:08:33.083438 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9804 13:08:33.090341 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9805 13:08:33.093525 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9806 13:08:33.096608 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9807 13:08:33.100369 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9808 13:08:33.106534 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9809 13:08:33.109661 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9810 13:08:33.113293 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9811 13:08:33.116405 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9812 13:08:33.122843 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9813 13:08:33.126627 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9814 13:08:33.129572 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9815 13:08:33.133145 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9816 13:08:33.139650 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9817 13:08:33.143153 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9818 13:08:33.146554 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9819 13:08:33.153503 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9820 13:08:33.156169 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9821 13:08:33.159702 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9822 13:08:33.166084 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9823 13:08:33.169705 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9824 13:08:33.176592 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9825 13:08:33.179563 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9826 13:08:33.183098 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9827 13:08:33.189656 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9828 13:08:33.192690 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9829 13:08:33.198916 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9830 13:08:33.202570 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9831 13:08:33.209215 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9832 13:08:33.212355 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9833 13:08:33.219432 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9834 13:08:33.222339 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9835 13:08:33.225795 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9836 13:08:33.232694 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9837 13:08:33.235525 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9838 13:08:33.242315 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9839 13:08:33.245408 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9840 13:08:33.249317 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9841 13:08:33.255637 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9842 13:08:33.259359 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9843 13:08:33.265618 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9844 13:08:33.268721 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9845 13:08:33.271952 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9846 13:08:33.278529 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9847 13:08:33.281925 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9848 13:08:33.288335 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9849 13:08:33.292306 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9850 13:08:33.295583 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9851 13:08:33.301676 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9852 13:08:33.305358 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9853 13:08:33.311734 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9854 13:08:33.315019 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9855 13:08:33.321725 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9856 13:08:33.325116 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9857 13:08:33.328684 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9858 13:08:33.334859 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9859 13:08:33.338555 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9860 13:08:33.345141 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9861 13:08:33.348214 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9862 13:08:33.351819 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9863 13:08:33.358016 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9864 13:08:33.361339 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9865 13:08:33.367943 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9866 13:08:33.371479 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9867 13:08:33.374716 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9868 13:08:33.381241 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9869 13:08:33.384385 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9870 13:08:33.391054 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9871 13:08:33.394779 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9872 13:08:33.401142 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9873 13:08:33.404896 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9874 13:08:33.407641 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9875 13:08:33.414457 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9876 13:08:33.417715 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9877 13:08:33.424587 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9878 13:08:33.427800 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9879 13:08:33.430740 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9880 13:08:33.437652 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9881 13:08:33.440684 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9882 13:08:33.447690 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9883 13:08:33.450591 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9884 13:08:33.453990 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9885 13:08:33.460520 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9886 13:08:33.463996 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9887 13:08:33.470457 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9888 13:08:33.474223 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9889 13:08:33.480682 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9890 13:08:33.484416 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9891 13:08:33.487197 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9892 13:08:33.494017 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9893 13:08:33.497005 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9894 13:08:33.503685 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9895 13:08:33.507491 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9896 13:08:33.513529 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9897 13:08:33.517228 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9898 13:08:33.520256 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9899 13:08:33.527339 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9900 13:08:33.530335 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9901 13:08:33.536909 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9902 13:08:33.540328 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9903 13:08:33.546915 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9904 13:08:33.550334 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9905 13:08:33.557101 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9906 13:08:33.560329 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9907 13:08:33.563397 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9908 13:08:33.569910 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9909 13:08:33.573409 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9910 13:08:33.580148 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9911 13:08:33.583198 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9912 13:08:33.590188 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9913 13:08:33.593155 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9914 13:08:33.596526 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9915 13:08:33.602813 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9916 13:08:33.606627 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9917 13:08:33.613111 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9918 13:08:33.616380 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9919 13:08:33.622944 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9920 13:08:33.626384 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9921 13:08:33.633178 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9922 13:08:33.636483 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9923 13:08:33.639754 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9924 13:08:33.646249 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9925 13:08:33.649965 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9926 13:08:33.656495 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9927 13:08:33.659713 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9928 13:08:33.666166 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9929 13:08:33.669979 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9930 13:08:33.672878 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9931 13:08:33.679380 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9932 13:08:33.682868 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9933 13:08:33.689640 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9934 13:08:33.692711 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9935 13:08:33.699631 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9936 13:08:33.702911 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9937 13:08:33.709379 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9938 13:08:33.712471 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9939 13:08:33.716159 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9940 13:08:33.722490 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9941 13:08:33.726135 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9942 13:08:33.732305 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9943 13:08:33.735918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9944 13:08:33.739327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9945 13:08:33.745663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9946 13:08:33.749142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9947 13:08:33.755783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9948 13:08:33.758920 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9949 13:08:33.765551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9950 13:08:33.769100 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9951 13:08:33.775720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9952 13:08:33.779260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9953 13:08:33.785125 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9954 13:08:33.788875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9955 13:08:33.795609 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9956 13:08:33.798921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9957 13:08:33.805931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9958 13:08:33.808585 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9959 13:08:33.815628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9960 13:08:33.819035 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9961 13:08:33.825809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9962 13:08:33.829033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9963 13:08:33.835166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9964 13:08:33.838749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9965 13:08:33.845020 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9966 13:08:33.848387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9967 13:08:33.855314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9968 13:08:33.858414 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9969 13:08:33.864981 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9970 13:08:33.868039 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9971 13:08:33.874606 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9972 13:08:33.874687 INFO: [APUAPC] vio 0
9973 13:08:33.881739 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9974 13:08:33.885159 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9975 13:08:33.888236 INFO: [APUAPC] D0_APC_0: 0x400510
9976 13:08:33.891688 INFO: [APUAPC] D0_APC_1: 0x0
9977 13:08:33.894700 INFO: [APUAPC] D0_APC_2: 0x1540
9978 13:08:33.898045 INFO: [APUAPC] D0_APC_3: 0x0
9979 13:08:33.901553 INFO: [APUAPC] D1_APC_0: 0xffffffff
9980 13:08:33.905110 INFO: [APUAPC] D1_APC_1: 0xffffffff
9981 13:08:33.908128 INFO: [APUAPC] D1_APC_2: 0x3fffff
9982 13:08:33.911241 INFO: [APUAPC] D1_APC_3: 0x0
9983 13:08:33.914925 INFO: [APUAPC] D2_APC_0: 0xffffffff
9984 13:08:33.917771 INFO: [APUAPC] D2_APC_1: 0xffffffff
9985 13:08:33.921133 INFO: [APUAPC] D2_APC_2: 0x3fffff
9986 13:08:33.924830 INFO: [APUAPC] D2_APC_3: 0x0
9987 13:08:33.927842 INFO: [APUAPC] D3_APC_0: 0xffffffff
9988 13:08:33.931169 INFO: [APUAPC] D3_APC_1: 0xffffffff
9989 13:08:33.934515 INFO: [APUAPC] D3_APC_2: 0x3fffff
9990 13:08:33.937911 INFO: [APUAPC] D3_APC_3: 0x0
9991 13:08:33.941071 INFO: [APUAPC] D4_APC_0: 0xffffffff
9992 13:08:33.944574 INFO: [APUAPC] D4_APC_1: 0xffffffff
9993 13:08:33.947597 INFO: [APUAPC] D4_APC_2: 0x3fffff
9994 13:08:33.951089 INFO: [APUAPC] D4_APC_3: 0x0
9995 13:08:33.954631 INFO: [APUAPC] D5_APC_0: 0xffffffff
9996 13:08:33.957818 INFO: [APUAPC] D5_APC_1: 0xffffffff
9997 13:08:33.961424 INFO: [APUAPC] D5_APC_2: 0x3fffff
9998 13:08:33.961519 INFO: [APUAPC] D5_APC_3: 0x0
9999 13:08:33.964389 INFO: [APUAPC] D6_APC_0: 0xffffffff
10000 13:08:33.971169 INFO: [APUAPC] D6_APC_1: 0xffffffff
10001 13:08:33.971234 INFO: [APUAPC] D6_APC_2: 0x3fffff
10002 13:08:33.974783 INFO: [APUAPC] D6_APC_3: 0x0
10003 13:08:33.978070 INFO: [APUAPC] D7_APC_0: 0xffffffff
10004 13:08:33.981128 INFO: [APUAPC] D7_APC_1: 0xffffffff
10005 13:08:33.984279 INFO: [APUAPC] D7_APC_2: 0x3fffff
10006 13:08:33.987818 INFO: [APUAPC] D7_APC_3: 0x0
10007 13:08:33.990917 INFO: [APUAPC] D8_APC_0: 0xffffffff
10008 13:08:33.994370 INFO: [APUAPC] D8_APC_1: 0xffffffff
10009 13:08:33.997606 INFO: [APUAPC] D8_APC_2: 0x3fffff
10010 13:08:34.000877 INFO: [APUAPC] D8_APC_3: 0x0
10011 13:08:34.004196 INFO: [APUAPC] D9_APC_0: 0xffffffff
10012 13:08:34.007865 INFO: [APUAPC] D9_APC_1: 0xffffffff
10013 13:08:34.010694 INFO: [APUAPC] D9_APC_2: 0x3fffff
10014 13:08:34.014608 INFO: [APUAPC] D9_APC_3: 0x0
10015 13:08:34.017279 INFO: [APUAPC] D10_APC_0: 0xffffffff
10016 13:08:34.020896 INFO: [APUAPC] D10_APC_1: 0xffffffff
10017 13:08:34.024142 INFO: [APUAPC] D10_APC_2: 0x3fffff
10018 13:08:34.027118 INFO: [APUAPC] D10_APC_3: 0x0
10019 13:08:34.030746 INFO: [APUAPC] D11_APC_0: 0xffffffff
10020 13:08:34.034217 INFO: [APUAPC] D11_APC_1: 0xffffffff
10021 13:08:34.037108 INFO: [APUAPC] D11_APC_2: 0x3fffff
10022 13:08:34.040690 INFO: [APUAPC] D11_APC_3: 0x0
10023 13:08:34.043989 INFO: [APUAPC] D12_APC_0: 0xffffffff
10024 13:08:34.047075 INFO: [APUAPC] D12_APC_1: 0xffffffff
10025 13:08:34.050850 INFO: [APUAPC] D12_APC_2: 0x3fffff
10026 13:08:34.053825 INFO: [APUAPC] D12_APC_3: 0x0
10027 13:08:34.057395 INFO: [APUAPC] D13_APC_0: 0xffffffff
10028 13:08:34.060280 INFO: [APUAPC] D13_APC_1: 0xffffffff
10029 13:08:34.064319 INFO: [APUAPC] D13_APC_2: 0x3fffff
10030 13:08:34.067271 INFO: [APUAPC] D13_APC_3: 0x0
10031 13:08:34.070660 INFO: [APUAPC] D14_APC_0: 0xffffffff
10032 13:08:34.073745 INFO: [APUAPC] D14_APC_1: 0xffffffff
10033 13:08:34.077056 INFO: [APUAPC] D14_APC_2: 0x3fffff
10034 13:08:34.080083 INFO: [APUAPC] D14_APC_3: 0x0
10035 13:08:34.083446 INFO: [APUAPC] D15_APC_0: 0xffffffff
10036 13:08:34.086723 INFO: [APUAPC] D15_APC_1: 0xffffffff
10037 13:08:34.090382 INFO: [APUAPC] D15_APC_2: 0x3fffff
10038 13:08:34.093505 INFO: [APUAPC] D15_APC_3: 0x0
10039 13:08:34.097069 INFO: [APUAPC] APC_CON: 0x4
10040 13:08:34.100384 INFO: [NOCDAPC] D0_APC_0: 0x0
10041 13:08:34.103310 INFO: [NOCDAPC] D0_APC_1: 0x0
10042 13:08:34.106556 INFO: [NOCDAPC] D1_APC_0: 0x0
10043 13:08:34.110394 INFO: [NOCDAPC] D1_APC_1: 0xfff
10044 13:08:34.113393 INFO: [NOCDAPC] D2_APC_0: 0x0
10045 13:08:34.117108 INFO: [NOCDAPC] D2_APC_1: 0xfff
10046 13:08:34.117197 INFO: [NOCDAPC] D3_APC_0: 0x0
10047 13:08:34.119867 INFO: [NOCDAPC] D3_APC_1: 0xfff
10048 13:08:34.123480 INFO: [NOCDAPC] D4_APC_0: 0x0
10049 13:08:34.127105 INFO: [NOCDAPC] D4_APC_1: 0xfff
10050 13:08:34.130176 INFO: [NOCDAPC] D5_APC_0: 0x0
10051 13:08:34.133290 INFO: [NOCDAPC] D5_APC_1: 0xfff
10052 13:08:34.136875 INFO: [NOCDAPC] D6_APC_0: 0x0
10053 13:08:34.140166 INFO: [NOCDAPC] D6_APC_1: 0xfff
10054 13:08:34.143137 INFO: [NOCDAPC] D7_APC_0: 0x0
10055 13:08:34.146859 INFO: [NOCDAPC] D7_APC_1: 0xfff
10056 13:08:34.149875 INFO: [NOCDAPC] D8_APC_0: 0x0
10057 13:08:34.149950 INFO: [NOCDAPC] D8_APC_1: 0xfff
10058 13:08:34.153150 INFO: [NOCDAPC] D9_APC_0: 0x0
10059 13:08:34.156584 INFO: [NOCDAPC] D9_APC_1: 0xfff
10060 13:08:34.160267 INFO: [NOCDAPC] D10_APC_0: 0x0
10061 13:08:34.163111 INFO: [NOCDAPC] D10_APC_1: 0xfff
10062 13:08:34.166453 INFO: [NOCDAPC] D11_APC_0: 0x0
10063 13:08:34.169870 INFO: [NOCDAPC] D11_APC_1: 0xfff
10064 13:08:34.173444 INFO: [NOCDAPC] D12_APC_0: 0x0
10065 13:08:34.176507 INFO: [NOCDAPC] D12_APC_1: 0xfff
10066 13:08:34.180229 INFO: [NOCDAPC] D13_APC_0: 0x0
10067 13:08:34.183184 INFO: [NOCDAPC] D13_APC_1: 0xfff
10068 13:08:34.186690 INFO: [NOCDAPC] D14_APC_0: 0x0
10069 13:08:34.189728 INFO: [NOCDAPC] D14_APC_1: 0xfff
10070 13:08:34.192959 INFO: [NOCDAPC] D15_APC_0: 0x0
10071 13:08:34.196474 INFO: [NOCDAPC] D15_APC_1: 0xfff
10072 13:08:34.196542 INFO: [NOCDAPC] APC_CON: 0x4
10073 13:08:34.199937 INFO: [APUAPC] set_apusys_apc done
10074 13:08:34.203626 INFO: [DEVAPC] devapc_init done
10075 13:08:34.209565 INFO: GICv3 without legacy support detected.
10076 13:08:34.213296 INFO: ARM GICv3 driver initialized in EL3
10077 13:08:34.216349 INFO: Maximum SPI INTID supported: 639
10078 13:08:34.219279 INFO: BL31: Initializing runtime services
10079 13:08:34.225918 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10080 13:08:34.229868 INFO: SPM: enable CPC mode
10081 13:08:34.232602 INFO: mcdi ready for mcusys-off-idle and system suspend
10082 13:08:34.239547 INFO: BL31: Preparing for EL3 exit to normal world
10083 13:08:34.242625 INFO: Entry point address = 0x80000000
10084 13:08:34.242724 INFO: SPSR = 0x8
10085 13:08:34.249808
10086 13:08:34.249884
10087 13:08:34.249942
10088 13:08:34.253688 Starting depthcharge on Spherion...
10089 13:08:34.253764
10090 13:08:34.253824 Wipe memory regions:
10091 13:08:34.253878
10092 13:08:34.254568 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10093 13:08:34.254660 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10094 13:08:34.254733 Setting prompt string to ['asurada:']
10095 13:08:34.254798 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10096 13:08:34.256450 [0x00000040000000, 0x00000054600000)
10097 13:08:34.378823
10098 13:08:34.378935 [0x00000054660000, 0x00000080000000)
10099 13:08:34.638964
10100 13:08:34.639091 [0x000000821a7280, 0x000000ffe64000)
10101 13:08:35.383870
10102 13:08:35.383997 [0x00000100000000, 0x00000240000000)
10103 13:08:37.274542
10104 13:08:37.277463 Initializing XHCI USB controller at 0x11200000.
10105 13:08:38.315570
10106 13:08:38.318519 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10107 13:08:38.318631
10108 13:08:38.318717
10109 13:08:38.319010 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10110 13:08:38.319114 Sending line: 'tftpboot 192.168.201.1 14878994/tftp-deploy-o87jl0sz/kernel/image.itb 14878994/tftp-deploy-o87jl0sz/kernel/cmdline '
10112 13:08:38.419607 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10113 13:08:38.419726 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10114 13:08:38.423609 asurada: tftpboot 192.168.201.1 14878994/tftp-deploy-o87jl0sz/kernel/image.itp-deploy-o87jl0sz/kernel/cmdline
10115 13:08:38.423688
10116 13:08:38.423761 Waiting for link
10117 13:08:38.582244
10118 13:08:38.582380 R8152: Initializing
10119 13:08:38.582469
10120 13:08:38.585095 Version 6 (ocp_data = 5c30)
10121 13:08:38.585164
10122 13:08:38.588612 R8152: Done initializing
10123 13:08:38.588702
10124 13:08:38.588786 Adding net device
10125 13:08:40.494724
10126 13:08:40.494846 done.
10127 13:08:40.494908
10128 13:08:40.494962 MAC: 00:24:32:30:78:ff
10129 13:08:40.495014
10130 13:08:40.498535 Sending DHCP discover... done.
10131 13:08:40.498615
10132 13:08:40.501411 Waiting for reply... done.
10133 13:08:40.501488
10134 13:08:40.505045 Sending DHCP request... done.
10135 13:08:40.505143
10136 13:08:40.509486 Waiting for reply... done.
10137 13:08:40.509563
10138 13:08:40.509621 My ip is 192.168.201.21
10139 13:08:40.509676
10140 13:08:40.512638 The DHCP server ip is 192.168.201.1
10141 13:08:40.512768
10142 13:08:40.519008 TFTP server IP predefined by user: 192.168.201.1
10143 13:08:40.519086
10144 13:08:40.525785 Bootfile predefined by user: 14878994/tftp-deploy-o87jl0sz/kernel/image.itb
10145 13:08:40.525883
10146 13:08:40.529105 Sending tftp read request... done.
10147 13:08:40.529196
10148 13:08:40.532895 Waiting for the transfer...
10149 13:08:40.532986
10150 13:08:41.059171 00000000 ################################################################
10151 13:08:41.059325
10152 13:08:41.580394 00080000 ################################################################
10153 13:08:41.580513
10154 13:08:42.103684 00100000 ################################################################
10155 13:08:42.103834
10156 13:08:42.635524 00180000 ################################################################
10157 13:08:42.635649
10158 13:08:43.169024 00200000 ################################################################
10159 13:08:43.169174
10160 13:08:43.690688 00280000 ################################################################
10161 13:08:43.690833
10162 13:08:44.230533 00300000 ################################################################
10163 13:08:44.230648
10164 13:08:44.800089 00380000 ################################################################
10165 13:08:44.800207
10166 13:08:45.414485 00400000 ################################################################
10167 13:08:45.414636
10168 13:08:45.950141 00480000 ################################################################
10169 13:08:45.950265
10170 13:08:46.532324 00500000 ################################################################
10171 13:08:46.532779
10172 13:08:47.109035 00580000 ################################################################
10173 13:08:47.109196
10174 13:08:47.656508 00600000 ################################################################
10175 13:08:47.656681
10176 13:08:48.211618 00680000 ################################################################
10177 13:08:48.211729
10178 13:08:48.765522 00700000 ################################################################
10179 13:08:48.765638
10180 13:08:49.373201 00780000 ################################################################
10181 13:08:49.373383
10182 13:08:49.966777 00800000 ################################################################
10183 13:08:49.967424
10184 13:08:50.644628 00880000 ################################################################
10185 13:08:50.645077
10186 13:08:51.266845 00900000 ################################################################
10187 13:08:51.266960
10188 13:08:51.884008 00980000 ################################################################
10189 13:08:51.884121
10190 13:08:52.518958 00a00000 ################################################################
10191 13:08:52.519480
10192 13:08:53.216978 00a80000 ################################################################
10193 13:08:53.217424
10194 13:08:53.898852 00b00000 ################################################################
10195 13:08:53.899327
10196 13:08:54.581195 00b80000 ################################################################
10197 13:08:54.581662
10198 13:08:55.253533 00c00000 ################################################################
10199 13:08:55.253985
10200 13:08:55.928828 00c80000 ################################################################
10201 13:08:55.928943
10202 13:08:56.599037 00d00000 ################################################################
10203 13:08:56.599463
10204 13:08:57.272040 00d80000 ################################################################
10205 13:08:57.272530
10206 13:08:57.923783 00e00000 ################################################################
10207 13:08:57.924284
10208 13:08:58.612953 00e80000 ################################################################
10209 13:08:58.613164
10210 13:08:59.259155 00f00000 ################################################################
10211 13:08:59.259303
10212 13:08:59.821769 00f80000 ################################################################
10213 13:08:59.821898
10214 13:09:00.387948 01000000 ################################################################
10215 13:09:00.388063
10216 13:09:00.963043 01080000 ################################################################
10217 13:09:00.963159
10218 13:09:01.541513 01100000 ################################################################
10219 13:09:01.541634
10220 13:09:02.115515 01180000 ################################################################
10221 13:09:02.115629
10222 13:09:02.739745 01200000 ################################################################
10223 13:09:02.740201
10224 13:09:03.379686 01280000 ################################################################
10225 13:09:03.380066
10226 13:09:04.031285 01300000 ################################################################
10227 13:09:04.031871
10228 13:09:04.743231 01380000 ################################################################
10229 13:09:04.743362
10230 13:09:05.434293 01400000 ################################################################
10231 13:09:05.434425
10232 13:09:06.020010 01480000 ################################################################
10233 13:09:06.020124
10234 13:09:06.598781 01500000 ################################################################
10235 13:09:06.598898
10236 13:09:07.179653 01580000 ################################################################
10237 13:09:07.179768
10238 13:09:07.887557 01600000 ################################################################
10239 13:09:07.887670
10240 13:09:08.599883 01680000 ################################################################
10241 13:09:08.600009
10242 13:09:09.187306 01700000 ################################################################
10243 13:09:09.187416
10244 13:09:09.751909 01780000 ################################################################
10245 13:09:09.752045
10246 13:09:10.349231 01800000 ################################################################
10247 13:09:10.349351
10248 13:09:10.942751 01880000 ################################################################
10249 13:09:10.942869
10250 13:09:11.520201 01900000 ################################################################
10251 13:09:11.520321
10252 13:09:12.090915 01980000 ################################################################
10253 13:09:12.091038
10254 13:09:12.668750 01a00000 ################################################################
10255 13:09:12.668867
10256 13:09:13.244534 01a80000 ################################################################
10257 13:09:13.244653
10258 13:09:13.829726 01b00000 ################################################################
10259 13:09:13.829903
10260 13:09:14.381479 01b80000 ################################################################
10261 13:09:14.381605
10262 13:09:14.972020 01c00000 ################################################################
10263 13:09:14.972176
10264 13:09:15.546433 01c80000 ################################################################
10265 13:09:15.546597
10266 13:09:16.129563 01d00000 ################################################################
10267 13:09:16.129724
10268 13:09:16.693009 01d80000 ################################################################
10269 13:09:16.693137
10270 13:09:17.213733 01e00000 #################################################### done.
10271 13:09:17.213853
10272 13:09:17.217412 The bootfile was 31881938 bytes long.
10273 13:09:17.217491
10274 13:09:17.220258 Sending tftp read request... done.
10275 13:09:17.220334
10276 13:09:17.220392 Waiting for the transfer...
10277 13:09:17.220446
10278 13:09:17.224024 00000000 # done.
10279 13:09:17.224127
10280 13:09:17.230255 Command line loaded dynamically from TFTP file: 14878994/tftp-deploy-o87jl0sz/kernel/cmdline
10281 13:09:17.230331
10282 13:09:17.253191 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14878994/extract-nfsrootfs-wgu7z_rn,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10283 13:09:17.253314
10284 13:09:17.253403 Loading FIT.
10285 13:09:17.253490
10286 13:09:17.256405 Image ramdisk-1 has 18718181 bytes.
10287 13:09:17.256499
10288 13:09:17.259760 Image fdt-1 has 47258 bytes.
10289 13:09:17.259855
10290 13:09:17.263249 Image kernel-1 has 13114469 bytes.
10291 13:09:17.263320
10292 13:09:17.273436 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10293 13:09:17.273511
10294 13:09:17.289741 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10295 13:09:17.289833
10296 13:09:17.296722 Choosing best match conf-1 for compat google,spherion-rev2.
10297 13:09:17.296821
10298 13:09:17.304327 Connected to device vid:did:rid of 1ae0:0028:00
10299 13:09:17.310866
10300 13:09:17.314349 tpm_get_response: command 0x17b, return code 0x0
10301 13:09:17.314422
10302 13:09:17.317478 ec_init: CrosEC protocol v3 supported (256, 248)
10303 13:09:17.321630
10304 13:09:17.325136 tpm_cleanup: add release locality here.
10305 13:09:17.325232
10306 13:09:17.325318 Shutting down all USB controllers.
10307 13:09:17.328607
10308 13:09:17.328700 Removing current net device
10309 13:09:17.328788
10310 13:09:17.335022 Exiting depthcharge with code 4 at timestamp: 72373018
10311 13:09:17.335124
10312 13:09:17.338446 LZMA decompressing kernel-1 to 0x821a6718
10313 13:09:17.338541
10314 13:09:17.341847 LZMA decompressing kernel-1 to 0x40000000
10315 13:09:18.956890
10316 13:09:18.957050 jumping to kernel
10317 13:09:18.957585 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10318 13:09:18.957716 start: 2.2.5 auto-login-action (timeout 00:03:36) [common]
10319 13:09:18.957820 Setting prompt string to ['Linux version [0-9]']
10320 13:09:18.957913 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10321 13:09:18.958011 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10322 13:09:19.037289
10323 13:09:19.040674 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10324 13:09:19.044134 start: 2.2.5.1 login-action (timeout 00:03:35) [common]
10325 13:09:19.044279 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10326 13:09:19.044377 Setting prompt string to []
10327 13:09:19.044485 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10328 13:09:19.044594 Using line separator: #'\n'#
10329 13:09:19.044679 No login prompt set.
10330 13:09:19.044772 Parsing kernel messages
10331 13:09:19.044854 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10332 13:09:19.045048 [login-action] Waiting for messages, (timeout 00:03:35)
10333 13:09:19.045138 Waiting using forced prompt support (timeout 00:01:48)
10334 13:09:19.063778 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j272990-arm64-gcc-12-defconfig-arm64-chromebook-fgzcq) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024
10335 13:09:19.067550 [ 0.000000] random: crng init done
10336 13:09:19.070722 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10337 13:09:19.073827 [ 0.000000] efi: UEFI not found.
10338 13:09:19.083567 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10339 13:09:19.090487 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10340 13:09:19.100090 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10341 13:09:19.110002 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10342 13:09:19.116533 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10343 13:09:19.119820 [ 0.000000] printk: bootconsole [mtk8250] enabled
10344 13:09:19.128594 [ 0.000000] NUMA: No NUMA configuration found
10345 13:09:19.135289 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10346 13:09:19.141358 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10347 13:09:19.141502 [ 0.000000] Zone ranges:
10348 13:09:19.148283 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10349 13:09:19.151613 [ 0.000000] DMA32 empty
10350 13:09:19.158243 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10351 13:09:19.161503 [ 0.000000] Movable zone start for each node
10352 13:09:19.165283 [ 0.000000] Early memory node ranges
10353 13:09:19.171537 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10354 13:09:19.177919 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10355 13:09:19.184986 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10356 13:09:19.191327 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10357 13:09:19.197624 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10358 13:09:19.204839 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10359 13:09:19.261662 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10360 13:09:19.268623 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10361 13:09:19.274642 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10362 13:09:19.278447 [ 0.000000] psci: probing for conduit method from DT.
10363 13:09:19.284851 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10364 13:09:19.288176 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10365 13:09:19.295070 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10366 13:09:19.298359 [ 0.000000] psci: SMC Calling Convention v1.2
10367 13:09:19.304864 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10368 13:09:19.308342 [ 0.000000] Detected VIPT I-cache on CPU0
10369 13:09:19.314866 [ 0.000000] CPU features: detected: GIC system register CPU interface
10370 13:09:19.321314 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10371 13:09:19.328082 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10372 13:09:19.334812 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10373 13:09:19.341128 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10374 13:09:19.351330 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10375 13:09:19.354460 [ 0.000000] alternatives: applying boot alternatives
10376 13:09:19.361012 [ 0.000000] Fallback order for Node 0: 0
10377 13:09:19.368073 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10378 13:09:19.370912 [ 0.000000] Policy zone: Normal
10379 13:09:19.394029 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14878994/extract-nfsrootfs-wgu7z_rn,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10380 13:09:19.404075 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10381 13:09:19.414425 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10382 13:09:19.424256 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10383 13:09:19.430642 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10384 13:09:19.433844 <6>[ 0.000000] software IO TLB: area num 8.
10385 13:09:19.490651 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10386 13:09:19.639693 <6>[ 0.000000] Memory: 7945780K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 406988K reserved, 32768K cma-reserved)
10387 13:09:19.646433 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10388 13:09:19.653205 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10389 13:09:19.656148 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10390 13:09:19.663021 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10391 13:09:19.669551 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10392 13:09:19.672916 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10393 13:09:19.682734 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10394 13:09:19.689830 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10395 13:09:19.695990 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10396 13:09:19.702745 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10397 13:09:19.705988 <6>[ 0.000000] GICv3: 608 SPIs implemented
10398 13:09:19.709711 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10399 13:09:19.715631 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10400 13:09:19.719132 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10401 13:09:19.726467 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10402 13:09:19.739148 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10403 13:09:19.749054 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10404 13:09:19.759141 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10405 13:09:19.766286 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10406 13:09:19.779857 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10407 13:09:19.786398 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10408 13:09:19.792772 <6>[ 0.009232] Console: colour dummy device 80x25
10409 13:09:19.802796 <6>[ 0.013963] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10410 13:09:19.809471 <6>[ 0.024470] pid_max: default: 32768 minimum: 301
10411 13:09:19.812407 <6>[ 0.029342] LSM: Security Framework initializing
10412 13:09:19.819893 <6>[ 0.034281] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10413 13:09:19.829303 <6>[ 0.042093] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10414 13:09:19.836209 <6>[ 0.051561] cblist_init_generic: Setting adjustable number of callback queues.
10415 13:09:19.842476 <6>[ 0.059001] cblist_init_generic: Setting shift to 3 and lim to 1.
10416 13:09:19.852640 <6>[ 0.065341] cblist_init_generic: Setting adjustable number of callback queues.
10417 13:09:19.859180 <6>[ 0.072767] cblist_init_generic: Setting shift to 3 and lim to 1.
10418 13:09:19.862714 <6>[ 0.079166] rcu: Hierarchical SRCU implementation.
10419 13:09:19.869446 <6>[ 0.084181] rcu: Max phase no-delay instances is 1000.
10420 13:09:19.875791 <6>[ 0.091215] EFI services will not be available.
10421 13:09:19.878625 <6>[ 0.096176] smp: Bringing up secondary CPUs ...
10422 13:09:19.887463 <6>[ 0.101256] Detected VIPT I-cache on CPU1
10423 13:09:19.893880 <6>[ 0.101328] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10424 13:09:19.900265 <6>[ 0.101361] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10425 13:09:19.903828 <6>[ 0.101706] Detected VIPT I-cache on CPU2
10426 13:09:19.913481 <6>[ 0.101759] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10427 13:09:19.920525 <6>[ 0.101777] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10428 13:09:19.923264 <6>[ 0.102040] Detected VIPT I-cache on CPU3
10429 13:09:19.930165 <6>[ 0.102088] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10430 13:09:19.936454 <6>[ 0.102102] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10431 13:09:19.940135 <6>[ 0.102412] CPU features: detected: Spectre-v4
10432 13:09:19.946912 <6>[ 0.102418] CPU features: detected: Spectre-BHB
10433 13:09:19.950207 <6>[ 0.102424] Detected PIPT I-cache on CPU4
10434 13:09:19.956833 <6>[ 0.102488] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10435 13:09:19.963234 <6>[ 0.102505] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10436 13:09:19.969993 <6>[ 0.102802] Detected PIPT I-cache on CPU5
10437 13:09:19.976994 <6>[ 0.102867] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10438 13:09:19.983313 <6>[ 0.102883] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10439 13:09:19.986935 <6>[ 0.103165] Detected PIPT I-cache on CPU6
10440 13:09:19.993242 <6>[ 0.103231] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10441 13:09:19.999950 <6>[ 0.103247] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10442 13:09:20.006374 <6>[ 0.103545] Detected PIPT I-cache on CPU7
10443 13:09:20.013374 <6>[ 0.103611] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10444 13:09:20.019942 <6>[ 0.103627] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10445 13:09:20.023382 <6>[ 0.103675] smp: Brought up 1 node, 8 CPUs
10446 13:09:20.029546 <6>[ 0.245084] SMP: Total of 8 processors activated.
10447 13:09:20.033398 <6>[ 0.250005] CPU features: detected: 32-bit EL0 Support
10448 13:09:20.042865 <6>[ 0.255368] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10449 13:09:20.049272 <6>[ 0.264168] CPU features: detected: Common not Private translations
10450 13:09:20.056504 <6>[ 0.270644] CPU features: detected: CRC32 instructions
10451 13:09:20.059582 <6>[ 0.275995] CPU features: detected: RCpc load-acquire (LDAPR)
10452 13:09:20.065949 <6>[ 0.281955] CPU features: detected: LSE atomic instructions
10453 13:09:20.072813 <6>[ 0.287736] CPU features: detected: Privileged Access Never
10454 13:09:20.079400 <6>[ 0.293552] CPU features: detected: RAS Extension Support
10455 13:09:20.085990 <6>[ 0.299160] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10456 13:09:20.089112 <6>[ 0.306425] CPU: All CPU(s) started at EL2
10457 13:09:20.095672 <6>[ 0.310741] alternatives: applying system-wide alternatives
10458 13:09:20.105290 <6>[ 0.321619] devtmpfs: initialized
10459 13:09:20.117212 <6>[ 0.330378] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10460 13:09:20.127453 <6>[ 0.340338] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10461 13:09:20.133946 <6>[ 0.348584] pinctrl core: initialized pinctrl subsystem
10462 13:09:20.136916 <6>[ 0.355436] DMI not present or invalid.
10463 13:09:20.143937 <6>[ 0.359857] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10464 13:09:20.154081 <6>[ 0.366756] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10465 13:09:20.160328 <6>[ 0.374342] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10466 13:09:20.170629 <6>[ 0.382573] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10467 13:09:20.173641 <6>[ 0.390824] audit: initializing netlink subsys (disabled)
10468 13:09:20.183322 <5>[ 0.396519] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10469 13:09:20.190823 <6>[ 0.397280] thermal_sys: Registered thermal governor 'step_wise'
10470 13:09:20.196839 <6>[ 0.404487] thermal_sys: Registered thermal governor 'power_allocator'
10471 13:09:20.200074 <6>[ 0.410742] cpuidle: using governor menu
10472 13:09:20.206438 <6>[ 0.421704] NET: Registered PF_QIPCRTR protocol family
10473 13:09:20.213123 <6>[ 0.427217] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10474 13:09:20.219756 <6>[ 0.434319] ASID allocator initialised with 32768 entries
10475 13:09:20.222993 <6>[ 0.440948] Serial: AMBA PL011 UART driver
10476 13:09:20.234715 <4>[ 0.451047] Trying to register duplicate clock ID: 134
10477 13:09:20.294802 <6>[ 0.514621] KASLR enabled
10478 13:09:20.308986 <6>[ 0.522266] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10479 13:09:20.315663 <6>[ 0.529280] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10480 13:09:20.322571 <6>[ 0.535767] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10481 13:09:20.328914 <6>[ 0.542771] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10482 13:09:20.335878 <6>[ 0.549260] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10483 13:09:20.341998 <6>[ 0.556263] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10484 13:09:20.348882 <6>[ 0.562749] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10485 13:09:20.355216 <6>[ 0.569756] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10486 13:09:20.358828 <6>[ 0.577238] ACPI: Interpreter disabled.
10487 13:09:20.367458 <6>[ 0.583763] iommu: Default domain type: Translated
10488 13:09:20.374073 <6>[ 0.588875] iommu: DMA domain TLB invalidation policy: strict mode
10489 13:09:20.377173 <5>[ 0.595531] SCSI subsystem initialized
10490 13:09:20.383989 <6>[ 0.599781] usbcore: registered new interface driver usbfs
10491 13:09:20.390585 <6>[ 0.605516] usbcore: registered new interface driver hub
10492 13:09:20.393807 <6>[ 0.611067] usbcore: registered new device driver usb
10493 13:09:20.401027 <6>[ 0.617232] pps_core: LinuxPPS API ver. 1 registered
10494 13:09:20.410805 <6>[ 0.622426] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10495 13:09:20.413720 <6>[ 0.631767] PTP clock support registered
10496 13:09:20.417073 <6>[ 0.636008] EDAC MC: Ver: 3.0.0
10497 13:09:20.425005 <6>[ 0.641250] FPGA manager framework
10498 13:09:20.428236 <6>[ 0.644927] Advanced Linux Sound Architecture Driver Initialized.
10499 13:09:20.431846 <6>[ 0.651726] vgaarb: loaded
10500 13:09:20.438519 <6>[ 0.654901] clocksource: Switched to clocksource arch_sys_counter
10501 13:09:20.445508 <5>[ 0.661349] VFS: Disk quotas dquot_6.6.0
10502 13:09:20.451908 <6>[ 0.665536] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10503 13:09:20.455181 <6>[ 0.672726] pnp: PnP ACPI: disabled
10504 13:09:20.462789 <6>[ 0.679517] NET: Registered PF_INET protocol family
10505 13:09:20.472758 <6>[ 0.685128] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10506 13:09:20.484652 <6>[ 0.697474] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10507 13:09:20.493985 <6>[ 0.706290] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10508 13:09:20.501477 <6>[ 0.714261] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10509 13:09:20.510847 <6>[ 0.722963] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10510 13:09:20.517153 <6>[ 0.732677] TCP: Hash tables configured (established 65536 bind 65536)
10511 13:09:20.524090 <6>[ 0.739543] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10512 13:09:20.534092 <6>[ 0.746739] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10513 13:09:20.540434 <6>[ 0.754448] NET: Registered PF_UNIX/PF_LOCAL protocol family
10514 13:09:20.543574 <6>[ 0.760545] RPC: Registered named UNIX socket transport module.
10515 13:09:20.550147 <6>[ 0.766696] RPC: Registered udp transport module.
10516 13:09:20.553281 <6>[ 0.771627] RPC: Registered tcp transport module.
10517 13:09:20.560269 <6>[ 0.776560] RPC: Registered tcp NFSv4.1 backchannel transport module.
10518 13:09:20.566764 <6>[ 0.783227] PCI: CLS 0 bytes, default 64
10519 13:09:20.570417 <6>[ 0.787618] Unpacking initramfs...
10520 13:09:20.593770 <6>[ 0.807008] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10521 13:09:20.603900 <6>[ 0.815674] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10522 13:09:20.607252 <6>[ 0.824537] kvm [1]: IPA Size Limit: 40 bits
10523 13:09:20.613756 <6>[ 0.829062] kvm [1]: GICv3: no GICV resource entry
10524 13:09:20.617091 <6>[ 0.834082] kvm [1]: disabling GICv2 emulation
10525 13:09:20.623367 <6>[ 0.838768] kvm [1]: GIC system register CPU interface enabled
10526 13:09:20.627096 <6>[ 0.844940] kvm [1]: vgic interrupt IRQ18
10527 13:09:20.633700 <6>[ 0.849290] kvm [1]: VHE mode initialized successfully
10528 13:09:20.640222 <5>[ 0.855794] Initialise system trusted keyrings
10529 13:09:20.646811 <6>[ 0.860623] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10530 13:09:20.654155 <6>[ 0.870565] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10531 13:09:20.660765 <5>[ 0.876924] NFS: Registering the id_resolver key type
10532 13:09:20.664018 <5>[ 0.882226] Key type id_resolver registered
10533 13:09:20.671093 <5>[ 0.886642] Key type id_legacy registered
10534 13:09:20.677319 <6>[ 0.890921] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10535 13:09:20.683926 <6>[ 0.897843] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10536 13:09:20.690167 <6>[ 0.905536] 9p: Installing v9fs 9p2000 file system support
10537 13:09:20.726841 <5>[ 0.943102] Key type asymmetric registered
10538 13:09:20.729747 <5>[ 0.947434] Asymmetric key parser 'x509' registered
10539 13:09:20.739998 <6>[ 0.952571] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10540 13:09:20.743175 <6>[ 0.960192] io scheduler mq-deadline registered
10541 13:09:20.746313 <6>[ 0.964950] io scheduler kyber registered
10542 13:09:20.766322 <6>[ 0.982912] EINJ: ACPI disabled.
10543 13:09:20.799940 <4>[ 1.009608] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10544 13:09:20.809379 <4>[ 1.020311] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10545 13:09:20.825662 <6>[ 1.041717] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10546 13:09:20.833399 <6>[ 1.049737] printk: console [ttyS0] disabled
10547 13:09:20.861067 <6>[ 1.074367] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10548 13:09:20.868004 <6>[ 1.083828] printk: console [ttyS0] enabled
10549 13:09:20.871028 <6>[ 1.083828] printk: console [ttyS0] enabled
10550 13:09:20.877783 <6>[ 1.092723] printk: bootconsole [mtk8250] disabled
10551 13:09:20.881124 <6>[ 1.092723] printk: bootconsole [mtk8250] disabled
10552 13:09:20.887577 <6>[ 1.103994] SuperH (H)SCI(F) driver initialized
10553 13:09:20.890956 <6>[ 1.109285] msm_serial: driver initialized
10554 13:09:20.905736 <6>[ 1.118400] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10555 13:09:20.915115 <6>[ 1.126957] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10556 13:09:20.921772 <6>[ 1.135500] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10557 13:09:20.931820 <6>[ 1.144134] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10558 13:09:20.941951 <6>[ 1.152841] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10559 13:09:20.948415 <6>[ 1.161555] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10560 13:09:20.958539 <6>[ 1.170097] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10561 13:09:20.964765 <6>[ 1.178910] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10562 13:09:20.975079 <6>[ 1.187452] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10563 13:09:20.986331 <6>[ 1.203061] loop: module loaded
10564 13:09:20.993560 <6>[ 1.209125] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10565 13:09:21.016226 <4>[ 1.232643] mtk-pmic-keys: Failed to locate of_node [id: -1]
10566 13:09:21.023181 <6>[ 1.239682] megasas: 07.719.03.00-rc1
10567 13:09:21.033004 <6>[ 1.249520] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10568 13:09:21.045691 <6>[ 1.262297] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10569 13:09:21.062755 <6>[ 1.279094] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10570 13:09:21.119996 <6>[ 1.329501] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10571 13:09:21.361386 <6>[ 1.578113] Freeing initrd memory: 18276K
10572 13:09:21.373003 <6>[ 1.589767] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10573 13:09:21.384386 <6>[ 1.600925] tun: Universal TUN/TAP device driver, 1.6
10574 13:09:21.387839 <6>[ 1.607036] thunder_xcv, ver 1.0
10575 13:09:21.390865 <6>[ 1.610534] thunder_bgx, ver 1.0
10576 13:09:21.394480 <6>[ 1.614031] nicpf, ver 1.0
10577 13:09:21.405051 <6>[ 1.618085] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10578 13:09:21.408429 <6>[ 1.625561] hns3: Copyright (c) 2017 Huawei Corporation.
10579 13:09:21.412030 <6>[ 1.631156] hclge is initializing
10580 13:09:21.418445 <6>[ 1.634735] e1000: Intel(R) PRO/1000 Network Driver
10581 13:09:21.425027 <6>[ 1.639865] e1000: Copyright (c) 1999-2006 Intel Corporation.
10582 13:09:21.428394 <6>[ 1.645881] e1000e: Intel(R) PRO/1000 Network Driver
10583 13:09:21.434944 <6>[ 1.651098] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10584 13:09:21.441494 <6>[ 1.657283] igb: Intel(R) Gigabit Ethernet Network Driver
10585 13:09:21.448328 <6>[ 1.662933] igb: Copyright (c) 2007-2014 Intel Corporation.
10586 13:09:21.454949 <6>[ 1.668770] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10587 13:09:21.461874 <6>[ 1.675289] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10588 13:09:21.464673 <6>[ 1.681760] sky2: driver version 1.30
10589 13:09:21.471466 <6>[ 1.686726] usbcore: registered new device driver r8152-cfgselector
10590 13:09:21.478061 <6>[ 1.693264] usbcore: registered new interface driver r8152
10591 13:09:21.481344 <6>[ 1.699082] VFIO - User Level meta-driver version: 0.3
10592 13:09:21.490891 <6>[ 1.707393] usbcore: registered new interface driver usb-storage
10593 13:09:21.497567 <6>[ 1.713841] usbcore: registered new device driver onboard-usb-hub
10594 13:09:21.506664 <6>[ 1.723089] mt6397-rtc mt6359-rtc: registered as rtc0
10595 13:09:21.517032 <6>[ 1.728553] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-18T13:09:21 UTC (1721308161)
10596 13:09:21.519927 <6>[ 1.738137] i2c_dev: i2c /dev entries driver
10597 13:09:21.533894 <4>[ 1.750449] cpu cpu0: supply cpu not found, using dummy regulator
10598 13:09:21.540891 <4>[ 1.756874] cpu cpu1: supply cpu not found, using dummy regulator
10599 13:09:21.547704 <4>[ 1.763296] cpu cpu2: supply cpu not found, using dummy regulator
10600 13:09:21.553918 <4>[ 1.769700] cpu cpu3: supply cpu not found, using dummy regulator
10601 13:09:21.561126 <4>[ 1.776098] cpu cpu4: supply cpu not found, using dummy regulator
10602 13:09:21.567279 <4>[ 1.782499] cpu cpu5: supply cpu not found, using dummy regulator
10603 13:09:21.574069 <4>[ 1.788895] cpu cpu6: supply cpu not found, using dummy regulator
10604 13:09:21.580352 <4>[ 1.795308] cpu cpu7: supply cpu not found, using dummy regulator
10605 13:09:21.599189 <6>[ 1.815944] cpu cpu0: EM: created perf domain
10606 13:09:21.602934 <6>[ 1.820856] cpu cpu4: EM: created perf domain
10607 13:09:21.609854 <6>[ 1.826492] sdhci: Secure Digital Host Controller Interface driver
10608 13:09:21.616376 <6>[ 1.832924] sdhci: Copyright(c) Pierre Ossman
10609 13:09:21.623118 <6>[ 1.837883] Synopsys Designware Multimedia Card Interface Driver
10610 13:09:21.629966 <6>[ 1.844538] sdhci-pltfm: SDHCI platform and OF driver helper
10611 13:09:21.633244 <6>[ 1.844660] mmc0: CQHCI version 5.10
10612 13:09:21.639693 <6>[ 1.854669] ledtrig-cpu: registered to indicate activity on CPUs
10613 13:09:21.646593 <6>[ 1.861710] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10614 13:09:21.653328 <6>[ 1.868768] usbcore: registered new interface driver usbhid
10615 13:09:21.656672 <6>[ 1.874590] usbhid: USB HID core driver
10616 13:09:21.663174 <6>[ 1.878795] spi_master spi0: will run message pump with realtime priority
10617 13:09:21.708467 <6>[ 1.918415] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10618 13:09:21.728681 <6>[ 1.934704] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10619 13:09:21.731305 <6>[ 1.944305] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10620 13:09:21.740465 <6>[ 1.956487] cros-ec-spi spi0.0: Chrome EC device registered
10621 13:09:21.747581 <6>[ 1.962560] mmc0: Command Queue Engine enabled
10622 13:09:21.753372 <6>[ 1.967317] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10623 13:09:21.757352 <6>[ 1.975054] mmcblk0: mmc0:0001 DA4128 116 GiB
10624 13:09:21.770190 <6>[ 1.986706] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10625 13:09:21.778699 <6>[ 1.994865] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10626 13:09:21.788473 <6>[ 1.998013] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10627 13:09:21.791497 <6>[ 2.001032] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10628 13:09:21.798476 <6>[ 2.010433] NET: Registered PF_PACKET protocol family
10629 13:09:21.804793 <6>[ 2.015371] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10630 13:09:21.808127 <6>[ 2.019998] 9pnet: Installing 9P2000 support
10631 13:09:21.815290 <5>[ 2.031003] Key type dns_resolver registered
10632 13:09:21.818260 <6>[ 2.035950] registered taskstats version 1
10633 13:09:21.824687 <5>[ 2.040337] Loading compiled-in X.509 certificates
10634 13:09:21.852894 <4>[ 2.062754] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10635 13:09:21.862948 <4>[ 2.073499] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10636 13:09:21.877216 <6>[ 2.093842] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10637 13:09:21.883942 <6>[ 2.100587] xhci-mtk 11200000.usb: xHCI Host Controller
10638 13:09:21.890633 <6>[ 2.106086] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10639 13:09:21.901010 <6>[ 2.113938] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10640 13:09:21.907249 <6>[ 2.123367] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10641 13:09:21.913918 <6>[ 2.129559] xhci-mtk 11200000.usb: xHCI Host Controller
10642 13:09:21.920915 <6>[ 2.135082] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10643 13:09:21.927385 <6>[ 2.142735] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10644 13:09:21.933998 <6>[ 2.150620] hub 1-0:1.0: USB hub found
10645 13:09:21.937610 <6>[ 2.154661] hub 1-0:1.0: 1 port detected
10646 13:09:21.943973 <6>[ 2.158962] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10647 13:09:21.951655 <6>[ 2.167803] hub 2-0:1.0: USB hub found
10648 13:09:21.954602 <6>[ 2.171828] hub 2-0:1.0: 1 port detected
10649 13:09:21.963423 <6>[ 2.179903] mtk-msdc 11f70000.mmc: Got CD GPIO
10650 13:09:21.976782 <6>[ 2.190106] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10651 13:09:21.986866 <6>[ 2.198476] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10652 13:09:21.993932 <6>[ 2.206819] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10653 13:09:22.003469 <6>[ 2.215164] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10654 13:09:22.010230 <6>[ 2.223503] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10655 13:09:22.019950 <6>[ 2.231844] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10656 13:09:22.026933 <6>[ 2.240182] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10657 13:09:22.036592 <6>[ 2.248522] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10658 13:09:22.043261 <6>[ 2.256862] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10659 13:09:22.053827 <6>[ 2.265201] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10660 13:09:22.059737 <6>[ 2.273539] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10661 13:09:22.069597 <6>[ 2.281884] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10662 13:09:22.076530 <6>[ 2.290224] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10663 13:09:22.086677 <6>[ 2.298561] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10664 13:09:22.093092 <6>[ 2.306901] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10665 13:09:22.099528 <6>[ 2.315603] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10666 13:09:22.106404 <6>[ 2.322779] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10667 13:09:22.112821 <6>[ 2.329551] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10668 13:09:22.122851 <6>[ 2.336359] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10669 13:09:22.129903 <6>[ 2.343299] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10670 13:09:22.136474 <6>[ 2.350187] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10671 13:09:22.146016 <6>[ 2.359323] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10672 13:09:22.156115 <6>[ 2.368444] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10673 13:09:22.165882 <6>[ 2.377740] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10674 13:09:22.175589 <6>[ 2.387208] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10675 13:09:22.185531 <6>[ 2.396680] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10676 13:09:22.192257 <6>[ 2.405800] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10677 13:09:22.202322 <6>[ 2.415269] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10678 13:09:22.212029 <6>[ 2.424392] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10679 13:09:22.221762 <6>[ 2.433687] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10680 13:09:22.232212 <6>[ 2.443846] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10681 13:09:22.242816 <6>[ 2.455873] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10682 13:09:22.250489 <6>[ 2.467051] Trying to probe devices needed for running init ...
10683 13:09:22.261392 <3>[ 2.474199] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10684 13:09:22.369822 <6>[ 2.583185] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10685 13:09:22.524203 <6>[ 2.740809] hub 1-1:1.0: USB hub found
10686 13:09:22.527643 <6>[ 2.745186] hub 1-1:1.0: 4 ports detected
10687 13:09:22.537616 <6>[ 2.754103] hub 1-1:1.0: USB hub found
10688 13:09:22.540699 <6>[ 2.758537] hub 1-1:1.0: 4 ports detected
10689 13:09:22.650084 <6>[ 2.863230] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10690 13:09:22.676555 <6>[ 2.893235] hub 2-1:1.0: USB hub found
10691 13:09:22.679874 <6>[ 2.897744] hub 2-1:1.0: 3 ports detected
10692 13:09:22.692887 <6>[ 2.908892] hub 2-1:1.0: USB hub found
10693 13:09:22.695764 <6>[ 2.913396] hub 2-1:1.0: 3 ports detected
10694 13:09:22.862028 <6>[ 3.075217] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10695 13:09:22.994694 <6>[ 3.210990] hub 1-1.4:1.0: USB hub found
10696 13:09:22.997636 <6>[ 3.215641] hub 1-1.4:1.0: 2 ports detected
10697 13:09:23.009742 <6>[ 3.226367] hub 1-1.4:1.0: USB hub found
10698 13:09:23.012823 <6>[ 3.230879] hub 1-1.4:1.0: 2 ports detected
10699 13:09:23.081838 <6>[ 3.295300] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10700 13:09:23.190430 <6>[ 3.403844] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10701 13:09:23.226917 <4>[ 3.440240] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10702 13:09:23.236749 <4>[ 3.449397] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10703 13:09:23.271902 <6>[ 3.488464] r8152 2-1.3:1.0 eth0: v1.12.13
10704 13:09:23.321341 <6>[ 3.535034] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10705 13:09:23.513994 <6>[ 3.727238] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10706 13:09:24.927873 <6>[ 5.144676] r8152 2-1.3:1.0 eth0: carrier on
10707 13:09:27.782260 <5>[ 5.175027] Sending DHCP requests .., OK
10708 13:09:27.788670 <6>[ 8.003581] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10709 13:09:27.792096 <6>[ 8.011907] IP-Config: Complete:
10710 13:09:27.805064 <6>[ 8.015406] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10711 13:09:27.811871 <6>[ 8.026111] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10712 13:09:27.821756 <6>[ 8.034729] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10713 13:09:27.825015 <6>[ 8.034739] nameserver0=192.168.201.1
10714 13:09:27.828245 <6>[ 8.046928] clk: Disabling unused clocks
10715 13:09:27.832247 <6>[ 8.052431] ALSA device list:
10716 13:09:27.840204 <6>[ 8.055704] No soundcards found.
10717 13:09:27.845955 <6>[ 8.063230] Freeing unused kernel memory: 8512K
10718 13:09:27.849598 <6>[ 8.068115] Run /init as init process
10719 13:09:27.858840 Loading, please wait...
10720 13:09:27.885103 Starting systemd-udevd version 252.22-1~deb12u1
10721 13:09:28.115263 <6>[ 8.329228] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10722 13:09:28.121846 <6>[ 8.331328] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10723 13:09:28.131708 <6>[ 8.344627] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10724 13:09:28.135100 <6>[ 8.351632] remoteproc remoteproc0: scp is available
10725 13:09:28.145241 <6>[ 8.354460] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10726 13:09:28.151869 <6>[ 8.360673] remoteproc remoteproc0: powering up scp
10727 13:09:28.158468 <6>[ 8.372603] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10728 13:09:28.165016 <6>[ 8.381113] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10729 13:09:28.175067 <6>[ 8.388132] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10730 13:09:28.190294 <6>[ 8.403845] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10731 13:09:28.196591 <6>[ 8.412014] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10732 13:09:28.206273 <4>[ 8.412148] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10733 13:09:28.213494 <4>[ 8.420083] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10734 13:09:28.223133 <6>[ 8.437162] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10735 13:09:28.230047 <3>[ 8.438026] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10736 13:09:28.239624 <4>[ 8.439920] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10737 13:09:28.246272 <6>[ 8.445454] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10738 13:09:28.253183 <3>[ 8.453456] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10739 13:09:28.263441 <6>[ 8.462134] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10740 13:09:28.269958 <3>[ 8.468694] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10741 13:09:28.279536 <6>[ 8.476763] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10742 13:09:28.282738 <6>[ 8.480152] mc: Linux media interface: v0.10
10743 13:09:28.289801 <3>[ 8.493209] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10744 13:09:28.299746 <6>[ 8.500574] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10745 13:09:28.309093 <6>[ 8.500581] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10746 13:09:28.315788 <6>[ 8.501885] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10747 13:09:28.322819 <3>[ 8.505200] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10748 13:09:28.329704 <6>[ 8.508306] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10749 13:09:28.339692 <6>[ 8.512261] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10750 13:09:28.346295 <6>[ 8.512267] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10751 13:09:28.352842 <6>[ 8.512271] remoteproc remoteproc0: remote processor scp is now up
10752 13:09:28.359859 <6>[ 8.513238] pci_bus 0000:00: root bus resource [bus 00-ff]
10753 13:09:28.365938 <3>[ 8.521046] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10754 13:09:28.373401 <3>[ 8.521054] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10755 13:09:28.380014 <6>[ 8.528467] videodev: Linux video capture interface: v2.00
10756 13:09:28.386952 <6>[ 8.530549] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10757 13:09:28.396900 <4>[ 8.533092] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10758 13:09:28.400045 <4>[ 8.533092] Fallback method does not support PEC.
10759 13:09:28.409727 <3>[ 8.537606] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10760 13:09:28.419449 <6>[ 8.545319] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10761 13:09:28.426298 <6>[ 8.545399] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10762 13:09:28.432952 <3>[ 8.553037] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10763 13:09:28.442772 <6>[ 8.559099] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10764 13:09:28.452901 <3>[ 8.561487] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10765 13:09:28.459203 <6>[ 8.561489] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10766 13:09:28.462873 <6>[ 8.561552] pci 0000:00:00.0: supports D1 D2
10767 13:09:28.469511 <6>[ 8.561554] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10768 13:09:28.479695 <6>[ 8.562628] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10769 13:09:28.486026 <6>[ 8.562758] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10770 13:09:28.492780 <6>[ 8.562789] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10771 13:09:28.498904 <6>[ 8.562810] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10772 13:09:28.505680 <6>[ 8.562826] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10773 13:09:28.512424 <6>[ 8.562967] pci 0000:01:00.0: supports D1 D2
10774 13:09:28.518875 <6>[ 8.562971] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10775 13:09:28.525356 <6>[ 8.563157] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10776 13:09:28.535291 <6>[ 8.565353] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10777 13:09:28.542063 <3>[ 8.568548] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 13:09:28.548521 <6>[ 8.575170] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10779 13:09:28.558535 <3>[ 8.580681] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 13:09:28.565415 <3>[ 8.580684] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10781 13:09:28.575247 <6>[ 8.588784] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10782 13:09:28.581768 <3>[ 8.596733] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10783 13:09:28.591566 <3>[ 8.596878] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10784 13:09:28.601518 <6>[ 8.597790] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10785 13:09:28.611298 <6>[ 8.598064] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10786 13:09:28.618127 <6>[ 8.602579] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10787 13:09:28.624614 <3>[ 8.609714] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10788 13:09:28.634361 <6>[ 8.623349] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10789 13:09:28.640937 <3>[ 8.631420] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10790 13:09:28.647696 <6>[ 8.632049] Bluetooth: Core ver 2.22
10791 13:09:28.650803 <6>[ 8.632117] NET: Registered PF_BLUETOOTH protocol family
10792 13:09:28.657401 <6>[ 8.632118] Bluetooth: HCI device and connection manager initialized
10793 13:09:28.664383 <6>[ 8.632131] Bluetooth: HCI socket layer initialized
10794 13:09:28.667519 <6>[ 8.632135] Bluetooth: L2CAP socket layer initialized
10795 13:09:28.674059 <6>[ 8.632141] Bluetooth: SCO socket layer initialized
10796 13:09:28.680730 <6>[ 8.641329] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10797 13:09:28.690628 <3>[ 8.647574] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10798 13:09:28.697025 <6>[ 8.655660] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10799 13:09:28.707733 <3>[ 8.664942] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10800 13:09:28.710511 <6>[ 8.673725] pci 0000:00:00.0: PCI bridge to [bus 01]
10801 13:09:28.720533 <3>[ 8.681228] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10802 13:09:28.727337 <6>[ 8.682166] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10803 13:09:28.740382 <6>[ 8.683444] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10804 13:09:28.743858 <6>[ 8.683605] usbcore: registered new interface driver uvcvideo
10805 13:09:28.753692 <6>[ 8.685708] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10806 13:09:28.759807 <6>[ 8.685958] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10807 13:09:28.763542 <6>[ 8.701754] usbcore: registered new interface driver btusb
10808 13:09:28.776719 <4>[ 8.702255] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10809 13:09:28.779778 <3>[ 8.702265] Bluetooth: hci0: Failed to load firmware file (-2)
10810 13:09:28.786597 <3>[ 8.702268] Bluetooth: hci0: Failed to set up firmware (-2)
10811 13:09:28.796210 <4>[ 8.702272] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10812 13:09:28.802857 <6>[ 8.707733] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10813 13:09:28.809523 <6>[ 8.707828] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10814 13:09:28.816205 <6>[ 9.033043] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10815 13:09:28.834497 <5>[ 9.048450] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10816 13:09:28.853317 <5>[ 9.067404] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10817 13:09:28.859845 <5>[ 9.074884] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10818 13:09:28.870071 <4>[ 9.083392] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10819 13:09:28.876371 <6>[ 9.092327] cfg80211: failed to load regulatory.db
10820 13:09:28.929961 <6>[ 9.143992] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10821 13:09:28.936616 <6>[ 9.151582] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10822 13:09:28.961222 <6>[ 9.178434] mt7921e 0000:01:00.0: ASIC revision: 79610010
10823 13:09:29.065219 <6>[ 9.279451] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10824 13:09:29.068605 <6>[ 9.279451]
10825 13:09:29.087018 Begin: Loading essential drivers ... done.
10826 13:09:29.090776 Begin: Running /scripts/init-premount ... done.
10827 13:09:29.097212 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10828 13:09:29.106837 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10829 13:09:29.109946 Device /sys/class/net/eth0 found
10830 13:09:29.110023 done.
10831 13:09:29.129821 Begin: Waiting up to 180 secs for any network device to become available ... done.
10832 13:09:29.169900 IP-Config: eth0 hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10833 13:09:29.190087 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10834 13:09:29.196809 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10835 13:09:29.203146 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10836 13:09:29.210205 host : mt8192-asurada-spherion-r0-cbg-8
10837 13:09:29.216571 domain : lava-rack
10838 13:09:29.220117 rootserver: 192.168.201.1 rootpath:
10839 13:09:29.222894 filename :
10840 13:09:29.232272 done.
10841 13:09:29.240116 Begin: Running /scripts/nfs-bottom ... done.
10842 13:09:29.265995 Begin: Running /scripts/init-bottom ... done.
10843 13:09:29.334243 <6>[ 9.548144] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10844 13:09:30.615908 <6>[ 10.833456] NET: Registered PF_INET6 protocol family
10845 13:09:30.623468 <6>[ 10.840697] Segment Routing with IPv6
10846 13:09:30.626338 <6>[ 10.844664] In-situ OAM (IOAM) with IPv6
10847 13:09:30.795561 <30>[ 10.986812] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10848 13:09:30.802452 <30>[ 11.020009] systemd[1]: Detected architecture arm64.
10849 13:09:30.811004
10850 13:09:30.814310 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10851 13:09:30.814406
10852 13:09:30.838895 <30>[ 11.056338] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10853 13:09:31.937129 <30>[ 12.151487] systemd[1]: Queued start job for default target graphical.target.
10854 13:09:31.974572 <30>[ 12.188597] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10855 13:09:31.980824 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10856 13:09:32.002641 <30>[ 12.217024] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10857 13:09:32.012606 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10858 13:09:32.030510 <30>[ 12.244977] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10859 13:09:32.040769 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10860 13:09:32.057989 <30>[ 12.272540] systemd[1]: Created slice user.slice - User and Session Slice.
10861 13:09:32.064856 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10862 13:09:32.088767 <30>[ 12.300069] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10863 13:09:32.098906 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10864 13:09:32.116206 <30>[ 12.327438] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10865 13:09:32.122818 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10866 13:09:32.151769 <30>[ 12.355842] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10867 13:09:32.161309 <30>[ 12.375772] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10868 13:09:32.167714 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10869 13:09:32.184984 <30>[ 12.399578] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10870 13:09:32.195016 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10871 13:09:32.213487 <30>[ 12.427726] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10872 13:09:32.222944 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10873 13:09:32.237659 <30>[ 12.455314] systemd[1]: Reached target paths.target - Path Units.
10874 13:09:32.247891 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10875 13:09:32.265480 <30>[ 12.479688] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10876 13:09:32.271833 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10877 13:09:32.285320 <30>[ 12.503187] systemd[1]: Reached target slices.target - Slice Units.
10878 13:09:32.295267 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10879 13:09:32.310413 <30>[ 12.527703] systemd[1]: Reached target swap.target - Swaps.
10880 13:09:32.316587 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10881 13:09:32.337021 <30>[ 12.551685] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10882 13:09:32.347247 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10883 13:09:32.365959 <30>[ 12.580176] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10884 13:09:32.375543 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10885 13:09:32.396135 <30>[ 12.610711] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10886 13:09:32.406210 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10887 13:09:32.422363 <30>[ 12.636810] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10888 13:09:32.432356 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10889 13:09:32.449199 <30>[ 12.663859] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10890 13:09:32.455774 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10891 13:09:32.474480 <30>[ 12.688790] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10892 13:09:32.484238 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10893 13:09:32.503789 <30>[ 12.718318] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10894 13:09:32.513570 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10895 13:09:32.529143 <30>[ 12.743671] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10896 13:09:32.538812 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10897 13:09:32.581010 <30>[ 12.795281] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10898 13:09:32.587287 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10899 13:09:32.609257 <30>[ 12.823773] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10900 13:09:32.616089 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10901 13:09:32.641650 <30>[ 12.855965] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10902 13:09:32.648545 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10903 13:09:32.675850 <30>[ 12.883402] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10904 13:09:32.691211 <30>[ 12.905518] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10905 13:09:32.700783 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10906 13:09:32.721980 <30>[ 12.936821] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10907 13:09:32.728726 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10908 13:09:32.754300 <30>[ 12.968742] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10909 13:09:32.760814 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10910 13:09:32.786354 <30>[ 13.001083] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10911 13:09:32.796432 Startin<6>[ 13.010777] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10912 13:09:32.802989 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10913 13:09:32.826456 <30>[ 13.040977] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10914 13:09:32.836421 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10915 13:09:32.857926 <30>[ 13.072674] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10916 13:09:32.864868 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10917 13:09:32.891123 <30>[ 13.104829] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10918 13:09:32.896963 Starting [0;1;39mmodpr<6>[ 13.115117] fuse: init (API version 7.37)
10919 13:09:32.903528 obe@loop.ser…e[0m - Load Kernel Module loop...
10920 13:09:32.953632 <30>[ 13.168030] systemd[1]: Starting systemd-journald.service - Journal Service...
10921 13:09:32.960237 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10922 13:09:32.994549 <30>[ 13.208912] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10923 13:09:33.000712 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10924 13:09:33.029767 <30>[ 13.241046] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10925 13:09:33.036443 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10926 13:09:33.061530 <30>[ 13.275986] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10927 13:09:33.071272 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10928 13:09:33.094763 <30>[ 13.308931] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10929 13:09:33.101405 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10930 13:09:33.121020 <3>[ 13.335354] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 13:09:33.127237 <30>[ 13.340786] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10932 13:09:33.137053 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10933 13:09:33.153801 <30>[ 13.367662] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10934 13:09:33.160353 <3>[ 13.371361] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 13:09:33.170645 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10936 13:09:33.188968 <30>[ 13.403610] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10937 13:09:33.195999 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10938 13:09:33.206219 <3>[ 13.420577] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 13:09:33.216366 <30>[ 13.430786] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10940 13:09:33.226516 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10941 13:09:33.238343 <3>[ 13.452430] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 13:09:33.248921 <30>[ 13.463570] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10943 13:09:33.255921 <30>[ 13.471810] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10944 13:09:33.269434 [[0;32m OK [0m] Finished [0<3>[ 13.482233] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 13:09:33.276544 ;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10946 13:09:33.294389 <30>[ 13.508238] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10947 13:09:33.301386 <3>[ 13.515774] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 13:09:33.311241 <30>[ 13.516091] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10949 13:09:33.317821 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10950 13:09:33.335492 <3>[ 13.549842] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 13:09:33.346382 <30>[ 13.560868] systemd[1]: modprobe@drm.service: Deactivated successfully.
10952 13:09:33.353176 <30>[ 13.568937] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10953 13:09:33.363532 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10954 13:09:33.370580 <3>[ 13.585849] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 13:09:33.383545 <30>[ 13.598057] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10956 13:09:33.393920 <30>[ 13.606574] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10957 13:09:33.407466 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Lo<3>[ 13.620764] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 13:09:33.410790 ad Kernel Module efi_pstore.
10959 13:09:33.430351 <30>[ 13.644697] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10960 13:09:33.436934 <30>[ 13.652267] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10961 13:09:33.446960 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10962 13:09:33.454015 <3>[ 13.668522] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 13:09:33.465752 <30>[ 13.680362] systemd[1]: modprobe@loop.service: Deactivated successfully.
10964 13:09:33.472506 <30>[ 13.687773] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10965 13:09:33.489260 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Mo<3>[ 13.701537] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 13:09:33.489386 dule loop.
10967 13:09:33.509225 <30>[ 13.724025] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10968 13:09:33.516565 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10969 13:09:33.535849 <3>[ 13.750083] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10970 13:09:33.545795 <3>[ 13.751510] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10971 13:09:33.562004 <4>[ 13.758920] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10972 13:09:33.572952 <30>[ 13.759840] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10973 13:09:33.579711 <3>[ 13.794596] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10974 13:09:33.589347 <3>[ 13.795448] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 13:09:33.595844 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10976 13:09:33.614400 <30>[ 13.828415] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10977 13:09:33.624189 <3>[ 13.836325] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10978 13:09:33.630792 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10979 13:09:33.650452 <30>[ 13.864424] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
10980 13:09:33.660505 <3>[ 13.871098] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10981 13:09:33.667183 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10982 13:09:33.686305 <30>[ 13.900463] systemd[1]: Reached target network-pre.target - Preparation for Network.
10983 13:09:33.696184 <3>[ 13.906334] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10984 13:09:33.702697 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10985 13:09:33.745493 <30>[ 13.959253] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
10986 13:09:33.751914 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10987 13:09:33.776429 <30>[ 13.990864] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
10988 13:09:33.783028 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10989 13:09:33.808128 <30>[ 14.019207] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
10990 13:09:33.824591 <30>[ 14.032780] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
10991 13:09:33.838578 <30>[ 14.053053] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
10992 13:09:33.845182 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10993 13:09:33.870515 <30>[ 14.082005] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
10994 13:09:33.897286 <30>[ 14.111779] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
10995 13:09:33.904255 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10996 13:09:33.931564 <30>[ 14.146135] systemd[1]: Starting systemd-sysusers.service - Create System Users...
10997 13:09:33.938365 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10998 13:09:33.967207 <30>[ 14.181634] systemd[1]: Started systemd-journald.service - Journal Service.
10999 13:09:33.973398 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11000 13:09:33.996085 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11001 13:09:34.013692 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11002 13:09:34.034661 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11003 13:09:34.054096 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11004 13:09:34.074041 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11005 13:09:34.117876 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11006 13:09:34.147579 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11007 13:09:34.187534 <46>[ 14.401972] systemd-journald[302]: Received client request to flush runtime journal.
11008 13:09:35.308199 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11009 13:09:35.319449 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11010 13:09:35.336976 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11011 13:09:35.617696 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11012 13:09:35.638578 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11013 13:09:35.686636 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11014 13:09:35.814746 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11015 13:09:35.890994 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11016 13:09:35.956916 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11017 13:09:36.229527 <6>[ 16.447728] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11018 13:09:36.239387 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11019 13:09:36.314380 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11020 13:09:36.379889 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11021 13:09:36.415620 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11022 13:09:36.461134 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11023 13:09:36.481094 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11024 13:09:36.503102 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11025 13:09:36.542157 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11026 13:09:36.572791 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11027 13:09:36.637450 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11028 13:09:36.659194 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11029 13:09:36.676914 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11030 13:09:36.708116 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11031 13:09:36.820051 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11032 13:09:36.836895 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11033 13:09:36.852585 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11034 13:09:36.868528 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11035 13:09:36.892976 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11036 13:09:36.915666 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11037 13:09:36.932669 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11038 13:09:36.952358 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11039 13:09:36.972370 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11040 13:09:36.988458 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11041 13:09:37.007294 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11042 13:09:37.024227 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11043 13:09:37.040615 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11044 13:09:37.089745 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11045 13:09:37.189683 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11046 13:09:37.341444 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11047 13:09:37.372705 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11048 13:09:37.493622 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11049 13:09:37.524959 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11050 13:09:37.549140 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11051 13:09:37.605175 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11052 13:09:37.626759 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11053 13:09:37.644712 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11054 13:09:37.663944 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11055 13:09:37.682273 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11056 13:09:37.701212 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11057 13:09:37.753989 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11058 13:09:37.797635 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11059 13:09:37.882691
11060 13:09:37.886060 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11061 13:09:37.886190
11062 13:09:37.889211 debian-bookworm-arm64 login: root (automatic login)
11063 13:09:37.889289
11064 13:09:38.195198 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024 aarch64
11065 13:09:38.195350
11066 13:09:38.202024 The programs included with the Debian GNU/Linux system are free software;
11067 13:09:38.208912 the exact distribution terms for each program are described in the
11068 13:09:38.212515 individual files in /usr/share/doc/*/copyright.
11069 13:09:38.212599
11070 13:09:38.218768 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11071 13:09:38.222005 permitted by applicable law.
11072 13:09:39.315962 Matched prompt #10: / #
11074 13:09:39.316305 Setting prompt string to ['/ #']
11075 13:09:39.316421 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11077 13:09:39.316698 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11078 13:09:39.316807 start: 2.2.6 expect-shell-connection (timeout 00:03:15) [common]
11079 13:09:39.316892 Setting prompt string to ['/ #']
11080 13:09:39.316973 Forcing a shell prompt, looking for ['/ #']
11081 13:09:39.317054 Sending line: ''
11083 13:09:39.367463 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11084 13:09:39.367553 Waiting using forced prompt support (timeout 00:02:30)
11085 13:09:39.372963 / #
11086 13:09:39.373235 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11087 13:09:39.373321 start: 2.2.7 export-device-env (timeout 00:03:15) [common]
11088 13:09:39.373397 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14878994/extract-nfsrootfs-wgu7z_rn'"
11090 13:09:39.479203 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14878994/extract-nfsrootfs-wgu7z_rn'
11091 13:09:39.479473 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
11093 13:09:39.584825 / # export NFS_SERVER_IP='192.168.201.1'
11094 13:09:39.585121 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11095 13:09:39.585215 end: 2.2 depthcharge-retry (duration 00:01:45) [common]
11096 13:09:39.585297 end: 2 depthcharge-action (duration 00:01:45) [common]
11097 13:09:39.585379 start: 3 lava-test-retry (timeout 00:07:33) [common]
11098 13:09:39.585461 start: 3.1 lava-test-shell (timeout 00:07:33) [common]
11099 13:09:39.585532 Using namespace: common
11100 13:09:39.585598 Sending line: '#'
11102 13:09:39.686123 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11103 13:09:39.691707 / # #
11104 13:09:39.691965 Using /lava-14878994
11105 13:09:39.692030 Sending line: 'export SHELL=/bin/bash'
11107 13:09:39.797209 / # export SHELL=/bin/bash
11108 13:09:39.797483 Sending line: '. /lava-14878994/environment'
11110 13:09:39.902948 / # . /lava-14878994/environment
11111 13:09:39.909004 Sending line: '/lava-14878994/bin/lava-test-runner /lava-14878994/0'
11113 13:09:40.009525 Test shell timeout: 10s (minimum of the action and connection timeout)
11114 13:09:40.014639 / # /lava-14878994/bin/lava-test-runner /lava-14878994/0
11115 13:09:40.292356 + export TESTRUN_ID=0_timesync-off
11116 13:09:40.295222 + TESTRUN_ID=0_timesync-off
11117 13:09:40.299132 + cd /lava-14878994/0/tests/0_timesync-off
11118 13:09:40.302306 ++ cat uuid
11119 13:09:40.306729 + UUID=14878994_1.6.2.3.1
11120 13:09:40.306812 + set +x
11121 13:09:40.313144 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14878994_1.6.2.3.1>
11122 13:09:40.313415 Received signal: <STARTRUN> 0_timesync-off 14878994_1.6.2.3.1
11123 13:09:40.313484 Starting test lava.0_timesync-off (14878994_1.6.2.3.1)
11124 13:09:40.313561 Skipping test definition patterns.
11125 13:09:40.316549 + systemctl stop systemd-timesyncd
11126 13:09:40.382060 + set +x
11127 13:09:40.385197 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14878994_1.6.2.3.1>
11128 13:09:40.385450 Received signal: <ENDRUN> 0_timesync-off 14878994_1.6.2.3.1
11129 13:09:40.385530 Ending use of test pattern.
11130 13:09:40.385586 Ending test lava.0_timesync-off (14878994_1.6.2.3.1), duration 0.07
11132 13:09:40.465215 + export TESTRUN_ID=1_kselftest-rtc
11133 13:09:40.469045 + TESTRUN_ID=1_kselftest-rtc
11134 13:09:40.471964 + cd /lava-14878994/0/tests/1_kselftest-rtc
11135 13:09:40.475387 ++ cat uuid
11136 13:09:40.479386 + UUID=14878994_1.6.2.3.5
11137 13:09:40.479465 + set +x
11138 13:09:40.485929 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 14878994_1.6.2.3.5>
11139 13:09:40.486213 Received signal: <STARTRUN> 1_kselftest-rtc 14878994_1.6.2.3.5
11140 13:09:40.486280 Starting test lava.1_kselftest-rtc (14878994_1.6.2.3.5)
11141 13:09:40.486357 Skipping test definition patterns.
11142 13:09:40.489827 + cd ./automated/linux/kselftest/
11143 13:09:40.515667 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
11144 13:09:40.559502 INFO: install_deps skipped
11145 13:09:41.070321 --2024-07-18 13:09:41-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz
11146 13:09:41.093807 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11147 13:09:41.223613 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11148 13:09:41.353470 HTTP request sent, awaiting response... 200 OK
11149 13:09:41.357157 Length: 1919140 (1.8M) [application/octet-stream]
11150 13:09:41.360508 Saving to: 'kselftest_armhf.tar.gz'
11151 13:09:41.360584
11152 13:09:41.360643
11153 13:09:41.614806 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11154 13:09:41.873802 kselftest_armhf.tar 2%[ ] 47.81K 183KB/s
11155 13:09:42.143908 kselftest_armhf.tar 11%[=> ] 217.50K 418KB/s
11156 13:09:42.402921 kselftest_armhf.tar 47%[========> ] 898.59K 1.11MB/s
11157 13:09:42.409665 kselftest_armhf.tar 90%[=================> ] 1.67M 1.59MB/s
11158 13:09:42.415858 kselftest_armhf.tar 100%[===================>] 1.83M 1.74MB/s in 1.1s
11159 13:09:42.415966
11160 13:09:42.582646 2024-07-18 13:09:42 (1.74 MB/s) - 'kselftest_armhf.tar.gz' saved [1919140/1919140]
11161 13:09:42.582778
11162 13:09:50.239859 skiplist:
11163 13:09:50.242996 ========================================
11164 13:09:50.246150 ========================================
11165 13:09:50.311601 rtc:rtctest
11166 13:09:50.336576 ============== Tests to run ===============
11167 13:09:50.340743 rtc:rtctest
11168 13:09:50.343855 ===========End Tests to run ===============
11169 13:09:50.350006 shardfile-rtc pass
11170 13:09:50.483407 <12>[ 30.702863] kselftest: Running tests in rtc
11171 13:09:50.494431 TAP version 13
11172 13:09:50.511955 1..1
11173 13:09:50.549799 # selftests: rtc: rtctest
11174 13:09:51.026411 # TAP version 13
11175 13:09:51.026872 # 1..8
11176 13:09:51.030393 # # Starting 8 tests from 2 test cases.
11177 13:09:51.033161 # # RUN rtc.date_read ...
11178 13:09:51.039871 # # rtctest.c:49:date_read:Current RTC date/time is 18/07/2024 13:09:50.
11179 13:09:51.043187 # # OK rtc.date_read
11180 13:09:51.046366 # ok 1 rtc.date_read
11181 13:09:51.049736 # # RUN rtc.date_read_loop ...
11182 13:09:51.059400 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11183 13:09:59.789644 <6>[ 40.013540] vpu: disabling
11184 13:09:59.792477 <6>[ 40.016647] vproc2: disabling
11185 13:09:59.796016 <6>[ 40.019982] vproc1: disabling
11186 13:09:59.799256 <6>[ 40.023294] vaud18: disabling
11187 13:09:59.806158 <6>[ 40.027080] vsram_others: disabling
11188 13:09:59.809441 <6>[ 40.031046] va09: disabling
11189 13:09:59.812765 <6>[ 40.034210] vsram_md: disabling
11190 13:09:59.816110 <6>[ 40.037775] Vgpu: disabling
11191 13:10:21.012506 # # rtctest.c:115:date_read_loop:Performed 2632 RTC time reads.
11192 13:10:21.015825 # # OK rtc.date_read_loop
11193 13:10:21.019202 # ok 2 rtc.date_read_loop
11194 13:10:21.022559 # # RUN rtc.uie_read ...
11195 13:10:23.999075 # # OK rtc.uie_read
11196 13:10:24.001899 # ok 3 rtc.uie_read
11197 13:10:24.005546 # # RUN rtc.uie_select ...
11198 13:10:26.998547 # # OK rtc.uie_select
11199 13:10:27.001839 # ok 4 rtc.uie_select
11200 13:10:27.005087 # # RUN rtc.alarm_alm_set ...
11201 13:10:27.011632 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 13:10:30.
11202 13:10:27.015121 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11203 13:10:27.021665 # # alarm_alm_set: Test terminated by assertion
11204 13:10:27.025443 # # FAIL rtc.alarm_alm_set
11205 13:10:27.028494 # not ok 5 rtc.alarm_alm_set
11206 13:10:27.031976 # # RUN rtc.alarm_wkalm_set ...
11207 13:10:27.038637 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 18/07/2024 13:10:30.
11208 13:10:30.001376 # # OK rtc.alarm_wkalm_set
11209 13:10:30.001503 # ok 6 rtc.alarm_wkalm_set
11210 13:10:30.007861 # # RUN rtc.alarm_alm_set_minute ...
11211 13:10:30.011406 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 13:11:00.
11212 13:10:30.017817 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11213 13:10:30.024814 # # alarm_alm_set_minute: Test terminated by assertion
11214 13:10:30.028008 # # FAIL rtc.alarm_alm_set_minute
11215 13:10:30.031008 # not ok 7 rtc.alarm_alm_set_minute
11216 13:10:30.034438 # # RUN rtc.alarm_wkalm_set_minute ...
11217 13:10:30.040954 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 18/07/2024 13:11:00.
11218 13:10:59.998032 # # OK rtc.alarm_wkalm_set_minute
11219 13:11:00.001424 # ok 8 rtc.alarm_wkalm_set_minute
11220 13:11:00.004774 # # FAILED: 6 / 8 tests passed.
11221 13:11:00.007835 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11222 13:11:00.010925 not ok 1 selftests: rtc: rtctest # exit=1
11223 13:11:01.481961 rtc_rtctest_rtc_date_read pass
11224 13:11:01.484868 rtc_rtctest_rtc_date_read_loop pass
11225 13:11:01.488379 rtc_rtctest_rtc_uie_read pass
11226 13:11:01.491627 rtc_rtctest_rtc_uie_select pass
11227 13:11:01.495095 rtc_rtctest_rtc_alarm_alm_set fail
11228 13:11:01.498381 rtc_rtctest_rtc_alarm_wkalm_set pass
11229 13:11:01.501798 rtc_rtctest_rtc_alarm_alm_set_minute fail
11230 13:11:01.505096 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11231 13:11:01.508621 rtc_rtctest fail
11232 13:11:01.558098 + ../../utils/send-to-lava.sh ./output/result.txt
11233 13:11:01.632244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11234 13:11:01.632556 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11236 13:11:01.681646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11237 13:11:01.681946 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11239 13:11:01.735337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11240 13:11:01.735624 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11242 13:11:01.781950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11243 13:11:01.782255 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11245 13:11:01.833609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11246 13:11:01.833893 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11248 13:11:01.887234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11249 13:11:01.887526 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11251 13:11:01.939608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11252 13:11:01.939896 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11254 13:11:01.988567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11255 13:11:01.988863 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11257 13:11:02.038391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11258 13:11:02.038681 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11260 13:11:02.084291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11261 13:11:02.084412 + set +x
11262 13:11:02.084674 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11264 13:11:02.091221 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 14878994_1.6.2.3.5>
11265 13:11:02.091521 Received signal: <ENDRUN> 1_kselftest-rtc 14878994_1.6.2.3.5
11266 13:11:02.091623 Ending use of test pattern.
11267 13:11:02.091720 Ending test lava.1_kselftest-rtc (14878994_1.6.2.3.5), duration 81.61
11269 13:11:02.092099 ok: lava_test_shell seems to have completed
11270 13:11:02.092307 shardfile-rtc: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest: fail
11271 13:11:02.092405 end: 3.1 lava-test-shell (duration 00:01:23) [common]
11272 13:11:02.092503 end: 3 lava-test-retry (duration 00:01:23) [common]
11273 13:11:02.092611 start: 4 finalize (timeout 00:06:11) [common]
11274 13:11:02.092746 start: 4.1 power-off (timeout 00:00:30) [common]
11275 13:11:02.092957 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
11276 13:11:04.212529 >> Command sent successfully.
11277 13:11:04.215666 Returned 0 in 2 seconds
11278 13:11:04.215797 end: 4.1 power-off (duration 00:00:02) [common]
11280 13:11:04.215988 start: 4.2 read-feedback (timeout 00:06:09) [common]
11282 13:11:04.216391 Listened to connection for namespace 'common' for up to 1s
11283 13:11:05.217158 Finalising connection for namespace 'common'
11284 13:11:05.217323 Disconnecting from shell: Finalise
11285 13:11:05.217388 / #
11286 13:11:05.317883 end: 4.2 read-feedback (duration 00:00:01) [common]
11287 13:11:05.318555 end: 4 finalize (duration 00:00:03) [common]
11288 13:11:05.319114 Cleaning after the job
11289 13:11:05.319595 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14878994/tftp-deploy-o87jl0sz/ramdisk
11290 13:11:05.324546 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14878994/tftp-deploy-o87jl0sz/kernel
11291 13:11:05.335316 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14878994/tftp-deploy-o87jl0sz/dtb
11292 13:11:05.335488 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14878994/tftp-deploy-o87jl0sz/nfsrootfs
11293 13:11:05.401868 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14878994/tftp-deploy-o87jl0sz/modules
11294 13:11:05.407804 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14878994
11295 13:11:06.028571 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14878994
11296 13:11:06.028745 Job finished correctly