Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 37
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 13:18:11.498088 lava-dispatcher, installed at version: 2024.05
2 13:18:11.498337 start: 0 validate
3 13:18:11.498500 Start time: 2024-07-18 13:18:11.498494+00:00 (UTC)
4 13:18:11.498642 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:18:11.498793 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 13:18:11.749402 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:18:11.749565 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 13:18:12.007069 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:18:12.007239 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:18:12.264726 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:18:12.264868 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:18:12.522534 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:18:12.522674 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 13:18:12.782702 validate duration: 1.28
16 13:18:12.782951 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:18:12.783044 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:18:12.783122 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:18:12.783275 Not decompressing ramdisk as can be used compressed.
20 13:18:12.783356 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 13:18:12.783413 saving as /var/lib/lava/dispatcher/tmp/14879048/tftp-deploy-56hlfbtr/ramdisk/initrd.cpio.gz
22 13:18:12.783528 total size: 5628169 (5 MB)
23 13:18:12.784637 progress 0 % (0 MB)
24 13:18:12.786313 progress 5 % (0 MB)
25 13:18:12.787886 progress 10 % (0 MB)
26 13:18:12.789293 progress 15 % (0 MB)
27 13:18:12.791163 progress 20 % (1 MB)
28 13:18:12.792870 progress 25 % (1 MB)
29 13:18:12.794584 progress 30 % (1 MB)
30 13:18:12.796121 progress 35 % (1 MB)
31 13:18:12.797460 progress 40 % (2 MB)
32 13:18:12.798950 progress 45 % (2 MB)
33 13:18:12.800447 progress 50 % (2 MB)
34 13:18:12.802012 progress 55 % (2 MB)
35 13:18:12.803646 progress 60 % (3 MB)
36 13:18:12.804981 progress 65 % (3 MB)
37 13:18:12.806549 progress 70 % (3 MB)
38 13:18:12.807941 progress 75 % (4 MB)
39 13:18:12.809506 progress 80 % (4 MB)
40 13:18:12.810891 progress 85 % (4 MB)
41 13:18:12.812447 progress 90 % (4 MB)
42 13:18:12.813936 progress 95 % (5 MB)
43 13:18:12.815279 progress 100 % (5 MB)
44 13:18:12.815534 5 MB downloaded in 0.03 s (167.72 MB/s)
45 13:18:12.815682 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:18:12.815899 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:18:12.815977 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:18:12.816051 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:18:12.816185 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 13:18:12.816249 saving as /var/lib/lava/dispatcher/tmp/14879048/tftp-deploy-56hlfbtr/kernel/Image
52 13:18:12.816301 total size: 54813184 (52 MB)
53 13:18:12.816353 No compression specified
54 13:18:12.817391 progress 0 % (0 MB)
55 13:18:12.831017 progress 5 % (2 MB)
56 13:18:12.844903 progress 10 % (5 MB)
57 13:18:12.858774 progress 15 % (7 MB)
58 13:18:12.872927 progress 20 % (10 MB)
59 13:18:12.886752 progress 25 % (13 MB)
60 13:18:12.900520 progress 30 % (15 MB)
61 13:18:12.914377 progress 35 % (18 MB)
62 13:18:12.928531 progress 40 % (20 MB)
63 13:18:12.942220 progress 45 % (23 MB)
64 13:18:12.956170 progress 50 % (26 MB)
65 13:18:12.970188 progress 55 % (28 MB)
66 13:18:12.984018 progress 60 % (31 MB)
67 13:18:12.997821 progress 65 % (34 MB)
68 13:18:13.011645 progress 70 % (36 MB)
69 13:18:13.025398 progress 75 % (39 MB)
70 13:18:13.039290 progress 80 % (41 MB)
71 13:18:13.052837 progress 85 % (44 MB)
72 13:18:13.066712 progress 90 % (47 MB)
73 13:18:13.080645 progress 95 % (49 MB)
74 13:18:13.094088 progress 100 % (52 MB)
75 13:18:13.094328 52 MB downloaded in 0.28 s (188.02 MB/s)
76 13:18:13.094474 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:18:13.094681 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:18:13.094760 start: 1.3 download-retry (timeout 00:10:00) [common]
80 13:18:13.094835 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 13:18:13.094973 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:18:13.095036 saving as /var/lib/lava/dispatcher/tmp/14879048/tftp-deploy-56hlfbtr/dtb/mt8192-asurada-spherion-r0.dtb
83 13:18:13.095089 total size: 47258 (0 MB)
84 13:18:13.095141 No compression specified
85 13:18:13.096265 progress 69 % (0 MB)
86 13:18:13.096521 progress 100 % (0 MB)
87 13:18:13.096701 0 MB downloaded in 0.00 s (28.00 MB/s)
88 13:18:13.096812 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:18:13.097009 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:18:13.097084 start: 1.4 download-retry (timeout 00:10:00) [common]
92 13:18:13.097163 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 13:18:13.097269 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 13:18:13.097328 saving as /var/lib/lava/dispatcher/tmp/14879048/tftp-deploy-56hlfbtr/nfsrootfs/full.rootfs.tar
95 13:18:13.097381 total size: 120894716 (115 MB)
96 13:18:13.097435 Using unxz to decompress xz
97 13:18:13.098783 progress 0 % (0 MB)
98 13:18:13.434719 progress 5 % (5 MB)
99 13:18:13.784372 progress 10 % (11 MB)
100 13:18:14.130572 progress 15 % (17 MB)
101 13:18:14.454147 progress 20 % (23 MB)
102 13:18:14.759891 progress 25 % (28 MB)
103 13:18:15.114364 progress 30 % (34 MB)
104 13:18:15.445840 progress 35 % (40 MB)
105 13:18:15.622768 progress 40 % (46 MB)
106 13:18:15.816543 progress 45 % (51 MB)
107 13:18:16.128996 progress 50 % (57 MB)
108 13:18:16.489398 progress 55 % (63 MB)
109 13:18:16.831443 progress 60 % (69 MB)
110 13:18:17.181886 progress 65 % (74 MB)
111 13:18:17.522186 progress 70 % (80 MB)
112 13:18:17.873530 progress 75 % (86 MB)
113 13:18:18.209730 progress 80 % (92 MB)
114 13:18:18.560831 progress 85 % (98 MB)
115 13:18:18.916789 progress 90 % (103 MB)
116 13:18:19.246308 progress 95 % (109 MB)
117 13:18:19.616423 progress 100 % (115 MB)
118 13:18:19.622188 115 MB downloaded in 6.52 s (17.67 MB/s)
119 13:18:19.622370 end: 1.4.1 http-download (duration 00:00:07) [common]
121 13:18:19.622631 end: 1.4 download-retry (duration 00:00:07) [common]
122 13:18:19.622712 start: 1.5 download-retry (timeout 00:09:53) [common]
123 13:18:19.622804 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 13:18:19.622930 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 13:18:19.622999 saving as /var/lib/lava/dispatcher/tmp/14879048/tftp-deploy-56hlfbtr/modules/modules.tar
126 13:18:19.623057 total size: 8611320 (8 MB)
127 13:18:19.623113 Using unxz to decompress xz
128 13:18:19.624381 progress 0 % (0 MB)
129 13:18:19.645085 progress 5 % (0 MB)
130 13:18:19.669680 progress 10 % (0 MB)
131 13:18:19.693773 progress 15 % (1 MB)
132 13:18:19.718379 progress 20 % (1 MB)
133 13:18:19.742328 progress 25 % (2 MB)
134 13:18:19.766187 progress 30 % (2 MB)
135 13:18:19.788926 progress 35 % (2 MB)
136 13:18:19.815549 progress 40 % (3 MB)
137 13:18:19.840475 progress 45 % (3 MB)
138 13:18:19.864650 progress 50 % (4 MB)
139 13:18:19.889631 progress 55 % (4 MB)
140 13:18:19.914129 progress 60 % (4 MB)
141 13:18:19.938014 progress 65 % (5 MB)
142 13:18:19.963652 progress 70 % (5 MB)
143 13:18:19.991197 progress 75 % (6 MB)
144 13:18:20.018873 progress 80 % (6 MB)
145 13:18:20.042730 progress 85 % (7 MB)
146 13:18:20.066384 progress 90 % (7 MB)
147 13:18:20.090064 progress 95 % (7 MB)
148 13:18:20.113178 progress 100 % (8 MB)
149 13:18:20.118852 8 MB downloaded in 0.50 s (16.56 MB/s)
150 13:18:20.119076 end: 1.5.1 http-download (duration 00:00:00) [common]
152 13:18:20.119434 end: 1.5 download-retry (duration 00:00:00) [common]
153 13:18:20.119518 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 13:18:20.119605 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 13:18:24.334872 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14879048/extract-nfsrootfs-brtvvc40
156 13:18:24.335032 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 13:18:24.335123 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 13:18:24.335289 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5
159 13:18:24.335411 makedir: /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin
160 13:18:24.335538 makedir: /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/tests
161 13:18:24.335635 makedir: /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/results
162 13:18:24.335722 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-add-keys
163 13:18:24.335849 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-add-sources
164 13:18:24.335974 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-background-process-start
165 13:18:24.336090 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-background-process-stop
166 13:18:24.336219 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-common-functions
167 13:18:24.336333 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-echo-ipv4
168 13:18:24.336453 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-install-packages
169 13:18:24.336591 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-installed-packages
170 13:18:24.336711 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-os-build
171 13:18:24.336823 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-probe-channel
172 13:18:24.336940 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-probe-ip
173 13:18:24.337055 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-target-ip
174 13:18:24.337205 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-target-mac
175 13:18:24.337314 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-target-storage
176 13:18:24.337432 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-test-case
177 13:18:24.337547 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-test-event
178 13:18:24.337665 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-test-feedback
179 13:18:24.337777 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-test-raise
180 13:18:24.337890 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-test-reference
181 13:18:24.338034 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-test-runner
182 13:18:24.338149 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-test-set
183 13:18:24.338262 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-test-shell
184 13:18:24.338374 Updating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-add-keys (debian)
185 13:18:24.338536 Updating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-add-sources (debian)
186 13:18:24.338674 Updating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-install-packages (debian)
187 13:18:24.338801 Updating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-installed-packages (debian)
188 13:18:24.338939 Updating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/bin/lava-os-build (debian)
189 13:18:24.339047 Creating /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/environment
190 13:18:24.339139 LAVA metadata
191 13:18:24.339203 - LAVA_JOB_ID=14879048
192 13:18:24.339257 - LAVA_DISPATCHER_IP=192.168.201.1
193 13:18:24.339347 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 13:18:24.339463 skipped lava-vland-overlay
195 13:18:24.339549 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 13:18:24.339627 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 13:18:24.339683 skipped lava-multinode-overlay
198 13:18:24.339746 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 13:18:24.339814 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 13:18:24.339882 Loading test definitions
201 13:18:24.339990 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 13:18:24.340050 Using /lava-14879048 at stage 0
203 13:18:24.340337 uuid=14879048_1.6.2.3.1 testdef=None
204 13:18:24.340419 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 13:18:24.340494 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 13:18:24.340897 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 13:18:24.341096 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 13:18:24.341618 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 13:18:24.341827 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 13:18:24.342329 runner path: /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/0/tests/0_timesync-off test_uuid 14879048_1.6.2.3.1
213 13:18:24.342475 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 13:18:24.342713 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 13:18:24.342782 Using /lava-14879048 at stage 0
217 13:18:24.342871 Fetching tests from https://github.com/kernelci/test-definitions.git
218 13:18:24.342945 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/0/tests/1_kselftest-tpm2'
219 13:18:28.589438 Running '/usr/bin/git checkout kernelci.org
220 13:18:28.736468 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 13:18:28.736829 uuid=14879048_1.6.2.3.5 testdef=None
222 13:18:28.736928 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 13:18:28.737123 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 13:18:28.737772 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 13:18:28.738013 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 13:18:28.738967 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 13:18:28.739184 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 13:18:28.740120 runner path: /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/0/tests/1_kselftest-tpm2 test_uuid 14879048_1.6.2.3.5
232 13:18:28.740199 BOARD='mt8192-asurada-spherion-r0'
233 13:18:28.740283 BRANCH='cip'
234 13:18:28.740349 SKIPFILE='/dev/null'
235 13:18:28.740418 SKIP_INSTALL='True'
236 13:18:28.740501 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz'
237 13:18:28.740592 TST_CASENAME=''
238 13:18:28.740646 TST_CMDFILES='tpm2'
239 13:18:28.740785 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 13:18:28.740964 Creating lava-test-runner.conf files
242 13:18:28.741018 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14879048/lava-overlay-l852_er5/lava-14879048/0 for stage 0
243 13:18:28.741135 - 0_timesync-off
244 13:18:28.741220 - 1_kselftest-tpm2
245 13:18:28.741312 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 13:18:28.741388 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 13:18:35.975067 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 13:18:35.975186 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 13:18:35.975271 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 13:18:35.975350 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 13:18:35.975429 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 13:18:36.132484 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 13:18:36.132613 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 13:18:36.132689 extracting modules file /var/lib/lava/dispatcher/tmp/14879048/tftp-deploy-56hlfbtr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14879048/extract-nfsrootfs-brtvvc40
255 13:18:36.362611 extracting modules file /var/lib/lava/dispatcher/tmp/14879048/tftp-deploy-56hlfbtr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14879048/extract-overlay-ramdisk-i0a15_nz/ramdisk
256 13:18:36.592569 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 13:18:36.592695 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 13:18:36.592770 [common] Applying overlay to NFS
259 13:18:36.592828 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14879048/compress-overlay-m2d8qph4/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14879048/extract-nfsrootfs-brtvvc40
260 13:18:37.432476 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 13:18:37.432635 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 13:18:37.432734 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 13:18:37.432855 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 13:18:37.433000 Building ramdisk /var/lib/lava/dispatcher/tmp/14879048/extract-overlay-ramdisk-i0a15_nz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14879048/extract-overlay-ramdisk-i0a15_nz/ramdisk
265 13:18:37.731565 >> 129966 blocks
266 13:18:39.806187 rename /var/lib/lava/dispatcher/tmp/14879048/extract-overlay-ramdisk-i0a15_nz/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14879048/tftp-deploy-56hlfbtr/ramdisk/ramdisk.cpio.gz
267 13:18:39.806340 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 13:18:39.806468 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 13:18:39.806564 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 13:18:39.806642 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14879048/tftp-deploy-56hlfbtr/kernel/Image']
271 13:18:53.894488 Returned 0 in 14 seconds
272 13:18:53.894680 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14879048/tftp-deploy-56hlfbtr/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14879048/tftp-deploy-56hlfbtr/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14879048/tftp-deploy-56hlfbtr/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14879048/tftp-deploy-56hlfbtr/kernel/image.itb
273 13:18:54.296720 output: FIT description: Kernel Image image with one or more FDT blobs
274 13:18:54.296844 output: Created: Thu Jul 18 14:18:54 2024
275 13:18:54.296903 output: Image 0 (kernel-1)
276 13:18:54.296957 output: Description:
277 13:18:54.297008 output: Created: Thu Jul 18 14:18:54 2024
278 13:18:54.297059 output: Type: Kernel Image
279 13:18:54.297109 output: Compression: lzma compressed
280 13:18:54.297160 output: Data Size: 13114469 Bytes = 12807.10 KiB = 12.51 MiB
281 13:18:54.297209 output: Architecture: AArch64
282 13:18:54.297257 output: OS: Linux
283 13:18:54.297304 output: Load Address: 0x00000000
284 13:18:54.297352 output: Entry Point: 0x00000000
285 13:18:54.297399 output: Hash algo: crc32
286 13:18:54.297448 output: Hash value: a47b020b
287 13:18:54.297496 output: Image 1 (fdt-1)
288 13:18:54.297543 output: Description: mt8192-asurada-spherion-r0
289 13:18:54.297590 output: Created: Thu Jul 18 14:18:54 2024
290 13:18:54.297638 output: Type: Flat Device Tree
291 13:18:54.297686 output: Compression: uncompressed
292 13:18:54.297732 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 13:18:54.297781 output: Architecture: AArch64
294 13:18:54.297828 output: Hash algo: crc32
295 13:18:54.297875 output: Hash value: 0f8e4d2e
296 13:18:54.297922 output: Image 2 (ramdisk-1)
297 13:18:54.297968 output: Description: unavailable
298 13:18:54.298016 output: Created: Thu Jul 18 14:18:54 2024
299 13:18:54.298064 output: Type: RAMDisk Image
300 13:18:54.298111 output: Compression: uncompressed
301 13:18:54.298158 output: Data Size: 18721602 Bytes = 18282.81 KiB = 17.85 MiB
302 13:18:54.298206 output: Architecture: AArch64
303 13:18:54.298252 output: OS: Linux
304 13:18:54.298299 output: Load Address: unavailable
305 13:18:54.298346 output: Entry Point: unavailable
306 13:18:54.298393 output: Hash algo: crc32
307 13:18:54.298468 output: Hash value: 81311f64
308 13:18:54.298548 output: Default Configuration: 'conf-1'
309 13:18:54.298623 output: Configuration 0 (conf-1)
310 13:18:54.298700 output: Description: mt8192-asurada-spherion-r0
311 13:18:54.298773 output: Kernel: kernel-1
312 13:18:54.298832 output: Init Ramdisk: ramdisk-1
313 13:18:54.298881 output: FDT: fdt-1
314 13:18:54.298928 output: Loadables: kernel-1
315 13:18:54.298975 output:
316 13:18:54.299071 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 13:18:54.299145 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 13:18:54.299218 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 13:18:54.299291 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 13:18:54.299347 No LXC device requested
321 13:18:54.299438 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 13:18:54.299513 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 13:18:54.299593 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 13:18:54.299647 Checking files for TFTP limit of 4294967296 bytes.
325 13:18:54.300019 end: 1 tftp-deploy (duration 00:00:42) [common]
326 13:18:54.300144 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 13:18:54.300237 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 13:18:54.300327 substitutions:
329 13:18:54.300385 - {DTB}: 14879048/tftp-deploy-56hlfbtr/dtb/mt8192-asurada-spherion-r0.dtb
330 13:18:54.300439 - {INITRD}: 14879048/tftp-deploy-56hlfbtr/ramdisk/ramdisk.cpio.gz
331 13:18:54.300491 - {KERNEL}: 14879048/tftp-deploy-56hlfbtr/kernel/Image
332 13:18:54.300541 - {LAVA_MAC}: None
333 13:18:54.300591 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14879048/extract-nfsrootfs-brtvvc40
334 13:18:54.300641 - {NFS_SERVER_IP}: 192.168.201.1
335 13:18:54.300690 - {PRESEED_CONFIG}: None
336 13:18:54.300742 - {PRESEED_LOCAL}: None
337 13:18:54.300791 - {RAMDISK}: 14879048/tftp-deploy-56hlfbtr/ramdisk/ramdisk.cpio.gz
338 13:18:54.300839 - {ROOT_PART}: None
339 13:18:54.300886 - {ROOT}: None
340 13:18:54.300934 - {SERVER_IP}: 192.168.201.1
341 13:18:54.300984 - {TEE}: None
342 13:18:54.301042 Parsed boot commands:
343 13:18:54.301089 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 13:18:54.301227 Parsed boot commands: tftpboot 192.168.201.1 14879048/tftp-deploy-56hlfbtr/kernel/image.itb 14879048/tftp-deploy-56hlfbtr/kernel/cmdline
345 13:18:54.301306 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 13:18:54.301379 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 13:18:54.301451 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 13:18:54.301521 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 13:18:54.301576 Not connected, no need to disconnect.
350 13:18:54.301641 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 13:18:54.301709 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 13:18:54.301763 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 13:18:54.304699 Setting prompt string to ['lava-test: # ']
354 13:18:54.305003 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 13:18:54.305099 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 13:18:54.305220 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 13:18:54.305330 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 13:18:54.305515 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=reboot']
359 13:19:03.449308 >> Command sent successfully.
360 13:19:03.453344 Returned 0 in 9 seconds
361 13:19:03.453496 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 13:19:03.453790 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 13:19:03.453900 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 13:19:03.453975 Setting prompt string to 'Starting depthcharge on Spherion...'
366 13:19:03.454030 Changing prompt to 'Starting depthcharge on Spherion...'
367 13:19:03.454095 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 13:19:03.454587 [Enter `^Ec?' for help]
369 13:19:05.079674
370 13:19:05.079801 F0: 102B 0000
371 13:19:05.079867
372 13:19:05.083125 F3: 1001 0000 [0200]
373 13:19:05.083202
374 13:19:05.083260 F3: 1001 0000
375 13:19:05.083319
376 13:19:05.083370 F7: 102D 0000
377 13:19:05.083423
378 13:19:05.086934 F1: 0000 0000
379 13:19:05.087038
380 13:19:05.087136 V0: 0000 0000 [0001]
381 13:19:05.087217
382 13:19:05.087300 00: 0007 8000
383 13:19:05.087381
384 13:19:05.090679 01: 0000 0000
385 13:19:05.090769
386 13:19:05.090851 BP: 0C00 0209 [0000]
387 13:19:05.090928
388 13:19:05.094461 G0: 1182 0000
389 13:19:05.094536
390 13:19:05.094592 EC: 0000 0021 [4000]
391 13:19:05.094645
392 13:19:05.098272 S7: 0000 0000 [0000]
393 13:19:05.098441
394 13:19:05.098543 CC: 0000 0000 [0001]
395 13:19:05.098618
396 13:19:05.101439 T0: 0000 0040 [010F]
397 13:19:05.101532
398 13:19:05.101611 Jump to BL
399 13:19:05.101694
400 13:19:05.126811
401 13:19:05.126901
402 13:19:05.133495 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 13:19:05.136581 ARM64: Exception handlers installed.
404 13:19:05.140149 ARM64: Testing exception
405 13:19:05.143953 ARM64: Done test exception
406 13:19:05.150794 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 13:19:05.160620 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 13:19:05.167617 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 13:19:05.177582 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 13:19:05.184221 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 13:19:05.194393 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 13:19:05.204261 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 13:19:05.211188 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 13:19:05.229477 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 13:19:05.232574 WDT: Last reset was cold boot
416 13:19:05.236309 SPI1(PAD0) initialized at 2873684 Hz
417 13:19:05.239798 SPI5(PAD0) initialized at 992727 Hz
418 13:19:05.242657 VBOOT: Loading verstage.
419 13:19:05.249213 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 13:19:05.252804 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 13:19:05.256137 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 13:19:05.259286 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 13:19:05.267035 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 13:19:05.273446 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 13:19:05.284623 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
426 13:19:05.284705
427 13:19:05.284764
428 13:19:05.294449 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 13:19:05.298069 ARM64: Exception handlers installed.
430 13:19:05.300912 ARM64: Testing exception
431 13:19:05.300986 ARM64: Done test exception
432 13:19:05.307911 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 13:19:05.311096 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 13:19:05.325501 Probing TPM: . done!
435 13:19:05.325617 TPM ready after 0 ms
436 13:19:05.332448 Connected to device vid:did:rid of 1ae0:0028:00
437 13:19:05.338717 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
438 13:19:05.379288 Initialized TPM device CR50 revision 0
439 13:19:05.391221 tlcl_send_startup: Startup return code is 0
440 13:19:05.391328 TPM: setup succeeded
441 13:19:05.402470 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 13:19:05.411319 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 13:19:05.417937 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 13:19:05.430550 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 13:19:05.433662 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 13:19:05.436923 in-header: 03 07 00 00 08 00 00 00
447 13:19:05.440449 in-data: aa e4 47 04 13 02 00 00
448 13:19:05.443658 Chrome EC: UHEPI supported
449 13:19:05.449990 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 13:19:05.453604 in-header: 03 a9 00 00 08 00 00 00
451 13:19:05.456971 in-data: 84 60 60 08 00 00 00 00
452 13:19:05.457034 Phase 1
453 13:19:05.460180 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 13:19:05.466931 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 13:19:05.473375 VB2:vb2_check_recovery() Recovery was requested manually
456 13:19:05.476472 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 13:19:05.480337 Recovery requested (1009000e)
458 13:19:05.488891 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 13:19:05.494181 tlcl_extend: response is 0
460 13:19:05.502026 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 13:19:05.507711 tlcl_extend: response is 0
462 13:19:05.513910 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 13:19:05.535562 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
464 13:19:05.541891 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 13:19:05.541969
466 13:19:05.542043
467 13:19:05.552807 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 13:19:05.555864 ARM64: Exception handlers installed.
469 13:19:05.555936 ARM64: Testing exception
470 13:19:05.558931 ARM64: Done test exception
471 13:19:05.579925 pmic_efuse_setting: Set efuses in 11 msecs
472 13:19:05.583700 pmwrap_interface_init: Select PMIF_VLD_RDY
473 13:19:05.589977 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 13:19:05.593645 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 13:19:05.599910 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 13:19:05.603671 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 13:19:05.609975 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 13:19:05.613040 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 13:19:05.620024 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 13:19:05.622863 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 13:19:05.626247 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 13:19:05.632751 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 13:19:05.636147 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 13:19:05.643133 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 13:19:05.646141 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 13:19:05.652897 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 13:19:05.659783 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 13:19:05.662640 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 13:19:05.669547 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 13:19:05.676275 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 13:19:05.679372 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 13:19:05.685725 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 13:19:05.692570 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 13:19:05.695754 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 13:19:05.702628 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 13:19:05.709479 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 13:19:05.712585 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 13:19:05.718918 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 13:19:05.725927 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 13:19:05.729165 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 13:19:05.735536 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 13:19:05.739131 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 13:19:05.745496 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 13:19:05.748977 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 13:19:05.755388 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 13:19:05.758947 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 13:19:05.765329 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 13:19:05.768701 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 13:19:05.775064 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 13:19:05.778768 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 13:19:05.781728 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 13:19:05.789528 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 13:19:05.792728 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 13:19:05.795915 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 13:19:05.802886 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 13:19:05.805916 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 13:19:05.809006 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 13:19:05.815862 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 13:19:05.819052 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 13:19:05.822239 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 13:19:05.826069 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 13:19:05.832510 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 13:19:05.835679 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 13:19:05.842639 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 13:19:05.852031 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 13:19:05.855561 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 13:19:05.865751 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 13:19:05.871980 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 13:19:05.875667 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 13:19:05.882141 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 13:19:05.885381 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 13:19:05.892738 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2
533 13:19:05.899676 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 13:19:05.902748 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
535 13:19:05.906610 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 13:19:05.917491 [RTC]rtc_get_frequency_meter,154: input=15, output=834
537 13:19:05.926948 [RTC]rtc_get_frequency_meter,154: input=7, output=708
538 13:19:05.936558 [RTC]rtc_get_frequency_meter,154: input=11, output=772
539 13:19:05.946002 [RTC]rtc_get_frequency_meter,154: input=13, output=803
540 13:19:05.955305 [RTC]rtc_get_frequency_meter,154: input=12, output=787
541 13:19:05.964782 [RTC]rtc_get_frequency_meter,154: input=12, output=787
542 13:19:05.974616 [RTC]rtc_get_frequency_meter,154: input=13, output=803
543 13:19:05.977868 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
544 13:19:05.984702 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
545 13:19:05.987862 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 13:19:05.991644 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
547 13:19:05.998384 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 13:19:06.001500 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
549 13:19:06.004550 ADC[4]: Raw value=905988 ID=7
550 13:19:06.004626 ADC[3]: Raw value=213282 ID=1
551 13:19:06.008129 RAM Code: 0x71
552 13:19:06.011089 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 13:19:06.017839 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 13:19:06.024494 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 13:19:06.030846 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 13:19:06.034210 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 13:19:06.038049 in-header: 03 07 00 00 08 00 00 00
558 13:19:06.041073 in-data: aa e4 47 04 13 02 00 00
559 13:19:06.044258 Chrome EC: UHEPI supported
560 13:19:06.051208 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 13:19:06.054444 in-header: 03 a9 00 00 08 00 00 00
562 13:19:06.057583 in-data: 84 60 60 08 00 00 00 00
563 13:19:06.061094 MRC: failed to locate region type 0.
564 13:19:06.067828 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 13:19:06.071343 DRAM-K: Running full calibration
566 13:19:06.077898 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 13:19:06.080970 header.status = 0x0
568 13:19:06.084181 header.version = 0x6 (expected: 0x6)
569 13:19:06.087376 header.size = 0xd00 (expected: 0xd00)
570 13:19:06.087501 header.flags = 0x0
571 13:19:06.094295 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 13:19:06.112415 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
573 13:19:06.118974 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 13:19:06.122038 dram_init: ddr_geometry: 2
575 13:19:06.125891 [EMI] MDL number = 2
576 13:19:06.125970 [EMI] Get MDL freq = 0
577 13:19:06.128451 dram_init: ddr_type: 0
578 13:19:06.128527 is_discrete_lpddr4: 1
579 13:19:06.132213 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 13:19:06.132287
581 13:19:06.132345
582 13:19:06.135258 [Bian_co] ETT version 0.0.0.1
583 13:19:06.142244 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 13:19:06.142343
585 13:19:06.145168 dramc_set_vcore_voltage set vcore to 650000
586 13:19:06.148779 Read voltage for 800, 4
587 13:19:06.148854 Vio18 = 0
588 13:19:06.148912 Vcore = 650000
589 13:19:06.152078 Vdram = 0
590 13:19:06.152153 Vddq = 0
591 13:19:06.152231 Vmddr = 0
592 13:19:06.155176 dram_init: config_dvfs: 1
593 13:19:06.158251 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 13:19:06.165131 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 13:19:06.168648 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
596 13:19:06.171467 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
597 13:19:06.175289 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
598 13:19:06.178462 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
599 13:19:06.181963 MEM_TYPE=3, freq_sel=18
600 13:19:06.185492 sv_algorithm_assistance_LP4_1600
601 13:19:06.188693 ============ PULL DRAM RESETB DOWN ============
602 13:19:06.192532 ========== PULL DRAM RESETB DOWN end =========
603 13:19:06.199967 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 13:19:06.200041 ===================================
605 13:19:06.203821 LPDDR4 DRAM CONFIGURATION
606 13:19:06.207438 ===================================
607 13:19:06.207518 EX_ROW_EN[0] = 0x0
608 13:19:06.211286 EX_ROW_EN[1] = 0x0
609 13:19:06.214436 LP4Y_EN = 0x0
610 13:19:06.214502 WORK_FSP = 0x0
611 13:19:06.214557 WL = 0x2
612 13:19:06.218800 RL = 0x2
613 13:19:06.218863 BL = 0x2
614 13:19:06.221797 RPST = 0x0
615 13:19:06.221862 RD_PRE = 0x0
616 13:19:06.225404 WR_PRE = 0x1
617 13:19:06.225470 WR_PST = 0x0
618 13:19:06.229049 DBI_WR = 0x0
619 13:19:06.229115 DBI_RD = 0x0
620 13:19:06.232124 OTF = 0x1
621 13:19:06.235948 ===================================
622 13:19:06.238959 ===================================
623 13:19:06.239044 ANA top config
624 13:19:06.242666 ===================================
625 13:19:06.245794 DLL_ASYNC_EN = 0
626 13:19:06.248865 ALL_SLAVE_EN = 1
627 13:19:06.252047 NEW_RANK_MODE = 1
628 13:19:06.252125 DLL_IDLE_MODE = 1
629 13:19:06.255755 LP45_APHY_COMB_EN = 1
630 13:19:06.258874 TX_ODT_DIS = 1
631 13:19:06.262342 NEW_8X_MODE = 1
632 13:19:06.265610 ===================================
633 13:19:06.268621 ===================================
634 13:19:06.272253 data_rate = 1600
635 13:19:06.272328 CKR = 1
636 13:19:06.275826 DQ_P2S_RATIO = 8
637 13:19:06.278633 ===================================
638 13:19:06.282212 CA_P2S_RATIO = 8
639 13:19:06.285316 DQ_CA_OPEN = 0
640 13:19:06.288921 DQ_SEMI_OPEN = 0
641 13:19:06.288997 CA_SEMI_OPEN = 0
642 13:19:06.292250 CA_FULL_RATE = 0
643 13:19:06.295383 DQ_CKDIV4_EN = 1
644 13:19:06.298886 CA_CKDIV4_EN = 1
645 13:19:06.302107 CA_PREDIV_EN = 0
646 13:19:06.305267 PH8_DLY = 0
647 13:19:06.305344 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 13:19:06.308851 DQ_AAMCK_DIV = 4
649 13:19:06.311975 CA_AAMCK_DIV = 4
650 13:19:06.315129 CA_ADMCK_DIV = 4
651 13:19:06.318838 DQ_TRACK_CA_EN = 0
652 13:19:06.322002 CA_PICK = 800
653 13:19:06.325175 CA_MCKIO = 800
654 13:19:06.325250 MCKIO_SEMI = 0
655 13:19:06.328931 PLL_FREQ = 3068
656 13:19:06.332364 DQ_UI_PI_RATIO = 32
657 13:19:06.335302 CA_UI_PI_RATIO = 0
658 13:19:06.338827 ===================================
659 13:19:06.341836 ===================================
660 13:19:06.344981 memory_type:LPDDR4
661 13:19:06.345057 GP_NUM : 10
662 13:19:06.348759 SRAM_EN : 1
663 13:19:06.351814 MD32_EN : 0
664 13:19:06.355036 ===================================
665 13:19:06.355112 [ANA_INIT] >>>>>>>>>>>>>>
666 13:19:06.358259 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 13:19:06.362011 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 13:19:06.365124 ===================================
669 13:19:06.368231 data_rate = 1600,PCW = 0X7600
670 13:19:06.372006 ===================================
671 13:19:06.374808 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 13:19:06.381848 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 13:19:06.384660 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 13:19:06.391892 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 13:19:06.394957 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 13:19:06.398034 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 13:19:06.398110 [ANA_INIT] flow start
678 13:19:06.401480 [ANA_INIT] PLL >>>>>>>>
679 13:19:06.404696 [ANA_INIT] PLL <<<<<<<<
680 13:19:06.404772 [ANA_INIT] MIDPI >>>>>>>>
681 13:19:06.408511 [ANA_INIT] MIDPI <<<<<<<<
682 13:19:06.411593 [ANA_INIT] DLL >>>>>>>>
683 13:19:06.411668 [ANA_INIT] flow end
684 13:19:06.418441 ============ LP4 DIFF to SE enter ============
685 13:19:06.421556 ============ LP4 DIFF to SE exit ============
686 13:19:06.424614 [ANA_INIT] <<<<<<<<<<<<<
687 13:19:06.428364 [Flow] Enable top DCM control >>>>>
688 13:19:06.431540 [Flow] Enable top DCM control <<<<<
689 13:19:06.431616 Enable DLL master slave shuffle
690 13:19:06.438387 ==============================================================
691 13:19:06.441659 Gating Mode config
692 13:19:06.445076 ==============================================================
693 13:19:06.448141 Config description:
694 13:19:06.457903 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 13:19:06.464772 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 13:19:06.468082 SELPH_MODE 0: By rank 1: By Phase
697 13:19:06.474328 ==============================================================
698 13:19:06.477966 GAT_TRACK_EN = 1
699 13:19:06.480941 RX_GATING_MODE = 2
700 13:19:06.484645 RX_GATING_TRACK_MODE = 2
701 13:19:06.487595 SELPH_MODE = 1
702 13:19:06.491198 PICG_EARLY_EN = 1
703 13:19:06.491273 VALID_LAT_VALUE = 1
704 13:19:06.497546 ==============================================================
705 13:19:06.501352 Enter into Gating configuration >>>>
706 13:19:06.504330 Exit from Gating configuration <<<<
707 13:19:06.507806 Enter into DVFS_PRE_config >>>>>
708 13:19:06.517707 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 13:19:06.520806 Exit from DVFS_PRE_config <<<<<
710 13:19:06.524514 Enter into PICG configuration >>>>
711 13:19:06.527707 Exit from PICG configuration <<<<
712 13:19:06.530970 [RX_INPUT] configuration >>>>>
713 13:19:06.534076 [RX_INPUT] configuration <<<<<
714 13:19:06.537753 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 13:19:06.544080 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 13:19:06.551040 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 13:19:06.557948 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 13:19:06.564258 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 13:19:06.567636 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 13:19:06.574332 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 13:19:06.577443 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 13:19:06.581159 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 13:19:06.584329 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 13:19:06.591058 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 13:19:06.594221 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 13:19:06.597774 ===================================
727 13:19:06.600766 LPDDR4 DRAM CONFIGURATION
728 13:19:06.604145 ===================================
729 13:19:06.604222 EX_ROW_EN[0] = 0x0
730 13:19:06.607216 EX_ROW_EN[1] = 0x0
731 13:19:06.607315 LP4Y_EN = 0x0
732 13:19:06.610898 WORK_FSP = 0x0
733 13:19:06.610973 WL = 0x2
734 13:19:06.614410 RL = 0x2
735 13:19:06.614484 BL = 0x2
736 13:19:06.617331 RPST = 0x0
737 13:19:06.617405 RD_PRE = 0x0
738 13:19:06.620438 WR_PRE = 0x1
739 13:19:06.624076 WR_PST = 0x0
740 13:19:06.624151 DBI_WR = 0x0
741 13:19:06.627276 DBI_RD = 0x0
742 13:19:06.627351 OTF = 0x1
743 13:19:06.630372 ===================================
744 13:19:06.634114 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 13:19:06.637177 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 13:19:06.644195 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 13:19:06.647391 ===================================
748 13:19:06.650520 LPDDR4 DRAM CONFIGURATION
749 13:19:06.653729 ===================================
750 13:19:06.653805 EX_ROW_EN[0] = 0x10
751 13:19:06.657504 EX_ROW_EN[1] = 0x0
752 13:19:06.657579 LP4Y_EN = 0x0
753 13:19:06.660554 WORK_FSP = 0x0
754 13:19:06.660629 WL = 0x2
755 13:19:06.663711 RL = 0x2
756 13:19:06.663786 BL = 0x2
757 13:19:06.667374 RPST = 0x0
758 13:19:06.667474 RD_PRE = 0x0
759 13:19:06.670296 WR_PRE = 0x1
760 13:19:06.670371 WR_PST = 0x0
761 13:19:06.673721 DBI_WR = 0x0
762 13:19:06.677212 DBI_RD = 0x0
763 13:19:06.677287 OTF = 0x1
764 13:19:06.680291 ===================================
765 13:19:06.686840 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 13:19:06.690471 nWR fixed to 40
767 13:19:06.694074 [ModeRegInit_LP4] CH0 RK0
768 13:19:06.694149 [ModeRegInit_LP4] CH0 RK1
769 13:19:06.697139 [ModeRegInit_LP4] CH1 RK0
770 13:19:06.700166 [ModeRegInit_LP4] CH1 RK1
771 13:19:06.700244 match AC timing 13
772 13:19:06.707090 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 13:19:06.710116 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 13:19:06.714124 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 13:19:06.720334 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 13:19:06.723705 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 13:19:06.727018 [EMI DOE] emi_dcm 0
778 13:19:06.730129 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 13:19:06.730205 ==
780 13:19:06.733319 Dram Type= 6, Freq= 0, CH_0, rank 0
781 13:19:06.736998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 13:19:06.737069 ==
783 13:19:06.743289 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 13:19:06.749710 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 13:19:06.757896 [CA 0] Center 37 (7~68) winsize 62
786 13:19:06.761057 [CA 1] Center 37 (6~68) winsize 63
787 13:19:06.764668 [CA 2] Center 34 (4~65) winsize 62
788 13:19:06.767805 [CA 3] Center 34 (4~65) winsize 62
789 13:19:06.771700 [CA 4] Center 34 (4~64) winsize 61
790 13:19:06.775370 [CA 5] Center 33 (3~64) winsize 62
791 13:19:06.775509
792 13:19:06.778528 [CmdBusTrainingLP45] Vref(ca) range 1: 32
793 13:19:06.778604
794 13:19:06.782311 [CATrainingPosCal] consider 1 rank data
795 13:19:06.785876 u2DelayCellTimex100 = 270/100 ps
796 13:19:06.789352 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
797 13:19:06.792221 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
798 13:19:06.796067 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
799 13:19:06.799543 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
800 13:19:06.802419 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
801 13:19:06.805804 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
802 13:19:06.805880
803 13:19:06.812354 CA PerBit enable=1, Macro0, CA PI delay=33
804 13:19:06.812444
805 13:19:06.815581 [CBTSetCACLKResult] CA Dly = 33
806 13:19:06.815656 CS Dly: 6 (0~37)
807 13:19:06.815714 ==
808 13:19:06.819331 Dram Type= 6, Freq= 0, CH_0, rank 1
809 13:19:06.822165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 13:19:06.822242 ==
811 13:19:06.828916 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 13:19:06.835590 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 13:19:06.844326 [CA 0] Center 37 (7~68) winsize 62
814 13:19:06.847537 [CA 1] Center 37 (7~68) winsize 62
815 13:19:06.850580 [CA 2] Center 34 (4~65) winsize 62
816 13:19:06.853877 [CA 3] Center 34 (4~65) winsize 62
817 13:19:06.857710 [CA 4] Center 33 (3~64) winsize 62
818 13:19:06.860774 [CA 5] Center 33 (3~64) winsize 62
819 13:19:06.860850
820 13:19:06.863923 [CmdBusTrainingLP45] Vref(ca) range 1: 30
821 13:19:06.863999
822 13:19:06.867642 [CATrainingPosCal] consider 2 rank data
823 13:19:06.870613 u2DelayCellTimex100 = 270/100 ps
824 13:19:06.873764 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
825 13:19:06.880614 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
826 13:19:06.884262 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
827 13:19:06.887384 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
828 13:19:06.890561 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
829 13:19:06.893757 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
830 13:19:06.893823
831 13:19:06.897350 CA PerBit enable=1, Macro0, CA PI delay=33
832 13:19:06.897424
833 13:19:06.900422 [CBTSetCACLKResult] CA Dly = 33
834 13:19:06.900500 CS Dly: 6 (0~38)
835 13:19:06.900561
836 13:19:06.907029 ----->DramcWriteLeveling(PI) begin...
837 13:19:06.907136 ==
838 13:19:06.910591 Dram Type= 6, Freq= 0, CH_0, rank 0
839 13:19:06.913326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 13:19:06.913402 ==
841 13:19:06.916855 Write leveling (Byte 0): 32 => 32
842 13:19:06.920350 Write leveling (Byte 1): 29 => 29
843 13:19:06.923696 DramcWriteLeveling(PI) end<-----
844 13:19:06.923784
845 13:19:06.923844 ==
846 13:19:06.926949 Dram Type= 6, Freq= 0, CH_0, rank 0
847 13:19:06.930399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 13:19:06.930496 ==
849 13:19:06.933305 [Gating] SW mode calibration
850 13:19:06.940033 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 13:19:06.947095 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 13:19:06.950226 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 13:19:06.953467 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
854 13:19:06.960263 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
855 13:19:06.963441 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 13:19:06.966613 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 13:19:06.973414 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 13:19:06.976500 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 13:19:06.980270 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 13:19:06.986475 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 13:19:06.990246 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 13:19:06.993318 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 13:19:06.996412 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 13:19:07.003141 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 13:19:07.006303 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 13:19:07.010193 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 13:19:07.016498 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 13:19:07.020103 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
869 13:19:07.023511 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
870 13:19:07.029730 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
871 13:19:07.033335 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
872 13:19:07.036326 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 13:19:07.042998 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 13:19:07.046475 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 13:19:07.049477 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 13:19:07.056496 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 13:19:07.059777 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 13:19:07.062924 0 9 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
879 13:19:07.069755 0 9 12 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
880 13:19:07.073005 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 13:19:07.076243 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 13:19:07.082881 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 13:19:07.086547 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 13:19:07.089571 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 13:19:07.095898 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
886 13:19:07.099736 0 10 8 | B1->B0 | 3333 2a2a | 0 0 | (0 1) (0 1)
887 13:19:07.102823 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
888 13:19:07.109652 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 13:19:07.113000 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 13:19:07.116060 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 13:19:07.122875 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 13:19:07.125932 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 13:19:07.129577 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 13:19:07.135759 0 11 8 | B1->B0 | 2424 3838 | 0 0 | (0 0) (0 0)
895 13:19:07.139447 0 11 12 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
896 13:19:07.142632 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 13:19:07.148992 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 13:19:07.152313 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 13:19:07.155619 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 13:19:07.159050 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 13:19:07.165558 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
902 13:19:07.168766 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
903 13:19:07.172799 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 13:19:07.179080 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 13:19:07.182824 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 13:19:07.185898 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 13:19:07.192788 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 13:19:07.195790 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 13:19:07.199020 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 13:19:07.205902 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 13:19:07.209044 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 13:19:07.212585 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 13:19:07.218856 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 13:19:07.222493 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 13:19:07.225625 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 13:19:07.232634 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 13:19:07.235867 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
918 13:19:07.238747 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 13:19:07.245713 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 13:19:07.245833 Total UI for P1: 0, mck2ui 16
921 13:19:07.252491 best dqsien dly found for B0: ( 0, 14, 6)
922 13:19:07.252567 Total UI for P1: 0, mck2ui 16
923 13:19:07.255569 best dqsien dly found for B1: ( 0, 14, 10)
924 13:19:07.262269 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
925 13:19:07.265121 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
926 13:19:07.265197
927 13:19:07.269048 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
928 13:19:07.272099 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
929 13:19:07.275188 [Gating] SW calibration Done
930 13:19:07.275301 ==
931 13:19:07.278529 Dram Type= 6, Freq= 0, CH_0, rank 0
932 13:19:07.282309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 13:19:07.282386 ==
934 13:19:07.285401 RX Vref Scan: 0
935 13:19:07.285476
936 13:19:07.285535 RX Vref 0 -> 0, step: 1
937 13:19:07.285589
938 13:19:07.289069 RX Delay -130 -> 252, step: 16
939 13:19:07.292215 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
940 13:19:07.299094 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
941 13:19:07.302301 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
942 13:19:07.305386 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
943 13:19:07.308434 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
944 13:19:07.312247 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
945 13:19:07.318462 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
946 13:19:07.322362 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
947 13:19:07.325438 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
948 13:19:07.328688 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
949 13:19:07.331917 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
950 13:19:07.338219 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
951 13:19:07.341925 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
952 13:19:07.345031 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
953 13:19:07.348722 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
954 13:19:07.355078 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
955 13:19:07.355155 ==
956 13:19:07.358513 Dram Type= 6, Freq= 0, CH_0, rank 0
957 13:19:07.361749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 13:19:07.361864 ==
959 13:19:07.361949 DQS Delay:
960 13:19:07.364708 DQS0 = 0, DQS1 = 0
961 13:19:07.364816 DQM Delay:
962 13:19:07.368514 DQM0 = 86, DQM1 = 71
963 13:19:07.368606 DQ Delay:
964 13:19:07.371644 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
965 13:19:07.374624 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
966 13:19:07.377982 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
967 13:19:07.381425 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
968 13:19:07.381495
969 13:19:07.381552
970 13:19:07.381605 ==
971 13:19:07.384428 Dram Type= 6, Freq= 0, CH_0, rank 0
972 13:19:07.387928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 13:19:07.388017 ==
974 13:19:07.388097
975 13:19:07.391254
976 13:19:07.391340 TX Vref Scan disable
977 13:19:07.394565 == TX Byte 0 ==
978 13:19:07.397797 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
979 13:19:07.401356 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
980 13:19:07.404457 == TX Byte 1 ==
981 13:19:07.407561 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
982 13:19:07.411244 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
983 13:19:07.411343 ==
984 13:19:07.414531 Dram Type= 6, Freq= 0, CH_0, rank 0
985 13:19:07.421348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
986 13:19:07.421422 ==
987 13:19:07.433156 TX Vref=22, minBit 8, minWin=27, winSum=443
988 13:19:07.437057 TX Vref=24, minBit 8, minWin=27, winSum=443
989 13:19:07.440105 TX Vref=26, minBit 14, minWin=27, winSum=449
990 13:19:07.443312 TX Vref=28, minBit 8, minWin=27, winSum=449
991 13:19:07.446407 TX Vref=30, minBit 8, minWin=27, winSum=447
992 13:19:07.453336 TX Vref=32, minBit 11, minWin=26, winSum=446
993 13:19:07.456498 [TxChooseVref] Worse bit 14, Min win 27, Win sum 449, Final Vref 26
994 13:19:07.456568
995 13:19:07.459608 Final TX Range 1 Vref 26
996 13:19:07.459712
997 13:19:07.459790 ==
998 13:19:07.463055 Dram Type= 6, Freq= 0, CH_0, rank 0
999 13:19:07.466510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1000 13:19:07.469895 ==
1001 13:19:07.469986
1002 13:19:07.470071
1003 13:19:07.470152 TX Vref Scan disable
1004 13:19:07.473646 == TX Byte 0 ==
1005 13:19:07.476750 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1006 13:19:07.483081 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1007 13:19:07.483179 == TX Byte 1 ==
1008 13:19:07.486635 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1009 13:19:07.490073 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1010 13:19:07.493381
1011 13:19:07.493477 [DATLAT]
1012 13:19:07.493569 Freq=800, CH0 RK0
1013 13:19:07.493649
1014 13:19:07.496343 DATLAT Default: 0xa
1015 13:19:07.496437 0, 0xFFFF, sum = 0
1016 13:19:07.499970 1, 0xFFFF, sum = 0
1017 13:19:07.500038 2, 0xFFFF, sum = 0
1018 13:19:07.503317 3, 0xFFFF, sum = 0
1019 13:19:07.506734 4, 0xFFFF, sum = 0
1020 13:19:07.506799 5, 0xFFFF, sum = 0
1021 13:19:07.509993 6, 0xFFFF, sum = 0
1022 13:19:07.510082 7, 0xFFFF, sum = 0
1023 13:19:07.513091 8, 0xFFFF, sum = 0
1024 13:19:07.513192 9, 0x0, sum = 1
1025 13:19:07.516903 10, 0x0, sum = 2
1026 13:19:07.516993 11, 0x0, sum = 3
1027 13:19:07.517078 12, 0x0, sum = 4
1028 13:19:07.519958 best_step = 10
1029 13:19:07.520043
1030 13:19:07.520125 ==
1031 13:19:07.523171 Dram Type= 6, Freq= 0, CH_0, rank 0
1032 13:19:07.526220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1033 13:19:07.526311 ==
1034 13:19:07.529934 RX Vref Scan: 1
1035 13:19:07.530019
1036 13:19:07.532951 Set Vref Range= 32 -> 127
1037 13:19:07.533053
1038 13:19:07.533133 RX Vref 32 -> 127, step: 1
1039 13:19:07.533211
1040 13:19:07.536128 RX Delay -111 -> 252, step: 8
1041 13:19:07.536188
1042 13:19:07.539269 Set Vref, RX VrefLevel [Byte0]: 32
1043 13:19:07.543066 [Byte1]: 32
1044 13:19:07.546144
1045 13:19:07.546207 Set Vref, RX VrefLevel [Byte0]: 33
1046 13:19:07.549422 [Byte1]: 33
1047 13:19:07.553823
1048 13:19:07.553897 Set Vref, RX VrefLevel [Byte0]: 34
1049 13:19:07.557084 [Byte1]: 34
1050 13:19:07.561361
1051 13:19:07.561438 Set Vref, RX VrefLevel [Byte0]: 35
1052 13:19:07.564605 [Byte1]: 35
1053 13:19:07.569518
1054 13:19:07.569592 Set Vref, RX VrefLevel [Byte0]: 36
1055 13:19:07.572507 [Byte1]: 36
1056 13:19:07.577148
1057 13:19:07.577215 Set Vref, RX VrefLevel [Byte0]: 37
1058 13:19:07.579987 [Byte1]: 37
1059 13:19:07.584356
1060 13:19:07.584424 Set Vref, RX VrefLevel [Byte0]: 38
1061 13:19:07.587506 [Byte1]: 38
1062 13:19:07.591916
1063 13:19:07.592003 Set Vref, RX VrefLevel [Byte0]: 39
1064 13:19:07.595777 [Byte1]: 39
1065 13:19:07.599870
1066 13:19:07.599958 Set Vref, RX VrefLevel [Byte0]: 40
1067 13:19:07.603187 [Byte1]: 40
1068 13:19:07.607377
1069 13:19:07.607492 Set Vref, RX VrefLevel [Byte0]: 41
1070 13:19:07.610542 [Byte1]: 41
1071 13:19:07.614964
1072 13:19:07.615055 Set Vref, RX VrefLevel [Byte0]: 42
1073 13:19:07.618394 [Byte1]: 42
1074 13:19:07.622762
1075 13:19:07.622870 Set Vref, RX VrefLevel [Byte0]: 43
1076 13:19:07.629044 [Byte1]: 43
1077 13:19:07.629138
1078 13:19:07.632586 Set Vref, RX VrefLevel [Byte0]: 44
1079 13:19:07.635740 [Byte1]: 44
1080 13:19:07.635809
1081 13:19:07.638891 Set Vref, RX VrefLevel [Byte0]: 45
1082 13:19:07.642656 [Byte1]: 45
1083 13:19:07.645833
1084 13:19:07.645898 Set Vref, RX VrefLevel [Byte0]: 46
1085 13:19:07.648993 [Byte1]: 46
1086 13:19:07.653374
1087 13:19:07.653465 Set Vref, RX VrefLevel [Byte0]: 47
1088 13:19:07.656519 [Byte1]: 47
1089 13:19:07.660956
1090 13:19:07.661028 Set Vref, RX VrefLevel [Byte0]: 48
1091 13:19:07.664006 [Byte1]: 48
1092 13:19:07.668361
1093 13:19:07.668428 Set Vref, RX VrefLevel [Byte0]: 49
1094 13:19:07.672048 [Byte1]: 49
1095 13:19:07.675908
1096 13:19:07.676003 Set Vref, RX VrefLevel [Byte0]: 50
1097 13:19:07.679739 [Byte1]: 50
1098 13:19:07.683988
1099 13:19:07.684081 Set Vref, RX VrefLevel [Byte0]: 51
1100 13:19:07.687501 [Byte1]: 51
1101 13:19:07.691419
1102 13:19:07.691527 Set Vref, RX VrefLevel [Byte0]: 52
1103 13:19:07.695026 [Byte1]: 52
1104 13:19:07.699277
1105 13:19:07.699385 Set Vref, RX VrefLevel [Byte0]: 53
1106 13:19:07.702391 [Byte1]: 53
1107 13:19:07.706681
1108 13:19:07.706772 Set Vref, RX VrefLevel [Byte0]: 54
1109 13:19:07.710266 [Byte1]: 54
1110 13:19:07.714495
1111 13:19:07.714580 Set Vref, RX VrefLevel [Byte0]: 55
1112 13:19:07.717742 [Byte1]: 55
1113 13:19:07.721788
1114 13:19:07.721868 Set Vref, RX VrefLevel [Byte0]: 56
1115 13:19:07.725008 [Byte1]: 56
1116 13:19:07.730033
1117 13:19:07.730125 Set Vref, RX VrefLevel [Byte0]: 57
1118 13:19:07.733039 [Byte1]: 57
1119 13:19:07.737585
1120 13:19:07.737675 Set Vref, RX VrefLevel [Byte0]: 58
1121 13:19:07.740833 [Byte1]: 58
1122 13:19:07.744942
1123 13:19:07.745010 Set Vref, RX VrefLevel [Byte0]: 59
1124 13:19:07.748472 [Byte1]: 59
1125 13:19:07.752882
1126 13:19:07.752977 Set Vref, RX VrefLevel [Byte0]: 60
1127 13:19:07.756085 [Byte1]: 60
1128 13:19:07.760490
1129 13:19:07.760585 Set Vref, RX VrefLevel [Byte0]: 61
1130 13:19:07.763604 [Byte1]: 61
1131 13:19:07.768022
1132 13:19:07.768115 Set Vref, RX VrefLevel [Byte0]: 62
1133 13:19:07.771192 [Byte1]: 62
1134 13:19:07.775522
1135 13:19:07.775618 Set Vref, RX VrefLevel [Byte0]: 63
1136 13:19:07.778590 [Byte1]: 63
1137 13:19:07.783003
1138 13:19:07.783115 Set Vref, RX VrefLevel [Byte0]: 64
1139 13:19:07.786823 [Byte1]: 64
1140 13:19:07.791170
1141 13:19:07.791263 Set Vref, RX VrefLevel [Byte0]: 65
1142 13:19:07.794206 [Byte1]: 65
1143 13:19:07.798453
1144 13:19:07.798546 Set Vref, RX VrefLevel [Byte0]: 66
1145 13:19:07.801934 [Byte1]: 66
1146 13:19:07.806147
1147 13:19:07.806241 Set Vref, RX VrefLevel [Byte0]: 67
1148 13:19:07.809251 [Byte1]: 67
1149 13:19:07.813596
1150 13:19:07.813693 Set Vref, RX VrefLevel [Byte0]: 68
1151 13:19:07.817240 [Byte1]: 68
1152 13:19:07.821661
1153 13:19:07.821759 Set Vref, RX VrefLevel [Byte0]: 69
1154 13:19:07.824774 [Byte1]: 69
1155 13:19:07.828776
1156 13:19:07.828872 Set Vref, RX VrefLevel [Byte0]: 70
1157 13:19:07.832600 [Byte1]: 70
1158 13:19:07.836995
1159 13:19:07.837078 Set Vref, RX VrefLevel [Byte0]: 71
1160 13:19:07.840146 [Byte1]: 71
1161 13:19:07.844658
1162 13:19:07.844723 Set Vref, RX VrefLevel [Byte0]: 72
1163 13:19:07.847655 [Byte1]: 72
1164 13:19:07.851964
1165 13:19:07.852028 Set Vref, RX VrefLevel [Byte0]: 73
1166 13:19:07.855358 [Byte1]: 73
1167 13:19:07.859782
1168 13:19:07.859857 Set Vref, RX VrefLevel [Byte0]: 74
1169 13:19:07.863030 [Byte1]: 74
1170 13:19:07.867312
1171 13:19:07.867390 Set Vref, RX VrefLevel [Byte0]: 75
1172 13:19:07.870857 [Byte1]: 75
1173 13:19:07.875319
1174 13:19:07.875389 Set Vref, RX VrefLevel [Byte0]: 76
1175 13:19:07.878446 [Byte1]: 76
1176 13:19:07.882926
1177 13:19:07.882994 Set Vref, RX VrefLevel [Byte0]: 77
1178 13:19:07.886039 [Byte1]: 77
1179 13:19:07.890460
1180 13:19:07.890524 Set Vref, RX VrefLevel [Byte0]: 78
1181 13:19:07.893502 [Byte1]: 78
1182 13:19:07.897868
1183 13:19:07.897931 Set Vref, RX VrefLevel [Byte0]: 79
1184 13:19:07.901444 [Byte1]: 79
1185 13:19:07.905748
1186 13:19:07.905842 Set Vref, RX VrefLevel [Byte0]: 80
1187 13:19:07.908663 [Byte1]: 80
1188 13:19:07.913416
1189 13:19:07.913485 Set Vref, RX VrefLevel [Byte0]: 81
1190 13:19:07.916466 [Byte1]: 81
1191 13:19:07.921000
1192 13:19:07.921088 Set Vref, RX VrefLevel [Byte0]: 82
1193 13:19:07.924142 [Byte1]: 82
1194 13:19:07.928624
1195 13:19:07.928694 Set Vref, RX VrefLevel [Byte0]: 83
1196 13:19:07.931707 [Byte1]: 83
1197 13:19:07.936188
1198 13:19:07.936252 Final RX Vref Byte 0 = 67 to rank0
1199 13:19:07.939740 Final RX Vref Byte 1 = 51 to rank0
1200 13:19:07.942463 Final RX Vref Byte 0 = 67 to rank1
1201 13:19:07.945976 Final RX Vref Byte 1 = 51 to rank1==
1202 13:19:07.949603 Dram Type= 6, Freq= 0, CH_0, rank 0
1203 13:19:07.955797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 13:19:07.955870 ==
1205 13:19:07.955927 DQS Delay:
1206 13:19:07.959404 DQS0 = 0, DQS1 = 0
1207 13:19:07.959511 DQM Delay:
1208 13:19:07.959565 DQM0 = 88, DQM1 = 76
1209 13:19:07.962616 DQ Delay:
1210 13:19:07.965672 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1211 13:19:07.969257 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =100
1212 13:19:07.972211 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1213 13:19:07.975561 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1214 13:19:07.975653
1215 13:19:07.975735
1216 13:19:07.982225 [DQSOSCAuto] RK0, (LSB)MR18= 0x4123, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
1217 13:19:07.985605 CH0 RK0: MR19=606, MR18=4123
1218 13:19:07.992447 CH0_RK0: MR19=0x606, MR18=0x4123, DQSOSC=393, MR23=63, INC=95, DEC=63
1219 13:19:07.992545
1220 13:19:08.036095 ----->DramcWriteLeveling(PI) begin...
1221 13:19:08.036225 ==
1222 13:19:08.036315 Dram Type= 6, Freq= 0, CH_0, rank 1
1223 13:19:08.036698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1224 13:19:08.036787 ==
1225 13:19:08.037407 Write leveling (Byte 0): 32 => 32
1226 13:19:08.037524 Write leveling (Byte 1): 30 => 30
1227 13:19:08.037792 DramcWriteLeveling(PI) end<-----
1228 13:19:08.037875
1229 13:19:08.037960 ==
1230 13:19:08.038046 Dram Type= 6, Freq= 0, CH_0, rank 1
1231 13:19:08.038134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1232 13:19:08.038219 ==
1233 13:19:08.038304 [Gating] SW mode calibration
1234 13:19:08.038390 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1235 13:19:08.038490 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1236 13:19:08.068749 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1237 13:19:08.069509 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1238 13:19:08.069664 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1239 13:19:08.069797 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 13:19:08.070075 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 13:19:08.070165 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 13:19:08.070255 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 13:19:08.070345 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 13:19:08.073061 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 13:19:08.080048 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 13:19:08.083122 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 13:19:08.086166 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 13:19:08.093249 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 13:19:08.096685 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 13:19:08.099406 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 13:19:08.106483 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 13:19:08.109573 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 13:19:08.112625 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 13:19:08.119463 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1255 13:19:08.122587 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 13:19:08.126026 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 13:19:08.132777 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 13:19:08.136008 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 13:19:08.139104 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 13:19:08.146063 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 13:19:08.149125 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 13:19:08.152235 0 9 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
1263 13:19:08.159080 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1264 13:19:08.162512 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1265 13:19:08.165426 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1266 13:19:08.172466 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1267 13:19:08.175974 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1268 13:19:08.178996 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1269 13:19:08.185741 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1270 13:19:08.188826 0 10 8 | B1->B0 | 3131 2525 | 1 0 | (1 0) (1 0)
1271 13:19:08.191960 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1272 13:19:08.199122 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1273 13:19:08.202099 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1274 13:19:08.205549 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1275 13:19:08.212056 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1276 13:19:08.215600 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1277 13:19:08.218741 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1278 13:19:08.225697 0 11 8 | B1->B0 | 2e2e 3b3b | 0 0 | (0 0) (1 1)
1279 13:19:08.228670 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1280 13:19:08.232412 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1281 13:19:08.238724 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1282 13:19:08.241980 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 13:19:08.245058 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 13:19:08.252021 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1285 13:19:08.255247 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 13:19:08.258338 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1287 13:19:08.265407 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 13:19:08.268480 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 13:19:08.271739 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 13:19:08.278364 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 13:19:08.281725 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 13:19:08.285137 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 13:19:08.291529 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 13:19:08.295107 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 13:19:08.298250 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 13:19:08.301811 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1297 13:19:08.308597 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1298 13:19:08.311620 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1299 13:19:08.315098 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1300 13:19:08.321722 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1301 13:19:08.325031 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1302 13:19:08.328176 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1303 13:19:08.335022 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1304 13:19:08.338140 Total UI for P1: 0, mck2ui 16
1305 13:19:08.341254 best dqsien dly found for B0: ( 0, 14, 8)
1306 13:19:08.344816 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1307 13:19:08.347762 Total UI for P1: 0, mck2ui 16
1308 13:19:08.350924 best dqsien dly found for B1: ( 0, 14, 10)
1309 13:19:08.354513 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1310 13:19:08.357870 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1311 13:19:08.357944
1312 13:19:08.360963 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1313 13:19:08.367938 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1314 13:19:08.368009 [Gating] SW calibration Done
1315 13:19:08.368068 ==
1316 13:19:08.371023 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 13:19:08.378000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1318 13:19:08.378066 ==
1319 13:19:08.378122 RX Vref Scan: 0
1320 13:19:08.378173
1321 13:19:08.381197 RX Vref 0 -> 0, step: 1
1322 13:19:08.381255
1323 13:19:08.384330 RX Delay -130 -> 252, step: 16
1324 13:19:08.387302 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1325 13:19:08.390933 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1326 13:19:08.394463 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1327 13:19:08.400903 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1328 13:19:08.404356 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1329 13:19:08.407612 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1330 13:19:08.410959 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1331 13:19:08.413866 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1332 13:19:08.420690 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1333 13:19:08.424153 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1334 13:19:08.427676 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1335 13:19:08.430682 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1336 13:19:08.433983 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1337 13:19:08.440768 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1338 13:19:08.444012 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1339 13:19:08.447156 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1340 13:19:08.447218 ==
1341 13:19:08.450796 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 13:19:08.454176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 13:19:08.457296 ==
1344 13:19:08.457358 DQS Delay:
1345 13:19:08.457411 DQS0 = 0, DQS1 = 0
1346 13:19:08.460453 DQM Delay:
1347 13:19:08.460526 DQM0 = 85, DQM1 = 77
1348 13:19:08.464158 DQ Delay:
1349 13:19:08.464229 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1350 13:19:08.467268 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1351 13:19:08.470456 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1352 13:19:08.477404 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1353 13:19:08.477497
1354 13:19:08.477549
1355 13:19:08.477628 ==
1356 13:19:08.480544 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 13:19:08.483769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 13:19:08.483853 ==
1359 13:19:08.483931
1360 13:19:08.484007
1361 13:19:08.486888 TX Vref Scan disable
1362 13:19:08.486946 == TX Byte 0 ==
1363 13:19:08.493537 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1364 13:19:08.496610 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1365 13:19:08.496686 == TX Byte 1 ==
1366 13:19:08.503372 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1367 13:19:08.506601 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1368 13:19:08.506701 ==
1369 13:19:08.510350 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 13:19:08.513320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 13:19:08.513418 ==
1372 13:19:08.527530 TX Vref=22, minBit 3, minWin=27, winSum=447
1373 13:19:08.530557 TX Vref=24, minBit 9, minWin=27, winSum=447
1374 13:19:08.534078 TX Vref=26, minBit 8, minWin=27, winSum=448
1375 13:19:08.537389 TX Vref=28, minBit 9, minWin=27, winSum=446
1376 13:19:08.540961 TX Vref=30, minBit 8, minWin=27, winSum=447
1377 13:19:08.547298 TX Vref=32, minBit 8, minWin=27, winSum=445
1378 13:19:08.550448 [TxChooseVref] Worse bit 8, Min win 27, Win sum 448, Final Vref 26
1379 13:19:08.550515
1380 13:19:08.554321 Final TX Range 1 Vref 26
1381 13:19:08.554396
1382 13:19:08.554454 ==
1383 13:19:08.557367 Dram Type= 6, Freq= 0, CH_0, rank 1
1384 13:19:08.560428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1385 13:19:08.560503 ==
1386 13:19:08.564330
1387 13:19:08.564405
1388 13:19:08.564473 TX Vref Scan disable
1389 13:19:08.567462 == TX Byte 0 ==
1390 13:19:08.570688 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1391 13:19:08.577435 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1392 13:19:08.577511 == TX Byte 1 ==
1393 13:19:08.580533 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1394 13:19:08.587508 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1395 13:19:08.587579
1396 13:19:08.587662 [DATLAT]
1397 13:19:08.587742 Freq=800, CH0 RK1
1398 13:19:08.587820
1399 13:19:08.590538 DATLAT Default: 0xa
1400 13:19:08.590626 0, 0xFFFF, sum = 0
1401 13:19:08.594157 1, 0xFFFF, sum = 0
1402 13:19:08.594221 2, 0xFFFF, sum = 0
1403 13:19:08.597072 3, 0xFFFF, sum = 0
1404 13:19:08.600807 4, 0xFFFF, sum = 0
1405 13:19:08.600873 5, 0xFFFF, sum = 0
1406 13:19:08.603953 6, 0xFFFF, sum = 0
1407 13:19:08.604047 7, 0xFFFF, sum = 0
1408 13:19:08.606969 8, 0xFFFF, sum = 0
1409 13:19:08.607062 9, 0x0, sum = 1
1410 13:19:08.610894 10, 0x0, sum = 2
1411 13:19:08.610959 11, 0x0, sum = 3
1412 13:19:08.611013 12, 0x0, sum = 4
1413 13:19:08.613890 best_step = 10
1414 13:19:08.613965
1415 13:19:08.614027 ==
1416 13:19:08.617030 Dram Type= 6, Freq= 0, CH_0, rank 1
1417 13:19:08.620565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 13:19:08.620659 ==
1419 13:19:08.623739 RX Vref Scan: 0
1420 13:19:08.623834
1421 13:19:08.626788 RX Vref 0 -> 0, step: 1
1422 13:19:08.626851
1423 13:19:08.626906 RX Delay -111 -> 252, step: 8
1424 13:19:08.634335 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1425 13:19:08.637280 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1426 13:19:08.640856 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1427 13:19:08.644333 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1428 13:19:08.647446 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1429 13:19:08.654068 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1430 13:19:08.657211 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1431 13:19:08.661014 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1432 13:19:08.664104 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1433 13:19:08.667197 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1434 13:19:08.674321 iDelay=217, Bit 10, Center 80 (-31 ~ 192) 224
1435 13:19:08.677523 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1436 13:19:08.680603 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1437 13:19:08.683745 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1438 13:19:08.690648 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1439 13:19:08.693822 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1440 13:19:08.693926 ==
1441 13:19:08.697068 Dram Type= 6, Freq= 0, CH_0, rank 1
1442 13:19:08.700685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 13:19:08.700757 ==
1444 13:19:08.700814 DQS Delay:
1445 13:19:08.703654 DQS0 = 0, DQS1 = 0
1446 13:19:08.703738 DQM Delay:
1447 13:19:08.707288 DQM0 = 85, DQM1 = 77
1448 13:19:08.707351 DQ Delay:
1449 13:19:08.710517 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =84
1450 13:19:08.714209 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1451 13:19:08.717325 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1452 13:19:08.720496 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1453 13:19:08.720570
1454 13:19:08.720631
1455 13:19:08.730196 [DQSOSCAuto] RK1, (LSB)MR18= 0x4007, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1456 13:19:08.730297 CH0 RK1: MR19=606, MR18=4007
1457 13:19:08.736946 CH0_RK1: MR19=0x606, MR18=0x4007, DQSOSC=393, MR23=63, INC=95, DEC=63
1458 13:19:08.740573 [RxdqsGatingPostProcess] freq 800
1459 13:19:08.747300 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1460 13:19:08.750361 Pre-setting of DQS Precalculation
1461 13:19:08.753404 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1462 13:19:08.753471 ==
1463 13:19:08.757008 Dram Type= 6, Freq= 0, CH_1, rank 0
1464 13:19:08.763736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1465 13:19:08.763809 ==
1466 13:19:08.766919 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1467 13:19:08.773593 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1468 13:19:08.782814 [CA 0] Center 36 (6~67) winsize 62
1469 13:19:08.785965 [CA 1] Center 37 (7~67) winsize 61
1470 13:19:08.789055 [CA 2] Center 34 (4~65) winsize 62
1471 13:19:08.792302 [CA 3] Center 34 (3~65) winsize 63
1472 13:19:08.795570 [CA 4] Center 34 (4~65) winsize 62
1473 13:19:08.799234 [CA 5] Center 34 (3~65) winsize 63
1474 13:19:08.799310
1475 13:19:08.802430 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1476 13:19:08.802507
1477 13:19:08.805447 [CATrainingPosCal] consider 1 rank data
1478 13:19:08.809046 u2DelayCellTimex100 = 270/100 ps
1479 13:19:08.811930 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1480 13:19:08.818958 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1481 13:19:08.822068 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1482 13:19:08.825273 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1483 13:19:08.829079 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1484 13:19:08.832166 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1485 13:19:08.832242
1486 13:19:08.835249 CA PerBit enable=1, Macro0, CA PI delay=34
1487 13:19:08.835348
1488 13:19:08.839003 [CBTSetCACLKResult] CA Dly = 34
1489 13:19:08.839078 CS Dly: 5 (0~36)
1490 13:19:08.842100 ==
1491 13:19:08.845332 Dram Type= 6, Freq= 0, CH_1, rank 1
1492 13:19:08.848361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1493 13:19:08.848434 ==
1494 13:19:08.855367 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1495 13:19:08.858270 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1496 13:19:08.868644 [CA 0] Center 36 (6~67) winsize 62
1497 13:19:08.871975 [CA 1] Center 37 (6~68) winsize 63
1498 13:19:08.875239 [CA 2] Center 34 (4~65) winsize 62
1499 13:19:08.878932 [CA 3] Center 34 (3~65) winsize 63
1500 13:19:08.881813 [CA 4] Center 34 (4~65) winsize 62
1501 13:19:08.885382 [CA 5] Center 34 (3~65) winsize 63
1502 13:19:08.885458
1503 13:19:08.888525 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1504 13:19:08.888600
1505 13:19:08.892283 [CATrainingPosCal] consider 2 rank data
1506 13:19:08.895357 u2DelayCellTimex100 = 270/100 ps
1507 13:19:08.898551 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1508 13:19:08.901824 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1509 13:19:08.908705 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1510 13:19:08.911635 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1511 13:19:08.915243 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1512 13:19:08.918331 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1513 13:19:08.918406
1514 13:19:08.921549 CA PerBit enable=1, Macro0, CA PI delay=34
1515 13:19:08.921634
1516 13:19:08.925330 [CBTSetCACLKResult] CA Dly = 34
1517 13:19:08.925393 CS Dly: 6 (0~38)
1518 13:19:08.928493
1519 13:19:08.931772 ----->DramcWriteLeveling(PI) begin...
1520 13:19:08.931850 ==
1521 13:19:08.934862 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 13:19:08.938456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1523 13:19:08.938555 ==
1524 13:19:08.941584 Write leveling (Byte 0): 27 => 27
1525 13:19:08.944767 Write leveling (Byte 1): 27 => 27
1526 13:19:08.948524 DramcWriteLeveling(PI) end<-----
1527 13:19:08.948607
1528 13:19:08.948666 ==
1529 13:19:08.951663 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 13:19:08.954914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 13:19:08.955028 ==
1532 13:19:08.958608 [Gating] SW mode calibration
1533 13:19:08.964938 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1534 13:19:08.971411 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1535 13:19:08.974696 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1536 13:19:08.978490 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1537 13:19:08.984728 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1538 13:19:08.987995 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 13:19:08.991145 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 13:19:08.998174 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 13:19:09.001533 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 13:19:09.004753 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 13:19:09.007871 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 13:19:09.014711 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 13:19:09.018288 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 13:19:09.021280 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 13:19:09.028136 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 13:19:09.031241 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 13:19:09.035048 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 13:19:09.041239 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 13:19:09.044366 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1552 13:19:09.047593 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1553 13:19:09.054636 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1554 13:19:09.057807 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 13:19:09.060896 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 13:19:09.067673 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 13:19:09.070751 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 13:19:09.074315 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 13:19:09.080494 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 13:19:09.084016 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 13:19:09.087149 0 9 8 | B1->B0 | 2e2e 3434 | 0 0 | (0 0) (0 0)
1562 13:19:09.093746 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1563 13:19:09.097324 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1564 13:19:09.100749 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1565 13:19:09.107196 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1566 13:19:09.110716 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1567 13:19:09.114036 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1568 13:19:09.120659 0 10 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 0)
1569 13:19:09.123695 0 10 8 | B1->B0 | 2a2a 2727 | 0 0 | (0 0) (0 0)
1570 13:19:09.127409 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1571 13:19:09.133798 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1572 13:19:09.136927 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1573 13:19:09.140626 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1574 13:19:09.147016 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1575 13:19:09.150683 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1576 13:19:09.153840 0 11 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
1577 13:19:09.160620 0 11 8 | B1->B0 | 3e3e 3c3c | 0 0 | (0 0) (0 0)
1578 13:19:09.163932 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 13:19:09.167020 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1580 13:19:09.173372 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 13:19:09.176531 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1582 13:19:09.180378 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1583 13:19:09.186494 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 13:19:09.189998 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1585 13:19:09.193234 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1586 13:19:09.199901 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 13:19:09.203570 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 13:19:09.206500 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 13:19:09.213032 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 13:19:09.216693 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 13:19:09.219726 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 13:19:09.226463 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 13:19:09.229814 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1594 13:19:09.233129 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1595 13:19:09.239715 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1596 13:19:09.242857 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1597 13:19:09.246574 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1598 13:19:09.249740 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1599 13:19:09.256672 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1600 13:19:09.259774 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1601 13:19:09.262838 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1602 13:19:09.266696 Total UI for P1: 0, mck2ui 16
1603 13:19:09.269838 best dqsien dly found for B0: ( 0, 14, 4)
1604 13:19:09.276482 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1605 13:19:09.279768 Total UI for P1: 0, mck2ui 16
1606 13:19:09.282904 best dqsien dly found for B1: ( 0, 14, 6)
1607 13:19:09.286031 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1608 13:19:09.289787 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1609 13:19:09.289851
1610 13:19:09.292879 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1611 13:19:09.295966 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1612 13:19:09.299530 [Gating] SW calibration Done
1613 13:19:09.299597 ==
1614 13:19:09.302890 Dram Type= 6, Freq= 0, CH_1, rank 0
1615 13:19:09.306051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1616 13:19:09.306138 ==
1617 13:19:09.309321 RX Vref Scan: 0
1618 13:19:09.309431
1619 13:19:09.309547 RX Vref 0 -> 0, step: 1
1620 13:19:09.309621
1621 13:19:09.312609 RX Delay -130 -> 252, step: 16
1622 13:19:09.319264 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1623 13:19:09.322591 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1624 13:19:09.326420 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1625 13:19:09.329442 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1626 13:19:09.332551 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1627 13:19:09.339492 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1628 13:19:09.342290 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1629 13:19:09.345962 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1630 13:19:09.349160 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1631 13:19:09.352206 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1632 13:19:09.359056 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1633 13:19:09.362229 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1634 13:19:09.365992 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1635 13:19:09.369101 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1636 13:19:09.372218 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1637 13:19:09.379126 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1638 13:19:09.379228 ==
1639 13:19:09.382281 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 13:19:09.385988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 13:19:09.386081 ==
1642 13:19:09.386160 DQS Delay:
1643 13:19:09.389119 DQS0 = 0, DQS1 = 0
1644 13:19:09.389211 DQM Delay:
1645 13:19:09.392371 DQM0 = 89, DQM1 = 78
1646 13:19:09.392456 DQ Delay:
1647 13:19:09.395403 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1648 13:19:09.398560 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1649 13:19:09.402393 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1650 13:19:09.405497 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1651 13:19:09.405581
1652 13:19:09.405654
1653 13:19:09.405724 ==
1654 13:19:09.408561 Dram Type= 6, Freq= 0, CH_1, rank 0
1655 13:19:09.412295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1656 13:19:09.415275 ==
1657 13:19:09.415382
1658 13:19:09.415481
1659 13:19:09.415564 TX Vref Scan disable
1660 13:19:09.418883 == TX Byte 0 ==
1661 13:19:09.421918 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1662 13:19:09.425393 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1663 13:19:09.428691 == TX Byte 1 ==
1664 13:19:09.432054 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1665 13:19:09.435480 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1666 13:19:09.438669 ==
1667 13:19:09.441765 Dram Type= 6, Freq= 0, CH_1, rank 0
1668 13:19:09.445012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1669 13:19:09.445112 ==
1670 13:19:09.457755 TX Vref=22, minBit 8, minWin=27, winSum=447
1671 13:19:09.460864 TX Vref=24, minBit 9, minWin=27, winSum=447
1672 13:19:09.464248 TX Vref=26, minBit 9, minWin=27, winSum=449
1673 13:19:09.467371 TX Vref=28, minBit 8, minWin=27, winSum=451
1674 13:19:09.471131 TX Vref=30, minBit 10, minWin=27, winSum=449
1675 13:19:09.477472 TX Vref=32, minBit 8, minWin=27, winSum=447
1676 13:19:09.480644 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 28
1677 13:19:09.480720
1678 13:19:09.484346 Final TX Range 1 Vref 28
1679 13:19:09.484421
1680 13:19:09.484479 ==
1681 13:19:09.487473 Dram Type= 6, Freq= 0, CH_1, rank 0
1682 13:19:09.490683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1683 13:19:09.493777 ==
1684 13:19:09.493851
1685 13:19:09.493909
1686 13:19:09.493962 TX Vref Scan disable
1687 13:19:09.497496 == TX Byte 0 ==
1688 13:19:09.501323 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1689 13:19:09.507656 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1690 13:19:09.507730 == TX Byte 1 ==
1691 13:19:09.510747 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1692 13:19:09.517654 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1693 13:19:09.517722
1694 13:19:09.517784 [DATLAT]
1695 13:19:09.517848 Freq=800, CH1 RK0
1696 13:19:09.517904
1697 13:19:09.520679 DATLAT Default: 0xa
1698 13:19:09.520740 0, 0xFFFF, sum = 0
1699 13:19:09.524266 1, 0xFFFF, sum = 0
1700 13:19:09.524330 2, 0xFFFF, sum = 0
1701 13:19:09.527545 3, 0xFFFF, sum = 0
1702 13:19:09.530716 4, 0xFFFF, sum = 0
1703 13:19:09.530793 5, 0xFFFF, sum = 0
1704 13:19:09.534341 6, 0xFFFF, sum = 0
1705 13:19:09.534418 7, 0xFFFF, sum = 0
1706 13:19:09.537411 8, 0xFFFF, sum = 0
1707 13:19:09.537488 9, 0x0, sum = 1
1708 13:19:09.540930 10, 0x0, sum = 2
1709 13:19:09.541007 11, 0x0, sum = 3
1710 13:19:09.541067 12, 0x0, sum = 4
1711 13:19:09.543982 best_step = 10
1712 13:19:09.544057
1713 13:19:09.544115 ==
1714 13:19:09.547586 Dram Type= 6, Freq= 0, CH_1, rank 0
1715 13:19:09.550682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1716 13:19:09.550776 ==
1717 13:19:09.554002 RX Vref Scan: 1
1718 13:19:09.554071
1719 13:19:09.557183 Set Vref Range= 32 -> 127
1720 13:19:09.557246
1721 13:19:09.557302 RX Vref 32 -> 127, step: 1
1722 13:19:09.557352
1723 13:19:09.560292 RX Delay -95 -> 252, step: 8
1724 13:19:09.560354
1725 13:19:09.564003 Set Vref, RX VrefLevel [Byte0]: 32
1726 13:19:09.567027 [Byte1]: 32
1727 13:19:09.570382
1728 13:19:09.570450 Set Vref, RX VrefLevel [Byte0]: 33
1729 13:19:09.573531 [Byte1]: 33
1730 13:19:09.577824
1731 13:19:09.577938 Set Vref, RX VrefLevel [Byte0]: 34
1732 13:19:09.581335 [Byte1]: 34
1733 13:19:09.585719
1734 13:19:09.585788 Set Vref, RX VrefLevel [Byte0]: 35
1735 13:19:09.588879 [Byte1]: 35
1736 13:19:09.593214
1737 13:19:09.593301 Set Vref, RX VrefLevel [Byte0]: 36
1738 13:19:09.596342 [Byte1]: 36
1739 13:19:09.600794
1740 13:19:09.600860 Set Vref, RX VrefLevel [Byte0]: 37
1741 13:19:09.603992 [Byte1]: 37
1742 13:19:09.608409
1743 13:19:09.608478 Set Vref, RX VrefLevel [Byte0]: 38
1744 13:19:09.611444 [Byte1]: 38
1745 13:19:09.615830
1746 13:19:09.615909 Set Vref, RX VrefLevel [Byte0]: 39
1747 13:19:09.618988 [Byte1]: 39
1748 13:19:09.623292
1749 13:19:09.623360 Set Vref, RX VrefLevel [Byte0]: 40
1750 13:19:09.626898 [Byte1]: 40
1751 13:19:09.631023
1752 13:19:09.631101 Set Vref, RX VrefLevel [Byte0]: 41
1753 13:19:09.634706 [Byte1]: 41
1754 13:19:09.638993
1755 13:19:09.639069 Set Vref, RX VrefLevel [Byte0]: 42
1756 13:19:09.642045 [Byte1]: 42
1757 13:19:09.646345
1758 13:19:09.646412 Set Vref, RX VrefLevel [Byte0]: 43
1759 13:19:09.649490 [Byte1]: 43
1760 13:19:09.653959
1761 13:19:09.657010 Set Vref, RX VrefLevel [Byte0]: 44
1762 13:19:09.660551 [Byte1]: 44
1763 13:19:09.660616
1764 13:19:09.663372 Set Vref, RX VrefLevel [Byte0]: 45
1765 13:19:09.666718 [Byte1]: 45
1766 13:19:09.666789
1767 13:19:09.670443 Set Vref, RX VrefLevel [Byte0]: 46
1768 13:19:09.673568 [Byte1]: 46
1769 13:19:09.676780
1770 13:19:09.676848 Set Vref, RX VrefLevel [Byte0]: 47
1771 13:19:09.679869 [Byte1]: 47
1772 13:19:09.684622
1773 13:19:09.684695 Set Vref, RX VrefLevel [Byte0]: 48
1774 13:19:09.687421 [Byte1]: 48
1775 13:19:09.691773
1776 13:19:09.691836 Set Vref, RX VrefLevel [Byte0]: 49
1777 13:19:09.695015 [Byte1]: 49
1778 13:19:09.699289
1779 13:19:09.699392 Set Vref, RX VrefLevel [Byte0]: 50
1780 13:19:09.703122 [Byte1]: 50
1781 13:19:09.706925
1782 13:19:09.707001 Set Vref, RX VrefLevel [Byte0]: 51
1783 13:19:09.710620 [Byte1]: 51
1784 13:19:09.714956
1785 13:19:09.715030 Set Vref, RX VrefLevel [Byte0]: 52
1786 13:19:09.718147 [Byte1]: 52
1787 13:19:09.722506
1788 13:19:09.722578 Set Vref, RX VrefLevel [Byte0]: 53
1789 13:19:09.725722 [Byte1]: 53
1790 13:19:09.729598
1791 13:19:09.729687 Set Vref, RX VrefLevel [Byte0]: 54
1792 13:19:09.733225 [Byte1]: 54
1793 13:19:09.737423
1794 13:19:09.737498 Set Vref, RX VrefLevel [Byte0]: 55
1795 13:19:09.740545 [Byte1]: 55
1796 13:19:09.744807
1797 13:19:09.744878 Set Vref, RX VrefLevel [Byte0]: 56
1798 13:19:09.748431 [Byte1]: 56
1799 13:19:09.752663
1800 13:19:09.755670 Set Vref, RX VrefLevel [Byte0]: 57
1801 13:19:09.759472 [Byte1]: 57
1802 13:19:09.759537
1803 13:19:09.762630 Set Vref, RX VrefLevel [Byte0]: 58
1804 13:19:09.765819 [Byte1]: 58
1805 13:19:09.765888
1806 13:19:09.768870 Set Vref, RX VrefLevel [Byte0]: 59
1807 13:19:09.772413 [Byte1]: 59
1808 13:19:09.775258
1809 13:19:09.775347 Set Vref, RX VrefLevel [Byte0]: 60
1810 13:19:09.778583 [Byte1]: 60
1811 13:19:09.783121
1812 13:19:09.783197 Set Vref, RX VrefLevel [Byte0]: 61
1813 13:19:09.786127 [Byte1]: 61
1814 13:19:09.790737
1815 13:19:09.790812 Set Vref, RX VrefLevel [Byte0]: 62
1816 13:19:09.793817 [Byte1]: 62
1817 13:19:09.798521
1818 13:19:09.798595 Set Vref, RX VrefLevel [Byte0]: 63
1819 13:19:09.801513 [Byte1]: 63
1820 13:19:09.805747
1821 13:19:09.805928 Set Vref, RX VrefLevel [Byte0]: 64
1822 13:19:09.809039 [Byte1]: 64
1823 13:19:09.813436
1824 13:19:09.813526 Set Vref, RX VrefLevel [Byte0]: 65
1825 13:19:09.816636 [Byte1]: 65
1826 13:19:09.820978
1827 13:19:09.821044 Set Vref, RX VrefLevel [Byte0]: 66
1828 13:19:09.824117 [Byte1]: 66
1829 13:19:09.828409
1830 13:19:09.828488 Set Vref, RX VrefLevel [Byte0]: 67
1831 13:19:09.832184 [Byte1]: 67
1832 13:19:09.836083
1833 13:19:09.836152 Set Vref, RX VrefLevel [Byte0]: 68
1834 13:19:09.839557 [Byte1]: 68
1835 13:19:09.843673
1836 13:19:09.843742 Set Vref, RX VrefLevel [Byte0]: 69
1837 13:19:09.847408 [Byte1]: 69
1838 13:19:09.851571
1839 13:19:09.851661 Set Vref, RX VrefLevel [Byte0]: 70
1840 13:19:09.854597 [Byte1]: 70
1841 13:19:09.858712
1842 13:19:09.858794 Set Vref, RX VrefLevel [Byte0]: 71
1843 13:19:09.862622 [Byte1]: 71
1844 13:19:09.866478
1845 13:19:09.866572 Set Vref, RX VrefLevel [Byte0]: 72
1846 13:19:09.870319 [Byte1]: 72
1847 13:19:09.873994
1848 13:19:09.874087 Set Vref, RX VrefLevel [Byte0]: 73
1849 13:19:09.877813 [Byte1]: 73
1850 13:19:09.881494
1851 13:19:09.881563 Set Vref, RX VrefLevel [Byte0]: 74
1852 13:19:09.888381 [Byte1]: 74
1853 13:19:09.888454
1854 13:19:09.891738 Set Vref, RX VrefLevel [Byte0]: 75
1855 13:19:09.894534 [Byte1]: 75
1856 13:19:09.894602
1857 13:19:09.898249 Set Vref, RX VrefLevel [Byte0]: 76
1858 13:19:09.901404 [Byte1]: 76
1859 13:19:09.901475
1860 13:19:09.905041 Set Vref, RX VrefLevel [Byte0]: 77
1861 13:19:09.908186 [Byte1]: 77
1862 13:19:09.912133
1863 13:19:09.912224 Final RX Vref Byte 0 = 53 to rank0
1864 13:19:09.915825 Final RX Vref Byte 1 = 66 to rank0
1865 13:19:09.919116 Final RX Vref Byte 0 = 53 to rank1
1866 13:19:09.922034 Final RX Vref Byte 1 = 66 to rank1==
1867 13:19:09.925711 Dram Type= 6, Freq= 0, CH_1, rank 0
1868 13:19:09.931963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1869 13:19:09.932072 ==
1870 13:19:09.932132 DQS Delay:
1871 13:19:09.932185 DQS0 = 0, DQS1 = 0
1872 13:19:09.935578 DQM Delay:
1873 13:19:09.935648 DQM0 = 86, DQM1 = 78
1874 13:19:09.938783 DQ Delay:
1875 13:19:09.941942 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
1876 13:19:09.945472 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1877 13:19:09.948423 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1878 13:19:09.951893 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1879 13:19:09.951995
1880 13:19:09.952069
1881 13:19:09.958564 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f1b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1882 13:19:09.962021 CH1 RK0: MR19=606, MR18=2F1B
1883 13:19:09.968901 CH1_RK0: MR19=0x606, MR18=0x2F1B, DQSOSC=397, MR23=63, INC=93, DEC=62
1884 13:19:09.968993
1885 13:19:09.972008 ----->DramcWriteLeveling(PI) begin...
1886 13:19:09.972077 ==
1887 13:19:09.975155 Dram Type= 6, Freq= 0, CH_1, rank 1
1888 13:19:09.978349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1889 13:19:09.978415 ==
1890 13:19:09.981593 Write leveling (Byte 0): 27 => 27
1891 13:19:09.984840 Write leveling (Byte 1): 28 => 28
1892 13:19:09.988685 DramcWriteLeveling(PI) end<-----
1893 13:19:09.988750
1894 13:19:09.988813 ==
1895 13:19:09.991672 Dram Type= 6, Freq= 0, CH_1, rank 1
1896 13:19:09.995193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1897 13:19:09.995258 ==
1898 13:19:09.998138 [Gating] SW mode calibration
1899 13:19:10.004974 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1900 13:19:10.011465 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1901 13:19:10.014674 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1902 13:19:10.021475 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1903 13:19:10.024960 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1904 13:19:10.027735 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 13:19:10.034696 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 13:19:10.037761 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 13:19:10.041505 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 13:19:10.044720 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 13:19:10.050976 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 13:19:10.054717 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 13:19:10.057638 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 13:19:10.064866 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 13:19:10.067881 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 13:19:10.071367 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 13:19:10.077590 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 13:19:10.081436 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 13:19:10.084593 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1918 13:19:10.090916 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1919 13:19:10.094720 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 13:19:10.097811 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 13:19:10.104262 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 13:19:10.107376 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 13:19:10.111355 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 13:19:10.117604 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 13:19:10.120809 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 13:19:10.123929 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 13:19:10.130740 0 9 8 | B1->B0 | 3131 2828 | 0 1 | (0 0) (1 1)
1928 13:19:10.134341 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1929 13:19:10.137493 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1930 13:19:10.144432 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1931 13:19:10.147474 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1932 13:19:10.150578 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1933 13:19:10.157526 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1934 13:19:10.160678 0 10 4 | B1->B0 | 3030 3434 | 1 0 | (1 0) (0 1)
1935 13:19:10.163720 0 10 8 | B1->B0 | 2828 2b2b | 0 0 | (0 0) (1 0)
1936 13:19:10.170075 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1937 13:19:10.173694 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1938 13:19:10.177398 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1939 13:19:10.183610 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1940 13:19:10.186656 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1941 13:19:10.190496 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1942 13:19:10.196770 0 11 4 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1943 13:19:10.199992 0 11 8 | B1->B0 | 3e3e 3939 | 1 0 | (0 0) (0 0)
1944 13:19:10.203811 0 11 12 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)
1945 13:19:10.210105 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1946 13:19:10.213297 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1947 13:19:10.217017 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1948 13:19:10.223715 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1949 13:19:10.226838 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1950 13:19:10.230540 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1951 13:19:10.236637 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 13:19:10.240172 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 13:19:10.243345 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 13:19:10.250209 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 13:19:10.253104 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1956 13:19:10.256530 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1957 13:19:10.263552 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1958 13:19:10.266718 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1959 13:19:10.269781 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1960 13:19:10.276455 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1961 13:19:10.279830 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1962 13:19:10.282864 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1963 13:19:10.286420 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1964 13:19:10.293284 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1965 13:19:10.296395 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1966 13:19:10.299498 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1967 13:19:10.306313 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1968 13:19:10.309453 Total UI for P1: 0, mck2ui 16
1969 13:19:10.312735 best dqsien dly found for B0: ( 0, 14, 6)
1970 13:19:10.312817 Total UI for P1: 0, mck2ui 16
1971 13:19:10.319543 best dqsien dly found for B1: ( 0, 14, 4)
1972 13:19:10.323222 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1973 13:19:10.326208 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1974 13:19:10.326318
1975 13:19:10.329461 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1976 13:19:10.333052 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1977 13:19:10.336261 [Gating] SW calibration Done
1978 13:19:10.336331 ==
1979 13:19:10.339444 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 13:19:10.343146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 13:19:10.343221 ==
1982 13:19:10.346131 RX Vref Scan: 0
1983 13:19:10.346195
1984 13:19:10.346260 RX Vref 0 -> 0, step: 1
1985 13:19:10.346334
1986 13:19:10.349529 RX Delay -130 -> 252, step: 16
1987 13:19:10.352826 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1988 13:19:10.359773 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1989 13:19:10.363026 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1990 13:19:10.366242 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1991 13:19:10.369644 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1992 13:19:10.373213 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1993 13:19:10.379793 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1994 13:19:10.382570 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1995 13:19:10.386029 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1996 13:19:10.389570 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1997 13:19:10.392538 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1998 13:19:10.399256 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1999 13:19:10.402422 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
2000 13:19:10.406157 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
2001 13:19:10.409220 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
2002 13:19:10.416207 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
2003 13:19:10.416279 ==
2004 13:19:10.419420 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 13:19:10.422389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 13:19:10.422460 ==
2007 13:19:10.422517 DQS Delay:
2008 13:19:10.425862 DQS0 = 0, DQS1 = 0
2009 13:19:10.425937 DQM Delay:
2010 13:19:10.428794 DQM0 = 87, DQM1 = 78
2011 13:19:10.428862 DQ Delay:
2012 13:19:10.432478 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
2013 13:19:10.435589 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2014 13:19:10.438843 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
2015 13:19:10.442486 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2016 13:19:10.442608
2017 13:19:10.442706
2018 13:19:10.442817 ==
2019 13:19:10.445735 Dram Type= 6, Freq= 0, CH_1, rank 1
2020 13:19:10.448897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2021 13:19:10.452146 ==
2022 13:19:10.452214
2023 13:19:10.452269
2024 13:19:10.452321 TX Vref Scan disable
2025 13:19:10.455746 == TX Byte 0 ==
2026 13:19:10.458738 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2027 13:19:10.462189 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2028 13:19:10.465624 == TX Byte 1 ==
2029 13:19:10.468754 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2030 13:19:10.472337 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2031 13:19:10.475348 ==
2032 13:19:10.475419 Dram Type= 6, Freq= 0, CH_1, rank 1
2033 13:19:10.482247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2034 13:19:10.482320 ==
2035 13:19:10.494319 TX Vref=22, minBit 8, minWin=27, winSum=445
2036 13:19:10.497771 TX Vref=24, minBit 1, minWin=27, winSum=445
2037 13:19:10.501276 TX Vref=26, minBit 13, minWin=27, winSum=450
2038 13:19:10.504293 TX Vref=28, minBit 13, minWin=27, winSum=450
2039 13:19:10.507484 TX Vref=30, minBit 13, minWin=27, winSum=449
2040 13:19:10.514418 TX Vref=32, minBit 8, minWin=27, winSum=449
2041 13:19:10.517553 [TxChooseVref] Worse bit 13, Min win 27, Win sum 450, Final Vref 26
2042 13:19:10.517619
2043 13:19:10.520604 Final TX Range 1 Vref 26
2044 13:19:10.520669
2045 13:19:10.520727 ==
2046 13:19:10.524292 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 13:19:10.530793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 13:19:10.530863 ==
2049 13:19:10.530919
2050 13:19:10.530970
2051 13:19:10.531020 TX Vref Scan disable
2052 13:19:10.534453 == TX Byte 0 ==
2053 13:19:10.538122 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2054 13:19:10.544869 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2055 13:19:10.544942 == TX Byte 1 ==
2056 13:19:10.548063 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2057 13:19:10.554862 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2058 13:19:10.554935
2059 13:19:10.554995 [DATLAT]
2060 13:19:10.555051 Freq=800, CH1 RK1
2061 13:19:10.555105
2062 13:19:10.557975 DATLAT Default: 0xa
2063 13:19:10.558035 0, 0xFFFF, sum = 0
2064 13:19:10.561038 1, 0xFFFF, sum = 0
2065 13:19:10.561099 2, 0xFFFF, sum = 0
2066 13:19:10.564698 3, 0xFFFF, sum = 0
2067 13:19:10.567642 4, 0xFFFF, sum = 0
2068 13:19:10.567719 5, 0xFFFF, sum = 0
2069 13:19:10.571216 6, 0xFFFF, sum = 0
2070 13:19:10.571287 7, 0xFFFF, sum = 0
2071 13:19:10.574822 8, 0xFFFF, sum = 0
2072 13:19:10.574943 9, 0x0, sum = 1
2073 13:19:10.577552 10, 0x0, sum = 2
2074 13:19:10.577652 11, 0x0, sum = 3
2075 13:19:10.577738 12, 0x0, sum = 4
2076 13:19:10.581351 best_step = 10
2077 13:19:10.581443
2078 13:19:10.581533 ==
2079 13:19:10.584373 Dram Type= 6, Freq= 0, CH_1, rank 1
2080 13:19:10.587409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2081 13:19:10.587532 ==
2082 13:19:10.591129 RX Vref Scan: 0
2083 13:19:10.591220
2084 13:19:10.594592 RX Vref 0 -> 0, step: 1
2085 13:19:10.594673
2086 13:19:10.594730 RX Delay -95 -> 252, step: 8
2087 13:19:10.601561 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2088 13:19:10.604467 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2089 13:19:10.607882 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2090 13:19:10.611360 iDelay=217, Bit 3, Center 88 (-23 ~ 200) 224
2091 13:19:10.617792 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2092 13:19:10.620975 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2093 13:19:10.624680 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2094 13:19:10.627760 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2095 13:19:10.631583 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2096 13:19:10.634784 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2097 13:19:10.641534 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
2098 13:19:10.644055 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2099 13:19:10.647769 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2100 13:19:10.650953 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2101 13:19:10.657317 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2102 13:19:10.661126 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2103 13:19:10.661196 ==
2104 13:19:10.664185 Dram Type= 6, Freq= 0, CH_1, rank 1
2105 13:19:10.667286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2106 13:19:10.667350 ==
2107 13:19:10.670988 DQS Delay:
2108 13:19:10.671051 DQS0 = 0, DQS1 = 0
2109 13:19:10.671107 DQM Delay:
2110 13:19:10.674143 DQM0 = 87, DQM1 = 77
2111 13:19:10.674208 DQ Delay:
2112 13:19:10.677328 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =88
2113 13:19:10.680437 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2114 13:19:10.683849 DQ8 =68, DQ9 =68, DQ10 =76, DQ11 =68
2115 13:19:10.687077 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2116 13:19:10.687180
2117 13:19:10.687263
2118 13:19:10.697005 [DQSOSCAuto] RK1, (LSB)MR18= 0x160e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
2119 13:19:10.700692 CH1 RK1: MR19=606, MR18=160E
2120 13:19:10.703686 CH1_RK1: MR19=0x606, MR18=0x160E, DQSOSC=404, MR23=63, INC=90, DEC=60
2121 13:19:10.707010 [RxdqsGatingPostProcess] freq 800
2122 13:19:10.713613 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2123 13:19:10.717083 Pre-setting of DQS Precalculation
2124 13:19:10.720534 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2125 13:19:10.730516 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2126 13:19:10.736768 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2127 13:19:10.736848
2128 13:19:10.736906
2129 13:19:10.740443 [Calibration Summary] 1600 Mbps
2130 13:19:10.740506 CH 0, Rank 0
2131 13:19:10.743281 SW Impedance : PASS
2132 13:19:10.743346 DUTY Scan : NO K
2133 13:19:10.747071 ZQ Calibration : PASS
2134 13:19:10.750193 Jitter Meter : NO K
2135 13:19:10.750263 CBT Training : PASS
2136 13:19:10.753332 Write leveling : PASS
2137 13:19:10.756486 RX DQS gating : PASS
2138 13:19:10.756549 RX DQ/DQS(RDDQC) : PASS
2139 13:19:10.760334 TX DQ/DQS : PASS
2140 13:19:10.763403 RX DATLAT : PASS
2141 13:19:10.763507 RX DQ/DQS(Engine): PASS
2142 13:19:10.766574 TX OE : NO K
2143 13:19:10.766639 All Pass.
2144 13:19:10.766695
2145 13:19:10.769725 CH 0, Rank 1
2146 13:19:10.769788 SW Impedance : PASS
2147 13:19:10.773503 DUTY Scan : NO K
2148 13:19:10.776528 ZQ Calibration : PASS
2149 13:19:10.776595 Jitter Meter : NO K
2150 13:19:10.779730 CBT Training : PASS
2151 13:19:10.782896 Write leveling : PASS
2152 13:19:10.782983 RX DQS gating : PASS
2153 13:19:10.786701 RX DQ/DQS(RDDQC) : PASS
2154 13:19:10.786767 TX DQ/DQS : PASS
2155 13:19:10.789905 RX DATLAT : PASS
2156 13:19:10.793060 RX DQ/DQS(Engine): PASS
2157 13:19:10.793131 TX OE : NO K
2158 13:19:10.796602 All Pass.
2159 13:19:10.796669
2160 13:19:10.796738 CH 1, Rank 0
2161 13:19:10.799530 SW Impedance : PASS
2162 13:19:10.799619 DUTY Scan : NO K
2163 13:19:10.802820 ZQ Calibration : PASS
2164 13:19:10.806297 Jitter Meter : NO K
2165 13:19:10.806375 CBT Training : PASS
2166 13:19:10.809738 Write leveling : PASS
2167 13:19:10.812820 RX DQS gating : PASS
2168 13:19:10.812890 RX DQ/DQS(RDDQC) : PASS
2169 13:19:10.816140 TX DQ/DQS : PASS
2170 13:19:10.819657 RX DATLAT : PASS
2171 13:19:10.819727 RX DQ/DQS(Engine): PASS
2172 13:19:10.822469 TX OE : NO K
2173 13:19:10.822540 All Pass.
2174 13:19:10.822612
2175 13:19:10.826041 CH 1, Rank 1
2176 13:19:10.826135 SW Impedance : PASS
2177 13:19:10.829411 DUTY Scan : NO K
2178 13:19:10.832764 ZQ Calibration : PASS
2179 13:19:10.832831 Jitter Meter : NO K
2180 13:19:10.835842 CBT Training : PASS
2181 13:19:10.839056 Write leveling : PASS
2182 13:19:10.839132 RX DQS gating : PASS
2183 13:19:10.842841 RX DQ/DQS(RDDQC) : PASS
2184 13:19:10.845861 TX DQ/DQS : PASS
2185 13:19:10.845961 RX DATLAT : PASS
2186 13:19:10.848728 RX DQ/DQS(Engine): PASS
2187 13:19:10.852371 TX OE : NO K
2188 13:19:10.852468 All Pass.
2189 13:19:10.852552
2190 13:19:10.852633 DramC Write-DBI off
2191 13:19:10.855411 PER_BANK_REFRESH: Hybrid Mode
2192 13:19:10.859218 TX_TRACKING: ON
2193 13:19:10.862430 [GetDramInforAfterCalByMRR] Vendor 6.
2194 13:19:10.865563 [GetDramInforAfterCalByMRR] Revision 606.
2195 13:19:10.869261 [GetDramInforAfterCalByMRR] Revision 2 0.
2196 13:19:10.869332 MR0 0x3b3b
2197 13:19:10.872409 MR8 0x5151
2198 13:19:10.875546 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2199 13:19:10.875607
2200 13:19:10.875660 MR0 0x3b3b
2201 13:19:10.875711 MR8 0x5151
2202 13:19:10.878589 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2203 13:19:10.882357
2204 13:19:10.888783 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2205 13:19:10.892003 [FAST_K] Save calibration result to emmc
2206 13:19:10.895673 [FAST_K] Save calibration result to emmc
2207 13:19:10.898990 dram_init: config_dvfs: 1
2208 13:19:10.902004 dramc_set_vcore_voltage set vcore to 662500
2209 13:19:10.905173 Read voltage for 1200, 2
2210 13:19:10.905238 Vio18 = 0
2211 13:19:10.909016 Vcore = 662500
2212 13:19:10.909111 Vdram = 0
2213 13:19:10.909186 Vddq = 0
2214 13:19:10.909269 Vmddr = 0
2215 13:19:10.915168 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2216 13:19:10.922012 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2217 13:19:10.922091 MEM_TYPE=3, freq_sel=15
2218 13:19:10.924989 sv_algorithm_assistance_LP4_1600
2219 13:19:10.928510 ============ PULL DRAM RESETB DOWN ============
2220 13:19:10.934985 ========== PULL DRAM RESETB DOWN end =========
2221 13:19:10.938544 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2222 13:19:10.941495 ===================================
2223 13:19:10.944777 LPDDR4 DRAM CONFIGURATION
2224 13:19:10.948412 ===================================
2225 13:19:10.948493 EX_ROW_EN[0] = 0x0
2226 13:19:10.951348 EX_ROW_EN[1] = 0x0
2227 13:19:10.955178 LP4Y_EN = 0x0
2228 13:19:10.955253 WORK_FSP = 0x0
2229 13:19:10.958130 WL = 0x4
2230 13:19:10.958199 RL = 0x4
2231 13:19:10.961396 BL = 0x2
2232 13:19:10.961464 RPST = 0x0
2233 13:19:10.965146 RD_PRE = 0x0
2234 13:19:10.965215 WR_PRE = 0x1
2235 13:19:10.968303 WR_PST = 0x0
2236 13:19:10.968371 DBI_WR = 0x0
2237 13:19:10.971513 DBI_RD = 0x0
2238 13:19:10.971585 OTF = 0x1
2239 13:19:10.974706 ===================================
2240 13:19:10.977800 ===================================
2241 13:19:10.981482 ANA top config
2242 13:19:10.984449 ===================================
2243 13:19:10.984519 DLL_ASYNC_EN = 0
2244 13:19:10.987629 ALL_SLAVE_EN = 0
2245 13:19:10.991372 NEW_RANK_MODE = 1
2246 13:19:10.994533 DLL_IDLE_MODE = 1
2247 13:19:10.997701 LP45_APHY_COMB_EN = 1
2248 13:19:10.997776 TX_ODT_DIS = 1
2249 13:19:11.001016 NEW_8X_MODE = 1
2250 13:19:11.004652 ===================================
2251 13:19:11.007667 ===================================
2252 13:19:11.010773 data_rate = 2400
2253 13:19:11.014583 CKR = 1
2254 13:19:11.017665 DQ_P2S_RATIO = 8
2255 13:19:11.021302 ===================================
2256 13:19:11.024170 CA_P2S_RATIO = 8
2257 13:19:11.024245 DQ_CA_OPEN = 0
2258 13:19:11.027548 DQ_SEMI_OPEN = 0
2259 13:19:11.031017 CA_SEMI_OPEN = 0
2260 13:19:11.034175 CA_FULL_RATE = 0
2261 13:19:11.037652 DQ_CKDIV4_EN = 0
2262 13:19:11.040503 CA_CKDIV4_EN = 0
2263 13:19:11.040580 CA_PREDIV_EN = 0
2264 13:19:11.044120 PH8_DLY = 17
2265 13:19:11.047230 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2266 13:19:11.050679 DQ_AAMCK_DIV = 4
2267 13:19:11.054074 CA_AAMCK_DIV = 4
2268 13:19:11.057430 CA_ADMCK_DIV = 4
2269 13:19:11.057506 DQ_TRACK_CA_EN = 0
2270 13:19:11.061109 CA_PICK = 1200
2271 13:19:11.064456 CA_MCKIO = 1200
2272 13:19:11.067594 MCKIO_SEMI = 0
2273 13:19:11.070670 PLL_FREQ = 2366
2274 13:19:11.073879 DQ_UI_PI_RATIO = 32
2275 13:19:11.077049 CA_UI_PI_RATIO = 0
2276 13:19:11.080776 ===================================
2277 13:19:11.083890 ===================================
2278 13:19:11.083966 memory_type:LPDDR4
2279 13:19:11.086917 GP_NUM : 10
2280 13:19:11.090685 SRAM_EN : 1
2281 13:19:11.090759 MD32_EN : 0
2282 13:19:11.093809 ===================================
2283 13:19:11.096903 [ANA_INIT] >>>>>>>>>>>>>>
2284 13:19:11.100714 <<<<<< [CONFIGURE PHASE]: ANA_TX
2285 13:19:11.103868 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2286 13:19:11.106945 ===================================
2287 13:19:11.110627 data_rate = 2400,PCW = 0X5b00
2288 13:19:11.113759 ===================================
2289 13:19:11.116887 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2290 13:19:11.120046 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2291 13:19:11.126927 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2292 13:19:11.130095 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2293 13:19:11.133616 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2294 13:19:11.136586 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2295 13:19:11.140252 [ANA_INIT] flow start
2296 13:19:11.143062 [ANA_INIT] PLL >>>>>>>>
2297 13:19:11.143133 [ANA_INIT] PLL <<<<<<<<
2298 13:19:11.146549 [ANA_INIT] MIDPI >>>>>>>>
2299 13:19:11.150117 [ANA_INIT] MIDPI <<<<<<<<
2300 13:19:11.153125 [ANA_INIT] DLL >>>>>>>>
2301 13:19:11.153193 [ANA_INIT] DLL <<<<<<<<
2302 13:19:11.156572 [ANA_INIT] flow end
2303 13:19:11.159697 ============ LP4 DIFF to SE enter ============
2304 13:19:11.163288 ============ LP4 DIFF to SE exit ============
2305 13:19:11.166296 [ANA_INIT] <<<<<<<<<<<<<
2306 13:19:11.169626 [Flow] Enable top DCM control >>>>>
2307 13:19:11.172857 [Flow] Enable top DCM control <<<<<
2308 13:19:11.176103 Enable DLL master slave shuffle
2309 13:19:11.182794 ==============================================================
2310 13:19:11.182875 Gating Mode config
2311 13:19:11.189692 ==============================================================
2312 13:19:11.189764 Config description:
2313 13:19:11.199573 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2314 13:19:11.206595 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2315 13:19:11.212834 SELPH_MODE 0: By rank 1: By Phase
2316 13:19:11.216463 ==============================================================
2317 13:19:11.219661 GAT_TRACK_EN = 1
2318 13:19:11.222733 RX_GATING_MODE = 2
2319 13:19:11.225886 RX_GATING_TRACK_MODE = 2
2320 13:19:11.229653 SELPH_MODE = 1
2321 13:19:11.232776 PICG_EARLY_EN = 1
2322 13:19:11.235930 VALID_LAT_VALUE = 1
2323 13:19:11.242568 ==============================================================
2324 13:19:11.246157 Enter into Gating configuration >>>>
2325 13:19:11.249132 Exit from Gating configuration <<<<
2326 13:19:11.249225 Enter into DVFS_PRE_config >>>>>
2327 13:19:11.262437 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2328 13:19:11.265815 Exit from DVFS_PRE_config <<<<<
2329 13:19:11.269130 Enter into PICG configuration >>>>
2330 13:19:11.272750 Exit from PICG configuration <<<<
2331 13:19:11.272822 [RX_INPUT] configuration >>>>>
2332 13:19:11.275852 [RX_INPUT] configuration <<<<<
2333 13:19:11.282444 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2334 13:19:11.288916 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2335 13:19:11.292438 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2336 13:19:11.299104 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2337 13:19:11.305489 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2338 13:19:11.312463 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2339 13:19:11.315610 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2340 13:19:11.318726 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2341 13:19:11.325670 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2342 13:19:11.328258 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2343 13:19:11.332061 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2344 13:19:11.338423 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2345 13:19:11.341459 ===================================
2346 13:19:11.341535 LPDDR4 DRAM CONFIGURATION
2347 13:19:11.345011 ===================================
2348 13:19:11.348031 EX_ROW_EN[0] = 0x0
2349 13:19:11.351471 EX_ROW_EN[1] = 0x0
2350 13:19:11.351618 LP4Y_EN = 0x0
2351 13:19:11.354447 WORK_FSP = 0x0
2352 13:19:11.354523 WL = 0x4
2353 13:19:11.357875 RL = 0x4
2354 13:19:11.358030 BL = 0x2
2355 13:19:11.361626 RPST = 0x0
2356 13:19:11.361701 RD_PRE = 0x0
2357 13:19:11.364658 WR_PRE = 0x1
2358 13:19:11.364732 WR_PST = 0x0
2359 13:19:11.367812 DBI_WR = 0x0
2360 13:19:11.367887 DBI_RD = 0x0
2361 13:19:11.371230 OTF = 0x1
2362 13:19:11.374169 ===================================
2363 13:19:11.377590 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2364 13:19:11.381132 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2365 13:19:11.387963 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2366 13:19:11.390991 ===================================
2367 13:19:11.391064 LPDDR4 DRAM CONFIGURATION
2368 13:19:11.394572 ===================================
2369 13:19:11.397597 EX_ROW_EN[0] = 0x10
2370 13:19:11.400845 EX_ROW_EN[1] = 0x0
2371 13:19:11.400920 LP4Y_EN = 0x0
2372 13:19:11.404126 WORK_FSP = 0x0
2373 13:19:11.404200 WL = 0x4
2374 13:19:11.407547 RL = 0x4
2375 13:19:11.407623 BL = 0x2
2376 13:19:11.410663 RPST = 0x0
2377 13:19:11.410739 RD_PRE = 0x0
2378 13:19:11.413960 WR_PRE = 0x1
2379 13:19:11.414035 WR_PST = 0x0
2380 13:19:11.417715 DBI_WR = 0x0
2381 13:19:11.417789 DBI_RD = 0x0
2382 13:19:11.420841 OTF = 0x1
2383 13:19:11.423969 ===================================
2384 13:19:11.430929 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2385 13:19:11.431007 ==
2386 13:19:11.434083 Dram Type= 6, Freq= 0, CH_0, rank 0
2387 13:19:11.437432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2388 13:19:11.437533 ==
2389 13:19:11.440571 [Duty_Offset_Calibration]
2390 13:19:11.440670 B0:1 B1:-1 CA:0
2391 13:19:11.440752
2392 13:19:11.443743 [DutyScan_Calibration_Flow] k_type=0
2393 13:19:11.454219
2394 13:19:11.454320 ==CLK 0==
2395 13:19:11.457921 Final CLK duty delay cell = 0
2396 13:19:11.460936 [0] MAX Duty = 5094%(X100), DQS PI = 16
2397 13:19:11.464476 [0] MIN Duty = 4875%(X100), DQS PI = 8
2398 13:19:11.464572 [0] AVG Duty = 4984%(X100)
2399 13:19:11.464654
2400 13:19:11.467912 CH0 CLK Duty spec in!! Max-Min= 219%
2401 13:19:11.474468 [DutyScan_Calibration_Flow] ====Done====
2402 13:19:11.474567
2403 13:19:11.477661 [DutyScan_Calibration_Flow] k_type=1
2404 13:19:11.492731
2405 13:19:11.492813 ==DQS 0 ==
2406 13:19:11.496255 Final DQS duty delay cell = -4
2407 13:19:11.499451 [-4] MAX Duty = 5062%(X100), DQS PI = 18
2408 13:19:11.502491 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2409 13:19:11.506394 [-4] AVG Duty = 4968%(X100)
2410 13:19:11.506468
2411 13:19:11.506526 ==DQS 1 ==
2412 13:19:11.509351 Final DQS duty delay cell = 0
2413 13:19:11.512676 [0] MAX Duty = 5124%(X100), DQS PI = 6
2414 13:19:11.515980 [0] MIN Duty = 5000%(X100), DQS PI = 20
2415 13:19:11.518936 [0] AVG Duty = 5062%(X100)
2416 13:19:11.519010
2417 13:19:11.522497 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2418 13:19:11.522572
2419 13:19:11.526082 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2420 13:19:11.529223 [DutyScan_Calibration_Flow] ====Done====
2421 13:19:11.529298
2422 13:19:11.532284 [DutyScan_Calibration_Flow] k_type=3
2423 13:19:11.550647
2424 13:19:11.550724 ==DQM 0 ==
2425 13:19:11.553736 Final DQM duty delay cell = 0
2426 13:19:11.557367 [0] MAX Duty = 5031%(X100), DQS PI = 16
2427 13:19:11.560360 [0] MIN Duty = 4875%(X100), DQS PI = 6
2428 13:19:11.560431 [0] AVG Duty = 4953%(X100)
2429 13:19:11.563508
2430 13:19:11.563570 ==DQM 1 ==
2431 13:19:11.567315 Final DQM duty delay cell = 4
2432 13:19:11.570374 [4] MAX Duty = 5187%(X100), DQS PI = 56
2433 13:19:11.573708 [4] MIN Duty = 4969%(X100), DQS PI = 24
2434 13:19:11.576734 [4] AVG Duty = 5078%(X100)
2435 13:19:11.576808
2436 13:19:11.580275 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2437 13:19:11.580350
2438 13:19:11.583360 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2439 13:19:11.587137 [DutyScan_Calibration_Flow] ====Done====
2440 13:19:11.587211
2441 13:19:11.590194 [DutyScan_Calibration_Flow] k_type=2
2442 13:19:11.605251
2443 13:19:11.605327 ==DQ 0 ==
2444 13:19:11.608342 Final DQ duty delay cell = -4
2445 13:19:11.612243 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2446 13:19:11.615347 [-4] MIN Duty = 4875%(X100), DQS PI = 52
2447 13:19:11.618518 [-4] AVG Duty = 4953%(X100)
2448 13:19:11.618592
2449 13:19:11.618649 ==DQ 1 ==
2450 13:19:11.622109 Final DQ duty delay cell = -4
2451 13:19:11.625227 [-4] MAX Duty = 5000%(X100), DQS PI = 56
2452 13:19:11.628735 [-4] MIN Duty = 4876%(X100), DQS PI = 14
2453 13:19:11.631991 [-4] AVG Duty = 4938%(X100)
2454 13:19:11.632066
2455 13:19:11.634971 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2456 13:19:11.635048
2457 13:19:11.638064 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2458 13:19:11.641341 [DutyScan_Calibration_Flow] ====Done====
2459 13:19:11.641415 ==
2460 13:19:11.645121 Dram Type= 6, Freq= 0, CH_1, rank 0
2461 13:19:11.648334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2462 13:19:11.648410 ==
2463 13:19:11.651460 [Duty_Offset_Calibration]
2464 13:19:11.654711 B0:-1 B1:1 CA:2
2465 13:19:11.654786
2466 13:19:11.657925 [DutyScan_Calibration_Flow] k_type=0
2467 13:19:11.665740
2468 13:19:11.665814 ==CLK 0==
2469 13:19:11.669472 Final CLK duty delay cell = 0
2470 13:19:11.672629 [0] MAX Duty = 5156%(X100), DQS PI = 22
2471 13:19:11.675659 [0] MIN Duty = 5000%(X100), DQS PI = 0
2472 13:19:11.675734 [0] AVG Duty = 5078%(X100)
2473 13:19:11.679249
2474 13:19:11.682751 CH1 CLK Duty spec in!! Max-Min= 156%
2475 13:19:11.685635 [DutyScan_Calibration_Flow] ====Done====
2476 13:19:11.685710
2477 13:19:11.689293 [DutyScan_Calibration_Flow] k_type=1
2478 13:19:11.705120
2479 13:19:11.705197 ==DQS 0 ==
2480 13:19:11.708601 Final DQS duty delay cell = 0
2481 13:19:11.711992 [0] MAX Duty = 5125%(X100), DQS PI = 48
2482 13:19:11.714950 [0] MIN Duty = 4875%(X100), DQS PI = 6
2483 13:19:11.718676 [0] AVG Duty = 5000%(X100)
2484 13:19:11.718750
2485 13:19:11.718816 ==DQS 1 ==
2486 13:19:11.721842 Final DQS duty delay cell = 0
2487 13:19:11.724966 [0] MAX Duty = 5062%(X100), DQS PI = 10
2488 13:19:11.728113 [0] MIN Duty = 4969%(X100), DQS PI = 54
2489 13:19:11.731313 [0] AVG Duty = 5015%(X100)
2490 13:19:11.731400
2491 13:19:11.735148 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2492 13:19:11.735237
2493 13:19:11.738244 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2494 13:19:11.741794 [DutyScan_Calibration_Flow] ====Done====
2495 13:19:11.741861
2496 13:19:11.744741 [DutyScan_Calibration_Flow] k_type=3
2497 13:19:11.760485
2498 13:19:11.760582 ==DQM 0 ==
2499 13:19:11.764350 Final DQM duty delay cell = -4
2500 13:19:11.767363 [-4] MAX Duty = 5031%(X100), DQS PI = 16
2501 13:19:11.771098 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2502 13:19:11.774260 [-4] AVG Duty = 4937%(X100)
2503 13:19:11.774337
2504 13:19:11.774391 ==DQM 1 ==
2505 13:19:11.777409 Final DQM duty delay cell = 0
2506 13:19:11.780451 [0] MAX Duty = 5187%(X100), DQS PI = 4
2507 13:19:11.784274 [0] MIN Duty = 4969%(X100), DQS PI = 28
2508 13:19:11.787451 [0] AVG Duty = 5078%(X100)
2509 13:19:11.787541
2510 13:19:11.790487 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2511 13:19:11.790562
2512 13:19:11.793760 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2513 13:19:11.797254 [DutyScan_Calibration_Flow] ====Done====
2514 13:19:11.797330
2515 13:19:11.800640 [DutyScan_Calibration_Flow] k_type=2
2516 13:19:11.817652
2517 13:19:11.817731 ==DQ 0 ==
2518 13:19:11.820655 Final DQ duty delay cell = 0
2519 13:19:11.824058 [0] MAX Duty = 5187%(X100), DQS PI = 30
2520 13:19:11.827734 [0] MIN Duty = 4907%(X100), DQS PI = 6
2521 13:19:11.827810 [0] AVG Duty = 5047%(X100)
2522 13:19:11.830868
2523 13:19:11.830944 ==DQ 1 ==
2524 13:19:11.834014 Final DQ duty delay cell = 0
2525 13:19:11.837237 [0] MAX Duty = 5124%(X100), DQS PI = 10
2526 13:19:11.840391 [0] MIN Duty = 4969%(X100), DQS PI = 0
2527 13:19:11.840468 [0] AVG Duty = 5046%(X100)
2528 13:19:11.840526
2529 13:19:11.844096 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2530 13:19:11.847202
2531 13:19:11.850360 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2532 13:19:11.854105 [DutyScan_Calibration_Flow] ====Done====
2533 13:19:11.857197 nWR fixed to 30
2534 13:19:11.857274 [ModeRegInit_LP4] CH0 RK0
2535 13:19:11.860679 [ModeRegInit_LP4] CH0 RK1
2536 13:19:11.863962 [ModeRegInit_LP4] CH1 RK0
2537 13:19:11.867312 [ModeRegInit_LP4] CH1 RK1
2538 13:19:11.867410 match AC timing 7
2539 13:19:11.873799 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2540 13:19:11.877122 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2541 13:19:11.880189 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2542 13:19:11.887108 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2543 13:19:11.890267 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2544 13:19:11.890344 ==
2545 13:19:11.893411 Dram Type= 6, Freq= 0, CH_0, rank 0
2546 13:19:11.897177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2547 13:19:11.897254 ==
2548 13:19:11.903798 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2549 13:19:11.909739 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2550 13:19:11.917312 [CA 0] Center 39 (9~70) winsize 62
2551 13:19:11.921060 [CA 1] Center 39 (9~69) winsize 61
2552 13:19:11.924086 [CA 2] Center 35 (5~66) winsize 62
2553 13:19:11.927631 [CA 3] Center 35 (5~66) winsize 62
2554 13:19:11.930556 [CA 4] Center 33 (4~63) winsize 60
2555 13:19:11.933969 [CA 5] Center 33 (3~63) winsize 61
2556 13:19:11.934045
2557 13:19:11.937030 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2558 13:19:11.937106
2559 13:19:11.940687 [CATrainingPosCal] consider 1 rank data
2560 13:19:11.943803 u2DelayCellTimex100 = 270/100 ps
2561 13:19:11.946967 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2562 13:19:11.953859 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2563 13:19:11.956997 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2564 13:19:11.960232 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2565 13:19:11.963363 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2566 13:19:11.967081 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2567 13:19:11.967156
2568 13:19:11.970116 CA PerBit enable=1, Macro0, CA PI delay=33
2569 13:19:11.970191
2570 13:19:11.973860 [CBTSetCACLKResult] CA Dly = 33
2571 13:19:11.976922 CS Dly: 8 (0~39)
2572 13:19:11.976997 ==
2573 13:19:11.980324 Dram Type= 6, Freq= 0, CH_0, rank 1
2574 13:19:11.983882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 13:19:11.983957 ==
2576 13:19:11.989900 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2577 13:19:11.993162 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2578 13:19:12.003056 [CA 0] Center 39 (8~70) winsize 63
2579 13:19:12.006244 [CA 1] Center 39 (9~70) winsize 62
2580 13:19:12.009430 [CA 2] Center 35 (5~66) winsize 62
2581 13:19:12.013100 [CA 3] Center 34 (4~65) winsize 62
2582 13:19:12.016511 [CA 4] Center 33 (3~64) winsize 62
2583 13:19:12.019420 [CA 5] Center 33 (3~63) winsize 61
2584 13:19:12.019498
2585 13:19:12.023213 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2586 13:19:12.023280
2587 13:19:12.026296 [CATrainingPosCal] consider 2 rank data
2588 13:19:12.029517 u2DelayCellTimex100 = 270/100 ps
2589 13:19:12.033149 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2590 13:19:12.039178 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2591 13:19:12.042660 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2592 13:19:12.045988 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2593 13:19:12.049073 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2594 13:19:12.052257 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2595 13:19:12.052333
2596 13:19:12.055977 CA PerBit enable=1, Macro0, CA PI delay=33
2597 13:19:12.056058
2598 13:19:12.059239 [CBTSetCACLKResult] CA Dly = 33
2599 13:19:12.062281 CS Dly: 9 (0~41)
2600 13:19:12.062371
2601 13:19:12.066086 ----->DramcWriteLeveling(PI) begin...
2602 13:19:12.066177 ==
2603 13:19:12.069187 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 13:19:12.072148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 13:19:12.072214 ==
2606 13:19:12.075337 Write leveling (Byte 0): 33 => 33
2607 13:19:12.079115 Write leveling (Byte 1): 29 => 29
2608 13:19:12.082224 DramcWriteLeveling(PI) end<-----
2609 13:19:12.082288
2610 13:19:12.082341 ==
2611 13:19:12.085335 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 13:19:12.089050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 13:19:12.089119 ==
2614 13:19:12.092106 [Gating] SW mode calibration
2615 13:19:12.099105 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2616 13:19:12.105341 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2617 13:19:12.108947 0 15 0 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
2618 13:19:12.111914 0 15 4 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
2619 13:19:12.118846 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2620 13:19:12.121859 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2621 13:19:12.125153 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2622 13:19:12.132148 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2623 13:19:12.135316 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2624 13:19:12.138495 0 15 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
2625 13:19:12.145379 1 0 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
2626 13:19:12.148317 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2627 13:19:12.151655 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2628 13:19:12.158107 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2629 13:19:12.161978 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2630 13:19:12.165048 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2631 13:19:12.171452 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2632 13:19:12.175187 1 0 28 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
2633 13:19:12.178249 1 1 0 | B1->B0 | 2323 4545 | 1 0 | (0 0) (0 0)
2634 13:19:12.184839 1 1 4 | B1->B0 | 3f3e 4646 | 1 0 | (0 0) (0 0)
2635 13:19:12.187949 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2636 13:19:12.191675 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2637 13:19:12.198084 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2638 13:19:12.201182 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2639 13:19:12.204323 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2640 13:19:12.211091 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2641 13:19:12.214434 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2642 13:19:12.217816 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2643 13:19:12.224409 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 13:19:12.227646 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 13:19:12.231030 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2646 13:19:12.237671 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2647 13:19:12.240803 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2648 13:19:12.243956 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2649 13:19:12.250911 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2650 13:19:12.254034 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2651 13:19:12.257646 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2652 13:19:12.264155 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2653 13:19:12.267533 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2654 13:19:12.270525 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2655 13:19:12.277463 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2656 13:19:12.280427 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2657 13:19:12.284067 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2658 13:19:12.287324 Total UI for P1: 0, mck2ui 16
2659 13:19:12.290407 best dqsien dly found for B0: ( 1, 3, 28)
2660 13:19:12.297168 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2661 13:19:12.297244 Total UI for P1: 0, mck2ui 16
2662 13:19:12.300328 best dqsien dly found for B1: ( 1, 4, 0)
2663 13:19:12.307266 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2664 13:19:12.310369 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2665 13:19:12.310465
2666 13:19:12.313484 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2667 13:19:12.316639 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2668 13:19:12.320228 [Gating] SW calibration Done
2669 13:19:12.320293 ==
2670 13:19:12.323353 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 13:19:12.326759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 13:19:12.326847 ==
2673 13:19:12.330372 RX Vref Scan: 0
2674 13:19:12.330448
2675 13:19:12.330506 RX Vref 0 -> 0, step: 1
2676 13:19:12.330561
2677 13:19:12.333253 RX Delay -40 -> 252, step: 8
2678 13:19:12.336471 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2679 13:19:12.343211 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2680 13:19:12.346740 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2681 13:19:12.349922 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2682 13:19:12.353168 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2683 13:19:12.356413 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2684 13:19:12.363118 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2685 13:19:12.366197 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2686 13:19:12.369978 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2687 13:19:12.373151 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2688 13:19:12.376714 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2689 13:19:12.383355 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2690 13:19:12.386443 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2691 13:19:12.389586 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2692 13:19:12.393374 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2693 13:19:12.396517 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2694 13:19:12.399491 ==
2695 13:19:12.403298 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 13:19:12.406447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 13:19:12.406524 ==
2698 13:19:12.406583 DQS Delay:
2699 13:19:12.409604 DQS0 = 0, DQS1 = 0
2700 13:19:12.409703 DQM Delay:
2701 13:19:12.413312 DQM0 = 119, DQM1 = 106
2702 13:19:12.413387 DQ Delay:
2703 13:19:12.416451 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2704 13:19:12.419661 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2705 13:19:12.422688 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2706 13:19:12.426559 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2707 13:19:12.426634
2708 13:19:12.426692
2709 13:19:12.426746 ==
2710 13:19:12.429674 Dram Type= 6, Freq= 0, CH_0, rank 0
2711 13:19:12.436541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2712 13:19:12.436615 ==
2713 13:19:12.436691
2714 13:19:12.436746
2715 13:19:12.436798 TX Vref Scan disable
2716 13:19:12.439678 == TX Byte 0 ==
2717 13:19:12.442660 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2718 13:19:12.449595 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2719 13:19:12.449693 == TX Byte 1 ==
2720 13:19:12.452935 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2721 13:19:12.459382 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2722 13:19:12.459503 ==
2723 13:19:12.462540 Dram Type= 6, Freq= 0, CH_0, rank 0
2724 13:19:12.465718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2725 13:19:12.465818 ==
2726 13:19:12.477549 TX Vref=22, minBit 5, minWin=25, winSum=416
2727 13:19:12.480667 TX Vref=24, minBit 10, minWin=25, winSum=422
2728 13:19:12.484418 TX Vref=26, minBit 4, minWin=26, winSum=429
2729 13:19:12.487308 TX Vref=28, minBit 15, minWin=26, winSum=433
2730 13:19:12.490748 TX Vref=30, minBit 4, minWin=26, winSum=433
2731 13:19:12.497621 TX Vref=32, minBit 5, minWin=26, winSum=432
2732 13:19:12.500860 [TxChooseVref] Worse bit 15, Min win 26, Win sum 433, Final Vref 28
2733 13:19:12.500932
2734 13:19:12.503802 Final TX Range 1 Vref 28
2735 13:19:12.503871
2736 13:19:12.503927 ==
2737 13:19:12.507458 Dram Type= 6, Freq= 0, CH_0, rank 0
2738 13:19:12.513916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2739 13:19:12.514009 ==
2740 13:19:12.514094
2741 13:19:12.514151
2742 13:19:12.514204 TX Vref Scan disable
2743 13:19:12.517529 == TX Byte 0 ==
2744 13:19:12.520647 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2745 13:19:12.527438 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2746 13:19:12.527531 == TX Byte 1 ==
2747 13:19:12.530660 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2748 13:19:12.537316 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2749 13:19:12.537393
2750 13:19:12.537452 [DATLAT]
2751 13:19:12.537507 Freq=1200, CH0 RK0
2752 13:19:12.537559
2753 13:19:12.540434 DATLAT Default: 0xd
2754 13:19:12.544117 0, 0xFFFF, sum = 0
2755 13:19:12.544194 1, 0xFFFF, sum = 0
2756 13:19:12.547184 2, 0xFFFF, sum = 0
2757 13:19:12.547274 3, 0xFFFF, sum = 0
2758 13:19:12.550370 4, 0xFFFF, sum = 0
2759 13:19:12.550462 5, 0xFFFF, sum = 0
2760 13:19:12.554138 6, 0xFFFF, sum = 0
2761 13:19:12.554226 7, 0xFFFF, sum = 0
2762 13:19:12.557231 8, 0xFFFF, sum = 0
2763 13:19:12.557330 9, 0xFFFF, sum = 0
2764 13:19:12.560808 10, 0xFFFF, sum = 0
2765 13:19:12.560876 11, 0xFFFF, sum = 0
2766 13:19:12.564087 12, 0x0, sum = 1
2767 13:19:12.564152 13, 0x0, sum = 2
2768 13:19:12.567406 14, 0x0, sum = 3
2769 13:19:12.567508 15, 0x0, sum = 4
2770 13:19:12.570837 best_step = 13
2771 13:19:12.570913
2772 13:19:12.570971 ==
2773 13:19:12.573648 Dram Type= 6, Freq= 0, CH_0, rank 0
2774 13:19:12.577277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2775 13:19:12.577354 ==
2776 13:19:12.580491 RX Vref Scan: 1
2777 13:19:12.580567
2778 13:19:12.580625 Set Vref Range= 32 -> 127
2779 13:19:12.580679
2780 13:19:12.583680 RX Vref 32 -> 127, step: 1
2781 13:19:12.583755
2782 13:19:12.586843 RX Delay -21 -> 252, step: 4
2783 13:19:12.586919
2784 13:19:12.590056 Set Vref, RX VrefLevel [Byte0]: 32
2785 13:19:12.593221 [Byte1]: 32
2786 13:19:12.593296
2787 13:19:12.596668 Set Vref, RX VrefLevel [Byte0]: 33
2788 13:19:12.600002 [Byte1]: 33
2789 13:19:12.604040
2790 13:19:12.604115 Set Vref, RX VrefLevel [Byte0]: 34
2791 13:19:12.607086 [Byte1]: 34
2792 13:19:12.612014
2793 13:19:12.612089 Set Vref, RX VrefLevel [Byte0]: 35
2794 13:19:12.615095 [Byte1]: 35
2795 13:19:12.619971
2796 13:19:12.620050 Set Vref, RX VrefLevel [Byte0]: 36
2797 13:19:12.623112 [Byte1]: 36
2798 13:19:12.627835
2799 13:19:12.627911 Set Vref, RX VrefLevel [Byte0]: 37
2800 13:19:12.630994 [Byte1]: 37
2801 13:19:12.636075
2802 13:19:12.636150 Set Vref, RX VrefLevel [Byte0]: 38
2803 13:19:12.639245 [Byte1]: 38
2804 13:19:12.643559
2805 13:19:12.643634 Set Vref, RX VrefLevel [Byte0]: 39
2806 13:19:12.647138 [Byte1]: 39
2807 13:19:12.651550
2808 13:19:12.651626 Set Vref, RX VrefLevel [Byte0]: 40
2809 13:19:12.655272 [Byte1]: 40
2810 13:19:12.659380
2811 13:19:12.659495 Set Vref, RX VrefLevel [Byte0]: 41
2812 13:19:12.663279 [Byte1]: 41
2813 13:19:12.667721
2814 13:19:12.667797 Set Vref, RX VrefLevel [Byte0]: 42
2815 13:19:12.670614 [Byte1]: 42
2816 13:19:12.675392
2817 13:19:12.675507 Set Vref, RX VrefLevel [Byte0]: 43
2818 13:19:12.678895 [Byte1]: 43
2819 13:19:12.683507
2820 13:19:12.683583 Set Vref, RX VrefLevel [Byte0]: 44
2821 13:19:12.686736 [Byte1]: 44
2822 13:19:12.691417
2823 13:19:12.691530 Set Vref, RX VrefLevel [Byte0]: 45
2824 13:19:12.694688 [Byte1]: 45
2825 13:19:12.699105
2826 13:19:12.699179 Set Vref, RX VrefLevel [Byte0]: 46
2827 13:19:12.702176 [Byte1]: 46
2828 13:19:12.706995
2829 13:19:12.707070 Set Vref, RX VrefLevel [Byte0]: 47
2830 13:19:12.710434 [Byte1]: 47
2831 13:19:12.715108
2832 13:19:12.715183 Set Vref, RX VrefLevel [Byte0]: 48
2833 13:19:12.718493 [Byte1]: 48
2834 13:19:12.722796
2835 13:19:12.722871 Set Vref, RX VrefLevel [Byte0]: 49
2836 13:19:12.726502 [Byte1]: 49
2837 13:19:12.730822
2838 13:19:12.730897 Set Vref, RX VrefLevel [Byte0]: 50
2839 13:19:12.734059 [Byte1]: 50
2840 13:19:12.739081
2841 13:19:12.739179 Set Vref, RX VrefLevel [Byte0]: 51
2842 13:19:12.742265 [Byte1]: 51
2843 13:19:12.746650
2844 13:19:12.746725 Set Vref, RX VrefLevel [Byte0]: 52
2845 13:19:12.749773 [Byte1]: 52
2846 13:19:12.754758
2847 13:19:12.754833 Set Vref, RX VrefLevel [Byte0]: 53
2848 13:19:12.757902 [Byte1]: 53
2849 13:19:12.762285
2850 13:19:12.762363 Set Vref, RX VrefLevel [Byte0]: 54
2851 13:19:12.765832 [Byte1]: 54
2852 13:19:12.770262
2853 13:19:12.770337 Set Vref, RX VrefLevel [Byte0]: 55
2854 13:19:12.774066 [Byte1]: 55
2855 13:19:12.778456
2856 13:19:12.778532 Set Vref, RX VrefLevel [Byte0]: 56
2857 13:19:12.781502 [Byte1]: 56
2858 13:19:12.786437
2859 13:19:12.786512 Set Vref, RX VrefLevel [Byte0]: 57
2860 13:19:12.789475 [Byte1]: 57
2861 13:19:12.794243
2862 13:19:12.794318 Set Vref, RX VrefLevel [Byte0]: 58
2863 13:19:12.797649 [Byte1]: 58
2864 13:19:12.801898
2865 13:19:12.801991 Set Vref, RX VrefLevel [Byte0]: 59
2866 13:19:12.805759 [Byte1]: 59
2867 13:19:12.810090
2868 13:19:12.810165 Set Vref, RX VrefLevel [Byte0]: 60
2869 13:19:12.813254 [Byte1]: 60
2870 13:19:12.818240
2871 13:19:12.818310 Set Vref, RX VrefLevel [Byte0]: 61
2872 13:19:12.821125 [Byte1]: 61
2873 13:19:12.826208
2874 13:19:12.826292 Set Vref, RX VrefLevel [Byte0]: 62
2875 13:19:12.829442 [Byte1]: 62
2876 13:19:12.833892
2877 13:19:12.833968 Set Vref, RX VrefLevel [Byte0]: 63
2878 13:19:12.837193 [Byte1]: 63
2879 13:19:12.842119
2880 13:19:12.842194 Set Vref, RX VrefLevel [Byte0]: 64
2881 13:19:12.845344 [Byte1]: 64
2882 13:19:12.849682
2883 13:19:12.849774 Set Vref, RX VrefLevel [Byte0]: 65
2884 13:19:12.853272 [Byte1]: 65
2885 13:19:12.857650
2886 13:19:12.857726 Set Vref, RX VrefLevel [Byte0]: 66
2887 13:19:12.860776 [Byte1]: 66
2888 13:19:12.865853
2889 13:19:12.865928 Set Vref, RX VrefLevel [Byte0]: 67
2890 13:19:12.868868 [Byte1]: 67
2891 13:19:12.873864
2892 13:19:12.873938 Set Vref, RX VrefLevel [Byte0]: 68
2893 13:19:12.876978 [Byte1]: 68
2894 13:19:12.881457
2895 13:19:12.881533 Set Vref, RX VrefLevel [Byte0]: 69
2896 13:19:12.884534 [Byte1]: 69
2897 13:19:12.889559
2898 13:19:12.889635 Set Vref, RX VrefLevel [Byte0]: 70
2899 13:19:12.892594 [Byte1]: 70
2900 13:19:12.897707
2901 13:19:12.897783 Set Vref, RX VrefLevel [Byte0]: 71
2902 13:19:12.900653 [Byte1]: 71
2903 13:19:12.905209
2904 13:19:12.905284 Set Vref, RX VrefLevel [Byte0]: 72
2905 13:19:12.908721 [Byte1]: 72
2906 13:19:12.913294
2907 13:19:12.913370 Set Vref, RX VrefLevel [Byte0]: 73
2908 13:19:12.916462 [Byte1]: 73
2909 13:19:12.921426
2910 13:19:12.921500 Set Vref, RX VrefLevel [Byte0]: 74
2911 13:19:12.924505 [Byte1]: 74
2912 13:19:12.929016
2913 13:19:12.929095 Set Vref, RX VrefLevel [Byte0]: 75
2914 13:19:12.932149 [Byte1]: 75
2915 13:19:12.936977
2916 13:19:12.937052 Set Vref, RX VrefLevel [Byte0]: 76
2917 13:19:12.940319 [Byte1]: 76
2918 13:19:12.945037
2919 13:19:12.945138 Set Vref, RX VrefLevel [Byte0]: 77
2920 13:19:12.948226 [Byte1]: 77
2921 13:19:12.952800
2922 13:19:12.952876 Set Vref, RX VrefLevel [Byte0]: 78
2923 13:19:12.956122 [Byte1]: 78
2924 13:19:12.960876
2925 13:19:12.960952 Final RX Vref Byte 0 = 61 to rank0
2926 13:19:12.963826 Final RX Vref Byte 1 = 49 to rank0
2927 13:19:12.967652 Final RX Vref Byte 0 = 61 to rank1
2928 13:19:12.970851 Final RX Vref Byte 1 = 49 to rank1==
2929 13:19:12.973758 Dram Type= 6, Freq= 0, CH_0, rank 0
2930 13:19:12.980536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 13:19:12.980612 ==
2932 13:19:12.980671 DQS Delay:
2933 13:19:12.983722 DQS0 = 0, DQS1 = 0
2934 13:19:12.983798 DQM Delay:
2935 13:19:12.983858 DQM0 = 118, DQM1 = 106
2936 13:19:12.986801 DQ Delay:
2937 13:19:12.990546 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2938 13:19:12.993611 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =126
2939 13:19:12.996676 DQ8 =96, DQ9 =92, DQ10 =108, DQ11 =100
2940 13:19:13.000567 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =116
2941 13:19:13.000667
2942 13:19:13.000756
2943 13:19:13.010469 [DQSOSCAuto] RK0, (LSB)MR18= 0x11fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2944 13:19:13.010546 CH0 RK0: MR19=403, MR18=11FD
2945 13:19:13.017095 CH0_RK0: MR19=0x403, MR18=0x11FD, DQSOSC=403, MR23=63, INC=40, DEC=26
2946 13:19:13.017172
2947 13:19:13.020299 ----->DramcWriteLeveling(PI) begin...
2948 13:19:13.020376 ==
2949 13:19:13.023463 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 13:19:13.029831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 13:19:13.029908 ==
2952 13:19:13.033595 Write leveling (Byte 0): 31 => 31
2953 13:19:13.036742 Write leveling (Byte 1): 28 => 28
2954 13:19:13.036818 DramcWriteLeveling(PI) end<-----
2955 13:19:13.036877
2956 13:19:13.039879 ==
2957 13:19:13.042925 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 13:19:13.046716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 13:19:13.046791 ==
2960 13:19:13.049729 [Gating] SW mode calibration
2961 13:19:13.056489 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2962 13:19:13.059444 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2963 13:19:13.066106 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2964 13:19:13.069462 0 15 4 | B1->B0 | 3231 3434 | 1 1 | (0 0) (1 1)
2965 13:19:13.073135 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2966 13:19:13.079591 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2967 13:19:13.082761 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2968 13:19:13.086473 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2969 13:19:13.093285 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2970 13:19:13.096355 0 15 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
2971 13:19:13.099468 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2972 13:19:13.106189 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2973 13:19:13.109288 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2974 13:19:13.112458 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2975 13:19:13.119248 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2976 13:19:13.122344 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2977 13:19:13.125872 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2978 13:19:13.132301 1 0 28 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
2979 13:19:13.135437 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2980 13:19:13.138717 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2981 13:19:13.145555 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2982 13:19:13.148701 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2983 13:19:13.152390 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2984 13:19:13.158527 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2985 13:19:13.161589 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2986 13:19:13.165109 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2987 13:19:13.171417 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2988 13:19:13.175297 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 13:19:13.178393 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 13:19:13.184815 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 13:19:13.188189 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 13:19:13.191585 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 13:19:13.198190 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 13:19:13.201448 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 13:19:13.204794 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 13:19:13.211353 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 13:19:13.214581 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2998 13:19:13.218154 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2999 13:19:13.224452 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3000 13:19:13.228099 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3001 13:19:13.231046 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3002 13:19:13.237657 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3003 13:19:13.240884 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3004 13:19:13.244034 Total UI for P1: 0, mck2ui 16
3005 13:19:13.247819 best dqsien dly found for B0: ( 1, 3, 28)
3006 13:19:13.251023 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3007 13:19:13.254134 Total UI for P1: 0, mck2ui 16
3008 13:19:13.257341 best dqsien dly found for B1: ( 1, 4, 0)
3009 13:19:13.260422 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3010 13:19:13.267526 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3011 13:19:13.267619
3012 13:19:13.270584 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3013 13:19:13.274057 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3014 13:19:13.276887 [Gating] SW calibration Done
3015 13:19:13.276963 ==
3016 13:19:13.280052 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 13:19:13.283798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 13:19:13.283877 ==
3019 13:19:13.286659 RX Vref Scan: 0
3020 13:19:13.286756
3021 13:19:13.286840 RX Vref 0 -> 0, step: 1
3022 13:19:13.286921
3023 13:19:13.289954 RX Delay -40 -> 252, step: 8
3024 13:19:13.293614 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3025 13:19:13.299888 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3026 13:19:13.303558 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3027 13:19:13.306600 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3028 13:19:13.310279 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3029 13:19:13.313042 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3030 13:19:13.319816 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3031 13:19:13.323162 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3032 13:19:13.326577 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3033 13:19:13.329863 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3034 13:19:13.332968 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3035 13:19:13.339721 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3036 13:19:13.342841 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3037 13:19:13.346066 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3038 13:19:13.349835 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3039 13:19:13.353080 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3040 13:19:13.356231 ==
3041 13:19:13.359285 Dram Type= 6, Freq= 0, CH_0, rank 1
3042 13:19:13.362970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3043 13:19:13.363068 ==
3044 13:19:13.363162 DQS Delay:
3045 13:19:13.366088 DQS0 = 0, DQS1 = 0
3046 13:19:13.366155 DQM Delay:
3047 13:19:13.369140 DQM0 = 116, DQM1 = 108
3048 13:19:13.369236 DQ Delay:
3049 13:19:13.372842 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
3050 13:19:13.376012 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
3051 13:19:13.379019 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3052 13:19:13.382475 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3053 13:19:13.382553
3054 13:19:13.382612
3055 13:19:13.382665 ==
3056 13:19:13.385936 Dram Type= 6, Freq= 0, CH_0, rank 1
3057 13:19:13.392099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3058 13:19:13.392184 ==
3059 13:19:13.392277
3060 13:19:13.392331
3061 13:19:13.392382 TX Vref Scan disable
3062 13:19:13.395895 == TX Byte 0 ==
3063 13:19:13.399618 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3064 13:19:13.405778 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3065 13:19:13.405880 == TX Byte 1 ==
3066 13:19:13.408969 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3067 13:19:13.415814 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3068 13:19:13.415903 ==
3069 13:19:13.418930 Dram Type= 6, Freq= 0, CH_0, rank 1
3070 13:19:13.422505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 13:19:13.422601 ==
3072 13:19:13.433953 TX Vref=22, minBit 5, minWin=25, winSum=417
3073 13:19:13.437366 TX Vref=24, minBit 5, minWin=25, winSum=422
3074 13:19:13.440736 TX Vref=26, minBit 13, minWin=25, winSum=424
3075 13:19:13.444410 TX Vref=28, minBit 2, minWin=26, winSum=431
3076 13:19:13.447841 TX Vref=30, minBit 8, minWin=26, winSum=430
3077 13:19:13.453965 TX Vref=32, minBit 14, minWin=26, winSum=433
3078 13:19:13.457725 [TxChooseVref] Worse bit 14, Min win 26, Win sum 433, Final Vref 32
3079 13:19:13.457833
3080 13:19:13.460857 Final TX Range 1 Vref 32
3081 13:19:13.460935
3082 13:19:13.460994 ==
3083 13:19:13.463826 Dram Type= 6, Freq= 0, CH_0, rank 1
3084 13:19:13.467616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3085 13:19:13.470688 ==
3086 13:19:13.470795
3087 13:19:13.470854
3088 13:19:13.470908 TX Vref Scan disable
3089 13:19:13.473929 == TX Byte 0 ==
3090 13:19:13.477692 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3091 13:19:13.484035 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3092 13:19:13.484143 == TX Byte 1 ==
3093 13:19:13.487670 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3094 13:19:13.494013 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3095 13:19:13.494105
3096 13:19:13.494164 [DATLAT]
3097 13:19:13.494219 Freq=1200, CH0 RK1
3098 13:19:13.494287
3099 13:19:13.497460 DATLAT Default: 0xd
3100 13:19:13.497562 0, 0xFFFF, sum = 0
3101 13:19:13.500700 1, 0xFFFF, sum = 0
3102 13:19:13.504355 2, 0xFFFF, sum = 0
3103 13:19:13.504459 3, 0xFFFF, sum = 0
3104 13:19:13.507420 4, 0xFFFF, sum = 0
3105 13:19:13.507565 5, 0xFFFF, sum = 0
3106 13:19:13.510440 6, 0xFFFF, sum = 0
3107 13:19:13.510538 7, 0xFFFF, sum = 0
3108 13:19:13.514268 8, 0xFFFF, sum = 0
3109 13:19:13.514350 9, 0xFFFF, sum = 0
3110 13:19:13.517495 10, 0xFFFF, sum = 0
3111 13:19:13.517602 11, 0xFFFF, sum = 0
3112 13:19:13.520630 12, 0x0, sum = 1
3113 13:19:13.520729 13, 0x0, sum = 2
3114 13:19:13.523746 14, 0x0, sum = 3
3115 13:19:13.523845 15, 0x0, sum = 4
3116 13:19:13.526972 best_step = 13
3117 13:19:13.527061
3118 13:19:13.527145 ==
3119 13:19:13.530580 Dram Type= 6, Freq= 0, CH_0, rank 1
3120 13:19:13.533650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 13:19:13.533732 ==
3122 13:19:13.533793 RX Vref Scan: 0
3123 13:19:13.537440
3124 13:19:13.537518 RX Vref 0 -> 0, step: 1
3125 13:19:13.537577
3126 13:19:13.540742 RX Delay -21 -> 252, step: 4
3127 13:19:13.546932 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3128 13:19:13.550520 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3129 13:19:13.553787 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3130 13:19:13.557081 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3131 13:19:13.560473 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3132 13:19:13.566591 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3133 13:19:13.569733 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3134 13:19:13.573519 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3135 13:19:13.576643 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3136 13:19:13.579876 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3137 13:19:13.586208 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3138 13:19:13.589925 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3139 13:19:13.593027 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3140 13:19:13.596260 iDelay=195, Bit 13, Center 114 (47 ~ 182) 136
3141 13:19:13.599618 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3142 13:19:13.606247 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3143 13:19:13.606346 ==
3144 13:19:13.609813 Dram Type= 6, Freq= 0, CH_0, rank 1
3145 13:19:13.612772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3146 13:19:13.612859 ==
3147 13:19:13.612919 DQS Delay:
3148 13:19:13.616454 DQS0 = 0, DQS1 = 0
3149 13:19:13.616645 DQM Delay:
3150 13:19:13.619423 DQM0 = 116, DQM1 = 107
3151 13:19:13.619527 DQ Delay:
3152 13:19:13.622643 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3153 13:19:13.625776 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3154 13:19:13.629111 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3155 13:19:13.635724 DQ12 =110, DQ13 =114, DQ14 =118, DQ15 =116
3156 13:19:13.635826
3157 13:19:13.635886
3158 13:19:13.642600 [DQSOSCAuto] RK1, (LSB)MR18= 0xae6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 406 ps
3159 13:19:13.645565 CH0 RK1: MR19=403, MR18=AE6
3160 13:19:13.652363 CH0_RK1: MR19=0x403, MR18=0xAE6, DQSOSC=406, MR23=63, INC=39, DEC=26
3161 13:19:13.656107 [RxdqsGatingPostProcess] freq 1200
3162 13:19:13.659179 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3163 13:19:13.662210 best DQS0 dly(2T, 0.5T) = (0, 11)
3164 13:19:13.665697 best DQS1 dly(2T, 0.5T) = (0, 12)
3165 13:19:13.668847 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3166 13:19:13.672444 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3167 13:19:13.675300 best DQS0 dly(2T, 0.5T) = (0, 11)
3168 13:19:13.678485 best DQS1 dly(2T, 0.5T) = (0, 12)
3169 13:19:13.682261 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3170 13:19:13.685324 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3171 13:19:13.688539 Pre-setting of DQS Precalculation
3172 13:19:13.691630 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3173 13:19:13.691711 ==
3174 13:19:13.695363 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 13:19:13.702253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3176 13:19:13.702380 ==
3177 13:19:13.705306 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3178 13:19:13.711635 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3179 13:19:13.720312 [CA 0] Center 37 (7~68) winsize 62
3180 13:19:13.723750 [CA 1] Center 37 (7~68) winsize 62
3181 13:19:13.727210 [CA 2] Center 34 (4~64) winsize 61
3182 13:19:13.730344 [CA 3] Center 33 (3~64) winsize 62
3183 13:19:13.733393 [CA 4] Center 34 (5~64) winsize 60
3184 13:19:13.736606 [CA 5] Center 33 (3~64) winsize 62
3185 13:19:13.736695
3186 13:19:13.740288 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3187 13:19:13.740372
3188 13:19:13.743400 [CATrainingPosCal] consider 1 rank data
3189 13:19:13.746642 u2DelayCellTimex100 = 270/100 ps
3190 13:19:13.750220 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3191 13:19:13.756287 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3192 13:19:13.760071 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3193 13:19:13.763182 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3194 13:19:13.766251 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3195 13:19:13.770014 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3196 13:19:13.770099
3197 13:19:13.773163 CA PerBit enable=1, Macro0, CA PI delay=33
3198 13:19:13.773242
3199 13:19:13.776083 [CBTSetCACLKResult] CA Dly = 33
3200 13:19:13.779298 CS Dly: 5 (0~36)
3201 13:19:13.779376 ==
3202 13:19:13.782677 Dram Type= 6, Freq= 0, CH_1, rank 1
3203 13:19:13.786232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3204 13:19:13.786315 ==
3205 13:19:13.792397 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3206 13:19:13.796124 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3207 13:19:13.805788 [CA 0] Center 37 (7~68) winsize 62
3208 13:19:13.808987 [CA 1] Center 38 (8~68) winsize 61
3209 13:19:13.812772 [CA 2] Center 34 (4~65) winsize 62
3210 13:19:13.815913 [CA 3] Center 33 (3~64) winsize 62
3211 13:19:13.818912 [CA 4] Center 34 (4~65) winsize 62
3212 13:19:13.822498 [CA 5] Center 33 (3~64) winsize 62
3213 13:19:13.822582
3214 13:19:13.825734 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3215 13:19:13.825828
3216 13:19:13.829028 [CATrainingPosCal] consider 2 rank data
3217 13:19:13.831937 u2DelayCellTimex100 = 270/100 ps
3218 13:19:13.835291 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3219 13:19:13.842120 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3220 13:19:13.845207 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3221 13:19:13.848997 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3222 13:19:13.852085 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3223 13:19:13.855211 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3224 13:19:13.855294
3225 13:19:13.858850 CA PerBit enable=1, Macro0, CA PI delay=33
3226 13:19:13.858949
3227 13:19:13.861909 [CBTSetCACLKResult] CA Dly = 33
3228 13:19:13.865475 CS Dly: 7 (0~40)
3229 13:19:13.865583
3230 13:19:13.868616 ----->DramcWriteLeveling(PI) begin...
3231 13:19:13.868691 ==
3232 13:19:13.871790 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 13:19:13.874908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 13:19:13.874981 ==
3235 13:19:13.878133 Write leveling (Byte 0): 24 => 24
3236 13:19:13.881834 Write leveling (Byte 1): 30 => 30
3237 13:19:13.885267 DramcWriteLeveling(PI) end<-----
3238 13:19:13.885396
3239 13:19:13.885456 ==
3240 13:19:13.888322 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 13:19:13.891873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 13:19:13.891952 ==
3243 13:19:13.894820 [Gating] SW mode calibration
3244 13:19:13.901447 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3245 13:19:13.908395 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3246 13:19:13.911471 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
3247 13:19:13.914661 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3248 13:19:13.921512 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3249 13:19:13.924682 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3250 13:19:13.927905 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3251 13:19:13.934448 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3252 13:19:13.938066 0 15 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
3253 13:19:13.941038 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3254 13:19:13.947193 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3255 13:19:13.950586 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3256 13:19:13.957106 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3257 13:19:13.960796 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3258 13:19:13.963822 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3259 13:19:13.970524 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3260 13:19:13.973684 1 0 24 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
3261 13:19:13.976918 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
3262 13:19:13.983738 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3263 13:19:13.986915 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3264 13:19:13.990461 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3265 13:19:13.996742 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3266 13:19:14.000304 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3267 13:19:14.003240 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3268 13:19:14.009988 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3269 13:19:14.013129 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3270 13:19:14.016293 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3271 13:19:14.023178 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3272 13:19:14.026242 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3273 13:19:14.029368 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3274 13:19:14.036251 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3275 13:19:14.039340 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3276 13:19:14.042957 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3277 13:19:14.049840 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3278 13:19:14.052968 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3279 13:19:14.056138 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3280 13:19:14.062497 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3281 13:19:14.066020 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3282 13:19:14.069054 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3283 13:19:14.076106 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3284 13:19:14.079307 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3285 13:19:14.082475 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3286 13:19:14.088767 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3287 13:19:14.088865 Total UI for P1: 0, mck2ui 16
3288 13:19:14.095545 best dqsien dly found for B0: ( 1, 3, 28)
3289 13:19:14.095679 Total UI for P1: 0, mck2ui 16
3290 13:19:14.098683 best dqsien dly found for B1: ( 1, 3, 28)
3291 13:19:14.105465 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3292 13:19:14.109085 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3293 13:19:14.109164
3294 13:19:14.112039 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3295 13:19:14.115693 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3296 13:19:14.118916 [Gating] SW calibration Done
3297 13:19:14.118996 ==
3298 13:19:14.122053 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 13:19:14.125214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 13:19:14.125285 ==
3301 13:19:14.128947 RX Vref Scan: 0
3302 13:19:14.129028
3303 13:19:14.129087 RX Vref 0 -> 0, step: 1
3304 13:19:14.129141
3305 13:19:14.132037 RX Delay -40 -> 252, step: 8
3306 13:19:14.135171 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3307 13:19:14.141983 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3308 13:19:14.145398 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3309 13:19:14.148341 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3310 13:19:14.151972 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3311 13:19:14.155113 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3312 13:19:14.162036 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3313 13:19:14.165106 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3314 13:19:14.167987 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3315 13:19:14.171343 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3316 13:19:14.174491 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3317 13:19:14.181214 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3318 13:19:14.184948 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3319 13:19:14.187828 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3320 13:19:14.191626 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3321 13:19:14.197884 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3322 13:19:14.197980 ==
3323 13:19:14.201492 Dram Type= 6, Freq= 0, CH_1, rank 0
3324 13:19:14.204506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3325 13:19:14.204587 ==
3326 13:19:14.204647 DQS Delay:
3327 13:19:14.207704 DQS0 = 0, DQS1 = 0
3328 13:19:14.207781 DQM Delay:
3329 13:19:14.210859 DQM0 = 117, DQM1 = 108
3330 13:19:14.210937 DQ Delay:
3331 13:19:14.214597 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3332 13:19:14.217757 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3333 13:19:14.221263 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3334 13:19:14.224294 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3335 13:19:14.224377
3336 13:19:14.224440
3337 13:19:14.224497 ==
3338 13:19:14.227361 Dram Type= 6, Freq= 0, CH_1, rank 0
3339 13:19:14.234235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3340 13:19:14.234354 ==
3341 13:19:14.234439
3342 13:19:14.234527
3343 13:19:14.237376 TX Vref Scan disable
3344 13:19:14.237476 == TX Byte 0 ==
3345 13:19:14.240664 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3346 13:19:14.247372 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3347 13:19:14.247521 == TX Byte 1 ==
3348 13:19:14.250276 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3349 13:19:14.256849 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3350 13:19:14.256969 ==
3351 13:19:14.260041 Dram Type= 6, Freq= 0, CH_1, rank 0
3352 13:19:14.263788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3353 13:19:14.263873 ==
3354 13:19:14.276079 TX Vref=22, minBit 10, minWin=23, winSum=411
3355 13:19:14.279107 TX Vref=24, minBit 10, minWin=24, winSum=423
3356 13:19:14.282512 TX Vref=26, minBit 9, minWin=24, winSum=422
3357 13:19:14.285676 TX Vref=28, minBit 8, minWin=26, winSum=433
3358 13:19:14.288938 TX Vref=30, minBit 11, minWin=25, winSum=428
3359 13:19:14.296239 TX Vref=32, minBit 8, minWin=25, winSum=426
3360 13:19:14.299277 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 28
3361 13:19:14.299364
3362 13:19:14.302363 Final TX Range 1 Vref 28
3363 13:19:14.302443
3364 13:19:14.302501 ==
3365 13:19:14.305929 Dram Type= 6, Freq= 0, CH_1, rank 0
3366 13:19:14.312092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3367 13:19:14.312184 ==
3368 13:19:14.312243
3369 13:19:14.312296
3370 13:19:14.312363 TX Vref Scan disable
3371 13:19:14.315834 == TX Byte 0 ==
3372 13:19:14.319683 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3373 13:19:14.325818 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3374 13:19:14.325912 == TX Byte 1 ==
3375 13:19:14.329378 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3376 13:19:14.335938 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3377 13:19:14.336042
3378 13:19:14.336102 [DATLAT]
3379 13:19:14.336156 Freq=1200, CH1 RK0
3380 13:19:14.336209
3381 13:19:14.339047 DATLAT Default: 0xd
3382 13:19:14.342230 0, 0xFFFF, sum = 0
3383 13:19:14.342298 1, 0xFFFF, sum = 0
3384 13:19:14.345950 2, 0xFFFF, sum = 0
3385 13:19:14.346025 3, 0xFFFF, sum = 0
3386 13:19:14.348964 4, 0xFFFF, sum = 0
3387 13:19:14.349037 5, 0xFFFF, sum = 0
3388 13:19:14.352153 6, 0xFFFF, sum = 0
3389 13:19:14.352236 7, 0xFFFF, sum = 0
3390 13:19:14.355607 8, 0xFFFF, sum = 0
3391 13:19:14.355678 9, 0xFFFF, sum = 0
3392 13:19:14.359229 10, 0xFFFF, sum = 0
3393 13:19:14.359330 11, 0xFFFF, sum = 0
3394 13:19:14.362243 12, 0x0, sum = 1
3395 13:19:14.362321 13, 0x0, sum = 2
3396 13:19:14.365426 14, 0x0, sum = 3
3397 13:19:14.365501 15, 0x0, sum = 4
3398 13:19:14.368545 best_step = 13
3399 13:19:14.368610
3400 13:19:14.368663 ==
3401 13:19:14.372392 Dram Type= 6, Freq= 0, CH_1, rank 0
3402 13:19:14.375647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3403 13:19:14.375724 ==
3404 13:19:14.378671 RX Vref Scan: 1
3405 13:19:14.378739
3406 13:19:14.378792 Set Vref Range= 32 -> 127
3407 13:19:14.378842
3408 13:19:14.381882 RX Vref 32 -> 127, step: 1
3409 13:19:14.381959
3410 13:19:14.385566 RX Delay -21 -> 252, step: 4
3411 13:19:14.385643
3412 13:19:14.388555 Set Vref, RX VrefLevel [Byte0]: 32
3413 13:19:14.391977 [Byte1]: 32
3414 13:19:14.392083
3415 13:19:14.395403 Set Vref, RX VrefLevel [Byte0]: 33
3416 13:19:14.398607 [Byte1]: 33
3417 13:19:14.402727
3418 13:19:14.402807 Set Vref, RX VrefLevel [Byte0]: 34
3419 13:19:14.405532 [Byte1]: 34
3420 13:19:14.410348
3421 13:19:14.410438 Set Vref, RX VrefLevel [Byte0]: 35
3422 13:19:14.414057 [Byte1]: 35
3423 13:19:14.418698
3424 13:19:14.418793 Set Vref, RX VrefLevel [Byte0]: 36
3425 13:19:14.421793 [Byte1]: 36
3426 13:19:14.426244
3427 13:19:14.426325 Set Vref, RX VrefLevel [Byte0]: 37
3428 13:19:14.429387 [Byte1]: 37
3429 13:19:14.434221
3430 13:19:14.434332 Set Vref, RX VrefLevel [Byte0]: 38
3431 13:19:14.437885 [Byte1]: 38
3432 13:19:14.442034
3433 13:19:14.442119 Set Vref, RX VrefLevel [Byte0]: 39
3434 13:19:14.445204 [Byte1]: 39
3435 13:19:14.450224
3436 13:19:14.450322 Set Vref, RX VrefLevel [Byte0]: 40
3437 13:19:14.453233 [Byte1]: 40
3438 13:19:14.458230
3439 13:19:14.458332 Set Vref, RX VrefLevel [Byte0]: 41
3440 13:19:14.461280 [Byte1]: 41
3441 13:19:14.466267
3442 13:19:14.466355 Set Vref, RX VrefLevel [Byte0]: 42
3443 13:19:14.469438 [Byte1]: 42
3444 13:19:14.473667
3445 13:19:14.473754 Set Vref, RX VrefLevel [Byte0]: 43
3446 13:19:14.476891 [Byte1]: 43
3447 13:19:14.481810
3448 13:19:14.481927 Set Vref, RX VrefLevel [Byte0]: 44
3449 13:19:14.485036 [Byte1]: 44
3450 13:19:14.489482
3451 13:19:14.489563 Set Vref, RX VrefLevel [Byte0]: 45
3452 13:19:14.493211 [Byte1]: 45
3453 13:19:14.497546
3454 13:19:14.497630 Set Vref, RX VrefLevel [Byte0]: 46
3455 13:19:14.500864 [Byte1]: 46
3456 13:19:14.505290
3457 13:19:14.508997 Set Vref, RX VrefLevel [Byte0]: 47
3458 13:19:14.511884 [Byte1]: 47
3459 13:19:14.511984
3460 13:19:14.515346 Set Vref, RX VrefLevel [Byte0]: 48
3461 13:19:14.518772 [Byte1]: 48
3462 13:19:14.518852
3463 13:19:14.521620 Set Vref, RX VrefLevel [Byte0]: 49
3464 13:19:14.525186 [Byte1]: 49
3465 13:19:14.528950
3466 13:19:14.529029 Set Vref, RX VrefLevel [Byte0]: 50
3467 13:19:14.532707 [Byte1]: 50
3468 13:19:14.537169
3469 13:19:14.537257 Set Vref, RX VrefLevel [Byte0]: 51
3470 13:19:14.540174 [Byte1]: 51
3471 13:19:14.544806
3472 13:19:14.544889 Set Vref, RX VrefLevel [Byte0]: 52
3473 13:19:14.548477 [Byte1]: 52
3474 13:19:14.553141
3475 13:19:14.553232 Set Vref, RX VrefLevel [Byte0]: 53
3476 13:19:14.556158 [Byte1]: 53
3477 13:19:14.561274
3478 13:19:14.561369 Set Vref, RX VrefLevel [Byte0]: 54
3479 13:19:14.564260 [Byte1]: 54
3480 13:19:14.569053
3481 13:19:14.569142 Set Vref, RX VrefLevel [Byte0]: 55
3482 13:19:14.572242 [Byte1]: 55
3483 13:19:14.576593
3484 13:19:14.576679 Set Vref, RX VrefLevel [Byte0]: 56
3485 13:19:14.580405 [Byte1]: 56
3486 13:19:14.584567
3487 13:19:14.584653 Set Vref, RX VrefLevel [Byte0]: 57
3488 13:19:14.587738 [Byte1]: 57
3489 13:19:14.592705
3490 13:19:14.592793 Set Vref, RX VrefLevel [Byte0]: 58
3491 13:19:14.595795 [Byte1]: 58
3492 13:19:14.600318
3493 13:19:14.600428 Set Vref, RX VrefLevel [Byte0]: 59
3494 13:19:14.603880 [Byte1]: 59
3495 13:19:14.608564
3496 13:19:14.608668 Set Vref, RX VrefLevel [Byte0]: 60
3497 13:19:14.611620 [Byte1]: 60
3498 13:19:14.616062
3499 13:19:14.616195 Set Vref, RX VrefLevel [Byte0]: 61
3500 13:19:14.619686 [Byte1]: 61
3501 13:19:14.624554
3502 13:19:14.624640 Set Vref, RX VrefLevel [Byte0]: 62
3503 13:19:14.627461 [Byte1]: 62
3504 13:19:14.631981
3505 13:19:14.632068 Set Vref, RX VrefLevel [Byte0]: 63
3506 13:19:14.635356 [Byte1]: 63
3507 13:19:14.640434
3508 13:19:14.640565 Set Vref, RX VrefLevel [Byte0]: 64
3509 13:19:14.643587 [Byte1]: 64
3510 13:19:14.647954
3511 13:19:14.648049 Set Vref, RX VrefLevel [Byte0]: 65
3512 13:19:14.651592 [Byte1]: 65
3513 13:19:14.655870
3514 13:19:14.655987 Set Vref, RX VrefLevel [Byte0]: 66
3515 13:19:14.659090 [Byte1]: 66
3516 13:19:14.664021
3517 13:19:14.664112 Set Vref, RX VrefLevel [Byte0]: 67
3518 13:19:14.667081 [Byte1]: 67
3519 13:19:14.671802
3520 13:19:14.671919 Final RX Vref Byte 0 = 51 to rank0
3521 13:19:14.675401 Final RX Vref Byte 1 = 55 to rank0
3522 13:19:14.678432 Final RX Vref Byte 0 = 51 to rank1
3523 13:19:14.681641 Final RX Vref Byte 1 = 55 to rank1==
3524 13:19:14.684776 Dram Type= 6, Freq= 0, CH_1, rank 0
3525 13:19:14.691505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 13:19:14.691604 ==
3527 13:19:14.691684 DQS Delay:
3528 13:19:14.694757 DQS0 = 0, DQS1 = 0
3529 13:19:14.694829 DQM Delay:
3530 13:19:14.694885 DQM0 = 116, DQM1 = 110
3531 13:19:14.697928 DQ Delay:
3532 13:19:14.701164 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =114
3533 13:19:14.704411 DQ4 =114, DQ5 =128, DQ6 =124, DQ7 =112
3534 13:19:14.708156 DQ8 =98, DQ9 =104, DQ10 =112, DQ11 =100
3535 13:19:14.711176 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3536 13:19:14.711281
3537 13:19:14.711368
3538 13:19:14.720906 [DQSOSCAuto] RK0, (LSB)MR18= 0x6fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 407 ps
3539 13:19:14.721042 CH1 RK0: MR19=403, MR18=6FA
3540 13:19:14.728130 CH1_RK0: MR19=0x403, MR18=0x6FA, DQSOSC=407, MR23=63, INC=39, DEC=26
3541 13:19:14.728233
3542 13:19:14.731099 ----->DramcWriteLeveling(PI) begin...
3543 13:19:14.731212 ==
3544 13:19:14.734031 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 13:19:14.740480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 13:19:14.740602 ==
3547 13:19:14.743859 Write leveling (Byte 0): 25 => 25
3548 13:19:14.747462 Write leveling (Byte 1): 28 => 28
3549 13:19:14.747591 DramcWriteLeveling(PI) end<-----
3550 13:19:14.750733
3551 13:19:14.750830 ==
3552 13:19:14.753710 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 13:19:14.757249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 13:19:14.757367 ==
3555 13:19:14.760426 [Gating] SW mode calibration
3556 13:19:14.767251 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3557 13:19:14.770449 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3558 13:19:14.776961 0 15 0 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
3559 13:19:14.780513 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3560 13:19:14.783515 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3561 13:19:14.789946 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3562 13:19:14.793759 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3563 13:19:14.796761 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3564 13:19:14.803632 0 15 24 | B1->B0 | 2d2d 3434 | 0 0 | (0 1) (0 1)
3565 13:19:14.806794 0 15 28 | B1->B0 | 2525 2626 | 0 0 | (1 0) (0 0)
3566 13:19:14.810068 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3567 13:19:14.816299 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3568 13:19:14.820149 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3569 13:19:14.823286 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3570 13:19:14.830047 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3571 13:19:14.832852 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3572 13:19:14.836354 1 0 24 | B1->B0 | 3838 2a2a | 0 1 | (0 0) (0 0)
3573 13:19:14.843182 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3574 13:19:14.846143 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3575 13:19:14.849601 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3576 13:19:14.856070 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3577 13:19:14.859164 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3578 13:19:14.862646 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3579 13:19:14.869471 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3580 13:19:14.872491 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3581 13:19:14.875813 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3582 13:19:14.882416 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3583 13:19:14.885981 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3584 13:19:14.892273 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3585 13:19:14.895342 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3586 13:19:14.899152 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3587 13:19:14.902252 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3588 13:19:14.908538 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3589 13:19:14.911802 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3590 13:19:14.915601 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3591 13:19:14.922350 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3592 13:19:14.925469 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3593 13:19:14.928549 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3594 13:19:14.934916 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3595 13:19:14.938473 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3596 13:19:14.941991 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3597 13:19:14.948321 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3598 13:19:14.951530 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3599 13:19:14.955168 Total UI for P1: 0, mck2ui 16
3600 13:19:14.958033 best dqsien dly found for B0: ( 1, 3, 26)
3601 13:19:14.961584 Total UI for P1: 0, mck2ui 16
3602 13:19:14.964980 best dqsien dly found for B1: ( 1, 3, 26)
3603 13:19:14.968354 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3604 13:19:14.971301 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3605 13:19:14.971396
3606 13:19:14.974757 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3607 13:19:14.981038 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3608 13:19:14.981136 [Gating] SW calibration Done
3609 13:19:14.981196 ==
3610 13:19:14.984821 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 13:19:14.990933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 13:19:14.991035 ==
3613 13:19:14.991155 RX Vref Scan: 0
3614 13:19:14.991238
3615 13:19:14.994523 RX Vref 0 -> 0, step: 1
3616 13:19:14.994603
3617 13:19:14.997697 RX Delay -40 -> 252, step: 8
3618 13:19:15.000774 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3619 13:19:15.004668 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3620 13:19:15.007864 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3621 13:19:15.014195 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3622 13:19:15.017399 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3623 13:19:15.021078 iDelay=208, Bit 5, Center 123 (48 ~ 199) 152
3624 13:19:15.024010 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3625 13:19:15.027720 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3626 13:19:15.033938 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3627 13:19:15.037692 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3628 13:19:15.040833 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3629 13:19:15.043949 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3630 13:19:15.047323 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3631 13:19:15.054209 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3632 13:19:15.057197 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3633 13:19:15.060303 iDelay=208, Bit 15, Center 115 (40 ~ 191) 152
3634 13:19:15.060388 ==
3635 13:19:15.063946 Dram Type= 6, Freq= 0, CH_1, rank 1
3636 13:19:15.067023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3637 13:19:15.070653 ==
3638 13:19:15.070761 DQS Delay:
3639 13:19:15.070846 DQS0 = 0, DQS1 = 0
3640 13:19:15.073742 DQM Delay:
3641 13:19:15.073821 DQM0 = 116, DQM1 = 109
3642 13:19:15.076683 DQ Delay:
3643 13:19:15.080313 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3644 13:19:15.083587 DQ4 =115, DQ5 =123, DQ6 =131, DQ7 =115
3645 13:19:15.086492 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3646 13:19:15.090243 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115
3647 13:19:15.090349
3648 13:19:15.090436
3649 13:19:15.090517 ==
3650 13:19:15.093320 Dram Type= 6, Freq= 0, CH_1, rank 1
3651 13:19:15.096935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3652 13:19:15.099603 ==
3653 13:19:15.099706
3654 13:19:15.099793
3655 13:19:15.099878 TX Vref Scan disable
3656 13:19:15.102895 == TX Byte 0 ==
3657 13:19:15.106681 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3658 13:19:15.109632 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3659 13:19:15.113297 == TX Byte 1 ==
3660 13:19:15.116395 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3661 13:19:15.119521 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3662 13:19:15.122764 ==
3663 13:19:15.125945 Dram Type= 6, Freq= 0, CH_1, rank 1
3664 13:19:15.129574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3665 13:19:15.129674 ==
3666 13:19:15.140949 TX Vref=22, minBit 8, minWin=25, winSum=421
3667 13:19:15.144015 TX Vref=24, minBit 9, minWin=25, winSum=429
3668 13:19:15.147173 TX Vref=26, minBit 0, minWin=27, winSum=435
3669 13:19:15.150905 TX Vref=28, minBit 9, minWin=26, winSum=433
3670 13:19:15.153852 TX Vref=30, minBit 8, minWin=26, winSum=438
3671 13:19:15.160690 TX Vref=32, minBit 7, minWin=26, winSum=432
3672 13:19:15.163536 [TxChooseVref] Worse bit 0, Min win 27, Win sum 435, Final Vref 26
3673 13:19:15.163625
3674 13:19:15.167066 Final TX Range 1 Vref 26
3675 13:19:15.167164
3676 13:19:15.167224 ==
3677 13:19:15.170081 Dram Type= 6, Freq= 0, CH_1, rank 1
3678 13:19:15.173798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3679 13:19:15.176760 ==
3680 13:19:15.176844
3681 13:19:15.176904
3682 13:19:15.176958 TX Vref Scan disable
3683 13:19:15.180502 == TX Byte 0 ==
3684 13:19:15.183650 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3685 13:19:15.190476 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3686 13:19:15.190575 == TX Byte 1 ==
3687 13:19:15.193305 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3688 13:19:15.200041 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3689 13:19:15.200140
3690 13:19:15.200199 [DATLAT]
3691 13:19:15.200275 Freq=1200, CH1 RK1
3692 13:19:15.200330
3693 13:19:15.203136 DATLAT Default: 0xd
3694 13:19:15.206556 0, 0xFFFF, sum = 0
3695 13:19:15.206643 1, 0xFFFF, sum = 0
3696 13:19:15.210038 2, 0xFFFF, sum = 0
3697 13:19:15.210121 3, 0xFFFF, sum = 0
3698 13:19:15.213542 4, 0xFFFF, sum = 0
3699 13:19:15.213625 5, 0xFFFF, sum = 0
3700 13:19:15.216299 6, 0xFFFF, sum = 0
3701 13:19:15.216382 7, 0xFFFF, sum = 0
3702 13:19:15.220043 8, 0xFFFF, sum = 0
3703 13:19:15.220126 9, 0xFFFF, sum = 0
3704 13:19:15.223231 10, 0xFFFF, sum = 0
3705 13:19:15.223314 11, 0xFFFF, sum = 0
3706 13:19:15.226462 12, 0x0, sum = 1
3707 13:19:15.226546 13, 0x0, sum = 2
3708 13:19:15.229548 14, 0x0, sum = 3
3709 13:19:15.229628 15, 0x0, sum = 4
3710 13:19:15.232753 best_step = 13
3711 13:19:15.232832
3712 13:19:15.232891 ==
3713 13:19:15.236442 Dram Type= 6, Freq= 0, CH_1, rank 1
3714 13:19:15.239529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3715 13:19:15.239628 ==
3716 13:19:15.242641 RX Vref Scan: 0
3717 13:19:15.242721
3718 13:19:15.242780 RX Vref 0 -> 0, step: 1
3719 13:19:15.242834
3720 13:19:15.246488 RX Delay -21 -> 252, step: 4
3721 13:19:15.252780 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3722 13:19:15.256211 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3723 13:19:15.259312 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3724 13:19:15.262933 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3725 13:19:15.266077 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3726 13:19:15.272625 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3727 13:19:15.276076 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3728 13:19:15.279111 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3729 13:19:15.282706 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3730 13:19:15.285889 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3731 13:19:15.292164 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3732 13:19:15.295933 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3733 13:19:15.299081 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3734 13:19:15.302055 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3735 13:19:15.308926 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3736 13:19:15.311784 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3737 13:19:15.311891 ==
3738 13:19:15.315321 Dram Type= 6, Freq= 0, CH_1, rank 1
3739 13:19:15.318345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3740 13:19:15.318456 ==
3741 13:19:15.322049 DQS Delay:
3742 13:19:15.322133 DQS0 = 0, DQS1 = 0
3743 13:19:15.322192 DQM Delay:
3744 13:19:15.324966 DQM0 = 116, DQM1 = 110
3745 13:19:15.325045 DQ Delay:
3746 13:19:15.328674 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =112
3747 13:19:15.331843 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =116
3748 13:19:15.338703 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =100
3749 13:19:15.341932 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3750 13:19:15.342021
3751 13:19:15.342082
3752 13:19:15.348064 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1ec, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 416 ps
3753 13:19:15.351834 CH1 RK1: MR19=303, MR18=F1EC
3754 13:19:15.358055 CH1_RK1: MR19=0x303, MR18=0xF1EC, DQSOSC=416, MR23=63, INC=37, DEC=25
3755 13:19:15.361764 [RxdqsGatingPostProcess] freq 1200
3756 13:19:15.364920 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3757 13:19:15.368003 best DQS0 dly(2T, 0.5T) = (0, 11)
3758 13:19:15.371834 best DQS1 dly(2T, 0.5T) = (0, 11)
3759 13:19:15.374786 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3760 13:19:15.377823 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3761 13:19:15.381554 best DQS0 dly(2T, 0.5T) = (0, 11)
3762 13:19:15.384308 best DQS1 dly(2T, 0.5T) = (0, 11)
3763 13:19:15.387682 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3764 13:19:15.391243 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3765 13:19:15.394372 Pre-setting of DQS Precalculation
3766 13:19:15.401270 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3767 13:19:15.407602 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3768 13:19:15.414236 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3769 13:19:15.414340
3770 13:19:15.414399
3771 13:19:15.417667 [Calibration Summary] 2400 Mbps
3772 13:19:15.417757 CH 0, Rank 0
3773 13:19:15.421288 SW Impedance : PASS
3774 13:19:15.424309 DUTY Scan : NO K
3775 13:19:15.424392 ZQ Calibration : PASS
3776 13:19:15.427323 Jitter Meter : NO K
3777 13:19:15.427448 CBT Training : PASS
3778 13:19:15.430620 Write leveling : PASS
3779 13:19:15.434074 RX DQS gating : PASS
3780 13:19:15.434163 RX DQ/DQS(RDDQC) : PASS
3781 13:19:15.437579 TX DQ/DQS : PASS
3782 13:19:15.441017 RX DATLAT : PASS
3783 13:19:15.441104 RX DQ/DQS(Engine): PASS
3784 13:19:15.444009 TX OE : NO K
3785 13:19:15.444089 All Pass.
3786 13:19:15.444147
3787 13:19:15.447137 CH 0, Rank 1
3788 13:19:15.447214 SW Impedance : PASS
3789 13:19:15.450979 DUTY Scan : NO K
3790 13:19:15.454129 ZQ Calibration : PASS
3791 13:19:15.454219 Jitter Meter : NO K
3792 13:19:15.457290 CBT Training : PASS
3793 13:19:15.460402 Write leveling : PASS
3794 13:19:15.460483 RX DQS gating : PASS
3795 13:19:15.463579 RX DQ/DQS(RDDQC) : PASS
3796 13:19:15.467319 TX DQ/DQS : PASS
3797 13:19:15.467424 RX DATLAT : PASS
3798 13:19:15.470431 RX DQ/DQS(Engine): PASS
3799 13:19:15.473548 TX OE : NO K
3800 13:19:15.473629 All Pass.
3801 13:19:15.473687
3802 13:19:15.473753 CH 1, Rank 0
3803 13:19:15.477219 SW Impedance : PASS
3804 13:19:15.480402 DUTY Scan : NO K
3805 13:19:15.480483 ZQ Calibration : PASS
3806 13:19:15.483684 Jitter Meter : NO K
3807 13:19:15.486747 CBT Training : PASS
3808 13:19:15.486827 Write leveling : PASS
3809 13:19:15.490492 RX DQS gating : PASS
3810 13:19:15.493557 RX DQ/DQS(RDDQC) : PASS
3811 13:19:15.493637 TX DQ/DQS : PASS
3812 13:19:15.496920 RX DATLAT : PASS
3813 13:19:15.497001 RX DQ/DQS(Engine): PASS
3814 13:19:15.500276 TX OE : NO K
3815 13:19:15.500356 All Pass.
3816 13:19:15.500415
3817 13:19:15.503448 CH 1, Rank 1
3818 13:19:15.503537 SW Impedance : PASS
3819 13:19:15.506587 DUTY Scan : NO K
3820 13:19:15.510281 ZQ Calibration : PASS
3821 13:19:15.510357 Jitter Meter : NO K
3822 13:19:15.513505 CBT Training : PASS
3823 13:19:15.516642 Write leveling : PASS
3824 13:19:15.516742 RX DQS gating : PASS
3825 13:19:15.520423 RX DQ/DQS(RDDQC) : PASS
3826 13:19:15.523580 TX DQ/DQS : PASS
3827 13:19:15.523700 RX DATLAT : PASS
3828 13:19:15.526798 RX DQ/DQS(Engine): PASS
3829 13:19:15.529794 TX OE : NO K
3830 13:19:15.529874 All Pass.
3831 13:19:15.529932
3832 13:19:15.533273 DramC Write-DBI off
3833 13:19:15.533351 PER_BANK_REFRESH: Hybrid Mode
3834 13:19:15.536718 TX_TRACKING: ON
3835 13:19:15.546280 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3836 13:19:15.549903 [FAST_K] Save calibration result to emmc
3837 13:19:15.552758 dramc_set_vcore_voltage set vcore to 650000
3838 13:19:15.552841 Read voltage for 600, 5
3839 13:19:15.556124 Vio18 = 0
3840 13:19:15.556204 Vcore = 650000
3841 13:19:15.556261 Vdram = 0
3842 13:19:15.559339 Vddq = 0
3843 13:19:15.559474 Vmddr = 0
3844 13:19:15.563182 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3845 13:19:15.569354 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3846 13:19:15.572501 MEM_TYPE=3, freq_sel=19
3847 13:19:15.576183 sv_algorithm_assistance_LP4_1600
3848 13:19:15.579386 ============ PULL DRAM RESETB DOWN ============
3849 13:19:15.582452 ========== PULL DRAM RESETB DOWN end =========
3850 13:19:15.589176 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3851 13:19:15.593090 ===================================
3852 13:19:15.593178 LPDDR4 DRAM CONFIGURATION
3853 13:19:15.596068 ===================================
3854 13:19:15.599291 EX_ROW_EN[0] = 0x0
3855 13:19:15.599394 EX_ROW_EN[1] = 0x0
3856 13:19:15.602322 LP4Y_EN = 0x0
3857 13:19:15.605744 WORK_FSP = 0x0
3858 13:19:15.605823 WL = 0x2
3859 13:19:15.609105 RL = 0x2
3860 13:19:15.609190 BL = 0x2
3861 13:19:15.612211 RPST = 0x0
3862 13:19:15.612289 RD_PRE = 0x0
3863 13:19:15.615399 WR_PRE = 0x1
3864 13:19:15.615511 WR_PST = 0x0
3865 13:19:15.619409 DBI_WR = 0x0
3866 13:19:15.619531 DBI_RD = 0x0
3867 13:19:15.622606 OTF = 0x1
3868 13:19:15.625697 ===================================
3869 13:19:15.628793 ===================================
3870 13:19:15.628873 ANA top config
3871 13:19:15.632513 ===================================
3872 13:19:15.635692 DLL_ASYNC_EN = 0
3873 13:19:15.638635 ALL_SLAVE_EN = 1
3874 13:19:15.642311 NEW_RANK_MODE = 1
3875 13:19:15.642385 DLL_IDLE_MODE = 1
3876 13:19:15.645419 LP45_APHY_COMB_EN = 1
3877 13:19:15.648519 TX_ODT_DIS = 1
3878 13:19:15.651674 NEW_8X_MODE = 1
3879 13:19:15.655458 ===================================
3880 13:19:15.658329 ===================================
3881 13:19:15.661823 data_rate = 1200
3882 13:19:15.661905 CKR = 1
3883 13:19:15.665375 DQ_P2S_RATIO = 8
3884 13:19:15.668164 ===================================
3885 13:19:15.671342 CA_P2S_RATIO = 8
3886 13:19:15.675017 DQ_CA_OPEN = 0
3887 13:19:15.677970 DQ_SEMI_OPEN = 0
3888 13:19:15.681276 CA_SEMI_OPEN = 0
3889 13:19:15.681383 CA_FULL_RATE = 0
3890 13:19:15.685000 DQ_CKDIV4_EN = 1
3891 13:19:15.688415 CA_CKDIV4_EN = 1
3892 13:19:15.691529 CA_PREDIV_EN = 0
3893 13:19:15.694622 PH8_DLY = 0
3894 13:19:15.697750 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3895 13:19:15.697821 DQ_AAMCK_DIV = 4
3896 13:19:15.700948 CA_AAMCK_DIV = 4
3897 13:19:15.704785 CA_ADMCK_DIV = 4
3898 13:19:15.707982 DQ_TRACK_CA_EN = 0
3899 13:19:15.710947 CA_PICK = 600
3900 13:19:15.714433 CA_MCKIO = 600
3901 13:19:15.717887 MCKIO_SEMI = 0
3902 13:19:15.721387 PLL_FREQ = 2288
3903 13:19:15.721478 DQ_UI_PI_RATIO = 32
3904 13:19:15.724532 CA_UI_PI_RATIO = 0
3905 13:19:15.727576 ===================================
3906 13:19:15.730597 ===================================
3907 13:19:15.734351 memory_type:LPDDR4
3908 13:19:15.737543 GP_NUM : 10
3909 13:19:15.737630 SRAM_EN : 1
3910 13:19:15.740596 MD32_EN : 0
3911 13:19:15.744240 ===================================
3912 13:19:15.747375 [ANA_INIT] >>>>>>>>>>>>>>
3913 13:19:15.747502 <<<<<< [CONFIGURE PHASE]: ANA_TX
3914 13:19:15.750793 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3915 13:19:15.754019 ===================================
3916 13:19:15.757085 data_rate = 1200,PCW = 0X5800
3917 13:19:15.760231 ===================================
3918 13:19:15.763998 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3919 13:19:15.770090 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3920 13:19:15.777129 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3921 13:19:15.780164 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3922 13:19:15.783265 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3923 13:19:15.786529 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3924 13:19:15.789998 [ANA_INIT] flow start
3925 13:19:15.793198 [ANA_INIT] PLL >>>>>>>>
3926 13:19:15.793322 [ANA_INIT] PLL <<<<<<<<
3927 13:19:15.796463 [ANA_INIT] MIDPI >>>>>>>>
3928 13:19:15.799769 [ANA_INIT] MIDPI <<<<<<<<
3929 13:19:15.799860 [ANA_INIT] DLL >>>>>>>>
3930 13:19:15.803291 [ANA_INIT] flow end
3931 13:19:15.806457 ============ LP4 DIFF to SE enter ============
3932 13:19:15.809672 ============ LP4 DIFF to SE exit ============
3933 13:19:15.812983 [ANA_INIT] <<<<<<<<<<<<<
3934 13:19:15.816712 [Flow] Enable top DCM control >>>>>
3935 13:19:15.819678 [Flow] Enable top DCM control <<<<<
3936 13:19:15.823283 Enable DLL master slave shuffle
3937 13:19:15.829658 ==============================================================
3938 13:19:15.829860 Gating Mode config
3939 13:19:15.836435 ==============================================================
3940 13:19:15.836546 Config description:
3941 13:19:15.846481 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3942 13:19:15.852743 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3943 13:19:15.859402 SELPH_MODE 0: By rank 1: By Phase
3944 13:19:15.862575 ==============================================================
3945 13:19:15.866551 GAT_TRACK_EN = 1
3946 13:19:15.869597 RX_GATING_MODE = 2
3947 13:19:15.872660 RX_GATING_TRACK_MODE = 2
3948 13:19:15.876478 SELPH_MODE = 1
3949 13:19:15.879646 PICG_EARLY_EN = 1
3950 13:19:15.882761 VALID_LAT_VALUE = 1
3951 13:19:15.889210 ==============================================================
3952 13:19:15.893097 Enter into Gating configuration >>>>
3953 13:19:15.896224 Exit from Gating configuration <<<<
3954 13:19:15.896306 Enter into DVFS_PRE_config >>>>>
3955 13:19:15.909127 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3956 13:19:15.912416 Exit from DVFS_PRE_config <<<<<
3957 13:19:15.915721 Enter into PICG configuration >>>>
3958 13:19:15.919011 Exit from PICG configuration <<<<
3959 13:19:15.922132 [RX_INPUT] configuration >>>>>
3960 13:19:15.922216 [RX_INPUT] configuration <<<<<
3961 13:19:15.928895 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3962 13:19:15.935389 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3963 13:19:15.938967 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3964 13:19:15.945245 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3965 13:19:15.952286 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3966 13:19:15.958398 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3967 13:19:15.962000 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3968 13:19:15.965043 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3969 13:19:15.971967 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3970 13:19:15.975011 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3971 13:19:15.978135 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3972 13:19:15.985080 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3973 13:19:15.988146 ===================================
3974 13:19:15.988229 LPDDR4 DRAM CONFIGURATION
3975 13:19:15.991359 ===================================
3976 13:19:15.994519 EX_ROW_EN[0] = 0x0
3977 13:19:15.998347 EX_ROW_EN[1] = 0x0
3978 13:19:15.998429 LP4Y_EN = 0x0
3979 13:19:16.001467 WORK_FSP = 0x0
3980 13:19:16.001544 WL = 0x2
3981 13:19:16.004663 RL = 0x2
3982 13:19:16.004749 BL = 0x2
3983 13:19:16.007756 RPST = 0x0
3984 13:19:16.007833 RD_PRE = 0x0
3985 13:19:16.010965 WR_PRE = 0x1
3986 13:19:16.011053 WR_PST = 0x0
3987 13:19:16.014771 DBI_WR = 0x0
3988 13:19:16.014849 DBI_RD = 0x0
3989 13:19:16.017853 OTF = 0x1
3990 13:19:16.020778 ===================================
3991 13:19:16.024092 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3992 13:19:16.027627 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3993 13:19:16.034254 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3994 13:19:16.037590 ===================================
3995 13:19:16.037680 LPDDR4 DRAM CONFIGURATION
3996 13:19:16.041117 ===================================
3997 13:19:16.044282 EX_ROW_EN[0] = 0x10
3998 13:19:16.047367 EX_ROW_EN[1] = 0x0
3999 13:19:16.047501 LP4Y_EN = 0x0
4000 13:19:16.050695 WORK_FSP = 0x0
4001 13:19:16.050775 WL = 0x2
4002 13:19:16.054022 RL = 0x2
4003 13:19:16.054103 BL = 0x2
4004 13:19:16.057538 RPST = 0x0
4005 13:19:16.057633 RD_PRE = 0x0
4006 13:19:16.060679 WR_PRE = 0x1
4007 13:19:16.060751 WR_PST = 0x0
4008 13:19:16.063833 DBI_WR = 0x0
4009 13:19:16.063910 DBI_RD = 0x0
4010 13:19:16.067355 OTF = 0x1
4011 13:19:16.070345 ===================================
4012 13:19:16.077235 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4013 13:19:16.080215 nWR fixed to 30
4014 13:19:16.083381 [ModeRegInit_LP4] CH0 RK0
4015 13:19:16.083514 [ModeRegInit_LP4] CH0 RK1
4016 13:19:16.087168 [ModeRegInit_LP4] CH1 RK0
4017 13:19:16.090191 [ModeRegInit_LP4] CH1 RK1
4018 13:19:16.090290 match AC timing 17
4019 13:19:16.096595 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4020 13:19:16.099786 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4021 13:19:16.103592 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4022 13:19:16.110024 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4023 13:19:16.113159 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4024 13:19:16.113247 ==
4025 13:19:16.116261 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 13:19:16.120031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 13:19:16.120110 ==
4028 13:19:16.126412 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4029 13:19:16.133138 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4030 13:19:16.136214 [CA 0] Center 36 (6~66) winsize 61
4031 13:19:16.139709 [CA 1] Center 36 (6~66) winsize 61
4032 13:19:16.142631 [CA 2] Center 34 (4~65) winsize 62
4033 13:19:16.146101 [CA 3] Center 34 (4~65) winsize 62
4034 13:19:16.149560 [CA 4] Center 33 (3~64) winsize 62
4035 13:19:16.153017 [CA 5] Center 33 (3~64) winsize 62
4036 13:19:16.153135
4037 13:19:16.155967 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4038 13:19:16.156044
4039 13:19:16.159382 [CATrainingPosCal] consider 1 rank data
4040 13:19:16.162698 u2DelayCellTimex100 = 270/100 ps
4041 13:19:16.166070 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4042 13:19:16.169312 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4043 13:19:16.172636 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4044 13:19:16.179370 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4045 13:19:16.182403 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4046 13:19:16.186069 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4047 13:19:16.186154
4048 13:19:16.189141 CA PerBit enable=1, Macro0, CA PI delay=33
4049 13:19:16.189218
4050 13:19:16.192221 [CBTSetCACLKResult] CA Dly = 33
4051 13:19:16.192297 CS Dly: 4 (0~35)
4052 13:19:16.192356 ==
4053 13:19:16.196060 Dram Type= 6, Freq= 0, CH_0, rank 1
4054 13:19:16.202340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 13:19:16.202434 ==
4056 13:19:16.206014 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4057 13:19:16.212242 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4058 13:19:16.215357 [CA 0] Center 36 (6~66) winsize 61
4059 13:19:16.219181 [CA 1] Center 36 (6~66) winsize 61
4060 13:19:16.222318 [CA 2] Center 34 (3~65) winsize 63
4061 13:19:16.225465 [CA 3] Center 33 (3~64) winsize 62
4062 13:19:16.229243 [CA 4] Center 33 (3~64) winsize 62
4063 13:19:16.232373 [CA 5] Center 33 (2~64) winsize 63
4064 13:19:16.232452
4065 13:19:16.235410 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4066 13:19:16.235523
4067 13:19:16.239174 [CATrainingPosCal] consider 2 rank data
4068 13:19:16.242131 u2DelayCellTimex100 = 270/100 ps
4069 13:19:16.245793 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4070 13:19:16.251812 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4071 13:19:16.255286 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4072 13:19:16.258977 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4073 13:19:16.262046 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4074 13:19:16.265059 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4075 13:19:16.265131
4076 13:19:16.268839 CA PerBit enable=1, Macro0, CA PI delay=33
4077 13:19:16.268904
4078 13:19:16.271889 [CBTSetCACLKResult] CA Dly = 33
4079 13:19:16.274987 CS Dly: 5 (0~38)
4080 13:19:16.275056
4081 13:19:16.278256 ----->DramcWriteLeveling(PI) begin...
4082 13:19:16.278358 ==
4083 13:19:16.281502 Dram Type= 6, Freq= 0, CH_0, rank 0
4084 13:19:16.285060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4085 13:19:16.285146 ==
4086 13:19:16.288386 Write leveling (Byte 0): 33 => 33
4087 13:19:16.291575 Write leveling (Byte 1): 32 => 32
4088 13:19:16.294537 DramcWriteLeveling(PI) end<-----
4089 13:19:16.294616
4090 13:19:16.294676 ==
4091 13:19:16.298043 Dram Type= 6, Freq= 0, CH_0, rank 0
4092 13:19:16.301445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4093 13:19:16.301528 ==
4094 13:19:16.304537 [Gating] SW mode calibration
4095 13:19:16.311389 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4096 13:19:16.318268 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4097 13:19:16.321450 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4098 13:19:16.324678 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4099 13:19:16.330977 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4100 13:19:16.334793 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4101 13:19:16.337973 0 9 16 | B1->B0 | 3232 2a2a | 0 0 | (1 1) (1 1)
4102 13:19:16.344094 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4103 13:19:16.347787 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4104 13:19:16.350968 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4105 13:19:16.357624 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4106 13:19:16.361091 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4107 13:19:16.363988 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4108 13:19:16.370701 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4109 13:19:16.374220 0 10 16 | B1->B0 | 3535 4040 | 0 0 | (0 0) (0 0)
4110 13:19:16.377217 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4111 13:19:16.384168 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4112 13:19:16.387289 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4113 13:19:16.390439 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4114 13:19:16.397239 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4115 13:19:16.400291 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4116 13:19:16.403682 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4117 13:19:16.410074 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4118 13:19:16.413657 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4119 13:19:16.416789 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4120 13:19:16.423408 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4121 13:19:16.426564 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4122 13:19:16.429784 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4123 13:19:16.436721 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4124 13:19:16.439818 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4125 13:19:16.442986 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4126 13:19:16.450309 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4127 13:19:16.453377 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4128 13:19:16.456533 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4129 13:19:16.463258 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4130 13:19:16.466791 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4131 13:19:16.469760 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4132 13:19:16.476412 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4133 13:19:16.479552 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4134 13:19:16.483162 Total UI for P1: 0, mck2ui 16
4135 13:19:16.486462 best dqsien dly found for B0: ( 0, 13, 12)
4136 13:19:16.489513 Total UI for P1: 0, mck2ui 16
4137 13:19:16.492703 best dqsien dly found for B1: ( 0, 13, 14)
4138 13:19:16.496537 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4139 13:19:16.499681 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4140 13:19:16.499761
4141 13:19:16.502822 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4142 13:19:16.506042 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4143 13:19:16.509714 [Gating] SW calibration Done
4144 13:19:16.509792 ==
4145 13:19:16.512926 Dram Type= 6, Freq= 0, CH_0, rank 0
4146 13:19:16.519512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 13:19:16.519621 ==
4148 13:19:16.519681 RX Vref Scan: 0
4149 13:19:16.519736
4150 13:19:16.522772 RX Vref 0 -> 0, step: 1
4151 13:19:16.522834
4152 13:19:16.526033 RX Delay -230 -> 252, step: 16
4153 13:19:16.529345 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4154 13:19:16.532590 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4155 13:19:16.535888 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4156 13:19:16.542656 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4157 13:19:16.545916 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4158 13:19:16.548926 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4159 13:19:16.552083 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4160 13:19:16.558968 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4161 13:19:16.562092 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4162 13:19:16.565765 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4163 13:19:16.568933 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4164 13:19:16.575361 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4165 13:19:16.578399 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4166 13:19:16.581811 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4167 13:19:16.585378 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4168 13:19:16.591608 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4169 13:19:16.591713 ==
4170 13:19:16.594956 Dram Type= 6, Freq= 0, CH_0, rank 0
4171 13:19:16.598136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4172 13:19:16.598233 ==
4173 13:19:16.598308 DQS Delay:
4174 13:19:16.601834 DQS0 = 0, DQS1 = 0
4175 13:19:16.601934 DQM Delay:
4176 13:19:16.604954 DQM0 = 46, DQM1 = 33
4177 13:19:16.605036 DQ Delay:
4178 13:19:16.608165 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4179 13:19:16.611341 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =57
4180 13:19:16.615092 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4181 13:19:16.618257 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4182 13:19:16.618341
4183 13:19:16.618399
4184 13:19:16.618453 ==
4185 13:19:16.621266 Dram Type= 6, Freq= 0, CH_0, rank 0
4186 13:19:16.624515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 13:19:16.624588 ==
4188 13:19:16.624641
4189 13:19:16.628194
4190 13:19:16.628262 TX Vref Scan disable
4191 13:19:16.631331 == TX Byte 0 ==
4192 13:19:16.634989 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4193 13:19:16.637954 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4194 13:19:16.641343 == TX Byte 1 ==
4195 13:19:16.644585 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4196 13:19:16.647730 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4197 13:19:16.647810 ==
4198 13:19:16.651259 Dram Type= 6, Freq= 0, CH_0, rank 0
4199 13:19:16.657940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 13:19:16.658031 ==
4201 13:19:16.658095
4202 13:19:16.658163
4203 13:19:16.661105 TX Vref Scan disable
4204 13:19:16.661192 == TX Byte 0 ==
4205 13:19:16.668042 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4206 13:19:16.671108 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4207 13:19:16.671186 == TX Byte 1 ==
4208 13:19:16.678018 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4209 13:19:16.681162 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4210 13:19:16.681249
4211 13:19:16.681308 [DATLAT]
4212 13:19:16.684270 Freq=600, CH0 RK0
4213 13:19:16.684340
4214 13:19:16.684394 DATLAT Default: 0x9
4215 13:19:16.687754 0, 0xFFFF, sum = 0
4216 13:19:16.687826 1, 0xFFFF, sum = 0
4217 13:19:16.690684 2, 0xFFFF, sum = 0
4218 13:19:16.690756 3, 0xFFFF, sum = 0
4219 13:19:16.694271 4, 0xFFFF, sum = 0
4220 13:19:16.694341 5, 0xFFFF, sum = 0
4221 13:19:16.697643 6, 0xFFFF, sum = 0
4222 13:19:16.700968 7, 0xFFFF, sum = 0
4223 13:19:16.701050 8, 0x0, sum = 1
4224 13:19:16.701109 9, 0x0, sum = 2
4225 13:19:16.704144 10, 0x0, sum = 3
4226 13:19:16.704215 11, 0x0, sum = 4
4227 13:19:16.707244 best_step = 9
4228 13:19:16.707311
4229 13:19:16.707370 ==
4230 13:19:16.711065 Dram Type= 6, Freq= 0, CH_0, rank 0
4231 13:19:16.714196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 13:19:16.714268 ==
4233 13:19:16.717350 RX Vref Scan: 1
4234 13:19:16.717423
4235 13:19:16.717478 RX Vref 0 -> 0, step: 1
4236 13:19:16.717530
4237 13:19:16.720474 RX Delay -195 -> 252, step: 8
4238 13:19:16.720541
4239 13:19:16.723606 Set Vref, RX VrefLevel [Byte0]: 61
4240 13:19:16.726797 [Byte1]: 49
4241 13:19:16.731031
4242 13:19:16.731107 Final RX Vref Byte 0 = 61 to rank0
4243 13:19:16.734742 Final RX Vref Byte 1 = 49 to rank0
4244 13:19:16.737982 Final RX Vref Byte 0 = 61 to rank1
4245 13:19:16.740952 Final RX Vref Byte 1 = 49 to rank1==
4246 13:19:16.744591 Dram Type= 6, Freq= 0, CH_0, rank 0
4247 13:19:16.751374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 13:19:16.751526 ==
4249 13:19:16.751588 DQS Delay:
4250 13:19:16.754243 DQS0 = 0, DQS1 = 0
4251 13:19:16.754338 DQM Delay:
4252 13:19:16.754428 DQM0 = 43, DQM1 = 32
4253 13:19:16.757458 DQ Delay:
4254 13:19:16.761017 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4255 13:19:16.764489 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4256 13:19:16.767225 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4257 13:19:16.770638 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4258 13:19:16.770717
4259 13:19:16.770776
4260 13:19:16.777306 [DQSOSCAuto] RK0, (LSB)MR18= 0x643c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
4261 13:19:16.780501 CH0 RK0: MR19=808, MR18=643C
4262 13:19:16.787288 CH0_RK0: MR19=0x808, MR18=0x643C, DQSOSC=391, MR23=63, INC=171, DEC=114
4263 13:19:16.787402
4264 13:19:16.790422 ----->DramcWriteLeveling(PI) begin...
4265 13:19:16.790502 ==
4266 13:19:16.794157 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 13:19:16.797135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 13:19:16.797221 ==
4269 13:19:16.800711 Write leveling (Byte 0): 33 => 33
4270 13:19:16.803761 Write leveling (Byte 1): 29 => 29
4271 13:19:16.807208 DramcWriteLeveling(PI) end<-----
4272 13:19:16.807304
4273 13:19:16.807365 ==
4274 13:19:16.810350 Dram Type= 6, Freq= 0, CH_0, rank 1
4275 13:19:16.814051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4276 13:19:16.817189 ==
4277 13:19:16.817293 [Gating] SW mode calibration
4278 13:19:16.827218 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4279 13:19:16.830421 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4280 13:19:16.833580 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4281 13:19:16.840254 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4282 13:19:16.843319 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4283 13:19:16.847093 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
4284 13:19:16.853450 0 9 16 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
4285 13:19:16.856573 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4286 13:19:16.860242 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4287 13:19:16.866582 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4288 13:19:16.869545 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4289 13:19:16.873117 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4290 13:19:16.879324 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4291 13:19:16.883055 0 10 12 | B1->B0 | 2929 2929 | 0 0 | (0 0) (0 0)
4292 13:19:16.886345 0 10 16 | B1->B0 | 3a3a 4444 | 0 1 | (1 1) (0 0)
4293 13:19:16.893095 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4294 13:19:16.896169 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4295 13:19:16.899209 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4296 13:19:16.905928 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4297 13:19:16.909560 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4298 13:19:16.912469 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4299 13:19:16.919324 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4300 13:19:16.922410 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4301 13:19:16.926166 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 13:19:16.932536 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 13:19:16.935780 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 13:19:16.939474 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 13:19:16.946219 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 13:19:16.949317 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 13:19:16.952322 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 13:19:16.959252 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 13:19:16.962524 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 13:19:16.965522 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 13:19:16.972095 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 13:19:16.975524 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 13:19:16.978561 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 13:19:16.985479 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 13:19:16.988470 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4316 13:19:16.991913 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4317 13:19:16.994788 Total UI for P1: 0, mck2ui 16
4318 13:19:16.998165 best dqsien dly found for B0: ( 0, 13, 12)
4319 13:19:17.001481 Total UI for P1: 0, mck2ui 16
4320 13:19:17.004972 best dqsien dly found for B1: ( 0, 13, 12)
4321 13:19:17.008466 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4322 13:19:17.014636 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4323 13:19:17.014736
4324 13:19:17.017772 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4325 13:19:17.021158 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4326 13:19:17.024802 [Gating] SW calibration Done
4327 13:19:17.024887 ==
4328 13:19:17.027869 Dram Type= 6, Freq= 0, CH_0, rank 1
4329 13:19:17.031159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 13:19:17.031232 ==
4331 13:19:17.034341 RX Vref Scan: 0
4332 13:19:17.034408
4333 13:19:17.034462 RX Vref 0 -> 0, step: 1
4334 13:19:17.034514
4335 13:19:17.038036 RX Delay -230 -> 252, step: 16
4336 13:19:17.041210 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4337 13:19:17.048144 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4338 13:19:17.051116 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4339 13:19:17.054252 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4340 13:19:17.057431 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4341 13:19:17.064381 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4342 13:19:17.067373 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4343 13:19:17.070529 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4344 13:19:17.074250 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4345 13:19:17.077304 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4346 13:19:17.084141 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4347 13:19:17.087103 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4348 13:19:17.090895 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4349 13:19:17.093923 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4350 13:19:17.100175 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4351 13:19:17.103775 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4352 13:19:17.103867 ==
4353 13:19:17.106819 Dram Type= 6, Freq= 0, CH_0, rank 1
4354 13:19:17.109936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 13:19:17.110037 ==
4356 13:19:17.113810 DQS Delay:
4357 13:19:17.113896 DQS0 = 0, DQS1 = 0
4358 13:19:17.116850 DQM Delay:
4359 13:19:17.116957 DQM0 = 42, DQM1 = 35
4360 13:19:17.117049 DQ Delay:
4361 13:19:17.120521 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4362 13:19:17.123568 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4363 13:19:17.127019 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4364 13:19:17.129883 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4365 13:19:17.129991
4366 13:19:17.130078
4367 13:19:17.133471 ==
4368 13:19:17.136561 Dram Type= 6, Freq= 0, CH_0, rank 1
4369 13:19:17.139721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 13:19:17.139809 ==
4371 13:19:17.139869
4372 13:19:17.139923
4373 13:19:17.143474 TX Vref Scan disable
4374 13:19:17.143583 == TX Byte 0 ==
4375 13:19:17.149598 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4376 13:19:17.153297 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4377 13:19:17.153393 == TX Byte 1 ==
4378 13:19:17.159371 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4379 13:19:17.163209 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4380 13:19:17.163327 ==
4381 13:19:17.166349 Dram Type= 6, Freq= 0, CH_0, rank 1
4382 13:19:17.169506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 13:19:17.169607 ==
4384 13:19:17.169692
4385 13:19:17.169775
4386 13:19:17.172614 TX Vref Scan disable
4387 13:19:17.176381 == TX Byte 0 ==
4388 13:19:17.179576 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4389 13:19:17.185771 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4390 13:19:17.185900 == TX Byte 1 ==
4391 13:19:17.189243 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4392 13:19:17.195942 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4393 13:19:17.196066
4394 13:19:17.196156 [DATLAT]
4395 13:19:17.196243 Freq=600, CH0 RK1
4396 13:19:17.196324
4397 13:19:17.198855 DATLAT Default: 0x9
4398 13:19:17.202432 0, 0xFFFF, sum = 0
4399 13:19:17.202543 1, 0xFFFF, sum = 0
4400 13:19:17.205645 2, 0xFFFF, sum = 0
4401 13:19:17.205748 3, 0xFFFF, sum = 0
4402 13:19:17.209321 4, 0xFFFF, sum = 0
4403 13:19:17.209420 5, 0xFFFF, sum = 0
4404 13:19:17.212290 6, 0xFFFF, sum = 0
4405 13:19:17.212370 7, 0xFFFF, sum = 0
4406 13:19:17.215519 8, 0x0, sum = 1
4407 13:19:17.215601 9, 0x0, sum = 2
4408 13:19:17.219039 10, 0x0, sum = 3
4409 13:19:17.219125 11, 0x0, sum = 4
4410 13:19:17.219185 best_step = 9
4411 13:19:17.219240
4412 13:19:17.222173 ==
4413 13:19:17.225599 Dram Type= 6, Freq= 0, CH_0, rank 1
4414 13:19:17.228637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 13:19:17.228745 ==
4416 13:19:17.228834 RX Vref Scan: 0
4417 13:19:17.228919
4418 13:19:17.231711 RX Vref 0 -> 0, step: 1
4419 13:19:17.231807
4420 13:19:17.235356 RX Delay -195 -> 252, step: 8
4421 13:19:17.242142 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4422 13:19:17.245333 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4423 13:19:17.248564 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4424 13:19:17.251789 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4425 13:19:17.258642 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4426 13:19:17.261578 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4427 13:19:17.265289 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4428 13:19:17.268504 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4429 13:19:17.271766 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4430 13:19:17.278224 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4431 13:19:17.281348 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4432 13:19:17.284490 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4433 13:19:17.288293 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4434 13:19:17.294603 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4435 13:19:17.297765 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4436 13:19:17.301354 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4437 13:19:17.301437 ==
4438 13:19:17.304617 Dram Type= 6, Freq= 0, CH_0, rank 1
4439 13:19:17.311286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4440 13:19:17.311389 ==
4441 13:19:17.311492 DQS Delay:
4442 13:19:17.311549 DQS0 = 0, DQS1 = 0
4443 13:19:17.314601 DQM Delay:
4444 13:19:17.314710 DQM0 = 40, DQM1 = 36
4445 13:19:17.317979 DQ Delay:
4446 13:19:17.320871 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =40
4447 13:19:17.324404 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4448 13:19:17.327337 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4449 13:19:17.331014 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4450 13:19:17.331116
4451 13:19:17.331202
4452 13:19:17.337530 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e12, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
4453 13:19:17.340652 CH0 RK1: MR19=808, MR18=5E12
4454 13:19:17.347643 CH0_RK1: MR19=0x808, MR18=0x5E12, DQSOSC=392, MR23=63, INC=170, DEC=113
4455 13:19:17.350920 [RxdqsGatingPostProcess] freq 600
4456 13:19:17.353963 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4457 13:19:17.357100 Pre-setting of DQS Precalculation
4458 13:19:17.363908 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4459 13:19:17.364033 ==
4460 13:19:17.366904 Dram Type= 6, Freq= 0, CH_1, rank 0
4461 13:19:17.370543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 13:19:17.370645 ==
4463 13:19:17.377022 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4464 13:19:17.383556 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4465 13:19:17.387348 [CA 0] Center 35 (5~66) winsize 62
4466 13:19:17.390487 [CA 1] Center 36 (6~66) winsize 61
4467 13:19:17.393628 [CA 2] Center 34 (4~65) winsize 62
4468 13:19:17.396713 [CA 3] Center 33 (3~64) winsize 62
4469 13:19:17.399838 [CA 4] Center 34 (4~65) winsize 62
4470 13:19:17.403118 [CA 5] Center 33 (3~64) winsize 62
4471 13:19:17.403214
4472 13:19:17.406813 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4473 13:19:17.406924
4474 13:19:17.409930 [CATrainingPosCal] consider 1 rank data
4475 13:19:17.413557 u2DelayCellTimex100 = 270/100 ps
4476 13:19:17.416517 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4477 13:19:17.419977 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4478 13:19:17.423352 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4479 13:19:17.426300 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4480 13:19:17.430112 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4481 13:19:17.433002 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4482 13:19:17.433125
4483 13:19:17.439607 CA PerBit enable=1, Macro0, CA PI delay=33
4484 13:19:17.439738
4485 13:19:17.443005 [CBTSetCACLKResult] CA Dly = 33
4486 13:19:17.443129 CS Dly: 4 (0~35)
4487 13:19:17.443221 ==
4488 13:19:17.446419 Dram Type= 6, Freq= 0, CH_1, rank 1
4489 13:19:17.449825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 13:19:17.449906 ==
4491 13:19:17.455928 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4492 13:19:17.462716 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4493 13:19:17.465888 [CA 0] Center 35 (5~66) winsize 62
4494 13:19:17.469628 [CA 1] Center 36 (6~66) winsize 61
4495 13:19:17.472603 [CA 2] Center 34 (4~65) winsize 62
4496 13:19:17.475793 [CA 3] Center 34 (4~65) winsize 62
4497 13:19:17.479534 [CA 4] Center 34 (3~65) winsize 63
4498 13:19:17.482670 [CA 5] Center 34 (3~65) winsize 63
4499 13:19:17.482772
4500 13:19:17.485854 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4501 13:19:17.485947
4502 13:19:17.488980 [CATrainingPosCal] consider 2 rank data
4503 13:19:17.492774 u2DelayCellTimex100 = 270/100 ps
4504 13:19:17.495951 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4505 13:19:17.499122 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4506 13:19:17.502885 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4507 13:19:17.505961 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4508 13:19:17.512436 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4509 13:19:17.515589 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4510 13:19:17.515693
4511 13:19:17.519283 CA PerBit enable=1, Macro0, CA PI delay=33
4512 13:19:17.519392
4513 13:19:17.522489 [CBTSetCACLKResult] CA Dly = 33
4514 13:19:17.522570 CS Dly: 4 (0~36)
4515 13:19:17.522630
4516 13:19:17.525619 ----->DramcWriteLeveling(PI) begin...
4517 13:19:17.525724 ==
4518 13:19:17.528612 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 13:19:17.535359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 13:19:17.535508 ==
4521 13:19:17.538938 Write leveling (Byte 0): 30 => 30
4522 13:19:17.542359 Write leveling (Byte 1): 31 => 31
4523 13:19:17.542485 DramcWriteLeveling(PI) end<-----
4524 13:19:17.542644
4525 13:19:17.545414 ==
4526 13:19:17.548928 Dram Type= 6, Freq= 0, CH_1, rank 0
4527 13:19:17.551931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4528 13:19:17.552030 ==
4529 13:19:17.555290 [Gating] SW mode calibration
4530 13:19:17.562075 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4531 13:19:17.565383 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4532 13:19:17.571737 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4533 13:19:17.575214 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4534 13:19:17.578282 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4535 13:19:17.585342 0 9 12 | B1->B0 | 3030 2d2d | 1 0 | (1 1) (1 0)
4536 13:19:17.588462 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4537 13:19:17.591656 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4538 13:19:17.598028 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4539 13:19:17.601301 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4540 13:19:17.604989 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4541 13:19:17.611294 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4542 13:19:17.614466 0 10 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (1 1)
4543 13:19:17.618280 0 10 12 | B1->B0 | 2c2c 3939 | 0 0 | (0 0) (0 0)
4544 13:19:17.624470 0 10 16 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
4545 13:19:17.627522 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4546 13:19:17.631288 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4547 13:19:17.638053 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4548 13:19:17.641194 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4549 13:19:17.644115 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4550 13:19:17.650760 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4551 13:19:17.654048 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4552 13:19:17.657586 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4553 13:19:17.664156 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4554 13:19:17.667026 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4555 13:19:17.670583 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4556 13:19:17.677189 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4557 13:19:17.680550 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4558 13:19:17.683857 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4559 13:19:17.690640 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4560 13:19:17.693763 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4561 13:19:17.696842 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4562 13:19:17.703764 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4563 13:19:17.706835 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4564 13:19:17.710023 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4565 13:19:17.716998 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4566 13:19:17.720164 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4567 13:19:17.723348 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4568 13:19:17.730291 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4569 13:19:17.733272 Total UI for P1: 0, mck2ui 16
4570 13:19:17.737042 best dqsien dly found for B0: ( 0, 13, 12)
4571 13:19:17.737127 Total UI for P1: 0, mck2ui 16
4572 13:19:17.743249 best dqsien dly found for B1: ( 0, 13, 14)
4573 13:19:17.746881 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4574 13:19:17.750059 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4575 13:19:17.750146
4576 13:19:17.753158 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4577 13:19:17.756267 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4578 13:19:17.759800 [Gating] SW calibration Done
4579 13:19:17.759906 ==
4580 13:19:17.762732 Dram Type= 6, Freq= 0, CH_1, rank 0
4581 13:19:17.766157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 13:19:17.766263 ==
4583 13:19:17.769478 RX Vref Scan: 0
4584 13:19:17.769581
4585 13:19:17.773164 RX Vref 0 -> 0, step: 1
4586 13:19:17.773266
4587 13:19:17.773351 RX Delay -230 -> 252, step: 16
4588 13:19:17.779930 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4589 13:19:17.782833 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4590 13:19:17.786496 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4591 13:19:17.789411 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4592 13:19:17.795996 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4593 13:19:17.799742 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4594 13:19:17.803001 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4595 13:19:17.806146 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4596 13:19:17.812965 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4597 13:19:17.816045 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4598 13:19:17.819191 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4599 13:19:17.822356 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4600 13:19:17.829464 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4601 13:19:17.832505 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4602 13:19:17.835454 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4603 13:19:17.839199 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4604 13:19:17.839285 ==
4605 13:19:17.842245 Dram Type= 6, Freq= 0, CH_1, rank 0
4606 13:19:17.849044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 13:19:17.849149 ==
4608 13:19:17.849209 DQS Delay:
4609 13:19:17.852307 DQS0 = 0, DQS1 = 0
4610 13:19:17.852388 DQM Delay:
4611 13:19:17.852447 DQM0 = 50, DQM1 = 36
4612 13:19:17.855401 DQ Delay:
4613 13:19:17.859257 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4614 13:19:17.862501 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4615 13:19:17.865650 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4616 13:19:17.869221 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =57
4617 13:19:17.869308
4618 13:19:17.869385
4619 13:19:17.869457 ==
4620 13:19:17.872243 Dram Type= 6, Freq= 0, CH_1, rank 0
4621 13:19:17.875802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 13:19:17.875891 ==
4623 13:19:17.875970
4624 13:19:17.876042
4625 13:19:17.878736 TX Vref Scan disable
4626 13:19:17.878846 == TX Byte 0 ==
4627 13:19:17.885401 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4628 13:19:17.888780 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4629 13:19:17.888896 == TX Byte 1 ==
4630 13:19:17.895389 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4631 13:19:17.898523 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4632 13:19:17.898609 ==
4633 13:19:17.902100 Dram Type= 6, Freq= 0, CH_1, rank 0
4634 13:19:17.905099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 13:19:17.905182 ==
4636 13:19:17.908528
4637 13:19:17.908608
4638 13:19:17.908685 TX Vref Scan disable
4639 13:19:17.912224 == TX Byte 0 ==
4640 13:19:17.915240 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4641 13:19:17.922035 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4642 13:19:17.922167 == TX Byte 1 ==
4643 13:19:17.925174 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4644 13:19:17.932067 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4645 13:19:17.932190
4646 13:19:17.932279 [DATLAT]
4647 13:19:17.932360 Freq=600, CH1 RK0
4648 13:19:17.932443
4649 13:19:17.935212 DATLAT Default: 0x9
4650 13:19:17.935307 0, 0xFFFF, sum = 0
4651 13:19:17.938754 1, 0xFFFF, sum = 0
4652 13:19:17.941961 2, 0xFFFF, sum = 0
4653 13:19:17.942052 3, 0xFFFF, sum = 0
4654 13:19:17.945246 4, 0xFFFF, sum = 0
4655 13:19:17.945329 5, 0xFFFF, sum = 0
4656 13:19:17.948233 6, 0xFFFF, sum = 0
4657 13:19:17.948315 7, 0xFFFF, sum = 0
4658 13:19:17.951965 8, 0x0, sum = 1
4659 13:19:17.952050 9, 0x0, sum = 2
4660 13:19:17.955125 10, 0x0, sum = 3
4661 13:19:17.955207 11, 0x0, sum = 4
4662 13:19:17.955310 best_step = 9
4663 13:19:17.955418
4664 13:19:17.958211 ==
4665 13:19:17.961305 Dram Type= 6, Freq= 0, CH_1, rank 0
4666 13:19:17.965109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 13:19:17.965245 ==
4668 13:19:17.965367 RX Vref Scan: 1
4669 13:19:17.965425
4670 13:19:17.968256 RX Vref 0 -> 0, step: 1
4671 13:19:17.968337
4672 13:19:17.971337 RX Delay -195 -> 252, step: 8
4673 13:19:17.971416
4674 13:19:17.975092 Set Vref, RX VrefLevel [Byte0]: 51
4675 13:19:17.978106 [Byte1]: 55
4676 13:19:17.978215
4677 13:19:17.981600 Final RX Vref Byte 0 = 51 to rank0
4678 13:19:17.984576 Final RX Vref Byte 1 = 55 to rank0
4679 13:19:17.987867 Final RX Vref Byte 0 = 51 to rank1
4680 13:19:17.991404 Final RX Vref Byte 1 = 55 to rank1==
4681 13:19:17.994528 Dram Type= 6, Freq= 0, CH_1, rank 0
4682 13:19:17.997868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 13:19:17.997997 ==
4684 13:19:18.001354 DQS Delay:
4685 13:19:18.001457 DQS0 = 0, DQS1 = 0
4686 13:19:18.004815 DQM Delay:
4687 13:19:18.004921 DQM0 = 44, DQM1 = 34
4688 13:19:18.007922 DQ Delay:
4689 13:19:18.008005 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =40
4690 13:19:18.011119 DQ4 =40, DQ5 =56, DQ6 =52, DQ7 =40
4691 13:19:18.014220 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4692 13:19:18.017880 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4693 13:19:18.017992
4694 13:19:18.021322
4695 13:19:18.027795 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f34, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4696 13:19:18.030930 CH1 RK0: MR19=808, MR18=4F34
4697 13:19:18.037870 CH1_RK0: MR19=0x808, MR18=0x4F34, DQSOSC=394, MR23=63, INC=168, DEC=112
4698 13:19:18.038008
4699 13:19:18.040990 ----->DramcWriteLeveling(PI) begin...
4700 13:19:18.041079 ==
4701 13:19:18.044553 Dram Type= 6, Freq= 0, CH_1, rank 1
4702 13:19:18.047568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4703 13:19:18.047657 ==
4704 13:19:18.051179 Write leveling (Byte 0): 28 => 28
4705 13:19:18.054334 Write leveling (Byte 1): 32 => 32
4706 13:19:18.057501 DramcWriteLeveling(PI) end<-----
4707 13:19:18.057578
4708 13:19:18.057637 ==
4709 13:19:18.061215 Dram Type= 6, Freq= 0, CH_1, rank 1
4710 13:19:18.064277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4711 13:19:18.064359 ==
4712 13:19:18.067420 [Gating] SW mode calibration
4713 13:19:18.073870 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4714 13:19:18.080754 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4715 13:19:18.083811 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4716 13:19:18.087324 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4717 13:19:18.093901 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4718 13:19:18.097063 0 9 12 | B1->B0 | 3131 3333 | 0 0 | (1 0) (1 1)
4719 13:19:18.100792 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4720 13:19:18.107136 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4721 13:19:18.110571 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4722 13:19:18.113688 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4723 13:19:18.120458 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4724 13:19:18.123533 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4725 13:19:18.127264 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4726 13:19:18.133617 0 10 12 | B1->B0 | 3737 2929 | 1 0 | (1 1) (0 0)
4727 13:19:18.136484 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4728 13:19:18.139734 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4729 13:19:18.146594 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4730 13:19:18.150194 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4731 13:19:18.153383 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4732 13:19:18.159996 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4733 13:19:18.163076 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4734 13:19:18.166154 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4735 13:19:18.173053 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4736 13:19:18.176304 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4737 13:19:18.179449 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4738 13:19:18.186256 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4739 13:19:18.189442 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4740 13:19:18.193004 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4741 13:19:18.199645 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4742 13:19:18.202751 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4743 13:19:18.206375 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4744 13:19:18.212671 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4745 13:19:18.215865 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4746 13:19:18.219040 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4747 13:19:18.226129 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4748 13:19:18.229422 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4749 13:19:18.232468 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4750 13:19:18.239024 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4751 13:19:18.242528 Total UI for P1: 0, mck2ui 16
4752 13:19:18.245390 best dqsien dly found for B0: ( 0, 13, 8)
4753 13:19:18.249232 Total UI for P1: 0, mck2ui 16
4754 13:19:18.252264 best dqsien dly found for B1: ( 0, 13, 10)
4755 13:19:18.255256 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4756 13:19:18.258479 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4757 13:19:18.258582
4758 13:19:18.261998 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4759 13:19:18.265343 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4760 13:19:18.268513 [Gating] SW calibration Done
4761 13:19:18.268617 ==
4762 13:19:18.271652 Dram Type= 6, Freq= 0, CH_1, rank 1
4763 13:19:18.274844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4764 13:19:18.274939 ==
4765 13:19:18.278647 RX Vref Scan: 0
4766 13:19:18.278722
4767 13:19:18.281737 RX Vref 0 -> 0, step: 1
4768 13:19:18.281808
4769 13:19:18.281865 RX Delay -230 -> 252, step: 16
4770 13:19:18.288634 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4771 13:19:18.291746 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4772 13:19:18.294935 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4773 13:19:18.297961 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4774 13:19:18.305191 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4775 13:19:18.308393 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4776 13:19:18.311375 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4777 13:19:18.314539 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4778 13:19:18.321421 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4779 13:19:18.324415 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4780 13:19:18.327854 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4781 13:19:18.331337 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4782 13:19:18.337920 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4783 13:19:18.341045 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4784 13:19:18.344553 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4785 13:19:18.347633 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4786 13:19:18.347732 ==
4787 13:19:18.351210 Dram Type= 6, Freq= 0, CH_1, rank 1
4788 13:19:18.357652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4789 13:19:18.357754 ==
4790 13:19:18.357842 DQS Delay:
4791 13:19:18.360694 DQS0 = 0, DQS1 = 0
4792 13:19:18.360765 DQM Delay:
4793 13:19:18.360820 DQM0 = 43, DQM1 = 38
4794 13:19:18.364501 DQ Delay:
4795 13:19:18.367591 DQ0 =57, DQ1 =41, DQ2 =25, DQ3 =41
4796 13:19:18.370588 DQ4 =33, DQ5 =57, DQ6 =57, DQ7 =33
4797 13:19:18.374497 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4798 13:19:18.377645 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4799 13:19:18.377757
4800 13:19:18.377873
4801 13:19:18.377968 ==
4802 13:19:18.380874 Dram Type= 6, Freq= 0, CH_1, rank 1
4803 13:19:18.383941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4804 13:19:18.384020 ==
4805 13:19:18.384077
4806 13:19:18.384130
4807 13:19:18.387042 TX Vref Scan disable
4808 13:19:18.390794 == TX Byte 0 ==
4809 13:19:18.393908 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4810 13:19:18.396927 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4811 13:19:18.400765 == TX Byte 1 ==
4812 13:19:18.403854 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4813 13:19:18.406808 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4814 13:19:18.406888 ==
4815 13:19:18.410418 Dram Type= 6, Freq= 0, CH_1, rank 1
4816 13:19:18.416671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4817 13:19:18.416767 ==
4818 13:19:18.416827
4819 13:19:18.416881
4820 13:19:18.416932 TX Vref Scan disable
4821 13:19:18.421092 == TX Byte 0 ==
4822 13:19:18.424291 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4823 13:19:18.431148 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4824 13:19:18.431249 == TX Byte 1 ==
4825 13:19:18.434030 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4826 13:19:18.441069 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4827 13:19:18.441171
4828 13:19:18.441230 [DATLAT]
4829 13:19:18.441283 Freq=600, CH1 RK1
4830 13:19:18.441339
4831 13:19:18.444087 DATLAT Default: 0x9
4832 13:19:18.444190 0, 0xFFFF, sum = 0
4833 13:19:18.447754 1, 0xFFFF, sum = 0
4834 13:19:18.450906 2, 0xFFFF, sum = 0
4835 13:19:18.451008 3, 0xFFFF, sum = 0
4836 13:19:18.453961 4, 0xFFFF, sum = 0
4837 13:19:18.454096 5, 0xFFFF, sum = 0
4838 13:19:18.457090 6, 0xFFFF, sum = 0
4839 13:19:18.457171 7, 0xFFFF, sum = 0
4840 13:19:18.460667 8, 0x0, sum = 1
4841 13:19:18.460776 9, 0x0, sum = 2
4842 13:19:18.464045 10, 0x0, sum = 3
4843 13:19:18.464133 11, 0x0, sum = 4
4844 13:19:18.464211 best_step = 9
4845 13:19:18.464284
4846 13:19:18.466938 ==
4847 13:19:18.470688 Dram Type= 6, Freq= 0, CH_1, rank 1
4848 13:19:18.473857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4849 13:19:18.473943 ==
4850 13:19:18.474020 RX Vref Scan: 0
4851 13:19:18.474092
4852 13:19:18.476921 RX Vref 0 -> 0, step: 1
4853 13:19:18.477001
4854 13:19:18.480397 RX Delay -195 -> 252, step: 8
4855 13:19:18.487243 iDelay=213, Bit 0, Center 44 (-107 ~ 196) 304
4856 13:19:18.490354 iDelay=213, Bit 1, Center 36 (-115 ~ 188) 304
4857 13:19:18.493475 iDelay=213, Bit 2, Center 28 (-123 ~ 180) 304
4858 13:19:18.496606 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4859 13:19:18.503248 iDelay=213, Bit 4, Center 40 (-115 ~ 196) 312
4860 13:19:18.507029 iDelay=213, Bit 5, Center 52 (-99 ~ 204) 304
4861 13:19:18.510053 iDelay=213, Bit 6, Center 56 (-99 ~ 212) 312
4862 13:19:18.513149 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4863 13:19:18.516879 iDelay=213, Bit 8, Center 20 (-139 ~ 180) 320
4864 13:19:18.523595 iDelay=213, Bit 9, Center 20 (-139 ~ 180) 320
4865 13:19:18.526684 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4866 13:19:18.529795 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4867 13:19:18.533014 iDelay=213, Bit 12, Center 44 (-115 ~ 204) 320
4868 13:19:18.539911 iDelay=213, Bit 13, Center 40 (-115 ~ 196) 312
4869 13:19:18.542882 iDelay=213, Bit 14, Center 40 (-115 ~ 196) 312
4870 13:19:18.546614 iDelay=213, Bit 15, Center 44 (-115 ~ 204) 320
4871 13:19:18.546716 ==
4872 13:19:18.549516 Dram Type= 6, Freq= 0, CH_1, rank 1
4873 13:19:18.553029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4874 13:19:18.553135 ==
4875 13:19:18.556115 DQS Delay:
4876 13:19:18.556212 DQS0 = 0, DQS1 = 0
4877 13:19:18.559810 DQM Delay:
4878 13:19:18.559906 DQM0 = 42, DQM1 = 33
4879 13:19:18.563024 DQ Delay:
4880 13:19:18.563116 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4881 13:19:18.566065 DQ4 =40, DQ5 =52, DQ6 =56, DQ7 =40
4882 13:19:18.569716 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4883 13:19:18.572751 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4884 13:19:18.572846
4885 13:19:18.576197
4886 13:19:18.582935 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 400 ps
4887 13:19:18.585992 CH1 RK1: MR19=808, MR18=2F24
4888 13:19:18.592513 CH1_RK1: MR19=0x808, MR18=0x2F24, DQSOSC=400, MR23=63, INC=163, DEC=109
4889 13:19:18.596386 [RxdqsGatingPostProcess] freq 600
4890 13:19:18.599357 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4891 13:19:18.602406 Pre-setting of DQS Precalculation
4892 13:19:18.609189 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4893 13:19:18.615946 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4894 13:19:18.622318 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4895 13:19:18.622453
4896 13:19:18.622544
4897 13:19:18.625935 [Calibration Summary] 1200 Mbps
4898 13:19:18.626035 CH 0, Rank 0
4899 13:19:18.628947 SW Impedance : PASS
4900 13:19:18.632751 DUTY Scan : NO K
4901 13:19:18.632850 ZQ Calibration : PASS
4902 13:19:18.635784 Jitter Meter : NO K
4903 13:19:18.638949 CBT Training : PASS
4904 13:19:18.639049 Write leveling : PASS
4905 13:19:18.642687 RX DQS gating : PASS
4906 13:19:18.642772 RX DQ/DQS(RDDQC) : PASS
4907 13:19:18.645717 TX DQ/DQS : PASS
4908 13:19:18.648823 RX DATLAT : PASS
4909 13:19:18.648921 RX DQ/DQS(Engine): PASS
4910 13:19:18.652579 TX OE : NO K
4911 13:19:18.652681 All Pass.
4912 13:19:18.652765
4913 13:19:18.655553 CH 0, Rank 1
4914 13:19:18.655637 SW Impedance : PASS
4915 13:19:18.658997 DUTY Scan : NO K
4916 13:19:18.661926 ZQ Calibration : PASS
4917 13:19:18.662002 Jitter Meter : NO K
4918 13:19:18.665528 CBT Training : PASS
4919 13:19:18.668728 Write leveling : PASS
4920 13:19:18.668810 RX DQS gating : PASS
4921 13:19:18.671947 RX DQ/DQS(RDDQC) : PASS
4922 13:19:18.675735 TX DQ/DQS : PASS
4923 13:19:18.675818 RX DATLAT : PASS
4924 13:19:18.678761 RX DQ/DQS(Engine): PASS
4925 13:19:18.681709 TX OE : NO K
4926 13:19:18.681792 All Pass.
4927 13:19:18.681869
4928 13:19:18.681941 CH 1, Rank 0
4929 13:19:18.685501 SW Impedance : PASS
4930 13:19:18.688481 DUTY Scan : NO K
4931 13:19:18.688564 ZQ Calibration : PASS
4932 13:19:18.691598 Jitter Meter : NO K
4933 13:19:18.695171 CBT Training : PASS
4934 13:19:18.695253 Write leveling : PASS
4935 13:19:18.698414 RX DQS gating : PASS
4936 13:19:18.701630 RX DQ/DQS(RDDQC) : PASS
4937 13:19:18.701730 TX DQ/DQS : PASS
4938 13:19:18.704848 RX DATLAT : PASS
4939 13:19:18.708614 RX DQ/DQS(Engine): PASS
4940 13:19:18.708713 TX OE : NO K
4941 13:19:18.708801 All Pass.
4942 13:19:18.708882
4943 13:19:18.711632 CH 1, Rank 1
4944 13:19:18.714745 SW Impedance : PASS
4945 13:19:18.714838 DUTY Scan : NO K
4946 13:19:18.717938 ZQ Calibration : PASS
4947 13:19:18.718044 Jitter Meter : NO K
4948 13:19:18.721494 CBT Training : PASS
4949 13:19:18.724700 Write leveling : PASS
4950 13:19:18.724785 RX DQS gating : PASS
4951 13:19:18.727791 RX DQ/DQS(RDDQC) : PASS
4952 13:19:18.731480 TX DQ/DQS : PASS
4953 13:19:18.731563 RX DATLAT : PASS
4954 13:19:18.734491 RX DQ/DQS(Engine): PASS
4955 13:19:18.738199 TX OE : NO K
4956 13:19:18.738284 All Pass.
4957 13:19:18.738362
4958 13:19:18.741401 DramC Write-DBI off
4959 13:19:18.741506 PER_BANK_REFRESH: Hybrid Mode
4960 13:19:18.744502 TX_TRACKING: ON
4961 13:19:18.754434 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4962 13:19:18.757543 [FAST_K] Save calibration result to emmc
4963 13:19:18.761282 dramc_set_vcore_voltage set vcore to 662500
4964 13:19:18.761369 Read voltage for 933, 3
4965 13:19:18.764211 Vio18 = 0
4966 13:19:18.764292 Vcore = 662500
4967 13:19:18.764351 Vdram = 0
4968 13:19:18.767699 Vddq = 0
4969 13:19:18.767776 Vmddr = 0
4970 13:19:18.774127 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4971 13:19:18.777254 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4972 13:19:18.781053 MEM_TYPE=3, freq_sel=17
4973 13:19:18.784256 sv_algorithm_assistance_LP4_1600
4974 13:19:18.787220 ============ PULL DRAM RESETB DOWN ============
4975 13:19:18.790656 ========== PULL DRAM RESETB DOWN end =========
4976 13:19:18.796937 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4977 13:19:18.800607 ===================================
4978 13:19:18.800697 LPDDR4 DRAM CONFIGURATION
4979 13:19:18.803533 ===================================
4980 13:19:18.807393 EX_ROW_EN[0] = 0x0
4981 13:19:18.810436 EX_ROW_EN[1] = 0x0
4982 13:19:18.810522 LP4Y_EN = 0x0
4983 13:19:18.813582 WORK_FSP = 0x0
4984 13:19:18.813661 WL = 0x3
4985 13:19:18.817224 RL = 0x3
4986 13:19:18.817328 BL = 0x2
4987 13:19:18.820453 RPST = 0x0
4988 13:19:18.820531 RD_PRE = 0x0
4989 13:19:18.823623 WR_PRE = 0x1
4990 13:19:18.823706 WR_PST = 0x0
4991 13:19:18.826696 DBI_WR = 0x0
4992 13:19:18.826774 DBI_RD = 0x0
4993 13:19:18.830402 OTF = 0x1
4994 13:19:18.833540 ===================================
4995 13:19:18.836531 ===================================
4996 13:19:18.836615 ANA top config
4997 13:19:18.840224 ===================================
4998 13:19:18.843316 DLL_ASYNC_EN = 0
4999 13:19:18.846516 ALL_SLAVE_EN = 1
5000 13:19:18.849697 NEW_RANK_MODE = 1
5001 13:19:18.849802 DLL_IDLE_MODE = 1
5002 13:19:18.853408 LP45_APHY_COMB_EN = 1
5003 13:19:18.856553 TX_ODT_DIS = 1
5004 13:19:18.859585 NEW_8X_MODE = 1
5005 13:19:18.862721 ===================================
5006 13:19:18.866476 ===================================
5007 13:19:18.869485 data_rate = 1866
5008 13:19:18.872604 CKR = 1
5009 13:19:18.872687 DQ_P2S_RATIO = 8
5010 13:19:18.876227 ===================================
5011 13:19:18.879198 CA_P2S_RATIO = 8
5012 13:19:18.882844 DQ_CA_OPEN = 0
5013 13:19:18.885858 DQ_SEMI_OPEN = 0
5014 13:19:18.889686 CA_SEMI_OPEN = 0
5015 13:19:18.892734 CA_FULL_RATE = 0
5016 13:19:18.892817 DQ_CKDIV4_EN = 1
5017 13:19:18.895814 CA_CKDIV4_EN = 1
5018 13:19:18.899317 CA_PREDIV_EN = 0
5019 13:19:18.902709 PH8_DLY = 0
5020 13:19:18.906187 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5021 13:19:18.909165 DQ_AAMCK_DIV = 4
5022 13:19:18.909270 CA_AAMCK_DIV = 4
5023 13:19:18.912513 CA_ADMCK_DIV = 4
5024 13:19:18.915723 DQ_TRACK_CA_EN = 0
5025 13:19:18.919242 CA_PICK = 933
5026 13:19:18.922339 CA_MCKIO = 933
5027 13:19:18.925466 MCKIO_SEMI = 0
5028 13:19:18.929153 PLL_FREQ = 3732
5029 13:19:18.929241 DQ_UI_PI_RATIO = 32
5030 13:19:18.932274 CA_UI_PI_RATIO = 0
5031 13:19:18.935400 ===================================
5032 13:19:18.938598 ===================================
5033 13:19:18.942183 memory_type:LPDDR4
5034 13:19:18.945252 GP_NUM : 10
5035 13:19:18.945337 SRAM_EN : 1
5036 13:19:18.948467 MD32_EN : 0
5037 13:19:18.952259 ===================================
5038 13:19:18.955401 [ANA_INIT] >>>>>>>>>>>>>>
5039 13:19:18.955512 <<<<<< [CONFIGURE PHASE]: ANA_TX
5040 13:19:18.961614 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5041 13:19:18.965451 ===================================
5042 13:19:18.965540 data_rate = 1866,PCW = 0X8f00
5043 13:19:18.968654 ===================================
5044 13:19:18.971668 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5045 13:19:18.978538 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5046 13:19:18.985173 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5047 13:19:18.988574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5048 13:19:18.991677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5049 13:19:18.994756 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5050 13:19:18.997971 [ANA_INIT] flow start
5051 13:19:18.998052 [ANA_INIT] PLL >>>>>>>>
5052 13:19:19.001638 [ANA_INIT] PLL <<<<<<<<
5053 13:19:19.004771 [ANA_INIT] MIDPI >>>>>>>>
5054 13:19:19.007726 [ANA_INIT] MIDPI <<<<<<<<
5055 13:19:19.007837 [ANA_INIT] DLL >>>>>>>>
5056 13:19:19.011251 [ANA_INIT] flow end
5057 13:19:19.014872 ============ LP4 DIFF to SE enter ============
5058 13:19:19.017965 ============ LP4 DIFF to SE exit ============
5059 13:19:19.021045 [ANA_INIT] <<<<<<<<<<<<<
5060 13:19:19.024645 [Flow] Enable top DCM control >>>>>
5061 13:19:19.027818 [Flow] Enable top DCM control <<<<<
5062 13:19:19.031236 Enable DLL master slave shuffle
5063 13:19:19.037946 ==============================================================
5064 13:19:19.038050 Gating Mode config
5065 13:19:19.044283 ==============================================================
5066 13:19:19.044407 Config description:
5067 13:19:19.054618 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5068 13:19:19.060736 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5069 13:19:19.067214 SELPH_MODE 0: By rank 1: By Phase
5070 13:19:19.074153 ==============================================================
5071 13:19:19.074295 GAT_TRACK_EN = 1
5072 13:19:19.077101 RX_GATING_MODE = 2
5073 13:19:19.080685 RX_GATING_TRACK_MODE = 2
5074 13:19:19.083843 SELPH_MODE = 1
5075 13:19:19.086937 PICG_EARLY_EN = 1
5076 13:19:19.090147 VALID_LAT_VALUE = 1
5077 13:19:19.097102 ==============================================================
5078 13:19:19.100208 Enter into Gating configuration >>>>
5079 13:19:19.103347 Exit from Gating configuration <<<<
5080 13:19:19.106515 Enter into DVFS_PRE_config >>>>>
5081 13:19:19.116474 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5082 13:19:19.119927 Exit from DVFS_PRE_config <<<<<
5083 13:19:19.123630 Enter into PICG configuration >>>>
5084 13:19:19.126642 Exit from PICG configuration <<<<
5085 13:19:19.129843 [RX_INPUT] configuration >>>>>
5086 13:19:19.133479 [RX_INPUT] configuration <<<<<
5087 13:19:19.136522 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5088 13:19:19.142913 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5089 13:19:19.149408 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5090 13:19:19.155854 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5091 13:19:19.159399 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5092 13:19:19.165686 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5093 13:19:19.172599 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5094 13:19:19.175701 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5095 13:19:19.179616 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5096 13:19:19.182637 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5097 13:19:19.185817 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5098 13:19:19.192832 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5099 13:19:19.195966 ===================================
5100 13:19:19.199061 LPDDR4 DRAM CONFIGURATION
5101 13:19:19.202543 ===================================
5102 13:19:19.202636 EX_ROW_EN[0] = 0x0
5103 13:19:19.205523 EX_ROW_EN[1] = 0x0
5104 13:19:19.205640 LP4Y_EN = 0x0
5105 13:19:19.209176 WORK_FSP = 0x0
5106 13:19:19.209310 WL = 0x3
5107 13:19:19.212301 RL = 0x3
5108 13:19:19.212388 BL = 0x2
5109 13:19:19.215370 RPST = 0x0
5110 13:19:19.215531 RD_PRE = 0x0
5111 13:19:19.219204 WR_PRE = 0x1
5112 13:19:19.219322 WR_PST = 0x0
5113 13:19:19.222346 DBI_WR = 0x0
5114 13:19:19.222456 DBI_RD = 0x0
5115 13:19:19.225314 OTF = 0x1
5116 13:19:19.229020 ===================================
5117 13:19:19.232051 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5118 13:19:19.235064 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5119 13:19:19.242016 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5120 13:19:19.245195 ===================================
5121 13:19:19.248336 LPDDR4 DRAM CONFIGURATION
5122 13:19:19.251976 ===================================
5123 13:19:19.252129 EX_ROW_EN[0] = 0x10
5124 13:19:19.254971 EX_ROW_EN[1] = 0x0
5125 13:19:19.255154 LP4Y_EN = 0x0
5126 13:19:19.258374 WORK_FSP = 0x0
5127 13:19:19.258474 WL = 0x3
5128 13:19:19.261709 RL = 0x3
5129 13:19:19.261847 BL = 0x2
5130 13:19:19.265102 RPST = 0x0
5131 13:19:19.265228 RD_PRE = 0x0
5132 13:19:19.268378 WR_PRE = 0x1
5133 13:19:19.271798 WR_PST = 0x0
5134 13:19:19.271878 DBI_WR = 0x0
5135 13:19:19.274545 DBI_RD = 0x0
5136 13:19:19.274660 OTF = 0x1
5137 13:19:19.278294 ===================================
5138 13:19:19.284438 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5139 13:19:19.288201 nWR fixed to 30
5140 13:19:19.291905 [ModeRegInit_LP4] CH0 RK0
5141 13:19:19.291993 [ModeRegInit_LP4] CH0 RK1
5142 13:19:19.295118 [ModeRegInit_LP4] CH1 RK0
5143 13:19:19.298165 [ModeRegInit_LP4] CH1 RK1
5144 13:19:19.298278 match AC timing 9
5145 13:19:19.304576 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5146 13:19:19.308210 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5147 13:19:19.311147 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5148 13:19:19.317766 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5149 13:19:19.321427 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5150 13:19:19.321529 ==
5151 13:19:19.324620 Dram Type= 6, Freq= 0, CH_0, rank 0
5152 13:19:19.327798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5153 13:19:19.327891 ==
5154 13:19:19.334419 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5155 13:19:19.340787 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5156 13:19:19.344575 [CA 0] Center 37 (7~68) winsize 62
5157 13:19:19.347938 [CA 1] Center 37 (7~68) winsize 62
5158 13:19:19.350978 [CA 2] Center 34 (4~65) winsize 62
5159 13:19:19.353893 [CA 3] Center 34 (4~65) winsize 62
5160 13:19:19.357672 [CA 4] Center 33 (3~64) winsize 62
5161 13:19:19.360786 [CA 5] Center 33 (3~64) winsize 62
5162 13:19:19.360895
5163 13:19:19.363987 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5164 13:19:19.364095
5165 13:19:19.367057 [CATrainingPosCal] consider 1 rank data
5166 13:19:19.370741 u2DelayCellTimex100 = 270/100 ps
5167 13:19:19.373549 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5168 13:19:19.377357 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5169 13:19:19.380311 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5170 13:19:19.387173 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5171 13:19:19.390293 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5172 13:19:19.393765 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5173 13:19:19.393877
5174 13:19:19.396919 CA PerBit enable=1, Macro0, CA PI delay=33
5175 13:19:19.397020
5176 13:19:19.400079 [CBTSetCACLKResult] CA Dly = 33
5177 13:19:19.400180 CS Dly: 7 (0~38)
5178 13:19:19.400267 ==
5179 13:19:19.403183 Dram Type= 6, Freq= 0, CH_0, rank 1
5180 13:19:19.410054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 13:19:19.410184 ==
5182 13:19:19.413273 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5183 13:19:19.419772 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5184 13:19:19.423202 [CA 0] Center 37 (7~68) winsize 62
5185 13:19:19.426783 [CA 1] Center 37 (7~68) winsize 62
5186 13:19:19.429927 [CA 2] Center 34 (4~65) winsize 62
5187 13:19:19.433012 [CA 3] Center 34 (4~65) winsize 62
5188 13:19:19.436861 [CA 4] Center 33 (3~64) winsize 62
5189 13:19:19.439955 [CA 5] Center 33 (3~63) winsize 61
5190 13:19:19.440037
5191 13:19:19.442973 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5192 13:19:19.443054
5193 13:19:19.446520 [CATrainingPosCal] consider 2 rank data
5194 13:19:19.449568 u2DelayCellTimex100 = 270/100 ps
5195 13:19:19.453359 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5196 13:19:19.459556 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5197 13:19:19.463278 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5198 13:19:19.466406 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5199 13:19:19.469490 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5200 13:19:19.473283 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5201 13:19:19.473382
5202 13:19:19.476320 CA PerBit enable=1, Macro0, CA PI delay=33
5203 13:19:19.476398
5204 13:19:19.479416 [CBTSetCACLKResult] CA Dly = 33
5205 13:19:19.482882 CS Dly: 7 (0~39)
5206 13:19:19.482993
5207 13:19:19.486271 ----->DramcWriteLeveling(PI) begin...
5208 13:19:19.486378 ==
5209 13:19:19.489334 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 13:19:19.492363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 13:19:19.492470 ==
5212 13:19:19.495880 Write leveling (Byte 0): 32 => 32
5213 13:19:19.499028 Write leveling (Byte 1): 30 => 30
5214 13:19:19.502230 DramcWriteLeveling(PI) end<-----
5215 13:19:19.502333
5216 13:19:19.502418 ==
5217 13:19:19.505414 Dram Type= 6, Freq= 0, CH_0, rank 0
5218 13:19:19.508977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5219 13:19:19.509083 ==
5220 13:19:19.512102 [Gating] SW mode calibration
5221 13:19:19.519231 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5222 13:19:19.525528 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5223 13:19:19.528996 0 14 0 | B1->B0 | 2322 2f2f | 1 1 | (0 0) (1 1)
5224 13:19:19.531891 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5225 13:19:19.538747 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5226 13:19:19.541789 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5227 13:19:19.545476 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5228 13:19:19.554039 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5229 13:19:19.555161 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5230 13:19:19.558321 0 14 28 | B1->B0 | 3434 2e2e | 0 0 | (0 1) (1 0)
5231 13:19:19.565259 0 15 0 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
5232 13:19:19.568363 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5233 13:19:19.571535 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5234 13:19:19.578259 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5235 13:19:19.581446 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5236 13:19:19.584635 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5237 13:19:19.591290 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5238 13:19:19.594802 0 15 28 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5239 13:19:19.597876 1 0 0 | B1->B0 | 3131 4343 | 0 0 | (0 0) (1 1)
5240 13:19:19.604847 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5241 13:19:19.607946 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5242 13:19:19.610994 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5243 13:19:19.618002 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5244 13:19:19.621018 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5245 13:19:19.624476 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5246 13:19:19.630854 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5247 13:19:19.634374 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5248 13:19:19.637812 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5249 13:19:19.644266 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5250 13:19:19.647378 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5251 13:19:19.654025 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5252 13:19:19.657060 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5253 13:19:19.660865 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5254 13:19:19.667213 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5255 13:19:19.670254 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5256 13:19:19.673996 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5257 13:19:19.680183 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5258 13:19:19.683360 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5259 13:19:19.686619 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5260 13:19:19.693577 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5261 13:19:19.696712 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5262 13:19:19.700066 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5263 13:19:19.706616 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5264 13:19:19.706721 Total UI for P1: 0, mck2ui 16
5265 13:19:19.709819 best dqsien dly found for B0: ( 1, 2, 30)
5266 13:19:19.716283 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5267 13:19:19.720008 Total UI for P1: 0, mck2ui 16
5268 13:19:19.723112 best dqsien dly found for B1: ( 1, 3, 0)
5269 13:19:19.726134 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5270 13:19:19.729367 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5271 13:19:19.729477
5272 13:19:19.733062 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5273 13:19:19.736419 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5274 13:19:19.739632 [Gating] SW calibration Done
5275 13:19:19.739713 ==
5276 13:19:19.742652 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 13:19:19.746201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 13:19:19.746311 ==
5279 13:19:19.749519 RX Vref Scan: 0
5280 13:19:19.749602
5281 13:19:19.752559 RX Vref 0 -> 0, step: 1
5282 13:19:19.752656
5283 13:19:19.752744 RX Delay -80 -> 252, step: 8
5284 13:19:19.759332 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5285 13:19:19.763000 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5286 13:19:19.765780 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5287 13:19:19.769562 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5288 13:19:19.772685 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5289 13:19:19.775964 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5290 13:19:19.782767 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5291 13:19:19.785886 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5292 13:19:19.789084 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5293 13:19:19.792806 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5294 13:19:19.795942 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5295 13:19:19.802200 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5296 13:19:19.805808 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5297 13:19:19.809141 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5298 13:19:19.812537 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5299 13:19:19.815682 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5300 13:19:19.818756 ==
5301 13:19:19.821930 Dram Type= 6, Freq= 0, CH_0, rank 0
5302 13:19:19.825641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 13:19:19.825730 ==
5304 13:19:19.825809 DQS Delay:
5305 13:19:19.828846 DQS0 = 0, DQS1 = 0
5306 13:19:19.828925 DQM Delay:
5307 13:19:19.831955 DQM0 = 96, DQM1 = 85
5308 13:19:19.832035 DQ Delay:
5309 13:19:19.835599 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5310 13:19:19.838634 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5311 13:19:19.842156 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =79
5312 13:19:19.845080 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5313 13:19:19.845162
5314 13:19:19.845249
5315 13:19:19.845351 ==
5316 13:19:19.848597 Dram Type= 6, Freq= 0, CH_0, rank 0
5317 13:19:19.852198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 13:19:19.852281 ==
5319 13:19:19.852341
5320 13:19:19.852395
5321 13:19:19.855076 TX Vref Scan disable
5322 13:19:19.858603 == TX Byte 0 ==
5323 13:19:19.862054 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5324 13:19:19.864988 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5325 13:19:19.868554 == TX Byte 1 ==
5326 13:19:19.871983 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5327 13:19:19.875107 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5328 13:19:19.875224 ==
5329 13:19:19.878191 Dram Type= 6, Freq= 0, CH_0, rank 0
5330 13:19:19.885166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5331 13:19:19.885258 ==
5332 13:19:19.885317
5333 13:19:19.885372
5334 13:19:19.885423 TX Vref Scan disable
5335 13:19:19.888952 == TX Byte 0 ==
5336 13:19:19.892658 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5337 13:19:19.898949 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5338 13:19:19.899050 == TX Byte 1 ==
5339 13:19:19.902102 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5340 13:19:19.909142 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5341 13:19:19.909240
5342 13:19:19.909301 [DATLAT]
5343 13:19:19.909355 Freq=933, CH0 RK0
5344 13:19:19.909408
5345 13:19:19.912209 DATLAT Default: 0xd
5346 13:19:19.912288 0, 0xFFFF, sum = 0
5347 13:19:19.915334 1, 0xFFFF, sum = 0
5348 13:19:19.918668 2, 0xFFFF, sum = 0
5349 13:19:19.918748 3, 0xFFFF, sum = 0
5350 13:19:19.921829 4, 0xFFFF, sum = 0
5351 13:19:19.921911 5, 0xFFFF, sum = 0
5352 13:19:19.924935 6, 0xFFFF, sum = 0
5353 13:19:19.925041 7, 0xFFFF, sum = 0
5354 13:19:19.928660 8, 0xFFFF, sum = 0
5355 13:19:19.928764 9, 0xFFFF, sum = 0
5356 13:19:19.931923 10, 0x0, sum = 1
5357 13:19:19.932025 11, 0x0, sum = 2
5358 13:19:19.935046 12, 0x0, sum = 3
5359 13:19:19.935146 13, 0x0, sum = 4
5360 13:19:19.938231 best_step = 11
5361 13:19:19.938359
5362 13:19:19.938443 ==
5363 13:19:19.941344 Dram Type= 6, Freq= 0, CH_0, rank 0
5364 13:19:19.945015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5365 13:19:19.945118 ==
5366 13:19:19.945204 RX Vref Scan: 1
5367 13:19:19.948005
5368 13:19:19.948102 RX Vref 0 -> 0, step: 1
5369 13:19:19.948186
5370 13:19:19.951138 RX Delay -69 -> 252, step: 4
5371 13:19:19.951241
5372 13:19:19.954763 Set Vref, RX VrefLevel [Byte0]: 61
5373 13:19:19.957802 [Byte1]: 49
5374 13:19:19.961785
5375 13:19:19.961889 Final RX Vref Byte 0 = 61 to rank0
5376 13:19:19.965252 Final RX Vref Byte 1 = 49 to rank0
5377 13:19:19.968227 Final RX Vref Byte 0 = 61 to rank1
5378 13:19:19.971673 Final RX Vref Byte 1 = 49 to rank1==
5379 13:19:19.975098 Dram Type= 6, Freq= 0, CH_0, rank 0
5380 13:19:19.981736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 13:19:19.981856 ==
5382 13:19:19.981943 DQS Delay:
5383 13:19:19.984523 DQS0 = 0, DQS1 = 0
5384 13:19:19.984626 DQM Delay:
5385 13:19:19.984709 DQM0 = 96, DQM1 = 85
5386 13:19:19.988360 DQ Delay:
5387 13:19:19.991479 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =92
5388 13:19:19.994573 DQ4 =98, DQ5 =86, DQ6 =106, DQ7 =106
5389 13:19:19.997768 DQ8 =76, DQ9 =74, DQ10 =84, DQ11 =78
5390 13:19:20.000966 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =92
5391 13:19:20.001068
5392 13:19:20.001154
5393 13:19:20.007871 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5394 13:19:20.011028 CH0 RK0: MR19=505, MR18=2F15
5395 13:19:20.017323 CH0_RK0: MR19=0x505, MR18=0x2F15, DQSOSC=407, MR23=63, INC=65, DEC=43
5396 13:19:20.017423
5397 13:19:20.020540 ----->DramcWriteLeveling(PI) begin...
5398 13:19:20.020637 ==
5399 13:19:20.024164 Dram Type= 6, Freq= 0, CH_0, rank 1
5400 13:19:20.027418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5401 13:19:20.027546 ==
5402 13:19:20.030574 Write leveling (Byte 0): 35 => 35
5403 13:19:20.033763 Write leveling (Byte 1): 29 => 29
5404 13:19:20.037010 DramcWriteLeveling(PI) end<-----
5405 13:19:20.037107
5406 13:19:20.037189 ==
5407 13:19:20.040211 Dram Type= 6, Freq= 0, CH_0, rank 1
5408 13:19:20.047074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5409 13:19:20.047173 ==
5410 13:19:20.047257 [Gating] SW mode calibration
5411 13:19:20.056671 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5412 13:19:20.060398 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5413 13:19:20.066891 0 14 0 | B1->B0 | 2525 2f2f | 1 0 | (1 1) (0 0)
5414 13:19:20.070281 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5415 13:19:20.073333 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5416 13:19:20.079918 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5417 13:19:20.083638 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5418 13:19:20.086604 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5419 13:19:20.090122 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5420 13:19:20.096697 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
5421 13:19:20.099724 0 15 0 | B1->B0 | 2e2e 2424 | 1 1 | (1 0) (1 0)
5422 13:19:20.106639 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5423 13:19:20.109748 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5424 13:19:20.112996 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5425 13:19:20.115968 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5426 13:19:20.123025 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5427 13:19:20.126231 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5428 13:19:20.129381 0 15 28 | B1->B0 | 2828 3636 | 0 0 | (0 0) (1 1)
5429 13:19:20.136462 1 0 0 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
5430 13:19:20.139630 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5431 13:19:20.142906 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5432 13:19:20.149116 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5433 13:19:20.152880 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5434 13:19:20.155983 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5435 13:19:20.162704 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5436 13:19:20.165833 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5437 13:19:20.169543 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5438 13:19:20.175488 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 13:19:20.178944 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 13:19:20.182258 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 13:19:20.189166 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 13:19:20.192246 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 13:19:20.195354 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 13:19:20.201893 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 13:19:20.205380 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 13:19:20.208923 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 13:19:20.215366 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 13:19:20.218568 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 13:19:20.222396 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 13:19:20.228489 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 13:19:20.231707 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 13:19:20.235525 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5453 13:19:20.241720 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5454 13:19:20.245093 Total UI for P1: 0, mck2ui 16
5455 13:19:20.248181 best dqsien dly found for B0: ( 1, 2, 28)
5456 13:19:20.251939 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5457 13:19:20.255074 Total UI for P1: 0, mck2ui 16
5458 13:19:20.258153 best dqsien dly found for B1: ( 1, 3, 0)
5459 13:19:20.262006 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5460 13:19:20.265248 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5461 13:19:20.265324
5462 13:19:20.268546 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5463 13:19:20.271351 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5464 13:19:20.275049 [Gating] SW calibration Done
5465 13:19:20.275118 ==
5466 13:19:20.278149 Dram Type= 6, Freq= 0, CH_0, rank 1
5467 13:19:20.285064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 13:19:20.285141 ==
5469 13:19:20.285200 RX Vref Scan: 0
5470 13:19:20.285256
5471 13:19:20.287991 RX Vref 0 -> 0, step: 1
5472 13:19:20.288076
5473 13:19:20.291384 RX Delay -80 -> 252, step: 8
5474 13:19:20.294919 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5475 13:19:20.297757 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5476 13:19:20.301300 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5477 13:19:20.304615 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5478 13:19:20.311324 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5479 13:19:20.314448 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5480 13:19:20.317980 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5481 13:19:20.321077 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5482 13:19:20.324185 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5483 13:19:20.327670 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5484 13:19:20.333997 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5485 13:19:20.337220 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5486 13:19:20.341080 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5487 13:19:20.344193 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5488 13:19:20.347269 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5489 13:19:20.354109 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5490 13:19:20.354240 ==
5491 13:19:20.357046 Dram Type= 6, Freq= 0, CH_0, rank 1
5492 13:19:20.360297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5493 13:19:20.360367 ==
5494 13:19:20.360424 DQS Delay:
5495 13:19:20.364114 DQS0 = 0, DQS1 = 0
5496 13:19:20.364222 DQM Delay:
5497 13:19:20.367197 DQM0 = 96, DQM1 = 87
5498 13:19:20.367287 DQ Delay:
5499 13:19:20.370317 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5500 13:19:20.374128 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5501 13:19:20.377214 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5502 13:19:20.380121 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5503 13:19:20.380223
5504 13:19:20.380316
5505 13:19:20.380406 ==
5506 13:19:20.383796 Dram Type= 6, Freq= 0, CH_0, rank 1
5507 13:19:20.390026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5508 13:19:20.390129 ==
5509 13:19:20.390246
5510 13:19:20.390344
5511 13:19:20.390426 TX Vref Scan disable
5512 13:19:20.393707 == TX Byte 0 ==
5513 13:19:20.396781 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5514 13:19:20.403725 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5515 13:19:20.403802 == TX Byte 1 ==
5516 13:19:20.406690 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5517 13:19:20.413280 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5518 13:19:20.413358 ==
5519 13:19:20.416464 Dram Type= 6, Freq= 0, CH_0, rank 1
5520 13:19:20.420209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5521 13:19:20.420313 ==
5522 13:19:20.420397
5523 13:19:20.420477
5524 13:19:20.423324 TX Vref Scan disable
5525 13:19:20.426479 == TX Byte 0 ==
5526 13:19:20.429686 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5527 13:19:20.433328 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5528 13:19:20.436642 == TX Byte 1 ==
5529 13:19:20.440064 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5530 13:19:20.443291 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5531 13:19:20.443403
5532 13:19:20.443484 [DATLAT]
5533 13:19:20.446461 Freq=933, CH0 RK1
5534 13:19:20.446541
5535 13:19:20.446601 DATLAT Default: 0xb
5536 13:19:20.449500 0, 0xFFFF, sum = 0
5537 13:19:20.453200 1, 0xFFFF, sum = 0
5538 13:19:20.453296 2, 0xFFFF, sum = 0
5539 13:19:20.456220 3, 0xFFFF, sum = 0
5540 13:19:20.456298 4, 0xFFFF, sum = 0
5541 13:19:20.459602 5, 0xFFFF, sum = 0
5542 13:19:20.459682 6, 0xFFFF, sum = 0
5543 13:19:20.463061 7, 0xFFFF, sum = 0
5544 13:19:20.463141 8, 0xFFFF, sum = 0
5545 13:19:20.466030 9, 0xFFFF, sum = 0
5546 13:19:20.466109 10, 0x0, sum = 1
5547 13:19:20.469820 11, 0x0, sum = 2
5548 13:19:20.469901 12, 0x0, sum = 3
5549 13:19:20.472885 13, 0x0, sum = 4
5550 13:19:20.472965 best_step = 11
5551 13:19:20.473043
5552 13:19:20.473119 ==
5553 13:19:20.476104 Dram Type= 6, Freq= 0, CH_0, rank 1
5554 13:19:20.479230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 13:19:20.479310 ==
5556 13:19:20.483018 RX Vref Scan: 0
5557 13:19:20.483100
5558 13:19:20.486119 RX Vref 0 -> 0, step: 1
5559 13:19:20.486198
5560 13:19:20.486275 RX Delay -61 -> 252, step: 4
5561 13:19:20.493985 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5562 13:19:20.497134 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5563 13:19:20.500927 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5564 13:19:20.504049 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5565 13:19:20.507120 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5566 13:19:20.514134 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5567 13:19:20.517229 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5568 13:19:20.520667 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5569 13:19:20.523360 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5570 13:19:20.527261 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5571 13:19:20.533760 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5572 13:19:20.536912 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5573 13:19:20.540002 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5574 13:19:20.543093 iDelay=203, Bit 13, Center 94 (-1 ~ 190) 192
5575 13:19:20.546714 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5576 13:19:20.553513 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5577 13:19:20.553592 ==
5578 13:19:20.556684 Dram Type= 6, Freq= 0, CH_0, rank 1
5579 13:19:20.559893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 13:19:20.559963 ==
5581 13:19:20.560035 DQS Delay:
5582 13:19:20.562968 DQS0 = 0, DQS1 = 0
5583 13:19:20.563035 DQM Delay:
5584 13:19:20.566578 DQM0 = 95, DQM1 = 86
5585 13:19:20.566645 DQ Delay:
5586 13:19:20.569574 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =94
5587 13:19:20.573058 DQ4 =94, DQ5 =86, DQ6 =106, DQ7 =104
5588 13:19:20.576353 DQ8 =76, DQ9 =74, DQ10 =86, DQ11 =78
5589 13:19:20.579691 DQ12 =92, DQ13 =94, DQ14 =96, DQ15 =92
5590 13:19:20.579759
5591 13:19:20.579830
5592 13:19:20.589572 [DQSOSCAuto] RK1, (LSB)MR18= 0x28f9, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 409 ps
5593 13:19:20.589656 CH0 RK1: MR19=504, MR18=28F9
5594 13:19:20.595592 CH0_RK1: MR19=0x504, MR18=0x28F9, DQSOSC=409, MR23=63, INC=64, DEC=43
5595 13:19:20.599170 [RxdqsGatingPostProcess] freq 933
5596 13:19:20.605980 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5597 13:19:20.609114 best DQS0 dly(2T, 0.5T) = (0, 10)
5598 13:19:20.612216 best DQS1 dly(2T, 0.5T) = (0, 11)
5599 13:19:20.615981 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5600 13:19:20.619023 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5601 13:19:20.622270 best DQS0 dly(2T, 0.5T) = (0, 10)
5602 13:19:20.625716 best DQS1 dly(2T, 0.5T) = (0, 11)
5603 13:19:20.629024 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5604 13:19:20.632077 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5605 13:19:20.632144 Pre-setting of DQS Precalculation
5606 13:19:20.638474 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5607 13:19:20.638566 ==
5608 13:19:20.641955 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 13:19:20.644975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 13:19:20.645042 ==
5611 13:19:20.652055 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5612 13:19:20.658168 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5613 13:19:20.661649 [CA 0] Center 36 (6~67) winsize 62
5614 13:19:20.665079 [CA 1] Center 36 (6~67) winsize 62
5615 13:19:20.668093 [CA 2] Center 34 (4~65) winsize 62
5616 13:19:20.671244 [CA 3] Center 33 (3~64) winsize 62
5617 13:19:20.674199 [CA 4] Center 34 (4~64) winsize 61
5618 13:19:20.677602 [CA 5] Center 33 (3~64) winsize 62
5619 13:19:20.677670
5620 13:19:20.681192 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5621 13:19:20.681260
5622 13:19:20.684303 [CATrainingPosCal] consider 1 rank data
5623 13:19:20.687543 u2DelayCellTimex100 = 270/100 ps
5624 13:19:20.691266 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5625 13:19:20.694337 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5626 13:19:20.697537 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5627 13:19:20.701211 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5628 13:19:20.707765 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5629 13:19:20.711195 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5630 13:19:20.711268
5631 13:19:20.714073 CA PerBit enable=1, Macro0, CA PI delay=33
5632 13:19:20.714151
5633 13:19:20.717232 [CBTSetCACLKResult] CA Dly = 33
5634 13:19:20.717308 CS Dly: 6 (0~37)
5635 13:19:20.717367 ==
5636 13:19:20.720986 Dram Type= 6, Freq= 0, CH_1, rank 1
5637 13:19:20.727276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 13:19:20.727362 ==
5639 13:19:20.730723 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5640 13:19:20.736937 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5641 13:19:20.740695 [CA 0] Center 36 (6~67) winsize 62
5642 13:19:20.743769 [CA 1] Center 37 (7~67) winsize 61
5643 13:19:20.747321 [CA 2] Center 34 (4~65) winsize 62
5644 13:19:20.750288 [CA 3] Center 34 (4~64) winsize 61
5645 13:19:20.753946 [CA 4] Center 34 (4~65) winsize 62
5646 13:19:20.757071 [CA 5] Center 33 (3~64) winsize 62
5647 13:19:20.757139
5648 13:19:20.760283 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5649 13:19:20.760349
5650 13:19:20.763387 [CATrainingPosCal] consider 2 rank data
5651 13:19:20.767143 u2DelayCellTimex100 = 270/100 ps
5652 13:19:20.770148 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5653 13:19:20.777016 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5654 13:19:20.780021 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5655 13:19:20.783633 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5656 13:19:20.786680 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5657 13:19:20.790101 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5658 13:19:20.790183
5659 13:19:20.793141 CA PerBit enable=1, Macro0, CA PI delay=33
5660 13:19:20.793221
5661 13:19:20.796783 [CBTSetCACLKResult] CA Dly = 33
5662 13:19:20.799947 CS Dly: 7 (0~39)
5663 13:19:20.800016
5664 13:19:20.803093 ----->DramcWriteLeveling(PI) begin...
5665 13:19:20.803161 ==
5666 13:19:20.806217 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 13:19:20.809399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 13:19:20.809503 ==
5669 13:19:20.813115 Write leveling (Byte 0): 26 => 26
5670 13:19:20.816113 Write leveling (Byte 1): 27 => 27
5671 13:19:20.819329 DramcWriteLeveling(PI) end<-----
5672 13:19:20.819446
5673 13:19:20.819520 ==
5674 13:19:20.822909 Dram Type= 6, Freq= 0, CH_1, rank 0
5675 13:19:20.825910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5676 13:19:20.826029 ==
5677 13:19:20.829649 [Gating] SW mode calibration
5678 13:19:20.836437 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5679 13:19:20.842606 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5680 13:19:20.845688 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5681 13:19:20.852638 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5682 13:19:20.855694 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5683 13:19:20.859167 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5684 13:19:20.865336 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5685 13:19:20.869190 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5686 13:19:20.872424 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5687 13:19:20.875545 0 14 28 | B1->B0 | 2e2e 2525 | 0 0 | (0 0) (0 0)
5688 13:19:20.882307 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5689 13:19:20.885188 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5690 13:19:20.888432 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5691 13:19:20.895584 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5692 13:19:20.898898 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5693 13:19:20.901898 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5694 13:19:20.908600 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5695 13:19:20.911797 0 15 28 | B1->B0 | 3737 403f | 0 1 | (0 0) (1 1)
5696 13:19:20.915009 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5697 13:19:20.922017 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5698 13:19:20.925095 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5699 13:19:20.928468 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5700 13:19:20.935034 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5701 13:19:20.938449 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5702 13:19:20.941377 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5703 13:19:20.947922 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5704 13:19:20.951581 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5705 13:19:20.954603 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5706 13:19:20.961540 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5707 13:19:20.964438 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5708 13:19:20.967967 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5709 13:19:20.974691 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5710 13:19:20.977811 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5711 13:19:20.980993 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5712 13:19:20.987845 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5713 13:19:20.991064 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5714 13:19:20.994042 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5715 13:19:21.000961 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5716 13:19:21.003716 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5717 13:19:21.010565 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5718 13:19:21.013897 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5719 13:19:21.017161 Total UI for P1: 0, mck2ui 16
5720 13:19:21.020799 best dqsien dly found for B0: ( 1, 2, 22)
5721 13:19:21.024045 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5722 13:19:21.027099 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5723 13:19:21.030260 Total UI for P1: 0, mck2ui 16
5724 13:19:21.033965 best dqsien dly found for B1: ( 1, 2, 26)
5725 13:19:21.037157 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5726 13:19:21.043573 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5727 13:19:21.043670
5728 13:19:21.046851 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5729 13:19:21.050322 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5730 13:19:21.053662 [Gating] SW calibration Done
5731 13:19:21.053745 ==
5732 13:19:21.057092 Dram Type= 6, Freq= 0, CH_1, rank 0
5733 13:19:21.060015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 13:19:21.060084 ==
5735 13:19:21.063197 RX Vref Scan: 0
5736 13:19:21.063272
5737 13:19:21.063329 RX Vref 0 -> 0, step: 1
5738 13:19:21.063382
5739 13:19:21.066401 RX Delay -80 -> 252, step: 8
5740 13:19:21.070162 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5741 13:19:21.076561 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5742 13:19:21.079724 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5743 13:19:21.082912 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5744 13:19:21.086625 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5745 13:19:21.089751 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5746 13:19:21.092877 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5747 13:19:21.099770 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5748 13:19:21.102900 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5749 13:19:21.106454 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5750 13:19:21.109497 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5751 13:19:21.113158 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5752 13:19:21.119340 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5753 13:19:21.122804 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5754 13:19:21.126121 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5755 13:19:21.129413 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5756 13:19:21.129490 ==
5757 13:19:21.132246 Dram Type= 6, Freq= 0, CH_1, rank 0
5758 13:19:21.135892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 13:19:21.135969 ==
5760 13:19:21.139113 DQS Delay:
5761 13:19:21.139211 DQS0 = 0, DQS1 = 0
5762 13:19:21.142756 DQM Delay:
5763 13:19:21.142831 DQM0 = 100, DQM1 = 91
5764 13:19:21.142889 DQ Delay:
5765 13:19:21.145969 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =99
5766 13:19:21.149000 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5767 13:19:21.152733 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =83
5768 13:19:21.155608 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5769 13:19:21.155683
5770 13:19:21.158917
5771 13:19:21.159027 ==
5772 13:19:21.162643 Dram Type= 6, Freq= 0, CH_1, rank 0
5773 13:19:21.165547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5774 13:19:21.165628 ==
5775 13:19:21.165688
5776 13:19:21.165779
5777 13:19:21.169327 TX Vref Scan disable
5778 13:19:21.169407 == TX Byte 0 ==
5779 13:19:21.175625 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5780 13:19:21.178832 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5781 13:19:21.178907 == TX Byte 1 ==
5782 13:19:21.185274 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5783 13:19:21.189078 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5784 13:19:21.189155 ==
5785 13:19:21.192144 Dram Type= 6, Freq= 0, CH_1, rank 0
5786 13:19:21.195295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5787 13:19:21.195394 ==
5788 13:19:21.195501
5789 13:19:21.195556
5790 13:19:21.198484 TX Vref Scan disable
5791 13:19:21.202293 == TX Byte 0 ==
5792 13:19:21.205409 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5793 13:19:21.208412 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5794 13:19:21.212238 == TX Byte 1 ==
5795 13:19:21.215101 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5796 13:19:21.218770 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5797 13:19:21.218846
5798 13:19:21.221888 [DATLAT]
5799 13:19:21.221981 Freq=933, CH1 RK0
5800 13:19:21.222063
5801 13:19:21.225128 DATLAT Default: 0xd
5802 13:19:21.225222 0, 0xFFFF, sum = 0
5803 13:19:21.228186 1, 0xFFFF, sum = 0
5804 13:19:21.228266 2, 0xFFFF, sum = 0
5805 13:19:21.231875 3, 0xFFFF, sum = 0
5806 13:19:21.231952 4, 0xFFFF, sum = 0
5807 13:19:21.234969 5, 0xFFFF, sum = 0
5808 13:19:21.235051 6, 0xFFFF, sum = 0
5809 13:19:21.238312 7, 0xFFFF, sum = 0
5810 13:19:21.238389 8, 0xFFFF, sum = 0
5811 13:19:21.241454 9, 0xFFFF, sum = 0
5812 13:19:21.241531 10, 0x0, sum = 1
5813 13:19:21.244671 11, 0x0, sum = 2
5814 13:19:21.244780 12, 0x0, sum = 3
5815 13:19:21.248304 13, 0x0, sum = 4
5816 13:19:21.248381 best_step = 11
5817 13:19:21.248439
5818 13:19:21.248493 ==
5819 13:19:21.251385 Dram Type= 6, Freq= 0, CH_1, rank 0
5820 13:19:21.258191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 13:19:21.258271 ==
5822 13:19:21.258331 RX Vref Scan: 1
5823 13:19:21.258389
5824 13:19:21.261277 RX Vref 0 -> 0, step: 1
5825 13:19:21.261352
5826 13:19:21.264949 RX Delay -69 -> 252, step: 4
5827 13:19:21.265024
5828 13:19:21.267847 Set Vref, RX VrefLevel [Byte0]: 51
5829 13:19:21.271361 [Byte1]: 55
5830 13:19:21.271493
5831 13:19:21.274502 Final RX Vref Byte 0 = 51 to rank0
5832 13:19:21.277641 Final RX Vref Byte 1 = 55 to rank0
5833 13:19:21.280838 Final RX Vref Byte 0 = 51 to rank1
5834 13:19:21.284647 Final RX Vref Byte 1 = 55 to rank1==
5835 13:19:21.287653 Dram Type= 6, Freq= 0, CH_1, rank 0
5836 13:19:21.291136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5837 13:19:21.294609 ==
5838 13:19:21.294714 DQS Delay:
5839 13:19:21.294776 DQS0 = 0, DQS1 = 0
5840 13:19:21.297857 DQM Delay:
5841 13:19:21.297933 DQM0 = 100, DQM1 = 94
5842 13:19:21.301060 DQ Delay:
5843 13:19:21.304234 DQ0 =104, DQ1 =98, DQ2 =92, DQ3 =98
5844 13:19:21.307987 DQ4 =98, DQ5 =110, DQ6 =110, DQ7 =96
5845 13:19:21.308067 DQ8 =82, DQ9 =84, DQ10 =96, DQ11 =84
5846 13:19:21.314140 DQ12 =102, DQ13 =102, DQ14 =104, DQ15 =104
5847 13:19:21.314239
5848 13:19:21.314317
5849 13:19:21.320586 [DQSOSCAuto] RK0, (LSB)MR18= 0x1909, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5850 13:19:21.324441 CH1 RK0: MR19=505, MR18=1909
5851 13:19:21.330733 CH1_RK0: MR19=0x505, MR18=0x1909, DQSOSC=413, MR23=63, INC=63, DEC=42
5852 13:19:21.330821
5853 13:19:21.333752 ----->DramcWriteLeveling(PI) begin...
5854 13:19:21.333831 ==
5855 13:19:21.336954 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 13:19:21.340819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 13:19:21.340900 ==
5858 13:19:21.344031 Write leveling (Byte 0): 24 => 24
5859 13:19:21.347017 Write leveling (Byte 1): 30 => 30
5860 13:19:21.350273 DramcWriteLeveling(PI) end<-----
5861 13:19:21.350349
5862 13:19:21.350451 ==
5863 13:19:21.353688 Dram Type= 6, Freq= 0, CH_1, rank 1
5864 13:19:21.356845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5865 13:19:21.360515 ==
5866 13:19:21.360592 [Gating] SW mode calibration
5867 13:19:21.370317 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5868 13:19:21.373462 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5869 13:19:21.376905 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5870 13:19:21.383380 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5871 13:19:21.386592 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5872 13:19:21.389786 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5873 13:19:21.396504 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5874 13:19:21.399881 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5875 13:19:21.402929 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5876 13:19:21.409937 0 14 28 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
5877 13:19:21.413006 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5878 13:19:21.416170 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5879 13:19:21.422679 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5880 13:19:21.426482 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5881 13:19:21.429770 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5882 13:19:21.436129 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5883 13:19:21.439187 0 15 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5884 13:19:21.443035 0 15 28 | B1->B0 | 4040 3333 | 0 0 | (0 0) (1 1)
5885 13:19:21.449450 1 0 0 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
5886 13:19:21.452330 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5887 13:19:21.456167 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5888 13:19:21.462339 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5889 13:19:21.465819 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5890 13:19:21.469183 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5891 13:19:21.475700 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5892 13:19:21.479044 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5893 13:19:21.482278 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5894 13:19:21.488572 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5895 13:19:21.492057 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5896 13:19:21.495145 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5897 13:19:21.501951 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5898 13:19:21.505550 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5899 13:19:21.508521 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5900 13:19:21.515332 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5901 13:19:21.518441 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5902 13:19:21.521950 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5903 13:19:21.528619 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5904 13:19:21.531824 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5905 13:19:21.535045 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5906 13:19:21.541841 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5907 13:19:21.544944 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5908 13:19:21.548056 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5909 13:19:21.551792 Total UI for P1: 0, mck2ui 16
5910 13:19:21.554926 best dqsien dly found for B1: ( 1, 2, 24)
5911 13:19:21.561341 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5912 13:19:21.561426 Total UI for P1: 0, mck2ui 16
5913 13:19:21.568319 best dqsien dly found for B0: ( 1, 2, 26)
5914 13:19:21.571377 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5915 13:19:21.574528 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5916 13:19:21.574607
5917 13:19:21.578081 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5918 13:19:21.580959 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5919 13:19:21.585081 [Gating] SW calibration Done
5920 13:19:21.585162 ==
5921 13:19:21.587891 Dram Type= 6, Freq= 0, CH_1, rank 1
5922 13:19:21.591196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5923 13:19:21.591277 ==
5924 13:19:21.594542 RX Vref Scan: 0
5925 13:19:21.594620
5926 13:19:21.594679 RX Vref 0 -> 0, step: 1
5927 13:19:21.597664
5928 13:19:21.597741 RX Delay -80 -> 252, step: 8
5929 13:19:21.604195 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5930 13:19:21.607443 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5931 13:19:21.611084 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5932 13:19:21.614489 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5933 13:19:21.617990 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5934 13:19:21.621111 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5935 13:19:21.627319 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5936 13:19:21.630917 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5937 13:19:21.633898 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5938 13:19:21.637689 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5939 13:19:21.640824 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5940 13:19:21.643912 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5941 13:19:21.650893 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5942 13:19:21.653877 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5943 13:19:21.656974 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5944 13:19:21.660624 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5945 13:19:21.660706 ==
5946 13:19:21.663875 Dram Type= 6, Freq= 0, CH_1, rank 1
5947 13:19:21.670666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5948 13:19:21.670750 ==
5949 13:19:21.670812 DQS Delay:
5950 13:19:21.670866 DQS0 = 0, DQS1 = 0
5951 13:19:21.673800 DQM Delay:
5952 13:19:21.673865 DQM0 = 100, DQM1 = 91
5953 13:19:21.677012 DQ Delay:
5954 13:19:21.680203 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5955 13:19:21.683343 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5956 13:19:21.686920 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =87
5957 13:19:21.689958 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5958 13:19:21.690053
5959 13:19:21.690136
5960 13:19:21.690219 ==
5961 13:19:21.693690 Dram Type= 6, Freq= 0, CH_1, rank 1
5962 13:19:21.696880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5963 13:19:21.696973 ==
5964 13:19:21.697066
5965 13:19:21.697147
5966 13:19:21.700021 TX Vref Scan disable
5967 13:19:21.703612 == TX Byte 0 ==
5968 13:19:21.706475 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5969 13:19:21.709987 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5970 13:19:21.712871 == TX Byte 1 ==
5971 13:19:21.716419 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5972 13:19:21.719574 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5973 13:19:21.719653 ==
5974 13:19:21.722778 Dram Type= 6, Freq= 0, CH_1, rank 1
5975 13:19:21.726230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5976 13:19:21.729496 ==
5977 13:19:21.729583
5978 13:19:21.729642
5979 13:19:21.729696 TX Vref Scan disable
5980 13:19:21.733182 == TX Byte 0 ==
5981 13:19:21.736568 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5982 13:19:21.743365 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5983 13:19:21.743502 == TX Byte 1 ==
5984 13:19:21.746569 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5985 13:19:21.753338 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5986 13:19:21.753421
5987 13:19:21.753481 [DATLAT]
5988 13:19:21.753534 Freq=933, CH1 RK1
5989 13:19:21.753586
5990 13:19:21.756471 DATLAT Default: 0xb
5991 13:19:21.756548 0, 0xFFFF, sum = 0
5992 13:19:21.759599 1, 0xFFFF, sum = 0
5993 13:19:21.763385 2, 0xFFFF, sum = 0
5994 13:19:21.763482 3, 0xFFFF, sum = 0
5995 13:19:21.766624 4, 0xFFFF, sum = 0
5996 13:19:21.766692 5, 0xFFFF, sum = 0
5997 13:19:21.769693 6, 0xFFFF, sum = 0
5998 13:19:21.769760 7, 0xFFFF, sum = 0
5999 13:19:21.772839 8, 0xFFFF, sum = 0
6000 13:19:21.772904 9, 0xFFFF, sum = 0
6001 13:19:21.776073 10, 0x0, sum = 1
6002 13:19:21.776150 11, 0x0, sum = 2
6003 13:19:21.779797 12, 0x0, sum = 3
6004 13:19:21.779873 13, 0x0, sum = 4
6005 13:19:21.779932 best_step = 11
6006 13:19:21.779994
6007 13:19:21.782963 ==
6008 13:19:21.786145 Dram Type= 6, Freq= 0, CH_1, rank 1
6009 13:19:21.789276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6010 13:19:21.789348 ==
6011 13:19:21.789405 RX Vref Scan: 0
6012 13:19:21.789459
6013 13:19:21.792934 RX Vref 0 -> 0, step: 1
6014 13:19:21.793000
6015 13:19:21.796009 RX Delay -61 -> 252, step: 4
6016 13:19:21.802735 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
6017 13:19:21.805864 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
6018 13:19:21.809001 iDelay=207, Bit 2, Center 88 (-1 ~ 178) 180
6019 13:19:21.812089 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6020 13:19:21.815561 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
6021 13:19:21.821981 iDelay=207, Bit 5, Center 108 (19 ~ 198) 180
6022 13:19:21.825526 iDelay=207, Bit 6, Center 112 (19 ~ 206) 188
6023 13:19:21.828543 iDelay=207, Bit 7, Center 96 (3 ~ 190) 188
6024 13:19:21.832181 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
6025 13:19:21.835737 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6026 13:19:21.838645 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
6027 13:19:21.845140 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6028 13:19:21.848799 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
6029 13:19:21.852074 iDelay=207, Bit 13, Center 100 (7 ~ 194) 188
6030 13:19:21.855150 iDelay=207, Bit 14, Center 102 (15 ~ 190) 176
6031 13:19:21.858293 iDelay=207, Bit 15, Center 104 (15 ~ 194) 180
6032 13:19:21.861996 ==
6033 13:19:21.865100 Dram Type= 6, Freq= 0, CH_1, rank 1
6034 13:19:21.868284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6035 13:19:21.868381 ==
6036 13:19:21.868466 DQS Delay:
6037 13:19:21.871394 DQS0 = 0, DQS1 = 0
6038 13:19:21.871530 DQM Delay:
6039 13:19:21.875158 DQM0 = 99, DQM1 = 94
6040 13:19:21.875249 DQ Delay:
6041 13:19:21.878252 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =98
6042 13:19:21.881504 DQ4 =98, DQ5 =108, DQ6 =112, DQ7 =96
6043 13:19:21.884624 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =84
6044 13:19:21.888467 DQ12 =104, DQ13 =100, DQ14 =102, DQ15 =104
6045 13:19:21.888542
6046 13:19:21.888600
6047 13:19:21.897910 [DQSOSCAuto] RK1, (LSB)MR18= 0x801, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
6048 13:19:21.897997 CH1 RK1: MR19=505, MR18=801
6049 13:19:21.904543 CH1_RK1: MR19=0x505, MR18=0x801, DQSOSC=419, MR23=63, INC=61, DEC=41
6050 13:19:21.908277 [RxdqsGatingPostProcess] freq 933
6051 13:19:21.914617 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6052 13:19:21.917525 best DQS0 dly(2T, 0.5T) = (0, 10)
6053 13:19:21.921303 best DQS1 dly(2T, 0.5T) = (0, 10)
6054 13:19:21.924413 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6055 13:19:21.927566 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6056 13:19:21.931129 best DQS0 dly(2T, 0.5T) = (0, 10)
6057 13:19:21.931200 best DQS1 dly(2T, 0.5T) = (0, 10)
6058 13:19:21.934285 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6059 13:19:21.937916 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6060 13:19:21.940960 Pre-setting of DQS Precalculation
6061 13:19:21.947560 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6062 13:19:21.953946 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6063 13:19:21.960767 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6064 13:19:21.960852
6065 13:19:21.960910
6066 13:19:21.963731 [Calibration Summary] 1866 Mbps
6067 13:19:21.967143 CH 0, Rank 0
6068 13:19:21.967221 SW Impedance : PASS
6069 13:19:21.970330 DUTY Scan : NO K
6070 13:19:21.974190 ZQ Calibration : PASS
6071 13:19:21.974265 Jitter Meter : NO K
6072 13:19:21.976879 CBT Training : PASS
6073 13:19:21.976953 Write leveling : PASS
6074 13:19:21.980547 RX DQS gating : PASS
6075 13:19:21.983753 RX DQ/DQS(RDDQC) : PASS
6076 13:19:21.983819 TX DQ/DQS : PASS
6077 13:19:21.986879 RX DATLAT : PASS
6078 13:19:21.990061 RX DQ/DQS(Engine): PASS
6079 13:19:21.990154 TX OE : NO K
6080 13:19:21.993828 All Pass.
6081 13:19:21.993903
6082 13:19:21.993960 CH 0, Rank 1
6083 13:19:21.996971 SW Impedance : PASS
6084 13:19:21.997046 DUTY Scan : NO K
6085 13:19:22.000136 ZQ Calibration : PASS
6086 13:19:22.003147 Jitter Meter : NO K
6087 13:19:22.003221 CBT Training : PASS
6088 13:19:22.006660 Write leveling : PASS
6089 13:19:22.009753 RX DQS gating : PASS
6090 13:19:22.009827 RX DQ/DQS(RDDQC) : PASS
6091 13:19:22.013446 TX DQ/DQS : PASS
6092 13:19:22.016571 RX DATLAT : PASS
6093 13:19:22.016647 RX DQ/DQS(Engine): PASS
6094 13:19:22.019713 TX OE : NO K
6095 13:19:22.019811 All Pass.
6096 13:19:22.019893
6097 13:19:22.023382 CH 1, Rank 0
6098 13:19:22.023492 SW Impedance : PASS
6099 13:19:22.026414 DUTY Scan : NO K
6100 13:19:22.029480 ZQ Calibration : PASS
6101 13:19:22.029555 Jitter Meter : NO K
6102 13:19:22.032677 CBT Training : PASS
6103 13:19:22.036363 Write leveling : PASS
6104 13:19:22.036438 RX DQS gating : PASS
6105 13:19:22.039333 RX DQ/DQS(RDDQC) : PASS
6106 13:19:22.042886 TX DQ/DQS : PASS
6107 13:19:22.042961 RX DATLAT : PASS
6108 13:19:22.045926 RX DQ/DQS(Engine): PASS
6109 13:19:22.049454 TX OE : NO K
6110 13:19:22.049536 All Pass.
6111 13:19:22.049625
6112 13:19:22.049679 CH 1, Rank 1
6113 13:19:22.052915 SW Impedance : PASS
6114 13:19:22.055974 DUTY Scan : NO K
6115 13:19:22.056049 ZQ Calibration : PASS
6116 13:19:22.059214 Jitter Meter : NO K
6117 13:19:22.059313 CBT Training : PASS
6118 13:19:22.062907 Write leveling : PASS
6119 13:19:22.066087 RX DQS gating : PASS
6120 13:19:22.066162 RX DQ/DQS(RDDQC) : PASS
6121 13:19:22.069234 TX DQ/DQS : PASS
6122 13:19:22.072363 RX DATLAT : PASS
6123 13:19:22.072437 RX DQ/DQS(Engine): PASS
6124 13:19:22.075733 TX OE : NO K
6125 13:19:22.075838 All Pass.
6126 13:19:22.075895
6127 13:19:22.078982 DramC Write-DBI off
6128 13:19:22.082481 PER_BANK_REFRESH: Hybrid Mode
6129 13:19:22.082556 TX_TRACKING: ON
6130 13:19:22.092498 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6131 13:19:22.095630 [FAST_K] Save calibration result to emmc
6132 13:19:22.099382 dramc_set_vcore_voltage set vcore to 650000
6133 13:19:22.102432 Read voltage for 400, 6
6134 13:19:22.102507 Vio18 = 0
6135 13:19:22.105581 Vcore = 650000
6136 13:19:22.105656 Vdram = 0
6137 13:19:22.105713 Vddq = 0
6138 13:19:22.105766 Vmddr = 0
6139 13:19:22.112237 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6140 13:19:22.118554 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6141 13:19:22.118636 MEM_TYPE=3, freq_sel=20
6142 13:19:22.122227 sv_algorithm_assistance_LP4_800
6143 13:19:22.125233 ============ PULL DRAM RESETB DOWN ============
6144 13:19:22.132200 ========== PULL DRAM RESETB DOWN end =========
6145 13:19:22.135239 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6146 13:19:22.138581 ===================================
6147 13:19:22.141577 LPDDR4 DRAM CONFIGURATION
6148 13:19:22.145191 ===================================
6149 13:19:22.145268 EX_ROW_EN[0] = 0x0
6150 13:19:22.148605 EX_ROW_EN[1] = 0x0
6151 13:19:22.148681 LP4Y_EN = 0x0
6152 13:19:22.151821 WORK_FSP = 0x0
6153 13:19:22.151896 WL = 0x2
6154 13:19:22.155306 RL = 0x2
6155 13:19:22.158113 BL = 0x2
6156 13:19:22.158195 RPST = 0x0
6157 13:19:22.161586 RD_PRE = 0x0
6158 13:19:22.161663 WR_PRE = 0x1
6159 13:19:22.164717 WR_PST = 0x0
6160 13:19:22.164792 DBI_WR = 0x0
6161 13:19:22.168466 DBI_RD = 0x0
6162 13:19:22.168543 OTF = 0x1
6163 13:19:22.171585 ===================================
6164 13:19:22.174775 ===================================
6165 13:19:22.177862 ANA top config
6166 13:19:22.181604 ===================================
6167 13:19:22.181681 DLL_ASYNC_EN = 0
6168 13:19:22.184929 ALL_SLAVE_EN = 1
6169 13:19:22.188208 NEW_RANK_MODE = 1
6170 13:19:22.191289 DLL_IDLE_MODE = 1
6171 13:19:22.194434 LP45_APHY_COMB_EN = 1
6172 13:19:22.194509 TX_ODT_DIS = 1
6173 13:19:22.197767 NEW_8X_MODE = 1
6174 13:19:22.201195 ===================================
6175 13:19:22.204722 ===================================
6176 13:19:22.207523 data_rate = 800
6177 13:19:22.210728 CKR = 1
6178 13:19:22.214338 DQ_P2S_RATIO = 4
6179 13:19:22.217453 ===================================
6180 13:19:22.217530 CA_P2S_RATIO = 4
6181 13:19:22.221327 DQ_CA_OPEN = 0
6182 13:19:22.224296 DQ_SEMI_OPEN = 1
6183 13:19:22.227393 CA_SEMI_OPEN = 1
6184 13:19:22.231011 CA_FULL_RATE = 0
6185 13:19:22.234228 DQ_CKDIV4_EN = 0
6186 13:19:22.237428 CA_CKDIV4_EN = 1
6187 13:19:22.237503 CA_PREDIV_EN = 0
6188 13:19:22.240428 PH8_DLY = 0
6189 13:19:22.244173 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6190 13:19:22.247409 DQ_AAMCK_DIV = 0
6191 13:19:22.250687 CA_AAMCK_DIV = 0
6192 13:19:22.254277 CA_ADMCK_DIV = 4
6193 13:19:22.254354 DQ_TRACK_CA_EN = 0
6194 13:19:22.257233 CA_PICK = 800
6195 13:19:22.260848 CA_MCKIO = 400
6196 13:19:22.263879 MCKIO_SEMI = 400
6197 13:19:22.267422 PLL_FREQ = 3016
6198 13:19:22.270636 DQ_UI_PI_RATIO = 32
6199 13:19:22.273608 CA_UI_PI_RATIO = 32
6200 13:19:22.277403 ===================================
6201 13:19:22.280434 ===================================
6202 13:19:22.280510 memory_type:LPDDR4
6203 13:19:22.283514 GP_NUM : 10
6204 13:19:22.286763 SRAM_EN : 1
6205 13:19:22.286838 MD32_EN : 0
6206 13:19:22.290505 ===================================
6207 13:19:22.293802 [ANA_INIT] >>>>>>>>>>>>>>
6208 13:19:22.297012 <<<<<< [CONFIGURE PHASE]: ANA_TX
6209 13:19:22.300030 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6210 13:19:22.303677 ===================================
6211 13:19:22.306735 data_rate = 800,PCW = 0X7400
6212 13:19:22.310465 ===================================
6213 13:19:22.313763 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6214 13:19:22.316783 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6215 13:19:22.329832 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6216 13:19:22.333463 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6217 13:19:22.336570 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6218 13:19:22.339656 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6219 13:19:22.343424 [ANA_INIT] flow start
6220 13:19:22.346696 [ANA_INIT] PLL >>>>>>>>
6221 13:19:22.346773 [ANA_INIT] PLL <<<<<<<<
6222 13:19:22.349801 [ANA_INIT] MIDPI >>>>>>>>
6223 13:19:22.352917 [ANA_INIT] MIDPI <<<<<<<<
6224 13:19:22.352994 [ANA_INIT] DLL >>>>>>>>
6225 13:19:22.356611 [ANA_INIT] flow end
6226 13:19:22.359645 ============ LP4 DIFF to SE enter ============
6227 13:19:22.362623 ============ LP4 DIFF to SE exit ============
6228 13:19:22.366108 [ANA_INIT] <<<<<<<<<<<<<
6229 13:19:22.369268 [Flow] Enable top DCM control >>>>>
6230 13:19:22.373004 [Flow] Enable top DCM control <<<<<
6231 13:19:22.376018 Enable DLL master slave shuffle
6232 13:19:22.382742 ==============================================================
6233 13:19:22.382829 Gating Mode config
6234 13:19:22.389577 ==============================================================
6235 13:19:22.392728 Config description:
6236 13:19:22.399139 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6237 13:19:22.405982 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6238 13:19:22.412426 SELPH_MODE 0: By rank 1: By Phase
6239 13:19:22.418968 ==============================================================
6240 13:19:22.422111 GAT_TRACK_EN = 0
6241 13:19:22.422194 RX_GATING_MODE = 2
6242 13:19:22.425816 RX_GATING_TRACK_MODE = 2
6243 13:19:22.428772 SELPH_MODE = 1
6244 13:19:22.432227 PICG_EARLY_EN = 1
6245 13:19:22.435296 VALID_LAT_VALUE = 1
6246 13:19:22.442074 ==============================================================
6247 13:19:22.445110 Enter into Gating configuration >>>>
6248 13:19:22.448887 Exit from Gating configuration <<<<
6249 13:19:22.452065 Enter into DVFS_PRE_config >>>>>
6250 13:19:22.462108 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6251 13:19:22.465325 Exit from DVFS_PRE_config <<<<<
6252 13:19:22.468441 Enter into PICG configuration >>>>
6253 13:19:22.471367 Exit from PICG configuration <<<<
6254 13:19:22.474894 [RX_INPUT] configuration >>>>>
6255 13:19:22.477993 [RX_INPUT] configuration <<<<<
6256 13:19:22.481792 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6257 13:19:22.488299 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6258 13:19:22.494627 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6259 13:19:22.501641 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6260 13:19:22.504700 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6261 13:19:22.511359 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6262 13:19:22.517665 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6263 13:19:22.520850 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6264 13:19:22.524424 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6265 13:19:22.527396 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6266 13:19:22.534347 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6267 13:19:22.537763 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6268 13:19:22.540656 ===================================
6269 13:19:22.544133 LPDDR4 DRAM CONFIGURATION
6270 13:19:22.546986 ===================================
6271 13:19:22.547090 EX_ROW_EN[0] = 0x0
6272 13:19:22.550754 EX_ROW_EN[1] = 0x0
6273 13:19:22.550835 LP4Y_EN = 0x0
6274 13:19:22.553898 WORK_FSP = 0x0
6275 13:19:22.554004 WL = 0x2
6276 13:19:22.557069 RL = 0x2
6277 13:19:22.557171 BL = 0x2
6278 13:19:22.560736 RPST = 0x0
6279 13:19:22.563891 RD_PRE = 0x0
6280 13:19:22.563968 WR_PRE = 0x1
6281 13:19:22.566991 WR_PST = 0x0
6282 13:19:22.567066 DBI_WR = 0x0
6283 13:19:22.570128 DBI_RD = 0x0
6284 13:19:22.570204 OTF = 0x1
6285 13:19:22.573803 ===================================
6286 13:19:22.576880 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6287 13:19:22.583354 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6288 13:19:22.587075 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6289 13:19:22.590190 ===================================
6290 13:19:22.593381 LPDDR4 DRAM CONFIGURATION
6291 13:19:22.596775 ===================================
6292 13:19:22.596880 EX_ROW_EN[0] = 0x10
6293 13:19:22.600025 EX_ROW_EN[1] = 0x0
6294 13:19:22.600145 LP4Y_EN = 0x0
6295 13:19:22.603387 WORK_FSP = 0x0
6296 13:19:22.603503 WL = 0x2
6297 13:19:22.606370 RL = 0x2
6298 13:19:22.610066 BL = 0x2
6299 13:19:22.610143 RPST = 0x0
6300 13:19:22.613184 RD_PRE = 0x0
6301 13:19:22.613262 WR_PRE = 0x1
6302 13:19:22.616704 WR_PST = 0x0
6303 13:19:22.616791 DBI_WR = 0x0
6304 13:19:22.619983 DBI_RD = 0x0
6305 13:19:22.620077 OTF = 0x1
6306 13:19:22.622956 ===================================
6307 13:19:22.629904 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6308 13:19:22.633637 nWR fixed to 30
6309 13:19:22.636852 [ModeRegInit_LP4] CH0 RK0
6310 13:19:22.636930 [ModeRegInit_LP4] CH0 RK1
6311 13:19:22.639997 [ModeRegInit_LP4] CH1 RK0
6312 13:19:22.643609 [ModeRegInit_LP4] CH1 RK1
6313 13:19:22.643710 match AC timing 19
6314 13:19:22.649901 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6315 13:19:22.653201 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6316 13:19:22.656360 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6317 13:19:22.662987 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6318 13:19:22.666769 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6319 13:19:22.666870 ==
6320 13:19:22.670019 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 13:19:22.673161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 13:19:22.673254 ==
6323 13:19:22.680137 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6324 13:19:22.686547 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6325 13:19:22.689573 [CA 0] Center 36 (8~64) winsize 57
6326 13:19:22.692972 [CA 1] Center 36 (8~64) winsize 57
6327 13:19:22.696243 [CA 2] Center 36 (8~64) winsize 57
6328 13:19:22.700066 [CA 3] Center 36 (8~64) winsize 57
6329 13:19:22.703140 [CA 4] Center 36 (8~64) winsize 57
6330 13:19:22.703246 [CA 5] Center 36 (8~64) winsize 57
6331 13:19:22.706185
6332 13:19:22.709689 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6333 13:19:22.709788
6334 13:19:22.713142 [CATrainingPosCal] consider 1 rank data
6335 13:19:22.716150 u2DelayCellTimex100 = 270/100 ps
6336 13:19:22.719273 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6337 13:19:22.722410 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6338 13:19:22.726219 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6339 13:19:22.729252 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6340 13:19:22.732328 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6341 13:19:22.736083 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6342 13:19:22.736218
6343 13:19:22.742216 CA PerBit enable=1, Macro0, CA PI delay=36
6344 13:19:22.742315
6345 13:19:22.742399 [CBTSetCACLKResult] CA Dly = 36
6346 13:19:22.746129 CS Dly: 1 (0~32)
6347 13:19:22.746219 ==
6348 13:19:22.749172 Dram Type= 6, Freq= 0, CH_0, rank 1
6349 13:19:22.752388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 13:19:22.752484 ==
6351 13:19:22.758998 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6352 13:19:22.765343 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6353 13:19:22.768655 [CA 0] Center 36 (8~64) winsize 57
6354 13:19:22.772171 [CA 1] Center 36 (8~64) winsize 57
6355 13:19:22.775118 [CA 2] Center 36 (8~64) winsize 57
6356 13:19:22.778380 [CA 3] Center 36 (8~64) winsize 57
6357 13:19:22.778458 [CA 4] Center 36 (8~64) winsize 57
6358 13:19:22.782141 [CA 5] Center 36 (8~64) winsize 57
6359 13:19:22.782216
6360 13:19:22.788418 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6361 13:19:22.788496
6362 13:19:22.791609 [CATrainingPosCal] consider 2 rank data
6363 13:19:22.795255 u2DelayCellTimex100 = 270/100 ps
6364 13:19:22.798266 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6365 13:19:22.801767 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6366 13:19:22.805043 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6367 13:19:22.808072 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6368 13:19:22.811747 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6369 13:19:22.814906 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6370 13:19:22.814980
6371 13:19:22.818421 CA PerBit enable=1, Macro0, CA PI delay=36
6372 13:19:22.818496
6373 13:19:22.821217 [CBTSetCACLKResult] CA Dly = 36
6374 13:19:22.824729 CS Dly: 1 (0~32)
6375 13:19:22.824806
6376 13:19:22.827939 ----->DramcWriteLeveling(PI) begin...
6377 13:19:22.828039 ==
6378 13:19:22.831647 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 13:19:22.834616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 13:19:22.834694 ==
6381 13:19:22.837845 Write leveling (Byte 0): 40 => 8
6382 13:19:22.841459 Write leveling (Byte 1): 32 => 0
6383 13:19:22.844581 DramcWriteLeveling(PI) end<-----
6384 13:19:22.844656
6385 13:19:22.844713 ==
6386 13:19:22.847710 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 13:19:22.850872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 13:19:22.850971 ==
6389 13:19:22.854642 [Gating] SW mode calibration
6390 13:19:22.860959 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6391 13:19:22.867774 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6392 13:19:22.870777 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6393 13:19:22.877478 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6394 13:19:22.880740 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6395 13:19:22.884137 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6396 13:19:22.890956 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6397 13:19:22.894170 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6398 13:19:22.897332 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6399 13:19:22.904189 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6400 13:19:22.907225 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6401 13:19:22.910667 Total UI for P1: 0, mck2ui 16
6402 13:19:22.913846 best dqsien dly found for B0: ( 0, 14, 24)
6403 13:19:22.917063 Total UI for P1: 0, mck2ui 16
6404 13:19:22.920756 best dqsien dly found for B1: ( 0, 14, 24)
6405 13:19:22.923814 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6406 13:19:22.927249 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6407 13:19:22.927324
6408 13:19:22.930652 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6409 13:19:22.933439 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6410 13:19:22.936912 [Gating] SW calibration Done
6411 13:19:22.936991 ==
6412 13:19:22.940544 Dram Type= 6, Freq= 0, CH_0, rank 0
6413 13:19:22.944052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 13:19:22.947007 ==
6415 13:19:22.947083 RX Vref Scan: 0
6416 13:19:22.947140
6417 13:19:22.950152 RX Vref 0 -> 0, step: 1
6418 13:19:22.950226
6419 13:19:22.953867 RX Delay -410 -> 252, step: 16
6420 13:19:22.956996 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6421 13:19:22.960216 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6422 13:19:22.963350 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6423 13:19:22.970004 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6424 13:19:22.973742 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6425 13:19:22.976900 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6426 13:19:22.980008 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6427 13:19:22.986844 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6428 13:19:22.989771 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6429 13:19:22.993067 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6430 13:19:22.999438 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6431 13:19:23.003299 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6432 13:19:23.006455 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6433 13:19:23.009571 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6434 13:19:23.016260 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6435 13:19:23.019495 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6436 13:19:23.019571 ==
6437 13:19:23.023024 Dram Type= 6, Freq= 0, CH_0, rank 0
6438 13:19:23.026133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 13:19:23.026237 ==
6440 13:19:23.029372 DQS Delay:
6441 13:19:23.029476 DQS0 = 43, DQS1 = 59
6442 13:19:23.029603 DQM Delay:
6443 13:19:23.033013 DQM0 = 9, DQM1 = 11
6444 13:19:23.033106 DQ Delay:
6445 13:19:23.036134 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6446 13:19:23.039097 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6447 13:19:23.042487 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6448 13:19:23.046000 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6449 13:19:23.046095
6450 13:19:23.046176
6451 13:19:23.046254 ==
6452 13:19:23.049111 Dram Type= 6, Freq= 0, CH_0, rank 0
6453 13:19:23.052940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 13:19:23.056244 ==
6455 13:19:23.056324
6456 13:19:23.056382
6457 13:19:23.056435 TX Vref Scan disable
6458 13:19:23.059273 == TX Byte 0 ==
6459 13:19:23.062400 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6460 13:19:23.066113 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6461 13:19:23.069329 == TX Byte 1 ==
6462 13:19:23.072451 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6463 13:19:23.075368 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6464 13:19:23.075481 ==
6465 13:19:23.079037 Dram Type= 6, Freq= 0, CH_0, rank 0
6466 13:19:23.085472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 13:19:23.085551 ==
6468 13:19:23.085607
6469 13:19:23.085666
6470 13:19:23.085717 TX Vref Scan disable
6471 13:19:23.089118 == TX Byte 0 ==
6472 13:19:23.092367 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6473 13:19:23.095449 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6474 13:19:23.099209 == TX Byte 1 ==
6475 13:19:23.102189 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6476 13:19:23.105360 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6477 13:19:23.108838
6478 13:19:23.108942 [DATLAT]
6479 13:19:23.109062 Freq=400, CH0 RK0
6480 13:19:23.109141
6481 13:19:23.111932 DATLAT Default: 0xf
6482 13:19:23.111995 0, 0xFFFF, sum = 0
6483 13:19:23.115131 1, 0xFFFF, sum = 0
6484 13:19:23.115193 2, 0xFFFF, sum = 0
6485 13:19:23.118994 3, 0xFFFF, sum = 0
6486 13:19:23.122107 4, 0xFFFF, sum = 0
6487 13:19:23.122179 5, 0xFFFF, sum = 0
6488 13:19:23.125123 6, 0xFFFF, sum = 0
6489 13:19:23.125193 7, 0xFFFF, sum = 0
6490 13:19:23.128638 8, 0xFFFF, sum = 0
6491 13:19:23.128751 9, 0xFFFF, sum = 0
6492 13:19:23.132222 10, 0xFFFF, sum = 0
6493 13:19:23.132304 11, 0xFFFF, sum = 0
6494 13:19:23.135315 12, 0xFFFF, sum = 0
6495 13:19:23.135420 13, 0x0, sum = 1
6496 13:19:23.138338 14, 0x0, sum = 2
6497 13:19:23.138440 15, 0x0, sum = 3
6498 13:19:23.141982 16, 0x0, sum = 4
6499 13:19:23.142086 best_step = 14
6500 13:19:23.142168
6501 13:19:23.142246 ==
6502 13:19:23.145346 Dram Type= 6, Freq= 0, CH_0, rank 0
6503 13:19:23.148389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 13:19:23.151651 ==
6505 13:19:23.151741 RX Vref Scan: 1
6506 13:19:23.151811
6507 13:19:23.154927 RX Vref 0 -> 0, step: 1
6508 13:19:23.155026
6509 13:19:23.158426 RX Delay -359 -> 252, step: 8
6510 13:19:23.158511
6511 13:19:23.161632 Set Vref, RX VrefLevel [Byte0]: 61
6512 13:19:23.164564 [Byte1]: 49
6513 13:19:23.164630
6514 13:19:23.167989 Final RX Vref Byte 0 = 61 to rank0
6515 13:19:23.171013 Final RX Vref Byte 1 = 49 to rank0
6516 13:19:23.174915 Final RX Vref Byte 0 = 61 to rank1
6517 13:19:23.177994 Final RX Vref Byte 1 = 49 to rank1==
6518 13:19:23.181012 Dram Type= 6, Freq= 0, CH_0, rank 0
6519 13:19:23.184741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 13:19:23.187903 ==
6521 13:19:23.187971 DQS Delay:
6522 13:19:23.188025 DQS0 = 48, DQS1 = 60
6523 13:19:23.191128 DQM Delay:
6524 13:19:23.191190 DQM0 = 11, DQM1 = 11
6525 13:19:23.194313 DQ Delay:
6526 13:19:23.194375 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6527 13:19:23.197373 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6528 13:19:23.201195 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6529 13:19:23.204392 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6530 13:19:23.204474
6531 13:19:23.204531
6532 13:19:23.214402 [DQSOSCAuto] RK0, (LSB)MR18= 0xc386, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 385 ps
6533 13:19:23.217382 CH0 RK0: MR19=C0C, MR18=C386
6534 13:19:23.224160 CH0_RK0: MR19=0xC0C, MR18=0xC386, DQSOSC=385, MR23=63, INC=398, DEC=265
6535 13:19:23.224261 ==
6536 13:19:23.227269 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 13:19:23.230998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 13:19:23.231110 ==
6539 13:19:23.234093 [Gating] SW mode calibration
6540 13:19:23.240436 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6541 13:19:23.247211 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6542 13:19:23.250354 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6543 13:19:23.254099 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6544 13:19:23.260159 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6545 13:19:23.263519 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6546 13:19:23.267194 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6547 13:19:23.273672 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6548 13:19:23.276974 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6549 13:19:23.280340 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6550 13:19:23.286920 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6551 13:19:23.287023 Total UI for P1: 0, mck2ui 16
6552 13:19:23.293113 best dqsien dly found for B0: ( 0, 14, 24)
6553 13:19:23.293187 Total UI for P1: 0, mck2ui 16
6554 13:19:23.296811 best dqsien dly found for B1: ( 0, 14, 24)
6555 13:19:23.303191 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6556 13:19:23.306368 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6557 13:19:23.306458
6558 13:19:23.309509 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6559 13:19:23.313359 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6560 13:19:23.316495 [Gating] SW calibration Done
6561 13:19:23.316573 ==
6562 13:19:23.319397 Dram Type= 6, Freq= 0, CH_0, rank 1
6563 13:19:23.322961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6564 13:19:23.323037 ==
6565 13:19:23.326504 RX Vref Scan: 0
6566 13:19:23.326601
6567 13:19:23.326690 RX Vref 0 -> 0, step: 1
6568 13:19:23.326753
6569 13:19:23.329711 RX Delay -410 -> 252, step: 16
6570 13:19:23.336514 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6571 13:19:23.339556 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6572 13:19:23.342716 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6573 13:19:23.346432 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6574 13:19:23.352549 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6575 13:19:23.356273 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6576 13:19:23.359407 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6577 13:19:23.362525 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6578 13:19:23.369082 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6579 13:19:23.372454 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6580 13:19:23.375493 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6581 13:19:23.379273 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6582 13:19:23.385940 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6583 13:19:23.388908 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6584 13:19:23.392584 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6585 13:19:23.395792 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6586 13:19:23.398877 ==
6587 13:19:23.402536 Dram Type= 6, Freq= 0, CH_0, rank 1
6588 13:19:23.405895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 13:19:23.405961 ==
6590 13:19:23.406017 DQS Delay:
6591 13:19:23.409031 DQS0 = 43, DQS1 = 51
6592 13:19:23.409111 DQM Delay:
6593 13:19:23.412122 DQM0 = 9, DQM1 = 9
6594 13:19:23.412219 DQ Delay:
6595 13:19:23.415452 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0
6596 13:19:23.418524 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6597 13:19:23.422197 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6598 13:19:23.425260 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6599 13:19:23.425366
6600 13:19:23.425486
6601 13:19:23.425596 ==
6602 13:19:23.428897 Dram Type= 6, Freq= 0, CH_0, rank 1
6603 13:19:23.431897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6604 13:19:23.431981 ==
6605 13:19:23.432042
6606 13:19:23.432107
6607 13:19:23.435002 TX Vref Scan disable
6608 13:19:23.435104 == TX Byte 0 ==
6609 13:19:23.441929 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6610 13:19:23.445114 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6611 13:19:23.445192 == TX Byte 1 ==
6612 13:19:23.452034 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6613 13:19:23.455031 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6614 13:19:23.455134 ==
6615 13:19:23.458634 Dram Type= 6, Freq= 0, CH_0, rank 1
6616 13:19:23.461891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 13:19:23.461971 ==
6618 13:19:23.462038
6619 13:19:23.462093
6620 13:19:23.464955 TX Vref Scan disable
6621 13:19:23.465032 == TX Byte 0 ==
6622 13:19:23.471712 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6623 13:19:23.475331 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6624 13:19:23.475416 == TX Byte 1 ==
6625 13:19:23.481780 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6626 13:19:23.484977 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6627 13:19:23.485057
6628 13:19:23.485117 [DATLAT]
6629 13:19:23.488049 Freq=400, CH0 RK1
6630 13:19:23.488127
6631 13:19:23.488188 DATLAT Default: 0xe
6632 13:19:23.491282 0, 0xFFFF, sum = 0
6633 13:19:23.491362 1, 0xFFFF, sum = 0
6634 13:19:23.495091 2, 0xFFFF, sum = 0
6635 13:19:23.495172 3, 0xFFFF, sum = 0
6636 13:19:23.498125 4, 0xFFFF, sum = 0
6637 13:19:23.498208 5, 0xFFFF, sum = 0
6638 13:19:23.501524 6, 0xFFFF, sum = 0
6639 13:19:23.501605 7, 0xFFFF, sum = 0
6640 13:19:23.504726 8, 0xFFFF, sum = 0
6641 13:19:23.508029 9, 0xFFFF, sum = 0
6642 13:19:23.508111 10, 0xFFFF, sum = 0
6643 13:19:23.511507 11, 0xFFFF, sum = 0
6644 13:19:23.511589 12, 0xFFFF, sum = 0
6645 13:19:23.514527 13, 0x0, sum = 1
6646 13:19:23.514623 14, 0x0, sum = 2
6647 13:19:23.517642 15, 0x0, sum = 3
6648 13:19:23.517721 16, 0x0, sum = 4
6649 13:19:23.517785 best_step = 14
6650 13:19:23.521480
6651 13:19:23.521558 ==
6652 13:19:23.524630 Dram Type= 6, Freq= 0, CH_0, rank 1
6653 13:19:23.527657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6654 13:19:23.527736 ==
6655 13:19:23.527796 RX Vref Scan: 0
6656 13:19:23.527852
6657 13:19:23.531123 RX Vref 0 -> 0, step: 1
6658 13:19:23.531201
6659 13:19:23.534628 RX Delay -343 -> 252, step: 8
6660 13:19:23.541420 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6661 13:19:23.545103 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6662 13:19:23.548253 iDelay=217, Bit 2, Center -44 (-287 ~ 200) 488
6663 13:19:23.554493 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6664 13:19:23.557714 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6665 13:19:23.561459 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6666 13:19:23.564550 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6667 13:19:23.570937 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6668 13:19:23.574091 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6669 13:19:23.577708 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6670 13:19:23.580811 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6671 13:19:23.587445 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6672 13:19:23.590884 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6673 13:19:23.594006 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6674 13:19:23.600945 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6675 13:19:23.604117 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6676 13:19:23.604193 ==
6677 13:19:23.607212 Dram Type= 6, Freq= 0, CH_0, rank 1
6678 13:19:23.610235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 13:19:23.610330 ==
6680 13:19:23.613950 DQS Delay:
6681 13:19:23.614015 DQS0 = 44, DQS1 = 60
6682 13:19:23.614068 DQM Delay:
6683 13:19:23.616973 DQM0 = 7, DQM1 = 15
6684 13:19:23.617035 DQ Delay:
6685 13:19:23.620432 DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =4
6686 13:19:23.623448 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6687 13:19:23.627258 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6688 13:19:23.630419 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6689 13:19:23.630519
6690 13:19:23.630605
6691 13:19:23.637179 [DQSOSCAuto] RK1, (LSB)MR18= 0xb945, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6692 13:19:23.640631 CH0 RK1: MR19=C0C, MR18=B945
6693 13:19:23.646620 CH0_RK1: MR19=0xC0C, MR18=0xB945, DQSOSC=386, MR23=63, INC=396, DEC=264
6694 13:19:23.650290 [RxdqsGatingPostProcess] freq 400
6695 13:19:23.656694 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6696 13:19:23.659918 best DQS0 dly(2T, 0.5T) = (0, 10)
6697 13:19:23.663626 best DQS1 dly(2T, 0.5T) = (0, 10)
6698 13:19:23.666767 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6699 13:19:23.669977 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6700 13:19:23.673160 best DQS0 dly(2T, 0.5T) = (0, 10)
6701 13:19:23.673263 best DQS1 dly(2T, 0.5T) = (0, 10)
6702 13:19:23.676343 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6703 13:19:23.679980 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6704 13:19:23.683107 Pre-setting of DQS Precalculation
6705 13:19:23.689930 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6706 13:19:23.690033 ==
6707 13:19:23.693037 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 13:19:23.696107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 13:19:23.696177 ==
6710 13:19:23.703099 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6711 13:19:23.709507 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6712 13:19:23.712497 [CA 0] Center 36 (8~64) winsize 57
6713 13:19:23.716335 [CA 1] Center 36 (8~64) winsize 57
6714 13:19:23.719360 [CA 2] Center 36 (8~64) winsize 57
6715 13:19:23.719480 [CA 3] Center 36 (8~64) winsize 57
6716 13:19:23.722582 [CA 4] Center 36 (8~64) winsize 57
6717 13:19:23.726210 [CA 5] Center 36 (8~64) winsize 57
6718 13:19:23.726286
6719 13:19:23.732432 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6720 13:19:23.732534
6721 13:19:23.735550 [CATrainingPosCal] consider 1 rank data
6722 13:19:23.738742 u2DelayCellTimex100 = 270/100 ps
6723 13:19:23.742494 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6724 13:19:23.745468 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6725 13:19:23.749073 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6726 13:19:23.752307 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6727 13:19:23.755791 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6728 13:19:23.759056 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6729 13:19:23.759234
6730 13:19:23.762074 CA PerBit enable=1, Macro0, CA PI delay=36
6731 13:19:23.762140
6732 13:19:23.765759 [CBTSetCACLKResult] CA Dly = 36
6733 13:19:23.768870 CS Dly: 1 (0~32)
6734 13:19:23.768949 ==
6735 13:19:23.772173 Dram Type= 6, Freq= 0, CH_1, rank 1
6736 13:19:23.775347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 13:19:23.775437 ==
6738 13:19:23.782197 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6739 13:19:23.788652 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6740 13:19:23.791570 [CA 0] Center 36 (8~64) winsize 57
6741 13:19:23.794826 [CA 1] Center 36 (8~64) winsize 57
6742 13:19:23.794904 [CA 2] Center 36 (8~64) winsize 57
6743 13:19:23.798098 [CA 3] Center 36 (8~64) winsize 57
6744 13:19:23.801748 [CA 4] Center 36 (8~64) winsize 57
6745 13:19:23.804728 [CA 5] Center 36 (8~64) winsize 57
6746 13:19:23.804806
6747 13:19:23.808408 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6748 13:19:23.811513
6749 13:19:23.815054 [CATrainingPosCal] consider 2 rank data
6750 13:19:23.815133 u2DelayCellTimex100 = 270/100 ps
6751 13:19:23.821296 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6752 13:19:23.824819 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6753 13:19:23.827923 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6754 13:19:23.831068 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6755 13:19:23.834598 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6756 13:19:23.837893 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6757 13:19:23.837986
6758 13:19:23.841033 CA PerBit enable=1, Macro0, CA PI delay=36
6759 13:19:23.841109
6760 13:19:23.844732 [CBTSetCACLKResult] CA Dly = 36
6761 13:19:23.847783 CS Dly: 1 (0~32)
6762 13:19:23.847860
6763 13:19:23.850977 ----->DramcWriteLeveling(PI) begin...
6764 13:19:23.851054 ==
6765 13:19:23.854608 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 13:19:23.857480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 13:19:23.857557 ==
6768 13:19:23.860861 Write leveling (Byte 0): 40 => 8
6769 13:19:23.864337 Write leveling (Byte 1): 40 => 8
6770 13:19:23.867857 DramcWriteLeveling(PI) end<-----
6771 13:19:23.867933
6772 13:19:23.867991 ==
6773 13:19:23.870998 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 13:19:23.874205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 13:19:23.874282 ==
6776 13:19:23.877407 [Gating] SW mode calibration
6777 13:19:23.884254 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6778 13:19:23.890718 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6779 13:19:23.893958 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6780 13:19:23.897541 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6781 13:19:23.903778 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6782 13:19:23.907634 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6783 13:19:23.910736 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6784 13:19:23.917023 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6785 13:19:23.920679 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6786 13:19:23.923482 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6787 13:19:23.930217 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6788 13:19:23.933563 Total UI for P1: 0, mck2ui 16
6789 13:19:23.936874 best dqsien dly found for B0: ( 0, 14, 24)
6790 13:19:23.940008 Total UI for P1: 0, mck2ui 16
6791 13:19:23.943519 best dqsien dly found for B1: ( 0, 14, 24)
6792 13:19:23.947159 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6793 13:19:23.949857 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6794 13:19:23.949951
6795 13:19:23.953535 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6796 13:19:23.956446 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6797 13:19:23.960245 [Gating] SW calibration Done
6798 13:19:23.960349 ==
6799 13:19:23.963236 Dram Type= 6, Freq= 0, CH_1, rank 0
6800 13:19:23.966760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 13:19:23.966852 ==
6802 13:19:23.969713 RX Vref Scan: 0
6803 13:19:23.969820
6804 13:19:23.973180 RX Vref 0 -> 0, step: 1
6805 13:19:23.973281
6806 13:19:23.973374 RX Delay -410 -> 252, step: 16
6807 13:19:23.980435 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6808 13:19:23.983581 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6809 13:19:23.986835 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6810 13:19:23.989916 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6811 13:19:23.996696 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6812 13:19:23.999792 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6813 13:19:24.002973 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6814 13:19:24.009933 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6815 13:19:24.013187 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6816 13:19:24.016239 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6817 13:19:24.019363 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6818 13:19:24.026300 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6819 13:19:24.029364 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6820 13:19:24.032884 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6821 13:19:24.035921 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6822 13:19:24.042829 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6823 13:19:24.042927 ==
6824 13:19:24.046073 Dram Type= 6, Freq= 0, CH_1, rank 0
6825 13:19:24.049079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 13:19:24.049146 ==
6827 13:19:24.052553 DQS Delay:
6828 13:19:24.052647 DQS0 = 43, DQS1 = 51
6829 13:19:24.052727 DQM Delay:
6830 13:19:24.055938 DQM0 = 12, DQM1 = 14
6831 13:19:24.056034 DQ Delay:
6832 13:19:24.059103 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6833 13:19:24.062265 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6834 13:19:24.065741 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6835 13:19:24.068945 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6836 13:19:24.069030
6837 13:19:24.069115
6838 13:19:24.069195 ==
6839 13:19:24.072171 Dram Type= 6, Freq= 0, CH_1, rank 0
6840 13:19:24.075287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 13:19:24.078676 ==
6842 13:19:24.078776
6843 13:19:24.078860
6844 13:19:24.078969 TX Vref Scan disable
6845 13:19:24.082222 == TX Byte 0 ==
6846 13:19:24.084999 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6847 13:19:24.088822 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6848 13:19:24.092038 == TX Byte 1 ==
6849 13:19:24.095107 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6850 13:19:24.098221 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6851 13:19:24.098321 ==
6852 13:19:24.101921 Dram Type= 6, Freq= 0, CH_1, rank 0
6853 13:19:24.107994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 13:19:24.108071 ==
6855 13:19:24.108140
6856 13:19:24.108198
6857 13:19:24.108249 TX Vref Scan disable
6858 13:19:24.111748 == TX Byte 0 ==
6859 13:19:24.115058 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6860 13:19:24.118254 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6861 13:19:24.121417 == TX Byte 1 ==
6862 13:19:24.124596 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6863 13:19:24.127910 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6864 13:19:24.127988
6865 13:19:24.131118 [DATLAT]
6866 13:19:24.131193 Freq=400, CH1 RK0
6867 13:19:24.131288
6868 13:19:24.134766 DATLAT Default: 0xf
6869 13:19:24.134860 0, 0xFFFF, sum = 0
6870 13:19:24.137782 1, 0xFFFF, sum = 0
6871 13:19:24.137875 2, 0xFFFF, sum = 0
6872 13:19:24.141365 3, 0xFFFF, sum = 0
6873 13:19:24.141466 4, 0xFFFF, sum = 0
6874 13:19:24.144419 5, 0xFFFF, sum = 0
6875 13:19:24.144517 6, 0xFFFF, sum = 0
6876 13:19:24.147557 7, 0xFFFF, sum = 0
6877 13:19:24.147654 8, 0xFFFF, sum = 0
6878 13:19:24.151346 9, 0xFFFF, sum = 0
6879 13:19:24.154521 10, 0xFFFF, sum = 0
6880 13:19:24.154598 11, 0xFFFF, sum = 0
6881 13:19:24.157719 12, 0xFFFF, sum = 0
6882 13:19:24.157825 13, 0x0, sum = 1
6883 13:19:24.160781 14, 0x0, sum = 2
6884 13:19:24.160876 15, 0x0, sum = 3
6885 13:19:24.164111 16, 0x0, sum = 4
6886 13:19:24.164204 best_step = 14
6887 13:19:24.164287
6888 13:19:24.164367 ==
6889 13:19:24.167164 Dram Type= 6, Freq= 0, CH_1, rank 0
6890 13:19:24.170719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 13:19:24.170814 ==
6892 13:19:24.173835 RX Vref Scan: 1
6893 13:19:24.173910
6894 13:19:24.177248 RX Vref 0 -> 0, step: 1
6895 13:19:24.177324
6896 13:19:24.177382 RX Delay -343 -> 252, step: 8
6897 13:19:24.180458
6898 13:19:24.180555 Set Vref, RX VrefLevel [Byte0]: 51
6899 13:19:24.184148 [Byte1]: 55
6900 13:19:24.189748
6901 13:19:24.189846 Final RX Vref Byte 0 = 51 to rank0
6902 13:19:24.192931 Final RX Vref Byte 1 = 55 to rank0
6903 13:19:24.196429 Final RX Vref Byte 0 = 51 to rank1
6904 13:19:24.199911 Final RX Vref Byte 1 = 55 to rank1==
6905 13:19:24.202759 Dram Type= 6, Freq= 0, CH_1, rank 0
6906 13:19:24.209471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 13:19:24.209553 ==
6908 13:19:24.209638 DQS Delay:
6909 13:19:24.212683 DQS0 = 48, DQS1 = 56
6910 13:19:24.212758 DQM Delay:
6911 13:19:24.212829 DQM0 = 11, DQM1 = 11
6912 13:19:24.215857 DQ Delay:
6913 13:19:24.219000 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =8
6914 13:19:24.219064 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6915 13:19:24.222864 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6916 13:19:24.225963 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6917 13:19:24.226032
6918 13:19:24.229138
6919 13:19:24.236087 [DQSOSCAuto] RK0, (LSB)MR18= 0x996f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6920 13:19:24.239229 CH1 RK0: MR19=C0C, MR18=996F
6921 13:19:24.245911 CH1_RK0: MR19=0xC0C, MR18=0x996F, DQSOSC=390, MR23=63, INC=388, DEC=258
6922 13:19:24.245989 ==
6923 13:19:24.248816 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 13:19:24.252456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 13:19:24.252533 ==
6926 13:19:24.255533 [Gating] SW mode calibration
6927 13:19:24.262434 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6928 13:19:24.268731 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6929 13:19:24.272362 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6930 13:19:24.275454 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6931 13:19:24.281890 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6932 13:19:24.285522 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6933 13:19:24.289047 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6934 13:19:24.295381 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6935 13:19:24.298563 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6936 13:19:24.302169 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6937 13:19:24.308936 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6938 13:19:24.309012 Total UI for P1: 0, mck2ui 16
6939 13:19:24.311741 best dqsien dly found for B0: ( 0, 14, 24)
6940 13:19:24.315185 Total UI for P1: 0, mck2ui 16
6941 13:19:24.318409 best dqsien dly found for B1: ( 0, 14, 24)
6942 13:19:24.324983 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6943 13:19:24.328395 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6944 13:19:24.328477
6945 13:19:24.332200 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6946 13:19:24.335305 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6947 13:19:24.338342 [Gating] SW calibration Done
6948 13:19:24.338440 ==
6949 13:19:24.341479 Dram Type= 6, Freq= 0, CH_1, rank 1
6950 13:19:24.345357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6951 13:19:24.345452 ==
6952 13:19:24.348486 RX Vref Scan: 0
6953 13:19:24.348556
6954 13:19:24.348629 RX Vref 0 -> 0, step: 1
6955 13:19:24.348699
6956 13:19:24.351695 RX Delay -410 -> 252, step: 16
6957 13:19:24.357988 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6958 13:19:24.361487 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6959 13:19:24.365007 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6960 13:19:24.368163 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6961 13:19:24.375118 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6962 13:19:24.378222 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6963 13:19:24.381389 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6964 13:19:24.384545 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6965 13:19:24.391528 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6966 13:19:24.394522 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6967 13:19:24.398113 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6968 13:19:24.401019 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6969 13:19:24.407723 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6970 13:19:24.410883 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6971 13:19:24.414581 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6972 13:19:24.417722 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6973 13:19:24.420795 ==
6974 13:19:24.424388 Dram Type= 6, Freq= 0, CH_1, rank 1
6975 13:19:24.427603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6976 13:19:24.427679 ==
6977 13:19:24.427737 DQS Delay:
6978 13:19:24.430544 DQS0 = 43, DQS1 = 51
6979 13:19:24.430679 DQM Delay:
6980 13:19:24.434352 DQM0 = 12, DQM1 = 14
6981 13:19:24.434428 DQ Delay:
6982 13:19:24.437798 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6983 13:19:24.440661 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6984 13:19:24.444191 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6985 13:19:24.447648 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6986 13:19:24.447727
6987 13:19:24.447784
6988 13:19:24.447837 ==
6989 13:19:24.450688 Dram Type= 6, Freq= 0, CH_1, rank 1
6990 13:19:24.453870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6991 13:19:24.453941 ==
6992 13:19:24.454007
6993 13:19:24.454063
6994 13:19:24.457036 TX Vref Scan disable
6995 13:19:24.457100 == TX Byte 0 ==
6996 13:19:24.463877 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6997 13:19:24.467394 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6998 13:19:24.467494 == TX Byte 1 ==
6999 13:19:24.473922 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
7000 13:19:24.477057 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
7001 13:19:24.477134 ==
7002 13:19:24.480185 Dram Type= 6, Freq= 0, CH_1, rank 1
7003 13:19:24.483726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7004 13:19:24.483802 ==
7005 13:19:24.483860
7006 13:19:24.483914
7007 13:19:24.486901 TX Vref Scan disable
7008 13:19:24.486976 == TX Byte 0 ==
7009 13:19:24.493318 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
7010 13:19:24.497110 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
7011 13:19:24.497187 == TX Byte 1 ==
7012 13:19:24.503281 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
7013 13:19:24.506695 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
7014 13:19:24.506770
7015 13:19:24.506829 [DATLAT]
7016 13:19:24.510281 Freq=400, CH1 RK1
7017 13:19:24.510356
7018 13:19:24.510414 DATLAT Default: 0xe
7019 13:19:24.513308 0, 0xFFFF, sum = 0
7020 13:19:24.513384 1, 0xFFFF, sum = 0
7021 13:19:24.516420 2, 0xFFFF, sum = 0
7022 13:19:24.516532 3, 0xFFFF, sum = 0
7023 13:19:24.520180 4, 0xFFFF, sum = 0
7024 13:19:24.523341 5, 0xFFFF, sum = 0
7025 13:19:24.523461 6, 0xFFFF, sum = 0
7026 13:19:24.526506 7, 0xFFFF, sum = 0
7027 13:19:24.526572 8, 0xFFFF, sum = 0
7028 13:19:24.529676 9, 0xFFFF, sum = 0
7029 13:19:24.529741 10, 0xFFFF, sum = 0
7030 13:19:24.532926 11, 0xFFFF, sum = 0
7031 13:19:24.532995 12, 0xFFFF, sum = 0
7032 13:19:24.536124 13, 0x0, sum = 1
7033 13:19:24.536193 14, 0x0, sum = 2
7034 13:19:24.539893 15, 0x0, sum = 3
7035 13:19:24.539960 16, 0x0, sum = 4
7036 13:19:24.543082 best_step = 14
7037 13:19:24.543171
7038 13:19:24.543250 ==
7039 13:19:24.545986 Dram Type= 6, Freq= 0, CH_1, rank 1
7040 13:19:24.549517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7041 13:19:24.549606 ==
7042 13:19:24.549684 RX Vref Scan: 0
7043 13:19:24.553050
7044 13:19:24.553113 RX Vref 0 -> 0, step: 1
7045 13:19:24.553166
7046 13:19:24.556477 RX Delay -343 -> 252, step: 8
7047 13:19:24.563775 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7048 13:19:24.566958 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
7049 13:19:24.570159 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
7050 13:19:24.576887 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7051 13:19:24.580292 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
7052 13:19:24.583341 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7053 13:19:24.586436 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7054 13:19:24.593274 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7055 13:19:24.596279 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7056 13:19:24.599558 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7057 13:19:24.603340 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7058 13:19:24.609576 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7059 13:19:24.613170 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7060 13:19:24.616632 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7061 13:19:24.619466 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7062 13:19:24.626394 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7063 13:19:24.626482 ==
7064 13:19:24.629574 Dram Type= 6, Freq= 0, CH_1, rank 1
7065 13:19:24.632652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7066 13:19:24.632724 ==
7067 13:19:24.632781 DQS Delay:
7068 13:19:24.635914 DQS0 = 48, DQS1 = 56
7069 13:19:24.635991 DQM Delay:
7070 13:19:24.639695 DQM0 = 11, DQM1 = 11
7071 13:19:24.639772 DQ Delay:
7072 13:19:24.642906 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =8
7073 13:19:24.646106 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
7074 13:19:24.649199 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7075 13:19:24.652449 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7076 13:19:24.652527
7077 13:19:24.652586
7078 13:19:24.659273 [DQSOSCAuto] RK1, (LSB)MR18= 0x6857, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7079 13:19:24.662471 CH1 RK1: MR19=C0C, MR18=6857
7080 13:19:24.669146 CH1_RK1: MR19=0xC0C, MR18=0x6857, DQSOSC=396, MR23=63, INC=376, DEC=251
7081 13:19:24.672708 [RxdqsGatingPostProcess] freq 400
7082 13:19:24.679377 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7083 13:19:24.682325 best DQS0 dly(2T, 0.5T) = (0, 10)
7084 13:19:24.685891 best DQS1 dly(2T, 0.5T) = (0, 10)
7085 13:19:24.689012 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7086 13:19:24.692193 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7087 13:19:24.692270 best DQS0 dly(2T, 0.5T) = (0, 10)
7088 13:19:24.695913 best DQS1 dly(2T, 0.5T) = (0, 10)
7089 13:19:24.698994 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7090 13:19:24.702531 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7091 13:19:24.705806 Pre-setting of DQS Precalculation
7092 13:19:24.712162 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7093 13:19:24.718444 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7094 13:19:24.725102 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7095 13:19:24.725183
7096 13:19:24.725242
7097 13:19:24.728621 [Calibration Summary] 800 Mbps
7098 13:19:24.731851 CH 0, Rank 0
7099 13:19:24.731929 SW Impedance : PASS
7100 13:19:24.735091 DUTY Scan : NO K
7101 13:19:24.735167 ZQ Calibration : PASS
7102 13:19:24.738744 Jitter Meter : NO K
7103 13:19:24.741898 CBT Training : PASS
7104 13:19:24.741973 Write leveling : PASS
7105 13:19:24.745077 RX DQS gating : PASS
7106 13:19:24.748268 RX DQ/DQS(RDDQC) : PASS
7107 13:19:24.748336 TX DQ/DQS : PASS
7108 13:19:24.751338 RX DATLAT : PASS
7109 13:19:24.755189 RX DQ/DQS(Engine): PASS
7110 13:19:24.755287 TX OE : NO K
7111 13:19:24.758219 All Pass.
7112 13:19:24.758294
7113 13:19:24.758352 CH 0, Rank 1
7114 13:19:24.761887 SW Impedance : PASS
7115 13:19:24.761960 DUTY Scan : NO K
7116 13:19:24.765044 ZQ Calibration : PASS
7117 13:19:24.768237 Jitter Meter : NO K
7118 13:19:24.768305 CBT Training : PASS
7119 13:19:24.771375 Write leveling : NO K
7120 13:19:24.774490 RX DQS gating : PASS
7121 13:19:24.774567 RX DQ/DQS(RDDQC) : PASS
7122 13:19:24.778260 TX DQ/DQS : PASS
7123 13:19:24.781481 RX DATLAT : PASS
7124 13:19:24.781584 RX DQ/DQS(Engine): PASS
7125 13:19:24.784544 TX OE : NO K
7126 13:19:24.784668 All Pass.
7127 13:19:24.784783
7128 13:19:24.788182 CH 1, Rank 0
7129 13:19:24.788276 SW Impedance : PASS
7130 13:19:24.790998 DUTY Scan : NO K
7131 13:19:24.794528 ZQ Calibration : PASS
7132 13:19:24.794624 Jitter Meter : NO K
7133 13:19:24.798056 CBT Training : PASS
7134 13:19:24.801059 Write leveling : PASS
7135 13:19:24.801139 RX DQS gating : PASS
7136 13:19:24.804641 RX DQ/DQS(RDDQC) : PASS
7137 13:19:24.804718 TX DQ/DQS : PASS
7138 13:19:24.807622 RX DATLAT : PASS
7139 13:19:24.810945 RX DQ/DQS(Engine): PASS
7140 13:19:24.811038 TX OE : NO K
7141 13:19:24.814157 All Pass.
7142 13:19:24.814223
7143 13:19:24.814277 CH 1, Rank 1
7144 13:19:24.817980 SW Impedance : PASS
7145 13:19:24.818079 DUTY Scan : NO K
7146 13:19:24.821057 ZQ Calibration : PASS
7147 13:19:24.823964 Jitter Meter : NO K
7148 13:19:24.824044 CBT Training : PASS
7149 13:19:24.827689 Write leveling : NO K
7150 13:19:24.830782 RX DQS gating : PASS
7151 13:19:24.830859 RX DQ/DQS(RDDQC) : PASS
7152 13:19:24.833846 TX DQ/DQS : PASS
7153 13:19:24.837450 RX DATLAT : PASS
7154 13:19:24.837528 RX DQ/DQS(Engine): PASS
7155 13:19:24.840599 TX OE : NO K
7156 13:19:24.840689 All Pass.
7157 13:19:24.840747
7158 13:19:24.844350 DramC Write-DBI off
7159 13:19:24.847540 PER_BANK_REFRESH: Hybrid Mode
7160 13:19:24.847634 TX_TRACKING: ON
7161 13:19:24.857506 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7162 13:19:24.860682 [FAST_K] Save calibration result to emmc
7163 13:19:24.863636 dramc_set_vcore_voltage set vcore to 725000
7164 13:19:24.867291 Read voltage for 1600, 0
7165 13:19:24.867393 Vio18 = 0
7166 13:19:24.867492 Vcore = 725000
7167 13:19:24.870524 Vdram = 0
7168 13:19:24.870599 Vddq = 0
7169 13:19:24.870657 Vmddr = 0
7170 13:19:24.876881 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7171 13:19:24.880125 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7172 13:19:24.883923 MEM_TYPE=3, freq_sel=13
7173 13:19:24.887028 sv_algorithm_assistance_LP4_3733
7174 13:19:24.889993 ============ PULL DRAM RESETB DOWN ============
7175 13:19:24.896755 ========== PULL DRAM RESETB DOWN end =========
7176 13:19:24.899747 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7177 13:19:24.903151 ===================================
7178 13:19:24.906584 LPDDR4 DRAM CONFIGURATION
7179 13:19:24.909777 ===================================
7180 13:19:24.909852 EX_ROW_EN[0] = 0x0
7181 13:19:24.912944 EX_ROW_EN[1] = 0x0
7182 13:19:24.913019 LP4Y_EN = 0x0
7183 13:19:24.916624 WORK_FSP = 0x1
7184 13:19:24.916702 WL = 0x5
7185 13:19:24.919721 RL = 0x5
7186 13:19:24.923161 BL = 0x2
7187 13:19:24.923295 RPST = 0x0
7188 13:19:24.926554 RD_PRE = 0x0
7189 13:19:24.926628 WR_PRE = 0x1
7190 13:19:24.929691 WR_PST = 0x1
7191 13:19:24.929771 DBI_WR = 0x0
7192 13:19:24.933119 DBI_RD = 0x0
7193 13:19:24.933196 OTF = 0x1
7194 13:19:24.936348 ===================================
7195 13:19:24.939885 ===================================
7196 13:19:24.942769 ANA top config
7197 13:19:24.946040 ===================================
7198 13:19:24.946173 DLL_ASYNC_EN = 0
7199 13:19:24.949729 ALL_SLAVE_EN = 0
7200 13:19:24.952913 NEW_RANK_MODE = 1
7201 13:19:24.956041 DLL_IDLE_MODE = 1
7202 13:19:24.956117 LP45_APHY_COMB_EN = 1
7203 13:19:24.959732 TX_ODT_DIS = 0
7204 13:19:24.962843 NEW_8X_MODE = 1
7205 13:19:24.965928 ===================================
7206 13:19:24.969563 ===================================
7207 13:19:24.972635 data_rate = 3200
7208 13:19:24.975962 CKR = 1
7209 13:19:24.979096 DQ_P2S_RATIO = 8
7210 13:19:24.982251 ===================================
7211 13:19:24.982327 CA_P2S_RATIO = 8
7212 13:19:24.986071 DQ_CA_OPEN = 0
7213 13:19:24.989208 DQ_SEMI_OPEN = 0
7214 13:19:24.992288 CA_SEMI_OPEN = 0
7215 13:19:24.996014 CA_FULL_RATE = 0
7216 13:19:24.999166 DQ_CKDIV4_EN = 0
7217 13:19:24.999242 CA_CKDIV4_EN = 0
7218 13:19:25.002287 CA_PREDIV_EN = 0
7219 13:19:25.005871 PH8_DLY = 12
7220 13:19:25.008987 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7221 13:19:25.012433 DQ_AAMCK_DIV = 4
7222 13:19:25.015491 CA_AAMCK_DIV = 4
7223 13:19:25.015567 CA_ADMCK_DIV = 4
7224 13:19:25.018646 DQ_TRACK_CA_EN = 0
7225 13:19:25.022452 CA_PICK = 1600
7226 13:19:25.025595 CA_MCKIO = 1600
7227 13:19:25.028836 MCKIO_SEMI = 0
7228 13:19:25.031936 PLL_FREQ = 3068
7229 13:19:25.035098 DQ_UI_PI_RATIO = 32
7230 13:19:25.038721 CA_UI_PI_RATIO = 0
7231 13:19:25.041902 ===================================
7232 13:19:25.045009 ===================================
7233 13:19:25.045090 memory_type:LPDDR4
7234 13:19:25.048311 GP_NUM : 10
7235 13:19:25.051793 SRAM_EN : 1
7236 13:19:25.051869 MD32_EN : 0
7237 13:19:25.054968 ===================================
7238 13:19:25.058562 [ANA_INIT] >>>>>>>>>>>>>>
7239 13:19:25.061748 <<<<<< [CONFIGURE PHASE]: ANA_TX
7240 13:19:25.065040 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7241 13:19:25.068308 ===================================
7242 13:19:25.071754 data_rate = 3200,PCW = 0X7600
7243 13:19:25.075116 ===================================
7244 13:19:25.078451 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7245 13:19:25.081591 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7246 13:19:25.087898 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7247 13:19:25.091632 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7248 13:19:25.094691 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7249 13:19:25.097768 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7250 13:19:25.101572 [ANA_INIT] flow start
7251 13:19:25.104620 [ANA_INIT] PLL >>>>>>>>
7252 13:19:25.104717 [ANA_INIT] PLL <<<<<<<<
7253 13:19:25.107722 [ANA_INIT] MIDPI >>>>>>>>
7254 13:19:25.111313 [ANA_INIT] MIDPI <<<<<<<<
7255 13:19:25.114450 [ANA_INIT] DLL >>>>>>>>
7256 13:19:25.114525 [ANA_INIT] DLL <<<<<<<<
7257 13:19:25.117569 [ANA_INIT] flow end
7258 13:19:25.121019 ============ LP4 DIFF to SE enter ============
7259 13:19:25.124070 ============ LP4 DIFF to SE exit ============
7260 13:19:25.127308 [ANA_INIT] <<<<<<<<<<<<<
7261 13:19:25.131084 [Flow] Enable top DCM control >>>>>
7262 13:19:25.134268 [Flow] Enable top DCM control <<<<<
7263 13:19:25.137467 Enable DLL master slave shuffle
7264 13:19:25.143724 ==============================================================
7265 13:19:25.143804 Gating Mode config
7266 13:19:25.150613 ==============================================================
7267 13:19:25.150692 Config description:
7268 13:19:25.160797 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7269 13:19:25.167118 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7270 13:19:25.173788 SELPH_MODE 0: By rank 1: By Phase
7271 13:19:25.179841 ==============================================================
7272 13:19:25.179969 GAT_TRACK_EN = 1
7273 13:19:25.183601 RX_GATING_MODE = 2
7274 13:19:25.186993 RX_GATING_TRACK_MODE = 2
7275 13:19:25.189999 SELPH_MODE = 1
7276 13:19:25.193652 PICG_EARLY_EN = 1
7277 13:19:25.196575 VALID_LAT_VALUE = 1
7278 13:19:25.203561 ==============================================================
7279 13:19:25.206653 Enter into Gating configuration >>>>
7280 13:19:25.209749 Exit from Gating configuration <<<<
7281 13:19:25.212937 Enter into DVFS_PRE_config >>>>>
7282 13:19:25.222978 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7283 13:19:25.226597 Exit from DVFS_PRE_config <<<<<
7284 13:19:25.229427 Enter into PICG configuration >>>>
7285 13:19:25.233231 Exit from PICG configuration <<<<
7286 13:19:25.236402 [RX_INPUT] configuration >>>>>
7287 13:19:25.239474 [RX_INPUT] configuration <<<<<
7288 13:19:25.242732 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7289 13:19:25.249782 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7290 13:19:25.256022 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7291 13:19:25.262756 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7292 13:19:25.265650 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7293 13:19:25.272340 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7294 13:19:25.275668 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7295 13:19:25.282590 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7296 13:19:25.285834 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7297 13:19:25.288903 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7298 13:19:25.292452 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7299 13:19:25.299040 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7300 13:19:25.302176 ===================================
7301 13:19:25.305739 LPDDR4 DRAM CONFIGURATION
7302 13:19:25.308659 ===================================
7303 13:19:25.308737 EX_ROW_EN[0] = 0x0
7304 13:19:25.312245 EX_ROW_EN[1] = 0x0
7305 13:19:25.312346 LP4Y_EN = 0x0
7306 13:19:25.315180 WORK_FSP = 0x1
7307 13:19:25.315257 WL = 0x5
7308 13:19:25.318215 RL = 0x5
7309 13:19:25.318291 BL = 0x2
7310 13:19:25.322031 RPST = 0x0
7311 13:19:25.322108 RD_PRE = 0x0
7312 13:19:25.325234 WR_PRE = 0x1
7313 13:19:25.325309 WR_PST = 0x1
7314 13:19:25.328401 DBI_WR = 0x0
7315 13:19:25.331421 DBI_RD = 0x0
7316 13:19:25.331560 OTF = 0x1
7317 13:19:25.335167 ===================================
7318 13:19:25.338678 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7319 13:19:25.341918 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7320 13:19:25.348131 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7321 13:19:25.351935 ===================================
7322 13:19:25.355148 LPDDR4 DRAM CONFIGURATION
7323 13:19:25.358236 ===================================
7324 13:19:25.358336 EX_ROW_EN[0] = 0x10
7325 13:19:25.361366 EX_ROW_EN[1] = 0x0
7326 13:19:25.361460 LP4Y_EN = 0x0
7327 13:19:25.365222 WORK_FSP = 0x1
7328 13:19:25.365299 WL = 0x5
7329 13:19:25.368385 RL = 0x5
7330 13:19:25.368453 BL = 0x2
7331 13:19:25.371363 RPST = 0x0
7332 13:19:25.371482 RD_PRE = 0x0
7333 13:19:25.374944 WR_PRE = 0x1
7334 13:19:25.375020 WR_PST = 0x1
7335 13:19:25.377929 DBI_WR = 0x0
7336 13:19:25.378027 DBI_RD = 0x0
7337 13:19:25.381429 OTF = 0x1
7338 13:19:25.384781 ===================================
7339 13:19:25.391075 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7340 13:19:25.391173 ==
7341 13:19:25.394893 Dram Type= 6, Freq= 0, CH_0, rank 0
7342 13:19:25.397937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7343 13:19:25.398036 ==
7344 13:19:25.401103 [Duty_Offset_Calibration]
7345 13:19:25.401193 B0:1 B1:-1 CA:0
7346 13:19:25.404185
7347 13:19:25.404276 [DutyScan_Calibration_Flow] k_type=0
7348 13:19:25.415915
7349 13:19:25.415999 ==CLK 0==
7350 13:19:25.418869 Final CLK duty delay cell = 0
7351 13:19:25.422712 [0] MAX Duty = 5124%(X100), DQS PI = 22
7352 13:19:25.425464 [0] MIN Duty = 4907%(X100), DQS PI = 4
7353 13:19:25.428885 [0] AVG Duty = 5015%(X100)
7354 13:19:25.428977
7355 13:19:25.432146 CH0 CLK Duty spec in!! Max-Min= 217%
7356 13:19:25.435526 [DutyScan_Calibration_Flow] ====Done====
7357 13:19:25.435636
7358 13:19:25.438735 [DutyScan_Calibration_Flow] k_type=1
7359 13:19:25.455006
7360 13:19:25.455122 ==DQS 0 ==
7361 13:19:25.458062 Final DQS duty delay cell = -4
7362 13:19:25.461286 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7363 13:19:25.465077 [-4] MIN Duty = 4844%(X100), DQS PI = 10
7364 13:19:25.468217 [-4] AVG Duty = 4906%(X100)
7365 13:19:25.468289
7366 13:19:25.468348 ==DQS 1 ==
7367 13:19:25.471280 Final DQS duty delay cell = 0
7368 13:19:25.475002 [0] MAX Duty = 5156%(X100), DQS PI = 2
7369 13:19:25.477908 [0] MIN Duty = 5000%(X100), DQS PI = 20
7370 13:19:25.481487 [0] AVG Duty = 5078%(X100)
7371 13:19:25.481561
7372 13:19:25.484628 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7373 13:19:25.484739
7374 13:19:25.487659 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7375 13:19:25.491174 [DutyScan_Calibration_Flow] ====Done====
7376 13:19:25.491241
7377 13:19:25.494210 [DutyScan_Calibration_Flow] k_type=3
7378 13:19:25.512427
7379 13:19:25.512533 ==DQM 0 ==
7380 13:19:25.515546 Final DQM duty delay cell = 0
7381 13:19:25.519331 [0] MAX Duty = 5124%(X100), DQS PI = 22
7382 13:19:25.522338 [0] MIN Duty = 4875%(X100), DQS PI = 10
7383 13:19:25.525323 [0] AVG Duty = 4999%(X100)
7384 13:19:25.525390
7385 13:19:25.525446 ==DQM 1 ==
7386 13:19:25.528988 Final DQM duty delay cell = 0
7387 13:19:25.532028 [0] MAX Duty = 5000%(X100), DQS PI = 4
7388 13:19:25.535651 [0] MIN Duty = 4782%(X100), DQS PI = 20
7389 13:19:25.539025 [0] AVG Duty = 4891%(X100)
7390 13:19:25.539096
7391 13:19:25.542049 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7392 13:19:25.542186
7393 13:19:25.545316 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7394 13:19:25.548780 [DutyScan_Calibration_Flow] ====Done====
7395 13:19:25.548855
7396 13:19:25.552176 [DutyScan_Calibration_Flow] k_type=2
7397 13:19:25.568597
7398 13:19:25.568681 ==DQ 0 ==
7399 13:19:25.572289 Final DQ duty delay cell = -4
7400 13:19:25.575486 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7401 13:19:25.578642 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7402 13:19:25.581812 [-4] AVG Duty = 4953%(X100)
7403 13:19:25.581904
7404 13:19:25.582000 ==DQ 1 ==
7405 13:19:25.585087 Final DQ duty delay cell = 0
7406 13:19:25.588843 [0] MAX Duty = 5125%(X100), DQS PI = 48
7407 13:19:25.591924 [0] MIN Duty = 4969%(X100), DQS PI = 36
7408 13:19:25.594977 [0] AVG Duty = 5047%(X100)
7409 13:19:25.595041
7410 13:19:25.598472 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7411 13:19:25.598559
7412 13:19:25.601804 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7413 13:19:25.604881 [DutyScan_Calibration_Flow] ====Done====
7414 13:19:25.604954 ==
7415 13:19:25.608046 Dram Type= 6, Freq= 0, CH_1, rank 0
7416 13:19:25.611727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7417 13:19:25.611817 ==
7418 13:19:25.614980 [Duty_Offset_Calibration]
7419 13:19:25.615070 B0:-1 B1:1 CA:2
7420 13:19:25.618071
7421 13:19:25.621162 [DutyScan_Calibration_Flow] k_type=0
7422 13:19:25.629347
7423 13:19:25.629419 ==CLK 0==
7424 13:19:25.632473 Final CLK duty delay cell = 0
7425 13:19:25.636132 [0] MAX Duty = 5187%(X100), DQS PI = 22
7426 13:19:25.639293 [0] MIN Duty = 4969%(X100), DQS PI = 62
7427 13:19:25.642484 [0] AVG Duty = 5078%(X100)
7428 13:19:25.642566
7429 13:19:25.645973 CH1 CLK Duty spec in!! Max-Min= 218%
7430 13:19:25.649137 [DutyScan_Calibration_Flow] ====Done====
7431 13:19:25.649246
7432 13:19:25.652142 [DutyScan_Calibration_Flow] k_type=1
7433 13:19:25.669231
7434 13:19:25.669341 ==DQS 0 ==
7435 13:19:25.672256 Final DQS duty delay cell = 0
7436 13:19:25.675523 [0] MAX Duty = 5124%(X100), DQS PI = 18
7437 13:19:25.679283 [0] MIN Duty = 4907%(X100), DQS PI = 8
7438 13:19:25.682427 [0] AVG Duty = 5015%(X100)
7439 13:19:25.682513
7440 13:19:25.682592 ==DQS 1 ==
7441 13:19:25.685514 Final DQS duty delay cell = 0
7442 13:19:25.688540 [0] MAX Duty = 5093%(X100), DQS PI = 26
7443 13:19:25.692107 [0] MIN Duty = 4969%(X100), DQS PI = 54
7444 13:19:25.695119 [0] AVG Duty = 5031%(X100)
7445 13:19:25.695193
7446 13:19:25.698876 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7447 13:19:25.698984
7448 13:19:25.702057 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7449 13:19:25.705140 [DutyScan_Calibration_Flow] ====Done====
7450 13:19:25.705238
7451 13:19:25.708628 [DutyScan_Calibration_Flow] k_type=3
7452 13:19:25.726363
7453 13:19:25.726449 ==DQM 0 ==
7454 13:19:25.729475 Final DQM duty delay cell = 0
7455 13:19:25.732606 [0] MAX Duty = 5218%(X100), DQS PI = 18
7456 13:19:25.735788 [0] MIN Duty = 5000%(X100), DQS PI = 8
7457 13:19:25.738886 [0] AVG Duty = 5109%(X100)
7458 13:19:25.738988
7459 13:19:25.739073 ==DQM 1 ==
7460 13:19:25.742573 Final DQM duty delay cell = 0
7461 13:19:25.745858 [0] MAX Duty = 5156%(X100), DQS PI = 2
7462 13:19:25.748915 [0] MIN Duty = 4969%(X100), DQS PI = 30
7463 13:19:25.752073 [0] AVG Duty = 5062%(X100)
7464 13:19:25.752174
7465 13:19:25.755185 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7466 13:19:25.755275
7467 13:19:25.758936 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7468 13:19:25.761928 [DutyScan_Calibration_Flow] ====Done====
7469 13:19:25.762030
7470 13:19:25.765088 [DutyScan_Calibration_Flow] k_type=2
7471 13:19:25.782930
7472 13:19:25.783025 ==DQ 0 ==
7473 13:19:25.786252 Final DQ duty delay cell = 0
7474 13:19:25.789442 [0] MAX Duty = 5156%(X100), DQS PI = 30
7475 13:19:25.792458 [0] MIN Duty = 4906%(X100), DQS PI = 8
7476 13:19:25.792564 [0] AVG Duty = 5031%(X100)
7477 13:19:25.796213
7478 13:19:25.796283 ==DQ 1 ==
7479 13:19:25.799173 Final DQ duty delay cell = 0
7480 13:19:25.802659 [0] MAX Duty = 5156%(X100), DQS PI = 8
7481 13:19:25.805657 [0] MIN Duty = 4969%(X100), DQS PI = 56
7482 13:19:25.805755 [0] AVG Duty = 5062%(X100)
7483 13:19:25.805840
7484 13:19:25.812657 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7485 13:19:25.812760
7486 13:19:25.815542 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7487 13:19:25.819062 [DutyScan_Calibration_Flow] ====Done====
7488 13:19:25.822568 nWR fixed to 30
7489 13:19:25.822642 [ModeRegInit_LP4] CH0 RK0
7490 13:19:25.825777 [ModeRegInit_LP4] CH0 RK1
7491 13:19:25.828875 [ModeRegInit_LP4] CH1 RK0
7492 13:19:25.832117 [ModeRegInit_LP4] CH1 RK1
7493 13:19:25.832310 match AC timing 5
7494 13:19:25.838686 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7495 13:19:25.842345 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7496 13:19:25.845512 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7497 13:19:25.852354 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7498 13:19:25.855408 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7499 13:19:25.855544 [MiockJmeterHQA]
7500 13:19:25.855633
7501 13:19:25.858551 [DramcMiockJmeter] u1RxGatingPI = 0
7502 13:19:25.862269 0 : 4255, 4027
7503 13:19:25.862378 4 : 4363, 4138
7504 13:19:25.865478 8 : 4253, 4027
7505 13:19:25.865592 12 : 4252, 4027
7506 13:19:25.865685 16 : 4252, 4027
7507 13:19:25.868519 20 : 4255, 4029
7508 13:19:25.868602 24 : 4255, 4029
7509 13:19:25.871874 28 : 4253, 4026
7510 13:19:25.871994 32 : 4253, 4027
7511 13:19:25.875059 36 : 4365, 4140
7512 13:19:25.875184 40 : 4252, 4027
7513 13:19:25.878718 44 : 4254, 4029
7514 13:19:25.878824 48 : 4252, 4027
7515 13:19:25.878912 52 : 4363, 4138
7516 13:19:25.881915 56 : 4252, 4026
7517 13:19:25.881995 60 : 4360, 4138
7518 13:19:25.884848 64 : 4250, 4027
7519 13:19:25.884951 68 : 4250, 4027
7520 13:19:25.888403 72 : 4250, 4027
7521 13:19:25.888499 76 : 4252, 4029
7522 13:19:25.891841 80 : 4360, 4137
7523 13:19:25.891938 84 : 4250, 4027
7524 13:19:25.892028 88 : 4361, 4137
7525 13:19:25.895128 92 : 4250, 238
7526 13:19:25.895222 96 : 4250, 0
7527 13:19:25.898313 100 : 4250, 0
7528 13:19:25.898416 104 : 4250, 0
7529 13:19:25.898511 108 : 4250, 0
7530 13:19:25.901972 112 : 4252, 0
7531 13:19:25.902053 116 : 4360, 0
7532 13:19:25.905036 120 : 4250, 0
7533 13:19:25.905115 124 : 4250, 0
7534 13:19:25.905176 128 : 4361, 0
7535 13:19:25.908601 132 : 4361, 0
7536 13:19:25.908671 136 : 4250, 0
7537 13:19:25.911622 140 : 4250, 0
7538 13:19:25.911691 144 : 4360, 0
7539 13:19:25.911760 148 : 4250, 0
7540 13:19:25.914892 152 : 4249, 0
7541 13:19:25.914990 156 : 4250, 0
7542 13:19:25.915076 160 : 4250, 0
7543 13:19:25.918130 164 : 4252, 0
7544 13:19:25.918226 168 : 4360, 0
7545 13:19:25.921308 172 : 4250, 0
7546 13:19:25.921405 176 : 4250, 0
7547 13:19:25.921496 180 : 4361, 0
7548 13:19:25.924966 184 : 4361, 0
7549 13:19:25.925069 188 : 4363, 0
7550 13:19:25.927829 192 : 4250, 0
7551 13:19:25.927927 196 : 4360, 0
7552 13:19:25.928013 200 : 4250, 0
7553 13:19:25.931208 204 : 4249, 0
7554 13:19:25.931309 208 : 4250, 0
7555 13:19:25.934941 212 : 4250, 0
7556 13:19:25.935016 216 : 4252, 0
7557 13:19:25.935100 220 : 4360, 0
7558 13:19:25.938024 224 : 4250, 75
7559 13:19:25.938130 228 : 4250, 3025
7560 13:19:25.941051 232 : 4361, 4137
7561 13:19:25.941158 236 : 4250, 4026
7562 13:19:25.944745 240 : 4250, 4027
7563 13:19:25.944823 244 : 4250, 4027
7564 13:19:25.947857 248 : 4252, 4029
7565 13:19:25.947934 252 : 4250, 4026
7566 13:19:25.950968 256 : 4250, 4027
7567 13:19:25.951046 260 : 4250, 4027
7568 13:19:25.951105 264 : 4252, 4029
7569 13:19:25.954804 268 : 4250, 4026
7570 13:19:25.954881 272 : 4361, 4137
7571 13:19:25.957998 276 : 4360, 4138
7572 13:19:25.958074 280 : 4249, 4027
7573 13:19:25.961128 284 : 4363, 4140
7574 13:19:25.961203 288 : 4250, 4026
7575 13:19:25.964291 292 : 4250, 4027
7576 13:19:25.964368 296 : 4250, 4027
7577 13:19:25.967388 300 : 4252, 4029
7578 13:19:25.967489 304 : 4250, 4026
7579 13:19:25.971113 308 : 4250, 4027
7580 13:19:25.971190 312 : 4250, 4027
7581 13:19:25.974230 316 : 4252, 4029
7582 13:19:25.974306 320 : 4250, 4026
7583 13:19:25.977358 324 : 4361, 4137
7584 13:19:25.977435 328 : 4360, 4138
7585 13:19:25.977495 332 : 4249, 4027
7586 13:19:25.981173 336 : 4362, 4030
7587 13:19:25.981250 340 : 4250, 2035
7588 13:19:25.981309
7589 13:19:25.984299 MIOCK jitter meter ch=0
7590 13:19:25.984374
7591 13:19:25.987200 1T = (340-92) = 248 dly cells
7592 13:19:25.994003 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7593 13:19:25.994080 ==
7594 13:19:25.997799 Dram Type= 6, Freq= 0, CH_0, rank 0
7595 13:19:26.000829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7596 13:19:26.000906 ==
7597 13:19:26.007307 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7598 13:19:26.010521 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7599 13:19:26.014178 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7600 13:19:26.020432 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7601 13:19:26.029949 [CA 0] Center 43 (13~74) winsize 62
7602 13:19:26.032968 [CA 1] Center 43 (13~73) winsize 61
7603 13:19:26.036544 [CA 2] Center 38 (9~68) winsize 60
7604 13:19:26.039484 [CA 3] Center 38 (9~68) winsize 60
7605 13:19:26.042908 [CA 4] Center 36 (7~66) winsize 60
7606 13:19:26.046293 [CA 5] Center 36 (6~66) winsize 61
7607 13:19:26.046369
7608 13:19:26.049481 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7609 13:19:26.049575
7610 13:19:26.053102 [CATrainingPosCal] consider 1 rank data
7611 13:19:26.056195 u2DelayCellTimex100 = 262/100 ps
7612 13:19:26.059380 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7613 13:19:26.066447 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7614 13:19:26.069532 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7615 13:19:26.072753 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7616 13:19:26.076278 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7617 13:19:26.079407 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7618 13:19:26.079518
7619 13:19:26.082610 CA PerBit enable=1, Macro0, CA PI delay=36
7620 13:19:26.082685
7621 13:19:26.085846 [CBTSetCACLKResult] CA Dly = 36
7622 13:19:26.088927 CS Dly: 11 (0~42)
7623 13:19:26.092542 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7624 13:19:26.095741 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7625 13:19:26.095817 ==
7626 13:19:26.098918 Dram Type= 6, Freq= 0, CH_0, rank 1
7627 13:19:26.105369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7628 13:19:26.105448 ==
7629 13:19:26.109182 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7630 13:19:26.115366 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7631 13:19:26.119113 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7632 13:19:26.125638 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7633 13:19:26.133076 [CA 0] Center 42 (12~73) winsize 62
7634 13:19:26.136491 [CA 1] Center 43 (13~73) winsize 61
7635 13:19:26.139664 [CA 2] Center 37 (8~67) winsize 60
7636 13:19:26.143193 [CA 3] Center 37 (8~67) winsize 60
7637 13:19:26.146704 [CA 4] Center 36 (6~66) winsize 61
7638 13:19:26.149662 [CA 5] Center 35 (5~65) winsize 61
7639 13:19:26.149739
7640 13:19:26.152971 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7641 13:19:26.153047
7642 13:19:26.156427 [CATrainingPosCal] consider 2 rank data
7643 13:19:26.159320 u2DelayCellTimex100 = 262/100 ps
7644 13:19:26.163138 CA0 delay=43 (13~73),Diff = 8 PI (29 cell)
7645 13:19:26.169434 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7646 13:19:26.172514 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7647 13:19:26.175723 CA3 delay=38 (9~67),Diff = 3 PI (11 cell)
7648 13:19:26.179370 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7649 13:19:26.182508 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7650 13:19:26.182584
7651 13:19:26.185594 CA PerBit enable=1, Macro0, CA PI delay=35
7652 13:19:26.185669
7653 13:19:26.189270 [CBTSetCACLKResult] CA Dly = 35
7654 13:19:26.192314 CS Dly: 12 (0~44)
7655 13:19:26.196040 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7656 13:19:26.199231 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7657 13:19:26.199311
7658 13:19:26.202326 ----->DramcWriteLeveling(PI) begin...
7659 13:19:26.202418 ==
7660 13:19:26.205488 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 13:19:26.212387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 13:19:26.212479 ==
7663 13:19:26.215590 Write leveling (Byte 0): 37 => 37
7664 13:19:26.218706 Write leveling (Byte 1): 29 => 29
7665 13:19:26.221910 DramcWriteLeveling(PI) end<-----
7666 13:19:26.222034
7667 13:19:26.222093 ==
7668 13:19:26.225412 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 13:19:26.229036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 13:19:26.229189 ==
7671 13:19:26.231845 [Gating] SW mode calibration
7672 13:19:26.238593 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7673 13:19:26.242184 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7674 13:19:26.248430 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7675 13:19:26.251814 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7676 13:19:26.258508 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7677 13:19:26.261365 1 4 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
7678 13:19:26.265093 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7679 13:19:26.271601 1 4 20 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
7680 13:19:26.274695 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7681 13:19:26.277926 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7682 13:19:26.284668 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7683 13:19:26.287869 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7684 13:19:26.291787 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7685 13:19:26.294851 1 5 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
7686 13:19:26.301073 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7687 13:19:26.304973 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (1 0) (0 0)
7688 13:19:26.308206 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7689 13:19:26.314516 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7690 13:19:26.317705 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7691 13:19:26.320880 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7692 13:19:26.328097 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7693 13:19:26.331096 1 6 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
7694 13:19:26.334038 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7695 13:19:26.340779 1 6 20 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
7696 13:19:26.344079 1 6 24 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
7697 13:19:26.347276 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7698 13:19:26.354262 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7699 13:19:26.357291 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7700 13:19:26.360448 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7701 13:19:26.367271 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7702 13:19:26.370441 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7703 13:19:26.373963 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7704 13:19:26.380455 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7705 13:19:26.383763 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7706 13:19:26.387279 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7707 13:19:26.393959 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7708 13:19:26.397013 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7709 13:19:26.400247 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7710 13:19:26.407184 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7711 13:19:26.410497 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7712 13:19:26.413848 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7713 13:19:26.419950 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7714 13:19:26.423777 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7715 13:19:26.427040 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7716 13:19:26.433530 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7717 13:19:26.436579 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7718 13:19:26.439691 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7719 13:19:26.443594 Total UI for P1: 0, mck2ui 16
7720 13:19:26.446770 best dqsien dly found for B0: ( 1, 9, 10)
7721 13:19:26.453087 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7722 13:19:26.456778 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7723 13:19:26.459792 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7724 13:19:26.462949 Total UI for P1: 0, mck2ui 16
7725 13:19:26.466518 best dqsien dly found for B1: ( 1, 9, 22)
7726 13:19:26.469498 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7727 13:19:26.472769 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7728 13:19:26.476570
7729 13:19:26.479804 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7730 13:19:26.483035 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7731 13:19:26.486210 [Gating] SW calibration Done
7732 13:19:26.486353 ==
7733 13:19:26.489798 Dram Type= 6, Freq= 0, CH_0, rank 0
7734 13:19:26.492544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7735 13:19:26.492662 ==
7736 13:19:26.495949 RX Vref Scan: 0
7737 13:19:26.496082
7738 13:19:26.496178 RX Vref 0 -> 0, step: 1
7739 13:19:26.496267
7740 13:19:26.499372 RX Delay 0 -> 252, step: 8
7741 13:19:26.502327 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7742 13:19:26.506179 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
7743 13:19:26.512634 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7744 13:19:26.515911 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7745 13:19:26.519016 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7746 13:19:26.522332 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7747 13:19:26.525613 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7748 13:19:26.532693 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7749 13:19:26.535766 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7750 13:19:26.539038 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7751 13:19:26.542649 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7752 13:19:26.545839 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7753 13:19:26.552579 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7754 13:19:26.555829 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7755 13:19:26.559033 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7756 13:19:26.562225 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7757 13:19:26.562571 ==
7758 13:19:26.565314 Dram Type= 6, Freq= 0, CH_0, rank 0
7759 13:19:26.572108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7760 13:19:26.572513 ==
7761 13:19:26.572822 DQS Delay:
7762 13:19:26.575613 DQS0 = 0, DQS1 = 0
7763 13:19:26.575896 DQM Delay:
7764 13:19:26.578690 DQM0 = 134, DQM1 = 126
7765 13:19:26.578992 DQ Delay:
7766 13:19:26.582366 DQ0 =135, DQ1 =135, DQ2 =131, DQ3 =131
7767 13:19:26.585559 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =147
7768 13:19:26.588717 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
7769 13:19:26.591891 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7770 13:19:26.592036
7771 13:19:26.592139
7772 13:19:26.592231 ==
7773 13:19:26.595118 Dram Type= 6, Freq= 0, CH_0, rank 0
7774 13:19:26.601706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7775 13:19:26.601839 ==
7776 13:19:26.601918
7777 13:19:26.601989
7778 13:19:26.602058 TX Vref Scan disable
7779 13:19:26.605121 == TX Byte 0 ==
7780 13:19:26.608177 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7781 13:19:26.615337 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7782 13:19:26.615421 == TX Byte 1 ==
7783 13:19:26.618215 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7784 13:19:26.625002 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7785 13:19:26.625085 ==
7786 13:19:26.628235 Dram Type= 6, Freq= 0, CH_0, rank 0
7787 13:19:26.631402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7788 13:19:26.631492 ==
7789 13:19:26.644667
7790 13:19:26.647813 TX Vref early break, caculate TX vref
7791 13:19:26.651579 TX Vref=16, minBit 3, minWin=22, winSum=374
7792 13:19:26.654623 TX Vref=18, minBit 0, minWin=23, winSum=384
7793 13:19:26.658099 TX Vref=20, minBit 1, minWin=23, winSum=389
7794 13:19:26.661265 TX Vref=22, minBit 4, minWin=24, winSum=404
7795 13:19:26.664496 TX Vref=24, minBit 3, minWin=24, winSum=411
7796 13:19:26.671289 TX Vref=26, minBit 4, minWin=25, winSum=423
7797 13:19:26.674290 TX Vref=28, minBit 3, minWin=25, winSum=424
7798 13:19:26.677989 TX Vref=30, minBit 5, minWin=24, winSum=414
7799 13:19:26.681125 TX Vref=32, minBit 0, minWin=24, winSum=405
7800 13:19:26.684233 TX Vref=34, minBit 0, minWin=23, winSum=393
7801 13:19:26.691265 [TxChooseVref] Worse bit 3, Min win 25, Win sum 424, Final Vref 28
7802 13:19:26.691705
7803 13:19:26.694436 Final TX Range 0 Vref 28
7804 13:19:26.694819
7805 13:19:26.695079 ==
7806 13:19:26.697714 Dram Type= 6, Freq= 0, CH_0, rank 0
7807 13:19:26.700966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7808 13:19:26.701314 ==
7809 13:19:26.701594
7810 13:19:26.701875
7811 13:19:26.704003 TX Vref Scan disable
7812 13:19:26.710761 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7813 13:19:26.711152 == TX Byte 0 ==
7814 13:19:26.714292 u2DelayCellOfst[0]=18 cells (5 PI)
7815 13:19:26.717519 u2DelayCellOfst[1]=18 cells (5 PI)
7816 13:19:26.720640 u2DelayCellOfst[2]=14 cells (4 PI)
7817 13:19:26.723624 u2DelayCellOfst[3]=14 cells (4 PI)
7818 13:19:26.727055 u2DelayCellOfst[4]=11 cells (3 PI)
7819 13:19:26.730647 u2DelayCellOfst[5]=0 cells (0 PI)
7820 13:19:26.733744 u2DelayCellOfst[6]=18 cells (5 PI)
7821 13:19:26.737179 u2DelayCellOfst[7]=22 cells (6 PI)
7822 13:19:26.740340 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7823 13:19:26.744239 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7824 13:19:26.747372 == TX Byte 1 ==
7825 13:19:26.750483 u2DelayCellOfst[8]=0 cells (0 PI)
7826 13:19:26.753678 u2DelayCellOfst[9]=3 cells (1 PI)
7827 13:19:26.756875 u2DelayCellOfst[10]=7 cells (2 PI)
7828 13:19:26.757230 u2DelayCellOfst[11]=0 cells (0 PI)
7829 13:19:26.760649 u2DelayCellOfst[12]=11 cells (3 PI)
7830 13:19:26.763710 u2DelayCellOfst[13]=11 cells (3 PI)
7831 13:19:26.767195 u2DelayCellOfst[14]=14 cells (4 PI)
7832 13:19:26.770363 u2DelayCellOfst[15]=14 cells (4 PI)
7833 13:19:26.777200 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7834 13:19:26.780187 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7835 13:19:26.780544 DramC Write-DBI on
7836 13:19:26.780817 ==
7837 13:19:26.783796 Dram Type= 6, Freq= 0, CH_0, rank 0
7838 13:19:26.790046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7839 13:19:26.790548 ==
7840 13:19:26.790980
7841 13:19:26.791400
7842 13:19:26.793145 TX Vref Scan disable
7843 13:19:26.793533 == TX Byte 0 ==
7844 13:19:26.800207 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7845 13:19:26.800675 == TX Byte 1 ==
7846 13:19:26.803478 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7847 13:19:26.806772 DramC Write-DBI off
7848 13:19:26.807181
7849 13:19:26.807617 [DATLAT]
7850 13:19:26.809980 Freq=1600, CH0 RK0
7851 13:19:26.810331
7852 13:19:26.810601 DATLAT Default: 0xf
7853 13:19:26.813181 0, 0xFFFF, sum = 0
7854 13:19:26.813697 1, 0xFFFF, sum = 0
7855 13:19:26.816782 2, 0xFFFF, sum = 0
7856 13:19:26.817112 3, 0xFFFF, sum = 0
7857 13:19:26.820133 4, 0xFFFF, sum = 0
7858 13:19:26.820465 5, 0xFFFF, sum = 0
7859 13:19:26.822843 6, 0xFFFF, sum = 0
7860 13:19:26.826699 7, 0xFFFF, sum = 0
7861 13:19:26.827033 8, 0xFFFF, sum = 0
7862 13:19:26.829878 9, 0xFFFF, sum = 0
7863 13:19:26.830217 10, 0xFFFF, sum = 0
7864 13:19:26.833022 11, 0xFFFF, sum = 0
7865 13:19:26.833354 12, 0xFFFF, sum = 0
7866 13:19:26.836166 13, 0xFFFF, sum = 0
7867 13:19:26.836601 14, 0x0, sum = 1
7868 13:19:26.839266 15, 0x0, sum = 2
7869 13:19:26.839711 16, 0x0, sum = 3
7870 13:19:26.842908 17, 0x0, sum = 4
7871 13:19:26.843321 best_step = 15
7872 13:19:26.843741
7873 13:19:26.844108 ==
7874 13:19:26.846443 Dram Type= 6, Freq= 0, CH_0, rank 0
7875 13:19:26.849596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7876 13:19:26.852894 ==
7877 13:19:26.853221 RX Vref Scan: 1
7878 13:19:26.853597
7879 13:19:26.856213 Set Vref Range= 24 -> 127
7880 13:19:26.856627
7881 13:19:26.859542 RX Vref 24 -> 127, step: 1
7882 13:19:26.859870
7883 13:19:26.860124 RX Delay 11 -> 252, step: 4
7884 13:19:26.860360
7885 13:19:26.862786 Set Vref, RX VrefLevel [Byte0]: 24
7886 13:19:26.865953 [Byte1]: 24
7887 13:19:26.869667
7888 13:19:26.869987 Set Vref, RX VrefLevel [Byte0]: 25
7889 13:19:26.873377 [Byte1]: 25
7890 13:19:26.877421
7891 13:19:26.880618 Set Vref, RX VrefLevel [Byte0]: 26
7892 13:19:26.883657 [Byte1]: 26
7893 13:19:26.883980
7894 13:19:26.887234 Set Vref, RX VrefLevel [Byte0]: 27
7895 13:19:26.890373 [Byte1]: 27
7896 13:19:26.890699
7897 13:19:26.893811 Set Vref, RX VrefLevel [Byte0]: 28
7898 13:19:26.896598 [Byte1]: 28
7899 13:19:26.900431
7900 13:19:26.900755 Set Vref, RX VrefLevel [Byte0]: 29
7901 13:19:26.903626 [Byte1]: 29
7902 13:19:26.908048
7903 13:19:26.908442 Set Vref, RX VrefLevel [Byte0]: 30
7904 13:19:26.911237 [Byte1]: 30
7905 13:19:26.915782
7906 13:19:26.916160 Set Vref, RX VrefLevel [Byte0]: 31
7907 13:19:26.918453 [Byte1]: 31
7908 13:19:26.922787
7909 13:19:26.923109 Set Vref, RX VrefLevel [Byte0]: 32
7910 13:19:26.926496 [Byte1]: 32
7911 13:19:26.930628
7912 13:19:26.930961 Set Vref, RX VrefLevel [Byte0]: 33
7913 13:19:26.934353 [Byte1]: 33
7914 13:19:26.937947
7915 13:19:26.938279 Set Vref, RX VrefLevel [Byte0]: 34
7916 13:19:26.941768 [Byte1]: 34
7917 13:19:26.945622
7918 13:19:26.945947 Set Vref, RX VrefLevel [Byte0]: 35
7919 13:19:26.949355 [Byte1]: 35
7920 13:19:26.953601
7921 13:19:26.954054 Set Vref, RX VrefLevel [Byte0]: 36
7922 13:19:26.956744 [Byte1]: 36
7923 13:19:26.961054
7924 13:19:26.961471 Set Vref, RX VrefLevel [Byte0]: 37
7925 13:19:26.964428 [Byte1]: 37
7926 13:19:26.968977
7927 13:19:26.969519 Set Vref, RX VrefLevel [Byte0]: 38
7928 13:19:26.971927 [Byte1]: 38
7929 13:19:26.976430
7930 13:19:26.979409 Set Vref, RX VrefLevel [Byte0]: 39
7931 13:19:26.982921 [Byte1]: 39
7932 13:19:26.983384
7933 13:19:26.985935 Set Vref, RX VrefLevel [Byte0]: 40
7934 13:19:26.989649 [Byte1]: 40
7935 13:19:26.989988
7936 13:19:26.992574 Set Vref, RX VrefLevel [Byte0]: 41
7937 13:19:26.995705 [Byte1]: 41
7938 13:19:26.998842
7939 13:19:26.999190 Set Vref, RX VrefLevel [Byte0]: 42
7940 13:19:27.002326 [Byte1]: 42
7941 13:19:27.006948
7942 13:19:27.007323 Set Vref, RX VrefLevel [Byte0]: 43
7943 13:19:27.010071 [Byte1]: 43
7944 13:19:27.014538
7945 13:19:27.014894 Set Vref, RX VrefLevel [Byte0]: 44
7946 13:19:27.017839 [Byte1]: 44
7947 13:19:27.022080
7948 13:19:27.022454 Set Vref, RX VrefLevel [Byte0]: 45
7949 13:19:27.025274 [Byte1]: 45
7950 13:19:27.029765
7951 13:19:27.030137 Set Vref, RX VrefLevel [Byte0]: 46
7952 13:19:27.032898 [Byte1]: 46
7953 13:19:27.036920
7954 13:19:27.037250 Set Vref, RX VrefLevel [Byte0]: 47
7955 13:19:27.040741 [Byte1]: 47
7956 13:19:27.044553
7957 13:19:27.044890 Set Vref, RX VrefLevel [Byte0]: 48
7958 13:19:27.048285 [Byte1]: 48
7959 13:19:27.052694
7960 13:19:27.053186 Set Vref, RX VrefLevel [Byte0]: 49
7961 13:19:27.055743 [Byte1]: 49
7962 13:19:27.060113
7963 13:19:27.060562 Set Vref, RX VrefLevel [Byte0]: 50
7964 13:19:27.063258 [Byte1]: 50
7965 13:19:27.067801
7966 13:19:27.068158 Set Vref, RX VrefLevel [Byte0]: 51
7967 13:19:27.070881 [Byte1]: 51
7968 13:19:27.075134
7969 13:19:27.078167 Set Vref, RX VrefLevel [Byte0]: 52
7970 13:19:27.081715 [Byte1]: 52
7971 13:19:27.082044
7972 13:19:27.085225 Set Vref, RX VrefLevel [Byte0]: 53
7973 13:19:27.088214 [Byte1]: 53
7974 13:19:27.088538
7975 13:19:27.091938 Set Vref, RX VrefLevel [Byte0]: 54
7976 13:19:27.094813 [Byte1]: 54
7977 13:19:27.097985
7978 13:19:27.098305 Set Vref, RX VrefLevel [Byte0]: 55
7979 13:19:27.101656 [Byte1]: 55
7980 13:19:27.105931
7981 13:19:27.106327 Set Vref, RX VrefLevel [Byte0]: 56
7982 13:19:27.109048 [Byte1]: 56
7983 13:19:27.113046
7984 13:19:27.113363 Set Vref, RX VrefLevel [Byte0]: 57
7985 13:19:27.116886 [Byte1]: 57
7986 13:19:27.120753
7987 13:19:27.121071 Set Vref, RX VrefLevel [Byte0]: 58
7988 13:19:27.124517 [Byte1]: 58
7989 13:19:27.128429
7990 13:19:27.129039 Set Vref, RX VrefLevel [Byte0]: 59
7991 13:19:27.131584 [Byte1]: 59
7992 13:19:27.136191
7993 13:19:27.136596 Set Vref, RX VrefLevel [Byte0]: 60
7994 13:19:27.139261 [Byte1]: 60
7995 13:19:27.143547
7996 13:19:27.143954 Set Vref, RX VrefLevel [Byte0]: 61
7997 13:19:27.147130 [Byte1]: 61
7998 13:19:27.151597
7999 13:19:27.151978 Set Vref, RX VrefLevel [Byte0]: 62
8000 13:19:27.154825 [Byte1]: 62
8001 13:19:27.159161
8002 13:19:27.159642 Set Vref, RX VrefLevel [Byte0]: 63
8003 13:19:27.162186 [Byte1]: 63
8004 13:19:27.166597
8005 13:19:27.166900 Set Vref, RX VrefLevel [Byte0]: 64
8006 13:19:27.169851 [Byte1]: 64
8007 13:19:27.174286
8008 13:19:27.177379 Set Vref, RX VrefLevel [Byte0]: 65
8009 13:19:27.180683 [Byte1]: 65
8010 13:19:27.181029
8011 13:19:27.183921 Set Vref, RX VrefLevel [Byte0]: 66
8012 13:19:27.187274 [Byte1]: 66
8013 13:19:27.187732
8014 13:19:27.190689 Set Vref, RX VrefLevel [Byte0]: 67
8015 13:19:27.193648 [Byte1]: 67
8016 13:19:27.196947
8017 13:19:27.197271 Set Vref, RX VrefLevel [Byte0]: 68
8018 13:19:27.200123 [Byte1]: 68
8019 13:19:27.204861
8020 13:19:27.205233 Set Vref, RX VrefLevel [Byte0]: 69
8021 13:19:27.208107 [Byte1]: 69
8022 13:19:27.212033
8023 13:19:27.212355 Set Vref, RX VrefLevel [Byte0]: 70
8024 13:19:27.215521 [Byte1]: 70
8025 13:19:27.219879
8026 13:19:27.220253 Set Vref, RX VrefLevel [Byte0]: 71
8027 13:19:27.223348 [Byte1]: 71
8028 13:19:27.227848
8029 13:19:27.228211 Set Vref, RX VrefLevel [Byte0]: 72
8030 13:19:27.230813 [Byte1]: 72
8031 13:19:27.235302
8032 13:19:27.235701 Set Vref, RX VrefLevel [Byte0]: 73
8033 13:19:27.238533 [Byte1]: 73
8034 13:19:27.242968
8035 13:19:27.243316 Set Vref, RX VrefLevel [Byte0]: 74
8036 13:19:27.246209 [Byte1]: 74
8037 13:19:27.250558
8038 13:19:27.250977 Set Vref, RX VrefLevel [Byte0]: 75
8039 13:19:27.253573 [Byte1]: 75
8040 13:19:27.257784
8041 13:19:27.258132 Set Vref, RX VrefLevel [Byte0]: 76
8042 13:19:27.261665 [Byte1]: 76
8043 13:19:27.265472
8044 13:19:27.265821 Set Vref, RX VrefLevel [Byte0]: 77
8045 13:19:27.269126 [Byte1]: 77
8046 13:19:27.273530
8047 13:19:27.273877 Set Vref, RX VrefLevel [Byte0]: 78
8048 13:19:27.276609 [Byte1]: 78
8049 13:19:27.280992
8050 13:19:27.281338 Set Vref, RX VrefLevel [Byte0]: 79
8051 13:19:27.284191 [Byte1]: 79
8052 13:19:27.288662
8053 13:19:27.289029 Final RX Vref Byte 0 = 69 to rank0
8054 13:19:27.291896 Final RX Vref Byte 1 = 57 to rank0
8055 13:19:27.295144 Final RX Vref Byte 0 = 69 to rank1
8056 13:19:27.298384 Final RX Vref Byte 1 = 57 to rank1==
8057 13:19:27.301509 Dram Type= 6, Freq= 0, CH_0, rank 0
8058 13:19:27.308278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 13:19:27.308670 ==
8060 13:19:27.308948 DQS Delay:
8061 13:19:27.311279 DQS0 = 0, DQS1 = 0
8062 13:19:27.311705 DQM Delay:
8063 13:19:27.314585 DQM0 = 132, DQM1 = 123
8064 13:19:27.314943 DQ Delay:
8065 13:19:27.317967 DQ0 =130, DQ1 =136, DQ2 =130, DQ3 =130
8066 13:19:27.321283 DQ4 =134, DQ5 =120, DQ6 =140, DQ7 =142
8067 13:19:27.324711 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =118
8068 13:19:27.327948 DQ12 =130, DQ13 =128, DQ14 =134, DQ15 =128
8069 13:19:27.328299
8070 13:19:27.328570
8071 13:19:27.328898
8072 13:19:27.331246 [DramC_TX_OE_Calibration] TA2
8073 13:19:27.334300 Original DQ_B0 (3 6) =30, OEN = 27
8074 13:19:27.337755 Original DQ_B1 (3 6) =30, OEN = 27
8075 13:19:27.340975 24, 0x0, End_B0=24 End_B1=24
8076 13:19:27.344168 25, 0x0, End_B0=25 End_B1=25
8077 13:19:27.344523 26, 0x0, End_B0=26 End_B1=26
8078 13:19:27.347326 27, 0x0, End_B0=27 End_B1=27
8079 13:19:27.351165 28, 0x0, End_B0=28 End_B1=28
8080 13:19:27.354186 29, 0x0, End_B0=29 End_B1=29
8081 13:19:27.354542 30, 0x0, End_B0=30 End_B1=30
8082 13:19:27.357441 31, 0x4141, End_B0=30 End_B1=30
8083 13:19:27.360481 Byte0 end_step=30 best_step=27
8084 13:19:27.364003 Byte1 end_step=30 best_step=27
8085 13:19:27.367454 Byte0 TX OE(2T, 0.5T) = (3, 3)
8086 13:19:27.370540 Byte1 TX OE(2T, 0.5T) = (3, 3)
8087 13:19:27.370890
8088 13:19:27.371162
8089 13:19:27.377019 [DQSOSCAuto] RK0, (LSB)MR18= 0x2314, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
8090 13:19:27.380835 CH0 RK0: MR19=303, MR18=2314
8091 13:19:27.387299 CH0_RK0: MR19=0x303, MR18=0x2314, DQSOSC=392, MR23=63, INC=24, DEC=16
8092 13:19:27.387703
8093 13:19:27.390413 ----->DramcWriteLeveling(PI) begin...
8094 13:19:27.390781 ==
8095 13:19:27.393668 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 13:19:27.396758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 13:19:27.397112 ==
8098 13:19:27.400120 Write leveling (Byte 0): 33 => 33
8099 13:19:27.403381 Write leveling (Byte 1): 29 => 29
8100 13:19:27.406593 DramcWriteLeveling(PI) end<-----
8101 13:19:27.406943
8102 13:19:27.407216 ==
8103 13:19:27.410198 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 13:19:27.416510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 13:19:27.416995 ==
8106 13:19:27.417434 [Gating] SW mode calibration
8107 13:19:27.426653 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8108 13:19:27.430221 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8109 13:19:27.436274 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8110 13:19:27.439762 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8111 13:19:27.443049 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8112 13:19:27.449666 1 4 12 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
8113 13:19:27.453221 1 4 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
8114 13:19:27.456461 1 4 20 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
8115 13:19:27.462858 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8116 13:19:27.466110 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8117 13:19:27.469331 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8118 13:19:27.476455 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8119 13:19:27.479281 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8120 13:19:27.482983 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
8121 13:19:27.486289 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
8122 13:19:27.492598 1 5 20 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
8123 13:19:27.495804 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8124 13:19:27.499671 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8125 13:19:27.506021 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8126 13:19:27.509204 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8127 13:19:27.512458 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8128 13:19:27.519183 1 6 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
8129 13:19:27.522358 1 6 16 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
8130 13:19:27.525599 1 6 20 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
8131 13:19:27.532505 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8132 13:19:27.536115 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8133 13:19:27.539174 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8134 13:19:27.545446 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8135 13:19:27.549151 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8136 13:19:27.552247 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8137 13:19:27.558708 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8138 13:19:27.562036 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8139 13:19:27.565309 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8140 13:19:27.572008 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8141 13:19:27.575121 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8142 13:19:27.578353 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8143 13:19:27.585244 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8144 13:19:27.588622 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8145 13:19:27.591709 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 13:19:27.597930 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 13:19:27.601133 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 13:19:27.605101 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 13:19:27.611521 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 13:19:27.614733 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 13:19:27.617764 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8152 13:19:27.624440 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8153 13:19:27.627570 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8154 13:19:27.630860 Total UI for P1: 0, mck2ui 16
8155 13:19:27.634623 best dqsien dly found for B0: ( 1, 9, 10)
8156 13:19:27.637661 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8157 13:19:27.644404 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8158 13:19:27.647353 Total UI for P1: 0, mck2ui 16
8159 13:19:27.650918 best dqsien dly found for B1: ( 1, 9, 18)
8160 13:19:27.654361 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8161 13:19:27.657362 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8162 13:19:27.657710
8163 13:19:27.660591 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8164 13:19:27.664424 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8165 13:19:27.667560 [Gating] SW calibration Done
8166 13:19:27.667931 ==
8167 13:19:27.670650 Dram Type= 6, Freq= 0, CH_0, rank 1
8168 13:19:27.674297 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8169 13:19:27.674656 ==
8170 13:19:27.677546 RX Vref Scan: 0
8171 13:19:27.677898
8172 13:19:27.680890 RX Vref 0 -> 0, step: 1
8173 13:19:27.681251
8174 13:19:27.681521 RX Delay 0 -> 252, step: 8
8175 13:19:27.687341 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8176 13:19:27.690493 iDelay=200, Bit 1, Center 139 (80 ~ 199) 120
8177 13:19:27.693656 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8178 13:19:27.697302 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8179 13:19:27.700373 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8180 13:19:27.706633 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8181 13:19:27.709878 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8182 13:19:27.713801 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8183 13:19:27.716943 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8184 13:19:27.723322 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8185 13:19:27.726423 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8186 13:19:27.730210 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8187 13:19:27.733386 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8188 13:19:27.736637 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8189 13:19:27.742940 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8190 13:19:27.746644 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8191 13:19:27.747014 ==
8192 13:19:27.749612 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 13:19:27.752817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 13:19:27.753174 ==
8195 13:19:27.756527 DQS Delay:
8196 13:19:27.756879 DQS0 = 0, DQS1 = 0
8197 13:19:27.757153 DQM Delay:
8198 13:19:27.759523 DQM0 = 134, DQM1 = 127
8199 13:19:27.759879 DQ Delay:
8200 13:19:27.763129 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =127
8201 13:19:27.765914 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8202 13:19:27.772710 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8203 13:19:27.776398 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8204 13:19:27.776750
8205 13:19:27.777022
8206 13:19:27.777275 ==
8207 13:19:27.779568 Dram Type= 6, Freq= 0, CH_0, rank 1
8208 13:19:27.782834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8209 13:19:27.783189 ==
8210 13:19:27.783503
8211 13:19:27.783766
8212 13:19:27.785898 TX Vref Scan disable
8213 13:19:27.789541 == TX Byte 0 ==
8214 13:19:27.792359 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8215 13:19:27.795643 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8216 13:19:27.799134 == TX Byte 1 ==
8217 13:19:27.802485 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8218 13:19:27.805742 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8219 13:19:27.806289 ==
8220 13:19:27.808791 Dram Type= 6, Freq= 0, CH_0, rank 1
8221 13:19:27.812274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8222 13:19:27.815344 ==
8223 13:19:27.826003
8224 13:19:27.829046 TX Vref early break, caculate TX vref
8225 13:19:27.832986 TX Vref=16, minBit 1, minWin=22, winSum=379
8226 13:19:27.836219 TX Vref=18, minBit 1, minWin=22, winSum=387
8227 13:19:27.839487 TX Vref=20, minBit 1, minWin=22, winSum=396
8228 13:19:27.842739 TX Vref=22, minBit 1, minWin=24, winSum=406
8229 13:19:27.845993 TX Vref=24, minBit 1, minWin=24, winSum=413
8230 13:19:27.852002 TX Vref=26, minBit 1, minWin=25, winSum=419
8231 13:19:27.855887 TX Vref=28, minBit 1, minWin=24, winSum=414
8232 13:19:27.859087 TX Vref=30, minBit 0, minWin=24, winSum=407
8233 13:19:27.862242 TX Vref=32, minBit 1, minWin=23, winSum=396
8234 13:19:27.868601 [TxChooseVref] Worse bit 1, Min win 25, Win sum 419, Final Vref 26
8235 13:19:27.869059
8236 13:19:27.872045 Final TX Range 0 Vref 26
8237 13:19:27.872496
8238 13:19:27.872902 ==
8239 13:19:27.875597 Dram Type= 6, Freq= 0, CH_0, rank 1
8240 13:19:27.878538 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8241 13:19:27.878908 ==
8242 13:19:27.879184
8243 13:19:27.879471
8244 13:19:27.882089 TX Vref Scan disable
8245 13:19:27.888519 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8246 13:19:27.888870 == TX Byte 0 ==
8247 13:19:27.891700 u2DelayCellOfst[0]=14 cells (4 PI)
8248 13:19:27.894841 u2DelayCellOfst[1]=22 cells (6 PI)
8249 13:19:27.898049 u2DelayCellOfst[2]=14 cells (4 PI)
8250 13:19:27.901634 u2DelayCellOfst[3]=18 cells (5 PI)
8251 13:19:27.905084 u2DelayCellOfst[4]=14 cells (4 PI)
8252 13:19:27.908188 u2DelayCellOfst[5]=0 cells (0 PI)
8253 13:19:27.911279 u2DelayCellOfst[6]=22 cells (6 PI)
8254 13:19:27.914703 u2DelayCellOfst[7]=22 cells (6 PI)
8255 13:19:27.918019 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8256 13:19:27.921567 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8257 13:19:27.924437 == TX Byte 1 ==
8258 13:19:27.928226 u2DelayCellOfst[8]=0 cells (0 PI)
8259 13:19:27.931253 u2DelayCellOfst[9]=3 cells (1 PI)
8260 13:19:27.931703 u2DelayCellOfst[10]=7 cells (2 PI)
8261 13:19:27.934381 u2DelayCellOfst[11]=3 cells (1 PI)
8262 13:19:27.937642 u2DelayCellOfst[12]=14 cells (4 PI)
8263 13:19:27.941465 u2DelayCellOfst[13]=14 cells (4 PI)
8264 13:19:27.944689 u2DelayCellOfst[14]=18 cells (5 PI)
8265 13:19:27.947922 u2DelayCellOfst[15]=11 cells (3 PI)
8266 13:19:27.954295 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8267 13:19:27.957419 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8268 13:19:27.957837 DramC Write-DBI on
8269 13:19:27.958117 ==
8270 13:19:27.961075 Dram Type= 6, Freq= 0, CH_0, rank 1
8271 13:19:27.967512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8272 13:19:27.967919 ==
8273 13:19:27.968246
8274 13:19:27.968569
8275 13:19:27.968816 TX Vref Scan disable
8276 13:19:27.971310 == TX Byte 0 ==
8277 13:19:27.975071 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8278 13:19:27.978201 == TX Byte 1 ==
8279 13:19:27.981394 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8280 13:19:27.985049 DramC Write-DBI off
8281 13:19:27.985399
8282 13:19:27.985673 [DATLAT]
8283 13:19:27.985929 Freq=1600, CH0 RK1
8284 13:19:27.986175
8285 13:19:27.987993 DATLAT Default: 0xf
8286 13:19:27.991540 0, 0xFFFF, sum = 0
8287 13:19:27.991896 1, 0xFFFF, sum = 0
8288 13:19:27.994685 2, 0xFFFF, sum = 0
8289 13:19:27.995040 3, 0xFFFF, sum = 0
8290 13:19:27.997860 4, 0xFFFF, sum = 0
8291 13:19:27.998218 5, 0xFFFF, sum = 0
8292 13:19:28.001036 6, 0xFFFF, sum = 0
8293 13:19:28.001393 7, 0xFFFF, sum = 0
8294 13:19:28.004322 8, 0xFFFF, sum = 0
8295 13:19:28.004676 9, 0xFFFF, sum = 0
8296 13:19:28.007521 10, 0xFFFF, sum = 0
8297 13:19:28.007945 11, 0xFFFF, sum = 0
8298 13:19:28.011194 12, 0xFFFF, sum = 0
8299 13:19:28.011582 13, 0xFFFF, sum = 0
8300 13:19:28.014615 14, 0x0, sum = 1
8301 13:19:28.014967 15, 0x0, sum = 2
8302 13:19:28.017706 16, 0x0, sum = 3
8303 13:19:28.018128 17, 0x0, sum = 4
8304 13:19:28.020860 best_step = 15
8305 13:19:28.021207
8306 13:19:28.021473 ==
8307 13:19:28.024597 Dram Type= 6, Freq= 0, CH_0, rank 1
8308 13:19:28.027631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8309 13:19:28.027982 ==
8310 13:19:28.030848 RX Vref Scan: 0
8311 13:19:28.031200
8312 13:19:28.031515 RX Vref 0 -> 0, step: 1
8313 13:19:28.031781
8314 13:19:28.034204 RX Delay 11 -> 252, step: 4
8315 13:19:28.040977 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8316 13:19:28.044011 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
8317 13:19:28.047219 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8318 13:19:28.050957 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8319 13:19:28.054323 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8320 13:19:28.060742 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8321 13:19:28.064143 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8322 13:19:28.067303 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8323 13:19:28.070739 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8324 13:19:28.073950 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8325 13:19:28.080158 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8326 13:19:28.083956 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8327 13:19:28.087226 iDelay=195, Bit 12, Center 128 (75 ~ 182) 108
8328 13:19:28.090372 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8329 13:19:28.097159 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8330 13:19:28.100018 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8331 13:19:28.100406 ==
8332 13:19:28.103243 Dram Type= 6, Freq= 0, CH_0, rank 1
8333 13:19:28.106541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8334 13:19:28.106929 ==
8335 13:19:28.110369 DQS Delay:
8336 13:19:28.110752 DQS0 = 0, DQS1 = 0
8337 13:19:28.111050 DQM Delay:
8338 13:19:28.113669 DQM0 = 129, DQM1 = 125
8339 13:19:28.114054 DQ Delay:
8340 13:19:28.116861 DQ0 =128, DQ1 =132, DQ2 =126, DQ3 =126
8341 13:19:28.119866 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =140
8342 13:19:28.123399 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8343 13:19:28.129944 DQ12 =128, DQ13 =132, DQ14 =136, DQ15 =132
8344 13:19:28.130506
8345 13:19:28.130979
8346 13:19:28.131454
8347 13:19:28.132939 [DramC_TX_OE_Calibration] TA2
8348 13:19:28.136512 Original DQ_B0 (3 6) =30, OEN = 27
8349 13:19:28.137009 Original DQ_B1 (3 6) =30, OEN = 27
8350 13:19:28.139457 24, 0x0, End_B0=24 End_B1=24
8351 13:19:28.142997 25, 0x0, End_B0=25 End_B1=25
8352 13:19:28.146038 26, 0x0, End_B0=26 End_B1=26
8353 13:19:28.149445 27, 0x0, End_B0=27 End_B1=27
8354 13:19:28.149979 28, 0x0, End_B0=28 End_B1=28
8355 13:19:28.152803 29, 0x0, End_B0=29 End_B1=29
8356 13:19:28.155824 30, 0x0, End_B0=30 End_B1=30
8357 13:19:28.159043 31, 0x4141, End_B0=30 End_B1=30
8358 13:19:28.162825 Byte0 end_step=30 best_step=27
8359 13:19:28.165983 Byte1 end_step=30 best_step=27
8360 13:19:28.166498 Byte0 TX OE(2T, 0.5T) = (3, 3)
8361 13:19:28.169008 Byte1 TX OE(2T, 0.5T) = (3, 3)
8362 13:19:28.169463
8363 13:19:28.169766
8364 13:19:28.178857 [DQSOSCAuto] RK1, (LSB)MR18= 0x2105, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
8365 13:19:28.182712 CH0 RK1: MR19=303, MR18=2105
8366 13:19:28.188980 CH0_RK1: MR19=0x303, MR18=0x2105, DQSOSC=393, MR23=63, INC=23, DEC=15
8367 13:19:28.189417 [RxdqsGatingPostProcess] freq 1600
8368 13:19:28.195271 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8369 13:19:28.199144 best DQS0 dly(2T, 0.5T) = (1, 1)
8370 13:19:28.202283 best DQS1 dly(2T, 0.5T) = (1, 1)
8371 13:19:28.205279 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8372 13:19:28.208701 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8373 13:19:28.211788 best DQS0 dly(2T, 0.5T) = (1, 1)
8374 13:19:28.215616 best DQS1 dly(2T, 0.5T) = (1, 1)
8375 13:19:28.218667 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8376 13:19:28.221793 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8377 13:19:28.222248 Pre-setting of DQS Precalculation
8378 13:19:28.227948 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8379 13:19:28.228249 ==
8380 13:19:28.231566 Dram Type= 6, Freq= 0, CH_1, rank 0
8381 13:19:28.235130 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8382 13:19:28.235300 ==
8383 13:19:28.241569 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8384 13:19:28.244563 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8385 13:19:28.251284 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8386 13:19:28.254561 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8387 13:19:28.264638 [CA 0] Center 42 (13~72) winsize 60
8388 13:19:28.267762 [CA 1] Center 42 (13~72) winsize 60
8389 13:19:28.271332 [CA 2] Center 38 (9~67) winsize 59
8390 13:19:28.274349 [CA 3] Center 36 (7~66) winsize 60
8391 13:19:28.277737 [CA 4] Center 38 (9~67) winsize 59
8392 13:19:28.280912 [CA 5] Center 37 (8~67) winsize 60
8393 13:19:28.280989
8394 13:19:28.284065 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8395 13:19:28.284141
8396 13:19:28.287250 [CATrainingPosCal] consider 1 rank data
8397 13:19:28.290507 u2DelayCellTimex100 = 262/100 ps
8398 13:19:28.297572 CA0 delay=42 (13~72),Diff = 6 PI (22 cell)
8399 13:19:28.300573 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8400 13:19:28.303680 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8401 13:19:28.307488 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8402 13:19:28.310638 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8403 13:19:28.313740 CA5 delay=37 (8~67),Diff = 1 PI (3 cell)
8404 13:19:28.313820
8405 13:19:28.316808 CA PerBit enable=1, Macro0, CA PI delay=36
8406 13:19:28.316895
8407 13:19:28.320566 [CBTSetCACLKResult] CA Dly = 36
8408 13:19:28.323723 CS Dly: 9 (0~40)
8409 13:19:28.326806 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8410 13:19:28.330637 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8411 13:19:28.330750 ==
8412 13:19:28.333995 Dram Type= 6, Freq= 0, CH_1, rank 1
8413 13:19:28.340333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8414 13:19:28.340472 ==
8415 13:19:28.344017 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8416 13:19:28.350303 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8417 13:19:28.353875 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8418 13:19:28.360044 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8419 13:19:28.367824 [CA 0] Center 42 (13~72) winsize 60
8420 13:19:28.371616 [CA 1] Center 42 (13~72) winsize 60
8421 13:19:28.374570 [CA 2] Center 37 (8~67) winsize 60
8422 13:19:28.377988 [CA 3] Center 37 (8~66) winsize 59
8423 13:19:28.381215 [CA 4] Center 37 (8~67) winsize 60
8424 13:19:28.384236 [CA 5] Center 37 (8~67) winsize 60
8425 13:19:28.384752
8426 13:19:28.387392 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8427 13:19:28.387789
8428 13:19:28.393864 [CATrainingPosCal] consider 2 rank data
8429 13:19:28.394245 u2DelayCellTimex100 = 262/100 ps
8430 13:19:28.400815 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8431 13:19:28.403933 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8432 13:19:28.407268 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8433 13:19:28.410445 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8434 13:19:28.413658 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8435 13:19:28.416840 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8436 13:19:28.417220
8437 13:19:28.419994 CA PerBit enable=1, Macro0, CA PI delay=37
8438 13:19:28.420513
8439 13:19:28.423792 [CBTSetCACLKResult] CA Dly = 37
8440 13:19:28.426792 CS Dly: 11 (0~44)
8441 13:19:28.429771 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8442 13:19:28.433750 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8443 13:19:28.434132
8444 13:19:28.436387 ----->DramcWriteLeveling(PI) begin...
8445 13:19:28.440195 ==
8446 13:19:28.443454 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 13:19:28.446596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 13:19:28.446983 ==
8449 13:19:28.449790 Write leveling (Byte 0): 23 => 23
8450 13:19:28.452902 Write leveling (Byte 1): 26 => 26
8451 13:19:28.456534 DramcWriteLeveling(PI) end<-----
8452 13:19:28.456916
8453 13:19:28.457254 ==
8454 13:19:28.459413 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 13:19:28.462767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 13:19:28.463194 ==
8457 13:19:28.466411 [Gating] SW mode calibration
8458 13:19:28.473142 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8459 13:19:28.479618 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8460 13:19:28.482839 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8461 13:19:28.485958 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8462 13:19:28.492865 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8463 13:19:28.495826 1 4 12 | B1->B0 | 2b2b 3433 | 1 1 | (1 1) (1 1)
8464 13:19:28.498970 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8465 13:19:28.506111 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8466 13:19:28.509232 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8467 13:19:28.512439 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8468 13:19:28.518939 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8469 13:19:28.522082 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8470 13:19:28.525964 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8471 13:19:28.532179 1 5 12 | B1->B0 | 3434 2828 | 0 0 | (0 1) (1 0)
8472 13:19:28.535637 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8473 13:19:28.538680 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8474 13:19:28.545712 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8475 13:19:28.548730 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8476 13:19:28.551952 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8477 13:19:28.558304 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8478 13:19:28.562108 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8479 13:19:28.565119 1 6 12 | B1->B0 | 3434 4444 | 0 0 | (0 0) (0 0)
8480 13:19:28.571794 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8481 13:19:28.575285 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8482 13:19:28.578140 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8483 13:19:28.585182 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8484 13:19:28.588403 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8485 13:19:28.591420 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8486 13:19:28.598476 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8487 13:19:28.601721 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8488 13:19:28.604635 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8489 13:19:28.611322 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8490 13:19:28.614589 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8491 13:19:28.618310 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8492 13:19:28.624552 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8493 13:19:28.627804 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8494 13:19:28.630997 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8495 13:19:28.638090 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8496 13:19:28.641136 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 13:19:28.644118 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 13:19:28.650896 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 13:19:28.654010 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 13:19:28.657215 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 13:19:28.664350 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 13:19:28.667538 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8503 13:19:28.670630 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8504 13:19:28.677340 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8505 13:19:28.677727 Total UI for P1: 0, mck2ui 16
8506 13:19:28.684054 best dqsien dly found for B0: ( 1, 9, 10)
8507 13:19:28.684443 Total UI for P1: 0, mck2ui 16
8508 13:19:28.690621 best dqsien dly found for B1: ( 1, 9, 10)
8509 13:19:28.693779 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8510 13:19:28.697484 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8511 13:19:28.697882
8512 13:19:28.700762 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8513 13:19:28.703900 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8514 13:19:28.707166 [Gating] SW calibration Done
8515 13:19:28.707597 ==
8516 13:19:28.710378 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 13:19:28.713509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 13:19:28.713908 ==
8519 13:19:28.716644 RX Vref Scan: 0
8520 13:19:28.717037
8521 13:19:28.717427 RX Vref 0 -> 0, step: 1
8522 13:19:28.717792
8523 13:19:28.720357 RX Delay 0 -> 252, step: 8
8524 13:19:28.723700 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8525 13:19:28.730067 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8526 13:19:28.733307 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8527 13:19:28.736541 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8528 13:19:28.739794 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8529 13:19:28.743492 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8530 13:19:28.749917 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8531 13:19:28.753457 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8532 13:19:28.756457 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8533 13:19:28.759976 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8534 13:19:28.763056 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8535 13:19:28.769596 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8536 13:19:28.772752 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8537 13:19:28.776513 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8538 13:19:28.779512 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8539 13:19:28.786371 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8540 13:19:28.786767 ==
8541 13:19:28.789361 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 13:19:28.792919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 13:19:28.793317 ==
8544 13:19:28.793711 DQS Delay:
8545 13:19:28.796369 DQS0 = 0, DQS1 = 0
8546 13:19:28.796763 DQM Delay:
8547 13:19:28.799372 DQM0 = 138, DQM1 = 128
8548 13:19:28.799823 DQ Delay:
8549 13:19:28.802562 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =135
8550 13:19:28.805708 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8551 13:19:28.809647 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8552 13:19:28.812759 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8553 13:19:28.815924
8554 13:19:28.816315
8555 13:19:28.816705 ==
8556 13:19:28.819160 Dram Type= 6, Freq= 0, CH_1, rank 0
8557 13:19:28.822314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8558 13:19:28.822710 ==
8559 13:19:28.823100
8560 13:19:28.823493
8561 13:19:28.825567 TX Vref Scan disable
8562 13:19:28.825965 == TX Byte 0 ==
8563 13:19:28.832104 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8564 13:19:28.835682 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8565 13:19:28.836083 == TX Byte 1 ==
8566 13:19:28.842056 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8567 13:19:28.845056 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8568 13:19:28.845453 ==
8569 13:19:28.848977 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 13:19:28.852278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 13:19:28.852692 ==
8572 13:19:28.865647
8573 13:19:28.868906 TX Vref early break, caculate TX vref
8574 13:19:28.872469 TX Vref=16, minBit 0, minWin=21, winSum=374
8575 13:19:28.875343 TX Vref=18, minBit 0, minWin=22, winSum=382
8576 13:19:28.879164 TX Vref=20, minBit 0, minWin=22, winSum=393
8577 13:19:28.882378 TX Vref=22, minBit 5, minWin=23, winSum=403
8578 13:19:28.885378 TX Vref=24, minBit 0, minWin=24, winSum=414
8579 13:19:28.892090 TX Vref=26, minBit 0, minWin=24, winSum=421
8580 13:19:28.895356 TX Vref=28, minBit 0, minWin=24, winSum=420
8581 13:19:28.898512 TX Vref=30, minBit 5, minWin=24, winSum=413
8582 13:19:28.901703 TX Vref=32, minBit 0, minWin=23, winSum=401
8583 13:19:28.905113 TX Vref=34, minBit 0, minWin=23, winSum=395
8584 13:19:28.911669 [TxChooseVref] Worse bit 0, Min win 24, Win sum 421, Final Vref 26
8585 13:19:28.912185
8586 13:19:28.915404 Final TX Range 0 Vref 26
8587 13:19:28.915851
8588 13:19:28.916238 ==
8589 13:19:28.918508 Dram Type= 6, Freq= 0, CH_1, rank 0
8590 13:19:28.921942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8591 13:19:28.922344 ==
8592 13:19:28.922737
8593 13:19:28.923103
8594 13:19:28.925068 TX Vref Scan disable
8595 13:19:28.931983 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8596 13:19:28.932382 == TX Byte 0 ==
8597 13:19:28.935154 u2DelayCellOfst[0]=14 cells (4 PI)
8598 13:19:28.938380 u2DelayCellOfst[1]=11 cells (3 PI)
8599 13:19:28.941582 u2DelayCellOfst[2]=0 cells (0 PI)
8600 13:19:28.944775 u2DelayCellOfst[3]=3 cells (1 PI)
8601 13:19:28.948183 u2DelayCellOfst[4]=7 cells (2 PI)
8602 13:19:28.951737 u2DelayCellOfst[5]=18 cells (5 PI)
8603 13:19:28.954966 u2DelayCellOfst[6]=18 cells (5 PI)
8604 13:19:28.958033 u2DelayCellOfst[7]=3 cells (1 PI)
8605 13:19:28.961316 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8606 13:19:28.964597 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8607 13:19:28.967972 == TX Byte 1 ==
8608 13:19:28.971749 u2DelayCellOfst[8]=0 cells (0 PI)
8609 13:19:28.972134 u2DelayCellOfst[9]=3 cells (1 PI)
8610 13:19:28.974878 u2DelayCellOfst[10]=11 cells (3 PI)
8611 13:19:28.977771 u2DelayCellOfst[11]=3 cells (1 PI)
8612 13:19:28.981165 u2DelayCellOfst[12]=14 cells (4 PI)
8613 13:19:28.984820 u2DelayCellOfst[13]=14 cells (4 PI)
8614 13:19:28.987683 u2DelayCellOfst[14]=18 cells (5 PI)
8615 13:19:28.990872 u2DelayCellOfst[15]=18 cells (5 PI)
8616 13:19:28.997470 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8617 13:19:29.001240 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8618 13:19:29.001642 DramC Write-DBI on
8619 13:19:29.001941 ==
8620 13:19:29.004365 Dram Type= 6, Freq= 0, CH_1, rank 0
8621 13:19:29.011292 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8622 13:19:29.011795 ==
8623 13:19:29.012100
8624 13:19:29.012373
8625 13:19:29.012638 TX Vref Scan disable
8626 13:19:29.014957 == TX Byte 0 ==
8627 13:19:29.018441 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8628 13:19:29.021457 == TX Byte 1 ==
8629 13:19:29.024725 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8630 13:19:29.027934 DramC Write-DBI off
8631 13:19:29.028335
8632 13:19:29.028634 [DATLAT]
8633 13:19:29.028942 Freq=1600, CH1 RK0
8634 13:19:29.029246
8635 13:19:29.031334 DATLAT Default: 0xf
8636 13:19:29.034433 0, 0xFFFF, sum = 0
8637 13:19:29.034825 1, 0xFFFF, sum = 0
8638 13:19:29.038210 2, 0xFFFF, sum = 0
8639 13:19:29.038625 3, 0xFFFF, sum = 0
8640 13:19:29.041294 4, 0xFFFF, sum = 0
8641 13:19:29.041685 5, 0xFFFF, sum = 0
8642 13:19:29.044555 6, 0xFFFF, sum = 0
8643 13:19:29.044968 7, 0xFFFF, sum = 0
8644 13:19:29.047970 8, 0xFFFF, sum = 0
8645 13:19:29.048360 9, 0xFFFF, sum = 0
8646 13:19:29.051123 10, 0xFFFF, sum = 0
8647 13:19:29.051554 11, 0xFFFF, sum = 0
8648 13:19:29.054302 12, 0xFFFF, sum = 0
8649 13:19:29.054728 13, 0xFFFF, sum = 0
8650 13:19:29.058011 14, 0x0, sum = 1
8651 13:19:29.058416 15, 0x0, sum = 2
8652 13:19:29.061014 16, 0x0, sum = 3
8653 13:19:29.061403 17, 0x0, sum = 4
8654 13:19:29.064639 best_step = 15
8655 13:19:29.065025
8656 13:19:29.065348 ==
8657 13:19:29.067875 Dram Type= 6, Freq= 0, CH_1, rank 0
8658 13:19:29.070955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8659 13:19:29.071342 ==
8660 13:19:29.074175 RX Vref Scan: 1
8661 13:19:29.074560
8662 13:19:29.074859 Set Vref Range= 24 -> 127
8663 13:19:29.075197
8664 13:19:29.077394 RX Vref 24 -> 127, step: 1
8665 13:19:29.077779
8666 13:19:29.080584 RX Delay 11 -> 252, step: 4
8667 13:19:29.080969
8668 13:19:29.084326 Set Vref, RX VrefLevel [Byte0]: 24
8669 13:19:29.087358 [Byte1]: 24
8670 13:19:29.087790
8671 13:19:29.091018 Set Vref, RX VrefLevel [Byte0]: 25
8672 13:19:29.094026 [Byte1]: 25
8673 13:19:29.097435
8674 13:19:29.097835 Set Vref, RX VrefLevel [Byte0]: 26
8675 13:19:29.101001 [Byte1]: 26
8676 13:19:29.105261
8677 13:19:29.105776 Set Vref, RX VrefLevel [Byte0]: 27
8678 13:19:29.108512 [Byte1]: 27
8679 13:19:29.112958
8680 13:19:29.113344 Set Vref, RX VrefLevel [Byte0]: 28
8681 13:19:29.116124 [Byte1]: 28
8682 13:19:29.120609
8683 13:19:29.120993 Set Vref, RX VrefLevel [Byte0]: 29
8684 13:19:29.123657 [Byte1]: 29
8685 13:19:29.128430
8686 13:19:29.128843 Set Vref, RX VrefLevel [Byte0]: 30
8687 13:19:29.131671 [Byte1]: 30
8688 13:19:29.135484
8689 13:19:29.135871 Set Vref, RX VrefLevel [Byte0]: 31
8690 13:19:29.139312 [Byte1]: 31
8691 13:19:29.143075
8692 13:19:29.143483 Set Vref, RX VrefLevel [Byte0]: 32
8693 13:19:29.146785 [Byte1]: 32
8694 13:19:29.151271
8695 13:19:29.151742 Set Vref, RX VrefLevel [Byte0]: 33
8696 13:19:29.154427 [Byte1]: 33
8697 13:19:29.158867
8698 13:19:29.159260 Set Vref, RX VrefLevel [Byte0]: 34
8699 13:19:29.162152 [Byte1]: 34
8700 13:19:29.166085
8701 13:19:29.166467 Set Vref, RX VrefLevel [Byte0]: 35
8702 13:19:29.169273 [Byte1]: 35
8703 13:19:29.173892
8704 13:19:29.174274 Set Vref, RX VrefLevel [Byte0]: 36
8705 13:19:29.177375 [Byte1]: 36
8706 13:19:29.181615
8707 13:19:29.181998 Set Vref, RX VrefLevel [Byte0]: 37
8708 13:19:29.184661 [Byte1]: 37
8709 13:19:29.189186
8710 13:19:29.189570 Set Vref, RX VrefLevel [Byte0]: 38
8711 13:19:29.192418 [Byte1]: 38
8712 13:19:29.196909
8713 13:19:29.197294 Set Vref, RX VrefLevel [Byte0]: 39
8714 13:19:29.200076 [Byte1]: 39
8715 13:19:29.204239
8716 13:19:29.204664 Set Vref, RX VrefLevel [Byte0]: 40
8717 13:19:29.207743 [Byte1]: 40
8718 13:19:29.212257
8719 13:19:29.212642 Set Vref, RX VrefLevel [Byte0]: 41
8720 13:19:29.215291 [Byte1]: 41
8721 13:19:29.219517
8722 13:19:29.219918 Set Vref, RX VrefLevel [Byte0]: 42
8723 13:19:29.222532 [Byte1]: 42
8724 13:19:29.226913
8725 13:19:29.227318 Set Vref, RX VrefLevel [Byte0]: 43
8726 13:19:29.230749 [Byte1]: 43
8727 13:19:29.234978
8728 13:19:29.235362 Set Vref, RX VrefLevel [Byte0]: 44
8729 13:19:29.238095 [Byte1]: 44
8730 13:19:29.242544
8731 13:19:29.242933 Set Vref, RX VrefLevel [Byte0]: 45
8732 13:19:29.245556 [Byte1]: 45
8733 13:19:29.249964
8734 13:19:29.250349 Set Vref, RX VrefLevel [Byte0]: 46
8735 13:19:29.253140 [Byte1]: 46
8736 13:19:29.257502
8737 13:19:29.257891 Set Vref, RX VrefLevel [Byte0]: 47
8738 13:19:29.260761 [Byte1]: 47
8739 13:19:29.265295
8740 13:19:29.265679 Set Vref, RX VrefLevel [Byte0]: 48
8741 13:19:29.268516 [Byte1]: 48
8742 13:19:29.273081
8743 13:19:29.273464 Set Vref, RX VrefLevel [Byte0]: 49
8744 13:19:29.276304 [Byte1]: 49
8745 13:19:29.280523
8746 13:19:29.280908 Set Vref, RX VrefLevel [Byte0]: 50
8747 13:19:29.283565 [Byte1]: 50
8748 13:19:29.288003
8749 13:19:29.288542 Set Vref, RX VrefLevel [Byte0]: 51
8750 13:19:29.291142 [Byte1]: 51
8751 13:19:29.295605
8752 13:19:29.296015 Set Vref, RX VrefLevel [Byte0]: 52
8753 13:19:29.298689 [Byte1]: 52
8754 13:19:29.303247
8755 13:19:29.303706 Set Vref, RX VrefLevel [Byte0]: 53
8756 13:19:29.306384 [Byte1]: 53
8757 13:19:29.310787
8758 13:19:29.311174 Set Vref, RX VrefLevel [Byte0]: 54
8759 13:19:29.314116 [Byte1]: 54
8760 13:19:29.318398
8761 13:19:29.318786 Set Vref, RX VrefLevel [Byte0]: 55
8762 13:19:29.321469 [Byte1]: 55
8763 13:19:29.326040
8764 13:19:29.326521 Set Vref, RX VrefLevel [Byte0]: 56
8765 13:19:29.329786 [Byte1]: 56
8766 13:19:29.333568
8767 13:19:29.333957 Set Vref, RX VrefLevel [Byte0]: 57
8768 13:19:29.336759 [Byte1]: 57
8769 13:19:29.341173
8770 13:19:29.341558 Set Vref, RX VrefLevel [Byte0]: 58
8771 13:19:29.344462 [Byte1]: 58
8772 13:19:29.348971
8773 13:19:29.349362 Set Vref, RX VrefLevel [Byte0]: 59
8774 13:19:29.351993 [Byte1]: 59
8775 13:19:29.356387
8776 13:19:29.356950 Set Vref, RX VrefLevel [Byte0]: 60
8777 13:19:29.359674 [Byte1]: 60
8778 13:19:29.364019
8779 13:19:29.364394 Set Vref, RX VrefLevel [Byte0]: 61
8780 13:19:29.367251 [Byte1]: 61
8781 13:19:29.371879
8782 13:19:29.372265 Set Vref, RX VrefLevel [Byte0]: 62
8783 13:19:29.374960 [Byte1]: 62
8784 13:19:29.379558
8785 13:19:29.380110 Set Vref, RX VrefLevel [Byte0]: 63
8786 13:19:29.382690 [Byte1]: 63
8787 13:19:29.387219
8788 13:19:29.387705 Set Vref, RX VrefLevel [Byte0]: 64
8789 13:19:29.390347 [Byte1]: 64
8790 13:19:29.394426
8791 13:19:29.394928 Set Vref, RX VrefLevel [Byte0]: 65
8792 13:19:29.397974 [Byte1]: 65
8793 13:19:29.402068
8794 13:19:29.402459 Set Vref, RX VrefLevel [Byte0]: 66
8795 13:19:29.405337 [Byte1]: 66
8796 13:19:29.409786
8797 13:19:29.410206 Set Vref, RX VrefLevel [Byte0]: 67
8798 13:19:29.413012 [Byte1]: 67
8799 13:19:29.417569
8800 13:19:29.417953 Set Vref, RX VrefLevel [Byte0]: 68
8801 13:19:29.420777 [Byte1]: 68
8802 13:19:29.425321
8803 13:19:29.425702 Set Vref, RX VrefLevel [Byte0]: 69
8804 13:19:29.428377 [Byte1]: 69
8805 13:19:29.432821
8806 13:19:29.433205 Set Vref, RX VrefLevel [Byte0]: 70
8807 13:19:29.435838 [Byte1]: 70
8808 13:19:29.440208
8809 13:19:29.440614 Set Vref, RX VrefLevel [Byte0]: 71
8810 13:19:29.443310 [Byte1]: 71
8811 13:19:29.447228
8812 13:19:29.447307 Set Vref, RX VrefLevel [Byte0]: 72
8813 13:19:29.450594 [Byte1]: 72
8814 13:19:29.455193
8815 13:19:29.455271 Final RX Vref Byte 0 = 53 to rank0
8816 13:19:29.458462 Final RX Vref Byte 1 = 59 to rank0
8817 13:19:29.461521 Final RX Vref Byte 0 = 53 to rank1
8818 13:19:29.465156 Final RX Vref Byte 1 = 59 to rank1==
8819 13:19:29.468179 Dram Type= 6, Freq= 0, CH_1, rank 0
8820 13:19:29.475007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 13:19:29.475087 ==
8822 13:19:29.475145 DQS Delay:
8823 13:19:29.478200 DQS0 = 0, DQS1 = 0
8824 13:19:29.478274 DQM Delay:
8825 13:19:29.478332 DQM0 = 133, DQM1 = 128
8826 13:19:29.481407 DQ Delay:
8827 13:19:29.484541 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8828 13:19:29.488389 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =128
8829 13:19:29.491648 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =118
8830 13:19:29.494750 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8831 13:19:29.494825
8832 13:19:29.494883
8833 13:19:29.494935
8834 13:19:29.497857 [DramC_TX_OE_Calibration] TA2
8835 13:19:29.501153 Original DQ_B0 (3 6) =30, OEN = 27
8836 13:19:29.504685 Original DQ_B1 (3 6) =30, OEN = 27
8837 13:19:29.507625 24, 0x0, End_B0=24 End_B1=24
8838 13:19:29.511052 25, 0x0, End_B0=25 End_B1=25
8839 13:19:29.511127 26, 0x0, End_B0=26 End_B1=26
8840 13:19:29.514755 27, 0x0, End_B0=27 End_B1=27
8841 13:19:29.518000 28, 0x0, End_B0=28 End_B1=28
8842 13:19:29.521223 29, 0x0, End_B0=29 End_B1=29
8843 13:19:29.521299 30, 0x0, End_B0=30 End_B1=30
8844 13:19:29.524428 31, 0x4141, End_B0=30 End_B1=30
8845 13:19:29.527701 Byte0 end_step=30 best_step=27
8846 13:19:29.530921 Byte1 end_step=30 best_step=27
8847 13:19:29.534251 Byte0 TX OE(2T, 0.5T) = (3, 3)
8848 13:19:29.537501 Byte1 TX OE(2T, 0.5T) = (3, 3)
8849 13:19:29.537575
8850 13:19:29.537632
8851 13:19:29.544065 [DQSOSCAuto] RK0, (LSB)MR18= 0x180e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8852 13:19:29.547179 CH1 RK0: MR19=303, MR18=180E
8853 13:19:29.554136 CH1_RK0: MR19=0x303, MR18=0x180E, DQSOSC=397, MR23=63, INC=23, DEC=15
8854 13:19:29.554224
8855 13:19:29.557328 ----->DramcWriteLeveling(PI) begin...
8856 13:19:29.557422 ==
8857 13:19:29.560455 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 13:19:29.564230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 13:19:29.564305 ==
8860 13:19:29.567249 Write leveling (Byte 0): 24 => 24
8861 13:19:29.570358 Write leveling (Byte 1): 28 => 28
8862 13:19:29.574058 DramcWriteLeveling(PI) end<-----
8863 13:19:29.574145
8864 13:19:29.574211 ==
8865 13:19:29.577143 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 13:19:29.580627 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 13:19:29.583969 ==
8868 13:19:29.584071 [Gating] SW mode calibration
8869 13:19:29.593612 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8870 13:19:29.596758 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8871 13:19:29.600040 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8872 13:19:29.606980 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8873 13:19:29.610211 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8874 13:19:29.613369 1 4 12 | B1->B0 | 3232 2424 | 0 0 | (0 0) (0 0)
8875 13:19:29.619704 1 4 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8876 13:19:29.623137 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8877 13:19:29.629557 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8878 13:19:29.632804 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8879 13:19:29.636027 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8880 13:19:29.639883 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8881 13:19:29.646138 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
8882 13:19:29.649287 1 5 12 | B1->B0 | 2929 3434 | 1 1 | (1 0) (1 0)
8883 13:19:29.652505 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8884 13:19:29.659497 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8885 13:19:29.662659 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8886 13:19:29.665934 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8887 13:19:29.672730 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8888 13:19:29.675815 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8889 13:19:29.679631 1 6 8 | B1->B0 | 2827 2323 | 1 0 | (0 0) (0 0)
8890 13:19:29.686111 1 6 12 | B1->B0 | 4444 2525 | 0 0 | (0 0) (0 0)
8891 13:19:29.689408 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8892 13:19:29.693076 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8893 13:19:29.699387 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8894 13:19:29.702860 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8895 13:19:29.706167 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8896 13:19:29.712417 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8897 13:19:29.715682 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8898 13:19:29.719485 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8899 13:19:29.725724 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8900 13:19:29.729534 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8901 13:19:29.732406 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8902 13:19:29.738899 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8903 13:19:29.742604 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8904 13:19:29.745844 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8905 13:19:29.752086 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8906 13:19:29.755932 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8907 13:19:29.759176 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8908 13:19:29.765419 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8909 13:19:29.768614 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8910 13:19:29.771892 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8911 13:19:29.778687 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8912 13:19:29.782346 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8913 13:19:29.785600 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8914 13:19:29.791922 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8915 13:19:29.794962 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8916 13:19:29.798847 Total UI for P1: 0, mck2ui 16
8917 13:19:29.802080 best dqsien dly found for B1: ( 1, 9, 10)
8918 13:19:29.805380 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8919 13:19:29.808301 Total UI for P1: 0, mck2ui 16
8920 13:19:29.811507 best dqsien dly found for B0: ( 1, 9, 12)
8921 13:19:29.814823 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8922 13:19:29.817931 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8923 13:19:29.821323
8924 13:19:29.824751 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8925 13:19:29.827771 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8926 13:19:29.831532 [Gating] SW calibration Done
8927 13:19:29.831921 ==
8928 13:19:29.834702 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 13:19:29.837812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 13:19:29.838205 ==
8931 13:19:29.841528 RX Vref Scan: 0
8932 13:19:29.841993
8933 13:19:29.842359 RX Vref 0 -> 0, step: 1
8934 13:19:29.842646
8935 13:19:29.844635 RX Delay 0 -> 252, step: 8
8936 13:19:29.848066 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8937 13:19:29.851157 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8938 13:19:29.857547 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8939 13:19:29.860795 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8940 13:19:29.864554 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8941 13:19:29.867646 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8942 13:19:29.870626 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8943 13:19:29.877615 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8944 13:19:29.880760 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8945 13:19:29.884322 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8946 13:19:29.887388 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8947 13:19:29.893784 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8948 13:19:29.896961 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8949 13:19:29.900733 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8950 13:19:29.904035 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8951 13:19:29.907211 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8952 13:19:29.910423 ==
8953 13:19:29.913652 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 13:19:29.916874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 13:19:29.917264 ==
8956 13:19:29.917562 DQS Delay:
8957 13:19:29.920126 DQS0 = 0, DQS1 = 0
8958 13:19:29.920511 DQM Delay:
8959 13:19:29.922974 DQM0 = 136, DQM1 = 129
8960 13:19:29.923048 DQ Delay:
8961 13:19:29.926935 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =131
8962 13:19:29.930095 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8963 13:19:29.933083 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8964 13:19:29.936620 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8965 13:19:29.936707
8966 13:19:29.936773
8967 13:19:29.939992 ==
8968 13:19:29.940085 Dram Type= 6, Freq= 0, CH_1, rank 1
8969 13:19:29.946494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8970 13:19:29.946596 ==
8971 13:19:29.946673
8972 13:19:29.946744
8973 13:19:29.949435 TX Vref Scan disable
8974 13:19:29.949562 == TX Byte 0 ==
8975 13:19:29.953069 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8976 13:19:29.959796 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8977 13:19:29.959935 == TX Byte 1 ==
8978 13:19:29.962838 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8979 13:19:29.969958 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8980 13:19:29.970143 ==
8981 13:19:29.973123 Dram Type= 6, Freq= 0, CH_1, rank 1
8982 13:19:29.976065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8983 13:19:29.976287 ==
8984 13:19:29.989418
8985 13:19:29.992965 TX Vref early break, caculate TX vref
8986 13:19:29.996066 TX Vref=16, minBit 1, minWin=22, winSum=378
8987 13:19:29.999801 TX Vref=18, minBit 8, minWin=23, winSum=395
8988 13:19:30.003016 TX Vref=20, minBit 1, minWin=24, winSum=399
8989 13:19:30.006126 TX Vref=22, minBit 0, minWin=25, winSum=410
8990 13:19:30.009358 TX Vref=24, minBit 0, minWin=25, winSum=415
8991 13:19:30.015722 TX Vref=26, minBit 1, minWin=25, winSum=421
8992 13:19:30.019529 TX Vref=28, minBit 0, minWin=25, winSum=421
8993 13:19:30.022744 TX Vref=30, minBit 0, minWin=24, winSum=418
8994 13:19:30.026000 TX Vref=32, minBit 0, minWin=24, winSum=409
8995 13:19:30.029291 TX Vref=34, minBit 0, minWin=24, winSum=398
8996 13:19:30.035677 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 26
8997 13:19:30.036066
8998 13:19:30.038840 Final TX Range 0 Vref 26
8999 13:19:30.039223
9000 13:19:30.039539 ==
9001 13:19:30.042149 Dram Type= 6, Freq= 0, CH_1, rank 1
9002 13:19:30.045941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9003 13:19:30.046373 ==
9004 13:19:30.046677
9005 13:19:30.046955
9006 13:19:30.049025 TX Vref Scan disable
9007 13:19:30.055514 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
9008 13:19:30.055915 == TX Byte 0 ==
9009 13:19:30.058817 u2DelayCellOfst[0]=18 cells (5 PI)
9010 13:19:30.062126 u2DelayCellOfst[1]=14 cells (4 PI)
9011 13:19:30.065773 u2DelayCellOfst[2]=0 cells (0 PI)
9012 13:19:30.068657 u2DelayCellOfst[3]=7 cells (2 PI)
9013 13:19:30.072392 u2DelayCellOfst[4]=7 cells (2 PI)
9014 13:19:30.076032 u2DelayCellOfst[5]=22 cells (6 PI)
9015 13:19:30.078793 u2DelayCellOfst[6]=18 cells (5 PI)
9016 13:19:30.082172 u2DelayCellOfst[7]=3 cells (1 PI)
9017 13:19:30.085686 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9018 13:19:30.088734 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9019 13:19:30.091894 == TX Byte 1 ==
9020 13:19:30.092271 u2DelayCellOfst[8]=0 cells (0 PI)
9021 13:19:30.095601 u2DelayCellOfst[9]=7 cells (2 PI)
9022 13:19:30.098617 u2DelayCellOfst[10]=14 cells (4 PI)
9023 13:19:30.101814 u2DelayCellOfst[11]=7 cells (2 PI)
9024 13:19:30.105681 u2DelayCellOfst[12]=14 cells (4 PI)
9025 13:19:30.108683 u2DelayCellOfst[13]=18 cells (5 PI)
9026 13:19:30.111833 u2DelayCellOfst[14]=18 cells (5 PI)
9027 13:19:30.115004 u2DelayCellOfst[15]=18 cells (5 PI)
9028 13:19:30.118802 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9029 13:19:30.125244 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9030 13:19:30.125631 DramC Write-DBI on
9031 13:19:30.125926 ==
9032 13:19:30.128489 Dram Type= 6, Freq= 0, CH_1, rank 1
9033 13:19:30.134880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9034 13:19:30.135266 ==
9035 13:19:30.135615
9036 13:19:30.135896
9037 13:19:30.136161 TX Vref Scan disable
9038 13:19:30.138674 == TX Byte 0 ==
9039 13:19:30.142427 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9040 13:19:30.145509 == TX Byte 1 ==
9041 13:19:30.148712 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9042 13:19:30.151998 DramC Write-DBI off
9043 13:19:30.152374
9044 13:19:30.152660 [DATLAT]
9045 13:19:30.152933 Freq=1600, CH1 RK1
9046 13:19:30.153197
9047 13:19:30.155073 DATLAT Default: 0xf
9048 13:19:30.158938 0, 0xFFFF, sum = 0
9049 13:19:30.159331 1, 0xFFFF, sum = 0
9050 13:19:30.162088 2, 0xFFFF, sum = 0
9051 13:19:30.162471 3, 0xFFFF, sum = 0
9052 13:19:30.165088 4, 0xFFFF, sum = 0
9053 13:19:30.165470 5, 0xFFFF, sum = 0
9054 13:19:30.168685 6, 0xFFFF, sum = 0
9055 13:19:30.169082 7, 0xFFFF, sum = 0
9056 13:19:30.171460 8, 0xFFFF, sum = 0
9057 13:19:30.171848 9, 0xFFFF, sum = 0
9058 13:19:30.174723 10, 0xFFFF, sum = 0
9059 13:19:30.175107 11, 0xFFFF, sum = 0
9060 13:19:30.177988 12, 0xFFFF, sum = 0
9061 13:19:30.178372 13, 0xFFFF, sum = 0
9062 13:19:30.181362 14, 0x0, sum = 1
9063 13:19:30.181637 15, 0x0, sum = 2
9064 13:19:30.184621 16, 0x0, sum = 3
9065 13:19:30.184841 17, 0x0, sum = 4
9066 13:19:30.188053 best_step = 15
9067 13:19:30.188257
9068 13:19:30.188467 ==
9069 13:19:30.191473 Dram Type= 6, Freq= 0, CH_1, rank 1
9070 13:19:30.194431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9071 13:19:30.194586 ==
9072 13:19:30.197871 RX Vref Scan: 0
9073 13:19:30.198008
9074 13:19:30.198142 RX Vref 0 -> 0, step: 1
9075 13:19:30.198247
9076 13:19:30.201065 RX Delay 11 -> 252, step: 4
9077 13:19:30.207961 iDelay=199, Bit 0, Center 138 (87 ~ 190) 104
9078 13:19:30.210877 iDelay=199, Bit 1, Center 128 (75 ~ 182) 108
9079 13:19:30.214115 iDelay=199, Bit 2, Center 122 (67 ~ 178) 112
9080 13:19:30.217703 iDelay=199, Bit 3, Center 130 (79 ~ 182) 104
9081 13:19:30.220888 iDelay=199, Bit 4, Center 132 (75 ~ 190) 116
9082 13:19:30.227333 iDelay=199, Bit 5, Center 144 (91 ~ 198) 108
9083 13:19:30.230630 iDelay=199, Bit 6, Center 144 (91 ~ 198) 108
9084 13:19:30.233900 iDelay=199, Bit 7, Center 130 (79 ~ 182) 104
9085 13:19:30.237549 iDelay=199, Bit 8, Center 112 (55 ~ 170) 116
9086 13:19:30.240761 iDelay=199, Bit 9, Center 116 (63 ~ 170) 108
9087 13:19:30.247107 iDelay=199, Bit 10, Center 126 (71 ~ 182) 112
9088 13:19:30.250292 iDelay=199, Bit 11, Center 116 (63 ~ 170) 108
9089 13:19:30.253537 iDelay=199, Bit 12, Center 134 (79 ~ 190) 112
9090 13:19:30.256818 iDelay=199, Bit 13, Center 134 (79 ~ 190) 112
9091 13:19:30.263875 iDelay=199, Bit 14, Center 134 (79 ~ 190) 112
9092 13:19:30.267104 iDelay=199, Bit 15, Center 138 (83 ~ 194) 112
9093 13:19:30.267189 ==
9094 13:19:30.270193 Dram Type= 6, Freq= 0, CH_1, rank 1
9095 13:19:30.273345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9096 13:19:30.273423 ==
9097 13:19:30.276436 DQS Delay:
9098 13:19:30.276521 DQS0 = 0, DQS1 = 0
9099 13:19:30.276624 DQM Delay:
9100 13:19:30.279583 DQM0 = 133, DQM1 = 126
9101 13:19:30.279689 DQ Delay:
9102 13:19:30.283093 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9103 13:19:30.289455 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
9104 13:19:30.293065 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9105 13:19:30.296029 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =138
9106 13:19:30.296103
9107 13:19:30.296160
9108 13:19:30.296213
9109 13:19:30.299685 [DramC_TX_OE_Calibration] TA2
9110 13:19:30.302905 Original DQ_B0 (3 6) =30, OEN = 27
9111 13:19:30.305968 Original DQ_B1 (3 6) =30, OEN = 27
9112 13:19:30.306043 24, 0x0, End_B0=24 End_B1=24
9113 13:19:30.309149 25, 0x0, End_B0=25 End_B1=25
9114 13:19:30.312758 26, 0x0, End_B0=26 End_B1=26
9115 13:19:30.315630 27, 0x0, End_B0=27 End_B1=27
9116 13:19:30.319035 28, 0x0, End_B0=28 End_B1=28
9117 13:19:30.319110 29, 0x0, End_B0=29 End_B1=29
9118 13:19:30.322827 30, 0x0, End_B0=30 End_B1=30
9119 13:19:30.325484 31, 0x4141, End_B0=30 End_B1=30
9120 13:19:30.328764 Byte0 end_step=30 best_step=27
9121 13:19:30.332488 Byte1 end_step=30 best_step=27
9122 13:19:30.335646 Byte0 TX OE(2T, 0.5T) = (3, 3)
9123 13:19:30.335804 Byte1 TX OE(2T, 0.5T) = (3, 3)
9124 13:19:30.335894
9125 13:19:30.338704
9126 13:19:30.345902 [DQSOSCAuto] RK1, (LSB)MR18= 0xa08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 404 ps
9127 13:19:30.348914 CH1 RK1: MR19=303, MR18=A08
9128 13:19:30.355476 CH1_RK1: MR19=0x303, MR18=0xA08, DQSOSC=404, MR23=63, INC=22, DEC=15
9129 13:19:30.355622 [RxdqsGatingPostProcess] freq 1600
9130 13:19:30.362052 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9131 13:19:30.365353 best DQS0 dly(2T, 0.5T) = (1, 1)
9132 13:19:30.368672 best DQS1 dly(2T, 0.5T) = (1, 1)
9133 13:19:30.371886 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9134 13:19:30.375126 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9135 13:19:30.378773 best DQS0 dly(2T, 0.5T) = (1, 1)
9136 13:19:30.381993 best DQS1 dly(2T, 0.5T) = (1, 1)
9137 13:19:30.385226 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9138 13:19:30.388421 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9139 13:19:30.391556 Pre-setting of DQS Precalculation
9140 13:19:30.395200 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9141 13:19:30.401569 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9142 13:19:30.408562 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9143 13:19:30.412237
9144 13:19:30.412759
9145 13:19:30.413245 [Calibration Summary] 3200 Mbps
9146 13:19:30.414817 CH 0, Rank 0
9147 13:19:30.415311 SW Impedance : PASS
9148 13:19:30.417931 DUTY Scan : NO K
9149 13:19:30.421775 ZQ Calibration : PASS
9150 13:19:30.422254 Jitter Meter : NO K
9151 13:19:30.424983 CBT Training : PASS
9152 13:19:30.428073 Write leveling : PASS
9153 13:19:30.428555 RX DQS gating : PASS
9154 13:19:30.431670 RX DQ/DQS(RDDQC) : PASS
9155 13:19:30.434724 TX DQ/DQS : PASS
9156 13:19:30.435281 RX DATLAT : PASS
9157 13:19:30.438265 RX DQ/DQS(Engine): PASS
9158 13:19:30.441540 TX OE : PASS
9159 13:19:30.441892 All Pass.
9160 13:19:30.442196
9161 13:19:30.442489 CH 0, Rank 1
9162 13:19:30.444379 SW Impedance : PASS
9163 13:19:30.447681 DUTY Scan : NO K
9164 13:19:30.447948 ZQ Calibration : PASS
9165 13:19:30.450737 Jitter Meter : NO K
9166 13:19:30.454591 CBT Training : PASS
9167 13:19:30.454761 Write leveling : PASS
9168 13:19:30.457789 RX DQS gating : PASS
9169 13:19:30.460880 RX DQ/DQS(RDDQC) : PASS
9170 13:19:30.461006 TX DQ/DQS : PASS
9171 13:19:30.464005 RX DATLAT : PASS
9172 13:19:30.467223 RX DQ/DQS(Engine): PASS
9173 13:19:30.467331 TX OE : PASS
9174 13:19:30.467414 All Pass.
9175 13:19:30.470415
9176 13:19:30.470511 CH 1, Rank 0
9177 13:19:30.474271 SW Impedance : PASS
9178 13:19:30.474391 DUTY Scan : NO K
9179 13:19:30.477504 ZQ Calibration : PASS
9180 13:19:30.477589 Jitter Meter : NO K
9181 13:19:30.480589 CBT Training : PASS
9182 13:19:30.483659 Write leveling : PASS
9183 13:19:30.483748 RX DQS gating : PASS
9184 13:19:30.487061 RX DQ/DQS(RDDQC) : PASS
9185 13:19:30.490170 TX DQ/DQS : PASS
9186 13:19:30.490288 RX DATLAT : PASS
9187 13:19:30.494100 RX DQ/DQS(Engine): PASS
9188 13:19:30.497331 TX OE : PASS
9189 13:19:30.497449 All Pass.
9190 13:19:30.497537
9191 13:19:30.497623 CH 1, Rank 1
9192 13:19:30.500432 SW Impedance : PASS
9193 13:19:30.503654 DUTY Scan : NO K
9194 13:19:30.503755 ZQ Calibration : PASS
9195 13:19:30.507217 Jitter Meter : NO K
9196 13:19:30.510424 CBT Training : PASS
9197 13:19:30.510523 Write leveling : PASS
9198 13:19:30.513767 RX DQS gating : PASS
9199 13:19:30.516949 RX DQ/DQS(RDDQC) : PASS
9200 13:19:30.517023 TX DQ/DQS : PASS
9201 13:19:30.520436 RX DATLAT : PASS
9202 13:19:30.523852 RX DQ/DQS(Engine): PASS
9203 13:19:30.523926 TX OE : PASS
9204 13:19:30.523983 All Pass.
9205 13:19:30.527160
9206 13:19:30.527257 DramC Write-DBI on
9207 13:19:30.530506 PER_BANK_REFRESH: Hybrid Mode
9208 13:19:30.530581 TX_TRACKING: ON
9209 13:19:30.539980 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9210 13:19:30.549665 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9211 13:19:30.556742 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9212 13:19:30.560120 [FAST_K] Save calibration result to emmc
9213 13:19:30.563169 sync common calibartion params.
9214 13:19:30.563328 sync cbt_mode0:1, 1:1
9215 13:19:30.566364 dram_init: ddr_geometry: 2
9216 13:19:30.569553 dram_init: ddr_geometry: 2
9217 13:19:30.569757 dram_init: ddr_geometry: 2
9218 13:19:30.572789 0:dram_rank_size:100000000
9219 13:19:30.576605 1:dram_rank_size:100000000
9220 13:19:30.583164 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9221 13:19:30.583443 DFS_SHUFFLE_HW_MODE: ON
9222 13:19:30.586636 dramc_set_vcore_voltage set vcore to 725000
9223 13:19:30.589710 Read voltage for 1600, 0
9224 13:19:30.590098 Vio18 = 0
9225 13:19:30.592957 Vcore = 725000
9226 13:19:30.593383 Vdram = 0
9227 13:19:30.593771 Vddq = 0
9228 13:19:30.596174 Vmddr = 0
9229 13:19:30.596808 switch to 3200 Mbps bootup
9230 13:19:30.599390 [DramcRunTimeConfig]
9231 13:19:30.599964 PHYPLL
9232 13:19:30.602716 DPM_CONTROL_AFTERK: ON
9233 13:19:30.603259 PER_BANK_REFRESH: ON
9234 13:19:30.605900 REFRESH_OVERHEAD_REDUCTION: ON
9235 13:19:30.609808 CMD_PICG_NEW_MODE: OFF
9236 13:19:30.610188 XRTWTW_NEW_MODE: ON
9237 13:19:30.612765 XRTRTR_NEW_MODE: ON
9238 13:19:30.613142 TX_TRACKING: ON
9239 13:19:30.616457 RDSEL_TRACKING: OFF
9240 13:19:30.619746 DQS Precalculation for DVFS: ON
9241 13:19:30.620135 RX_TRACKING: OFF
9242 13:19:30.622894 HW_GATING DBG: ON
9243 13:19:30.623280 ZQCS_ENABLE_LP4: ON
9244 13:19:30.626300 RX_PICG_NEW_MODE: ON
9245 13:19:30.626688 TX_PICG_NEW_MODE: ON
9246 13:19:30.629319 ENABLE_RX_DCM_DPHY: ON
9247 13:19:30.632503 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9248 13:19:30.636085 DUMMY_READ_FOR_TRACKING: OFF
9249 13:19:30.638922 !!! SPM_CONTROL_AFTERK: OFF
9250 13:19:30.639323 !!! SPM could not control APHY
9251 13:19:30.642449 IMPEDANCE_TRACKING: ON
9252 13:19:30.645408 TEMP_SENSOR: ON
9253 13:19:30.645975 HW_SAVE_FOR_SR: OFF
9254 13:19:30.648648 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9255 13:19:30.652016 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9256 13:19:30.655644 Read ODT Tracking: ON
9257 13:19:30.656188 Refresh Rate DeBounce: ON
9258 13:19:30.658638 DFS_NO_QUEUE_FLUSH: ON
9259 13:19:30.661660 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9260 13:19:30.665164 ENABLE_DFS_RUNTIME_MRW: OFF
9261 13:19:30.665705 DDR_RESERVE_NEW_MODE: ON
9262 13:19:30.668778 MR_CBT_SWITCH_FREQ: ON
9263 13:19:30.671720 =========================
9264 13:19:30.690454 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9265 13:19:30.693577 dram_init: ddr_geometry: 2
9266 13:19:30.711402 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9267 13:19:30.714690 dram_init: dram init end (result: 0)
9268 13:19:30.721282 DRAM-K: Full calibration passed in 24637 msecs
9269 13:19:30.725029 MRC: failed to locate region type 0.
9270 13:19:30.725475 DRAM rank0 size:0x100000000,
9271 13:19:30.728214 DRAM rank1 size=0x100000000
9272 13:19:30.737661 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9273 13:19:30.744358 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9274 13:19:30.750828 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9275 13:19:30.760422 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9276 13:19:30.760616 DRAM rank0 size:0x100000000,
9277 13:19:30.764202 DRAM rank1 size=0x100000000
9278 13:19:30.764362 CBMEM:
9279 13:19:30.767380 IMD: root @ 0xfffff000 254 entries.
9280 13:19:30.770518 IMD: root @ 0xffffec00 62 entries.
9281 13:19:30.773998 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9282 13:19:30.780665 WARNING: RO_VPD is uninitialized or empty.
9283 13:19:30.783439 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9284 13:19:30.791181 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9285 13:19:30.804164 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9286 13:19:30.815646 BS: romstage times (exec / console): total (unknown) / 24126 ms
9287 13:19:30.815749
9288 13:19:30.815833
9289 13:19:30.825319 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9290 13:19:30.828728 ARM64: Exception handlers installed.
9291 13:19:30.832475 ARM64: Testing exception
9292 13:19:30.835778 ARM64: Done test exception
9293 13:19:30.835858 Enumerating buses...
9294 13:19:30.838954 Show all devs... Before device enumeration.
9295 13:19:30.842115 Root Device: enabled 1
9296 13:19:30.845360 CPU_CLUSTER: 0: enabled 1
9297 13:19:30.845457 CPU: 00: enabled 1
9298 13:19:30.849158 Compare with tree...
9299 13:19:30.849256 Root Device: enabled 1
9300 13:19:30.851740 CPU_CLUSTER: 0: enabled 1
9301 13:19:30.855006 CPU: 00: enabled 1
9302 13:19:30.855121 Root Device scanning...
9303 13:19:30.858961 scan_static_bus for Root Device
9304 13:19:30.862238 CPU_CLUSTER: 0 enabled
9305 13:19:30.864946 scan_static_bus for Root Device done
9306 13:19:30.868769 scan_bus: bus Root Device finished in 8 msecs
9307 13:19:30.868915 done
9308 13:19:30.874844 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9309 13:19:30.878548 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9310 13:19:30.884975 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9311 13:19:30.888411 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9312 13:19:30.891790 Allocating resources...
9313 13:19:30.894545 Reading resources...
9314 13:19:30.898080 Root Device read_resources bus 0 link: 0
9315 13:19:30.901551 DRAM rank0 size:0x100000000,
9316 13:19:30.901678 DRAM rank1 size=0x100000000
9317 13:19:30.907995 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9318 13:19:30.908127 CPU: 00 missing read_resources
9319 13:19:30.914489 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9320 13:19:30.917703 Root Device read_resources bus 0 link: 0 done
9321 13:19:30.920911 Done reading resources.
9322 13:19:30.924212 Show resources in subtree (Root Device)...After reading.
9323 13:19:30.927475 Root Device child on link 0 CPU_CLUSTER: 0
9324 13:19:30.930639 CPU_CLUSTER: 0 child on link 0 CPU: 00
9325 13:19:30.940933 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9326 13:19:30.941013 CPU: 00
9327 13:19:30.947242 Root Device assign_resources, bus 0 link: 0
9328 13:19:30.951032 CPU_CLUSTER: 0 missing set_resources
9329 13:19:30.954134 Root Device assign_resources, bus 0 link: 0 done
9330 13:19:30.954212 Done setting resources.
9331 13:19:30.960534 Show resources in subtree (Root Device)...After assigning values.
9332 13:19:30.963665 Root Device child on link 0 CPU_CLUSTER: 0
9333 13:19:30.970143 CPU_CLUSTER: 0 child on link 0 CPU: 00
9334 13:19:30.976784 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9335 13:19:30.976902 CPU: 00
9336 13:19:30.980527 Done allocating resources.
9337 13:19:30.987213 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9338 13:19:30.987359 Enabling resources...
9339 13:19:30.989970 done.
9340 13:19:30.993705 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9341 13:19:30.996920 Initializing devices...
9342 13:19:30.997122 Root Device init
9343 13:19:31.000485 init hardware done!
9344 13:19:31.000706 0x00000018: ctrlr->caps
9345 13:19:31.003414 52.000 MHz: ctrlr->f_max
9346 13:19:31.006980 0.400 MHz: ctrlr->f_min
9347 13:19:31.010161 0x40ff8080: ctrlr->voltages
9348 13:19:31.010451 sclk: 390625
9349 13:19:31.010731 Bus Width = 1
9350 13:19:31.013219 sclk: 390625
9351 13:19:31.013492 Bus Width = 1
9352 13:19:31.016717 Early init status = 3
9353 13:19:31.020327 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9354 13:19:31.024067 in-header: 03 fc 00 00 01 00 00 00
9355 13:19:31.027905 in-data: 00
9356 13:19:31.031225 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9357 13:19:31.036430 in-header: 03 fd 00 00 00 00 00 00
9358 13:19:31.040310 in-data:
9359 13:19:31.043405 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9360 13:19:31.047550 in-header: 03 fc 00 00 01 00 00 00
9361 13:19:31.051154 in-data: 00
9362 13:19:31.054338 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9363 13:19:31.060261 in-header: 03 fd 00 00 00 00 00 00
9364 13:19:31.063512 in-data:
9365 13:19:31.066757 [SSUSB] Setting up USB HOST controller...
9366 13:19:31.069888 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9367 13:19:31.073174 [SSUSB] phy power-on done.
9368 13:19:31.076353 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9369 13:19:31.083109 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9370 13:19:31.086304 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9371 13:19:31.093145 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9372 13:19:31.099776 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9373 13:19:31.105786 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9374 13:19:31.112214 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9375 13:19:31.118783 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9376 13:19:31.122241 SPM: binary array size = 0x9dc
9377 13:19:31.125306 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9378 13:19:31.132067 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9379 13:19:31.138466 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9380 13:19:31.145405 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9381 13:19:31.148632 configure_display: Starting display init
9382 13:19:31.183303 anx7625_power_on_init: Init interface.
9383 13:19:31.186304 anx7625_disable_pd_protocol: Disabled PD feature.
9384 13:19:31.190030 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9385 13:19:31.217739 anx7625_start_dp_work: Secure OCM version=00
9386 13:19:31.220971 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9387 13:19:31.235874 sp_tx_get_edid_block: EDID Block = 1
9388 13:19:31.338012 Extracted contents:
9389 13:19:31.341575 header: 00 ff ff ff ff ff ff 00
9390 13:19:31.344990 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9391 13:19:31.348238 version: 01 04
9392 13:19:31.351365 basic params: 95 1f 11 78 0a
9393 13:19:31.354498 chroma info: 76 90 94 55 54 90 27 21 50 54
9394 13:19:31.358261 established: 00 00 00
9395 13:19:31.364717 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9396 13:19:31.367693 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9397 13:19:31.374621 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9398 13:19:31.381178 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9399 13:19:31.387490 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9400 13:19:31.390734 extensions: 00
9401 13:19:31.391135 checksum: fb
9402 13:19:31.391471
9403 13:19:31.394528 Manufacturer: IVO Model 57d Serial Number 0
9404 13:19:31.397798 Made week 0 of 2020
9405 13:19:31.400985 EDID version: 1.4
9406 13:19:31.401388 Digital display
9407 13:19:31.404053 6 bits per primary color channel
9408 13:19:31.404445 DisplayPort interface
9409 13:19:31.407773 Maximum image size: 31 cm x 17 cm
9410 13:19:31.410693 Gamma: 220%
9411 13:19:31.411095 Check DPMS levels
9412 13:19:31.417113 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9413 13:19:31.420338 First detailed timing is preferred timing
9414 13:19:31.420889 Established timings supported:
9415 13:19:31.423952 Standard timings supported:
9416 13:19:31.427474 Detailed timings
9417 13:19:31.430236 Hex of detail: 383680a07038204018303c0035ae10000019
9418 13:19:31.437211 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9419 13:19:31.440346 0780 0798 07c8 0820 hborder 0
9420 13:19:31.443485 0438 043b 0447 0458 vborder 0
9421 13:19:31.447240 -hsync -vsync
9422 13:19:31.447646 Did detailed timing
9423 13:19:31.453760 Hex of detail: 000000000000000000000000000000000000
9424 13:19:31.456723 Manufacturer-specified data, tag 0
9425 13:19:31.459787 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9426 13:19:31.463665 ASCII string: InfoVision
9427 13:19:31.466820 Hex of detail: 000000fe00523134304e574635205248200a
9428 13:19:31.469945 ASCII string: R140NWF5 RH
9429 13:19:31.470428 Checksum
9430 13:19:31.473023 Checksum: 0xfb (valid)
9431 13:19:31.476279 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9432 13:19:31.480147 DSI data_rate: 832800000 bps
9433 13:19:31.486761 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9434 13:19:31.489852 anx7625_parse_edid: pixelclock(138800).
9435 13:19:31.493050 hactive(1920), hsync(48), hfp(24), hbp(88)
9436 13:19:31.496300 vactive(1080), vsync(12), vfp(3), vbp(17)
9437 13:19:31.499919 anx7625_dsi_config: config dsi.
9438 13:19:31.506275 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9439 13:19:31.520166 anx7625_dsi_config: success to config DSI
9440 13:19:31.523385 anx7625_dp_start: MIPI phy setup OK.
9441 13:19:31.526677 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9442 13:19:31.529785 mtk_ddp_mode_set invalid vrefresh 60
9443 13:19:31.532891 main_disp_path_setup
9444 13:19:31.533297 ovl_layer_smi_id_en
9445 13:19:31.536487 ovl_layer_smi_id_en
9446 13:19:31.536880 ccorr_config
9447 13:19:31.539864 aal_config
9448 13:19:31.540246 gamma_config
9449 13:19:31.540541 postmask_config
9450 13:19:31.542958 dither_config
9451 13:19:31.546064 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9452 13:19:31.553037 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9453 13:19:31.556225 Root Device init finished in 555 msecs
9454 13:19:31.559171 CPU_CLUSTER: 0 init
9455 13:19:31.566266 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9456 13:19:31.572719 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9457 13:19:31.573109 APU_MBOX 0x190000b0 = 0x10001
9458 13:19:31.575798 APU_MBOX 0x190001b0 = 0x10001
9459 13:19:31.579012 APU_MBOX 0x190005b0 = 0x10001
9460 13:19:31.582162 APU_MBOX 0x190006b0 = 0x10001
9461 13:19:31.588660 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9462 13:19:31.599407 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9463 13:19:31.611306 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9464 13:19:31.617914 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9465 13:19:31.630098 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9466 13:19:31.639084 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9467 13:19:31.642185 CPU_CLUSTER: 0 init finished in 81 msecs
9468 13:19:31.645682 Devices initialized
9469 13:19:31.649190 Show all devs... After init.
9470 13:19:31.649583 Root Device: enabled 1
9471 13:19:31.652376 CPU_CLUSTER: 0: enabled 1
9472 13:19:31.655298 CPU: 00: enabled 1
9473 13:19:31.658789 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9474 13:19:31.662010 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9475 13:19:31.665471 ELOG: NV offset 0x57f000 size 0x1000
9476 13:19:31.671962 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9477 13:19:31.678291 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9478 13:19:31.681963 ELOG: Event(17) added with size 13 at 2024-07-18 13:19:31 UTC
9479 13:19:31.688335 out: cmd=0x121: 03 db 21 01 00 00 00 00
9480 13:19:31.691565 in-header: 03 22 00 00 2c 00 00 00
9481 13:19:31.701707 in-data: 1a 73 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9482 13:19:31.708465 ELOG: Event(A1) added with size 10 at 2024-07-18 13:19:31 UTC
9483 13:19:31.714815 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9484 13:19:31.721699 ELOG: Event(A0) added with size 9 at 2024-07-18 13:19:31 UTC
9485 13:19:31.724786 elog_add_boot_reason: Logged dev mode boot
9486 13:19:31.731348 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9487 13:19:31.731922 Finalize devices...
9488 13:19:31.734593 Devices finalized
9489 13:19:31.737864 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9490 13:19:31.741708 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9491 13:19:31.744461 in-header: 03 07 00 00 08 00 00 00
9492 13:19:31.748364 in-data: aa e4 47 04 13 02 00 00
9493 13:19:31.751497 Chrome EC: UHEPI supported
9494 13:19:31.757742 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9495 13:19:31.761420 in-header: 03 a9 00 00 08 00 00 00
9496 13:19:31.764295 in-data: 84 60 60 08 00 00 00 00
9497 13:19:31.771190 ELOG: Event(91) added with size 10 at 2024-07-18 13:19:31 UTC
9498 13:19:31.774656 Chrome EC: clear events_b mask to 0x0000000020004000
9499 13:19:31.781029 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9500 13:19:31.784796 in-header: 03 fd 00 00 00 00 00 00
9501 13:19:31.785186 in-data:
9502 13:19:31.791769 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9503 13:19:31.794893 Writing coreboot table at 0xffe64000
9504 13:19:31.798067 0. 000000000010a000-0000000000113fff: RAMSTAGE
9505 13:19:31.801278 1. 0000000040000000-00000000400fffff: RAM
9506 13:19:31.807972 2. 0000000040100000-000000004032afff: RAMSTAGE
9507 13:19:31.811204 3. 000000004032b000-00000000545fffff: RAM
9508 13:19:31.814358 4. 0000000054600000-000000005465ffff: BL31
9509 13:19:31.817463 5. 0000000054660000-00000000ffe63fff: RAM
9510 13:19:31.824330 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9511 13:19:31.827514 7. 0000000100000000-000000023fffffff: RAM
9512 13:19:31.831200 Passing 5 GPIOs to payload:
9513 13:19:31.834377 NAME | PORT | POLARITY | VALUE
9514 13:19:31.837616 EC in RW | 0x000000aa | low | undefined
9515 13:19:31.844018 EC interrupt | 0x00000005 | low | undefined
9516 13:19:31.847409 TPM interrupt | 0x000000ab | high | undefined
9517 13:19:31.854468 SD card detect | 0x00000011 | high | undefined
9518 13:19:31.857483 speaker enable | 0x00000093 | high | undefined
9519 13:19:31.860671 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9520 13:19:31.863887 in-header: 03 f9 00 00 02 00 00 00
9521 13:19:31.866972 in-data: 02 00
9522 13:19:31.870730 ADC[4]: Raw value=900443 ID=7
9523 13:19:31.871238 ADC[3]: Raw value=214021 ID=1
9524 13:19:31.873720 RAM Code: 0x71
9525 13:19:31.877385 ADC[6]: Raw value=75036 ID=0
9526 13:19:31.877833 ADC[5]: Raw value=212912 ID=1
9527 13:19:31.880322 SKU Code: 0x1
9528 13:19:31.883954 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 8c58
9529 13:19:31.886950 coreboot table: 964 bytes.
9530 13:19:31.890323 IMD ROOT 0. 0xfffff000 0x00001000
9531 13:19:31.893768 IMD SMALL 1. 0xffffe000 0x00001000
9532 13:19:31.897185 RO MCACHE 2. 0xffffc000 0x00001104
9533 13:19:31.900311 CONSOLE 3. 0xfff7c000 0x00080000
9534 13:19:31.903487 FMAP 4. 0xfff7b000 0x00000452
9535 13:19:31.906733 TIME STAMP 5. 0xfff7a000 0x00000910
9536 13:19:31.910617 VBOOT WORK 6. 0xfff66000 0x00014000
9537 13:19:31.913606 RAMOOPS 7. 0xffe66000 0x00100000
9538 13:19:31.916780 COREBOOT 8. 0xffe64000 0x00002000
9539 13:19:31.920455 IMD small region:
9540 13:19:31.923513 IMD ROOT 0. 0xffffec00 0x00000400
9541 13:19:31.926580 VPD 1. 0xffffeb80 0x0000006c
9542 13:19:31.930220 MMC STATUS 2. 0xffffeb60 0x00000004
9543 13:19:31.933397 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9544 13:19:31.939931 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9545 13:19:31.980701 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9546 13:19:31.984300 Checking segment from ROM address 0x40100000
9547 13:19:31.987873 Checking segment from ROM address 0x4010001c
9548 13:19:31.993994 Loading segment from ROM address 0x40100000
9549 13:19:31.994454 code (compression=0)
9550 13:19:32.003881 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9551 13:19:32.010827 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9552 13:19:32.011350 it's not compressed!
9553 13:19:32.017072 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9554 13:19:32.023819 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9555 13:19:32.041255 Loading segment from ROM address 0x4010001c
9556 13:19:32.041786 Entry Point 0x80000000
9557 13:19:32.044298 Loaded segments
9558 13:19:32.048100 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9559 13:19:32.054522 Jumping to boot code at 0x80000000(0xffe64000)
9560 13:19:32.060960 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9561 13:19:32.067789 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9562 13:19:32.076109 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9563 13:19:32.079142 Checking segment from ROM address 0x40100000
9564 13:19:32.082365 Checking segment from ROM address 0x4010001c
9565 13:19:32.088635 Loading segment from ROM address 0x40100000
9566 13:19:32.089019 code (compression=1)
9567 13:19:32.095603 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9568 13:19:32.104918 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9569 13:19:32.105456 using LZMA
9570 13:19:32.113925 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9571 13:19:32.120621 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9572 13:19:32.123929 Loading segment from ROM address 0x4010001c
9573 13:19:32.127244 Entry Point 0x54601000
9574 13:19:32.127827 Loaded segments
9575 13:19:32.130315 NOTICE: MT8192 bl31_setup
9576 13:19:32.137653 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9577 13:19:32.140830 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9578 13:19:32.143958 WARNING: region 0:
9579 13:19:32.147228 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9580 13:19:32.147640 WARNING: region 1:
9581 13:19:32.154241 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9582 13:19:32.157436 WARNING: region 2:
9583 13:19:32.160664 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9584 13:19:32.163798 WARNING: region 3:
9585 13:19:32.170797 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9586 13:19:32.171189 WARNING: region 4:
9587 13:19:32.176989 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9588 13:19:32.177380 WARNING: region 5:
9589 13:19:32.180201 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9590 13:19:32.183990 WARNING: region 6:
9591 13:19:32.187088 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9592 13:19:32.190386 WARNING: region 7:
9593 13:19:32.193554 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9594 13:19:32.200118 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9595 13:19:32.203828 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9596 13:19:32.210611 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9597 13:19:32.213697 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9598 13:19:32.216876 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9599 13:19:32.223339 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9600 13:19:32.226445 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9601 13:19:32.230207 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9602 13:19:32.236518 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9603 13:19:32.239879 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9604 13:19:32.246728 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9605 13:19:32.249842 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9606 13:19:32.253094 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9607 13:19:32.259507 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9608 13:19:32.263279 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9609 13:19:32.266560 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9610 13:19:32.272875 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9611 13:19:32.276076 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9612 13:19:32.283201 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9613 13:19:32.286141 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9614 13:19:32.289353 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9615 13:19:32.296376 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9616 13:19:32.299482 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9617 13:19:32.306284 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9618 13:19:32.309626 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9619 13:19:32.312787 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9620 13:19:32.319555 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9621 13:19:32.322644 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9622 13:19:32.329717 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9623 13:19:32.332942 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9624 13:19:32.336121 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9625 13:19:32.342503 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9626 13:19:32.345717 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9627 13:19:32.349415 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9628 13:19:32.355660 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9629 13:19:32.359020 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9630 13:19:32.362437 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9631 13:19:32.365868 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9632 13:19:32.372500 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9633 13:19:32.375534 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9634 13:19:32.378733 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9635 13:19:32.382503 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9636 13:19:32.388781 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9637 13:19:32.391838 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9638 13:19:32.395530 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9639 13:19:32.398747 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9640 13:19:32.405161 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9641 13:19:32.409055 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9642 13:19:32.412074 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9643 13:19:32.418563 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9644 13:19:32.421967 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9645 13:19:32.428283 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9646 13:19:32.432131 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9647 13:19:32.438477 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9648 13:19:32.441648 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9649 13:19:32.444873 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9650 13:19:32.451883 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9651 13:19:32.455007 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9652 13:19:32.461669 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9653 13:19:32.464840 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9654 13:19:32.471497 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9655 13:19:32.474655 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9656 13:19:32.481716 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9657 13:19:32.484737 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9658 13:19:32.491407 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9659 13:19:32.494482 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9660 13:19:32.498116 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9661 13:19:32.504401 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9662 13:19:32.507699 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9663 13:19:32.514647 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9664 13:19:32.517823 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9665 13:19:32.524367 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9666 13:19:32.527474 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9667 13:19:32.530927 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9668 13:19:32.537495 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9669 13:19:32.540740 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9670 13:19:32.547753 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9671 13:19:32.550864 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9672 13:19:32.557359 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9673 13:19:32.560443 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9674 13:19:32.567228 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9675 13:19:32.570901 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9676 13:19:32.577434 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9677 13:19:32.580772 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9678 13:19:32.583687 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9679 13:19:32.590031 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9680 13:19:32.593747 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9681 13:19:32.600377 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9682 13:19:32.603579 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9683 13:19:32.610376 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9684 13:19:32.613649 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9685 13:19:32.616888 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9686 13:19:32.623175 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9687 13:19:32.626957 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9688 13:19:32.633201 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9689 13:19:32.636899 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9690 13:19:32.643310 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9691 13:19:32.646697 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9692 13:19:32.649899 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9693 13:19:32.653151 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9694 13:19:32.660001 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9695 13:19:32.663070 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9696 13:19:32.666254 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9697 13:19:32.672995 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9698 13:19:32.676115 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9699 13:19:32.683049 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9700 13:19:32.687787 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9701 13:19:32.689515 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9702 13:19:32.695944 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9703 13:19:32.699761 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9704 13:19:32.706013 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9705 13:19:32.709742 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9706 13:19:32.716063 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9707 13:19:32.719662 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9708 13:19:32.722675 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9709 13:19:32.729438 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9710 13:19:32.732630 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9711 13:19:32.735801 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9712 13:19:32.742511 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9713 13:19:32.745817 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9714 13:19:32.748881 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9715 13:19:32.752345 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9716 13:19:32.759185 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9717 13:19:32.762366 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9718 13:19:32.765525 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9719 13:19:32.771892 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9720 13:19:32.775771 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9721 13:19:32.778857 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9722 13:19:32.785391 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9723 13:19:32.788634 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9724 13:19:32.795739 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9725 13:19:32.798911 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9726 13:19:32.801934 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9727 13:19:32.808529 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9728 13:19:32.811732 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9729 13:19:32.818573 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9730 13:19:32.821585 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9731 13:19:32.825333 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9732 13:19:32.831624 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9733 13:19:32.834803 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9734 13:19:32.841663 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9735 13:19:32.844712 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9736 13:19:32.848187 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9737 13:19:32.854499 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9738 13:19:32.857971 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9739 13:19:32.864775 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9740 13:19:32.867955 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9741 13:19:32.871124 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9742 13:19:32.878020 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9743 13:19:32.881147 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9744 13:19:32.887630 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9745 13:19:32.890937 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9746 13:19:32.894426 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9747 13:19:32.900745 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9748 13:19:32.904100 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9749 13:19:32.911090 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9750 13:19:32.914276 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9751 13:19:32.917449 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9752 13:19:32.923839 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9753 13:19:32.927492 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9754 13:19:32.933918 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9755 13:19:32.937093 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9756 13:19:32.940390 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9757 13:19:32.947350 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9758 13:19:32.950524 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9759 13:19:32.957277 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9760 13:19:32.960255 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9761 13:19:32.963634 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9762 13:19:32.969918 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9763 13:19:32.973290 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9764 13:19:32.980096 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9765 13:19:32.983296 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9766 13:19:32.986566 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9767 13:19:32.993472 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9768 13:19:32.996439 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9769 13:19:33.003233 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9770 13:19:33.006463 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9771 13:19:33.009696 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9772 13:19:33.016807 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9773 13:19:33.019933 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9774 13:19:33.026228 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9775 13:19:33.029878 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9776 13:19:33.032983 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9777 13:19:33.039351 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9778 13:19:33.042595 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9779 13:19:33.049634 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9780 13:19:33.052848 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9781 13:19:33.056042 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9782 13:19:33.062912 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9783 13:19:33.066108 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9784 13:19:33.072343 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9785 13:19:33.075613 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9786 13:19:33.082222 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9787 13:19:33.085824 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9788 13:19:33.088728 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9789 13:19:33.095249 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9790 13:19:33.098624 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9791 13:19:33.105338 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9792 13:19:33.108484 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9793 13:19:33.115478 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9794 13:19:33.118606 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9795 13:19:33.122037 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9796 13:19:33.128417 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9797 13:19:33.132291 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9798 13:19:33.138614 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9799 13:19:33.141872 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9800 13:19:33.148247 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9801 13:19:33.152024 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9802 13:19:33.155221 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9803 13:19:33.161568 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9804 13:19:33.164846 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9805 13:19:33.171675 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9806 13:19:33.174642 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9807 13:19:33.178459 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9808 13:19:33.184940 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9809 13:19:33.188182 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9810 13:19:33.194763 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9811 13:19:33.198405 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9812 13:19:33.204591 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9813 13:19:33.208313 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9814 13:19:33.211521 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9815 13:19:33.217632 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9816 13:19:33.221129 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9817 13:19:33.227582 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9818 13:19:33.231037 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9819 13:19:33.237901 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9820 13:19:33.240849 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9821 13:19:33.244541 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9822 13:19:33.251107 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9823 13:19:33.254276 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9824 13:19:33.257580 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9825 13:19:33.260863 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9826 13:19:33.268029 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9827 13:19:33.271294 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9828 13:19:33.274500 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9829 13:19:33.280857 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9830 13:19:33.283965 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9831 13:19:33.287792 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9832 13:19:33.294160 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9833 13:19:33.297326 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9834 13:19:33.301109 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9835 13:19:33.307109 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9836 13:19:33.310680 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9837 13:19:33.316909 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9838 13:19:33.320732 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9839 13:19:33.323731 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9840 13:19:33.330399 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9841 13:19:33.333416 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9842 13:19:33.337159 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9843 13:19:33.343174 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9844 13:19:33.346536 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9845 13:19:33.353103 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9846 13:19:33.356274 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9847 13:19:33.360129 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9848 13:19:33.366498 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9849 13:19:33.369877 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9850 13:19:33.376184 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9851 13:19:33.379307 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9852 13:19:33.382438 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9853 13:19:33.389426 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9854 13:19:33.392679 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9855 13:19:33.395812 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9856 13:19:33.402269 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9857 13:19:33.406062 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9858 13:19:33.409077 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9859 13:19:33.415664 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9860 13:19:33.418998 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9861 13:19:33.425229 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9862 13:19:33.429077 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9863 13:19:33.432150 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9864 13:19:33.435638 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9865 13:19:33.442468 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9866 13:19:33.445553 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9867 13:19:33.448750 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9868 13:19:33.451819 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9869 13:19:33.458329 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9870 13:19:33.461904 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9871 13:19:33.465047 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9872 13:19:33.468820 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9873 13:19:33.475233 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9874 13:19:33.478382 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9875 13:19:33.482206 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9876 13:19:33.488505 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9877 13:19:33.492215 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9878 13:19:33.495279 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9879 13:19:33.501697 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9880 13:19:33.504823 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9881 13:19:33.511834 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9882 13:19:33.515027 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9883 13:19:33.518385 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9884 13:19:33.525188 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9885 13:19:33.528235 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9886 13:19:33.535188 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9887 13:19:33.538496 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9888 13:19:33.545020 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9889 13:19:33.547884 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9890 13:19:33.551418 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9891 13:19:33.557774 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9892 13:19:33.561542 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9893 13:19:33.567946 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9894 13:19:33.571413 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9895 13:19:33.574626 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9896 13:19:33.581110 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9897 13:19:33.584996 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9898 13:19:33.591261 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9899 13:19:33.594436 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9900 13:19:33.597629 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9901 13:19:33.604621 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9902 13:19:33.607854 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9903 13:19:33.614273 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9904 13:19:33.617443 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9905 13:19:33.624352 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9906 13:19:33.627564 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9907 13:19:33.630563 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9908 13:19:33.637853 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9909 13:19:33.640905 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9910 13:19:33.647223 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9911 13:19:33.650451 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9912 13:19:33.656917 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9913 13:19:33.660281 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9914 13:19:33.663601 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9915 13:19:33.670116 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9916 13:19:33.673865 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9917 13:19:33.680437 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9918 13:19:33.683737 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9919 13:19:33.686887 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9920 13:19:33.693320 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9921 13:19:33.697191 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9922 13:19:33.703387 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9923 13:19:33.706517 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9924 13:19:33.710381 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9925 13:19:33.716897 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9926 13:19:33.719981 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9927 13:19:33.726357 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9928 13:19:33.730160 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9929 13:19:33.736457 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9930 13:19:33.739575 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9931 13:19:33.743344 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9932 13:19:33.749702 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9933 13:19:33.752951 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9934 13:19:33.759771 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9935 13:19:33.762895 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9936 13:19:33.769223 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9937 13:19:33.772641 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9938 13:19:33.775871 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9939 13:19:33.782444 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9940 13:19:33.785957 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9941 13:19:33.792602 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9942 13:19:33.795862 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9943 13:19:33.799036 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9944 13:19:33.806048 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9945 13:19:33.809264 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9946 13:19:33.815633 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9947 13:19:33.818955 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9948 13:19:33.822054 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9949 13:19:33.829055 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9950 13:19:33.832198 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9951 13:19:33.838628 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9952 13:19:33.841853 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9953 13:19:33.848837 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9954 13:19:33.852028 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9955 13:19:33.858464 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9956 13:19:33.861729 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9957 13:19:33.865462 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9958 13:19:33.871990 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9959 13:19:33.875198 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9960 13:19:33.881760 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9961 13:19:33.885121 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9962 13:19:33.892221 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9963 13:19:33.895463 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9964 13:19:33.898418 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9965 13:19:33.904975 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9966 13:19:33.908508 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9967 13:19:33.915415 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9968 13:19:33.918619 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9969 13:19:33.924901 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9970 13:19:33.928120 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9971 13:19:33.931836 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9972 13:19:33.938292 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9973 13:19:33.941449 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9974 13:19:33.947916 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9975 13:19:33.951176 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9976 13:19:33.958020 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9977 13:19:33.961216 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9978 13:19:33.967630 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9979 13:19:33.971518 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9980 13:19:33.974678 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9981 13:19:33.981287 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9982 13:19:33.984200 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9983 13:19:33.991017 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9984 13:19:33.994440 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9985 13:19:34.000874 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9986 13:19:34.004374 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9987 13:19:34.011182 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9988 13:19:34.014156 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9989 13:19:34.017758 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9990 13:19:34.024506 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9991 13:19:34.027504 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9992 13:19:34.033789 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9993 13:19:34.037525 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9994 13:19:34.044049 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9995 13:19:34.047256 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9996 13:19:34.050562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9997 13:19:34.056885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9998 13:19:34.060621 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9999 13:19:34.066895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
10000 13:19:34.070208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
10001 13:19:34.077102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
10002 13:19:34.080252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
10003 13:19:34.087122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
10004 13:19:34.090230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
10005 13:19:34.096831 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
10006 13:19:34.100361 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
10007 13:19:34.107043 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10008 13:19:34.110218 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10009 13:19:34.116748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10010 13:19:34.120258 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10011 13:19:34.126503 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10012 13:19:34.130155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10013 13:19:34.136520 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10014 13:19:34.140158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10015 13:19:34.146590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10016 13:19:34.149824 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10017 13:19:34.156161 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10018 13:19:34.160013 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10019 13:19:34.166397 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10020 13:19:34.169701 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10021 13:19:34.176063 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10022 13:19:34.179946 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10023 13:19:34.186135 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10024 13:19:34.189288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10025 13:19:34.196030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10026 13:19:34.199821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10027 13:19:34.205833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10028 13:19:34.209383 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10029 13:19:34.212989 INFO: [APUAPC] vio 0
10030 13:19:34.216317 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10031 13:19:34.219320 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10032 13:19:34.222887 INFO: [APUAPC] D0_APC_0: 0x400510
10033 13:19:34.225847 INFO: [APUAPC] D0_APC_1: 0x0
10034 13:19:34.229343 INFO: [APUAPC] D0_APC_2: 0x1540
10035 13:19:34.232487 INFO: [APUAPC] D0_APC_3: 0x0
10036 13:19:34.236185 INFO: [APUAPC] D1_APC_0: 0xffffffff
10037 13:19:34.239138 INFO: [APUAPC] D1_APC_1: 0xffffffff
10038 13:19:34.242931 INFO: [APUAPC] D1_APC_2: 0x3fffff
10039 13:19:34.245699 INFO: [APUAPC] D1_APC_3: 0x0
10040 13:19:34.249257 INFO: [APUAPC] D2_APC_0: 0xffffffff
10041 13:19:34.252211 INFO: [APUAPC] D2_APC_1: 0xffffffff
10042 13:19:34.256155 INFO: [APUAPC] D2_APC_2: 0x3fffff
10043 13:19:34.259335 INFO: [APUAPC] D2_APC_3: 0x0
10044 13:19:34.262553 INFO: [APUAPC] D3_APC_0: 0xffffffff
10045 13:19:34.265800 INFO: [APUAPC] D3_APC_1: 0xffffffff
10046 13:19:34.268905 INFO: [APUAPC] D3_APC_2: 0x3fffff
10047 13:19:34.272114 INFO: [APUAPC] D3_APC_3: 0x0
10048 13:19:34.276058 INFO: [APUAPC] D4_APC_0: 0xffffffff
10049 13:19:34.279205 INFO: [APUAPC] D4_APC_1: 0xffffffff
10050 13:19:34.282409 INFO: [APUAPC] D4_APC_2: 0x3fffff
10051 13:19:34.285620 INFO: [APUAPC] D4_APC_3: 0x0
10052 13:19:34.288806 INFO: [APUAPC] D5_APC_0: 0xffffffff
10053 13:19:34.292507 INFO: [APUAPC] D5_APC_1: 0xffffffff
10054 13:19:34.295618 INFO: [APUAPC] D5_APC_2: 0x3fffff
10055 13:19:34.298738 INFO: [APUAPC] D5_APC_3: 0x0
10056 13:19:34.301985 INFO: [APUAPC] D6_APC_0: 0xffffffff
10057 13:19:34.305657 INFO: [APUAPC] D6_APC_1: 0xffffffff
10058 13:19:34.308853 INFO: [APUAPC] D6_APC_2: 0x3fffff
10059 13:19:34.311820 INFO: [APUAPC] D6_APC_3: 0x0
10060 13:19:34.315374 INFO: [APUAPC] D7_APC_0: 0xffffffff
10061 13:19:34.318434 INFO: [APUAPC] D7_APC_1: 0xffffffff
10062 13:19:34.321810 INFO: [APUAPC] D7_APC_2: 0x3fffff
10063 13:19:34.325470 INFO: [APUAPC] D7_APC_3: 0x0
10064 13:19:34.328573 INFO: [APUAPC] D8_APC_0: 0xffffffff
10065 13:19:34.332124 INFO: [APUAPC] D8_APC_1: 0xffffffff
10066 13:19:34.335073 INFO: [APUAPC] D8_APC_2: 0x3fffff
10067 13:19:34.338801 INFO: [APUAPC] D8_APC_3: 0x0
10068 13:19:34.341810 INFO: [APUAPC] D9_APC_0: 0xffffffff
10069 13:19:34.345464 INFO: [APUAPC] D9_APC_1: 0xffffffff
10070 13:19:34.348659 INFO: [APUAPC] D9_APC_2: 0x3fffff
10071 13:19:34.348742 INFO: [APUAPC] D9_APC_3: 0x0
10072 13:19:34.354995 INFO: [APUAPC] D10_APC_0: 0xffffffff
10073 13:19:34.358612 INFO: [APUAPC] D10_APC_1: 0xffffffff
10074 13:19:34.361680 INFO: [APUAPC] D10_APC_2: 0x3fffff
10075 13:19:34.361800 INFO: [APUAPC] D10_APC_3: 0x0
10076 13:19:34.368712 INFO: [APUAPC] D11_APC_0: 0xffffffff
10077 13:19:34.371799 INFO: [APUAPC] D11_APC_1: 0xffffffff
10078 13:19:34.375072 INFO: [APUAPC] D11_APC_2: 0x3fffff
10079 13:19:34.378330 INFO: [APUAPC] D11_APC_3: 0x0
10080 13:19:34.381555 INFO: [APUAPC] D12_APC_0: 0xffffffff
10081 13:19:34.384755 INFO: [APUAPC] D12_APC_1: 0xffffffff
10082 13:19:34.388011 INFO: [APUAPC] D12_APC_2: 0x3fffff
10083 13:19:34.391840 INFO: [APUAPC] D12_APC_3: 0x0
10084 13:19:34.395014 INFO: [APUAPC] D13_APC_0: 0xffffffff
10085 13:19:34.398161 INFO: [APUAPC] D13_APC_1: 0xffffffff
10086 13:19:34.401402 INFO: [APUAPC] D13_APC_2: 0x3fffff
10087 13:19:34.405185 INFO: [APUAPC] D13_APC_3: 0x0
10088 13:19:34.408276 INFO: [APUAPC] D14_APC_0: 0xffffffff
10089 13:19:34.411443 INFO: [APUAPC] D14_APC_1: 0xffffffff
10090 13:19:34.415102 INFO: [APUAPC] D14_APC_2: 0x3fffff
10091 13:19:34.418284 INFO: [APUAPC] D14_APC_3: 0x0
10092 13:19:34.421245 INFO: [APUAPC] D15_APC_0: 0xffffffff
10093 13:19:34.424855 INFO: [APUAPC] D15_APC_1: 0xffffffff
10094 13:19:34.427938 INFO: [APUAPC] D15_APC_2: 0x3fffff
10095 13:19:34.431641 INFO: [APUAPC] D15_APC_3: 0x0
10096 13:19:34.431750 INFO: [APUAPC] APC_CON: 0x4
10097 13:19:34.434623 INFO: [NOCDAPC] D0_APC_0: 0x0
10098 13:19:34.437752 INFO: [NOCDAPC] D0_APC_1: 0x0
10099 13:19:34.441603 INFO: [NOCDAPC] D1_APC_0: 0x0
10100 13:19:34.444468 INFO: [NOCDAPC] D1_APC_1: 0xfff
10101 13:19:34.447942 INFO: [NOCDAPC] D2_APC_0: 0x0
10102 13:19:34.450923 INFO: [NOCDAPC] D2_APC_1: 0xfff
10103 13:19:34.454710 INFO: [NOCDAPC] D3_APC_0: 0x0
10104 13:19:34.458058 INFO: [NOCDAPC] D3_APC_1: 0xfff
10105 13:19:34.461062 INFO: [NOCDAPC] D4_APC_0: 0x0
10106 13:19:34.464565 INFO: [NOCDAPC] D4_APC_1: 0xfff
10107 13:19:34.464649 INFO: [NOCDAPC] D5_APC_0: 0x0
10108 13:19:34.467691 INFO: [NOCDAPC] D5_APC_1: 0xfff
10109 13:19:34.470842 INFO: [NOCDAPC] D6_APC_0: 0x0
10110 13:19:34.474022 INFO: [NOCDAPC] D6_APC_1: 0xfff
10111 13:19:34.477829 INFO: [NOCDAPC] D7_APC_0: 0x0
10112 13:19:34.481067 INFO: [NOCDAPC] D7_APC_1: 0xfff
10113 13:19:34.484344 INFO: [NOCDAPC] D8_APC_0: 0x0
10114 13:19:34.487380 INFO: [NOCDAPC] D8_APC_1: 0xfff
10115 13:19:34.490576 INFO: [NOCDAPC] D9_APC_0: 0x0
10116 13:19:34.494334 INFO: [NOCDAPC] D9_APC_1: 0xfff
10117 13:19:34.497453 INFO: [NOCDAPC] D10_APC_0: 0x0
10118 13:19:34.500677 INFO: [NOCDAPC] D10_APC_1: 0xfff
10119 13:19:34.500759 INFO: [NOCDAPC] D11_APC_0: 0x0
10120 13:19:34.503833 INFO: [NOCDAPC] D11_APC_1: 0xfff
10121 13:19:34.507622 INFO: [NOCDAPC] D12_APC_0: 0x0
10122 13:19:34.510700 INFO: [NOCDAPC] D12_APC_1: 0xfff
10123 13:19:34.513875 INFO: [NOCDAPC] D13_APC_0: 0x0
10124 13:19:34.517073 INFO: [NOCDAPC] D13_APC_1: 0xfff
10125 13:19:34.520854 INFO: [NOCDAPC] D14_APC_0: 0x0
10126 13:19:34.523855 INFO: [NOCDAPC] D14_APC_1: 0xfff
10127 13:19:34.526980 INFO: [NOCDAPC] D15_APC_0: 0x0
10128 13:19:34.530463 INFO: [NOCDAPC] D15_APC_1: 0xfff
10129 13:19:34.533635 INFO: [NOCDAPC] APC_CON: 0x4
10130 13:19:34.537320 INFO: [APUAPC] set_apusys_apc done
10131 13:19:34.540381 INFO: [DEVAPC] devapc_init done
10132 13:19:34.543637 INFO: GICv3 without legacy support detected.
10133 13:19:34.546829 INFO: ARM GICv3 driver initialized in EL3
10134 13:19:34.550565 INFO: Maximum SPI INTID supported: 639
10135 13:19:34.556536 INFO: BL31: Initializing runtime services
10136 13:19:34.560131 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10137 13:19:34.563689 INFO: SPM: enable CPC mode
10138 13:19:34.569821 INFO: mcdi ready for mcusys-off-idle and system suspend
10139 13:19:34.573498 INFO: BL31: Preparing for EL3 exit to normal world
10140 13:19:34.576803 INFO: Entry point address = 0x80000000
10141 13:19:34.579986 INFO: SPSR = 0x8
10142 13:19:34.585117
10143 13:19:34.585208
10144 13:19:34.585269
10145 13:19:34.588342 Starting depthcharge on Spherion...
10146 13:19:34.588421
10147 13:19:34.588480 Wipe memory regions:
10148 13:19:34.588536
10149 13:19:34.589170 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10150 13:19:34.589262 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10151 13:19:34.589338 Setting prompt string to ['asurada:']
10152 13:19:34.589405 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10153 13:19:34.592129 [0x00000040000000, 0x00000054600000)
10154 13:19:34.714107
10155 13:19:34.714287 [0x00000054660000, 0x00000080000000)
10156 13:19:34.974327
10157 13:19:34.974487 [0x000000821a7280, 0x000000ffe64000)
10158 13:19:35.718731
10159 13:19:35.718894 [0x00000100000000, 0x00000240000000)
10160 13:19:37.605852
10161 13:19:37.608804 Initializing XHCI USB controller at 0x11200000.
10162 13:19:38.647807
10163 13:19:38.651561 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10164 13:19:38.651642
10165 13:19:38.651701
10166 13:19:38.651976 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10167 13:19:38.652090 Sending line: 'tftpboot 192.168.201.1 14879048/tftp-deploy-56hlfbtr/kernel/image.itb 14879048/tftp-deploy-56hlfbtr/kernel/cmdline '
10169 13:19:38.752607 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10170 13:19:38.752701 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10171 13:19:38.757029 asurada: tftpboot 192.168.201.1 14879048/tftp-deploy-56hlfbtr/kernel/image.itp-deploy-56hlfbtr/kernel/cmdline
10172 13:19:38.757107
10173 13:19:38.757165 Waiting for link
10174 13:19:38.915022
10175 13:19:38.915155 R8152: Initializing
10176 13:19:38.915215
10177 13:19:38.918130 Version 6 (ocp_data = 5c30)
10178 13:19:38.918205
10179 13:19:38.921324 R8152: Done initializing
10180 13:19:38.921399
10181 13:19:38.921457 Adding net device
10182 13:19:40.827115
10183 13:19:40.827271 done.
10184 13:19:40.827363
10185 13:19:40.827469 MAC: 00:e0:4c:68:02:81
10186 13:19:40.827554
10187 13:19:40.830316 Sending DHCP discover... done.
10188 13:19:40.830392
10189 13:19:40.834471 Waiting for reply... done.
10190 13:19:40.834573
10191 13:19:40.836870 Sending DHCP request... done.
10192 13:19:40.836961
10193 13:19:40.841360 Waiting for reply... done.
10194 13:19:40.841477
10195 13:19:40.841567 My ip is 192.168.201.14
10196 13:19:40.841653
10197 13:19:40.844531 The DHCP server ip is 192.168.201.1
10198 13:19:40.844606
10199 13:19:40.851380 TFTP server IP predefined by user: 192.168.201.1
10200 13:19:40.851503
10201 13:19:40.857728 Bootfile predefined by user: 14879048/tftp-deploy-56hlfbtr/kernel/image.itb
10202 13:19:40.857806
10203 13:19:40.860916 Sending tftp read request... done.
10204 13:19:40.860992
10205 13:19:40.865324 Waiting for the transfer...
10206 13:19:40.865398
10207 13:19:41.425573 00000000 ################################################################
10208 13:19:41.425719
10209 13:19:41.985044 00080000 ################################################################
10210 13:19:41.985166
10211 13:19:42.545051 00100000 ################################################################
10212 13:19:42.545177
10213 13:19:43.102315 00180000 ################################################################
10214 13:19:43.102455
10215 13:19:43.661566 00200000 ################################################################
10216 13:19:43.661692
10217 13:19:44.207403 00280000 ################################################################
10218 13:19:44.207532
10219 13:19:44.760123 00300000 ################################################################
10220 13:19:44.760270
10221 13:19:45.318034 00380000 ################################################################
10222 13:19:45.318164
10223 13:19:45.904187 00400000 ################################################################
10224 13:19:45.904401
10225 13:19:46.465839 00480000 ################################################################
10226 13:19:46.465972
10227 13:19:47.087351 00500000 ################################################################
10228 13:19:47.087785
10229 13:19:47.747238 00580000 ################################################################
10230 13:19:47.747904
10231 13:19:48.401856 00600000 ################################################################
10232 13:19:48.402312
10233 13:19:49.059123 00680000 ################################################################
10234 13:19:49.059591
10235 13:19:49.741499 00700000 ################################################################
10236 13:19:49.742156
10237 13:19:50.420371 00780000 ################################################################
10238 13:19:50.420996
10239 13:19:51.091849 00800000 ################################################################
10240 13:19:51.092293
10241 13:19:51.740527 00880000 ################################################################
10242 13:19:51.740829
10243 13:19:52.373854 00900000 ################################################################
10244 13:19:52.374344
10245 13:19:53.014547 00980000 ################################################################
10246 13:19:53.014659
10247 13:19:53.607384 00a00000 ################################################################
10248 13:19:53.607624
10249 13:19:54.244927 00a80000 ################################################################
10250 13:19:54.245240
10251 13:19:54.905319 00b00000 ################################################################
10252 13:19:54.905451
10253 13:19:55.466326 00b80000 ################################################################
10254 13:19:55.466460
10255 13:19:56.011167 00c00000 ################################################################
10256 13:19:56.011299
10257 13:19:56.573197 00c80000 ################################################################
10258 13:19:56.573340
10259 13:19:57.094129 00d00000 ################################################################
10260 13:19:57.094262
10261 13:19:57.617830 00d80000 ################################################################
10262 13:19:57.618049
10263 13:19:58.161371 00e00000 ################################################################
10264 13:19:58.161479
10265 13:19:58.688796 00e80000 ################################################################
10266 13:19:58.688938
10267 13:19:59.203392 00f00000 ################################################################
10268 13:19:59.203534
10269 13:19:59.724011 00f80000 ################################################################
10270 13:19:59.724135
10271 13:20:00.270382 01000000 ################################################################
10272 13:20:00.270520
10273 13:20:00.793442 01080000 ################################################################
10274 13:20:00.793577
10275 13:20:01.314001 01100000 ################################################################
10276 13:20:01.314119
10277 13:20:01.846935 01180000 ################################################################
10278 13:20:01.847084
10279 13:20:02.388631 01200000 ################################################################
10280 13:20:02.388755
10281 13:20:02.924132 01280000 ################################################################
10282 13:20:02.924276
10283 13:20:03.461941 01300000 ################################################################
10284 13:20:03.462091
10285 13:20:03.994729 01380000 ################################################################
10286 13:20:03.994869
10287 13:20:04.531590 01400000 ################################################################
10288 13:20:04.531703
10289 13:20:05.074137 01480000 ################################################################
10290 13:20:05.074253
10291 13:20:05.608996 01500000 ################################################################
10292 13:20:05.609120
10293 13:20:06.144743 01580000 ################################################################
10294 13:20:06.144870
10295 13:20:06.666962 01600000 ################################################################
10296 13:20:06.667117
10297 13:20:07.187159 01680000 ################################################################
10298 13:20:07.187313
10299 13:20:07.710889 01700000 ################################################################
10300 13:20:07.711000
10301 13:20:08.239747 01780000 ################################################################
10302 13:20:08.239874
10303 13:20:08.794565 01800000 ################################################################
10304 13:20:08.794685
10305 13:20:09.394758 01880000 ################################################################
10306 13:20:09.394907
10307 13:20:09.967923 01900000 ################################################################
10308 13:20:09.968045
10309 13:20:10.504631 01980000 ################################################################
10310 13:20:10.504743
10311 13:20:11.047959 01a00000 ################################################################
10312 13:20:11.048074
10313 13:20:11.587969 01a80000 ################################################################
10314 13:20:11.588082
10315 13:20:12.117302 01b00000 ################################################################
10316 13:20:12.117420
10317 13:20:12.645275 01b80000 ################################################################
10318 13:20:12.645394
10319 13:20:13.167764 01c00000 ################################################################
10320 13:20:13.167881
10321 13:20:13.718698 01c80000 ################################################################
10322 13:20:13.718812
10323 13:20:14.273131 01d00000 ################################################################
10324 13:20:14.273246
10325 13:20:14.819552 01d80000 ################################################################
10326 13:20:14.819665
10327 13:20:15.267202 01e00000 ##################################################### done.
10328 13:20:15.267375
10329 13:20:15.270384 The bootfile was 31885358 bytes long.
10330 13:20:15.273280
10331 13:20:15.273378 Sending tftp read request... done.
10332 13:20:15.273467
10333 13:20:15.276937 Waiting for the transfer...
10334 13:20:15.277035
10335 13:20:15.279913 00000000 # done.
10336 13:20:15.279991
10337 13:20:15.287131 Command line loaded dynamically from TFTP file: 14879048/tftp-deploy-56hlfbtr/kernel/cmdline
10338 13:20:15.287233
10339 13:20:15.309644 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14879048/extract-nfsrootfs-brtvvc40,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10340 13:20:15.309735
10341 13:20:15.309795 Loading FIT.
10342 13:20:15.309850
10343 13:20:15.313393 Image ramdisk-1 has 18721602 bytes.
10344 13:20:15.313469
10345 13:20:15.316324 Image fdt-1 has 47258 bytes.
10346 13:20:15.316402
10347 13:20:15.319536 Image kernel-1 has 13114469 bytes.
10348 13:20:15.319613
10349 13:20:15.329903 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10350 13:20:15.329982
10351 13:20:15.345807 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10352 13:20:15.345915
10353 13:20:15.352900 Choosing best match conf-1 for compat google,spherion-rev2.
10354 13:20:15.353000
10355 13:20:15.359986 Connected to device vid:did:rid of 1ae0:0028:00
10356 13:20:15.367044
10357 13:20:15.370330 tpm_get_response: command 0x17b, return code 0x0
10358 13:20:15.370422
10359 13:20:15.373564 ec_init: CrosEC protocol v3 supported (256, 248)
10360 13:20:15.378072
10361 13:20:15.381804 tpm_cleanup: add release locality here.
10362 13:20:15.381896
10363 13:20:15.381980 Shutting down all USB controllers.
10364 13:20:15.384853
10365 13:20:15.384953 Removing current net device
10366 13:20:15.385036
10367 13:20:15.391576 Exiting depthcharge with code 4 at timestamp: 70260983
10368 13:20:15.391647
10369 13:20:15.394919 LZMA decompressing kernel-1 to 0x821a6718
10370 13:20:15.395010
10371 13:20:15.397937 LZMA decompressing kernel-1 to 0x40000000
10372 13:20:17.013815
10373 13:20:17.013948 jumping to kernel
10374 13:20:17.014646 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10375 13:20:17.014741 start: 2.2.5 auto-login-action (timeout 00:03:37) [common]
10376 13:20:17.014836 Setting prompt string to ['Linux version [0-9]']
10377 13:20:17.014924 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10378 13:20:17.015015 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10379 13:20:17.094509
10380 13:20:17.097861 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10381 13:20:17.101589 start: 2.2.5.1 login-action (timeout 00:03:37) [common]
10382 13:20:17.101710 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10383 13:20:17.101804 Setting prompt string to []
10384 13:20:17.101905 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10385 13:20:17.101996 Using line separator: #'\n'#
10386 13:20:17.102078 No login prompt set.
10387 13:20:17.102160 Parsing kernel messages
10388 13:20:17.102236 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10389 13:20:17.102397 [login-action] Waiting for messages, (timeout 00:03:37)
10390 13:20:17.102498 Waiting using forced prompt support (timeout 00:01:49)
10391 13:20:17.120921 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j272990-arm64-gcc-12-defconfig-arm64-chromebook-fgzcq) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024
10392 13:20:17.124070 [ 0.000000] random: crng init done
10393 13:20:17.127213 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10394 13:20:17.130356 [ 0.000000] efi: UEFI not found.
10395 13:20:17.140629 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10396 13:20:17.146919 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10397 13:20:17.157152 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10398 13:20:17.166686 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10399 13:20:17.173574 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10400 13:20:17.176803 [ 0.000000] printk: bootconsole [mtk8250] enabled
10401 13:20:17.185230 [ 0.000000] NUMA: No NUMA configuration found
10402 13:20:17.192111 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10403 13:20:17.198425 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10404 13:20:17.198521 [ 0.000000] Zone ranges:
10405 13:20:17.205180 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10406 13:20:17.208319 [ 0.000000] DMA32 empty
10407 13:20:17.215261 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10408 13:20:17.218650 [ 0.000000] Movable zone start for each node
10409 13:20:17.221787 [ 0.000000] Early memory node ranges
10410 13:20:17.228282 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10411 13:20:17.234810 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10412 13:20:17.241208 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10413 13:20:17.247599 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10414 13:20:17.254380 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10415 13:20:17.260568 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10416 13:20:17.319066 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10417 13:20:17.325245 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10418 13:20:17.332341 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10419 13:20:17.335420 [ 0.000000] psci: probing for conduit method from DT.
10420 13:20:17.342109 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10421 13:20:17.345304 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10422 13:20:17.352223 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10423 13:20:17.355365 [ 0.000000] psci: SMC Calling Convention v1.2
10424 13:20:17.361674 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10425 13:20:17.365410 [ 0.000000] Detected VIPT I-cache on CPU0
10426 13:20:17.372025 [ 0.000000] CPU features: detected: GIC system register CPU interface
10427 13:20:17.378130 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10428 13:20:17.385370 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10429 13:20:17.391775 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10430 13:20:17.401336 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10431 13:20:17.408194 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10432 13:20:17.411409 [ 0.000000] alternatives: applying boot alternatives
10433 13:20:17.417821 [ 0.000000] Fallback order for Node 0: 0
10434 13:20:17.424212 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10435 13:20:17.427885 [ 0.000000] Policy zone: Normal
10436 13:20:17.451207 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14879048/extract-nfsrootfs-brtvvc40,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10437 13:20:17.460831 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10438 13:20:17.470708 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10439 13:20:17.480773 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10440 13:20:17.487120 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10441 13:20:17.490767 <6>[ 0.000000] software IO TLB: area num 8.
10442 13:20:17.547742 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10443 13:20:17.696872 <6>[ 0.000000] Memory: 7945776K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 406992K reserved, 32768K cma-reserved)
10444 13:20:17.703946 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10445 13:20:17.710428 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10446 13:20:17.713536 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10447 13:20:17.720204 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10448 13:20:17.726992 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10449 13:20:17.730043 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10450 13:20:17.739897 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10451 13:20:17.746669 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10452 13:20:17.752891 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10453 13:20:17.759674 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10454 13:20:17.763079 <6>[ 0.000000] GICv3: 608 SPIs implemented
10455 13:20:17.765904 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10456 13:20:17.772905 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10457 13:20:17.776060 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10458 13:20:17.782918 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10459 13:20:17.795715 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10460 13:20:17.809141 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10461 13:20:17.815627 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10462 13:20:17.823840 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10463 13:20:17.836781 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10464 13:20:17.843717 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10465 13:20:17.850007 <6>[ 0.009178] Console: colour dummy device 80x25
10466 13:20:17.860423 <6>[ 0.013911] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10467 13:20:17.866970 <6>[ 0.024353] pid_max: default: 32768 minimum: 301
10468 13:20:17.870005 <6>[ 0.029226] LSM: Security Framework initializing
10469 13:20:17.876635 <6>[ 0.034164] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10470 13:20:17.886669 <6>[ 0.041977] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10471 13:20:17.896394 <6>[ 0.051401] cblist_init_generic: Setting adjustable number of callback queues.
10472 13:20:17.899593 <6>[ 0.058889] cblist_init_generic: Setting shift to 3 and lim to 1.
10473 13:20:17.909803 <6>[ 0.065228] cblist_init_generic: Setting adjustable number of callback queues.
10474 13:20:17.916358 <6>[ 0.072654] cblist_init_generic: Setting shift to 3 and lim to 1.
10475 13:20:17.919655 <6>[ 0.079054] rcu: Hierarchical SRCU implementation.
10476 13:20:17.925876 <6>[ 0.084100] rcu: Max phase no-delay instances is 1000.
10477 13:20:17.932481 <6>[ 0.091132] EFI services will not be available.
10478 13:20:17.935641 <6>[ 0.096121] smp: Bringing up secondary CPUs ...
10479 13:20:17.945014 <6>[ 0.101202] Detected VIPT I-cache on CPU1
10480 13:20:17.951571 <6>[ 0.101274] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10481 13:20:17.957899 <6>[ 0.101306] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10482 13:20:17.961531 <6>[ 0.101651] Detected VIPT I-cache on CPU2
10483 13:20:17.971044 <6>[ 0.101706] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10484 13:20:17.977430 <6>[ 0.101723] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10485 13:20:17.981212 <6>[ 0.101988] Detected VIPT I-cache on CPU3
10486 13:20:17.987881 <6>[ 0.102035] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10487 13:20:17.994082 <6>[ 0.102049] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10488 13:20:18.000766 <6>[ 0.102357] CPU features: detected: Spectre-v4
10489 13:20:18.004203 <6>[ 0.102364] CPU features: detected: Spectre-BHB
10490 13:20:18.007654 <6>[ 0.102370] Detected PIPT I-cache on CPU4
10491 13:20:18.014288 <6>[ 0.102430] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10492 13:20:18.020913 <6>[ 0.102447] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10493 13:20:18.027226 <6>[ 0.102742] Detected PIPT I-cache on CPU5
10494 13:20:18.033732 <6>[ 0.102804] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10495 13:20:18.040173 <6>[ 0.102820] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10496 13:20:18.043362 <6>[ 0.103105] Detected PIPT I-cache on CPU6
10497 13:20:18.050416 <6>[ 0.103170] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10498 13:20:18.056952 <6>[ 0.103186] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10499 13:20:18.063273 <6>[ 0.103485] Detected PIPT I-cache on CPU7
10500 13:20:18.070066 <6>[ 0.103551] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10501 13:20:18.076336 <6>[ 0.103566] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10502 13:20:18.079641 <6>[ 0.103614] smp: Brought up 1 node, 8 CPUs
10503 13:20:18.086640 <6>[ 0.244889] SMP: Total of 8 processors activated.
10504 13:20:18.089787 <6>[ 0.249810] CPU features: detected: 32-bit EL0 Support
10505 13:20:18.099741 <6>[ 0.255206] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10506 13:20:18.106071 <6>[ 0.264007] CPU features: detected: Common not Private translations
10507 13:20:18.112524 <6>[ 0.270483] CPU features: detected: CRC32 instructions
10508 13:20:18.119562 <6>[ 0.275834] CPU features: detected: RCpc load-acquire (LDAPR)
10509 13:20:18.122902 <6>[ 0.281794] CPU features: detected: LSE atomic instructions
10510 13:20:18.129237 <6>[ 0.287575] CPU features: detected: Privileged Access Never
10511 13:20:18.136017 <6>[ 0.293355] CPU features: detected: RAS Extension Support
10512 13:20:18.142563 <6>[ 0.298963] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10513 13:20:18.145745 <6>[ 0.306226] CPU: All CPU(s) started at EL2
10514 13:20:18.152162 <6>[ 0.310543] alternatives: applying system-wide alternatives
10515 13:20:18.162323 <6>[ 0.321414] devtmpfs: initialized
10516 13:20:18.177705 <6>[ 0.330269] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10517 13:20:18.184616 <6>[ 0.340232] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10518 13:20:18.191094 <6>[ 0.348481] pinctrl core: initialized pinctrl subsystem
10519 13:20:18.194390 <6>[ 0.355152] DMI not present or invalid.
10520 13:20:18.200892 <6>[ 0.359563] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10521 13:20:18.211299 <6>[ 0.366455] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10522 13:20:18.217744 <6>[ 0.374042] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10523 13:20:18.227193 <6>[ 0.382274] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10524 13:20:18.230831 <6>[ 0.390514] audit: initializing netlink subsys (disabled)
10525 13:20:18.240304 <5>[ 0.396198] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10526 13:20:18.247042 <6>[ 0.396900] thermal_sys: Registered thermal governor 'step_wise'
10527 13:20:18.254060 <6>[ 0.404161] thermal_sys: Registered thermal governor 'power_allocator'
10528 13:20:18.257251 <6>[ 0.410413] cpuidle: using governor menu
10529 13:20:18.263768 <6>[ 0.421370] NET: Registered PF_QIPCRTR protocol family
10530 13:20:18.270153 <6>[ 0.426871] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10531 13:20:18.276442 <6>[ 0.433971] ASID allocator initialised with 32768 entries
10532 13:20:18.280220 <6>[ 0.440545] Serial: AMBA PL011 UART driver
10533 13:20:18.290915 <4>[ 0.449902] Trying to register duplicate clock ID: 134
10534 13:20:18.350541 <6>[ 0.512938] KASLR enabled
10535 13:20:18.365218 <6>[ 0.520634] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10536 13:20:18.371315 <6>[ 0.527651] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10537 13:20:18.378410 <6>[ 0.534143] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10538 13:20:18.384854 <6>[ 0.541150] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10539 13:20:18.391528 <6>[ 0.547641] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10540 13:20:18.398060 <6>[ 0.554647] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10541 13:20:18.404481 <6>[ 0.561131] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10542 13:20:18.410859 <6>[ 0.568134] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10543 13:20:18.414632 <6>[ 0.575655] ACPI: Interpreter disabled.
10544 13:20:18.423301 <6>[ 0.582107] iommu: Default domain type: Translated
10545 13:20:18.429502 <6>[ 0.587220] iommu: DMA domain TLB invalidation policy: strict mode
10546 13:20:18.433415 <5>[ 0.593876] SCSI subsystem initialized
10547 13:20:18.439875 <6>[ 0.598039] usbcore: registered new interface driver usbfs
10548 13:20:18.446379 <6>[ 0.603775] usbcore: registered new interface driver hub
10549 13:20:18.449299 <6>[ 0.609321] usbcore: registered new device driver usb
10550 13:20:18.456451 <6>[ 0.615439] pps_core: LinuxPPS API ver. 1 registered
10551 13:20:18.466518 <6>[ 0.620634] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10552 13:20:18.469603 <6>[ 0.629981] PTP clock support registered
10553 13:20:18.473046 <6>[ 0.634220] EDAC MC: Ver: 3.0.0
10554 13:20:18.480245 <6>[ 0.639394] FPGA manager framework
10555 13:20:18.486677 <6>[ 0.643081] Advanced Linux Sound Architecture Driver Initialized.
10556 13:20:18.490034 <6>[ 0.649885] vgaarb: loaded
10557 13:20:18.496567 <6>[ 0.653056] clocksource: Switched to clocksource arch_sys_counter
10558 13:20:18.500367 <5>[ 0.659499] VFS: Disk quotas dquot_6.6.0
10559 13:20:18.506876 <6>[ 0.663681] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10560 13:20:18.509928 <6>[ 0.670868] pnp: PnP ACPI: disabled
10561 13:20:18.518780 <6>[ 0.677593] NET: Registered PF_INET protocol family
10562 13:20:18.528299 <6>[ 0.683183] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10563 13:20:18.539674 <6>[ 0.695493] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10564 13:20:18.549832 <6>[ 0.704308] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10565 13:20:18.556147 <6>[ 0.712279] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10566 13:20:18.565863 <6>[ 0.720985] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10567 13:20:18.572361 <6>[ 0.730741] TCP: Hash tables configured (established 65536 bind 65536)
10568 13:20:18.578970 <6>[ 0.737609] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10569 13:20:18.589066 <6>[ 0.744805] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10570 13:20:18.595350 <6>[ 0.752508] NET: Registered PF_UNIX/PF_LOCAL protocol family
10571 13:20:18.602313 <6>[ 0.758674] RPC: Registered named UNIX socket transport module.
10572 13:20:18.605367 <6>[ 0.764829] RPC: Registered udp transport module.
10573 13:20:18.612108 <6>[ 0.769763] RPC: Registered tcp transport module.
10574 13:20:18.618308 <6>[ 0.774696] RPC: Registered tcp NFSv4.1 backchannel transport module.
10575 13:20:18.622159 <6>[ 0.781364] PCI: CLS 0 bytes, default 64
10576 13:20:18.625300 <6>[ 0.785705] Unpacking initramfs...
10577 13:20:18.649511 <6>[ 0.805199] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10578 13:20:18.659637 <6>[ 0.813869] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10579 13:20:18.662964 <6>[ 0.822731] kvm [1]: IPA Size Limit: 40 bits
10580 13:20:18.669223 <6>[ 0.827264] kvm [1]: GICv3: no GICV resource entry
10581 13:20:18.672403 <6>[ 0.832283] kvm [1]: disabling GICv2 emulation
10582 13:20:18.679273 <6>[ 0.836970] kvm [1]: GIC system register CPU interface enabled
10583 13:20:18.682499 <6>[ 0.843130] kvm [1]: vgic interrupt IRQ18
10584 13:20:18.688954 <6>[ 0.847478] kvm [1]: VHE mode initialized successfully
10585 13:20:18.695620 <5>[ 0.853916] Initialise system trusted keyrings
10586 13:20:18.702557 <6>[ 0.858746] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10587 13:20:18.709932 <6>[ 0.868750] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10588 13:20:18.716805 <5>[ 0.875138] NFS: Registering the id_resolver key type
10589 13:20:18.719671 <5>[ 0.880443] Key type id_resolver registered
10590 13:20:18.726060 <5>[ 0.884858] Key type id_legacy registered
10591 13:20:18.732684 <6>[ 0.889137] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10592 13:20:18.739553 <6>[ 0.896056] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10593 13:20:18.745723 <6>[ 0.903792] 9p: Installing v9fs 9p2000 file system support
10594 13:20:18.783140 <5>[ 0.942028] Key type asymmetric registered
10595 13:20:18.786347 <5>[ 0.946361] Asymmetric key parser 'x509' registered
10596 13:20:18.795957 <6>[ 0.951530] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10597 13:20:18.799714 <6>[ 0.959153] io scheduler mq-deadline registered
10598 13:20:18.803064 <6>[ 0.963912] io scheduler kyber registered
10599 13:20:18.822304 <6>[ 0.981170] EINJ: ACPI disabled.
10600 13:20:18.855248 <4>[ 1.007731] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10601 13:20:18.865398 <4>[ 1.018359] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10602 13:20:18.880348 <6>[ 1.039416] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10603 13:20:18.888560 <6>[ 1.047512] printk: console [ttyS0] disabled
10604 13:20:18.916137 <6>[ 1.072143] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10605 13:20:18.922851 <6>[ 1.081617] printk: console [ttyS0] enabled
10606 13:20:18.926180 <6>[ 1.081617] printk: console [ttyS0] enabled
10607 13:20:18.932722 <6>[ 1.090512] printk: bootconsole [mtk8250] disabled
10608 13:20:18.935951 <6>[ 1.090512] printk: bootconsole [mtk8250] disabled
10609 13:20:18.942902 <6>[ 1.101780] SuperH (H)SCI(F) driver initialized
10610 13:20:18.946138 <6>[ 1.107058] msm_serial: driver initialized
10611 13:20:18.960823 <6>[ 1.116098] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10612 13:20:18.970274 <6>[ 1.124647] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10613 13:20:18.976905 <6>[ 1.133189] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10614 13:20:18.986801 <6>[ 1.141817] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10615 13:20:18.997002 <6>[ 1.150523] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10616 13:20:19.003350 <6>[ 1.159244] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10617 13:20:19.013302 <6>[ 1.167786] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10618 13:20:19.019594 <6>[ 1.176593] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10619 13:20:19.030018 <6>[ 1.185136] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10620 13:20:19.041511 <6>[ 1.200726] loop: module loaded
10621 13:20:19.048023 <6>[ 1.206707] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10622 13:20:19.071166 <4>[ 1.230158] mtk-pmic-keys: Failed to locate of_node [id: -1]
10623 13:20:19.078061 <6>[ 1.237115] megasas: 07.719.03.00-rc1
10624 13:20:19.087770 <6>[ 1.246955] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10625 13:20:19.097765 <6>[ 1.256444] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10626 13:20:19.114420 <6>[ 1.273074] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10627 13:20:19.174979 <6>[ 1.327174] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10628 13:20:19.428693 <6>[ 1.587958] Freeing initrd memory: 18280K
10629 13:20:19.440408 <6>[ 1.599578] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10630 13:20:19.451448 <6>[ 1.610646] tun: Universal TUN/TAP device driver, 1.6
10631 13:20:19.455112 <6>[ 1.616729] thunder_xcv, ver 1.0
10632 13:20:19.458284 <6>[ 1.620235] thunder_bgx, ver 1.0
10633 13:20:19.461493 <6>[ 1.623733] nicpf, ver 1.0
10634 13:20:19.471696 <6>[ 1.627777] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10635 13:20:19.475478 <6>[ 1.635254] hns3: Copyright (c) 2017 Huawei Corporation.
10636 13:20:19.481688 <6>[ 1.640842] hclge is initializing
10637 13:20:19.485583 <6>[ 1.644422] e1000: Intel(R) PRO/1000 Network Driver
10638 13:20:19.491983 <6>[ 1.649551] e1000: Copyright (c) 1999-2006 Intel Corporation.
10639 13:20:19.495156 <6>[ 1.655567] e1000e: Intel(R) PRO/1000 Network Driver
10640 13:20:19.501518 <6>[ 1.660783] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10641 13:20:19.508527 <6>[ 1.666969] igb: Intel(R) Gigabit Ethernet Network Driver
10642 13:20:19.514848 <6>[ 1.672619] igb: Copyright (c) 2007-2014 Intel Corporation.
10643 13:20:19.521489 <6>[ 1.678456] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10644 13:20:19.528601 <6>[ 1.684973] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10645 13:20:19.531785 <6>[ 1.691438] sky2: driver version 1.30
10646 13:20:19.538174 <6>[ 1.696369] usbcore: registered new device driver r8152-cfgselector
10647 13:20:19.545002 <6>[ 1.702905] usbcore: registered new interface driver r8152
10648 13:20:19.551727 <6>[ 1.708732] VFIO - User Level meta-driver version: 0.3
10649 13:20:19.557780 <6>[ 1.716963] usbcore: registered new interface driver usb-storage
10650 13:20:19.564389 <6>[ 1.723418] usbcore: registered new device driver onboard-usb-hub
10651 13:20:19.573503 <6>[ 1.732599] mt6397-rtc mt6359-rtc: registered as rtc0
10652 13:20:19.583223 <6>[ 1.738067] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-18T13:20:19 UTC (1721308819)
10653 13:20:19.586955 <6>[ 1.747641] i2c_dev: i2c /dev entries driver
10654 13:20:19.600962 <4>[ 1.759717] cpu cpu0: supply cpu not found, using dummy regulator
10655 13:20:19.607032 <4>[ 1.766148] cpu cpu1: supply cpu not found, using dummy regulator
10656 13:20:19.614067 <4>[ 1.772551] cpu cpu2: supply cpu not found, using dummy regulator
10657 13:20:19.620576 <4>[ 1.778957] cpu cpu3: supply cpu not found, using dummy regulator
10658 13:20:19.627186 <4>[ 1.785389] cpu cpu4: supply cpu not found, using dummy regulator
10659 13:20:19.633712 <4>[ 1.791797] cpu cpu5: supply cpu not found, using dummy regulator
10660 13:20:19.640191 <4>[ 1.798196] cpu cpu6: supply cpu not found, using dummy regulator
10661 13:20:19.647131 <4>[ 1.804591] cpu cpu7: supply cpu not found, using dummy regulator
10662 13:20:19.666433 <6>[ 1.825233] cpu cpu0: EM: created perf domain
10663 13:20:19.669675 <6>[ 1.830163] cpu cpu4: EM: created perf domain
10664 13:20:19.676940 <6>[ 1.835807] sdhci: Secure Digital Host Controller Interface driver
10665 13:20:19.683129 <6>[ 1.842240] sdhci: Copyright(c) Pierre Ossman
10666 13:20:19.690053 <6>[ 1.847198] Synopsys Designware Multimedia Card Interface Driver
10667 13:20:19.696534 <6>[ 1.853836] sdhci-pltfm: SDHCI platform and OF driver helper
10668 13:20:19.699771 <6>[ 1.853877] mmc0: CQHCI version 5.10
10669 13:20:19.706779 <6>[ 1.864150] ledtrig-cpu: registered to indicate activity on CPUs
10670 13:20:19.713066 <6>[ 1.870974] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10671 13:20:19.720118 <6>[ 1.878028] usbcore: registered new interface driver usbhid
10672 13:20:19.723275 <6>[ 1.883849] usbhid: USB HID core driver
10673 13:20:19.729775 <6>[ 1.888059] spi_master spi0: will run message pump with realtime priority
10674 13:20:19.780212 <6>[ 1.932329] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10675 13:20:19.800175 <6>[ 1.948971] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10676 13:20:19.803238 <6>[ 1.960934] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15014
10677 13:20:19.810563 <6>[ 1.964189] cros-ec-spi spi0.0: Chrome EC device registered
10678 13:20:19.813926 <6>[ 1.974435] mmc0: Command Queue Engine enabled
10679 13:20:19.820012 <6>[ 1.979212] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10680 13:20:19.827694 <6>[ 1.986488] mmcblk0: mmc0:0001 DA4128 116 GiB
10681 13:20:19.837354 <6>[ 1.988909] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10682 13:20:19.841012 <6>[ 1.995264] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10683 13:20:19.847372 <6>[ 2.001717] NET: Registered PF_PACKET protocol family
10684 13:20:19.854283 <6>[ 2.007935] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10685 13:20:19.857379 <6>[ 2.011852] 9pnet: Installing 9P2000 support
10686 13:20:19.863847 <6>[ 2.017677] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10687 13:20:19.867005 <5>[ 2.021521] Key type dns_resolver registered
10688 13:20:19.873779 <6>[ 2.027245] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10689 13:20:19.877000 <6>[ 2.031922] registered taskstats version 1
10690 13:20:19.883924 <5>[ 2.042167] Loading compiled-in X.509 certificates
10691 13:20:19.910938 <4>[ 2.063549] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10692 13:20:19.920846 <4>[ 2.074242] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10693 13:20:19.934996 <6>[ 2.094134] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10694 13:20:19.941970 <6>[ 2.100945] xhci-mtk 11200000.usb: xHCI Host Controller
10695 13:20:19.948337 <6>[ 2.106458] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10696 13:20:19.958692 <6>[ 2.114319] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10697 13:20:19.964944 <6>[ 2.123755] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10698 13:20:19.971973 <6>[ 2.129981] xhci-mtk 11200000.usb: xHCI Host Controller
10699 13:20:19.978279 <6>[ 2.135491] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10700 13:20:19.984943 <6>[ 2.143154] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10701 13:20:19.991900 <6>[ 2.151017] hub 1-0:1.0: USB hub found
10702 13:20:19.995131 <6>[ 2.155041] hub 1-0:1.0: 1 port detected
10703 13:20:20.002253 <6>[ 2.159327] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10704 13:20:20.008739 <6>[ 2.168084] hub 2-0:1.0: USB hub found
10705 13:20:20.012007 <6>[ 2.172105] hub 2-0:1.0: 1 port detected
10706 13:20:20.020995 <6>[ 2.179847] mtk-msdc 11f70000.mmc: Got CD GPIO
10707 13:20:20.039330 <6>[ 2.194856] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10708 13:20:20.049083 <6>[ 2.203263] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10709 13:20:20.055449 <6>[ 2.211603] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10710 13:20:20.065744 <6>[ 2.219945] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10711 13:20:20.072178 <6>[ 2.228285] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10712 13:20:20.082366 <6>[ 2.236624] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10713 13:20:20.088664 <6>[ 2.244963] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10714 13:20:20.098238 <6>[ 2.253302] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10715 13:20:20.105391 <6>[ 2.261641] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10716 13:20:20.115025 <6>[ 2.269982] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10717 13:20:20.122223 <6>[ 2.278333] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10718 13:20:20.131679 <6>[ 2.286672] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10719 13:20:20.138540 <6>[ 2.295010] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10720 13:20:20.148087 <6>[ 2.303349] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10721 13:20:20.154697 <6>[ 2.311688] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10722 13:20:20.161415 <6>[ 2.320384] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10723 13:20:20.168467 <6>[ 2.327567] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10724 13:20:20.174921 <6>[ 2.334338] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10725 13:20:20.185084 <6>[ 2.341123] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10726 13:20:20.191996 <6>[ 2.348099] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10727 13:20:20.198291 <6>[ 2.354946] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10728 13:20:20.208541 <6>[ 2.364083] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10729 13:20:20.218274 <6>[ 2.373204] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10730 13:20:20.228535 <6>[ 2.382498] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10731 13:20:20.238318 <6>[ 2.391965] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10732 13:20:20.248021 <6>[ 2.401432] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10733 13:20:20.254331 <6>[ 2.410552] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10734 13:20:20.264304 <6>[ 2.420019] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10735 13:20:20.274379 <6>[ 2.429139] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10736 13:20:20.284505 <6>[ 2.438438] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10737 13:20:20.294382 <6>[ 2.448599] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10738 13:20:20.304439 <6>[ 2.460607] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10739 13:20:20.312794 <6>[ 2.471765] Trying to probe devices needed for running init ...
10740 13:20:20.323193 <3>[ 2.479024] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10741 13:20:20.401701 <6>[ 2.557554] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10742 13:20:20.429093 <6>[ 2.588358] hub 2-1:1.0: USB hub found
10743 13:20:20.432313 <6>[ 2.592804] hub 2-1:1.0: 3 ports detected
10744 13:20:20.441695 <6>[ 2.601027] hub 2-1:1.0: USB hub found
10745 13:20:20.444860 <6>[ 2.605481] hub 2-1:1.0: 3 ports detected
10746 13:20:20.553124 <6>[ 2.709335] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10747 13:20:20.707885 <6>[ 2.867297] hub 1-1:1.0: USB hub found
10748 13:20:20.711099 <6>[ 2.871767] hub 1-1:1.0: 4 ports detected
10749 13:20:20.723825 <6>[ 2.882968] hub 1-1:1.0: USB hub found
10750 13:20:20.727098 <6>[ 2.887383] hub 1-1:1.0: 4 ports detected
10751 13:20:20.785350 <6>[ 2.941442] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10752 13:20:20.889871 <6>[ 3.045740] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10753 13:20:20.922218 <4>[ 3.077851] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10754 13:20:20.931804 <4>[ 3.086928] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10755 13:20:20.966572 <6>[ 3.125896] r8152 2-1.3:1.0 eth0: v1.12.13
10756 13:20:21.053493 <6>[ 3.209304] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10757 13:20:21.186438 <6>[ 3.345343] hub 1-1.4:1.0: USB hub found
10758 13:20:21.189681 <6>[ 3.350023] hub 1-1.4:1.0: 2 ports detected
10759 13:20:21.201095 <6>[ 3.360223] hub 1-1.4:1.0: USB hub found
10760 13:20:21.204231 <6>[ 3.364749] hub 1-1.4:1.0: 2 ports detected
10761 13:20:21.501393 <6>[ 3.657228] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10762 13:20:21.697503 <6>[ 3.853372] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10763 13:20:22.585524 <6>[ 4.745212] r8152 2-1.3:1.0 eth0: carrier on
10764 13:20:24.837833 <5>[ 4.765173] Sending DHCP requests .., OK
10765 13:20:24.844072 <6>[ 7.001570] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10766 13:20:24.847118 <6>[ 7.009864] IP-Config: Complete:
10767 13:20:24.860447 <6>[ 7.013357] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10768 13:20:24.867399 <6>[ 7.024063] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10769 13:20:24.877322 <6>[ 7.032677] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10770 13:20:24.880571 <6>[ 7.032686] nameserver0=192.168.201.1
10771 13:20:24.883588 <6>[ 7.044839] clk: Disabling unused clocks
10772 13:20:24.887329 <6>[ 7.050303] ALSA device list:
10773 13:20:24.893600 <6>[ 7.053562] No soundcards found.
10774 13:20:24.900303 <6>[ 7.058836] Freeing unused kernel memory: 8512K
10775 13:20:24.903439 <6>[ 7.063734] Run /init as init process
10776 13:20:24.911519 Loading, please wait...
10777 13:20:24.939933 Starting systemd-udevd version 252.22-1~deb12u1
10778 13:20:25.159541 <6>[ 7.316054] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10779 13:20:25.166073 <6>[ 7.324095] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10780 13:20:25.176000 <6>[ 7.324925] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10781 13:20:25.182809 <6>[ 7.331768] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10782 13:20:25.189157 <6>[ 7.334480] remoteproc remoteproc0: scp is available
10783 13:20:25.192363 <6>[ 7.334506] remoteproc remoteproc0: powering up scp
10784 13:20:25.202341 <6>[ 7.334509] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10785 13:20:25.209074 <6>[ 7.334518] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10786 13:20:25.212808 <6>[ 7.354059] mc: Linux media interface: v0.10
10787 13:20:25.219201 <3>[ 7.356505] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10788 13:20:25.229268 <3>[ 7.356512] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10789 13:20:25.235527 <3>[ 7.356517] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10790 13:20:25.245386 <3>[ 7.356563] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10791 13:20:25.252316 <3>[ 7.356567] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10792 13:20:25.261808 <3>[ 7.356570] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10793 13:20:25.269055 <3>[ 7.356574] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10794 13:20:25.278427 <3>[ 7.356578] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10795 13:20:25.285172 <3>[ 7.356601] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10796 13:20:25.295006 <3>[ 7.356621] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10797 13:20:25.301432 <3>[ 7.356624] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10798 13:20:25.307941 <3>[ 7.356627] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10799 13:20:25.318339 <3>[ 7.356652] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10800 13:20:25.324596 <3>[ 7.356655] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10801 13:20:25.334457 <3>[ 7.356658] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10802 13:20:25.340961 <3>[ 7.356662] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10803 13:20:25.351251 <3>[ 7.356665] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10804 13:20:25.357612 <3>[ 7.356684] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10805 13:20:25.367675 <6>[ 7.359287] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10806 13:20:25.374235 <6>[ 7.360952] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10807 13:20:25.384433 <6>[ 7.360957] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10808 13:20:25.391650 <4>[ 7.361111] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10809 13:20:25.401484 <6>[ 7.361740] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10810 13:20:25.407843 <6>[ 7.361744] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10811 13:20:25.414601 <6>[ 7.361861] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10812 13:20:25.424492 <6>[ 7.361869] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10813 13:20:25.430928 <6>[ 7.361873] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10814 13:20:25.440799 <6>[ 7.361878] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10815 13:20:25.447838 <6>[ 7.412079] videodev: Linux video capture interface: v2.00
10816 13:20:25.454216 <4>[ 7.416369] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10817 13:20:25.460538 <4>[ 7.418550] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10818 13:20:25.467744 <6>[ 7.422852] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10819 13:20:25.477120 <4>[ 7.447259] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10820 13:20:25.484089 <4>[ 7.447259] Fallback method does not support PEC.
10821 13:20:25.490506 <6>[ 7.459700] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10822 13:20:25.497009 <6>[ 7.459743] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10823 13:20:25.503367 <6>[ 7.459748] remoteproc remoteproc0: remote processor scp is now up
10824 13:20:25.510487 <6>[ 7.538528] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10825 13:20:25.520126 <6>[ 7.542592] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10826 13:20:25.527041 <6>[ 7.547692] pci_bus 0000:00: root bus resource [bus 00-ff]
10827 13:20:25.536484 <6>[ 7.548680] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10828 13:20:25.543087 <3>[ 7.554024] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10829 13:20:25.553325 <6>[ 7.557393] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10830 13:20:25.563138 <6>[ 7.561965] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10831 13:20:25.569637 <6>[ 7.564827] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10832 13:20:25.576657 <6>[ 7.566378] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10833 13:20:25.586268 <3>[ 7.578755] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10834 13:20:25.596423 <6>[ 7.580636] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10835 13:20:25.599674 <6>[ 7.612193] Bluetooth: Core ver 2.22
10836 13:20:25.606199 <6>[ 7.618512] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10837 13:20:25.612692 <6>[ 7.625747] NET: Registered PF_BLUETOOTH protocol family
10838 13:20:25.619179 <6>[ 7.633389] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10839 13:20:25.625616 <6>[ 7.647010] Bluetooth: HCI device and connection manager initialized
10840 13:20:25.632471 <6>[ 7.648031] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10841 13:20:25.645409 <6>[ 7.649088] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10842 13:20:25.651978 <6>[ 7.649235] usbcore: registered new interface driver uvcvideo
10843 13:20:25.655270 <6>[ 7.654102] pci 0000:00:00.0: supports D1 D2
10844 13:20:25.662068 <6>[ 7.662570] Bluetooth: HCI socket layer initialized
10845 13:20:25.665207 <6>[ 7.662573] Bluetooth: L2CAP socket layer initialized
10846 13:20:25.672196 <6>[ 7.662578] Bluetooth: SCO socket layer initialized
10847 13:20:25.678330 <6>[ 7.669020] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10848 13:20:25.685320 <6>[ 7.692123] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10849 13:20:25.691930 <6>[ 7.727267] usbcore: registered new interface driver btusb
10850 13:20:25.701791 <4>[ 7.728000] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10851 13:20:25.708162 <3>[ 7.728004] Bluetooth: hci0: Failed to load firmware file (-2)
10852 13:20:25.711364 <3>[ 7.728005] Bluetooth: hci0: Failed to set up firmware (-2)
10853 13:20:25.724803 <4>[ 7.728007] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10854 13:20:25.731159 <6>[ 7.734747] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10855 13:20:25.738199 <6>[ 7.896543] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10856 13:20:25.744437 <6>[ 7.902827] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10857 13:20:25.754576 <6>[ 7.910311] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10858 13:20:25.761263 <6>[ 7.917794] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10859 13:20:25.764212 <6>[ 7.925365] pci 0000:01:00.0: supports D1 D2
10860 13:20:25.771153 <6>[ 7.929884] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10861 13:20:25.793052 <6>[ 7.949161] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10862 13:20:25.799288 <6>[ 7.956049] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10863 13:20:25.806015 <6>[ 7.964131] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10864 13:20:25.815704 <6>[ 7.972129] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10865 13:20:25.822766 <6>[ 7.980131] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10866 13:20:25.832318 <6>[ 7.988132] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10867 13:20:25.835610 <6>[ 7.996132] pci 0000:00:00.0: PCI bridge to [bus 01]
10868 13:20:25.845704 <6>[ 8.001348] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10869 13:20:25.852471 <6>[ 8.009413] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10870 13:20:25.858878 <6>[ 8.016132] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10871 13:20:25.865256 <6>[ 8.022665] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10872 13:20:25.883757 <5>[ 8.040438] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10873 13:20:25.902838 <5>[ 8.059086] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10874 13:20:25.908893 <5>[ 8.066581] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10875 13:20:25.918901 <4>[ 8.075014] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10876 13:20:25.925357 <6>[ 8.083919] cfg80211: failed to load regulatory.db
10877 13:20:25.961576 <6>[ 8.117776] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10878 13:20:25.967993 <6>[ 8.125319] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10879 13:20:25.992184 <6>[ 8.152036] mt7921e 0000:01:00.0: ASIC revision: 79610010
10880 13:20:26.091635 <6>[ 8.247937] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10881 13:20:26.094752 <6>[ 8.247937]
10882 13:20:26.103030 Begin: Loading essential drivers ... done.
10883 13:20:26.106184 Begin: Running /scripts/init-premount ... done.
10884 13:20:26.112961 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10885 13:20:26.122628 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10886 13:20:26.125761 Device /sys/class/net/eth0 found
10887 13:20:26.125868 done.
10888 13:20:26.132435 Begin: Waiting up to 180 secs for any network device to become available ... done.
10889 13:20:26.169032 IP-Config: eth0 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10890 13:20:26.176000 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10891 13:20:26.182437 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10892 13:20:26.189055 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10893 13:20:26.195347 host : mt8192-asurada-spherion-r0-cbg-9
10894 13:20:26.202076 domain : lava-rack
10895 13:20:26.205184 rootserver: 192.168.201.1 rootpath:
10896 13:20:26.205277 filename :
10897 13:20:26.219223 done.
10898 13:20:26.226433 Begin: Running /scripts/nfs-bottom ... done.
10899 13:20:26.237719 Begin: Running /scripts/init-bottom ... done.
10900 13:20:26.358285 <6>[ 8.514663] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10901 13:20:27.637124 <6>[ 9.797436] NET: Registered PF_INET6 protocol family
10902 13:20:27.645060 <6>[ 9.804841] Segment Routing with IPv6
10903 13:20:27.648171 <6>[ 9.808841] In-situ OAM (IOAM) with IPv6
10904 13:20:27.822067 <30>[ 9.952858] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10905 13:20:27.825269 <30>[ 9.986047] systemd[1]: Detected architecture arm64.
10906 13:20:27.834789
10907 13:20:27.837873 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10908 13:20:27.837966
10909 13:20:27.867123 <30>[ 10.027143] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10910 13:20:28.934403 <30>[ 11.091082] systemd[1]: Queued start job for default target graphical.target.
10911 13:20:28.977873 <30>[ 11.134630] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10912 13:20:28.984291 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10913 13:20:29.006499 <30>[ 11.163103] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10914 13:20:29.015990 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10915 13:20:29.034077 <30>[ 11.191077] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10916 13:20:29.043903 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10917 13:20:29.062694 <30>[ 11.219410] systemd[1]: Created slice user.slice - User and Session Slice.
10918 13:20:29.069059 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10919 13:20:29.092654 <30>[ 11.246115] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10920 13:20:29.102385 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10921 13:20:29.119880 <30>[ 11.273594] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10922 13:20:29.126305 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10923 13:20:29.154935 <30>[ 11.301919] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10924 13:20:29.164724 <30>[ 11.321799] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10925 13:20:29.171185 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10926 13:20:29.188617 <30>[ 11.345354] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10927 13:20:29.194997 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10928 13:20:29.212246 <30>[ 11.369270] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10929 13:20:29.221892 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10930 13:20:29.237463 <30>[ 11.397460] systemd[1]: Reached target paths.target - Path Units.
10931 13:20:29.247088 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10932 13:20:29.265000 <30>[ 11.421707] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10933 13:20:29.271186 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10934 13:20:29.284860 <30>[ 11.445354] systemd[1]: Reached target slices.target - Slice Units.
10935 13:20:29.295265 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10936 13:20:29.309402 <30>[ 11.469732] systemd[1]: Reached target swap.target - Swaps.
10937 13:20:29.315831 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10938 13:20:29.336263 <30>[ 11.493416] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10939 13:20:29.346038 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10940 13:20:29.365246 <30>[ 11.522185] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10941 13:20:29.374792 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10942 13:20:29.396098 <30>[ 11.552892] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10943 13:20:29.405929 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10944 13:20:29.421922 <30>[ 11.578870] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10945 13:20:29.431567 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10946 13:20:29.449267 <30>[ 11.606022] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10947 13:20:29.455818 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10948 13:20:29.473650 <30>[ 11.630845] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10949 13:20:29.483539 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10950 13:20:29.503583 <30>[ 11.660294] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10951 13:20:29.513131 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10952 13:20:29.528753 <30>[ 11.685852] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10953 13:20:29.538891 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10954 13:20:29.592747 <30>[ 11.749589] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10955 13:20:29.599041 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10956 13:20:29.621030 <30>[ 11.778072] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10957 13:20:29.627749 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10958 13:20:29.652831 <30>[ 11.809926] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10959 13:20:29.659332 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10960 13:20:29.687308 <30>[ 11.837846] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10961 13:20:29.736965 <30>[ 11.893985] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10962 13:20:29.746669 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10963 13:20:29.769729 <30>[ 11.926747] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10964 13:20:29.776065 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10965 13:20:29.800761 <30>[ 11.957501] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10966 13:20:29.807206 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10967 13:20:29.834618 <30>[ 11.991393] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10968 13:20:29.847377 Starting [0;1;39mmodprobe@drm.service[0m - Load Kerne<6>[ 12.003928] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10969 13:20:29.851046 l Module drm...
10970 13:20:29.900974 <30>[ 12.058022] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10971 13:20:29.910868 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10972 13:20:29.930791 <30>[ 12.088071] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10973 13:20:29.937840 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10974 13:20:29.960255 <30>[ 12.117480] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10975 13:20:29.967060 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10976 13:20:29.985341 <6>[ 12.145467] fuse: init (API version 7.37)
10977 13:20:29.996421 <30>[ 12.153393] systemd[1]: Starting systemd-journald.service - Journal Service...
10978 13:20:30.002833 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10979 13:20:30.056809 <30>[ 12.213919] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10980 13:20:30.063195 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10981 13:20:30.093470 <30>[ 12.246839] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10982 13:20:30.099950 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10983 13:20:30.125804 <30>[ 12.282662] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10984 13:20:30.139316 Starting [0;1;39msystemd-remount-f…n<3>[ 12.295413] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10985 13:20:30.142554 t Root and Kernel File Systems...
10986 13:20:30.163293 <30>[ 12.320273] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10987 13:20:30.173358 <3>[ 12.326376] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10988 13:20:30.179719 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10989 13:20:30.200911 <30>[ 12.358075] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10990 13:20:30.207356 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10991 13:20:30.220650 <3>[ 12.377661] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10992 13:20:30.230301 <30>[ 12.387028] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10993 13:20:30.237567 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10994 13:20:30.250530 <3>[ 12.407717] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10995 13:20:30.260604 <30>[ 12.417332] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10996 13:20:30.266952 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10997 13:20:30.283177 <3>[ 12.440227] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10998 13:20:30.293124 <30>[ 12.450330] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10999 13:20:30.303323 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
11000 13:20:30.314907 <3>[ 12.472237] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11001 13:20:30.326224 <30>[ 12.483559] systemd[1]: modprobe@configfs.service: Deactivated successfully.
11002 13:20:30.333351 <30>[ 12.491800] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
11003 13:20:30.346928 [[0;32m OK [0m] Finished [0<3>[ 12.503200] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11004 13:20:30.353814 ;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
11005 13:20:30.369726 <30>[ 12.526287] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
11006 13:20:30.376776 <30>[ 12.534029] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
11007 13:20:30.386590 <3>[ 12.536872] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11008 13:20:30.393235 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
11009 13:20:30.414225 <30>[ 12.571058] systemd[1]: modprobe@drm.service: Deactivated successfully.
11010 13:20:30.420796 <3>[ 12.572293] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11011 13:20:30.430875 <30>[ 12.578938] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
11012 13:20:30.437172 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
11013 13:20:30.451952 <3>[ 12.608808] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11014 13:20:30.462411 <30>[ 12.619619] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
11015 13:20:30.473222 <30>[ 12.628453] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11016 13:20:30.486129 [[0;32m OK [0m] Finished [0;1;39mmodprobe@e<3>[ 12.640621] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11017 13:20:30.489246 fi_psto…m - Load Kernel Module efi_pstore.
11018 13:20:30.507109 <30>[ 12.667057] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11019 13:20:30.517359 <3>[ 12.672432] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11020 13:20:30.523990 <30>[ 12.675085] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11021 13:20:30.533939 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11022 13:20:30.549797 <3>[ 12.707082] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11023 13:20:30.560611 <30>[ 12.717847] systemd[1]: modprobe@loop.service: Deactivated successfully.
11024 13:20:30.567335 <30>[ 12.725828] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
11025 13:20:30.583882 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Mo<3>[ 12.740506] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11026 13:20:30.583994 dule loop.
11027 13:20:30.606203 <30>[ 12.762866] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
11028 13:20:30.619567 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…servic<3>[ 12.776396] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11029 13:20:30.629683 <3>[ 12.777477] power_supply sbs-5-000b: driver failed to report `voltage_now' property: -6
11030 13:20:30.642781 <4>[ 12.785620] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11031 13:20:30.652527 <3>[ 12.785624] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11032 13:20:30.655726 e[0m - Load Kernel Modules.
11033 13:20:30.677777 <30>[ 12.830893] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
11034 13:20:30.684680 <3>[ 12.840193] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11035 13:20:30.694381 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11036 13:20:30.714073 <30>[ 12.870699] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
11037 13:20:30.724241 <3>[ 12.876103] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11038 13:20:30.730554 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11039 13:20:30.749907 <30>[ 12.906719] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
11040 13:20:30.759375 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11041 13:20:30.777837 <30>[ 12.934666] systemd[1]: Reached target network-pre.target - Preparation for Network.
11042 13:20:30.784027 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11043 13:20:30.848897 <30>[ 13.005709] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
11044 13:20:30.855055 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11045 13:20:30.880612 <30>[ 13.038054] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
11046 13:20:30.890838 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11047 13:20:30.911747 <30>[ 13.065563] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
11048 13:20:30.928839 <30>[ 13.079232] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
11049 13:20:30.972603 <30>[ 13.129958] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
11050 13:20:30.979628 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11051 13:20:31.010567 <30>[ 13.164095] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
11052 13:20:31.021912 <30>[ 13.179154] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
11053 13:20:31.028282 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11054 13:20:31.053641 <30>[ 13.210681] systemd[1]: Starting systemd-sysusers.service - Create System Users...
11055 13:20:31.060018 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11056 13:20:31.090649 <30>[ 13.247730] systemd[1]: Started systemd-journald.service - Journal Service.
11057 13:20:31.096990 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11058 13:20:31.120976 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11059 13:20:31.141151 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11060 13:20:31.162244 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11061 13:20:31.181540 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11062 13:20:31.202013 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11063 13:20:31.249022 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11064 13:20:31.269540 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11065 13:20:31.329291 <46>[ 13.486299] systemd-journald[301]: Received client request to flush runtime journal.
11066 13:20:31.364372 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11067 13:20:31.380813 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11068 13:20:31.396707 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11069 13:20:32.112987 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11070 13:20:32.742510 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11071 13:20:32.792696 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11072 13:20:32.872334 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11073 13:20:32.924609 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11074 13:20:32.977439 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11075 13:20:33.112393 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11076 13:20:33.172411 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11077 13:20:33.269638 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11078 13:20:33.288996 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11079 13:20:33.336776 <6>[ 15.497427] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11080 13:20:33.356738 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11081 13:20:33.382043 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11082 13:20:33.491600 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11083 13:20:33.604520 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11084 13:20:33.621573 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11085 13:20:33.685817 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11086 13:20:33.732613 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11087 13:20:33.750096 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11088 13:20:33.790753 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11089 13:20:33.896004 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11090 13:20:33.916239 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11091 13:20:33.936420 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11092 13:20:33.952229 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11093 13:20:33.977244 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11094 13:20:33.999301 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11095 13:20:34.016593 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11096 13:20:34.035348 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11097 13:20:34.055568 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11098 13:20:34.071894 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11099 13:20:34.089037 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11100 13:20:34.107816 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11101 13:20:34.124576 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11102 13:20:34.168964 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11103 13:20:34.204895 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11104 13:20:34.249778 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11105 13:20:34.273632 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11106 13:20:34.356304 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11107 13:20:34.400650 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11108 13:20:34.425861 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11109 13:20:34.448921 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11110 13:20:34.580410 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11111 13:20:34.616425 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11112 13:20:34.634690 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11113 13:20:34.657718 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11114 13:20:34.676200 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11115 13:20:34.730869 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11116 13:20:34.772340 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11117 13:20:34.826217
11118 13:20:34.829418 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11119 13:20:34.829497
11120 13:20:34.832580 debian-bookworm-arm64 login: root (automatic login)
11121 13:20:34.832700
11122 13:20:35.129189 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024 aarch64
11123 13:20:35.129315
11124 13:20:35.135630 The programs included with the Debian GNU/Linux system are free software;
11125 13:20:35.142702 the exact distribution terms for each program are described in the
11126 13:20:35.145775 individual files in /usr/share/doc/*/copyright.
11127 13:20:35.145851
11128 13:20:35.152065 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11129 13:20:35.155651 permitted by applicable law.
11130 13:20:36.142222 Matched prompt #10: / #
11132 13:20:36.142469 Setting prompt string to ['/ #']
11133 13:20:36.142559 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11135 13:20:36.142737 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11136 13:20:36.142820 start: 2.2.6 expect-shell-connection (timeout 00:03:18) [common]
11137 13:20:36.142881 Setting prompt string to ['/ #']
11138 13:20:36.142936 Forcing a shell prompt, looking for ['/ #']
11139 13:20:36.142990 Sending line: ''
11141 13:20:36.193322 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11142 13:20:36.193394 Waiting using forced prompt support (timeout 00:02:30)
11143 13:20:36.198156 / #
11144 13:20:36.198427 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11145 13:20:36.198518 start: 2.2.7 export-device-env (timeout 00:03:18) [common]
11146 13:20:36.198596 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14879048/extract-nfsrootfs-brtvvc40'"
11148 13:20:36.304100 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14879048/extract-nfsrootfs-brtvvc40'
11149 13:20:36.304354 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
11151 13:20:36.410142 / # export NFS_SERVER_IP='192.168.201.1'
11152 13:20:36.410449 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11153 13:20:36.410556 end: 2.2 depthcharge-retry (duration 00:01:42) [common]
11154 13:20:36.410645 end: 2 depthcharge-action (duration 00:01:42) [common]
11155 13:20:36.410728 start: 3 lava-test-retry (timeout 00:07:36) [common]
11156 13:20:36.410807 start: 3.1 lava-test-shell (timeout 00:07:36) [common]
11157 13:20:36.410874 Using namespace: common
11158 13:20:36.410941 Sending line: '#'
11160 13:20:36.511406 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11161 13:20:36.516628 / # #
11162 13:20:36.516918 Using /lava-14879048
11163 13:20:36.516985 Sending line: 'export SHELL=/bin/bash'
11165 13:20:36.622078 / # export SHELL=/bin/bash
11166 13:20:36.622423 Sending line: '. /lava-14879048/environment'
11168 13:20:36.727714 / # . /lava-14879048/environment
11169 13:20:36.733081 Sending line: '/lava-14879048/bin/lava-test-runner /lava-14879048/0'
11171 13:20:36.833568 Test shell timeout: 10s (minimum of the action and connection timeout)
11172 13:20:36.837904 / # /lava-14879048/bin/lava-test-runner /lava-14879048/0
11173 13:20:37.083253 + export TESTRUN_ID=0_timesync-off
11174 13:20:37.086583 + TESTRUN_ID=0_timesync-off
11175 13:20:37.090282 + cd /lava-14879048/0/tests/0_timesync-off
11176 13:20:37.093384 ++ cat uuid
11177 13:20:37.096330 + UUID=14879048_1.6.2.3.1
11178 13:20:37.096409 + set +x
11179 13:20:37.103002 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14879048_1.6.2.3.1>
11180 13:20:37.103285 Received signal: <STARTRUN> 0_timesync-off 14879048_1.6.2.3.1
11181 13:20:37.103390 Starting test lava.0_timesync-off (14879048_1.6.2.3.1)
11182 13:20:37.103494 Skipping test definition patterns.
11183 13:20:37.106169 + systemctl stop systemd-timesyncd
11184 13:20:37.165709 + set +x
11185 13:20:37.169323 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14879048_1.6.2.3.1>
11186 13:20:37.169582 Received signal: <ENDRUN> 0_timesync-off 14879048_1.6.2.3.1
11187 13:20:37.169658 Ending use of test pattern.
11188 13:20:37.169716 Ending test lava.0_timesync-off (14879048_1.6.2.3.1), duration 0.07
11190 13:20:37.243133 + export TESTRUN_ID=1_kselftest-tpm2
11191 13:20:37.246256 + TESTRUN_ID=1_kselftest-tpm2
11192 13:20:37.252640 + cd /lava-14879048/0/tests/1_kselftest-tpm2
11193 13:20:37.252737 ++ cat uuid
11194 13:20:37.256370 + UUID=14879048_1.6.2.3.5
11195 13:20:37.256444 + set +x
11196 13:20:37.262619 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 14879048_1.6.2.3.5>
11197 13:20:37.262874 Received signal: <STARTRUN> 1_kselftest-tpm2 14879048_1.6.2.3.5
11198 13:20:37.262991 Starting test lava.1_kselftest-tpm2 (14879048_1.6.2.3.5)
11199 13:20:37.263075 Skipping test definition patterns.
11200 13:20:37.266293 + cd ./automated/linux/kselftest/
11201 13:20:37.292184 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
11202 13:20:37.329234 INFO: install_deps skipped
11203 13:20:37.833284 --2024-07-18 13:20:37-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz
11204 13:20:37.840336 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11205 13:20:37.969446 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11206 13:20:38.101186 HTTP request sent, awaiting response... 200 OK
11207 13:20:38.104254 Length: 1919140 (1.8M) [application/octet-stream]
11208 13:20:38.107377 Saving to: 'kselftest_armhf.tar.gz'
11209 13:20:38.107504
11210 13:20:38.107578
11211 13:20:38.360875 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11212 13:20:38.619112 kselftest_armhf.tar 2%[ ] 47.81K 184KB/s
11213 13:20:38.957244 kselftest_armhf.tar 11%[=> ] 217.50K 420KB/s
11214 13:20:39.329006 kselftest_armhf.tar 44%[=======> ] 834.03K 975KB/s
11215 13:20:39.335847 kselftest_armhf.tar 76%[==============> ] 1.40M 1.14MB/s
11216 13:20:39.342259 kselftest_armhf.tar 100%[===================>] 1.83M 1.49MB/s in 1.2s
11217 13:20:39.342358
11218 13:20:39.507718 2024-07-18 13:20:39 (1.49 MB/s) - 'kselftest_armhf.tar.gz' saved [1919140/1919140]
11219 13:20:39.507848
11220 13:20:46.621483 skiplist:
11221 13:20:46.624540 ========================================
11222 13:20:46.627674 ========================================
11223 13:20:46.676238 tpm2:test_smoke.sh
11224 13:20:46.679948 tpm2:test_space.sh
11225 13:20:46.696985 ============== Tests to run ===============
11226 13:20:46.697093 tpm2:test_smoke.sh
11227 13:20:46.700084 tpm2:test_space.sh
11228 13:20:46.703207 ===========End Tests to run ===============
11229 13:20:46.706256 shardfile-tpm2 pass
11230 13:20:46.810097 <12>[ 28.972461] kselftest: Running tests in tpm2
11231 13:20:46.818888 TAP version 13
11232 13:20:46.831910 1..2
11233 13:20:46.861149 # selftests: tpm2: test_smoke.sh
11234 13:20:48.675252 # test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite) ... ERROR
11235 13:20:48.682160 # test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp) ... ERROR
11236 13:20:48.688413 # Exception ignored in: <function Client.__del__ at 0xffff9c46ccc0>
11237 13:20:48.692136 # Traceback (most recent call last):
11238 13:20:48.701533 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11239 13:20:48.701621 # if self.tpm:
11240 13:20:48.705222 # ^^^^^^^^
11241 13:20:48.708402 # AttributeError: 'Client' object has no attribute 'tpm'
11242 13:20:48.714903 # test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth) ... ERROR
11243 13:20:48.721157 # Exception ignored in: <function Client.__del__ at 0xffff9c46ccc0>
11244 13:20:48.725003 # Traceback (most recent call last):
11245 13:20:48.734802 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11246 13:20:48.734902 # if self.tpm:
11247 13:20:48.737925 # ^^^^^^^^
11248 13:20:48.741141 # AttributeError: 'Client' object has no attribute 'tpm'
11249 13:20:48.750989 # test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy) ... ERROR
11250 13:20:48.754797 # Exception ignored in: <function Client.__del__ at 0xffff9c46ccc0>
11251 13:20:48.757750 # Traceback (most recent call last):
11252 13:20:48.767566 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11253 13:20:48.771180 # if self.tpm:
11254 13:20:48.771274 # ^^^^^^^^
11255 13:20:48.777995 # AttributeError: 'Client' object has no attribute 'tpm'
11256 13:20:48.784283 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth) ... ERROR
11257 13:20:48.791102 # Exception ignored in: <function Client.__del__ at 0xffff9c46ccc0>
11258 13:20:48.794010 # Traceback (most recent call last):
11259 13:20:48.804211 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11260 13:20:48.807800 # if self.tpm:
11261 13:20:48.807876 # ^^^^^^^^
11262 13:20:48.814111 # AttributeError: 'Client' object has no attribute 'tpm'
11263 13:20:48.820524 # test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds) ... ERROR
11264 13:20:48.824244 # Exception ignored in: <function Client.__del__ at 0xffff9c46ccc0>
11265 13:20:48.827342 # Traceback (most recent call last):
11266 13:20:48.837436 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11267 13:20:48.840925 # if self.tpm:
11268 13:20:48.840992 # ^^^^^^^^
11269 13:20:48.847574 # AttributeError: 'Client' object has no attribute 'tpm'
11270 13:20:48.854284 # test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd) ... ERROR
11271 13:20:48.860618 # Exception ignored in: <function Client.__del__ at 0xffff9c46ccc0>
11272 13:20:48.863623 # Traceback (most recent call last):
11273 13:20:48.873741 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11274 13:20:48.873823 # if self.tpm:
11275 13:20:48.877239 # ^^^^^^^^
11276 13:20:48.880783 # AttributeError: 'Client' object has no attribute 'tpm'
11277 13:20:48.886927 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth) ... ERROR
11278 13:20:48.893997 # Exception ignored in: <function Client.__del__ at 0xffff9c46ccc0>
11279 13:20:48.897133 # Traceback (most recent call last):
11280 13:20:48.907007 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11281 13:20:48.910609 # if self.tpm:
11282 13:20:48.910686 # ^^^^^^^^
11283 13:20:48.917405 # AttributeError: 'Client' object has no attribute 'tpm'
11284 13:20:48.923336 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy) ... ERROR
11285 13:20:48.930447 # Exception ignored in: <function Client.__del__ at 0xffff9c46ccc0>
11286 13:20:48.933683 # Traceback (most recent call last):
11287 13:20:48.943229 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11288 13:20:48.946945 # if self.tpm:
11289 13:20:48.947047 # ^^^^^^^^
11290 13:20:48.953212 # AttributeError: 'Client' object has no attribute 'tpm'
11291 13:20:48.953314 #
11292 13:20:48.960373 # ======================================================================
11293 13:20:48.966440 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite)
11294 13:20:48.973374 # ----------------------------------------------------------------------
11295 13:20:48.976381 # Traceback (most recent call last):
11296 13:20:48.986699 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11297 13:20:48.990249 # self.root_key = self.client.create_root_key()
11298 13:20:48.997010 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11299 13:20:49.006820 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11300 13:20:49.010598 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11301 13:20:49.016891 # ^^^^^^^^^^^^^^^^^^
11302 13:20:49.027287 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11303 13:20:49.030632 # raise ProtocolError(cc, rc)
11304 13:20:49.033646 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11305 13:20:49.036756 #
11306 13:20:49.043785 # ======================================================================
11307 13:20:49.050184 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp)
11308 13:20:49.053922 # ----------------------------------------------------------------------
11309 13:20:49.057138 # Traceback (most recent call last):
11310 13:20:49.070312 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11311 13:20:49.070466 # self.client = tpm2.Client()
11312 13:20:49.073178 # ^^^^^^^^^^^^^
11313 13:20:49.083220 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11314 13:20:49.090022 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11315 13:20:49.093657 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11316 13:20:49.100027 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11317 13:20:49.100480 #
11318 13:20:49.106872 # ======================================================================
11319 13:20:49.113095 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth)
11320 13:20:49.120225 # ----------------------------------------------------------------------
11321 13:20:49.123366 # Traceback (most recent call last):
11322 13:20:49.133494 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11323 13:20:49.136569 # self.client = tpm2.Client()
11324 13:20:49.140094 # ^^^^^^^^^^^^^
11325 13:20:49.149625 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11326 13:20:49.153338 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11327 13:20:49.159906 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11328 13:20:49.162993 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11329 13:20:49.163464 #
11330 13:20:49.169445 # ======================================================================
11331 13:20:49.176436 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy)
11332 13:20:49.182862 # ----------------------------------------------------------------------
11333 13:20:49.186107 # Traceback (most recent call last):
11334 13:20:49.195903 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11335 13:20:49.199589 # self.client = tpm2.Client()
11336 13:20:49.202559 # ^^^^^^^^^^^^^
11337 13:20:49.212542 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11338 13:20:49.219029 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11339 13:20:49.222857 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11340 13:20:49.229095 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11341 13:20:49.229614 #
11342 13:20:49.235979 # ======================================================================
11343 13:20:49.242511 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth)
11344 13:20:49.249088 # ----------------------------------------------------------------------
11345 13:20:49.252365 # Traceback (most recent call last):
11346 13:20:49.262286 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11347 13:20:49.265513 # self.client = tpm2.Client()
11348 13:20:49.269123 # ^^^^^^^^^^^^^
11349 13:20:49.278765 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11350 13:20:49.281897 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11351 13:20:49.288395 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11352 13:20:49.292280 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11353 13:20:49.292680 #
11354 13:20:49.298833 # ======================================================================
11355 13:20:49.305439 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds)
11356 13:20:49.312476 # ----------------------------------------------------------------------
11357 13:20:49.316210 # Traceback (most recent call last):
11358 13:20:49.326074 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11359 13:20:49.332359 # self.client = tpm2.Client()
11360 13:20:49.332641 # ^^^^^^^^^^^^^
11361 13:20:49.343047 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11362 13:20:49.348079 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11363 13:20:49.351548 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11364 13:20:49.355095 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11365 13:20:49.358854 #
11366 13:20:49.363504 # ======================================================================
11367 13:20:49.370315 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd)
11368 13:20:49.377301 # ----------------------------------------------------------------------
11369 13:20:49.380523 # Traceback (most recent call last):
11370 13:20:49.390380 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11371 13:20:49.393898 # self.client = tpm2.Client()
11372 13:20:49.396946 # ^^^^^^^^^^^^^
11373 13:20:49.403727 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11374 13:20:49.410523 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11375 13:20:49.413444 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11376 13:20:49.420177 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11377 13:20:49.420529 #
11378 13:20:49.427016 # ======================================================================
11379 13:20:49.433334 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth)
11380 13:20:49.440029 # ----------------------------------------------------------------------
11381 13:20:49.443250 # Traceback (most recent call last):
11382 13:20:49.453151 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11383 13:20:49.457007 # self.client = tpm2.Client()
11384 13:20:49.459922 # ^^^^^^^^^^^^^
11385 13:20:49.469682 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11386 13:20:49.476187 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11387 13:20:49.480168 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11388 13:20:49.486400 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11389 13:20:49.486773 #
11390 13:20:49.492891 # ======================================================================
11391 13:20:49.499364 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy)
11392 13:20:49.506349 # ----------------------------------------------------------------------
11393 13:20:49.509446 # Traceback (most recent call last):
11394 13:20:49.519562 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11395 13:20:49.522947 # self.client = tpm2.Client()
11396 13:20:49.525814 # ^^^^^^^^^^^^^
11397 13:20:49.535812 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11398 13:20:49.542452 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11399 13:20:49.545853 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11400 13:20:49.552636 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11401 13:20:49.553072 #
11402 13:20:49.558904 # ----------------------------------------------------------------------
11403 13:20:49.559291 # Ran 9 tests in 0.057s
11404 13:20:49.559635 #
11405 13:20:49.562115 # FAILED (errors=9)
11406 13:20:49.565859 # test_async (tpm2_tests.AsyncTest.test_async) ... ok
11407 13:20:49.575490 # test_flush_invalid_context (tpm2_tests.AsyncTest.test_flush_invalid_context) ... ok
11408 13:20:49.575877 #
11409 13:20:49.582352 # ----------------------------------------------------------------------
11410 13:20:49.582734 # Ran 2 tests in 0.032s
11411 13:20:49.583029 #
11412 13:20:49.585523 # OK
11413 13:20:49.588630 ok 1 selftests: tpm2: test_smoke.sh
11414 13:20:49.589016 # selftests: tpm2: test_space.sh
11415 13:20:49.595464 # test_flush_context (tpm2_tests.SpaceTest.test_flush_context) ... ERROR
11416 13:20:49.602061 # test_get_handles (tpm2_tests.SpaceTest.test_get_handles) ... ERROR
11417 13:20:49.608381 # test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc) ... ERROR
11418 13:20:49.615177 # test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces) ... ERROR
11419 13:20:49.615610 #
11420 13:20:49.621961 # ======================================================================
11421 13:20:49.628454 # ERROR: test_flush_context (tpm2_tests.SpaceTest.test_flush_context)
11422 13:20:49.634689 # ----------------------------------------------------------------------
11423 13:20:49.638152 # Traceback (most recent call last):
11424 13:20:49.648101 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11425 13:20:49.651542 # root1 = space1.create_root_key()
11426 13:20:49.654664 # ^^^^^^^^^^^^^^^^^^^^^^^^
11427 13:20:49.667984 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11428 13:20:49.671746 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11429 13:20:49.677937 # ^^^^^^^^^^^^^^^^^^
11430 13:20:49.688150 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11431 13:20:49.691475 # raise ProtocolError(cc, rc)
11432 13:20:49.694633 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11433 13:20:49.697805 #
11434 13:20:49.700978 # ======================================================================
11435 13:20:49.707771 # ERROR: test_get_handles (tpm2_tests.SpaceTest.test_get_handles)
11436 13:20:49.714099 # ----------------------------------------------------------------------
11437 13:20:49.717357 # Traceback (most recent call last):
11438 13:20:49.730999 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11439 13:20:49.731280 # space1.create_root_key()
11440 13:20:49.744110 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11441 13:20:49.747041 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11442 13:20:49.753611 # ^^^^^^^^^^^^^^^^^^
11443 13:20:49.763618 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11444 13:20:49.766669 # raise ProtocolError(cc, rc)
11445 13:20:49.770208 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11446 13:20:49.773377 #
11447 13:20:49.776848 # ======================================================================
11448 13:20:49.783646 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc)
11449 13:20:49.790272 # ----------------------------------------------------------------------
11450 13:20:49.793228 # Traceback (most recent call last):
11451 13:20:49.803232 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11452 13:20:49.810026 # root1 = space1.create_root_key()
11453 13:20:49.812995 # ^^^^^^^^^^^^^^^^^^^^^^^^
11454 13:20:49.823205 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11455 13:20:49.826868 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11456 13:20:49.833187 # ^^^^^^^^^^^^^^^^^^
11457 13:20:49.842677 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11458 13:20:49.846428 # raise ProtocolError(cc, rc)
11459 13:20:49.849597 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11460 13:20:49.852735 #
11461 13:20:49.859744 # ======================================================================
11462 13:20:49.865895 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces)
11463 13:20:49.869444 # ----------------------------------------------------------------------
11464 13:20:49.872484 # Traceback (most recent call last):
11465 13:20:49.885944 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11466 13:20:49.889213 # root1 = space1.create_root_key()
11467 13:20:49.892872 # ^^^^^^^^^^^^^^^^^^^^^^^^
11468 13:20:49.902622 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11469 13:20:49.909095 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11470 13:20:49.912087 # ^^^^^^^^^^^^^^^^^^
11471 13:20:49.922266 # File "/lava-14879048/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11472 13:20:49.925533 # raise ProtocolError(cc, rc)
11473 13:20:49.931901 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11474 13:20:49.931977 #
11475 13:20:49.938327 # ----------------------------------------------------------------------
11476 13:20:49.942083 # Ran 4 tests in 0.070s
11477 13:20:49.942157 #
11478 13:20:49.942215 # FAILED (errors=4)
11479 13:20:49.948595 not ok 2 selftests: tpm2: test_space.sh # exit=1
11480 13:20:50.329105 tpm2_test_smoke_sh pass
11481 13:20:50.332027 tpm2_test_space_sh fail
11482 13:20:50.393907 + ../../utils/send-to-lava.sh ./output/result.txt
11483 13:20:50.477952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11484 13:20:50.478830 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11486 13:20:50.536202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11487 13:20:50.536476 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11489 13:20:50.597312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11490 13:20:50.598081 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11492 13:20:50.601021 + set +x
11493 13:20:50.604128 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 14879048_1.6.2.3.5>
11494 13:20:50.604794 Received signal: <ENDRUN> 1_kselftest-tpm2 14879048_1.6.2.3.5
11495 13:20:50.605143 Ending use of test pattern.
11496 13:20:50.605429 Ending test lava.1_kselftest-tpm2 (14879048_1.6.2.3.5), duration 13.34
11498 13:20:50.607285 <LAVA_TEST_RUNNER EXIT>
11499 13:20:50.608000 ok: lava_test_shell seems to have completed
11500 13:20:50.608584 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11501 13:20:50.608983 end: 3.1 lava-test-shell (duration 00:00:14) [common]
11502 13:20:50.609385 end: 3 lava-test-retry (duration 00:00:14) [common]
11503 13:20:50.609904 start: 4 finalize (timeout 00:07:22) [common]
11504 13:20:50.610388 start: 4.1 power-off (timeout 00:00:30) [common]
11505 13:20:50.611112 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
11506 13:20:52.751986 >> Command sent successfully.
11507 13:20:52.765922 Returned 0 in 2 seconds
11508 13:20:52.766494 end: 4.1 power-off (duration 00:00:02) [common]
11510 13:20:52.767418 start: 4.2 read-feedback (timeout 00:07:20) [common]
11511 13:20:52.768061 Listened to connection for namespace 'common' for up to 1s
11512 13:20:53.769108 Finalising connection for namespace 'common'
11513 13:20:53.769622 Disconnecting from shell: Finalise
11514 13:20:53.769942 / #
11515 13:20:53.870784 end: 4.2 read-feedback (duration 00:00:01) [common]
11516 13:20:53.871300 end: 4 finalize (duration 00:00:03) [common]
11517 13:20:53.871832 Cleaning after the job
11518 13:20:53.872311 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879048/tftp-deploy-56hlfbtr/ramdisk
11519 13:20:53.881547 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879048/tftp-deploy-56hlfbtr/kernel
11520 13:20:53.911755 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879048/tftp-deploy-56hlfbtr/dtb
11521 13:20:53.912063 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879048/tftp-deploy-56hlfbtr/nfsrootfs
11522 13:20:53.980209 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879048/tftp-deploy-56hlfbtr/modules
11523 13:20:53.985839 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14879048
11524 13:20:54.537908 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14879048
11525 13:20:54.538057 Job finished correctly